[gem5-dev] [XS] Change in gem5/gem5[release-staging-v23-0]: configs: Fix SPEC benchmarks example scripts
Ayaz Akram has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/71718?usp=email )
Change subject: configs: Fix SPEC benchmarks example scripts
..
configs: Fix SPEC benchmarks example scripts
This small change fixes the gem5_library example
scripts for SPEC benchmarks to make them compatible
with the latest version of the std library.
Change-Id: I3da9745f0ee6b253871e32082e135e0fa4040108
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71718
Maintainer: Jason Lowe-Power
Tested-by: kokoro
Reviewed-by: Jason Lowe-Power
---
M configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py
M configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py
2 files changed, 2 insertions(+), 2 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py
b/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py
index 60d93eb..10d5da0 100644
--- a/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py
+++ b/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py
@@ -262,7 +262,7 @@
kernel=Resource("x86-linux-kernel-4.19.83"),
# The location of the x86 SPEC CPU 2017 image
disk_image=CustomDiskImageResource(
-args.image, disk_root_partition=args.partition
+args.image, root_partition=args.partition
),
readfile_contents=command,
)
diff --git a/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py
b/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py
index c491c9b..cb5f5d1 100644
--- a/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py
+++ b/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py
@@ -278,7 +278,7 @@
kernel=Resource("x86-linux-kernel-4.19.83"),
# The location of the x86 SPEC CPU 2017 image
disk_image=CustomDiskImageResource(
-args.image, disk_root_partition=args.partition
+args.image, root_partition=args.partition
),
readfile_contents=command,
)
--
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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v23-0
Gerrit-Change-Id: I3da9745f0ee6b253871e32082e135e0fa4040108
Gerrit-Change-Number: 71718
Gerrit-PatchSet: 3
Gerrit-Owner: Ayaz Akram
Gerrit-Reviewer: Ayaz Akram
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-CC: kokoro
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[gem5-dev] [XS] Change in gem5/gem5[release-staging-v23-0]: configs: Fix SPEC example scripts
Ayaz Akram has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/71718?usp=email )
Change subject: configs: Fix SPEC example scripts
..
configs: Fix SPEC example scripts
Change-Id: I3da9745f0ee6b253871e32082e135e0fa4040108
---
M configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py
M configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py
b/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py
index 60d93eb..10d5da0 100644
--- a/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py
+++ b/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py
@@ -262,7 +262,7 @@
kernel=Resource("x86-linux-kernel-4.19.83"),
# The location of the x86 SPEC CPU 2017 image
disk_image=CustomDiskImageResource(
-args.image, disk_root_partition=args.partition
+args.image, root_partition=args.partition
),
readfile_contents=command,
)
diff --git a/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py
b/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py
index c491c9b..cb5f5d1 100644
--- a/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py
+++ b/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py
@@ -278,7 +278,7 @@
kernel=Resource("x86-linux-kernel-4.19.83"),
# The location of the x86 SPEC CPU 2017 image
disk_image=CustomDiskImageResource(
-args.image, disk_root_partition=args.partition
+args.image, root_partition=args.partition
),
readfile_contents=command,
)
--
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Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v23-0
Gerrit-Change-Id: I3da9745f0ee6b253871e32082e135e0fa4040108
Gerrit-Change-Number: 71718
Gerrit-PatchSet: 1
Gerrit-Owner: Ayaz Akram
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[gem5-dev] [M] Change in gem5/gem5[develop]: mem: HBMCtrl changes to allow PC data buses to be in different states
Ayaz Akram has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/65491?usp=email )
Change subject: mem: HBMCtrl changes to allow PC data buses to be in
different states
..
mem: HBMCtrl changes to allow PC data buses to be in different states
This change updates the HBMCtrl such that both pseudo channels
can be in separate states (read or write) at the same time. In
addition, the controller queues are now always split in two
halves for both pseudo channels.
Change-Id: Ifb599e611ad99f6c511baaf245bad2b5c9210a86
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65491
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/HBMCtrl.py
M src/mem/dram_interface.cc
M src/mem/hbm_ctrl.cc
M src/mem/hbm_ctrl.hh
M src/mem/mem_ctrl.cc
M src/mem/mem_ctrl.hh
M src/mem/mem_interface.hh
M src/mem/nvm_interface.cc
M src/mem/qos/mem_ctrl.cc
M src/mem/qos/mem_ctrl.hh
M src/mem/qos/mem_sink.cc
M src/python/gem5/components/memory/hbm.py
12 files changed, 122 insertions(+), 116 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/HBMCtrl.py b/src/mem/HBMCtrl.py
index 0c7c1ea..45d89a7 100644
--- a/src/mem/HBMCtrl.py
+++ b/src/mem/HBMCtrl.py
@@ -46,5 +46,3 @@
# gives the best results with following min_r/w_per_switch
min_reads_per_switch = 64
min_writes_per_switch = 64
-
-partitioned_q = Param.Bool(False, "split queues for pseudo channels")
diff --git a/src/mem/dram_interface.cc b/src/mem/dram_interface.cc
index d745fe5..65e06db 100644
--- a/src/mem/dram_interface.cc
+++ b/src/mem/dram_interface.cc
@@ -1068,13 +1068,14 @@
// latest Tick for which ACT can occur without
// incurring additoinal delay on the data bus
-const Tick tRCD = ctrl->inReadBusState(false) ?
- tRCD_RD : tRCD_WR;
+const Tick tRCD = ctrl->inReadBusState(false, this) ?
+tRCD_RD : tRCD_WR;
const Tick hidden_act_max =
std::max(min_col_at - tRCD, curTick());
// When is the earliest the R/W burst can issue?
-const Tick col_allowed_at = ctrl->inReadBusState(false) ?
+const Tick col_allowed_at = ctrl->inReadBusState(false,
+ this) ?
ranks[i]->banks[j].rdAllowedAt :
ranks[i]->banks[j].wrAllowedAt;
Tick col_at = std::max(col_allowed_at, act_at + tRCD);
@@ -1180,10 +1181,10 @@
DRAMInterface::Rank::isQueueEmpty() const
{
// check commmands in Q based on current bus direction
-bool no_queued_cmds = (dram.ctrl->inReadBusState(true) &&
- (readEntries == 0))
- || (dram.ctrl->inWriteBusState(true) &&
- (writeEntries == 0));
+bool no_queued_cmds = (dram.ctrl->inReadBusState(true, &(this->dram))
+ && (readEntries == 0)) ||
+ (dram.ctrl->inWriteBusState(true, &(this->dram))
+ && (writeEntries == 0));
return no_queued_cmds;
}
@@ -1669,7 +1670,7 @@
// completed refresh event, ensure next request is scheduled
if (!(dram.ctrl->requestEventScheduled(dram.pseudoChannel))) {
DPRINTF(DRAM, "Scheduling next request after refreshing"
- " rank %d\n", rank);
+ " rank %d, PC %d \n", rank, dram.pseudoChannel);
dram.ctrl->restartScheduler(curTick(), dram.pseudoChannel);
}
}
@@ -1831,7 +1832,8 @@
bool
DRAMInterface::Rank::forceSelfRefreshExit() const {
return (readEntries != 0) ||
- (dram.ctrl->inWriteBusState(true) && (writeEntries != 0));
+ (dram.ctrl->inWriteBusState(true, &(this->dram))
+&& (writeEntries != 0));
}
void
diff --git a/src/mem/hbm_ctrl.cc b/src/mem/hbm_ctrl.cc
index 747e714..f87fa2d 100644
--- a/src/mem/hbm_ctrl.cc
+++ b/src/mem/hbm_ctrl.cc
@@ -51,8 +51,7 @@
name()),
respondEventPC1([this] {processRespondEvent(pc1Int, respQueuePC1,
respondEventPC1, retryRdReqPC1); }, name()),
-pc1Int(p.dram_2),
-partitionedQ(p.partitioned_q)
+pc1Int(p.dram_2)
{
DPRINTF(MemCtrl, "Setting up HBM controller\n");
@@ -69,17 +68,8 @@
pc0Int->setCtrl(this, commandWindow, 0);
pc1Int->setCtrl(this, commandWindow, 1);
-if (partitionedQ) {
-writeHighThreshold = (writeBufferSize *
(p.write_high_thresh_perc/2)
- / 100.0);
-writeLowThreshold = (writeBufferSize *
[gem5-dev] [L] Change in gem5/gem5[develop]: mem: Add a DDR5 memory interface
Ayaz Akram has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/68257?usp=email ) Change subject: mem: Add a DDR5 memory interface .. mem: Add a DDR5 memory interface This change adds a single DDR5 memory inteface. A DDR5 DIMM contains two physical channels. Therefore, two instances of this interface should be used to model a DDR5 DIMM. The configuration includes 3 different speed bins models. The configuration is tested with different types of memory traffic using the traffic generator and shows performance similar to what is observed in existing literature [1]. One of the key features of DDR5 "same bank refresh" is yet not supported in gem5, but is expected to improve the performance of the DDR5 model. [1] Exploration of DDR5 with the Open-Source Simulator DRAMSys. Change-Id: I5856a10c8dcd92dbecc7fd4dcea0f674b2412dd7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68257 Maintainer: Jason Lowe-Power Reviewed-by: Jason Lowe-Power Tested-by: kokoro --- M src/mem/DRAMInterface.py M src/python/SConscript M src/python/gem5/components/memory/__init__.py A src/python/gem5/components/memory/dram_interfaces/ddr5.py M src/python/gem5/components/memory/single_channel.py 5 files changed, 588 insertions(+), 7 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/mem/DRAMInterface.py b/src/mem/DRAMInterface.py index 9c041e5..dea62a6 100644 --- a/src/mem/DRAMInterface.py +++ b/src/mem/DRAMInterface.py @@ -41,6 +41,7 @@ from m5.objects.MemCtrl import MemCtrl from m5.objects.MemInterface import * + # Enum for the page policy, either open, open_adaptive, close, or # close_adaptive. class PageManage(Enum): @@ -1179,7 +1180,6 @@ # on HBM gen2 specifications. 4H stack, 8Gb per die and total capacity # of 4GiB. class HBM_2000_4H_1x64(DRAMInterface): - # 64-bit interface for a single pseudo channel device_bus_width = 64 @@ -1256,6 +1256,268 @@ two_cycle_activate = True +# A single DDR5-4400 32bit channel (4x8 configuration) +# A DDR5 DIMM is made up of two (32 bit) channels. +# Following configuration is modeling only a single 32bit channel. +# Timings are based on Micron data sheet: +# https://media-www.micron.com/-/media/client/global/ +# documents/products/data-sheet/dram/ddr5/ddr5_sdram_core.pdf +# Configuration: 4Gbx8 devices (32Gb addressing) +# Maximum bandwidth of DDR5_4400_4x8 (4400 MT/s) can be 17.6GB/s +class DDR5_4400_4x8(DRAMInterface): +# size of a single device +device_size = "512MiB" + +# single channel of 32bit width +# requires 8-bit wide 4 devices +device_bus_width = 8 + +# DDR5 is a BL16 device +burst_length = 16 + +# Each device has a page (row buffer) size of 256B +# Four devices lead to a page size of 1KB +device_rowbuffer_size = "256B" + +# 4Gbx8 configuration +devices_per_rank = 4 + +ranks_per_channel = 1 + +# 4Gbx8 configuration of DDR5 has 8 bank groups, +# 4 banks per bank group and 32 banks in total +bank_groups_per_rank = 8 +banks_per_rank = 32 + +write_buffer_size = 64 +read_buffer_size = 64 + +# For 4400 MT/s +tCK = "0.454ns" + +# 16 beats across an x32 interface translates to 8 clocks @ 2200 MHz +tBURST = "3.632ns" + +# For 4400 MT/s, the number is max(8nCK, 5ns) +tCCD_L = "5ns" + +# page 389 of the data sheet +tRCD = "14.545ns" +tCL = "14.545ns" +# tCWL = tCL - 2(nCK) +tCWL = "13.637ns" +tRP = "14.545ns" +tRAS = "32ns" + +# RRD_S (different bank group) : 8nCK +tRRD = "3.632ns" + +# RRD_L (same bank group) is MAX(8nCK, 5ns) for 1KB page +tRRD_L = "5ns" + +# tFAW for 1KB page is MAX(32nCK, 14.545ns) +tXAW = "14.545ns" +activation_limit = 4 + +# Note: could not find the rank to rank delay +# from the datasheet, but, since we are modeling +# a single rank device, it should not matter. +# Using the DDR4 number as default (i.e. ~2tCK) +tCS = "1ns" + +# tRFC (Normal) for 16Gb device is 295ns +tRFC = "295ns" + +tPPD = "0.908ns" # 2nCK +tWR = "30ns" + +# Rd/Wr turnaround timings +### +# Note: gem5 adds tBURST separately while calculting rd--rd/wr or +# wr--wr/rd delays so we can ignore tBURST factor from the following +# equations while calculating the final value of the timing parameter + +# From the datasheet +# (1) tCCD_L_RTW = +# CL - CWL + RBL/2 + 2 tCK - (Read DQS offset) + (tRPST - 0.5 tCK) + tWPRE +# where CWL = CL-2, RBL/2 = tBURST, Read DQS offset = 1ck, tRPST = 1.5tCK +# Therefore, tCCD_L_RTW = +# (14.545 - 13.637) + (2*0.454) - 0.454 + +# ((1.5*0.454)-(0.5*0.454) +
[gem5-dev] [XS] Change in gem5/gem5[develop]: configs: Update riscv/fs_linux.py script
Ayaz Akram has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/70177?usp=email )
Change subject: configs: Update riscv/fs_linux.py script
..
configs: Update riscv/fs_linux.py script
This change fixes a couple of small issues with
the configs/example/riscv/fs_linux.py script to ensure
that it works with the latest version of gem5.
Change-Id: I9753ca4c8dd0b87d05681b167cf51e3c097e9152
---
M configs/example/riscv/fs_linux.py
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/configs/example/riscv/fs_linux.py
b/configs/example/riscv/fs_linux.py
index aec126a..949c7e2 100644
--- a/configs/example/riscv/fs_linux.py
+++ b/configs/example/riscv/fs_linux.py
@@ -187,6 +187,7 @@
# RTCCLK (Set to 100MHz for faster simulation)
system.platform.rtc = RiscvRTC(frequency=Frequency("100MHz"))
system.platform.clint.int_pin = system.platform.rtc.int_pin
+system.platform.pci_host.pio = system.iobus.mem_side_ports
# VirtIOMMIO
if args.disk_image:
@@ -236,8 +237,6 @@
clock=args.cpu_clock, voltage_domain=system.cpu_voltage_domain
)
-system.workload.object_file = args.kernel
-
# NOTE: Not yet tested
if args.script is not None:
system.readfile = args.script
--
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[gem5-dev] [XS] Change in gem5/gem5[develop]: stdlib: Small fix in mesi three level component
Ayaz Akram has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/69297?usp=email )
Change subject: stdlib: Small fix in mesi three level component
..
stdlib: Small fix in mesi three level component
This change ensures that if cache_line_size is not
an integer type, we don't incorrectly raise the
exception of cache size not equal to 2^bits.
Change-Id: I5a06cdac820283feb54f23d805fd87490fae1c3b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69297
Tested-by: kokoro
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
---
M
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py
M
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py
2 files changed, 2 insertions(+), 2 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py
index b485481..e746579 100644
---
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py
+++
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py
@@ -92,7 +92,7 @@
def getBlockSizeBits(self, cache_line_size):
bits = int(math.log(cache_line_size, 2))
-if 2**bits != cache_line_size:
+if 2**bits != int(cache_line_size):
raise Exception("Cache line size is not a power of 2!")
return bits
diff --git
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py
index d54e1ab..dfc1304 100644
---
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py
+++
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py
@@ -90,7 +90,7 @@
def getBlockSizeBits(self, cache_line_size):
bits = int(math.log(cache_line_size, 2))
-if 2**bits != cache_line_size:
+if 2**bits != int(cache_line_size):
raise Exception("Cache line size is not a power of 2!")
return bits
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5a06cdac820283feb54f23d805fd87490fae1c3b
Gerrit-Change-Number: 69297
Gerrit-PatchSet: 2
Gerrit-Owner: Ayaz Akram
Gerrit-Reviewer: Ayaz Akram
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Hoa Nguyen
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [XS] Change in gem5/gem5[develop]: stdlib: Small fix in mesi three level component
Ayaz Akram has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/69297?usp=email )
Change subject: stdlib: Small fix in mesi three level component
..
stdlib: Small fix in mesi three level component
This change ensures that if cache_line_size is not
an integer type, we don't incorrectly raise the
exception of cache size not equal to 2^bits.
Change-Id: I5a06cdac820283feb54f23d805fd87490fae1c3b
---
M
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py
M
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py
index b485481..e746579 100644
---
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py
+++
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py
@@ -92,7 +92,7 @@
def getBlockSizeBits(self, cache_line_size):
bits = int(math.log(cache_line_size, 2))
-if 2**bits != cache_line_size:
+if 2**bits != int(cache_line_size):
raise Exception("Cache line size is not a power of 2!")
return bits
diff --git
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py
index d54e1ab..dfc1304 100644
---
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py
+++
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py
@@ -90,7 +90,7 @@
def getBlockSizeBits(self, cache_line_size):
bits = int(math.log(cache_line_size, 2))
-if 2**bits != cache_line_size:
+if 2**bits != int(cache_line_size):
raise Exception("Cache line size is not a power of 2!")
return bits
--
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Gerrit-Change-Id: I5a06cdac820283feb54f23d805fd87490fae1c3b
Gerrit-Change-Number: 69297
Gerrit-PatchSet: 1
Gerrit-Owner: Ayaz Akram
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[gem5-dev] Change in gem5/gem5[develop]: mem: Trigger NVM interface startup on a switch to timing CPU mode
Ayaz Akram has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/55023 )
Change subject: mem: Trigger NVM interface startup on a switch to timing
CPU mode
..
mem: Trigger NVM interface startup on a switch to timing CPU mode
Currently, if only NVM interface is used, switching from KVM to timing cpu
leads to a
segmentation fault. This change makes sure that the interface's startup
function is called
only for the interface which is used in a given simulation.
Change-Id: I85eab6e1de5c84076512c7653bf5d7ad0ff7e327
---
M src/mem/mem_ctrl.cc
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/src/mem/mem_ctrl.cc b/src/mem/mem_ctrl.cc
index 18b8476..7c37b67 100644
--- a/src/mem/mem_ctrl.cc
+++ b/src/mem/mem_ctrl.cc
@@ -1450,7 +1450,12 @@
// if we switched to timing mode, kick things into action,
// and behave as if we restored from a checkpoint
startup();
-dram->startup();
+if (dram) {
+dram->startup();
+}
+if (nvm) {
+nvm->startup();
+}
} else if (isTimingMode && !system()->isTimingMode()) {
// if we switch from timing mode, stop the refresh events to
// not cause issues with KVM
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I85eab6e1de5c84076512c7653bf5d7ad0ff7e327
Gerrit-Change-Number: 55023
Gerrit-PatchSet: 1
Gerrit-Owner: Ayaz Akram
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: add pma/pmp checks during page table walks
Ayaz Akram has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/46279 )
Change subject: arch-riscv: add pma/pmp checks during page table walks
..
arch-riscv: add pma/pmp checks during page table walks
This change adds pma/pmp checks when page table entries
are accessed by hardware page table walker.
Change-Id: I161aad514bb7421e61a8c56af088c73969837704
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46279
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/riscv/pagetable_walker.cc
M src/arch/riscv/pmp.cc
M src/arch/riscv/pmp.hh
3 files changed, 111 insertions(+), 68 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/riscv/pagetable_walker.cc
b/src/arch/riscv/pagetable_walker.cc
index 8dadd96..0a0c719 100644
--- a/src/arch/riscv/pagetable_walker.cc
+++ b/src/arch/riscv/pagetable_walker.cc
@@ -295,76 +295,101 @@
DPRINTF(PageTableWalker, "Got level%d PTE: %#x\n", level, pte);
-// step 2: TODO check PMA and PMP
+// step 2:
+// Performing PMA/PMP checks on physical address of PTE
-// step 3:
-if (!pte.v || (!pte.r && pte.w)) {
-doEndWalk = true;
-DPRINTF(PageTableWalker, "PTE invalid, raising PF\n");
-fault = pageFault(pte.v);
-}
-else {
-// step 4:
-if (pte.r || pte.x) {
-// step 5: leaf PTE
+walker->pma->check(read->req);
+// Effective privilege mode for pmp checks for page table
+// walks is S mode according to specs
+fault = walker->pmp->pmpCheck(read->req, mode,
+RiscvISA::PrivilegeMode::PRV_S, tc, entry.vaddr);
+
+if (fault == NoFault) {
+// step 3:
+if (!pte.v || (!pte.r && pte.w)) {
doEndWalk = true;
-fault = walker->tlb->checkPermissions(status, pmode,
- entry.vaddr, mode, pte);
-
-// step 6
-if (fault == NoFault) {
-if (level >= 1 && pte.ppn0 != 0) {
-DPRINTF(PageTableWalker,
-"PTE has misaligned PPN, raising PF\n");
-fault = pageFault(true);
-}
-else if (level == 2 && pte.ppn1 != 0) {
-DPRINTF(PageTableWalker,
-"PTE has misaligned PPN, raising PF\n");
-fault = pageFault(true);
-}
-}
-
-if (fault == NoFault) {
-// step 7
-if (!pte.a) {
-pte.a = 1;
-doWrite = true;
-}
-if (!pte.d && mode == TLB::Write) {
-pte.d = 1;
-doWrite = true;
-}
-// TODO check if this violates a PMA or PMP
-
-// step 8
-entry.logBytes = PageShift + (level * LEVEL_BITS);
-entry.paddr = pte.ppn;
-entry.vaddr &= ~((1 << entry.logBytes) - 1);
-entry.pte = pte;
-// put it non-writable into the TLB to detect writes and
redo
-// the page table walk in order to update the dirty flag.
-if (!pte.d && mode != TLB::Write)
-entry.pte.w = 0;
-doTLBInsert = true;
-}
+DPRINTF(PageTableWalker, "PTE invalid, raising PF\n");
+fault = pageFault(pte.v);
}
else {
-level--;
-if (level < 0) {
-DPRINTF(PageTableWalker, "No leaf PTE found, raising
PF\n");
+// step 4:
+if (pte.r || pte.x) {
+// step 5: leaf PTE
doEndWalk = true;
-fault = pageFault(true);
-}
-else {
-Addr shift = (PageShift + LEVEL_BITS * level);
-Addr idx = (entry.vaddr >> shift) & LEVEL_MASK;
-nextRead = (pte.ppn << PageShift) + (idx * sizeof(pte));
-nextState = Translate;
+fault = walker->tlb->checkPermissions(status, pmode,
+entry.vaddr, mode,
pte);
+
+// step 6
+if (fault == NoFault) {
+if (level >= 1 && pte.ppn0 != 0) {
+DPRINTF(PageTableWalker,
+"PTE has misaligned PPN, raising PF\n");
+fault = pageFault(true);
+}
+else if (level == 2 && pte.ppn1 != 0) {
+DPRINTF(PageTableWalker,
+"PTE has misaligned PPN, raising PF\n");
+fault = pageFault(true);
+
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: update all pmp rules on pmp addr update
Ayaz Akram has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/47059 )
Change subject: arch-riscv: update all pmp rules on pmp addr update
..
arch-riscv: update all pmp rules on pmp addr update
Update in a pmp addr register can have effect on other
pmp rules, for example if TOR mode is used.
According to specs, update in a pmp entry is made using
an update to a pmpaddr reg, followed by an update to pmpcfg
reg which should be followed by sfence.vma. Currently,
in gem5 update in cfg register (combination of 8 pmpcfg
regs.), which should happen after a pmpaddr reg. update,
leads to an update in all pmp rules. However, there seems to
be a case where we receive an interrupt right before execution
of an instruction to update cfg register, which leads to unindented
side-effects of S mode addresses falsely falling into a wrong
pmp region. Updating pmp rules right after pmpaddr update, might
be redundant, but should not break anything otherwise.
Change-Id: I3776ee6ba40e1249c98d11076a2d176de40a957e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47059
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/riscv/pmp.cc
1 file changed, 3 insertions(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/riscv/pmp.cc b/src/arch/riscv/pmp.cc
index e9fcb7b..c0e53bf 100644
--- a/src/arch/riscv/pmp.cc
+++ b/src/arch/riscv/pmp.cc
@@ -204,7 +204,9 @@
// will convert it into a range, once cfg
// reg is written
pmpTable[pmp_index].rawAddr = this_addr;
-pmpUpdateRule(pmp_index);
+for (int index = 0; index < pmpEntries; index++) {
+pmpUpdateRule(index);
+}
}
bool
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3776ee6ba40e1249c98d11076a2d176de40a957e
Gerrit-Change-Number: 47059
Gerrit-PatchSet: 2
Gerrit-Owner: Ayaz Akram
Gerrit-Reviewer: Ayaz Akram
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: update all pmp rules on pmp addr update
Ayaz Akram has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/47059 )
Change subject: arch-riscv: update all pmp rules on pmp addr update
..
arch-riscv: update all pmp rules on pmp addr update
Update in a pmp addr register can have effect on other
pmp rules, for example if TOR mode is used.
According to specs, update in a pmp entry is made using
an update to a pmpaddr reg, followed by an update to pmpcfg
reg which should be followed by sfence.vma. Currently,
in gem5 update in cfg register (combination of 8 pmpcfg
regs.), which should happen after a pmpaddr reg. update,
leads to an update in all pmp rules. However, there seems to
be a case where we receive an interrupt right before execution
of an instruction to update cfg register, which leads to unindented
side-effects of S mode addresses falsely falling into a wrong
pmp region. Updating pmp rules right after pmpaddr update, might
be redundant, but should not break anything otherwise.
Change-Id: I3776ee6ba40e1249c98d11076a2d176de40a957e
---
M src/arch/riscv/pmp.cc
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/arch/riscv/pmp.cc b/src/arch/riscv/pmp.cc
index e9fcb7b..c0e53bf 100644
--- a/src/arch/riscv/pmp.cc
+++ b/src/arch/riscv/pmp.cc
@@ -204,7 +204,9 @@
// will convert it into a range, once cfg
// reg is written
pmpTable[pmp_index].rawAddr = this_addr;
-pmpUpdateRule(pmp_index);
+for (int index = 0; index < pmpEntries; index++) {
+pmpUpdateRule(index);
+}
}
bool
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I3776ee6ba40e1249c98d11076a2d176de40a957e
Gerrit-Change-Number: 47059
Gerrit-PatchSet: 1
Gerrit-Owner: Ayaz Akram
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Update the way a valid virtual address is computed
Ayaz Akram has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/45920 )
Change subject: arch-riscv: Update the way a valid virtual address is
computed
..
arch-riscv: Update the way a valid virtual address is computed
According to privileged ISA specs, a valid 64 bit virtual address should
have bit 63-39 same as bit 38 (for Sv39). Without this change, kernel page
fault handler does not seem to work correctly. For example, while running
a program, the kernel was segfaulting complaining that it cannot handle
kernel paging request at some virtual address (which is the faulting
address returned by gem5 currently, with all bits after first 39 cleared).
With this change, that error goes away.
Change-Id: Iae7c9d0af19e29214e14a0db08d7c0ac122122bc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45920
Reviewed-by: Jason Lowe-Power
Reviewed-by: Nils Asmussen
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/riscv/pagetable_walker.cc
M src/arch/riscv/tlb.cc
2 files changed, 3 insertions(+), 3 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Nils Asmussen: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/riscv/pagetable_walker.cc
b/src/arch/riscv/pagetable_walker.cc
index d3c3905..8dadd96 100644
--- a/src/arch/riscv/pagetable_walker.cc
+++ b/src/arch/riscv/pagetable_walker.cc
@@ -418,7 +418,7 @@
void
Walker::WalkerState::setupWalk(Addr vaddr)
{
-vaddr &= (static_cast(1) << VADDR_BITS) - 1;
+vaddr = Addr(sext(vaddr));
Addr shift = PageShift + LEVEL_BITS * 2;
Addr idx = (vaddr >> shift) & LEVEL_MASK;
@@ -486,7 +486,7 @@
* well.
*/
Addr vaddr = req->getVaddr();
-vaddr &= (static_cast(1) << VADDR_BITS) - 1;
+vaddr = Addr(sext(vaddr));
Addr paddr = walker->tlb->translateWithTLB(vaddr, satp.asid,
mode);
req->setPaddr(paddr);
walker->pma->check(req);
diff --git a/src/arch/riscv/tlb.cc b/src/arch/riscv/tlb.cc
index a5e4107..1ec848e 100644
--- a/src/arch/riscv/tlb.cc
+++ b/src/arch/riscv/tlb.cc
@@ -277,7 +277,7 @@
{
delayed = false;
-Addr vaddr = req->getVaddr() & ((static_cast(1) << VADDR_BITS) -
1);
+Addr vaddr = Addr(sext(req->getVaddr()));
SATP satp = tc->readMiscReg(MISCREG_SATP);
TlbEntry *e = lookup(vaddr, satp.asid, mode, false);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iae7c9d0af19e29214e14a0db08d7c0ac122122bc
Gerrit-Change-Number: 45920
Gerrit-PatchSet: 6
Gerrit-Owner: Ayaz Akram
Gerrit-Reviewer: Ayaz Akram
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nils Asmussen
Gerrit-Reviewer: kokoro
Gerrit-CC: Gabe Black
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: add pma/pmp checks during page table walks
Ayaz Akram has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/46279 )
Change subject: arch-riscv: add pma/pmp checks during page table walks
..
arch-riscv: add pma/pmp checks during page table walks
This change adds pma/pmp checks when page table entries
are accessed by hardware page table walker.
Change-Id: I161aad514bb7421e61a8c56af088c73969837704
---
M src/arch/riscv/pagetable_walker.cc
M src/arch/riscv/pmp.cc
2 files changed, 103 insertions(+), 64 deletions(-)
diff --git a/src/arch/riscv/pagetable_walker.cc
b/src/arch/riscv/pagetable_walker.cc
index d3c3905..54725e7 100644
--- a/src/arch/riscv/pagetable_walker.cc
+++ b/src/arch/riscv/pagetable_walker.cc
@@ -295,76 +295,99 @@
DPRINTF(PageTableWalker, "Got level%d PTE: %#x\n", level, pte);
-// step 2: TODO check PMA and PMP
+// step 2:
+// Performing PMA/PMP checks on physical address of PTE
-// step 3:
-if (!pte.v || (!pte.r && pte.w)) {
-doEndWalk = true;
-DPRINTF(PageTableWalker, "PTE invalid, raising PF\n");
-fault = pageFault(pte.v);
-}
-else {
-// step 4:
-if (pte.r || pte.x) {
-// step 5: leaf PTE
+walker->pma->check(read->req);
+fault = walker->pmp->pmpCheck(read->req, mode, pmode, tc);
+
+if (fault == NoFault) {
+// step 3:
+if (!pte.v || (!pte.r && pte.w)) {
doEndWalk = true;
-fault = walker->tlb->checkPermissions(status, pmode,
- entry.vaddr, mode, pte);
-
-// step 6
-if (fault == NoFault) {
-if (level >= 1 && pte.ppn0 != 0) {
-DPRINTF(PageTableWalker,
-"PTE has misaligned PPN, raising PF\n");
-fault = pageFault(true);
-}
-else if (level == 2 && pte.ppn1 != 0) {
-DPRINTF(PageTableWalker,
-"PTE has misaligned PPN, raising PF\n");
-fault = pageFault(true);
-}
-}
-
-if (fault == NoFault) {
-// step 7
-if (!pte.a) {
-pte.a = 1;
-doWrite = true;
-}
-if (!pte.d && mode == TLB::Write) {
-pte.d = 1;
-doWrite = true;
-}
-// TODO check if this violates a PMA or PMP
-
-// step 8
-entry.logBytes = PageShift + (level * LEVEL_BITS);
-entry.paddr = pte.ppn;
-entry.vaddr &= ~((1 << entry.logBytes) - 1);
-entry.pte = pte;
-// put it non-writable into the TLB to detect writes and
redo
-// the page table walk in order to update the dirty flag.
-if (!pte.d && mode != TLB::Write)
-entry.pte.w = 0;
-doTLBInsert = true;
-}
+DPRINTF(PageTableWalker, "PTE invalid, raising PF\n");
+fault = pageFault(pte.v);
}
else {
-level--;
-if (level < 0) {
-DPRINTF(PageTableWalker, "No leaf PTE found, raising
PF\n");
+// step 4:
+if (pte.r || pte.x) {
+// step 5: leaf PTE
doEndWalk = true;
-fault = pageFault(true);
+fault = walker->tlb->checkPermissions(status, pmode,
+entry.vaddr, mode,
pte);
+
+// step 6
+if (fault == NoFault) {
+if (level >= 1 && pte.ppn0 != 0) {
+DPRINTF(PageTableWalker,
+"PTE has misaligned PPN, raising PF\n");
+fault = pageFault(true);
+}
+else if (level == 2 && pte.ppn1 != 0) {
+DPRINTF(PageTableWalker,
+"PTE has misaligned PPN, raising PF\n");
+fault = pageFault(true);
+}
+}
+
+if (fault == NoFault) {
+// step 7
+if (!pte.a) {
+pte.a = 1;
+doWrite = true;
+}
+if (!pte.d && mode == TLB::Write) {
+pte.d = 1;
+doWrite = true;
+}
+// Performing PMA/PMP checks
+
+if (doWrite) {
+
+// this read will eventually become write
+// if doWrite is True
+
+walker->pma->check(read->req);
+
+fault =
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Use inst virtual address to create a page fault
Ayaz Akram has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/45920 )
Change subject: arch-riscv: Use inst virtual address to create a page fault
..
arch-riscv: Use inst virtual address to create a page fault
According to privileged ISA specs, on a page fault, mtval
is written with the faulting virtual address and not the page
address.
Change-Id: Iae7c9d0af19e29214e14a0db08d7c0ac122122bc
---
M src/arch/riscv/pagetable_walker.cc
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/arch/riscv/pagetable_walker.cc
b/src/arch/riscv/pagetable_walker.cc
index d3c3905..45dcf7f 100644
--- a/src/arch/riscv/pagetable_walker.cc
+++ b/src/arch/riscv/pagetable_walker.cc
@@ -582,7 +582,7 @@
Walker::WalkerState::pageFault(bool present)
{
DPRINTF(PageTableWalker, "Raising page fault.\n");
-return walker->tlb->createPagefault(entry.vaddr, mode);
+return walker->tlb->createPagefault(req->getVaddr(), mode);
}
} /* end namespace RiscvISA */
--
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Gerrit-Change-Id: Iae7c9d0af19e29214e14a0db08d7c0ac122122bc
Gerrit-Change-Number: 45920
Gerrit-PatchSet: 1
Gerrit-Owner: Ayaz Akram
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Add riscv pmp support
Ayaz Akram has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/43945 )
Change subject: arch-riscv: Add riscv pmp support
..
arch-riscv: Add riscv pmp support
This change adds the pmp (physical memory protection)
feature of riscv previliged isa.
Change-Id: Ica701223cfc1be91a0bf953e6a3df6d72d6d3130
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43945
Reviewed-by: Jason Lowe-Power
Reviewed-by: Peter Yuen
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
A src/arch/riscv/PMP.py
M src/arch/riscv/RiscvMMU.py
M src/arch/riscv/RiscvTLB.py
M src/arch/riscv/SConscript
M src/arch/riscv/isa.cc
M src/arch/riscv/mmu.hh
M src/arch/riscv/pagetable_walker.cc
M src/arch/riscv/pagetable_walker.hh
A src/arch/riscv/pmp.cc
A src/arch/riscv/pmp.hh
M src/arch/riscv/tlb.cc
M src/arch/riscv/tlb.hh
12 files changed, 556 insertions(+), 2 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Peter Yuen: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/riscv/PMP.py b/src/arch/riscv/PMP.py
new file mode 100644
index 000..8628bd6
--- /dev/null
+++ b/src/arch/riscv/PMP.py
@@ -0,0 +1,35 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All Rights Reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
+
+class PMP(SimObject):
+type = 'PMP'
+cxx_header = 'arch/riscv/pmp.hh'
+pmp_entries = Param.Int(16, "Maximum PMP Entries Supported")
+
diff --git a/src/arch/riscv/RiscvMMU.py b/src/arch/riscv/RiscvMMU.py
index 38f1da9..f4fca6e 100644
--- a/src/arch/riscv/RiscvMMU.py
+++ b/src/arch/riscv/RiscvMMU.py
@@ -40,6 +40,7 @@
from m5.objects.BaseMMU import BaseMMU
from m5.objects.RiscvTLB import RiscvTLB
from m5.objects.PMAChecker import PMAChecker
+from m5.objects.PMP import PMP
class RiscvMMU(BaseMMU):
type = 'RiscvMMU'
@@ -48,6 +49,7 @@
itb = RiscvTLB()
dtb = RiscvTLB()
pma_checker = Param.PMAChecker(PMAChecker(), "PMA Checker")
+pmp = Param.PMP(PMP(), "Physical Memory Protection Unit")
@classmethod
def walkerPorts(cls):
diff --git a/src/arch/riscv/RiscvTLB.py b/src/arch/riscv/RiscvTLB.py
index 05ff521..d66d870 100644
--- a/src/arch/riscv/RiscvTLB.py
+++ b/src/arch/riscv/RiscvTLB.py
@@ -44,6 +44,7 @@
"Number of outstanding walks that can be squashed per cycle")
# Grab the pma_checker from the MMU
pma_checker = Param.PMAChecker(Parent.any, "PMA Checker")
+pmp = Param.PMP(Parent.any, "PMP")
class RiscvTLB(BaseTLB):
type = 'RiscvTLB'
@@ -54,3 +55,4 @@
RiscvPagetableWalker(), "page table walker")
# Grab the pma_checker from the MMU
pma_checker = Param.PMAChecker(Parent.any, "PMA Checker")
+pmp = Param.PMP(Parent.any, "Physical Memory Protection Unit")
diff --git a/src/arch/riscv/SConscript b/src/arch/riscv/SConscript
index ac47df5..03e382c 100644
--- a/src/arch/riscv/SConscript
+++ b/src/arch/riscv/SConscript
@@ -52,6 +52,7 @@
Source('pagetable.cc')
Source('pagetable_walker.cc')
Source('pma_checker.cc')
+Source('pmp.cc')
Source('reg_abi.cc')
Source('remote_gdb.cc')
Source('tlb.cc')
@@ -63,6 +64,7 @@
Source('bare_metal/fs_workload.cc')
SimObject('PMAChecker.py')
+SimObject('PMP.py')
SimObject('RiscvFsWorkload.py')
SimObject('RiscvInterrupts.py')
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv,util: update riscv crosstool-ng config and m5 README entry
Ayaz Akram has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/44032 ) Change subject: arch-riscv,util: update riscv crosstool-ng config and m5 README entry .. arch-riscv,util: update riscv crosstool-ng config and m5 README entry Change-Id: I751a6c97a0ac97f7b3fce360577d0ee16f29fda4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44032 Reviewed-by: Gabe Black Reviewed-by: Jason Lowe-Power Maintainer: Gabe Black Tested-by: kokoro --- R util/crosstool-ng/riscv64-unknown-linux-gnu.defconfig M util/m5/README.md 2 files changed, 1 insertion(+), 2 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved Gabe Black: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/util/crosstool-ng/riscv-linux-gnu.defconfig b/util/crosstool-ng/riscv64-unknown-linux-gnu.defconfig similarity index 90% rename from util/crosstool-ng/riscv-linux-gnu.defconfig rename to util/crosstool-ng/riscv64-unknown-linux-gnu.defconfig index f458630..2fff658 100644 --- a/util/crosstool-ng/riscv-linux-gnu.defconfig +++ b/util/crosstool-ng/riscv64-unknown-linux-gnu.defconfig @@ -1,7 +1,6 @@ CT_CONFIG_VERSION="3" CT_EXPERIMENTAL=y CT_ARCH_RISCV=y -CT_OMIT_TARGET_VENDOR=y CT_ARCH_USE_MMU=y CT_ARCH_64=y CT_KERNEL_LINUX=y diff --git a/util/m5/README.md b/util/m5/README.md index 9bae153..0257d13 100644 --- a/util/m5/README.md +++ b/util/m5/README.md @@ -167,7 +167,7 @@ thumb | arm | arm-linux-gnueabihf- sparc | sparc64 | sparc64-linux-gnu- x86 | x86_64| - riscv | riscv64 | riscv64-linux-gnu- + riscv | riscv64 | riscv64-unknown-linux-gnu- Note that the default setting for the x86 cross compiler prefix is blank, meaning that the native/host compiler will be used. If building on a non-x86 -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/44032 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I751a6c97a0ac97f7b3fce360577d0ee16f29fda4 Gerrit-Change-Number: 44032 Gerrit-PatchSet: 3 Gerrit-Owner: Ayaz Akram Gerrit-Reviewer: Ayaz Akram Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv,util: update riscv crosstool-ng config and m5 README entry
Ayaz Akram has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/44032 ) Change subject: arch-riscv,util: update riscv crosstool-ng config and m5 README entry .. arch-riscv,util: update riscv crosstool-ng config and m5 README entry Change-Id: I751a6c97a0ac97f7b3fce360577d0ee16f29fda4 --- R util/crosstool-ng/riscv64-unknown-linux-gnu.defconfig M util/m5/README.md 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/util/crosstool-ng/riscv-linux-gnu.defconfig b/util/crosstool-ng/riscv64-unknown-linux-gnu.defconfig similarity index 100% rename from util/crosstool-ng/riscv-linux-gnu.defconfig rename to util/crosstool-ng/riscv64-unknown-linux-gnu.defconfig diff --git a/util/m5/README.md b/util/m5/README.md index 9bae153..0257d13 100644 --- a/util/m5/README.md +++ b/util/m5/README.md @@ -167,7 +167,7 @@ thumb | arm | arm-linux-gnueabihf- sparc | sparc64 | sparc64-linux-gnu- x86 | x86_64| - riscv | riscv64 | riscv64-linux-gnu- + riscv | riscv64 | riscv64-unknown-linux-gnu- Note that the default setting for the x86 cross compiler prefix is blank, meaning that the native/host compiler will be used. If building on a non-x86 -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/44032 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I751a6c97a0ac97f7b3fce360577d0ee16f29fda4 Gerrit-Change-Number: 44032 Gerrit-PatchSet: 1 Gerrit-Owner: Ayaz Akram Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Add riscv pmp support
Ayaz Akram has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/43945 )
Change subject: arch-riscv: Add riscv pmp support
..
arch-riscv: Add riscv pmp support
This change adds the pmp (physical memory protection)
feature of riscv previliged isa.
Change-Id: Ica701223cfc1be91a0bf953e6a3df6d72d6d3130
---
A src/arch/riscv/PMP.py
M src/arch/riscv/RiscvMMU.py
M src/arch/riscv/RiscvTLB.py
M src/arch/riscv/SConscript
M src/arch/riscv/isa.cc
M src/arch/riscv/mmu.hh
M src/arch/riscv/pagetable_walker.cc
M src/arch/riscv/pagetable_walker.hh
A src/arch/riscv/pmp.cc
A src/arch/riscv/pmp.hh
M src/arch/riscv/tlb.cc
M src/arch/riscv/tlb.hh
12 files changed, 570 insertions(+), 2 deletions(-)
diff --git a/src/arch/riscv/PMP.py b/src/arch/riscv/PMP.py
new file mode 100644
index 000..05084ee
--- /dev/null
+++ b/src/arch/riscv/PMP.py
@@ -0,0 +1,35 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All Rights Reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
+
+class PMP(SimObject):
+type = 'PMP'
+cxx_header = 'arch/riscv/pmp.hh'
+max_pmp = Param.Int(16, "Max PMP Entries")
+
diff --git a/src/arch/riscv/RiscvMMU.py b/src/arch/riscv/RiscvMMU.py
index 38f1da9..5f1aa11 100644
--- a/src/arch/riscv/RiscvMMU.py
+++ b/src/arch/riscv/RiscvMMU.py
@@ -40,6 +40,7 @@
from m5.objects.BaseMMU import BaseMMU
from m5.objects.RiscvTLB import RiscvTLB
from m5.objects.PMAChecker import PMAChecker
+from m5.objects.PMP import PMP
class RiscvMMU(BaseMMU):
type = 'RiscvMMU'
@@ -48,6 +49,7 @@
itb = RiscvTLB()
dtb = RiscvTLB()
pma_checker = Param.PMAChecker(PMAChecker(), "PMA Checker")
+pmp = PMP()
@classmethod
def walkerPorts(cls):
diff --git a/src/arch/riscv/RiscvTLB.py b/src/arch/riscv/RiscvTLB.py
index 05ff521..0a4e257 100644
--- a/src/arch/riscv/RiscvTLB.py
+++ b/src/arch/riscv/RiscvTLB.py
@@ -44,6 +44,7 @@
"Number of outstanding walks that can be squashed per cycle")
# Grab the pma_checker from the MMU
pma_checker = Param.PMAChecker(Parent.any, "PMA Checker")
+pmp = Param.PMP(Parent.any, "PMP")
class RiscvTLB(BaseTLB):
type = 'RiscvTLB'
@@ -54,3 +55,4 @@
RiscvPagetableWalker(), "page table walker")
# Grab the pma_checker from the MMU
pma_checker = Param.PMAChecker(Parent.any, "PMA Checker")
+pmp = Param.PMP(Parent.any, "PMP")
diff --git a/src/arch/riscv/SConscript b/src/arch/riscv/SConscript
index ac47df5..03e382c 100644
--- a/src/arch/riscv/SConscript
+++ b/src/arch/riscv/SConscript
@@ -52,6 +52,7 @@
Source('pagetable.cc')
Source('pagetable_walker.cc')
Source('pma_checker.cc')
+Source('pmp.cc')
Source('reg_abi.cc')
Source('remote_gdb.cc')
Source('tlb.cc')
@@ -63,6 +64,7 @@
Source('bare_metal/fs_workload.cc')
SimObject('PMAChecker.py')
+SimObject('PMP.py')
SimObject('RiscvFsWorkload.py')
SimObject('RiscvInterrupts.py')
SimObject('RiscvISA.py')
@@ -72,6 +74,7 @@
DebugFlag('RiscvMisc')
DebugFlag('TLBVerbose')
+DebugFlag('PMP')
DebugFlag('PageTableWalker', \
"Page table walker state machine debugging")
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index c6f0ca0..177957b 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -35,7 +35,9 @@
#include
#include
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv,util: fix the default cross compiler for riscv
Ayaz Akram has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/43607 )
Change subject: arch-riscv,util: fix the default cross compiler for riscv
..
arch-riscv,util: fix the default cross compiler for riscv
Change-Id: I44b5f10fd9d0f3b7ac25a1adad16d5acaa44ddc3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43607
Reviewed-by: Jason Lowe-Power
Maintainer: Gabe Black
Tested-by: kokoro
---
M util/m5/src/abi/riscv/SConsopts
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/util/m5/src/abi/riscv/SConsopts
b/util/m5/src/abi/riscv/SConsopts
index e46ef74..203cb6f 100644
--- a/util/m5/src/abi/riscv/SConsopts
+++ b/util/m5/src/abi/riscv/SConsopts
@@ -26,7 +26,7 @@
Import('*')
env['ABI'] = 'riscv'
-get_abi_opt('CROSS_COMPILE', 'riscv64-linux-gnu-')
+get_abi_opt('CROSS_COMPILE', 'riscv64-unknown-linux-gnu-')
get_abi_opt('QEMU_ARCH', 'riscv64')
env['CALL_TYPE']['inst'].impl('m5op.S', 'verify_inst.cc', default=True)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/43607
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I44b5f10fd9d0f3b7ac25a1adad16d5acaa44ddc3
Gerrit-Change-Number: 43607
Gerrit-PatchSet: 2
Gerrit-Owner: Ayaz Akram
Gerrit-Reviewer: Ayaz Akram
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv,util: fix the default cross compiler for riscv
Ayaz Akram has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/43607 )
Change subject: arch-riscv,util: fix the default cross compiler for riscv
..
arch-riscv,util: fix the default cross compiler for riscv
Change-Id: I44b5f10fd9d0f3b7ac25a1adad16d5acaa44ddc3
---
M util/m5/src/abi/riscv/SConsopts
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/m5/src/abi/riscv/SConsopts
b/util/m5/src/abi/riscv/SConsopts
index e46ef74..203cb6f 100644
--- a/util/m5/src/abi/riscv/SConsopts
+++ b/util/m5/src/abi/riscv/SConsopts
@@ -26,7 +26,7 @@
Import('*')
env['ABI'] = 'riscv'
-get_abi_opt('CROSS_COMPILE', 'riscv64-linux-gnu-')
+get_abi_opt('CROSS_COMPILE', 'riscv64-unknown-linux-gnu-')
get_abi_opt('QEMU_ARCH', 'riscv64')
env['CALL_TYPE']['inst'].impl('m5op.S', 'verify_inst.cc', default=True)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/43607
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I44b5f10fd9d0f3b7ac25a1adad16d5acaa44ddc3
Gerrit-Change-Number: 43607
Gerrit-PatchSet: 1
Gerrit-Owner: Ayaz Akram
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv,util: Add m5op.S for riscv to enable pseudo inst use
Ayaz Akram has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/38515 )
Change subject: arch-riscv,util: Add m5op.S for riscv to enable pseudo inst
use
..
arch-riscv,util: Add m5op.S for riscv to enable pseudo inst use
This change adds assembly code for riscv pseudo instructions so
that they can be used with riscv benchmarks.
Change-Id: Ic979fd375e7750e92f52b900bf39e351f629fe2c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38515
Reviewed-by: Jason Lowe-Power
Reviewed-by: Gabe Black
Maintainer: Jason Lowe-Power
Maintainer: Gabe Black
Tested-by: kokoro
---
M util/m5/README.md
A util/m5/src/abi/riscv/SConsopts
A util/m5/src/abi/riscv/m5op.S
A util/m5/src/abi/riscv/verify_inst.cc
4 files changed, 137 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, but someone else must approve; Looks
good to me, approved
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/util/m5/README.md b/util/m5/README.md
index cbdff1d..9bae153 100644
--- a/util/m5/README.md
+++ b/util/m5/README.md
@@ -98,6 +98,7 @@
thumb | ARM thumb| instruction
sparc | 64 bit SPARC | instruction
x86 | amd64/x86_64 | instruction, address
+ riscv | 64 bit RISCV | instruction
## SCons
@@ -166,6 +167,7 @@
thumb | arm | arm-linux-gnueabihf-
sparc | sparc64 | sparc64-linux-gnu-
x86 | x86_64|
+ riscv | riscv64 | riscv64-linux-gnu-
Note that the default setting for the x86 cross compiler prefix is blank,
meaning that the native/host compiler will be used. If building on a
non-x86
@@ -254,6 +256,7 @@
thumb | instruction
sparc | instruction
x86 | address
+ riscv | instruction
The default is usually to use a magic instruction, which for most ABIs is
the
only mechanism that's supported, and is what the m5 utility would
diff --git a/util/m5/src/abi/riscv/SConsopts
b/util/m5/src/abi/riscv/SConsopts
new file mode 100644
index 000..e46ef74
--- /dev/null
+++ b/util/m5/src/abi/riscv/SConsopts
@@ -0,0 +1,32 @@
+# Copyright 2020 Google, Inc.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+Import('*')
+
+env['ABI'] = 'riscv'
+get_abi_opt('CROSS_COMPILE', 'riscv64-linux-gnu-')
+get_abi_opt('QEMU_ARCH', 'riscv64')
+
+env['CALL_TYPE']['inst'].impl('m5op.S', 'verify_inst.cc', default=True)
diff --git a/util/m5/src/abi/riscv/m5op.S b/util/m5/src/abi/riscv/m5op.S
new file mode 100644
index 000..babe854
--- /dev/null
+++ b/util/m5/src/abi/riscv/m5op.S
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2020 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv,util: Add m5op.S for riscv to enable pseudo inst use
Ayaz Akram has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/38515 )
Change subject: arch-riscv,util: Add m5op.S for riscv to enable pseudo inst
use
..
arch-riscv,util: Add m5op.S for riscv to enable pseudo inst use
This change adds assembly code for riscv pseudo instructions so
that they can be used with riscv benchmarks.
Change-Id: Ic979fd375e7750e92f52b900bf39e351f629fe2c
---
A util/m5/src/abi/riscv/SConsopts
A util/m5/src/abi/riscv/m5op.S
A util/m5/src/abi/riscv/verify_inst.cc
3 files changed, 109 insertions(+), 0 deletions(-)
diff --git a/util/m5/src/abi/riscv/SConsopts
b/util/m5/src/abi/riscv/SConsopts
new file mode 100644
index 000..e46ef74
--- /dev/null
+++ b/util/m5/src/abi/riscv/SConsopts
@@ -0,0 +1,32 @@
+# Copyright 2020 Google, Inc.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+Import('*')
+
+env['ABI'] = 'riscv'
+get_abi_opt('CROSS_COMPILE', 'riscv64-linux-gnu-')
+get_abi_opt('QEMU_ARCH', 'riscv64')
+
+env['CALL_TYPE']['inst'].impl('m5op.S', 'verify_inst.cc', default=True)
diff --git a/util/m5/src/abi/riscv/m5op.S b/util/m5/src/abi/riscv/m5op.S
new file mode 100644
index 000..c80a284
--- /dev/null
+++ b/util/m5/src/abi/riscv/m5op.S
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2003-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include
+
+.macro m5op_func, name, func
+.globl \name
+\name:
+.long 0x007b | (\func << 25)
+ret
+.endm
+
+.text
+#define M5OP(name, func) m5op_func name, func;
+M5OP_FOREACH
+#undef M5OP
diff --git a/util/m5/src/abi/riscv/verify_inst.cc
b/util/m5/src/abi/riscv/verify_inst.cc
new file mode 100644
index 000..7370e9e
--- /dev/null
+++ b/util/m5/src/abi/riscv/verify_inst.cc
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2020 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
[gem5-dev] Change in gem5/gem5[develop]: stats: Update Ticked class stats
Ayaz Akram has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/37397 )
Change subject: stats: Update Ticked class stats
..
stats: Update Ticked class stats
This change updates the Ticked class to
use new style stats.
Change-Id: Iaf244e436cadb51f3684d4dd4a18012bc46fd9ee
---
M src/cpu/minor/cpu.cc
M src/cpu/minor/ticked.cc
M src/cpu/minor/ticked.hh
3 files changed, 14 insertions(+), 26 deletions(-)
diff --git a/src/cpu/minor/cpu.cc b/src/cpu/minor/cpu.cc
old mode 100644
new mode 100755
index 18a3fee..8319a69
--- a/src/cpu/minor/cpu.cc
+++ b/src/cpu/minor/cpu.cc
@@ -114,7 +114,6 @@
{
BaseCPU::regStats();
stats.regStats(name(), *this);
-pipeline->regStats();
}
void
diff --git a/src/cpu/minor/ticked.cc b/src/cpu/minor/ticked.cc
old mode 100644
new mode 100755
index 0448a16..c09a9b4
--- a/src/cpu/minor/ticked.cc
+++ b/src/cpu/minor/ticked.cc
@@ -37,7 +37,6 @@
#include "cpu/minor/ticked.hh"
-#include "params/Ticked.hh"
#include "sim/clocked_object.hh"
Ticked::Ticked(ClockedObject _,
@@ -47,15 +46,14 @@
event([this]{ processClockEvent(); }, object_.name(), false, priority),
running(false),
lastStopped(0),
-/* Allocate numCycles if an external stat wasn't passed in */
-numCyclesLocal((imported_num_cycles ? NULL : new Stats::Scalar)),
-numCycles((imported_num_cycles ? *imported_num_cycles :
-*numCyclesLocal))
+// Pass the external cycles stat to numCycles.
+numCycles(*imported_num_cycles),
+stats(_, numCycles)
{ }
void
Ticked::processClockEvent() {
-++tickCycles;
+++stats.tickCycles;
++numCycles;
countCycles(Cycles(1));
evaluate();
@@ -63,23 +61,14 @@
object.schedule(event, object.clockEdge(Cycles(1)));
}
-void
-Ticked::regStats()
+Ticked::TickedStats::TickedStats(ClockedObject *parent,
+Stats::Scalar ) : Stats::Group(parent),
+ ADD_STAT(tickCycles,
+"Number of cycles that the object actually ticked."),
+ ADD_STAT(idleCycles, "Total number of cycles that the object"
+"has spent stopped.", numCycles - tickCycles)
{
-if (numCyclesLocal) {
-numCycles
-.name(object.name() + ".totalTickCycles")
-.desc("Number of cycles that the object ticked or was
stopped");
-}
-tickCycles
-.name(object.name() + ".tickCycles")
-.desc("Number of cycles that the object actually ticked");
-
-idleCycles
-.name(object.name() + ".idleCycles")
-.desc("Total number of cycles that the object has spent stopped");
-idleCycles = numCycles - tickCycles;
}
void
diff --git a/src/cpu/minor/ticked.hh b/src/cpu/minor/ticked.hh
old mode 100644
new mode 100755
index b89befe..bc4a231
--- a/src/cpu/minor/ticked.hh
+++ b/src/cpu/minor/ticked.hh
@@ -78,11 +78,15 @@
/** Total number of cycles either ticked or spend stopped */
Stats::Scalar
+struct TickedStats : public Stats::Group {
+ TickedStats(ClockedObject *parent, Stats::Scalar );
+
/** Number of cycles ticked */
Stats::Scalar tickCycles;
/** Number of cycles stopped */
Stats::Formula idleCycles;
+} stats;
public:
Ticked(ClockedObject _,
@@ -91,10 +95,6 @@
virtual ~Ticked() { }
-/** Register {num,ticks}Cycles if necessary. If numCycles is
- * imported, be sure to register it *before* calling this regStats */
-void regStats();
-
/** Start ticking */
void
start()
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iaf244e436cadb51f3684d4dd4a18012bc46fd9ee
Gerrit-Change-Number: 37397
Gerrit-PatchSet: 1
Gerrit-Owner: Ayaz Akram
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: misc: get rid of TickedObject
Ayaz Akram has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/37395 )
Change subject: misc: get rid of TickedObject
..
misc: get rid of TickedObject
TickedObject is not used by anything else.
This change removes TickedObject and keeps only
Ticked class which is used by MinorCPU only.
Change-Id: I625052f466ab27aca74f55b706dc12929af44ab6
---
M src/sim/SConscript
R src/sim/Ticked.py
R src/sim/ticked.cc
R src/sim/ticked.hh
4 files changed, 10 insertions(+), 59 deletions(-)
diff --git a/src/sim/SConscript b/src/sim/SConscript
index 78d9bf5..fcde7ee 100644
--- a/src/sim/SConscript
+++ b/src/sim/SConscript
@@ -29,7 +29,7 @@
Import('*')
SimObject('ClockedObject.py')
-SimObject('TickedObject.py')
+SimObject('Ticked.py')
SimObject('Workload.py')
SimObject('Root.py')
SimObject('ClockDomain.py')
@@ -67,7 +67,7 @@
Source('sim_events.cc')
Source('sim_object.cc')
Source('sub_system.cc')
-Source('ticked_object.cc')
+Source('ticked.cc')
Source('simulate.cc')
Source('stat_control.cc')
Source('stat_register.cc', add_tags='python')
diff --git a/src/sim/TickedObject.py b/src/sim/Ticked.py
similarity index 96%
rename from src/sim/TickedObject.py
rename to src/sim/Ticked.py
index 283edff..5161b9c 100644
--- a/src/sim/TickedObject.py
+++ b/src/sim/Ticked.py
@@ -36,6 +36,6 @@
from m5.objects.ClockedObject import ClockedObject
class TickedObject(ClockedObject):
-type = 'TickedObject'
+type = 'Ticked'
abstract = True
-cxx_header = "sim/ticked_object.hh"
+cxx_header = "sim/ticked.hh"
diff --git a/src/sim/ticked_object.cc b/src/sim/ticked.cc
similarity index 87%
rename from src/sim/ticked_object.cc
rename to src/sim/ticked.cc
index 3564b4d..11dfc70 100644
--- a/src/sim/ticked_object.cc
+++ b/src/sim/ticked.cc
@@ -35,9 +35,9 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include "sim/ticked_object.hh"
+#include "sim/ticked.hh"
-#include "params/TickedObject.hh"
+#include "params/Ticked.hh"
#include "sim/clocked_object.hh"
Ticked::Ticked(ClockedObject _,
@@ -105,30 +105,3 @@
lastStopped = Cycles(lastStoppedUint);
}
-
-TickedObject::TickedObject(const TickedObjectParams ,
-Event::Priority priority) :
-ClockedObject(params),
-/* Make numCycles in Ticked */
-Ticked(*this, NULL, priority)
-{ }
-
-void
-TickedObject::regStats()
-{
-Ticked::regStats();
-ClockedObject::regStats();
-}
-
-void
-TickedObject::serialize(CheckpointOut ) const
-{
-Ticked::serialize(cp);
-ClockedObject::serialize(cp);
-}
-void
-TickedObject::unserialize(CheckpointIn )
-{
-Ticked::unserialize(cp);
-ClockedObject::unserialize(cp);
-}
diff --git a/src/sim/ticked_object.hh b/src/sim/ticked.hh
similarity index 84%
rename from src/sim/ticked_object.hh
rename to src/sim/ticked.hh
index 3991618..b89befe 100644
--- a/src/sim/ticked_object.hh
+++ b/src/sim/ticked.hh
@@ -39,17 +39,14 @@
* @file
*
* Base classes for ClockedObjects which have evaluate functions to
- * look like clock ticking operations. TickedObject attaches gem5's event
- * queue to Ticked to apply actual scheduling.
+ * look like clock ticking operations.
*/
-#ifndef __SIM_TICKED_OBJECT_HH__
-#define __SIM_TICKED_OBJECT_HH__
+#ifndef __SIM_TICKED_HH__
+#define __SIM_TICKED_HH__
#include "sim/clocked_object.hh"
-class TickedObjectParams;
-
/** Ticked attaches gem5's event queue/scheduler to evaluate
* calls and provides a start/stop interface to ticking.
*
@@ -158,23 +155,4 @@
virtual void countCycles(Cycles delta) {}
};
-/** TickedObject attaches Ticked to ClockedObject and can be used as
- * a base class where ticked operation */
-class TickedObject : public ClockedObject, public Ticked
-{
- public:
-TickedObject(const TickedObjectParams ,
-Event::Priority priority = Event::CPU_Tick_Pri);
-
-/** Disambiguate to make these functions overload correctly */
-using ClockedObject::regStats;
-using ClockedObject::serialize;
-using ClockedObject::unserialize;
-
-/** Pass on regStats, serialize etc. onto Ticked */
-void regStats() override;
-void serialize(CheckpointOut ) const override;
-void unserialize(CheckpointIn ) override;
-};
-
-#endif /* __SIM_TICKED_OBJECT_HH__ */
+#endif /* __SIM_TICKED_HH__ */
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/37395
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I625052f466ab27aca74f55b706dc12929af44ab6
Gerrit-Change-Number: 37395
Gerrit-PatchSet: 1
Gerrit-Owner: Ayaz Akram
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: mem: Add support to tag tlb entries with PCID
Ayaz Akram has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/35836 )
Change subject: mem: Add support to tag tlb entries with PCID
..
mem: Add support to tag tlb entries with PCID
This change adds support to tag tlb entries with PCID to
avoid the conflict between different processes with same
virtual addresses sharing a tlb. This eventually is required
to enable smt support for x86.
Change-Id: Ia91dc371482793962e3fc83afe7a3fd2cdb60eab
---
M src/arch/x86/pagetable_walker.cc
M src/arch/x86/tlb.cc
M src/arch/x86/tlb.hh
3 files changed, 49 insertions(+), 8 deletions(-)
diff --git a/src/arch/x86/pagetable_walker.cc
b/src/arch/x86/pagetable_walker.cc
index fd9d043..07d20b4 100644
--- a/src/arch/x86/pagetable_walker.cc
+++ b/src/arch/x86/pagetable_walker.cc
@@ -510,8 +510,22 @@
}
if (doEndWalk) {
if (doTLBInsert)
-if (!functional)
-walker->tlb->insert(entry.vaddr, entry);
+if (!functional) {
+
+// Check if PCIDE is set in CR4
+CR4 cr4 = tc->readMiscRegNoEffect(MISCREG_CR4);
+if (cr4.pcide){
+CR3 cr3 = tc->readMiscRegNoEffect(MISCREG_CR3);
+walker->tlb->insert(entry.vaddr, entry, cr3.pcid);
+}
+else{
+// The current PCID is always 000H if PCIDE
+// is not set [sec 4.10.1 of Intel's Software
+// Developer Manual]
+walker->tlb->insert(entry.vaddr, entry, 0x000);
+}
+}
+
endWalk();
} else {
PacketPtr oldRead = read;
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 11ce660..0eebdcf 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -94,8 +94,14 @@
}
TlbEntry *
-TLB::insert(Addr vpn, const TlbEntry )
+TLB::insert(Addr vpn, const TlbEntry , uint64_t pcid)
{
+//Adding pcid to the page address so
+//that multiple processes using the same
+//tlb do not conflict when using the same
+//virtual addresses
+vpn = concAddrPcid(vpn, pcid);
+
// If somebody beat us to it, just use that existing entry.
TlbEntry *newEntry = trie.lookup(vpn);
if (newEntry) {
@@ -113,7 +119,7 @@
newEntry->lruSeq = nextSeq();
newEntry->vaddr = vpn;
newEntry->trieHandle =
-trie.insert(vpn, TlbEntryTrie::MaxBits - entry.logBytes, newEntry);
+trie.insert(vpn, TlbEntryTrie::MaxBits, newEntry);
return newEntry;
}
@@ -371,7 +377,22 @@
if (m5Reg.paging) {
DPRINTF(TLB, "Paging enabled.\n");
// The vaddr already has the segment base applied.
-TlbEntry *entry = lookup(vaddr);
+
+//Appending the pcid (last 12 bits of CR3) to the
+//page aligned vaddr if pcide is set
+CR4 cr4 = tc->readMiscRegNoEffect(MISCREG_CR4);
+Addr pageAlignedVaddr = vaddr & mask(X86ISA::PageShift);
+CR3 cr3 = tc->readMiscRegNoEffect(MISCREG_CR3);
+uint64_t pcid;
+
+if (cr4.pcide)
+pcid = cr3.pcid;
+else
+pcid = 0x000;
+
+pageAlignedVaddr = concAddrPcid(pageAlignedVaddr, pcid);
+TlbEntry *entry = lookup(pageAlignedVaddr);
+
if (mode == Read) {
stats.rdAccesses++;
} else {
@@ -393,7 +414,7 @@
delayedResponse = true;
return fault;
}
-entry = lookup(vaddr);
+entry = lookup(pageAlignedVaddr);
assert(entry);
} else {
Process *p = tc->getProcessPtr();
@@ -409,7 +430,8 @@
entry = insert(alignedVaddr, TlbEntry(
p->pTable->pid(), alignedVaddr, pte->paddr,
pte->flags &
EmulationPageTable::Uncacheable,
-pte->flags &
EmulationPageTable::ReadOnly));
+pte->flags & EmulationPageTable::ReadOnly),
+pcid);
}
DPRINTF(TLB, "Miss was serviced.\n");
}
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index 671b165..c5fe3a6 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -73,6 +73,11 @@
TlbEntry *lookup(Addr va, bool update_lru = true);
void setConfigAddress(uint32_t addr);
+//concatenate Page Addr and pcid
+inline Addr concAddrPcid(Addr vpn, uint64_t pcid)
+{
+ return (vpn | pcid);
+}
protected:
@@ -150,7 +155,7 @@
Fault finalizePhysical(const RequestPtr , ThreadContext *tc,
Mode mode) const override;
-TlbEntry
[gem5-dev] Change in gem5/gem5[develop]: mem: Add support for PCID to x86
Ayaz Akram has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/35835 )
Change subject: mem: Add support for PCID to x86
..
mem: Add support for PCID to x86
This change adds Process Context Identifier (PCID) support
to x86, so that tlb entries can be tagged using pcid.
Change-Id: I695eccc4b08476b32d4b3728fc3c42b2ad6f5a28
---
M src/arch/x86/cpuid.cc
M src/arch/x86/pagetable_walker.cc
M src/arch/x86/process.cc
M src/arch/x86/regs/misc.hh
4 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/src/arch/x86/cpuid.cc b/src/arch/x86/cpuid.cc
index 64d4544..0210111 100644
--- a/src/arch/x86/cpuid.cc
+++ b/src/arch/x86/cpuid.cc
@@ -102,7 +102,7 @@
break;
case FamilyModelSteppingBrandFeatures:
result = CpuidResult(0x00020f51, 0x0405,
- 0xe3d3fbff, 0x0001);
+ 0xe3d3fbff, 0x00020001);
break;
case NameString1:
case NameString2:
diff --git a/src/arch/x86/pagetable_walker.cc
b/src/arch/x86/pagetable_walker.cc
index f5b5521..fd9d043 100644
--- a/src/arch/x86/pagetable_walker.cc
+++ b/src/arch/x86/pagetable_walker.cc
@@ -549,6 +549,7 @@
{
VAddr addr = vaddr;
CR3 cr3 = tc->readMiscRegNoEffect(MISCREG_CR3);
+CR4 cr4 = tc->readMiscRegNoEffect(MISCREG_CR4);
// Check if we're in long mode or not
Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER);
dataSize = 8;
@@ -560,7 +561,6 @@
enableNX = efer.nxe;
} else {
// We're in some flavor of legacy mode.
-CR4 cr4 = tc->readMiscRegNoEffect(MISCREG_CR4);
if (cr4.pae) {
// Do legacy PAE.
state = PAEPDP;
@@ -584,7 +584,10 @@
entry.vaddr = vaddr;
Request::Flags flags = Request::PHYSICAL;
-if (cr3.pcd)
+
+// PCD can't be used if CR4.PCIDE=1 [sec 2.5
+// of Intel's Software Developer's manual]
+if (!cr4.pcide && cr3.pcd)
flags.set(Request::UNCACHEABLE);
RequestPtr request = std::make_shared(
diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc
index 7718fdc..2d0439f 100644
--- a/src/arch/x86/process.cc
+++ b/src/arch/x86/process.cc
@@ -580,6 +580,17 @@
tc->setMiscReg(MISCREG_CR0, cr0);
tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
+
+// Setting CR3 to the process pid so that concatinated
+// page addr with lower 12 bits of CR3 can be used in SE
+// mode as well to avoid conflicts between tlb entries with
+// same virtual addresses belonging to different processes
+tc->setMiscReg(MISCREG_CR3, pTable->pid());
+
+// Setting pcide bit in CR4
+CR4 cr4 = 0;
+cr4.pcide = 1;
+tc->setMiscReg(MISCREG_CR4, cr4);
}
}
}
diff --git a/src/arch/x86/regs/misc.hh b/src/arch/x86/regs/misc.hh
index 42b1862..2de38a6 100644
--- a/src/arch/x86/regs/misc.hh
+++ b/src/arch/x86/regs/misc.hh
@@ -616,12 +616,14 @@
// Base Address
Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table
// Base Address
+Bitfield<11, 0> pcid; // Process-Context Identifier
Bitfield<4> pcd; // Page-Level Cache Disable
Bitfield<3> pwt; // Page-Level Writethrough
EndBitUnion(CR3)
BitUnion64(CR4)
Bitfield<18> osxsave; // Enable XSAVE and Proc Extended States
+Bitfield<17> pcide; // PCID Enable
Bitfield<16> fsgsbase; // Enable RDFSBASE, RDGSBASE, WRFSBASE,
// WRGSBASE instructions
Bitfield<10> osxmmexcpt; // Operating System Unmasked
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I695eccc4b08476b32d4b3728fc3c42b2ad6f5a28
Gerrit-Change-Number: 35835
Gerrit-PatchSet: 1
Gerrit-Owner: Ayaz Akram
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[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Append thread number to APIC id
Ayaz Akram has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/35837 ) Change subject: arch-x86: Append thread number to APIC id .. arch-x86: Append thread number to APIC id This change appends the smt thread number to APIC id to enable smt support for x86 Change-Id: I3e7034b358623577c5ad4be3e51f08e48291ce49 --- M src/arch/x86/interrupts.cc 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/arch/x86/interrupts.cc b/src/arch/x86/interrupts.cc index 7767c80..c955f67 100644 --- a/src/arch/x86/interrupts.cc +++ b/src/arch/x86/interrupts.cc @@ -279,7 +279,8 @@ BaseInterrupts::setThreadContext(_tc); -initialApicId = tc->cpuId(); +//Update APIC id to consider SMT threads +initialApicId = (tc->cpuId() << sys->threads.size()) + _tc->threadId(); regs[APIC_ID] = (initialApicId << 24); pioAddr = x86LocalAPICAddress(initialApicId, 0); } -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/35837 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I3e7034b358623577c5ad4be3e51f08e48291ce49 Gerrit-Change-Number: 35837 Gerrit-PatchSet: 1 Gerrit-Owner: Ayaz Akram Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: arch-riscv,tests: small update to make gem5.fast compile
Ayaz Akram has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28893 )
Change subject: arch-riscv,tests: small update to make gem5.fast compile
..
arch-riscv,tests: small update to make gem5.fast compile
This small change is meant to enable gem5.fast compilation
for riscv. Also, the riscv tests based on gem5.fast
work now and are removed from .testignore.
Change-Id: Id9c96d8e4682a74ec1d77a66eae53d6f9b64d302
Issue-On: https://gem5.atlassian.net/browse/GEM5-526
Issue-On: https://gem5.atlassian.net/browse/GEM5-527
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28893
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/riscv/pagetable_walker.cc
M tests/gem5/.testignore
2 files changed, 2 insertions(+), 8 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/riscv/pagetable_walker.cc
b/src/arch/riscv/pagetable_walker.cc
index 6ec118d..786cb81 100644
--- a/src/arch/riscv/pagetable_walker.cc
+++ b/src/arch/riscv/pagetable_walker.cc
@@ -386,10 +386,9 @@
if (!functional)
walker->tlb->insert(entry.vaddr, entry);
else {
-Addr offset = entry.vaddr & mask(entry.logBytes);
-Addr paddr = entry.paddr << PageShift | offset;
DPRINTF(PageTableWalker, "Translated %#x -> %#x\n",
-entry.vaddr, paddr);
+entry.vaddr, entry.paddr << PageShift |
+(entry.vaddr & mask(entry.logBytes)));
}
}
endWalk();
diff --git a/tests/gem5/.testignore b/tests/gem5/.testignore
index cc61aa6..b8cfc7f 100644
--- a/tests/gem5/.testignore
+++ b/tests/gem5/.testignore
@@ -20,12 +20,7 @@
test-insttest-rv64i-linux-DerivO3CPU-RISCV-x86_64-debug
test-insttest-linux-AtomicSimpleCPU-SPARC-x86_64-debug
test-insttest-linux-TimingSimpleCPU-SPARC-x86_64-debug
-test-insttest-rv64a-linux-MinorCPU-RISCV-x86_64-fast
-test-insttest-rv64c-linux-MinorCPU-RISCV-x86_64-fast
-test-insttest-rv64d-linux-MinorCPU-RISCV-x86_64-fast
-test-insttest-rv64f-linux-MinorCPU-RISCV-x86_64-fast
test-insttest-rv64i-linux-MinorCPU-RISCV-x86_64-fast
-test-insttest-rv64m-linux-MinorCPU-RISCV-x86_64-fast
test-insttest-rv64i-linux-AtomicSimpleCPU-RISCV-x86_64-fast
test-insttest-rv64i-linux-TimingSimpleCPU-RISCV-x86_64-fast
test-insttest-rv64i-linux-DerivO3CPU-RISCV-x86_64-fast
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28893
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v20.0.0.0
Gerrit-Change-Id: Id9c96d8e4682a74ec1d77a66eae53d6f9b64d302
Gerrit-Change-Number: 28893
Gerrit-PatchSet: 2
Gerrit-Owner: Ayaz Akram
Gerrit-Reviewer: Ayaz Akram
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: arch-riscv,tests: small update to make gem5.fast compile
Ayaz Akram has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28893 )
Change subject: arch-riscv,tests: small update to make gem5.fast compile
..
arch-riscv,tests: small update to make gem5.fast compile
This small change is meant to enable gem5.fast compilation
for riscv. Also, the riscv tests based on gem5.fast
work now and are removed from .testignore.
Change-Id: Id9c96d8e4682a74ec1d77a66eae53d6f9b64d302
Issue-On: https://gem5.atlassian.net/browse/GEM5-526
Issue-On: https://gem5.atlassian.net/browse/GEM5-527
---
M src/arch/riscv/pagetable_walker.cc
M tests/gem5/.testignore
2 files changed, 2 insertions(+), 8 deletions(-)
diff --git a/src/arch/riscv/pagetable_walker.cc
b/src/arch/riscv/pagetable_walker.cc
index 6ec118d..786cb81 100644
--- a/src/arch/riscv/pagetable_walker.cc
+++ b/src/arch/riscv/pagetable_walker.cc
@@ -386,10 +386,9 @@
if (!functional)
walker->tlb->insert(entry.vaddr, entry);
else {
-Addr offset = entry.vaddr & mask(entry.logBytes);
-Addr paddr = entry.paddr << PageShift | offset;
DPRINTF(PageTableWalker, "Translated %#x -> %#x\n",
-entry.vaddr, paddr);
+entry.vaddr, entry.paddr << PageShift |
+(entry.vaddr & mask(entry.logBytes)));
}
}
endWalk();
diff --git a/tests/gem5/.testignore b/tests/gem5/.testignore
index cc61aa6..b8cfc7f 100644
--- a/tests/gem5/.testignore
+++ b/tests/gem5/.testignore
@@ -20,12 +20,7 @@
test-insttest-rv64i-linux-DerivO3CPU-RISCV-x86_64-debug
test-insttest-linux-AtomicSimpleCPU-SPARC-x86_64-debug
test-insttest-linux-TimingSimpleCPU-SPARC-x86_64-debug
-test-insttest-rv64a-linux-MinorCPU-RISCV-x86_64-fast
-test-insttest-rv64c-linux-MinorCPU-RISCV-x86_64-fast
-test-insttest-rv64d-linux-MinorCPU-RISCV-x86_64-fast
-test-insttest-rv64f-linux-MinorCPU-RISCV-x86_64-fast
test-insttest-rv64i-linux-MinorCPU-RISCV-x86_64-fast
-test-insttest-rv64m-linux-MinorCPU-RISCV-x86_64-fast
test-insttest-rv64i-linux-AtomicSimpleCPU-RISCV-x86_64-fast
test-insttest-rv64i-linux-TimingSimpleCPU-RISCV-x86_64-fast
test-insttest-rv64i-linux-DerivO3CPU-RISCV-x86_64-fast
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28893
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v20.0.0.0
Gerrit-Change-Id: Id9c96d8e4682a74ec1d77a66eae53d6f9b64d302
Gerrit-Change-Number: 28893
Gerrit-PatchSet: 1
Gerrit-Owner: Ayaz Akram
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: mem-ruby: Deep renaming of Prefetcher to RubyPrefetcher
Ayaz Akram has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28667 )
Change subject: mem-ruby: Deep renaming of Prefetcher to RubyPrefetcher
..
mem-ruby: Deep renaming of Prefetcher to RubyPrefetcher
A recent change (https://gem5-review.googlesource.com/c/
public/gem5/+/27949) updated the ruby prefetcher name,
which breaks the use of old name in some SLICC files.
This change makes sure that the new name is used at all
places.
Issue-On: https://gem5.atlassian.net/browse/GEM5-498
Change-Id: Ic667b61eac13dc7c267cee7dce3aa970f7ae9a8b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28667
Reviewed-by: Timothy Hayes
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M configs/ruby/MESI_Three_Level.py
M configs/ruby/MESI_Two_Level.py
M src/mem/ruby/SConscript
M src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
M src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
M src/mem/ruby/protocol/RubySlicc_Types.sm
R src/mem/ruby/structures/RubyPrefetcher.cc
R src/mem/ruby/structures/RubyPrefetcher.hh
M src/mem/ruby/structures/RubyPrefetcher.py
M src/mem/ruby/structures/SConscript
M src/mem/slicc/symbols/StateMachine.py
11 files changed, 19 insertions(+), 15 deletions(-)
Approvals:
Timothy Hayes: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/configs/ruby/MESI_Three_Level.py
b/configs/ruby/MESI_Three_Level.py
index 61d6c52..0bd893e 100644
--- a/configs/ruby/MESI_Three_Level.py
+++ b/configs/ruby/MESI_Three_Level.py
@@ -121,7 +121,7 @@
clk_domain = system.cpu[i].clk_domain
# Ruby prefetcher
-prefetcher = RubyPrefetcher.Prefetcher(
+prefetcher = RubyPrefetcher(
num_streams=16,
unit_filter = 256,
nonunit_filter = 256,
diff --git a/configs/ruby/MESI_Two_Level.py b/configs/ruby/MESI_Two_Level.py
index 8d2e01f..3ddf8ef 100644
--- a/configs/ruby/MESI_Two_Level.py
+++ b/configs/ruby/MESI_Two_Level.py
@@ -78,7 +78,7 @@
start_index_bit = block_size_bits,
is_icache = False)
-prefetcher = RubyPrefetcher.Prefetcher()
+prefetcher = RubyPrefetcher()
# the ruby random tester reuses num_cpus to specify the
# number of cpu ports connected to the tester object, which
diff --git a/src/mem/ruby/SConscript b/src/mem/ruby/SConscript
index 8c22ae4..fc90f8a 100644
--- a/src/mem/ruby/SConscript
+++ b/src/mem/ruby/SConscript
@@ -126,7 +126,7 @@
MakeInclude('structures/DirectoryMemory.hh')
MakeInclude('structures/PerfectCacheMemory.hh')
MakeInclude('structures/PersistentTable.hh')
-MakeInclude('structures/Prefetcher.hh')
+MakeInclude('structures/RubyPrefetcher.hh')
MakeInclude('structures/TBETable.hh')
MakeInclude('structures/TimerTable.hh')
MakeInclude('structures/WireBuffer.hh')
diff --git a/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
b/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
index 3639ef2..4de4a29 100644
--- a/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
+++ b/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
@@ -46,7 +46,7 @@
Cycles response_latency := 2;
bool send_evictions;
- Prefetcher * prefetcher;
+ RubyPrefetcher * prefetcher;
bool enable_prefetch := "False";
// From this node's L0 cache to the network
diff --git a/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
b/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
index 7c83478..3e3580f 100644
--- a/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
+++ b/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
@@ -30,7 +30,7 @@
: Sequencer * sequencer;
CacheMemory * L1Icache;
CacheMemory * L1Dcache;
- Prefetcher * prefetcher;
+ RubyPrefetcher * prefetcher;
int l2_select_num_bits;
Cycles l1_request_latency := 2;
Cycles l1_response_latency := 2;
diff --git a/src/mem/ruby/protocol/RubySlicc_Types.sm
b/src/mem/ruby/protocol/RubySlicc_Types.sm
index 66d84fc..6ab0f3f 100644
--- a/src/mem/ruby/protocol/RubySlicc_Types.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Types.sm
@@ -246,7 +246,7 @@
bool isSet(Addr);
}
-structure (Prefetcher, external = "yes") {
+structure (RubyPrefetcher, external = "yes") {
void observeMiss(Addr, RubyRequestType);
void observePfHit(Addr);
void observePfMiss(Addr);
diff --git a/src/mem/ruby/structures/Prefetcher.cc
b/src/mem/ruby/structures/RubyPrefetcher.cc
similarity index 99%
rename from src/mem/ruby/structures/Prefetcher.cc
rename to src/mem/ruby/structures/RubyPrefetcher.cc
index 0602115..8646b99 100644
--- a/src/mem/ruby/structures/Prefetcher.cc
+++ b/src/mem/ruby/structures/RubyPrefetcher.cc
@@ -38,7 +38,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include "mem/ruby/structures/Prefetcher.hh"
+#include "mem/ruby/structures/RubyPrefetcher.hh"
[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: mem-ruby: Deep renaming of Prefetcher to RubyPrefetcher
Ayaz Akram has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28667 )
Change subject: mem-ruby: Deep renaming of Prefetcher to RubyPrefetcher
..
mem-ruby: Deep renaming of Prefetcher to RubyPrefetcher
A recent change (https://gem5-review.googlesource.com/c/
public/gem5/+/27949) updated the ruby prefetcher name,
which breaks the use of old name in some SLICC files.
This change makes sure that the new name is used at all
places.
JIRA: https://gem5.atlassian.net/browse/GEM5-498
Change-Id: Ic667b61eac13dc7c267cee7dce3aa970f7ae9a8b
---
M src/mem/ruby/SConscript
M src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
M src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
M src/mem/ruby/protocol/RubySlicc_Types.sm
R src/mem/ruby/structures/RubyPrefetcher.cc
R src/mem/ruby/structures/RubyPrefetcher.hh
M src/mem/ruby/structures/RubyPrefetcher.py
M src/mem/ruby/structures/SConscript
M src/mem/slicc/symbols/StateMachine.py
9 files changed, 17 insertions(+), 13 deletions(-)
diff --git a/src/mem/ruby/SConscript b/src/mem/ruby/SConscript
index 8c22ae4..fc90f8a 100644
--- a/src/mem/ruby/SConscript
+++ b/src/mem/ruby/SConscript
@@ -126,7 +126,7 @@
MakeInclude('structures/DirectoryMemory.hh')
MakeInclude('structures/PerfectCacheMemory.hh')
MakeInclude('structures/PersistentTable.hh')
-MakeInclude('structures/Prefetcher.hh')
+MakeInclude('structures/RubyPrefetcher.hh')
MakeInclude('structures/TBETable.hh')
MakeInclude('structures/TimerTable.hh')
MakeInclude('structures/WireBuffer.hh')
diff --git a/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
b/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
index 3639ef2..4de4a29 100644
--- a/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
+++ b/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
@@ -46,7 +46,7 @@
Cycles response_latency := 2;
bool send_evictions;
- Prefetcher * prefetcher;
+ RubyPrefetcher * prefetcher;
bool enable_prefetch := "False";
// From this node's L0 cache to the network
diff --git a/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
b/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
index 7c83478..3e3580f 100644
--- a/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
+++ b/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
@@ -30,7 +30,7 @@
: Sequencer * sequencer;
CacheMemory * L1Icache;
CacheMemory * L1Dcache;
- Prefetcher * prefetcher;
+ RubyPrefetcher * prefetcher;
int l2_select_num_bits;
Cycles l1_request_latency := 2;
Cycles l1_response_latency := 2;
diff --git a/src/mem/ruby/protocol/RubySlicc_Types.sm
b/src/mem/ruby/protocol/RubySlicc_Types.sm
index 66d84fc..6ab0f3f 100644
--- a/src/mem/ruby/protocol/RubySlicc_Types.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Types.sm
@@ -246,7 +246,7 @@
bool isSet(Addr);
}
-structure (Prefetcher, external = "yes") {
+structure (RubyPrefetcher, external = "yes") {
void observeMiss(Addr, RubyRequestType);
void observePfHit(Addr);
void observePfMiss(Addr);
diff --git a/src/mem/ruby/structures/Prefetcher.cc
b/src/mem/ruby/structures/RubyPrefetcher.cc
similarity index 99%
rename from src/mem/ruby/structures/Prefetcher.cc
rename to src/mem/ruby/structures/RubyPrefetcher.cc
index 0602115..8646b99 100644
--- a/src/mem/ruby/structures/Prefetcher.cc
+++ b/src/mem/ruby/structures/RubyPrefetcher.cc
@@ -38,7 +38,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include "mem/ruby/structures/Prefetcher.hh"
+#include "mem/ruby/structures/RubyPrefetcher.hh"
#include "base/bitfield.hh"
#include "debug/RubyPrefetcher.hh"
@@ -46,7 +46,7 @@
#include "mem/ruby/system/RubySystem.hh"
RubyPrefetcher*
-PrefetcherParams::create()
+RubyPrefetcherParams::create()
{
return new RubyPrefetcher(this);
}
diff --git a/src/mem/ruby/structures/Prefetcher.hh
b/src/mem/ruby/structures/RubyPrefetcher.hh
similarity index 98%
rename from src/mem/ruby/structures/Prefetcher.hh
rename to src/mem/ruby/structures/RubyPrefetcher.hh
index 4d2513f..b691d3d 100644
--- a/src/mem/ruby/structures/Prefetcher.hh
+++ b/src/mem/ruby/structures/RubyPrefetcher.hh
@@ -51,7 +51,7 @@
#include "mem/ruby/slicc_interface/AbstractController.hh"
#include "mem/ruby/slicc_interface/RubyRequest.hh"
#include "mem/ruby/system/RubySystem.hh"
-#include "params/Prefetcher.hh"
+#include "params/RubyPrefetcher.hh"
#include "sim/sim_object.hh"
#include "sim/system.hh"
@@ -93,7 +93,7 @@
class RubyPrefetcher : public SimObject
{
public:
-typedef PrefetcherParams Params;
+typedef RubyPrefetcherParams Params;
RubyPrefetcher(const Params *p);
~RubyPrefetcher();
diff --git a/src/mem/ruby/structures/RubyPrefetcher.py
b/src/mem/ruby/structures/RubyPrefetcher.py
index d762ba5..38397c3 100644
--- a/src/mem/ruby/structures/RubyPrefetcher.py
+++ b/src/mem/ruby/structures/RubyPrefetcher.py
@@ -42,10 +42,10 @@
from
[gem5-dev] Change in gem5/gem5[develop]: tests: update linux boot tests
Ayaz Akram has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28427 )
Change subject: tests: update linux boot tests
..
tests: update linux boot tests
This change updates the config scripts used by linux boot
tests to make them compatible with change that deprecated
LinuxX86System
JIRA: https://gem5.atlassian.net/browse/GEM5-440
Change-Id: I04beff2915c03a2c3a774351edbba60d7ff26867
Signed-off-by: Ayaz Akram
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28427
Maintainer: Bobby R. Bruce
Maintainer: Jason Lowe-Power
Reviewed-by: Jason Lowe-Power
Tested-by: kokoro
---
M tests/gem5/x86-boot-tests/run_exit.py
M tests/gem5/x86-boot-tests/system/system.py
2 files changed, 9 insertions(+), 8 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/tests/gem5/x86-boot-tests/run_exit.py
b/tests/gem5/x86-boot-tests/run_exit.py
index 24edcc5..ecb3a84 100644
--- a/tests/gem5/x86-boot-tests/run_exit.py
+++ b/tests/gem5/x86-boot-tests/run_exit.py
@@ -51,7 +51,7 @@
if args.boot_type == "init":
# Simply run "exit.sh"
-system.boot_osflags += ' init=/root/exit.sh'
+system.workload.command_line += ' init=/root/exit.sh'
else:
if args.boot_type != "systemd":
m5.fatal("Bad option for boot_type. init or systemd.")
diff --git a/tests/gem5/x86-boot-tests/system/system.py
b/tests/gem5/x86-boot-tests/system/system.py
index 0b69be9..c55664e 100755
--- a/tests/gem5/x86-boot-tests/system/system.py
+++ b/tests/gem5/x86-boot-tests/system/system.py
@@ -30,11 +30,12 @@
from caches import *
import sys
-class MySystem(LinuxX86System):
+class MySystem(System):
def __init__(self, kernel, disk, cpu_type, num_cpus):
super(MySystem, self).__init__()
+self.workload = X86FsLinux()
self._host_parallel = cpu_type == "kvm"
# Set up the clock domain and the voltage domain
@@ -63,12 +64,12 @@
self.setDiskImages(disk, disk)
# Change this path to point to the kernel you want to use
-self.kernel = kernel
+self.workload.object_file = kernel
# Options specified on the kernel command line
boot_options =
['earlyprintk=ttyS0', 'console=ttyS0', 'lpj=723',
'root=/dev/hda1']
-self.boot_osflags = ' '.join(boot_options)
+self.workload.command_line = ' '.join(boot_options)
# Create the CPUs for our system.
self.createCPU(cpu_type, num_cpus)
@@ -235,7 +236,7 @@
###
# Add in a Bios information structure.
-self.smbios_table.structures = [X86SMBiosBiosInformation()]
+self.workload.smbios_table.structures =
[X86SMBiosBiosInformation()]
# Set up the Intel MP table
base_entries = []
@@ -293,8 +294,8 @@
assignISAInt(1, 1)
for i in range(3, 15):
assignISAInt(i, i)
-self.intel_mp_table.base_entries = base_entries
-self.intel_mp_table.ext_entries = ext_entries
+self.workload.intel_mp_table.base_entries = base_entries
+self.workload.intel_mp_table.ext_entries = ext_entries
entries = \
[
@@ -311,7 +312,7 @@
entries.append(X86E820Entry(addr = 0x, size = '64kB',
range_type=2))
-self.e820_table.entries = entries
+self.workload.e820_table.entries = entries
class CowDisk(IdeDisk):
def __init__(self, filename):
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I04beff2915c03a2c3a774351edbba60d7ff26867
Gerrit-Change-Number: 28427
Gerrit-PatchSet: 3
Gerrit-Owner: Ayaz Akram
Gerrit-Reviewer: Ayaz Akram
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: tests: update linux boot tests
Ayaz Akram has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28427 )
Change subject: tests: update linux boot tests
..
tests: update linux boot tests
This change updates the config scripts used by linux boot
tests to make them compatible with change that deprecated
LinuxX86System
JIRA: https://gem5.atlassian.net/browse/GEM5-440
Change-Id: I04beff2915c03a2c3a774351edbba60d7ff26867
Signed-off-by: Ayaz Akram
---
M tests/gem5/x86-boot-tests/run_exit.py
M tests/gem5/x86-boot-tests/system/system.py
2 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/tests/gem5/x86-boot-tests/run_exit.py
b/tests/gem5/x86-boot-tests/run_exit.py
index 24edcc5..ecb3a84 100644
--- a/tests/gem5/x86-boot-tests/run_exit.py
+++ b/tests/gem5/x86-boot-tests/run_exit.py
@@ -51,7 +51,7 @@
if args.boot_type == "init":
# Simply run "exit.sh"
-system.boot_osflags += ' init=/root/exit.sh'
+system.workload.command_line += ' init=/root/exit.sh'
else:
if args.boot_type != "systemd":
m5.fatal("Bad option for boot_type. init or systemd.")
diff --git a/tests/gem5/x86-boot-tests/system/system.py
b/tests/gem5/x86-boot-tests/system/system.py
index 0b69be9..c55664e 100755
--- a/tests/gem5/x86-boot-tests/system/system.py
+++ b/tests/gem5/x86-boot-tests/system/system.py
@@ -30,11 +30,12 @@
from caches import *
import sys
-class MySystem(LinuxX86System):
+class MySystem(System):
def __init__(self, kernel, disk, cpu_type, num_cpus):
super(MySystem, self).__init__()
+self.workload = X86FsLinux()
self._host_parallel = cpu_type == "kvm"
# Set up the clock domain and the voltage domain
@@ -63,12 +64,12 @@
self.setDiskImages(disk, disk)
# Change this path to point to the kernel you want to use
-self.kernel = kernel
+self.workload.object_file = kernel
# Options specified on the kernel command line
boot_options =
['earlyprintk=ttyS0', 'console=ttyS0', 'lpj=723',
'root=/dev/hda1']
-self.boot_osflags = ' '.join(boot_options)
+self.workload.command_line = ' '.join(boot_options)
# Create the CPUs for our system.
self.createCPU(cpu_type, num_cpus)
@@ -235,7 +236,7 @@
###
# Add in a Bios information structure.
-self.smbios_table.structures = [X86SMBiosBiosInformation()]
+self.workload.smbios_table.structures =
[X86SMBiosBiosInformation()]
# Set up the Intel MP table
base_entries = []
@@ -293,8 +294,8 @@
assignISAInt(1, 1)
for i in range(3, 15):
assignISAInt(i, i)
-self.intel_mp_table.base_entries = base_entries
-self.intel_mp_table.ext_entries = ext_entries
+self.workload.intel_mp_table.base_entries = base_entries
+self.workload.intel_mp_table.ext_entries = ext_entries
entries = \
[
@@ -311,7 +312,7 @@
entries.append(X86E820Entry(addr = 0x, size = '64kB',
range_type=2))
-self.e820_table.entries = entries
+self.workload.e820_table.entries = entries
class CowDisk(IdeDisk):
def __init__(self, filename):
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28427
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I04beff2915c03a2c3a774351edbba60d7ff26867
Gerrit-Change-Number: 28427
Gerrit-PatchSet: 1
Gerrit-Owner: Ayaz Akram
Gerrit-MessageType: newchange
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