[gem5-dev] How to prefetch some specified address of store instruction in MinorCPU?
Hello all, I am implementing a data prefetcher that only prefetches the address of some store instructions. My application scenario is that we know which store will reside in the store buffer for a long while. Thus, it is beneficial to perform data prefetching over such sorts of stores. I've checked the existing prefetchers which are used together with cache and configured by python options. Somehow, it is not my goal. Is there someone who could help me out? Thanks, Jianping. ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] A question about setting the memory access latency of some stores to zero in Minor CPU model
Hello, I am working on a research project and need to dynamically set the memory access latency of some store instructions to 0 on a simulated gem5 Minor CPU+NVMain without cache. I have no idea where I should start to modify the code. Is there someone who might help me with this? Thanks, Jianping. ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
