[gem5-dev] Change in gem5/gem5[master]: ruby: 2x protocols has typo/syntax error that fails building

2019-09-28 Thread Timothy Hayes (Gerrit) 
Timothy Hayes has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/21259 )


Change subject: ruby: 2x protocols has typo/syntax error that fails building
..

ruby: 2x protocols has typo/syntax error that fails building

MOESI_hammer and MOESI_CMP_token contain incorrect lines.

Change-Id: I1f9ac429d0f4dcb0241f21c8c9b831bee7aa37a4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21259
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/mem/ruby/protocol/MOESI_CMP_token-L1cache.sm
M src/mem/ruby/protocol/MOESI_hammer-dir.sm
2 files changed, 0 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/ruby/protocol/MOESI_CMP_token-L1cache.sm  
b/src/mem/ruby/protocol/MOESI_CMP_token-L1cache.sm

index 960afda..17c518a 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_token-L1cache.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_token-L1cache.sm
@@ -695,7 +695,6 @@
   in_msg.LineAddress, L1Icache_entry, tbe);
 } else {
   // No room in the L1, so we need to make room
-  trigger(Event:L1_Replacement,
   Addr victim := L1Icache.cacheProbe(in_msg.LineAddress);
   trigger(Event:L1_Replacement,
   victim, getL1ICacheEntry(victim), L1_TBEs[victim]);
diff --git a/src/mem/ruby/protocol/MOESI_hammer-dir.sm  
b/src/mem/ruby/protocol/MOESI_hammer-dir.sm

index d85ff19..3b00168 100644
--- a/src/mem/ruby/protocol/MOESI_hammer-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_hammer-dir.sm
@@ -426,7 +426,6 @@
 trigger(cache_request_to_event(in_msg.Type), in_msg.addr,
 pf_entry, tbe);
   } else {
-trigger(Event:Pf_Replacement,
 Addr victim := probeFilter.cacheProbe(in_msg.addr);
 trigger(Event:Pf_Replacement,
 victim, getProbeFilterEntry(victim), TBEs[victim]);

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I1f9ac429d0f4dcb0241f21c8c9b831bee7aa37a4
Gerrit-Change-Number: 21259
Gerrit-PatchSet: 3
Gerrit-Owner: Timothy Hayes 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: JING QU 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Timothy Hayes 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Daniel Carvalho 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: ruby: 2x protocols has typo/syntax error that fails building

2019-09-27 Thread Timothy Hayes (Gerrit) 

Hello Andreas Sandberg, Jason Lowe-Power,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/21259

to look at the new patch set (#2).

Change subject: ruby: 2x protocols has typo/syntax error that fails building
..

ruby: 2x protocols has typo/syntax error that fails building

MOESI_hammer and MOESI_CMP_token contain incorrect lines.

Change-Id: I1f9ac429d0f4dcb0241f21c8c9b831bee7aa37a4
---
M src/mem/ruby/protocol/MOESI_CMP_token-L1cache.sm
M src/mem/ruby/protocol/MOESI_hammer-dir.sm
2 files changed, 0 insertions(+), 2 deletions(-)


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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I1f9ac429d0f4dcb0241f21c8c9b831bee7aa37a4
Gerrit-Change-Number: 21259
Gerrit-PatchSet: 2
Gerrit-Owner: Timothy Hayes 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-CC: Daniel Carvalho 
Gerrit-MessageType: newpatchset
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[gem5-dev] Change in gem5/gem5[master]: ruby: MOESI_hammer has typo/syntax error that fails building

2019-09-27 Thread Timothy Hayes (Gerrit) 
Timothy Hayes has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/21259 )



Change subject: ruby: MOESI_hammer has typo/syntax error that fails building
..

ruby: MOESI_hammer has typo/syntax error that fails building

Change-Id: I1f9ac429d0f4dcb0241f21c8c9b831bee7aa37a4
---
M src/mem/ruby/protocol/MOESI_hammer-dir.sm
1 file changed, 0 insertions(+), 1 deletion(-)



diff --git a/src/mem/ruby/protocol/MOESI_hammer-dir.sm  
b/src/mem/ruby/protocol/MOESI_hammer-dir.sm

index d85ff19..3b00168 100644
--- a/src/mem/ruby/protocol/MOESI_hammer-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_hammer-dir.sm
@@ -426,7 +426,6 @@
 trigger(cache_request_to_event(in_msg.Type), in_msg.addr,
 pf_entry, tbe);
   } else {
-trigger(Event:Pf_Replacement,
 Addr victim := probeFilter.cacheProbe(in_msg.addr);
 trigger(Event:Pf_Replacement,
 victim, getProbeFilterEntry(victim), TBEs[victim]);

--
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Gerrit-Branch: master
Gerrit-Change-Id: I1f9ac429d0f4dcb0241f21c8c9b831bee7aa37a4
Gerrit-Change-Number: 21259
Gerrit-PatchSet: 1
Gerrit-Owner: Timothy Hayes 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: multiple memory requests to same cache line

2019-09-24 Thread Timothy Hayes (Gerrit) 
Hello kokoro, Daniel Carvalho, Nikos Nikoleris, Bradford Beckmann, Anthony  
Gutierrez, Tuan Ta, Jason Lowe-Power, Nikos Nikoleris,


I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/21161

to look at the new patch set (#2).

Change subject: mem-ruby: multiple memory requests to same cache line
..

mem-ruby: multiple memory requests to same cache line

Ruby's Sequencer::insertRequest() is responsible for bookkeeping
memory requests before they are sent to the cache hierarchy. It
first checks if there are other outstanding requests to the
cache line and fails inserting accordingly. The failure in turn
informs the O3 core that the cache is blocked and no more memory
requests are sent that cycle. This is very restrictive and
unrealistic behaviour since it is common to load/store from/to
contiguous memory locations back to back (and therefore the same
cache line). This fix allows the Sequencer to augment some of
the outstanding memory requests with linked subrequests. This
loosely mimics MSHRs for loads and merge buffers for stores.

Change-Id: I270c2151709a5e3ce334d73594ad57654c5a0dd2
Signed-off-by: Timothy Hayes 
---
M src/mem/ruby/protocol/RubySlicc_Exports.sm
M src/mem/ruby/system/Sequencer.cc
M src/mem/ruby/system/Sequencer.hh
3 files changed, 105 insertions(+), 11 deletions(-)


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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I270c2151709a5e3ce334d73594ad57654c5a0dd2
Gerrit-Change-Number: 21161
Gerrit-PatchSet: 2
Gerrit-Owner: Timothy Hayes 
Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Bradford Beckmann 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: Tuan Ta 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Andreas Sandberg 
Gerrit-MessageType: newpatchset
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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: multiple memory requests to same cache line

2019-09-24 Thread Timothy Hayes (Gerrit) 
g write request for the same
@@ -230,8 +259,26 @@
 m_outstanding_count++;
 } else {
 // There is an outstanding read request for the cache line
-m_load_waiting_on_load++;
-return RequestStatus_Aliased;
+RequestTable::iterator i = r.first;
+assert(i->first == line_addr);
+SequencerRequest* in_flight_req = i->second;
+
+if ((request_type == RubyRequestType_LD ||
+ request_type == RubyRequestType_IFETCH) &&
+(request_type == in_flight_req->m_type)) {
+
+// iterate until finding an empty MSHR entry
+while (in_flight_req->next_request != nullptr)
+in_flight_req = in_flight_req->next_request;
+
+in_flight_req->next_request =
+new SequencerRequest(pkt, request_type, curCycle());
+
+return RequestStatus_ReadyAppend;
+} else {
+m_load_waiting_on_load++;
+return RequestStatus_Aliased;
+}
 }
 }

@@ -404,8 +451,16 @@
 m_controller->unblock(address);
 }

-hitCallback(request, data, success, mach, externalHit,
-initialRequestTime, forwardRequestTime, firstResponseTime);
+// there may be multiple outstanding store requests
+// to the same cache line.
+do {
+SequencerRequest* next_request = request->next_request;
+
+hitCallback(request, data, scsuccess, mach, externalHit,
+initialRequestTime, forwardRequestTime,  
firstResponseTime);

+
+request = next_request;
+} while (request != nullptr);
 }

 void
@@ -428,8 +483,16 @@
 assert((request->m_type == RubyRequestType_LD) ||
(request->m_type == RubyRequestType_IFETCH));

-hitCallback(request, data, true, mach, externalHit,
-initialRequestTime, forwardRequestTime, firstResponseTime);
+// there may be multiple outstanding load requests
+// to the same cache line.
+do {
+SequencerRequest* next_request = request->next_request;
+
+hitCallback(request, data, true, mach, externalHit,
+initialRequestTime, forwardRequestTime,  
firstResponseTime);

+
+request = next_request;
+} while (request != nullptr);
 }

 void
@@ -607,6 +670,11 @@
 }

 RequestStatus status = insertRequest(pkt, primary_type);
+
+// check if outstanding request was appended
+if (status == RequestStatus_ReadyAppend)
+return RequestStatus_Issued;
+
 if (status != RequestStatus_Ready)
 return status;

diff --git a/src/mem/ruby/system/Sequencer.hh  
b/src/mem/ruby/system/Sequencer.hh

index 33fd530..2f1d901f 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2019 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
  * All rights reserved.
  *
@@ -45,10 +57,12 @@
 PacketPtr pkt;
 RubyRequestType m_type;
 Cycles issue_time;
+SequencerRequest* next_request;

 SequencerRequest(PacketPtr _pkt, RubyRequestType _m_type,
  Cycles _issue_time)
-: pkt(_pkt), m_type(_m_type), issue_time(_issue_time)
+: pkt(_pkt), m_type(_m_type), issue_time(_issue_time),
+  next_request(nullptr)
 {}
 };


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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I270c2151709a5e3ce334d73594ad57654c5a0dd2
Gerrit-Change-Number: 21161
Gerrit-PatchSet: 1
Gerrit-Owner: Timothy Hayes 
Gerrit-MessageType: newchange
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