[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Move RO values from ISA::read to the reset field
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/70558?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: arch-arm: Move RO values from ISA::read to the reset field
..
arch-arm: Move RO values from ISA::read to the reset field
This is simplyfying the ISA::readMiscReg, and it is stopping
us from recomputing values that won't change throughout the
simulation
Change-Id: I62270cdb59f39b8a143e9554c8beaa8cd15824aa
Signed-off-by: Giacomo Travaglini
Reviewed-by: Richard Cooper
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70558
Tested-by: kokoro
Maintainer: Jason Lowe-Power
---
M src/arch/arm/isa.cc
M src/arch/arm/regs/misc.cc
2 files changed, 49 insertions(+), 66 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Richard Cooper: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index f55235d..14349b1 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -486,35 +486,6 @@
warn_once("The ccsidr register isn't implemented and "
"always reads as 0.\n");
break;
- case MISCREG_CTR: // AArch32, ARMv7, top bit set
- case MISCREG_CTR_EL0: // AArch64
-{
-//all caches have the same line size in gem5
-//4 byte words in ARM
-unsigned lineSizeWords =
-tc->getSystemPtr()->cacheLineSize() / 4;
-unsigned log2LineSizeWords = 0;
-
-while (lineSizeWords >>= 1) {
-++log2LineSizeWords;
-}
-
-CTR ctr = 0;
-//log2 of minimun i-cache line size (words)
-ctr.iCacheLineSize = log2LineSizeWords;
-//b11 - gem5 uses pipt
-ctr.l1IndexPolicy = 0x3;
-//log2 of minimum d-cache line size (words)
-ctr.dCacheLineSize = log2LineSizeWords;
-//log2 of max reservation size (words)
-ctr.erg = log2LineSizeWords;
-//log2 of max writeback size (words)
-ctr.cwg = log2LineSizeWords;
-//b100 - gem5 format is ARMv7
-ctr.format = 0x4;
-
-return ctr;
-}
case MISCREG_ACTLR:
warn("Not doing anything for miscreg ACTLR\n");
break;
@@ -615,11 +586,6 @@
l2ctlr.numCPUs = tc->getSystemPtr()->threads.size() - 1;
return l2ctlr;
}
- case MISCREG_DBGDIDR:
-/* For now just implement the version number.
- * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
- */
-return 0x5 << 16;
case MISCREG_DBGDSCRint:
return readMiscRegNoEffect(MISCREG_DBGDSCRint);
case MISCREG_ISR:
@@ -632,8 +598,6 @@
readMiscRegNoEffect(MISCREG_CPSR),
readMiscRegNoEffect(MISCREG_SCR_EL3));
}
- case MISCREG_DCZID_EL0:
-return 0x04; // DC ZVA clear 64-byte chunks
case MISCREG_HCPTR:
{
RegVal val = readMiscRegNoEffect(idx);
@@ -656,36 +620,6 @@
case MISCREG_HIFAR: // alias for secure IFAR
return readMiscRegNoEffect(MISCREG_IFAR_S);
- case MISCREG_ID_PFR0:
-// !ThumbEE | !Jazelle | Thumb | ARM
-return 0x0031;
- case MISCREG_ID_PFR1:
-{ // Timer | Virti | !M Profile | TrustZone | ARMv4
-bool have_timer = (system->getGenericTimer() != nullptr);
-return 0x0001 |
-(release->has(ArmExtension::SECURITY) ?
-0x0010 : 0x0) |
-(release->has(ArmExtension::VIRTUALIZATION) ?
-0x1000 : 0x0) |
-(have_timer ? 0x0001 : 0x0);
-}
- case MISCREG_ID_AA64PFR0_EL1:
-return 0x0002 | // AArch{64,32} supported at EL0
- 0x0020 | // EL1
- (release->has(ArmExtension::VIRTUALIZATION) ?
-0x0200 : 0) | // EL2
- (release->has(ArmExtension::SECURITY) ?
-0x2000 : 0) | // EL3
- (release->has(ArmExtension::FEAT_SVE) ?
-0x0001 : 0) | // SVE
- (release->has(ArmExtension::FEAT_SEL2) ?
-0x0010 : 0) | // SecEL2
- (gicv3CpuInterface ? 0x0100 : 0);
- case MISCREG_ID_AA64PFR1_EL1:
-return 0x0 |
- (release->has(ArmExtension::FEAT_SME) ?
-0x1 << 24 : 0); // SME
-
// Generic Timer registers
case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
diff --git a/src/arch/arm/regs/misc.cc
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Move RO values from ISA::read to the reset field
Attention is currently required from: Richard Cooper.
Hello Richard Cooper,
I'd like you to do a code review.
Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/70558?usp=email
to review the following change.
Change subject: arch-arm: Move RO values from ISA::read to the reset field
..
arch-arm: Move RO values from ISA::read to the reset field
This is simplyfying the ISA::readMiscReg, and it is stopping
us from recomputing values that won't change throughout the
simulation
Change-Id: I62270cdb59f39b8a143e9554c8beaa8cd15824aa
Signed-off-by: Giacomo Travaglini
Reviewed-by: Richard Cooper
---
M src/arch/arm/isa.cc
M src/arch/arm/regs/misc.cc
2 files changed, 49 insertions(+), 66 deletions(-)
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index f55235d..14349b1 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -486,35 +486,6 @@
warn_once("The ccsidr register isn't implemented and "
"always reads as 0.\n");
break;
- case MISCREG_CTR: // AArch32, ARMv7, top bit set
- case MISCREG_CTR_EL0: // AArch64
-{
-//all caches have the same line size in gem5
-//4 byte words in ARM
-unsigned lineSizeWords =
-tc->getSystemPtr()->cacheLineSize() / 4;
-unsigned log2LineSizeWords = 0;
-
-while (lineSizeWords >>= 1) {
-++log2LineSizeWords;
-}
-
-CTR ctr = 0;
-//log2 of minimun i-cache line size (words)
-ctr.iCacheLineSize = log2LineSizeWords;
-//b11 - gem5 uses pipt
-ctr.l1IndexPolicy = 0x3;
-//log2 of minimum d-cache line size (words)
-ctr.dCacheLineSize = log2LineSizeWords;
-//log2 of max reservation size (words)
-ctr.erg = log2LineSizeWords;
-//log2 of max writeback size (words)
-ctr.cwg = log2LineSizeWords;
-//b100 - gem5 format is ARMv7
-ctr.format = 0x4;
-
-return ctr;
-}
case MISCREG_ACTLR:
warn("Not doing anything for miscreg ACTLR\n");
break;
@@ -615,11 +586,6 @@
l2ctlr.numCPUs = tc->getSystemPtr()->threads.size() - 1;
return l2ctlr;
}
- case MISCREG_DBGDIDR:
-/* For now just implement the version number.
- * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
- */
-return 0x5 << 16;
case MISCREG_DBGDSCRint:
return readMiscRegNoEffect(MISCREG_DBGDSCRint);
case MISCREG_ISR:
@@ -632,8 +598,6 @@
readMiscRegNoEffect(MISCREG_CPSR),
readMiscRegNoEffect(MISCREG_SCR_EL3));
}
- case MISCREG_DCZID_EL0:
-return 0x04; // DC ZVA clear 64-byte chunks
case MISCREG_HCPTR:
{
RegVal val = readMiscRegNoEffect(idx);
@@ -656,36 +620,6 @@
case MISCREG_HIFAR: // alias for secure IFAR
return readMiscRegNoEffect(MISCREG_IFAR_S);
- case MISCREG_ID_PFR0:
-// !ThumbEE | !Jazelle | Thumb | ARM
-return 0x0031;
- case MISCREG_ID_PFR1:
-{ // Timer | Virti | !M Profile | TrustZone | ARMv4
-bool have_timer = (system->getGenericTimer() != nullptr);
-return 0x0001 |
-(release->has(ArmExtension::SECURITY) ?
-0x0010 : 0x0) |
-(release->has(ArmExtension::VIRTUALIZATION) ?
-0x1000 : 0x0) |
-(have_timer ? 0x0001 : 0x0);
-}
- case MISCREG_ID_AA64PFR0_EL1:
-return 0x0002 | // AArch{64,32} supported at EL0
- 0x0020 | // EL1
- (release->has(ArmExtension::VIRTUALIZATION) ?
-0x0200 : 0) | // EL2
- (release->has(ArmExtension::SECURITY) ?
-0x2000 : 0) | // EL3
- (release->has(ArmExtension::FEAT_SVE) ?
-0x0001 : 0) | // SVE
- (release->has(ArmExtension::FEAT_SEL2) ?
-0x0010 : 0) | // SecEL2
- (gicv3CpuInterface ? 0x0100 : 0);
- case MISCREG_ID_AA64PFR1_EL1:
-return 0x0 |
- (release->has(ArmExtension::FEAT_SME) ?
-0x1 << 24 : 0); // SME
-
// Generic Timer registers
case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 7a06da1..960c2be 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -2273,6 +2273,10 @@
// AArch32 CP14 registers
InitReg(MISCREG_DBGDIDR)
+ /* For now just implement the version number.
+ * ARMv7, v7.1 Debug
