[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm, cpu, configs: Add new Op Classes for Matrix Multiply insts

2023-05-25 Thread Bobby Bruce (Gerrit) via gem5-dev 
Bobby Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70734?usp=email )


 (

7 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.
 )Change subject: arch-arm, cpu, configs: Add new Op Classes for Matrix  
Multiply insts

..

arch-arm, cpu, configs: Add new Op Classes for Matrix Multiply insts

Add SimdMatMultAcc and SimdFloatMatMultAcc Op Classes for the SVE
Matrix Multiply Accumulate instructions in the SVE F32MM, F64MM and
I8MM extensions.

Initial latencies have been set to be the same as SimdMultAcc and
SimdFloatMultAcc respectively.

Change-Id: Ifab63a0efbb0ccfbd272245e0b0b055279f66e3a
Reviewed-by: Richard Cooper 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70734
Maintainer: Andreas Sandberg 
Reviewed-by: Andreas Sandberg 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
Reviewed-by: Giacomo Travaglini 
---
M configs/common/cores/arm/HPI.py
M configs/common/cores/arm/O3_ARM_v7a.py
M configs/common/cores/arm/ex5_LITTLE.py
M configs/common/cores/arm/ex5_big.py
M src/arch/arm/isa/insts/sve.isa
M src/cpu/FuncUnit.py
M src/cpu/minor/BaseMinorCPU.py
M src/cpu/o3/FuncUnitConfig.py
M src/cpu/op_class.hh
9 files changed, 23 insertions(+), 7 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/configs/common/cores/arm/HPI.py  
b/configs/common/cores/arm/HPI.py

index c7a8127..d3d4605 100644
--- a/configs/common/cores/arm/HPI.py
+++ b/configs/common/cores/arm/HPI.py
@@ -1420,6 +1420,7 @@
 "SimdMisc",
 "SimdMult",
 "SimdMultAcc",
+"SimdMatMultAcc",
 "SimdShift",
 "SimdShiftAcc",
 "SimdSqrt",
@@ -1431,6 +1432,7 @@
 "SimdFloatMisc",
 "SimdFloatMult",
 "SimdFloatMultAcc",
+"SimdFloatMatMultAcc",
 "SimdFloatSqrt",
 ]
 )
diff --git a/configs/common/cores/arm/O3_ARM_v7a.py  
b/configs/common/cores/arm/O3_ARM_v7a.py

index 77dc4e4..6a17342 100644
--- a/configs/common/cores/arm/O3_ARM_v7a.py
+++ b/configs/common/cores/arm/O3_ARM_v7a.py
@@ -53,6 +53,7 @@
 OpDesc(opClass="SimdMisc", opLat=3),
 OpDesc(opClass="SimdMult", opLat=5),
 OpDesc(opClass="SimdMultAcc", opLat=5),
+OpDesc(opClass="SimdMatMultAcc", opLat=5),
 OpDesc(opClass="SimdShift", opLat=3),
 OpDesc(opClass="SimdShiftAcc", opLat=3),
 OpDesc(opClass="SimdSqrt", opLat=9),
@@ -64,6 +65,7 @@
 OpDesc(opClass="SimdFloatMisc", opLat=3),
 OpDesc(opClass="SimdFloatMult", opLat=3),
 OpDesc(opClass="SimdFloatMultAcc", opLat=5),
+OpDesc(opClass="SimdFloatMatMultAcc", opLat=5),
 OpDesc(opClass="SimdFloatSqrt", opLat=9),
 OpDesc(opClass="FloatAdd", opLat=5),
 OpDesc(opClass="FloatCmp", opLat=5),
diff --git a/configs/common/cores/arm/ex5_LITTLE.py  
b/configs/common/cores/arm/ex5_LITTLE.py

index 6974837..982792d 100644
--- a/configs/common/cores/arm/ex5_LITTLE.py
+++ b/configs/common/cores/arm/ex5_LITTLE.py
@@ -56,6 +56,7 @@
 OpDesc(opClass="SimdMisc", opLat=3),
 OpDesc(opClass="SimdMult", opLat=4),
 OpDesc(opClass="SimdMultAcc", opLat=5),
+OpDesc(opClass="SimdMatMultAcc", opLat=5),
 OpDesc(opClass="SimdShift", opLat=3),
 OpDesc(opClass="SimdShiftAcc", opLat=3),
 OpDesc(opClass="SimdSqrt", opLat=9),
@@ -67,6 +68,7 @@
 OpDesc(opClass="SimdFloatMisc", opLat=6),
 OpDesc(opClass="SimdFloatMult", opLat=15),
 OpDesc(opClass="SimdFloatMultAcc", opLat=6),
+OpDesc(opClass="SimdFloatMatMultAcc", opLat=6),
 OpDesc(opClass="SimdFloatSqrt", opLat=17),
 OpDesc(opClass="FloatAdd", opLat=8),
 OpDesc(opClass="FloatCmp", opLat=6),
diff --git a/configs/common/cores/arm/ex5_big.py  
b/configs/common/cores/arm/ex5_big.py

index 70af6b8..0d4d490 100644
--- a/configs/common/cores/arm/ex5_big.py
+++ b/configs/common/cores/arm/ex5_big.py
@@ -58,6 +58,7 @@
 OpDesc(opClass="SimdMisc", opLat=3),
 OpDesc(opClass="SimdMult", opLat=6),
 OpDesc(opClass="SimdMultAcc", opLat=5),
+OpDesc(opClass="SimdMatMultAcc", opLat=5),
 OpDesc(opClass="SimdShift", opLat=3),
 OpDesc(opClass="SimdShiftAcc", opLat=3),
 OpDesc(opClass="SimdSqrt", opLat=9),
@@ -69,6 +70,7 @@
 OpDesc(opClass="SimdFloatMisc", opLat=3),
 OpDesc(opClass="SimdFloatMult", opLat=6),
 OpDesc(opClass="SimdFloatMultAcc", opLat=1),
+OpDesc(opClass="SimdFloatMatMultAcc", opLat=1),
 OpDesc(opClass="SimdFloatSqrt", opLat=9),
 OpDesc(opClass="FloatAdd", opLat=6),
 OpDesc(opClass="FloatCmp", opLat=5),
diff --git

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm, cpu, configs: Add new Op Classes for Matrix Multiply insts

2023-05-17 Thread Giacomo Travaglini (Gerrit) via gem5-dev 

Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70734?usp=email

to review the following change.


Change subject: arch-arm, cpu, configs: Add new Op Classes for Matrix  
Multiply insts

..

arch-arm, cpu, configs: Add new Op Classes for Matrix Multiply insts

Add SimdMatMultAcc and SimdFloatMatMultAcc Op Classes for the SVE
Matrix Multiply Accumulate instructions in the SVE F32MM, F64MM and
I8MM extensions.

Initial latencies have been set to be the same as SimdMultAcc and
SimdFloatMultAcc respectively.

Change-Id: Ifab63a0efbb0ccfbd272245e0b0b055279f66e3a
Reviewed-by: Richard Cooper 
---
M configs/common/cores/arm/HPI.py
M configs/common/cores/arm/O3_ARM_v7a.py
M configs/common/cores/arm/ex5_LITTLE.py
M configs/common/cores/arm/ex5_big.py
M src/arch/arm/isa/insts/sve.isa
M src/cpu/FuncUnit.py
M src/cpu/minor/BaseMinorCPU.py
M src/cpu/o3/FuncUnitConfig.py
M src/cpu/op_class.hh
9 files changed, 23 insertions(+), 7 deletions(-)



diff --git a/configs/common/cores/arm/HPI.py  
b/configs/common/cores/arm/HPI.py

index c7a8127..d3d4605 100644
--- a/configs/common/cores/arm/HPI.py
+++ b/configs/common/cores/arm/HPI.py
@@ -1420,6 +1420,7 @@
 "SimdMisc",
 "SimdMult",
 "SimdMultAcc",
+"SimdMatMultAcc",
 "SimdShift",
 "SimdShiftAcc",
 "SimdSqrt",
@@ -1431,6 +1432,7 @@
 "SimdFloatMisc",
 "SimdFloatMult",
 "SimdFloatMultAcc",
+"SimdFloatMatMultAcc",
 "SimdFloatSqrt",
 ]
 )
diff --git a/configs/common/cores/arm/O3_ARM_v7a.py  
b/configs/common/cores/arm/O3_ARM_v7a.py

index 77dc4e4..be9abd6 100644
--- a/configs/common/cores/arm/O3_ARM_v7a.py
+++ b/configs/common/cores/arm/O3_ARM_v7a.py
@@ -53,6 +53,7 @@
 OpDesc(opClass="SimdMisc", opLat=3),
 OpDesc(opClass="SimdMult", opLat=5),
 OpDesc(opClass="SimdMultAcc", opLat=5),
+OpDesc(opClass='SimdMatMultAcc',opLat=5),
 OpDesc(opClass="SimdShift", opLat=3),
 OpDesc(opClass="SimdShiftAcc", opLat=3),
 OpDesc(opClass="SimdSqrt", opLat=9),
@@ -64,6 +65,7 @@
 OpDesc(opClass="SimdFloatMisc", opLat=3),
 OpDesc(opClass="SimdFloatMult", opLat=3),
 OpDesc(opClass="SimdFloatMultAcc", opLat=5),
+OpDesc(opClass='SimdFloatMatMultAcc',opLat=5),
 OpDesc(opClass="SimdFloatSqrt", opLat=9),
 OpDesc(opClass="FloatAdd", opLat=5),
 OpDesc(opClass="FloatCmp", opLat=5),
diff --git a/configs/common/cores/arm/ex5_LITTLE.py  
b/configs/common/cores/arm/ex5_LITTLE.py

index 6974837..b6fed94 100644
--- a/configs/common/cores/arm/ex5_LITTLE.py
+++ b/configs/common/cores/arm/ex5_LITTLE.py
@@ -56,6 +56,7 @@
 OpDesc(opClass="SimdMisc", opLat=3),
 OpDesc(opClass="SimdMult", opLat=4),
 OpDesc(opClass="SimdMultAcc", opLat=5),
+OpDesc(opClass='SimdMatMultAcc',opLat=5),
 OpDesc(opClass="SimdShift", opLat=3),
 OpDesc(opClass="SimdShiftAcc", opLat=3),
 OpDesc(opClass="SimdSqrt", opLat=9),
@@ -67,6 +68,7 @@
 OpDesc(opClass="SimdFloatMisc", opLat=6),
 OpDesc(opClass="SimdFloatMult", opLat=15),
 OpDesc(opClass="SimdFloatMultAcc", opLat=6),
+OpDesc(opClass='SimdFloatMatMultAcc',opLat=6),
 OpDesc(opClass="SimdFloatSqrt", opLat=17),
 OpDesc(opClass="FloatAdd", opLat=8),
 OpDesc(opClass="FloatCmp", opLat=6),
diff --git a/configs/common/cores/arm/ex5_big.py  
b/configs/common/cores/arm/ex5_big.py

index 70af6b8..4383f96 100644
--- a/configs/common/cores/arm/ex5_big.py
+++ b/configs/common/cores/arm/ex5_big.py
@@ -58,6 +58,7 @@
 OpDesc(opClass="SimdMisc", opLat=3),
 OpDesc(opClass="SimdMult", opLat=6),
 OpDesc(opClass="SimdMultAcc", opLat=5),
+OpDesc(opClass='SimdMatMultAcc',opLat=5),
 OpDesc(opClass="SimdShift", opLat=3),
 OpDesc(opClass="SimdShiftAcc", opLat=3),
 OpDesc(opClass="SimdSqrt", opLat=9),
@@ -69,6 +70,7 @@
 OpDesc(opClass="SimdFloatMisc", opLat=3),
 OpDesc(opClass="SimdFloatMult", opLat=6),
 OpDesc(opClass="SimdFloatMultAcc", opLat=1),
+OpDesc(opClass='SimdFloatMatMultAcc',opLat=1),
 OpDesc(opClass="SimdFloatSqrt", opLat=9),
 OpDesc(opClass="FloatAdd", opLat=6),
 OpDesc(opClass="FloatCmp", opLat=5),
diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa
index b6b560d..0993c47 100644
--- a/src/arch/arm/isa/insts/sve.isa
+++ b/src/arch/arm/isa/insts/sve.isa
@@ -3929,7 +3929,7 @@
 fplibMul(srcElemA, srcElemB, fpscr), fpscr);
 '''
 # FMMLA (vectors)
-sveMatMulInst('fmmla', 'Fmmla', 'SimdFloatMultAccOp', floatTypes,
+sveMatMulInst('fmmla', 'Fmmla', 'SimdFloatMatMultAccOp',