[gem5-dev] Change in gem5/gem5[develop]: mem: Adding PortTerminator
Mahyar Samani has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/51609 )
Change subject: mem: Adding PortTerminator
..
mem: Adding PortTerminator
This change adds the source code for the PortTerminator SimObject.
It could be used to connect request/response ports in the system
that can not be connected to any other ports. This will prevent
errors caused by orphan ports in the system.
Change-Id: I5e19cdd3ce064638ffabf29d29225eda77ffc146
---
A src/mem/PortTerminator.py
A src/mem/port_terminator.cc
A src/mem/port_terminator.hh
M src/mem/SConscript
4 files changed, 240 insertions(+), 0 deletions(-)
diff --git a/src/mem/PortTerminator.py b/src/mem/PortTerminator.py
new file mode 100644
index 000..d0b7169
--- /dev/null
+++ b/src/mem/PortTerminator.py
@@ -0,0 +1,53 @@
+# Copyright (c) 2012-2021 Arm Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Copyright (c) 2013 Amin Farmahini-Farahani
+# Copyright (c) 2015 University of Kaiserslautern
+# Copyright (c) 2015 The University of Bologna
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from m5.params import *
+from m5.SimObject import SimObject
+
+class PortTerminator(SimObject):
+type = 'PortTerminator'
+abstract = False
+cxx_header = "mem/port_terminator.hh"
+cxx_class = 'gem5::PortTerminator'
+
+req_ports = VectorRequestPort("Vector port for connecting terminating "
+"response ports.")
+resp_ports = VectorResponsePort("Vector port for terminating "
+"request ports.")
\ No newline at end of file
diff --git a/src/mem/SConscript b/src/mem/SConscript
index 5d3c5e6..e200982 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -58,6 +58,7 @@
SimObject('HMCController.py')
SimObject('SerialLink.py')
SimObject('MemDelay.py')
+SimObject('PortTerminator.py')
Source('abstract_mem.cc')
Source('addr_mapper.cc')
@@ -85,6 +86,7 @@
Source('htm.cc')
Source('serial_link.cc')
Source('mem_delay.cc')
+Source('port_terminator.cc')
if env['TARGET_ISA'] != 'null':
Source('translating_port_proxy.cc')
diff --git a/src/mem/port_terminator.cc b/src/mem/port_terminator.cc
new file mode 100644
index 000..cd56c53
--- /dev/null
+++ b/src/mem/port_terminator.cc
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2011-2015, 2018-2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ *
[gem5-dev] Change in gem5/gem5[develop]: mem: Adding PortTerminator
Mahyar Samani has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/51609 )
(
4 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: mem: Adding PortTerminator
..
mem: Adding PortTerminator
This change adds the source code for the PortTerminator SimObject.
It could be used to connect request/response ports in the system
that can not be connected to any other ports. This will prevent
errors caused by orphan ports in the system. As an example if
you have set up a cache hierarchy and do not want to test its
performance in full system mode and want to use PyTrafficGen
instead, your system will end up with an icache or walker ports
that are not connected to anything. In this case, you can use a
PortTerminator to connect the orphan ports in your system.
Change-Id: I5e19cdd3ce064638ffabf29d29225eda77ffc146
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51609
Tested-by: kokoro
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
---
A src/mem/PortTerminator.py
A src/mem/port_terminator.cc
A src/mem/port_terminator.hh
M src/mem/SConscript
4 files changed, 239 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/PortTerminator.py b/src/mem/PortTerminator.py
new file mode 100644
index 000..761f5ed
--- /dev/null
+++ b/src/mem/PortTerminator.py
@@ -0,0 +1,39 @@
+# Copyright (c) 2021 The Regents of the University of California.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+from m5.params import *
+from m5.SimObject import SimObject
+
+class PortTerminator(SimObject):
+type = 'PortTerminator'
+cxx_header = "mem/port_terminator.hh"
+cxx_class = 'gem5::PortTerminator'
+
+req_ports = VectorRequestPort("Vector port for connecting terminating "
+"response ports.")
+resp_ports = VectorResponsePort("Vector port for terminating "
+"request ports.")
\ No newline at end of file
diff --git a/src/mem/SConscript b/src/mem/SConscript
index 5338b79..ddf6fee 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -58,6 +58,7 @@
SimObject('HMCController.py')
SimObject('SerialLink.py')
SimObject('MemDelay.py')
+SimObject('PortTerminator.py')
Source('abstract_mem.cc')
Source('addr_mapper.cc')
@@ -85,6 +86,7 @@
Source('htm.cc')
Source('serial_link.cc')
Source('mem_delay.cc')
+Source('port_terminator.cc')
GTest('translation_gen.test', 'translation_gen.test.cc')
diff --git a/src/mem/port_terminator.cc b/src/mem/port_terminator.cc
new file mode 100644
index 000..57263b4
--- /dev/null
+++ b/src/mem/port_terminator.cc
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2021 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the na
