[gem5-dev] Change in gem5/gem5[master]: arch-arm, cpu: Add initial support for Arm SVE
Giacomo Gabrielli has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/13515 ) Change subject: arch-arm,cpu: Add initial support for Arm SVE .. arch-arm,cpu: Add initial support for Arm SVE This changeset adds initial support for the Arm Scalable Vector Extension (SVE) by implementing: - support for most data-processing instructions (no loads/stores yet); - basic system-level support. Additional authors: - Javier Setoain - Gabor Dozsa - Giacomo Travaglini Thanks to Pau Cabre for his contribution of bugfixes. Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709 Signed-off-by: Giacomo Gabrielli Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13515 Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg --- M src/arch/arm/ArmISA.py M src/arch/arm/ArmSystem.py M src/arch/arm/SConscript M src/arch/arm/decoder.cc M src/arch/arm/decoder.hh M src/arch/arm/insts/static_inst.cc M src/arch/arm/insts/static_inst.hh A src/arch/arm/insts/sve.cc A src/arch/arm/insts/sve.hh M src/arch/arm/isa.cc M src/arch/arm/isa.hh M src/arch/arm/isa/formats/aarch64.isa M src/arch/arm/isa/formats/formats.isa A src/arch/arm/isa/formats/sve_2nd_level.isa A src/arch/arm/isa/formats/sve_top_level.isa M src/arch/arm/isa/includes.isa M src/arch/arm/isa/insts/fp64.isa M src/arch/arm/isa/insts/insts.isa M src/arch/arm/isa/insts/ldr64.isa M src/arch/arm/isa/insts/mem.isa M src/arch/arm/isa/insts/neon64.isa M src/arch/arm/isa/insts/neon64_mem.isa A src/arch/arm/isa/insts/sve.isa M src/arch/arm/isa/operands.isa A src/arch/arm/isa/templates/sve.isa M src/arch/arm/isa/templates/templates.isa M src/arch/arm/miscregs.cc M src/arch/arm/miscregs.hh M src/arch/arm/miscregs_types.hh M src/arch/arm/nativetrace.cc M src/arch/arm/process.cc M src/arch/arm/registers.hh M src/arch/arm/system.cc M src/arch/arm/system.hh M src/arch/arm/types.hh M src/arch/arm/utility.cc M src/arch/arm/utility.hh M src/arch/generic/vec_reg.hh M src/cpu/FuncUnit.py M src/cpu/exetrace.cc M src/cpu/minor/MinorCPU.py M src/cpu/o3/FUPool.py M src/cpu/o3/FuncUnitConfig.py M src/cpu/op_class.hh M src/cpu/simple_thread.cc A util/cpt_upgraders/arm-sve.py 46 files changed, 11,605 insertions(+), 61 deletions(-) Approvals: Andreas Sandberg: Looks good to me, approved; Looks good to me, approved -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13515 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709 Gerrit-Change-Number: 13515 Gerrit-PatchSet: 18 Gerrit-Owner: Giacomo Gabrielli Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Anthony Gutierrez Gerrit-Reviewer: Giacomo Gabrielli Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-CC: Daniel Carvalho Gerrit-MessageType: merged ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-arm, cpu: Add initial support for Arm SVE
Giacomo Travaglini has uploaded a new patch set (#17) to the change originally created by Giacomo Gabrielli. ( https://gem5-review.googlesource.com/c/public/gem5/+/13515 ) Change subject: arch-arm,cpu: Add initial support for Arm SVE .. arch-arm,cpu: Add initial support for Arm SVE This changeset adds initial support for the Arm Scalable Vector Extension (SVE) by implementing: - support for most data-processing instructions (no loads/stores yet); - basic system-level support. Additional authors: - Javier Setoain - Gabor Dozsa - Giacomo Travaglini Thanks to Pau Cabre for his contribution of bugfixes. Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709 Signed-off-by: Giacomo Gabrielli --- M src/arch/arm/ArmISA.py M src/arch/arm/ArmSystem.py M src/arch/arm/SConscript M src/arch/arm/decoder.cc M src/arch/arm/decoder.hh M src/arch/arm/insts/static_inst.cc M src/arch/arm/insts/static_inst.hh A src/arch/arm/insts/sve.cc A src/arch/arm/insts/sve.hh M src/arch/arm/isa.cc M src/arch/arm/isa.hh M src/arch/arm/isa/formats/aarch64.isa M src/arch/arm/isa/formats/formats.isa A src/arch/arm/isa/formats/sve_2nd_level.isa A src/arch/arm/isa/formats/sve_top_level.isa M src/arch/arm/isa/includes.isa M src/arch/arm/isa/insts/fp64.isa M src/arch/arm/isa/insts/insts.isa M src/arch/arm/isa/insts/ldr64.isa M src/arch/arm/isa/insts/mem.isa M src/arch/arm/isa/insts/neon64.isa M src/arch/arm/isa/insts/neon64_mem.isa A src/arch/arm/isa/insts/sve.isa M src/arch/arm/isa/operands.isa A src/arch/arm/isa/templates/sve.isa M src/arch/arm/isa/templates/templates.isa M src/arch/arm/miscregs.cc M src/arch/arm/miscregs.hh M src/arch/arm/miscregs_types.hh M src/arch/arm/nativetrace.cc M src/arch/arm/process.cc M src/arch/arm/registers.hh M src/arch/arm/system.cc M src/arch/arm/system.hh M src/arch/arm/types.hh M src/arch/arm/utility.cc M src/arch/arm/utility.hh M src/arch/generic/vec_reg.hh M src/cpu/FuncUnit.py M src/cpu/exetrace.cc M src/cpu/minor/MinorCPU.py M src/cpu/o3/FUPool.py M src/cpu/o3/FuncUnitConfig.py M src/cpu/op_class.hh M src/cpu/simple_thread.cc A util/cpt_upgraders/arm-sve.py 46 files changed, 11,605 insertions(+), 61 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13515 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709 Gerrit-Change-Number: 13515 Gerrit-PatchSet: 17 Gerrit-Owner: Giacomo Gabrielli Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Anthony Gutierrez Gerrit-Reviewer: Giacomo Gabrielli Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-CC: Daniel Carvalho Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-arm, cpu: Add initial support for Arm SVE
Hello Jason Lowe-Power, Giacomo Travaglini, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/13515 to look at the new patch set (#15). Change subject: arch-arm,cpu: Add initial support for Arm SVE .. arch-arm,cpu: Add initial support for Arm SVE This changeset adds initial support for the Arm Scalable Vector Extension (SVE) by implementing: - support for most data-processing instructions (no loads/stores yet); - basic system-level support. Additional authors: - Javier Setoain - Gabor Dozsa - Giacomo Travaglini Thanks to Pau Cabre for his contribution of bugfixes. Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709 Signed-off-by: Giacomo Gabrielli --- M src/arch/arm/ArmISA.py M src/arch/arm/ArmSystem.py M src/arch/arm/SConscript M src/arch/arm/decoder.cc M src/arch/arm/decoder.hh M src/arch/arm/insts/static_inst.cc M src/arch/arm/insts/static_inst.hh A src/arch/arm/insts/sve.cc A src/arch/arm/insts/sve.hh M src/arch/arm/isa.cc M src/arch/arm/isa.hh M src/arch/arm/isa/formats/aarch64.isa M src/arch/arm/isa/formats/formats.isa A src/arch/arm/isa/formats/sve_2nd_level.isa A src/arch/arm/isa/formats/sve_top_level.isa M src/arch/arm/isa/includes.isa M src/arch/arm/isa/insts/fp64.isa M src/arch/arm/isa/insts/insts.isa M src/arch/arm/isa/insts/ldr64.isa M src/arch/arm/isa/insts/mem.isa M src/arch/arm/isa/insts/neon64.isa M src/arch/arm/isa/insts/neon64_mem.isa A src/arch/arm/isa/insts/sve.isa M src/arch/arm/isa/operands.isa A src/arch/arm/isa/templates/sve.isa M src/arch/arm/isa/templates/templates.isa M src/arch/arm/miscregs.cc M src/arch/arm/miscregs.hh M src/arch/arm/miscregs_types.hh M src/arch/arm/nativetrace.cc M src/arch/arm/process.cc M src/arch/arm/registers.hh M src/arch/arm/system.cc M src/arch/arm/system.hh M src/arch/arm/types.hh M src/arch/arm/utility.cc M src/arch/arm/utility.hh M src/arch/generic/vec_reg.hh M src/cpu/FuncUnit.py M src/cpu/exetrace.cc M src/cpu/minor/MinorCPU.py M src/cpu/o3/FUPool.py M src/cpu/o3/FuncUnitConfig.py M src/cpu/op_class.hh M src/cpu/simple_thread.cc 45 files changed, 11,568 insertions(+), 61 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13515 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709 Gerrit-Change-Number: 13515 Gerrit-PatchSet: 15 Gerrit-Owner: Giacomo Gabrielli Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Gabrielli Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-arm, cpu: Add initial support for Arm SVE
Giacomo Travaglini has uploaded a new patch set (#13) to the change originally created by Giacomo Gabrielli. ( https://gem5-review.googlesource.com/c/public/gem5/+/13515 ) Change subject: arch-arm,cpu: Add initial support for Arm SVE .. arch-arm,cpu: Add initial support for Arm SVE This changeset adds initial support for the Arm Scalable Vector Extension (SVE) by implementing: - support for most data-processing instructions (no loads/stores yet); - basic system-level support. Additional authors: - Javier Setoain - Gabor Dozsa - Giacomo Travaglini Thanks to Pau Cabre for his contribution of bugfixes. Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709 Signed-off-by: Giacomo Gabrielli --- M src/arch/arm/ArmISA.py M src/arch/arm/ArmSystem.py M src/arch/arm/SConscript M src/arch/arm/decoder.cc M src/arch/arm/decoder.hh M src/arch/arm/insts/static_inst.cc M src/arch/arm/insts/static_inst.hh A src/arch/arm/insts/sve.cc A src/arch/arm/insts/sve.hh M src/arch/arm/isa.cc M src/arch/arm/isa.hh M src/arch/arm/isa/formats/aarch64.isa M src/arch/arm/isa/formats/formats.isa A src/arch/arm/isa/formats/sve_2nd_level.isa A src/arch/arm/isa/formats/sve_top_level.isa M src/arch/arm/isa/includes.isa M src/arch/arm/isa/insts/fp64.isa M src/arch/arm/isa/insts/insts.isa M src/arch/arm/isa/insts/ldr64.isa M src/arch/arm/isa/insts/mem.isa M src/arch/arm/isa/insts/neon64.isa M src/arch/arm/isa/insts/neon64_mem.isa A src/arch/arm/isa/insts/sve.isa M src/arch/arm/isa/operands.isa A src/arch/arm/isa/templates/sve.isa M src/arch/arm/isa/templates/templates.isa M src/arch/arm/miscregs.cc M src/arch/arm/miscregs.hh M src/arch/arm/miscregs_types.hh M src/arch/arm/nativetrace.cc M src/arch/arm/process.cc M src/arch/arm/registers.hh M src/arch/arm/system.cc M src/arch/arm/system.hh M src/arch/arm/types.hh M src/arch/arm/utility.cc M src/arch/arm/utility.hh M src/arch/generic/vec_reg.hh M src/cpu/FuncUnit.py M src/cpu/exetrace.cc M src/cpu/minor/MinorCPU.py M src/cpu/o3/FUPool.py M src/cpu/o3/FuncUnitConfig.py M src/cpu/op_class.hh M src/cpu/simple_thread.cc 45 files changed, 11,191 insertions(+), 61 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13515 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709 Gerrit-Change-Number: 13515 Gerrit-PatchSet: 13 Gerrit-Owner: Giacomo Gabrielli Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Gabrielli Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-arm, cpu: Add initial support for Arm SVE
Hello Giacomo Travaglini, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/13515 to look at the new patch set (#12). Change subject: arch-arm,cpu: Add initial support for Arm SVE .. arch-arm,cpu: Add initial support for Arm SVE This changeset adds initial support for the Arm Scalable Vector Extension (SVE) by implementing: - support for most data-processing instructions (no loads/stores yet); - basic system-level support. Additional authors: - Javier Setoain - Gabor Dozsa - Giacomo Travaglini Thanks to Pau Cabre for his contribution of bugfixes. Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709 Signed-off-by: Giacomo Gabrielli --- M src/arch/arm/ArmISA.py M src/arch/arm/ArmSystem.py M src/arch/arm/SConscript M src/arch/arm/decoder.cc M src/arch/arm/decoder.hh M src/arch/arm/insts/static_inst.cc M src/arch/arm/insts/static_inst.hh A src/arch/arm/insts/sve.cc A src/arch/arm/insts/sve.hh M src/arch/arm/isa.cc M src/arch/arm/isa.hh M src/arch/arm/isa/formats/aarch64.isa M src/arch/arm/isa/formats/formats.isa A src/arch/arm/isa/formats/sve_2nd_level.isa A src/arch/arm/isa/formats/sve_top_level.isa M src/arch/arm/isa/includes.isa M src/arch/arm/isa/insts/fp64.isa M src/arch/arm/isa/insts/insts.isa M src/arch/arm/isa/insts/ldr64.isa M src/arch/arm/isa/insts/mem.isa M src/arch/arm/isa/insts/neon64.isa M src/arch/arm/isa/insts/neon64_mem.isa A src/arch/arm/isa/insts/sve.isa M src/arch/arm/isa/operands.isa A src/arch/arm/isa/templates/sve.isa M src/arch/arm/isa/templates/templates.isa M src/arch/arm/miscregs.cc M src/arch/arm/miscregs.hh M src/arch/arm/miscregs_types.hh M src/arch/arm/nativetrace.cc M src/arch/arm/process.cc M src/arch/arm/registers.hh M src/arch/arm/system.cc M src/arch/arm/system.hh M src/arch/arm/types.hh M src/arch/arm/utility.cc M src/arch/arm/utility.hh M src/arch/generic/vec_reg.hh M src/cpu/FuncUnit.py M src/cpu/checker/thread_context.hh M src/cpu/exetrace.cc M src/cpu/minor/MinorCPU.py M src/cpu/o3/FUPool.py M src/cpu/o3/FuncUnitConfig.py M src/cpu/o3/thread_context.hh M src/cpu/op_class.hh M src/cpu/simple_thread.cc M src/cpu/simple_thread.hh M src/cpu/thread_context.hh 49 files changed, 11,209 insertions(+), 61 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13515 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709 Gerrit-Change-Number: 13515 Gerrit-PatchSet: 12 Gerrit-Owner: Giacomo Gabrielli Gerrit-Reviewer: Giacomo Gabrielli Gerrit-Reviewer: Giacomo Travaglini Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-arm, cpu: Add initial support for Arm SVE
Hello Giacomo Travaglini, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/13515 to look at the new patch set (#8). Change subject: arch-arm,cpu: Add initial support for Arm SVE .. arch-arm,cpu: Add initial support for Arm SVE This changeset adds initial support for the Arm Scalable Vector Extension (SVE) by implementing: - support for most data-processing instructions (no loads/stores yet); - basic system-level support. Additional authors: - Javier Setoain - Gabor Dozsa - Giacomo Travaglini Thanks to Pau Cabre for his contribution of bugfixes. Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709 Signed-off-by: Giacomo Gabrielli --- M src/arch/arm/ArmISA.py M src/arch/arm/ArmSystem.py M src/arch/arm/SConscript M src/arch/arm/decoder.cc M src/arch/arm/decoder.hh M src/arch/arm/insts/static_inst.cc M src/arch/arm/insts/static_inst.hh A src/arch/arm/insts/sve.cc A src/arch/arm/insts/sve.hh M src/arch/arm/isa.cc M src/arch/arm/isa.hh M src/arch/arm/isa/formats/aarch64.isa M src/arch/arm/isa/formats/formats.isa A src/arch/arm/isa/formats/sve_2nd_level.isa A src/arch/arm/isa/formats/sve_top_level.isa M src/arch/arm/isa/includes.isa M src/arch/arm/isa/insts/fp64.isa M src/arch/arm/isa/insts/insts.isa M src/arch/arm/isa/insts/ldr64.isa M src/arch/arm/isa/insts/mem.isa M src/arch/arm/isa/insts/neon64.isa M src/arch/arm/isa/insts/neon64_mem.isa A src/arch/arm/isa/insts/sve.isa M src/arch/arm/isa/operands.isa A src/arch/arm/isa/templates/sve.isa M src/arch/arm/isa/templates/templates.isa M src/arch/arm/miscregs.cc M src/arch/arm/miscregs.hh M src/arch/arm/miscregs_types.hh M src/arch/arm/nativetrace.cc M src/arch/arm/process.cc M src/arch/arm/registers.hh M src/arch/arm/system.cc M src/arch/arm/system.hh M src/arch/arm/types.hh M src/arch/arm/utility.cc M src/arch/arm/utility.hh M src/arch/generic/vec_reg.hh M src/cpu/FuncUnit.py M src/cpu/checker/thread_context.hh M src/cpu/exetrace.cc M src/cpu/minor/MinorCPU.py M src/cpu/o3/FUPool.py M src/cpu/o3/FuncUnitConfig.py M src/cpu/o3/thread_context.hh M src/cpu/op_class.hh M src/cpu/simple_thread.cc M src/cpu/simple_thread.hh M src/cpu/thread_context.hh 49 files changed, 11,205 insertions(+), 58 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13515 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709 Gerrit-Change-Number: 13515 Gerrit-PatchSet: 8 Gerrit-Owner: Giacomo Gabrielli Gerrit-Reviewer: Giacomo Travaglini Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-arm, cpu: Add initial support for Arm SVE
Hello Giacomo Travaglini, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/13515 to look at the new patch set (#5). Change subject: arch-arm,cpu: Add initial support for Arm SVE .. arch-arm,cpu: Add initial support for Arm SVE This changeset adds initial support for the Arm Scalable Vector Extension (SVE) by implementing: - support for most data-processing instructions (no loads/stores yet); - basic system-level support. Additional authors: - Javier Setoain - Gabor Dozsa - Giacomo Travaglini Thanks to Pau Cabre for his contribution of bugfixes. Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709 Signed-off-by: Giacomo Gabrielli --- M src/arch/arm/ArmISA.py M src/arch/arm/ArmSystem.py M src/arch/arm/SConscript M src/arch/arm/decoder.cc M src/arch/arm/decoder.hh M src/arch/arm/insts/static_inst.cc M src/arch/arm/insts/static_inst.hh A src/arch/arm/insts/sve.cc A src/arch/arm/insts/sve.hh M src/arch/arm/isa.cc M src/arch/arm/isa.hh M src/arch/arm/isa/formats/aarch64.isa M src/arch/arm/isa/formats/formats.isa A src/arch/arm/isa/formats/sve_2nd_level.isa A src/arch/arm/isa/formats/sve_top_level.isa M src/arch/arm/isa/includes.isa M src/arch/arm/isa/insts/fp64.isa M src/arch/arm/isa/insts/insts.isa M src/arch/arm/isa/insts/ldr64.isa M src/arch/arm/isa/insts/mem.isa M src/arch/arm/isa/insts/neon64.isa M src/arch/arm/isa/insts/neon64_mem.isa A src/arch/arm/isa/insts/sve.isa M src/arch/arm/isa/operands.isa A src/arch/arm/isa/templates/sve.isa M src/arch/arm/isa/templates/templates.isa M src/arch/arm/miscregs.cc M src/arch/arm/miscregs.hh M src/arch/arm/miscregs_types.hh M src/arch/arm/nativetrace.cc M src/arch/arm/process.cc M src/arch/arm/registers.hh M src/arch/arm/system.cc M src/arch/arm/system.hh M src/arch/arm/types.hh M src/arch/arm/utility.cc M src/arch/arm/utility.hh M src/arch/generic/vec_reg.hh M src/cpu/FuncUnit.py M src/cpu/checker/thread_context.hh M src/cpu/exetrace.cc M src/cpu/minor/MinorCPU.py M src/cpu/o3/FUPool.py M src/cpu/o3/FuncUnitConfig.py M src/cpu/o3/thread_context.hh M src/cpu/op_class.hh M src/cpu/simple_thread.cc M src/cpu/simple_thread.hh M src/cpu/thread_context.hh 49 files changed, 11,193 insertions(+), 59 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13515 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709 Gerrit-Change-Number: 13515 Gerrit-PatchSet: 5 Gerrit-Owner: Giacomo Gabrielli Gerrit-Reviewer: Giacomo Travaglini Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
