[gem5-dev] changeset in gem5: mem: adding architectural page table support ...
changeset bec0c5ffc323 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=bec0c5ffc323
description:
mem: adding architectural page table support for SE mode
This patch enables the use of page tables that are stored in system
memory
and respect x86 specification, in SE mode. It defines an architectural
page table for x86 as a MultiLevelPageTable class and puts a placeholder
class for other ISAs page tables, giving the possibility for future
implementation.
diffstat:
src/arch/alpha/process.hh| 3 +
src/arch/arm/process.hh | 3 +
src/arch/mips/process.hh | 3 +
src/arch/power/process.hh| 3 +
src/arch/sparc/process.hh| 3 +
src/arch/x86/pagetable.hh| 85
src/arch/x86/pagetable_walker.cc | 17
src/arch/x86/process.hh | 9
src/arch/x86/system.hh | 14 ++
src/mem/SConscript | 2 +
src/sim/Process.py | 2 +
src/sim/process.cc | 5 +-
src/sim/process.hh | 2 +
13 files changed, 133 insertions(+), 18 deletions(-)
diffs (truncated from 305 to 300 lines):
diff -r 77af86f37337 -r bec0c5ffc323 src/arch/alpha/process.hh
--- a/src/arch/alpha/process.hh Tue Apr 01 12:18:12 2014 -0500
+++ b/src/arch/alpha/process.hh Thu Aug 28 10:11:44 2014 -0500
@@ -55,4 +55,7 @@
void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value);
};
+/* No architectural page table defined for this ISA */
+typedef NoArchPageTable ArchPageTable;
+
#endif // __ARCH_ALPHA_PROCESS_HH__
diff -r 77af86f37337 -r bec0c5ffc323 src/arch/arm/process.hh
--- a/src/arch/arm/process.hh Tue Apr 01 12:18:12 2014 -0500
+++ b/src/arch/arm/process.hh Thu Aug 28 10:11:44 2014 -0500
@@ -98,5 +98,8 @@
void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value);
};
+/* No architectural page table defined for this ISA */
+typedef NoArchPageTable ArchPageTable;
+
#endif // __ARM_PROCESS_HH__
diff -r 77af86f37337 -r bec0c5ffc323 src/arch/mips/process.hh
--- a/src/arch/mips/process.hh Tue Apr 01 12:18:12 2014 -0500
+++ b/src/arch/mips/process.hh Thu Aug 28 10:11:44 2014 -0500
@@ -59,5 +59,8 @@
void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value);
};
+/* No architectural page table defined for this ISA */
+typedef NoArchPageTable ArchPageTable;
+
#endif // __MIPS_PROCESS_HH__
diff -r 77af86f37337 -r bec0c5ffc323 src/arch/power/process.hh
--- a/src/arch/power/process.hh Tue Apr 01 12:18:12 2014 -0500
+++ b/src/arch/power/process.hh Thu Aug 28 10:11:44 2014 -0500
@@ -58,5 +58,8 @@
void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value);
};
+/* No architectural page table defined for this ISA */
+typedef NoArchPageTable ArchPageTable;
+
#endif // __POWER_PROCESS_HH__
diff -r 77af86f37337 -r bec0c5ffc323 src/arch/sparc/process.hh
--- a/src/arch/sparc/process.hh Tue Apr 01 12:18:12 2014 -0500
+++ b/src/arch/sparc/process.hh Thu Aug 28 10:11:44 2014 -0500
@@ -131,4 +131,7 @@
void setSyscallArg(ThreadContext *tc, int i, SparcISA::IntReg val);
};
+/* No architectural page table defined for this ISA */
+typedef NoArchPageTable ArchPageTable;
+
#endif // __SPARC_PROCESS_HH__
diff -r 77af86f37337 -r bec0c5ffc323 src/arch/x86/pagetable.hh
--- a/src/arch/x86/pagetable.hh Tue Apr 01 12:18:12 2014 -0500
+++ b/src/arch/x86/pagetable.hh Thu Aug 28 10:11:44 2014 -0500
@@ -1,4 +1,5 @@
/*
+ * Copyright (c) 2014 Advanced Micro Devices, Inc.
* Copyright (c) 2007 The Hewlett-Packard Development Company
* All rights reserved.
*
@@ -42,11 +43,15 @@
#include iostream
#include string
+#include vector
#include base/bitunion.hh
#include base/misc.hh
#include base/types.hh
#include base/trie.hh
+#include cpu/thread_context.hh
+#include arch/x86/system.hh
+#include debug/MMU.hh
class Checkpoint;
@@ -73,6 +78,25 @@
Bitfield31, 22 norml2;
EndBitUnion(VAddr)
+// Unfortunately, the placement of the base field in a page table entry is
+// very erratic and would make a mess here. It might be moved here at some
+// point in the future.
+BitUnion64(PageTableEntry)
+Bitfield63 nx;
+Bitfield51, 12 base;
+Bitfield11, 9 avl;
+Bitfield8 g;
+Bitfield7 ps;
+Bitfield6 d;
+Bitfield5 a;
+Bitfield4 pcd;
+Bitfield3 pwt;
+Bitfield2 u;
+Bitfield1 w;
+Bitfield0 p;
+EndBitUnion(PageTableEntry)
+
+
struct TlbEntry
{
// The base of the physical page.
@@ -127,6 +151,67 @@
void serialize(std::ostream os);
void unserialize(Checkpoint *cp, const std::string section);
};
+
+/** The size of each level of the page table expressed in base 2
+ * logarithmic values
+ */
+const std::vectoruint8_t PageTableLayout = {9, 9, 9, 9};
+
+enum PTEField{
+
Re: [gem5-dev] changeset in gem5: mem: adding architectural page table support ...
Hi Alexandru,
I merely wanted to point out that there are quite some places where the
new changes violate the 80 char limit. It might not be worth fixing on its
own, but for any future changes...
Thanks,
Andreas
On 28/08/2014 16:31, Alexandru via gem5-dev gem5-dev@gem5.org wrote:
changeset bec0c5ffc323 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=bec0c5ffc323
description:
mem: adding architectural page table support for SE mode
This patch enables the use of page tables that are stored in system
memory
and respect x86 specification, in SE mode. It defines an architectural
page table for x86 as a MultiLevelPageTable class and puts a placeholder
class for other ISAs page tables, giving the possibility for future
implementation.
diffstat:
src/arch/alpha/process.hh| 3 +
src/arch/arm/process.hh | 3 +
src/arch/mips/process.hh | 3 +
src/arch/power/process.hh| 3 +
src/arch/sparc/process.hh| 3 +
src/arch/x86/pagetable.hh| 85
src/arch/x86/pagetable_walker.cc | 17
src/arch/x86/process.hh | 9
src/arch/x86/system.hh | 14 ++
src/mem/SConscript | 2 +
src/sim/Process.py | 2 +
src/sim/process.cc | 5 +-
src/sim/process.hh | 2 +
13 files changed, 133 insertions(+), 18 deletions(-)
diffs (truncated from 305 to 300 lines):
diff -r 77af86f37337 -r bec0c5ffc323 src/arch/alpha/process.hh
--- a/src/arch/alpha/process.hhTue Apr 01 12:18:12 2014 -0500
+++ b/src/arch/alpha/process.hhThu Aug 28 10:11:44 2014 -0500
@@ -55,4 +55,7 @@
void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value);
};
+/* No architectural page table defined for this ISA */
+typedef NoArchPageTable ArchPageTable;
+
#endif // __ARCH_ALPHA_PROCESS_HH__
diff -r 77af86f37337 -r bec0c5ffc323 src/arch/arm/process.hh
--- a/src/arch/arm/process.hh Tue Apr 01 12:18:12 2014 -0500
+++ b/src/arch/arm/process.hh Thu Aug 28 10:11:44 2014 -0500
@@ -98,5 +98,8 @@
void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value);
};
+/* No architectural page table defined for this ISA */
+typedef NoArchPageTable ArchPageTable;
+
#endif // __ARM_PROCESS_HH__
diff -r 77af86f37337 -r bec0c5ffc323 src/arch/mips/process.hh
--- a/src/arch/mips/process.hh Tue Apr 01 12:18:12 2014 -0500
+++ b/src/arch/mips/process.hh Thu Aug 28 10:11:44 2014 -0500
@@ -59,5 +59,8 @@
void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value);
};
+/* No architectural page table defined for this ISA */
+typedef NoArchPageTable ArchPageTable;
+
#endif // __MIPS_PROCESS_HH__
diff -r 77af86f37337 -r bec0c5ffc323 src/arch/power/process.hh
--- a/src/arch/power/process.hhTue Apr 01 12:18:12 2014 -0500
+++ b/src/arch/power/process.hhThu Aug 28 10:11:44 2014 -0500
@@ -58,5 +58,8 @@
void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value);
};
+/* No architectural page table defined for this ISA */
+typedef NoArchPageTable ArchPageTable;
+
#endif // __POWER_PROCESS_HH__
diff -r 77af86f37337 -r bec0c5ffc323 src/arch/sparc/process.hh
--- a/src/arch/sparc/process.hhTue Apr 01 12:18:12 2014 -0500
+++ b/src/arch/sparc/process.hhThu Aug 28 10:11:44 2014 -0500
@@ -131,4 +131,7 @@
void setSyscallArg(ThreadContext *tc, int i, SparcISA::IntReg val);
};
+/* No architectural page table defined for this ISA */
+typedef NoArchPageTable ArchPageTable;
+
#endif // __SPARC_PROCESS_HH__
diff -r 77af86f37337 -r bec0c5ffc323 src/arch/x86/pagetable.hh
--- a/src/arch/x86/pagetable.hhTue Apr 01 12:18:12 2014 -0500
+++ b/src/arch/x86/pagetable.hhThu Aug 28 10:11:44 2014 -0500
@@ -1,4 +1,5 @@
/*
+ * Copyright (c) 2014 Advanced Micro Devices, Inc.
* Copyright (c) 2007 The Hewlett-Packard Development Company
* All rights reserved.
*
@@ -42,11 +43,15 @@
#include iostream
#include string
+#include vector
#include base/bitunion.hh
#include base/misc.hh
#include base/types.hh
#include base/trie.hh
+#include cpu/thread_context.hh
+#include arch/x86/system.hh
+#include debug/MMU.hh
class Checkpoint;
@@ -73,6 +78,25 @@
Bitfield31, 22 norml2;
EndBitUnion(VAddr)
+// Unfortunately, the placement of the base field in a page table
entry is
+// very erratic and would make a mess here. It might be moved here
at some
+// point in the future.
+BitUnion64(PageTableEntry)
+Bitfield63 nx;
+Bitfield51, 12 base;
+Bitfield11, 9 avl;
+Bitfield8 g;
+Bitfield7 ps;
+Bitfield6 d;
+Bitfield5 a;
+Bitfield4 pcd;
+Bitfield3 pwt;
+Bitfield2 u;
+Bitfield1 w;
+Bitfield0 p;
+EndBitUnion(PageTableEntry)
+
+
struct TlbEntry
{
// The base of the physical page.
@@ -127,6 +151,67 @@
Re: [gem5-dev] changeset in gem5: mem: adding architectural page table support ...
Hi Andreas,
You are right, grep -ERsonH '.{80,}$' reveales 7 lines being longer.
Sorry about this, next time I will double check. Thanks for pointing this out!
Alex
From: gem5-dev [gem5-dev-boun...@gem5.org] on behalf of Andreas Hansson via
gem5-dev [gem5-dev@gem5.org]
Sent: Thursday, August 28, 2014 11:31 AM
To: gem5 Developer List
Subject: Re: [gem5-dev] changeset in gem5: mem: adding architectural page table
support ...
Hi Alexandru,
I merely wanted to point out that there are quite some places where the
new changes violate the 80 char limit. It might not be worth fixing on its
own, but for any future changes...
Thanks,
Andreas
On 28/08/2014 16:31, Alexandru via gem5-dev gem5-dev@gem5.org wrote:
changeset bec0c5ffc323 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=bec0c5ffc323
description:
mem: adding architectural page table support for SE mode
This patch enables the use of page tables that are stored in system
memory
and respect x86 specification, in SE mode. It defines an architectural
page table for x86 as a MultiLevelPageTable class and puts a placeholder
class for other ISAs page tables, giving the possibility for future
implementation.
diffstat:
src/arch/alpha/process.hh| 3 +
src/arch/arm/process.hh | 3 +
src/arch/mips/process.hh | 3 +
src/arch/power/process.hh| 3 +
src/arch/sparc/process.hh| 3 +
src/arch/x86/pagetable.hh| 85
src/arch/x86/pagetable_walker.cc | 17
src/arch/x86/process.hh | 9
src/arch/x86/system.hh | 14 ++
src/mem/SConscript | 2 +
src/sim/Process.py | 2 +
src/sim/process.cc | 5 +-
src/sim/process.hh | 2 +
13 files changed, 133 insertions(+), 18 deletions(-)
diffs (truncated from 305 to 300 lines):
diff -r 77af86f37337 -r bec0c5ffc323 src/arch/alpha/process.hh
--- a/src/arch/alpha/process.hhTue Apr 01 12:18:12 2014 -0500
+++ b/src/arch/alpha/process.hhThu Aug 28 10:11:44 2014 -0500
@@ -55,4 +55,7 @@
void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value);
};
+/* No architectural page table defined for this ISA */
+typedef NoArchPageTable ArchPageTable;
+
#endif // __ARCH_ALPHA_PROCESS_HH__
diff -r 77af86f37337 -r bec0c5ffc323 src/arch/arm/process.hh
--- a/src/arch/arm/process.hh Tue Apr 01 12:18:12 2014 -0500
+++ b/src/arch/arm/process.hh Thu Aug 28 10:11:44 2014 -0500
@@ -98,5 +98,8 @@
void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value);
};
+/* No architectural page table defined for this ISA */
+typedef NoArchPageTable ArchPageTable;
+
#endif // __ARM_PROCESS_HH__
diff -r 77af86f37337 -r bec0c5ffc323 src/arch/mips/process.hh
--- a/src/arch/mips/process.hh Tue Apr 01 12:18:12 2014 -0500
+++ b/src/arch/mips/process.hh Thu Aug 28 10:11:44 2014 -0500
@@ -59,5 +59,8 @@
void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value);
};
+/* No architectural page table defined for this ISA */
+typedef NoArchPageTable ArchPageTable;
+
#endif // __MIPS_PROCESS_HH__
diff -r 77af86f37337 -r bec0c5ffc323 src/arch/power/process.hh
--- a/src/arch/power/process.hhTue Apr 01 12:18:12 2014 -0500
+++ b/src/arch/power/process.hhThu Aug 28 10:11:44 2014 -0500
@@ -58,5 +58,8 @@
void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value);
};
+/* No architectural page table defined for this ISA */
+typedef NoArchPageTable ArchPageTable;
+
#endif // __POWER_PROCESS_HH__
diff -r 77af86f37337 -r bec0c5ffc323 src/arch/sparc/process.hh
--- a/src/arch/sparc/process.hhTue Apr 01 12:18:12 2014 -0500
+++ b/src/arch/sparc/process.hhThu Aug 28 10:11:44 2014 -0500
@@ -131,4 +131,7 @@
void setSyscallArg(ThreadContext *tc, int i, SparcISA::IntReg val);
};
+/* No architectural page table defined for this ISA */
+typedef NoArchPageTable ArchPageTable;
+
#endif // __SPARC_PROCESS_HH__
diff -r 77af86f37337 -r bec0c5ffc323 src/arch/x86/pagetable.hh
--- a/src/arch/x86/pagetable.hhTue Apr 01 12:18:12 2014 -0500
+++ b/src/arch/x86/pagetable.hhThu Aug 28 10:11:44 2014 -0500
@@ -1,4 +1,5 @@
/*
+ * Copyright (c) 2014 Advanced Micro Devices, Inc.
* Copyright (c) 2007 The Hewlett-Packard Development Company
* All rights reserved.
*
@@ -42,11 +43,15 @@
#include iostream
#include string
+#include vector
#include base/bitunion.hh
#include base/misc.hh
#include base/types.hh
#include base/trie.hh
+#include cpu/thread_context.hh
+#include arch/x86/system.hh
+#include debug/MMU.hh
class Checkpoint;
@@ -73,6 +78,25 @@
Bitfield31, 22 norml2;
EndBitUnion(VAddr)
+// Unfortunately, the placement of the base field in a page table
entry is
+// very erratic and would make a mess here. It might be moved here
at some
