[m5-dev] Cron m5t...@zizzer /z/m5/regression/do-regression quick
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[m5-dev] Review Request: Ruby: Update MOESI Hammer protocol
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/280/ --- Review request for Default. Summary --- This request is for reviewing the updates made to the MOESI Hammer protocol so that it conforms with the new interfaces of CacheMemory and TBETable classes, and the changes in SLICC. Diffs - src/mem/protocol/MOESI_hammer-cache.sm 2f26548628fd src/mem/protocol/MOESI_hammer-dir.sm 2f26548628fd Diff: http://reviews.m5sim.org/r/280/diff Testing --- The changes have been tested using ruby_random_test.py for a 1,000,000 loads and 20 different seed values. Thanks, Nilay ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Review Request: Ruby: Update MOESI Hammer protocol
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/280/ --- (Updated 2010-12-31 17:26:11.666038) Review request for Default. Changes --- As usual, I had forgotten to mention the option --git while executing the command 'hg qdiff' to generate the diff. Summary --- This request is for reviewing the updates made to the MOESI Hammer protocol so that it conforms with the new interfaces of CacheMemory and TBETable classes, and the changes in SLICC. Diffs (updated) - src/mem/protocol/MOESI_hammer-cache.sm UNKNOWN src/mem/protocol/MOESI_hammer-dir.sm UNKNOWN Diff: http://reviews.m5sim.org/r/280/diff Testing --- The changes have been tested using ruby_random_test.py for a 1,000,000 loads and 20 different seed values. Thanks, Nilay ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Review Request: Updates MI cache coherence protocol
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/335/ --- (Updated 2010-12-31 17:28:19.882643) Review request for Default. Changes --- Some more changes have been made to SLICC. This necessitated changes to the protocol implementation. Summary --- This is a review request for the patch that updates the MI cache coherence protocol to conform with the new interfaces of CacheMemory and TBETable classes, and the changes in SLICC. Diffs (updated) - src/mem/protocol/MI_example-cache.sm UNKNOWN src/mem/protocol/MI_example-dir.sm UNKNOWN Diff: http://reviews.m5sim.org/r/335/diff Testing --- Tested using ruby_random_tester.py with l = 10,000,000 and n = 2. Thanks, Nilay ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Review Request: Ruby: Update MOESI CMP token protocol
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/326/ --- Review request for Default. Summary --- This request for reviewing the updates to implementation of the MOESI CMP token protocol. These updates have been carried out so as to conform with the changes made to CacheMemory and TBETable classes, and to SLICC. Diffs - src/mem/protocol/MOESI_CMP_token-L1cache.sm UNKNOWN src/mem/protocol/MOESI_CMP_token-L2cache.sm UNKNOWN src/mem/protocol/MOESI_CMP_token-dir.sm UNKNOWN Diff: http://reviews.m5sim.org/r/326/diff Testing --- Changes have been tested using ruby_random_test.py for 1,000,000 loads and 20 different seeds for random number generator. Thanks, Nilay ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Review Request: Updating MOESI CMP Directory protocol as per the new interface
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/359/ --- (Updated 2010-12-31 17:35:16.274524) Review request for Default. Changes --- The changes made were necessitated by the changes made to SLICC and CacheMemory class. Summary --- This is a request for reviewing the proposed changes to the MOESI CMP directory cache coherence protocol to make it conform with the new cache memory interface and changes to SLICC. Diffs (updated) - src/mem/protocol/MOESI_CMP_directory-L1cache.sm UNKNOWN src/mem/protocol/MOESI_CMP_directory-L2cache.sm UNKNOWN src/mem/protocol/MOESI_CMP_directory-dir.sm UNKNOWN src/mem/protocol/MOESI_CMP_directory-dma.sm UNKNOWN Diff: http://reviews.m5sim.org/r/359/diff Testing --- These changes have been tested using the Ruby random tester. The tester was used with -l = 1048576 and -n = 2. Thanks, Nilay ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Review Request: Changing how CacheMemory interfaces with SLICC
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/358/ --- (Updated 2010-12-31 17:50:59.779517) Review request for Default. Changes --- 1. lookup_ptr() function has been removed from CacheMemory class. Instead, lookup() function has been changed so that it returns a pointer to an AbstractCacheEntry, as opposed to a reference. 2. The manner in which the declaration of a CacheEntry structure in the protocol file is detected has been changed. Earlier detection was carried out using the name of the structure i.e. the structure should be named 'Entry' for the compiler to assume that it is the CacheEntry structure for that particular machine under consideration. Now, the check is made on the interface supplied with the structure declaration. It should be 'AbstractCacheEntry'. I think an assumption has been made that this would happen only once in the entire file. An error is raised if it happens more than once, though the error condition has not yet been tested. 3. While making changes to the MOESI Hammer protocol, I realized that the previously made changes to SLICC would not suffice. Earlier, the changes had been made under the assumption that at any given point of time, only one cache entry would be updated. But in the Hammer protocol, two cache entries can be processed in a single step. One of these would belong to L1 and the other to L2. I think the Hammer protocol could not have been supported with just one cache entry variable being passed to the trigger function. So, now the number of cache entries passed to the trigger function and subsequently to actions is same as the number of cache memories in the machine under consideration. This is two for MOESI_CMP_* and three for MOESI_hammer. Most of the changes that have been made since the previous version of the diff, are there to support because of the reason outlined above. Summary --- The purpose of this patch is to change the way CacheMemory interfaces with coherence protocols. Currently, whenever a cache controller (defined in the protocol under consideration) needs to carry out any operation on a cache block, it looks up the tag hash map and figures out whether or not the block exists in the cache. In case it does exist, the operation is carried out (which requires another lookup). Over a single clock cycle, multiple such lookups take place as observed through profiling of different protocols. It was seen that the tag lookup takes anything from 10% to 20% of the simulation time. In order to reduce this time, this patch is being posted. The CacheMemory class now will have a function that will return pointer to a cache block entry, instead of a reference (though the function that returns the reference has been retained currently). Functions have been introduced for setting/unsetting a pointer and check its pointer. Similar changes have been carried out for Transaction Buffer entries as well. Note that changes are required to both SLICC and the protocol files. This patch carries out changes to SLICC and committing this patch alone, I believe, will ___break___ all the protocols. I am working on patching the protocols as well. This patch is being put to get feed back from other developers. Diffs (updated) - src/mem/protocol/RubySlicc_Types.sm UNKNOWN src/mem/ruby/slicc_interface/AbstractCacheEntry.hh UNKNOWN src/mem/ruby/slicc_interface/AbstractCacheEntry.cc UNKNOWN src/mem/ruby/system/CacheMemory.hh UNKNOWN src/mem/ruby/system/CacheMemory.cc UNKNOWN src/mem/ruby/system/TBETable.hh UNKNOWN src/mem/slicc/ast/ActionDeclAST.py UNKNOWN src/mem/slicc/ast/FormalParamAST.py UNKNOWN src/mem/slicc/ast/FuncCallExprAST.py UNKNOWN src/mem/slicc/ast/FuncDeclAST.py UNKNOWN src/mem/slicc/ast/InPortDeclAST.py UNKNOWN src/mem/slicc/ast/IsValidPtrExprAST.py PRE-CREATION src/mem/slicc/ast/MethodCallExprAST.py UNKNOWN src/mem/slicc/ast/StaticCastAST.py UNKNOWN src/mem/slicc/ast/TypeDeclAST.py UNKNOWN src/mem/slicc/ast/__init__.py UNKNOWN src/mem/slicc/parser.py UNKNOWN src/mem/slicc/symbols/StateMachine.py UNKNOWN src/mem/slicc/symbols/SymbolTable.py UNKNOWN Diff: http://reviews.m5sim.org/r/358/diff Testing --- I have tested these changes using the MOESI_CMP_directory and MI protocols. Thanks, Nilay ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
