date:20110227

Re: [m5-dev] Review Request: O3: Tighten memory order violation checking to 16 bytes.

2011-02-27 Thread Gabe Black

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---

Should we put an assert in there to make sure no access is bigger than 16 
bytes? Also what about unaligned accesses? I think those will be split on cache 
block boundaries which may be bigger or smaller than 16 bytes. We might have an 
access that spans from one 16 byte chunk to the next. These aren't really 
problems with this change, but it might make them easier to hit.

I'm assuming this had some effect on the regressions. Did things generally go 
faster, slower, etc.?

- Gabe

On 2011-02-27 18:52:51, Ali Saidi wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/520/
> ---
> 
> (Updated 2011-02-27 18:52:51)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> O3: Tighten memory order violation checking to 16 bytes.
> 
> The comment in the code suggests that the checking granularity should be 16
> bytes, however in reality the shift by 8 is 256 bytes which seems much
> larger than required.
> 
> 
> Diffs
> -
> 
>   src/cpu/o3/lsq_unit_impl.hh 9dc17725f795 
> 
> Diff: http://reviews.m5sim.org/r/520/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Ali
> 
>

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[m5-dev] Review Request: O3: Tighten memory order violation checking to 16 bytes.

2011-02-27 Thread Ali Saidi


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This is an automatically generated e-mail. To reply, visit:
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---

Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan 
Binkert.


Summary
---

O3: Tighten memory order violation checking to 16 bytes.

The comment in the code suggests that the checking granularity should be 16
bytes, however in reality the shift by 8 is 256 bytes which seems much
larger than required.


Diffs
-

  src/cpu/o3/lsq_unit_impl.hh 9dc17725f795 

Diff: http://reviews.m5sim.org/r/520/diff


Testing
---


Thanks,

Ali

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[m5-dev] Review Request: Spelling: Fix the a spelling error by changing mmaped to mmapped.

2011-02-27 Thread Gabe Black


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http://reviews.m5sim.org/r/519/
---

Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan 
Binkert.


Summary
---

Spelling: Fix the a spelling error by changing mmaped to mmapped.

There may not be a formally correct spelling for the past tense of mmap, but
mmapped is the spelling Google doesn't try to autocorrect. This makes sense
because it mirrors the past tense of map->mapped and not the past tense of
cape->caped.


Diffs
-

  src/arch/SConscript 59a19310ca65 
  src/arch/alpha/mmaped_ipr.hh 59a19310ca65 
  src/arch/alpha/mmapped_ipr.hh PRE-CREATION 
  src/arch/arm/mmaped_ipr.hh 59a19310ca65 
  src/arch/arm/mmapped_ipr.hh PRE-CREATION 
  src/arch/mips/mmaped_ipr.hh 59a19310ca65 
  src/arch/mips/mmapped_ipr.hh PRE-CREATION 
  src/arch/power/mmaped_ipr.hh 59a19310ca65 
  src/arch/power/mmapped_ipr.hh PRE-CREATION 
  src/arch/sparc/mmaped_ipr.hh 59a19310ca65 
  src/arch/sparc/mmapped_ipr.hh PRE-CREATION 
  src/arch/sparc/tlb.cc 59a19310ca65 
  src/arch/x86/mmaped_ipr.hh 59a19310ca65 
  src/arch/x86/mmapped_ipr.hh PRE-CREATION 
  src/arch/x86/tlb.cc 59a19310ca65 
  src/cpu/simple/atomic.cc 59a19310ca65 
  src/cpu/simple/timing.cc 59a19310ca65 
  src/mem/physical.cc 59a19310ca65 
  src/mem/request.hh 59a19310ca65 

Diff: http://reviews.m5sim.org/r/519/diff


Testing
---


Thanks,

Gabe

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[m5-dev] Review Request: X86: Mark IO reads and writes as non-speculative.

2011-02-27 Thread Gabe Black


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This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/518/
---

Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan 
Binkert.


Summary
---

X86: Mark IO reads and writes as non-speculative.


Diffs
-

  src/arch/x86/isa/insts/general_purpose/input_output/general_io.py 
ac1bd3d1aa54 
  src/arch/x86/isa/insts/general_purpose/input_output/string_io.py ac1bd3d1aa54 
  src/arch/x86/isa/microops/ldstop.isa ac1bd3d1aa54 

Diff: http://reviews.m5sim.org/r/518/diff


Testing
---


Thanks,

Gabe

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[m5-dev] Review Request: X86: Mark prefetches as such in their instruction and request flags.

2011-02-27 Thread Gabe Black


---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/517/
---

Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan 
Binkert.


Summary
---

X86: Mark prefetches as such in their instruction and request flags.


Diffs
-

  src/arch/x86/isa/microops/ldstop.isa ac1bd3d1aa54 

Diff: http://reviews.m5sim.org/r/517/diff


Testing
---


Thanks,

Gabe

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[m5-dev] changeset in m5: X86: If PCI config space is disabled, pass thro...

2011-02-27 Thread Gabe Black

changeset 59a19310ca65 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=59a19310ca65
description:
X86: If PCI config space is disabled, pass through to regular IO 
addresses.

diffstat:

 src/arch/x86/tlb.cc |  2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diffs (12 lines):

diff -r a314f5c2caa0 -r 59a19310ca65 src/arch/x86/tlb.cc
--- a/src/arch/x86/tlb.cc   Sun Feb 27 16:24:54 2011 -0800
+++ b/src/arch/x86/tlb.cc   Sun Feb 27 16:25:06 2011 -0800
@@ -518,6 +518,8 @@
 req->setPaddr(PhysAddrPrefixPciConfig |
 mbits(configAddress, 30, 2) |
 (IOPort & mask(2)));
+} else {
+req->setPaddr(PhysAddrPrefixIO | IOPort);
 }
 } else {
 req->setFlags(Request::UNCACHEABLE);
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[m5-dev] changeset in m5: X86: Use regular read requests in the walker in...

2011-02-27 Thread Gabe Black

changeset 021a0724c5c0 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=021a0724c5c0
description:
X86: Use regular read requests in the walker instead of read exclusive.

diffstat:

 src/arch/x86/pagetable_walker.cc |  4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diffs (21 lines):

diff -r 5651f447e601 -r 021a0724c5c0 src/arch/x86/pagetable_walker.cc
--- a/src/arch/x86/pagetable_walker.cc  Sun Feb 27 14:17:26 2011 -0500
+++ b/src/arch/x86/pagetable_walker.cc  Sun Feb 27 16:24:10 2011 -0800
@@ -508,7 +508,7 @@
 flags.set(Request::UNCACHEABLE, uncacheable);
 RequestPtr request =
 new Request(nextRead, oldRead->getSize(), flags);
-read = new Packet(request, MemCmd::ReadExReq, Packet::Broadcast);
+read = new Packet(request, MemCmd::ReadReq, Packet::Broadcast);
 read->allocate();
 // If we need to write, adjust the read packet to write the modified
 // value back to memory.
@@ -578,7 +578,7 @@
 if (cr3.pcd)
 flags.set(Request::UNCACHEABLE);
 RequestPtr request = new Request(topAddr, dataSize, flags);
-read = new Packet(request, MemCmd::ReadExReq, Packet::Broadcast);
+read = new Packet(request, MemCmd::ReadReq, Packet::Broadcast);
 read->allocate();
 }
 
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[m5-dev] changeset in m5: X86: Update X86_FS stats.

2011-02-27 Thread Gabe Black

changeset a314f5c2caa0 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a314f5c2caa0
description:
X86: Update X86_FS stats.

diffstat:

 tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout|   11 +-
 tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt |  351 ++--
 tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/simout|   11 +-
 tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt |  791 
-
 4 files changed, 578 insertions(+), 586 deletions(-)

diffs (truncated from 1666 to 300 lines):

diff -r 021a0724c5c0 -r a314f5c2caa0 
tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
--- a/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/simoutSun Feb 
27 16:24:10 2011 -0800
+++ b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/simoutSun Feb 
27 16:24:54 2011 -0800
@@ -5,12 +5,13 @@
 All Rights Reserved
 
 
-M5 compiled Feb  8 2011 00:58:27
-M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip
-M5 started Feb  8 2011 00:58:30
+M5 compiled Feb 26 2011 16:13:31
+M5 revision 412ef0f728a5 8092 default qtip tip updatefsstats.patch
+M5 started Feb 26 2011 16:13:35
 M5 executing on burrito
-command line: build/X86_FS/m5.fast -d 
build/X86_FS/tests/fast/long/10.linux-boot/x86/linux/pc-simple-atomic -re 
tests/run.py 
build/X86_FS/tests/fast/long/10.linux-boot/x86/linux/pc-simple-atomic
+command line: build/X86_FS/m5.opt -d 
build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-simple-atomic -re 
tests/run.py 
build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-simple-atomic
 Global frequency set at 1 ticks per second
 info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+  0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 5112051463500 because m5_exit instruction encountered
+Exiting @ tick 5112051446000 because m5_exit instruction encountered
diff -r 021a0724c5c0 -r a314f5c2caa0 
tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
--- a/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt Sun Feb 
27 16:24:10 2011 -0800
+++ b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt Sun Feb 
27 16:24:54 2011 -0800
@@ -1,30 +1,30 @@
 
 -- Begin Simulation Statistics --
-host_inst_rate1892986   # 
Simulator instruction rate (inst/s)
-host_mem_usage 370804   # 
Number of bytes of host memory used
-host_seconds   214.81   # 
Real time elapsed on the host
-host_tick_rate23798444654   # 
Simulator tick rate (ticks/s)
+host_inst_rate2446370   # 
Simulator instruction rate (inst/s)
+host_mem_usage 368136   # 
Number of bytes of host memory used
+host_seconds   166.22   # 
Real time elapsed on the host
+host_tick_rate30755543746   # 
Simulator tick rate (ticks/s)
 sim_freq 1   # 
Frequency of simulated ticks
-sim_insts   406624453   # 
Number of instructions simulated
+sim_insts   406624458   # 
Number of instructions simulated
 sim_seconds  5.112051   # 
Number of seconds simulated
-sim_ticks5112051463500   # 
Number of ticks simulated
+sim_ticks5112051446000   # 
Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses::013367989   # 
number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total 13367989   # 
number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_hits::012053700   # 
number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total12053700   # 
number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_rate::0   0.098316   # 
miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::0   1314289   # 
number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total   1314289   # 
number of ReadReq misses
+system.cpu.dcache.ReadReq_hits::012059464   # 
number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total12059464   # 
number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_rate::0   0.097885

Re: [m5-dev] Cron /z/m5/regression/do-regression --scratch all

2011-02-27 Thread Korey Sewell

Sorry about that folks.

Looks like I committed the regression stats from some uncommitted patches.

Should be updated now.

On Sun, Feb 27, 2011 at 1:13 PM, Ali Saidi  wrote:

> Korey,
>
> It doesn't look like anything committed between when you added your
> regression test and this failing could have changed the inorder stats. Could
> you take a look at it?
>
> Thanks,
> Ali
>
>
>
>
> On Feb 27, 2011, at 10:33 AM, Cron Daemon wrote:
>
> > * build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/inorder-timing
> FAILED!
> > * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing
> passed.
> > *
> build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby
> passed.
> > * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing
> passed.
> > *
> build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp passed.
> > * build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest
> passed.
> > *
> build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing
> passed.
> > *
> build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby
> passed.
> > * build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing
> passed.
> > * build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing
> passed.
> > * build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic
> passed.
> > * build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing
> passed.
> > * build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing
> passed.
> > *
> build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby
> passed.
> > * build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing
> passed.
> > * build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby
> passed.
> > * build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic
> passed.
> > * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic
> passed.
> > * build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing
> passed.
> > *
> build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp passed.
> > * build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic
> passed.
> > * build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing
> passed.
> > * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic
> passed.
> > * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing
> passed.
> > *
> build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic passed.
> > * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing
> passed.
> > * build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing
> passed.
> > * build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic
> passed.
> > * build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic
> passed.
> > * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing
> passed.
> > * build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing passed.
> > *
> build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing passed.
> > * build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
> passed.
> > * build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic
> passed.
> > * build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing
> passed.
> > *
> build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer
> passed.
> > *
> build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
> passed.
> > * build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing
> passed.
> > *
> build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
> passed.
> > *
> build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer
> passed.
> > *
> build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory
> passed.
> > *
> build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory
> passed.
> > *
> build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory
> passed.
> > *
> build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory
> passed.
> > *
> build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory
> passed.
> > *
> build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
> passed.
> > *
> build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
> passed.
> > *
> build/ALPHA_SE_MOESI_CMP_direct

[m5-dev] changeset in m5: inorder: bzip2 regression update

2011-02-27 Thread Korey Sewell

changeset 5651f447e601 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5651f447e601
description:
inorder: bzip2 regression update

diffstat:

 tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout|   10 +-
 tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt |  348 +-
 2 files changed, 178 insertions(+), 180 deletions(-)

diffs (truncated from 489 to 300 lines):

diff -r baf4b5f6782e -r 5651f447e601 
tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout
--- a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout Sat Feb 26 
21:43:11 2011 -0800
+++ b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout Sun Feb 27 
14:17:26 2011 -0500
@@ -7,10 +7,10 @@
 All Rights Reserved
 
 
-M5 compiled Feb 23 2011 12:26:45
-M5 revision Unknown
-M5 started Feb 23 2011 14:50:29
-M5 executing on m55-001.pool
+M5 compiled Feb 27 2011 03:06:45
+M5 revision baf4b5f6782e 8094 default tip
+M5 started Feb 27 2011 03:13:10
+M5 executing on zizzer
 command line: build/ALPHA_SE/m5.fast -d 
build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/inorder-timing -re 
tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/inorder-timing
 Global frequency set at 1 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -30,4 +30,4 @@
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 916989799500 because target called exit()
+Exiting @ tick 979951369500 because target called exit()
diff -r baf4b5f6782e -r 5651f447e601 
tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
--- a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt  Sat Feb 
26 21:43:11 2011 -0800
+++ b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt  Sun Feb 
27 14:17:26 2011 -0500
@@ -1,38 +1,37 @@
 
 -- Begin Simulation Statistics --
-host_inst_rate 136726   # 
Simulator instruction rate (inst/s)
-host_mem_usage 444148   # 
Number of bytes of host memory used
-host_seconds 13309.73   # 
Real time elapsed on the host
-host_tick_rate   68896185   # 
Simulator tick rate (ticks/s)
+host_inst_rate 121455   # 
Simulator instruction rate (inst/s)
+host_mem_usage1130520   # 
Number of bytes of host memory used
+host_seconds 14983.11   # 
Real time elapsed on the host
+host_tick_rate   65403738   # 
Simulator tick rate (ticks/s)
 sim_freq 1   # 
Frequency of simulated ticks
 sim_insts  1819780127   # 
Number of instructions simulated
-sim_seconds  0.916990   # 
Number of seconds simulated
-sim_ticks916989799500   # 
Number of ticks simulated
-system.cpu.AGEN-Unit.agens  608310443   # 
Number of Address Generations
-system.cpu.Branch-Predictor.BTBHitPct   99.483708   # 
BTB Hit Percentage
-system.cpu.Branch-Predictor.BTBHits 174550225   # 
Number of BTB hits
-system.cpu.Branch-Predictor.BTBLookups  175456091   # 
Number of BTB lookups
-system.cpu.Branch-Predictor.BTBNoTargets   905866   # 
Number of times BTB has no targets for prediction
+sim_seconds  0.979951   # 
Number of seconds simulated
+sim_ticks979951369500   # 
Number of ticks simulated
+system.cpu.AGEN-Unit.agens  614316005   # 
Number of Address Generations
+system.cpu.Branch-Predictor.BTBHitPct   69.872947   # 
BTB Hit Percentage
+system.cpu.Branch-Predictor.BTBHits  82064192   # 
Number of BTB hits
+system.cpu.Branch-Predictor.BTBLookups  117447733   # 
Number of BTB lookups
 system.cpu.Branch-Predictor.RASInCorrect6   # 
Number of incorrect RAS predictions.
-system.cpu.Branch-Predictor.condIncorrect 24019275   # 
Number of conditional branches incorrect
-system.cpu.Branch-Predictor.condPredicted170526345   # 
Number of conditional branches predicted
-system.cpu.Branch-Predictor.lookups 223585344   # 
Number of BP lookups
-system.cpu.Branch-Predictor.predictedNotTaken 14030167 
  # Number of Branches Pre

Re: [m5-dev] Cron /z/m5/regression/do-regression --scratch all

2011-02-27 Thread Ali Saidi


Korey,

It doesn't look like anything committed between when you added your regression 
test and this failing could have changed the inorder stats. Could you take a 
look at it?

Thanks,
Ali
On Feb 27, 2011, at 10:33 AM, Cron Daemon wrote:

> * build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/inorder-timing 
> FAILED!
> * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing 
> passed.
> * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby 
> passed.
> * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing 
> passed.
> * build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp 
> passed.
> * build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest passed.
> * build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing 
> passed.
> * build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby 
> passed.
> * build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing passed.
> * build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing passed.
> * build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic passed.
> * build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing 
> passed.
> * build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing 
> passed.
> * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby 
> passed.
> * build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing 
> passed.
> * build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby 
> passed.
> * build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic passed.
> * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic 
> passed.
> * build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing 
> passed.
> * build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp 
> passed.
> * build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic 
> passed.
> * build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing 
> passed.
> * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic 
> passed.
> * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing 
> passed.
> * build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic 
> passed.
> * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing passed.
> * build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing passed.
> * build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic 
> passed.
> * build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic 
> passed.
> * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing passed.
> * build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing passed.
> * build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing 
> passed.
> * build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing passed.
> * build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic 
> passed.
> * build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing passed.
> * 
> build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer
>  passed.
> * 
> build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
>  passed.
> * build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing 
> passed.
> * 
> build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
>  passed.
> * 
> build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer
>  passed.
> * 
> build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory
>  passed.
> * 
> build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory
>  passed.
> * 
> build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory
>  passed.
> * 
> build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory
>  passed.
> * 
> build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory
>  passed.
> * 
> build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
>  passed.
> * 
> build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
>  passed.
> * 
> build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory
>  passed.
> * 
> build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token
>  passed.
> * 
> build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.h

Re: [m5-dev] Review Request: X86: If PCI config space is disabled, pass through to regular IO addresses.

2011-02-27 Thread Ali Saidi


---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/515/#review914
---

Ship it!


- Ali


On 2011-02-26 01:45:04, Gabe Black wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/515/
> ---
> 
> (Updated 2011-02-26 01:45:04)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> X86: If PCI config space is disabled, pass through to regular IO addresses.
> 
> 
> Diffs
> -
> 
>   src/arch/x86/tlb.cc ac1bd3d1aa54 
> 
> Diff: http://reviews.m5sim.org/r/515/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Gabe
> 
>

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Re: [m5-dev] Review Request: O3: Send instruction back to fetch on squash to seed predecoder correctly.

2011-02-27 Thread Ali Saidi



> On 2011-02-26 16:55:02, Gabe Black wrote:
> > I see what you're doing here, I think. For the strategy your taking your 
> > implementation seems ok (other than some weird whitespace), but I'm not 
> > sure this is the way to go. The itstate should be part of the pc and then 
> > wouldn't depend on anything in the previous instruction. The way you've 
> > implemented this forced itstate stuff may be the real culprit. I don't 
> > remember all the details of our previous conversation about it, but I do 
> > remember suggesting a way to implement that that fit better with the rest 
> > of the pc state information and I expect would make this change unnecessary.

I'll keep that in mind... this is the last bug that I know about that mucks 
with IT state. If we do find some other issues I'll see if putting it state in 
the PC helps, but I'm pretty sure matt tried that without success.


> On 2011-02-26 16:55:02, Gabe Black wrote:
> > src/arch/arm/predecoder.hh, line 92
> > 
> >
> > Why all the extra blank lines?

I went a little over board, I can clean them up.


- Ali


---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/511/#review909
---


On 2011-02-25 21:05:49, Ali Saidi wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/511/
> ---
> 
> (Updated 2011-02-25 21:05:49)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> O3: Send instruction back to fetch on squash to seed predecoder correctly.
> 
> 
> Diffs
> -
> 
>   src/arch/alpha/predecoder.hh 9dc17725f795 
>   src/arch/arm/predecoder.hh 9dc17725f795 
>   src/arch/mips/predecoder.hh 9dc17725f795 
>   src/arch/power/predecoder.hh 9dc17725f795 
>   src/arch/sparc/predecoder.hh 9dc17725f795 
>   src/arch/x86/predecoder.hh 9dc17725f795 
>   src/cpu/o3/cpu.cc 9dc17725f795 
>   src/cpu/o3/fetch.hh 9dc17725f795 
>   src/cpu/o3/fetch_impl.hh 9dc17725f795 
> 
> Diff: http://reviews.m5sim.org/r/511/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Ali
> 
>

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Re: [m5-dev] Review Request: O3: Cleanup the commitInfo comm struct.

2011-02-27 Thread Ali Saidi



> On 2011-02-26 16:48:07, Gabe Black wrote:
> > I don't see anything obviously wrong here, although I'm sure it wouldn't be 
> > hard to slip a bug into this code accidentally. Please be sure to run all 
> > the regressions just in case.

They all run. I was very careful when I did it, so I believe it is correct.


> On 2011-02-26 16:48:07, Gabe Black wrote:
> > src/cpu/o3/comm.hh, line 200
> > 
> >
> > You have two sentences mushed together here.

yup.


- Ali


---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/510/#review908
---


On 2011-02-25 21:04:59, Ali Saidi wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/510/
> ---
> 
> (Updated 2011-02-25 21:04:59)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> O3: Cleanup the commitInfo comm struct.
> 
> Get rid of unused members and use base types rather than derrived values
> where possible to limit amount of state. This cleans up a change to the
> fetch stage I promised Steve a month ago.
> 
> 
> Diffs
> -
> 
>   src/cpu/o3/comm.hh 9dc17725f795 
>   src/cpu/o3/commit.hh 9dc17725f795 
>   src/cpu/o3/commit_impl.hh 9dc17725f795 
>   src/cpu/o3/fetch_impl.hh 9dc17725f795 
>   src/cpu/o3/iew_impl.hh 9dc17725f795 
> 
> Diff: http://reviews.m5sim.org/r/510/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Ali
> 
>

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[m5-dev] Cron /z/m5/regression/do-regression --scratch all

2011-02-27 Thread Cron Daemon

* build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/inorder-timing FAILED!
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing passed.
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby 
passed.
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing 
passed.
* build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp 
passed.
* build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest passed.
* build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing 
passed.
* build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby 
passed.
* build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing passed.
* build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing passed.
* build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic passed.
* build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing passed.
* build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing 
passed.
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby 
passed.
* build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing passed.
* build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby 
passed.
* build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic passed.
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic passed.
* build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing passed.
* build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp 
passed.
* build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic passed.
* build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing passed.
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic passed.
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing passed.
* build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic 
passed.
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing passed.
* build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing passed.
* build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic passed.
* build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic 
passed.
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing passed.
* build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing passed.
* build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing 
passed.
* build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing passed.
* build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic passed.
* build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing passed.
* 
build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer
 passed.
* 
build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
 passed.
* build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing 
passed.
* 
build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
 passed.
* 
build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer
 passed.
* 
build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory
 passed.
* 
build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory
 passed.
* 
build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory
 passed.
* 
build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory
 passed.
* 
build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory
 passed.
* 
build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
 passed.
* 
build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
 passed.
* 
build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory
 passed.
* 
build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token
 passed.
* 
build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
 passed.
* 
build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
 passed.
* 
build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token
 passed.
* 
build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic 
passed.
* 
build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/

Re: [m5-dev] Review Request: O3: Tighten memory order violation checking to 16 bytes.

[m5-dev] Review Request: O3: Tighten memory order violation checking to 16 bytes.

[m5-dev] Review Request: Spelling: Fix the a spelling error by changing mmaped to mmapped.

[m5-dev] Review Request: X86: Mark IO reads and writes as non-speculative.

[m5-dev] Review Request: X86: Mark prefetches as such in their instruction and request flags.

[m5-dev] changeset in m5: X86: If PCI config space is disabled, pass thro...

[m5-dev] changeset in m5: X86: Use regular read requests in the walker in...

[m5-dev] changeset in m5: X86: Update X86_FS stats.

Re: [m5-dev] Cron /z/m5/regression/do-regression --scratch all

[m5-dev] changeset in m5: inorder: bzip2 regression update

Re: [m5-dev] Cron /z/m5/regression/do-regression --scratch all

Re: [m5-dev] Review Request: X86: If PCI config space is disabled, pass through to regular IO addresses.

Re: [m5-dev] Review Request: O3: Send instruction back to fetch on squash to seed predecoder correctly.

Re: [m5-dev] Review Request: O3: Cleanup the commitInfo comm struct.

[m5-dev] Cron /z/m5/regression/do-regression --scratch all

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