[gem5-users] L1/L2 cache bandwidth

2014-09-08 Thread senni sophiane via gem5-users
Hi all,

I saw in stats.txt there are information about memory bandwidth for
mem_ctrls. But I did not find this kind of information for cache memory.
I want to know if there are any information about (or related to) L1/L2
cache bandwidth ?

Thanks

-- 
Cordialement / Best Regards

SENNI Sophiane
Ph.D. candidate - Microelectronics
LIRMM - www.lirmm.fr

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[gem5-users] gem5 PC and function name mismatch

2014-09-08 Thread Scott Lerner via gem5-users
Hi all,

I am trying to do some validation of gem5 by looking at the output memory
traces and comparing them to the static-compiled binary.

What I have seen is that in the memory trace there will be an output line
like:
5228735114000: system.l1_cntrl3.sequencer: Ruby Hit Callback: Read, Thread
number=3, Pkt Address=0x3ff250c0,Pkt Size=8, Func=pthread_barrier_wait,
PC=0x402088

But when looking at the dump of the binary, the PC 0x402088 maps to a
different function:
004016d0 lu:
...
402083:   0f 8e f4 00 00 00   jle40217d lu+0xaad
...
00402740 OneSolve:

My question is should I trust the PC or the function name? Is there a way
to verify that either one is correct?

Thanks,

Scott
Ph.D. candidate
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[gem5-users] 3C's and classic memory model

2014-09-08 Thread Nizamudheen Ahmed via gem5-users
Hi,

I would like to categorize the cache misses into Cold/Capacity/Conflict
misses. I use classic memory-model. Is this cache-categorization scheme
already implemented in this model?
Thanks and regards,
Nizam
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[gem5-users] Questions on DRAM Controller model

2014-09-08 Thread Prathap Kolakkampadath via gem5-users
Hello Everybody,

I am using DDR3_1600_x64. I am trying to understand the memory controller
design and  have few doubts about it.

1) Do the memory controller has a separate  Bank request buffer (read and
write buffer) for each bank or just a global queue?
2) Is there a scheduler per bank which arbitrates between different queue
requests parallel with other bank schedulers?
3) Is there DRAM bus scheduler that arbitrates between different bank
requests?

Thanks,
Prathap
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Re: [gem5-users] Questions on DRAM Controller model

2014-09-08 Thread Andreas Hansson via gem5-users
Hi Prathap,

Have you read our ISPASS paper from last year? It’s referenced in the header 
file, as well as on gem5.org.

 1.  Yes and no. Two different buffers are used in the model are used, but they 
are random access, so you can treat the entries any way you want.
 2.  Yes and no. It’s a C++ model, so the scheduler executes in 0 time. Thus, 
when looking at the various requests it effectively sees all the banks.
 3.  Yes and no. See above.

Remember that this is a model. The goal is not to be representative down to 
every last element of an RTL design. The goal is to be representative of a real 
design, and then be fast. Both of these goals are delivered upon by the model.

I hope that explains it. IF there is anything in the results you do not agree 
with, please do say so.

Thanks,

Andreas

From: Prathap Kolakkampadath via gem5-users 
gem5-users@gem5.orgmailto:gem5-users@gem5.org
Reply-To: Prathap Kolakkampadath 
kvprat...@gmail.commailto:kvprat...@gmail.com, gem5 users mailing list 
gem5-users@gem5.orgmailto:gem5-users@gem5.org
Date: Monday, 8 September 2014 18:38
To: gem5 users mailing list gem5-users@gem5.orgmailto:gem5-users@gem5.org
Subject: [gem5-users] Questions on DRAM Controller model

Hello Everybody,

I am using DDR3_1600_x64. I am trying to understand the memory controller 
design and  have few doubts about it.

1) Do the memory controller has a separate  Bank request buffer (read and write 
buffer) for each bank or just a global queue?
2) Is there a scheduler per bank which arbitrates between different queue 
requests parallel with other bank schedulers?
3) Is there DRAM bus scheduler that arbitrates between different bank requests?

Thanks,
Prathap

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