[gem5-users] Switching CPU type from a checkpoint fails when using memory type dramsim2
Hello Everybody, I have created a checkpoint with cpu type 'atomic' and mem type 'dramsim2. While switching to cpu type 'detailed' from this checkpoint simulation fails with below error. Switch at curTick count:1 info: Entering event queue @ 3534903961500. Starting simulation... writing vis file to ext/dramsim2/DRAMSim2//results//DDR3_micron_32M_8B_x8_sg15/2GB.1Ch.1R.scheme2.open_page.32TQ.32CQ.RtB.pRank.vis Switched CPUS @ tick 3534903971500 switching cpus REAL SIMULATION info: Entering event queue @ 3534903971500. Starting simulation... gem5.opt: build/ARM/mem/dramsim2.cc:293: void DRAMSim2::readComplete(unsigned int, uint64_t, uint64_t): Assertion `cycle == divCeil(curTick() - startTick, wrapper.clockPeriod() * SimClock::Int::ns)' failed. Program aborted at tick 3535124958500 Aborted (core dumped) Do anyone know what went wrong? Thanks, Prathap ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Switching CPU type from a checkpoint fails when using memory type dramsim2
Hi Prathap, That’s unfortunate. Perhaps you can add some debug printouts to figure out what is going wrong in the restoring. In either case, I would suggest to use the SimpleMemory for getting to the region of interest (as it is much faster). Also, you are probably better off with the native gem5 DRAMCtrl model as it is much faster, and far more tested. Andreas From: Prathap Kolakkampadath via gem5-users gem5-users@gem5.orgmailto:gem5-users@gem5.org Reply-To: Prathap Kolakkampadath kvprat...@gmail.commailto:kvprat...@gmail.com, gem5 users mailing list gem5-users@gem5.orgmailto:gem5-users@gem5.org Date: Tuesday, 9 September 2014 18:32 To: gem5 users mailing list gem5-users@gem5.orgmailto:gem5-users@gem5.org Subject: [gem5-users] Switching CPU type from a checkpoint fails when using memory type dramsim2 Hello Everybody, I have created a checkpoint with cpu type 'atomic' and mem type 'dramsim2. While switching to cpu type 'detailed' from this checkpoint simulation fails with below error. Switch at curTick count:1 info: Entering event queue @ 3534903961500. Starting simulation... writing vis file to ext/dramsim2/DRAMSim2//results//DDR3_micron_32M_8B_x8_sg15/2GB.1Ch.1R.scheme2.open_page.32TQ.32CQ.RtB.pRank.vis Switched CPUS @ tick 3534903971500 switching cpus REAL SIMULATION info: Entering event queue @ 3534903971500. Starting simulation... gem5.opt: build/ARM/mem/dramsim2.cc:293: void DRAMSim2::readComplete(unsigned int, uint64_t, uint64_t): Assertion `cycle == divCeil(curTick() - startTick, wrapper.clockPeriod() * SimClock::Int::ns)' failed. Program aborted at tick 3535124958500 Aborted (core dumped) Do anyone know what went wrong? Thanks, Prathap -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2548782___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Questions on DRAM Controller model
Hello Andreas, Thanks for your reply. I read your ISPASS paper and got a fair understanding about the architecture. I am trying to reproduce the results, collected from running synthetic benchmarks (latency and bandwidth) on real hardware, in Simulator Environment.However, i could see variations in the results and i am trying to understand the reasons. The experiment has latency(memory non-intensive with random access) as the primary task and bandwidth(memory intensive with sequential access) as the co-runner task. On real hardware case 1 - 0 corunner : latency of the test is 74.88ns and b/w 854.74MB/s case 2 - 1 corunner : latency of the test is 225.95ns and b/w 283.24MB/s On simulator case 1 - 0 corunner : latency of the test is 76.08ns and b/w 802.25MB/s case 2 - 1 corunner : latency of the test is 93.69ns and b/w 651.57MB/s Case 1 where latency test run alone(0 corunner), the results matches on both environment. However Case 2, when run with bandwidth(1 corunner), the results varies a lot. Do you have any thoughts about this? Thanks, Prathap On Mon, Sep 8, 2014 at 1:46 PM, Andreas Hansson andreas.hans...@arm.com wrote: Hi Prathap, Have you read our ISPASS paper from last year? It’s referenced in the header file, as well as on gem5.org. 1. Yes and no. Two different buffers are used in the model are used, but they are random access, so you can treat the entries any way you want. 2. Yes and no. It’s a C++ model, so the scheduler executes in 0 time. Thus, when looking at the various requests it effectively sees all the banks. 3. Yes and no. See above. Remember that this is a model. The goal is not to be representative down to every last element of an RTL design. The goal is to be representative of a real design, and then be fast. Both of these goals are delivered upon by the model. I hope that explains it. IF there is anything in the results you do not agree with, please do say so. Thanks, Andreas From: Prathap Kolakkampadath via gem5-users gem5-users@gem5.org Reply-To: Prathap Kolakkampadath kvprat...@gmail.com, gem5 users mailing list gem5-users@gem5.org Date: Monday, 8 September 2014 18:38 To: gem5 users mailing list gem5-users@gem5.org Subject: [gem5-users] Questions on DRAM Controller model Hello Everybody, I am using DDR3_1600_x64. I am trying to understand the memory controller design and have few doubts about it. 1) Do the memory controller has a separate Bank request buffer (read and write buffer) for each bank or just a global queue? 2) Is there a scheduler per bank which arbitrates between different queue requests parallel with other bank schedulers? 3) Is there DRAM bus scheduler that arbitrates between different bank requests? Thanks, Prathap -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2548782 ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Questions on DRAM Controller model
Hi Prathap, There are many possible reasons for the discrepancy, and obviously there are many ways of building a memory controller :-). Have you configured the model to look like the actual hardware? The most obvious differences would be in terms of buffer sizes, the page policy, arbitration policy, the threshold before closing a page, the read/write switching, actual timings etc. It is also worth checking if the controller hardware treats writes the same way the model does (early responses, minimise switching). Andreas From: Prathap Kolakkampadath kvprat...@gmail.commailto:kvprat...@gmail.com Date: Tuesday, 9 September 2014 18:56 To: Andreas Hansson andreas.hans...@arm.commailto:andreas.hans...@arm.com Cc: gem5 users mailing list gem5-users@gem5.orgmailto:gem5-users@gem5.org Subject: Re: [gem5-users] Questions on DRAM Controller model Hello Andreas, Thanks for your reply. I read your ISPASS paper and got a fair understanding about the architecture. I am trying to reproduce the results, collected from running synthetic benchmarks (latency and bandwidth) on real hardware, in Simulator Environment.However, i could see variations in the results and i am trying to understand the reasons. The experiment has latency(memory non-intensive with random access) as the primary task and bandwidth(memory intensive with sequential access) as the co-runner task. On real hardware case 1 - 0 corunner : latency of the test is 74.88ns and b/w 854.74MB/s case 2 - 1 corunner : latency of the test is 225.95ns and b/w 283.24MB/s On simulator case 1 - 0 corunner : latency of the test is 76.08ns and b/w 802.25MB/s case 2 - 1 corunner : latency of the test is 93.69ns and b/w 651.57MB/s Case 1 where latency test run alone(0 corunner), the results matches on both environment. However Case 2, when run with bandwidth(1 corunner), the results varies a lot. Do you have any thoughts about this? Thanks, Prathap On Mon, Sep 8, 2014 at 1:46 PM, Andreas Hansson andreas.hans...@arm.commailto:andreas.hans...@arm.com wrote: Hi Prathap, Have you read our ISPASS paper from last year? It’s referenced in the header file, as well as on gem5.orghttp://gem5.org. 1. Yes and no. Two different buffers are used in the model are used, but they are random access, so you can treat the entries any way you want. 2. Yes and no. It’s a C++ model, so the scheduler executes in 0 time. Thus, when looking at the various requests it effectively sees all the banks. 3. Yes and no. See above. Remember that this is a model. The goal is not to be representative down to every last element of an RTL design. The goal is to be representative of a real design, and then be fast. Both of these goals are delivered upon by the model. I hope that explains it. IF there is anything in the results you do not agree with, please do say so. Thanks, Andreas From: Prathap Kolakkampadath via gem5-users gem5-users@gem5.orgmailto:gem5-users@gem5.org Reply-To: Prathap Kolakkampadath kvprat...@gmail.commailto:kvprat...@gmail.com, gem5 users mailing list gem5-users@gem5.orgmailto:gem5-users@gem5.org Date: Monday, 8 September 2014 18:38 To: gem5 users mailing list gem5-users@gem5.orgmailto:gem5-users@gem5.org Subject: [gem5-users] Questions on DRAM Controller model Hello Everybody, I am using DDR3_1600_x64. I am trying to understand the memory controller design and have few doubts about it. 1) Do the memory controller has a separate Bank request buffer (read and write buffer) for each bank or just a global queue? 2) Is there a scheduler per bank which arbitrates between different queue requests parallel with other bank schedulers? 3) Is there DRAM bus scheduler that arbitrates between different bank requests? Thanks, Prathap -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2548782 -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2548782___ gem5-users mailing list
