[gem5-users] Question on maximum number of outstanding DRAM memory requests that can be generated by a core.
Hello Users, Is the maximum number of outstanding DRAM memory requests that can be generated by a core at a time is limited by number of MSHRs in its private cache? For example, In a 4 core system configuration, each core has a private L1 cache with 6 MSHRs each. The systems Last Level cache has 24 MSHRs, which is shared by all the four cores. If a memory intensive program running core 0 generates many L2 data cache read request misses, then the number of outstanding memory requests it can generate at a time is limited by number of L1 MSHRs or L2 MSHRs? Thanks and Regards, Prathap Kumar Valsan ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Communication monitor is not connected on both sides
Dear all I need to trace the address and the data exchanged between CPU and L1 data cache - in SE mode on X86, classical memory - and I have modified the CacheConfig.py to add CommMonitor in the following way: After the line about setting the cache line size (system.cache_line_size = options.cacheline_size) I have added these two lines: system.icachemonitor = CommMonitor(trace_file='Icachecontent.ptrc') system.dcachemonitor = CommMonitor(trace_file='DCache_content.ptrc',trace_enable=True) Then after: if buildEnv['TARGET_ISA'] == 'x86': I have commented this line: system.cpu[i].addPrivateSplitL1Caches(icache, dcache, PageTableWalkerCache(), PageTableWalkerCache()) and instead, inserted these three lines: system.dcachemonitor.master = dcache.cpu_side system.icachemonitor.master = icache.cpu_side system.cpu[i].addPrivateSplitL1Caches(system.icachemonitor.slave, system.dcachemonitor.slave, PageTableWalkerCache(), PageTableWalkerCache()) Then I have compiled using: scons build/X86/gem5.opt And then run: build/X86/gem5.opt configs/example/se.py -c tests/test-progs/hello/bin/x86/linux/hello As a result, I get in CacheConfig.py a: SyntaxWarning: Import * only allowed at module level def config_cache(options, system) : fatal: Communication monitor is not connected on both sides @ tick 0 [init:build/X86/mem/comm_monitor.cc, line 144] Memory Usage: 627592 KBytes Program aborted at tick 0 Aborted (core dumped) Then I saw in email threads that some people have modified BaseCPU.py, so keeping the changes in CacheConfig.py, I tried that as well. In the following section in BaseCPU.py: def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): self.icache = ic self.dcache = dc self.icache_port = ic.cpu_side I commented the following line: self.dcache_port = dc.cpu_side and added these lines instead: self.L1MONITOR = CommMonitor(trace_file=L1.txt) self.dcache_port = self.L1MONITOR.slave self.L1MONITOR.master = dc.cpu_side After compiling and running in the same way as above, I do not get the warning message anymore, but the fatal error still exists: fatal: Communication monitor is not connected on both sides @ tick 0 [init:build/X86/mem/comm_monitor.cc, line 144] Memory Usage: 627564 KBytes Program aborted at tick 0 Aborted (core dumped) Actually, it is not clear to me which file I should modify: BaseCPU.py or CacheConfig.py or both. And I would really like to know how I can get rid of this fatal error and finally see the trace. I would appreciate any help. Azadeh ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Pause Resume Simulation
Hi English isn’t myfirst language, so please excuse any mistakes. I am trying to use theGEM5 to take stats.txt file and create file input for McPAT. I use ARM multi-core architecture. I want to simulate multitask benchmark thatconcurrently runs on multi-core processor without scheduler algorithm(i.e., SEmode). Based on my algorithm, i need to stop GEM5 simulation in each timeinterval(e.g., few millisecond that this time is execuation time of core(s)) and pass GEM5 result(stats.txt) to the McPAT powersimulator and compute power consumptions of each core individually. Then after computation of power consumption, my algorithm changesfrequency-voltage setting of each core and passes this new setting to GEM5 andcontinue GEM5 simulation and repeat this steps for next time slot. Is this possible? Best, Hadi ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] interconnection network between l1 and l2
Dear Jafari, You are able to determine l2 nodes from other nodes by considering their types. The type of l2 nodes are l2cache_controller. Regards, On Jan 18, 2015 8:37 PM, Bahareh Jafari via gem5-users gem5-users@gem5.org wrote: Hi I am implementing my topology .. in my topology ,each tile composed of CPU,Router, L1 and L2 cache memory . Now وhow do i implement connections between cache L1, L2 to the network and router interconnects that each node has its own CPU and caches? ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Communication monitor is not connected on both sides
Hi Azadeh, It should not be too difficult. Besides adding '—caches' command line, here is all you have to do to trace the d-side. Note that the trace is in a binary format (and not ASCII). Andreas diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -52,6 +52,7 @@ from ExeTracer import ExeTracer from MemObject import MemObject from ClockDomain import * +from CommMonitor import CommMonitor default_tracer = ExeTracer() @@ -267,7 +268,9 @@ self.icache = ic self.dcache = dc self.icache_port = ic.cpu_side -self.dcache_port = dc.cpu_side +self.dmon = CommMonitor(trace_enable=True) +self.dcache_port = self.dmon.slave +self.dmon.master = dc.cpu_side self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] if buildEnv['TARGET_ISA'] in ['x86', 'arm']: if iwc and dwc: From: Azadeh Shirvanian via gem5-users gem5-users@gem5.orgmailto:gem5-users@gem5.org Reply-To: Azadeh Shirvanian azadeh.shirvan...@gmail.commailto:azadeh.shirvan...@gmail.com, gem5 users mailing list gem5-users@gem5.orgmailto:gem5-users@gem5.org Date: Sunday, 18 January 2015 14:46 To: gem5-users@gem5.orgmailto:gem5-users@gem5.org gem5-users@gem5.orgmailto:gem5-users@gem5.org Subject: [gem5-users] Communication monitor is not connected on both sides Dear all I need to trace the address and the data exchanged between CPU and L1 data cache - in SE mode on X86, classical memory - and I have modified the CacheConfig.py to add CommMonitor in the following way: After the line about setting the cache line size (system.cache_line_size = options.cacheline_size) I have added these two lines: system.icachemonitor = CommMonitor(trace_file='Icachecontent.ptrc') system.dcachemonitor = CommMonitor(trace_file='DCache_content.ptrc',trace_enable=True) Then after: if buildEnv['TARGET_ISA'] == 'x86': I have commented this line: system.cpu[i].addPrivateSplitL1Caches(icache, dcache, PageTableWalkerCache(), PageTableWalkerCache()) and instead, inserted these three lines: system.dcachemonitor.master = dcache.cpu_side system.icachemonitor.master = icache.cpu_side system.cpu[i].addPrivateSplitL1Caches(system.icachemonitor.slave, system.dcachemonitor.slave, PageTableWalkerCache(), PageTableWalkerCache()) Then I have compiled using: scons build/X86/gem5.opt And then run: build/X86/gem5.opt configs/example/se.py -c tests/test-progs/hello/bin/x86/linux/hello As a result, I get in CacheConfig.py a: SyntaxWarning: Import * only allowed at module level def config_cache(options, system) : fatal: Communication monitor is not connected on both sides @ tick 0 [init:build/X86/mem/comm_monitor.cc, line 144] Memory Usage: 627592 KBytes Program aborted at tick 0 Aborted (core dumped) Then I saw in email threads that some people have modified BaseCPU.py, so keeping the changes in CacheConfig.py, I tried that as well. In the following section in BaseCPU.py: def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): self.icache = ic self.dcache = dc self.icache_port = ic.cpu_side I commented the following line: self.dcache_port = dc.cpu_side and added these lines instead: self.L1MONITOR = CommMonitor(trace_file=L1.txt) self.dcache_port = self.L1MONITOR.slave self.L1MONITOR.master = dc.cpu_side After compiling and running in the same way as above, I do not get the warning message anymore, but the fatal error still exists: fatal: Communication monitor is not connected on both sides @ tick 0 [init:build/X86/mem/comm_monitor.cc, line 144] Memory Usage: 627564 KBytes Program aborted at tick 0 Aborted (core dumped) Actually, it is not clear to me which file I should modify: BaseCPU.py or CacheConfig.py or both. And I would really like to know how I can get rid of this fatal error and finally see the trace. I would appreciate any help. Azadeh -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2548782 ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
