Re: [gem5-users] Dynamic frequency change

2015-06-18 Thread Andreas Hansson
Hi Simone,

The method does not exist in Python. Remember that essential all objects in 
gem5 have both a Python object (used for setting parameters mostly), and a C++ 
object (actually involved in the simulation).

In general you should either use full-system and leave the DVFS to the OS (I 
would say this is the most sensible), or use a subclass of the DVFSHandler 
where you implement the decision making in hardware.

Good luck.

Andreas

From: Simone Corbetta 
simone.corbe...@gmail.commailto:simone.corbe...@gmail.com
Reply-To: gem5 users mailing list 
gem5-users@gem5.orgmailto:gem5-users@gem5.org
Date: Thursday, 18 June 2015 00:04
To: gem5-users@gem5.orgmailto:gem5-users@gem5.org 
gem5-users@gem5.orgmailto:gem5-users@gem5.org
Subject: [gem5-users] Dynamic frequency change

Dear all,

I'm trying to dynamically change the clock frequency, and I noticed that the 
SrcClockDomain object has a clockPeriod(Tick) method that automatically 
forwards its changes to the children objects (as per the method documentation). 
Thus, I included in the Simulate.py script, within the repeatSwitch() method 
the following line (at appropriate point):

testsys.cpu_clk_domain.clockPeriod(4000)

However, while executing Python complains that

Traceback (most recent call last):
  File string, line 1, in module
  File /home/imec/gem5/gem5/src/python/m5/main.py, line 388, in main
exec filecode in scope
  File ../configs/example/se.py, line 278, in module
Simulation.run(options, root, system, FutureClass)
  File /home/imec/gem5/gem5/configs/common/Simulation.py, line 728, in run
maxtick, options.repeat_switch)
  File /home/imec/gem5/gem5/configs/common/Simulation.py, line 451, in 
repeatSwitch
testsys.cpu_clk_domain.clockPeriod(4000)
  File /home/imec/gem5/gem5/src/python/m5/SimObject.py, line 1103, in 
__getattr__
raise AttributeError, err_string
AttributeError: object 'SrcClockDomain' has no attribute 'clockPeriod'

while it is clear that clockPeriod is present in the SrClockDomain object.

Am I missing somethng? How to fix this?

Thanks
Best regards

Simone

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Re: [gem5-users] Physical address too long!!!!

2015-06-18 Thread Andreas Hansson
Hi Kassan,

Perhaps I have misunderstood your question… Why on earth would the address be 
in the range [0 : 64 kByte] ? Just because the cache is small does not mean it 
holds addresses in any specific range.

Andreas

From: kassan unda kassanu...@gmail.commailto:kassanu...@gmail.com
Reply-To: gem5 users mailing list 
gem5-users@gem5.orgmailto:gem5-users@gem5.org
Date: Wednesday, 17 June 2015 17:18
To: gem5 users mailing list gem5-users@gem5.orgmailto:gem5-users@gem5.org
Subject: [gem5-users] Physical address too long

Hi all,

I am trying to print the physical address of the data read write from data 
cache.
I am printing the physical address using pkt-getAddr() in cache_impl.hh address
inside the following function
templateclass TagStore
bool
CacheTagStore::access(PacketPtr pkt, BlkType *blk,
Cycles lat, PacketList writebacks

I am printing address like 1244784 (after converting hex to decimal). The 
dcache is only 64kb. Can anyone point out whats wrong. Appreciate your help!!
Regards,
Kassan Unda
Doctoral Candidate
Computer Engineering
Missouri ST (Formerly University of Missouri Rolla)
WebPage: http://web.mst.edu/~kutx9

Do not go where the path may lead, go instead where there is no path  and 
leave a trail. Ralph Waldo Emerson

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medium. Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered 
in England  Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, 
Registered in England  Wales, Company No: 2548782
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Re: [gem5-users] ARM KVM support

2015-06-18 Thread Andreas Hansson
Hi Junaid,

That was a long time ago…

The aarch64 KVM cpu model should be working just fine (in full-system mode).

Andreas

From: Junaid Shuja 
junaidsh...@siswa.um.edu.mymailto:junaidsh...@siswa.um.edu.my
Reply-To: gem5 users mailing list 
gem5-users@gem5.orgmailto:gem5-users@gem5.org
Date: Thursday, 18 June 2015 00:33
To: gem5-users@gem5.orgmailto:gem5-users@gem5.org 
gem5-users@gem5.orgmailto:gem5-users@gem5.org
Subject: [gem5-users] ARM KVM support

Hi,
In the gem5 tutorial, it is stated that KVM ARM support is under work.
http://gem5.org/dist/tutorials/hipeac2012/gem5_hipeac.pdf

Can you please specify the current status of this work?
--
Junaid Shuja
WHA130039
PhD Student, FSKTM
University of Malaya

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in England  Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, 
Registered in England  Wales, Company No: 2548782
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Re: [gem5-users] Physical address too long!!!!

2015-06-18 Thread kassan unda
Yes I know. What I am trying to do is to print the exact location of the
dcache being read from not the physical address of the data stored in the
memory. I meant that since the DCache is only 64 kb the address of this
physical location in the dcache cant be too long. So I am guessing this is
not the right way to do it. Can you please point me to the correct
direction. Thx in advance.

*Regards,*
*Kassan Unda*

*Doctoral Candidate*
*Computer Engineering*
*Missouri ST (Formerly University of Missouri Rolla)*
*WebPage: http://web.mst.edu/~kutx9 http://web.mst.edu/~kutx9*

*Do not go where the path may lead, go instead where there is no path  and
leave a trail.* Ralph Waldo Emerson


On Thu, Jun 18, 2015 at 5:15 AM, Andreas Hansson andreas.hans...@arm.com
wrote:

  Hi Kassan,

  Perhaps I have misunderstood your question… Why on earth would the
 address be in the range [0 : 64 kByte] ? Just because the cache is small
 does not mean it holds addresses in any specific range.

  Andreas

   From: kassan unda kassanu...@gmail.com
 Reply-To: gem5 users mailing list gem5-users@gem5.org
 Date: Wednesday, 17 June 2015 17:18
 To: gem5 users mailing list gem5-users@gem5.org
 Subject: [gem5-users] Physical address too long

   Hi all,

  I am trying to print the physical address of the data read write from
 data cache.
  I am printing the physical address using pkt-getAddr() in cache_impl.hh
 address
  inside the following function
 templateclass TagStore
 bool
 CacheTagStore::access(PacketPtr pkt, BlkType *blk,
 Cycles lat, PacketList writebacks

  I am printing address like 1244784 (after converting hex to decimal).
 The dcache is only 64kb. Can anyone point out whats wrong. Appreciate your
 help!!
*Regards,*
 *Kassan Unda*

 *Doctoral Candidate *
 *Computer Engineering*
 *Missouri ST (Formerly University of Missouri Rolla)*
 *WebPage: http://web.mst.edu/~kutx9 http://web.mst.edu/~kutx9*

  *Do not go where the path may lead, go instead where there is no path
 and leave a trail.* Ralph Waldo Emerson


 -- IMPORTANT NOTICE: The contents of this email and any attachments are
 confidential and may also be privileged. If you are not the intended
 recipient, please notify the sender immediately and do not disclose the
 contents to any other person, use it for any purpose, or store or copy the
 information in any medium. Thank you.

 ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
 Registered in England  Wales, Company No: 2557590
 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
 Registered in England  Wales, Company No: 2548782

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Re: [gem5-users] SOC design questions

2015-06-18 Thread chelin
Hi Andreas

Thank you very much for your help. One more question, if I use the classic 
memory system, will I be able to write my own bus controller or protocol?

Best,
Vivian


Hi Vivian,

I would suggest your best option is to stick with the classic (non-Ruby)
memory system, and use the CommMonitor for packet tracing.

Andreas

On 16/06/2015 20:51, chelin chelin...@gmail.com 
mailto:chelin...@gmail.com wrote:

 HI there
 
 I'm trying to simulate a post silicon SOC validation by creating my own
 platform and monitor the ports output. I just started learning Gem5 so if
 some of you can help me answer couple questions I would really appreciate
 it.
 
 1. Can I create my own interconnection object, like my own bus with
 2. If yes, can I create my own protocol for this bus. I know that Ruby
 seems to be very powerful, but there is not too much examples online, can
 you give me some tips on where to find those documentations.
 3. For ruby, I want to connect it to CPUs and some other peripherals,
 does the protocol also cover the peripheral part?
 4. According to the Ruby documentation, it only use ports for CPu and
 devices, inside the RUby, the MessageBuffer is used instead. Is there
 anyway for me to monitor the information sent in between with the port
 content. I try to figure out the structure inside ruby but failed. and
 when I use debug-flags=Ruby, the ports name they provide is just numbers,
 so I don't really know which content send the message.
 
 Thanks.
 Best,
 Vivian
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[gem5-users] How to model a die-stacked DRAM?

2015-06-18 Thread Prathap Kolakkampadath
Hello Users,

Has anyone tried to model a die-stacked DRAM using gem5's classic memory
system?
I read a couple of papers, in which they model die-stacked DRAM using
DRAMSim2.
How difficult it would be to model and any pointers on where to start?

Thanks,
Prathap Kumar Valsan
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[gem5-users] Dynamic frequency change

2015-06-18 Thread Simone Corbetta
Dear all,

I'm trying to dynamically change the clock frequency, and I noticed that
the SrcClockDomain object has a clockPeriod(Tick) method that automatically
forwards its changes to the children objects (as per the method
documentation). Thus, I included in the Simulate.py script, within the
repeatSwitch() method the following line (at appropriate point):

testsys.cpu_clk_domain.clockPeriod(4000)

However, while executing Python complains that

Traceback (most recent call last):
  File string, line 1, in module
  File /home/imec/gem5/gem5/src/python/m5/main.py, line 388, in main
exec filecode in scope
  File ../configs/example/se.py, line 278, in module
Simulation.run(options, root, system, FutureClass)
  File /home/imec/gem5/gem5/configs/common/Simulation.py, line 728, in run
maxtick, options.repeat_switch)
  File /home/imec/gem5/gem5/configs/common/Simulation.py, line 451, in
repeatSwitch
testsys.cpu_clk_domain.clockPeriod(4000)
  File /home/imec/gem5/gem5/src/python/m5/SimObject.py, line 1103, in
__getattr__
raise AttributeError, err_string
AttributeError: object 'SrcClockDomain' has no attribute 'clockPeriod'

while it is clear that clockPeriod is present in the SrClockDomain object.

Am I missing somethng? How to fix this?

Thanks
Best regards

Simone
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[gem5-users] ARM KVM support

2015-06-18 Thread Junaid Shuja
Hi,
In the gem5 tutorial, it is stated that KVM ARM support is under work.
http://gem5.org/dist/tutorials/hipeac2012/gem5_hipeac.pdf

Can you please specify the current status of this work?
-- 
Junaid Shuja
WHA130039
PhD Student, FSKTM
University of Malaya
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[gem5-users] Range of Address in a Large Memory System

2015-06-18 Thread Majid Jalili
Hi,

I run gem5 in SE mode with following command for SPEC CPU 2006 workloads.

./build/ALPHA/gem5.opt  ./configs/example/cmp.py -b
libq,libq,libq,libq,libq,libq,libq,libq --mem-size=16GB
--mem-type=simple_mem -n 8 --caches --l2cache --cpu-type=atomic
--cpu-clock=4GHz --l2_size=4MB  --cacheline_size=64 --l1i_size=64kB
--l1d_size=64kB --l2_assoc=8 -I 10

I determined the maximum address received in the memory system for all my
applications (mcf, libq, namd, perl, gcc, milc, omntp,...). I saw lbm
accessed the largest address among all (3435354624) which is a 32-bit
address.

Why my applications did not use at least the half of the 16-GB memory
system?

I reduced the mem_size to 4GB and every thing is OK..
I checked the workload-to-CPU assignments. They assigned to the different
CPUs with different objects.
--Assigning---
Process( 0 )= orphan lbm
system.cpu[ 0 ].workload = [Mybench.lbm object at 0x3f2fa50]
Process( 1 )= orphan lbm
system.cpu[ 1 ].workload = [Mybench.lbm object at 0x4077e10]
Process( 2 )= orphan lbm
system.cpu[ 2 ].workload = [Mybench.lbm object at 0x4077ed0]
Process( 3 )= orphan lbm
system.cpu[ 3 ].workload = [Mybench.lbm object at 0x4077f90]
Process( 4 )= orphan lbm
system.cpu[ 4 ].workload = [Mybench.lbm object at 0x4081090]
Process( 5 )= orphan lbm
system.cpu[ 5 ].workload = [Mybench.lbm object at 0x4081150]
Process( 6 )= orphan lbm
system.cpu[ 6 ].workload = [Mybench.lbm object at 0x4081210]
Process( 7 )= orphan lbm
system.cpu[ 7 ].workload = [Mybench.lbm object at 0x40812d0]
workloads assigned to cpus

I knew that some SPEC applications have a very large working sets. What is
wrong with my system?
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