Re: [gem5-users] Stat of type Formula getting value from function
No, it should only be calculated at the end. > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Stat of type Formula getting value from function
Hi Varun, Will this stat will be calculated on every tick? On Fri, Nov 29, 2019 at 7:01 PM Victor Kariofillis wrote: > Hi, > > I have created a Stat of type Formula. Since the formula is complicated, > instead of having it in the regStats file, I want to call another function > that returns the proper value. The code would be something like this. > > zeroPercentage.flags(total); > zeroPercentage = calcZeroPercentage(); > > The calcZeroPercentage is a typical function in the file. The numbers that > I'm crunching to get the value that I want are not stats. Would something > like this be possible? In the gem5 documentation statistics page, it states > that if the variables are not stats they should be qualified with constant. > > "If bar or num are regular variables, then they must be qualified with > constant(bar)." > > Is this true for this case as well? > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Stat of type Formula getting value from function
Hi, I have created a Stat of type Formula. Since the formula is complicated, instead of having it in the regStats file, I want to call another function that returns the proper value. The code would be something like this. zeroPercentage.flags(total); zeroPercentage = calcZeroPercentage(); The calcZeroPercentage is a typical function in the file. The numbers that I'm crunching to get the value that I want are not stats. Would something like this be possible? In the gem5 documentation statistics page, it states that if the variables are not stats they should be qualified with constant. "If bar or num are regular variables, then they must be qualified with constant(bar)." Is this true for this case as well? ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] x86 O3 SMT: Int port not connected to anything
Hi everyone, This is an update on the issue I posted earlier. It seems that when using SMT with x86, the se.py configuration file defines the connections of PIO and interrupt ports to the memory bus only for the first SMT core. I got around this issue by modifying se.py as follows (I added the last three lines in the code below), assuming there are two SMT cores in total: if buildEnv['TARGET_ISA'] == 'x86': system.cpu[i].interrupts[0].pio = ruby_port.master system.cpu[i].interrupts[0].int_master = ruby_port.slave system.cpu[i].interrupts[0].int_slave = ruby_port.master system.cpu[i].interrupts[1].pio = ruby_port.master system.cpu[i].interrupts[1].int_master = ruby_port.slave system.cpu[i].interrupts[1].int_slave = ruby_port.master Adding such connections for the classic caches seems to be harder, so I did it for the ruby model. I then ran gem5 and got this new error: gem5.opt: build/X86/cpu/o3/rename_map.cc:82: SimpleRenameMap::RenameInfo SimpleRenameMap::rename(const RegId&): Assertion `prev_reg->isZeroReg()' failed. This problem of the zero register has been discussed a long time ago in the gem5 mailing list: https://www.mail-archive.com/gem5-users@gem5.org/msg04271.html It seems that a patch was suggested for it. Since this zero register issue still persists, I wonder if it has been reviewed/applied. Thanks, Hossein On Wed, Oct 30, 2019 at 3:42 PM Hossein Golestani wrote: > Hello, > > When I use an O3 SMT core with the x86 ISA in gem5 SE mode, I get the > following error: > panic: panic condition !intMasterPort.isConnected() occurred: Int port not > connected to anything! > > The command I'm using is: > $GEM5/build/X86/gem5.opt $GEM5/configs/example/se.py --cmd="./test;./test" > --cpu-type=DerivO3CPU --smt --caches --l2cache > > (When I use only one workload, i.e., --cmd="./test", there will be no > error.) > > The only occurrence of the interrupt port in se.py is the following: > if buildEnv['TARGET_ISA'] == 'x86': > system.cpu[i].interrupts[0].pio = ruby_port.master > system.cpu[i].interrupts[0].int_master = ruby_port.slave > system.cpu[i].interrupts[0].int_slave = ruby_port.master > > So, I also used the ruby memory model (--ruby). But I still get the same > error. > > I would really appreciate any help on this issue. > > Thanks, > Hossein > > > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Running bare-metal RISCV simulations ...
Dear Anuj, I am not sure what you mean by "using bare-metal RISCV ISA support". In case you are referencing to the Diploma Thesis by Robert Scheffel [1], you can find his work in a fork of gem5 [2]. Unfortunately, we never had the time to bring those changes to the mainline gem5. Let me know if you have any problems with setting this up. I did not follow the development in mainline gem5 and I am not sure what the current status of RISC-V support is there. Maybe what you ask is also already supported there. [1] https://cfaed.tu-dresden.de/publications?pubId=2203 [2] https://github.com/tud-ccc/gem5-riscv-ccc Best, Chrisitan Anuj Falcon writes: > What is the exact procedure to execute a binary with TimingSimpleCPU using > bare-metal RISCV ISA support ? (Without system call support) > -- > - > J ANUJ > - > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
