[gem5-users] Run Apk files on Gem5

[ABD ALRHMAN ABO ALKHEEL]

Hello Everyone, I wanna run apk files on gem5 with arm. I don’t have any idea 
about that. Any help would be appreciated. Best Regards
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Re: [gem5-users] Simulation does not stop, SE mode, 2 cpus, DerivO3CPU, ruby memory

[Abhishek Singh]

Hi Arun,

My bad the issue is still there

Best regards,

Abhishek


On Mon, Mar 2, 2020 at 12:57 AM Abhishek Singh <
abhishek.singh199...@gmail.com> wrote:

> Hi Arun,
>
> I tested gem5_19 with classic cache x86 with O3CPU, both smt and multicore
> simulations are working
>
> Best regards,
>
> Abhishek
>
>
> On Mon, Mar 2, 2020 at 12:34 AM Arun Kavumkal 
> wrote:
>
>> Hi Ciro
>> I was debugging the X86, mutlticore issue as suggested by you.
>> I could see that the simulation exits as expected by changing
>>  * if (activeContexts ==0)*
>> at 
>> https://github.com/gem5/gem5/blob/9fc9c67b4242c03f165951775be5cd0812f2a705/src/sim/syscall_emul.cc#L212
>> to *if (activeContexts == 1).*
>> This change is done as per the commit
>> https://github.com/gem5/gem5/commit/bae0edb0d26dc6c4738855cf38e9a6a109ae8003
>> I want to ask, whether this change ie  *if (activeContexts ==0) *was a
>> bug or intentional for some other reason?
>>
>> Thanks
>> KP Arun
>>
>> On Tue, Feb 18, 2020 at 11:45 PM Abhishek Singh <
>> abhishek.singh199...@gmail.com> wrote:
>>
>>> Hi,
>>>
>>> A ticket is already opened about this at Jira
>>> https://gem5.atlassian.net/projects/GEM5/issues
>>>
>>> Arun: This repo (https://gem5.googlesource.com/amd/gem5/) will solve
>>> your problem
>>>
>>>
>>> On Tue, Feb 18, 2020 at 1:06 PM Ciro Santilli 
>>> wrote:
>>>
 Hi Arun,

 "I started using ruby memory model after reading from gem5 email
 archive that classic memory does not work with multicore DerivO3CPU.":
 I didn't know this, where was this mentioned? I have just run an ARM
 pthread hello world on DerivO3CPU 2 cores and it worked on master.

 I reproduce your problem on X86 DerivO3CPU classic but not ARM
 DerivO3CPU. But a pthread hello world (single binary under --cmd that
 spanws threads) with 2 CPUs worked, I don't know the cause. If no one
 knows about this issue, you need to try and debug it :-)

 I would also open a ticket for this bug at
 https://gem5.atlassian.net/browse/GEM5 and move all discussion there.




 On Tue, Feb 18, 2020 at 4:43 AM Arun Kavumkal 
 wrote:
 >
 > Hi,
 > I am trying to run gem5 in SE mode with number of cpus 2, cpu type
 DerivO3CPU, and ruby memory model using following command, but the
 simulation does not stop even after results are produced , ie "Hello
 world!" is printed to stdout
 >
 > build/X86_MESI_Three_Level/gem5.opt configs/example/se.py -n 2 --ruby
 --cpu-type=DerivO3CPU -c
 'tests/test-progs/hello/bin/x86/linux/hello;tests/test-progs/hello/bin/x86/linux/hello'
 >
 > I started using ruby memory model after reading from gem5 email
 archive that classic memory does not work with multicore DerivO3CPU.
 >
 > Thanks
 > Arun KP
 > ___
 > gem5-users mailing list
 > gem5-users@gem5.org
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 ___
 gem5-users mailing list
 gem5-users@gem5.org
 http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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Re: [gem5-users] Simulation does not stop, SE mode, 2 cpus, DerivO3CPU, ruby memory

[Abhishek Singh]

Hi Arun,

I tested gem5_19 with classic cache x86 with O3CPU, both smt and multicore
simulations are working

Best regards,

Abhishek


On Mon, Mar 2, 2020 at 12:34 AM Arun Kavumkal 
wrote:

> Hi Ciro
> I was debugging the X86, mutlticore issue as suggested by you.
> I could see that the simulation exits as expected by changing
>  * if (activeContexts ==0)*
> at 
> https://github.com/gem5/gem5/blob/9fc9c67b4242c03f165951775be5cd0812f2a705/src/sim/syscall_emul.cc#L212
> to *if (activeContexts == 1).*
> This change is done as per the commit
> https://github.com/gem5/gem5/commit/bae0edb0d26dc6c4738855cf38e9a6a109ae8003
> I want to ask, whether this change ie  *if (activeContexts ==0) *was a
> bug or intentional for some other reason?
>
> Thanks
> KP Arun
>
> On Tue, Feb 18, 2020 at 11:45 PM Abhishek Singh <
> abhishek.singh199...@gmail.com> wrote:
>
>> Hi,
>>
>> A ticket is already opened about this at Jira
>> https://gem5.atlassian.net/projects/GEM5/issues
>>
>> Arun: This repo (https://gem5.googlesource.com/amd/gem5/) will solve
>> your problem
>>
>>
>> On Tue, Feb 18, 2020 at 1:06 PM Ciro Santilli 
>> wrote:
>>
>>> Hi Arun,
>>>
>>> "I started using ruby memory model after reading from gem5 email
>>> archive that classic memory does not work with multicore DerivO3CPU.":
>>> I didn't know this, where was this mentioned? I have just run an ARM
>>> pthread hello world on DerivO3CPU 2 cores and it worked on master.
>>>
>>> I reproduce your problem on X86 DerivO3CPU classic but not ARM
>>> DerivO3CPU. But a pthread hello world (single binary under --cmd that
>>> spanws threads) with 2 CPUs worked, I don't know the cause. If no one
>>> knows about this issue, you need to try and debug it :-)
>>>
>>> I would also open a ticket for this bug at
>>> https://gem5.atlassian.net/browse/GEM5 and move all discussion there.
>>>
>>>
>>>
>>>
>>> On Tue, Feb 18, 2020 at 4:43 AM Arun Kavumkal 
>>> wrote:
>>> >
>>> > Hi,
>>> > I am trying to run gem5 in SE mode with number of cpus 2, cpu type
>>> DerivO3CPU, and ruby memory model using following command, but the
>>> simulation does not stop even after results are produced , ie "Hello
>>> world!" is printed to stdout
>>> >
>>> > build/X86_MESI_Three_Level/gem5.opt configs/example/se.py -n 2 --ruby
>>> --cpu-type=DerivO3CPU -c
>>> 'tests/test-progs/hello/bin/x86/linux/hello;tests/test-progs/hello/bin/x86/linux/hello'
>>> >
>>> > I started using ruby memory model after reading from gem5 email
>>> archive that classic memory does not work with multicore DerivO3CPU.
>>> >
>>> > Thanks
>>> > Arun KP
>>> > ___
>>> > gem5-users mailing list
>>> > gem5-users@gem5.org
>>> > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>> ___
>>> gem5-users mailing list
>>> gem5-users@gem5.org
>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>
>>
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Re: [gem5-users] Simulation does not stop, SE mode, 2 cpus, DerivO3CPU, ruby memory

[Arun Kavumkal]

Hi Ciro
I was debugging the X86, mutlticore issue as suggested by you.
I could see that the simulation exits as expected by changing
 * if (activeContexts ==0)*
at 
https://github.com/gem5/gem5/blob/9fc9c67b4242c03f165951775be5cd0812f2a705/src/sim/syscall_emul.cc#L212
to *if (activeContexts == 1).*
This change is done as per the commit
https://github.com/gem5/gem5/commit/bae0edb0d26dc6c4738855cf38e9a6a109ae8003
I want to ask, whether this change ie  *if (activeContexts ==0) *was a bug
or intentional for some other reason?

Thanks
KP Arun

On Tue, Feb 18, 2020 at 11:45 PM Abhishek Singh <
abhishek.singh199...@gmail.com> wrote:

> Hi,
>
> A ticket is already opened about this at Jira
> https://gem5.atlassian.net/projects/GEM5/issues
>
> Arun: This repo (https://gem5.googlesource.com/amd/gem5/) will solve
> your problem
>
>
> On Tue, Feb 18, 2020 at 1:06 PM Ciro Santilli 
> wrote:
>
>> Hi Arun,
>>
>> "I started using ruby memory model after reading from gem5 email
>> archive that classic memory does not work with multicore DerivO3CPU.":
>> I didn't know this, where was this mentioned? I have just run an ARM
>> pthread hello world on DerivO3CPU 2 cores and it worked on master.
>>
>> I reproduce your problem on X86 DerivO3CPU classic but not ARM
>> DerivO3CPU. But a pthread hello world (single binary under --cmd that
>> spanws threads) with 2 CPUs worked, I don't know the cause. If no one
>> knows about this issue, you need to try and debug it :-)
>>
>> I would also open a ticket for this bug at
>> https://gem5.atlassian.net/browse/GEM5 and move all discussion there.
>>
>>
>>
>>
>> On Tue, Feb 18, 2020 at 4:43 AM Arun Kavumkal 
>> wrote:
>> >
>> > Hi,
>> > I am trying to run gem5 in SE mode with number of cpus 2, cpu type
>> DerivO3CPU, and ruby memory model using following command, but the
>> simulation does not stop even after results are produced , ie "Hello
>> world!" is printed to stdout
>> >
>> > build/X86_MESI_Three_Level/gem5.opt configs/example/se.py -n 2 --ruby
>> --cpu-type=DerivO3CPU -c
>> 'tests/test-progs/hello/bin/x86/linux/hello;tests/test-progs/hello/bin/x86/linux/hello'
>> >
>> > I started using ruby memory model after reading from gem5 email archive
>> that classic memory does not work with multicore DerivO3CPU.
>> >
>> > Thanks
>> > Arun KP
>> > ___
>> > gem5-users mailing list
>> > gem5-users@gem5.org
>> > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>> ___
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>> gem5-users@gem5.org
>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
>
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Re: [gem5-users] Question about CacheLoad/StorePorts

[Abhishek Singh]

Hi,

The configuration in source code are not decided depending on any specific
architecture.
One needs to change it depending on what architecture they are targeting.
If you read papers who have used gem5, they always target a particular
architecture (skylake, coffee lake, or any and or arm, etc) and change
parameters accordingly

On Sun, Mar 1, 2020 at 5:06 PM Chang Hyun Park 
wrote:

> Hello all,
>
> I ran into a question while looking through the `cacheLoadPorts` and
> `cacheStorePorts` variable in `src/cpu/o3/O3CPU.py`[1].
>
> The default values are set to 200, and a search through GitHub shows
> that this default value seems to be always used. (At least for the
> provided example configurations)
>
> My question is doesn't this value look way too large?
> It is known that the Intel Skylake microarchitecture has two loads and
> one store ports.[2]
>
> Should we change the cacheLoadPorts and cacheStorePorts to two and
> one, respectively for more accurate results?
>
> Thank you,
> Chang Hyun Park
>
> [1]
> https://github.com/gem5/gem5/blob/ca1d09608e52f6ca8db8c2288b292731c4cee739/src/cpu/o3/O3CPU.py
> [2]
> https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(client)#Scheduler_Ports_.26_Execution_Units
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[gem5-users] Question about CacheLoad/StorePorts

[Chang Hyun Park]

Hello all,

I ran into a question while looking through the `cacheLoadPorts` and
`cacheStorePorts` variable in `src/cpu/o3/O3CPU.py`[1].

The default values are set to 200, and a search through GitHub shows
that this default value seems to be always used. (At least for the
provided example configurations)

My question is doesn't this value look way too large?
It is known that the Intel Skylake microarchitecture has two loads and
one store ports.[2]

Should we change the cacheLoadPorts and cacheStorePorts to two and
one, respectively for more accurate results?

Thank you,
Chang Hyun Park

[1] 
https://github.com/gem5/gem5/blob/ca1d09608e52f6ca8db8c2288b292731c4cee739/src/cpu/o3/O3CPU.py
[2] 
https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(client)#Scheduler_Ports_.26_Execution_Units
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Re: [gem5-users] RISC-V non-branch instructions detected as a branch

[Hossein Golestani]

Hi,

As a follow-up to my previous email, I think I know what causes
the problem, but I don't know how to solve it.

The source of the problem seems to be that the value of the private
variable _compressed of RISC-V PCState objects is not set properly. In
other words, I couldn't find any place in the code where the setter
function "void compressed(bool c)" (implemented in src/arc/riscv/types.hh)
is called. So, since this variable is used in the "bool branching()"
function of the PCState class, branching() returns an incorrect value for
non-branch compressed instructions.

I'm going to make my RISC-V compiler not generate compressed instruction as
a temporary work-around. But I'd appreciate it if someone could help to
solve this problem.

Thanks,
Hossein




On Tue, Feb 25, 2020 at 12:48 PM Hossein Golestani 
wrote:

> Hello everyone,
>
> I'm facing an issue regarding using the RISC-V ISA with the DerivO3CPU
> model. Apparently, some RISC-V instructions are incorrectly detected as a
> branch. Here's a piece of debugging output:
> 5682918000: system.switch_cpus.fetch: [tid:0] Instruction PC 0x10586 (0)
> created [sn:1].
> 5682918000: system.switch_cpus.fetch: [tid:0] Instruction is: *c_fsd*
> fa5, 72(a5)
> 5682918000: system.switch_cpus.fetch: [tid:0] Fetch queue entry created
> (1/32).
> 5682918000: system.switch_cpus.fetch: *Branch detected* with PC =
> (0x10586=>0x10588).(0=>1)
> 5682918000: system.switch_cpus.fetch: [tid:0] *Done fetching*, predicted
> branch instruction encountered.
>
> c_fsd is a floating-point store rather than a branch. I observed such an
> issue for other non-branch instructions, including c_ld, c_sd, and c_mv.
> As you can see, this problem seems to have to do with RISC-V compressed
> instructions, as also suggested in a previous post (link
> ). This
> problem causes inaccuracies in performance modeling of the OoO core, that
> is, since branch prediction needs to be performed at the fetch stage, no
> other instruction (as far as fetch bandwidth allows) is fetched after the
> wrong branches.
>
> Looking a bit in the code of the DefaultFetch::fetch function in
> src/cpu/o3/fetch_impl.hh, it seems thisPC.branching() returns true for
> the instructions mentioned above. For the RISC-V ISA, this function is
> implemented in src/arc/riscv/types.hh.
>
> Before trying to solve this problem on my own, I just wanted to report it
> here to see if anyone can help. I will send a follow-up email if I make
> progress on this.
>
> By the way, I'm using the commit c4724cac6 of gem5 (3 months old as of
> today).
>
> Thanks,
> Hossein
>
>
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Re: [gem5-users] Commit numbers/tags of previous stable version missing

[Abhishek Singh]

Thank you Bobby for your reply.

I just found all the tags in my old repos and saved them.



On Sun, Mar 1, 2020 at 11:50 AM Bobby R. Bruce  wrote:

> Abhishek,
>
> I’m not aware of any tags that were previously used to mark stable
> versions. As far as I know, gem5-19 is the first stable release. If patches
> were made to previous versions of the product then I suspect they were made
> to arbitrary revisions, in which case I’d advise getting in contact with
> those who developed these patches for more information. I’m sorry I can’t
> be of more help.
>
> If anyone else has any more information about this then it’d be much
> appreciated.
>
> Kind regards
> Bobby
>
> --
> Dr. Bobby R. Bruce
> Room 2235,
> Kemper Hall, UC Davis
> Davis,
> CA, 95616
>
> On Mar 1, 2020, at 02:50, Abhishek Singh 
> wrote:
>
> 
>
> Hello everyone,
>
> Can anyone provide me with the commit number of the previous stable
> version of gem5?
>
> This stable-tags has been removed recently like 3 days before.
>
> *Bobby and Jason*: Is there any reason for removing it?
> I am asking this because there are other simulators (mostly from Prof.
> Onur Mutlu’s group are based on it and they have just provided patches to
> the old stable versions) which are based on it. And I wanted to use them.
>
> Also, if the tags of them are not coming back, is it possible to get
> information on their commit numbers ?
>
>
>
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Re: [gem5-users] Commit numbers/tags of previous stable version missing

[Bobby R. Bruce]

Abhishek,

I’m not aware of any tags that were previously used to mark stable versions. As 
far as I know, gem5-19 is the first stable release. If patches were made to 
previous versions of the product then I suspect they were made to arbitrary 
revisions, in which case I’d advise getting in contact with those who developed 
these patches for more information. I’m sorry I can’t be of more help.

If anyone else has any more information about this then it’d be much 
appreciated.

Kind regards
Bobby

--
Dr. Bobby R. Bruce
Room 2235,
Kemper Hall, UC Davis
Davis,
CA, 95616

> On Mar 1, 2020, at 02:50, Abhishek Singh  
> wrote:
> 
> 
> Hello everyone,
> 
> Can anyone provide me with the commit number of the previous stable version 
> of gem5?
> 
> This stable-tags has been removed recently like 3 days before.
> 
> Bobby and Jason: Is there any reason for removing it?
> I am asking this because there are other simulators (mostly from Prof. Onur 
> Mutlu’s group are based on it and they have just provided patches to the old 
> stable versions) which are based on it. And I wanted to use them.
> 
> Also, if the tags of them are not coming back, is it possible to get 
> information on their commit numbers ?
> 
> 
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Re: [gem5-users] Modifying source code in gem5

[Francisco Carlos]

Could you give me more details? Where did you add the cprintf()? Which command 
are you using for running gem5?

If you want to modify the gem for test purposes, I suggest inserting the 
cprintf() in the tick() method because this method is always called in the 
O3CPU model. I guess you might add the cprintf() for a method that was not 
called.

Best regards.

--
Francisco Carlos Silva Junior
Ph.D Student


De: gem5-users  em nome de Eun-Sung Kim 

Enviado: domingo, 1 de março de 2020 06:27
Para: gem5-users@gem5.org 
Assunto: [gem5-users] Modifying source code in gem5

I’m trying to modify source code in gem5.
For testing, I add a cprintf() statement to src/cpu/o3/fetch_impl.hh. Then 
using scons, I rebuild gem5. But, any change didn’t happen.
What did I miss?
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[gem5-users] Commit numbers/tags of previous stable version missing

[Abhishek Singh]

Hello everyone,

Can anyone provide me with the commit number of the previous stable version
of gem5?

This stable-tags has been removed recently like 3 days before.

*Bobby and Jason*: Is there any reason for removing it?
I am asking this because there are other simulators (mostly from Prof. Onur
Mutlu’s group are based on it and they have just provided patches to the
old stable versions) which are based on it. And I wanted to use them.

Also, if the tags of them are not coming back, is it possible to get
information on their commit numbers ?
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[gem5-users] Modifying source code in gem5

[Eun-Sung Kim]

I’m trying to modify source code in gem5.
For testing, I add a cprintf() statement to src/cpu/o3/fetch_impl.hh. Then
using scons, I rebuild gem5. But, any change didn’t happen.
What did I miss?
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