[gem5-users] Question about SimpleMemory latency
Hello, For a default memory configuration using SimpleMemory in SE mode, config.ini is showing a latency of 3. Is this latency in cycles (same question for cache latency values)? In addition, a professor has told me that typical DRAM latency is more like 300 cycles; can someone explain the factor of 100 difference? Finally, what's the easiest way to change the memory latency for our simulation? [system.physmem] type=SimpleMemory bandwidth=73.00 clock=1000 conf_table_reported=false in_addr_map=true latency=3 latency_var=0 null=false range=0:536870911 zero=false port=system.membus.master[0] Thanks, David G. -- David Gloe Masters Student, Computer Science University of Minnesota ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] gdb debugging issues
Hello, I'm testing some instrumented code on gem5 and the instrumented version of an application runs faster than the non-instrumented version. That seemed very fishy to me because the instrumentation adds a function call to every conditional in the program; it should run significantly slower. I wanted to check the code using the remote gdb interface to make sure the instrumentation wasn't changing program semantics but I'm having some issues. I was able to compile gdb with an ARM target (host is x86_64, gem5 is running ARM) and connect using the arm-with-neon.xml file. However, I get a panic when trying to set a breakpoint: GNU gdb (GDB) 7.5.1 Copyright (C) 2012 Free Software Foundation, Inc. License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html> This is free software: you are free to change and redistribute it. There is NO WARRANTY, to the extent permitted by law. Type "show copying" and "show warranty" for details. This GDB was configured as "--host=x86_64-unknown-linux-gnu --target=arm-linux". For bug reporting instructions, please see: <http://www.gnu.org/software/gdb/bugs/>. (gdb) set remote Z-packet on (gdb) set tdesc filename ./gdb/features/arm-with-neon.xml (gdb) target remote 127.0.0.1:7000 Remote debugging using 127.0.0.1:7000 0x8b10 in ?? () (gdb) symbol-file ~/gem5/App Reading symbols from /home/david/gem5/App...done. (gdb) break mr_microwave Breakpoint 1 at 0x8a5e: file Instrumented/microwaveCollatedInstrumented.c, line 201. (gdb) c Continuing. Remote connection closed gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. gem5 compiled Apr 4 2013 01:47:25 gem5 started Apr 7 2013 13:38:41 gem5 executing on david-ThinkPad-T410 command line: ./build/ARM/gem5.opt -d /home/david/Documents/Crisys/2010-InVivoMonitoring/Monitoring.gem5/Results/20130407133828 configs/example/se.py --clock=1GHz -c ./App Global frequency set at 1 ticks per second 0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 REAL SIMULATION info: Entering event queue @ 0. Starting simulation... 5559854000: system.remote_gdb: remote gdb attached panic: invalid length @ cycle 5559855000 [insertSoftBreak:build/ARM/base/remote_gdb.cc, line 543] Memory Usage: 627016 KBytes Program aborted at cycle 5559855000 ./runTest.sh: line 159: 28922 Aborted (core dumped) nice ./build/ARM/gem5.opt $DEBUG_ARG -d $WORKSPACE_HOME/$RESULT_DIR/$DATE $SIM_SCRIPT $SE_OPTS -c "./$APP" From looking at remote_gdb.cc it seems that the length of the breakpoint doesn't match the size of TheISA::MachInst but I'm not sure how to configure gdb to send the correct length. Has anyone had this problem before, or knows how to work around it? Thanks, David -- David Gloe gloex...@umn.edu da...@cs.umn.edu dcg...@gmail.com Masters Student, Computer Science University of Minnesota ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Instrument a program with gem5
Ali, Thank you for responding. Basically what I have set up now is a separate branch monitor program running on a second core; I want to compare this against instrumentation on one core. My thread context idea was to have the monitor running in a separate thread context. Then it would be similar to how my two-core version works where some branch information is stored within the simulator, thread context is switched to the monitor to handle it, then switched back to the original application. The applications I'm using are fairly large (one has more than 2000 lines) so I wanted to avoid manual instrumentation. Compiler modification might be ideal, but I have no experience or time to attempt modifying LLVM at this time. I'll look into modifying the branch instructions. Thanks, David G. On 03/25/2013 07:28 AM, gem5-users-requ...@gem5.org wrote: Hi David, It's certainly possible, but it's going to take some work. My random idea would be to change how all the branch instructions are defined, so the stash their real target address somewhere and jump to your handler. Other than that manually instrumenting the program (or doing it with some compiler modifications) would probably be your best bet. While it doesn't take any time to switch thread contexts, by definition the context has all the state from the thread in it, so I'm not sure how switching would solve your problem. Ali On Mar 24, 2013, at 11:18 PM, David Gloe wrote: >Hello, > >I am attempting to instrument branch instructions in a program in gem5. So far, I have code in AtomicSimpleCPU which determines when branch instructions are executed. For every branch, I would like to call an instrumentation function and then return to execution of the simulated program. This would be fairly simple, but I would like to execute the instrumentation function within the simulator, so the instrumentation time is taken into account on the simulator statistics. > >Is it possible to do something like this? Any ideas on how to do this? The function could be compiled in with the program, so we might be able to instrument by manually setting up arguments and changing the PC to the instrumentation function. Another idea I had would be to have two thread contexts for one CPU with one running the application and one doing instrumentation, and switching between them as needed. Is this sort of thing possible; is there any simulation time used by thread context switches? > >Thanks, >David G. > >-- >David Gloe >gloex...@umn.edu da...@cs.umn.edu dcg...@gmail.com >Masters Student, Computer Science >University of Minnesota > >___ >gem5-users mailing list >gem5-users@gem5.org >http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- David Gloe gloex...@umn.edu da...@cs.umn.edu dcg...@gmail.com Masters Student, Computer Science University of Minnesota ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Instrument a program with gem5
Hello, I am attempting to instrument branch instructions in a program in gem5. So far, I have code in AtomicSimpleCPU which determines when branch instructions are executed. For every branch, I would like to call an instrumentation function and then return to execution of the simulated program. This would be fairly simple, but I would like to execute the instrumentation function within the simulator, so the instrumentation time is taken into account on the simulator statistics. Is it possible to do something like this? Any ideas on how to do this? The function could be compiled in with the program, so we might be able to instrument by manually setting up arguments and changing the PC to the instrumentation function. Another idea I had would be to have two thread contexts for one CPU with one running the application and one doing instrumentation, and switching between them as needed. Is this sort of thing possible; is there any simulation time used by thread context switches? Thanks, David G. -- David Gloe gloex...@umn.edu da...@cs.umn.edu dcg...@gmail.com Masters Student, Computer Science University of Minnesota ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Creating a barrier in SE mode
Hello, I am running a two CPU simulation in SE mode, and I would like to be able to have both of the programs reach a specific point before continuing (a barrier). Is there a built-in way for gem5 to do this? I was thinking perhaps suspending one CPU when the barrier is reached and then resuming it when the other CPU reaches the barrier. If there isn't a way already in gem5, what would be the best way to add it? A new pseudo-instruction? Thanks, David Gloe ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Suspend/Idle and Resume in SE mode
Hi again, I think I've solved the issue myself. I was incorrectly using a static variable instead of a member variable, causing both CPUs to be suspended. I've got it working now with suspending and resuming. -David On Fri, Nov 30, 2012 at 1:45 PM, David Gloe wrote: > Hello, > > I'm running a two CPU simulation in SE mode with a queue to transmit > information between the CPUs. I would like to be able to suspend or idle > the first CPU if the queue is full, and resume once the second CPU dequeues. > > However, I've been having an issue where it looks like the second CPU > isn't executing at all, so it doesn't have a chance to dequeue anything. > Whenever I suspend the first CPU, I get the message 'Exiting because > simulate() limit reached'. When I simply ignore a full queue, the > simulation runs fine. > > I'm suspending using tc->suspend() and waking up with tc->activate(), > though I don't think the activate ever gets called. I'm using a modified > AtomicSimpleCPU in SE mode with two CPUs (-n 2). > > Here are some questions I have: > * Will a quiesce() on a two-CPU system suspend both CPUs? > * If so, is there a way to suspend or idle only one CPU and later resume? > * Is the tick() function still called if a CPU is idle or suspended? > > Thanks, > David G. > > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Suspend/Idle and Resume in SE mode
Hello, I'm running a two CPU simulation in SE mode with a queue to transmit information between the CPUs. I would like to be able to suspend or idle the first CPU if the queue is full, and resume once the second CPU dequeues. However, I've been having an issue where it looks like the second CPU isn't executing at all, so it doesn't have a chance to dequeue anything. Whenever I suspend the first CPU, I get the message 'Exiting because simulate() limit reached'. When I simply ignore a full queue, the simulation runs fine. I'm suspending using tc->suspend() and waking up with tc->activate(), though I don't think the activate ever gets called. I'm using a modified AtomicSimpleCPU in SE mode with two CPUs (-n 2). Here are some questions I have: * Will a quiesce() on a two-CPU system suspend both CPUs? * If so, is there a way to suspend or idle only one CPU and later resume? * Is the tick() function still called if a CPU is idle or suspended? Thanks, David G. ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Arguments to Pseudo Instructions
I think I found the answer to my own question. The version of Linux I'm compiling on is 32 bit, but gem5 uses the 64 bit Rdi Rsi calling convention. I'm looking into either upgrading my laptop to 64 bit or using ARM with a cross compiler. -David -- David Gloe gloex...@umn.edu da...@cs.umn.edu dcg...@gmail.com Masters Student, Computer Science University of Minnesota ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Arguments to Pseudo Instructions
Hello,
I'm trying to add a pseudo instruction for my SE mode program, and it
looks like the arguments aren't being passed correctly. I tried to
follow the other functions with the changes I made, but I can't see
what's going wrong. Here are the changes I made to various places in gem5.
In two_byte_opcodes.isa:
0x57: m5reserved3({{
// enqueue
PseudoInst::crisysenqueue(xc->tcBase(), Rdi, Rsi);
}}, IsNonSpeculative);
In pseudo_inst.cc:
void crisysenqueue(ThreadContext *tc, uint64_t addr, uint64_t info)
...
DPRINTF(Crisys, "Queuing address %llx info %llx\n",
(long long unsigned)addr, (long long unsigned)info);
...
m5op.h: void m5_crisysenqueue(uint64_t addr, uint64_t info);
m5ops.h: #define crisysenqueue_func 0x57
m5op_x86.S: TWO_BYTE_OP(m5_crisysenqueue, crisysenqueue_func)
And this is an excerpt from my test program:
for (i = 0; i < 1000; i++) {
m5_crisysenqueue(i, i);
}
Which was compiled with: gcc -o enqueue -I util/m5 enqueue.c
util/m5/m5op_x86.S -static
However, when I turn debug output on, it always shows
18609000: global: Queuing address 80496c0 info 0
The same address and info, regardless of the parameters I pass to the
function.
Am I missing some instruction addressing mode issue? Is there another
file I need to modify that I missed?
Thanks,
David
--
David Gloe
gloex...@umn.edu da...@cs.umn.edu dcg...@gmail.com
Masters Student, Computer Science
University of Minnesota
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Re: [gem5-users] Sending information between CPUs
Amin, Another idea I had was using some of the reserved pseudo-instructions to do this. Would that be how you would do this with a shared resource in the simulator? I figure I can use one reserved instruction for enqueue and one for dequeue, storing the buffer in a global variable in pseudo_inst.cc. From what I've been looking at, it seems that I need to update (for x86) two_byte_opcodes.isa, pseudo_inst.cc, and the various m5op files. Anything missing? Also, the pseudo-instruction will work in SE mode as long as I don't include the panicFsOnlyPseudoInst call in pseudo_inst.cc, right? Thanks again, David -- David Gloe gloex...@umn.edu da...@cs.umn.edu dcg...@gmail.com Masters Student, Computer Science University of Minnesota ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Sending information between CPUs
Hello again, Does anyone know the function(s) to copy the register file that Amin was alluding to? How about advice on using m5_readfile and m5_writefile, or a MessageBuffer? Thanks, David -- David Gloe gloex...@umn.edu da...@cs.umn.edu dcg...@gmail.com Masters Student, Computer Science University of Minnesota ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Sending information between CPUs
Hello, I would like to be able to send information (the PC and an integer value) between CPUs in a gem5 simulation. Instead of using interprocess communication, I would like to simulate the existence of an instantaneous or nearly instantaneous buffer which can be written to and read from with assembly or C instructions. Right now I am using an SE mode set up with two CPUs, with one process running on each. One crude idea I had would be to use a file with the m5_writefile and m5_readfile commands to have one process write to a file and the other read from it. Do those functions take simulation time? Another idea I had would be to use a MessageBuffer. Is it possible to use a MessageBuffer in SE mode? How would I add such a buffer to my simulation, and then write to it and read from it using C or assembly language? Thanks, David G. -- David Gloe gloex...@umn.edu da...@cs.umn.edu dcg...@gmail.com Masters Student, Computer Science University of Minnesota ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] gem5 --list-sim-objects is broken
Hello, I'm just starting to try out gem5, and a I ran into an error today using the gem5 --list-sim-objects argument. This is from week old gem5 checkout. david@david-ThinkPad-T410:~/gem5$ build/ARM/gem5.opt --list-sim-objects ... ArmTLB size default: 64 desc: TLB size walker Traceback (most recent call last): File "", line 1, in File "/home/david/gem5/src/python/m5/main.py", line 243, in main print "default: %s" % default File "/home/david/gem5/src/python/m5/SimObject.py", line 833, in __str__ return self.path() File "/home/david/gem5/src/python/m5/SimObject.py", line 827, in path ppath = self._parent.path() TypeError: unbound method path() must be called with ArmTLB instance as first argument (got nothing instead) I'm no python expert, but from googling, it seems that _parent returns the class itself, not a reference to it. Since the path function isn't a static method, path() fails. Would it be better instead to use the getmro function for this purpose? http://docs.python.org/library/inspect.html#inspect.getmro Thanks, David -- David Gloe gloex...@umn.edu da...@cs.umn.edu dcg...@gmail.com Masters Student, Computer Science University of Minnesota ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
