[gem5-users] Question about Page fault in gem5

[Fengze Yu via gem5-users]

Hi
I have been looking at the mmu source code in gem5, and I am curious about how 
gem5 handles page table fault. It seems that instruction will be labled Fault 
everytime a TLB miss happens in both SE and FullSystem mode, but I could not 
see how that page fault is dealt with afterwards. So my questions are:


1. Where are the page tables located in both SE and FullSystem mode?


2. How does gem5 deal with page fault in both SE and FullSystem mode? 


I will be ready greatful if you can also point me to the document/source code 
for each of the above question.






Thanks in advance!


Best


Fengze___
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[gem5-users] fatal when adding a new CPU

[Fengze Yu via gem5-users]

Hi


I was trying to add a new CPU inherit from BaseCPU:


class MY_CPU: public BaseCPU
{
public:


    MY_CPU(const MY_CPUParams& p);
    ~MY_CPU(){}

    ...
private:
    ...
}


but incurs the following running error: fatal: Process system.cpu.workload is 
not associated with any HW contexts!


...
warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
Global frequency set at 1 ticks per second
warn: No dot file generated. Please install pydot to generate the dot file and 
pdf.
build/RISCV/mem/mem_interface.cc:793: warn: DRAM device capacity (8192 Mbytes) 
does not match the address range assigned (512 Mbytes)
build/RISCV/base/statistics.hh:277: warn: One of the stats is a legacy stat. 
Legacy stat is a stat that does not belong to any statistics::Group. Legacy 
stat is deprecated.
build/RISCV/arch/riscv/linux/se_workload.cc:60: warn: Unknown operating system; 
assuming Linux.
build/RISCV/sim/process.cc:290: fatal: Process system.cpu.workload is not 
associated with any HW contexts!

...


Did I miss anything essential when creating a new CPU class?




Thanks in advance


Fengze___
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[gem5-users] L2 or L3 cache interface

[Fengze Yu via gem5-users]

Hi 


What is the interface between L1 and L2 cache in Ruby cache coherence model? Is 
there a clear defined interface, similar to the icachePort and dcachePort 
between CPU and memory, between different levels of caches in Ruby?




Thanks in advance


Fengze Yu ___
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[gem5-users] Compile GEM5 to .a or .so file

[Fengze Yu via gem5-users]

Hi 


  Building GEM5 using scons generates an executable file gem5.opt. What if 
I want to generate a static or dynamic library, which is either a .a or .so 
file, instead of an executable? 
  I have noticed that in SConscript under gem5/src, there is a 
process to make all the object into an library, but I could not find any file 
with .a or .so suffix under the build/ directory.


# First make a library of everything but main() so other programs can
# link against m5.
static_lib = new_env.StaticLibrary(libname, static_objs)
shared_lib = new_env.SharedLibrary(libname, shared_objs)





Thanks


Fengze___
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