Hi Tushar,
I tried running a simple 5x4 cpus in Mesh_XY topology using the command:
idris@idris-HP-EliteBook-8460p:~/Desktop/gem5$
build/Garnet_standalone/gem5.opt configs/example/garnet_synth_traffic.py
--network=garnet2.0 --num-cpus=20 --num-dirs=20 --topology=Mesh_XY
--mesh-rows=5 --sim-cycles=3000 --injectionrate=0.12
--synthetic=uniform_random --routing-algorithm=1
but received the following memory interleaving error.
...
...
...
warn: DRAM device capacity (8192 Mbytes) does not match the address range
assigned (32 Mbytes)
warn: rounding error > tolerance
1.25 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range
assigned (32 Mbytes)
fatal: fatal condition intlvBits && intlvMatch >= ULL(1) << intlvBits
occurred: Match value 16 does not fit in 4 interleaving bits
Memory Usage: 94504 KBytes
idris@idris-HP-EliteBook-8460p:~/Desktop/gem5$
Hacking into the above creates a chain reaction.
This is the main reason why I find it difficult to create the pyramid
topology. It seems the simulator can only run a square matrix of (n to
power 2) cpus.
In the decoupling techniques I used, I declared the base layer and the
first upper hierarchy as follows:
1. routers = [Router(router_id=i, latency=router_latency)\
for i in xrange(num_routers)]# num_routers = 64
network.routers = routers
2. hier_routers = [Router(router_id=i+j+1, latency=router_latency)
\
for j in range(num_h_routers)] # num_h_routers = 16
# Update the network routers here
routers.extend(hier_routers)
network.routers = routers
Logs in config.ini shows that all routers were created, all internal links
and external links were also created. But the upper layers router could not
wakeup.
This led me to the first mail I wrote: Inquiry on router wakeup in
garnet2.0. Debug flags cannot see beyond the base layer (64) routers.
That is why I want to replace routers with switches at the upper layers. Do
you thinks that is okay? or is there something wrong with the technique I
deploy?
Thanks
Kimiya F.
On Thu, Aug 15, 2019 at 5:00 PM wrote:
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> Today's Topics:
>
>1. CPUID function 0_7 - CacheParams (Pouya Fotouhi)
>2. Re: CPUID function 0_7 - CacheParams (Gabe Black)
>3. Re: CPUID function 0_7 - CacheParams (Gabe Black)
>4. Re: CPUID function 0_7 - CacheParams (Pouya Fotouhi)
>5. Re: CPUID function 0_7 - CacheParams (Gabe Black)
>6. Re: CPUID function 0_7 - CacheParams (Pouya Fotouhi)
>7. Question on how to create a command line options for a switch
> (router) in garnet2.0 (Kimiya Fasahar)
>8. Re: Question on how to create a command line options for a
> switch (router) in garnet2.0 (Krishna, Tushar)
>
>
> --
>
> Message: 1
> Date: Wed, 14 Aug 2019 14:01:26 -0700
> From: Pouya Fotouhi
> To: gem5 users mailing list
> Subject: [gem5-users] CPUID function 0_7 - CacheParams
> Message-ID:
> egdbrjpyu11ibymregobjj7nntzebsypy6azmbjr5v...@mail.gmail.com>
> Content-Type: text/plain; charset="utf-8"
>
> Hi All,
>
> During kernel boot up with the timing/atomic/O3 CPU modes I get the
> following kernel oops at native_flush_tlb_global. Looking closer at the
> issue, Exec traces show:
>
> 2014093750: system.cpu A0 T0 : @native_flush_tlb_global+96: mov
> eax, 0x2
> 2014093750: system.cpu A0 T0 : @native_flush_tlb_global+96.0 : MOV_R_I :
> limm eax, 0x2 : IntAlu : D=0x0002
> flags=(IsInteger|IsMicroop|IsLastMicroop|IsFirstMicroop)
> 2014094250: system.cpu A0 T0 : @native_flush_tlb_global+101: ud2
> 2014094250: system.cpu A0 T0 : @native_flush_tlb_global+101.0 : UD2 :
> fault Invalid-Opcode : No_OpClass :
> flags=(IsMicroop|IsLastMicroop|IsFirstMicroop)
> 2014094500: system.cpu A0 T0 : @native_flush_tlb_global+101.32768 :
> Microcode_ROM : slli t4, t1, 0x4 : IntAlu : D=0x0060
> flags=(IsInteger|IsMicroop|IsDelayedCommit)
>
> Looking at the decode of the "undefined" instruction raising the fault:
> 2014094250: system.cpu: Decode: Decoded fault instruction:
> {
> leg = 0x10,
> rex = 0,
> vex/xop = 0,
>
