Re: [gem5-users] L2 cache partitioning
Hi all,
I made a patch to enable L2 cache partitioning on gem5. Please find it at
https://github.com/farzadfch/gem5-cache-partitioning
I wrote this code a while ago and I wanted to make it more flexible and
implement it on a later version of gem5 before making it publicly available,
but this has not happened so far therefore, I decided to release it anyway. I
believe it can be still useful for someone who wants to implement cache
partitioning on gem5. More explanations about using this patch are given in the
readme next to it.
Cheers,
Farzad
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
Hi,
Have a look at src/mem/cache/tags/base_set_assoc.{hh,cc}
You will find that there is already functionality to restrict the
allocation to certain set indices (allocAssoc) for any access. It
shouldn't be too hard extending this to do what you want.
Please do post the patches once you have something working.
Andreas
On 23/02/2016, 23:33, "gem5-users on behalf of Farzad Farshchi"
<gem5-users-boun...@gem5.org on behalf of farsh...@ku.edu> wrote:
>Andreas Hansson arm.com> writes:
>
>>
>>
>> Hi Prathap,
>>
>> We have some patches to restrict way allocation in the cache itself
>>(not
>per core though). You can probably use that as a starting point. I'm
>afraid
>beyond that you will need to add the appropriate functionality to look at
>e.g. masterId and decide on a
>> way. I'll try and get those patches posted in the next few days.
>>
>> Andreas
>>
>>
>>
>> From: Prathap Kolakkampadath gmail.com>Reply-To: gem5
>users mailing list gem5.org>Date: Monday, 8 June 2015
>17:29To: gem5 users mailing list gem5.org>Subject: [gem5-
>users] L2 cache partitioning
>>
>>
>>
>> Dear Users,
>>
>> I am using ARM Full System configuration, where L2 is 8-way set
>associative shared Last Level Cache. I am trying to partition the L2
>cache
>by
>> ways among four cores, so that each core gets two ways.
>>
>> Is there a hardware support(configuration register) available to do
>>this?
>If not can anyone throw some pointers to achieve way partitioning.
>>
>> Thanks in advance.
>>
>> Prathap
>>
>>
>>
>> -- IMPORTANT NOTICE: The contents of this email and any attachments are
>confidential and may also be privileged. If you are not the intended
>recipient, please notify the sender immediately and do not disclose the
>contents
>> to any other person, use it for any purpose, or store or copy the
>information in any medium. Thank you.
>> ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
>Registered in England & Wales, Company No: 2557590
>> ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1
>>9NJ,
>Registered in England & Wales, Company No: 2548782
>>
>>
>> ___
>> gem5-users mailing list
>> gem5-users gem5.org
>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
>Hi Andreas,
>
>I am also looking for the same feature in gem5. I was wondering if you
>have
>posted your patches. If you did, can you please give me a pointer to them?
>
>Thanks,
>Farzad
>___
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Re: [gem5-users] L2 cache partitioning
Thanks. Farzad ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] L2 cache partitioning
Andreas Hansson arm.com> writes: > > > Hi Prathap, > > We have some patches to restrict way allocation in the cache itself (not per core though). You can probably use that as a starting point. I’m afraid beyond that you will need to add the appropriate functionality to look at e.g. masterId and decide on a > way. I’ll try and get those patches posted in the next few days. > > Andreas > > > > From: Prathap Kolakkampadath gmail.com>Reply-To: gem5 users mailing list gem5.org>Date: Monday, 8 June 2015 17:29To: gem5 users mailing list gem5.org>Subject: [gem5- users] L2 cache partitioning > > > > Dear Users, > > I am using ARM Full System configuration, where L2 is 8-way set associative shared Last Level Cache. I am trying to partition the L2 cache by > ways among four cores, so that each core gets two ways. > > Is there a hardware support(configuration register) available to do this? If not can anyone throw some pointers to achieve way partitioning. > > Thanks in advance. > > Prathap > > > > -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents > to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. > ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590 > ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782 > > > ___ > gem5-users mailing list > gem5-users gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users Hi Andreas, I am also looking for the same feature in gem5. I was wondering if you have posted your patches. If you did, can you please give me a pointer to them? Thanks, Farzad ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] L2 cache partitioning
Thanks On Sat, Jun 13, 2015 at 4:38 AM, Andreas Hansson andreas.hans...@arm.com wrote: Hi Prathap, We have some patches to restrict way allocation in the cache itself (not per core though). You can probably use that as a starting point. I’m afraid beyond that you will need to add the appropriate functionality to look at e.g. masterId and decide on a way. I’ll try and get those patches posted in the next few days. Andreas From: Prathap Kolakkampadath kvprat...@gmail.com Reply-To: gem5 users mailing list gem5-users@gem5.org Date: Monday, 8 June 2015 17:29 To: gem5 users mailing list gem5-users@gem5.org Subject: [gem5-users] L2 cache partitioning Dear Users, I am using ARM Full System configuration, where L2 is 8-way set associative shared Last Level Cache. I am trying to partition the L2 cache by *ways* among four cores, so that each core gets two ways. Is there a hardware support(configuration register) available to do this? If not can anyone throw some pointers to achieve way partitioning. Thanks in advance. Prathap -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2548782 ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] L2 cache partitioning
Hi Prathap, We have some patches to restrict way allocation in the cache itself (not per core though). You can probably use that as a starting point. I’m afraid beyond that you will need to add the appropriate functionality to look at e.g. masterId and decide on a way. I’ll try and get those patches posted in the next few days. Andreas From: Prathap Kolakkampadath kvprat...@gmail.commailto:kvprat...@gmail.com Reply-To: gem5 users mailing list gem5-users@gem5.orgmailto:gem5-users@gem5.org Date: Monday, 8 June 2015 17:29 To: gem5 users mailing list gem5-users@gem5.orgmailto:gem5-users@gem5.org Subject: [gem5-users] L2 cache partitioning Dear Users, I am using ARM Full System configuration, where L2 is 8-way set associative shared Last Level Cache. I am trying to partition the L2 cache by ways among four cores, so that each core gets two ways. Is there a hardware support(configuration register) available to do this? If not can anyone throw some pointers to achieve way partitioning. Thanks in advance. Prathap -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2548782 ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] L2 cache partitioning
Dear Users, I am using ARM Full System configuration, where L2 is 8-way set associative shared Last Level Cache. I am trying to partition the L2 cache by *ways* among four cores, so that each core gets two ways. Is there a hardware support(configuration register) available to do this? If not can anyone throw some pointers to achieve way partitioning. Thanks in advance. Prathap ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
