[gem5-users] Re: How to connected CpuSidePort and MemSidePort within a simobject ( not in config file)

[Eliot Moss via gem5-users]

On 8/14/2023 3:47 PM, Khan Shaikhul Hadi wrote:
Instead of directly connecting all level 1 caches ( icache, dcache etc) to CPU and next level bus, I 
want to create a controller module that will have all those caches . This controller module will 
receive all cpu requests and distribute them to caches. Similarly it will receive all requests to 
next level caches and send them to next level cache. The reason I want to do such a thing because, 
for my current work, I need to observe requests and responses from caches and modify them based on 
some protocol. Initially I thought of modifying the caches all together, but that became more 
complicated and I thought if I could connect those caches within a module, that would simplify 
things without sacrificing any performance modeling of the caches. Problem is I could not figure out 
how to connect the cache simobject cpu and mem side port with the internal port of the controller 
module.


Best
Shaikhul


I'd be tempted to make a new subclass of CommMonitor and interpose instances between modules.  You 
could keeps the stats capabilities or not.


Regards - EM
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[gem5-users] Re: How to connected CpuSidePort and MemSidePort within a simobject ( not in config file)

[Eliot Moss via gem5-users]

On 8/14/2023 1:42 PM, Khan Shaikhul Hadi wrote:

Initially I was thinking doing something like this as you suggested:

CpuSidePort cacheMemSidePortConnection = cache.memSidePort;
MemSidePort cacheCpuSidePortConnection = cache.cpuSidePort;


problem is when I looked into how python code done this connection, constructor 
has


  cpuSidePort(p.name  + ".cpu_side_port", *this, 
"CpuSidePort"),
      memSidePort(p.name  + ".mem_side_port", this, 
"MemSidePort"),


So, when I was thinking about using CpuSidePort cacheMemSidePortConnection = cache.memSidePort, I 
could not make sense of howto deal with those constructor arguments . Especially"this" pointer which 
is supposed to be a pointer or reference to the cache object, but my simobject is not cache_object. 
So, I'm not sure how to deal withthis.


Thanks for your input though.

Best
Shaikhul


If you have already declared Cache cache, then the Cache constructor has run 
and the fields are
available for assigning to other variables - assuming they are public or you 
can arrange access.
Of course you really need to write:

Cache cache(parameters to Cache constructor);

But perhaps you could clarify what you're really trying to do (bigger picture) 
rather than
saying "I want this port connected to that one".

Best - EM
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[gem5-users] Re: How to connected CpuSidePort and MemSidePort within a simobject ( not in config file)

[Eliot Moss via gem5-users]

On 8/14/2023 11:58 AM, Khan Shaikhul Hadi via gem5-users wrote:
In my code I'll have a simobject which has its own cache. As classical cache use CpuSidePort and 
MemSidePort to receive and respond to request, I want to create some internal CpuSidePort and 
MemSidePort in my simobject like below


class SimObject : public ClockedObject
{
  Cache cache;
CpuSidePort  cacheMemSidePortConnection;
MemSidePort cacheCpuSidePortConnection; 



// CpuSidePort and MemSidePort class could follow same structure as 
BaseCache CpuSidePort and
MemSidePort


...
...
...
}

My question is how could I connect this ports with cache such that when I schedule some request pkt 
using cacheCpuSidePortConnection, cache's cpuSidePort will catch that packet, when cache's 
memSidePort schedule some req pkt, cacheMemSidePort will catch that pkt.
In the front end, I could see in the library, we could do that using param ( cache.cpu_side_port = 
cpu.mem_side_port). But could not find any reference that connects to port within a simobject.

Any suggestions  or resources which I could follow ?


Why not just do this?

CpuSidePort cacheMemSidePortConnection = cache.memSidePort;
MemSidePort cacheCpuSidePortConnection = cache.cpuSidePort;

Then whatever is connected with the cache is exactly what;s connected to your 
thing -
though I am not sure what you get by doing this.

The connecting up is generally done by Python code in terms of parameters
in the Python classes.  Thus Cache.py has class BaseCache  with:

cpu_side = ResponsePort(...)
mem_side = RequestPort(...)

and in cache/base.cc the constructor has:

cpuSidePort(p.name + ".cpu_side_port", *this, "CpuSidePort"),
memSidePort(p.name + ".mem_side_port", this, "MemSidePort"),

cache/base.hh has (after a whole series of class definitions):

   CpuSidePort cpuSidePort;
   MemSidePort memSidePort;

Here's another possibility: write your thing as a subclass of Cache, assuming 
it is
supposed to act somewhat like a cache.

I don't feel totally confident in guiding you here since it's not clear what 
you're
really hoping to do ...

Maybe others will have other, more useful, perspectives for you ...   EM
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