Re: New Opcodes

2008-01-31 Thread Tom Schmidt
On Fri, 25 Jan 2008 13:12:22 -0800, Keith E. Moe wrote:
Second, there was one mnemonic that caught my eye.  I do not know what 
it does, but it's probably one that none of us will forget:  PTF.
 
 
Are you certain that it wasn't PTFF (which was already described in the 
current Principles of Operations -05 pub)?  If so there's no NDA worries.  
  
 
I'm still waiting for MVCOS to finally make it out into the PoO... it was 
leaked 
pretty thoroughly a few SHAREs ago in several IBM sessions but didn't make it 
into either of the last 2 PoOs.  (I don't care about what issues caused it to 
be 
late, I just want it to be born after all this time.)  
 
-- 
Tom Schmidt 
 

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Re: New Opcodes

2008-01-30 Thread Anne Lynn Wheeler
The following message is a courtesy copy of an article
that has been posted to bit.listserv.ibm-main,alt.folklore.computers as well.


[EMAIL PROTECTED] (Tom Marchant) writes:
 There may have been speculation within IBM that Macrocode, and the 
 architecture that enabled it, was to make it easier to develop new features.  
 I 
 can tell you that I was at Amdahl at the time working on the 580.  That was 
 definitely a major reason for it.

re:
http://www.garlic.com/~lynn/2008c.html#29 New Opcodes
http://www.garlic.com/~lynn/2008c.html#32 New Opcodes
http://www.garlic.com/~lynn/2008c.html#33 New Opcodes
http://www.garlic.com/~lynn/2008c.html#35 New Opcodes

well, how should i have phrased it? ...

i would run into lots people ... including at the monthly SLAC meetings
... and frequently be asked for advice ... there was lots of issues
about not divulging confidences ... even confidences for companies i
didn't work for.

complicating things, i had a nearly complete set of individually serial
numbered (candy striped) 811 documents (i.e. architecture documents
named for their nov78 date).

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Re: New Opcodes

2008-01-29 Thread Anne Lynn Wheeler
The following message is a courtesy copy of an article
that has been posted to bit.listserv.ibm-main,alt.folklore.computers as well.


[EMAIL PROTECTED] (Tom Marchant) writes:
 It also says, 894 instructions (668 implemented entirely in hardware)

 The latest POO lists about 750 instructions.  I know that there are a few not 
 listed in the POO.  Still, it sounds like it's a lot over 50.

as per past discussions re the architecture red book (i.e. cms script
file where command line option would print the full machine architecture
or just the POO subset, full machine architecture was distributed in red
3ring binders) and compareswap instruction
http://www.garlic.com/~lynn/subtopic.html#smp

getting an instruction added could require a lot of justification.

so one way of parsing of the reference to 50+ added instructions to
improve compiled code efficiency ... could be referring to over 50 of
the added instructions were justified for improving compiled code
efficiency (w/o saying anything at all about the total number of added
instructions and/or what was the justification for any of the other
added instructions).

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Re: New Opcodes

2008-01-29 Thread Anne Lynn Wheeler
The following message is a courtesy copy of an article
that has been posted to bit.listserv.ibm-main,alt.folklore.computers as well.

Anne  Lynn Wheeler [EMAIL PROTECTED] writes:
 as an aside ... there was some similar speculation two decades ago about
 such stuff. there was even some speculation that one of the other clone
 processor vendors creation of macrocode was to enable them to quickly
 adapt to such things (be more agile in tracking, implementing, deploying
 changes).

re:
http://www.garlic.com/~lynn/2008c.html#29 New Opcdoes
http://www.garlic.com/~lynn/2008c.html#32 New Opcdoes

actually such speculation dates back three decades to the introduction
of cross-memory instructions and dual-address space mode on 3033

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Re: New Opcodes

2008-01-29 Thread Tom Marchant
On Tue, 29 Jan 2008 10:47:05 -0500, Anne  Lynn Wheeler wrote:

... there was even some speculation that one of the other clone
 processor vendors creation of macrocode was to enable them to quickly
 adapt to such things (be more agile in tracking, implementing, deploying
 changes).

There may have been speculation within IBM that Macrocode, and the 
architecture that enabled it, was to make it easier to develop new features.  I 
can tell you that I was at Amdahl at the time working on the 580.  That was 
definitely a major reason for it.


actually such speculation dates back three decades to the introduction
of cross-memory instructions and dual-address space mode on 3033

With the introduction of MVS/SE, Amdahl provided something called SE Assist, 
which provided software emulation of the new instructions that SE used.  
There was also a ZAP to NIP to no-op a TPROT instruction that seemed to be 
there only to prevent MVS/SE from IPLing on a processor without the new 
instructions.   When the 580 was being designed, the enhanced architecture 
of the processor allowed for such software emulation of new instructions in 
Macrocode without having to install code in the operating system.  This 
allowed instructions in NIP to be emulated.  The 580 also had an advanced 
channel architecture that made it much easier to implement the XA I/O 
subsystem. 

-- 
Tom Marchant

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Re: New Opcodes

2008-01-29 Thread Anne Lynn Wheeler
The following message is a courtesy copy of an article
that has been posted to bit.listserv.ibm-main,alt.folklore.computers as well.

Anne  Lynn Wheeler [EMAIL PROTECTED] writes:
 actually such speculation dates back three decades to the introduction
 of cross-memory instructions and dual-address space mode on 3033

re:
http://www.garlic.com/~lynn/2008c.html#29 New Opcdoes
http://www.garlic.com/~lynn/2008c.html#32 New Opcdoes
http://www.garlic.com/~lynn/2008c.html#33 New Opcdoes

part of the speculation was that the cross-memory/dual-address space
instructions used more STOs (segment table origins) simultaneously
... and the 3033 had inherited its TLB (and STO-associative)
implementation from 168.  The additional concurrent STO use activity was
putting pressure on TLB-miss and therefor performance.

one the other hand, large 168  3033 installation were facing enormous
pressure on amount of application addressable space ...

aka pasts posts about pointer passing paradigm from real memory heritage
dictated the SVS and subsequent MVS implementation with the kernel
appearing in the application address space. The MVS design included
moving (non-kernel) subsystems into their own address space
... dictating the common segment implementation (supporting squirreling
away data for pointer passing APIs). Larger installations were having to
constantly grow the common segment ... with 24bit addressing (16mbyte),
kernel taking up 8mbytes ... and the common segment growing from 4mbytes
to 5mbytes (and more) ... was only leave 3-4mbytes (or less) for
applications (even tho there was a virtual address space per
application).

the future system distraction had redirected a lot of effort
into non-370 activity
http://www.garlic.com/~lynn/subtopic.html#futuresys

when future system was killed, there was mad rush to get stuff back into
the 370 product pipeline. 370-xa was going to take 7-8 yrs (with 31-bit
addressing, access registers, program call  return, etc). the stop-gap
was 3033 ... which was 168 wiring/logic remapped to faster chip
technology.  The increasing machine capacity was adding more
applications, tending to grow the common segment and putting massive
pressure on available (virtual) memory for applications.

There was speculation that 3033 cross-memory and dual-address space
hardware changes was purely to create incompatibilities for the clone
processor vendors ... however there was more than enuf other
justification, even if the clone vendors hadn't existed at all
(intermediate step on the way to access registers) ... aka dual-address
space instructions allowed subsystem to reach directly into the calling
application's virtual address to direclty access values pointed to by
the passed pointers (w/o requiring the common segment hack).

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Re: New Opcodes

2008-01-29 Thread Anne Lynn Wheeler
The following message is a courtesy copy of an article
that has been posted to bit.listserv.ibm-main,alt.folklore.computers as well.


re:
http://www.garlic.com/~lynn/2008c.html#29 New Opcodes

justification is justification ... not all have to be there based on the
same justification.

as an aside ... there was some similar speculation two decades ago about
such stuff. there was even some speculation that one of the other clone
processor vendors creation of macrocode was to enable them to quickly
adapt to such things (be more agile in tracking, implementing, deploying
changes).

misc. past posts mentioning macrocode.
http://www.garlic.com/~lynn/2002p.html#44 Linux paging
http://www.garlic.com/~lynn/2002p.html#48 Linux paging
http://www.garlic.com/~lynn/2003.html#9 Mainframe System 
Programmer/Administrator market demand?
http://www.garlic.com/~lynn/2003.html#56 Wild hardware idea
http://www.garlic.com/~lynn/2005d.html#59 Misuse of word microcode
http://www.garlic.com/~lynn/2005d.html#60 Misuse of word microcode
http://www.garlic.com/~lynn/2005h.html#24 Description of a new old-fashioned 
programming language
http://www.garlic.com/~lynn/2005p.html#14 Multicores
http://www.garlic.com/~lynn/2005p.html#29 Documentation for the New 
Instructions for the z9 Processor
http://www.garlic.com/~lynn/2005u.html#40 POWER6 on zSeries?
http://www.garlic.com/~lynn/2005u.html#43 POWER6 on zSeries?
http://www.garlic.com/~lynn/2005u.html#48 POWER6 on zSeries?
http://www.garlic.com/~lynn/2006b.html#38 blast from the past ... macrocode
http://www.garlic.com/~lynn/2006c.html#9 Mainframe Jobs Going Away
http://www.garlic.com/~lynn/2006j.html#32 Code density and performance?
http://www.garlic.com/~lynn/2006j.html#35 Code density and performance?
http://www.garlic.com/~lynn/2006m.html#39 Using different storage key's
http://www.garlic.com/~lynn/2006p.html#42 old hypervisor email
http://www.garlic.com/~lynn/2006u.html#33 Assembler question
http://www.garlic.com/~lynn/2006u.html#34 Assembler question
http://www.garlic.com/~lynn/2006v.html#20 Ranking of non-IBM mainframe builders?
http://www.garlic.com/~lynn/2007b.html#1 How many 36-bit Unix ports in the old 
days?
http://www.garlic.com/~lynn/2007d.html#3 Has anyone ever used self-modifying 
microcode? Would it even be useful?
http://www.garlic.com/~lynn/2007d.html#9 Has anyone ever used self-modifying 
microcode? Would it even be useful?
http://www.garlic.com/~lynn/2007j.html#84 VLIW pre-history
http://www.garlic.com/~lynn/2007k.html#74 Non-Standard Mainframe Language?
http://www.garlic.com/~lynn/2007n.html#96 some questions about System z PR/SM

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Re: New Opcodes

2008-01-29 Thread Ed Gould

On Jan 29, 2008, at 8:00 AM, Anne  Lynn Wheeler wrote:
---SNIP--



getting an instruction added could require a lot of justification.

-SNIP---


Or is this new behavior on  IBM's part  to starve off the INTEL  
Emulator?


I think my idea makes more sense.

Ed

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Re: New Opcodes

2008-01-29 Thread McKown, John
 -Original Message-
 From: IBM Mainframe Discussion List 
 [mailto:[EMAIL PROTECTED] On Behalf Of Phil Payne
 Sent: Monday, January 28, 2008 5:43 AM
 To: IBM-MAIN@BAMA.UA.EDU
 Subject: New Opcodes
 
 
 New opcodes aren't something I worry too much about - I 
 managed to solve quite a few business
 problems with System/360.
 
 Now old opcodes - I hope they all stick around.
 
 The terminology used in the PDF file is interesting: 50+ 
 instructions added to improve
 compiled code efficiency.  It almost sounds like these will 
 be unpublished instructions foro
 use exclusively by IBM's compilers.

I hope not. I really __despise__ undocumented instructions. I don't know
why, but I do. I guess because I find computer architecture interesting.
But I don't see how a compiler can use an undocumented instruction. How
would I debug the program if the instruction gets an exception of some
sort? Or do source level, interactive, debugging at the assembler level?


And, if they are reserved for IBM only compilers, that is anti
competative. And what about GCC on Linux? I guess it would not be able
to use the instructions.

Undocumented, problem state, instructions are __EVIL__ as far as I am
concerned. Yes, you've finally found something that I am a bit
passionate about grin.

 
 Down at metal level it's quite a different architecture.  I 
 wouldn't be surprised to see some
 object code optimized a little with special instructions.
 
 -- 
   Phil Payne

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Re: New Opcodes

2008-01-29 Thread Ed Finnell
 
In a message dated 1/29/2008 7:49:27 A.M. Central Standard Time,  
[EMAIL PROTECTED] writes:

I know that there are a few not 
listed in the POO.  Still, it  sounds like it's a lot over 50.



Those are just the graphics and sound   instructions for the GDDM replacement?







**Start the year off right.  Easy ways to stay in shape. 
http://body.aol.com/fitness/winter-exercise?NCID=aolcmp0030002489

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Re: New Opcodes

2008-01-29 Thread Tom Schmidt
On Tue, 29 Jan 2008 12:54:53 EST, Ed Finnell wrote:

Message dated 1/29/2008 7:49:27 A.M. CST, m42tom-ibmmain writes:

I know that there are a few not
listed in the POO.  Still, it  sounds like it's a lot over 50.

Those are just the graphics and sound   instructions for the GDDM 
replacement?
 
 
Oh, that makes sense -- the new PTF instruction must mean:
 Play The Flute
   (or Play The Fiddle?) 
 
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Re: New Opcodes

2008-01-29 Thread Ed Finnell
 
In a message dated 1/29/2008 12:06:27 P.M. Central Standard Time,  
[EMAIL PROTECTED] writes:

Play The Flute



Getting kind of silly but I liked-Plunk  Twanger Froggie or Push The FUD.







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Re: New Opcodes

2008-01-29 Thread Tom Marchant
On Mon, 28 Jan 2008 11:42:37 -, Phil Payne wrote:

The terminology used in the PDF file is interesting: 50+ instructions added 
to 
improve
compiled code efficiency.

It also says, 894 instructions (668 implemented entirely in hardware)

The latest POO lists about 750 instructions.  I know that there are a few not 
listed in the POO.  Still, it sounds like it's a lot over 50.

-- 
Tom Marchant

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Re: New Opcodes

2008-01-29 Thread Jon Brock
I think it's Pity The Fool.  It's a very dangerous op-code to attempt.

Not many people know that Mr. T moonlights as a hardware architect.

Jon



snip
 Second, there was one mnemonic that caught my eye.  I do not 
 know what it does, but it's probably one that none of us will 
 forget:  PTF.
 
 
 
 Keith E. Moe

Perform The Following? Maybe it is the long wanted execute immediate
instruction? Waiting with worm on tongue to read more.
/snip

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Re: New Opcodes

2008-01-29 Thread Chase, John
 -Original Message-
 From: IBM Mainframe Discussion List On Behalf Of Tom Schmidt
 
 On Tue, 29 Jan 2008 12:54:53 EST, Ed Finnell wrote:
 
 Message dated 1/29/2008 7:49:27 A.M. CST, m42tom-ibmmain writes:
 
 I know that there are a few not
 listed in the POO.  Still, it  sounds like it's a lot over 50.
 
 Those are just the graphics and sound   instructions for the GDDM 
 replacement?
  
  
 Oh, that makes sense -- the new PTF instruction must mean:
  Play The Flute
(or Play The Fiddle?) 

I doubt IBM would call it a Fiddle.  Violin would seem more their
style.  :-)

How about Point The Finger?

-jc-

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Re: New Opcodes

2008-01-28 Thread Timothy Sipples
As far as I know there are only two things IBM has said publicly about a
future mainframe processor, and I guess they could be the same or
different. Here's the first, from August:

http://www2.hursley.ibm.com/decimal/IBM-z6-mainframe-microprocessor-Webb.pdf


which says 50+ instructions added to improve compiled code efficiency.

The second is what the IBM CFO said in his prepared remarks concerning
IBM's 4th quarter, 2007 earnings.

Beyond that, I haven't seen any more information. So let's wait to see
if/when IBM says more, OK?

- - - - -
Timothy Sipples
IBM Consulting Enterprise Software Architect
Specializing in Software Architectures Related to System z
Based in Tokyo, Serving IBM Japan and IBM Asia-Pacific
E-Mail: [EMAIL PROTECTED]

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Re: New Opcodes

2008-01-28 Thread Shane
On Mon, 2008-01-28 at 18:23 +0900, Timothy Sipples wrote:

 Beyond that, I haven't seen any more information. So let's wait to see
 if/when IBM says more, OK?

Timothy, you'd have to be sleeping under blue plastic in a Tokyo park to
not have some idea of what's coming.
I gotta say that after all these years, I find the secret handshake
bullshit prior to announcements just a little puerile.

Jaundiced from from too years I guess.

Shane ...

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Re: New Opcodes

2008-01-28 Thread Bob Shannon
I guess I miss the point. A new processor is coming, details to follow. New 
opcodes are coming; watch for HLASM PTFs to support them. How does one code the 
new instructions? Wait for the POO. This is all out of sight, out of mind. 
Anyone who knows about this stuff can't discuss it, and frankly it shouldn't 
have been mentioned on this list.

Bob Shannon
Rocket Software

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Re: New Opcodes

2008-01-25 Thread Ted MacNEIL
 I am NOT going to post the list here, as that would be a violation of the 
 non-disclosure. 

You might already be in violation.


I tend to agree.
You could have just ended your ISV partnership with IBM!

-
Too busy driving to stop for gas!

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Re: New Opcodes

2008-01-25 Thread Edward Jaffe

Keith E. Moe wrote:
I am NOT going to post the list here, as that would be a violation of the non-disclosure. 


You might already be in violation.


First, there are some SIX letter mnemonics.  Historically, mnemonics had been 
limited to FIVE characters.
  


You've miscounted. (There should be a note describing what the + means.)

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Re: New Opcodes

2008-01-25 Thread McKown, John
 -Original Message-
 From: IBM Mainframe Discussion List 
 [mailto:[EMAIL PROTECTED] On Behalf Of Keith E. Moe
 Sent: Friday, January 25, 2008 3:12 PM
 To: IBM-MAIN@BAMA.UA.EDU
 Subject: New Opcodes
 
 
 IBM just posted the list of new mnemonics  that the HLASM 
 will soon support (and by inference, some new fangled type of 
 hardware) via their 
 vendor non-disclosure channel.
 
 I am NOT going to post the list here, as that would be a 
 violation of the non-disclosure.  However, I will post a 
 couple of observations that 
 hopefully won't get me in trouble.
 
 First, there are some SIX letter mnemonics.  Historically, 
 mnemonics had been limited to FIVE characters.
 
 Second, there was one mnemonic that caught my eye.  I do not 
 know what it does, but it's probably one that none of us will 
 forget:  PTF.
 
 
 
 Keith E. Moe

Perform The Following? Maybe it is the long wanted execute immediate
instruction? Waiting with worm on tongue to read more.

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Senior Systems Programmer
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