Re: ASMA034E
On Thu, 15 Nov 2018 22:22:31 -0500, Gord Tomlin wrote: >On 2018-11-15 16:43, Tom Marchant wrote: >> I believe that you can have a relative branch to a symbol in another >> CSECT that is resolved at binder time. > >Yes, if you include GOFF in your HLASM parameters. You will find that >when you specify GOFF, you will also need LIST(133) . > Wouldn't you think it would be able to figure that out for itself? -- gil -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: ASMA034E
On 2018-11-15 16:43, Tom Marchant wrote: I believe that you can have a relative branch to a symbol in another CSECT that is resolved at binder time. Yes, if you include GOFF in your HLASM parameters. You will find that when you specify GOFF, you will also need LIST(133) . -- Regards, Gord Tomlin Action Software International (a division of Mazda Computer Corporation) Tel: (905) 470-7113, Fax: (905) 470-6507 Support: https://actionsoftware.com/support/ -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: ASMA034E
Just habit. Just what I do. Charles -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf Of Steve Smith Sent: Thursday, November 15, 2018 3:34 PM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: ASMA034E A nitpick, but why would you change everything to Jxx except BAL/BAS? JAS would be more consistent. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: ASMA034E
AFAIK. Did you try? Charles -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf Of Paul Gilmartin Sent: Thursday, November 15, 2018 3:23 PM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: ASMA034E On Thu, 15 Nov 2018 15:43:12 -0600, Tom Marchant wrote: > >>If the programmer is so rash as to define an ENTRY point with an odd >>address, Bad Things can happen. > >I don't think that HLASM will allow you to do that. > How about: FRED CSECT DCC'A' JOE DCC'Data only; not executable.' ENTRY JOE END -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: ASMA034E
A nitpick, but why would you change everything to Jxx except BAL/BAS? JAS would be more consistent. IEABRC is pretty clever, but I've found it pretty quick to just rename all the B* to J* and clean up the exceptions. However, in my recent environment, virtually no branches of any kind were hard-coded; only some macro maintenance was needed. sas On Thu, Nov 15, 2018 at 11:34 AM Charles Mills wrote: > @Greg is right -- Jump is not a big learning curve with lots of gotchas > (unlike say 64-bit or AR mode). > > In addition to replacing Bxx with Jxx, you need to replace BAL with BRAS. > Again, works exactly the same, one-for-one, but no base register needed. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: ASMA034E
On Thu, 15 Nov 2018 15:43:12 -0600, Tom Marchant wrote: > >>If the programmer is so rash as to define an ENTRY point with an odd >>address, Bad Things can happen. > >I don't think that HLASM will allow you to do that. > How about: FRED CSECT DCC'A' JOE DCC'Data only; not executable.' ENTRY JOE END -- gil -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: RESMGR exit vs. end of task
This is an intentional change in APAR OA55657. You should see the same results on z/OS 2.1 with PTF UA97322. Jim Mulder z/OS Diagnosis, Design, Development, Test IBM Corp. Poughkeepsie NY "IBM Mainframe Discussion List" wrote on 11/15/2018 02:52:41 PM: > From: "Gary Weinhold" > To: IBM-MAIN@LISTSERV.UA.EDU > Date: 11/15/2018 05:23 PM > Subject: RESMGR exit vs. end of task > Sent by: "IBM Mainframe Discussion List" > > Our product is called as a subroutine of the user's program (usually > COBOL). Most of our code is user key, but on the first call for a task > we issue a PC to set a RESMGR exit. This exit allows us to freemain our > control blocks and close any datasets we may have opened whether the > task abends or not. > > Recently we observed that when a task abends, the DCBs/ACBs are already > closed when we get control in the RESMGR exit. We know this was not > true under z/OS 2.1, but has occurred on our z/OS 2.3 system and at a > customer site recently. This has no significant consequences because > all we do is issue a message. But I have not been able to find any > documentation which would have allowed us to anticipate this behavioural > change. So I thought I'd ask you all if you'd observed this or know > what changed.. > > Gary -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: ShopzSeries redirects to 404?
Tom, I agree in principle, but it does get attention! Wonder how long it's been upside down and I never noticed. And it introduces a little 'poke fun at myself' from IBM. Think this horse is dead... David On Thursday, November 15, 2018 Tom Brennan wrote: More seriously, I really wish they would change that upside down logo page. Not just the upside down IBM, but the whole thing could be more professional. A customer who needs something right away and gets a 404 (whoever's fault that is doesn't matter) probably isn't in the mood for a joke. On 11/15/2018 1:17 PM, David Purdy wrote: > Yes I saw the same, plus the IBM logo was upside down. I just assumed the > website was down under . > > David > On Thursday, November 15, 2018 Ambros, Thomas > wrote: > Anybody else having issues getting to shopz? This is what we're getting, > different browsers, different nets: > > https://www.ibm.com/;www-03.ibm.com//software/shopzseries/ShopzSeries_public.wss > > This isn't right... looks like it injects ';www-03.ibm.com/'. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: ShopzSeries redirects to 404?
I received an IBM page that said "patience is a virtue" before getting the 404 On Thu, Nov 15, 2018, 16:50 Tom Brennan More seriously, I really wish they would change that upside down logo > page. Not just the upside down IBM, but the whole thing could be more > professional. A customer who needs something right away and gets a 404 > (whoever's fault that is doesn't matter) probably isn't in the mood for > a joke. > > On 11/15/2018 1:17 PM, David Purdy wrote: > > Yes I saw the same, plus the IBM logo was upside down. I just assumed > the website was down under . > > > > David > > On Thursday, November 15, 2018 Ambros, Thomas > wrote: > > Anybody else having issues getting to shopz? This is what we're > getting, different browsers, different nets: > > > > > https://urldefense.proofpoint.com/v2/url?u=https-3A__www.ibm.com_-3Bwww-2D03.ibm.com__software_shopzseries_ShopzSeries-5Fpublic.wss&d=DwIDaQ&c=7f1YSuqIGbgL_Gzm5POfng&r=unuy1IauTT8_BnXaEWJu99tLgShEyROqbi1xNCvlPGQ&m=Wc64UaNFjCltSKt2otEeTVj1RC5g0aeIupEPyrBT9f8&s=u8p3fhxRmKAAJGp1hroX-el8fmTxDqXaahA21OFSCpQ&e= > > > > This isn't right... looks like it injects ';www-03.ibm.com/'. > > -- > For IBM-MAIN subscribe / signoff / archive access instructions, > send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN > -- ** Privileged and/or confidential information may be contained in this message. If you are not the addressee indicated in this message (or are not responsible for delivery of this message to that person), you may not copy or deliver this message to anyone. In such case, you should destroy this message and notify the sender by reply e-mail. If you or your employer do not consent to Internet e-mail for messages of this kind, please advise the sender. Shaw Industries does not provide or endorse any opinions, conclusions or other information in this message that do not relate to the official business of the company or its subsidiaries. ** -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: ASMA034E
> I believe that you can have a relative branch to a symbol in another > CSECT that is resolved at binder time. You can but you need the enhanced object code format to do that. GOFF? Some such thing. >If the programmer is so rash as to define an ENTRY point with an odd >address, Bad Things can happen. I am pretty certain HLASM will let you do that, and there is nothing inherently wrong with that. It is not a Bad Thing. (Arguably bad programming style, but not bad technology if you will). Instructions of course cannot be on an odd boundary, so an instruction-type entry point also cannot. That is an instruction issue. An entry can be odd, provided it is a variable or constant. AFAIK HLASM fully supports. I once played with absolute entry points, but I have forgotten the outcome. The idea was that a "parameter" or customization type module might contain BUFFLEN EQU 5000/ENTRY BUFFLEN. Then in a functional module one might code L R0,=A(BUFFLEN)/GETMAIN ... Charles -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf Of Tom Marchant Sent: Thursday, November 15, 2018 1:43 PM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: ASMA034E On Thu, 15 Nov 2018 13:21:01 -0600, Paul Gilmartin wrote: >On Thu, 15 Nov 2018 12:38:05 -0600, Tom Marchant wrote: > >>On Thu, 15 Nov 2018 08:33:55 -0800, Charles Mills wrote: >> >>>LARL is also very cool. It is like LA without a base register. >> >>Agreed. One thing to be aware of with LARL. It uses a signed >>halfword that is added to the current PSW address. As a result >>it cannot be used to get the address of an odd address. ... >> >I believe the stumbling block is not the signedness but that the >displacement is multiplied by 2 in order to double the reach. Right. The fact that it is signed allows references forward or backward. I neglected to say that the signed offset is in halfwords, and so it is multiplied by 2. Thanks for the correction. > >>... Nor can it be used to get an address in a DSECT, or in a CSECT that >>is not part of the same load module. >> >The requires using the result from STORAGE; the latter a V-constant. > >Is Binder nowadays savvy to RL displacements to honor RLD entries? I believe that you can have a relative branch to a symbol in another CSECT that is resolved at binder time. I'm not sure if that is what you mean. I haven't used it, so I'm not writing this from experience. >If the programmer is so rash as to define an ENTRY point with an odd >address, Bad Things can happen. I don't think that HLASM will allow you to do that. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: ShopzSeries redirects to 404?
More seriously, I really wish they would change that upside down logo page. Not just the upside down IBM, but the whole thing could be more professional. A customer who needs something right away and gets a 404 (whoever's fault that is doesn't matter) probably isn't in the mood for a joke. On 11/15/2018 1:17 PM, David Purdy wrote: Yes I saw the same, plus the IBM logo was upside down. I just assumed the website was down under . David On Thursday, November 15, 2018 Ambros, Thomas wrote: Anybody else having issues getting to shopz? This is what we're getting, different browsers, different nets: https://www.ibm.com/;www-03.ibm.com//software/shopzseries/ShopzSeries_public.wss This isn't right... looks like it injects ';www-03.ibm.com/'. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: ASMA034E
On Thu, 15 Nov 2018 13:21:01 -0600, Paul Gilmartin wrote: >On Thu, 15 Nov 2018 12:38:05 -0600, Tom Marchant wrote: > >>On Thu, 15 Nov 2018 08:33:55 -0800, Charles Mills wrote: >> >>>LARL is also very cool. It is like LA without a base register. >> >>Agreed. One thing to be aware of with LARL. It uses a signed >>halfword that is added to the current PSW address. As a result >>it cannot be used to get the address of an odd address. ... >> >I believe the stumbling block is not the signedness but that the >displacement is multiplied by 2 in order to double the reach. Right. The fact that it is signed allows references forward or backward. I neglected to say that the signed offset is in halfwords, and so it is multiplied by 2. Thanks for the correction. > >>... Nor can it be used to get an address in a DSECT, or in a CSECT that >>is not part of the same load module. >> >The requires using the result from STORAGE; the latter a V-constant. > >Is Binder nowadays savvy to RL displacements to honor RLD entries? I believe that you can have a relative branch to a symbol in another CSECT that is resolved at binder time. I'm not sure if that is what you mean. I haven't used it, so I'm not writing this from experience. >If the programmer is so rash as to define an ENTRY point with an odd >address, Bad Things can happen. I don't think that HLASM will allow you to do that. -- Tom Marchant -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: ShopzSeries redirects to 404?
Surely a Hack-even the most loathsome PFCSK would do a blink test. In a message dated 11/15/2018 3:17:44 PM Central Standard Time, 00ac4b1d56b3-dmarc-requ...@listserv.ua.edu writes: Yes I saw the same, plus the IBM logo was upside down. I just assumed the website was down under . -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: ShopzSeries redirects to 404?
Yes I saw the same, plus the IBM logo was upside down. I just assumed the website was down under . David On Thursday, November 15, 2018 Ambros, Thomas wrote: Anybody else having issues getting to shopz? This is what we're getting, different browsers, different nets: https://www.ibm.com/;www-03.ibm.com//software/shopzseries/ShopzSeries_public.wss This isn't right... looks like it injects ';www-03.ibm.com/'. Thomas Ambros zEnterprise Operating Systems zEnterprise Systems Management 518-436-6433 This communication may contain privileged and/or confidential information. It is intended solely for the use of the addressee. If you are not the intended recipient, you are strictly prohibited from disclosing, copying, distributing or using any of this information. If you received this communication in error, please contact the sender immediately and destroy the material in its entirety, whether electronic or hard copy. This communication may contain nonpublic personal information about consumers subject to the restrictions of the Gramm-Leach-Bliley Act. You may not directly or indirectly reuse or redisclose such information for any purpose other than to provide the services for which you are receiving the information. 127 Public Square, Cleveland, OH 44114 If you prefer not to receive future e-mail offers for products or services from Key send an e-mail to mailto:dnereque...@key.com with 'No Promotional E-mails' in the SUBJECT line. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Question on TNF start up in V2R3 z/OS
For both 2.1 and 2.3 we have SUBSYS SUBNAME(TNF) /* IBM TCP/IP */ No problems on our side. I am curious about your SEZALOAD. You say that it's added to link list *after* NIP. Like all other PDSE libraries, we have it in PROGxx. That's particularly important for a subsystem that names an initialization routine; apparently not true in this case, but we did have some issues with startup of other tasks in 2.3 that we had not seen before. . . J.O.Skip Robinson Southern California Edison Company Electric Dragon Team Paddler SHARE MVS Program Co-Manager 323-715-0595 Mobile 626-543-6132 Office ⇐=== NEW robin...@sce.com -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf Of Jake Anderson Sent: Thursday, November 15, 2018 10:34 AM To: IBM-MAIN@LISTSERV.UA.EDU Subject: (External):Re: Question on TNF start up in V2R3 z/OS Lizette, Just one test, Can you add the IEFSSN entry dynamically and try starting TNF ? See if it comes up ? On Thu 15 Nov, 2018, 9:48 PM Lizette Koehler Cross posted to TCPIP/IBMMAIN > > List - > > When I IPL z/OS V2.1 TNF comes up correctly. > > When I IPL z/OS V2.3 TNF fails to start. I get a message saying it is > not in the IEFSSNxx - but it is the same IEFSSNxx member for 2.1 and > 2.3. > > So has anyone run across this issue in 2.3? > > The message is: EZY6014E Node/Subsystem name in IEFSSNxx is not TNF > > The SEZALOAD is in the linklist (activated later in the IPL Process > with all of our PDSE Linklst datasets) > > The TNF is in the IEFSSNxx member > > This is not making sense. With the exception of the level of z/OS it > is the same at IPL time. > > Thanks > > > Lizette > A theory can never be proven, but it can be falsified. Karl Raimund > Popper -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
RESMGR exit vs. end of task
Our product is called as a subroutine of the user's program (usually COBOL). Most of our code is user key, but on the first call for a task we issue a PC to set a RESMGR exit. This exit allows us to freemain our control blocks and close any datasets we may have opened whether the task abends or not. Recently we observed that when a task abends, the DCBs/ACBs are already closed when we get control in the RESMGR exit. We know this was not true under z/OS 2.1, but has occurred on our z/OS 2.3 system and at a customer site recently. This has no significant consequences because all we do is issue a message. But I have not been able to find any documentation which would have allowed us to anticipate this behavioural change. So I thought I'd ask you all if you'd observed this or know what changed.. Gary Gary Weinhold Senior Application Architect DATAKINETICS | Data Performance & Optimization Phone +1.613.523.5500 x216 Email: weinh...@dkl.com Visit us online at www.DKL.com E-mail Notification: The information contained in this email and any attachments is confidential and may be subject to copyright or other intellectual property protection. If you are not the intended recipient, you are not authorized to use or disclose this information, and we request that you notify us by reply mail or telephone and delete the original message from your mail system. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: ASMA034E
On Thu, 15 Nov 2018 12:38:05 -0600, Tom Marchant wrote: >On Thu, 15 Nov 2018 08:33:55 -0800, Charles Mills wrote: > >>LARL is also very cool. It is like LA without a base register. > >Agreed. One thing to be aware of with LARL. It uses a signed >halfword that is added to the current PSW address. As a result >it cannot be used to get the address of an odd address. ... > I believe the stumbling block is not the signedness but that the displacement is multiplied by 2 in order to double the reach. >... Nor can it be used to get an address in a DSECT, or in a CSECT that >is not part of the same load module. > The requires using the result from STORAGE; the latter a V-constant. Is Binder nowadays savvy to RL displacements to honor RLD entries? If the programmer is so rash as to define an ENTRY point with an odd address, Bad Things can happen. >There are still situations where LA is appropriate. > >There is no need to change every Branch instruction to Branch >Relative (Jump) in order to start using relative instructions. If you >are changing an existing program you can code any new branches >as branch relative, except for the situation where you want to use >an indexed branch. > A compiler can make the choice of format to use to minimize I-fetch bandwidth. -- gil -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: ASMA034E
On Thu, 15 Nov 2018 08:33:55 -0800, Charles Mills wrote: >LARL is also very cool. It is like LA without a base register. Agreed. One thing to be aware of with LARL. It uses a signed halfword that is added to the current PSW address. As a result it cannot be used to get the address of an odd address. Nor can it be used to get an address in a DSECT, or in a CSECT that is not part of the same load module. There are still situations where LA is appropriate. There is no need to change every Branch instruction to Branch Relative (Jump) in order to start using relative instructions. If you are changing an existing program you can code any new branches as branch relative, except for the situation where you want to use an indexed branch. -- Tom Marchant -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Question on TNF start up in V2R3 z/OS
Lizette, Just one test, Can you add the IEFSSN entry dynamically and try starting TNF ? See if it comes up ? On Thu 15 Nov, 2018, 9:48 PM Lizette Koehler Cross posted to TCPIP/IBMMAIN > > List - > > When I IPL z/OS V2.1 TNF comes up correctly. > > When I IPL z/OS V2.3 TNF fails to start. I get a message saying it is not > in > the IEFSSNxx - but it is the same IEFSSNxx member for 2.1 and 2.3. > > So has anyone run across this issue in 2.3? > > The message is: EZY6014E Node/Subsystem name in IEFSSNxx is not TNF > > The SEZALOAD is in the linklist (activated later in the IPL Process with > all of > our PDSE Linklst datasets) > > The TNF is in the IEFSSNxx member > > This is not making sense. With the exception of the level of z/OS it is > the > same at IPL time. > > Thanks > > > Lizette > A theory can never be proven, but it can be falsified. Karl Raimund Popper > > -- > For IBM-MAIN subscribe / signoff / archive access instructions, > send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN > -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: ShopzSeries redirects to 404?
John, Are they preparing for Black Friday??? _ Dave Jousma Mainframe Engineering, Assistant Vice President david.jou...@53.com 1830 East Paris, Grand Rapids, MI 49546 MD RSCB2H p 616.653.8429 f 616.653.2717 -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf Of John Eells Sent: Thursday, November 15, 2018 1:03 PM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: ShopzSeries redirects to 404? **CAUTION EXTERNAL EMAIL** **DO NOT open attachments or click on links from unknown senders or unexpected emails** The problem is on our end. The team supporting the Shopz servers is aware of it and working on it. Ambros, Thomas wrote: > Anybody else having issues getting to shopz? This is what we're getting, > different browsers, different nets: > > https://www.ibm.com/;www-03.ibm.com//software/shopzseries/ShopzSeries_ > public.wss > > This isn't right... looks like it injects ';www-03.ibm.com/'. > -- John Eells IBM Poughkeepsie ee...@us.ibm.com -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN **CAUTION EXTERNAL EMAIL** **DO NOT open attachments or click on links from unknown senders or unexpected emails** This e-mail transmission contains information that is confidential and may be privileged. It is intended only for the addressee(s) named above. If you receive this e-mail in error, please do not read, copy or disseminate it in any manner. If you are not the intended recipient, any disclosure, copying, distribution or use of the contents of this information is prohibited. Please reply to the message immediately by informing the sender that the message was misdirected. After replying, please erase it from your computer system. Your assistance in correcting this error is appreciated. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: ASMA034E
So where you have a problem with what is generated, turn off IEABRCX. Then turn it back on. The documentation explains this. The macro could only have so much smarts. Sent from my iPhone — small keyboarf, fat fungrs, stupd spell manglr. Expct mistaks > On Nov 15, 2018, at 11:33 AM, Charles Mills wrote: > > @Greg is right -- Jump is not a big learning curve with lots of gotchas > (unlike say 64-bit or AR mode). > > In addition to replacing Bxx with Jxx, you need to replace BAL with BRAS. > Again, works exactly the same, one-for-one, but no base register needed. > > LARL is also very cool. It is like LA without a base register. If you code LA > R1,FOO you first need a base register pointing to FOO (assuming FOO is not a > numeric constant). If you code LARL R1,FOO you do not. > > I am personally not fond of IEABRCX. The whole point of assembler is tight > control of the generated machine code; not compiler magic. It is not hard at > all to do CHG B J PREFIX and work through them one at a time either accepting > each proposed change or finding the next. Or CHG BE JE WORD and work through > all of the BH, BL, BNE and so forth. Anything you miss is easy to find: > you'll get an addressability error message from the assembler. > > I am not absolutely positive -- I fixed my problem and moved on -- but I > *think* IEACBRCX fouled up the LE entry macro EDCPRLG. I *think* something in > LE was expecting to see a 47 opcode specifically. > > I also prefer the use of LOCTR to LARL Rn,STATIC but different strokes for > different folks. > > Charles > > > -Original Message- > From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On > Behalf Of Greg Price > Sent: Thursday, November 15, 2018 7:18 AM > To: IBM-MAIN@LISTSERV.UA.EDU > Subject: Re: ASMA034E > >> On 2018-11-16 1:47 AM, Ward Able, Grant wrote: >> Can someone point me to a reasonably simple example? > > If you can do branch instructions then you can do branch-relative > instructions. Apart from RR instructions (BR, BASR, BALR, BASSM, BSM, > BAKR and any others I've missed) replace the B that starts the branch > instruction mnemonic with BR, or as I prefer to do, with J (for jump). > > eg. BNH -> JNH and BCT -> JCT and BAS -> JAS etc. > > Put all the stuff which needs to be cover by a base register after all > the instructions, and start the area with a label, and "use" that. > > eg. > LARL R11,Static > USING Static,R11 > ... > > Static DC 0D My module's constants and literals and non-RENT variables > > > Then all you need to cover is code generated by macros, which is why > Peter mentioned ARCHLVL (look up the SYSSTATE macro) to cover macros > with logic to test it, and the IEABRCX macro to cover the rest. > > IEABRCX DEFINE > will define and activate the facility where the older "branch" > instructions will be converted to newer "branch relative" instructions > when encountered by the assembler in the source code. With IEABRCX you > could even leave the old branch source code as-is, but personally I > prefer to use the newer mnemonics to make it obvious that the code is > probably not covered by a base register, and to keep the listing a bit > tidier. > > IEABRCX is "better" than IEABRC because you can turn it on and off as > needed. The most well known scenario where you might was to turn it off > (I'd say) is if you have a branch table where you use the index register > of the branch-on-condition instruction to provide an index into a table > of branch (or even jump) instructions. > > That's probably enough to get you started. Have fun with it. > > Cheers, > Greg P. > > -- > For IBM-MAIN subscribe / signoff / archive access instructions, > send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN > > -- > For IBM-MAIN subscribe / signoff / archive access instructions, > send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: ShopzSeries redirects to 404?
The problem is on our end. The team supporting the Shopz servers is aware of it and working on it. Ambros, Thomas wrote: Anybody else having issues getting to shopz? This is what we're getting, different browsers, different nets: https://www.ibm.com/;www-03.ibm.com//software/shopzseries/ShopzSeries_public.wss This isn't right... looks like it injects ';www-03.ibm.com/'. -- John Eells IBM Poughkeepsie ee...@us.ibm.com -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Question on TNF start up in V2R3 z/OS
Cross posted to TCPIP/IBMMAIN List - When I IPL z/OS V2.1 TNF comes up correctly. When I IPL z/OS V2.3 TNF fails to start. I get a message saying it is not in the IEFSSNxx - but it is the same IEFSSNxx member for 2.1 and 2.3. So has anyone run across this issue in 2.3? The message is: EZY6014E Node/Subsystem name in IEFSSNxx is not TNF The SEZALOAD is in the linklist (activated later in the IPL Process with all of our PDSE Linklst datasets) The TNF is in the IEFSSNxx member This is not making sense. With the exception of the level of z/OS it is the same at IPL time. Thanks Lizette A theory can never be proven, but it can be falsified. Karl Raimund Popper -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: ASMA034E
Thanks a lot Greg. I am sure to have fun with that! Regards – Grant DTCC Internal (Green) -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf Of Greg Price Sent: 15 November 2018 15:18 To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: ASMA034E ATTENTION! This email originated outside of DTCC; exercise caution. On 2018-11-16 1:47 AM, Ward Able, Grant wrote: > Can someone point me to a reasonably simple example? If you can do branch instructions then you can do branch-relative instructions. Apart from RR instructions (BR, BASR, BALR, BASSM, BSM, BAKR and any others I've missed) replace the B that starts the branch instruction mnemonic with BR, or as I prefer to do, with J (for jump). eg. BNH -> JNH and BCT -> JCT and BAS -> JAS etc. Put all the stuff which needs to be cover by a base register after all the instructions, and start the area with a label, and "use" that. eg. LARL R11,Static USING Static,R11 ... Static DC 0D My module's constants and literals and non-RENT variables Then all you need to cover is code generated by macros, which is why Peter mentioned ARCHLVL (look up the SYSSTATE macro) to cover macros with logic to test it, and the IEABRCX macro to cover the rest. IEABRCX DEFINE will define and activate the facility where the older "branch" instructions will be converted to newer "branch relative" instructions when encountered by the assembler in the source code. With IEABRCX you could even leave the old branch source code as-is, but personally I prefer to use the newer mnemonics to make it obvious that the code is probably not covered by a base register, and to keep the listing a bit tidier. IEABRCX is "better" than IEABRC because you can turn it on and off as needed. The most well known scenario where you might was to turn it off (I'd say) is if you have a branch table where you use the index register of the branch-on-condition instruction to provide an index into a table of branch (or even jump) instructions. That's probably enough to get you started. Have fun with it. Cheers, Greg P. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN DTCC DISCLAIMER: This email and any files transmitted with it are confidential and intended solely for the use of the individual or entity to whom they are addressed. If you have received this email in error, please notify us immediately and delete the email and any attachments from your system. The recipient should check this email and any attachments for the presence of viruses. The company accepts no liability for any damage caused by any virus transmitted by this email. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: ASMA034E
On Nov 15, 2018, at 10:33 AM, Charles Mills wrote: > > I am personally not fond of IEABRCX. The whole point of assembler is tight > control of the generated machine code; not compiler magic. It is not hard at > all to do CHG B J PREFIX and work through them one at a time either accepting > each proposed change or finding the next. Or CHG BE JE WORD and work through > all of the BH, BL, BNE and so forth. Anything you miss is easy to find: > you'll get an addressability error message from the assembler. > I would always use Jxx in code I write myself, but IEABRCX is useful if you’re using older macros that haven’t been updated to take ARCHLVL into account. -- Pew, Curtis G curtis@austin.utexas.edu ITS Systems/Core/Administrative Services -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: ASMA034E
Or you can just put CODE LOCTR before your entry point instruction. Here is the slightly edited beginning of one of my modules. This gets the copyright constant first in the object code, and avoids any extra branches. (ABEND EDCPRLG is an entry point.) CZ4MIA$L CSECT SYSSTATE ARCHLVL=2,OSREL=ZOSV1R6V1R9 makes no difference? DATA LOCTR , DCC'Copyright 2010, 2015, 2016 CorreLog Inc.' CODE LOCTR , ABENDEDCPRLG DSALEN=CDSALEN,BASEREG=NONE LARL R12,CZ4MIA$L USING CZ4MIA$L,R12 Etc. Charles -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf Of Tom Marchant Sent: Thursday, November 15, 2018 8:28 AM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: ASMA034E On Fri, 16 Nov 2018 02:17:47 +1100, Greg Price wrote: >On 2018-11-16 1:47 AM, Ward Able, Grant wrote: >> Can someone point me to a reasonably simple example? > >If you can do branch instructions then you can do branch-relative >instructions. Apart from RR instructions (BR, BASR, BALR, BASSM, BSM, >BAKR and any others I've missed) replace the B that starts the branch >instruction mnemonic with BR, or as I prefer to do, with J (for jump). > >eg. BNH -> JNH and BCT -> JCT and BAS -> JAS etc. The only thing that you can't do is an indexed branch, where you use a base register and an index register. >Put all the stuff which needs to be cover by a base register after all >the instructions, and start the area with a label, and "use" that. That's one way to do it. Another is to consolidate all the constants at the beginning of the program using LOCTR. For example, like this: PROGNAME J START DATA LOCTR -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
ShopzSeries redirects to 404?
Anybody else having issues getting to shopz? This is what we're getting, different browsers, different nets: https://www.ibm.com/;www-03.ibm.com//software/shopzseries/ShopzSeries_public.wss This isn't right... looks like it injects ';www-03.ibm.com/'. Thomas Ambros zEnterprise Operating Systems zEnterprise Systems Management 518-436-6433 This communication may contain privileged and/or confidential information. It is intended solely for the use of the addressee. If you are not the intended recipient, you are strictly prohibited from disclosing, copying, distributing or using any of this information. If you received this communication in error, please contact the sender immediately and destroy the material in its entirety, whether electronic or hard copy. This communication may contain nonpublic personal information about consumers subject to the restrictions of the Gramm-Leach-Bliley Act. You may not directly or indirectly reuse or redisclose such information for any purpose other than to provide the services for which you are receiving the information. 127 Public Square, Cleveland, OH 44114 If you prefer not to receive future e-mail offers for products or services from Key send an e-mail to mailto:dnereque...@key.com with 'No Promotional E-mails' in the SUBJECT line. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: ASMA034E
@Greg is right -- Jump is not a big learning curve with lots of gotchas (unlike say 64-bit or AR mode). In addition to replacing Bxx with Jxx, you need to replace BAL with BRAS. Again, works exactly the same, one-for-one, but no base register needed. LARL is also very cool. It is like LA without a base register. If you code LA R1,FOO you first need a base register pointing to FOO (assuming FOO is not a numeric constant). If you code LARL R1,FOO you do not. I am personally not fond of IEABRCX. The whole point of assembler is tight control of the generated machine code; not compiler magic. It is not hard at all to do CHG B J PREFIX and work through them one at a time either accepting each proposed change or finding the next. Or CHG BE JE WORD and work through all of the BH, BL, BNE and so forth. Anything you miss is easy to find: you'll get an addressability error message from the assembler. I am not absolutely positive -- I fixed my problem and moved on -- but I *think* IEACBRCX fouled up the LE entry macro EDCPRLG. I *think* something in LE was expecting to see a 47 opcode specifically. I also prefer the use of LOCTR to LARL Rn,STATIC but different strokes for different folks. Charles -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf Of Greg Price Sent: Thursday, November 15, 2018 7:18 AM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: ASMA034E On 2018-11-16 1:47 AM, Ward Able, Grant wrote: > Can someone point me to a reasonably simple example? If you can do branch instructions then you can do branch-relative instructions. Apart from RR instructions (BR, BASR, BALR, BASSM, BSM, BAKR and any others I've missed) replace the B that starts the branch instruction mnemonic with BR, or as I prefer to do, with J (for jump). eg. BNH -> JNH and BCT -> JCT and BAS -> JAS etc. Put all the stuff which needs to be cover by a base register after all the instructions, and start the area with a label, and "use" that. eg. LARL R11,Static USING Static,R11 ... Static DC 0D My module's constants and literals and non-RENT variables Then all you need to cover is code generated by macros, which is why Peter mentioned ARCHLVL (look up the SYSSTATE macro) to cover macros with logic to test it, and the IEABRCX macro to cover the rest. IEABRCX DEFINE will define and activate the facility where the older "branch" instructions will be converted to newer "branch relative" instructions when encountered by the assembler in the source code. With IEABRCX you could even leave the old branch source code as-is, but personally I prefer to use the newer mnemonics to make it obvious that the code is probably not covered by a base register, and to keep the listing a bit tidier. IEABRCX is "better" than IEABRC because you can turn it on and off as needed. The most well known scenario where you might was to turn it off (I'd say) is if you have a branch table where you use the index register of the branch-on-condition instruction to provide an index into a table of branch (or even jump) instructions. That's probably enough to get you started. Have fun with it. Cheers, Greg P. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: ASMA034E
On Fri, 16 Nov 2018 02:17:47 +1100, Greg Price wrote: >On 2018-11-16 1:47 AM, Ward Able, Grant wrote: >> Can someone point me to a reasonably simple example? > >If you can do branch instructions then you can do branch-relative >instructions. Apart from RR instructions (BR, BASR, BALR, BASSM, BSM, >BAKR and any others I've missed) replace the B that starts the branch >instruction mnemonic with BR, or as I prefer to do, with J (for jump). > >eg. BNH -> JNH and BCT -> JCT and BAS -> JAS etc. The only thing that you can't do is an indexed branch, where you use a base register and an index register. >Put all the stuff which needs to be cover by a base register after all >the instructions, and start the area with a label, and "use" that. That's one way to do it. Another is to consolidate all the constants at the beginning of the program using LOCTR. For example, like this: PROGNAME J START DATA LOCTR (any eyecatcher data that you want at the beginning of your program) CODE LOCTR STARTSTM 14,12,12(13) or whatever method you use to save the registers LARL 12,PROGNAME establish base register for the program USING PROGNAME,12 Register 12 is just an example (more code) DATA LOCTR (constants for the main routine) CODE LOCTR (code for the first subroutine) DATA LOCTR (constants for the first subroutine) CODE LOCTR (code for the second subroutine) DATA LOCTR (constants for the second subroutine) ... LTORG "DATA" and "CODE" are arbitrary labels that are used to name the location counters that you need for your program. The assembler will consolidate all of the sections that use the same named location counter together, and will put them together in the order that each named location counter is first used. Because "DATA" is the first one used in the program, all DATA will be before all CODE. There is also an unnamed location counter that is used for the first instruction (J START). -- Tom Marchant -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: ASMA034E
On 2018-11-16 1:47 AM, Ward Able, Grant wrote: Can someone point me to a reasonably simple example? If you can do branch instructions then you can do branch-relative instructions. Apart from RR instructions (BR, BASR, BALR, BASSM, BSM, BAKR and any others I've missed) replace the B that starts the branch instruction mnemonic with BR, or as I prefer to do, with J (for jump). eg. BNH -> JNH and BCT -> JCT and BAS -> JAS etc. Put all the stuff which needs to be cover by a base register after all the instructions, and start the area with a label, and "use" that. eg. LARL R11,Static USING Static,R11 ... Static DC 0D My module's constants and literals and non-RENT variables Then all you need to cover is code generated by macros, which is why Peter mentioned ARCHLVL (look up the SYSSTATE macro) to cover macros with logic to test it, and the IEABRCX macro to cover the rest. IEABRCX DEFINE will define and activate the facility where the older "branch" instructions will be converted to newer "branch relative" instructions when encountered by the assembler in the source code. With IEABRCX you could even leave the old branch source code as-is, but personally I prefer to use the newer mnemonics to make it obvious that the code is probably not covered by a base register, and to keep the listing a bit tidier. IEABRCX is "better" than IEABRC because you can turn it on and off as needed. The most well known scenario where you might was to turn it off (I'd say) is if you have a branch table where you use the index register of the branch-on-condition instruction to provide an index into a table of branch (or even jump) instructions. That's probably enough to get you started. Have fun with it. Cheers, Greg P. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: ASMA034E
I have been following the ASMA034E discussion and am interested in learning how to do the new-fangled relative branching stuff. Can someone point me to a reasonably simple example? I learned my Assembler in the 80's and have been using that way of coding ever since. I think it is time to upgrade my so-called skills. Regards - Grant DTCC Internal (Green) -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf Of Peter Relson Sent: 15 November 2018 12:45 To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: ASMA034E ATTENTION! This email originated outside of DTCC; exercise caution. A more modern (over 20 years old by now?) would suggest not having a USING for your "code" at all, but rather using relative branch with one register set up to point to your static data and a USING for that. It is relatively infrequent that your static data would exceed 4K, and even if it did you could often use long-displacement instructions to access any data that is more than 4K from the beginning. In some cases you might be able to take advantage of the "immediate" instructions and not even need access to static data. The IEABRCX macro can help in modules that want to use relative branch, particularly if they invoke system macros. Also be sure to identify the architecture level that macros are allowed to assume you are running with, via SYSSTATE ARCHLVL=. Some macro expansions might need local code register addressability, but that is usually easy to provide. Peter Relson z/OS Core Technology Design -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN DTCC DISCLAIMER: This email and any files transmitted with it are confidential and intended solely for the use of the individual or entity to whom they are addressed. If you have received this email in error, please notify us immediately and delete the email and any attachments from your system. The recipient should check this email and any attachments for the presence of viruses. The company accepts no liability for any damage caused by any virus transmitted by this email. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: ASMA034E
The other key tool for eliminating excessive base register dependencies is LOCTR. Too long a topic for an e-mail, but LOCTR lets you code instructions in whatever order you prefer, such as putting DC's at the "bottom," and lets you use LTORG in the normal fashion -- while still putting everything that might require base register addressability (such as DC's and literals and possibly executed instructions) well within the first 4K of the CSECT. Look it up in the assembler manual and/or search for a SHARE presentation. Charles -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf Of Peter Relson Sent: Thursday, November 15, 2018 4:45 AM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: ASMA034E A more modern (over 20 years old by now?) would suggest not having a USING for your "code" at all, but rather using relative branch with one register set up to point to your static data and a USING for that. It is relatively infrequent that your static data would exceed 4K, and even if it did you could often use long-displacement instructions to access any data that is more than 4K from the beginning. In some cases you might be able to take advantage of the "immediate" instructions and not even need access to static data. The IEABRCX macro can help in modules that want to use relative branch, particularly if they invoke system macros. Also be sure to identify the architecture level that macros are allowed to assume you are running with, via SYSSTATE ARCHLVL=. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: ASMA034E
On Nov 15, 2018, at 6:44 AM, Peter Relson wrote: > > A more modern (over 20 years old by now?) would suggest not having a USING > for your "code" at all, but rather using relative branch with one register > set up to point to your static data and a USING for that. It is relatively > infrequent that your static data would exceed 4K, and even if it did you > could often use long-displacement instructions to access any data that is > more than 4K from the beginning. In some cases you might be able to take > advantage of the "immediate" instructions and not even need access to > static data. > > The IEABRCX macro can help in modules that want to use relative branch, > particularly if they invoke system macros. > Also be sure to identify the architecture level that macros are allowed to > assume you are running with, via SYSSTATE ARCHLVL=. > > Some macro expansions might need local code register addressability, but > that is usually easy to provide. > +1 As I’ve had occasion to maintain assembler routines, I’ve tried to do this. It makes the code cleaner and I believe (I haven’t tested) it makes it run faster. -- Pew, Curtis G curtis@austin.utexas.edu ITS Systems/Core/Administrative Services -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: automatic tape library - DR
Dean, You say you only have "stand alone tape drives" at the DR location. Are they defined as MTL devices (Manual Tape Library)? They would be defined in the I/O Gen. Or are you using the same I/O Gen as your home location and these devices are genned to be inside a robotic device? If the I/O Gen says the device must be in a library, it must be in a library. Russell Witt res09...@verizon.net -Original Message- From: Nai, Dean To: IBM-MAIN Sent: Wed, Nov 14, 2018 2:08 pm Subject: automatic tape library - DR Hi, Did anyone ever run into this problem at a DR site? At our production site we have an automated tape library that looks like this: TAPELIB1 AL 3584-L22888 248 6 113 Y Y When we bring our LPAR up in DR we are getting an IGD330I Library Logical Type Not Defined. IGD306I Return code=12 Reason code=65 At the DR site we don't have a library, only stand alone tape drives. When I looked at the library in OAM the lib type was UNK. Any thoughts. Dean Nai > -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: Ask the experts about running things
Thanks for the links and some of the definitions provided, I will pass this information along to the programmer. -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: ASMA034E
A more modern (over 20 years old by now?) would suggest not having a USING for your "code" at all, but rather using relative branch with one register set up to point to your static data and a USING for that. It is relatively infrequent that your static data would exceed 4K, and even if it did you could often use long-displacement instructions to access any data that is more than 4K from the beginning. In some cases you might be able to take advantage of the "immediate" instructions and not even need access to static data. The IEABRCX macro can help in modules that want to use relative branch, particularly if they invoke system macros. Also be sure to identify the architecture level that macros are allowed to assume you are running with, via SYSSTATE ARCHLVL=. Some macro expansions might need local code register addressability, but that is usually easy to provide. Peter Relson z/OS Core Technology Design -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
Re: [EXTERNAL] Re: Co-posted: Rexx performance measures
I think IBM is like sleeping beauty, waiting for a price to awake from the Watson nightmare (or the prince called RAD HAT ?!)... ITschak On Thu, Nov 15, 2018 at 5:57 AM zMan wrote: > Welcome to the new IBM. > > And they think they're going to woo cloud customers with this level of > support... > > -- > For IBM-MAIN subscribe / signoff / archive access instructions, > send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN > -- ITschak Mugzach *|** IronSphere Platform* *|* *Information Security Contiguous Monitoring for Legacy **| * -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
