ECTG usage

2013-07-25 Thread Richard Verville
I'm trying to benchmark cputime (under CICS) with pieces of code I'm changing, 
ECTG before and ECTG after. I'm zeroing out operand 1 before the ECTG thus I 
get a negative value in GPR0(because ETCG subtracts the operand 1 with the 
timer value) after I'm doing a LCR of GPR0 to get the positive timer value. If 
the cputimer went negative during the test (timer interrupt), the second ECTG 
is higher than the 1st one and since I don't know the refeed value of the 
CPUTIMER, I can't tell how much cputime was spend. I know I could use CICS 
internal values or statistics) but since they made ECTG as non-privilege I 
figured I'd give it a try. So... I'm missing something in the concept (the 
refeed value and how many times the interrupt occured ?) Richard

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Re: Dynamic LPA Services

2013-07-14 Thread Richard Verville
John Gilmore-There is no need for further assertions that things
that manifestly do work may not or for something less than clarity
about, for example, the fact that AMODE(64) code is faster than
AMODE(31) code.

Are you saying that AMODE(64) is faster than AMODE(31) ? If so, why would that 
be ? 


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Benchmark of Relative instructions vers Base+displacement ones

2013-07-09 Thread Richard Verville
Has anyone done benchmarks on different scenarios with instructions with 
immediate  relative instructions versus the old instructions. I have to 
rewrite some code for CICS on zOS  VSE and I wonder if it's worth it. Also I 
can't find a Load Fullword Immediate instruction (like LHI) where the intent is 
to load a value greater than 64K into a register and finally, why can't we 
inspect control register 0 in problem state (without the extraction bit on), 
instructions like ISVK should be free, don't you think ? Richard

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Re: Benchmark of Relative instructions vers Base+displacement ones

2013-07-09 Thread Richard Verville
Now I feel really stupid, I went back to the POP manual I have and It's dated 
October 2001. I just tried the LGFI instruction and it compiles . Now I need to 
get my hands on the latest POP manual...The control register R0 has the 
extraction bit (if ISVK is allowed for example) , so we could test the bit 
before getting a privilege operation exception. Richard

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Re: Benchmark of Relative instructions vers Base+displacement ones

2013-07-09 Thread Richard Verville
that link has the same manual I have already and the LGFI instruction is not in 
it, unless I'm doing something wrong. Richard

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Re: Benchmark of Relative instructions vers Base+displacement ones

2013-07-09 Thread Richard Verville
J R 's link works just fine... and indeed has the LGFI and others in it. Thanks 
very much for this...Richard

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S0C4-4

2013-01-17 Thread Richard Verville
REFRPROT is what is causing my S0C4. I wonder why this is not happening with TS 
3.2, the program has the same characteristics (refr,rent etc...) as the one in 
TS 4.2. Is there a parm on the SVC 08(load) that would change the REFR 
attribute (or make it ignore it). Richard

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S0C4-004

2013-01-16 Thread Richard Verville
PSW:  070C2000 8000  00D4DC6E   Instruction Length:  4 
Interrupt Code:  04
Exception Address:  _0001F004  
   
Execution key at Program Check/Abend: 0 Addressing Mode:  31   
   
Space at Program Check/Abend: Basespace
   
Breaking Event Address: _00D4DB86  
- offset UNKNOWN in module UNKNOWN 
   
64-BIT REGISTERS 0-15  
   
GPR 0-1   _8001E150  _0005DC58 
GPR 2-3   _0005DC58  _0001F0F8 
GPR 4-5   _001CAB60  _000B 
GPR 6-7   _001CAB84  _00F96100 
GRR 8-9   _  _80D4DB7A 
GPR A-B   _00AFD608  _7F559430 
GPR C-D   _010C52C0  _0005DBCC 
GPR E-F   _00FF3900  _ 
   
ACCESS REGISTERS 0-15  
   
AR  0-3   00AFF208  0002       
AR  4-7            
AR  8-B            
AR  C-F            
   
FLOATING POINT REGISTERS 0-15  
   
FPR 0-1   _  _ 
FPR 2-3   _  _ 
FPR 4-5   _  _ 
FPR 6-7   _  _ 
FPR 8-9   _  _ 
FPR A-B   _  _ 
FPR C-F   _  _ 
FPR E-F   _  _ 
FPCR   
  REG 6   _001CAB84 

64-bit data follows:

REGDATA _001CAB84   

  -0080       **001CAB04
  -0070 -   -0031 LINES SAME AS ABOVE   
  -0030   D3C4C5D9 C8D6D6D2 5000100C  *LDERHOOK...*001CAB54
  -0020  9680100B 9620100A 5000100C 9680100B  *o...o..o...*001CAB64
  -0010  9620100A 05F058F0 F00607FF 0001F104  *o0.00.1.*001CAB74

     05F058F0 F00607FF 001CA958 58F0021C  *.0.00.z..0..*001CAB84
   0010  58F0F0D0 58F0F014 58F0F00C 58FF0010  *.00}.00..00.*001CAB94
   0020  07FF     **001CABA4
   0030       **001CABB4
   0040 -00FF LINES SAME AS ABOVE   

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S0C4 - 4 problem in a SVC

2013-01-15 Thread Richard Verville
I have this strange problem with CICS TS 4.2 (trial version) which has NOT been 
happening with other TS 4.2 clients. I need to hook in a CICS program (12 
bytes) to get control in my routine. In order to do so, my prog issues a LOAD 
(SVC 08) to get the address and issue a SVC (I coded) to actually zap the 12 
bytes. The loaded routine is in private storage SUBPOOL 252 KEY-0 storage. My 
SVC is running KEY 0. The starting address I want to modify is 0001F080 for 12 
bytes. I'm getting the exception on 0001F004.The SVC is doing an EXECUTE 
instruction which points to a MVC instruction. I don't understand why I'm 
getting this as this runs at many other sites w/o problems. Any ideas anyone ? 
Richard

 MVS Registers and PSW.  
 
PSW:  070C2000 8000  00D4DC6E   Instruction Length:  4   
Interrupt Code:  04  
Exception Address:  _0001F004
 
Execution key at Program Check/Abend: 0 Addressing Mode:  31 
 
Space at Program Check/Abend: Basespace  
 
Breaking Event Address: _00D4DB86
- offset UNKNOWN in module UNKNOWN   
 
64-BIT REGISTERS 0-15
 
GPR 0-1   _8001E150  _0005DC58   
GPR 2-3   _0005DC58  _0001F0F8   
GPR 4-5   _001CAB60  _000B   

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S0C4-4

2013-01-15 Thread Richard Verville
I have this strange problem with CICS TS 4.2 (trial version) which has NOT been 
happening with other TS 4.2 clients. I need to hook in a CICS program (12 
bytes) to get control in my routine. In order to do so, my prog issues a LOAD 
(SVC 08) to get the address and issue a SVC (I coded) to actually zap the 12 
bytes. The loaded routine is in private storage SUBPOOL 252 KEY-0 storage. My 
SVC is running KEY 0. The starting address I want to modify is 0001F080 for 12 
bytes. I'm getting the exception on 0001F004.The SVC is doing an EXECUTE 
instruction which points to a MVC instruction. I don't understand why I'm 
getting this as this runs at many other sites w/o problems. Any ideas anyone ? 
Richard
MVS Registers and PSW. 

PSW: 070C2000 8000  00D4DC6E Instruction Length: 4 
Interrupt Code: 04 
Exception Address: _0001F004 

Execution key at Program Check/Abend: 0 Addressing Mode: 31 

Space at Program Check/Abend: Basespace 

Breaking Event Address: _00D4DB86 
- offset UNKNOWN in module UNKNOWN 

64-BIT REGISTERS 0-15 

GPR 0-1 _8001E150 _0005DC58 
GPR 2-3 _0005DC58 _0001F0F8 
GPR 4-5 _001CAB60 _000B 

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S0C4-004

2013-01-15 Thread Richard Verville
E2 4450 90FC000FE  1959  EX R5,VERSTOR  
  CHECK STORAGE TO VERIFY   00062600
 E6 4770 91280012A  1960  BNEERRVER 
 00062700
 EA BF6F 201000010  1961  ICMR6,15,VSISVWTM 
   L.A. OF DATA TO MODIFY00062802
 EE 4780 913000132  1962  BZ ERRWTM 
 00062900
1963  AIF   ('SYSPARM' NE 
'MVS').NMVS003
 F2 4450 910200104  1964  EX R5,MODSTOR 
   GO MODIFY STORAGE 00063000
1965 .NMVS003 ANOP
1966  AIF   ('SYSPARM' NE 
'VSE').NVSE003
1967 .NVSE003 ANOP
 F6 41F0 0  1968  LA 15,0   
  SET DONE RC00063100
 FA 47F0 914000142  1969  B  RETURN 
 00063200
1970 *  
 00063300
 FE D500 3000 4000 0 0  1971 VERSTOR  CLC0(*-*,R3),0(R4)
   VERIFY STORAGE00063400
 000104 D200 3000 6000 0 0  1972 MODSTOR  MVC0(*-*,R3),0(R6)
   MODIFY STORAGE00063500
 0010A  1973 ERRFUNC  EQU*  
 00063600
 00010A 41F0 00011  1974  LA R15,1  
 00063700
 
The PSW points after the highlighted one. Richard

GRR 8-9   _  _80D4DB7A   
GPR A-B   _00AFD608  _7F559430   
GPR C-D   _010C52C0  _0005DBCC   
GPR E-F   _00FF3900  _   
 
ACCESS REGISTERS 0-15
 
AR  0-3   00AFF208  0002     
AR  4-7          
AR  8-B          
AR  C-F          
 
FLOATING POINT REGISTERS 0-15
 
FPR 0-1   _  _   
FPR 2-3   _  _   
FPR 4-5   _  _   
FPR 6-7   _  _   
FPR 8-9   _  _   

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