[Intel-gfx] [PATCH 1/2] drm/i915: constify find_section in VBT parsing
Make input and output of find_section const, and fix the fallout. We
shouldn't modify the VBT, so make the compiler help us here.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_bios.c | 60 ---
1 file changed, 31 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index c08368c03dad..4e3f3f427178 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -36,10 +36,11 @@
static int panel_type;
-static void *
-find_section(struct bdb_header *bdb, int section_id)
+static const void *
+find_section(const void *_bdb, int section_id)
{
- u8 *base = (u8 *)bdb;
+ const struct bdb_header *bdb = _bdb;
+ const u8 *base = _bdb;
int index = 0;
u16 total, current_size;
u8 current_id;
@@ -53,7 +54,7 @@ find_section(struct bdb_header *bdb, int section_id)
current_id = *(base + index);
index++;
- current_size = *((u16 *)(base + index));
+ current_size = *((const u16 *)(base + index));
index += 2;
if (index + current_size total)
@@ -69,7 +70,7 @@ find_section(struct bdb_header *bdb, int section_id)
}
static u16
-get_blocksize(void *p)
+get_blocksize(const void *p)
{
u16 *block_ptr, block_size;
@@ -350,7 +351,7 @@ static void
parse_sdvo_panel_data(struct drm_i915_private *dev_priv,
struct bdb_header *bdb)
{
- struct lvds_dvo_timing *dvo_timing;
+ const struct lvds_dvo_timing *dvo_timing;
struct drm_display_mode *panel_fixed_mode;
int index;
@@ -361,7 +362,7 @@ parse_sdvo_panel_data(struct drm_i915_private *dev_priv,
}
if (index == -1) {
- struct bdb_sdvo_lvds_options *sdvo_lvds_options;
+ const struct bdb_sdvo_lvds_options *sdvo_lvds_options;
sdvo_lvds_options = find_section(bdb, BDB_SDVO_LVDS_OPTIONS);
if (!sdvo_lvds_options)
@@ -405,7 +406,7 @@ parse_general_features(struct drm_i915_private *dev_priv,
struct bdb_header *bdb)
{
struct drm_device *dev = dev_priv-dev;
- struct bdb_general_features *general;
+ const struct bdb_general_features *general;
general = find_section(bdb, BDB_GENERAL_FEATURES);
if (general) {
@@ -430,7 +431,7 @@ static void
parse_general_definitions(struct drm_i915_private *dev_priv,
struct bdb_header *bdb)
{
- struct bdb_general_definitions *general;
+ const struct bdb_general_definitions *general;
general = find_section(bdb, BDB_GENERAL_DEFINITIONS);
if (general) {
@@ -447,10 +448,10 @@ parse_general_definitions(struct drm_i915_private
*dev_priv,
}
}
-static union child_device_config *
-child_device_ptr(struct bdb_general_definitions *p_defs, int i)
+static const union child_device_config *
+child_device_ptr(const struct bdb_general_definitions *p_defs, int i)
{
- return (void *) p_defs-devices[i * p_defs-child_dev_size];
+ return (const void *) p_defs-devices[i * p_defs-child_dev_size];
}
static void
@@ -458,8 +459,8 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
struct bdb_header *bdb)
{
struct sdvo_device_mapping *p_mapping;
- struct bdb_general_definitions *p_defs;
- union child_device_config *p_child;
+ const struct bdb_general_definitions *p_defs;
+ const union child_device_config *p_child;
int i, child_device_num, count;
u16 block_size;
@@ -547,7 +548,7 @@ static void
parse_driver_features(struct drm_i915_private *dev_priv,
struct bdb_header *bdb)
{
- struct bdb_driver_features *driver;
+ const struct bdb_driver_features *driver;
driver = find_section(bdb, BDB_DRIVER_FEATURES);
if (!driver)
@@ -573,9 +574,9 @@ parse_driver_features(struct drm_i915_private *dev_priv,
static void
parse_edp(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
{
- struct bdb_edp *edp;
- struct edp_power_seq *edp_pps;
- struct edp_link_params *edp_link_params;
+ const struct bdb_edp *edp;
+ const struct edp_power_seq *edp_pps;
+ const struct edp_link_params *edp_link_params;
edp = find_section(bdb, BDB_EDP);
if (!edp) {
@@ -680,8 +681,8 @@ parse_edp(struct drm_i915_private *dev_priv, struct
bdb_header *bdb)
static void
parse_psr(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
{
- struct bdb_psr *psr;
- struct psr_table *psr_table;
+ const struct bdb_psr *psr;
+ const struct psr_table *psr_table;
psr = find_section(bdb, BDB_PSR);
if (!psr) {
@@ -791,11 +792,12 @@ static u8 *goto_next_sequence(u8 *data, int *size)
static void
parse_mipi(struct
[Intel-gfx] [PATCH 2/2] drm/i915: constify validate_vbt in VBT parsing
Make input and output of validate_vbt const, and fix the fallout. We
shouldn't modify the VBT, so make the compiler help us here.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_bios.c | 50 ---
1 file changed, 26 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index 4e3f3f427178..b1e047c5e594 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -205,7 +205,7 @@ get_lvds_fp_timing(const struct bdb_header *bdb,
/* Try to find integrated panel data */
static void
parse_lfp_panel_data(struct drm_i915_private *dev_priv,
- struct bdb_header *bdb)
+const struct bdb_header *bdb)
{
const struct bdb_lvds_options *lvds_options;
const struct bdb_lvds_lfp_data *lvds_lfp_data;
@@ -311,7 +311,8 @@ parse_lfp_panel_data(struct drm_i915_private *dev_priv,
}
static void
-parse_lfp_backlight(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
+parse_lfp_backlight(struct drm_i915_private *dev_priv,
+ const struct bdb_header *bdb)
{
const struct bdb_lfp_backlight_data *backlight_data;
const struct bdb_lfp_backlight_data_entry *entry;
@@ -349,7 +350,7 @@ parse_lfp_backlight(struct drm_i915_private *dev_priv,
struct bdb_header *bdb)
/* Try to find sdvo panel data */
static void
parse_sdvo_panel_data(struct drm_i915_private *dev_priv,
- struct bdb_header *bdb)
+ const struct bdb_header *bdb)
{
const struct lvds_dvo_timing *dvo_timing;
struct drm_display_mode *panel_fixed_mode;
@@ -403,7 +404,7 @@ static int intel_bios_ssc_frequency(struct drm_device *dev,
static void
parse_general_features(struct drm_i915_private *dev_priv,
- struct bdb_header *bdb)
+ const struct bdb_header *bdb)
{
struct drm_device *dev = dev_priv-dev;
const struct bdb_general_features *general;
@@ -429,7 +430,7 @@ parse_general_features(struct drm_i915_private *dev_priv,
static void
parse_general_definitions(struct drm_i915_private *dev_priv,
- struct bdb_header *bdb)
+ const struct bdb_header *bdb)
{
const struct bdb_general_definitions *general;
@@ -456,7 +457,7 @@ child_device_ptr(const struct bdb_general_definitions
*p_defs, int i)
static void
parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
- struct bdb_header *bdb)
+ const struct bdb_header *bdb)
{
struct sdvo_device_mapping *p_mapping;
const struct bdb_general_definitions *p_defs;
@@ -546,7 +547,7 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
static void
parse_driver_features(struct drm_i915_private *dev_priv,
- struct bdb_header *bdb)
+ const struct bdb_header *bdb)
{
const struct bdb_driver_features *driver;
@@ -572,7 +573,7 @@ parse_driver_features(struct drm_i915_private *dev_priv,
}
static void
-parse_edp(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
+parse_edp(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
{
const struct bdb_edp *edp;
const struct edp_power_seq *edp_pps;
@@ -679,7 +680,7 @@ parse_edp(struct drm_i915_private *dev_priv, struct
bdb_header *bdb)
}
static void
-parse_psr(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
+parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
{
const struct bdb_psr *psr;
const struct psr_table *psr_table;
@@ -790,7 +791,7 @@ static u8 *goto_next_sequence(u8 *data, int *size)
}
static void
-parse_mipi(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
+parse_mipi(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
{
const struct bdb_mipi_config *start;
const struct bdb_mipi_sequence *sequence;
@@ -941,7 +942,7 @@ err:
}
static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port,
- struct bdb_header *bdb)
+ const struct bdb_header *bdb)
{
union child_device_config *it, *child = NULL;
struct ddi_vbt_port_info *info = dev_priv-vbt.ddi_port_info[port];
@@ -1043,7 +1044,7 @@ static void parse_ddi_port(struct drm_i915_private
*dev_priv, enum port port,
}
static void parse_ddi_ports(struct drm_i915_private *dev_priv,
- struct bdb_header *bdb)
+ const struct bdb_header *bdb)
{
struct drm_device *dev = dev_priv-dev;
enum port port;
@@ -1063,7 +1064,7 @@ static void parse_ddi_ports(struct drm_i915_private
*dev_priv,
static void
parse_device_mapping(struct drm_i915_private *dev_priv,
- struct bdb_header *bdb)
+
[Intel-gfx] [PATCH 11/14] drm/i915: Add IS_BDW_ULX
We need to tell BDW ULT and ULX apart.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Mika Kahola mika.kah...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bae1ce9..0c307f9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2327,6 +2327,9 @@ struct drm_i915_cmd_table {
((INTEL_DEVID(dev) 0xf) == 0x6 ||\
(INTEL_DEVID(dev) 0xf) == 0xb || \
(INTEL_DEVID(dev) 0xf) == 0xe))
+/* ULX machines are also considered ULT. */
+#define IS_BDW_ULX(dev)(IS_BROADWELL(dev) \
+(INTEL_DEVID(dev) 0xf) == 0xe)
#define IS_BDW_GT3(dev)(IS_BROADWELL(dev) \
(INTEL_DEVID(dev) 0x00F0) == 0x0020)
#define IS_HSW_ULT(dev)(IS_HASWELL(dev) \
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 12/14] drm/i915: BDW clock change support
Add support for changing cdclk frequency during runtime on BDW. The
procedure is quite a bit different on BDW from the one on HSW, so
add a separate function for it.
Also with IPS enabled the actual pixel rate mustn't exceed 95% of cdclk,
so take that into account when computing the max pixel rate.
v2: Grab rps.hw_lock around sandybridge_pcode_write()
v3: Rebase due to power well vs. .global_resources() reordering
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
v4: Rebased to the latest
Signed-off-by: Mika Kahola mika.kah...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 138 ++-
2 files changed, 122 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 74ff995..782d471 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6411,6 +6411,7 @@ enum skl_disp_power_wells {
#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
#define GEN6_DECODE_RC6_VID(vids)(((vids) * 5) + 245)
#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
+#define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ0x18
#define DISPLAY_IPS_CONTROL 0x19
#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
#define GEN6_PCODE_DATA0x138128
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 35489cd..09f3518 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5214,7 +5214,22 @@ static void intel_update_max_cdclk(struct drm_device
*dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
- if (IS_HASWELL(dev)) {
+ if (IS_BROADWELL(dev)) {
+ /*
+* FIXME with extra cooling we can allow
+* 540 MHz for ULX and 675 Mhz for ULT.
+* How can we know if extra cooling is
+* available? PCI ID, VTB, something else?
+*/
+ if (I915_READ(FUSE_STRAP) HSW_CDCLK_LIMIT)
+ dev_priv-max_cdclk_freq = 45;
+ else if (IS_BDW_ULX(dev))
+ dev_priv-max_cdclk_freq = 45;
+ else if (IS_BDW_ULT(dev))
+ dev_priv-max_cdclk_freq = 54;
+ else
+ dev_priv-max_cdclk_freq = 675000;
+ } else if (IS_HASWELL(dev)) {
if (I915_READ(FUSE_STRAP) HSW_CDCLK_LIMIT)
dev_priv-max_cdclk_freq = 45;
else if (IS_HSW_ULX(dev))
@@ -6092,13 +6107,11 @@ static bool pipe_config_supports_ips(struct
drm_i915_private *dev_priv,
return true;
/*
-* FIXME if we compare against max we should then
-* increase the cdclk frequency when the current
-* value is too low. The other option is to compare
-* against the cdclk frequency we're going have post
-* modeset (ie. one we computed using other constraints).
-* Need to measure whether using a lower cdclk w/o IPS
-* is better or worse than a higher cdclk w/ IPS.
+* We compare against max which means we must take
+* the increased cdclk requirement into account when
+* calculating the new cdclk.
+*
+* Should measure whether using a lower cdclk w/o IPS
*/
return ilk_pipe_pixel_rate(pipe_config) =
dev_priv-max_cdclk_freq * 95 / 100;
@@ -9082,9 +9095,18 @@ static int ilk_max_pixel_rate(struct drm_i915_private
*dev_priv)
int max_pixel_rate = 0;
for_each_intel_crtc(dev, crtc) {
- if (crtc-new_enabled)
- max_pixel_rate = max((int)max_pixel_rate,
-
(int)ilk_pipe_pixel_rate(crtc-config));
+ int pixel_rate;
+
+ if (!crtc-new_enabled)
+ continue;
+
+ pixel_rate = ilk_pipe_pixel_rate(crtc-config);
+
+ /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
+ if (IS_BROADWELL(dev) crtc-config-ips_enabled)
+ pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
+
+ max_pixel_rate = max(max_pixel_rate, pixel_rate);
}
return max_pixel_rate;
@@ -9099,7 +9121,9 @@ static int haswell_calc_cdclk(struct drm_i915_private
*dev_priv,
* FIXME should also account for plane ratio
* once 64bpp pixel formats are supported.
*/
- if (max_pixel_rate 45)
+ if (max_pixel_rate 54)
+ cdclk = 675000;
+ else if (max_pixel_rate 45)
cdclk = 54;
else if (max_pixel_rate 337500 || !IS_HSW_ULX(dev_priv))
cdclk = 45;
@@ -9164,6 +9188,83 @@ static void haswell_set_cdclk(struct drm_device *dev,
int
[Intel-gfx] [PATCH 09/14] drm/i915: Don't enable IPS when pixel rate exceeds 95%
Bspec says we shouldn't enable IPS on BDW when the pipe pixel rate
exceeds 95% of the core display clock. Apparently this can cause
underruns.
There's no similar restriction listed for HSW, so leave that one alone
for now.
v2: Add pipe_config_supports_ips() (Chris)
v3: Compare against the max cdclk insted of the current cdclk
Tested-by: Timo Aaltonen tjaal...@ubuntu.com
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83497
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
v4: Rebased to the latest
Signed-off-by: Mika Kahola mika.kah...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 30 --
drivers/gpu/drm/i915/intel_drv.h | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 17 -
3 files changed, 37 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index dbc880e..fa7baf2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6072,12 +6072,38 @@ retry:
return ret;
}
+static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
+struct intel_crtc_state *pipe_config)
+{
+ if (pipe_config-pipe_bpp 24)
+ return false;
+
+ /* HSW can handle pixel rate up to cdclk? */
+ if (IS_HASWELL(dev_priv-dev))
+ return true;
+
+ /*
+* FIXME if we compare against max we should then
+* increase the cdclk frequency when the current
+* value is too low. The other option is to compare
+* against the cdclk frequency we're going have post
+* modeset (ie. one we computed using other constraints).
+* Need to measure whether using a lower cdclk w/o IPS
+* is better or worse than a higher cdclk w/ IPS.
+*/
+ return ilk_pipe_pixel_rate(pipe_config) =
+ dev_priv-max_cdclk_freq * 95 / 100;
+}
+
static void hsw_compute_ips_config(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config)
{
+ struct drm_device *dev = crtc-base.dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+
pipe_config-ips_enabled = i915.enable_ips
- hsw_crtc_supports_ips(crtc)
- pipe_config-pipe_bpp = 24;
+ hsw_crtc_supports_ips(crtc)
+ pipe_config_supports_ips(dev_priv, pipe_config);
}
static int intel_crtc_compute_config(struct intel_crtc *crtc,
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 082be71..34ee6b9 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1351,7 +1351,7 @@ void ilk_wm_get_hw_state(struct drm_device *dev);
void skl_wm_get_hw_state(struct drm_device *dev);
void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
struct skl_ddb_allocation *ddb /* out */);
-
+uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
/* intel_sdvo.c */
bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 79e4afd..b130520 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1435,23 +1435,22 @@ static void i845_update_wm(struct drm_crtc *unused_crtc)
I915_WRITE(FW_BLC, fwater_lo);
}
-static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
- struct drm_crtc *crtc)
+uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
{
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
uint32_t pixel_rate;
- pixel_rate = intel_crtc-config-base.adjusted_mode.crtc_clock;
+ pixel_rate = pipe_config-base.adjusted_mode.crtc_clock;
/* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
* adjust the pixel_rate here. */
- if (intel_crtc-config-pch_pfit.enabled) {
+ if (pipe_config-pch_pfit.enabled) {
uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
- uint32_t pfit_size = intel_crtc-config-pch_pfit.size;
+ uint32_t pfit_size = pipe_config-pch_pfit.size;
+
+ pipe_w = pipe_config-pipe_src_w;
+ pipe_h = pipe_config-pipe_src_h;
- pipe_w = intel_crtc-config-pipe_src_w;
- pipe_h = intel_crtc-config-pipe_src_h;
pfit_w = (pfit_size 16) 0x;
pfit_h = pfit_size 0x;
if (pipe_w pfit_w)
@@ -2067,7 +2066,7 @@ static void ilk_compute_wm_parameters(struct drm_crtc
*crtc,
p-active = true;
p-pipe_htotal = intel_crtc-config-base.adjusted_mode.crtc_htotal;
- p-pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
+ p-pixel_rate = ilk_pipe_pixel_rate(intel_crtc-config);
if
[Intel-gfx] [PATCH 05/14] drm/i915: Cache current cdclk frequency in dev_priv
Rather that extracting the current cdclk freuqncy every time someone
wants to know it, cache the current value and use that. VLV/CHV already
stored a cached value there so just expand that to cover all platforms.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
V2: Rebased to the latest
Signed-off-by: Mika Kahola mika.kah...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_display.c | 40 +++-
2 files changed, 27 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 89231ae..baec8d2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1657,7 +1657,7 @@ struct drm_i915_private {
int num_fence_regs; /* 8 on pre-965, 16 otherwise */
unsigned int fsb_freq, mem_freq, is_ddr3;
- unsigned int vlv_cdclk_freq;
+ unsigned int cdclk_freq;
unsigned int hpll_freq;
/**
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 20aa288..3204e5e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5210,20 +5210,27 @@ static int valleyview_get_vco(struct drm_i915_private
*dev_priv)
return vco_freq[hpll_freq] * 1000;
}
-static void vlv_update_cdclk(struct drm_device *dev)
+static void intel_update_cdclk(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
- dev_priv-vlv_cdclk_freq =
dev_priv-display.get_display_clock_speed(dev);
+ dev_priv-cdclk_freq = dev_priv-display.get_display_clock_speed(dev);
DRM_DEBUG_DRIVER(Current CD clock rate: %d kHz\n,
-dev_priv-vlv_cdclk_freq);
+dev_priv-cdclk_freq);
/*
* Program the gmbus_freq based on the cdclk frequency.
* BSpec erroneously claims we should aim for 4MHz, but
* in fact 1MHz is the correct frequency.
*/
- I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv-vlv_cdclk_freq, 1000));
+ if (IS_VALLEYVIEW(dev)) {
+ /*
+* Program the gmbus_freq based on the cdclk frequency.
+* BSpec erroneously claims we should aim for 4MHz, but
+* in fact 1MHz is the correct frequency.
+*/
+ I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv-cdclk_freq,
1000));
+ }
}
/* Adjust CDclk dividers to allow high res or save power if possible */
@@ -5232,7 +5239,7 @@ static void valleyview_set_cdclk(struct drm_device *dev,
int cdclk)
struct drm_i915_private *dev_priv = dev-dev_private;
u32 val, cmd;
- WARN_ON(dev_priv-display.get_display_clock_speed(dev) !=
dev_priv-vlv_cdclk_freq);
+ WARN_ON(dev_priv-display.get_display_clock_speed(dev) !=
dev_priv-cdclk_freq);
if (cdclk = 32) /* jump to highest voltage for 400MHz too */
cmd = 2;
@@ -5288,7 +5295,7 @@ static void valleyview_set_cdclk(struct drm_device *dev,
int cdclk)
vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
mutex_unlock(dev_priv-dpio_lock);
- vlv_update_cdclk(dev);
+ intel_update_cdclk(dev);
}
static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
@@ -5296,7 +5303,7 @@ static void cherryview_set_cdclk(struct drm_device *dev,
int cdclk)
struct drm_i915_private *dev_priv = dev-dev_private;
u32 val, cmd;
- WARN_ON(dev_priv-display.get_display_clock_speed(dev) !=
dev_priv-vlv_cdclk_freq);
+ WARN_ON(dev_priv-display.get_display_clock_speed(dev) !=
dev_priv-cdclk_freq);
switch (cdclk) {
case 33:
@@ -5328,7 +5335,7 @@ static void cherryview_set_cdclk(struct drm_device *dev,
int cdclk)
}
mutex_unlock(dev_priv-rps.hw_lock);
- vlv_update_cdclk(dev);
+ intel_update_cdclk(dev);
}
static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
@@ -5395,7 +5402,7 @@ static int valleyview_modeset_global_pipes(struct
drm_atomic_state *state,
return max_pixclk;
if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
- dev_priv-vlv_cdclk_freq)
+ dev_priv-cdclk_freq)
return 0;
/* disable/enable all currently active pipes while we change cdclk */
@@ -5415,7 +5422,7 @@ static void vlv_program_pfi_credits(struct
drm_i915_private *dev_priv)
else
default_credits = PFI_CREDIT(8);
- if (DIV_ROUND_CLOSEST(dev_priv-vlv_cdclk_freq, 1000) =
dev_priv-rps.cz_freq) {
+ if (DIV_ROUND_CLOSEST(dev_priv-cdclk_freq, 1000) =
dev_priv-rps.cz_freq) {
/* CHV suggested value is 31 or 63 */
if (IS_CHERRYVIEW(dev_priv))
credits = PFI_CREDIT_31;
@@ -5459,7 +5466,7 @@ static void valleyview_modeset_global_resources(struct
drm_atomic_state *state)
[Intel-gfx] [PATCH 03/14] drm/i915: Add cdclk extraction for g33, g965gm and g4x
Implement cdclk extraction for g33, 965gm and g4x platforms. The details
came from configdb. Sadly there isn't anything there for other gen3/gen4
chipsets.
So far I've tested this on one ELK where it gave me a HPLL VCO of 5333
MHz and cdclk of 444 MHz which seems perfectly sane for this machine.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
V2: Rebased to the latest
Signed-off-by: Mika Kahola mika.kah...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 3 +
drivers/gpu/drm/i915/intel_display.c | 183 ++-
2 files changed, 185 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 441bf38..d4cf3bc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2223,6 +2223,9 @@ enum skl_disp_power_wells {
#define CLKCFG_MEM_800 (3 4)
#define CLKCFG_MEM_MASK(7 4)
+#define HPLLVCO (MCHBAR_MIRROR_BASE + 0xc38)
+#define HPLLVCO_MOBILE (MCHBAR_MIRROR_BASE + 0xc0f)
+
#define TSC1 0x11001
#define TSE (10)
#define TR10x11006
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 7afde69..ac5031c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6343,6 +6343,175 @@ static int i830_get_display_clock_speed(struct
drm_device *dev)
return 13;
}
+static unsigned int intel_hpll_vco(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ static const unsigned int blb_vco[8] = {
+ [0] = 320,
+ [1] = 400,
+ [2] = 533,
+ [3] = 480,
+ [4] = 640,
+ };
+ static const unsigned int pnv_vco[8] = {
+ [0] = 320,
+ [1] = 400,
+ [2] = 533,
+ [3] = 480,
+ [4] = 267,
+ };
+ static const unsigned int cl_vco[8] = {
+ [0] = 320,
+ [1] = 400,
+ [2] = 533,
+ [3] = 640,
+ [4] = 333,
+ [5] = 357,
+ [6] = 427,
+ };
+ static const unsigned int elk_vco[8] = {
+ [0] = 320,
+ [1] = 400,
+ [2] = 533,
+ [3] = 480,
+ };
+ static const unsigned int ctg_vco[8] = {
+ [0] = 320,
+ [1] = 400,
+ [2] = 533,
+ [3] = 640,
+ [4] = 267,
+ [5] = 427,
+ };
+ const unsigned int *vco_table;
+ unsigned int vco;
+ uint8_t tmp = 0;
+
+ /* FIXME other chipsets? */
+ if (IS_GM45(dev))
+ vco_table = ctg_vco;
+ else if (IS_G4X(dev))
+ vco_table = elk_vco;
+ else if (IS_CRESTLINE(dev))
+ vco_table = cl_vco;
+ else if (IS_PINEVIEW(dev))
+ vco_table = pnv_vco;
+ else if (IS_G33(dev))
+ vco_table = blb_vco;
+ else
+ return 0;
+
+ tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
+
+ vco = vco_table[tmp 0x7];
+ if (vco == 0)
+ DRM_ERROR(Bad HPLL VCO (HPLLVCO=0x%02x)\n, tmp);
+ else
+ DRM_DEBUG_KMS(HPLL VCO %u kHz\n, vco);
+
+ return vco;
+}
+
+static int gm45_get_display_clock_speed(struct drm_device *dev)
+{
+ unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
+ uint16_t tmp = 0;
+
+ pci_read_config_word(dev-pdev, GCFGC, tmp);
+
+ cdclk_sel = (tmp 12) 0x1;
+
+ switch (vco) {
+ case 267:
+ case 400:
+ case 533:
+ return cdclk_sel ? 33 : 22;
+ case 320:
+ return cdclk_sel ? 32 : 228571;
+ default:
+ DRM_ERROR(Unable to determine CDCLK. HPLL VCO=%u,
CFGC=0x%04x\n, vco, tmp);
+ return 22;
+ }
+}
+
+static int i965gm_get_display_clock_speed(struct drm_device *dev)
+{
+ static const uint8_t div_3200[] = { 16, 10, 8 };
+ static const uint8_t div_4000[] = { 20, 12, 10 };
+ static const uint8_t div_5333[] = { 24, 16, 14 };
+ const uint8_t *div_table;
+ unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
+ uint16_t tmp = 0;
+
+ pci_read_config_word(dev-pdev, GCFGC, tmp);
+
+ cdclk_sel = ((tmp 8) 0x1f) - 1;
+
+ if (cdclk_sel = ARRAY_SIZE(div_3200))
+ goto fail;
+
+ switch (vco) {
+ case 320:
+ div_table = div_3200;
+ break;
+ case 400:
+ div_table = div_4000;
+ break;
+ case 533:
+
[Intel-gfx] [PATCH 04/14] drm/i915: Warn when cdclk for the platforms is not known
Print a warning if we fall through the .get_display_clock_speed() function
pointer setup. We end up assuming a 133MHz cdclk which should mean that
at least we avoid any 0 deivisions and whatnot. But this could at least
help remind people that they have to provide this function for new platforms.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Mika Kahola mika.kah...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index ac5031c..20aa288 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14185,9 +14185,11 @@ static void intel_init_display(struct drm_device *dev)
else if (IS_I85X(dev))
dev_priv-display.get_display_clock_speed =
i85x_get_display_clock_speed;
- else /* 830 */
+ else { /* 830 */
+ WARN(!IS_I830(dev), Unknown platform. Assuming 133 MHz
CDCLK\n);
dev_priv-display.get_display_clock_speed =
i830_get_display_clock_speed;
+ }
if (IS_GEN5(dev)) {
dev_priv-display.fdi_link_train = ironlake_fdi_link_train;
--
1.9.1
___
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 08/14] drm/i915: Store max cdclk value in dev_priv
Keep the cdclk maximum supported frequency around in dev_priv so that we
can verify certain things against it before actually changing the cdclk
frequency.
For now only VLV/CHV have support changing cdclk frequency, so other
plarforms get to assume cdclk is fixed.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Mika Kahola mika.kah...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_display.c | 20 +++-
2 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index baec8d2..bae1ce9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1657,7 +1657,7 @@ struct drm_i915_private {
int num_fence_regs; /* 8 on pre-965, 16 otherwise */
unsigned int fsb_freq, mem_freq, is_ddr3;
- unsigned int cdclk_freq;
+ unsigned int cdclk_freq, max_cdclk_freq;
unsigned int hpll_freq;
/**
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 8965eb3..dbc880e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5210,6 +5210,21 @@ static int valleyview_get_vco(struct drm_i915_private
*dev_priv)
return vco_freq[hpll_freq] * 1000;
}
+static void intel_update_max_cdclk(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+
+ if (IS_VALLEYVIEW(dev)) {
+ dev_priv-max_cdclk_freq = 40;
+ } else {
+ /* otherwise assume cdclk is fixed */
+ dev_priv-max_cdclk_freq = dev_priv-cdclk_freq;
+ }
+
+ DRM_DEBUG_DRIVER(Max CD clock rate: %d kHz\n,
+dev_priv-max_cdclk_freq);
+}
+
static void intel_update_cdclk(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -5231,6 +5246,9 @@ static void intel_update_cdclk(struct drm_device *dev)
*/
I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv-cdclk_freq,
1000));
}
+
+ if (dev_priv-max_cdclk_freq == 0)
+ intel_update_max_cdclk(dev);
}
/* Adjust CDclk dividers to allow high res or save power if possible */
@@ -6072,7 +6090,7 @@ static int intel_crtc_compute_config(struct intel_crtc
*crtc,
/* FIXME should check pixel clock limits on all platforms */
if (INTEL_INFO(dev)-gen 4) {
- int clock_limit = dev_priv-cdclk_freq;
+ int clock_limit = dev_priv-max_cdclk_freq;
/*
* Enable pixel doubling when the dot clock
--
1.9.1
___
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[Intel-gfx] [PATCH 07/14] drm/i915: Unify ilk and hsw .get_aux_clock_divider
ilk_get_aux_clock_divider() is now a subset of
hsw_get_aux_clock_divider() so unify them.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Mika Kahola mika.kah...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 23 +++
1 file changed, 3 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 91ccdaa..b415d3e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -698,23 +698,6 @@ static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp, int index)
struct drm_device *dev = intel_dig_port-base.base.dev;
struct drm_i915_private *dev_priv = dev-dev_private;
- if (index)
- return 0;
-
- if (intel_dig_port-port == PORT_A) {
- return DIV_ROUND_UP(dev_priv-cdclk_freq, 2000);
-
- } else {
- return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
- }
-}
-
-static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
-{
- struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
- struct drm_device *dev = intel_dig_port-base.base.dev;
- struct drm_i915_private *dev_priv = dev-dev_private;
-
if (intel_dig_port-port == PORT_A) {
if (index)
return 0;
@@ -727,7 +710,9 @@ static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp, int index)
default: return 0;
}
} else {
- return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
+ if (index)
+ return 0;
+ return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
}
}
@@ -5474,8 +5459,6 @@ intel_dp_init_connector(struct intel_digital_port
*intel_dig_port,
intel_dp-get_aux_clock_divider = skl_get_aux_clock_divider;
else if (IS_VALLEYVIEW(dev))
intel_dp-get_aux_clock_divider = vlv_get_aux_clock_divider;
- else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
- intel_dp-get_aux_clock_divider = hsw_get_aux_clock_divider;
else if (HAS_PCH_SPLIT(dev))
intel_dp-get_aux_clock_divider = ilk_get_aux_clock_divider;
else
--
1.9.1
___
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[Intel-gfx] All sort of cdclk stuff
This patch series rebases Ville's original cdclk patch series excluding the ones that have been reviewed. http://lists.freedesktop.org/archives/intel-gfx/2014-November/055633.html The patches include modifications to drm/i915: Fix i855_get_display_clock_speed() drm/i915: Fix 852GM/GMV cdclk drm/i915: Add cdclk extraction for g33, 965gm and g4x drm/i915: Warn when cdclk for the platforms is not known drm/i915: Cache the current cdclk frequency in dev_priv drm/i915: Use cached cdclk value drm/i915: Unify ilk and hsw .get_aux_clock_divider() drm/i915: Store max cdclk value in dev_priv drm/i915: Don't enable IPS when pixel rate exceeds 95% of cdclk drm/i915: HSW cdclk change support drm/i915: Add IS_BDW_ULX() drm/i915: BDW cdclk change support drm/i915: Limit CHV max cdclk to 320 MHz drm/i915: Modeset global_pipes() update ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 01/14] drm/i915: Fix i855 get_display_clock_speed
Actually read the HPLLCC register insted of assuming it's 0. Fix the
HPLLCC bit definitions and all the missing ones from the 852GME spec.
852GME, 854 and 855 all seem to match the same HPLLC encoding even
though only some of the values are valid is some of the platforms.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Mika Kahola mika.kah...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 11 ---
drivers/gpu/drm/i915/intel_display.c | 15 ---
2 files changed, 20 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 077cb90..441bf38 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -50,12 +50,17 @@
/* PCI config space */
-#define HPLLCC 0xc0 /* 855 only */
-#define GC_CLOCK_CONTROL_MASK(0xf 0)
+#define HPLLCC 0xc0 /* 85x only */
+#define GC_CLOCK_CONTROL_MASK(0x7 0)
#define GC_CLOCK_133_200 (0 0)
#define GC_CLOCK_100_200 (1 0)
#define GC_CLOCK_100_133 (2 0)
-#define GC_CLOCK_166_250 (3 0)
+#define GC_CLOCK_133_266 (3 0)
+#define GC_CLOCK_133_200_2 (4 0)
+#define GC_CLOCK_133_266_2 (5 0)
+#define GC_CLOCK_166_266 (6 0)
+#define GC_CLOCK_166_250 (7 0)
+
#define GCFGC2 0xda
#define GCFGC 0xf0 /* 915+ only */
#define GC_LOW_FREQUENCY_ENABLE (1 7)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 75afa6e..71123c7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6301,20 +6301,29 @@ static int i865_get_display_clock_speed(struct
drm_device *dev)
return 27;
}
-static int i855_get_display_clock_speed(struct drm_device *dev)
+static int i85x_get_display_clock_speed(struct drm_device *dev)
{
u16 hpllcc = 0;
+
+ pci_bus_read_config_word(dev-pdev-bus,
+PCI_DEVFN(0, 3), HPLLCC, hpllcc);
+
/* Assume that the hardware is in the high speed state. This
* should be the default.
*/
switch (hpllcc GC_CLOCK_CONTROL_MASK) {
case GC_CLOCK_133_200:
+ case GC_CLOCK_133_200_2:
case GC_CLOCK_100_200:
return 20;
case GC_CLOCK_166_250:
return 25;
case GC_CLOCK_100_133:
return 13;
+ case GC_CLOCK_133_266:
+ case GC_CLOCK_133_266_2:
+ case GC_CLOCK_166_266:
+ return 27;
}
/* Shouldn't happen */
@@ -13986,8 +13995,8 @@ static void intel_init_display(struct drm_device *dev)
i865_get_display_clock_speed;
else if (IS_I85X(dev))
dev_priv-display.get_display_clock_speed =
- i855_get_display_clock_speed;
- else /* 852, 830 */
+ i85x_get_display_clock_speed;
+ else /* 830 */
dev_priv-display.get_display_clock_speed =
i830_get_display_clock_speed;
--
1.9.1
___
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[Intel-gfx] [PATCH 10/14] drm/i915: HSW cdclk support
Implement support for changing the cdclk frequency during runtime on
HSW. VLV/CHV already have support for this, so we can follow their
example for the most part. Only the actual hardware programming differs,
the rest is pretty much the same.
The pipe pixel rate stuff is handled a bit differently for now due to
the difference in pch vs. gmch pfit handling. Eventually we should unify
that part to eliminate what is essentially duplicated code.
v2: Grab rps.hw_lock around sandybridge_pcode_write()
v3: Rebase due to power well vs. .global_resources() reordering
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
v3: Rebased to the latest
Signed-off-by: Mika Kahola mika.kah...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 3 +
drivers/gpu/drm/i915/intel_display.c | 140 ++-
2 files changed, 140 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d4cf3bc..74ff995 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6410,6 +6410,7 @@ enum skl_disp_power_wells {
#define GEN6_PCODE_WRITE_D_COMP 0x11
#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
#define GEN6_DECODE_RC6_VID(vids)(((vids) * 5) + 245)
+#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
#define DISPLAY_IPS_CONTROL 0x19
#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
#define GEN6_PCODE_DATA0x138128
@@ -6859,10 +6860,12 @@ enum skl_disp_power_wells {
#define LCPLL_PLL_LOCK(130)
#define LCPLL_CLK_FREQ_MASK (326)
#define LCPLL_CLK_FREQ_450(026)
+#define LCPLL_CLK_FREQ_ALT_HSW(126) /* 337.5 (ULX) or 540 */
#define LCPLL_CLK_FREQ_54O_BDW(126)
#define LCPLL_CLK_FREQ_337_5_BDW (226)
#define LCPLL_CLK_FREQ_675_BDW(326)
#define LCPLL_CD_CLOCK_DISABLE(125)
+#define LCPLL_ROOT_CD_CLOCK_DISABLE (124)
#define LCPLL_CD2X_CLOCK_DISABLE (123)
#define LCPLL_POWER_DOWN_ALLOW(122)
#define LCPLL_CD_SOURCE_FCLK (121)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index fa7baf2..35489cd 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5214,7 +5214,16 @@ static void intel_update_max_cdclk(struct drm_device
*dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
- if (IS_VALLEYVIEW(dev)) {
+ if (IS_HASWELL(dev)) {
+ if (I915_READ(FUSE_STRAP) HSW_CDCLK_LIMIT)
+ dev_priv-max_cdclk_freq = 45;
+ else if (IS_HSW_ULX(dev))
+ dev_priv-max_cdclk_freq = 337500;
+ else if (IS_HSW_ULT(dev))
+ dev_priv-max_cdclk_freq = 45;
+ else
+ dev_priv-max_cdclk_freq = 54;
+ } else if (IS_VALLEYVIEW(dev)) {
dev_priv-max_cdclk_freq = 40;
} else {
/* otherwise assume cdclk is fixed */
@@ -9065,6 +9074,125 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv)
intel_prepare_ddi(dev);
}
+/* compute the max rate for new configuration */
+static int ilk_max_pixel_rate(struct drm_i915_private *dev_priv)
+{
+ struct drm_device *dev = dev_priv-dev;
+ struct intel_crtc *crtc;
+ int max_pixel_rate = 0;
+
+ for_each_intel_crtc(dev, crtc) {
+ if (crtc-new_enabled)
+ max_pixel_rate = max((int)max_pixel_rate,
+
(int)ilk_pipe_pixel_rate(crtc-config));
+ }
+
+ return max_pixel_rate;
+}
+
+static int haswell_calc_cdclk(struct drm_i915_private *dev_priv,
+ int max_pixel_rate)
+{
+ int cdclk;
+
+ /*
+* FIXME should also account for plane ratio
+* once 64bpp pixel formats are supported.
+*/
+ if (max_pixel_rate 45)
+ cdclk = 54;
+ else if (max_pixel_rate 337500 || !IS_HSW_ULX(dev_priv))
+ cdclk = 45;
+ else
+ cdclk = 337500;
+
+ /*
+* FIXME move the cdclk caclulation to
+* compute_config() so we can fail gracegully.
+*/
+ if (cdclk dev_priv-max_cdclk_freq) {
+ DRM_ERROR(requested cdclk (%d kHz) exceeds max (%d kHz)\n,
+ cdclk, dev_priv-max_cdclk_freq);
+ cdclk = dev_priv-max_cdclk_freq;
+ }
+
+ return cdclk;
+}
+
+static void haswell_set_cdclk(struct drm_device *dev, int cdclk)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ uint32_t val;
+
+ if (WARN((I915_READ(LCPLL_CTL)
+ (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
+ LCPLL_CD_CLOCK_DISABLE |
[Intel-gfx] [PATCH 06/14] drm/i915: Use cached cdclk value
Rather than reading out the current cdclk value use the cached value we
have tucked away in dev_priv.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Mika Kahola mika.kah...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 3 +--
drivers/gpu/drm/i915/intel_dp.c | 5 +++--
drivers/gpu/drm/i915/intel_pm.c | 2 +-
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 3204e5e..8965eb3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6072,8 +6072,7 @@ static int intel_crtc_compute_config(struct intel_crtc
*crtc,
/* FIXME should check pixel clock limits on all platforms */
if (INTEL_INFO(dev)-gen 4) {
- int clock_limit =
- dev_priv-display.get_display_clock_speed(dev);
+ int clock_limit = dev_priv-cdclk_freq;
/*
* Enable pixel doubling when the dot clock
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 14cdd00..91ccdaa 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -702,7 +702,8 @@ static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp, int index)
return 0;
if (intel_dig_port-port == PORT_A) {
- return
DIV_ROUND_UP(dev_priv-display.get_display_clock_speed(dev), 2000);
+ return DIV_ROUND_UP(dev_priv-cdclk_freq, 2000);
+
} else {
return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
}
@@ -717,7 +718,7 @@ static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp, int index)
if (intel_dig_port-port == PORT_A) {
if (index)
return 0;
- return
DIV_ROUND_CLOSEST(dev_priv-display.get_display_clock_speed(dev), 2000);
+ return DIV_ROUND_CLOSEST(dev_priv-cdclk_freq, 2000);
} else if (dev_priv-pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
/* Workaround for non-ULT HSW */
switch (index) {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a80bfd5..79e4afd 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1816,7 +1816,7 @@ hsw_compute_linetime_wm(struct drm_device *dev, struct
drm_crtc *crtc)
linetime = DIV_ROUND_CLOSEST(mode-crtc_htotal * 1000 * 8,
mode-crtc_clock);
ips_linetime = DIV_ROUND_CLOSEST(mode-crtc_htotal * 1000 * 8,
-
dev_priv-display.get_display_clock_speed(dev_priv-dev));
+dev_priv-cdclk_freq);
return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
PIPE_WM_LINETIME_TIME(linetime);
--
1.9.1
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[Intel-gfx] [PATCH 13/14] drm/i915: Limit CHV max cdclk
Limit CHV maximum cdclk to 320MHz.
Signed-off-by: Mika Kahola mika.kah...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 09f3518..d79421a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5239,7 +5239,7 @@ static void intel_update_max_cdclk(struct drm_device *dev)
else
dev_priv-max_cdclk_freq = 54;
} else if (IS_VALLEYVIEW(dev)) {
- dev_priv-max_cdclk_freq = 40;
+ dev_priv-max_cdclk_freq = IS_CHERRYVIEW(dev) ? 32 : 40;
} else {
/* otherwise assume cdclk is fixed */
dev_priv-max_cdclk_freq = dev_priv-cdclk_freq;
--
1.9.1
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[Intel-gfx] [PATCH 14/14] drm/i915: Modeset global_pipes() update
Combined Valleyview, Haswell and Broadwell '*_modeset_global_pipes()'
into one function 'intel_modeset_global_pipes()'
v2:
- we don't modify 'disable_pipes', so passing this as a pointer
is removed (based on Ville's comment)
- introduced a new function 'intel_calc_cdclk()' that combines
routines from 'valleyview_calc_cdclk()' and 'haswell_calc_cdclk()'
v3:
- Let's take a step back and not remove the routines 'valleyview_calc_cdclk()'
and 'haswell_calc_cdclk()' from newly introduced routine
'intel_calc_cdclk()' (based on Ville's comment)
v4:
- Rebased to the latest
Signed-off-by: Mika Kahola mika.kah...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 70 +---
1 file changed, 32 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index d79421a..f199faa 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5433,28 +5433,6 @@ static int intel_mode_max_pixclk(struct drm_atomic_state
*state)
return max_pixclk;
}
-static int valleyview_modeset_global_pipes(struct drm_atomic_state *state,
- unsigned *prepare_pipes)
-{
- struct drm_i915_private *dev_priv = to_i915(state-dev);
- struct intel_crtc *intel_crtc;
- int max_pixclk = intel_mode_max_pixclk(state);
-
- if (max_pixclk 0)
- return max_pixclk;
-
- if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
- dev_priv-cdclk_freq)
- return 0;
-
- /* disable/enable all currently active pipes while we change cdclk */
- for_each_intel_crtc(state-dev, intel_crtc)
- if (intel_crtc-base.state-enable)
- *prepare_pipes |= (1 intel_crtc-pipe);
-
- return 0;
-}
-
static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
{
unsigned int credits, default_credits;
@@ -9265,21 +9243,47 @@ static void broadwell_set_cdclk(struct drm_device *dev,
int cdclk)
cdclk, dev_priv-cdclk_freq);
}
-static void haswell_modeset_global_pipes(struct drm_atomic_state *state,
-unsigned *prepare_pipes)
+static int intel_calc_cdclk(struct drm_device *dev, int max_pixclk)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ int cdclk = 20;
+
+ if (IS_VALLEYVIEW(dev))
+ cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
+ else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+ cdclk = haswell_calc_cdclk(dev_priv, max_pixclk);
+
+ return cdclk;
+}
+
+static void intel_modeset_global_pipes(struct drm_atomic_state *state,
+unsigned *prepare_pipes,
+unsigned disable_pipes)
{
struct drm_device *dev = state-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
struct intel_crtc *crtc;
- int max_pixel_rate = ilk_max_pixel_rate(dev_priv);
+ int max_pixclk;
- if (haswell_calc_cdclk(dev_priv, max_pixel_rate) ==
dev_priv-cdclk_freq)
+ /* this modeset is valid only for VLV, HSW, and BDW */
+ if (!IS_VALLEYVIEW(dev) !IS_HASWELL(dev) !IS_BROADWELL(dev))
+ return;
+
+ if (IS_VALLEYVIEW(dev))
+ max_pixclk = intel_mode_max_pixclk(state);
+ else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+ max_pixclk = ilk_max_pixel_rate(dev_priv);
+
+ if (intel_calc_cdclk(dev, max_pixclk) == dev_priv-cdclk_freq)
return;
/* disable/enable all currently active pipes while we change cdclk */
for_each_intel_crtc(dev, crtc)
- if (crtc-base.enabled)
+ if (crtc-base.state-enable)
*prepare_pipes |= 1 crtc-pipe;
+
+ /* may have added more to prepare_pipes than we should */
+ *prepare_pipes = ~disable_pipes;
}
static void haswell_modeset_global_resources(struct drm_atomic_state *state)
@@ -12453,17 +12457,7 @@ static int __intel_set_mode(struct drm_crtc *crtc,
* mode set on this crtc. For other crtcs we need to use the
* adjusted_mode bits in the crtc directly.
*/
- if (IS_VALLEYVIEW(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
- if (IS_VALLEYVIEW(dev))
- valleyview_modeset_global_pipes(state, prepare_pipes);
- else
- haswell_modeset_global_pipes(state, prepare_pipes);
- if (ret)
- goto done;
-
- /* may have added more to prepare_pipes than we should */
- prepare_pipes = ~disable_pipes;
- }
+ intel_modeset_global_pipes(state, prepare_pipes, disable_pipes);
ret = __intel_set_mode_setup_plls(state, modeset_pipes, disable_pipes);
if (ret)
--
1.9.1
[Intel-gfx] [PATCH 02/14] drm/i915: Fix 852GM/GMV cdclk
It seems 852GM/GMV uses a different HPLLCC encoding than the other
85x platforms. For 852GM/GMV cdclk is always 133MHz. Try to detect that
using the PCI revision (sinc the device ID seems useless for that). I'm
not at all sure this is a good idea, but according to the specs it
should work.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Mika Kahola mika.kah...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 71123c7..7afde69 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6305,6 +6305,14 @@ static int i85x_get_display_clock_speed(struct
drm_device *dev)
{
u16 hpllcc = 0;
+ /*
+* 852GM/852GMV only supports 133 MHz and the HPLLCC
+* encoding is different :(
+* FIXME is this the right way to detect 852GM/852GMV?
+*/
+ if (dev-pdev-revision == 0x1)
+ return 13;
+
pci_bus_read_config_word(dev-pdev-bus,
PCI_DEVFN(0, 3), HPLLCC, hpllcc);
--
1.9.1
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Re: [Intel-gfx] [PATCH] intel: Leak the userptr test bo
On 04/14/2015 05:31 PM, Chris Wilson wrote: In order to use userptr, the kernel tracks the owner's mm with a mmu_notifier. Setting that is very expensive - it involves taking all mm_locks and a stop_machine(). This tracking lives only for as long as the client is using userptr objects - so if the client allocates then frees a userptr in a loop, we will be executing that heavyweight setup everytime. To ammoritize this cost, just leak the test bo and the single Spellcheck on this line. Also, if drm_intel_bufmgr_destroy is what I think it is, I think for correctness we would need to release that stuff there. What do you think? I could respin it with that if you are too busy? Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 34/49] drm/i915/bxt: Restrict PORT_CLK_SEL programming below gen9
From: Satheeshakrishna M satheeshakrishn...@intel.com
PORT_CLK_SEL programming is needed only on HSW/BDW.
v2:
- don't program PORT_CLK_SEL from mst encoders either (imre)
v3:
- fix the check for GEN9+ in intel_mst_pre_enable_dp() (damien)
Signed-off-by: Satheeshakrishna M satheeshakrishn...@intel.com
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/intel_ddi.c| 4 ++--
drivers/gpu/drm/i915/intel_dp_mst.c | 6 --
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 31cadb8..6bdccb2 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1565,7 +1565,7 @@ static void intel_ddi_pre_enable(struct intel_encoder
*intel_encoder)
I915_WRITE(DPLL_CTRL2, val);
- } else {
+ } else if (INTEL_INFO(dev)-gen 9) {
WARN_ON(crtc-config-ddi_pll_sel == PORT_CLK_SEL_NONE);
I915_WRITE(PORT_CLK_SEL(port), crtc-config-ddi_pll_sel);
}
@@ -1624,7 +1624,7 @@ static void intel_ddi_post_disable(struct intel_encoder
*intel_encoder)
if (IS_SKYLAKE(dev))
I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
DPLL_CTRL2_DDI_CLK_OFF(port)));
- else
+ else if (INTEL_INFO(dev)-gen 9)
I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
}
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
b/drivers/gpu/drm/i915/intel_dp_mst.c
index 7335089..3945057 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -173,8 +173,10 @@ static void intel_mst_pre_enable_dp(struct intel_encoder
*encoder)
if (intel_dp-active_mst_links == 0) {
enum port port = intel_ddi_get_encoder_port(encoder);
- I915_WRITE(PORT_CLK_SEL(port),
- intel_crtc-config-ddi_pll_sel);
+ /* FIXME: add support for SKL */
+ if (INTEL_INFO(dev)-gen 9)
+ I915_WRITE(PORT_CLK_SEL(port),
+ intel_crtc-config-ddi_pll_sel);
intel_ddi_init_dp_buf_reg(intel_dig_port-base);
--
2.1.0
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Re: [Intel-gfx] [PATCH v4 30/49] drm/i915/bxt: add display initialize/uninitialize sequence (CDCLK)
On Wed, Apr 15, 2015 at 04:42:56PM +0300, Imre Deak wrote:
From: Vandana Kannan vandana.kan...@intel.com
Add CDCLK specific display clock initialization sequence as per BSpec.
Note that the CDCLK initialization/uninitialization are done at their
current place only for simplicity, in a future patch - when more of the
runtime PM features will be enabled - these will be moved to power
well#1 and modeset encoder enabling/disabling hooks respectively. This
also means that atm dynamic power gating power well #1 is effectively
disabled.
The call to uninitialize CDCLK during system/runtime suspend will be
added later in this patchset.
v1: Added function definitions in header files
v2: Imre's review comments addressed
- Moved CDCLK related definitions to i915_reg.h
- Removed defintions for CDCLK frequency
- Split uninit_cdclk() by adding a phy_uninit function
- Calculate freq and decimal based on input frequency
- Program SSA precharge based on input frequency
- Use wait_for 1ms instead 200us udelay for DE PLL locking
- Removed initial value for divider, freq, decimal, ratio.
- Replaced polling loops with wait_for
- Parameterized latency optim setting
- Fix the parts where DE PLL has to be disabled.
- Call CDCLK selection from mode set
v3: (imre)
- add note about the plan to move the cdclk/phy init to a better place
- take rps.hw_lock around pcode access
- move DE PLL register macros here from another patch since they are
used here first
- add BXT_ prefix to CDCLK flags
- add missing masking when programming CDCLK_FREQ_DECIMAL
v4: (ville)
- split the CDCLK/PHY parts into two patches, update commit message
accordingly
- s/DISPLAY_PCU_CONTROL/HSW_PCODE_DE_WRITE_FREQ_REQ/
- simplify BXT_DE_PLL_RATIO macros
- fix BXT_DE_PLL_RATIO_MASK
- s/bxt_select_cdclk_freq/broxton_set_cdclk_freq/
- move cdclk init/uninit/set code from intel_ddi.c to intel_display.c
- remove redundant code comments for broxton_set_cdclk_freq()
- sanitize fixed point-integer frequency value conversion
- use DRM_ERROR instead of WARN
- do RMW when programming BXT_DE_PLL_CTL for safety
- add note about PLL lock timeout being exactly 200us
- make PCU error messages more descriptive
- instead of using 0 freq to mean PLL off/bypass freq use 19200
for clarity, as the latter one is the actual rate
- simplify pcode programming, removing duplicated
sandybridge_pcode_write() call
- sanitize code flow, remove unnecessary scratch vars in
broxton_set_cdclk() (imre)
- Remove bound check for maxmimum freq to match current code.
This check will be added later at a more proper platform
independent place once atomic support lands.
- add note to remove freq guard band which isn't needed on BXT
- add note to reduce freq to minimum if no pipe is enabled
- combine broxton_modeset_global_pipes() with
valleyview_modeset_global_pipes()
Signed-off-by: Vandana Kannan vandana.kan...@intel.com (v2)
Signed-off-by: Imre Deak imre.d...@intel.com
That's quite a changelog I caused. Sorry :)
But I like how it's looking now. A few minor FIXMEs in there, but I
agree that those can be dealt with later.
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 20
drivers/gpu/drm/i915/intel_ddi.c | 2 +
drivers/gpu/drm/i915/intel_display.c | 226
++-
drivers/gpu/drm/i915/intel_drv.h | 3 +
4 files changed, 248 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4b53b20..c79bf8d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5452,6 +5452,9 @@ enum skl_disp_power_wells {
#define DISP_FBC_WM_DIS (115)
#define DISP_ARB_CTL20x45004
#define DISP_DATA_PARTITION_5_6 (16)
+#define DBUF_CTL 0x45008
+#define DBUF_POWER_REQUEST (131)
+#define DBUF_POWER_STATE(130)
#define GEN7_MSG_CTL 0x45010
#define WAIT_FOR_PCH_RESET_ACK (11)
#define WAIT_FOR_PCH_FLR_ACK(10)
@@ -6403,6 +6406,7 @@ enum skl_disp_power_wells {
#define GEN6_PCODE_WRITE_D_COMP0x11
#define GEN6_ENCODE_RC6_VID(mv)(((mv) - 245) / 5)
#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
+#define HSW_PCODE_DE_WRITE_FREQ_REQ0x17
#define DISPLAY_IPS_CONTROL0x19
#defineHSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
#define GEN6_PCODE_DATA 0x138128
@@ -6874,6 +6878,13 @@ enum skl_disp_power_wells {
#define CDCLK_FREQ_675_617 (326)
#define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
+#define BXT_CDCLK_CD2X_DIV_SEL_MASK (322)
+#define BXT_CDCLK_CD2X_DIV_SEL_1(022)
+#define BXT_CDCLK_CD2X_DIV_SEL_1_5 (122)
+#define BXT_CDCLK_CD2X_DIV_SEL_2(222)
+#define BXT_CDCLK_CD2X_DIV_SEL_4(322)
[Intel-gfx] [PATCH v4 33/49] drm/i915/bxt: Add DC9 Trigger sequence
From: Suketu Shah suketu.j.s...@intel.com
Add triggers for DC9 as per details provided in bxt_enable_dc9
and bxt_disable_dc9 implementations.
v1:
- Add SKL check in gen9_disable_dc5 as it is possible for DC5
to remain disabled only for SKL.
- Add additional checks for whether DC5 is already disabled during
DC5-disabling only for BXT.
v2:
- rebase to latest.
- Load CSR during DC9 disabling in the beginning before DC9 is
disabled.
- Make gen9_disable_dc5 function non-static as it's being called by
functions in i915_drv.c.
- Enable DC9-related functionality using a macro.
v3: (imre)
- remove BXT_ENABLE_DC9, we want DC9 always, and it's only valid on BXT
- remove DC5 disabling and CSR FW loaded check, these are nop atm
- squash in Vandana's Do ddi_phy_init always patch
v4:
- add TODO to re-enable DC5 during resume if CSR FW is available (sagar)
Signed-off-by: Suketu Shah suketu.j.s...@intel.com
Signed-off-by: A.Sunil Kamath sunil.kam...@intel.com (v2)
Signed-off-by: Imre Deak imre.d...@intel.com
Reviewed-by: Sagar Kamble sagar.a.kam...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 39 ++-
1 file changed, 38 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index c3fdbb0..f9754c3 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1009,6 +1009,38 @@ static int hsw_suspend_complete(struct drm_i915_private
*dev_priv)
return 0;
}
+static int bxt_suspend_complete(struct drm_i915_private *dev_priv)
+{
+ struct drm_device *dev = dev_priv-dev;
+
+ /* TODO: when DC5 support is added disable DC5 here. */
+
+ broxton_ddi_phy_uninit(dev);
+ broxton_uninit_cdclk(dev);
+ bxt_enable_dc9(dev_priv);
+
+ return 0;
+}
+
+static int bxt_resume_prepare(struct drm_i915_private *dev_priv)
+{
+ struct drm_device *dev = dev_priv-dev;
+
+ /* TODO: when CSR FW support is added make sure the FW is loaded */
+
+ bxt_disable_dc9(dev_priv);
+
+ /*
+* TODO: when DC5 support is added enable DC5 here if the CSR FW
+* is available.
+*/
+ broxton_init_cdclk(dev);
+ broxton_ddi_phy_init(dev);
+ intel_prepare_ddi(dev);
+
+ return 0;
+}
+
/*
* Save all Gunit registers that may be lost after a D3 and a subsequent
* S0i[R123] transition. The list of registers needing a save/restore is
@@ -1467,6 +1499,9 @@ static int intel_runtime_resume(struct device *device)
if (IS_GEN6(dev_priv))
intel_init_pch_refclk(dev);
+
+ if (IS_BROXTON(dev))
+ ret = bxt_resume_prepare(dev_priv);
else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
hsw_disable_pc8(dev_priv);
else if (IS_VALLEYVIEW(dev_priv))
@@ -1499,7 +1534,9 @@ static int intel_suspend_complete(struct drm_i915_private
*dev_priv)
struct drm_device *dev = dev_priv-dev;
int ret;
- if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+ if (IS_BROXTON(dev))
+ ret = bxt_suspend_complete(dev_priv);
+ else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ret = hsw_suspend_complete(dev_priv);
else if (IS_VALLEYVIEW(dev))
ret = vlv_suspend_complete(dev_priv);
--
2.1.0
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[Intel-gfx] [PATCH v2 35/49] drm/i915/bxt: fix panel fitter setup in crtc disable/enable
From: Jesse Barnes jbar...@virtuousgeek.org
Broxton has the same panel fitter registers as Skylake.
v2:
- add MISSING_CASE for future platforms (daniel)
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Imre Deak imre.d...@intel.com
Reviewed-by: Sagar Kamble sagar.a.kam...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 19 +--
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 5ee5d8c..11281f4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4881,10 +4881,12 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
intel_ddi_enable_pipe_clock(intel_crtc);
- if (IS_SKYLAKE(dev))
+ if (INTEL_INFO(dev)-gen == 9)
skylake_pfit_update(intel_crtc, 1);
- else
+ else if (INTEL_INFO(dev)-gen 9)
ironlake_pfit_enable(intel_crtc);
+ else
+ MISSING_CASE(INTEL_INFO(dev)-gen);
/*
* On ILK+ LUT must be loaded before the pipe is running but with
@@ -5029,10 +5031,12 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
- if (IS_SKYLAKE(dev))
+ if (INTEL_INFO(dev)-gen == 9)
skylake_pfit_update(intel_crtc, 0);
- else
+ else if (INTEL_INFO(dev)-gen 9)
ironlake_pfit_disable(intel_crtc);
+ else
+ MISSING_CASE(INTEL_INFO(dev)-gen);
intel_ddi_disable_pipe_clock(intel_crtc);
@@ -9199,10 +9203,13 @@ static bool haswell_get_pipe_config(struct intel_crtc
*crtc,
pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc-pipe);
if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
- if (IS_SKYLAKE(dev))
+ if (INTEL_INFO(dev)-gen == 9)
skylake_get_pfit_config(crtc, pipe_config);
- else
+ else if (INTEL_INFO(dev)-gen 9)
ironlake_get_pfit_config(crtc, pipe_config);
+ else
+ MISSING_CASE(INTEL_INFO(dev)-gen);
+
} else {
pipe_config-scaler_state.scaler_id = -1;
pipe_config-scaler_state.scaler_users = ~(1
SKL_CRTC_INDEX);
--
2.1.0
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[Intel-gfx] [PULL] topic/drm-misc
Hi Dave,
One more drm-misch pull for 4.1 with mostly simple stuff and boring
refactoring. Even the cursor fix from Matt is just to make a really anal
igt happy.
Cheers, Daniel
The following changes since commit 502e95c6678505474f1056480310cd9382bacbac:
drm/vgem: implement virtual GEM (2015-04-02 09:21:48 +1000)
are available in the git repository at:
git://anongit.freedesktop.org/drm-intel tags/topic/drm-misc-2015-04-15
for you to fetch changes up to 2b1193d5287004edfbf89407149a3159656f47f1:
drm: fix trivial typo mistake (2015-04-14 12:41:03 +0200)
Ander Conselvan de Oliveira (1):
drm/atomic: Add for_each_{connector,crtc,plane}_in_state helper macros
Jani Nikula (11):
drm/exynos: constify all struct drm_*_helper funcs pointers
drm/mgag200: constify all struct drm_*_helper funcs pointers
drm/gma500: constify all struct drm_*_helper funcs pointers
drm/radeon: constify all struct drm_*_helper funcs pointers
drm/nouveau: constify all struct drm_*_helper funcs pointers
drm/qxl: constify all struct drm_*_helper funcs pointers
drm/drm: constify all struct drm_*_helper funcs pointers
drm/edid: add #defines for ELD versions
drm/radeon: constify more struct drm_*_helper funcs pointers
drm/armada: constify struct drm_encoder_helper_funcs pointer
drm: make crtc/encoder/connector/plane helper_private a const pointer
John Hunter (2):
drm: Fix some typos
drm: fix trivial typo mistake
Maarten Lankhorst (1):
drm: Use kref_put_mutex in drm_gem_object_unreference_unlocked
Matt Roper (1):
drm: Make integer overflow checking cover universal cursor updates (v2)
drivers/gpu/drm/armada/armada_output.h | 2 +-
drivers/gpu/drm/drm_atomic.c| 66 ++-
drivers/gpu/drm/drm_atomic_helper.c | 253 +++-
drivers/gpu/drm/drm_crtc.c | 22 +--
drivers/gpu/drm/drm_crtc_helper.c | 24 +--
drivers/gpu/drm/drm_fb_helper.c | 8 +-
drivers/gpu/drm/drm_plane_helper.c | 4 +-
drivers/gpu/drm/drm_probe_helper.c | 2 +-
drivers/gpu/drm/exynos/exynos_hdmi.c| 2 +-
drivers/gpu/drm/gma500/cdv_intel_display.c | 2 +-
drivers/gpu/drm/gma500/cdv_intel_hdmi.c | 2 +-
drivers/gpu/drm/gma500/cdv_intel_lvds.c | 2 +-
drivers/gpu/drm/gma500/gma_display.c| 10 +-
drivers/gpu/drm/gma500/mdfld_dsi_output.c | 2 +-
drivers/gpu/drm/gma500/mdfld_intel_display.c| 2 +-
drivers/gpu/drm/gma500/oaktrail_crtc.c | 2 +-
drivers/gpu/drm/gma500/oaktrail_hdmi.c | 2 +-
drivers/gpu/drm/gma500/psb_intel_display.c | 2 +-
drivers/gpu/drm/gma500/psb_intel_lvds.c | 2 +-
drivers/gpu/drm/mgag200/mgag200_mode.c | 2 +-
drivers/gpu/drm/nouveau/dispnv04/crtc.c | 4 +-
drivers/gpu/drm/nouveau/dispnv04/dac.c | 4 +-
drivers/gpu/drm/nouveau/dispnv04/dfp.c | 4 +-
drivers/gpu/drm/nouveau/dispnv04/disp.c | 6 +-
drivers/gpu/drm/nouveau/dispnv04/tvnv04.c | 4 +-
drivers/gpu/drm/nouveau/dispnv04/tvnv17.c | 4 +-
drivers/gpu/drm/nouveau/nouveau_connector.c | 4 +-
drivers/gpu/drm/qxl/qxl_drv.c | 2 +-
drivers/gpu/drm/radeon/radeon_connectors.c | 20 +-
drivers/gpu/drm/radeon/radeon_dp_mst.c | 2 +-
drivers/gpu/drm/radeon/radeon_legacy_encoders.c | 2 +-
include/drm/drm_atomic.h| 24 +++
include/drm/drm_crtc.h | 10 +-
include/drm/drm_crtc_helper.h | 6 +-
include/drm/drm_edid.h | 2 +
include/drm/drm_gem.h | 14 +-
include/drm/drm_plane_helper.h | 2 +-
37 files changed, 213 insertions(+), 314 deletions(-)
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH 2/2] drm/i915: Log view type when printing warnings
I ended up needing this bit too, so maybe better have it committed. On ti, 2015-03-17 at 14:45 +, Tvrtko Ursulin wrote: From: Tvrtko Ursulin tvrtko.ursu...@intel.com It may save someone a bit of debugging time one day. Signed-off-by: Tvrtko Ursulin tvrtko.ursu...@intel.com Reviewed-by: Joonas Lahtinen joonas.lahti...@linux.intel.com Cc: Joonas Lahtinen joonas.lahti...@linux.intel.com --- drivers/gpu/drm/i915/i915_gem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index cc8672a..e150038 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -5267,7 +5267,7 @@ i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o, if (vma-vm == ggtt vma-ggtt_view.type == view) return vma-node.start; - WARN(1, global vma for this object not found.\n); + WARN(1, global vma for this object not found. (view=%u)\n, view); return -1; } ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] All sort of cdclk stuff
Hi Mika, On Wed, Apr 15, 2015 at 04:07:10PM +0300, Mika Kahola wrote: This patch series rebases Ville's original cdclk patch series excluding the ones that have been reviewed. I believe you still have the authorship problem in that series. It'll be great to have it fixed so Daniel doesn't pull those ones by mistake. Thanks! -- Damien ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 31/49] drm/i915/bxt: add description about the BXT PHYs
On Wed, Apr 15, 2015 at 04:42:58PM +0300, Imre Deak wrote:
Extend the VLV/CHV DPIO (PHY) documentation with the BXT specifics.
v2:
- add more detail about the mapping between ports and transcoders (ville)
Signed-off-by: Imre Deak imre.d...@intel.com
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
Documentation/DocBook/drm.tmpl | 4 ++--
drivers/gpu/drm/i915/i915_reg.h | 18 --
2 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl
index f4976cd..a8509c2 100644
--- a/Documentation/DocBook/drm.tmpl
+++ b/Documentation/DocBook/drm.tmpl
@@ -4067,7 +4067,7 @@ int num_ioctls;/synopsis
titleDPIO/title
!Pdrivers/gpu/drm/i915/i915_reg.h DPIO
table id=dpiox2
- titleDual channel PHY (VLV/CHV)/title
+ titleDual channel PHY (VLV/CHV/BXT)/title
tgroup cols=8
colspec colname=c0 /
colspec colname=c1 /
@@ -4118,7 +4118,7 @@ int num_ioctls;/synopsis
/tgroup
/table
table id=dpiox1
- titleSingle channel PHY (CHV)/title
+ titleSingle channel PHY (CHV/BXT)/title
tgroup cols=4
colspec colname=c0 /
colspec colname=c1 /
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1903e37..abea462 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -715,7 +715,7 @@ enum skl_disp_power_wells {
/**
* DOC: DPIO
*
- * VLV and CHV have slightly peculiar display PHYs for driving DP/HDMI
+ * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI
* ports. DPIO is the name given to such a display PHY. These PHYs
* don't follow the standard programming model using direct MMIO
* registers, and instead their registers must be accessed trough IOSF
@@ -746,7 +746,7 @@ enum skl_disp_power_wells {
* controlled from the display controller side. No DPIO registers
* need to be accessed during AUX communication,
*
- * Generally the common lane corresponds to the pipe and
+ * Generally on VLV/CHV the common lane corresponds to the pipe and
* the spline (PCS/TX) corresponds to the port.
*
* For dual channel PHY (VLV/CHV):
@@ -768,11 +768,17 @@ enum skl_disp_power_wells {
*
* port D == PCS/TX CH0
*
- * Note: digital port B is DDI0, digital port C is DDI1,
- * digital port D is DDI2
+ * On BXT the entire PHY channel corresponds to the port. That means
+ * the PLL is also now associated with the port rather than the pipe,
+ * and so the clock needs to be routed to the appropriate transcoder.
+ * Port A PLL is directly connected to transcoder EDP and port B/C
+ * PLLs can be routed to any transcoder A/B/C.
+ *
+ * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is
+ * digital port D (CHV) or port A (BXT).
*/
/*
- * Dual channel PHY (VLV/CHV)
+ * Dual channel PHY (VLV/CHV/BXT)
* -
* | CH0 | CH1 |
* | CMN/PLL/REF | CMN/PLL/REF |
@@ -784,7 +790,7 @@ enum skl_disp_power_wells {
* | DDI0 | DDI1 | DP/HDMI ports
* -
*
- * Single channel PHY (CHV)
+ * Single channel PHY (CHV/BXT)
* -
* | CH0 |
* | CMN/PLL/REF |
--
2.1.0
--
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH] drm/vblank: Fixup and document timestamp update/read barriers
Hi Daniel,
On 04/15/2015 03:17 AM, Daniel Vetter wrote:
This was a bit too much cargo-culted, so lets make it solid:
- vblank-count doesn't need to be an atomic, writes are always done
under the protection of dev-vblank_time_lock. Switch to an unsigned
long instead and update comments. Note that atomic_read is just a
normal read of a volatile variable, so no need to audit all the
read-side access specifically.
- The barriers for the vblank counter seqlock weren't complete: The
read-side was missing the first barrier between the counter read and
the timestamp read, it only had a barrier between the ts and the
counter read. We need both.
- Barriers weren't properly documented. Since barriers only work if
you have them on boths sides of the transaction it's prudent to
reference where the other side is. To avoid duplicating the
write-side comment 3 times extract a little store_vblank() helper.
In that helper also assert that we do indeed hold
dev-vblank_time_lock, since in some cases the lock is acquired a
few functions up in the callchain.
Spotted while reviewing a patch from Chris Wilson to add a fastpath to
the vblank_wait ioctl.
Cc: Chris Wilson ch...@chris-wilson.co.uk
Cc: Mario Kleiner mario.kleiner...@gmail.com
Cc: Ville Syrjälä ville.syrj...@linux.intel.com
Cc: Michel Dänzer mic...@daenzer.net
Signed-off-by: Daniel Vetter daniel.vet...@intel.com
---
drivers/gpu/drm/drm_irq.c | 92
---
include/drm/drmP.h| 8 +++--
2 files changed, 54 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c
index c8a34476570a..23bfbc61a494 100644
--- a/drivers/gpu/drm/drm_irq.c
+++ b/drivers/gpu/drm/drm_irq.c
@@ -74,6 +74,33 @@ module_param_named(vblankoffdelay, drm_vblank_offdelay,
int, 0600);
module_param_named(timestamp_precision_usec, drm_timestamp_precision, int,
0600);
module_param_named(timestamp_monotonic, drm_timestamp_monotonic, int, 0600);
+static void store_vblank(struct drm_device *dev, int crtc,
+ unsigned vblank_count_inc,
+ struct timeval *t_vblank)
+{
+ struct drm_vblank_crtc *vblank = dev-vblank[crtc];
+ u32 tslot;
+
+ assert_spin_locked(dev-vblank_time_lock);
+
+ if (t_vblank) {
+ tslot = vblank-count + vblank_count_inc;
+ vblanktimestamp(dev, crtc, tslot) = *t_vblank;
+ }
+
+ /*
+ * vblank timestamp updates are protected on the write side with
+ * vblank_time_lock, but on the read side done locklessly using a
+ * sequence-lock on the vblank counter. Ensure correct ordering using
+ * memory barrriers. We need the barrier both before and also after the
+ * counter update to synchronize with the next timestamp write.
+ * The read-side barriers for this are in drm_vblank_count_and_time.
+ */
+ smp_wmb();
+ vblank-count += vblank_count_inc;
+ smp_wmb();
The comment and the code are each self-contradictory.
If vblank-count writes are always protected by vblank_time_lock (something I
did not verify but that the comment above asserts), then the trailing write
barrier is not required (and the assertion that it is in the comment is
incorrect).
A spin unlock operation is always a write barrier.
Regards,
Peter Hurley
+}
+
/**
* drm_update_vblank_count - update the master vblank counter
* @dev: DRM device
@@ -93,7 +120,7 @@ module_param_named(timestamp_monotonic,
drm_timestamp_monotonic, int, 0600);
static void drm_update_vblank_count(struct drm_device *dev, int crtc)
{
struct drm_vblank_crtc *vblank = dev-vblank[crtc];
- u32 cur_vblank, diff, tslot;
+ u32 cur_vblank, diff;
bool rc;
struct timeval t_vblank;
@@ -129,18 +156,12 @@ static void drm_update_vblank_count(struct drm_device
*dev, int crtc)
if (diff == 0)
return;
- /* Reinitialize corresponding vblank timestamp if high-precision query
- * available. Skip this step if query unsupported or failed. Will
- * reinitialize delayed at next vblank interrupt in that case.
+ /*
+ * Only reinitialize corresponding vblank timestamp if high-precision
query
+ * available and didn't fail. Will reinitialize delayed at next vblank
+ * interrupt in that case.
*/
- if (rc) {
- tslot = atomic_read(vblank-count) + diff;
- vblanktimestamp(dev, crtc, tslot) = t_vblank;
- }
-
- smp_mb__before_atomic();
- atomic_add(diff, vblank-count);
- smp_mb__after_atomic();
+ store_vblank(dev, crtc, diff, rc ? t_vblank : NULL);
}
/*
@@ -218,7 +239,7 @@ static void vblank_disable_and_save(struct drm_device
*dev, int crtc)
/* Compute time difference to stored timestamp of last vblank
* as updated by last invocation of drm_handle_vblank() in vblank
Re: [Intel-gfx] All sort of cdclk stuff
On Wed, Apr 15, 2015 at 04:07:10PM +0300, Mika Kahola wrote: This patch series rebases Ville's original cdclk patch series excluding the ones that have been reviewed. http://lists.freedesktop.org/archives/intel-gfx/2014-November/055633.html The patches include modifications to BTW it would be a good idaa to include some kind of version number note on the whole series as well. Otherwise it could get a bit hard to find out which was the latest one. So the usual form is [PATCH vN 00/MM] ... or something like that. Also 'git format-patch --cover-letter ...' will generate a reasonably nice template for your cover letter with shortlog included. drm/i915: Fix i855_get_display_clock_speed() drm/i915: Fix 852GM/GMV cdclk drm/i915: Add cdclk extraction for g33, 965gm and g4x drm/i915: Warn when cdclk for the platforms is not known drm/i915: Cache the current cdclk frequency in dev_priv drm/i915: Use cached cdclk value drm/i915: Unify ilk and hsw .get_aux_clock_divider() drm/i915: Store max cdclk value in dev_priv drm/i915: Don't enable IPS when pixel rate exceeds 95% of cdclk drm/i915: HSW cdclk change support drm/i915: Add IS_BDW_ULX() drm/i915: BDW cdclk change support drm/i915: Limit CHV max cdclk to 320 MHz drm/i915: Modeset global_pipes() update ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] All sort of cdclk stuff
Hi, I forgot to update authorships. I'll fix this and resend the patch series. Thanks for pointing this out! -Mika- On Wed, 2015-04-15 at 14:16 +0100, Damien Lespiau wrote: Hi Mika, On Wed, Apr 15, 2015 at 04:07:10PM +0300, Mika Kahola wrote: This patch series rebases Ville's original cdclk patch series excluding the ones that have been reviewed. I believe you still have the authorship problem in that series. It'll be great to have it fixed so Daniel doesn't pull those ones by mistake. Thanks! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3] drm/i915/chv: Implement WaDisableShadowRegForCpd
From: Deepak S deepa...@linux.intel.com
This WA is avoid problem between shadow vs wake FIFO unload
problem during CPD/RC6 transactions on CHV.
v2: Define individual bits GTFIFOCTL (Ville)
v3: move WA to uncore_early_sanitize (ville)
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_uncore.c | 8
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9c97842..a642a58 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6206,6 +6206,8 @@ enum skl_disp_power_wells {
#define GTFIFOCTL 0x120008
#defineGT_FIFO_FREE_ENTRIES_MASK 0x7f
#defineGT_FIFO_NUM_RESERVED_ENTRIES20
+#define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 12)
+#define GT_FIFO_CTL_RC6_POLICY_STALL (1 11)
#define HSW_IDICR 0x9008
#defineIDIHASHMSK(x) (((x) 0x3f) 16)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index d96d15f..26d6dda 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -360,6 +360,14 @@ static void __intel_uncore_early_sanitize(struct
drm_device *dev,
__raw_i915_write32(dev_priv, GTFIFODBG,
__raw_i915_read32(dev_priv, GTFIFODBG));
+ /* WaDisableShadowRegForCpd */
+ if (IS_CHERRYVIEW(dev)) {
+ __raw_i915_write32(dev_priv, GTFIFOCTL,
+ __raw_i915_read32(dev_priv, GTFIFOCTL) |
+
GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
+ GT_FIFO_CTL_RC6_POLICY_STALL);
+ }
+
intel_uncore_forcewake_reset(dev, restore_forcewake);
}
--
1.9.1
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Re: [Intel-gfx] [PATCH] intel: Leak the userptr test bo
On Wed, Apr 15, 2015 at 03:08:56PM +0100, Tvrtko Ursulin wrote: On 04/14/2015 05:31 PM, Chris Wilson wrote: In order to use userptr, the kernel tracks the owner's mm with a mmu_notifier. Setting that is very expensive - it involves taking all mm_locks and a stop_machine(). This tracking lives only for as long as the client is using userptr objects - so if the client allocates then frees a userptr in a loop, we will be executing that heavyweight setup everytime. To ammoritize this cost, just leak the test bo and the single Spellcheck on this line. Also, if drm_intel_bufmgr_destroy is what I think it is, I think for correctness we would need to release that stuff there. What do you think? I could respin it with that if you are too busy? I contemplated it, then decided I was too lazy to store a couple of pointers. If you want to respin with that and push, please do. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PULL] drm-intel-next-fixes
Hi Dave - As promised, here's a batch of fixes for drm-next/4.1. BR, Jani. The following changes since commit 6e0aa8018f9c676b115b7ca6c20a056fc57c68a9: Merge tag 'v4.0-rc6' into drm-intel-next (2015-03-30 16:37:08 +0200) are available in the git repository at: git://anongit.freedesktop.org/drm-intel tags/drm-intel-next-fixes-2015-04-15 for you to fetch changes up to 37ef01ab5d24d1d520dc79f6a98099d451c2a901: drm/i915: Dont enable CS_PARSER_ERROR interrupts at all (2015-04-14 17:03:12 +0300) Ander Conselvan de Oliveira (1): drm/i915: Allocate connector state together with the connectors Clint Taylor (1): drm/i915/chv: Remove DPIO force latency causing interpair skew issue Daniel Vetter (3): drm/i915: Fix locking in DRRS flush/invalidate hooks drm/i915: Don't cancel DRRS worker synchronously for flush/invalidate drm/i915: Dont enable CS_PARSER_ERROR interrupts at all Tvrtko Ursulin (1): drm/i915: Move drm_framebuffer_unreference out of struct_mutex for takeover drivers/gpu/drm/i915/i915_irq.c | 8 +--- drivers/gpu/drm/i915/intel_crt.c | 2 +- drivers/gpu/drm/i915/intel_ddi.c | 4 +- drivers/gpu/drm/i915/intel_display.c | 76 +--- drivers/gpu/drm/i915/intel_dp.c | 33 +--- drivers/gpu/drm/i915/intel_dp_mst.c | 2 +- drivers/gpu/drm/i915/intel_drv.h | 2 + drivers/gpu/drm/i915/intel_dsi.c | 2 +- drivers/gpu/drm/i915/intel_dvo.c | 2 +- drivers/gpu/drm/i915/intel_hdmi.c| 7 +--- drivers/gpu/drm/i915/intel_lvds.c| 6 +++ drivers/gpu/drm/i915/intel_sdvo.c| 22 +-- drivers/gpu/drm/i915/intel_tv.c | 2 +- 13 files changed, 91 insertions(+), 77 deletions(-) -- Jani Nikula, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/skl: Add back HDMI translation table
On Wed, Apr 15, 2015 at 11:02:33AM +0530, Sonika Jindal wrote:
The HDMI translation table is added back to bspec, so adding it,
and defaulting the 800mV+0dB entry.
The HDMI translation table was removed by following commit as per HW team's
recommendation:
commit 7ff446708bd1 (drm/i915/skl: Only use the 800mV+2bB HDMI translation
entry)
v2: Adding reference to commit which removed this table (Jani)
Cc: Damien Lespiau damien.lesp...@intel.com
Signed-off-by: Sonika Jindal sonika.jin...@intel.com
Reviewed-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/i915/intel_ddi.c | 22 --
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c
b/drivers/gpu/drm/i915/intel_ddi.c
index 5b50484..b974f8e 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -155,8 +155,17 @@ static const struct ddi_buf_trans
skl_ddi_translations_edp[] = {
static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
- /* Idx NT mV T mVdb */
- { 0x4014, 0x0087 }, /* 0: 800 10002 */
+ { 0x0018, 0x00ac },
+ { 0x5012, 0x009d },
+ { 0x7011, 0x0088 },
+ { 0x0018, 0x00a1 },
+ { 0x0018, 0x0098 },
+ { 0x4013, 0x0088 },
+ { 0x6012, 0x0087 },
+ { 0x0018, 0x00df },
+ { 0x3015, 0x0087 },
+ { 0x3015, 0x00c7 },
+ { 0x0018, 0x00c7 },
};
enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
@@ -214,16 +223,9 @@ static void intel_prepare_ddi_buffers(struct drm_device
*dev, enum port port)
n_edp_entries = ARRAY_SIZE(skl_ddi_translations_dp);
}
- /*
- * On SKL, the recommendation from the hw team is to always use
- * a certain type of level shifter (and thus the corresponding
- * 800mV+2dB entry). Given that's the only validated entry, we
- * override what is in the VBT, at least until further notice.
- */
- hdmi_level = 0;
ddi_translations_hdmi = skl_ddi_translations_hdmi;
n_hdmi_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
- hdmi_default_entry = 0;
+ hdmi_default_entry = 7;
} else if (IS_BROADWELL(dev)) {
ddi_translations_fdi = bdw_ddi_translations_fdi;
ddi_translations_dp = bdw_ddi_translations_dp;
--
1.7.10.4
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[Intel-gfx] [PATCH v4 30/49] drm/i915/bxt: add display initialize/uninitialize sequence (CDCLK)
From: Vandana Kannan vandana.kan...@intel.com
Add CDCLK specific display clock initialization sequence as per BSpec.
Note that the CDCLK initialization/uninitialization are done at their
current place only for simplicity, in a future patch - when more of the
runtime PM features will be enabled - these will be moved to power
well#1 and modeset encoder enabling/disabling hooks respectively. This
also means that atm dynamic power gating power well #1 is effectively
disabled.
The call to uninitialize CDCLK during system/runtime suspend will be
added later in this patchset.
v1: Added function definitions in header files
v2: Imre's review comments addressed
- Moved CDCLK related definitions to i915_reg.h
- Removed defintions for CDCLK frequency
- Split uninit_cdclk() by adding a phy_uninit function
- Calculate freq and decimal based on input frequency
- Program SSA precharge based on input frequency
- Use wait_for 1ms instead 200us udelay for DE PLL locking
- Removed initial value for divider, freq, decimal, ratio.
- Replaced polling loops with wait_for
- Parameterized latency optim setting
- Fix the parts where DE PLL has to be disabled.
- Call CDCLK selection from mode set
v3: (imre)
- add note about the plan to move the cdclk/phy init to a better place
- take rps.hw_lock around pcode access
- move DE PLL register macros here from another patch since they are
used here first
- add BXT_ prefix to CDCLK flags
- add missing masking when programming CDCLK_FREQ_DECIMAL
v4: (ville)
- split the CDCLK/PHY parts into two patches, update commit message
accordingly
- s/DISPLAY_PCU_CONTROL/HSW_PCODE_DE_WRITE_FREQ_REQ/
- simplify BXT_DE_PLL_RATIO macros
- fix BXT_DE_PLL_RATIO_MASK
- s/bxt_select_cdclk_freq/broxton_set_cdclk_freq/
- move cdclk init/uninit/set code from intel_ddi.c to intel_display.c
- remove redundant code comments for broxton_set_cdclk_freq()
- sanitize fixed point-integer frequency value conversion
- use DRM_ERROR instead of WARN
- do RMW when programming BXT_DE_PLL_CTL for safety
- add note about PLL lock timeout being exactly 200us
- make PCU error messages more descriptive
- instead of using 0 freq to mean PLL off/bypass freq use 19200
for clarity, as the latter one is the actual rate
- simplify pcode programming, removing duplicated
sandybridge_pcode_write() call
- sanitize code flow, remove unnecessary scratch vars in
broxton_set_cdclk() (imre)
- Remove bound check for maxmimum freq to match current code.
This check will be added later at a more proper platform
independent place once atomic support lands.
- add note to remove freq guard band which isn't needed on BXT
- add note to reduce freq to minimum if no pipe is enabled
- combine broxton_modeset_global_pipes() with
valleyview_modeset_global_pipes()
Signed-off-by: Vandana Kannan vandana.kan...@intel.com (v2)
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 20
drivers/gpu/drm/i915/intel_ddi.c | 2 +
drivers/gpu/drm/i915/intel_display.c | 226 ++-
drivers/gpu/drm/i915/intel_drv.h | 3 +
4 files changed, 248 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4b53b20..c79bf8d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5452,6 +5452,9 @@ enum skl_disp_power_wells {
#define DISP_FBC_WM_DIS (115)
#define DISP_ARB_CTL2 0x45004
#define DISP_DATA_PARTITION_5_6 (16)
+#define DBUF_CTL 0x45008
+#define DBUF_POWER_REQUEST(131)
+#define DBUF_POWER_STATE (130)
#define GEN7_MSG_CTL 0x45010
#define WAIT_FOR_PCH_RESET_ACK(11)
#define WAIT_FOR_PCH_FLR_ACK (10)
@@ -6403,6 +6406,7 @@ enum skl_disp_power_wells {
#define GEN6_PCODE_WRITE_D_COMP 0x11
#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
#define GEN6_DECODE_RC6_VID(vids)(((vids) * 5) + 245)
+#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
#define DISPLAY_IPS_CONTROL 0x19
#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
#define GEN6_PCODE_DATA0x138128
@@ -6874,6 +6878,13 @@ enum skl_disp_power_wells {
#define CDCLK_FREQ_675_617(326)
#define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
+#define BXT_CDCLK_CD2X_DIV_SEL_MASK (322)
+#define BXT_CDCLK_CD2X_DIV_SEL_1 (022)
+#define BXT_CDCLK_CD2X_DIV_SEL_1_5(122)
+#define BXT_CDCLK_CD2X_DIV_SEL_2 (222)
+#define BXT_CDCLK_CD2X_DIV_SEL_4 (322)
+#define BXT_CDCLK_SSA_PRECHARGE_ENABLE(116)
+
/* LCPLL_CTL */
#define LCPLL1_CTL 0x46010
#define LCPLL2_CTL 0x46014
@@ -6938,6 +6949,15 @@ enum skl_disp_power_wells {
#define GET_CFG_CR1_REG(id) (DPLL1_CFGCR1 + (id - SKL_DPLL1) * 8)
#define GET_CFG_CR2_REG(id) (DPLL1_CFGCR2 + (id - SKL_DPLL1) * 8)
+/* BXT display engine PLL */
[Intel-gfx] [PATCH v2 31/49] drm/i915/bxt: add description about the BXT PHYs
Extend the VLV/CHV DPIO (PHY) documentation with the BXT specifics.
v2:
- add more detail about the mapping between ports and transcoders (ville)
Signed-off-by: Imre Deak imre.d...@intel.com
---
Documentation/DocBook/drm.tmpl | 4 ++--
drivers/gpu/drm/i915/i915_reg.h | 18 --
2 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl
index f4976cd..a8509c2 100644
--- a/Documentation/DocBook/drm.tmpl
+++ b/Documentation/DocBook/drm.tmpl
@@ -4067,7 +4067,7 @@ int num_ioctls;/synopsis
titleDPIO/title
!Pdrivers/gpu/drm/i915/i915_reg.h DPIO
table id=dpiox2
- titleDual channel PHY (VLV/CHV)/title
+ titleDual channel PHY (VLV/CHV/BXT)/title
tgroup cols=8
colspec colname=c0 /
colspec colname=c1 /
@@ -4118,7 +4118,7 @@ int num_ioctls;/synopsis
/tgroup
/table
table id=dpiox1
- titleSingle channel PHY (CHV)/title
+ titleSingle channel PHY (CHV/BXT)/title
tgroup cols=4
colspec colname=c0 /
colspec colname=c1 /
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1903e37..abea462 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -715,7 +715,7 @@ enum skl_disp_power_wells {
/**
* DOC: DPIO
*
- * VLV and CHV have slightly peculiar display PHYs for driving DP/HDMI
+ * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI
* ports. DPIO is the name given to such a display PHY. These PHYs
* don't follow the standard programming model using direct MMIO
* registers, and instead their registers must be accessed trough IOSF
@@ -746,7 +746,7 @@ enum skl_disp_power_wells {
* controlled from the display controller side. No DPIO registers
* need to be accessed during AUX communication,
*
- * Generally the common lane corresponds to the pipe and
+ * Generally on VLV/CHV the common lane corresponds to the pipe and
* the spline (PCS/TX) corresponds to the port.
*
* For dual channel PHY (VLV/CHV):
@@ -768,11 +768,17 @@ enum skl_disp_power_wells {
*
* port D == PCS/TX CH0
*
- * Note: digital port B is DDI0, digital port C is DDI1,
- * digital port D is DDI2
+ * On BXT the entire PHY channel corresponds to the port. That means
+ * the PLL is also now associated with the port rather than the pipe,
+ * and so the clock needs to be routed to the appropriate transcoder.
+ * Port A PLL is directly connected to transcoder EDP and port B/C
+ * PLLs can be routed to any transcoder A/B/C.
+ *
+ * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is
+ * digital port D (CHV) or port A (BXT).
*/
/*
- * Dual channel PHY (VLV/CHV)
+ * Dual channel PHY (VLV/CHV/BXT)
* -
* | CH0 | CH1 |
* | CMN/PLL/REF | CMN/PLL/REF |
@@ -784,7 +790,7 @@ enum skl_disp_power_wells {
* | DDI0 | DDI1 | DP/HDMI ports
* -
*
- * Single channel PHY (CHV)
+ * Single channel PHY (CHV/BXT)
* -
* | CH0 |
* | CMN/PLL/REF |
--
2.1.0
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Re: [Intel-gfx] [PATCH v2] drm/i915/chv: Implement WaDisableShadowRegForCpd
On Wednesday 15 April 2015 04:48 PM, Ville Syrjälä wrote:
On Wed, Apr 15, 2015 at 02:16:18PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
This WA is avoid problem between shadow vs wake FIFO unload
problem during CPD/RC6 transactions on CHV.
v2: Define individual bits GTFIFOCTL (Ville)
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_pm.c | 5 +
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9c97842..a642a58 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6206,6 +6206,8 @@ enum skl_disp_power_wells {
#define GTFIFOCTL0x120008
#defineGT_FIFO_FREE_ENTRIES_MASK 0x7f
#defineGT_FIFO_NUM_RESERVED_ENTRIES 20
+#define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 12)
+#define GT_FIFO_CTL_RC6_POLICY_STALL (1 11)
#define HSW_IDICR0x9008
#defineIDIHASHMSK(x) (((x) 0x3f) 16)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4dd8b41..2b86915 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6431,6 +6431,11 @@ static void cherryview_init_clock_gating(struct
drm_device *dev)
/* WaDisableSDEUnitClockGating:chv */
I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
+
+ /* WaDisableShadowRegForCpd */
+ I915_WRITE(GTFIFOCTL, I915_READ(GTFIFOCTL) |
+
GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
+ GT_FIFO_CTL_RC6_POLICY_STALL);
uncore early sanitize would still seem like the better place for this.
you mean intel_uncore_early_sanitize(). But func is called during early resume
right?
Since GTFIFOCTL will be saved and resorted by gunit. I think programming reg in
cherryview_init_clock_gating should be good enough?
}
static void g4x_init_clock_gating(struct drm_device *dev)
--
1.9.1
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[Intel-gfx] [PATCH 30.1/49] drm/i915/bxt: add display initialize/uninitialize sequence (PHY)
From: Vandana Kannan vandana.kan...@intel.com
Add PHY specific display initialization sequence as per BSpec.
Note that the PHY initialization/uninitialization are done
at their current place only for simplicity, in a future patch - when more
of the runtime PM features will be enabled - these will be moved to
power well#1 and modeset encoder enabling/disabling hooks respectively.
The call to uninitialize the PHY during system/runtime suspend will be
added later in this patchset.
v1: Added function definitions in header files
v2: Imre's review comments addressed
- Moved CDCLK related definitions to i915_reg.h
- Removed defintions for CDCLK frequency
- Split uninit_cdclk() by adding a phy_uninit function
- Calculate freq and decimal based on input frequency
- Program SSA precharge based on input frequency
- Use wait_for 1ms instead 200us udelay for DE PLL locking
- Removed initial value for divider, freq, decimal, ratio.
- Replaced polling loops with wait_for
- Parameterized latency optim setting
- Fix the parts where DE PLL has to be disabled.
- Call CDCLK selection from mode set
v3: (imre)
- add note about the plan to move the cdclk/phy init to a better place
- take rps.hw_lock around pcode access
- fix DDI PHY timeout value
- squash in Vandana's PORT_CL2CM_DW6_A BUN fix,
DDI PHY programming register defn, Do ddi_phy_init always,
- move PHY register macros next to the corresponding CHV/VLV macros
- move DE PLL register macros here from another patch since they are
used here first
- add BXT_ prefix to CDCLK flags
- s/COMMON_RESET/COMMON_RESET_DIS/ and clarify related code comments
- fix incorrect read value for the RMW of BXT_PHY_CTL_FAMILY_DDI
- fix using GT_DISPLAY_EDP_POWER_ON vs. GT_DISPLAY_DDI_POWER_ON
when powering on DDI ports
- fix incorrect port when setting BXT_PORT_TX_DW14_LN for DDI ports
- add missing masking when programming CDCLK_FREQ_DECIMAL
- add missing powering on for DDI-C port, rename OCL2_LDOFUSE_PWR_EN
to OCL2_LDOFUSE_PWR_DIS to reduce confusion
- add note about mismatch with bspec in the PORT_REF_DW6 fields
- factor out PHY init code to a new function, so we can call it for
PHY1 and PHY0, instead of open-coding the same
v4: (ville)
- split the CDCLK/PHY parts into two patches, update commit message
accordingly
- use the existing dpio_phy enum instead of adding a new one for the
same purpose
- flip the meaning of PHYs so that PHY_A is PHY1 and PHY_BC is PHY0 to
better match CHV
- s/BXT_PHY/_BXT_PHY/
- use _PIPE for _BXT_PHY instead of open-coding it
- drop _0_2_0_GTTMMADR suffix from BXT_P_CR_GT_DISP_PWRON
- define GT_DISPLAY_POWER_ON in a more standard way
- make a note that the CHV ConfigDB also disagrees about GRC_CODE field
definitions
- fix lane optimization refactoring fumble from v3
- add per PHY uninit functions to match the init counterparts
Signed-off-by: Vandana Kannan vandana.kan...@intel.com (v2)
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 96 ++
drivers/gpu/drm/i915/intel_ddi.c | 125 +++
drivers/gpu/drm/i915/intel_drv.h | 2 +
3 files changed, 223 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c79bf8d..1903e37 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1117,6 +1117,102 @@ enum skl_disp_power_wells {
#define DPIO_FRC_LATENCY_SHFIT 8
#define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
#define DPIO_UPAR_SHIFT 30
+
+/* BXT PHY registers */
+#define _BXT_PHY(phy, a, b)_PIPE((phy), (a), (b))
+
+#define BXT_P_CR_GT_DISP_PWRON 0x138090
+#define GT_DISPLAY_POWER_ON(phy) (1 (phy))
+
+#define _PHY_CTL_FAMILY_EDP0x64C80
+#define _PHY_CTL_FAMILY_DDI0x64C90
+#define COMMON_RESET_DIS (1 31)
+#define BXT_PHY_CTL_FAMILY(phy)_BXT_PHY((phy),
_PHY_CTL_FAMILY_DDI, \
+ _PHY_CTL_FAMILY_EDP)
+
+/* BXT PHY common lane registers */
+#define _PORT_CL1CM_DW0_A 0x162000
+#define _PORT_CL1CM_DW0_BC 0x6C000
+#define PHY_POWER_GOOD (1 16)
+#define BXT_PORT_CL1CM_DW0(phy)_BXT_PHY((phy),
_PORT_CL1CM_DW0_BC, \
+ _PORT_CL1CM_DW0_A)
+
+#define _PORT_CL1CM_DW9_A 0x162024
+#define _PORT_CL1CM_DW9_BC 0x6C024
+#define IREF0RC_OFFSET_SHIFT 8
+#define IREF0RC_OFFSET_MASK (0xFF IREF0RC_OFFSET_SHIFT)
+#define BXT_PORT_CL1CM_DW9(phy)_BXT_PHY((phy),
_PORT_CL1CM_DW9_BC, \
+ _PORT_CL1CM_DW9_A)
+
+#define _PORT_CL1CM_DW10_A 0x162028
+#define _PORT_CL1CM_DW10_BC0x6C028
+#define IREF1RC_OFFSET_SHIFT 8
+#define IREF1RC_OFFSET_MASK (0xFF IREF1RC_OFFSET_SHIFT)
[Intel-gfx] [PATCH 2/8] drm/i915: Add a way to disable planes without updating state
This is used by the next commit to disable all planes on a crtc
without caring what type it is.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 38 +---
drivers/gpu/drm/i915/intel_drv.h | 2 +-
drivers/gpu/drm/i915/intel_sprite.c | 16 +++
3 files changed, 44 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 75afa6ef22c7..84e21efe10cf 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2669,7 +2669,7 @@ static void i9xx_update_primary_plane(struct drm_crtc
*crtc,
u32 reg = DSPCNTR(plane);
int pixel_size;
- if (!intel_crtc-primary_enabled) {
+ if (!intel_crtc-primary_enabled || !fb) {
I915_WRITE(reg, 0);
if (INTEL_INFO(dev)-gen = 4)
I915_WRITE(DSPSURF(plane), 0);
@@ -2798,7 +2798,7 @@ static void ironlake_update_primary_plane(struct drm_crtc
*crtc,
u32 reg = DSPCNTR(plane);
int pixel_size;
- if (!intel_crtc-primary_enabled) {
+ if (!intel_crtc-primary_enabled || !fb) {
I915_WRITE(reg, 0);
I915_WRITE(DSPSURF(plane), 0);
POSTING_READ(reg);
@@ -2976,7 +2976,7 @@ static void skylake_update_primary_plane(struct drm_crtc
*crtc,
unsigned long surf_addr;
struct drm_plane *plane;
- if (!intel_crtc-primary_enabled) {
+ if (!intel_crtc-primary_enabled || !fb) {
I915_WRITE(PLANE_CTL(pipe, 0), 0);
I915_WRITE(PLANE_SURF(pipe, 0), 0);
POSTING_READ(PLANE_CTL(pipe, 0));
@@ -12978,6 +12978,20 @@ intel_commit_primary_plane(struct drm_plane *plane,
}
}
+static void
+intel_disable_primary_plane(struct drm_plane *plane,
+ struct drm_crtc *crtc,
+ bool force)
+{
+ struct drm_device *dev = plane-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+
+ if (!force)
+ to_intel_crtc(crtc)-primary_enabled = false;
+
+ dev_priv-display.update_primary_plane(crtc, NULL, 0, 0);
+}
+
static void intel_begin_crtc_commit(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc-dev;
@@ -13119,6 +13133,7 @@ static struct drm_plane
*intel_primary_plane_create(struct drm_device *dev,
primary-plane = pipe;
primary-check_plane = intel_check_primary_plane;
primary-commit_plane = intel_commit_primary_plane;
+ primary-disable_plane = intel_disable_primary_plane;
primary-ckey.flags = I915_SET_COLORKEY_NONE;
if (HAS_FBC(dev) INTEL_INFO(dev)-gen 4)
primary-plane = !pipe;
@@ -13224,6 +13239,22 @@ finish:
}
static void
+intel_disable_cursor_plane(struct drm_plane *plane,
+ struct drm_crtc *crtc,
+ bool force)
+{
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+
+ if (!force) {
+ plane-fb = NULL;
+ intel_crtc-cursor_bo = NULL;
+ intel_crtc-cursor_addr = 0;
+ }
+
+ intel_crtc_update_cursor(crtc, false);
+}
+
+static void
intel_commit_cursor_plane(struct drm_plane *plane,
struct intel_plane_state *state)
{
@@ -13282,6 +13313,7 @@ static struct drm_plane
*intel_cursor_plane_create(struct drm_device *dev,
state-scaler_id = -1;
cursor-check_plane = intel_check_cursor_plane;
cursor-commit_plane = intel_commit_cursor_plane;
+ cursor-disable_plane = intel_disable_cursor_plane;
drm_universal_plane_init(dev, cursor-base, 0,
intel_plane_funcs,
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index ec12948e76aa..27dbd8145610 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -597,7 +597,7 @@ struct intel_plane {
uint32_t x, uint32_t y,
uint32_t src_w, uint32_t src_h);
void (*disable_plane)(struct drm_plane *plane,
- struct drm_crtc *crtc);
+ struct drm_crtc *crtc, bool force);
int (*check_plane)(struct drm_plane *plane,
struct intel_plane_state *state);
void (*commit_plane)(struct drm_plane *plane,
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 612d8e0b3e02..631645420683 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -313,11 +313,11 @@ skl_update_plane(struct drm_plane *drm_plane, struct
drm_crtc *crtc,
}
static void
-skl_disable_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc)
+skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc, bool force)
[Intel-gfx] [PATCH 6/8] drm/i915: Rename intel_crtc_dpms_overlay.
To make it clear that it isn't called during crtc enable.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index d6f14765cf7d..47fbdb5c71cb 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4587,9 +4587,9 @@ static void intel_crtc_load_lut(struct drm_crtc *crtc)
hsw_enable_ips(intel_crtc);
}
-static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
+static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
{
- if (!enable intel_crtc-overlay) {
+ if (intel_crtc-overlay) {
struct drm_device *dev = intel_crtc-base.dev;
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -4718,7 +4718,6 @@ static void intel_crtc_enable_planes(struct drm_crtc
*crtc)
intel_enable_primary_hw_plane(crtc-primary, crtc);
intel_enable_sprite_planes(crtc);
intel_crtc_update_cursor(crtc, true);
- intel_crtc_dpms_overlay(intel_crtc, true);
intel_post_enable_primary(crtc);
}
@@ -4734,7 +4733,7 @@ static void intel_crtc_disable_planes(struct drm_crtc
*crtc)
intel_pre_disable_primary(crtc);
- intel_crtc_dpms_overlay(intel_crtc, false);
+ intel_crtc_dpms_overlay_disable(intel_crtc);
for_each_intel_plane(dev, intel_plane) {
if (intel_plane-pipe == pipe) {
struct drm_crtc *from = intel_plane-base.crtc;
--
2.1.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 7/8] drm/i915: Move toggling planes out of crtc enable/disable.
This makes disabling planes more explicit.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 4
drivers/gpu/drm/i915/intel_display.c | 36 ++--
drivers/gpu/drm/i915/intel_drv.h | 2 ++
3 files changed, 24 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 07a71c0ff775..2d63e15a8669 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3594,8 +3594,10 @@ static void hsw_trans_edp_pipe_A_crc_wa(struct
drm_device *dev)
intel_display_power_get(dev_priv,
POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
+ intel_crtc_disable_planes(crtc-base);
dev_priv-display.crtc_disable(crtc-base);
dev_priv-display.crtc_enable(crtc-base);
+ intel_crtc_enable_planes(crtc-base);
}
drm_modeset_unlock_all(dev);
}
@@ -3616,8 +3618,10 @@ static void hsw_undo_trans_edp_pipe_A_crc_wa(struct
drm_device *dev)
if (crtc-config-pch_pfit.force_thru) {
crtc-config-pch_pfit.force_thru = false;
+ intel_crtc_disable_planes(crtc-base);
dev_priv-display.crtc_disable(crtc-base);
dev_priv-display.crtc_enable(crtc-base);
+ intel_crtc_enable_planes(crtc-base);
intel_display_power_put(dev_priv,
POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 47fbdb5c71cb..cb677aff4245 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3123,8 +3123,8 @@ void intel_prepare_reset(struct drm_device *dev)
* g33 docs say we should at least disable all the planes.
*/
for_each_intel_crtc(dev, crtc) {
- if (crtc-active)
- dev_priv-display.crtc_disable(crtc-base);
+ intel_crtc_disable_planes(crtc-base);
+ dev_priv-display.crtc_disable(crtc-base);
}
}
@@ -4711,10 +4711,13 @@ intel_pre_disable_primary(struct drm_crtc *crtc)
hsw_disable_ips(intel_crtc);
}
-static void intel_crtc_enable_planes(struct drm_crtc *crtc)
+void intel_crtc_enable_planes(struct drm_crtc *crtc)
{
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ if (intel_crtc-active)
+ return;
+
intel_enable_primary_hw_plane(crtc-primary, crtc);
intel_enable_sprite_planes(crtc);
intel_crtc_update_cursor(crtc, true);
@@ -4722,13 +4725,16 @@ static void intel_crtc_enable_planes(struct drm_crtc
*crtc)
intel_post_enable_primary(crtc);
}
-static void intel_crtc_disable_planes(struct drm_crtc *crtc)
+void intel_crtc_disable_planes(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc-dev;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_plane *intel_plane;
int pipe = intel_crtc-pipe;
+ if (!intel_crtc-active)
+ return;
+
intel_crtc_wait_for_pending_flips(crtc);
intel_pre_disable_primary(crtc);
@@ -4820,8 +4826,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
if (HAS_PCH_CPT(dev))
cpt_verify_modeset(dev, intel_crtc-pipe);
-
- intel_crtc_enable_planes(crtc);
}
/* IPS only exists on ULT machines and is tied to pipe A. */
@@ -4943,7 +4947,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
/* If we change the relative order between pipe/planes enabling, we need
* to change the workaround. */
haswell_mode_set_planes_workaround(intel_crtc);
- intel_crtc_enable_planes(crtc);
}
static void ironlake_pfit_disable(struct intel_crtc *crtc)
@@ -4973,8 +4976,6 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
if (!intel_crtc-active)
return;
- intel_crtc_disable_planes(crtc);
-
for_each_encoder_on_crtc(dev, crtc, encoder)
encoder-disable(encoder);
@@ -5037,8 +5038,6 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
if (!intel_crtc-active)
return;
- intel_crtc_disable_planes(crtc);
-
for_each_encoder_on_crtc(dev, crtc, encoder) {
intel_opregion_notify_encoder(encoder, false);
encoder-disable(encoder);
@@ -5578,8 +5577,6 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
for_each_encoder_on_crtc(dev, crtc, encoder)
encoder-enable(encoder);
-
- intel_crtc_enable_planes(crtc);
}
static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
@@ -5636,8 +5633,6 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
for_each_encoder_on_crtc(dev, crtc, encoder)
[Intel-gfx] [PATCH 8/8] drm/i915: Move atomic crtc update checking to the check crtc function.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_atomic_plane.c | 18 +--
drivers/gpu/drm/i915/intel_display.c | 196 --
drivers/gpu/drm/i915/intel_sprite.c | 25 +---
3 files changed, 134 insertions(+), 105 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c
b/drivers/gpu/drm/i915/intel_atomic_plane.c
index a27ee8cbb627..4b639b54583d 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -123,8 +123,10 @@ static int intel_plane_atomic_check(struct drm_plane
*plane,
* anything driver-specific we need to test in that case, so
* just return success.
*/
- if (!crtc)
+ if (!crtc || !intel_crtc-active || !state-fb) {
+ intel_state-visible = 0;
return 0;
+ }
/*
* The original src/dest coordinates are stored in state-base, but
@@ -148,20 +150,6 @@ static int intel_plane_atomic_check(struct drm_plane
*plane,
intel_state-clip.y2 =
intel_crtc-active ? intel_crtc-config-pipe_src_h : 0;
- /*
-* Disabling a plane is always okay; we just need to update
-* fb tracking in a special way since cleanup_fb() won't
-* get called by the plane helpers.
-*/
- if (state-fb == NULL plane-state-fb != NULL) {
- /*
-* 'prepare' is never called when plane is being disabled, so
-* we need to handle frontbuffer tracking as a special case
-*/
- intel_crtc-atomic.disabled_planes |=
- (1 drm_plane_index(plane));
- }
-
if (state-fb intel_rotation_90_or_270(state-rotation)) {
if (!(state-fb-modifier[0] == I915_FORMAT_MOD_Y_TILED ||
state-fb-modifier[0] == I915_FORMAT_MOD_Yf_TILED)) {
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index cb677aff4245..4f27597486d8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -101,6 +101,8 @@ static void vlv_prepare_pll(struct intel_crtc *crtc,
const struct intel_crtc_state *pipe_config);
static void chv_prepare_pll(struct intel_crtc *crtc,
const struct intel_crtc_state *pipe_config);
+static int intel_atomic_check_crtc(struct drm_crtc *crtc,
+ struct drm_crtc_state *crtc_state);
static void intel_begin_crtc_commit(struct drm_crtc *crtc);
static void intel_finish_crtc_commit(struct drm_crtc *crtc);
static void skl_init_scalers(struct drm_device *dev, struct intel_crtc
*intel_crtc,
@@ -10646,6 +10648,7 @@ static struct drm_crtc_helper_funcs intel_helper_funcs
= {
.load_lut = intel_crtc_load_lut,
.atomic_begin = intel_begin_crtc_commit,
.atomic_flush = intel_finish_crtc_commit,
+ .atomic_check = intel_atomic_check_crtc,
};
/**
@@ -12773,6 +12776,9 @@ bool intel_wm_need_update(struct drm_plane *plane,
plane-state-rotation != state-rotation)
return true;
+ if (plane-type == DRM_PLANE_TYPE_CURSOR)
+ return plane-state-crtc_w != state-crtc_w;
+
return false;
}
@@ -12867,7 +12873,6 @@ intel_check_primary_plane(struct drm_plane *plane,
struct intel_plane_state *state)
{
struct drm_device *dev = plane-dev;
- struct drm_i915_private *dev_priv = dev-dev_private;
struct drm_crtc *crtc = state-base.crtc;
struct intel_crtc *intel_crtc;
struct drm_framebuffer *fb = state-base.fb;
@@ -12875,7 +12880,6 @@ intel_check_primary_plane(struct drm_plane *plane,
struct drm_rect *src = state-src;
const struct drm_rect *clip = state-clip;
bool can_position = false;
- int ret;
crtc = crtc ? crtc : plane-crtc;
intel_crtc = to_intel_crtc(crtc);
@@ -12883,58 +12887,12 @@ intel_check_primary_plane(struct drm_plane *plane,
if (INTEL_INFO(dev)-gen = 9)
can_position = true;
- ret = drm_plane_helper_check_update(plane, crtc, fb,
- src, dest, clip,
- DRM_PLANE_HELPER_NO_SCALING,
- DRM_PLANE_HELPER_NO_SCALING,
- can_position, true,
- state-visible);
- if (ret)
- return ret;
-
- if (intel_crtc-active) {
- struct intel_plane_state *old_state =
- to_intel_plane_state(plane-state);
-
- intel_crtc-atomic.wait_for_flips = true;
-
- /*
-* FBC does not work on some platforms for rotated
-* planes, so disable it when rotation is not 0 and
[Intel-gfx] [PATCH 5/8] drm/i915: Move intel_(pre_disable/post_enable)_primary to intel_display.c, and use it there.
They're the same code, so why not?
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 158 ++-
drivers/gpu/drm/i915/intel_drv.h | 2 -
drivers/gpu/drm/i915/intel_sprite.c | 68 ---
3 files changed, 102 insertions(+), 126 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 0a34ac731f0e..d6f14765cf7d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2215,14 +2215,6 @@ static void intel_enable_primary_hw_plane(struct
drm_plane *plane,
dev_priv-display.update_primary_plane(crtc, plane-fb,
crtc-x, crtc-y);
-
- /*
-* BDW signals flip done immediately if the plane
-* is disabled, even if the plane enable is already
-* armed to occur at the next vblank :(
-*/
- if (IS_BROADWELL(dev))
- intel_wait_for_vblank(dev, intel_crtc-pipe);
}
static bool need_vtd_wa(struct drm_device *dev)
@@ -4613,17 +4605,38 @@ static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc, bool enable)
*/
}
-static void intel_crtc_enable_planes(struct drm_crtc *crtc)
+/**
+ * intel_post_enable_primary - Perform operations after enabling primary plane
+ * @crtc: the CRTC whose primary plane was just enabled
+ *
+ * Performs potentially sleeping operations that must be done after the primary
+ * plane is enabled, such as updating FBC and IPS. Note that this may be
+ * called due to an explicit primary plane update, or due to an implicit
+ * re-enable that is caused when a sprite plane is updated to no longer
+ * completely hide the primary plane.
+ */
+static void
+intel_post_enable_primary(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
int pipe = intel_crtc-pipe;
- intel_enable_primary_hw_plane(crtc-primary, crtc);
- intel_enable_sprite_planes(crtc);
- intel_crtc_update_cursor(crtc, true);
- intel_crtc_dpms_overlay(intel_crtc, true);
+ /*
+* BDW signals flip done immediately if the plane
+* is disabled, even if the plane enable is already
+* armed to occur at the next vblank :(
+*/
+ if (IS_BROADWELL(dev))
+ intel_wait_for_vblank(dev, pipe);
+ /*
+* FIXME IPS should be fine as long as one plane is
+* enabled, but in practice it seems to have problems
+* when going from primary only to sprite only and vice
+* versa.
+*/
hsw_enable_ips(intel_crtc);
mutex_lock(dev-struct_mutex);
@@ -4631,27 +4644,95 @@ static void intel_crtc_enable_planes(struct drm_crtc
*crtc)
mutex_unlock(dev-struct_mutex);
/*
-* FIXME: Once we grow proper nuclear flip support out of this we need
-* to compute the mask of flip planes precisely. For the time being
-* consider this a flip from a NULL plane.
+* Gen2 reports pipe underruns whenever all planes are disabled.
+* So don't enable underrun reporting before at least some planes
+* are enabled.
+* FIXME: Need to fix the logic to work when we turn off all planes
+* but leave the pipe running.
*/
- intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
+ if (IS_GEN2(dev))
+ intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
+
+ /* Underruns don't raise interrupts, so check manually. */
+ if (HAS_GMCH_DISPLAY(dev))
+ i9xx_check_fifo_underruns(dev_priv);
}
-static void intel_crtc_disable_planes(struct drm_crtc *crtc)
+/**
+ * intel_pre_disable_primary - Perform operations before disabling primary
plane
+ * @crtc: the CRTC whose primary plane is to be disabled
+ *
+ * Performs potentially sleeping operations that must be done before the
+ * primary plane is disabled, such as updating FBC and IPS. Note that this may
+ * be called due to an explicit primary plane update, or due to an implicit
+ * disable that is caused when a sprite plane completely hides the primary
+ * plane.
+ */
+static void
+intel_pre_disable_primary(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- struct intel_plane *intel_plane;
int pipe = intel_crtc-pipe;
- intel_crtc_wait_for_pending_flips(crtc);
+ /*
+* Gen2 reports pipe underruns whenever all planes are disabled.
+* So diasble underrun reporting before all the planes get disabled.
+* FIXME: Need to fix the logic to work when we turn off all planes
+* but leave the pipe running.
+*/
[Intel-gfx] [PATCH 4/8] drm/i915: get rid of primary_enabled and use atomic state
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 50
drivers/gpu/drm/i915/intel_drv.h | 1 -
drivers/gpu/drm/i915/intel_fbc.c | 2 +-
3 files changed, 29 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 742829f3bb1d..0a34ac731f0e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2211,11 +2211,7 @@ static void intel_enable_primary_hw_plane(struct
drm_plane *plane,
/* If the pipe isn't enabled, we can't pump pixels and may hang */
assert_pipe_enabled(dev_priv, intel_crtc-pipe);
-
- if (intel_crtc-primary_enabled)
- return;
-
- intel_crtc-primary_enabled = true;
+ to_intel_plane_state(plane-state)-visible = true;
dev_priv-display.update_primary_plane(crtc, plane-fb,
crtc-x, crtc-y);
@@ -2636,6 +2632,8 @@ static void i9xx_update_primary_plane(struct drm_crtc
*crtc,
struct drm_device *dev = crtc-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct drm_plane *primary = crtc-primary;
+ bool visible = to_intel_plane_state(primary-state)-visible;
struct drm_i915_gem_object *obj;
int plane = intel_crtc-plane;
unsigned long linear_offset;
@@ -2643,7 +2641,7 @@ static void i9xx_update_primary_plane(struct drm_crtc
*crtc,
u32 reg = DSPCNTR(plane);
int pixel_size;
- if (!intel_crtc-primary_enabled || !fb) {
+ if (!visible || !fb) {
I915_WRITE(reg, 0);
if (INTEL_INFO(dev)-gen = 4)
I915_WRITE(DSPSURF(plane), 0);
@@ -2765,6 +2763,8 @@ static void ironlake_update_primary_plane(struct drm_crtc
*crtc,
struct drm_device *dev = crtc-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct drm_plane *primary = crtc-primary;
+ bool visible = to_intel_plane_state(primary-state)-visible;
struct drm_i915_gem_object *obj;
int plane = intel_crtc-plane;
unsigned long linear_offset;
@@ -2772,7 +2772,7 @@ static void ironlake_update_primary_plane(struct drm_crtc
*crtc,
u32 reg = DSPCNTR(plane);
int pixel_size;
- if (!intel_crtc-primary_enabled || !fb) {
+ if (!visible || !fb) {
I915_WRITE(reg, 0);
I915_WRITE(DSPSURF(plane), 0);
POSTING_READ(reg);
@@ -2941,6 +2941,8 @@ static void skylake_update_primary_plane(struct drm_crtc
*crtc,
struct drm_device *dev = crtc-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct drm_plane *plane = crtc-primary;
+ bool visible = to_intel_plane_state(plane-state)-visible;
struct drm_i915_gem_object *obj;
int pipe = intel_crtc-pipe;
u32 plane_ctl, stride_div, stride;
@@ -2948,9 +2950,8 @@ static void skylake_update_primary_plane(struct drm_crtc
*crtc,
unsigned int rotation;
int x_offset, y_offset;
unsigned long surf_addr;
- struct drm_plane *plane;
- if (!intel_crtc-primary_enabled || !fb) {
+ if (!visible || !fb) {
I915_WRITE(PLANE_CTL(pipe, 0), 0);
I915_WRITE(PLANE_SURF(pipe, 0), 0);
POSTING_READ(PLANE_CTL(pipe, 0));
@@ -3010,7 +3011,6 @@ static void skylake_update_primary_plane(struct drm_crtc
*crtc,
plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
- plane = crtc-primary;
rotation = plane-state-rotation;
switch (rotation) {
case BIT(DRM_ROTATE_90):
@@ -4654,7 +4654,6 @@ static void intel_crtc_disable_planes(struct drm_crtc
*crtc)
hsw_disable_ips(intel_crtc);
intel_crtc_dpms_overlay(intel_crtc, false);
- intel_crtc-primary_enabled = false;
for_each_intel_plane(dev, intel_plane) {
if (intel_plane-pipe == pipe) {
struct drm_crtc *from = intel_plane-base.crtc;
@@ -12536,6 +12535,9 @@ static int intel_crtc_set_config(struct drm_mode_set
*set)
} else if (config-fb_changed) {
struct intel_crtc *intel_crtc = to_intel_crtc(set-crtc);
struct drm_plane *primary = set-crtc-primary;
+ struct intel_plane_state *plane_state =
+ to_intel_plane_state(primary-state);
+ bool was_visible = plane_state-visible;
int vdisplay, hdisplay;
drm_crtc_get_hv_timing(set-mode, hdisplay, vdisplay);
@@ -12548,7 +12550,8 @@ static int intel_crtc_set_config(struct drm_mode_set
*set)
* We need to make sure the primary
[Intel-gfx] [PATCH 1/8] drm/i915: Remove implicitly disabling primary plane for now
Some of the flags that were used are still useful when transitioning
to atomic, so keep those around for now. This removes some of the
complications of crtc-primary_enabled, making it easier to remove.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_drv.h| 6 -
drivers/gpu/drm/i915/intel_sprite.c | 45 +
2 files changed, 1 insertion(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 082be7161203..ec12948e76aa 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -252,12 +252,6 @@ struct intel_plane_state {
bool visible;
/*
-* used only for sprite planes to determine when to implicitly
-* enable/disable the primary plane
-*/
- bool hides_primary;
-
- /*
* scaler_id
*= -1 : not using a scaler
*= 0 : using a scalers
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index e3d41c096dc6..612d8e0b3e02 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -165,17 +165,6 @@ void intel_pipe_update_end(struct intel_crtc *crtc, u32
start_vbl_count)
pipe_name(pipe), start_vbl_count, end_vbl_count);
}
-static void intel_update_primary_plane(struct intel_crtc *crtc)
-{
- struct drm_i915_private *dev_priv = crtc-base.dev-dev_private;
- int reg = DSPCNTR(crtc-plane);
-
- if (crtc-primary_enabled)
- I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE);
- else
- I915_WRITE(reg, I915_READ(reg) ~DISPLAY_PLANE_ENABLE);
-}
-
static void
skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc,
struct drm_framebuffer *fb,
@@ -479,8 +468,6 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc
*crtc,
linear_offset += src_h * fb-pitches[0] + src_w * pixel_size;
}
- intel_update_primary_plane(intel_crtc);
-
if (key-flags) {
I915_WRITE(SPKEYMINVAL(pipe, plane), key-min_value);
I915_WRITE(SPKEYMAXVAL(pipe, plane), key-max_value);
@@ -521,8 +508,6 @@ vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc
*crtc)
int pipe = intel_plane-pipe;
int plane = intel_plane-plane;
- intel_update_primary_plane(intel_crtc);
-
I915_WRITE(SPCNTR(pipe, plane), 0);
/* Activate double buffered register update */
@@ -626,8 +611,6 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc
*crtc,
}
}
- intel_update_primary_plane(intel_crtc);
-
if (key-flags) {
I915_WRITE(SPRKEYVAL(pipe), key-min_value);
I915_WRITE(SPRKEYMAX(pipe), key-max_value);
@@ -670,8 +653,6 @@ ivb_disable_plane(struct drm_plane *plane, struct drm_crtc
*crtc)
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
int pipe = intel_plane-pipe;
- intel_update_primary_plane(intel_crtc);
-
I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) ~SPRITE_ENABLE);
/* Can't leave the scaler enabled... */
if (intel_plane-can_scale)
@@ -766,8 +747,6 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc
*crtc,
linear_offset += src_h * fb-pitches[0] + src_w * pixel_size;
}
- intel_update_primary_plane(intel_crtc);
-
if (key-flags) {
I915_WRITE(DVSKEYVAL(pipe), key-min_value);
I915_WRITE(DVSKEYMAX(pipe), key-max_value);
@@ -805,8 +784,6 @@ ilk_disable_plane(struct drm_plane *plane, struct drm_crtc
*crtc)
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
int pipe = intel_plane-pipe;
- intel_update_primary_plane(intel_crtc);
-
I915_WRITE(DVSCNTR(pipe), 0);
/* Disable the scaler */
I915_WRITE(DVSSCALE(pipe), 0);
@@ -859,7 +836,7 @@ intel_post_enable_primary(struct drm_crtc *crtc)
* @crtc: the CRTC whose primary plane is to be disabled
*
* Performs potentially sleeping operations that must be done before the
- * primary plane is enabled, such as updating FBC and IPS. Note that this may
+ * primary plane is disabled, such as updating FBC and IPS. Note that this may
* be called due to an explicit primary plane update, or due to an implicit
* disable that is caused when a sprite plane completely hides the primary
* plane.
@@ -885,11 +862,6 @@ intel_pre_disable_primary(struct drm_crtc *crtc)
hsw_disable_ips(intel_crtc);
}
-static bool colorkey_enabled(struct intel_plane *intel_plane)
-{
- return intel_plane-ckey.flags != I915_SET_COLORKEY_NONE;
-}
-
static int
intel_check_sprite_plane(struct drm_plane *plane,
struct intel_plane_state *state)
@@ -1053,23 +1025,10 @@ finish:
* If the sprite is completely
[Intel-gfx] [PATCH 3/8] drm/i915: Use the disable callback for disabling planes.
This allows disabling all planes affecting a crtc without caring what type it
is.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 5 ++
drivers/gpu/drm/i915/intel_display.c | 91 ++--
2 files changed, 20 insertions(+), 76 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 89231aee31c0..61b756bdbaad 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -238,6 +238,11 @@ enum hpd_pin {
#define for_each_crtc(dev, crtc) \
list_for_each_entry(crtc, dev-mode_config.crtc_list, head)
+#define for_each_intel_plane(dev, intel_plane) \
+ list_for_each_entry(intel_plane,\
+ dev-mode_config.plane_list, \
+ base.head)
+
#define for_each_intel_crtc(dev, intel_crtc) \
list_for_each_entry(intel_crtc, dev-mode_config.crtc_list, base.head)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 84e21efe10cf..742829f3bb1d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2229,32 +2229,6 @@ static void intel_enable_primary_hw_plane(struct
drm_plane *plane,
intel_wait_for_vblank(dev, intel_crtc-pipe);
}
-/**
- * intel_disable_primary_hw_plane - disable the primary hardware plane
- * @plane: plane to be disabled
- * @crtc: crtc for the plane
- *
- * Disable @plane on @crtc, making sure that the pipe is running first.
- */
-static void intel_disable_primary_hw_plane(struct drm_plane *plane,
- struct drm_crtc *crtc)
-{
- struct drm_device *dev = plane-dev;
- struct drm_i915_private *dev_priv = dev-dev_private;
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-
- if (WARN_ON(!intel_crtc-active))
- return;
-
- if (!intel_crtc-primary_enabled)
- return;
-
- intel_crtc-primary_enabled = false;
-
- dev_priv-display.update_primary_plane(crtc, plane-fb,
- crtc-x, crtc-y);
-}
-
static bool need_vtd_wa(struct drm_device *dev)
{
#ifdef CONFIG_INTEL_IOMMU
@@ -4516,38 +4490,6 @@ static void intel_enable_sprite_planes(struct drm_crtc
*crtc)
}
}
-/*
- * Disable a plane internally without actually modifying the plane's state.
- * This will allow us to easily restore the plane later by just reprogramming
- * its state.
- */
-static void disable_plane_internal(struct drm_plane *plane)
-{
- struct intel_plane *intel_plane = to_intel_plane(plane);
- struct drm_plane_state *state =
- plane-funcs-atomic_duplicate_state(plane);
- struct intel_plane_state *intel_state = to_intel_plane_state(state);
-
- intel_state-visible = false;
- intel_plane-commit_plane(plane, intel_state);
-
- intel_plane_destroy_state(plane, state);
-}
-
-static void intel_disable_sprite_planes(struct drm_crtc *crtc)
-{
- struct drm_device *dev = crtc-dev;
- enum pipe pipe = to_intel_crtc(crtc)-pipe;
- struct drm_plane *plane;
- struct intel_plane *intel_plane;
-
- drm_for_each_legacy_plane(plane, dev-mode_config.plane_list) {
- intel_plane = to_intel_plane(plane);
- if (plane-fb intel_plane-pipe == pipe)
- disable_plane_internal(plane);
- }
-}
-
void hsw_enable_ips(struct intel_crtc *crtc)
{
struct drm_device *dev = crtc-base.dev;
@@ -4701,6 +4643,7 @@ static void intel_crtc_disable_planes(struct drm_crtc
*crtc)
struct drm_device *dev = crtc-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct intel_plane *intel_plane;
int pipe = intel_crtc-pipe;
intel_crtc_wait_for_pending_flips(crtc);
@@ -4711,9 +4654,15 @@ static void intel_crtc_disable_planes(struct drm_crtc
*crtc)
hsw_disable_ips(intel_crtc);
intel_crtc_dpms_overlay(intel_crtc, false);
- intel_crtc_update_cursor(crtc, false);
- intel_disable_sprite_planes(crtc);
- intel_disable_primary_hw_plane(crtc-primary, crtc);
+ intel_crtc-primary_enabled = false;
+ for_each_intel_plane(dev, intel_plane) {
+ if (intel_plane-pipe == pipe) {
+ struct drm_crtc *from = intel_plane-base.crtc;
+
+ intel_plane-disable_plane(intel_plane-base,
+ from ?: crtc, true);
+ }
+ }
/*
* FIXME: Once we grow proper nuclear flip support out of this we need
@@ -12957,24 +12906,14 @@ intel_commit_primary_plane(struct drm_plane *plane,
crtc-y = src-y1 16;
if (intel_crtc-active) {
- if (state-visible) {
+
Re: [Intel-gfx] [PATCH 30.1/49] drm/i915/bxt: add display initialize/uninitialize sequence (PHY)
On Wed, Apr 15, 2015 at 04:42:57PM +0300, Imre Deak wrote:
From: Vandana Kannan vandana.kan...@intel.com
Add PHY specific display initialization sequence as per BSpec.
Note that the PHY initialization/uninitialization are done
at their current place only for simplicity, in a future patch - when more
of the runtime PM features will be enabled - these will be moved to
power well#1 and modeset encoder enabling/disabling hooks respectively.
The call to uninitialize the PHY during system/runtime suspend will be
added later in this patchset.
v1: Added function definitions in header files
v2: Imre's review comments addressed
- Moved CDCLK related definitions to i915_reg.h
- Removed defintions for CDCLK frequency
- Split uninit_cdclk() by adding a phy_uninit function
- Calculate freq and decimal based on input frequency
- Program SSA precharge based on input frequency
- Use wait_for 1ms instead 200us udelay for DE PLL locking
- Removed initial value for divider, freq, decimal, ratio.
- Replaced polling loops with wait_for
- Parameterized latency optim setting
- Fix the parts where DE PLL has to be disabled.
- Call CDCLK selection from mode set
v3: (imre)
- add note about the plan to move the cdclk/phy init to a better place
- take rps.hw_lock around pcode access
- fix DDI PHY timeout value
- squash in Vandana's PORT_CL2CM_DW6_A BUN fix,
DDI PHY programming register defn, Do ddi_phy_init always,
- move PHY register macros next to the corresponding CHV/VLV macros
- move DE PLL register macros here from another patch since they are
used here first
- add BXT_ prefix to CDCLK flags
- s/COMMON_RESET/COMMON_RESET_DIS/ and clarify related code comments
- fix incorrect read value for the RMW of BXT_PHY_CTL_FAMILY_DDI
- fix using GT_DISPLAY_EDP_POWER_ON vs. GT_DISPLAY_DDI_POWER_ON
when powering on DDI ports
- fix incorrect port when setting BXT_PORT_TX_DW14_LN for DDI ports
- add missing masking when programming CDCLK_FREQ_DECIMAL
- add missing powering on for DDI-C port, rename OCL2_LDOFUSE_PWR_EN
to OCL2_LDOFUSE_PWR_DIS to reduce confusion
- add note about mismatch with bspec in the PORT_REF_DW6 fields
- factor out PHY init code to a new function, so we can call it for
PHY1 and PHY0, instead of open-coding the same
v4: (ville)
- split the CDCLK/PHY parts into two patches, update commit message
accordingly
- use the existing dpio_phy enum instead of adding a new one for the
same purpose
- flip the meaning of PHYs so that PHY_A is PHY1 and PHY_BC is PHY0 to
better match CHV
- s/BXT_PHY/_BXT_PHY/
- use _PIPE for _BXT_PHY instead of open-coding it
- drop _0_2_0_GTTMMADR suffix from BXT_P_CR_GT_DISP_PWRON
- define GT_DISPLAY_POWER_ON in a more standard way
- make a note that the CHV ConfigDB also disagrees about GRC_CODE field
definitions
- fix lane optimization refactoring fumble from v3
- add per PHY uninit functions to match the init counterparts
Signed-off-by: Vandana Kannan vandana.kan...@intel.com (v2)
Signed-off-by: Imre Deak imre.d...@intel.com
Looking OK. Stuffing some/all of it into a power well and/or into the
port enable/disable code may be the right thing to do later, but this
should at least get it up and running for now.
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 96 ++
drivers/gpu/drm/i915/intel_ddi.c | 125
+++
drivers/gpu/drm/i915/intel_drv.h | 2 +
3 files changed, 223 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c79bf8d..1903e37 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1117,6 +1117,102 @@ enum skl_disp_power_wells {
#define DPIO_FRC_LATENCY_SHFIT 8
#define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
#define DPIO_UPAR_SHIFT30
+
+/* BXT PHY registers */
+#define _BXT_PHY(phy, a, b) _PIPE((phy), (a), (b))
+
+#define BXT_P_CR_GT_DISP_PWRON 0x138090
+#define GT_DISPLAY_POWER_ON(phy) (1 (phy))
+
+#define _PHY_CTL_FAMILY_EDP 0x64C80
+#define _PHY_CTL_FAMILY_DDI 0x64C90
+#define COMMON_RESET_DIS (1 31)
+#define BXT_PHY_CTL_FAMILY(phy) _BXT_PHY((phy),
_PHY_CTL_FAMILY_DDI, \
+ _PHY_CTL_FAMILY_EDP)
+
+/* BXT PHY common lane registers */
+#define _PORT_CL1CM_DW0_A0x162000
+#define _PORT_CL1CM_DW0_BC 0x6C000
+#define PHY_POWER_GOOD (1 16)
+#define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy),
_PORT_CL1CM_DW0_BC, \
+ _PORT_CL1CM_DW0_A)
+
+#define _PORT_CL1CM_DW9_A0x162024
+#define _PORT_CL1CM_DW9_BC 0x6C024
+#define IREF0RC_OFFSET_SHIFT 8
+#define IREF0RC_OFFSET_MASK(0xFF
Re: [Intel-gfx] [PATCH 04/13] drm/i915: Add EDID read in intel_dp_check_link_status() for Link CTS 4.2.2.1
On 4/14/2015 9:53 AM, Paulo Zanoni wrote:
2015-04-13 11:53 GMT-03:00 Todd Previte tprev...@gmail.com:
Adds in an EDID read after the DPCD read to accommodate test 4.2.2.1 in the
Displayport Link CTS Core 1.2 rev1.1. This test requires an EDID read for
all HPD plug events. To reduce the amount of code, this EDID read is also
used for Link CTS tests 4.2.2.3, 4.2.2.4, 4.2.2.5 and 4.2.2.6. Actual
support for these tests is implemented in later patches in this series.
V2:
- Fixed compilation error introduced during rework
Signed-off-by: Todd Previte tprev...@gmail.com
---
drivers/gpu/drm/i915/intel_dp.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 23184b0..75df3e2 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3890,6 +3890,9 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
{
struct drm_device *dev = intel_dp_to_dev(intel_dp);
struct intel_encoder *intel_encoder = dp_to_dig_port(intel_dp)-base;
+ struct drm_connector *connector = intel_dp-attached_connector-base;
+ struct i2c_adapter *adapter = intel_dp-aux.ddc;
+ struct edid *edid_read = NULL;
u8 sink_irq_vector;
u8 link_status[DP_LINK_STATUS_SIZE];
@@ -3906,6 +3909,14 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
return;
}
+ /* Displayport Link CTS Core 1.2 rev1.1 EDID testing
+* 4.2.2.1 - EDID read required for all HPD events
+ */
+edid_read = drm_get_edid(connector, adapter);
+if (!edid_read) {
+DRM_DEBUG_DRIVER(Invalid EDID detected\n);
+}
+
We already briefly discussed this patch in private, so I'm going to
summarize the discussion and also add some more points here.
Frist, the actual detailed review: the indentation here is using
spaces and we're leaking the EDID. This will cause rebases to a few of
the next patches.
Back to the hight level architecture: your initial versions of the
series contained just 1 extra EDID read, and it was contained inside
the compliance testing function. Then the versions submitted a few
days ago had 2 extra EDID reads, then after some discussion you
reduced to 1 extra EDID read (the one on this patch). I previously
asked But what about the automatic EDID read we do when we get a
hotplug? Can't we just rely on it?. I got some answers to the
question, but I was not really convinced.
Yesterday I was arguing that this extra EDID read is going to add a
small delay to every hotplug event we get, so my initial suggestion
was to organize the compliance testing in a way that would require the
user space program to call the GetResources() IOCTL to force the EDID
when needed. Your argument was that then the DP compliance testing
procedure would be testing our app for compliance, not the Kernel.
But today I decided to finally do some debugging regarding this, and I
was able to confirm that we do follow the DP requirements: we do have
an automatic EDID read done by the Kernel whenever we do a hotplug:
i915_hotplug_work_func() calls intel_dp_detect(), which ends calling
drm_get_edid() at some point. This function also does other stuff that
is required by the compliance testing, such as the DPCD reads.
Now there's a problem with using i915_hotplug_work_func(), which could
the reason why you rejected it: it only happens after
intel_dp_hpd_pulse(), which means that we only really do the EDID read
after intel_dp_handle_test_request().
I consider i915_hotplug_work_func() a fundamental part of our DP
framework, and the DP compliance testing seems to be just ignoring its
existence. So my idea for a solution here would be to make
intel_dp_handle_test_request() run on its own delayed work function.
It would wait for both i915_digport_work_func() and
i915_hotplug_work_func() to finish, and only then it would do the
normal processing. With this, we would be able to avoid the edid read
on this patch, we would maybe be able to avoid at least part of patch
2, we would maybe be able to completely avoid patch 7, and then on
patch 8 we would start touching intel_dp_get_edid() instead.
I know this is sort of a fundamental change that is being requested a
little late in the review process, and it can be frustrating, but this
aspect of the code only recently changed (I was fine with the EDID
reads just in the compliance testing function), and since the DP
compliance code is quite complex, it took me a while to realize
everything that's going on and what is the purpose of each piece. I
also think that, since this idea will allow the compliance testing to
take into consideration the work done by i915_hotplug_work_func(),
compliance testing will better reflect the behavior that is actually
done by the Kernel when DP devices are plugged/unplugged. And I did
ask about those new EDID reads as soon as I started reviewing the
patch that introduced them.
[Intel-gfx] [PATCH] drm/i915: Simplify i915_gem_obj_is_pinned() test for set-tiling
Since the removal of the user pin_ioctl, the only means for pinning an
object is either through binding to the scanout or during execbuf
reservation. As the later prevents a call to set-tiling, we need only
check if the obj is pinned into the display plane to see if we need
reject the set-tiling ioctl.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_gem_tiling.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c
b/drivers/gpu/drm/i915/i915_gem_tiling.c
index e1fa1d9aec6c..fd1b89a4d02d 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -338,7 +338,7 @@ i915_gem_set_tiling(struct drm_device *dev, void *data,
}
mutex_lock(dev-struct_mutex);
- if (i915_gem_obj_is_pinned(obj) || obj-framebuffer_references) {
+ if (obj-pin_display || obj-framebuffer_references) {
ret = -EBUSY;
goto err;
}
--
2.1.4
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Re: [Intel-gfx] [PATCH] drm: Kernel Crash in drm_unlock
Hi Daniel,
I am having a look at this now, as have some time.
So, to sum up what I think you want.
1. Re-base and apply the patches (so that the known holes are closed in
the Nouveau driver).
2. Add DRIVER_KMS_LEGACY_CONTEXT to include/drm/drmP.h
3. Add DRIVER_KMS_LEGACY_CONTEXT to .driver_features in file
drivers/gpu/drm/nouveau/nouveau_drm.h.
4. Change all the hw_lock IOCTL functions to have:
+ if (!drm_core_check_feature(dev, DRIVER_KMS_LEGACY_CONTEXT))
+ return -EINVAL;
+
5. Add an igt test, that would induce the crash on platforms that are
not patched and have DRIVER_KMS_LEGACY_CONTEXT enabled?
Is this about right?
Thanks,
Peter.
On Tue, 2015-03-31 at 16:00 +0200, Daniel Vetter wrote:
On Tue, Mar 31, 2015 at 01:34:25PM +, Antoine, Peter wrote:
This was found by the security guys using an ioctl fuzzer.
12 lines of code from a new unprivileged user and the kernel goes bang.
The other crash was just found using code inspection, but it is the same
basic issue.
Either the hw_lock was not created or the was deleted and the pointer is
dereferenced.
For the escalation, there is not proof of concept, but it is a bad
comparison as the bits are stripped off for other checks.
I'll be re-spinning the patches when I get notified that I am on the no
footer list.
In that case I think an igt testcase to make this go boom would be great.
Testbinary prefix for drm core is drm_ (there's some already).
Meanwhile I did dig out the history for this and it's not pretty. See
commit c21eb21cb50d58e7cbdcb8b9e7ff68b85cfa5095
Author: Dave Airlie airl...@redhat.com
Date: Fri Sep 20 08:32:59 2013 +1000
Revert drm: mark context support as a legacy subsystem
Imo the correct way to fix this isn't to try to fix the code (it's
hopeless, making it go boom with fuzzing is just the tip of the iceberg),
but instead to disable it. But we may not break nouvea, so needs a bit
more elaborate:
1. Add DRIVER_KMS_LEGACY_CONTEXT driver flag and add it to nouveau.
2. Modify all the DRIVER_MODESET checks from my patch
(7c510133d93dd6f15ca040733ba7b2891ed61fd1) to still let the ioctls through
when DRIVER_KMS_LEGACY_CONTEXT is set.
Can you please sign up for this plus the minimal igt?
Thanks, Daniel
Peter.
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
Vetter
Sent: Tuesday, March 31, 2015 2:26 PM
To: Antoine, Peter
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm: Kernel Crash in drm_unlock
On Tue, Mar 31, 2015 at 09:09:33AM +0100, Peter Antoine wrote:
This patch fixes a possible kernel crash when drm_unlock
(DRM_IOCTL_UNLOCK) is called by a application that has not had a lock
created by it. This crash can be caused by any application from all users.
Issue: GMINL-7446
Change-Id: I901ff713be53c5ec1c9eaf7ee0ff4314a659af05
Signed-off-by: Peter Antoine peter.anto...@intel.com
Can you really blow this up at runtime with modern modeset drivers like
i915? Counts for all three patches ...
---
drivers/gpu/drm/drm_lock.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/drm_lock.c b/drivers/gpu/drm/drm_lock.c
index f645268..80253a7 100644
--- a/drivers/gpu/drm/drm_lock.c
+++ b/drivers/gpu/drm/drm_lock.c
@@ -156,6 +156,14 @@ int drm_unlock(struct drm_device *dev, void
*data, struct drm_file *file_priv)
Also please rebase to latest upstream when submitting patches to the public
(the function is now called drm_legacy_unlock).
return -EINVAL;
}
+ if (!master-lock.hw_lock) {
+ DRM_ERROR(
+ Device has been unregistered. Hard exit. Process %d\n,
+ task_pid_nr(current));
+ send_sig(SIGTERM, current, 0);
+ return -EINTR;
+ }
+
if (drm_lock_free(master-lock, lock-context)) {
/* FIXME: Should really bail out here. */
}
--
1.9.1
-
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Registered No. 1134945 (England)
Registered Office: Pipers Way, Swindon SN3 1RJ VAT No: 860 2173 47
This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
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recipient, please contact the sender and delete all copies.
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--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
-
Intel Corporation (UK)
[Intel-gfx] [PATCH 05/10] drm: Add supporting structure for Displayport Link CTS test 4.2.2.6
Displayport compliance test 4.2.2.6 requires that a source device be capable of
detecting a corrupt EDID. The test specification states that the sink device
sets up the EDID with an invalid checksum. To do this, the sink sets up an
invalid EDID header, expecting the source device to generate the checksum and
compare it to the value stored in the last byte of the block data.
Unfortunately, the DRM EDID reading and parsing functions are actually too good
in this case; the header is fixed before the checksum is computed and thus the
code never sees the invalid checksum. This results in a failure to pass the
compliance test.
To correct this issue, a checksum is generated when the EDID header is detected
as corrupted. If the checksum is invalid, it sets the header_corrupt flag and
logs the errors. In the case of a more seriously damaged header (fixup score
less than the threshold) the code does not generate the checksum but does set
the header_corrupt flag.
V2:
- Removed the static bool global
- Added a bool to the drm_connector struct to reaplce the static one for
holding the status of raw edid header corruption detection
- Modified the function signature of the is_valid function to take an
additional parameter to store the corruption detected value
- Fixed the other callers of the above is_valid function
V3:
- Updated the commit message to be more clear about what and why this
patch does what it does.
- Added comment in code to clarify the operations there
- Removed compliance variable and check_link_status update; those
have been moved to a later patch
- Removed variable assignment from the bottom of the test handler
V4:
- Removed i915 tag from subject line as the patch is not i915-specific
V5:
- Moved code causing a compilation error to this patch where the variable
is actually declared
- Maintained blank lines / spacing so as to not contaminate the patch
V6:
- Removed extra debug messages
- Added documentation to for the added parameter on drm_edid_block_valid
- Fixed more whitespace issues in check_link_status
- Added a clear of the header_corrupt flag to the end of the test handler
in intel_dp.c
- Changed the usage of the new function prototype in several places to use
NULL where it is not needed by compliance testing
Signed-off-by: Todd Previte tprev...@gmail.com
Cc: dri-de...@lists.freedesktop.org
---
drivers/gpu/drm/drm_edid.c | 30 ++
drivers/gpu/drm/drm_edid_load.c | 7 +--
drivers/gpu/drm/i915/intel_dp.c | 6 +-
include/drm/drm_crtc.h | 8 +++-
4 files changed, 43 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 53bc7a6..1ed18f5 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1041,13 +1041,15 @@ static bool drm_edid_is_zero(const u8 *in_edid, int
length)
* @raw_edid: pointer to raw EDID block
* @block: type of block to validate (0 for base, extension otherwise)
* @print_bad_edid: if true, dump bad EDID blocks to the console
+ * @header_corrupt: if true, the header or checksum is invalid
*
* Validate a base or extension EDID block and optionally dump bad blocks to
* the console.
*
* Return: True if the block is valid, false otherwise.
*/
-bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid)
+bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
+ bool *header_corrupt)
{
u8 csum;
struct edid *edid = (struct edid *)raw_edid;
@@ -1062,9 +1064,25 @@ bool drm_edid_block_valid(u8 *raw_edid, int block, bool
print_bad_edid)
int score = drm_edid_header_is_valid(raw_edid);
if (score == 8) ;
else if (score = edid_fixup) {
+ /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
+* In order to properly generate the invalid checksum
+* required for this test, it must be generated using
+* the raw EDID data. Otherwise, the fix-up code here
+* will correct the problem, the checksum is correct
+* and the test fails
+*/
+ csum = drm_edid_block_checksum(raw_edid);
+ if (csum) {
+ if (header_corrupt)
+ *header_corrupt = 1;
+ }
DRM_DEBUG(Fixing EDID header, your hardware may be
failing\n);
memcpy(raw_edid, edid_header, sizeof(edid_header));
} else {
+ if (header_corrupt) {
+ DRM_DEBUG_DRIVER(Invalid EDID header\n);
+ *header_corrupt = 1;
+ }
goto bad;
}
}
@@ -1129,7 +1147,7 @@ bool drm_edid_is_valid(struct edid
[Intel-gfx] [PATCH 03/10] drm/i915: Add EDID read in intel_dp_check_link_status() for Link CTS 4.2.2.1
Adds in an EDID read after the DPCD read to accommodate test 4.2.2.1 in the
Displayport Link CTS Core 1.2 rev1.1. This test requires an EDID read for
all HPD plug events. To reduce the amount of code, this EDID read is also
used for Link CTS tests 4.2.2.3, 4.2.2.4, 4.2.2.5 and 4.2.2.6. Actual
support for these tests is implemented in later patches in this series.
V2:
- Fixed compilation error introduced during rework
V3:
- Plugged a memory leak where the EDID data wasn't being freed
after allocation in this function
V4:
- Fixed whitespace problems
- Cleaned up formatting
Signed-off-by: Todd Previte tprev...@gmail.com
---
drivers/gpu/drm/i915/intel_dp.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 1352c00..c112359 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4114,11 +4114,24 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
{
struct drm_device *dev = intel_dp_to_dev(intel_dp);
struct intel_encoder *intel_encoder = dp_to_dig_port(intel_dp)-base;
+ struct drm_connector *connector = intel_dp-attached_connector-base;
+ struct i2c_adapter *adapter = intel_dp-aux.ddc;
+ struct edid *edid_read = NULL;
u8 sink_irq_vector;
u8 link_status[DP_LINK_STATUS_SIZE];
WARN_ON(!drm_modeset_is_locked(dev-mode_config.connection_mutex));
+ /* Displayport Link CTS Core 1.2 rev1.1 EDID testing
+* 4.2.2.1 - EDID read required for all HPD events
+*/
+ edid_read = drm_get_edid(connector, adapter);
+ if (!edid_read) {
+ DRM_DEBUG_DRIVER(Invalid EDID detected\n);
+ } else {
+ kfree(edid_read);
+ }
+
/* Try to read the source of the interrupt */
if (intel_dp-dpcd[DP_DPCD_REV] = 0x11
intel_dp_get_sink_irq(intel_dp, sink_irq_vector)) {
--
1.9.1
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[Intel-gfx] [PATCH V6] Displayport compliance testing V6
This is the 6th iteration of the Displayport compliance testing patch set for performing compliance testing operations of the i915 driver. High level changes are listed below, with the specifics for each patch listed in the commit messages. Kernel: Changes for V4: - Removed the code for link configuration in debugfs. It wasn’t used in this patch set so there was no need to add 500+ lines of code to the kernel. It may be reintroduced in a future patch if it becomes necessary to support link configuration testing for Displayport compliance - Merged working changes in to the kernel code to keep the patches smaller and as discrete, testable units. This included moving variables around between patches such that their declaration and use appears in the same patch. One variable was removed entirely as it was no longer necessary. - Changed the debugfs interface for test control. Previously test control was handled by a single file that contained tags and values that were parsed and used by both the user app and the kernel. This required a lot of parsing code on both sides of the equation. That has been eliminated in favor of 3 separate, single value files for test type, test data and testing active. This reduces the overhead of polling on test_active in the user app as well as eliminating the need to parse a single monolithic file every time it checks the flag (currently 1ms intervals). The net result is a more responsible app and a lot less code on both sides. Changes for V5: - Removed a duplicate EDID read from the EDID auto test function - Added a failsafe check in the I2C DEFER check to make sure a misbhaving device wouldn’t cause an infinite loop - Shuffled around some variable declarations and assignments to put them in the correct patches and places - Fixed a commit message that was no longer accurate - Removed the main stream disable code from check_link_status as this doesn’t play nice with a number of systems. A replacement for this will be done in the user app when necessary. Changes for V6: - Addressed all the review feedback from V5 and made the necessary changes - Added a new flag for detecting EDID header corruption for compliance testing - Cleaned up checkpatch.pl issues - Fixed whitespace/formatting problems - Made substantial adjustments to the hpd_pulse code to make sure it works for all permutations of SST/MST and short/long pulses - Reintegrated patches 2 and 3 into a single patch again - Removed several instances of duplicate code - Propagate the long_hpd flag into check_link_status to only perform the EDID read for a long pulse (hot plug event) Userspace app: The userspace app can be found here: https://github.com/tprevite/intel-gpu-tools/tree/dp_compliance The user app has the following requirements: - Must be executed as root from the command line - No other display managers can be running. Must be in console mode. - Only the test device should be connected to one of the external Displayport ports. No other displays should be connected via Displayport. eDP displays are ignored by the compliance code so they should operate normally. Previous versions of the user app disabled all displays on the DUT. That is no longer necessary in order to execute Displayport compliance testing. The app can be run remotely via an SSH login or directly on the DUT at the preference of the operator. Aside from starting and stopping the app itself, no direct interaction is necessary at this time on the part of the test operator to perform compliance testing. Some of the tests will still pass if the user app isn't running. The primary purpose of the user space application is to handle the heavy lifting of the mode sets required to set the specific display resolutions for the tests. Changes for V2: - Removed unnecessary memcpy()s and replaced with assignments - Updated the README - Moved the menu code around and reworded it to be more accurate - Added a “NONE” display mode to disable the main link Changes for V3: - Rewrote the input handling code - Cleaned up some minor issues / extraneous tags - Fixed a minor bug in the setup of the failsafe video mode - Removed the delay on startup and updated the output messages accordingly The Github version is the most up to date, with several patches having been applied recently which are encapsulated in the high level notes for V3 above. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 06/10] drm/i915: Update intel_dp_hpd_pulse() for non-MST operation
Update the hot plug function to handle the SST case. Instead of placing
the SST case within the long/short pulse block, it is now handled after
determining that MST mode is not in use. This way, the topology management
layer can handle any MST-related operations while SST operations are still
correctly handled afterwards.
This patch also corrects the problem of SST mode only being handled in the
case of a short (0.5ms - 1.0ms) HPD pulse. For compliance testing purposes
both short and long pulses are used by the different tests, thus both cases
need to be addressed for SST.
This patch replaces [PATCH 10/10] drm/i915: Fix intel_dp_hot_plug() in the
previous compliance testing patch sequence. Review feedback on that patch
indicated that updating intel_dp_hot_plug() was not the correct place for
the test handler.
For the SST case, the main stream is disabled for long HPD pulses as this
generally indicates either a connect/disconnect event or link failure. For
a number of case in compliance testing, the source is required to disable
the main link upon detection of a long HPD.
V2:
- N/A
V3:
- Place the SST mode link status check into the mst_fail case
- Remove obsolete comment regarding SST mode operation
- Removed an erroneous line of code that snuck in during rebasing
V4:
- Added a disable of the main stream (DP transport) for the long pulse case
for SST to support compliance testing
V5:
- Reworked SST handling to support tests 4.2.2.7 and 4.2.2.8
V6:
- Reformatted a comment
V7:
- Moved a comment again that was inadvertently moved
- Updated the code to properly handle all permutations of MST/SST and
short/long pulse.
- Adds a new 'connected' flag that prevents unnecessary operations when
the link is disconnected.
- Added a function to encapsulate detection of the HPD pin status in
in order to determine connected status
- Reformatted the if-statements in the function so the braces are
consistent for those with single statements after the if-statement
Signed-off-by: Todd Previte tprev...@gmail.com
---
drivers/gpu/drm/i915/intel_dp.c | 55 +---
drivers/gpu/drm/i915/intel_drv.h | 1 +
2 files changed, 35 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 9181483..f70d20e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4745,6 +4745,7 @@ intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port, bool long_hpd)
struct drm_i915_private *dev_priv = dev-dev_private;
enum intel_display_power_domain power_domain;
enum irqreturn ret = IRQ_NONE;
+ bool connected = false;
if (intel_dig_port-base.type != INTEL_OUTPUT_EDP)
intel_dig_port-base.type = INTEL_OUTPUT_DISPLAYPORT;
@@ -4768,19 +4769,15 @@ intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port, bool long_hpd)
power_domain = intel_display_port_power_domain(intel_encoder);
intel_display_power_get(dev_priv, power_domain);
+ connected = intel_dp_digital_port_connected(intel_dp);
+
if (long_hpd) {
- if (HAS_PCH_SPLIT(dev)) {
- if (!ibx_digital_port_connected(dev_priv,
intel_dig_port))
- goto mst_fail;
- } else {
- if (g4x_digital_port_connected(dev, intel_dig_port) !=
1)
- goto mst_fail;
- }
+ if (!connected)
+ goto mst_fail;
- if (!intel_dp_get_dpcd(intel_dp)) {
+ if (!intel_dp_get_dpcd(intel_dp))
goto mst_fail;
- }
intel_dp_probe_oui(intel_dp);
@@ -4788,20 +4785,9 @@ intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port, bool long_hpd)
goto mst_fail;
} else {
- if (intel_dp-is_mst) {
+ if (intel_dp-is_mst)
if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
goto mst_fail;
- }
-
- if (!intel_dp-is_mst) {
- /*
-* we'll check the link status via the normal hot plug
path later -
-* but for short hpds we should check it now
-*/
- drm_modeset_lock(dev-mode_config.connection_mutex,
NULL);
- intel_dp_check_link_status(intel_dp);
- drm_modeset_unlock(dev-mode_config.connection_mutex);
- }
}
ret = IRQ_HANDLED;
@@ -4815,6 +4801,15 @@ mst_fail:
drm_dp_mst_topology_mgr_set_mst(intel_dp-mst_mgr,
intel_dp-is_mst);
}
put_power:
+ /* SST mode - handle short/long pulses here */
+ if (!intel_dp-is_mst) {
+
+ drm_modeset_lock(dev-mode_config.connection_mutex, NULL);
+
[Intel-gfx] [PATCH 07/10] drm/i915: Support EDID compliance tests with the intel_dp_autotest_edid() function
Updates the EDID compliance test function to perform the EDID read as
required by the tests. This read needs to take place in the kernel for
reasons of speed and efficiency. The results of the EDID read operations
are handed off to userspace so that the userspace app can set the display
mode appropriately for the test response.
The compliance_test_active flag now appears at the end of the individual
test handling functions. This is so that the kernel-side operations can
be completed without the risk of interruption from the userspace app
that is polling on that flag.
V2:
- Addressed mailing list feedback
- Removed excess debug messages
- Removed extraneous comments
- Fixed formatting issues (line length 80)
- Updated the debug message in compute_edid_checksum to output hex values
instead of decimal
V3:
- Addressed more list feedback
- Added the test_active flag to the autotest function
- Removed test_active flag from handler
- Added failsafe check on the compliance test active flag
at the end of the test handler
- Fixed checkpatch.pl issues
V4:
- Removed the checksum computation function and its use as it has been
rendered superfluous by changes to the core DRM EDID functions
- Updated to use the raw header corruption detection mechanism
- Moved the declaration of the test_data variable here
V5:
- Update test active flag variable name to match the change in the
first patch of the series.
- Relocated the test active flag declaration and initialization
to this patch
V6:
- Updated to use the new flag for raw EDID header corruption
- Removed the extra EDID read from the autotest function
- Added the edid_checksum variable to struct intel_dp so that the
autotest function can write it to the sink device
- Moved the update to the hpd_pulse function to another patch
- Removed extraneous constants
V7:
- Fixed erroneous placement of the checksum assignment. In some cases
such as when the EDID read fails and is NULL, this causes a NULL ptr
dereference in the kernel. Bad news. Fixed now.
V8:
- Updated to support the kfree() on the EDID data added previously
Signed-off-by: Todd Previte tprev...@gmail.com
---
drivers/gpu/drm/i915/intel_dp.c | 47 +++-
drivers/gpu/drm/i915/intel_drv.h | 4
2 files changed, 50 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f70d20e..033b0ef 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -41,6 +41,12 @@
#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
+/* Compliance test status bits */
+#define INTEL_DP_RESOLUTION_SHIFT_MASK 4
+#define INTEL_DP_RESOLUTION_PREFERRED (1 INTEL_DP_RESOLUTION_SHIFT_MASK)
+#define INTEL_DP_RESOLUTION_STANDARD (2 INTEL_DP_RESOLUTION_SHIFT_MASK)
+#define INTEL_DP_RESOLUTION_FAILSAFE (3 INTEL_DP_RESOLUTION_SHIFT_MASK)
+
struct dp_link_dpll {
int link_bw;
struct dpll dpll;
@@ -3994,6 +4000,35 @@ static uint8_t intel_dp_autotest_video_pattern(struct
intel_dp *intel_dp)
static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
{
uint8_t test_result = DP_TEST_NAK;
+ uint32_t ret = 0;
+
+ if (intel_dp-compliance_edid_invalid ||
+ intel_dp-aux.i2c_defer_count 6) {
+ /* Check for NACKs/DEFERs, use failsafe if detected
+* (DP CTS 1.2 Core Rev 1.1, 4.2.2.4, 4.2.2.5)
+*/
+ if (intel_dp-aux.i2c_nack_count 0 ||
+ intel_dp-aux.i2c_defer_count 0)
+ DRM_DEBUG_KMS(EDID read had %d NACKs, %d DEFERs\n,
+ intel_dp-aux.i2c_nack_count,
+ intel_dp-aux.i2c_defer_count);
+ intel_dp-compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
+ } else {
+ ret = drm_dp_dpcd_write(intel_dp-aux,
+ DP_TEST_EDID_CHECKSUM,
+ intel_dp-compliance_edid_checksum, 1);
+ if (ret = 0)
+ DRM_DEBUG_DRIVER(Failed to write EDID checksum\n);
+ else
+ DRM_DEBUG_DRIVER(EDID checksum written to sink\n);
+
+ test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
+ intel_dp-compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
+ }
+
+ /* Set test active flag here so userspace doesn't interrupt things */
+ intel_dp-compliance_test_active = 1;
+
return test_result;
}
@@ -4010,7 +4045,10 @@ static void intel_dp_handle_test_request(struct intel_dp
*intel_dp)
uint8_t rxdata = 0;
int status = 0;
+ intel_dp-compliance_test_active = 0;
intel_dp-compliance_test_type = 0;
+ intel_dp-compliance_test_data = 0;
+
intel_dp-aux.i2c_nack_count = 0;
intel_dp-aux.i2c_defer_count = 0;
@@ -4137,11 +4175,18 @@
[Intel-gfx] [PATCH 08/10] drm: Fix for DP CTS test 4.2.2.5 - I2C DEFER handling
For test 4.2.2.5 to pass per the Link CTS Core 1.2 rev1.1 spec, the source
device must attempt at least 7 times to read the EDID when it receives an
I2C defer. The normal DRM code makes only 7 retries, regardless of whether
or not the response is a native defer or an I2C defer. Test 4.2.2.5 fails
since there are native defers interspersed with the I2C defers which
results in less than 7 EDID read attempts.
The solution is to add the numer of defers to the retry counter when an I2C
DEFER is returned such that another read attempt will be made. This situation
should normally only occur in compliance testing, however, as a worse case
real-world scenario, it would result in 13 attempts ( 6 native defers, 7 I2C
defers) for a single transaction to complete. The net result is a slightly
slower response to an EDID read that shouldn't significantly impact overall
performance.
V2:
- Added a check on the number of I2C Defers to limit the number
of times that the retries variable will be decremented. This
is to address review feedback regarding possible infinite loops
from misbehaving sink devices.
V3:
- Fixed the limit value to 7 instead of 8 to get the correct retry
count.
- Combined the increment of the defer count into the if-statement
V4:
- Removed i915 tag from subject as the patch is not i915-specific
V5:
- Updated the for-loop to add the number of i2c defers to the retry
counter such that the correct number of retry attempts will be
made
Signed-off-by: Todd Previte tprev...@gmail.com
Cc: dri-de...@lists.freedesktop.org
---
drivers/gpu/drm/drm_dp_helper.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 71dcbc6..7f0356e 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -432,7 +432,7 @@ static u32 drm_dp_i2c_functionality(struct i2c_adapter
*adapter)
*/
static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg
*msg)
{
- unsigned int retry;
+ unsigned int retry, defer_i2c;
int ret;
/*
@@ -440,7 +440,7 @@ static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct
drm_dp_aux_msg *msg)
* is required to retry at least seven times upon receiving AUX_DEFER
* before giving up the AUX transaction.
*/
- for (retry = 0; retry 7; retry++) {
+ for (retry = 0, defer_i2c = 0; retry (7 + defer_i2c); retry++) {
mutex_lock(aux-hw_mutex);
ret = aux-transfer(aux, msg);
mutex_unlock(aux-hw_mutex);
@@ -499,7 +499,13 @@ static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux,
struct drm_dp_aux_msg *msg)
case DP_AUX_I2C_REPLY_DEFER:
DRM_DEBUG_KMS(I2C defer\n);
+ /* DP Compliance Test 4.2.2.5 Requirement:
+* Must have at least 7 retries for I2C defers on the
+* transaction to pass this test
+*/
aux-i2c_defer_count++;
+ if (defer_i2c 7)
+ defer_i2c++;
usleep_range(400, 500);
continue;
--
1.9.1
___
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[Intel-gfx] [PATCH 09/10] drm/i915: Add debugfs test control files for Displayport compliance testing
This patch adds 3 debugfs files for handling Displayport compliance testing
and supercedes the previous patches that implemented debugfs support for
compliance testing. Those patches were:
- [PATCH 04/17] drm/i915: Add debugfs functions for Displayport
compliance testing
- [PATCH 08/17] drm/i915: Add new debugfs file for Displayport
compliance test control
- [PATCH 09/17] drm/i915: Add debugfs write and test param parsing
functions for DP test control
This new patch simplifies the debugfs implementation by places a single
test control value into an individual file. Each file is readable by
the usersapce application and the test_active file is writable to
indicate to the kernel when userspace has completed its portion of the
test sequence.
Replacing the previous files simplifies operation and speeds response
time for the user app, as it is required to poll on the test_active file
in order to determine when it needs to begin its operations.
V2:
- Updated the test active variable name to match the change in
the initial patch of the series
V3:
- Added a fix in the test_active_write function to prevent a NULL pointer
dereference if the encoder on the connector is invalid
Signed-off-by: Todd Previte tprev...@gmail.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 209
1 file changed, 209 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 2394924..c33d390 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3937,6 +3937,212 @@ static const struct file_operations
i915_display_crc_ctl_fops = {
.write = display_crc_ctl_write
};
+static ssize_t i915_displayport_test_active_write(struct file *file,
+ const char __user *ubuf,
+ size_t len, loff_t *offp)
+{
+ char *input_buffer;
+ int status = 0;
+ struct seq_file *m;
+ struct drm_device *dev;
+ struct drm_connector *connector;
+ struct list_head *connector_list;
+ struct intel_dp *intel_dp;
+ int val = 0;
+
+ m = file-private_data;
+ if (!m) {
+ status = -ENODEV;
+ return status;
+ }
+ dev = m-private;
+
+ if (!dev) {
+ status = -ENODEV;
+ return status;
+ }
+ connector_list = dev-mode_config.connector_list;
+
+ if (len == 0)
+ return 0;
+
+ input_buffer = kmalloc(len + 1, GFP_KERNEL);
+ if (!input_buffer)
+ return -ENOMEM;
+
+ if (copy_from_user(input_buffer, ubuf, len)) {
+ status = -EFAULT;
+ goto out;
+ }
+
+ input_buffer[len] = '\0';
+ DRM_DEBUG_DRIVER(Copied %d bytes from user\n, (unsigned int)len);
+
+ list_for_each_entry(connector, connector_list, head) {
+
+ if (connector-connector_type !=
+ DRM_MODE_CONNECTOR_DisplayPort)
+ continue;
+
+ if (connector-connector_type ==
+ DRM_MODE_CONNECTOR_DisplayPort
+ connector-status == connector_status_connected
+ connector-encoder != NULL) {
+ intel_dp = enc_to_intel_dp(connector-encoder);
+ status = kstrtoint(input_buffer, 10, val);
+ if (status 0)
+ goto out;
+ DRM_DEBUG_DRIVER(Got %d for test active\n, val);
+ /* To prevent erroneous activation of the compliance
+* testing code, only accept an actual value of 1 here
+*/
+ if (val == 1)
+ intel_dp-compliance_test_active = 1;
+ else
+ intel_dp-compliance_test_active = 0;
+ }
+ }
+out:
+ kfree(input_buffer);
+ if (status 0)
+ return status;
+
+ *offp += len;
+ return len;
+}
+
+static int i915_displayport_test_active_show(struct seq_file *m, void *data)
+{
+ struct drm_device *dev = m-private;
+ struct drm_connector *connector;
+ struct list_head *connector_list = dev-mode_config.connector_list;
+ struct intel_dp *intel_dp;
+
+ if (!dev)
+ return -ENODEV;
+
+ list_for_each_entry(connector, connector_list, head) {
+
+ if (connector-connector_type !=
+ DRM_MODE_CONNECTOR_DisplayPort)
+ continue;
+
+ if (connector-status == connector_status_connected
+ connector-encoder != NULL) {
+ intel_dp = enc_to_intel_dp(connector-encoder);
+ if (intel_dp-compliance_test_active)
+
[Intel-gfx] [PATCH 02/10] drm/i915: Update intel_dp_check_link_status() for Displayport compliance testing
This patch is a combination of changes that does the following:
- Ignore disconnected Displayport connectors in check_link_status
- Move the DPCD read further up in intel_dp_check_link_status()
- Adds a new function that checks the HW HPD pin status
- Replace the check for SW connected status with the new function
Adds a check at the top to verify that the device is connected. This is
necessary for DP compliance testing to ensure that test requests are captured
and acknowledged. If a test request is present during a connected-disconnected
transition, the test code will attempt to execute even though the device is
disconnected, resulting in a faied test.
This patch is actually both a bug fix and a component of compliance testing.
Because HPD events are received both on connect and disconnect actions, it's
vital that we don't try and train the link when we're transitioning from
connected-disconnected. That results in errors and warning in the logs from
failed AUX transactions and can trigger the WARN for the check of !base.crtc.
By making the check at the beginning to see if the connection is truly active,
those problems are avoided and testing / link training will only be attempted
when there is a valid Displayport connection.
Move the DPCD read to the top and check for an interrupt from the sink to catch
Displayport automated testing requests necessary to support Displayport
compliance testing. The checks for active connectors and link status are moved
below the check for the interrupt.
The main reason for doing this is to make sure that a test request isn't missed.
Checking for the status of the encoder/crtc isn't necessary for some test cases
(AUX channel tests are one example) and without moving the check for the
interrupt, these tests may not execute if one of those checks fails.
Additionally, if reading the DPCD fails, regardless of whether or not testing is
happening, there's no way to train the link since configurations and status
can't be read, nor can link training parameters be written.
V1:
- This is the second part of the single-patch split previously
mentioned.
V2:
- Remerge the two split patches into one and update the commit message
accordingly.
- Replace the SW connected status check with a HW HPD pin status check
- Adds a new function that examines the status of the HPD pin to
determine if a sink device is connected
V3:
- Removed duplicate code from the hpd_pulse - check_link_status path
Signed-off-by: Todd Previte tprev...@gmail.com
---
drivers/gpu/drm/i915/intel_dp.c | 32 +---
1 file changed, 13 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 263eff3..1352c00 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4119,6 +4119,19 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
WARN_ON(!drm_modeset_is_locked(dev-mode_config.connection_mutex));
+ /* Try to read the source of the interrupt */
+ if (intel_dp-dpcd[DP_DPCD_REV] = 0x11
+ intel_dp_get_sink_irq(intel_dp, sink_irq_vector)) {
+ /* Clear interrupt source */
+ drm_dp_dpcd_writeb(intel_dp-aux,
+ DP_DEVICE_SERVICE_IRQ_VECTOR,
+ sink_irq_vector);
+ if (sink_irq_vector DP_AUTOMATED_TEST_REQUEST)
+ intel_dp_handle_test_request(intel_dp);
+ if (sink_irq_vector (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
+ DRM_DEBUG_DRIVER(CP or sink specific irq unhandled\n);
+ }
+
if (!intel_encoder-connectors_active)
return;
@@ -4133,25 +4146,6 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
return;
}
- /* Now read the DPCD to see if it's actually running */
- if (!intel_dp_get_dpcd(intel_dp)) {
- return;
- }
-
- /* Try to read the source of the interrupt */
- if (intel_dp-dpcd[DP_DPCD_REV] = 0x11
- intel_dp_get_sink_irq(intel_dp, sink_irq_vector)) {
- /* Clear interrupt source */
- drm_dp_dpcd_writeb(intel_dp-aux,
- DP_DEVICE_SERVICE_IRQ_VECTOR,
- sink_irq_vector);
-
- if (sink_irq_vector DP_AUTOMATED_TEST_REQUEST)
- intel_dp_handle_test_request(intel_dp);
- if (sink_irq_vector (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
- DRM_DEBUG_DRIVER(CP or sink specific irq unhandled\n);
- }
-
if (!drm_dp_channel_eq_ok(link_status, intel_dp-lane_count)) {
DRM_DEBUG_KMS(%s: channel EQ not ok, retraining\n,
intel_encoder-base.name);
--
1.9.1
___
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[Intel-gfx] [PATCH 04/10] drm/i915: Add a delay in Displayport AUX transactions for compliance testing
The Displayport Link Layer Compliance Testing Specification 1.2 rev 1.1
specifies that repeated AUX transactions after a failure (no response /
invalid response) must have a minimum delay of 400us before the resend can
occur. Tests 4.2.1.1 and 4.2.1.2 are two tests that require this specifically.
Also, the check for DP_AUX_CH_CTL_TIME_OUT_ERROR has been moved out into a
separate case. This case just continues with the next iteration of the loop
as the HW has already waited the required amount of time.
V2:
- Changed udelay() to usleep_range()
V3:
- Removed extraneous check for timeout
- Updated comment to reflect this change
V4:
- Reformatted a comment
V5:
- Added separate check for HW timeout on AUX transactions. A message
is logged upon detection of this case.
V6:
- Add continue statement to HW timeout detect case
- Remove the log message indicating a timeout has been
detected (review feedback)
V7:
- Updated the commit message to remove verbage about the HW timeout
case that is no longer valid.
Signed-off-by: Todd Previte tprev...@gmail.com
Reviewed-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c112359..dae5c9a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -874,9 +874,18 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
DP_AUX_CH_CTL_TIME_OUT_ERROR |
DP_AUX_CH_CTL_RECEIVE_ERROR);
- if (status (DP_AUX_CH_CTL_TIME_OUT_ERROR |
- DP_AUX_CH_CTL_RECEIVE_ERROR))
+ if (status DP_AUX_CH_CTL_TIME_OUT_ERROR)
continue;
+
+ /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 4.2.1.2
+* 400us delay required for errors and timeouts
+* Timeout errors from the HW already meet this
+* requirement so skip to next iteration
+*/
+ if (status DP_AUX_CH_CTL_RECEIVE_ERROR) {
+ usleep_range(400, 500);
+ continue;
+ }
if (status DP_AUX_CH_CTL_DONE)
break;
}
--
1.9.1
___
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[Intel-gfx] [PATCH 10/10] drm: Fix the 'native defer' message in drm_dp_i2c_do_msg()
The debug message is missing a newline at the end and it makes the logs hard to read when a device defers a lot. Simple 2-character fix adds the newline at the end. Signed-off-by: Todd Previte tprev...@gmail.com Cc: dri-de...@lists.freedesktop.org Reviewed-by: Paulo Zanoni paulo.r.zan...@intel.com Reviewed-by: Alex Deucher alexander.deuc...@amd.com --- drivers/gpu/drm/drm_dp_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index 7f0356e..80a02a4 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -466,7 +466,7 @@ static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) return -EREMOTEIO; case DP_AUX_NATIVE_REPLY_DEFER: - DRM_DEBUG_KMS(native defer); + DRM_DEBUG_KMS(native defer\n); /* * We could check for I2C bit rate capabilities and if * available adjust this interval. We could also be -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 01/10] drm/i915: Add automated testing support for Displayport compliance testing
Add the skeleton framework for supporting automation for Displayport compliance
testing. This patch adds the necessary framework for the source device to
appropriately respond to test automation requests from a sink device.
V2:
- Addressed previous mailing list feedback
- Fixed compilation issue (struct members declared in a later patch)
- Updated debug messages to be more accurate
- Added status checks for the DPCD read/write calls
- Removed excess comments and debug messages
- Fixed debug message compilation warnings
- Fixed compilation issue with missing variables
- Updated link training autotest to ACK
V3:
- Fixed the checks on the DPCD return code to be = 0
rather than != 0
- Removed extraneous assignment of a NAK return code in the
DPCD read failure case
- Changed the return in the DPCD read failure case to a goto
to the exit point where the status code is written to the sink
- Removed FAUX test case since it's deprecated now
- Removed the compliance flag assignment in handle_test_request
V4:
- Moved declaration of type_type here
- Removed declaration of test_data (moved to a later patch)
- Added reset to 0 for compliance test variables
V5:
- Moved test_active variable declaration and initialization out of
this patch and into the patch where it's used
- Changed variable name compliance_testing_active to
compliance_test_active to unify the naming convention
- Added initialization for compliance_test_type variable
Signed-off-by: Todd Previte tprev...@gmail.com
Reviewed-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 75 +---
drivers/gpu/drm/i915/intel_drv.h | 3 ++
2 files changed, 74 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 14cdd00..263eff3 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3970,11 +3970,78 @@ intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8
*sink_irq_vector)
return true;
}
-static void
-intel_dp_handle_test_request(struct intel_dp *intel_dp)
+static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
+{
+ uint8_t test_result = DP_TEST_ACK;
+ return test_result;
+}
+
+static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
+{
+ uint8_t test_result = DP_TEST_NAK;
+ return test_result;
+}
+
+static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
+{
+ uint8_t test_result = DP_TEST_NAK;
+ return test_result;
+}
+
+static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
+{
+ uint8_t test_result = DP_TEST_NAK;
+ return test_result;
+}
+
+static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
{
- /* NAK by default */
- drm_dp_dpcd_writeb(intel_dp-aux, DP_TEST_RESPONSE, DP_TEST_NAK);
+ uint8_t response = DP_TEST_NAK;
+ uint8_t rxdata = 0;
+ int status = 0;
+
+ intel_dp-compliance_test_type = 0;
+ intel_dp-aux.i2c_nack_count = 0;
+ intel_dp-aux.i2c_defer_count = 0;
+
+ status = drm_dp_dpcd_read(intel_dp-aux, DP_TEST_REQUEST, rxdata, 1);
+ if (status = 0) {
+ DRM_DEBUG_KMS(Could not read test request from sink\n);
+ goto update_status;
+ }
+
+ switch (rxdata) {
+ case DP_TEST_LINK_TRAINING:
+ DRM_DEBUG_KMS(LINK_TRAINING test requested\n);
+ intel_dp-compliance_test_type = DP_TEST_LINK_TRAINING;
+ response = intel_dp_autotest_link_training(intel_dp);
+ break;
+ case DP_TEST_LINK_VIDEO_PATTERN:
+ DRM_DEBUG_KMS(TEST_PATTERN test requested\n);
+ intel_dp-compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
+ response = intel_dp_autotest_video_pattern(intel_dp);
+ break;
+ case DP_TEST_LINK_EDID_READ:
+ DRM_DEBUG_KMS(EDID test requested\n);
+ intel_dp-compliance_test_type = DP_TEST_LINK_EDID_READ;
+ response = intel_dp_autotest_edid(intel_dp);
+ break;
+ case DP_TEST_LINK_PHY_TEST_PATTERN:
+ DRM_DEBUG_KMS(PHY_PATTERN test requested\n);
+ intel_dp-compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
+ response = intel_dp_autotest_phy_pattern(intel_dp);
+ break;
+ default:
+ DRM_DEBUG_KMS(Invalid test request '%02x'\n, rxdata);
+ break;
+ }
+
+update_status:
+ status = drm_dp_dpcd_write(intel_dp-aux,
+ DP_TEST_RESPONSE,
+ response, 1);
+ if (status = 0)
+ DRM_DEBUG_KMS(Could not write test response to sink\n);
}
static int
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 6a2ee0c..a4675fa 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++
[Intel-gfx] [PATCH] drm/i915: Update meaning of debugfs object's pin_flag
Since the pin_ioctl is defunct, we only care about whether an object is
pinned into the display for debug purposes.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index ed48387762b2..61785c92e1b9 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -94,7 +94,7 @@ static int i915_capabilities(struct seq_file *m, void *data)
static const char *get_pin_flag(struct drm_i915_gem_object *obj)
{
- if (i915_gem_obj_is_pinned(obj))
+ if (obj-pin_display)
return p;
else
return ;
--
2.1.4
___
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[Intel-gfx] [PATCH v4] drm/i915: Workaround to avoid lite restore with HEAD==TAIL
WaIdleLiteRestore is an execlists-only workaround, and requires the driver
to ensure that any context always has HEAD!=TAIL when attempting lite
restore.
Add two extra MI_NOOP instructions at the end of each request, but keep
the requests tail pointing before the MI_NOOPs. We may not need to
executed them, and this is why request-tail is sampled before adding
these extra instructions.
If we submit a context to the ELSP which has previously been submitted,
move the tail pointer past the MI_NOOPs. This ensures HEAD!=TAIL.
v2: Move overallocation to gen8_emit_request, and added note about
sampling request-tail in commit message (Chris).
v3: Remove redundant request-tail assignment in __i915_add_request, in
lrc mode this is already set in execlists_context_queue.
Do not add wa implementation details inside gem (Chris).
v4: Apply the wa whenever the req has been resubmitted and update
comment (Chris).
Cc: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Thomas Daniel thomas.dan...@intel.com
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_gem.c | 3 ++-
drivers/gpu/drm/i915/intel_lrc.c | 35 ++-
2 files changed, 36 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 3d5a5a8..980e17c 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2400,10 +2400,11 @@ int __i915_add_request(struct intel_engine_cs *ring,
ret = ring-add_request(ring);
if (ret)
return ret;
+
+ request-tail = intel_ring_get_tail(ringbuf);
}
request-head = request_start;
- request-tail = intel_ring_get_tail(ringbuf);
/* Whilst this request exists, batch_obj will be on the
* active_list, and so will hold the active reference. Only when this
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index f4a5ef9..50ed977 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -427,6 +427,26 @@ static void execlists_context_unqueue(struct
intel_engine_cs *ring)
}
}
+ if (IS_GEN8(ring-dev) || IS_GEN9(ring-dev)) {
+ /*
+* WaIdleLiteRestore: make sure we never cause a lite
+* restore with HEAD==TAIL
+*/
+ if (req0 req0-elsp_submitted) {
+ /*
+* Apply the wa NOOPS to prevent ring:HEAD == req:TAIL
+* as we resubmit the request. See gen8_emit_request()
+* for where we prepare the padding after the end of the
+* request.
+*/
+ struct intel_ringbuffer *ringbuf;
+
+ ringbuf = req0-ctx-engine[ring-id].ringbuf;
+ req0-tail += 8;
+ req0-tail = ringbuf-size - 1;
+ }
+ }
+
WARN_ON(req1 req1-elsp_submitted);
execlists_submit_contexts(ring, req0-ctx, req0-tail,
@@ -1289,7 +1309,12 @@ static int gen8_emit_request(struct intel_ringbuffer
*ringbuf,
u32 cmd;
int ret;
- ret = intel_logical_ring_begin(ringbuf, request-ctx, 6);
+ /*
+* Reserve space for 2 NOOPs at the end of each request to be
+* used as a workaround for not being allowed to do lite
+* restore with HEAD==TAIL (WaIdleLiteRestore).
+*/
+ ret = intel_logical_ring_begin(ringbuf, request-ctx, 8);
if (ret)
return ret;
@@ -1307,6 +1332,14 @@ static int gen8_emit_request(struct intel_ringbuffer
*ringbuf,
intel_logical_ring_emit(ringbuf, MI_NOOP);
intel_logical_ring_advance_and_submit(ringbuf, request-ctx, request);
+ /*
+* Here we add two extra NOOPs as padding to avoid
+* lite restore of a context with HEAD==TAIL.
+*/
+ intel_logical_ring_emit(ringbuf, MI_NOOP);
+ intel_logical_ring_emit(ringbuf, MI_NOOP);
+ intel_logical_ring_advance(ringbuf);
+
return 0;
}
--
2.1.1
___
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[Intel-gfx] [PATCH v3] drm/i915: Workaround to avoid lite restore with HEAD==TAIL
WaIdleLiteRestore is an execlists-only workaround, and requires the driver
to ensure that any context always has HEAD!=TAIL when attempting lite
restore.
Add two extra MI_NOOP instructions at the end of each request, but keep
the requests tail pointing before the MI_NOOPs. We may not need to
executed them, and this is why request-tail must be sampled before adding
these extra instructions.
If we submit a context to the ELSP which has previously been submitted,
move the tail pointer past the MI_NOOPs. This ensures HEAD!=TAIL.
v2: Move overallocation to gen8_emit_request, and added note about
sampling request-tail in commit message (Chris).
v3: Remove redundant request-tail assignment in __i915_add_request, in
lrc mode this is already set in execlists_context_queue.
Do not add wa implementation details inside gem (Chris).
Cc: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Thomas Daniel thomas.dan...@intel.com
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_gem.c | 3 ++-
drivers/gpu/drm/i915/intel_lrc.c | 35 ++-
2 files changed, 36 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 3d5a5a8..980e17c 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2400,10 +2400,11 @@ int __i915_add_request(struct intel_engine_cs *ring,
ret = ring-add_request(ring);
if (ret)
return ret;
+
+ request-tail = intel_ring_get_tail(ringbuf);
}
request-head = request_start;
- request-tail = intel_ring_get_tail(ringbuf);
/* Whilst this request exists, batch_obj will be on the
* active_list, and so will hold the active reference. Only when this
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index f4a5ef9..0296350 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -427,6 +427,26 @@ static void execlists_context_unqueue(struct
intel_engine_cs *ring)
}
}
+ if (IS_GEN8(ring-dev) || IS_GEN9(ring-dev)) {
+ /*
+* WaIdleLiteRestore: make sure we never cause a lite
+* restore with HEAD==TAIL
+*/
+ if (req0 req0-elsp_submitted == 1) {
+ /*
+* Consume the buffer NOOPs to ensure HEAD != TAIL when
+* submitting. elsp_submitted can only be 1 after
+* reset, in which case we don't need the workaround as
+* a lite restore will not occur.
+*/
+ struct intel_ringbuffer *ringbuf;
+
+ ringbuf = req0-ctx-engine[ring-id].ringbuf;
+ req0-tail += 8;
+ req0-tail = ringbuf-size - 1;
+ }
+ }
+
WARN_ON(req1 req1-elsp_submitted);
execlists_submit_contexts(ring, req0-ctx, req0-tail,
@@ -1289,7 +1309,12 @@ static int gen8_emit_request(struct intel_ringbuffer
*ringbuf,
u32 cmd;
int ret;
- ret = intel_logical_ring_begin(ringbuf, request-ctx, 6);
+ /*
+* Reserve space for 2 NOOPs at the end of each request to be
+* used as a workaround for not being allowed to do lite
+* restore with HEAD==TAIL (WaIdleLiteRestore).
+*/
+ ret = intel_logical_ring_begin(ringbuf, request-ctx, 8);
if (ret)
return ret;
@@ -1307,6 +1332,14 @@ static int gen8_emit_request(struct intel_ringbuffer
*ringbuf,
intel_logical_ring_emit(ringbuf, MI_NOOP);
intel_logical_ring_advance_and_submit(ringbuf, request-ctx, request);
+ /*
+* Here we add two extra NOOPs as padding to avoid
+* lite restore of a context with HEAD==TAIL.
+*/
+ intel_logical_ring_emit(ringbuf, MI_NOOP);
+ intel_logical_ring_emit(ringbuf, MI_NOOP);
+ intel_logical_ring_advance(ringbuf);
+
return 0;
}
--
2.1.1
___
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Re: [Intel-gfx] [PATCH v3] drm/i915: Workaround to avoid lite restore with HEAD==TAIL
On Wed, Apr 15, 2015 at 05:17:13PM +0100, Michel Thierry wrote:
WaIdleLiteRestore is an execlists-only workaround, and requires the driver
to ensure that any context always has HEAD!=TAIL when attempting lite
restore.
Add two extra MI_NOOP instructions at the end of each request, but keep
the requests tail pointing before the MI_NOOPs. We may not need to
executed them, and this is why request-tail must be sampled before adding
these extra instructions.
If we submit a context to the ELSP which has previously been submitted,
move the tail pointer past the MI_NOOPs. This ensures HEAD!=TAIL.
v2: Move overallocation to gen8_emit_request, and added note about
sampling request-tail in commit message (Chris).
v3: Remove redundant request-tail assignment in __i915_add_request, in
lrc mode this is already set in execlists_context_queue.
Do not add wa implementation details inside gem (Chris).
Cc: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Thomas Daniel thomas.dan...@intel.com
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_gem.c | 3 ++-
drivers/gpu/drm/i915/intel_lrc.c | 35 ++-
2 files changed, 36 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 3d5a5a8..980e17c 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2400,10 +2400,11 @@ int __i915_add_request(struct intel_engine_cs *ring,
ret = ring-add_request(ring);
if (ret)
return ret;
+
+ request-tail = intel_ring_get_tail(ringbuf);
}
request-head = request_start;
- request-tail = intel_ring_get_tail(ringbuf);
/* Whilst this request exists, batch_obj will be on the
* active_list, and so will hold the active reference. Only when this
diff --git a/drivers/gpu/drm/i915/intel_lrc.c
b/drivers/gpu/drm/i915/intel_lrc.c
index f4a5ef9..0296350 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -427,6 +427,26 @@ static void execlists_context_unqueue(struct
intel_engine_cs *ring)
}
}
+ if (IS_GEN8(ring-dev) || IS_GEN9(ring-dev)) {
+ /*
+ * WaIdleLiteRestore: make sure we never cause a lite
+ * restore with HEAD==TAIL
+ */
+ if (req0 req0-elsp_submitted == 1) {
+ /*
+ * Consume the buffer NOOPs to ensure HEAD != TAIL when
+ * submitting. elsp_submitted can only be 1 after
+ * reset, in which case we don't need the workaround as
+ * a lite restore will not occur.
I actually think you can remove the == 1 and hence remove comment since
the wa is safe to apply in that case as well.
/* Apply the wa NOOPS to prevent ring:HEAD == rq:TAIL as we
* resubmit the request. See gen8_emit_request() for where we
* prepare the padding after the end of the request.
*/
+ */
+ struct intel_ringbuffer *ringbuf;
+
+ ringbuf = req0-ctx-engine[ring-id].ringbuf;
+ req0-tail += 8;
+ req0-tail = ringbuf-size - 1;
+ }
+ }
+
WARN_ON(req1 req1-elsp_submitted);
execlists_submit_contexts(ring, req0-ctx, req0-tail,
@@ -1289,7 +1309,12 @@ static int gen8_emit_request(struct intel_ringbuffer
*ringbuf,
u32 cmd;
int ret;
- ret = intel_logical_ring_begin(ringbuf, request-ctx, 6);
+ /*
+ * Reserve space for 2 NOOPs at the end of each request to be
+ * used as a workaround for not being allowed to do lite
+ * restore with HEAD==TAIL (WaIdleLiteRestore).
+ */
+ ret = intel_logical_ring_begin(ringbuf, request-ctx, 8);
if (ret)
return ret;
@@ -1307,6 +1332,14 @@ static int gen8_emit_request(struct intel_ringbuffer
*ringbuf,
intel_logical_ring_emit(ringbuf, MI_NOOP);
intel_logical_ring_advance_and_submit(ringbuf, request-ctx, request);
+ /*
+ * Here we add two extra NOOPs as padding to avoid
+ * lite restore of a context with HEAD==TAIL.
+ */
+ intel_logical_ring_emit(ringbuf, MI_NOOP);
+ intel_logical_ring_emit(ringbuf, MI_NOOP);
+ intel_logical_ring_advance(ringbuf);
+
Ok, looks better.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
___
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Re: [Intel-gfx] [PATCH v3] drm/i915: Workaround to avoid lite restore with HEAD==TAIL
On 4/15/2015 5:40 PM, Chris Wilson wrote:
On Wed, Apr 15, 2015 at 05:17:13PM +0100, Michel Thierry wrote:
WaIdleLiteRestore is an execlists-only workaround, and requires the driver
to ensure that any context always has HEAD!=TAIL when attempting lite
restore.
Add two extra MI_NOOP instructions at the end of each request, but keep
the requests tail pointing before the MI_NOOPs. We may not need to
executed them, and this is why request-tail must be sampled before adding
these extra instructions.
If we submit a context to the ELSP which has previously been submitted,
move the tail pointer past the MI_NOOPs. This ensures HEAD!=TAIL.
v2: Move overallocation to gen8_emit_request, and added note about
sampling request-tail in commit message (Chris).
v3: Remove redundant request-tail assignment in __i915_add_request, in
lrc mode this is already set in execlists_context_queue.
Do not add wa implementation details inside gem (Chris).
Cc: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Thomas Daniel thomas.dan...@intel.com
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_gem.c | 3 ++-
drivers/gpu/drm/i915/intel_lrc.c | 35 ++-
2 files changed, 36 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 3d5a5a8..980e17c 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2400,10 +2400,11 @@ int __i915_add_request(struct intel_engine_cs *ring,
ret = ring-add_request(ring);
if (ret)
return ret;
+
+ request-tail = intel_ring_get_tail(ringbuf);
}
request-head = request_start;
- request-tail = intel_ring_get_tail(ringbuf);
/* Whilst this request exists, batch_obj will be on the
* active_list, and so will hold the active reference. Only when this
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index f4a5ef9..0296350 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -427,6 +427,26 @@ static void execlists_context_unqueue(struct
intel_engine_cs *ring)
}
}
+ if (IS_GEN8(ring-dev) || IS_GEN9(ring-dev)) {
+ /*
+* WaIdleLiteRestore: make sure we never cause a lite
+* restore with HEAD==TAIL
+*/
+ if (req0 req0-elsp_submitted == 1) {
+ /*
+* Consume the buffer NOOPs to ensure HEAD != TAIL when
+* submitting. elsp_submitted can only be 1 after
+* reset, in which case we don't need the workaround as
+* a lite restore will not occur.
I actually think you can remove the == 1 and hence remove comment since
the wa is safe to apply in that case as well.
/* Apply the wa NOOPS to prevent ring:HEAD == rq:TAIL as we
* resubmit the request. See gen8_emit_request() for where we
* prepare the padding after the end of the request.
*/
Yes, it's safe to apply it after the request has been submitted multiple
times.
I'll change that and update the comment.
Thanks,
-Michel
+*/
+ struct intel_ringbuffer *ringbuf;
+
+ ringbuf = req0-ctx-engine[ring-id].ringbuf;
+ req0-tail += 8;
+ req0-tail = ringbuf-size - 1;
+ }
+ }
+
WARN_ON(req1 req1-elsp_submitted);
execlists_submit_contexts(ring, req0-ctx, req0-tail,
@@ -1289,7 +1309,12 @@ static int gen8_emit_request(struct intel_ringbuffer
*ringbuf,
u32 cmd;
int ret;
- ret = intel_logical_ring_begin(ringbuf, request-ctx, 6);
+ /*
+* Reserve space for 2 NOOPs at the end of each request to be
+* used as a workaround for not being allowed to do lite
+* restore with HEAD==TAIL (WaIdleLiteRestore).
+*/
+ ret = intel_logical_ring_begin(ringbuf, request-ctx, 8);
if (ret)
return ret;
@@ -1307,6 +1332,14 @@ static int gen8_emit_request(struct intel_ringbuffer *ringbuf,
intel_logical_ring_emit(ringbuf, MI_NOOP);
intel_logical_ring_advance_and_submit(ringbuf, request-ctx, request);
+ /*
+* Here we add two extra NOOPs as padding to avoid
+* lite restore of a context with HEAD==TAIL.
+*/
+ intel_logical_ring_emit(ringbuf, MI_NOOP);
+ intel_logical_ring_emit(ringbuf, MI_NOOP);
+ intel_logical_ring_advance(ringbuf);
+
Ok, looks better.
-Chris
___
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[Intel-gfx] [PATCH 03/12] drm/i915: Add EDID read in intel_dp_check_link_status() for Link CTS 4.2.2.1
Adds in an EDID read after the DPCD read to accommodate test 4.2.2.1 in the
Displayport Link CTS Core 1.2 rev1.1. This test requires an EDID read for
all HPD plug events. To reduce the amount of code, this EDID read is also
used for Link CTS tests 4.2.2.3, 4.2.2.4, 4.2.2.5 and 4.2.2.6. Actual
support for these tests is implemented in later patches in this series.
V2:
- Fixed compilation error introduced during rework
V3:
- Plugged a memory leak where the EDID data wasn't being freed
after allocation in this function
V4:
- Fixed whitespace problems
- Cleaned up formatting
V5:
- Added propagation of the long_hpd flag from the hot_pulse function
Signed-off-by: Todd Previte tprev...@gmail.com
---
drivers/gpu/drm/i915/intel_dp.c | 19 +--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 1352c00..23586f6 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4110,15 +4110,30 @@ go_again:
* 4. Check link status on receipt of hot-plug interrupt
*/
static void
-intel_dp_check_link_status(struct intel_dp *intel_dp)
+intel_dp_check_link_status(struct intel_dp *intel_dp, bool long_hpd)
{
struct drm_device *dev = intel_dp_to_dev(intel_dp);
struct intel_encoder *intel_encoder = dp_to_dig_port(intel_dp)-base;
+ struct drm_connector *connector = intel_dp-attached_connector-base;
+ struct i2c_adapter *adapter = intel_dp-aux.ddc;
+ struct edid *edid_read = NULL;
u8 sink_irq_vector;
u8 link_status[DP_LINK_STATUS_SIZE];
WARN_ON(!drm_modeset_is_locked(dev-mode_config.connection_mutex));
+ /* Displayport Link CTS Core 1.2 rev1.1 EDID testing
+* 4.2.2.1 - EDID read required for all HPD events
+*/
+ if (long_hpd) {
+ edid_read = drm_get_edid(connector, adapter);
+ if (!edid_read) {
+ DRM_DEBUG_DRIVER(Invalid EDID detected\n);
+ } else {
+ kfree(edid_read);
+ }
+ }
+
/* Try to read the source of the interrupt */
if (intel_dp-dpcd[DP_DPCD_REV] = 0x11
intel_dp_get_sink_irq(intel_dp, sink_irq_vector)) {
@@ -4773,7 +4788,7 @@ intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port, bool long_hpd)
* but for short hpds we should check it now
*/
drm_modeset_lock(dev-mode_config.connection_mutex,
NULL);
- intel_dp_check_link_status(intel_dp);
+ intel_dp_check_link_status(intel_dp, long_hpd);
drm_modeset_unlock(dev-mode_config.connection_mutex);
}
}
--
1.9.1
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[Intel-gfx] [PATCH 1/2] drm/i915: Add psr_ready on pipe_config
Let's know beforehand if PSR is ready and will be enabled so we can
prevent DRRS to get enabled.
v2: Removing is_edp_psr func that is not used after this patch.
Rename match_conditions and document it since it is now external.
Moving to a propper place as pointed out by Sivakumar.
Use a better name as pointed out by Ram.
v3: Don't dereferrence drm_encoder-crtc and intel_crtc-config on psr_ready
check.
Fix a opps caused with previous versions.
Cc: Sivakumar Thulasimani sivakumar.thulasim...@intel.com
Cc: Ramalingam C ramalinga...@intel.com
Cc: Chris Wilson ch...@chris-wilson.co.uk
Cc: Daniel Vetter dan...@ffwll.ch
Reviewed-by: Ramalingam C ramalinga...@intel.com (v2)
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 1 +
drivers/gpu/drm/i915/intel_dp.c | 2 ++
drivers/gpu/drm/i915/intel_drv.h | 3 ++
drivers/gpu/drm/i915/intel_psr.c | 57
4 files changed, 38 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 75afa6e..50f2db7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10895,6 +10895,7 @@ static void intel_dump_pipe_config(struct intel_crtc
*crtc,
pipe_config-pch_pfit.pos,
pipe_config-pch_pfit.size,
pipe_config-pch_pfit.enabled ? enabled : disabled);
+ DRM_DEBUG_KMS(psr ready: %i\n, pipe_config-psr_ready);
DRM_DEBUG_KMS(ips: %i\n, pipe_config-ips_enabled);
DRM_DEBUG_KMS(double wide: %i\n, pipe_config-double_wide);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 14cdd00..94bbdf4 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1394,6 +1394,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
*/
min_lane_count = max_lane_count;
min_clock = max_clock;
+
+ pipe_config-psr_ready = intel_psr_ready(intel_dp, pipe_config);
}
for (; bpp = 6*3; bpp -= 2*3) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 082be71..9895772 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -448,6 +448,7 @@ struct intel_crtc_state {
int fdi_lanes;
struct intel_link_m_n fdi_m_n;
+ bool psr_ready;
bool ips_enabled;
bool double_wide;
@@ -1287,6 +1288,8 @@ void intel_backlight_unregister(struct drm_device *dev);
/* intel_psr.c */
+bool intel_psr_ready(struct intel_dp *intel_dp,
+struct intel_crtc_state *pipe_config);
void intel_psr_enable(struct intel_dp *intel_dp);
void intel_psr_disable(struct intel_dp *intel_dp);
void intel_psr_invalidate(struct drm_device *dev,
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 5ee0fa5..61d582b 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -56,11 +56,6 @@
#include intel_drv.h
#include i915_drv.h
-static bool is_edp_psr(struct intel_dp *intel_dp)
-{
- return intel_dp-psr_dpcd[0] DP_PSR_IS_SUPPORTED;
-}
-
static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe)
{
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -282,19 +277,32 @@ static void hsw_psr_enable_source(struct intel_dp
*intel_dp)
EDP_SU_TRACK_ENABLE | EDP_PSR2_TP2_TIME_100);
}
-static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
+/**
+ * intel_psr_ready - PSR ready
+ * @intel_dp: Intel DP
+ * @pipe_config: Pipe Config
+ *
+ * This function Checks if PSR is supported by Hardware/Source and
+ * Panel/Sink and if all conditions to be enabled are fulfilled.
+ *
+ * It is used to know beforehand if PSR is going to be enabled.
+ *
+ * Returns:
+ * True when PSR is ready to be enabled, false otherwise.
+ */
+bool intel_psr_ready(struct intel_dp *intel_dp,
+struct intel_crtc_state *pipe_config)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_device *dev = dig_port-base.base.dev;
struct drm_i915_private *dev_priv = dev-dev_private;
- struct drm_crtc *crtc = dig_port-base.base.crtc;
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- lockdep_assert_held(dev_priv-psr.lock);
- WARN_ON(!drm_modeset_is_locked(dev-mode_config.connection_mutex));
- WARN_ON(!drm_modeset_is_locked(crtc-mutex));
+ if (!HAS_PSR(dev)) {
+ DRM_DEBUG_KMS(PSR not supported on this platform\n);
+ return false;
+ }
- dev_priv-psr.source_ok = false;
+ WARN_ON(!drm_modeset_is_locked(dev-mode_config.connection_mutex));
if (IS_HASWELL(dev) dig_port-port != PORT_A) {
DRM_DEBUG_KMS(HSW ties PSR to DDI
[Intel-gfx] [PATCH 2/2] drm/i915: Only enabled DRRS if PRS won't be enabled on this pipe.
With PSR enabled being pre computed on pipe_config we can now
prevent DRRS to be enabled along with PSR.
v2: Rebase after changing previous patch
Cc: Ramalingam C ramalinga...@intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
Reviewed-by: Ramalingam C ramalinga...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 94bbdf4..bf4b0cf 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5011,11 +5011,6 @@ static void intel_dp_set_drrs_state(struct drm_device
*dev, int refresh_rate)
return;
}
- /*
-* FIXME: This needs proper synchronization with psr state for some
-* platforms that cannot have PSR and DRRS enabled at the same time.
-*/
-
dig_port = dp_to_dig_port(intel_dp);
encoder = dig_port-base;
intel_crtc = to_intel_crtc(encoder-base.crtc);
@@ -5101,6 +5096,11 @@ void intel_edp_drrs_enable(struct intel_dp *intel_dp)
return;
}
+ if (intel_crtc-config-psr_ready) {
+ DRM_DEBUG_KMS(DRRS: PSR will be enabled on this crtc\n);
+ return;
+ }
+
mutex_lock(dev_priv-drrs.mutex);
if (WARN_ON(dev_priv-drrs.dp)) {
DRM_ERROR(DRRS already enabled\n);
--
2.1.0
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Re: [Intel-gfx] [PATCH v4] drm/i915: Workaround to avoid lite restore with HEAD==TAIL
On Wed, Apr 15, 2015 at 06:11:33PM +0100, Michel Thierry wrote: WaIdleLiteRestore is an execlists-only workaround, and requires the driver to ensure that any context always has HEAD!=TAIL when attempting lite restore. Add two extra MI_NOOP instructions at the end of each request, but keep the requests tail pointing before the MI_NOOPs. We may not need to executed them, and this is why request-tail is sampled before adding these extra instructions. If we submit a context to the ELSP which has previously been submitted, move the tail pointer past the MI_NOOPs. This ensures HEAD!=TAIL. v2: Move overallocation to gen8_emit_request, and added note about sampling request-tail in commit message (Chris). v3: Remove redundant request-tail assignment in __i915_add_request, in lrc mode this is already set in execlists_context_queue. Do not add wa implementation details inside gem (Chris). v4: Apply the wa whenever the req has been resubmitted and update comment (Chris). Cc: Chris Wilson ch...@chris-wilson.co.uk Signed-off-by: Thomas Daniel thomas.dan...@intel.com Signed-off-by: Michel Thierry michel.thie...@intel.com Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 05/12] drm: Add supporting structure for Displayport Link CTS test 4.2.2.6
Displayport compliance test 4.2.2.6 requires that a source device be capable of
detecting a corrupt EDID. The test specification states that the sink device
sets up the EDID with an invalid checksum. To do this, the sink sets up an
invalid EDID header, expecting the source device to generate the checksum and
compare it to the value stored in the last byte of the block data.
Unfortunately, the DRM EDID reading and parsing functions are actually too good
in this case; the header is fixed before the checksum is computed and thus the
code never sees the invalid checksum. This results in a failure to pass the
compliance test.
To correct this issue, a checksum is generated when the EDID header is detected
as corrupted. If the checksum is invalid, it sets the header_corrupt flag and
logs the errors. In the case of a more seriously damaged header (fixup score
less than the threshold) the code does not generate the checksum but does set
the header_corrupt flag.
V2:
- Removed the static bool global
- Added a bool to the drm_connector struct to reaplce the static one for
holding the status of raw edid header corruption detection
- Modified the function signature of the is_valid function to take an
additional parameter to store the corruption detected value
- Fixed the other callers of the above is_valid function
V3:
- Updated the commit message to be more clear about what and why this
patch does what it does.
- Added comment in code to clarify the operations there
- Removed compliance variable and check_link_status update; those
have been moved to a later patch
- Removed variable assignment from the bottom of the test handler
V4:
- Removed i915 tag from subject line as the patch is not i915-specific
V5:
- Moved code causing a compilation error to this patch where the variable
is actually declared
- Maintained blank lines / spacing so as to not contaminate the patch
V6:
- Removed extra debug messages
- Added documentation to for the added parameter on drm_edid_block_valid
- Fixed more whitespace issues in check_link_status
- Added a clear of the header_corrupt flag to the end of the test handler
in intel_dp.c
- Changed the usage of the new function prototype in several places to use
NULL where it is not needed by compliance testing
V7:
- Updated to account for long_pulse flag propagation
Signed-off-by: Todd Previte tprev...@gmail.com
Cc: dri-de...@lists.freedesktop.org
---
drivers/gpu/drm/drm_edid.c | 30 ++
drivers/gpu/drm/drm_edid_load.c | 7 +--
drivers/gpu/drm/i915/intel_dp.c | 6 +-
include/drm/drm_crtc.h | 8 +++-
4 files changed, 43 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 53bc7a6..1ed18f5 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1041,13 +1041,15 @@ static bool drm_edid_is_zero(const u8 *in_edid, int
length)
* @raw_edid: pointer to raw EDID block
* @block: type of block to validate (0 for base, extension otherwise)
* @print_bad_edid: if true, dump bad EDID blocks to the console
+ * @header_corrupt: if true, the header or checksum is invalid
*
* Validate a base or extension EDID block and optionally dump bad blocks to
* the console.
*
* Return: True if the block is valid, false otherwise.
*/
-bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid)
+bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
+ bool *header_corrupt)
{
u8 csum;
struct edid *edid = (struct edid *)raw_edid;
@@ -1062,9 +1064,25 @@ bool drm_edid_block_valid(u8 *raw_edid, int block, bool
print_bad_edid)
int score = drm_edid_header_is_valid(raw_edid);
if (score == 8) ;
else if (score = edid_fixup) {
+ /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
+* In order to properly generate the invalid checksum
+* required for this test, it must be generated using
+* the raw EDID data. Otherwise, the fix-up code here
+* will correct the problem, the checksum is correct
+* and the test fails
+*/
+ csum = drm_edid_block_checksum(raw_edid);
+ if (csum) {
+ if (header_corrupt)
+ *header_corrupt = 1;
+ }
DRM_DEBUG(Fixing EDID header, your hardware may be
failing\n);
memcpy(raw_edid, edid_header, sizeof(edid_header));
} else {
+ if (header_corrupt) {
+ DRM_DEBUG_DRIVER(Invalid EDID header\n);
+ *header_corrupt = 1;
+ }
goto bad;
}
}
[Intel-gfx] [PATCH 06/12] drm/i915: Update intel_dp_hpd_pulse() for non-MST operation
Update the hot plug function to handle the SST case. Instead of placing
the SST case within the long/short pulse block, it is now handled after
determining that MST mode is not in use. This way, the topology management
layer can handle any MST-related operations while SST operations are still
correctly handled afterwards.
This patch also corrects the problem of SST mode only being handled in the
case of a short (0.5ms - 1.0ms) HPD pulse. For compliance testing purposes
both short and long pulses are used by the different tests, thus both cases
need to be addressed for SST.
This patch replaces [PATCH 10/10] drm/i915: Fix intel_dp_hot_plug() in the
previous compliance testing patch sequence. Review feedback on that patch
indicated that updating intel_dp_hot_plug() was not the correct place for
the test handler.
For the SST case, the main stream is disabled for long HPD pulses as this
generally indicates either a connect/disconnect event or link failure. For
a number of case in compliance testing, the source is required to disable
the main link upon detection of a long HPD.
V2:
- N/A
V3:
- Place the SST mode link status check into the mst_fail case
- Remove obsolete comment regarding SST mode operation
- Removed an erroneous line of code that snuck in during rebasing
V4:
- Added a disable of the main stream (DP transport) for the long pulse case
for SST to support compliance testing
V5:
- Reworked SST handling to support tests 4.2.2.7 and 4.2.2.8
V6:
- Reformatted a comment
V7:
- Moved a comment again that was inadvertently moved
- Updated the code to properly handle all permutations of MST/SST and
short/long pulse.
- Adds a new 'connected' flag that prevents unnecessary operations when
the link is disconnected.
- Added a function to encapsulate detection of the HPD pin status in
in order to determine connected status
- Reformatted the if-statements in the function so the braces are
consistent for those with single statements after the if-statement
V8:
- Updated to account for long_hpd flag propagation
Signed-off-by: Todd Previte tprev...@gmail.com
---
drivers/gpu/drm/i915/intel_dp.c | 55 +---
drivers/gpu/drm/i915/intel_drv.h | 1 +
2 files changed, 35 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index ee41e10..aa3b89d 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4747,6 +4747,7 @@ intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port, bool long_hpd)
struct drm_i915_private *dev_priv = dev-dev_private;
enum intel_display_power_domain power_domain;
enum irqreturn ret = IRQ_NONE;
+ bool connected = false;
if (intel_dig_port-base.type != INTEL_OUTPUT_EDP)
intel_dig_port-base.type = INTEL_OUTPUT_DISPLAYPORT;
@@ -4770,19 +4771,15 @@ intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port, bool long_hpd)
power_domain = intel_display_port_power_domain(intel_encoder);
intel_display_power_get(dev_priv, power_domain);
+ connected = intel_dp_digital_port_connected(intel_dp);
+
if (long_hpd) {
- if (HAS_PCH_SPLIT(dev)) {
- if (!ibx_digital_port_connected(dev_priv,
intel_dig_port))
- goto mst_fail;
- } else {
- if (g4x_digital_port_connected(dev, intel_dig_port) !=
1)
- goto mst_fail;
- }
+ if (!connected)
+ goto mst_fail;
- if (!intel_dp_get_dpcd(intel_dp)) {
+ if (!intel_dp_get_dpcd(intel_dp))
goto mst_fail;
- }
intel_dp_probe_oui(intel_dp);
@@ -4790,20 +4787,9 @@ intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port, bool long_hpd)
goto mst_fail;
} else {
- if (intel_dp-is_mst) {
+ if (intel_dp-is_mst)
if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
goto mst_fail;
- }
-
- if (!intel_dp-is_mst) {
- /*
-* we'll check the link status via the normal hot plug
path later -
-* but for short hpds we should check it now
-*/
- drm_modeset_lock(dev-mode_config.connection_mutex,
NULL);
- intel_dp_check_link_status(intel_dp, long_hpd);
- drm_modeset_unlock(dev-mode_config.connection_mutex);
- }
}
ret = IRQ_HANDLED;
@@ -4817,6 +4803,15 @@ mst_fail:
drm_dp_mst_topology_mgr_set_mst(intel_dp-mst_mgr,
intel_dp-is_mst);
}
put_power:
+ /* SST mode - handle short/long pulses here */
+ if (!intel_dp-is_mst) {
+
+
[Intel-gfx] [PATCH 07/12] drm/i915: Support EDID compliance tests with the intel_dp_autotest_edid() function
Updates the EDID compliance test function to perform the EDID read as
required by the tests. This read needs to take place in the kernel for
reasons of speed and efficiency. The results of the EDID read operations
are handed off to userspace so that the userspace app can set the display
mode appropriately for the test response.
The compliance_test_active flag now appears at the end of the individual
test handling functions. This is so that the kernel-side operations can
be completed without the risk of interruption from the userspace app
that is polling on that flag.
V2:
- Addressed mailing list feedback
- Removed excess debug messages
- Removed extraneous comments
- Fixed formatting issues (line length 80)
- Updated the debug message in compute_edid_checksum to output hex values
instead of decimal
V3:
- Addressed more list feedback
- Added the test_active flag to the autotest function
- Removed test_active flag from handler
- Added failsafe check on the compliance test active flag
at the end of the test handler
- Fixed checkpatch.pl issues
V4:
- Removed the checksum computation function and its use as it has been
rendered superfluous by changes to the core DRM EDID functions
- Updated to use the raw header corruption detection mechanism
- Moved the declaration of the test_data variable here
V5:
- Update test active flag variable name to match the change in the
first patch of the series.
- Relocated the test active flag declaration and initialization
to this patch
V6:
- Updated to use the new flag for raw EDID header corruption
- Removed the extra EDID read from the autotest function
- Added the edid_checksum variable to struct intel_dp so that the
autotest function can write it to the sink device
- Moved the update to the hpd_pulse function to another patch
- Removed extraneous constants
V7:
- Fixed erroneous placement of the checksum assignment. In some cases
such as when the EDID read fails and is NULL, this causes a NULL ptr
dereference in the kernel. Bad news. Fixed now.
V8:
- Updated to support the kfree() on the EDID data added previously
V9:
- Updated for the long_hpd flag propagation
Signed-off-by: Todd Previte tprev...@gmail.com
---
drivers/gpu/drm/i915/intel_dp.c | 47 +++-
drivers/gpu/drm/i915/intel_drv.h | 4
2 files changed, 50 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index aa3b89d..714d48b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -41,6 +41,12 @@
#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
+/* Compliance test status bits */
+#define INTEL_DP_RESOLUTION_SHIFT_MASK 4
+#define INTEL_DP_RESOLUTION_PREFERRED (1 INTEL_DP_RESOLUTION_SHIFT_MASK)
+#define INTEL_DP_RESOLUTION_STANDARD (2 INTEL_DP_RESOLUTION_SHIFT_MASK)
+#define INTEL_DP_RESOLUTION_FAILSAFE (3 INTEL_DP_RESOLUTION_SHIFT_MASK)
+
struct dp_link_dpll {
int link_bw;
struct dpll dpll;
@@ -3994,6 +4000,35 @@ static uint8_t intel_dp_autotest_video_pattern(struct
intel_dp *intel_dp)
static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
{
uint8_t test_result = DP_TEST_NAK;
+ uint32_t ret = 0;
+
+ if (intel_dp-compliance_edid_invalid ||
+ intel_dp-aux.i2c_defer_count 6) {
+ /* Check for NACKs/DEFERs, use failsafe if detected
+* (DP CTS 1.2 Core Rev 1.1, 4.2.2.4, 4.2.2.5)
+*/
+ if (intel_dp-aux.i2c_nack_count 0 ||
+ intel_dp-aux.i2c_defer_count 0)
+ DRM_DEBUG_KMS(EDID read had %d NACKs, %d DEFERs\n,
+ intel_dp-aux.i2c_nack_count,
+ intel_dp-aux.i2c_defer_count);
+ intel_dp-compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
+ } else {
+ ret = drm_dp_dpcd_write(intel_dp-aux,
+ DP_TEST_EDID_CHECKSUM,
+ intel_dp-compliance_edid_checksum, 1);
+ if (ret = 0)
+ DRM_DEBUG_DRIVER(Failed to write EDID checksum\n);
+ else
+ DRM_DEBUG_DRIVER(EDID checksum written to sink\n);
+
+ test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
+ intel_dp-compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
+ }
+
+ /* Set test active flag here so userspace doesn't interrupt things */
+ intel_dp-compliance_test_active = 1;
+
return test_result;
}
@@ -4010,7 +4045,10 @@ static void intel_dp_handle_test_request(struct intel_dp
*intel_dp)
uint8_t rxdata = 0;
int status = 0;
+ intel_dp-compliance_test_active = 0;
intel_dp-compliance_test_type = 0;
+ intel_dp-compliance_test_data = 0;
+
intel_dp-aux.i2c_nack_count = 0;
intel_dp-aux.i2c_defer_count = 0;
@@
Re: [Intel-gfx] [PATCH v3] drm/i915/chv: Implement WaDisableShadowRegForCpd
On Wed, Apr 15, 2015 at 07:41:39PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
This WA is avoid problem between shadow vs wake FIFO unload
problem during CPD/RC6 transactions on CHV.
v2: Define individual bits GTFIFOCTL (Ville)
v3: move WA to uncore_early_sanitize (ville)
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_uncore.c | 8
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9c97842..a642a58 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6206,6 +6206,8 @@ enum skl_disp_power_wells {
#define GTFIFOCTL 0x120008
#defineGT_FIFO_FREE_ENTRIES_MASK 0x7f
#defineGT_FIFO_NUM_RESERVED_ENTRIES 20
+#define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 12)
+#define GT_FIFO_CTL_RC6_POLICY_STALL (1 11)
#define HSW_IDICR 0x9008
#defineIDIHASHMSK(x) (((x) 0x3f) 16)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index d96d15f..26d6dda 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -360,6 +360,14 @@ static void __intel_uncore_early_sanitize(struct
drm_device *dev,
__raw_i915_write32(dev_priv, GTFIFODBG,
__raw_i915_read32(dev_priv, GTFIFODBG));
+ /* WaDisableShadowRegForCpd */
I couldn't find this w/a name anywhere official, but I guess it's fine.
Should be WaDisableShadowRegForCpd:chv though. Otherwise looks good, so
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
+ if (IS_CHERRYVIEW(dev)) {
+ __raw_i915_write32(dev_priv, GTFIFOCTL,
+ __raw_i915_read32(dev_priv, GTFIFOCTL) |
+
GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
+ GT_FIFO_CTL_RC6_POLICY_STALL);
+ }
+
intel_uncore_forcewake_reset(dev, restore_forcewake);
}
--
1.9.1
--
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH] drm/vblank: Fixup and document timestamp update/read barriers
On Wed, Apr 15, 2015 at 09:00:04AM -0400, Peter Hurley wrote:
Hi Daniel,
On 04/15/2015 03:17 AM, Daniel Vetter wrote:
This was a bit too much cargo-culted, so lets make it solid:
- vblank-count doesn't need to be an atomic, writes are always done
under the protection of dev-vblank_time_lock. Switch to an unsigned
long instead and update comments. Note that atomic_read is just a
normal read of a volatile variable, so no need to audit all the
read-side access specifically.
- The barriers for the vblank counter seqlock weren't complete: The
read-side was missing the first barrier between the counter read and
the timestamp read, it only had a barrier between the ts and the
counter read. We need both.
- Barriers weren't properly documented. Since barriers only work if
you have them on boths sides of the transaction it's prudent to
reference where the other side is. To avoid duplicating the
write-side comment 3 times extract a little store_vblank() helper.
In that helper also assert that we do indeed hold
dev-vblank_time_lock, since in some cases the lock is acquired a
few functions up in the callchain.
Spotted while reviewing a patch from Chris Wilson to add a fastpath to
the vblank_wait ioctl.
Cc: Chris Wilson ch...@chris-wilson.co.uk
Cc: Mario Kleiner mario.kleiner...@gmail.com
Cc: Ville Syrjälä ville.syrj...@linux.intel.com
Cc: Michel Dänzer mic...@daenzer.net
Signed-off-by: Daniel Vetter daniel.vet...@intel.com
---
drivers/gpu/drm/drm_irq.c | 92
---
include/drm/drmP.h| 8 +++--
2 files changed, 54 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c
index c8a34476570a..23bfbc61a494 100644
--- a/drivers/gpu/drm/drm_irq.c
+++ b/drivers/gpu/drm/drm_irq.c
@@ -74,6 +74,33 @@ module_param_named(vblankoffdelay, drm_vblank_offdelay,
int, 0600);
module_param_named(timestamp_precision_usec, drm_timestamp_precision, int,
0600);
module_param_named(timestamp_monotonic, drm_timestamp_monotonic, int,
0600);
+static void store_vblank(struct drm_device *dev, int crtc,
+unsigned vblank_count_inc,
+struct timeval *t_vblank)
+{
+ struct drm_vblank_crtc *vblank = dev-vblank[crtc];
+ u32 tslot;
+
+ assert_spin_locked(dev-vblank_time_lock);
+
+ if (t_vblank) {
+ tslot = vblank-count + vblank_count_inc;
+ vblanktimestamp(dev, crtc, tslot) = *t_vblank;
+ }
+
+ /*
+* vblank timestamp updates are protected on the write side with
+* vblank_time_lock, but on the read side done locklessly using a
+* sequence-lock on the vblank counter. Ensure correct ordering using
+* memory barrriers. We need the barrier both before and also after the
+* counter update to synchronize with the next timestamp write.
+* The read-side barriers for this are in drm_vblank_count_and_time.
+*/
+ smp_wmb();
+ vblank-count += vblank_count_inc;
+ smp_wmb();
The comment and the code are each self-contradictory.
If vblank-count writes are always protected by vblank_time_lock (something I
did not verify but that the comment above asserts), then the trailing write
barrier is not required (and the assertion that it is in the comment is
incorrect).
A spin unlock operation is always a write barrier.
Hm yeah. Otoh to me that's bordering on code too clever for my own good.
That the spinlock is held I can assure. That no one goes around and does
multiple vblank updates (because somehow that code raced with the hw
itself) I can't easily assure with a simple assert or something similar.
It's not the case right now, but that can changes.
Also it's not contradictory here, since you'd need to audit all the
callers to be able to make the claim that the 2nd smp_wmb() is redundant.
I'll just add a comment about this.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
___
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[Intel-gfx] [PATCH] Enable dithering for ns2501 DVO (2)
Hi Daniel, hi Ville, please find the reworked NS2501 DVO patch with changes as suggested attached. Unfortunately, the relation between the DVO scaler settings and the actual mode values remain still somewhat mysterious, so the mode settings remain a table lookup at this time. On the bright side, the image quality improved notably due to dithering. Greetings, Thomas Signed-off-by: Thomas Richter t...@math.tu-berlin.de This patch enables the (unfortunately undocumented) scaler of the NatSemi 2501 DVO found in the Fujitsu-Siemens S6010 laptop and other machines of the same series and age. Parts of the DVO scaler logic have been revealed by reverse engineering and trial and error, so your milage may vary. The patch (and the whole ns2501 DVO code) is currently only good for the 1024x768 panel of the S6010, and may hopefully work on other machines with the same panel size. The mode-specific configuration of the scaler have been moved out into a separate class, the mode-agnostic settings remain as raw register list as their purpose remains unclear at this point. --- --- dvo_ns2501.c2015-04-15 19:36:31.0 +0200 +++ dvo_ns2501.c-org2015-04-14 15:34:34.0 +0200 @@ -60,130 +60,6 @@ #define NS2501_REGC 0x0c -/* - * The following registers are not part of the official datasheet - * and are the result of reverse engineering. - */ - -/* - * Register c0 controls how the DVO synchronizes with - * its input. - */ -#define NS2501_REGC0 0xc0 -#define NS2501_C0_ENABLE (10)/* enable the DVO sync in general */ -#define NS2501_C0_HSYNC (11) /* synchronize horizontal with input */ -#define NS2501_C0_VSYNC (12) /* synchronize vertical with input */ -#define NS2501_C0_RESET (17) /* reset the synchronization flip/flops */ - -/* - * Register 41 is somehow related to the sync register and sync - * configuration. It should be 0x32 whenever regC0 is 0x05 (hsync off) - * and 0x00 otherwise. - */ -#define NS2501_REG41 0x41 - -/* - * this register controls the dithering of the DVO - * One bit enables it, the other define the dithering depth. - * The higher the value, the lower the dithering depth. - */ -#define NS2501_F9_REG 0xf9 -#define NS2501_F9_ENABLE (10)/* if set, dithering is enabled */ -#define NS2501_F9_DITHER_MASK (0x7f1)/* controls the dither depth */ -#define NS2501_F9_DITHER_SHIFT 1 /* shifts the dither mask */ - -/* - * PLL configuration register. This is a pair of registers, - * one single byte register at 1B, and a pair at 1C,1D. - * These registers are counters/dividers. - */ -#define NS2501_REG1B 0x1b /* one byte PLL control register */ -#define NS2501_REG1C 0x1c /* low-part of the second register */ -#define NS2501_REG1D 0x1d /* high-part of the second register */ - -/* - * Scaler control registers. Horizontal at b8,b9, - * vertical at 10,11. The scale factor is computed as - * 2^16/control-value. The low-byte comes first. - */ -#define NS2501_REG10 0x10 /* low-byte vertical scaler */ -#define NS2501_REG11 0x11 /* high-byte vertical scaler */ -#define NS2501_REGB8 0xb8 /* low-byte horizontal scaler */ -#define NS2501_REGB9 0xb9 /* high-byte horizontal scaler */ - -/* - * Display window definition. This consists of four registers - * per dimension. One register pair defines the start of the - * display, one the end. - * As far as I understand, this defines the window within which - * the scaler samples the input. - */ -#define NS2501_REGC1 0xc1 /* low-byte horizontal display start */ -#define NS2501_REGC2 0xc2 /* high-byte horizontal display start */ -#define NS2501_REGC3 0xc3 /* low-byte horizontal display stop */ -#define NS2501_REGC4 0xc4 /* high-byte horizontal display stop */ -#define NS2501_REGC5 0xc5 /* low-byte vertical display start */ -#define NS2501_REGC6 0xc6 /* high-byte vertical display start */ -#define NS2501_REGC7 0xc7 /* low-byte vertical display stop */ -#define NS2501_REGC8 0xc8 /* high-byte vertical display stop */ - -/* - * The following register pair seems to define the start of - * the vertical sync. If automatic syncing is enabled, and the - * register value defines a sync pulse that is later than the - * incoming sync, then the register value is ignored and the - * external hsync triggers the synchronization. - */ -#define NS2501_REG80 0x80 /* low-byte vsync-start */ -#define NS2501_REG81 0x81 /* high-byte vsync-start */ - -/* - * The following register pair seems to define the total number - * of lines created at the output side of the scaler. - * This is again a low-high register pair. - */ -#define NS2501_REG82 0x82 /* output display height, low byte */ -#define NS2501_REG83 0x83 /* output display height, high byte */ - -/* - * The following registers define the end of the front-porch - * in horizontal and vertical position and hence allow to shift - * the image left/right or up/down. - */ -#define NS2501_REG98 0x98 /* horizontal start of display + 256, low */ -#define NS2501_REG99 0x99 /* horizontal start
Re: [Intel-gfx] [PATCH] drm/vblank: Fixup and document timestamp update/read barriers
On Wed, Apr 15, 2015 at 07:34:43PM +0200, Daniel Vetter wrote: This was a bit too much cargo-culted, so lets make it solid: - vblank-count doesn't need to be an atomic, writes are always done under the protection of dev-vblank_time_lock. Switch to an unsigned long instead and update comments. Note that atomic_read is just a normal read of a volatile variable, so no need to audit all the read-side access specifically. - The barriers for the vblank counter seqlock weren't complete: The read-side was missing the first barrier between the counter read and the timestamp read, it only had a barrier between the ts and the counter read. We need both. - Barriers weren't properly documented. Since barriers only work if you have them on boths sides of the transaction it's prudent to reference where the other side is. To avoid duplicating the write-side comment 3 times extract a little store_vblank() helper. In that helper also assert that we do indeed hold dev-vblank_time_lock, since in some cases the lock is acquired a few functions up in the callchain. Spotted while reviewing a patch from Chris Wilson to add a fastpath to the vblank_wait ioctl. v2: Add comment to better explain how store_vblank works, suggested by Chris. v3: Peter noticed that as-is the 2nd smp_wmb is redundant with the implicit barrier in the spin_unlock. But that can only be proven by auditing all callers and my point in extracting this little helper was to localize all the locking into just one place. Hence I think that additional optimization is too risky. Cc: Chris Wilson ch...@chris-wilson.co.uk Cc: Mario Kleiner mario.kleiner...@gmail.com Cc: Ville Syrjälä ville.syrj...@linux.intel.com Cc: Michel Dänzer mic...@daenzer.net Cc: Peter Hurley pe...@hurleysoftware.com Signed-off-by: Daniel Vetter daniel.vet...@intel.com Fwiw, there was no discernible difference in the time to query the vblank counter (on an ivb i7-3720QM). Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 34/49] drm/i915/bxt: Restrict PORT_CLK_SEL programming below gen9
On Wed, 2015-04-15 at 17:15 +0300, Imre Deak wrote:
From: Satheeshakrishna M satheeshakrishn...@intel.com
PORT_CLK_SEL programming is needed only on HSW/BDW.
v2:
- don't program PORT_CLK_SEL from mst encoders either (imre)
v3:
- fix the check for GEN9+ in intel_mst_pre_enable_dp() (damien)
Signed-off-by: Satheeshakrishna M satheeshakrishn...@intel.com
Signed-off-by: Imre Deak imre.d...@intel.com
Reviewed-by: Sagar Kamble sagar.a.kamble at intel.com
---
drivers/gpu/drm/i915/intel_ddi.c| 4 ++--
drivers/gpu/drm/i915/intel_dp_mst.c | 6 --
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c
b/drivers/gpu/drm/i915/intel_ddi.c
index 31cadb8..6bdccb2 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1565,7 +1565,7 @@ static void intel_ddi_pre_enable(struct intel_encoder
*intel_encoder)
I915_WRITE(DPLL_CTRL2, val);
- } else {
+ } else if (INTEL_INFO(dev)-gen 9) {
WARN_ON(crtc-config-ddi_pll_sel == PORT_CLK_SEL_NONE);
I915_WRITE(PORT_CLK_SEL(port), crtc-config-ddi_pll_sel);
}
@@ -1624,7 +1624,7 @@ static void intel_ddi_post_disable(struct intel_encoder
*intel_encoder)
if (IS_SKYLAKE(dev))
I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
DPLL_CTRL2_DDI_CLK_OFF(port)));
- else
+ else if (INTEL_INFO(dev)-gen 9)
I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
}
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
b/drivers/gpu/drm/i915/intel_dp_mst.c
index 7335089..3945057 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -173,8 +173,10 @@ static void intel_mst_pre_enable_dp(struct intel_encoder
*encoder)
if (intel_dp-active_mst_links == 0) {
enum port port = intel_ddi_get_encoder_port(encoder);
- I915_WRITE(PORT_CLK_SEL(port),
-intel_crtc-config-ddi_pll_sel);
+ /* FIXME: add support for SKL */
+ if (INTEL_INFO(dev)-gen 9)
+ I915_WRITE(PORT_CLK_SEL(port),
+intel_crtc-config-ddi_pll_sel);
intel_ddi_init_dp_buf_reg(intel_dig_port-base);
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Re: [Intel-gfx] [PATCH 04/13] drm/i915: Add EDID read in intel_dp_check_link_status() for Link CTS 4.2.2.1
2015-04-15 12:37 GMT-03:00 Todd Previte tprev...@gmail.com:
On 4/14/2015 9:53 AM, Paulo Zanoni wrote:
2015-04-13 11:53 GMT-03:00 Todd Previte tprev...@gmail.com:
Adds in an EDID read after the DPCD read to accommodate test 4.2.2.1 in
the
Displayport Link CTS Core 1.2 rev1.1. This test requires an EDID read for
all HPD plug events. To reduce the amount of code, this EDID read is also
used for Link CTS tests 4.2.2.3, 4.2.2.4, 4.2.2.5 and 4.2.2.6. Actual
support for these tests is implemented in later patches in this series.
V2:
- Fixed compilation error introduced during rework
Signed-off-by: Todd Previte tprev...@gmail.com
---
drivers/gpu/drm/i915/intel_dp.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c
b/drivers/gpu/drm/i915/intel_dp.c
index 23184b0..75df3e2 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3890,6 +3890,9 @@ intel_dp_check_link_status(struct intel_dp
*intel_dp)
{
struct drm_device *dev = intel_dp_to_dev(intel_dp);
struct intel_encoder *intel_encoder =
dp_to_dig_port(intel_dp)-base;
+ struct drm_connector *connector =
intel_dp-attached_connector-base;
+ struct i2c_adapter *adapter = intel_dp-aux.ddc;
+ struct edid *edid_read = NULL;
u8 sink_irq_vector;
u8 link_status[DP_LINK_STATUS_SIZE];
@@ -3906,6 +3909,14 @@ intel_dp_check_link_status(struct intel_dp
*intel_dp)
return;
}
+ /* Displayport Link CTS Core 1.2 rev1.1 EDID testing
+* 4.2.2.1 - EDID read required for all HPD events
+ */
+edid_read = drm_get_edid(connector, adapter);
+if (!edid_read) {
+DRM_DEBUG_DRIVER(Invalid EDID detected\n);
+}
+
We already briefly discussed this patch in private, so I'm going to
summarize the discussion and also add some more points here.
Frist, the actual detailed review: the indentation here is using
spaces and we're leaking the EDID. This will cause rebases to a few of
the next patches.
Back to the hight level architecture: your initial versions of the
series contained just 1 extra EDID read, and it was contained inside
the compliance testing function. Then the versions submitted a few
days ago had 2 extra EDID reads, then after some discussion you
reduced to 1 extra EDID read (the one on this patch). I previously
asked But what about the automatic EDID read we do when we get a
hotplug? Can't we just rely on it?. I got some answers to the
question, but I was not really convinced.
Yesterday I was arguing that this extra EDID read is going to add a
small delay to every hotplug event we get, so my initial suggestion
was to organize the compliance testing in a way that would require the
user space program to call the GetResources() IOCTL to force the EDID
when needed. Your argument was that then the DP compliance testing
procedure would be testing our app for compliance, not the Kernel.
But today I decided to finally do some debugging regarding this, and I
was able to confirm that we do follow the DP requirements: we do have
an automatic EDID read done by the Kernel whenever we do a hotplug:
i915_hotplug_work_func() calls intel_dp_detect(), which ends calling
drm_get_edid() at some point. This function also does other stuff that
is required by the compliance testing, such as the DPCD reads.
Now there's a problem with using i915_hotplug_work_func(), which could
the reason why you rejected it: it only happens after
intel_dp_hpd_pulse(), which means that we only really do the EDID read
after intel_dp_handle_test_request().
I consider i915_hotplug_work_func() a fundamental part of our DP
framework, and the DP compliance testing seems to be just ignoring its
existence. So my idea for a solution here would be to make
intel_dp_handle_test_request() run on its own delayed work function.
It would wait for both i915_digport_work_func() and
i915_hotplug_work_func() to finish, and only then it would do the
normal processing. With this, we would be able to avoid the edid read
on this patch, we would maybe be able to avoid at least part of patch
2, we would maybe be able to completely avoid patch 7, and then on
patch 8 we would start touching intel_dp_get_edid() instead.
I know this is sort of a fundamental change that is being requested a
little late in the review process, and it can be frustrating, but this
aspect of the code only recently changed (I was fine with the EDID
reads just in the compliance testing function), and since the DP
compliance code is quite complex, it took me a while to realize
everything that's going on and what is the purpose of each piece. I
also think that, since this idea will allow the compliance testing to
take into consideration the work done by i915_hotplug_work_func(),
compliance testing will better reflect the behavior that is actually
done by the
Re: [Intel-gfx] [PATCH v2] drm/i915/chv: Implement WaDisableShadowRegForCpd
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 6196 -Summary- Platform Delta drm-intel-nightly Series Applied PNV 276/276 276/276 ILK 302/302 302/302 SNB 318/318 318/318 IVB 341/341 341/341 BYT 287/287 287/287 HSW -1 395/395 394/395 BDW 318/318 318/318 -Detailed- Platform Testdrm-intel-nightly Series Applied *HSW igt@gem_pwrite_pread@snooped-copy-performance PASS(2) DMESG_WARN(1)PASS(1) (dmesg patch applied)drm:i915_hangcheck_elapsed[i915]]*ERROR*Hangcheck_timer_elapsed...blitter_ring_idle@Hangcheck timer elapsed... blitter ring idle Note: You need to pay more attention to line start with '*' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/vblank: Fixup and document timestamp update/read barriers
This was a bit too much cargo-culted, so lets make it solid:
- vblank-count doesn't need to be an atomic, writes are always done
under the protection of dev-vblank_time_lock. Switch to an unsigned
long instead and update comments. Note that atomic_read is just a
normal read of a volatile variable, so no need to audit all the
read-side access specifically.
- The barriers for the vblank counter seqlock weren't complete: The
read-side was missing the first barrier between the counter read and
the timestamp read, it only had a barrier between the ts and the
counter read. We need both.
- Barriers weren't properly documented. Since barriers only work if
you have them on boths sides of the transaction it's prudent to
reference where the other side is. To avoid duplicating the
write-side comment 3 times extract a little store_vblank() helper.
In that helper also assert that we do indeed hold
dev-vblank_time_lock, since in some cases the lock is acquired a
few functions up in the callchain.
Spotted while reviewing a patch from Chris Wilson to add a fastpath to
the vblank_wait ioctl.
v2: Add comment to better explain how store_vblank works, suggested by
Chris.
v3: Peter noticed that as-is the 2nd smp_wmb is redundant with the
implicit barrier in the spin_unlock. But that can only be proven by
auditing all callers and my point in extracting this little helper was
to localize all the locking into just one place. Hence I think that
additional optimization is too risky.
Cc: Chris Wilson ch...@chris-wilson.co.uk
Cc: Mario Kleiner mario.kleiner...@gmail.com
Cc: Ville Syrjälä ville.syrj...@linux.intel.com
Cc: Michel Dänzer mic...@daenzer.net
Cc: Peter Hurley pe...@hurleysoftware.com
Signed-off-by: Daniel Vetter daniel.vet...@intel.com
---
drivers/gpu/drm/drm_irq.c | 95 +--
include/drm/drmP.h| 8 +++-
2 files changed, 57 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c
index c8a34476570a..8694b77d0002 100644
--- a/drivers/gpu/drm/drm_irq.c
+++ b/drivers/gpu/drm/drm_irq.c
@@ -74,6 +74,36 @@ module_param_named(vblankoffdelay, drm_vblank_offdelay, int,
0600);
module_param_named(timestamp_precision_usec, drm_timestamp_precision, int,
0600);
module_param_named(timestamp_monotonic, drm_timestamp_monotonic, int, 0600);
+static void store_vblank(struct drm_device *dev, int crtc,
+unsigned vblank_count_inc,
+struct timeval *t_vblank)
+{
+ struct drm_vblank_crtc *vblank = dev-vblank[crtc];
+ u32 tslot;
+
+ assert_spin_locked(dev-vblank_time_lock);
+
+ if (t_vblank) {
+ /* All writers hold the spinlock, but readers are serialized by
+* the latching of vblank-count below.
+*/
+ tslot = vblank-count + vblank_count_inc;
+ vblanktimestamp(dev, crtc, tslot) = *t_vblank;
+ }
+
+ /*
+* vblank timestamp updates are protected on the write side with
+* vblank_time_lock, but on the read side done locklessly using a
+* sequence-lock on the vblank counter. Ensure correct ordering using
+* memory barrriers. We need the barrier both before and also after the
+* counter update to synchronize with the next timestamp write.
+* The read-side barriers for this are in drm_vblank_count_and_time.
+*/
+ smp_wmb();
+ vblank-count += vblank_count_inc;
+ smp_wmb();
+}
+
/**
* drm_update_vblank_count - update the master vblank counter
* @dev: DRM device
@@ -93,7 +123,7 @@ module_param_named(timestamp_monotonic,
drm_timestamp_monotonic, int, 0600);
static void drm_update_vblank_count(struct drm_device *dev, int crtc)
{
struct drm_vblank_crtc *vblank = dev-vblank[crtc];
- u32 cur_vblank, diff, tslot;
+ u32 cur_vblank, diff;
bool rc;
struct timeval t_vblank;
@@ -129,18 +159,12 @@ static void drm_update_vblank_count(struct drm_device
*dev, int crtc)
if (diff == 0)
return;
- /* Reinitialize corresponding vblank timestamp if high-precision query
-* available. Skip this step if query unsupported or failed. Will
-* reinitialize delayed at next vblank interrupt in that case.
+ /*
+* Only reinitialize corresponding vblank timestamp if high-precision
query
+* available and didn't fail. Will reinitialize delayed at next vblank
+* interrupt in that case.
*/
- if (rc) {
- tslot = atomic_read(vblank-count) + diff;
- vblanktimestamp(dev, crtc, tslot) = t_vblank;
- }
-
- smp_mb__before_atomic();
- atomic_add(diff, vblank-count);
- smp_mb__after_atomic();
+ store_vblank(dev, crtc, diff, rc ? t_vblank : NULL);
}
/*
@@ -218,7 +242,7 @@ static void vblank_disable_and_save(struct drm_device *dev,
int crtc)
Re: [Intel-gfx] [PATCH 05/12] drm: Add supporting structure for Displayport Link CTS test 4.2.2.6
2015-04-15 14:15 GMT-03:00 Todd Previte tprev...@gmail.com:
Displayport compliance test 4.2.2.6 requires that a source device be capable
of
detecting a corrupt EDID. The test specification states that the sink device
sets up the EDID with an invalid checksum. To do this, the sink sets up an
invalid EDID header, expecting the source device to generate the checksum and
compare it to the value stored in the last byte of the block data.
Unfortunately, the DRM EDID reading and parsing functions are actually too
good
in this case; the header is fixed before the checksum is computed and thus the
code never sees the invalid checksum. This results in a failure to pass the
compliance test.
To correct this issue, a checksum is generated when the EDID header is
detected
as corrupted. If the checksum is invalid, it sets the header_corrupt flag and
logs the errors. In the case of a more seriously damaged header (fixup score
less than the threshold) the code does not generate the checksum but does set
the header_corrupt flag.
V2:
- Removed the static bool global
- Added a bool to the drm_connector struct to reaplce the static one for
holding the status of raw edid header corruption detection
- Modified the function signature of the is_valid function to take an
additional parameter to store the corruption detected value
- Fixed the other callers of the above is_valid function
V3:
- Updated the commit message to be more clear about what and why this
patch does what it does.
- Added comment in code to clarify the operations there
- Removed compliance variable and check_link_status update; those
have been moved to a later patch
- Removed variable assignment from the bottom of the test handler
V4:
- Removed i915 tag from subject line as the patch is not i915-specific
V5:
- Moved code causing a compilation error to this patch where the variable
is actually declared
- Maintained blank lines / spacing so as to not contaminate the patch
V6:
- Removed extra debug messages
- Added documentation to for the added parameter on drm_edid_block_valid
- Fixed more whitespace issues in check_link_status
- Added a clear of the header_corrupt flag to the end of the test handler
in intel_dp.c
- Changed the usage of the new function prototype in several places to use
NULL where it is not needed by compliance testing
V7:
- Updated to account for long_pulse flag propagation
Signed-off-by: Todd Previte tprev...@gmail.com
Cc: dri-de...@lists.freedesktop.org
---
drivers/gpu/drm/drm_edid.c | 30 ++
drivers/gpu/drm/drm_edid_load.c | 7 +--
drivers/gpu/drm/i915/intel_dp.c | 6 +-
include/drm/drm_crtc.h | 8 +++-
4 files changed, 43 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 53bc7a6..1ed18f5 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1041,13 +1041,15 @@ static bool drm_edid_is_zero(const u8 *in_edid, int
length)
* @raw_edid: pointer to raw EDID block
* @block: type of block to validate (0 for base, extension otherwise)
* @print_bad_edid: if true, dump bad EDID blocks to the console
+ * @header_corrupt: if true, the header or checksum is invalid
*
* Validate a base or extension EDID block and optionally dump bad blocks to
* the console.
*
* Return: True if the block is valid, false otherwise.
*/
-bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid)
+bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
+ bool *header_corrupt)
{
u8 csum;
struct edid *edid = (struct edid *)raw_edid;
@@ -1062,9 +1064,25 @@ bool drm_edid_block_valid(u8 *raw_edid, int block,
bool print_bad_edid)
int score = drm_edid_header_is_valid(raw_edid);
if (score == 8) ;
else if (score = edid_fixup) {
+ /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
+* In order to properly generate the invalid checksum
+* required for this test, it must be generated using
+* the raw EDID data. Otherwise, the fix-up code here
+* will correct the problem, the checksum is correct
+* and the test fails
+*/
+ csum = drm_edid_block_checksum(raw_edid);
+ if (csum) {
+ if (header_corrupt)
+ *header_corrupt = 1;
+ }
DRM_DEBUG(Fixing EDID header, your hardware may be
failing\n);
memcpy(raw_edid, edid_header, sizeof(edid_header));
} else {
+ if (header_corrupt) {
+
Re: [Intel-gfx] [PATCH v2] drm/i915: Workaround to avoid lite restore with HEAD==TAIL
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 6192 -Summary- Platform Delta drm-intel-nightly Series Applied PNV 276/276 276/276 ILK 301/301 301/301 SNB 316/316 316/316 IVB -1 328/328 327/328 BYT 285/285 285/285 HSW 394/394 394/394 BDW 321/321 321/321 -Detailed- Platform Testdrm-intel-nightly Series Applied IVB igt@gem_pwrite_pread@uncached-copy-performance DMESG_WARN(3)PASS(8) DMESG_WARN(1)PASS(1) (dmesg patch applied)drm:i915_hangcheck_elapsed[i915]]*ERROR*Hangcheck_timer_elapsed...blitter_ring_idle@Hangcheck timer elapsed... blitter ring idle Note: You need to pay more attention to line start with '*' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 13/14] drm/i915: Limit CHV max cdclk
On Wed, Apr 15, 2015 at 04:07:23PM +0300, Mika Kahola wrote:
Limit CHV maximum cdclk to 320MHz.
Signed-off-by: Mika Kahola mika.kah...@intel.com
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 09f3518..d79421a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5239,7 +5239,7 @@ static void intel_update_max_cdclk(struct drm_device
*dev)
else
dev_priv-max_cdclk_freq = 54;
} else if (IS_VALLEYVIEW(dev)) {
- dev_priv-max_cdclk_freq = 40;
+ dev_priv-max_cdclk_freq = IS_CHERRYVIEW(dev) ? 32 : 40;
} else {
/* otherwise assume cdclk is fixed */
dev_priv-max_cdclk_freq = dev_priv-cdclk_freq;
--
1.9.1
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Intel OTC
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Re: [Intel-gfx] [PATCH 02/12] drm/i915: Update intel_dp_check_link_status() for Displayport compliance testing
2015-04-15 16:28 GMT-03:00 Todd Previte tprev...@gmail.com:
Move the DPCD read to the top and check for an interrupt from the sink to
catch
Displayport automated testing requests necessary to support Displayport
compliance testing. The checks for active connectors and link status are moved
below the check for the interrupt.
The main reason for doing this is to make sure that a test request isn't
missed.
Checking for the status of the encoder/crtc isn't necessary for some test
cases
(AUX channel tests are one example) and without moving the check for the
interrupt, these tests may not execute if one of those checks fails.
Additionally, if reading the DPCD fails, regardless of whether or not testing
is
happening, there's no way to train the link since configurations and status
can't be read, nor can link training parameters be written.
V1:
- This is the second part of the single-patch split previously
mentioned.
V2:
- Remerge the two split patches into one and update the commit message
accordingly.
- Replace the SW connected status check with a HW HPD pin status check
- Adds a new function that examines the status of the HPD pin to
determine if a sink device is connected
V3:
- CLean up of the patch merge from previous split
- Updated the commit message
Signed-off-by: Todd Previte tprev...@gmail.com
Reviewed-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 33 +++--
1 file changed, 15 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 263eff3..9c38986 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4119,24 +4119,8 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
WARN_ON(!drm_modeset_is_locked(dev-mode_config.connection_mutex));
- if (!intel_encoder-connectors_active)
- return;
-
- if (WARN_ON(!intel_encoder-base.crtc))
- return;
-
- if (!to_intel_crtc(intel_encoder-base.crtc)-active)
- return;
-
- /* Try to read receiver status if the link appears to be up */
- if (!intel_dp_get_link_status(intel_dp, link_status)) {
- return;
- }
-
- /* Now read the DPCD to see if it's actually running */
- if (!intel_dp_get_dpcd(intel_dp)) {
+ if (!intel_dp_get_dpcd(intel_dp))
return;
- }
/* Try to read the source of the interrupt */
if (intel_dp-dpcd[DP_DPCD_REV] = 0x11
@@ -4145,13 +4129,26 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
drm_dp_dpcd_writeb(intel_dp-aux,
DP_DEVICE_SERVICE_IRQ_VECTOR,
sink_irq_vector);
-
if (sink_irq_vector DP_AUTOMATED_TEST_REQUEST)
intel_dp_handle_test_request(intel_dp);
if (sink_irq_vector (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
DRM_DEBUG_DRIVER(CP or sink specific irq
unhandled\n);
}
+ if (!intel_encoder-connectors_active)
+ return;
+
+ if (WARN_ON(!intel_encoder-base.crtc))
+ return;
+
+ if (!to_intel_crtc(intel_encoder-base.crtc)-active)
+ return;
+
+ /* Try to read receiver status if the link appears to be up */
+ if (!intel_dp_get_link_status(intel_dp, link_status)) {
+ return;
+ }
+
if (!drm_dp_channel_eq_ok(link_status, intel_dp-lane_count)) {
DRM_DEBUG_KMS(%s: channel EQ not ok, retraining\n,
intel_encoder-base.name);
--
1.9.1
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[Intel-gfx] [PATCH] drm/i915: Add psr_ready on pipe_config
Let's know beforehand if PSR is ready and will be enabled so we can
prevent DRRS to get enabled.
WARN_ON(!drm_modeset_is_locked(crtc-mutex)) on intel_psr_ready()
has been removed on v3. We don't dereferrence crtc here anymore so
we don't need this check. All configs are now checked from received
pipe config.
v2: Removing is_edp_psr func that is not used after this patch.
Rename match_conditions and document it since it is now external.
Moving to a propper place as pointed out by Sivakumar.
Use a better name as pointed out by Ram.
v3: Don't dereferrence drm_encoder-crtc and intel_crtc-config on psr_ready
check. Fix a opps caused with previous versions.
v4: Mention and explain on commit message the crtc-mutex check removal that
happened on v3.
Cc: Sivakumar Thulasimani sivakumar.thulasim...@intel.com
Cc: Ramalingam C ramalinga...@intel.com
Cc: Chris Wilson ch...@chris-wilson.co.uk
Cc: Daniel Vetter dan...@ffwll.ch
Reviewed-by: Ramalingam C ramalinga...@intel.com (v2)
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 1 +
drivers/gpu/drm/i915/intel_dp.c | 2 ++
drivers/gpu/drm/i915/intel_drv.h | 3 ++
drivers/gpu/drm/i915/intel_psr.c | 57
4 files changed, 38 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 75afa6e..50f2db7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10895,6 +10895,7 @@ static void intel_dump_pipe_config(struct intel_crtc
*crtc,
pipe_config-pch_pfit.pos,
pipe_config-pch_pfit.size,
pipe_config-pch_pfit.enabled ? enabled : disabled);
+ DRM_DEBUG_KMS(psr ready: %i\n, pipe_config-psr_ready);
DRM_DEBUG_KMS(ips: %i\n, pipe_config-ips_enabled);
DRM_DEBUG_KMS(double wide: %i\n, pipe_config-double_wide);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 14cdd00..94bbdf4 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1394,6 +1394,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
*/
min_lane_count = max_lane_count;
min_clock = max_clock;
+
+ pipe_config-psr_ready = intel_psr_ready(intel_dp, pipe_config);
}
for (; bpp = 6*3; bpp -= 2*3) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 082be71..9895772 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -448,6 +448,7 @@ struct intel_crtc_state {
int fdi_lanes;
struct intel_link_m_n fdi_m_n;
+ bool psr_ready;
bool ips_enabled;
bool double_wide;
@@ -1287,6 +1288,8 @@ void intel_backlight_unregister(struct drm_device *dev);
/* intel_psr.c */
+bool intel_psr_ready(struct intel_dp *intel_dp,
+struct intel_crtc_state *pipe_config);
void intel_psr_enable(struct intel_dp *intel_dp);
void intel_psr_disable(struct intel_dp *intel_dp);
void intel_psr_invalidate(struct drm_device *dev,
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 5ee0fa5..61d582b 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -56,11 +56,6 @@
#include intel_drv.h
#include i915_drv.h
-static bool is_edp_psr(struct intel_dp *intel_dp)
-{
- return intel_dp-psr_dpcd[0] DP_PSR_IS_SUPPORTED;
-}
-
static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe)
{
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -282,19 +277,32 @@ static void hsw_psr_enable_source(struct intel_dp
*intel_dp)
EDP_SU_TRACK_ENABLE | EDP_PSR2_TP2_TIME_100);
}
-static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
+/**
+ * intel_psr_ready - PSR ready
+ * @intel_dp: Intel DP
+ * @pipe_config: Pipe Config
+ *
+ * This function Checks if PSR is supported by Hardware/Source and
+ * Panel/Sink and if all conditions to be enabled are fulfilled.
+ *
+ * It is used to know beforehand if PSR is going to be enabled.
+ *
+ * Returns:
+ * True when PSR is ready to be enabled, false otherwise.
+ */
+bool intel_psr_ready(struct intel_dp *intel_dp,
+struct intel_crtc_state *pipe_config)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_device *dev = dig_port-base.base.dev;
struct drm_i915_private *dev_priv = dev-dev_private;
- struct drm_crtc *crtc = dig_port-base.base.crtc;
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- lockdep_assert_held(dev_priv-psr.lock);
- WARN_ON(!drm_modeset_is_locked(dev-mode_config.connection_mutex));
- WARN_ON(!drm_modeset_is_locked(crtc-mutex));
+ if (!HAS_PSR(dev)) {
+
[Intel-gfx] [PATCH 02/12] drm/i915: Update intel_dp_check_link_status() for Displayport compliance testing
Move the DPCD read to the top and check for an interrupt from the sink to catch
Displayport automated testing requests necessary to support Displayport
compliance testing. The checks for active connectors and link status are moved
below the check for the interrupt.
The main reason for doing this is to make sure that a test request isn't missed.
Checking for the status of the encoder/crtc isn't necessary for some test cases
(AUX channel tests are one example) and without moving the check for the
interrupt, these tests may not execute if one of those checks fails.
Additionally, if reading the DPCD fails, regardless of whether or not testing is
happening, there's no way to train the link since configurations and status
can't be read, nor can link training parameters be written.
V1:
- This is the second part of the single-patch split previously
mentioned.
V2:
- Remerge the two split patches into one and update the commit message
accordingly.
- Replace the SW connected status check with a HW HPD pin status check
- Adds a new function that examines the status of the HPD pin to
determine if a sink device is connected
V3:
- CLean up of the patch merge from previous split
- Updated the commit message
Signed-off-by: Todd Previte tprev...@gmail.com
---
drivers/gpu/drm/i915/intel_dp.c | 33 +++--
1 file changed, 15 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 263eff3..9c38986 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4119,24 +4119,8 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
WARN_ON(!drm_modeset_is_locked(dev-mode_config.connection_mutex));
- if (!intel_encoder-connectors_active)
- return;
-
- if (WARN_ON(!intel_encoder-base.crtc))
- return;
-
- if (!to_intel_crtc(intel_encoder-base.crtc)-active)
- return;
-
- /* Try to read receiver status if the link appears to be up */
- if (!intel_dp_get_link_status(intel_dp, link_status)) {
- return;
- }
-
- /* Now read the DPCD to see if it's actually running */
- if (!intel_dp_get_dpcd(intel_dp)) {
+ if (!intel_dp_get_dpcd(intel_dp))
return;
- }
/* Try to read the source of the interrupt */
if (intel_dp-dpcd[DP_DPCD_REV] = 0x11
@@ -4145,13 +4129,26 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
drm_dp_dpcd_writeb(intel_dp-aux,
DP_DEVICE_SERVICE_IRQ_VECTOR,
sink_irq_vector);
-
if (sink_irq_vector DP_AUTOMATED_TEST_REQUEST)
intel_dp_handle_test_request(intel_dp);
if (sink_irq_vector (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
DRM_DEBUG_DRIVER(CP or sink specific irq unhandled\n);
}
+ if (!intel_encoder-connectors_active)
+ return;
+
+ if (WARN_ON(!intel_encoder-base.crtc))
+ return;
+
+ if (!to_intel_crtc(intel_encoder-base.crtc)-active)
+ return;
+
+ /* Try to read receiver status if the link appears to be up */
+ if (!intel_dp_get_link_status(intel_dp, link_status)) {
+ return;
+ }
+
if (!drm_dp_channel_eq_ok(link_status, intel_dp-lane_count)) {
DRM_DEBUG_KMS(%s: channel EQ not ok, retraining\n,
intel_encoder-base.name);
--
1.9.1
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Re: [Intel-gfx] [PATCH] drm/vblank: Fixup and document timestamp update/read barriers
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 6195 -Summary- Platform Delta drm-intel-nightly Series Applied PNV 276/276 276/276 ILK -1 302/302 301/302 SNB 318/318 318/318 IVB 341/341 341/341 BYT 287/287 287/287 HSW 395/395 395/395 BDW 318/318 318/318 -Detailed- Platform Testdrm-intel-nightly Series Applied *ILK igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible PASS(2) DMESG_WARN(1)PASS(1) (dmesg patch applied)drm:i915_hangcheck_elapsed[i915]]*ERROR*Hangcheck_timer_elapsed...bsd_ring_idle@Hangcheck timer elapsed... bsd ring idle Note: You need to pay more attention to line start with '*' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/skl: Add back HDMI translation table
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 6190 -Summary- Platform Delta drm-intel-nightly Series Applied PNV -3 276/276 273/276 ILK -1 301/301 300/301 SNB 316/316 316/316 IVB -1 328/328 327/328 BYT 285/285 285/285 HSW 394/394 394/394 BDW 321/321 321/321 -Detailed- Platform Testdrm-intel-nightly Series Applied *PNV igt@gem_userptr_blits@coherency-sync CRASH(2)PASS(5) FAIL(1)PASS(1) PNV igt@gem_userptr_blits@coherency-unsync CRASH(2)PASS(6) CRASH(1)PASS(1) *PNV igt@gen3_render_tiledy_blits FAIL(4)PASS(8) CRASH(1)PASS(1) *ILK igt@gem_unfence_active_buffers PASS(2) DMESG_WARN(1)PASS(1) (dmesg patch applied)drm:i915_hangcheck_elapsed[i915]]*ERROR*Hangcheck_timer_elapsed...bsd_ring_idle@Hangcheck timer elapsed... bsd ring idle IVB igt@gem_pwrite_pread@uncached-copy-performance DMESG_WARN(3)PASS(8) DMESG_WARN(2) (dmesg patch applied)drm:i915_hangcheck_elapsed[i915]]*ERROR*Hangcheck_timer_elapsed...blitter_ring_idle@Hangcheck timer elapsed... blitter ring idle Note: You need to pay more attention to line start with '*' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/skl: Add back HDMI translation table
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 6190 -Summary- Platform Delta drm-intel-nightly Series Applied PNV -3 276/276 273/276 ILK -1 301/301 300/301 SNB 316/316 316/316 IVB -1 328/328 327/328 BYT 285/285 285/285 HSW 394/394 394/394 BDW 321/321 321/321 -Detailed- Platform Testdrm-intel-nightly Series Applied *PNV igt@gem_userptr_blits@coherency-sync CRASH(2)PASS(5) FAIL(1)PASS(1) PNV igt@gem_userptr_blits@coherency-unsync CRASH(2)PASS(6) CRASH(1)PASS(1) *PNV igt@gen3_render_tiledy_blits FAIL(4)PASS(8) CRASH(1)PASS(1) *ILK igt@gem_unfence_active_buffers PASS(2) DMESG_WARN(1)PASS(1) (dmesg patch applied)drm:i915_hangcheck_elapsed[i915]]*ERROR*Hangcheck_timer_elapsed...bsd_ring_idle@Hangcheck timer elapsed... bsd ring idle IVB igt@gem_pwrite_pread@uncached-copy-performance DMESG_WARN(3)PASS(8) DMESG_WARN(2) (dmesg patch applied)drm:i915_hangcheck_elapsed[i915]]*ERROR*Hangcheck_timer_elapsed...blitter_ring_idle@Hangcheck timer elapsed... blitter ring idle Note: You need to pay more attention to line start with '*' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 29/49] drm/i915: Rename vlv_cdclk_freq to cdclk_freq
On Tue, Mar 17, 2015 at 11:39:55AM +0200, Imre Deak wrote:
From: Vandana Kannan vandana.kan...@intel.com
Rename vlv_cdclk_freq to cdclk_freq so that it can be used for all
platforms as required. Needed by the next patch.
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Signed-off-by: A.Sunil Kamath sunil.kam...@intel.com
Signed-off-by: Imre Deak imre.d...@intel.com
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_display.c | 18 ++
2 files changed, 11 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 52e5f18..1b2a294 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1659,7 +1659,7 @@ struct drm_i915_private {
int num_fence_regs; /* 8 on pre-965, 16 otherwise */
unsigned int fsb_freq, mem_freq, is_ddr3;
- unsigned int vlv_cdclk_freq;
+ unsigned int cdclk_freq;
unsigned int hpll_freq;
/**
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index e54e948..b91862e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4879,16 +4879,16 @@ static void vlv_update_cdclk(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
- dev_priv-vlv_cdclk_freq =
dev_priv-display.get_display_clock_speed(dev);
+ dev_priv-cdclk_freq = dev_priv-display.get_display_clock_speed(dev);
DRM_DEBUG_DRIVER(Current CD clock rate: %d kHz\n,
- dev_priv-vlv_cdclk_freq);
+ dev_priv-cdclk_freq);
/*
* Program the gmbus_freq based on the cdclk frequency.
* BSpec erroneously claims we should aim for 4MHz, but
* in fact 1MHz is the correct frequency.
*/
- I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv-vlv_cdclk_freq, 1000));
+ I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv-cdclk_freq, 1000));
}
/* Adjust CDclk dividers to allow high res or save power if possible */
@@ -4897,7 +4897,8 @@ static void valleyview_set_cdclk(struct drm_device
*dev, int cdclk)
struct drm_i915_private *dev_priv = dev-dev_private;
u32 val, cmd;
- WARN_ON(dev_priv-display.get_display_clock_speed(dev) !=
dev_priv-vlv_cdclk_freq);
+ WARN_ON(dev_priv-display.get_display_clock_speed(dev)
+ != dev_priv-cdclk_freq);
if (cdclk = 32) /* jump to highest voltage for 400MHz too */
cmd = 2;
@@ -4961,7 +4962,8 @@ static void cherryview_set_cdclk(struct drm_device
*dev, int cdclk)
struct drm_i915_private *dev_priv = dev-dev_private;
u32 val, cmd;
- WARN_ON(dev_priv-display.get_display_clock_speed(dev) !=
dev_priv-vlv_cdclk_freq);
+ WARN_ON(dev_priv-display.get_display_clock_speed(dev)
+ != dev_priv-cdclk_freq);
switch (cdclk) {
case 33:
@@ -5050,7 +5052,7 @@ static void valleyview_modeset_global_pipes(struct
drm_device *dev,
int max_pixclk = intel_mode_max_pixclk(dev_priv);
if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
- dev_priv-vlv_cdclk_freq)
+ dev_priv-cdclk_freq)
return;
/* disable/enable all currently active pipes while we change cdclk */
@@ -5068,7 +5070,7 @@ static void vlv_program_pfi_credits(struct
drm_i915_private *dev_priv)
else
default_credits = PFI_CREDIT(8);
- if (DIV_ROUND_CLOSEST(dev_priv-vlv_cdclk_freq, 1000) =
dev_priv-rps.cz_freq) {
+ if (DIV_ROUND_CLOSEST(dev_priv-cdclk_freq, 1000) =
dev_priv-rps.cz_freq) {
/* CHV suggested value is 31 or 63 */
if (IS_CHERRYVIEW(dev_priv))
credits = PFI_CREDIT_31;
@@ -5101,7 +5103,7 @@ static void valleyview_modeset_global_resources(struct
drm_device *dev)
int max_pixclk = intel_mode_max_pixclk(dev_priv);
int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
- if (req_cdclk != dev_priv-vlv_cdclk_freq) {
+ if (req_cdclk != dev_priv-cdclk_freq) {
/*
* FIXME: We can end up here with all power domains off, yet
* with a CDCLK frequency other than the minimum. To account
--
2.1.0
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--
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH 14/14] drm/i915: Modeset global_pipes() update
On Wed, Apr 15, 2015 at 04:07:24PM +0300, Mika Kahola wrote:
Combined Valleyview, Haswell and Broadwell '*_modeset_global_pipes()'
into one function 'intel_modeset_global_pipes()'
v2:
- we don't modify 'disable_pipes', so passing this as a pointer
is removed (based on Ville's comment)
- introduced a new function 'intel_calc_cdclk()' that combines
routines from 'valleyview_calc_cdclk()' and 'haswell_calc_cdclk()'
v3:
- Let's take a step back and not remove the routines 'valleyview_calc_cdclk()'
and 'haswell_calc_cdclk()' from newly introduced routine
'intel_calc_cdclk()' (based on Ville's comment)
v4:
- Rebased to the latest
Signed-off-by: Mika Kahola mika.kah...@intel.com
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 70
+---
1 file changed, 32 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index d79421a..f199faa 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5433,28 +5433,6 @@ static int intel_mode_max_pixclk(struct
drm_atomic_state *state)
return max_pixclk;
}
-static int valleyview_modeset_global_pipes(struct drm_atomic_state *state,
- unsigned *prepare_pipes)
-{
- struct drm_i915_private *dev_priv = to_i915(state-dev);
- struct intel_crtc *intel_crtc;
- int max_pixclk = intel_mode_max_pixclk(state);
-
- if (max_pixclk 0)
- return max_pixclk;
-
- if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
- dev_priv-cdclk_freq)
- return 0;
-
- /* disable/enable all currently active pipes while we change cdclk */
- for_each_intel_crtc(state-dev, intel_crtc)
- if (intel_crtc-base.state-enable)
- *prepare_pipes |= (1 intel_crtc-pipe);
-
- return 0;
-}
-
static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
{
unsigned int credits, default_credits;
@@ -9265,21 +9243,47 @@ static void broadwell_set_cdclk(struct drm_device
*dev, int cdclk)
cdclk, dev_priv-cdclk_freq);
}
-static void haswell_modeset_global_pipes(struct drm_atomic_state *state,
- unsigned *prepare_pipes)
+static int intel_calc_cdclk(struct drm_device *dev, int max_pixclk)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ int cdclk = 20;
+
+ if (IS_VALLEYVIEW(dev))
+ cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
+ else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+ cdclk = haswell_calc_cdclk(dev_priv, max_pixclk);
+
+ return cdclk;
+}
+
+static void intel_modeset_global_pipes(struct drm_atomic_state *state,
+ unsigned *prepare_pipes,
+ unsigned disable_pipes)
{
struct drm_device *dev = state-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
struct intel_crtc *crtc;
- int max_pixel_rate = ilk_max_pixel_rate(dev_priv);
+ int max_pixclk;
- if (haswell_calc_cdclk(dev_priv, max_pixel_rate) ==
dev_priv-cdclk_freq)
+ /* this modeset is valid only for VLV, HSW, and BDW */
+ if (!IS_VALLEYVIEW(dev) !IS_HASWELL(dev) !IS_BROADWELL(dev))
+ return;
+
+ if (IS_VALLEYVIEW(dev))
+ max_pixclk = intel_mode_max_pixclk(state);
+ else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+ max_pixclk = ilk_max_pixel_rate(dev_priv);
+
+ if (intel_calc_cdclk(dev, max_pixclk) == dev_priv-cdclk_freq)
return;
/* disable/enable all currently active pipes while we change cdclk */
for_each_intel_crtc(dev, crtc)
- if (crtc-base.enabled)
+ if (crtc-base.state-enable)
*prepare_pipes |= 1 crtc-pipe;
+
+ /* may have added more to prepare_pipes than we should */
+ *prepare_pipes = ~disable_pipes;
}
static void haswell_modeset_global_resources(struct drm_atomic_state *state)
@@ -12453,17 +12457,7 @@ static int __intel_set_mode(struct drm_crtc *crtc,
* mode set on this crtc. For other crtcs we need to use the
* adjusted_mode bits in the crtc directly.
*/
- if (IS_VALLEYVIEW(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
- if (IS_VALLEYVIEW(dev))
- valleyview_modeset_global_pipes(state, prepare_pipes);
- else
- haswell_modeset_global_pipes(state, prepare_pipes);
- if (ret)
- goto done;
-
- /* may have added more to prepare_pipes than we should */
- prepare_pipes = ~disable_pipes;
- }
+ intel_modeset_global_pipes(state, prepare_pipes, disable_pipes);
ret
[Intel-gfx] [PATCH 03/12] drm/i915: Add EDID read in intel_dp_check_link_status() for Link CTS 4.2.2.1
Adds in an EDID read after the DPCD read to accommodate test 4.2.2.1 in the
Displayport Link CTS Core 1.2 rev1.1. This test requires an EDID read for
all HPD plug events. To reduce the amount of code, this EDID read is also
used for Link CTS tests 4.2.2.3, 4.2.2.4, 4.2.2.5 and 4.2.2.6. Actual
support for these tests is implemented in later patches in this series.
V2:
- Fixed compilation error introduced during rework
V3:
- Plugged a memory leak where the EDID data wasn't being freed
after allocation in this function
V4:
- Fixed whitespace problems
- Cleaned up formatting
V5:
- Added propagation of the long_hpd flag from the hot_pulse function
V6:
- Versioning, accommodating changes from previous patch
Signed-off-by: Todd Previte tprev...@gmail.com
---
drivers/gpu/drm/i915/intel_dp.c | 19 +--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 9c38986..a875b44 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4110,10 +4110,13 @@ go_again:
* 4. Check link status on receipt of hot-plug interrupt
*/
static void
-intel_dp_check_link_status(struct intel_dp *intel_dp)
+intel_dp_check_link_status(struct intel_dp *intel_dp, bool long_hpd)
{
struct drm_device *dev = intel_dp_to_dev(intel_dp);
struct intel_encoder *intel_encoder = dp_to_dig_port(intel_dp)-base;
+ struct drm_connector *connector = intel_dp-attached_connector-base;
+ struct i2c_adapter *adapter = intel_dp-aux.ddc;
+ struct edid *edid_read = NULL;
u8 sink_irq_vector;
u8 link_status[DP_LINK_STATUS_SIZE];
@@ -4122,6 +4125,18 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
if (!intel_dp_get_dpcd(intel_dp))
return;
+ /* Displayport Link CTS Core 1.2 rev1.1 EDID testing
+* 4.2.2.1 - EDID read required for all HPD events
+*/
+ if (long_hpd) {
+ edid_read = drm_get_edid(connector, adapter);
+ if (!edid_read) {
+ DRM_DEBUG_DRIVER(Invalid EDID detected\n);
+ } else {
+ kfree(edid_read);
+ }
+ }
+
/* Try to read the source of the interrupt */
if (intel_dp-dpcd[DP_DPCD_REV] = 0x11
intel_dp_get_sink_irq(intel_dp, sink_irq_vector)) {
@@ -4776,7 +4791,7 @@ intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port, bool long_hpd)
* but for short hpds we should check it now
*/
drm_modeset_lock(dev-mode_config.connection_mutex,
NULL);
- intel_dp_check_link_status(intel_dp);
+ intel_dp_check_link_status(intel_dp, long_hpd);
drm_modeset_unlock(dev-mode_config.connection_mutex);
}
}
--
1.9.1
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[Intel-gfx] [PATCH 3/9] drm/i915: vlv: fix save/restore of GFX_MAX_REQ_COUNT reg
From: Imre Deak imre.d...@intel.com Due this typo we don't save/restore the GFX_MAX_REQ_COUNT register across suspend/resume, so fix this. This was introduced in commit ddeea5b0c36f3665446518c609be91f9336ef674 Author: Imre Deak imre.d...@intel.com Date: Mon May 5 15:19:56 2014 +0300 drm/i915: vlv: add runtime PM support I noticed this only by reading the code. To my knowledge it shouldn't cause any real problems at the moment, since the power well backing this register remains on across a runtime s/r. This may change once system-wide s0ix functionality is enabled in the kernel. v2: - resend after a missing git add -u :/ Signed-off-by: Imre Deak imre.d...@intel.com Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_drv.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index c3fdbb0..e179da6 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1051,7 +1051,7 @@ static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv) s-lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4); s-media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT); - s-gfx_max_req_count= I915_READ(GEN7_MEDIA_MAX_REQ_COUNT); + s-gfx_max_req_count= I915_READ(GEN7_GFX_MAX_REQ_COUNT); s-render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7); s-ecochk = I915_READ(GAM_ECOCHK); @@ -1133,7 +1133,7 @@ static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv) I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s-lra_limits[i]); I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s-media_max_req_count); - I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s-gfx_max_req_count); + I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s-gfx_max_req_count); I915_WRITE(RENDER_HWS_PGA_GEN7, s-render_hwsp); I915_WRITE(GAM_ECOCHK, s-ecochk); -- 2.1.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 9/9] drm/i915: Attach a PSR property on eDP
Let userspace know the status of Panel Self-Refresh by virtue of a
property on the appropriate connector.
v2: Only attach the property if the driver is capable of PSR.
v3: Add docbook courtesy of Damien.
v4: Mark the initial value as 'unsupported' - it will be determined
correctly when we later read the DCPD from the panel.
v5: Done by Rodrigo:
- Add disabled state to match all cases
- Attach it anyway to eDP since it is started as unsupported
- Change prop name to PSR
- Add enum to make states more clear
- Rebased on intel_psr.c changing func name and fixing states
v6: Done by Rodrigo:
- Revert name to Panel Self-Refresh
- Only report Enable/Disable since Active/Exit change so rapidily
triggering many uevents as Chris pointed out.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc: Damien Lespiau damien.lesp...@intel.com
Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com (v4)
Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk (v6)
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
Documentation/DocBook/drm.tmpl | 10 -
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_dp.c | 1 +
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_psr.c | 47
5 files changed, 59 insertions(+), 1 deletion(-)
diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl
index f4976cd..bda3948 100644
--- a/Documentation/DocBook/drm.tmpl
+++ b/Documentation/DocBook/drm.tmpl
@@ -2834,7 +2834,7 @@ void intel_crt_init(struct drm_device *dev)
td valign=top TBD/td
/tr
tr
- td rowspan=21 valign=top i915/td
+ td rowspan=22 valign=top i915/td
td rowspan=2 valign=top Generic/td
td valign=top Broadcast RGB/td
td valign=top ENUM/td
@@ -2986,6 +2986,14 @@ void intel_crt_init(struct drm_device *dev)
td valign=top TBD/td
/tr
tr
+ td valign=top eDP/td
+ td valign=top “Panel Self-Refresh”/td
+ td valign=top ENUM | IMMUTABLE/td
+ td valign=top { Unsupported, Idle, Active }/td
+ td valign=top Connector/td
+ td valign=top Whether the eDP panel supports using self-refresh,
which is a power saving mode for static displays as the panel is able to read
from its own buffer rather than require the host to send the same frame on
every vertical refresh, and whether it is idle or active/td
+ /tr
+ tr
td rowspan=2 valign=top CDV gma-500/td
td rowspan=2 valign=top Generic/td
td valign=top Broadcast RGB/td
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1a5e976..48e35a8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -884,6 +884,7 @@ struct i915_psr {
bool link_standby;
bool psr2_support;
bool aux_frame_sync;
+ struct drm_property *property;
};
enum intel_pch {
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 1b87969..325805d 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4788,6 +4788,7 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct
drm_connector *connect
intel_dp-color_range_auto = true;
if (is_edp(intel_dp)) {
+ intel_attach_psr_property(connector);
drm_mode_create_scaling_mode_property(connector-dev);
drm_object_attach_property(
connector-base,
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 6e34978..f6297d4 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1206,6 +1206,7 @@ void intel_backlight_unregister(struct drm_device *dev);
/* intel_psr.c */
+void intel_attach_psr_property(struct drm_connector *connector);
void intel_psr_enable(struct intel_dp *intel_dp);
void intel_psr_disable(struct intel_dp *intel_dp);
void intel_psr_invalidate(struct drm_device *dev,
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 27608ce..fb9ff42 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -56,6 +56,50 @@
#include intel_drv.h
#include i915_drv.h
+enum psr_state {
+ PSR_UNSUPPORTED = -1,
+ PSR_DISABLED,
+ PSR_ENABLED,
+};
+
+static const struct drm_prop_enum_list psr_names[] = {
+ { PSR_UNSUPPORTED, Unsupported },
+ { PSR_DISABLED, Disabled },
+ { PSR_ENABLED, Enabled },
+};
+
+void intel_attach_psr_property(struct drm_connector *connector)
+{
+ struct drm_device *dev = connector-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct drm_property *prop;
+
+ prop = dev_priv-psr.property;
+ if (prop == NULL) {
+ prop = drm_property_create_enum(dev,
+
[Intel-gfx] [PATCH 0/9] drm-intel-collector - update
This is another drm-intel-collector updated notice: http://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=drm-intel-collector Here goes the update list in order for better reviewers assignment: Patch drm/i915: Remove pinned check from madvise_ioctl - Reviewer: Patch drm/i915/vlv: check port in infoframe_enabled v2 - Reviewer: Patch drm/i915: vlv: fix save/restore of GFX_MAX_REQ_COUNT reg - Reviewer: Patch drm/i915: Remove unused head member in request struct - Reviewer: Patch drm/i915: Remove unneeded check on execlist ringbuf alloc - Reviewer: Patch drm/i915: Support for higher DSI clk - Reviewer: Patch drm/i915: Changes required to enable DSI Video Mode on CHT - Reviewer: Patch drm/i915: Remove duplicated intel_fbc_update calls. - Reviewer: Patch drm/i915: Attach a PSR property on eDP - Reviewer: 2 rounds here: Feb 27 - Mar 13 Mar 13 - Mar 27 Thanks, Rodrigo. Chris Wilson (1): drm/i915: Remove pinned check from madvise_ioctl Gaurav K Singh (2): drm/i915: Support for higher DSI clk drm/i915: Changes required to enable DSI Video Mode on CHT Imre Deak (1): drm/i915: vlv: fix save/restore of GFX_MAX_REQ_COUNT reg Jesse Barnes (1): drm/i915/vlv: check port in infoframe_enabled v2 Mika Kuoppala (2): drm/i915: Remove unused head member in request struct drm/i915: Remove unneeded check on execlist ringbuf alloc Rodrigo Vivi (2): drm/i915: Remove duplicated intel_fbc_update calls. drm/i915: Attach a PSR property on eDP Documentation/DocBook/drm.tmpl | 10 +++- drivers/gpu/drm/i915/i915_drv.c | 4 +-- drivers/gpu/drm/i915/i915_drv.h | 4 +-- drivers/gpu/drm/i915/i915_gem.c | 9 --- drivers/gpu/drm/i915/intel_display.c | 12 - drivers/gpu/drm/i915/intel_dp.c | 1 + drivers/gpu/drm/i915/intel_drv.h | 2 +- drivers/gpu/drm/i915/intel_dsi_pll.c | 47 +++- drivers/gpu/drm/i915/intel_hdmi.c| 7 +- drivers/gpu/drm/i915/intel_lrc.c | 29 ++ drivers/gpu/drm/i915/intel_psr.c | 47 11 files changed, 115 insertions(+), 57 deletions(-) -- 2.1.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/9] drm/i915/vlv: check port in infoframe_enabled v2
From: Jesse Barnes jbar...@virtuousgeek.org Same as IBX and G4x, they all share the same genetic material. v2: we all need a bit more port in our lives Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/intel_hdmi.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 26222e6..0863f1e 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -324,10 +324,15 @@ static bool vlv_infoframe_enabled(struct drm_encoder *encoder) struct drm_device *dev = encoder-dev; struct drm_i915_private *dev_priv = dev-dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder-crtc); + struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); int reg = VLV_TVIDEO_DIP_CTL(intel_crtc-pipe); u32 val = I915_READ(reg); + u32 port = intel_dig_port-port; - return val VIDEO_DIP_ENABLE; + if (port == (val VIDEO_DIP_PORT_MASK)) + return val VIDEO_DIP_ENABLE; + + return false; } static void hsw_write_infoframe(struct drm_encoder *encoder, -- 2.1.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/9] drm/i915: Remove unneeded check on execlist ringbuf alloc
From: Mika Kuoppala mika.kuopp...@linux.intel.com
We just allocated the intel_ringbuffer with kzalloc. There
is no chance of the ringbuf-obj being other than NULL
so remove the redudant check.
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/intel_lrc.c | 29 +
1 file changed, 13 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 4373754..dcfd975 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1879,25 +1879,22 @@ int intel_lr_context_deferred_create(struct
intel_context *ctx,
ringbuf-last_retired_head = -1;
intel_ring_update_space(ringbuf);
- if (ringbuf-obj == NULL) {
- ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
+ ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
+ if (ret) {
+ DRM_DEBUG_DRIVER(
+ Failed to allocate ringbuffer obj %s: %d\n,
+ ring-name, ret);
+ goto error_free_rbuf;
+ }
+
+ if (is_global_default_ctx) {
+ ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
if (ret) {
- DRM_DEBUG_DRIVER(
- Failed to allocate ringbuffer obj %s: %d\n,
+ DRM_ERROR(
+ Failed to pin and map ringbuffer %s: %d\n,
ring-name, ret);
- goto error_free_rbuf;
+ goto error_destroy_rbuf;
}
-
- if (is_global_default_ctx) {
- ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
- if (ret) {
- DRM_ERROR(
- Failed to pin and map ringbuffer %s:
%d\n,
- ring-name, ret);
- goto error_destroy_rbuf;
- }
- }
-
}
ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf);
--
2.1.0
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[Intel-gfx] [PATCH 7/9] drm/i915: Changes required to enable DSI Video Mode on CHT
From: Gaurav K Singh gaurav.k.si...@intel.com
On CHT, changes are required for calculating the correct m,n p with
minimal error +/- for the required DSI clock, so that the correct dividor
ctrl values are written in cck regs for DSI. This patch has been tested
on CHT RVP with 1200 x 1920 panel.
Signed-off-by: Gaurav K Singh gaurav.k.si...@intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/intel_dsi_pll.c | 43 +++-
1 file changed, 33 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c
b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 471336d..5e44c9b 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -162,7 +162,8 @@ static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format,
int lane_count)
#endif
-static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp)
+static int dsi_calc_mnp(struct drm_i915_private *dev_priv,
+ u32 dsi_clk, struct dsi_mnp *dsi_mnp)
{
u32 m, n, p;
u32 ref_clk;
@@ -173,6 +174,10 @@ static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp
*dsi_mnp)
u32 calc_m;
u32 calc_p;
u32 m_seed;
+ u32 m_start;
+ u32 m_limit;
+ u32 n_limit;
+ u32 p_limit;
/* dsi_clk is expected in KHZ */
if (dsi_clk 30 || dsi_clk 115) {
@@ -180,18 +185,33 @@ static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp
*dsi_mnp)
return -ECHRNG;
}
- ref_clk = 25000;
+ if (IS_CHERRYVIEW(dev_priv-dev)) {
+ ref_clk = 10;
+ m_start = 70;
+ m_limit = 96;
+ n_limit = 4;
+ p_limit = 6;
+ } else if (IS_VALLEYVIEW(dev_priv-dev)) {
+ ref_clk = 25000;
+ m_start = 62;
+ m_limit = 92;
+ n_limit = 1;
+ p_limit = 6;
+ } else {
+ DRM_ERROR(Unsupported device\n);
+ return -ENODEV;
+ }
target_dsi_clk = dsi_clk;
error = 0x;
tmp_error = 0x;
calc_m = 0;
calc_p = 0;
- for (m = 62; m = 92; m++) {
- for (p = 2; p = 6; p++) {
+ for (m = m_start; m = m_limit; m++) {
+ for (p = 2; p = p_limit; p++) {
/* Find the optimal m and p divisors
with minimal error +/- the required clock */
- calc_dsi_clk = (m * ref_clk) / p;
+ calc_dsi_clk = (m * ref_clk) / (p * n_limit);
if (calc_dsi_clk == target_dsi_clk) {
calc_m = m;
calc_p = p;
@@ -212,11 +232,14 @@ static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp
*dsi_mnp)
}
m_seed = lfsr_converts[calc_m - 62];
- n = 1;
+ n = n_limit;
dsi_mnp-dsi_pll_ctrl = 1 (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2);
- dsi_mnp-dsi_pll_div = (n - 1) DSI_PLL_N1_DIV_SHIFT |
- m_seed DSI_PLL_M1_DIV_SHIFT;
-
+ if (IS_CHERRYVIEW(dev_priv-dev))
+ dsi_mnp-dsi_pll_div = (n/2) DSI_PLL_N1_DIV_SHIFT |
+ m_seed DSI_PLL_M1_DIV_SHIFT;
+ else
+ dsi_mnp-dsi_pll_div = (n - 1) DSI_PLL_N1_DIV_SHIFT |
+ m_seed DSI_PLL_M1_DIV_SHIFT;
return 0;
}
@@ -235,7 +258,7 @@ static void vlv_configure_dsi_pll(struct intel_encoder
*encoder)
dsi_clk = dsi_clk_from_pclk(intel_dsi-pclk, intel_dsi-pixel_format,
intel_dsi-lane_count);
- ret = dsi_calc_mnp(dsi_clk, dsi_mnp);
+ ret = dsi_calc_mnp(dev_priv, dsi_clk, dsi_mnp);
if (ret) {
DRM_DEBUG_KMS(dsi_calc_mnp failed\n);
return;
--
2.1.0
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[Intel-gfx] [PATCH 4/9] drm/i915: Remove unused head member in request struct
From: Mika Kuoppala mika.kuopp...@linux.intel.com
commit 939fd762083f988be271da8c96398178daf9baf0
Author: Mika Kuoppala mika.kuopp...@linux.intel.com
Date: Thu Jan 30 19:04:44 2014 +0200
drm/i915: Get rid of acthd based guilty batch search
Failed to cleanup properly as it made the head obsolete.
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 3 ---
drivers/gpu/drm/i915/i915_gem.c | 3 ---
2 files changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 822f259..1a5e976 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2050,9 +2050,6 @@ struct drm_i915_gem_request {
/** GEM sequence number associated with this request. */
uint32_t seqno;
- /** Position in the ringbuffer of the start of the request */
- u32 head;
-
/**
* Position in the ringbuffer of the start of the postfix.
* This is required to calculate the maximum available ringbuffer
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index de6717e..11dfd49 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2323,7 +2323,6 @@ int __i915_add_request(struct intel_engine_cs *ring,
struct drm_i915_private *dev_priv = ring-dev-dev_private;
struct drm_i915_gem_request *request;
struct intel_ringbuffer *ringbuf;
- u32 request_start;
int ret;
request = ring-outstanding_lazy_request;
@@ -2335,7 +2334,6 @@ int __i915_add_request(struct intel_engine_cs *ring,
} else
ringbuf = ring-buffer;
- request_start = intel_ring_get_tail(ringbuf);
/*
* Emit any outstanding flushes - execbuf can fail to emit the flush
* after having emitted the batchbuffer command. Hence we need to fix
@@ -2370,7 +2368,6 @@ int __i915_add_request(struct intel_engine_cs *ring,
return ret;
}
- request-head = request_start;
request-tail = intel_ring_get_tail(ringbuf);
/* Whilst this request exists, batch_obj will be on the
--
2.1.0
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[Intel-gfx] [PATCH 8/9] drm/i915: Remove duplicated intel_fbc_update calls.
With frontbuffer tracking taking care of fbc
we were duplicating fbc update call on these cases here.
Cc: Paulo Zanoni paulo.r.zan...@intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 12
drivers/gpu/drm/i915/intel_drv.h | 1 -
2 files changed, 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 7bfe2af..1de6fda 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4467,10 +4467,6 @@ static void intel_crtc_enable_planes(struct drm_crtc
*crtc)
hsw_enable_ips(intel_crtc);
- mutex_lock(dev-struct_mutex);
- intel_fbc_update(dev);
- mutex_unlock(dev-struct_mutex);
-
/*
* FIXME: Once we grow proper nuclear flip support out of this we need
* to compute the mask of flip planes precisely. For the time being
@@ -12620,8 +12616,6 @@ intel_check_primary_plane(struct drm_plane *plane,
intel_crtc-atomic.fb_bits |=
INTEL_FRONTBUFFER_PRIMARY(intel_crtc-pipe);
- intel_crtc-atomic.update_fbc = true;
-
if (intel_wm_need_update(plane, state-base))
intel_crtc-atomic.update_wm = true;
}
@@ -12741,12 +12735,6 @@ static void intel_finish_crtc_commit(struct drm_crtc
*crtc)
intel_frontbuffer_flip(dev, intel_crtc-atomic.fb_bits);
- if (intel_crtc-atomic.update_fbc) {
- mutex_lock(dev-struct_mutex);
- intel_fbc_update(dev);
- mutex_unlock(dev-struct_mutex);
- }
-
if (intel_crtc-atomic.post_enable_primary)
intel_post_enable_primary(crtc);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index efa53d5..6e34978 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -434,7 +434,6 @@ struct intel_crtc_atomic_commit {
/* Sleepable operations to perform after commit */
unsigned fb_bits;
bool wait_vblank;
- bool update_fbc;
bool post_enable_primary;
unsigned update_sprite_watermarks;
};
--
2.1.0
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