[Intel-gfx] [PATCH v2 2/3] drm/i915/bxt: Add WaEnablePooledEuFor2x6

[Arun Siluvery]

Pooled EU is enabled by default for BXT but for fused down 2x6 parts it is
advised to turn it off. But there is another HW issue in these parts (fused
down 2x6 parts) before C0 that requires Pooled EU to be enabled as a
workaround. In this case the pool configuration changes depending upon
which subslice is disabled. This doesn't affect if the device has all 3
subslices enabled.

Userspace need to know min no. of eus in a pool as it varies based on which
subslice is disabled, this is not yet exported because userspace support is
not available yet. Once the support is available this needs to be exported
using getparam ioctls.

Cc: Winiarski, Michal 
Cc: Zou, Nanhai 
Cc: Yang, Rong R 
Cc: Tim Gore 
Cc: Jeff McGee 
Signed-off-by: Arun Siluvery 
---
 drivers/gpu/drm/i915/i915_dma.c | 10 ++
 drivers/gpu/drm/i915/i915_drv.c |  2 +-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index a6c5d87..50aedfd 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -767,6 +767,16 @@ static void gen9_sseu_info_init(struct drm_device *dev)
 
if (IS_BROXTON(dev)) {
 #define IS_SS_DISABLED(_ss_disable, ss)(_ss_disable & (0x1 << ss))
+   /*
+* There is a HW issue in 2x6 fused down parts that requires
+* Pooled EU to be enabled as a WA. The pool configuration
+* changes depending upon which subslice is fused down. This
+* doesn't affect if the device has all 3 subslices enabled.
+*/
+   /* WaEnablePooledEuFor2x6:bxt */
+   info->has_pooled_eu = ((info->subslice_total == 3) ||
+  (info->subslice_total == 2 &&
+   INTEL_REVID(dev) < BXT_REVID_C0));
 
info->min_eu_in_pool = 0;
if (info->has_pooled_eu) {
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index de78a30..84593c1 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -357,7 +357,7 @@ static const struct intel_device_info intel_broxton_info = {
.has_ddi = 1,
.has_fpga_dbg = 1,
.has_fbc = 1,
-   .has_pooled_eu = 1,
+   .has_pooled_eu = 0,
GEN_DEFAULT_PIPEOFFSETS,
IVB_CURSOR_OFFSETS,
BDW_COLORS,
-- 
1.9.1

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[Intel-gfx] [PATCH v2 3/3] drm/i915/bxt: Add WaDisablePooledEuLoadBalancingFix

[Arun Siluvery]

This is a WA affecting pooled eu which is a bxt specific feature.

Cc: Winiarski, Michal 
Cc: Zou, Nanhai 
Cc: Yang, Rong R 
Cc: Jeff McGee 
Signed-off-by: Arun Siluvery 
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_ringbuffer.c | 6 ++
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1d97321e..5268aed 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6072,6 +6072,7 @@ enum skl_disp_power_wells {
 
 #define FF_SLICE_CS_CHICKEN2   _MMIO(0x20e4)
 #define  GEN9_TSG_BARRIER_ACK_DISABLE  (1<<8)
+#define  GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE  (1<<10)
 
 #define GEN9_CS_DEBUG_MODE1_MMIO(0x20ec)
 #define GEN8_CS_CHICKEN1   _MMIO(0x2580)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 8d35a39..a21eced 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1145,6 +1145,12 @@ static int bxt_init_workarounds(struct intel_engine_cs 
*engine)
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
  STALL_DOP_GATING_DISABLE);
 
+   /* WaDisablePooledEuLoadBalancingFix:bxt */
+   if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) {
+   WA_SET_BIT_MASKED(FF_SLICE_CS_CHICKEN2,
+ GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE);
+   }
+
/* WaDisableSbeCacheDispatchPortSharing:bxt */
if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) {
WA_SET_BIT_MASKED(
-- 
1.9.1

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[Intel-gfx] [PATCH v2 0/3] BXT Pooled EU kernel support and WA patches

[Arun Siluvery]

These patches enable Pooled EU support for BXT.
These patches were sent to the list before and as suggested in [1], code that 
exposes this feature to userspace is removed as support in userspace is 
currently being implemented by beignet. Other users of this feature are mesa, 
libva.

Some of the related WA patches are also included in this series.

[1] https://lists.freedesktop.org/archives/intel-gfx/2016-May/095890.html

Arun Siluvery (3):
  drm/i915:bxt: Enable Pooled EU support
  drm/i915/bxt: Add WaEnablePooledEuFor2x6
  drm/i915/bxt: Add WaDisablePooledEuLoadBalancingFix

 drivers/gpu/drm/i915/i915_debugfs.c  |  4 
 drivers/gpu/drm/i915/i915_dma.c  | 29 
 drivers/gpu/drm/i915/i915_drv.c  |  1 +
 drivers/gpu/drm/i915/i915_drv.h  |  6 +-
 drivers/gpu/drm/i915/i915_gem_render_state.c | 28 +++
 drivers/gpu/drm/i915/i915_reg.h  |  3 +++
 drivers/gpu/drm/i915/intel_ringbuffer.c  |  6 ++
 7 files changed, 76 insertions(+), 1 deletion(-)

-- 
1.9.1

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[Intel-gfx] [PATCH v2 1/3] drm/i915:bxt: Enable Pooled EU support

[Arun Siluvery]

This mode allows to assign EUs to pools which can process work collectively.
The command to enable this mode should be issued as part of context 
initialization.

The pooled mode is global, once enabled it has to stay the same across all
contexts until HW reset hence this is sent in auxiliary golden context batch.
Thanks to Mika for the preliminary review and comments.

v2: explain why this is enabled in golden context, use feature flag while
enabling the support (Chris)

v3: Include only kernel support as userspace support is not available yet.

User space clients need to know when the pooled EU feature is present
and enabled on the hardware so that they can adapt work submissions.
Create a new device info flag for this purpose.

Set has_pooled_eu to true in the Broxton static device info - Broxton
supports the feature in hardware and the driver will enable it by
default.

We need to add getparam ioctls to enable userspace to query availability of
this feature and to retrieve min. no of eus in a pool but we will expose
them once userspace support is available. Opensource users for this feature
are mesa, libva and beignet.

Beignet team is currently working on adding userspace support.

Reviewed-by: Chris Wilson  (v2)
Cc: Winiarski, Michal 
Cc: Zou, Nanhai 
Cc: Yang, Rong R 
Cc: Mika Kuoppala 
Cc: Chris Wilson 
Cc: Armin Reese 
Cc: Tim Gore 
Signed-off-by: Jeff McGee 
Signed-off-by: Arun Siluvery 
---
 drivers/gpu/drm/i915/i915_debugfs.c  |  4 
 drivers/gpu/drm/i915/i915_dma.c  | 19 +++
 drivers/gpu/drm/i915/i915_drv.c  |  1 +
 drivers/gpu/drm/i915/i915_drv.h  |  6 +-
 drivers/gpu/drm/i915/i915_gem_render_state.c | 28 
 drivers/gpu/drm/i915/i915_reg.h  |  2 ++
 6 files changed, 59 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index e606c6a..1577fad 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -5284,6 +5284,10 @@ static int i915_sseu_status(struct seq_file *m, void 
*unused)
   INTEL_INFO(dev)->eu_total);
seq_printf(m, "  Available EU Per Subslice: %u\n",
   INTEL_INFO(dev)->eu_per_subslice);
+   seq_printf(m, "  Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev)));
+   if (HAS_POOLED_EU(dev))
+   seq_printf(m, "  Min EU in pool: %u\n",
+  INTEL_INFO(dev)->min_eu_in_pool);
seq_printf(m, "  Has Slice Power Gating: %s\n",
   yesno(INTEL_INFO(dev)->has_slice_pg));
seq_printf(m, "  Has Subslice Power Gating: %s\n",
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 07edaed..a6c5d87 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -764,6 +764,22 @@ static void gen9_sseu_info_init(struct drm_device *dev)
   (info->slice_total > 1));
info->has_subslice_pg = (IS_BROXTON(dev) && (info->subslice_total > 1));
info->has_eu_pg = (info->eu_per_subslice > 2);
+
+   if (IS_BROXTON(dev)) {
+#define IS_SS_DISABLED(_ss_disable, ss)(_ss_disable & (0x1 << ss))
+
+   info->min_eu_in_pool = 0;
+   if (info->has_pooled_eu) {
+   if (IS_SS_DISABLED(ss_disable, 0) ||
+   IS_SS_DISABLED(ss_disable, 2))
+   info->min_eu_in_pool = 3;
+   else if (IS_SS_DISABLED(ss_disable, 1))
+   info->min_eu_in_pool = 6;
+   else
+   info->min_eu_in_pool = 9;
+   }
+#undef IS_SS_DISABLED
+   }
 }
 
 static void broadwell_sseu_info_init(struct drm_device *dev)
@@ -962,6 +978,9 @@ static void intel_device_info_runtime_init(struct 
drm_device *dev)
DRM_DEBUG_DRIVER("subslice per slice: %u\n", info->subslice_per_slice);
DRM_DEBUG_DRIVER("EU total: %u\n", info->eu_total);
DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->eu_per_subslice);
+   DRM_DEBUG_DRIVER("Has Pooled EU: %s\n", HAS_POOLED_EU(dev) ? "y" : "n");
+   if (HAS_POOLED_EU(dev))
+   DRM_DEBUG_DRIVER("Min EU in pool: %u\n", info->min_eu_in_pool);
DRM_DEBUG_DRIVER("has slice power gating: %s\n",
 info->has_slice_pg ? "y" : "n");
DRM_DEBUG_DRIVER("has subslice power gating: %s\n",
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 943d7b2..de78a30 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -357,6 +357,7 @@ static const struct 

[Intel-gfx] linux-next: build warning after merge of the drm-misc tree

[Stephen Rothwell]

Hi all,

After merging the drm-misc tree, today's linux-next build (x86_64
allmodconfig) produced this warning:

drivers/dma-buf/sync_file.c: In function 'sync_file_create':
drivers/dma-buf/sync_file.c:85:53: warning: format '%d' expects argument of 
type 'int', but argument 6 has type 'u64 {aka long long unsigned int}' 
[-Wformat=]
  snprintf(sync_file->name, sizeof(sync_file->name), "%s-%s%d-%d",
 ^

Introduced by commit

  76bf0db55439 ("dma-buf/fence: make fence context 64 bit v2")

-- 
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Re: [Intel-gfx] [PATCH 04/26] drm/rcar-du: Use for_each_*_in_state

[Laurent Pinchart]

Hi Daniel,

On Monday 30 May 2016 16:54:10 Daniel Vetter wrote:
> On Mon, May 30, 2016 at 11:58:27AM +0200, Maarten Lankhorst wrote:
> > Op 30-05-16 om 11:18 schreef Laurent Pinchart:
> >> Hi Daniel,
> >> 
> >> Thank you for the patch.
> >> 
> >> This looks good to me as the resulting code is mostly similar. However,
> >> the for_each_*_in_state macros end with an for_each_if() that tests if
> >> the object's state is NULL, which isn't present in this code. I'm
> >> wondering whether that was an oversight on my side possibly leading to a
> >> crash when dereferencing a NULL state, or an unneeded check in the
> >> macros. Can atomic_state->*_states[i] be NULL if atomic_state->*[i] is
> >> not NULL ?
> > 
> > Not in any normal case.
> 
> Yeah, the drm_atomic_get_*_state functions only ever fill in both of
> neither. If this gets out of sync it's a bug ;-)

Should the check be removed then ? Or replaced by a WARN_ON() ?

-- 
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Re: [Intel-gfx] [PATCH 01/20] drm/atomic: Fix remaining places where !funcs->best_encoder is valid

[Chris Wilson]

On Thu, Jun 02, 2016 at 11:57:02PM +0200, Daniel Vetter wrote:
> drm_encoder_find is an idr lookup. That should be plenty fast,
> especially for modeset code. Usually what's too expensive even for
> modeset code is linear list walks. But Chris just submitted patches to
> convert most of them into simple lookups.

For the idr_find, I'm tempted to replace the mutex with a rwlock. It
helps pathological cases, but in reality there are more crucial
locks around the hw that limit concurrency. ;-)
-Chris

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Re: [Intel-gfx] [PATCH 01/11] drm/i915: Add support for mapping an object page by page

[Chris Wilson]

On Tue, May 31, 2016 at 11:49:14AM +0530, ankitprasad.r.sha...@intel.com wrote:
> From: Chris Wilson 
> 
> Introduced a new vm specfic callback insert_page() to program a single pte in
> ggtt or ppgtt. This allows us to map a single page in to the mappable aperture
> space. This can be iterated over to access the whole object by using space as
> meagre as page size.
> 
> v2: Added low level rpm assertions to insert_page routines (Chris)
> 
> v3: Added POSTING_READ post register write (Tvrtko)
> 
> v4: Rebase (Ankit)
> 
> v5: Removed wmb() and FLUSH_CTL from insert_page, caller to take care
> of it (Chris)
> 
> v6: insert_page not working correctly without FLSH_CNTL write, added the
> write again.

Confirmed. Sorry, it took me a bit to get a test box ready for a bit of
digging.
-Chris

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Re: [Intel-gfx] [PATCH v3] drm: Store the plane's index

[Daniel Vetter]

On Fri, May 27, 2016 at 01:43:19PM -0700, Matt Roper wrote:
> On Fri, May 27, 2016 at 08:05:00PM +0100, Chris Wilson wrote:
> > Currently the plane's index is determined by walking the list of all
> > planes in the mode and finding the position of that plane in the list. A
> > linear walk, especially a linear walk within a linear walk as frequently
> > conceived by i915.ko [O(N^2)] quickly comes to dominate profiles.
> > 
> > The plane's index is constant for as long as no earlier planes are
> > removed from the list. For all drivers, planes are static, determined
> > at boot and then untouched until shutdown. In fact, there is no locking
> > provided to allow for dynamic removal of planes/encoders/crtcs.
> > 
> > v2: Convert drm_crtc_index() and drm_encoder_index() as well.
> > v3: Stop adjusting the indices upon removal; consider the list
> > construct-only.
> > 
> > Signed-off-by: Chris Wilson 
> > Cc: Daniel Vetter 
> > Cc: Matt Roper 
> > Cc: Ville Syrjälä 
> > ---
> ...snip...
> > @@ -2337,7 +2369,18 @@ extern int drm_plane_init(struct drm_device *dev,
> >   const uint32_t *formats, unsigned int format_count,
> >   bool is_primary);
> >  extern void drm_plane_cleanup(struct drm_plane *plane);
> > -extern unsigned int drm_plane_index(struct drm_plane *plane);
> > +
> > +/**
> > + * drm_plane_index - find the index of a registered plane
> > + * @plane: plane to find index for
> > + *
> > + * Given a registered plane, return the index of that CRTC within a DRM
> 
> "index of that plane"

Fixed ..
> 
> Otherwise,
> 
> Reviewed-by: Matt Roper 

... and applied to drm-misc.
-Daniel

> 
> 
> 
> Matt
> 
> > + * device's list of planes.
> > + */
> > +static inline unsigned int drm_plane_index(struct drm_plane *plane)
> > +{
> > +   return plane->index;
> > +}
> >  extern struct drm_plane * drm_plane_from_index(struct drm_device *dev, int 
> > idx);
> >  extern void drm_plane_force_disable(struct drm_plane *plane);
> >  extern int drm_plane_check_pixel_format(const struct drm_plane *plane,
> > -- 
> > 2.8.1
> > 
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> IoTG Platform Enabling & Development
> Intel Corporation
> (916) 356-2795

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Re: [Intel-gfx] [PATCH 01/20] drm/atomic: Fix remaining places where !funcs->best_encoder is valid

[Daniel Vetter]

On Thu, Jun 2, 2016 at 11:05 PM, Laurent Pinchart
 wrote:
> Hi Boris,
>
> Thank you for the patch.
>
> On Thursday 02 Jun 2016 16:31:28 Boris Brezillon wrote:
>> Adapt drm_pick_crtcs() and update_connector_routing() to fallback to
>> drm_atomic_helper_best_encoder() if funcs->best_encoder() is NULL so
>> that DRM drivers can leave this hook unassigned if they know they want
>> to use drm_atomic_helper_best_encoder().
>
> Could you please update include/drm/drm_modeset_helper_vtables.h to document
> this new behaviour ?

Thanks for reminding me. Please update hooks for both
atomic_best_encoder and best_encoder. Also mention that it's only
optional for atomic drivers. There's lots of examples in that file for
the wording usually used.

> The only drawback I see in this patch is the additional object lookup
> performed by drm_atomic_helper_best_encoder() at runtime. I wonder if we could
> somehow cache the information, as the assignment can't change when there's a
> 1:1 correspondence between encoders and connectors.

drm_encoder_find is an idr lookup. That should be plenty fast,
especially for modeset code. Usually what's too expensive even for
modeset code is linear list walks. But Chris just submitted patches to
convert most of them into simple lookups.
-Daniel

>>> Signed-off-by: Boris Brezillon 
>> ---
>>  drivers/gpu/drm/drm_atomic_helper.c |  4 +++-
>>  drivers/gpu/drm/drm_fb_helper.c | 13 -
>>  2 files changed, 15 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/drm_atomic_helper.c
>> b/drivers/gpu/drm/drm_atomic_helper.c index f6a3350..849d029 100644
>> --- a/drivers/gpu/drm/drm_atomic_helper.c
>> +++ b/drivers/gpu/drm/drm_atomic_helper.c
>> @@ -300,8 +300,10 @@ update_connector_routing(struct drm_atomic_state
>> *state, if (funcs->atomic_best_encoder)
>>   new_encoder = funcs->atomic_best_encoder(connector,
>>connector_state);
>> - else
>> + else if (funcs->best_encoder)
>>   new_encoder = funcs->best_encoder(connector);
>> + else
>> + new_encoder = drm_atomic_helper_best_encoder(connector);
>>
>>   if (!new_encoder) {
>>   DRM_DEBUG_ATOMIC("No suitable encoder found for 
>> [CONNECTOR:%d:%s]\n",
>> diff --git a/drivers/gpu/drm/drm_fb_helper.c
>> b/drivers/gpu/drm/drm_fb_helper.c index 7c2eb75..d44389a 100644
>> --- a/drivers/gpu/drm/drm_fb_helper.c
>> +++ b/drivers/gpu/drm/drm_fb_helper.c
>> @@ -2000,7 +2000,18 @@ static int drm_pick_crtcs(struct drm_fb_helper
>> *fb_helper, my_score++;
>>
>>   connector_funcs = connector->helper_private;
>> - encoder = connector_funcs->best_encoder(connector);
>> +
>> + /*
>> +  * If the DRM device implements atomic hooks and ->best_encoder() is
>> +  * NULL we fallback to the default drm_atomic_helper_best_encoder()
>> +  * helper.
>> +  */
>> + if (fb_helper->dev->mode_config.funcs->atomic_commit &&
>> + !connector_funcs->best_encoder)
>> + encoder = drm_atomic_helper_best_encoder(connector);
>> + else
>> + encoder = connector_funcs->best_encoder(connector);
>> +
>>   if (!encoder)
>>   goto out;
>
> --
> Regards,
>
> Laurent Pinchart
>



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Re: [Intel-gfx] [PATCH 04/38] drm/rcar-du: Use for_each_*_in_state

[Laurent Pinchart]

Hi Daniel,

Thank you for the patch.

On Thursday 02 Jun 2016 00:06:27 Daniel Vetter wrote:
> We want to hide drm_atomic_state internals better.
> 
> Cc: Laurent Pinchart 
> Signed-off-by: Daniel Vetter 

Acked-by: Laurent Pinchart 

> ---
>  drivers/gpu/drm/rcar-du/rcar_du_kms.c   |  8 
>  drivers/gpu/drm/rcar-du/rcar_du_plane.c | 20 
>  2 files changed, 12 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> b/drivers/gpu/drm/rcar-du/rcar_du_kms.c index e70a4f33d970..f315c55c1f65
> 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> @@ -288,6 +288,8 @@ static int rcar_du_atomic_commit(struct drm_device *dev,
> {
>   struct rcar_du_device *rcdu = dev->dev_private;
>   struct rcar_du_commit *commit;
> + struct drm_crtc *crtc;
> + struct drm_crtc_state *crtc_state;
>   unsigned int i;
>   int ret;
> 
> @@ -309,10 +311,8 @@ static int rcar_du_atomic_commit(struct drm_device
> *dev, /* Wait until all affected CRTCs have completed previous commits and
> * mark them as pending.
>*/
> - for (i = 0; i < dev->mode_config.num_crtc; ++i) {
> - if (state->crtcs[i])
> - commit->crtcs |= 1 << drm_crtc_index(state->crtcs[i]);
> - }
> + for_each_crtc_in_state(state, crtc, crtc_state, i)
> + commit->crtcs |= 1 << drm_crtc_index(crtc);
> 
>   spin_lock(>commit.wait.lock);
>   ret = wait_event_interruptible_locked(rcdu->commit.wait,
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_plane.c
> b/drivers/gpu/drm/rcar-du/rcar_du_plane.c index d445e67f78e1..bfe31ca870cc
> 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_plane.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_plane.c
> @@ -140,18 +140,17 @@ int rcar_du_atomic_check_planes(struct drm_device
> *dev, bool needs_realloc = false;
>   unsigned int groups = 0;
>   unsigned int i;
> + struct drm_plane *drm_plane;
> + struct drm_plane_state *drm_plane_state;
> 
>   /* Check if hardware planes need to be reallocated. */
> - for (i = 0; i < dev->mode_config.num_total_plane; ++i) {
> + for_each_plane_in_state(state, drm_plane, drm_plane_state, i) {
>   struct rcar_du_plane_state *plane_state;
>   struct rcar_du_plane *plane;
>   unsigned int index;
> 
> - if (!state->planes[i])
> - continue;
> -
> - plane = to_rcar_plane(state->planes[i]);
> - plane_state = to_rcar_plane_state(state->plane_states[i]);
> + plane = to_rcar_plane(drm_plane);
> + plane_state = to_rcar_plane_state(drm_plane_state);
> 
>   dev_dbg(rcdu->dev, "%s: checking plane (%u,%tu)\n", __func__,
>   plane->group->index, plane - plane->group->planes);
> @@ -247,18 +246,15 @@ int rcar_du_atomic_check_planes(struct drm_device
> *dev, }
> 
>   /* Reallocate hardware planes for each plane that needs it. */
> - for (i = 0; i < dev->mode_config.num_total_plane; ++i) {
> + for_each_plane_in_state(state, drm_plane, drm_plane_state, i) {
>   struct rcar_du_plane_state *plane_state;
>   struct rcar_du_plane *plane;
>   unsigned int crtc_planes;
>   unsigned int free;
>   int idx;
> 
> - if (!state->planes[i])
> - continue;
> -
> - plane = to_rcar_plane(state->planes[i]);
> - plane_state = to_rcar_plane_state(state->plane_states[i]);
> + plane = to_rcar_plane(drm_plane);
> + plane_state = to_rcar_plane_state(drm_plane_state);
> 
>   dev_dbg(rcdu->dev, "%s: allocating plane (%u,%tu)\n", __func__,
>   plane->group->index, plane - plane->group->planes);

-- 
Regards,

Laurent Pinchart

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Re: [Intel-gfx] [PATCH 06/38] drm/omap: Use for_each_plane_in_state

[Laurent Pinchart]

Hi Daniel,

Thank you for the patch.

On Thursday 02 Jun 2016 00:06:29 Daniel Vetter wrote:
> We want to hide drm_atomic_stat internals a bit better.
> 
> Cc: Laurent Pinchart 
> Cc: Tomi Valkeinen 
> Signed-off-by: Daniel Vetter 

Acked-by: Laurent Pinchart 

> ---
>  drivers/gpu/drm/omapdrm/omap_drv.c | 11 +--
>  1 file changed, 5 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/omapdrm/omap_drv.c
> b/drivers/gpu/drm/omapdrm/omap_drv.c index d86f5479345b..4798ba43ff5b
> 100644
> --- a/drivers/gpu/drm/omapdrm/omap_drv.c
> +++ b/drivers/gpu/drm/omapdrm/omap_drv.c
> @@ -142,8 +142,9 @@ static int omap_atomic_commit(struct drm_device *dev,
>  {
>   struct omap_drm_private *priv = dev->dev_private;
>   struct omap_atomic_state_commit *commit;
> - unsigned int i;
> - int ret;
> + struct drm_crtc *crtc;
> + struct drm_crtc_state *crtc_state;
> + int i, ret;
> 
>   ret = drm_atomic_helper_prepare_planes(dev, state);
>   if (ret)
> @@ -163,10 +164,8 @@ static int omap_atomic_commit(struct drm_device *dev,
>   /* Wait until all affected CRTCs have completed previous commits and
>* mark them as pending.
>*/
> - for (i = 0; i < dev->mode_config.num_crtc; ++i) {
> - if (state->crtcs[i])
> - commit->crtcs |= 1 << drm_crtc_index(state->crtcs[i]);
> - }
> + for_each_crtc_in_state(state, crtc, crtc_state, i)
> + commit->crtcs |= 1 << drm_crtc_index(crtc);
> 
>   wait_event(priv->commit.wait, !omap_atomic_is_pending(priv, commit));

-- 
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Laurent Pinchart

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Re: [Intel-gfx] [PATCH 01/20] drm/atomic: Fix remaining places where !funcs->best_encoder is valid

[Laurent Pinchart]

Hi Boris,

Thank you for the patch.

On Thursday 02 Jun 2016 16:31:28 Boris Brezillon wrote:
> Adapt drm_pick_crtcs() and update_connector_routing() to fallback to
> drm_atomic_helper_best_encoder() if funcs->best_encoder() is NULL so
> that DRM drivers can leave this hook unassigned if they know they want
> to use drm_atomic_helper_best_encoder().

Could you please update include/drm/drm_modeset_helper_vtables.h to document 
this new behaviour ?

The only drawback I see in this patch is the additional object lookup 
performed by drm_atomic_helper_best_encoder() at runtime. I wonder if we could 
somehow cache the information, as the assignment can't change when there's a 
1:1 correspondence between encoders and connectors.

> Signed-off-by: Boris Brezillon 
> ---
>  drivers/gpu/drm/drm_atomic_helper.c |  4 +++-
>  drivers/gpu/drm/drm_fb_helper.c | 13 -
>  2 files changed, 15 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_atomic_helper.c
> b/drivers/gpu/drm/drm_atomic_helper.c index f6a3350..849d029 100644
> --- a/drivers/gpu/drm/drm_atomic_helper.c
> +++ b/drivers/gpu/drm/drm_atomic_helper.c
> @@ -300,8 +300,10 @@ update_connector_routing(struct drm_atomic_state
> *state, if (funcs->atomic_best_encoder)
>   new_encoder = funcs->atomic_best_encoder(connector,
>connector_state);
> - else
> + else if (funcs->best_encoder)
>   new_encoder = funcs->best_encoder(connector);
> + else
> + new_encoder = drm_atomic_helper_best_encoder(connector);
> 
>   if (!new_encoder) {
>   DRM_DEBUG_ATOMIC("No suitable encoder found for 
> [CONNECTOR:%d:%s]\n",
> diff --git a/drivers/gpu/drm/drm_fb_helper.c
> b/drivers/gpu/drm/drm_fb_helper.c index 7c2eb75..d44389a 100644
> --- a/drivers/gpu/drm/drm_fb_helper.c
> +++ b/drivers/gpu/drm/drm_fb_helper.c
> @@ -2000,7 +2000,18 @@ static int drm_pick_crtcs(struct drm_fb_helper
> *fb_helper, my_score++;
> 
>   connector_funcs = connector->helper_private;
> - encoder = connector_funcs->best_encoder(connector);
> +
> + /*
> +  * If the DRM device implements atomic hooks and ->best_encoder() is
> +  * NULL we fallback to the default drm_atomic_helper_best_encoder()
> +  * helper.
> +  */
> + if (fb_helper->dev->mode_config.funcs->atomic_commit &&
> + !connector_funcs->best_encoder)
> + encoder = drm_atomic_helper_best_encoder(connector);
> + else
> + encoder = connector_funcs->best_encoder(connector);
> +
>   if (!encoder)
>   goto out;

-- 
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Laurent Pinchart

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Re: [Intel-gfx] [PATCH 16/20] drm: omap: Rely on the default ->best_encoder() behavior

[Laurent Pinchart]

Hi Boris,

Thank you for the patch.

On Thursday 02 Jun 2016 16:31:43 Boris Brezillon wrote:
> We have a 1:1 relationship between connectors and encoders and the
> driver is relying on the atomic helpers: we can drop the custom
> ->best_encoder() implementation and let the core call
> drm_atomic_helper_best_encoder() for us.
> 
> Signed-off-by: Boris Brezillon 
> ---
>  drivers/gpu/drm/omapdrm/omap_connector.c | 8 
>  1 file changed, 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/omapdrm/omap_connector.c
> b/drivers/gpu/drm/omapdrm/omap_connector.c index ce2d67b..80af5e1 100644
> --- a/drivers/gpu/drm/omapdrm/omap_connector.c
> +++ b/drivers/gpu/drm/omapdrm/omap_connector.c
> @@ -256,13 +256,6 @@ static int omap_connector_mode_valid(struct
> drm_connector *connector, return ret;
>  }
> 
> -struct drm_encoder *omap_connector_attached_encoder(
> - struct drm_connector *connector)
> -{
> - struct omap_connector *omap_connector = to_omap_connector(connector);
> - return omap_connector->encoder;

The omap_connector::encoder field is assigned but not used anymore, you can 
remove it.

With that fixed,

Reviewed-by: Laurent Pinchart 

> -}
> -
>  static const struct drm_connector_funcs omap_connector_funcs = {
>   .dpms = drm_atomic_helper_connector_dpms,
>   .reset = drm_atomic_helper_connector_reset,
> @@ -276,7 +269,6 @@ static const struct drm_connector_funcs
> omap_connector_funcs = { static const struct drm_connector_helper_funcs
> omap_connector_helper_funcs = { .get_modes = omap_connector_get_modes,
>   .mode_valid = omap_connector_mode_valid,
> - .best_encoder = omap_connector_attached_encoder,
>  };
> 
>  /* initialize connector */

-- 
Regards,

Laurent Pinchart

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Re: [Intel-gfx] [PATCH 09/20] drm: rcar-du: Rely on the default ->best_encoder() behavior

[Laurent Pinchart]

Hi Boris,

Thank you for the patch.

On Thursday 02 Jun 2016 16:31:36 Boris Brezillon wrote:
> All outputs have a 1:1 relationship between connectors and encoders,
> and the driver is relying on the atomic helpers: we can drop the custom
> ->best_encoder() implementations and let the core call
> drm_atomic_helper_best_encoder() for us.
> 
> Signed-off-by: Boris Brezillon 
> ---
>  drivers/gpu/drm/rcar-du/rcar_du_encoder.c | 12 
>  drivers/gpu/drm/rcar-du/rcar_du_encoder.h |  3 ---
>  drivers/gpu/drm/rcar-du/rcar_du_hdmicon.c |  1 -
>  drivers/gpu/drm/rcar-du/rcar_du_lvdscon.c |  1 -
>  drivers/gpu/drm/rcar-du/rcar_du_vgacon.c  |  1 -
>  5 files changed, 18 deletions(-)
> 
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_encoder.c
> b/drivers/gpu/drm/rcar-du/rcar_du_encoder.c index 4e939e4..55149e9 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_encoder.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_encoder.c
> @@ -27,18 +27,6 @@
>  #include "rcar_du_vgacon.h"
> 
>  /*
> ---
> -- - * Common connector functions
> - */
> -
> -struct drm_encoder *
> -rcar_du_connector_best_encoder(struct drm_connector *connector)
> -{
> - struct rcar_du_connector *rcon = to_rcar_connector(connector);
> -
> - return rcar_encoder_to_drm_encoder(rcon->encoder);
> -}
> -
> -/*
> ---
> -- * Encoder
>   */
> 
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_encoder.h
> b/drivers/gpu/drm/rcar-du/rcar_du_encoder.h index 719b6f2a..a8669c3 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_encoder.h
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_encoder.h
> @@ -49,9 +49,6 @@ struct rcar_du_connector {
>  #define to_rcar_connector(c) \
>   container_of(c, struct rcar_du_connector, connector)
> 
> -struct drm_encoder *
> -rcar_du_connector_best_encoder(struct drm_connector *connector);
> -
>  int rcar_du_encoder_init(struct rcar_du_device *rcdu,
>enum rcar_du_encoder_type type,
>enum rcar_du_output output,
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_hdmicon.c
> b/drivers/gpu/drm/rcar-du/rcar_du_hdmicon.c index 6c92714..612b4d5 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_hdmicon.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_hdmicon.c
> @@ -52,7 +52,6 @@ static int rcar_du_hdmi_connector_mode_valid(struct
> drm_connector *connector, static const struct drm_connector_helper_funcs
> connector_helper_funcs = { .get_modes = rcar_du_hdmi_connector_get_modes,
>   .mode_valid = rcar_du_hdmi_connector_mode_valid,
> - .best_encoder = rcar_du_connector_best_encoder,
>  };
> 
>  static enum drm_connector_status
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_lvdscon.c
> b/drivers/gpu/drm/rcar-du/rcar_du_lvdscon.c index e905f5d..6afd0af 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_lvdscon.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_lvdscon.c
> @@ -59,7 +59,6 @@ static int rcar_du_lvds_connector_get_modes(struct
> drm_connector *connector)
> 
>  static const struct drm_connector_helper_funcs connector_helper_funcs = {
>   .get_modes = rcar_du_lvds_connector_get_modes,
> - .best_encoder = rcar_du_connector_best_encoder,
>  };
> 
>  static enum drm_connector_status
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vgacon.c
> b/drivers/gpu/drm/rcar-du/rcar_du_vgacon.c index 9d7e5c9..68f7ffa 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_vgacon.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_vgacon.c
> @@ -28,7 +28,6 @@ static int rcar_du_vga_connector_get_modes(struct
> drm_connector *connector)
> 
>  static const struct drm_connector_helper_funcs connector_helper_funcs = {
>   .get_modes = rcar_du_vga_connector_get_modes,
> - .best_encoder = rcar_du_connector_best_encoder,
>  };
> 
>  static enum drm_connector_status

You can also remove

rcon->encoder = renc;

from rcar_du_vga_connector_init(), it's not needed anymore. The same code in 
rcar_du_hdmi_connector_init() has to stay for now though, as it's used to 
locate the slave encoder in the HDMI support code. That should change when the 
driver will be converted to use drm_bridge.

I can also fix this during the conversion to drm_bridge if you don't want to 
resubmit. In any case,

Reviewed-by: Laurent Pinchart 

-- 
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Laurent Pinchart

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Re: [Intel-gfx] [PATCH] drm/i915: Fix a buch of kerneldoc warnings

[Daniel Vetter]

On Thu, Jun 02, 2016 at 04:19:48PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> Just a bunch of stale kerneldocs generating warnings when
> building the docs. Mostly function parameters so not very
> useful but still.
> 
> Signed-off-by: Tvrtko Ursulin 
> Cc: Daniel Vetter 

Minor nit: Mostly we dont put a blank line between the title - purpose
line and the start of the @parameter list. There's also a bunch of
kerneldoc comments that don't even start with the function name. Do they
work and show up correctly in the generated output?

One more special case below
> ---
>  drivers/gpu/drm/i915/i915_cmd_parser.c  |  9 +++---
>  drivers/gpu/drm/i915/i915_gem.c | 54 
> +++--
>  drivers/gpu/drm/i915/i915_irq.c |  7 +++--
>  drivers/gpu/drm/i915/i915_vgpu.c|  4 +--
>  drivers/gpu/drm/i915/intel_lrc.c| 20 +---
>  drivers/gpu/drm/i915/intel_runtime_pm.c |  1 +
>  6 files changed, 70 insertions(+), 25 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c 
> b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index d97f28bfa9db..b0fd6a7b0603 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -737,7 +737,7 @@ static void fini_hash_table(struct intel_engine_cs 
> *engine)
>  
>  /**
>   * i915_cmd_parser_init_ring() - set cmd parser related fields for a 
> ringbuffer
> - * @ring: the ringbuffer to initialize
> + * @engine: the engine to initialize
>   *
>   * Optionally initializes fields related to batch buffer command parsing in 
> the
>   * struct intel_engine_cs based on whether the platform requires software
> @@ -830,7 +830,7 @@ int i915_cmd_parser_init_ring(struct intel_engine_cs 
> *engine)
>  
>  /**
>   * i915_cmd_parser_fini_ring() - clean up cmd parser related fields
> - * @ring: the ringbuffer to clean up
> + * @engine: the engine to clean up
>   *
>   * Releases any resources related to command parsing that may have been
>   * initialized for the specified ring.
> @@ -1024,7 +1024,7 @@ unpin_src:
>  
>  /**
>   * i915_needs_cmd_parser() - should a given ring use software command 
> parsing?
> - * @ring: the ring in question
> + * @engine: the engine in question
>   *
>   * Only certain platforms require software batch buffer command parsing, and
>   * only when enabled via module parameter.
> @@ -1176,7 +1176,7 @@ static bool check_cmd(const struct intel_engine_cs 
> *engine,
>  
>  /**
>   * i915_parse_cmds() - parse a submitted batch buffer for privilege 
> violations
> - * @ring: the ring on which the batch is to execute
> + * @engine: the engine on which the batch is to execute
>   * @batch_obj: the batch buffer in question
>   * @shadow_batch_obj: copy of the batch buffer in question
>   * @batch_start_offset: byte offset in the batch at which execution starts
> @@ -1281,6 +1281,7 @@ int i915_parse_cmds(struct intel_engine_cs *engine,
>  
>  /**
>   * i915_cmd_parser_get_version() - get the cmd parser version number
> + * @dev_priv: i915 device private
>   *
>   * The cmd parser maintains a simple increasing integer version number 
> suitable
>   * for passing to userspace clients to determine what operations are 
> permitted.
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 343d88114f3b..6c46ddbe927a 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -409,6 +409,10 @@ i915_gem_dumb_create(struct drm_file *file,
>  
>  /**
>   * Creates a new mm object and returns a handle to it.
> + *
> + * @dev: drm device pointer
> + * @data: ioctl data blob
> + * @file: drm file pointer
>   */
>  int
>  i915_gem_create_ioctl(struct drm_device *dev, void *data,
> @@ -673,6 +677,10 @@ out:
>  /**
>   * Reads data from the object referenced by handle.
>   *
> + * @dev: drm_device pointer
> + * @data: ioctl data blob
> + * @file: drm_file pointer
> + *
>   * On error, the contents of *data are undefined.
>   */
>  int
> @@ -753,6 +761,11 @@ fast_user_write(struct io_mapping *mapping,
>  /**
>   * This is the fast pwrite path, where we copy the data directly from the
>   * user into the GTT, uncached.
> + *
> + * @dev: drm device pointer
> + * @obj: i915 gem object
> + * @args: pwrite arguments structure
> + * @file: drm file pointer
>   */
>  static int
>  i915_gem_gtt_pwrite_fast(struct drm_device *dev,
> @@ -1016,6 +1029,9 @@ out:
>  
>  /**
>   * Writes data to the object referenced by handle.
> + * @dev: drm device
> + * @data: ioctl data blob
> + * @file: drm file
>   *
>   * On error, the contents of the buffer that were to be modified are 
> undefined.
>   */
> @@ -1213,6 +1229,7 @@ static int __i915_spin_request(struct 
> drm_i915_gem_request *req, int state)
>   * @req: duh!
>   * @interruptible: do an interruptible wait (normally yes)
>   * @timeout: in - how long to wait (NULL forever); out - how much time 
> 

Re: [Intel-gfx] [PATCH 12/38] drm/fence: add fence to drm_pending_event

[Daniel Vetter]

On Thu, Jun 02, 2016 at 02:49:13PM -0400, Sean Paul wrote:
> On Wed, Jun 1, 2016 at 6:06 PM, Daniel Vetter  wrote:
> > From: Gustavo Padovan 
> >
> > Now a drm_pending_event can either send a real drm_event or signal a
> > fence, or both. It allow us to signal via fences when the buffer is
> > displayed on the screen. Which in turn means that the previous buffer
> > is not in use anymore and can be freed or sent back to another driver
> > for processing.
> >
> > v2: Comments from Daniel Vetter
> > - call fence_signal in drm_send_event_locked()
> > - remove unneeded !e->event check
> >
> > v3: Remove drm_pending_event->destroy to fix a leak when e->file_priv
> > is not set.
> >
> > Signed-off-by: Gustavo Padovan  (v2)
> > Signed-off-by: Daniel Vetter 
> 
> 
> I suppose one could argue that the s/destroy/kfree/ change might
> warrant a separate change, but the patch is very readable as-is, so:
 
Yeah I got somewhat lazy with this one ;-)

> Reviewed-by: Sean Paul 

Thanks for the review, patch merged to drm-misc.
-Daniel

> 
> > ---
> >  drivers/gpu/drm/drm_atomic.c| 19 +--
> >  drivers/gpu/drm/drm_fops.c  | 16 +---
> >  drivers/gpu/drm/nouveau/nouveau_usif.c  |  1 -
> >  drivers/gpu/drm/rockchip/rockchip_drm_vop.c |  2 +-
> >  include/drm/drmP.h  |  3 ++-
> >  5 files changed, 25 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
> > index 5093d81f60f7..5e4b820a977c 100644
> > --- a/drivers/gpu/drm/drm_atomic.c
> > +++ b/drivers/gpu/drm/drm_atomic.c
> > @@ -1413,7 +1413,8 @@ EXPORT_SYMBOL(drm_atomic_nonblocking_commit);
> >   */
> >
> >  static struct drm_pending_vblank_event *create_vblank_event(
> > -   struct drm_device *dev, struct drm_file *file_priv, 
> > uint64_t user_data)
> > +   struct drm_device *dev, struct drm_file *file_priv,
> > +   struct fence *fence, uint64_t user_data)
> >  {
> > struct drm_pending_vblank_event *e = NULL;
> > int ret;
> > @@ -1426,12 +1427,17 @@ static struct drm_pending_vblank_event 
> > *create_vblank_event(
> > e->event.base.length = sizeof(e->event);
> > e->event.user_data = user_data;
> >
> > -   ret = drm_event_reserve_init(dev, file_priv, >base, 
> > >event.base);
> > -   if (ret) {
> > -   kfree(e);
> > -   return NULL;
> > +   if (file_priv) {
> > +   ret = drm_event_reserve_init(dev, file_priv, >base,
> > +>event.base);
> > +   if (ret) {
> > +   kfree(e);
> > +   return NULL;
> > +   }
> > }
> >
> > +   e->base.fence = fence;
> > +
> > return e;
> >  }
> >
> > @@ -1671,7 +1677,8 @@ retry:
> > for_each_crtc_in_state(state, crtc, crtc_state, i) {
> > struct drm_pending_vblank_event *e;
> >
> > -   e = create_vblank_event(dev, file_priv, 
> > arg->user_data);
> > +   e = create_vblank_event(dev, file_priv, NULL,
> > +   arg->user_data);
> > if (!e) {
> > ret = -ENOMEM;
> > goto out;
> > diff --git a/drivers/gpu/drm/drm_fops.c b/drivers/gpu/drm/drm_fops.c
> > index 868871068956..4c4b30f7a9f2 100644
> > --- a/drivers/gpu/drm/drm_fops.c
> > +++ b/drivers/gpu/drm/drm_fops.c
> > @@ -294,7 +294,7 @@ static void drm_events_release(struct drm_file 
> > *file_priv)
> > /* Remove unconsumed events */
> > list_for_each_entry_safe(e, et, _priv->event_list, link) {
> > list_del(>link);
> > -   e->destroy(e);
> > +   kfree(e);
> > }
> >
> > spin_unlock_irqrestore(>event_lock, flags);
> > @@ -525,7 +525,7 @@ put_back_event:
> > }
> >
> > ret += length;
> > -   e->destroy(e);
> > +   kfree(e);
> > }
> > }
> > mutex_unlock(_priv->event_read_lock);
> > @@ -602,9 +602,6 @@ int drm_event_reserve_init_locked(struct drm_device 
> > *dev,
> > list_add(>pending_link, _priv->pending_event_list);
> > p->file_priv = file_priv;
> >
> > -   /* we *could* pass this in as arg, but everyone uses kfree: */
> > -   p->destroy = (void (*) (struct drm_pending_event *)) kfree;
> > -
> > return 0;
> >  }
> >  EXPORT_SYMBOL(drm_event_reserve_init_locked);
> > @@ -667,7 +664,7 @@ void drm_event_cancel_free(struct drm_device *dev,
> > list_del(>pending_link);
> > }
> > spin_unlock_irqrestore(>event_lock, 

[Intel-gfx] [PATCH 6/7] drm/i915: Remove mostly duplicated video DIP handling from PSR code

[ville . syrjala]

From: Ville Syrjälä 

Now that the infoframe hooks are part of the intel_dig_port, we can use
the normal .write_infoframe() hook to update the VSC SDP. We do need to
deal with the size difference between the VSC DIP and the others though.

Another minor snag is that the compiler will complain to use if we keep
using enum hdmi_infoframe_type type and passing in the DP define instead,
so et's just change to unsigned int all over for the inforframe type.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_drv.h  |  2 +-
 drivers/gpu/drm/i915/intel_hdmi.c | 26 +++--
 drivers/gpu/drm/i915/intel_psr.c  | 41 ---
 3 files changed, 25 insertions(+), 44 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 4c8451e3d8f1..5dcaa14ff90d 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -900,7 +900,7 @@ struct intel_digital_port {
/* for communication with audio component; protected by av_mutex */
const struct drm_connector *audio_connector;
void (*write_infoframe)(struct drm_encoder *encoder,
-   enum hdmi_infoframe_type type,
+   unsigned int type,
const void *frame, ssize_t len);
void (*set_infoframes)(struct drm_encoder *encoder,
   bool enable,
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
b/drivers/gpu/drm/i915/intel_hdmi.c
index 637b17baf798..600a58210450 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -68,7 +68,7 @@ static struct intel_hdmi *intel_attached_hdmi(struct 
drm_connector *connector)
return enc_to_intel_hdmi(_attached_encoder(connector)->base);
 }
 
-static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
+static u32 g4x_infoframe_index(unsigned int type)
 {
switch (type) {
case HDMI_INFOFRAME_TYPE_AVI:
@@ -83,7 +83,7 @@ static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
}
 }
 
-static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
+static u32 g4x_infoframe_enable(unsigned int type)
 {
switch (type) {
case HDMI_INFOFRAME_TYPE_AVI:
@@ -98,9 +98,11 @@ static u32 g4x_infoframe_enable(enum hdmi_infoframe_type 
type)
}
 }
 
-static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
+static u32 hsw_infoframe_enable(unsigned int type)
 {
switch (type) {
+   case DP_SDP_VSC:
+   return VIDEO_DIP_ENABLE_VSC_HSW;
case HDMI_INFOFRAME_TYPE_AVI:
return VIDEO_DIP_ENABLE_AVI_HSW;
case HDMI_INFOFRAME_TYPE_SPD:
@@ -116,10 +118,12 @@ static u32 hsw_infoframe_enable(enum hdmi_infoframe_type 
type)
 static i915_reg_t
 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
 enum transcoder cpu_transcoder,
-enum hdmi_infoframe_type type,
+unsigned int type,
 int i)
 {
switch (type) {
+   case DP_SDP_VSC:
+   return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
case HDMI_INFOFRAME_TYPE_AVI:
return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
case HDMI_INFOFRAME_TYPE_SPD:
@@ -133,7 +137,7 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv,
 }
 
 static void g4x_write_infoframe(struct drm_encoder *encoder,
-   enum hdmi_infoframe_type type,
+   unsigned int type,
const void *frame, ssize_t len)
 {
const uint32_t *data = frame;
@@ -187,7 +191,7 @@ static bool g4x_infoframe_enabled(struct drm_encoder 
*encoder,
 }
 
 static void ibx_write_infoframe(struct drm_encoder *encoder,
-   enum hdmi_infoframe_type type,
+   unsigned int type,
const void *frame, ssize_t len)
 {
const uint32_t *data = frame;
@@ -246,7 +250,7 @@ static bool ibx_infoframe_enabled(struct drm_encoder 
*encoder,
 }
 
 static void cpt_write_infoframe(struct drm_encoder *encoder,
-   enum hdmi_infoframe_type type,
+   unsigned int type,
const void *frame, ssize_t len)
 {
const uint32_t *data = frame;
@@ -303,7 +307,7 @@ static bool cpt_infoframe_enabled(struct drm_encoder 
*encoder,
 }
 
 static void vlv_write_infoframe(struct drm_encoder *encoder,
-   enum hdmi_infoframe_type type,
+   unsigned int type,
const void *frame, ssize_t len)
 {
const uint32_t *data = frame;
@@ -361,7 +365,7 @@ static bool vlv_infoframe_enabled(struct drm_encoder 
*encoder,
 }
 
 static void hsw_write_infoframe(struct drm_encoder *encoder,
-   

[Intel-gfx] [PATCH 1/7] drm/dp: Add defines for DP SDP types

[ville . syrjala]

From: Ville Syrjälä 

Add defines for the secondary data packet (SDP) types from the spec.
These are the DP specific ones, and in addition HDMI infoframe types
(see enum hdmi_infoframe_type) are also valid SDP types.

Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Ville Syrjälä 
---
 include/drm/drm_dp_helper.h | 8 
 1 file changed, 8 insertions(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 5a848e734422..9ae1aa5f6713 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -630,6 +630,14 @@ void drm_dp_link_train_channel_eq_delay(const u8 
dpcd[DP_RECEIVER_CAP_SIZE]);
 u8 drm_dp_link_rate_to_bw_code(int link_rate);
 int drm_dp_bw_code_to_link_rate(u8 link_bw);
 
+#define DP_SDP_AUDIO_TIMESTAMP 0x01
+#define DP_SDP_AUDIO_STREAM0x02
+#define DP_SDP_EXTENSION   0x04
+#define DP_SDP_AUDIO_COPYMANAGEMENT0x05
+#define DP_SDP_ISRC0x06
+#define DP_SDP_VSC 0x07
+#define DP_SDP_CAMERA_GENERIC(i)   (0x08 + (i)) /* 0x08-0x0f */
+
 struct edp_sdp_header {
u8 HB0; /* Secondary Data Packet ID */
u8 HB1; /* Secondary Data Packet Type */
-- 
2.7.4

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[Intel-gfx] [PATCH 3/7] drm/i915: Disable infoframes when shutting down DDI HDMI

[ville . syrjala]

From: Ville Syrjälä 

Disabling the video DIP when shutting the port down seems like a good
idea.

Bspec says:
"When disabling both the DIP port and DIP transmission,
 first disable the port and then disable DIP."
and
"Restriction : GCP is only supported with HDMI when the bits per color is
 not equal to 8. GCP must be enabled prior to enabling TRANS_DDI_FUNC_CTL
 for HDMI with bits per color not equal to 8 and disabled after disabling
 TRANS_DDI_FUNC_CTL"

So let's do it in the .post_disable() hook.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_ddi.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 2fb28d310c22..6ff2a7b97ca6 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1661,6 +1661,12 @@ static void intel_ddi_post_disable(struct intel_encoder 
*intel_encoder)
if (wait)
intel_wait_ddi_buf_idle(dev_priv, port);
 
+   if (type == INTEL_OUTPUT_HDMI) {
+   struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
+
+   intel_hdmi->set_infoframes(encoder, false, NULL);
+   }
+
if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
-- 
2.7.4

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[Intel-gfx] [PATCH 5/7] drm/i915: Init infoframe vfuncs for DP encoders as well

[ville . syrjala]

From: Ville Syrjälä 

DP ports may want to use the video DIP for SDP transmission, so let's
initiialize the vfuncs for DP encoders as well. The only exception is
port A eDP prior to HSW as that one doesn't have a video DIP instance.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_ddi.c  |  2 ++
 drivers/gpu/drm/i915/intel_dp.c   |  3 +++
 drivers/gpu/drm/i915/intel_drv.h  |  1 +
 drivers/gpu/drm/i915/intel_hdmi.c | 51 ++-
 4 files changed, 35 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 3a882a979e5d..c5611e9d9b9c 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2392,6 +2392,8 @@ void intel_ddi_init(struct drm_device *dev, enum port 
port)
intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
intel_encoder->cloneable = 0;
 
+   intel_infoframe_init(intel_dig_port);
+
if (init_dp) {
if (!intel_ddi_init_dp_connector(intel_dig_port))
goto err;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f97cd5305e4c..a2d0ee363307 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5637,6 +5637,9 @@ bool intel_dp_init(struct drm_device *dev,
intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
dev_priv->hotplug.irq_port[port] = intel_dig_port;
 
+   if (port != PORT_A)
+   intel_infoframe_init(intel_dig_port);
+
if (!intel_dp_init_connector(intel_dig_port, intel_connector))
goto err_init_connector;
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a607799b7776..4c8451e3d8f1 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1445,6 +1445,7 @@ struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder 
*encoder);
 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
   struct intel_crtc_state *pipe_config);
 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
+void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
 
 
 /* intel_lvds.c */
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
b/drivers/gpu/drm/i915/intel_hdmi.c
index 319f5013923c..637b17baf798 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1801,6 +1801,33 @@ intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, 
struct drm_connector *c
intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
 }
 
+void intel_infoframe_init(struct intel_digital_port *intel_dig_port)
+{
+   struct drm_device *dev = intel_dig_port->base.base.dev;
+
+   if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
+   intel_dig_port->write_infoframe = vlv_write_infoframe;
+   intel_dig_port->set_infoframes = vlv_set_infoframes;
+   intel_dig_port->infoframe_enabled = vlv_infoframe_enabled;
+   } else if (IS_G4X(dev)) {
+   intel_dig_port->write_infoframe = g4x_write_infoframe;
+   intel_dig_port->set_infoframes = g4x_set_infoframes;
+   intel_dig_port->infoframe_enabled = g4x_infoframe_enabled;
+   } else if (HAS_DDI(dev)) {
+   intel_dig_port->write_infoframe = hsw_write_infoframe;
+   intel_dig_port->set_infoframes = hsw_set_infoframes;
+   intel_dig_port->infoframe_enabled = hsw_infoframe_enabled;
+   } else if (HAS_PCH_IBX(dev)) {
+   intel_dig_port->write_infoframe = ibx_write_infoframe;
+   intel_dig_port->set_infoframes = ibx_set_infoframes;
+   intel_dig_port->infoframe_enabled = ibx_infoframe_enabled;
+   } else {
+   intel_dig_port->write_infoframe = cpt_write_infoframe;
+   intel_dig_port->set_infoframes = cpt_set_infoframes;
+   intel_dig_port->infoframe_enabled = cpt_infoframe_enabled;
+   }
+}
+
 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
   struct intel_connector *intel_connector)
 {
@@ -1883,28 +1910,6 @@ void intel_hdmi_init_connector(struct intel_digital_port 
*intel_dig_port,
BUG();
}
 
-   if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
-   intel_dig_port->write_infoframe = vlv_write_infoframe;
-   intel_dig_port->set_infoframes = vlv_set_infoframes;
-   intel_dig_port->infoframe_enabled = vlv_infoframe_enabled;
-   } else if (IS_G4X(dev)) {
-   intel_dig_port->write_infoframe = g4x_write_infoframe;
-   intel_dig_port->set_infoframes = g4x_set_infoframes;
-   intel_dig_port->infoframe_enabled = g4x_infoframe_enabled;
-   } else if (HAS_DDI(dev)) {
-   intel_dig_port->write_infoframe = 

[Intel-gfx] [PATCH 7/7] drm/i915: Allow DP ports to set/readout infoframe state (WIP)

[ville . syrjala]

From: Ville Syrjälä 

The video DIP can be used with DP ports as well. So let's at least read
out the state, and disable all infoframes when disabling the port.
Otherwise we might get left with whatever the previous guy was doing.

If we were totally paranaoid, I suppose we might consider doing this
for FDI too on DDI platforms. But that would require first decoupling
the infoframe code from intel_digital_port. So leave it be for now at
least.

FIXME need to figure out how to handle the PSR VSC SDP usage before
doing this, as that might make the state checker unhappy.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_ddi.c | 13 -
 drivers/gpu/drm/i915/intel_dp.c  |  9 +
 2 files changed, 17 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index c5611e9d9b9c..6543feeb58f2 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2157,7 +2157,6 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
-   struct intel_digital_port *intel_dig_port;
u32 temp, flags = 0;
 
/* XXX: DSI transcoder paranoia */
@@ -2193,13 +2192,17 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
break;
}
 
-   switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
-   case TRANS_DDI_MODE_SELECT_HDMI:
-   pipe_config->has_hdmi_sink = true;
-   intel_dig_port = enc_to_dig_port(>base);
+   if (encoder->type != INTEL_OUTPUT_ANALOG) {
+   struct intel_digital_port *intel_dig_port =
+   enc_to_dig_port(>base);
 
if (intel_dig_port->infoframe_enabled(>base, 
pipe_config))
pipe_config->has_infoframe = true;
+   }
+
+   switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
+   case TRANS_DDI_MODE_SELECT_HDMI:
+   pipe_config->has_hdmi_sink = true;
/* fall through */
case TRANS_DDI_MODE_SELECT_DVI:
pipe_config->lane_count = 4;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a2d0ee363307..b43009ed1dab 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2355,6 +2355,7 @@ static void intel_dp_get_config(struct intel_encoder 
*encoder,
struct intel_crtc_state *pipe_config)
 {
struct intel_dp *intel_dp = enc_to_intel_dp(>base);
+   struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
u32 tmp, flags = 0;
struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -2395,6 +2396,10 @@ static void intel_dp_get_config(struct intel_encoder 
*encoder,
!IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235)
pipe_config->limited_color_range = true;
 
+   if (intel_dig_port->infoframe_enabled &&
+   intel_dig_port->infoframe_enabled(>base, pipe_config))
+   pipe_config->has_infoframe = true;
+
pipe_config->has_dp_encoder = true;
 
pipe_config->lane_count =
@@ -3343,6 +3348,10 @@ intel_dp_link_down(struct intel_dp *intel_dp)
intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
}
 
+   if (intel_dig_port->set_infoframes)
+   intel_dig_port->set_infoframes(_dig_port->base.base,
+  NULL, false);
+
msleep(intel_dp->panel_power_down_delay);
 
intel_dp->DP = DP;
-- 
2.7.4

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[Intel-gfx] [PATCH 4/7] drm/i915: Move infoframe vfuncs into intel_digital_port

[ville . syrjala]

From: Ville Syrjälä 

DP ports will also want to utilize the video DIP for SDP transmission.
So let's move the vfuncs into the dig_port.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_ddi.c  | 20 ++--
 drivers/gpu/drm/i915/intel_drv.h  | 16 +-
 drivers/gpu/drm/i915/intel_hdmi.c | 64 ---
 3 files changed, 52 insertions(+), 48 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 6ff2a7b97ca6..3a882a979e5d 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1628,11 +1628,12 @@ static void intel_ddi_pre_enable(struct intel_encoder 
*intel_encoder)
if (port != PORT_A || INTEL_INFO(dev_priv)->gen >= 9)
intel_dp_stop_link_train(intel_dp);
} else if (type == INTEL_OUTPUT_HDMI) {
-   struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
+   struct intel_digital_port *intel_dig_port =
+   enc_to_dig_port(encoder);
 
-   intel_hdmi->set_infoframes(encoder,
-  crtc->config->has_infoframe,
-  >config->base.adjusted_mode);
+   intel_dig_port->set_infoframes(encoder,
+  crtc->config->has_infoframe,
+  
>config->base.adjusted_mode);
}
 }
 
@@ -1662,9 +1663,10 @@ static void intel_ddi_post_disable(struct intel_encoder 
*intel_encoder)
intel_wait_ddi_buf_idle(dev_priv, port);
 
if (type == INTEL_OUTPUT_HDMI) {
-   struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
+   struct intel_digital_port *intel_dig_port =
+   enc_to_dig_port(encoder);
 
-   intel_hdmi->set_infoframes(encoder, false, NULL);
+   intel_dig_port->set_infoframes(encoder, false, NULL);
}
 
if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
@@ -2155,7 +2157,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
-   struct intel_hdmi *intel_hdmi;
+   struct intel_digital_port *intel_dig_port;
u32 temp, flags = 0;
 
/* XXX: DSI transcoder paranoia */
@@ -2194,9 +2196,9 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
case TRANS_DDI_MODE_SELECT_HDMI:
pipe_config->has_hdmi_sink = true;
-   intel_hdmi = enc_to_intel_hdmi(>base);
+   intel_dig_port = enc_to_dig_port(>base);
 
-   if (intel_hdmi->infoframe_enabled(>base, pipe_config))
+   if (intel_dig_port->infoframe_enabled(>base, 
pipe_config))
pipe_config->has_infoframe = true;
/* fall through */
case TRANS_DDI_MODE_SELECT_DVI:
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index ebe7b3427e2e..a607799b7776 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -790,14 +790,6 @@ struct intel_hdmi {
bool rgb_quant_range_selectable;
enum hdmi_picture_aspect aspect_ratio;
struct intel_connector *attached_connector;
-   void (*write_infoframe)(struct drm_encoder *encoder,
-   enum hdmi_infoframe_type type,
-   const void *frame, ssize_t len);
-   void (*set_infoframes)(struct drm_encoder *encoder,
-  bool enable,
-  const struct drm_display_mode *adjusted_mode);
-   bool (*infoframe_enabled)(struct drm_encoder *encoder,
- const struct intel_crtc_state *pipe_config);
 };
 
 struct intel_dp_mst_encoder;
@@ -907,6 +899,14 @@ struct intel_digital_port {
uint8_t max_lanes;
/* for communication with audio component; protected by av_mutex */
const struct drm_connector *audio_connector;
+   void (*write_infoframe)(struct drm_encoder *encoder,
+   enum hdmi_infoframe_type type,
+   const void *frame, ssize_t len);
+   void (*set_infoframes)(struct drm_encoder *encoder,
+  bool enable,
+  const struct drm_display_mode *adjusted_mode);
+   bool (*infoframe_enabled)(struct drm_encoder *encoder,
+ const struct intel_crtc_state *pipe_config);
 };
 
 struct intel_dp_mst_encoder {
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 

[Intel-gfx] [PATCH 2/7] drm/i915: Check has_infoframes when enabling infoframes

[ville . syrjala]

From: Ville Syrjälä 

has_infoframe is what tells us whether infoframes should be enabled, so
let's pass that instead of has_hdmi_sink to .set_infoframes().

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_ddi.c  | 2 +-
 drivers/gpu/drm/i915/intel_hdmi.c | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 022b41d422dc..2fb28d310c22 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1631,7 +1631,7 @@ static void intel_ddi_pre_enable(struct intel_encoder 
*intel_encoder)
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 
intel_hdmi->set_infoframes(encoder,
-  crtc->config->has_hdmi_sink,
+  crtc->config->has_infoframe,
   >config->base.adjusted_mode);
}
 }
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
b/drivers/gpu/drm/i915/intel_hdmi.c
index eb455ea6ea92..067b10a7cb04 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1665,7 +1665,7 @@ static void intel_hdmi_pre_enable(struct intel_encoder 
*encoder)
intel_hdmi_prepare(encoder);
 
intel_hdmi->set_infoframes(>base,
-  intel_crtc->config->has_hdmi_sink,
+  intel_crtc->config->has_infoframe,
   adjusted_mode);
 }
 
@@ -1686,7 +1686,7 @@ static void vlv_hdmi_pre_enable(struct intel_encoder 
*encoder)
 0x2b247878);
 
intel_hdmi->set_infoframes(>base,
-  intel_crtc->config->has_hdmi_sink,
+  intel_crtc->config->has_infoframe,
   adjusted_mode);
 
g4x_enable_hdmi(encoder);
@@ -1749,7 +1749,7 @@ static void chv_hdmi_pre_enable(struct intel_encoder 
*encoder)
chv_set_phy_signal_level(encoder, 128, 102, false);
 
intel_hdmi->set_infoframes(>base,
-  intel_crtc->config->has_hdmi_sink,
+  intel_crtc->config->has_infoframe,
   adjusted_mode);
 
g4x_enable_hdmi(encoder);
-- 
2.7.4

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[Intel-gfx] [PATCH 0/7] drm/i915: Make infoframe code available to (e)DP ports

[ville . syrjala]

From: Ville Syrjälä 

The video DIP can be used for DP SDP transmission, so I figured we should
move the vfuncs into the intel_digital_port structure. This migth help
with the LSPCON work, and it will also allow us to rip out the duplicated
video DIP routine from the PSR code.

The last patch we don't want to merge just yet. The state checker would get
angry at the VSC DIP being enabled even though the pipe config didn't indicate
that infoframes are used. I think we'll want to convert the has_infoframe into
a bitmask and then do something about the VSC DIP. Not quite sure yet.

Entire series available here:
git://github.com/vsyrjala/linux.git infoframe_dig_port_2

Ville Syrjälä (7):
  drm/dp: Add defines for DP SDP types
  drm/i915: Check has_infoframes when enabling infoframes
  drm/i915: Disable infoframes when shutting down DDI HDMI
  drm/i915: Move infoframe vfuncs into intel_digital_port
  drm/i915: Init infoframe vfuncs for DP encoders as well
  drm/i915: Remove mostly duplicated video DIP handling from PSR code
  drm/i915: Allow DP ports to set/readout infoframe state (WIP)

 drivers/gpu/drm/i915/intel_ddi.c  |  31 +++
 drivers/gpu/drm/i915/intel_dp.c   |  12 +
 drivers/gpu/drm/i915/intel_drv.h  |  17 +++---
 drivers/gpu/drm/i915/intel_hdmi.c | 111 +-
 drivers/gpu/drm/i915/intel_psr.c  |  41 +++---
 include/drm/drm_dp_helper.h   |   8 +++
 6 files changed, 122 insertions(+), 98 deletions(-)

-- 
2.7.4

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Re: [Intel-gfx] [PATCH 12/38] drm/fence: add fence to drm_pending_event

[Sean Paul]

On Wed, Jun 1, 2016 at 6:06 PM, Daniel Vetter  wrote:
> From: Gustavo Padovan 
>
> Now a drm_pending_event can either send a real drm_event or signal a
> fence, or both. It allow us to signal via fences when the buffer is
> displayed on the screen. Which in turn means that the previous buffer
> is not in use anymore and can be freed or sent back to another driver
> for processing.
>
> v2: Comments from Daniel Vetter
> - call fence_signal in drm_send_event_locked()
> - remove unneeded !e->event check
>
> v3: Remove drm_pending_event->destroy to fix a leak when e->file_priv
> is not set.
>
> Signed-off-by: Gustavo Padovan  (v2)
> Signed-off-by: Daniel Vetter 


I suppose one could argue that the s/destroy/kfree/ change might
warrant a separate change, but the patch is very readable as-is, so:

Reviewed-by: Sean Paul 

> ---
>  drivers/gpu/drm/drm_atomic.c| 19 +--
>  drivers/gpu/drm/drm_fops.c  | 16 +---
>  drivers/gpu/drm/nouveau/nouveau_usif.c  |  1 -
>  drivers/gpu/drm/rockchip/rockchip_drm_vop.c |  2 +-
>  include/drm/drmP.h  |  3 ++-
>  5 files changed, 25 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
> index 5093d81f60f7..5e4b820a977c 100644
> --- a/drivers/gpu/drm/drm_atomic.c
> +++ b/drivers/gpu/drm/drm_atomic.c
> @@ -1413,7 +1413,8 @@ EXPORT_SYMBOL(drm_atomic_nonblocking_commit);
>   */
>
>  static struct drm_pending_vblank_event *create_vblank_event(
> -   struct drm_device *dev, struct drm_file *file_priv, uint64_t 
> user_data)
> +   struct drm_device *dev, struct drm_file *file_priv,
> +   struct fence *fence, uint64_t user_data)
>  {
> struct drm_pending_vblank_event *e = NULL;
> int ret;
> @@ -1426,12 +1427,17 @@ static struct drm_pending_vblank_event 
> *create_vblank_event(
> e->event.base.length = sizeof(e->event);
> e->event.user_data = user_data;
>
> -   ret = drm_event_reserve_init(dev, file_priv, >base, 
> >event.base);
> -   if (ret) {
> -   kfree(e);
> -   return NULL;
> +   if (file_priv) {
> +   ret = drm_event_reserve_init(dev, file_priv, >base,
> +>event.base);
> +   if (ret) {
> +   kfree(e);
> +   return NULL;
> +   }
> }
>
> +   e->base.fence = fence;
> +
> return e;
>  }
>
> @@ -1671,7 +1677,8 @@ retry:
> for_each_crtc_in_state(state, crtc, crtc_state, i) {
> struct drm_pending_vblank_event *e;
>
> -   e = create_vblank_event(dev, file_priv, 
> arg->user_data);
> +   e = create_vblank_event(dev, file_priv, NULL,
> +   arg->user_data);
> if (!e) {
> ret = -ENOMEM;
> goto out;
> diff --git a/drivers/gpu/drm/drm_fops.c b/drivers/gpu/drm/drm_fops.c
> index 868871068956..4c4b30f7a9f2 100644
> --- a/drivers/gpu/drm/drm_fops.c
> +++ b/drivers/gpu/drm/drm_fops.c
> @@ -294,7 +294,7 @@ static void drm_events_release(struct drm_file *file_priv)
> /* Remove unconsumed events */
> list_for_each_entry_safe(e, et, _priv->event_list, link) {
> list_del(>link);
> -   e->destroy(e);
> +   kfree(e);
> }
>
> spin_unlock_irqrestore(>event_lock, flags);
> @@ -525,7 +525,7 @@ put_back_event:
> }
>
> ret += length;
> -   e->destroy(e);
> +   kfree(e);
> }
> }
> mutex_unlock(_priv->event_read_lock);
> @@ -602,9 +602,6 @@ int drm_event_reserve_init_locked(struct drm_device *dev,
> list_add(>pending_link, _priv->pending_event_list);
> p->file_priv = file_priv;
>
> -   /* we *could* pass this in as arg, but everyone uses kfree: */
> -   p->destroy = (void (*) (struct drm_pending_event *)) kfree;
> -
> return 0;
>  }
>  EXPORT_SYMBOL(drm_event_reserve_init_locked);
> @@ -667,7 +664,7 @@ void drm_event_cancel_free(struct drm_device *dev,
> list_del(>pending_link);
> }
> spin_unlock_irqrestore(>event_lock, flags);
> -   p->destroy(p);
> +   kfree(p);
>  }
>  EXPORT_SYMBOL(drm_event_cancel_free);
>
> @@ -689,8 +686,13 @@ void drm_send_event_locked(struct drm_device *dev, 
> struct drm_pending_event *e)
>  {
> assert_spin_locked(>event_lock);
>
> +   if (e->fence) {
> +   fence_signal(e->fence);
> +   fence_put(e->fence);
> +   }
> +
> if (!e->file_priv) {
> 

Re: [Intel-gfx] ✗ Ro.CI.BAT: failure for drm/i915: Remaining PSR fixes

[Ville Syrjälä]

On Tue, May 31, 2016 at 04:17:00PM -, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915: Remaining PSR fixes
> URL   : https://patchwork.freedesktop.org/series/8046/
> State : failure
> 
> == Summary ==
> 
> Series 8046v1 drm/i915: Remaining PSR fixes
> http://patchwork.freedesktop.org/api/1.0/series/8046/revisions/1/mbox
> 
> Test gem_close_race:
> Subgroup basic-process:
> dmesg-warn -> PASS   (ro-ivb2-i7-3770)

ivb fails are
[  176.194435] BUG: using smp_processor_id() in preemptible [] code: 
usb-storage/216

https://bugs.freedesktop.org/show_bug.cgi?id=96293

> Test gem_cpu_reloc:
> Subgroup basic:
> dmesg-warn -> PASS   (ro-ivb2-i7-3770)
> Test gem_ctx_param:
> Subgroup basic:
> pass   -> DMESG-WARN (ro-ivb2-i7-3770)
> Test gem_exec_basic:
> Subgroup gtt-default:
> dmesg-warn -> PASS   (ro-skl-i7-6700hq)
> Subgroup gtt-vebox:
> dmesg-warn -> PASS   (ro-skl-i7-6700hq)
> Subgroup readonly-bsd:
> dmesg-warn -> PASS   (ro-ivb2-i7-3770)
> Test gem_exec_flush:
> Subgroup basic-uc-pro-default:
> pass   -> DMESG-WARN (ro-skl-i7-6700hq)

skl fails are
[  360.358514] [drm:intel_pipe_update_start [i915]] *ERROR* Potential atomic 
update failure on pipe A

https://bugs.freedesktop.org/show_bug.cgi?id=95632

> Test kms_pipe_crc_basic:
> Subgroup suspend-read-crc-pipe-a:
> pass   -> INCOMPLETE (fi-hsw-i7-4770k)

Hmm. Nothing in dmesg after
[  403.811416] kms_pipe_crc_basic: starting subtest suspend-read-crc-pipe-A

so no clue what happened.

> Test kms_sink_crc_basic:
> pass   -> SKIP   (ro-bdw-i7-5600u)
> pass   -> SKIP   (ro-skl-i7-6700hq)

[  114.613007] [drm:intel_dp_sink_crc [i915]] *ERROR* Panel is unable to 
calculate any CRC after 6 vblanks

Hmm. This could actually have something to with the patch set.

Looking at the long term CI results, at least the bdw seems to have
been rather solid since RO_CI_DRM_419 which included [1]. The skl
has been fluctuating until ~RO_CI_DRM_453, but I see no PSR related
changes around that time so I'm going to assume the apparent recent
stability was more of a fluke.

[1]
dc00b6a drm/i915/psr: Implement PSR2 w/a for gen9
d4dcbdc drm/i915/psr: Use ->get_aux_send_ctl functions
6f32ea7 drm/i915/psr: Order DP aux transactions correctly
1c80c25 drm/i915/psr: Make idle_frames sensible again
50db139 drm/i915/psr: Try to program link training times correctly


> 
> fi-byt-n2820 total:209  pass:168  dwarn:0   dfail:0   fail:3   skip:38 
> fi-hsw-i7-4770k  total:184  pass:166  dwarn:0   dfail:0   fail:0   skip:17 
> fi-hsw-i7-4770r  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
> fi-skl-i5-6260u  total:209  pass:198  dwarn:0   dfail:0   fail:0   skip:11 
> fi-skl-i7-6700k  total:209  pass:184  dwarn:0   dfail:0   fail:0   skip:25 
> fi-snb-i7-2600   total:209  pass:170  dwarn:0   dfail:0   fail:0   skip:39 
> ro-bdw-i5-5250u  total:102  pass:93   dwarn:0   dfail:0   fail:0   skip:8  
> ro-bdw-i7-5600u  total:102  pass:74   dwarn:0   dfail:0   fail:0   skip:27 
> ro-bsw-n3050 total:209  pass:168  dwarn:0   dfail:0   fail:2   skip:39 
> ro-byt-n2820 total:209  pass:169  dwarn:0   dfail:0   fail:3   skip:37 
> ro-hsw-i3-4010u  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
> ro-hsw-i7-4770r  total:102  pass:82   dwarn:0   dfail:0   fail:0   skip:19 
> ro-ilk1-i5-650   total:204  pass:146  dwarn:0   dfail:0   fail:1   skip:57 
> ro-ivb2-i7-3770  total:102  pass:47   dwarn:32  dfail:0   fail:0   skip:22 
> ro-skl-i7-6700hq total:204  pass:172  dwarn:9   dfail:1   fail:0   skip:22 
> fi-bdw-i7-5557u failed to connect after reboot
> fi-bsw-n3050 failed to connect after reboot
> ro-bdw-i7-5557U failed to connect after reboot
> ro-ilk-i7-620lm failed to connect after reboot
> ro-ivb-i7-3770 failed to connect after reboot
> ro-snb-i7-2620M failed to connect after reboot
> 
> Results at /archive/results/CI_IGT_test/RO_Patchwork_1068/
> 
> 877a1d2 drm-intel-nightly: 2016y-05m-31d-14h-57m-44s UTC integration manifest
> 8238bdb drm/i915: Move psr.link_standby setup to intel_psr_match_conditions()
> 58ee76a drm/i915: Ask the sink whether training is required when exiting PSR 
> main-link off mode
> 5fe07aa drm/i915/psr: Skip aux handeshake if the vbt tells us to
> 6e98304 drm/i915: Check PSR setup time vs. vblank length
> 2a67384 drm/dp: Add drm_dp_psr_need_train_on_exit()
> 3ad03bc drm/dp: Add drm_dp_psr_setup_time()

-- 
Ville Syrjälä
Intel OTC
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[Intel-gfx] ✗ Ro.CI.BAT: failure for drm/atomic: Provide default ->best_encoder() behavior

[Patchwork]

== Series Details ==

Series: drm/atomic: Provide default ->best_encoder() behavior
URL   : https://patchwork.freedesktop.org/series/8164/
State : failure

== Summary ==

Series 8164v1 drm/atomic: Provide default ->best_encoder() behavior
http://patchwork.freedesktop.org/api/1.0/series/8164/revisions/1/mbox

Test core_auth:
Subgroup basic-auth:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Test gem_busy:
Subgroup basic-parallel-vebox:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Subgroup basic-vebox:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Test gem_close_race:
Subgroup basic-process:
pass   -> DMESG-WARN (ro-skl-i7-6700hq)
Test gem_exec_basic:
Subgroup gtt-blt:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Test gem_exec_flush:
Subgroup basic-batch-kernel-default-cmd:
pass   -> FAIL   (ro-byt-n2820)
Subgroup basic-uc-pro-default:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Subgroup basic-wb-prw-default:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Test gem_mmap_gtt:
Subgroup basic-write-no-prefault:
pass   -> DMESG-WARN (ro-skl-i7-6700hq)
Test gem_tiled_pread_basic:
pass   -> DMESG-WARN (ro-skl-i7-6700hq)
Test kms_addfb_basic:
Subgroup addfb25-framebuffer-vs-set-tiling:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Subgroup addfb25-modifier-no-flag:
pass   -> DMESG-WARN (ro-skl-i7-6700hq)
Subgroup addfb25-y-tiled:
pass   -> DMESG-WARN (ro-skl-i7-6700hq)
Subgroup addfb25-yf-tiled:
pass   -> DMESG-WARN (ro-skl-i7-6700hq)
Subgroup bad-pitch-0:
pass   -> DMESG-WARN (ro-skl-i7-6700hq)
Subgroup bad-pitch-65536:
pass   -> DMESG-WARN (ro-skl-i7-6700hq)
Subgroup bad-pitch-999:
pass   -> DMESG-WARN (ro-skl-i7-6700hq)
Subgroup basic-y-tiled:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Subgroup framebuffer-vs-set-tiling:
pass   -> DMESG-WARN (ro-skl-i7-6700hq)
Subgroup too-high:
pass   -> DMESG-WARN (ro-skl-i7-6700hq)
Subgroup unused-modifier:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Subgroup unused-offsets:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Test kms_psr_sink_crc:
Subgroup psr_basic:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)

ro-bdw-i5-5250u  total:24   pass:18   dwarn:0   dfail:0   fail:0   skip:5  
ro-bdw-i7-5600u  total:102  pass:75   dwarn:0   dfail:0   fail:0   skip:26 
ro-bsw-n3050 total:209  pass:167  dwarn:1   dfail:0   fail:2   skip:39 
ro-byt-n2820 total:209  pass:169  dwarn:0   dfail:0   fail:3   skip:37 
ro-hsw-i3-4010u  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
ro-hsw-i7-4770r  total:102  pass:82   dwarn:0   dfail:0   fail:0   skip:19 
ro-ilk-i7-620lm  total:1pass:0dwarn:0   dfail:0   fail:0   skip:0  
ro-ilk1-i5-650   total:204  pass:146  dwarn:0   dfail:0   fail:1   skip:57 
ro-ivb-i7-3770   total:15   pass:11   dwarn:0   dfail:0   fail:0   skip:3  
ro-ivb2-i7-3770  total:102  pass:79   dwarn:0   dfail:0   fail:0   skip:22 
ro-skl-i7-6700hq total:204  pass:168  dwarn:15  dfail:0   fail:0   skip:21 
ro-snb-i7-2620M  total:102  pass:72   dwarn:0   dfail:0   fail:0   skip:29 
ro-bdw-i5-5250u failed to connect after reboot
ro-bdw-i7-5557U failed to connect after reboot
ro-ivb-i7-3770 failed to connect after reboot

Results at /archive/results/CI_IGT_test/RO_Patchwork_1083/

976092d drm-intel-nightly: 2016y-06m-02d-15h-42m-07s UTC integration manifest
e7f349a drm/bridge: dw-hdmi: Use drm_atomic_helper_best_encoder()
f48cb7e drm/bridge: ps8622: Rely on the default ->best_encoder() behavior
25365b8 drm/bridge: ptn3460: Rely on the default ->best_encoder() behavior
61bed8c drm/bridge: anx78xx: Rely on the default ->best_encoder() behavior
b8e3331 drm: omap: Rely on the default ->best_encoder() behavior
f741cc0 drm: virtgpu: Rely on the default ->best_encoder() behavior
f278d8d drm: vc4: Rely on the default ->best_encoder() behavior
824edeb drm: tegra: Rely on the default ->best_encoder() behavior
a25e7e2 drm: sun4i: Rely on the default ->best_encoder() behavior
082d524 drm: sti: Rely on the default ->best_encoder() behavior
190b84f drm: rockchip: Rely on the default ->best_encoder() behavior
6fd6bb5 drm: rcar-du: Rely on the default ->best_encoder() behavior
a4ae51f drm: msm: Rely on the default ->best_encoder() behavior where 
appropriate
924c45e drm: mediatek: Rely on the default ->best_encoder() behavior
18ac6f0 drm: i915: Rely on the default ->best_encoder() behavior where 
appropriate
ca3705d drm: fsl-dcu: Rely on the default ->best_encoder() behavior
c5e87b2 drm: exynos: Rely 

[Intel-gfx] [PATCH 1/2] Revert "drm/i915/kbl: drm/i915: Avoid GuC loading for now on Kabylake."

[Peter Antoine]

This reverts commit 2b81b84471b9

Signed-off-by: Peter Antoine 
---
 drivers/gpu/drm/i915/i915_drv.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 96d5034..fa4b96e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2812,7 +2812,7 @@ struct drm_i915_cmd_table {
  * command submission once loaded. But these are logically independent
  * properties, so we have separate macros to test them.
  */
-#define HAS_GUC(dev)   (IS_GEN9(dev) && !IS_KABYLAKE(dev))
+#define HAS_GUC(dev)   (IS_GEN9(dev))
 #define HAS_GUC_UCODE(dev) (HAS_GUC(dev))
 #define HAS_GUC_SCHED(dev) (HAS_GUC(dev))
 
-- 
1.9.1

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[Intel-gfx] [PATCH 0/2] Enable GuC on KBL

[Peter Antoine]

The following patches will enable GuC loading for the KBL.
The version of firmware that is required 9.14.

Peter Antoine (2):
  Revert "drm/i915/kbl: drm/i915: Avoid GuC loading for now on
Kabylake."
  i915/guc: Add Kabylake GuC Loading

 drivers/gpu/drm/i915/i915_drv.h | 2 +-
 drivers/gpu/drm/i915/intel_guc_loader.c | 7 +++
 2 files changed, 8 insertions(+), 1 deletion(-)

-- 
1.9.1

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[Intel-gfx] [PATCH 2/2] i915/guc: Add Kabylake GuC Loading

[Peter Antoine]

This patch added the loading of the GuC for Kabylake.
It loads a 2.4 firmware.

Signed-off-by: Peter Antoine 
Signed-off-by: Michel Thierry 
---
 drivers/gpu/drm/i915/intel_guc_loader.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c 
b/drivers/gpu/drm/i915/intel_guc_loader.c
index f2b88c7..413af19 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -65,6 +65,9 @@ MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
 #define I915_BXT_GUC_UCODE "i915/bxt_guc_ver8_7.bin"
 MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
 
+#define I915_KBL_GUC_UCODE "i915/kbl_guc_ver9.bin"
+MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
+
 /* User-friendly representation of an enum */
 const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
 {
@@ -696,6 +699,10 @@ void intel_guc_init(struct drm_device *dev)
fw_path = I915_BXT_GUC_UCODE;
guc_fw->guc_fw_major_wanted = 8;
guc_fw->guc_fw_minor_wanted = 7;
+   } else if (IS_KABYLAKE(dev)) {
+   fw_path = I915_KBL_GUC_UCODE;
+   guc_fw->guc_fw_major_wanted = 9;
+   guc_fw->guc_fw_minor_wanted = 14;
} else {
fw_path = "";   /* unknown device */
}
-- 
1.9.1

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[Intel-gfx] ✗ Ro.CI.BAT: warning for drm/i915/debugfs: Missing intel_runtime_pm_* (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/debugfs: Missing intel_runtime_pm_* (rev2)
URL   : https://patchwork.freedesktop.org/series/8140/
State : warning

== Summary ==

Series 8140v2 drm/i915/debugfs: Missing intel_runtime_pm_*
http://patchwork.freedesktop.org/api/1.0/series/8140/revisions/2/mbox

Test core_auth:
Subgroup basic-auth:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Test gem_busy:
Subgroup basic-parallel-vebox:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Subgroup basic-vebox:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Test gem_exec_basic:
Subgroup gtt-blt:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Test gem_exec_flush:
Subgroup basic-uc-pro-default:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Subgroup basic-uc-set-default:
pass   -> DMESG-WARN (ro-skl-i7-6700hq)
Subgroup basic-wb-pro-default:
pass   -> DMESG-WARN (ro-skl-i7-6700hq)
Test gem_mmap_gtt:
Subgroup basic-write-gtt:
pass   -> DMESG-WARN (ro-skl-i7-6700hq)
Subgroup basic-write-gtt-no-prefault:
pass   -> DMESG-WARN (ro-skl-i7-6700hq)
Test gem_storedw_loop:
Subgroup basic-render:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Subgroup basic-vebox:
pass   -> DMESG-WARN (ro-skl-i7-6700hq)
Test gem_tiled_pread_basic:
pass   -> DMESG-WARN (ro-skl-i7-6700hq)
Test kms_addfb_basic:
Subgroup addfb25-bad-modifier:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Subgroup addfb25-framebuffer-vs-set-tiling:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Subgroup bad-pitch-128:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Subgroup bad-pitch-256:
pass   -> DMESG-WARN (ro-skl-i7-6700hq)
Subgroup bad-pitch-32:
pass   -> DMESG-WARN (ro-skl-i7-6700hq)
Subgroup basic-y-tiled:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Subgroup unused-modifier:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Subgroup unused-offsets:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Test kms_flip:
Subgroup basic-flip-vs-wf_vblank:
pass   -> SKIP   (fi-skl-i5-6260u)

fi-hsw-i7-4770k  total:209  pass:190  dwarn:0   dfail:0   fail:0   skip:19 
fi-skl-i5-6260u  total:209  pass:197  dwarn:0   dfail:0   fail:0   skip:12 
fi-skl-i7-6700k  total:209  pass:184  dwarn:0   dfail:0   fail:0   skip:25 
fi-snb-i7-2600   total:209  pass:170  dwarn:0   dfail:0   fail:0   skip:39 
ro-bdw-i5-5250u  total:102  pass:93   dwarn:0   dfail:0   fail:0   skip:8  
ro-bdw-i7-5600u  total:102  pass:75   dwarn:0   dfail:0   fail:0   skip:26 
ro-bsw-n3050 total:209  pass:168  dwarn:0   dfail:0   fail:2   skip:39 
ro-hsw-i3-4010u  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
ro-hsw-i7-4770r  total:102  pass:82   dwarn:0   dfail:0   fail:0   skip:19 
ro-ilk1-i5-650   total:204  pass:146  dwarn:0   dfail:0   fail:1   skip:57 
ro-ivb-i7-3770   total:102  pass:75   dwarn:0   dfail:0   fail:0   skip:26 
ro-skl-i7-6700hq total:204  pass:172  dwarn:11  dfail:0   fail:0   skip:21 
ro-snb-i7-2620M  total:102  pass:72   dwarn:0   dfail:0   fail:0   skip:29 
fi-bdw-i7-5557u failed to connect after reboot
ro-bdw-i7-5557U failed to connect after reboot
ro-ivb2-i7-3770 failed to connect after reboot

Results at /archive/results/CI_IGT_test/RO_Patchwork_1082/

976092d drm-intel-nightly: 2016y-06m-02d-15h-42m-07s UTC integration manifest
bbd2511 drm/i915/debugfs: Missing intel_runtime_pm_*

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Re: [Intel-gfx] [PATCH i-g-t] kms_plane_scaling: Don't try to use second scaler on pipe C

[Ville Syrjälä]

On Thu, Jun 02, 2016 at 07:50:33AM -0700, Matt Roper wrote:
> On Thu, Jun 02, 2016 at 11:35:08AM +0300, Ville Syrjälä wrote:
> > On Wed, Jun 01, 2016 at 03:13:19PM -0700, Matt Roper wrote:
> > > Gen9 has two scalers on pipes A & B, but only a single scaler on pipe C.
> > > We should bail out of the test early on pipe C so that we don't ask the
> > > kernel to use more scalers than we really have.
> > > 
> > > Note that this test may still fail (on any pipe) if we're already using
> > > one of the scalers as a panel fitter.  But at least this is an
> > > improvement over the existing state where the test is guaranteed to fail
> > > if run with pipe C active.
> > > 
> > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92248
> > > Signed-off-by: Matt Roper 
> > > ---
> > >  tests/kms_plane_scaling.c | 7 ++-
> > >  1 file changed, 6 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/tests/kms_plane_scaling.c b/tests/kms_plane_scaling.c
> > > index ad5404d..2b17702 100644
> > > --- a/tests/kms_plane_scaling.c
> > > +++ b/tests/kms_plane_scaling.c
> > > @@ -264,6 +264,9 @@ static void test_plane_scaling(data_t *d)
> > >   igt_display_commit2(display, COMMIT_UNIVERSAL);
> > >   }
> > >  
> > > + if (pipe == PIPE_C)
> > > + goto crtcdone;
> > > +
> > 
> > You you make assumptions like that, then you should probably make the
> > test skip on !gen9.
> 
> It already does as far as I can see.  It sets data.num_scalers to 0 for
> pre-gen9 in the main function and then has a
> igt_require(d->num_scalers) in the test function.

Hmm. Seems like a rather roundabout way of writing "I want gen9".

> 
> > The test is making a lot of assumptions already though, so probably
> > would blow up on many other platforms anyway. It also makes some
> > assumptions about display resolutions and whatnot, so might blow up on
> > gen9 as well.
> 
> Yep, agreed with this.  I think there's a lot of improvement that could
> be done here, but at the moment I just wanted to fix one case of low
> hanging fruit that would fail 100% of the time.
> 
> 
> Matt
> 
> > 
> > Would be cool if someone could make this use CRCs as well, but that
> > would probably be a little difficult since the hardware scaling
> > algorithm is naturally undocumented :( How I long for the old video
> > overlay... Hmm. Actually there does seem to be a way to force bilinear
> > scaling at least. Matching that with software rendering might be doable.
> > 
> > >   /* Set up fb3->plane3 mapping. */
> > >   d->plane3 = igt_output_get_plane(output, IGT_PLANE_3);
> > >   igt_plane_set_fb(d->plane3, >fb3);
> > > @@ -301,9 +304,11 @@ static void test_plane_scaling(data_t *d)
> > >   igt_display_commit2(display, COMMIT_UNIVERSAL);
> > >   }
> > >  
> > > +crtcdone:
> > >   /* back to single plane mode */
> > >   igt_plane_set_fb(d->plane2, NULL);
> > > - igt_plane_set_fb(d->plane3, NULL);
> > > + if (pipe != PIPE_C)
> > > + igt_plane_set_fb(d->plane3, NULL);
> > >   igt_display_commit2(display, COMMIT_UNIVERSAL);
> > >  
> > >   valid_tests++;
> > > -- 
> > > 2.1.4
> > > 
> > > ___
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
> > -- 
> > Ville Syrjälä
> > Intel OTC
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> IoTG Platform Enabling & Development
> Intel Corporation
> (916) 356-2795

-- 
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Intel OTC
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[Intel-gfx] [PATCH v6 6/9] drm/i915: Make addressing mode bits in context descriptor configurable

[Zhi Wang]

Currently the addressing mode bit in context descriptor is statically
generated from the configuration of system-wide PPGTT usage model.

GVT-g will load the PPGTT shadow page table by itself and probably one
guest is using a different addressing mode with i915 host. The addressing
mode bits of a LRC context should be configurable under this case.

v6:

- Directly save the addressing mode bits inside i915_gem_context. (Chris)
- Move the LRC context addressing mode bits into intel_lrc.h. (Chris)

v5:

- Change USES_FULL_48BIT(dev) to USES_FULL_48BIT(dev_priv) (Tvrtko)

Signed-off-by: Zhi Wang 
---
 drivers/gpu/drm/i915/i915_drv.h |  1 +
 drivers/gpu/drm/i915/i915_gem_context.c |  2 ++
 drivers/gpu/drm/i915/intel_lrc.c| 13 +
 drivers/gpu/drm/i915/intel_lrc.h| 11 +++
 4 files changed, 15 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a4af035..f6cb60a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -879,6 +879,7 @@ struct i915_gem_context {
bool initialised;
} engine[I915_NUM_ENGINES];
u32 lrc_ring_buffer_size;
+   u32 lrc_addressing_mode_bits;
 
struct list_head link;
 
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 1663981..d9d7779 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -296,6 +296,8 @@ __create_hw_context(struct drm_device *dev,
 
ctx->hang_stats.ban_period_seconds = DRM_I915_CTX_BAN_PERIOD;
ctx->lrc_ring_buffer_size = 4 * PAGE_SIZE;
+   ctx->lrc_addressing_mode_bits = GEN8_CTX_ADDRESSING_MODE(dev_priv) <<
+   GEN8_CTX_ADDRESSING_MODE_SHIFT;
 
return ctx;
 
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 72a0cca..ffb436c 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -208,16 +208,6 @@
 } while (0)
 
 enum {
-   ADVANCED_CONTEXT = 0,
-   LEGACY_32B_CONTEXT,
-   ADVANCED_AD_CONTEXT,
-   LEGACY_64B_CONTEXT
-};
-#define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
-#define GEN8_CTX_ADDRESSING_MODE(dev)  (USES_FULL_48BIT_PPGTT(dev) ?\
-   LEGACY_64B_CONTEXT :\
-   LEGACY_32B_CONTEXT)
-enum {
FAULT_AND_HANG = 0,
FAULT_AND_HALT, /* Debug only */
FAULT_AND_STREAM,
@@ -281,8 +271,6 @@ logical_ring_init_platform_invariants(struct 
intel_engine_cs *engine)
(engine->id == VCS || engine->id == 
VCS2);
 
engine->ctx_desc_template = GEN8_CTX_VALID;
-   engine->ctx_desc_template |= GEN8_CTX_ADDRESSING_MODE(dev_priv) <<
-  GEN8_CTX_ADDRESSING_MODE_SHIFT;
if (IS_GEN8(dev_priv))
engine->ctx_desc_template |= GEN8_CTX_L3LLC_COHERENT;
engine->ctx_desc_template |= GEN8_CTX_PRIVILEGE;
@@ -326,6 +314,7 @@ intel_lr_context_descriptor_update(struct i915_gem_context 
*ctx,
BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (1<ctx_desc_template;   /* bits  0-11 */
+   desc |= ctx->lrc_addressing_mode_bits;  /* bits  3-4  */
desc |= ce->lrc_vma->node.start + LRC_PPHWSP_PN * PAGE_SIZE;
/* bits 12-31 */
desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT;   /* bits 32-52 */
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index a8db42a..e133c33 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -28,6 +28,17 @@
 
 #define GEN8_LR_CONTEXT_ALIGN 4096
 
+enum {
+   ADVANCED_CONTEXT = 0,
+   LEGACY_32B_CONTEXT,
+   ADVANCED_AD_CONTEXT,
+   LEGACY_64B_CONTEXT
+};
+#define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
+#define GEN8_CTX_ADDRESSING_MODE(dev_priv) (USES_FULL_48BIT_PPGTT(dev_priv) ?\
+   LEGACY_64B_CONTEXT : \
+   LEGACY_32B_CONTEXT)
+
 /* Execlists regs */
 #define RING_ELSP(ring)_MMIO((ring)->mmio_base 
+ 0x230)
 #define RING_EXECLIST_STATUS_LO(ring)  _MMIO((ring)->mmio_base + 0x234)
-- 
1.9.1

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[Intel-gfx] [PATCH v6 9/9] drm/i915: Introduce GVT context creation API

[Zhi Wang]

GVT workload scheduler needs special host LRC contexts, the so called
"shadow LRC context" to submit guest workload to host i915. During the
guest workload submission, GVT fills the shadow LRC context with the
content of guest LRC context: engine context is copied without changes,
ring context is mostly owned by host i915.

The GVT-g workload scheduler flow:

 +---+   +---+
 | GVT Guest |   | GVT Guest |
 +-+-^---+   +-+-^---+
   | | | |
   | | GVT-g   | | GVT-g
vELSP write| | emulates vELSP write| | emulates
   | | Execlist/CSB| | Execlist/CSB
   | | Status  | | Status
   | | | |
+--v-+-v-+-+
|   GVT Virtual Execlist Submission|
+--+---+---+
   |   |
   | Per-VM/Ring Workoad Q | Per-VM/Ring Workload Q
   +-+--+  ++
   +---v+^ +---v+
   |GVT Workload|... | |GVT Workload|...
   ++| ++
 |
 | Pick Workload from Q
++-+
|GVT Workload Scheduler|
++-+
 | * Shadow guest LRC context
  +--v--+  * Shadow guest ring buffer
  | GVT Context |  * Scan/Patch guest RB instructions
  +--+--+
 |
 v
  Host i915 GEM Submission

v6:

- Make GVT code as dead code when !CONFIG_DRM_I915_GVT. (Chris)

v5:
- Only compile this feature when CONFIG_DRM_I915_GVT is enabled. (Tvrtko)
- Rebase the code into new repo.
- Add a comment about the ring buffer size. (Joonas)

v2:

Mostly based on Daniel's idea. Call the refactored core logic of GEM
context creation service and LRC context creation service to create the GVT
context.

Signed-off-by: Zhi Wang 
---
 drivers/gpu/drm/i915/i915_gem_context.c | 32 
 1 file changed, 32 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index d9d7779..c0259d7 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -342,6 +342,38 @@ i915_gem_create_context(struct drm_device *dev,
return ctx;
 }
 
+/**
+ * i915_gem_create_gvt_context - create a GVT GEM context
+ * @dev: drm device *
+ *
+ * This function is used to create a GVT specific GEM context.
+ *
+ * Returns:
+ * pointer to i915_gem_context on success, error pointer if failed
+ *
+ */
+struct i915_gem_context *
+i915_gem_create_gvt_context(struct drm_device *dev)
+{
+   struct i915_gem_context *ctx;
+
+   if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
+   return ERR_PTR(-ENODEV);
+
+   mutex_lock(>struct_mutex);
+
+   ctx = i915_gem_create_context(dev, NULL);
+   if (IS_ERR(ctx))
+   goto out;
+
+   ctx->enable_lrc_status_change_notification = true;
+   ctx->enable_lrc_single_submission = true;
+   ctx->lrc_ring_buffer_size = 512 * PAGE_SIZE; /* Max ring buffer size */
+out:
+   mutex_unlock(>struct_mutex);
+   return ctx;
+}
+
 static void i915_gem_context_unpin(struct i915_gem_context *ctx,
   struct intel_engine_cs *engine)
 {
-- 
1.9.1

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[Intel-gfx] [PATCH v6 8/9] drm/i915: Support LRC context single submission

[Zhi Wang]

This patch introduces the support of LRC context signle submission.
As GVT context may come from different guests, which requires different
configuration of render registers. It can't be combined into a dual ELSP
submission combo.

Only GVT-g will create this kinds of GEM context currently.

v6:
- Make GVT code as dead code when !CONFIG_DRM_I915_GVT. (Chris)

v5:

- Only compile this feature when CONFIG_DRM_I915_GVT=y. (Tvrtko)

Signed-off-by: Zhi Wang 
---
 drivers/gpu/drm/i915/i915_drv.h  |  1 +
 drivers/gpu/drm/i915/intel_lrc.c | 15 +++
 2 files changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index dee72d3..92d01e3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -882,6 +882,7 @@ struct i915_gem_context {
u32 lrc_ring_buffer_size;
u32 lrc_addressing_mode_bits;
bool enable_lrc_status_change_notification;
+   bool enable_lrc_single_submission;
 
struct list_head link;
 
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 96d20c8..ce707ea 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -446,6 +446,21 @@ static void execlists_context_unqueue(struct 
intel_engine_cs *engine)
i915_gem_request_unreference(req0);
req0 = cursor;
} else {
+   /* Compiler will do the dead-code elimination */
+   if (IS_ENABLED(CONFIG_DRM_I915_GVT)) {
+   /*
+* req0 (after merged) ctx requires single
+* submission, stop picking
+*/
+   if (req0->ctx->enable_lrc_single_submission)
+   break;
+   /*
+* req0 ctx doesn't require single submission,
+* but next req ctx requires, stop picking
+*/
+   if (cursor->ctx->enable_lrc_single_submission)
+   break;
+   }
req1 = cursor;
WARN_ON(req1->elsp_submitted);
break;
-- 
1.9.1

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[Intel-gfx] [PATCH v6 7/9] drm/i915: Introduce execlist context status change notification

[Zhi Wang]

This patch introduces an approach to track the execlist context status
change.

GVT-g uses GVT context as the "shadow context". The content inside GVT
context will be copied back to guest after the context is idle. So GVT-g
has to know the status of the execlist context.

This function is configurable in the context creation service. Currently,
Only GVT-g will create the "status-change-notification" enabled GEM
context.

v6:

- When !CONFIG_DRM_I915_GVT, make GVT code as dead code then compiler
could automatically eliminate them for us. (Chris)
- Always initialize the notifier header, so it could be switched on/off
at runtime. (Chris)

v5:

- Only compile this feature when CONFIG_DRM_I915_GVT is enabled.(Tvrtko)

Signed-off-by: Zhi Wang 
---
 drivers/gpu/drm/i915/i915_drv.h  |  2 ++
 drivers/gpu/drm/i915/intel_lrc.c | 24 
 drivers/gpu/drm/i915/intel_lrc.h |  5 +
 3 files changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f6cb60a..dee72d3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -877,9 +877,11 @@ struct i915_gem_context {
u64 lrc_desc;
int pin_count;
bool initialised;
+   struct atomic_notifier_head status_notifier;
} engine[I915_NUM_ENGINES];
u32 lrc_ring_buffer_size;
u32 lrc_addressing_mode_bits;
+   bool enable_lrc_status_change_notification;
 
struct list_head link;
 
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index ffb436c..96d20c8 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -404,6 +404,22 @@ static void execlists_submit_requests(struct 
drm_i915_gem_request *rq0,
spin_unlock_irq(_priv->uncore.lock);
 }
 
+static inline void execlists_context_status_change(
+   struct drm_i915_gem_request *rq,
+   unsigned long status)
+{
+   /* The compiler should be fine with the dead-code elimination */
+   if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
+   return;
+
+   if (!rq->ctx->enable_lrc_status_change_notification)
+   return;
+
+   atomic_notifier_call_chain(
+   >ctx->engine[rq->engine->id].status_notifier,
+   status, rq);
+}
+
 static void execlists_context_unqueue(struct intel_engine_cs *engine)
 {
struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;
@@ -439,6 +455,11 @@ static void execlists_context_unqueue(struct 
intel_engine_cs *engine)
if (unlikely(!req0))
return;
 
+   execlists_context_status_change(req0, CONTEXT_SCHEDULE_IN);
+
+   if (req1)
+   execlists_context_status_change(req1, CONTEXT_SCHEDULE_IN);
+
if (req0->elsp_submitted & engine->idle_lite_restore_wa) {
/*
 * WaIdleLiteRestore: make sure we never cause a lite restore
@@ -477,6 +498,8 @@ execlists_check_remove_request(struct intel_engine_cs 
*engine, u32 ctx_id)
if (--head_req->elsp_submitted > 0)
return 0;
 
+   execlists_context_status_change(head_req, CONTEXT_SCHEDULE_OUT);
+
list_del(_req->execlist_link);
i915_gem_request_unreference(head_req);
 
@@ -2489,6 +2512,7 @@ static int execlists_context_deferred_alloc(struct 
i915_gem_context *ctx,
ce->ringbuf = ringbuf;
ce->state = ctx_obj;
ce->initialised = engine->init_context == NULL;
+   ATOMIC_INIT_NOTIFIER_HEAD(>status_notifier);
 
return 0;
 
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index e133c33..7a7ae8d 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -68,6 +68,11 @@ enum {
 #define GEN8_CSB_READ_PTR(csb_status) \
(((csb_status) & GEN8_CSB_READ_PTR_MASK) >> 8)
 
+enum {
+   CONTEXT_SCHEDULE_IN = 0,
+   CONTEXT_SCHEDULE_OUT,
+};
+
 /* Logical Rings */
 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request 
*request);
 int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request);
-- 
1.9.1

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[Intel-gfx] [PATCH v6 4/9] drm/i915: Introduce host graphics memory partition for GVT-g

[Zhi Wang]

From: Bing Niu 

This patch introduces host graphics memory partition when GVT-g
is enabled.

Under GVT-g, i915 host driver only owned limited graphics resources,
others are managed by GVT-g resource allocator and kept for other vGPUs.

v6:

- Remove kernel parameters used to configure GGTT owned by host. (Chris)
- Other coding style comments from Chris.
- Add more comments for reviewer.

v3:

- Remove fence partition, will use i915 fence stealing in future.(Kevin)
- Santinize GVT host gm kernel parameters. (Joonas)

v2:
- Address all coding-style comments from Joonas previously.
- Fix errors and warnning reported by checkpatch.pl. (Joonas)
- Move the graphs into the header files. (Daniel)

Signed-off-by: Bing Niu 
Signed-off-by: Zhi Wang 
---
 drivers/gpu/drm/i915/i915_vgpu.c | 23 +--
 drivers/gpu/drm/i915/intel_gvt.h | 25 +
 2 files changed, 42 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 5312816..0d891a3 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -189,14 +189,25 @@ int intel_vgt_balloon(struct drm_i915_private *dev_priv)
unsigned long unmappable_base, unmappable_size, unmappable_end;
int ret;
 
-   if (!intel_vgpu_active(dev_priv))
+   if (intel_gvt_active(dev_priv)) {
+   /* Retrieve GGTT partition information from macros */
+   mappable_base = 0;
+   mappable_size = INTEL_GVT_HOST_LOW_GM_SIZE;
+   unmappable_base = dev_priv->ggtt.mappable_end;
+   unmappable_size = INTEL_GVT_HOST_HIGH_GM_SIZE;
+   } else if (intel_vgpu_active(dev_priv)) {
+   /* Retrieve GGTT partition information from PVINFO */
+   mappable_base = I915_READ(
+   vgtif_reg(avail_rs.mappable_gmadr.base));
+   mappable_size = I915_READ(
+   vgtif_reg(avail_rs.mappable_gmadr.size));
+   unmappable_base = I915_READ(
+   vgtif_reg(avail_rs.nonmappable_gmadr.base));
+   unmappable_size = I915_READ(
+   vgtif_reg(avail_rs.nonmappable_gmadr.size));
+   } else
return 0;
 
-   mappable_base = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.base));
-   mappable_size = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.size));
-   unmappable_base = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.base));
-   unmappable_size = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.size));
-
mappable_end = mappable_base + mappable_size;
unmappable_end = unmappable_base + unmappable_size;
 
diff --git a/drivers/gpu/drm/i915/intel_gvt.h b/drivers/gpu/drm/i915/intel_gvt.h
index b9b361b..f0b9aac 100644
--- a/drivers/gpu/drm/i915/intel_gvt.h
+++ b/drivers/gpu/drm/i915/intel_gvt.h
@@ -24,6 +24,31 @@
 #ifndef _INTEL_GVT_H_
 #define _INTEL_GVT_H_
 
+/*
+ * Under GVT-g, i915 host driver only owned limited graphics resources,
+ * others are managed by GVT-g resource allocator and kept for other vGPUs.
+ *
+ * For graphics memory space partition, a typical layout looks like:
+ *
+ * +---+---+--+---+
+ * |* Host |   *GVT-g Resource |* Host|   *GVT-g Resource |
+ * | Owned |   Allocator Managed   | Owned|   Allocator Managed   |
+ * |   |   |  |   |
+ * +---+---+--+---+---+
+ * |   |   |   |   |  |   |   |   |
+ * | i915  | vm 1  | vm 2  | vm 3  | i915 | vm 1  | vm 2  | vm 3  |
+ * |   |   |   |   |  |   |   |   |
+ * +---+---+---+--+---+---+---+
+ * |   Aperture|Hidden|
+ * +---+--+
+ * |   GGTT memory space  |
+ * +--+
+ */
+
+/* GGTT memory space owned by host */
+#define INTEL_GVT_HOST_LOW_GM_SIZE (96 * 1024 * 1024)
+#define INTEL_GVT_HOST_HIGH_GM_SIZE (384 * 1024 * 1024)
+
 #ifdef CONFIG_DRM_I915_GVT
 #include "gvt/gvt.h"
 extern int intel_gvt_init(struct drm_i915_private *dev_priv);
-- 
1.9.1

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[Intel-gfx] [PATCH v6 5/9] drm/i915: Make ring buffer size of a LRC context configurable

[Zhi Wang]

This patch introduces an option for configuring the ring buffer size
of a LRC context after the context creation.

Signed-off-by: Zhi Wang 
---
 drivers/gpu/drm/i915/i915_drv.h | 1 +
 drivers/gpu/drm/i915/i915_gem_context.c | 1 +
 drivers/gpu/drm/i915/intel_lrc.c| 3 ++-
 3 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bdf499f..a4af035 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -878,6 +878,7 @@ struct i915_gem_context {
int pin_count;
bool initialised;
} engine[I915_NUM_ENGINES];
+   u32 lrc_ring_buffer_size;
 
struct list_head link;
 
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index a3b11aa..1663981 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -295,6 +295,7 @@ __create_hw_context(struct drm_device *dev,
ctx->remap_slice = ALL_L3_SLICES(dev_priv);
 
ctx->hang_stats.ban_period_seconds = DRM_I915_CTX_BAN_PERIOD;
+   ctx->lrc_ring_buffer_size = 4 * PAGE_SIZE;
 
return ctx;
 
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 5c191a1..72a0cca 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2484,7 +2484,8 @@ static int execlists_context_deferred_alloc(struct 
i915_gem_context *ctx,
return PTR_ERR(ctx_obj);
}
 
-   ringbuf = intel_engine_create_ringbuffer(engine, 4 * PAGE_SIZE);
+   ringbuf = intel_engine_create_ringbuffer(engine,
+   ctx->lrc_ring_buffer_size);
if (IS_ERR(ringbuf)) {
ret = PTR_ERR(ringbuf);
goto error_deref_obj;
-- 
1.9.1

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[Intel-gfx] [PATCH v6 3/9] drm/i915: gvt: Introduce the basic architecture of GVT-g

[Zhi Wang]

This patch introduces the very basic framework of GVT-g device model,
includes basic prototypes, definitions, initialization.

v6:
- Refine introduction in Kconfig. (Chris)
- The exposed API functions will take struct intel_gvt * instead of
void *. (Chris/Tvrtko)
- Remove most memebers of strct intel_gvt_device_info. Will add them
in the device model patches.(Chris)
- Remove gvt_info() and gvt_err() in debug.h. (Chris)
- Move GVT kernel parameter into i915_params. (Chris)
- Remove include/drm/i915_gvt.h, as GVT-g will be built within i915.
- Remove the redundant struct i915_gvt *, as the functions in i915
will directly take struct intel_gvt *.
- Add more comments for reviewer.

v5:
Take Tvrtko's comments:
- Fix the misspelled words in Kconfig
- Let functions take drm_i915_private * instead of struct drm_device *
- Remove redundant prints/local varible initialization

v3:
Take Joonas' comments:
- Change file name i915_gvt.* to intel_gvt.*
- Move GVT kernel parameter into intel_gvt.c
- Remove redundant debug macros
- Change error handling style
- Add introductions for some stub functions
- Introduce drm/i915_gvt.h.

Take Kevin's comments:
- Move GVT-g host/guest check into intel_vgt_balloon in i915_gem_gtt.c

v2:
- Introduce i915_gvt.c.
It's necessary to introduce the stubs between i915 driver and GVT-g host,
as GVT-g components is configurable in kernel config. When disabled, the
stubs here do nothing.

Take Joonas' comments:
- Replace boolean return value with int.
- Replace customized info/warn/debug macros with DRM macros.
- Document all non-static functions like i915.
- Remove empty and unused functions.
- Replace magic number with marcos.
- Set GVT-g in kernel config to "n" by default.

Signed-off-by: Zhi Wang 
---
 drivers/gpu/drm/i915/Kconfig |  19 
 drivers/gpu/drm/i915/Makefile|   5 +
 drivers/gpu/drm/i915/gvt/Makefile|   5 +
 drivers/gpu/drm/i915/gvt/debug.h |  34 +++
 drivers/gpu/drm/i915/gvt/gvt.c   | 181 +++
 drivers/gpu/drm/i915/gvt/gvt.h   |  75 +++
 drivers/gpu/drm/i915/gvt/hypercall.h |  38 
 drivers/gpu/drm/i915/gvt/mpt.h   |  49 ++
 drivers/gpu/drm/i915/i915_dma.c  |  17 +++-
 drivers/gpu/drm/i915/i915_drv.h  |  10 ++
 drivers/gpu/drm/i915/i915_params.c   |   5 +
 drivers/gpu/drm/i915/i915_params.h   |   1 +
 drivers/gpu/drm/i915/intel_gvt.c |  90 +
 drivers/gpu/drm/i915/intel_gvt.h |  46 +
 14 files changed, 571 insertions(+), 4 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gvt/Makefile
 create mode 100644 drivers/gpu/drm/i915/gvt/debug.h
 create mode 100644 drivers/gpu/drm/i915/gvt/gvt.c
 create mode 100644 drivers/gpu/drm/i915/gvt/gvt.h
 create mode 100644 drivers/gpu/drm/i915/gvt/hypercall.h
 create mode 100644 drivers/gpu/drm/i915/gvt/mpt.h
 create mode 100644 drivers/gpu/drm/i915/intel_gvt.c
 create mode 100644 drivers/gpu/drm/i915/intel_gvt.h

diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 29a32b1..e4fd9da 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -57,6 +57,25 @@ config DRM_I915_USERPTR
 
  If in doubt, say "Y".
 
+config DRM_I915_GVT
+bool "Enable Intel GVT-g graphics virtualization host support"
+depends on DRM_I915
+default n
+help
+ Choose this option if you want to enable Intel GVT-g graphics
+ virtualization technology host support with integrated graphics.
+ With GVT-g, it's possible to have one integrated graphics
+ device shared by multiple VMs under different hypervisors.
+
+ Note that at least one hypervisor like Xen or KVM is required for
+ this driver to work, and it only supports newer device from
+ Broadwell+. For further information and setup guide, you can
+ visit: http://01.org/zh/igvt-g.
+
+ The first version is still preliminary. Use it under you own risk.
+
+ If in doubt, say "N".
+
 menu "drm/i915 Debugging"
 depends on DRM_I915
 depends on EXPERT
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 7e29444..276abf1 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -104,6 +104,11 @@ i915-y += i915_vgpu.o
 # legacy horrors
 i915-y += i915_dma.o
 
+ifeq ($(CONFIG_DRM_I915_GVT),y)
+i915-y += intel_gvt.o
+include $(src)/gvt/Makefile
+endif
+
 obj-$(CONFIG_DRM_I915)  += i915.o
 
 CFLAGS_i915_trace_points.o := -I$(src)
diff --git a/drivers/gpu/drm/i915/gvt/Makefile 
b/drivers/gpu/drm/i915/gvt/Makefile
new file mode 100644
index 000..d0f21a6
--- /dev/null
+++ b/drivers/gpu/drm/i915/gvt/Makefile
@@ -0,0 +1,5 @@
+GVT_DIR := gvt
+GVT_SOURCE := gvt.o
+
+ccflags-y  += -I$(src) -I$(src)/$(GVT_DIR) -Wall
+i915-y+= $(addprefix $(GVT_DIR)/, $(GVT_SOURCE))
diff --git a/drivers/gpu/drm/i915/gvt/debug.h 

[Intel-gfx] [PATCH v6 1/9] drm/i915: Factor out i915_pvinfo.h

[Zhi Wang]

As the PVINFO page definition is used by both GVT-g guest (vGPU) and GVT-g
host (GVT-g kernel device model), factor it out for better code structure.

v3:

Take Joonas's comments:
- Use offsetof to calculate the member offset of PVINFO structure

Signed-off-by: Zhi Wang 
---
 drivers/gpu/drm/i915/i915_pvinfo.h | 116 +
 drivers/gpu/drm/i915/i915_vgpu.h   |  86 +--
 2 files changed, 117 insertions(+), 85 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/i915_pvinfo.h

diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h 
b/drivers/gpu/drm/i915/i915_pvinfo.h
new file mode 100644
index 000..eb45afb
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -0,0 +1,116 @@
+/*
+ * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 
THE
+ * SOFTWARE.
+ */
+
+#ifndef _I915_PVINFO_H_
+#define _I915_PVINFO_H_
+
+/* The MMIO offset of the shared info between guest and host emulator */
+#define VGT_PVINFO_PAGE0x78000
+#define VGT_PVINFO_SIZE0x1000
+
+/*
+ * The following structure pages are defined in GEN MMIO space
+ * for virtualization. (One page for now)
+ */
+#define VGT_MAGIC 0x4776544776544776ULL/* 'vGTvGTvG' */
+#define VGT_VERSION_MAJOR 1
+#define VGT_VERSION_MINOR 0
+
+#define INTEL_VGT_IF_VERSION_ENCODE(major, minor) ((major) << 16 | (minor))
+#define INTEL_VGT_IF_VERSION \
+   INTEL_VGT_IF_VERSION_ENCODE(VGT_VERSION_MAJOR, VGT_VERSION_MINOR)
+
+/*
+ * notifications from guest to vgpu device model
+ */
+enum vgt_g2v_type {
+   VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE = 2,
+   VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY,
+   VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE,
+   VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY,
+   VGT_G2V_EXECLIST_CONTEXT_CREATE,
+   VGT_G2V_EXECLIST_CONTEXT_DESTROY,
+   VGT_G2V_MAX,
+};
+
+struct vgt_if {
+   uint64_t magic; /* VGT_MAGIC */
+   uint16_t version_major;
+   uint16_t version_minor;
+   uint32_t vgt_id;/* ID of vGT instance */
+   uint32_t rsv1[12];  /* pad to offset 0x40 */
+   /*
+*  Data structure to describe the balooning info of resources.
+*  Each VM can only have one portion of continuous area for now.
+*  (May support scattered resource in future)
+*  (starting from offset 0x40)
+*/
+   struct {
+   /* Aperture register balooning */
+   struct {
+   uint32_t base;
+   uint32_t size;
+   } mappable_gmadr;   /* aperture */
+   /* GMADR register balooning */
+   struct {
+   uint32_t base;
+   uint32_t size;
+   } nonmappable_gmadr;/* non aperture */
+   /* allowed fence registers */
+   uint32_t fence_num;
+   uint32_t rsv2[3];
+   } avail_rs; /* available/assigned resource */
+   uint32_t rsv3[0x200 - 24];  /* pad to half page */
+   /*
+* The bottom half page is for response from Gfx driver to hypervisor.
+*/
+   uint32_t rsv4;
+   uint32_t display_ready; /* ready for display owner switch */
+
+   uint32_t rsv5[4];
+
+   uint32_t g2v_notify;
+   uint32_t rsv6[7];
+
+   struct {
+   uint32_t lo;
+   uint32_t hi;
+   } pdp[4];
+
+   uint32_t execlist_context_descriptor_lo;
+   uint32_t execlist_context_descriptor_hi;
+
+   uint32_t  rsv7[0x200 - 24];/* pad to one page */
+} __packed;
+
+#define _vgtif_reg(x) \
+   (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x))
+
+#define vgtif_reg(x) \
+   _MMIO(_vgtif_reg(x))
+
+/* vGPU display status to be used by the host side */
+#define VGT_DRV_DISPLAY_NOT_READY 0
+#define VGT_DRV_DISPLAY_READY 1  /* ready 

[Intel-gfx] [PATCH v6 2/9] drm/i915: Fold vGPU active check into inner functions

[Zhi Wang]

v5:
- Let functions take struct drm_i915_private *. (Tvrtko)

- Fold vGPU related active check into the inner functions. (Kevin)

Signed-off-by: Zhi Wang 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 11 ---
 drivers/gpu/drm/i915/i915_vgpu.c| 13 +
 drivers/gpu/drm/i915/i915_vgpu.h|  4 ++--
 3 files changed, 15 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 4668477..6f203fa 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2732,11 +2732,9 @@ static int i915_gem_setup_global_gtt(struct drm_device 
*dev,
i915_address_space_init(>base, dev_priv);
ggtt->base.total += PAGE_SIZE;
 
-   if (intel_vgpu_active(dev_priv)) {
-   ret = intel_vgt_balloon(dev);
-   if (ret)
-   return ret;
-   }
+   ret = intel_vgt_balloon(dev_priv);
+   if (ret)
+   return ret;
 
if (!HAS_LLC(dev))
ggtt->base.mm.color_adjust = i915_gtt_color_adjust;
@@ -2836,8 +2834,7 @@ void i915_ggtt_cleanup_hw(struct drm_device *dev)
i915_gem_cleanup_stolen(dev);
 
if (drm_mm_initialized(>base.mm)) {
-   if (intel_vgpu_active(dev_priv))
-   intel_vgt_deballoon();
+   intel_vgt_deballoon(dev_priv);
 
drm_mm_takedown(>base.mm);
list_del(>base.global_link);
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index d5a7a5e..5312816 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -101,10 +101,13 @@ static struct _balloon_info_ bl_info;
  * This function is called to deallocate the ballooned-out graphic memory, when
  * driver is unloaded or when ballooning fails.
  */
-void intel_vgt_deballoon(void)
+void intel_vgt_deballoon(struct drm_i915_private *dev_priv)
 {
int i;
 
+   if (!intel_vgpu_active(dev_priv))
+   return;
+
DRM_DEBUG("VGT deballoon.\n");
 
for (i = 0; i < 4; i++) {
@@ -177,9 +180,8 @@ static int vgt_balloon_space(struct drm_mm *mm,
  * Returns:
  * zero on success, non-zero if configuration invalid or ballooning failed
  */
-int intel_vgt_balloon(struct drm_device *dev)
+int intel_vgt_balloon(struct drm_i915_private *dev_priv)
 {
-   struct drm_i915_private *dev_priv = to_i915(dev);
struct i915_ggtt *ggtt = _priv->ggtt;
unsigned long ggtt_end = ggtt->base.start + ggtt->base.total;
 
@@ -187,6 +189,9 @@ int intel_vgt_balloon(struct drm_device *dev)
unsigned long unmappable_base, unmappable_size, unmappable_end;
int ret;
 
+   if (!intel_vgpu_active(dev_priv))
+   return 0;
+
mappable_base = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.base));
mappable_size = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.size));
unmappable_base = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.base));
@@ -258,6 +263,6 @@ int intel_vgt_balloon(struct drm_device *dev)
 
 err:
DRM_ERROR("VGT balloon fail\n");
-   intel_vgt_deballoon();
+   intel_vgt_deballoon(dev_priv);
return ret;
 }
diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
index 07e67d5..f8917c6 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.h
+++ b/drivers/gpu/drm/i915/i915_vgpu.h
@@ -27,7 +27,7 @@
 #include "i915_pvinfo.h"
 
 extern void i915_check_vgpu(struct drm_i915_private *dev_priv);
-extern int intel_vgt_balloon(struct drm_device *dev);
-extern void intel_vgt_deballoon(void);
+extern int intel_vgt_balloon(struct drm_i915_private *dev_priv);
+extern void intel_vgt_deballoon(struct drm_i915_private *dev_priv);
 
 #endif /* _I915_VGPU_H_ */
-- 
1.9.1

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[Intel-gfx] [PATCH v6 0/9] Introduce the implementation of GVT context

[Zhi Wang]

Mostly this patchset introduces the implementation of GVT context. GVT
context is a special GEM context used by GVT-g. GVT-g uses it as the shadow
context.It doesn't have a drm client nor a PPGTT. And it requires a larger
ring buffer with several special features need by GVT-g workload scheduler
like context status change notification, context single submission...

v6:

- Take Chris comments.

v5:

- Drop PPGTT related patches.
- Let most functions take struct drm_i915_private *
- Fixed some misspelled words in Kconfig
- Only complied some feature when CONFIG_DRM_I915_GVT=y
- Drop the fecne related changes, will send it after this series.

v4:

- Based on the latest drm-intel-nightly branch.
- Drop PPGTT refactor patches. (GVT-g will use LRI to load PDPs)
- Drop i915_gem_context() refactor patches, reuse kernel context functions.
  (Dave Gordon)
- Drop context allocation params and refactor as the lrc deferred
  allocation function has been refactored in another styles.
- Re-wrtie GVT context creation function

Difference from community release
-

This patchset is different from regular iGVT-g code release[4], which
is still based on old host-mediated architecture. Furthermore, this
patchset only supports BDW whereas code release supports HSW/BDW/SKL.
We will add SKL support later based on this RFC code and HSW support
will be dropped.

Internally we tested this RFC patchset with both linux and windows VM
and the architecture changes work fine.

Acknowledgment
---

iGVT-g implementation is several years effort and many people
contributed to the code. There names are not here yet. In later formal
patchset we will reflect individual's contribution.

Meanwhile, in the previous iGVT-g related discussion, Daniel, Chris
and Joonas ever gave very good inputs. We appreciate them and look
forward to more comments/suggestions from community.

We are trying to get more familiar with i915 but may still have gaps.
We are willing to adopt suggestions to keep improving. We hope to work
with community together to make iGVT-g a great component in i915 to
support graphics virtualization. Thanks!

Reference
-

[1] https://01.org/igvt-g
[2] http://lists.freedesktop.org/archives/intel-gfx/2014-September/053098.html
[3] http://lists.freedesktop.org/archives/intel-gfx/2015-September/075397.html

Bing Niu (1):
  drm/i915: Introduce host graphics memory partition for GVT-g

Zhi Wang (8):
  drm/i915: Factor out i915_pvinfo.h
  drm/i915: Fold vGPU active check into inner functions
  drm/i915: gvt: Introduce the basic architecture of GVT-g
  drm/i915: Make ring buffer size of a LRC context configurable
  drm/i915: Make addressing mode bits in context descriptor configurable
  drm/i915: Introduce execlist context status change notification
  drm/i915: Support LRC context single submission
  drm/i915: Introduce GVT context creation API

 drivers/gpu/drm/i915/Kconfig|  19 
 drivers/gpu/drm/i915/Makefile   |   5 +
 drivers/gpu/drm/i915/gvt/Makefile   |   5 +
 drivers/gpu/drm/i915/gvt/debug.h|  34 ++
 drivers/gpu/drm/i915/gvt/gvt.c  | 181 
 drivers/gpu/drm/i915/gvt/gvt.h  |  75 +
 drivers/gpu/drm/i915/gvt/hypercall.h|  38 +++
 drivers/gpu/drm/i915/gvt/mpt.h  |  49 +
 drivers/gpu/drm/i915/i915_dma.c |  17 ++-
 drivers/gpu/drm/i915/i915_drv.h |  15 +++
 drivers/gpu/drm/i915/i915_gem_context.c |  35 ++
 drivers/gpu/drm/i915/i915_gem_gtt.c |  11 +-
 drivers/gpu/drm/i915/i915_params.c  |   5 +
 drivers/gpu/drm/i915/i915_params.h  |   1 +
 drivers/gpu/drm/i915/i915_pvinfo.h  | 116 
 drivers/gpu/drm/i915/i915_vgpu.c|  32 --
 drivers/gpu/drm/i915/i915_vgpu.h|  90 +---
 drivers/gpu/drm/i915/intel_gvt.c|  90 
 drivers/gpu/drm/i915/intel_gvt.h|  71 +
 drivers/gpu/drm/i915/intel_lrc.c|  55 +++---
 drivers/gpu/drm/i915/intel_lrc.h|  16 +++
 21 files changed, 841 insertions(+), 119 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gvt/Makefile
 create mode 100644 drivers/gpu/drm/i915/gvt/debug.h
 create mode 100644 drivers/gpu/drm/i915/gvt/gvt.c
 create mode 100644 drivers/gpu/drm/i915/gvt/gvt.h
 create mode 100644 drivers/gpu/drm/i915/gvt/hypercall.h
 create mode 100644 drivers/gpu/drm/i915/gvt/mpt.h
 create mode 100644 drivers/gpu/drm/i915/i915_pvinfo.h
 create mode 100644 drivers/gpu/drm/i915/intel_gvt.c
 create mode 100644 drivers/gpu/drm/i915/intel_gvt.h

-- 
1.9.1

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Re: [Intel-gfx] [PATCH 0/9] Introduce the implementation of GVT context

[Wang, Zhi A]

Drop this one. Will resend it later.

> -Original Message-
> From: Wang, Zhi A
> Sent: Thursday, June 02, 2016 7:27 PM
> To: intel-gfx@lists.freedesktop.org; tvrtko.ursu...@linux.intel.com;
> joonas.lahti...@linux.intel.com; Tian, Kevin ; Lv,
> Zhiyuan ; ch...@chris-wilson.co.uk
> Cc: Wang, Zhi A 
> Subject: [PATCH 0/9] Introduce the implementation of GVT context
> 
> Mostly this patchset introduces the implementation of GVT context. GVT
> context is a special GEM context used by GVT-g. GVT-g uses it as the shadow
> context.It doesn't have a drm client nor a PPGTT. And it requires a larger 
> ring
> buffer with several special features need by GVT-g workload scheduler like
> context status change notification, context single submission...
> 
> v6:
> 
> - Take Chris comments.
> 
> v5:
> 
> - Drop PPGTT related patches.
> - Let most functions take struct drm_i915_private *
> - Fixed some misspelled words in Kconfig
> - Only complied some feature when CONFIG_DRM_I915_GVT=y
> - Drop the fecne related changes, will send it after this series.
> 
> v4:
> 
> - Based on the latest drm-intel-nightly branch.
> - Drop PPGTT refactor patches. (GVT-g will use LRI to load PDPs)
> - Drop i915_gem_context() refactor patches, reuse kernel context functions.
>   (Dave Gordon)
> - Drop context allocation params and refactor as the lrc deferred
>   allocation function has been refactored in another styles.
> - Re-wrtie GVT context creation function
> 
> Difference from community release
> -
> 
> This patchset is different from regular iGVT-g code release[4], which is still
> based on old host-mediated architecture. Furthermore, this patchset only
> supports BDW whereas code release supports HSW/BDW/SKL.
> We will add SKL support later based on this RFC code and HSW support will be
> dropped.
> 
> Internally we tested this RFC patchset with both linux and windows VM and the
> architecture changes work fine.
> 
> Acknowledgment
> ---
> 
> iGVT-g implementation is several years effort and many people contributed to
> the code. There names are not here yet. In later formal patchset we will 
> reflect
> individual's contribution.
> 
> Meanwhile, in the previous iGVT-g related discussion, Daniel, Chris and Joonas
> ever gave very good inputs. We appreciate them and look forward to more
> comments/suggestions from community.
> 
> We are trying to get more familiar with i915 but may still have gaps.
> We are willing to adopt suggestions to keep improving. We hope to work with
> community together to make iGVT-g a great component in i915 to support
> graphics virtualization. Thanks!
> 
> Reference
> -
> 
> [1] https://01.org/igvt-g
> [2]
> http://lists.freedesktop.org/archives/intel-gfx/2014-September/053098.html
> [3]
> http://lists.freedesktop.org/archives/intel-gfx/2015-September/075397.html
> 
> Bing Niu (1):
>   drm/i915: Introduce host graphics memory partition for GVT-g
> 
> Zhi Wang (8):
>   drm/i915: Factor out i915_pvinfo.h
>   drm/i915: Fold vGPU active check into inner functions
>   drm/i915: gvt: Introduce the basic architecture of GVT-g
>   drm/i915: Make ring buffer size of a LRC context configurable
>   drm/i915: Make addressing mode bits in context descriptor configurable
>   drm/i915: Introduce execlist context status change notification
>   drm/i915: Support LRC context single submission
>   drm/i915: Introduce GVT context creation API
> 
>  drivers/gpu/drm/i915/Kconfig|  19 
>  drivers/gpu/drm/i915/Makefile   |   5 +
>  drivers/gpu/drm/i915/gvt/Makefile   |   5 +
>  drivers/gpu/drm/i915/gvt/debug.h|  34 ++
>  drivers/gpu/drm/i915/gvt/gvt.c  | 181
> 
>  drivers/gpu/drm/i915/gvt/gvt.h  |  75 +
>  drivers/gpu/drm/i915/gvt/hypercall.h|  38 +++
>  drivers/gpu/drm/i915/gvt/mpt.h  |  49 +
>  drivers/gpu/drm/i915/i915_dma.c |  17 ++-
>  drivers/gpu/drm/i915/i915_drv.h |  15 +++
>  drivers/gpu/drm/i915/i915_gem_context.c |  35 ++
>  drivers/gpu/drm/i915/i915_gem_gtt.c |  11 +-
>  drivers/gpu/drm/i915/i915_params.c  |   5 +
>  drivers/gpu/drm/i915/i915_params.h  |   1 +
>  drivers/gpu/drm/i915/i915_pvinfo.h  | 116 
>  drivers/gpu/drm/i915/i915_vgpu.c|  32 --
>  drivers/gpu/drm/i915/i915_vgpu.h|  90 +---
>  drivers/gpu/drm/i915/intel_gvt.c|  90 
>  drivers/gpu/drm/i915/intel_gvt.h|  71 +
>  drivers/gpu/drm/i915/intel_lrc.c|  55 +++---
>  drivers/gpu/drm/i915/intel_lrc.h|  16 +++
>  21 files changed, 841 insertions(+), 119 deletions(-)  create mode 100644
> drivers/gpu/drm/i915/gvt/Makefile  create mode 100644
> drivers/gpu/drm/i915/gvt/debug.h  create mode 100644
> drivers/gpu/drm/i915/gvt/gvt.c  create mode 100644
> 

[Intel-gfx] [PATCH 9/9] drm/i915: Introduce GVT context creation API

[Zhi Wang]

GVT workload scheduler needs special host LRC contexts, the so called
"shadow LRC context" to submit guest workload to host i915. During the
guest workload submission, GVT fills the shadow LRC context with the
content of guest LRC context: engine context is copied without changes,
ring context is mostly owned by host i915.

The GVT-g workload scheduler flow:

 +---+   +---+
 | GVT Guest |   | GVT Guest |
 +-+-^---+   +-+-^---+
   | | | |
   | | GVT-g   | | GVT-g
vELSP write| | emulates vELSP write| | emulates
   | | Execlist/CSB| | Execlist/CSB
   | | Status  | | Status
   | | | |
+--v-+-v-+-+
|   GVT Virtual Execlist Submission|
+--+---+---+
   |   |
   | Per-VM/Ring Workoad Q | Per-VM/Ring Workload Q
   +-+--+  ++
   +---v+^ +---v+
   |GVT Workload|... | |GVT Workload|...
   ++| ++
 |
 | Pick Workload from Q
++-+
|GVT Workload Scheduler|
++-+
 | * Shadow guest LRC context
  +--v--+  * Shadow guest ring buffer
  | GVT Context |  * Scan/Patch guest RB instructions
  +--+--+
 |
 v
  Host i915 GEM Submission

v6:

- Make GVT code as dead code when !CONFIG_DRM_I915_GVT. (Chris)

v5:
- Only compile this feature when CONFIG_DRM_I915_GVT is enabled. (Tvrtko)
- Rebase the code into new repo.
- Add a comment about the ring buffer size. (Joonas)

v2:

Mostly based on Daniel's idea. Call the refactored core logic of GEM
context creation service and LRC context creation service to create the GVT
context.

Signed-off-by: Zhi Wang 
---
 drivers/gpu/drm/i915/i915_gem_context.c | 32 
 drivers/gpu/drm/i915/intel_lrc.c|  4 ++--
 2 files changed, 34 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index d9d7779..c0259d7 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -342,6 +342,38 @@ i915_gem_create_context(struct drm_device *dev,
return ctx;
 }
 
+/**
+ * i915_gem_create_gvt_context - create a GVT GEM context
+ * @dev: drm device *
+ *
+ * This function is used to create a GVT specific GEM context.
+ *
+ * Returns:
+ * pointer to i915_gem_context on success, error pointer if failed
+ *
+ */
+struct i915_gem_context *
+i915_gem_create_gvt_context(struct drm_device *dev)
+{
+   struct i915_gem_context *ctx;
+
+   if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
+   return ERR_PTR(-ENODEV);
+
+   mutex_lock(>struct_mutex);
+
+   ctx = i915_gem_create_context(dev, NULL);
+   if (IS_ERR(ctx))
+   goto out;
+
+   ctx->enable_lrc_status_change_notification = true;
+   ctx->enable_lrc_single_submission = true;
+   ctx->lrc_ring_buffer_size = 512 * PAGE_SIZE; /* Max ring buffer size */
+out:
+   mutex_unlock(>struct_mutex);
+   return ctx;
+}
+
 static void i915_gem_context_unpin(struct i915_gem_context *ctx,
   struct intel_engine_cs *engine)
 {
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 407159c..ce707ea 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -452,13 +452,13 @@ static void execlists_context_unqueue(struct 
intel_engine_cs *engine)
 * req0 (after merged) ctx requires single
 * submission, stop picking
 */
-   if (req0->ctx->lrc_ctx_single_submission)
+   if (req0->ctx->enable_lrc_single_submission)
break;
/*
 * req0 ctx doesn't require single submission,
 * but next req ctx requires, stop picking
 */
-   if (cursor->ctx->lrc_ctx_single_submission)
+   if (cursor->ctx->enable_lrc_single_submission)
break;

[Intel-gfx] [PATCH 8/9] drm/i915: Support LRC context single submission

[Zhi Wang]

This patch introduces the support of LRC context signle submission.
As GVT context may come from different guests, which requires different
configuration of render registers. It can't be combined into a dual ELSP
submission combo.

Only GVT-g will create this kinds of GEM context currently.

v6:
- Make GVT code as dead code when !CONFIG_DRM_I915_GVT. (Chris)

v5:

- Only compile this feature when CONFIG_DRM_I915_GVT=y. (Tvrtko)

Signed-off-by: Zhi Wang 
---
 drivers/gpu/drm/i915/i915_drv.h  |  1 +
 drivers/gpu/drm/i915/intel_lrc.c | 15 +++
 2 files changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index dee72d3..92d01e3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -882,6 +882,7 @@ struct i915_gem_context {
u32 lrc_ring_buffer_size;
u32 lrc_addressing_mode_bits;
bool enable_lrc_status_change_notification;
+   bool enable_lrc_single_submission;
 
struct list_head link;
 
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 96d20c8..407159c 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -446,6 +446,21 @@ static void execlists_context_unqueue(struct 
intel_engine_cs *engine)
i915_gem_request_unreference(req0);
req0 = cursor;
} else {
+   /* Compiler will do the dead-code elimination */
+   if (IS_ENABLED(CONFIG_DRM_I915_GVT)) {
+   /*
+* req0 (after merged) ctx requires single
+* submission, stop picking
+*/
+   if (req0->ctx->lrc_ctx_single_submission)
+   break;
+   /*
+* req0 ctx doesn't require single submission,
+* but next req ctx requires, stop picking
+*/
+   if (cursor->ctx->lrc_ctx_single_submission)
+   break;
+   }
req1 = cursor;
WARN_ON(req1->elsp_submitted);
break;
-- 
1.9.1

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[Intel-gfx] [PATCH 5/9] drm/i915: Make ring buffer size of a LRC context configurable

[Zhi Wang]

This patch introduces an option for configuring the ring buffer size
of a LRC context after the context creation.

Signed-off-by: Zhi Wang 
---
 drivers/gpu/drm/i915/i915_drv.h | 1 +
 drivers/gpu/drm/i915/i915_gem_context.c | 1 +
 drivers/gpu/drm/i915/intel_lrc.c| 3 ++-
 3 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bdf499f..a4af035 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -878,6 +878,7 @@ struct i915_gem_context {
int pin_count;
bool initialised;
} engine[I915_NUM_ENGINES];
+   u32 lrc_ring_buffer_size;
 
struct list_head link;
 
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index a3b11aa..1663981 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -295,6 +295,7 @@ __create_hw_context(struct drm_device *dev,
ctx->remap_slice = ALL_L3_SLICES(dev_priv);
 
ctx->hang_stats.ban_period_seconds = DRM_I915_CTX_BAN_PERIOD;
+   ctx->lrc_ring_buffer_size = 4 * PAGE_SIZE;
 
return ctx;
 
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 5c191a1..72a0cca 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2484,7 +2484,8 @@ static int execlists_context_deferred_alloc(struct 
i915_gem_context *ctx,
return PTR_ERR(ctx_obj);
}
 
-   ringbuf = intel_engine_create_ringbuffer(engine, 4 * PAGE_SIZE);
+   ringbuf = intel_engine_create_ringbuffer(engine,
+   ctx->lrc_ring_buffer_size);
if (IS_ERR(ringbuf)) {
ret = PTR_ERR(ringbuf);
goto error_deref_obj;
-- 
1.9.1

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[Intel-gfx] [PATCH 6/9] drm/i915: Make addressing mode bits in context descriptor configurable

[Zhi Wang]

Currently the addressing mode bit in context descriptor is statically
generated from the configuration of system-wide PPGTT usage model.

GVT-g will load the PPGTT shadow page table by itself and probably one
guest is using a different addressing mode with i915 host. The addressing
mode bits of a LRC context should be configurable under this case.

v6:

- Directly save the addressing mode bits inside i915_gem_context. (Chris)
- Move the LRC context addressing mode bits into intel_lrc.h. (Chris)

v5:

- Change USES_FULL_48BIT(dev) to USES_FULL_48BIT(dev_priv) (Tvrtko)

Signed-off-by: Zhi Wang 
---
 drivers/gpu/drm/i915/i915_drv.h |  1 +
 drivers/gpu/drm/i915/i915_gem_context.c |  2 ++
 drivers/gpu/drm/i915/intel_lrc.c| 13 +
 drivers/gpu/drm/i915/intel_lrc.h| 11 +++
 4 files changed, 15 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a4af035..f6cb60a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -879,6 +879,7 @@ struct i915_gem_context {
bool initialised;
} engine[I915_NUM_ENGINES];
u32 lrc_ring_buffer_size;
+   u32 lrc_addressing_mode_bits;
 
struct list_head link;
 
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 1663981..d9d7779 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -296,6 +296,8 @@ __create_hw_context(struct drm_device *dev,
 
ctx->hang_stats.ban_period_seconds = DRM_I915_CTX_BAN_PERIOD;
ctx->lrc_ring_buffer_size = 4 * PAGE_SIZE;
+   ctx->lrc_addressing_mode_bits = GEN8_CTX_ADDRESSING_MODE(dev_priv) <<
+   GEN8_CTX_ADDRESSING_MODE_SHIFT;
 
return ctx;
 
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 72a0cca..ffb436c 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -208,16 +208,6 @@
 } while (0)
 
 enum {
-   ADVANCED_CONTEXT = 0,
-   LEGACY_32B_CONTEXT,
-   ADVANCED_AD_CONTEXT,
-   LEGACY_64B_CONTEXT
-};
-#define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
-#define GEN8_CTX_ADDRESSING_MODE(dev)  (USES_FULL_48BIT_PPGTT(dev) ?\
-   LEGACY_64B_CONTEXT :\
-   LEGACY_32B_CONTEXT)
-enum {
FAULT_AND_HANG = 0,
FAULT_AND_HALT, /* Debug only */
FAULT_AND_STREAM,
@@ -281,8 +271,6 @@ logical_ring_init_platform_invariants(struct 
intel_engine_cs *engine)
(engine->id == VCS || engine->id == 
VCS2);
 
engine->ctx_desc_template = GEN8_CTX_VALID;
-   engine->ctx_desc_template |= GEN8_CTX_ADDRESSING_MODE(dev_priv) <<
-  GEN8_CTX_ADDRESSING_MODE_SHIFT;
if (IS_GEN8(dev_priv))
engine->ctx_desc_template |= GEN8_CTX_L3LLC_COHERENT;
engine->ctx_desc_template |= GEN8_CTX_PRIVILEGE;
@@ -326,6 +314,7 @@ intel_lr_context_descriptor_update(struct i915_gem_context 
*ctx,
BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (1<ctx_desc_template;   /* bits  0-11 */
+   desc |= ctx->lrc_addressing_mode_bits;  /* bits  3-4  */
desc |= ce->lrc_vma->node.start + LRC_PPHWSP_PN * PAGE_SIZE;
/* bits 12-31 */
desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT;   /* bits 32-52 */
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index a8db42a..e133c33 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -28,6 +28,17 @@
 
 #define GEN8_LR_CONTEXT_ALIGN 4096
 
+enum {
+   ADVANCED_CONTEXT = 0,
+   LEGACY_32B_CONTEXT,
+   ADVANCED_AD_CONTEXT,
+   LEGACY_64B_CONTEXT
+};
+#define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
+#define GEN8_CTX_ADDRESSING_MODE(dev_priv) (USES_FULL_48BIT_PPGTT(dev_priv) ?\
+   LEGACY_64B_CONTEXT : \
+   LEGACY_32B_CONTEXT)
+
 /* Execlists regs */
 #define RING_ELSP(ring)_MMIO((ring)->mmio_base 
+ 0x230)
 #define RING_EXECLIST_STATUS_LO(ring)  _MMIO((ring)->mmio_base + 0x234)
-- 
1.9.1

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[Intel-gfx] [PATCH 7/9] drm/i915: Introduce execlist context status change notification

[Zhi Wang]

This patch introduces an approach to track the execlist context status
change.

GVT-g uses GVT context as the "shadow context". The content inside GVT
context will be copied back to guest after the context is idle. So GVT-g
has to know the status of the execlist context.

This function is configurable in the context creation service. Currently,
Only GVT-g will create the "status-change-notification" enabled GEM
context.

v6:

- When !CONFIG_DRM_I915_GVT, make GVT code as dead code then compiler
could automatically eliminate them for us. (Chris)
- Always initialize the notifier header, so it could be switched on/off
at runtime. (Chris)

v5:

- Only compile this feature when CONFIG_DRM_I915_GVT is enabled.(Tvrtko)

Signed-off-by: Zhi Wang 
---
 drivers/gpu/drm/i915/i915_drv.h  |  2 ++
 drivers/gpu/drm/i915/intel_lrc.c | 24 
 drivers/gpu/drm/i915/intel_lrc.h |  5 +
 3 files changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f6cb60a..dee72d3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -877,9 +877,11 @@ struct i915_gem_context {
u64 lrc_desc;
int pin_count;
bool initialised;
+   struct atomic_notifier_head status_notifier;
} engine[I915_NUM_ENGINES];
u32 lrc_ring_buffer_size;
u32 lrc_addressing_mode_bits;
+   bool enable_lrc_status_change_notification;
 
struct list_head link;
 
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index ffb436c..96d20c8 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -404,6 +404,22 @@ static void execlists_submit_requests(struct 
drm_i915_gem_request *rq0,
spin_unlock_irq(_priv->uncore.lock);
 }
 
+static inline void execlists_context_status_change(
+   struct drm_i915_gem_request *rq,
+   unsigned long status)
+{
+   /* The compiler should be fine with the dead-code elimination */
+   if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
+   return;
+
+   if (!rq->ctx->enable_lrc_status_change_notification)
+   return;
+
+   atomic_notifier_call_chain(
+   >ctx->engine[rq->engine->id].status_notifier,
+   status, rq);
+}
+
 static void execlists_context_unqueue(struct intel_engine_cs *engine)
 {
struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;
@@ -439,6 +455,11 @@ static void execlists_context_unqueue(struct 
intel_engine_cs *engine)
if (unlikely(!req0))
return;
 
+   execlists_context_status_change(req0, CONTEXT_SCHEDULE_IN);
+
+   if (req1)
+   execlists_context_status_change(req1, CONTEXT_SCHEDULE_IN);
+
if (req0->elsp_submitted & engine->idle_lite_restore_wa) {
/*
 * WaIdleLiteRestore: make sure we never cause a lite restore
@@ -477,6 +498,8 @@ execlists_check_remove_request(struct intel_engine_cs 
*engine, u32 ctx_id)
if (--head_req->elsp_submitted > 0)
return 0;
 
+   execlists_context_status_change(head_req, CONTEXT_SCHEDULE_OUT);
+
list_del(_req->execlist_link);
i915_gem_request_unreference(head_req);
 
@@ -2489,6 +2512,7 @@ static int execlists_context_deferred_alloc(struct 
i915_gem_context *ctx,
ce->ringbuf = ringbuf;
ce->state = ctx_obj;
ce->initialised = engine->init_context == NULL;
+   ATOMIC_INIT_NOTIFIER_HEAD(>status_notifier);
 
return 0;
 
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index e133c33..7a7ae8d 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -68,6 +68,11 @@ enum {
 #define GEN8_CSB_READ_PTR(csb_status) \
(((csb_status) & GEN8_CSB_READ_PTR_MASK) >> 8)
 
+enum {
+   CONTEXT_SCHEDULE_IN = 0,
+   CONTEXT_SCHEDULE_OUT,
+};
+
 /* Logical Rings */
 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request 
*request);
 int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request);
-- 
1.9.1

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[Intel-gfx] [PATCH 4/9] drm/i915: Introduce host graphics memory partition for GVT-g

[Zhi Wang]

From: Bing Niu 

This patch introduces host graphics memory partition when GVT-g
is enabled.

Under GVT-g, i915 host driver only owned limited graphics resources,
others are managed by GVT-g resource allocator and kept for other vGPUs.

v6:

- Remove kernel parameters used to configure GGTT owned by host. (Chris)
- Other coding style comments from Chris.
- Add more comments for reviewer.

v3:

- Remove fence partition, will use i915 fence stealing in future.(Kevin)
- Santinize GVT host gm kernel parameters. (Joonas)

v2:
- Address all coding-style comments from Joonas previously.
- Fix errors and warnning reported by checkpatch.pl. (Joonas)
- Move the graphs into the header files. (Daniel)

Signed-off-by: Bing Niu 
Signed-off-by: Zhi Wang 
---
 drivers/gpu/drm/i915/i915_vgpu.c | 23 +--
 drivers/gpu/drm/i915/intel_gvt.h | 25 +
 2 files changed, 42 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 5312816..0d891a3 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -189,14 +189,25 @@ int intel_vgt_balloon(struct drm_i915_private *dev_priv)
unsigned long unmappable_base, unmappable_size, unmappable_end;
int ret;
 
-   if (!intel_vgpu_active(dev_priv))
+   if (intel_gvt_active(dev_priv)) {
+   /* Retrieve GGTT partition information from macros */
+   mappable_base = 0;
+   mappable_size = INTEL_GVT_HOST_LOW_GM_SIZE;
+   unmappable_base = dev_priv->ggtt.mappable_end;
+   unmappable_size = INTEL_GVT_HOST_HIGH_GM_SIZE;
+   } else if (intel_vgpu_active(dev_priv)) {
+   /* Retrieve GGTT partition information from PVINFO */
+   mappable_base = I915_READ(
+   vgtif_reg(avail_rs.mappable_gmadr.base));
+   mappable_size = I915_READ(
+   vgtif_reg(avail_rs.mappable_gmadr.size));
+   unmappable_base = I915_READ(
+   vgtif_reg(avail_rs.nonmappable_gmadr.base));
+   unmappable_size = I915_READ(
+   vgtif_reg(avail_rs.nonmappable_gmadr.size));
+   } else
return 0;
 
-   mappable_base = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.base));
-   mappable_size = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.size));
-   unmappable_base = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.base));
-   unmappable_size = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.size));
-
mappable_end = mappable_base + mappable_size;
unmappable_end = unmappable_base + unmappable_size;
 
diff --git a/drivers/gpu/drm/i915/intel_gvt.h b/drivers/gpu/drm/i915/intel_gvt.h
index b9b361b..f0b9aac 100644
--- a/drivers/gpu/drm/i915/intel_gvt.h
+++ b/drivers/gpu/drm/i915/intel_gvt.h
@@ -24,6 +24,31 @@
 #ifndef _INTEL_GVT_H_
 #define _INTEL_GVT_H_
 
+/*
+ * Under GVT-g, i915 host driver only owned limited graphics resources,
+ * others are managed by GVT-g resource allocator and kept for other vGPUs.
+ *
+ * For graphics memory space partition, a typical layout looks like:
+ *
+ * +---+---+--+---+
+ * |* Host |   *GVT-g Resource |* Host|   *GVT-g Resource |
+ * | Owned |   Allocator Managed   | Owned|   Allocator Managed   |
+ * |   |   |  |   |
+ * +---+---+--+---+---+
+ * |   |   |   |   |  |   |   |   |
+ * | i915  | vm 1  | vm 2  | vm 3  | i915 | vm 1  | vm 2  | vm 3  |
+ * |   |   |   |   |  |   |   |   |
+ * +---+---+---+--+---+---+---+
+ * |   Aperture|Hidden|
+ * +---+--+
+ * |   GGTT memory space  |
+ * +--+
+ */
+
+/* GGTT memory space owned by host */
+#define INTEL_GVT_HOST_LOW_GM_SIZE (96 * 1024 * 1024)
+#define INTEL_GVT_HOST_HIGH_GM_SIZE (384 * 1024 * 1024)
+
 #ifdef CONFIG_DRM_I915_GVT
 #include "gvt/gvt.h"
 extern int intel_gvt_init(struct drm_i915_private *dev_priv);
-- 
1.9.1

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[Intel-gfx] [PATCH 3/9] drm/i915: gvt: Introduce the basic architecture of GVT-g

[Zhi Wang]

This patch introduces the very basic framework of GVT-g device model,
includes basic prototypes, definitions, initialization.

v6:
- Refine introduction in Kconfig. (Chris)
- The exposed API functions will take struct intel_gvt * instead of
void *. (Chris/Tvrtko)
- Remove most memebers of strct intel_gvt_device_info. Will add them
in the device model patches.(Chris)
- Remove gvt_info() and gvt_err() in debug.h. (Chris)
- Move GVT kernel parameter into i915_params. (Chris)
- Remove include/drm/i915_gvt.h, as GVT-g will be built within i915.
- Remove the redundant struct i915_gvt *, as the functions in i915
will directly take struct intel_gvt *.
- Add more comments for reviewer.

v5:
Take Tvrtko's comments:
- Fix the misspelled words in Kconfig
- Let functions take drm_i915_private * instead of struct drm_device *
- Remove redundant prints/local varible initialization

v3:
Take Joonas' comments:
- Change file name i915_gvt.* to intel_gvt.*
- Move GVT kernel parameter into intel_gvt.c
- Remove redundant debug macros
- Change error handling style
- Add introductions for some stub functions
- Introduce drm/i915_gvt.h.

Take Kevin's comments:
- Move GVT-g host/guest check into intel_vgt_balloon in i915_gem_gtt.c

v2:
- Introduce i915_gvt.c.
It's necessary to introduce the stubs between i915 driver and GVT-g host,
as GVT-g components is configurable in kernel config. When disabled, the
stubs here do nothing.

Take Joonas' comments:
- Replace boolean return value with int.
- Replace customized info/warn/debug macros with DRM macros.
- Document all non-static functions like i915.
- Remove empty and unused functions.
- Replace magic number with marcos.
- Set GVT-g in kernel config to "n" by default.

Signed-off-by: Zhi Wang 
---
 drivers/gpu/drm/i915/Kconfig |  19 
 drivers/gpu/drm/i915/Makefile|   5 +
 drivers/gpu/drm/i915/gvt/Makefile|   5 +
 drivers/gpu/drm/i915/gvt/debug.h |  34 +++
 drivers/gpu/drm/i915/gvt/gvt.c   | 181 +++
 drivers/gpu/drm/i915/gvt/gvt.h   |  75 +++
 drivers/gpu/drm/i915/gvt/hypercall.h |  38 
 drivers/gpu/drm/i915/gvt/mpt.h   |  49 ++
 drivers/gpu/drm/i915/i915_dma.c  |  17 +++-
 drivers/gpu/drm/i915/i915_drv.h  |  10 ++
 drivers/gpu/drm/i915/i915_params.c   |   5 +
 drivers/gpu/drm/i915/i915_params.h   |   1 +
 drivers/gpu/drm/i915/intel_gvt.c |  90 +
 drivers/gpu/drm/i915/intel_gvt.h |  46 +
 14 files changed, 571 insertions(+), 4 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gvt/Makefile
 create mode 100644 drivers/gpu/drm/i915/gvt/debug.h
 create mode 100644 drivers/gpu/drm/i915/gvt/gvt.c
 create mode 100644 drivers/gpu/drm/i915/gvt/gvt.h
 create mode 100644 drivers/gpu/drm/i915/gvt/hypercall.h
 create mode 100644 drivers/gpu/drm/i915/gvt/mpt.h
 create mode 100644 drivers/gpu/drm/i915/intel_gvt.c
 create mode 100644 drivers/gpu/drm/i915/intel_gvt.h

diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 29a32b1..e4fd9da 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -57,6 +57,25 @@ config DRM_I915_USERPTR
 
  If in doubt, say "Y".
 
+config DRM_I915_GVT
+bool "Enable Intel GVT-g graphics virtualization host support"
+depends on DRM_I915
+default n
+help
+ Choose this option if you want to enable Intel GVT-g graphics
+ virtualization technology host support with integrated graphics.
+ With GVT-g, it's possible to have one integrated graphics
+ device shared by multiple VMs under different hypervisors.
+
+ Note that at least one hypervisor like Xen or KVM is required for
+ this driver to work, and it only supports newer device from
+ Broadwell+. For further information and setup guide, you can
+ visit: http://01.org/zh/igvt-g.
+
+ The first version is still preliminary. Use it under you own risk.
+
+ If in doubt, say "N".
+
 menu "drm/i915 Debugging"
 depends on DRM_I915
 depends on EXPERT
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 7e29444..276abf1 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -104,6 +104,11 @@ i915-y += i915_vgpu.o
 # legacy horrors
 i915-y += i915_dma.o
 
+ifeq ($(CONFIG_DRM_I915_GVT),y)
+i915-y += intel_gvt.o
+include $(src)/gvt/Makefile
+endif
+
 obj-$(CONFIG_DRM_I915)  += i915.o
 
 CFLAGS_i915_trace_points.o := -I$(src)
diff --git a/drivers/gpu/drm/i915/gvt/Makefile 
b/drivers/gpu/drm/i915/gvt/Makefile
new file mode 100644
index 000..d0f21a6
--- /dev/null
+++ b/drivers/gpu/drm/i915/gvt/Makefile
@@ -0,0 +1,5 @@
+GVT_DIR := gvt
+GVT_SOURCE := gvt.o
+
+ccflags-y  += -I$(src) -I$(src)/$(GVT_DIR) -Wall
+i915-y+= $(addprefix $(GVT_DIR)/, $(GVT_SOURCE))
diff --git a/drivers/gpu/drm/i915/gvt/debug.h 

[Intel-gfx] [PATCH 1/9] drm/i915: Factor out i915_pvinfo.h

[Zhi Wang]

As the PVINFO page definition is used by both GVT-g guest (vGPU) and GVT-g
host (GVT-g kernel device model), factor it out for better code structure.

v3:

Take Joonas's comments:
- Use offsetof to calculate the member offset of PVINFO structure

Signed-off-by: Zhi Wang 
---
 drivers/gpu/drm/i915/i915_pvinfo.h | 116 +
 drivers/gpu/drm/i915/i915_vgpu.h   |  86 +--
 2 files changed, 117 insertions(+), 85 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/i915_pvinfo.h

diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h 
b/drivers/gpu/drm/i915/i915_pvinfo.h
new file mode 100644
index 000..eb45afb
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -0,0 +1,116 @@
+/*
+ * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 
THE
+ * SOFTWARE.
+ */
+
+#ifndef _I915_PVINFO_H_
+#define _I915_PVINFO_H_
+
+/* The MMIO offset of the shared info between guest and host emulator */
+#define VGT_PVINFO_PAGE0x78000
+#define VGT_PVINFO_SIZE0x1000
+
+/*
+ * The following structure pages are defined in GEN MMIO space
+ * for virtualization. (One page for now)
+ */
+#define VGT_MAGIC 0x4776544776544776ULL/* 'vGTvGTvG' */
+#define VGT_VERSION_MAJOR 1
+#define VGT_VERSION_MINOR 0
+
+#define INTEL_VGT_IF_VERSION_ENCODE(major, minor) ((major) << 16 | (minor))
+#define INTEL_VGT_IF_VERSION \
+   INTEL_VGT_IF_VERSION_ENCODE(VGT_VERSION_MAJOR, VGT_VERSION_MINOR)
+
+/*
+ * notifications from guest to vgpu device model
+ */
+enum vgt_g2v_type {
+   VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE = 2,
+   VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY,
+   VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE,
+   VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY,
+   VGT_G2V_EXECLIST_CONTEXT_CREATE,
+   VGT_G2V_EXECLIST_CONTEXT_DESTROY,
+   VGT_G2V_MAX,
+};
+
+struct vgt_if {
+   uint64_t magic; /* VGT_MAGIC */
+   uint16_t version_major;
+   uint16_t version_minor;
+   uint32_t vgt_id;/* ID of vGT instance */
+   uint32_t rsv1[12];  /* pad to offset 0x40 */
+   /*
+*  Data structure to describe the balooning info of resources.
+*  Each VM can only have one portion of continuous area for now.
+*  (May support scattered resource in future)
+*  (starting from offset 0x40)
+*/
+   struct {
+   /* Aperture register balooning */
+   struct {
+   uint32_t base;
+   uint32_t size;
+   } mappable_gmadr;   /* aperture */
+   /* GMADR register balooning */
+   struct {
+   uint32_t base;
+   uint32_t size;
+   } nonmappable_gmadr;/* non aperture */
+   /* allowed fence registers */
+   uint32_t fence_num;
+   uint32_t rsv2[3];
+   } avail_rs; /* available/assigned resource */
+   uint32_t rsv3[0x200 - 24];  /* pad to half page */
+   /*
+* The bottom half page is for response from Gfx driver to hypervisor.
+*/
+   uint32_t rsv4;
+   uint32_t display_ready; /* ready for display owner switch */
+
+   uint32_t rsv5[4];
+
+   uint32_t g2v_notify;
+   uint32_t rsv6[7];
+
+   struct {
+   uint32_t lo;
+   uint32_t hi;
+   } pdp[4];
+
+   uint32_t execlist_context_descriptor_lo;
+   uint32_t execlist_context_descriptor_hi;
+
+   uint32_t  rsv7[0x200 - 24];/* pad to one page */
+} __packed;
+
+#define _vgtif_reg(x) \
+   (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x))
+
+#define vgtif_reg(x) \
+   _MMIO(_vgtif_reg(x))
+
+/* vGPU display status to be used by the host side */
+#define VGT_DRV_DISPLAY_NOT_READY 0
+#define VGT_DRV_DISPLAY_READY 1  /* ready 

[Intel-gfx] [PATCH 0/9] Introduce the implementation of GVT context

[Zhi Wang]

Mostly this patchset introduces the implementation of GVT context. GVT
context is a special GEM context used by GVT-g. GVT-g uses it as the shadow
context.It doesn't have a drm client nor a PPGTT. And it requires a larger
ring buffer with several special features need by GVT-g workload scheduler
like context status change notification, context single submission...

v6:

- Take Chris comments.

v5:

- Drop PPGTT related patches.
- Let most functions take struct drm_i915_private *
- Fixed some misspelled words in Kconfig
- Only complied some feature when CONFIG_DRM_I915_GVT=y
- Drop the fecne related changes, will send it after this series.

v4:

- Based on the latest drm-intel-nightly branch.
- Drop PPGTT refactor patches. (GVT-g will use LRI to load PDPs)
- Drop i915_gem_context() refactor patches, reuse kernel context functions.
  (Dave Gordon)
- Drop context allocation params and refactor as the lrc deferred
  allocation function has been refactored in another styles.
- Re-wrtie GVT context creation function

Difference from community release
-

This patchset is different from regular iGVT-g code release[4], which
is still based on old host-mediated architecture. Furthermore, this
patchset only supports BDW whereas code release supports HSW/BDW/SKL.
We will add SKL support later based on this RFC code and HSW support
will be dropped.

Internally we tested this RFC patchset with both linux and windows VM
and the architecture changes work fine.

Acknowledgment
---

iGVT-g implementation is several years effort and many people
contributed to the code. There names are not here yet. In later formal
patchset we will reflect individual's contribution.

Meanwhile, in the previous iGVT-g related discussion, Daniel, Chris
and Joonas ever gave very good inputs. We appreciate them and look
forward to more comments/suggestions from community.

We are trying to get more familiar with i915 but may still have gaps.
We are willing to adopt suggestions to keep improving. We hope to work
with community together to make iGVT-g a great component in i915 to
support graphics virtualization. Thanks!

Reference
-

[1] https://01.org/igvt-g
[2] http://lists.freedesktop.org/archives/intel-gfx/2014-September/053098.html
[3] http://lists.freedesktop.org/archives/intel-gfx/2015-September/075397.html

Bing Niu (1):
  drm/i915: Introduce host graphics memory partition for GVT-g

Zhi Wang (8):
  drm/i915: Factor out i915_pvinfo.h
  drm/i915: Fold vGPU active check into inner functions
  drm/i915: gvt: Introduce the basic architecture of GVT-g
  drm/i915: Make ring buffer size of a LRC context configurable
  drm/i915: Make addressing mode bits in context descriptor configurable
  drm/i915: Introduce execlist context status change notification
  drm/i915: Support LRC context single submission
  drm/i915: Introduce GVT context creation API

 drivers/gpu/drm/i915/Kconfig|  19 
 drivers/gpu/drm/i915/Makefile   |   5 +
 drivers/gpu/drm/i915/gvt/Makefile   |   5 +
 drivers/gpu/drm/i915/gvt/debug.h|  34 ++
 drivers/gpu/drm/i915/gvt/gvt.c  | 181 
 drivers/gpu/drm/i915/gvt/gvt.h  |  75 +
 drivers/gpu/drm/i915/gvt/hypercall.h|  38 +++
 drivers/gpu/drm/i915/gvt/mpt.h  |  49 +
 drivers/gpu/drm/i915/i915_dma.c |  17 ++-
 drivers/gpu/drm/i915/i915_drv.h |  15 +++
 drivers/gpu/drm/i915/i915_gem_context.c |  35 ++
 drivers/gpu/drm/i915/i915_gem_gtt.c |  11 +-
 drivers/gpu/drm/i915/i915_params.c  |   5 +
 drivers/gpu/drm/i915/i915_params.h  |   1 +
 drivers/gpu/drm/i915/i915_pvinfo.h  | 116 
 drivers/gpu/drm/i915/i915_vgpu.c|  32 --
 drivers/gpu/drm/i915/i915_vgpu.h|  90 +---
 drivers/gpu/drm/i915/intel_gvt.c|  90 
 drivers/gpu/drm/i915/intel_gvt.h|  71 +
 drivers/gpu/drm/i915/intel_lrc.c|  55 +++---
 drivers/gpu/drm/i915/intel_lrc.h|  16 +++
 21 files changed, 841 insertions(+), 119 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gvt/Makefile
 create mode 100644 drivers/gpu/drm/i915/gvt/debug.h
 create mode 100644 drivers/gpu/drm/i915/gvt/gvt.c
 create mode 100644 drivers/gpu/drm/i915/gvt/gvt.h
 create mode 100644 drivers/gpu/drm/i915/gvt/hypercall.h
 create mode 100644 drivers/gpu/drm/i915/gvt/mpt.h
 create mode 100644 drivers/gpu/drm/i915/i915_pvinfo.h
 create mode 100644 drivers/gpu/drm/i915/intel_gvt.c
 create mode 100644 drivers/gpu/drm/i915/intel_gvt.h

-- 
1.9.1

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[Intel-gfx] [PATCH 2/9] drm/i915: Fold vGPU active check into inner functions

[Zhi Wang]

v5:
- Let functions take struct drm_i915_private *. (Tvrtko)

- Fold vGPU related active check into the inner functions. (Kevin)

Signed-off-by: Zhi Wang 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 11 ---
 drivers/gpu/drm/i915/i915_vgpu.c| 13 +
 drivers/gpu/drm/i915/i915_vgpu.h|  4 ++--
 3 files changed, 15 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 4668477..6f203fa 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2732,11 +2732,9 @@ static int i915_gem_setup_global_gtt(struct drm_device 
*dev,
i915_address_space_init(>base, dev_priv);
ggtt->base.total += PAGE_SIZE;
 
-   if (intel_vgpu_active(dev_priv)) {
-   ret = intel_vgt_balloon(dev);
-   if (ret)
-   return ret;
-   }
+   ret = intel_vgt_balloon(dev_priv);
+   if (ret)
+   return ret;
 
if (!HAS_LLC(dev))
ggtt->base.mm.color_adjust = i915_gtt_color_adjust;
@@ -2836,8 +2834,7 @@ void i915_ggtt_cleanup_hw(struct drm_device *dev)
i915_gem_cleanup_stolen(dev);
 
if (drm_mm_initialized(>base.mm)) {
-   if (intel_vgpu_active(dev_priv))
-   intel_vgt_deballoon();
+   intel_vgt_deballoon(dev_priv);
 
drm_mm_takedown(>base.mm);
list_del(>base.global_link);
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index d5a7a5e..5312816 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -101,10 +101,13 @@ static struct _balloon_info_ bl_info;
  * This function is called to deallocate the ballooned-out graphic memory, when
  * driver is unloaded or when ballooning fails.
  */
-void intel_vgt_deballoon(void)
+void intel_vgt_deballoon(struct drm_i915_private *dev_priv)
 {
int i;
 
+   if (!intel_vgpu_active(dev_priv))
+   return;
+
DRM_DEBUG("VGT deballoon.\n");
 
for (i = 0; i < 4; i++) {
@@ -177,9 +180,8 @@ static int vgt_balloon_space(struct drm_mm *mm,
  * Returns:
  * zero on success, non-zero if configuration invalid or ballooning failed
  */
-int intel_vgt_balloon(struct drm_device *dev)
+int intel_vgt_balloon(struct drm_i915_private *dev_priv)
 {
-   struct drm_i915_private *dev_priv = to_i915(dev);
struct i915_ggtt *ggtt = _priv->ggtt;
unsigned long ggtt_end = ggtt->base.start + ggtt->base.total;
 
@@ -187,6 +189,9 @@ int intel_vgt_balloon(struct drm_device *dev)
unsigned long unmappable_base, unmappable_size, unmappable_end;
int ret;
 
+   if (!intel_vgpu_active(dev_priv))
+   return 0;
+
mappable_base = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.base));
mappable_size = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.size));
unmappable_base = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.base));
@@ -258,6 +263,6 @@ int intel_vgt_balloon(struct drm_device *dev)
 
 err:
DRM_ERROR("VGT balloon fail\n");
-   intel_vgt_deballoon();
+   intel_vgt_deballoon(dev_priv);
return ret;
 }
diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
index 07e67d5..f8917c6 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.h
+++ b/drivers/gpu/drm/i915/i915_vgpu.h
@@ -27,7 +27,7 @@
 #include "i915_pvinfo.h"
 
 extern void i915_check_vgpu(struct drm_i915_private *dev_priv);
-extern int intel_vgt_balloon(struct drm_device *dev);
-extern void intel_vgt_deballoon(void);
+extern int intel_vgt_balloon(struct drm_i915_private *dev_priv);
+extern void intel_vgt_deballoon(struct drm_i915_private *dev_priv);
 
 #endif /* _I915_VGPU_H_ */
-- 
1.9.1

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Re: [Intel-gfx] [PATCH 11/38] drm: Consolidate crtc arrays in drm_atomic_state

[Daniel Vetter]

On Thu, Jun 02, 2016 at 04:42:07PM +0200, Maarten Lankhorst wrote:
> Op 02-06-16 om 00:06 schreef Daniel Vetter:
> > It's silly to have 2 mallocs when we could tie these two together.
> >
> > Also, Gustavo adds another one in his per-crtc out-fence patches. And
> > I want to add more stuff here for nonblocking commit helpers.
> >
> > In the future we can use this to store a pointer to the preceeding
> > state, making an atomic update entirely free-standing. This will be
> > needed to be able to queue them up with a depth > 1.
> Patch 9,10,11:
> 
> Reviewed-by: Maarten Lankhorst 

Thanks a lot for your review, applied everything up to this point to
drm-misc.
-Daniel
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http://blog.ffwll.ch
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[Intel-gfx] [PATCH] drm/i915: Fix a buch of kerneldoc warnings

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Just a bunch of stale kerneldocs generating warnings when
building the docs. Mostly function parameters so not very
useful but still.

Signed-off-by: Tvrtko Ursulin 
Cc: Daniel Vetter 
---
 drivers/gpu/drm/i915/i915_cmd_parser.c  |  9 +++---
 drivers/gpu/drm/i915/i915_gem.c | 54 +++--
 drivers/gpu/drm/i915/i915_irq.c |  7 +++--
 drivers/gpu/drm/i915/i915_vgpu.c|  4 +--
 drivers/gpu/drm/i915/intel_lrc.c| 20 +---
 drivers/gpu/drm/i915/intel_runtime_pm.c |  1 +
 6 files changed, 70 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c 
b/drivers/gpu/drm/i915/i915_cmd_parser.c
index d97f28bfa9db..b0fd6a7b0603 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -737,7 +737,7 @@ static void fini_hash_table(struct intel_engine_cs *engine)
 
 /**
  * i915_cmd_parser_init_ring() - set cmd parser related fields for a ringbuffer
- * @ring: the ringbuffer to initialize
+ * @engine: the engine to initialize
  *
  * Optionally initializes fields related to batch buffer command parsing in the
  * struct intel_engine_cs based on whether the platform requires software
@@ -830,7 +830,7 @@ int i915_cmd_parser_init_ring(struct intel_engine_cs 
*engine)
 
 /**
  * i915_cmd_parser_fini_ring() - clean up cmd parser related fields
- * @ring: the ringbuffer to clean up
+ * @engine: the engine to clean up
  *
  * Releases any resources related to command parsing that may have been
  * initialized for the specified ring.
@@ -1024,7 +1024,7 @@ unpin_src:
 
 /**
  * i915_needs_cmd_parser() - should a given ring use software command parsing?
- * @ring: the ring in question
+ * @engine: the engine in question
  *
  * Only certain platforms require software batch buffer command parsing, and
  * only when enabled via module parameter.
@@ -1176,7 +1176,7 @@ static bool check_cmd(const struct intel_engine_cs 
*engine,
 
 /**
  * i915_parse_cmds() - parse a submitted batch buffer for privilege violations
- * @ring: the ring on which the batch is to execute
+ * @engine: the engine on which the batch is to execute
  * @batch_obj: the batch buffer in question
  * @shadow_batch_obj: copy of the batch buffer in question
  * @batch_start_offset: byte offset in the batch at which execution starts
@@ -1281,6 +1281,7 @@ int i915_parse_cmds(struct intel_engine_cs *engine,
 
 /**
  * i915_cmd_parser_get_version() - get the cmd parser version number
+ * @dev_priv: i915 device private
  *
  * The cmd parser maintains a simple increasing integer version number suitable
  * for passing to userspace clients to determine what operations are permitted.
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 343d88114f3b..6c46ddbe927a 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -409,6 +409,10 @@ i915_gem_dumb_create(struct drm_file *file,
 
 /**
  * Creates a new mm object and returns a handle to it.
+ *
+ * @dev: drm device pointer
+ * @data: ioctl data blob
+ * @file: drm file pointer
  */
 int
 i915_gem_create_ioctl(struct drm_device *dev, void *data,
@@ -673,6 +677,10 @@ out:
 /**
  * Reads data from the object referenced by handle.
  *
+ * @dev: drm_device pointer
+ * @data: ioctl data blob
+ * @file: drm_file pointer
+ *
  * On error, the contents of *data are undefined.
  */
 int
@@ -753,6 +761,11 @@ fast_user_write(struct io_mapping *mapping,
 /**
  * This is the fast pwrite path, where we copy the data directly from the
  * user into the GTT, uncached.
+ *
+ * @dev: drm device pointer
+ * @obj: i915 gem object
+ * @args: pwrite arguments structure
+ * @file: drm file pointer
  */
 static int
 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
@@ -1016,6 +1029,9 @@ out:
 
 /**
  * Writes data to the object referenced by handle.
+ * @dev: drm device
+ * @data: ioctl data blob
+ * @file: drm file
  *
  * On error, the contents of the buffer that were to be modified are undefined.
  */
@@ -1213,6 +1229,7 @@ static int __i915_spin_request(struct 
drm_i915_gem_request *req, int state)
  * @req: duh!
  * @interruptible: do an interruptible wait (normally yes)
  * @timeout: in - how long to wait (NULL forever); out - how much time 
remaining
+ * @rps: RPS client
  *
  * Note: It is of utmost importance that the passed in seqno and reset_counter
  * values have been read by the caller in an smp safe manner. Where read-side
@@ -1446,6 +1463,7 @@ __i915_gem_request_retire__upto(struct 
drm_i915_gem_request *req)
 /**
  * Waits for a request to be signaled, and cleans up the
  * request and object lists appropriately for that event.
+ * @req: request to wait on
  */
 int
 i915_wait_request(struct drm_i915_gem_request *req)
@@ -1472,6 +1490,8 @@ i915_wait_request(struct drm_i915_gem_request *req)
 /**
  * Ensures that all rendering to the object has 

Re: [Intel-gfx] [PATCH] drm/atomic: Add __drm_atomic_get_current_plane_state

[Daniel Vetter]

On Thu, Jun 02, 2016 at 04:43:51PM +0200, Maarten Lankhorst wrote:
> Op 02-06-16 om 16:21 schreef Daniel Vetter:
> > ... and use it in msm Again just want to encapsulate
> > drm_atomic_state internals a bit.
> >
> > The const threading is a bit awkward in vc4 since C sucks, but I still
> > think it's worth to enforce this. Eventually I want to make all the
> > obj->state pointers const too, but that's a lot more work ...
> >
> > v2: Provide safe macro to wrap up the unsafe helper better, suggested
> > by Maarten.
> Much better, thanks!
> 
> Reviewed-by: Maarten Lankhorst 

Also fixed up the subject and the 2 typos eric spotted and applied it to
drm-misc. Thanks for thefeedback!
-Daniel
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http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH i-g-t] kms_plane_scaling: Don't try to use second scaler on pipe C

[Matt Roper]

On Thu, Jun 02, 2016 at 11:35:08AM +0300, Ville Syrjälä wrote:
> On Wed, Jun 01, 2016 at 03:13:19PM -0700, Matt Roper wrote:
> > Gen9 has two scalers on pipes A & B, but only a single scaler on pipe C.
> > We should bail out of the test early on pipe C so that we don't ask the
> > kernel to use more scalers than we really have.
> > 
> > Note that this test may still fail (on any pipe) if we're already using
> > one of the scalers as a panel fitter.  But at least this is an
> > improvement over the existing state where the test is guaranteed to fail
> > if run with pipe C active.
> > 
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92248
> > Signed-off-by: Matt Roper 
> > ---
> >  tests/kms_plane_scaling.c | 7 ++-
> >  1 file changed, 6 insertions(+), 1 deletion(-)
> > 
> > diff --git a/tests/kms_plane_scaling.c b/tests/kms_plane_scaling.c
> > index ad5404d..2b17702 100644
> > --- a/tests/kms_plane_scaling.c
> > +++ b/tests/kms_plane_scaling.c
> > @@ -264,6 +264,9 @@ static void test_plane_scaling(data_t *d)
> > igt_display_commit2(display, COMMIT_UNIVERSAL);
> > }
> >  
> > +   if (pipe == PIPE_C)
> > +   goto crtcdone;
> > +
> 
> You you make assumptions like that, then you should probably make the
> test skip on !gen9.

It already does as far as I can see.  It sets data.num_scalers to 0 for
pre-gen9 in the main function and then has a
igt_require(d->num_scalers) in the test function.

> The test is making a lot of assumptions already though, so probably
> would blow up on many other platforms anyway. It also makes some
> assumptions about display resolutions and whatnot, so might blow up on
> gen9 as well.

Yep, agreed with this.  I think there's a lot of improvement that could
be done here, but at the moment I just wanted to fix one case of low
hanging fruit that would fail 100% of the time.


Matt

> 
> Would be cool if someone could make this use CRCs as well, but that
> would probably be a little difficult since the hardware scaling
> algorithm is naturally undocumented :( How I long for the old video
> overlay... Hmm. Actually there does seem to be a way to force bilinear
> scaling at least. Matching that with software rendering might be doable.
> 
> > /* Set up fb3->plane3 mapping. */
> > d->plane3 = igt_output_get_plane(output, IGT_PLANE_3);
> > igt_plane_set_fb(d->plane3, >fb3);
> > @@ -301,9 +304,11 @@ static void test_plane_scaling(data_t *d)
> > igt_display_commit2(display, COMMIT_UNIVERSAL);
> > }
> >  
> > +crtcdone:
> > /* back to single plane mode */
> > igt_plane_set_fb(d->plane2, NULL);
> > -   igt_plane_set_fb(d->plane3, NULL);
> > +   if (pipe != PIPE_C)
> > +   igt_plane_set_fb(d->plane3, NULL);
> > igt_display_commit2(display, COMMIT_UNIVERSAL);
> >  
> > valid_tests++;
> > -- 
> > 2.1.4
> > 
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Ville Syrjälä
> Intel OTC

-- 
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IoTG Platform Enabling & Development
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(916) 356-2795
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Re: [Intel-gfx] [PATCH] drm/atomic: Add __drm_atomic_get_current_plane_state

[Eric Engestrom]

On Thu, Jun 02, 2016 at 04:21:44PM +0200, Daniel Vetter wrote:
> ... and use it in msm Again just want to encapsulate
> drm_atomic_state internals a bit.
> 
> The const threading is a bit awkward in vc4 since C sucks, but I still
> think it's worth to enforce this. Eventually I want to make all the
> obj->state pointers const too, but that's a lot more work ...
> 
> v2: Provide safe macro to wrap up the unsafe helper better, suggested
> by Maarten.
> 
> Cc: Eric Anholt 
> Cc: Rob Clark 
> Cc: Maarten Lankhorst 
> Signed-off-by: Daniel Vetter 
> ---
>  drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 10 ++---
>  drivers/gpu/drm/vc4/vc4_crtc.c   | 13 ++--
>  drivers/gpu/drm/vc4/vc4_drv.h|  2 +-
>  drivers/gpu/drm/vc4/vc4_plane.c  |  5 +++--
>  include/drm/drm_atomic.h | 36 
> 
>  include/drm/drm_atomic_helper.h  | 24 +++--
>  6 files changed, 66 insertions(+), 24 deletions(-)

[...]

> diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h
> index 92c84e9ab09a..4e97186293be 100644
> --- a/include/drm/drm_atomic.h
> +++ b/include/drm/drm_atomic.h
> @@ -109,6 +109,42 @@ drm_atomic_get_existing_connector_state(struct 
> drm_atomic_state *state,
>   return state->connector_states[index];
>  }
>  
> +/**
> + * __drm_atomic_get_current_plane_state - get current plane state
> + * @state: global atomic state object
> + * @plane: plane to grab
> + *
> + * This function returns the plane state for the given plane, either from
> + * @state, or if the plane isn't part of the atomic state update, from 
> @plane.
> + * This is useful in atomic check callbacks, when drivers need to peek at, 
> but
> + * not change, state of other planes, since it avoids threading an error code
> + * back up the call chain.
> + *
> + * WARNING:
> + *
> + * Note that this function is in general unsafe since it doesn't check for 
> the
> + * required locking for access state structures. Drivers must ensure that it 
> is
> + * save to access the returned state structure through other means. One 
> commone

s/save/safe/
s/commone/common/

> + * example is when planes are fixed to a single CRTC, and the driver knows 
> that
> + * the CRTC locks is held already. In that case holding the CRTC locks gives 
> a
> + * read-lock on all planes connected to that CRTC. But if planes can be
> + * reassigned things get more tricky. In that case it's better to use
> + * drm_atomic_get_plane_state and wire up full error handling.
> + *
> + * Returns:
> + *
> + * Read-only pointer to the current plane state.
> + */
> +static inline const struct drm_plane_state *
> +__drm_atomic_get_current_plane_state(struct drm_atomic_state *state,
> +  struct drm_plane *plane)
> +{
> + if (state->plane_states[drm_plane_index(plane)])
> + return state->plane_states[drm_plane_index(plane)];
> +
> + return plane->state;
> +}
> +
>  int __must_check
>  drm_atomic_set_mode_for_crtc(struct drm_crtc_state *state,
>struct drm_display_mode *mode);
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Re: [Intel-gfx] [PATCH] drm/atomic: Add __drm_atomic_get_current_plane_state

[Maarten Lankhorst]

Op 02-06-16 om 16:21 schreef Daniel Vetter:
> ... and use it in msm Again just want to encapsulate
> drm_atomic_state internals a bit.
>
> The const threading is a bit awkward in vc4 since C sucks, but I still
> think it's worth to enforce this. Eventually I want to make all the
> obj->state pointers const too, but that's a lot more work ...
>
> v2: Provide safe macro to wrap up the unsafe helper better, suggested
> by Maarten.
Much better, thanks!

Reviewed-by: Maarten Lankhorst 
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Re: [Intel-gfx] [PATCH 11/38] drm: Consolidate crtc arrays in drm_atomic_state

[Maarten Lankhorst]

Op 02-06-16 om 00:06 schreef Daniel Vetter:
> It's silly to have 2 mallocs when we could tie these two together.
>
> Also, Gustavo adds another one in his per-crtc out-fence patches. And
> I want to add more stuff here for nonblocking commit helpers.
>
> In the future we can use this to store a pointer to the preceeding
> state, making an atomic update entirely free-standing. This will be
> needed to be able to queue them up with a depth > 1.
Patch 9,10,11:

Reviewed-by: Maarten Lankhorst 
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[Intel-gfx] [PATCH 15/20] drm: virtgpu: Rely on the default ->best_encoder() behavior

[Boris Brezillon]

The virtgpu output exposes a 1:1 relationship between connectors and
encoders and the driver is relying on the atomic helpers: we can drop
the custom ->best_encoder() implementation and let the core call
drm_atomic_helper_best_encoder() for us.

Signed-off-by: Boris Brezillon 
---
 drivers/gpu/drm/virtio/virtgpu_display.c | 10 --
 1 file changed, 10 deletions(-)

diff --git a/drivers/gpu/drm/virtio/virtgpu_display.c 
b/drivers/gpu/drm/virtio/virtgpu_display.c
index d4305da..4d41dcb 100644
--- a/drivers/gpu/drm/virtio/virtgpu_display.c
+++ b/drivers/gpu/drm/virtio/virtgpu_display.c
@@ -341,15 +341,6 @@ static int virtio_gpu_conn_mode_valid(struct drm_connector 
*connector,
return MODE_BAD;
 }
 
-static struct drm_encoder*
-virtio_gpu_best_encoder(struct drm_connector *connector)
-{
-   struct virtio_gpu_output *virtio_gpu_output =
-   drm_connector_to_virtio_gpu_output(connector);
-
-   return _gpu_output->enc;
-}
-
 static const struct drm_encoder_helper_funcs virtio_gpu_enc_helper_funcs = {
.mode_set   = virtio_gpu_enc_mode_set,
.enable = virtio_gpu_enc_enable,
@@ -359,7 +350,6 @@ static const struct drm_encoder_helper_funcs 
virtio_gpu_enc_helper_funcs = {
 static const struct drm_connector_helper_funcs virtio_gpu_conn_helper_funcs = {
.get_modes= virtio_gpu_conn_get_modes,
.mode_valid   = virtio_gpu_conn_mode_valid,
-   .best_encoder = virtio_gpu_best_encoder,
 };
 
 static enum drm_connector_status virtio_gpu_conn_detect(
-- 
2.7.4

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[Intel-gfx] [PATCH 05/20] drm: fsl-dcu: Rely on the default ->best_encoder() behavior

[Boris Brezillon]

We have a 1:1 relationship between connectors and encoders and the
driver is relying on the atomic helpers: we can drop the custom
->best_encoder() and let the core call drm_atomic_helper_best_encoder()
for us.

Signed-off-by: Boris Brezillon 
---
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c | 9 -
 1 file changed, 9 deletions(-)

diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c 
b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c
index 98c998d..0b0989e 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c
@@ -102,14 +102,6 @@ static const struct drm_connector_funcs 
fsl_dcu_drm_connector_funcs = {
.reset = drm_atomic_helper_connector_reset,
 };
 
-static struct drm_encoder *
-fsl_dcu_drm_connector_best_encoder(struct drm_connector *connector)
-{
-   struct fsl_dcu_drm_connector *fsl_con = to_fsl_dcu_connector(connector);
-
-   return fsl_con->encoder;
-}
-
 static int fsl_dcu_drm_connector_get_modes(struct drm_connector *connector)
 {
struct fsl_dcu_drm_connector *fsl_connector;
@@ -136,7 +128,6 @@ static int fsl_dcu_drm_connector_mode_valid(struct 
drm_connector *connector,
 }
 
 static const struct drm_connector_helper_funcs connector_helper_funcs = {
-   .best_encoder = fsl_dcu_drm_connector_best_encoder,
.get_modes = fsl_dcu_drm_connector_get_modes,
.mode_valid = fsl_dcu_drm_connector_mode_valid,
 };
-- 
2.7.4

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[Intel-gfx] [PATCH 12/20] drm: sun4i: Rely on the default ->best_encoder() behavior

[Boris Brezillon]

All outputs have a 1:1 relationship between connectors and encoders
and the driver is relying on the atomic helpers: we can drop the custom
->best_encoder() implementations and let the core call
drm_atomic_helper_best_encoder() for us.

Signed-off-by: Boris Brezillon 
---
 drivers/gpu/drm/sun4i/sun4i_rgb.c | 10 --
 drivers/gpu/drm/sun4i/sun4i_tv.c  |  9 -
 2 files changed, 19 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_rgb.c 
b/drivers/gpu/drm/sun4i/sun4i_rgb.c
index ab64948..442cfe2 100644
--- a/drivers/gpu/drm/sun4i/sun4i_rgb.c
+++ b/drivers/gpu/drm/sun4i/sun4i_rgb.c
@@ -90,19 +90,9 @@ static int sun4i_rgb_mode_valid(struct drm_connector 
*connector,
return MODE_OK;
 }
 
-static struct drm_encoder *
-sun4i_rgb_best_encoder(struct drm_connector *connector)
-{
-   struct sun4i_rgb *rgb =
-   drm_connector_to_sun4i_rgb(connector);
-
-   return >encoder;
-}
-
 static struct drm_connector_helper_funcs sun4i_rgb_con_helper_funcs = {
.get_modes  = sun4i_rgb_get_modes,
.mode_valid = sun4i_rgb_mode_valid,
-   .best_encoder   = sun4i_rgb_best_encoder,
 };
 
 static enum drm_connector_status
diff --git a/drivers/gpu/drm/sun4i/sun4i_tv.c b/drivers/gpu/drm/sun4i/sun4i_tv.c
index bc047f9..b841478 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tv.c
@@ -526,18 +526,9 @@ static int sun4i_tv_comp_mode_valid(struct drm_connector 
*connector,
return MODE_OK;
 }
 
-static struct drm_encoder *
-sun4i_tv_comp_best_encoder(struct drm_connector *connector)
-{
-   struct sun4i_tv *tv = drm_connector_to_sun4i_tv(connector);
-
-   return >encoder;
-}
-
 static struct drm_connector_helper_funcs sun4i_tv_comp_connector_helper_funcs 
= {
.get_modes  = sun4i_tv_comp_get_modes,
.mode_valid = sun4i_tv_comp_mode_valid,
-   .best_encoder   = sun4i_tv_comp_best_encoder,
 };
 
 static enum drm_connector_status
-- 
2.7.4

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[Intel-gfx] [PATCH 07/20] drm: mediatek: Rely on the default ->best_encoder() behavior

[Boris Brezillon]

We have a 1:1 relationship between connectors and encoders and the
driver is relying on the atomic helpers: we can drop the custom
->best_encoder() implementation and let the core call
drm_atomic_helper_best_encoder() for us.

Signed-off-by: Boris Brezillon 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 9 -
 1 file changed, 9 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 2d808e5..7343ffc 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -575,14 +575,6 @@ static int mtk_dsi_connector_get_modes(struct 
drm_connector *connector)
return drm_panel_get_modes(dsi->panel);
 }
 
-static struct drm_encoder *mtk_dsi_connector_best_encoder(
-   struct drm_connector *connector)
-{
-   struct mtk_dsi *dsi = connector_to_dsi(connector);
-
-   return >encoder;
-}
-
 static const struct drm_encoder_helper_funcs mtk_dsi_encoder_helper_funcs = {
.mode_fixup = mtk_dsi_encoder_mode_fixup,
.mode_set = mtk_dsi_encoder_mode_set,
@@ -603,7 +595,6 @@ static const struct drm_connector_funcs 
mtk_dsi_connector_funcs = {
 static const struct drm_connector_helper_funcs
mtk_dsi_connector_helper_funcs = {
.get_modes = mtk_dsi_connector_get_modes,
-   .best_encoder = mtk_dsi_connector_best_encoder,
 };
 
 static int mtk_drm_attach_bridge(struct drm_bridge *bridge,
-- 
2.7.4

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[Intel-gfx] [PATCH 20/20] drm/bridge: dw-hdmi: Use drm_atomic_helper_best_encoder()

[Boris Brezillon]

We have a 1:1 relationship between connectors and encoders, which means
we can rely on the drm_atomic_helper_best_encoder() behavior.

We still have to explicitly assign ->best_encoder() to
drm_atomic_helper_best_encoder(), because the automated fallback to
drm_atomic_helper_best_encoder() when ->best_encoder() is NULL is only
available when the DRM device is using the atomic helpers, and this bridge
is compatible with non-atomic and atomic devices.

Signed-off-by: Boris Brezillon 
---
 drivers/gpu/drm/bridge/dw-hdmi.c | 11 +--
 1 file changed, 1 insertion(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/bridge/dw-hdmi.c b/drivers/gpu/drm/bridge/dw-hdmi.c
index c9d9412..70b1f7d 100644
--- a/drivers/gpu/drm/bridge/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/dw-hdmi.c
@@ -1476,15 +1476,6 @@ dw_hdmi_connector_mode_valid(struct drm_connector 
*connector,
return mode_status;
 }
 
-static struct drm_encoder *dw_hdmi_connector_best_encoder(struct drm_connector
-  *connector)
-{
-   struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
-connector);
-
-   return hdmi->encoder;
-}
-
 static void dw_hdmi_connector_destroy(struct drm_connector *connector)
 {
drm_connector_unregister(connector);
@@ -1525,7 +1516,7 @@ static const struct drm_connector_funcs 
dw_hdmi_atomic_connector_funcs = {
 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs 
= {
.get_modes = dw_hdmi_connector_get_modes,
.mode_valid = dw_hdmi_connector_mode_valid,
-   .best_encoder = dw_hdmi_connector_best_encoder,
+   .best_encoder = drm_atomic_helper_best_encoder,
 };
 
 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
-- 
2.7.4

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[Intel-gfx] [PATCH 19/20] drm/bridge: ps8622: Rely on the default ->best_encoder() behavior

[Boris Brezillon]

We have a 1:1 relationship between connectors and encoders, and the driver
is relying on the atomic helpers: we can drop the custom ->best_encoder(),
and let the core call drm_atomic_helper_best_encoder() for us.

Signed-off-by: Boris Brezillon 
---
 drivers/gpu/drm/bridge/parade-ps8622.c | 10 --
 1 file changed, 10 deletions(-)

diff --git a/drivers/gpu/drm/bridge/parade-ps8622.c 
b/drivers/gpu/drm/bridge/parade-ps8622.c
index be881e9..5cd8dd7 100644
--- a/drivers/gpu/drm/bridge/parade-ps8622.c
+++ b/drivers/gpu/drm/bridge/parade-ps8622.c
@@ -474,18 +474,8 @@ static int ps8622_get_modes(struct drm_connector 
*connector)
return drm_panel_get_modes(ps8622->panel);
 }
 
-static struct drm_encoder *ps8622_best_encoder(struct drm_connector *connector)
-{
-   struct ps8622_bridge *ps8622;
-
-   ps8622 = connector_to_ps8622(connector);
-
-   return ps8622->bridge.encoder;
-}
-
 static const struct drm_connector_helper_funcs ps8622_connector_helper_funcs = 
{
.get_modes = ps8622_get_modes,
-   .best_encoder = ps8622_best_encoder,
 };
 
 static enum drm_connector_status ps8622_detect(struct drm_connector *connector,
-- 
2.7.4

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[Intel-gfx] [PATCH 18/20] drm/bridge: ptn3460: Rely on the default ->best_encoder() behavior

[Boris Brezillon]

We have a 1:1 relationship between connectors and encoders, and the driver
is relying on the atomic helpers: we can drop the custom ->best_encoder(),
and let the core call drm_atomic_helper_best_encoder() for us.

Signed-off-by: Boris Brezillon 
---
 drivers/gpu/drm/bridge/nxp-ptn3460.c | 8 
 1 file changed, 8 deletions(-)

diff --git a/drivers/gpu/drm/bridge/nxp-ptn3460.c 
b/drivers/gpu/drm/bridge/nxp-ptn3460.c
index 7ecd59f..93f3dac 100644
--- a/drivers/gpu/drm/bridge/nxp-ptn3460.c
+++ b/drivers/gpu/drm/bridge/nxp-ptn3460.c
@@ -235,16 +235,8 @@ out:
return num_modes;
 }
 
-static struct drm_encoder *ptn3460_best_encoder(struct drm_connector 
*connector)
-{
-   struct ptn3460_bridge *ptn_bridge = connector_to_ptn3460(connector);
-
-   return ptn_bridge->bridge.encoder;
-}
-
 static const struct drm_connector_helper_funcs ptn3460_connector_helper_funcs 
= {
.get_modes = ptn3460_get_modes,
-   .best_encoder = ptn3460_best_encoder,
 };
 
 static enum drm_connector_status ptn3460_detect(struct drm_connector 
*connector,
-- 
2.7.4

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[Intel-gfx] [PATCH 13/20] drm: tegra: Rely on the default ->best_encoder() behavior

[Boris Brezillon]

All outputs have a 1:1 relationship between connectors and encoders
and the driver is relying on the atomic helpers: we can drop the custom
->best_encoder() implementation and let the core call
drm_atomic_helper_best_encoder() for us.

Signed-off-by: Boris Brezillon 
---
 drivers/gpu/drm/tegra/drm.h| 2 --
 drivers/gpu/drm/tegra/dsi.c| 1 -
 drivers/gpu/drm/tegra/hdmi.c   | 1 -
 drivers/gpu/drm/tegra/output.c | 8 
 drivers/gpu/drm/tegra/rgb.c| 1 -
 drivers/gpu/drm/tegra/sor.c| 1 -
 6 files changed, 14 deletions(-)

diff --git a/drivers/gpu/drm/tegra/drm.h b/drivers/gpu/drm/tegra/drm.h
index f52d6cb2..0ddcce1 100644
--- a/drivers/gpu/drm/tegra/drm.h
+++ b/drivers/gpu/drm/tegra/drm.h
@@ -239,8 +239,6 @@ int tegra_output_init(struct drm_device *drm, struct 
tegra_output *output);
 void tegra_output_exit(struct tegra_output *output);
 
 int tegra_output_connector_get_modes(struct drm_connector *connector);
-struct drm_encoder *
-tegra_output_connector_best_encoder(struct drm_connector *connector);
 enum drm_connector_status
 tegra_output_connector_detect(struct drm_connector *connector, bool force);
 void tegra_output_connector_destroy(struct drm_connector *connector);
diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c
index d1239eb..099cccb 100644
--- a/drivers/gpu/drm/tegra/dsi.c
+++ b/drivers/gpu/drm/tegra/dsi.c
@@ -794,7 +794,6 @@ tegra_dsi_connector_mode_valid(struct drm_connector 
*connector,
 static const struct drm_connector_helper_funcs 
tegra_dsi_connector_helper_funcs = {
.get_modes = tegra_output_connector_get_modes,
.mode_valid = tegra_dsi_connector_mode_valid,
-   .best_encoder = tegra_output_connector_best_encoder,
 };
 
 static const struct drm_encoder_funcs tegra_dsi_encoder_funcs = {
diff --git a/drivers/gpu/drm/tegra/hdmi.c b/drivers/gpu/drm/tegra/hdmi.c
index b7ef492..2fdb879 100644
--- a/drivers/gpu/drm/tegra/hdmi.c
+++ b/drivers/gpu/drm/tegra/hdmi.c
@@ -806,7 +806,6 @@ static const struct drm_connector_helper_funcs
 tegra_hdmi_connector_helper_funcs = {
.get_modes = tegra_output_connector_get_modes,
.mode_valid = tegra_hdmi_connector_mode_valid,
-   .best_encoder = tegra_output_connector_best_encoder,
 };
 
 static const struct drm_encoder_funcs tegra_hdmi_encoder_funcs = {
diff --git a/drivers/gpu/drm/tegra/output.c b/drivers/gpu/drm/tegra/output.c
index 46664b6..1480f6a 100644
--- a/drivers/gpu/drm/tegra/output.c
+++ b/drivers/gpu/drm/tegra/output.c
@@ -42,14 +42,6 @@ int tegra_output_connector_get_modes(struct drm_connector 
*connector)
return err;
 }
 
-struct drm_encoder *
-tegra_output_connector_best_encoder(struct drm_connector *connector)
-{
-   struct tegra_output *output = connector_to_output(connector);
-
-   return >encoder;
-}
-
 enum drm_connector_status
 tegra_output_connector_detect(struct drm_connector *connector, bool force)
 {
diff --git a/drivers/gpu/drm/tegra/rgb.c b/drivers/gpu/drm/tegra/rgb.c
index e246334..a131b44 100644
--- a/drivers/gpu/drm/tegra/rgb.c
+++ b/drivers/gpu/drm/tegra/rgb.c
@@ -112,7 +112,6 @@ tegra_rgb_connector_mode_valid(struct drm_connector 
*connector,
 static const struct drm_connector_helper_funcs 
tegra_rgb_connector_helper_funcs = {
.get_modes = tegra_output_connector_get_modes,
.mode_valid = tegra_rgb_connector_mode_valid,
-   .best_encoder = tegra_output_connector_best_encoder,
 };
 
 static const struct drm_encoder_funcs tegra_rgb_encoder_funcs = {
diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c
index 757c6e8..34958d7 100644
--- a/drivers/gpu/drm/tegra/sor.c
+++ b/drivers/gpu/drm/tegra/sor.c
@@ -1087,7 +1087,6 @@ tegra_sor_connector_mode_valid(struct drm_connector 
*connector,
 static const struct drm_connector_helper_funcs 
tegra_sor_connector_helper_funcs = {
.get_modes = tegra_sor_connector_get_modes,
.mode_valid = tegra_sor_connector_mode_valid,
-   .best_encoder = tegra_output_connector_best_encoder,
 };
 
 static const struct drm_encoder_funcs tegra_sor_encoder_funcs = {
-- 
2.7.4

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[Intel-gfx] [PATCH 11/20] drm: sti: Rely on the default ->best_encoder() behavior

[Boris Brezillon]

All outputs have a 1:1 relationship between connectors and encoders
and the driver is relying on the atomic helpers: we can drop the custom
->best_encoder() implementations and let the core call
drm_atomic_helper_best_encoder() for us.

Signed-off-by: Boris Brezillon 
---
 drivers/gpu/drm/sti/sti_dvo.c  | 10 --
 drivers/gpu/drm/sti/sti_hda.c  | 10 --
 drivers/gpu/drm/sti/sti_hdmi.c | 10 --
 3 files changed, 30 deletions(-)

diff --git a/drivers/gpu/drm/sti/sti_dvo.c b/drivers/gpu/drm/sti/sti_dvo.c
index 25f7663..d5627d1 100644
--- a/drivers/gpu/drm/sti/sti_dvo.c
+++ b/drivers/gpu/drm/sti/sti_dvo.c
@@ -384,20 +384,10 @@ static int sti_dvo_connector_mode_valid(struct 
drm_connector *connector,
return MODE_OK;
 }
 
-struct drm_encoder *sti_dvo_best_encoder(struct drm_connector *connector)
-{
-   struct sti_dvo_connector *dvo_connector
-   = to_sti_dvo_connector(connector);
-
-   /* Best encoder is the one associated during connector creation */
-   return dvo_connector->encoder;
-}
-
 static const
 struct drm_connector_helper_funcs sti_dvo_connector_helper_funcs = {
.get_modes = sti_dvo_connector_get_modes,
.mode_valid = sti_dvo_connector_mode_valid,
-   .best_encoder = sti_dvo_best_encoder,
 };
 
 static enum drm_connector_status
diff --git a/drivers/gpu/drm/sti/sti_hda.c b/drivers/gpu/drm/sti/sti_hda.c
index f7d3464..c4649f5 100644
--- a/drivers/gpu/drm/sti/sti_hda.c
+++ b/drivers/gpu/drm/sti/sti_hda.c
@@ -676,20 +676,10 @@ static int sti_hda_connector_mode_valid(struct 
drm_connector *connector,
return MODE_OK;
 }
 
-struct drm_encoder *sti_hda_best_encoder(struct drm_connector *connector)
-{
-   struct sti_hda_connector *hda_connector
-   = to_sti_hda_connector(connector);
-
-   /* Best encoder is the one associated during connector creation */
-   return hda_connector->encoder;
-}
-
 static const
 struct drm_connector_helper_funcs sti_hda_connector_helper_funcs = {
.get_modes = sti_hda_connector_get_modes,
.mode_valid = sti_hda_connector_mode_valid,
-   .best_encoder = sti_hda_best_encoder,
 };
 
 static enum drm_connector_status
diff --git a/drivers/gpu/drm/sti/sti_hdmi.c b/drivers/gpu/drm/sti/sti_hdmi.c
index 6ef0715..dc9ab6e 100644
--- a/drivers/gpu/drm/sti/sti_hdmi.c
+++ b/drivers/gpu/drm/sti/sti_hdmi.c
@@ -897,20 +897,10 @@ static int sti_hdmi_connector_mode_valid(struct 
drm_connector *connector,
return MODE_OK;
 }
 
-struct drm_encoder *sti_hdmi_best_encoder(struct drm_connector *connector)
-{
-   struct sti_hdmi_connector *hdmi_connector
-   = to_sti_hdmi_connector(connector);
-
-   /* Best encoder is the one associated during connector creation */
-   return hdmi_connector->encoder;
-}
-
 static const
 struct drm_connector_helper_funcs sti_hdmi_connector_helper_funcs = {
.get_modes = sti_hdmi_connector_get_modes,
.mode_valid = sti_hdmi_connector_mode_valid,
-   .best_encoder = sti_hdmi_best_encoder,
 };
 
 /* get detection status of display device */
-- 
2.7.4

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[Intel-gfx] [PATCH 06/20] drm: i915: Rely on the default ->best_encoder() behavior where appropriate

[Boris Brezillon]

For all outputs except dp_mst, we have a 1:1 relationship between
connectors and encoders and the driver is relying on the atomic helpers:
we can drop the custom ->best_encoder() implementation and let the core
call drm_atomic_helper_best_encoder() for us.

Signed-off-by: Boris Brezillon 
---
 drivers/gpu/drm/i915/intel_crt.c | 1 -
 drivers/gpu/drm/i915/intel_display.c | 8 
 drivers/gpu/drm/i915/intel_dp.c  | 1 -
 drivers/gpu/drm/i915/intel_drv.h | 1 -
 drivers/gpu/drm/i915/intel_dsi.c | 1 -
 drivers/gpu/drm/i915/intel_dvo.c | 1 -
 drivers/gpu/drm/i915/intel_hdmi.c| 1 -
 drivers/gpu/drm/i915/intel_lvds.c| 1 -
 drivers/gpu/drm/i915/intel_sdvo.c| 1 -
 drivers/gpu/drm/i915/intel_tv.c  | 1 -
 10 files changed, 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 3fbb6fc..bd0cd68 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -753,7 +753,6 @@ static const struct drm_connector_funcs 
intel_crt_connector_funcs = {
 static const struct drm_connector_helper_funcs 
intel_crt_connector_helper_funcs = {
.mode_valid = intel_crt_mode_valid,
.get_modes = intel_crt_get_modes,
-   .best_encoder = intel_best_encoder,
 };
 
 static const struct drm_encoder_funcs intel_crt_enc_funcs = {
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 2113f40..77026ce 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -16113,14 +16113,6 @@ void intel_modeset_cleanup(struct drm_device *dev)
intel_teardown_gmbus(dev);
 }
 
-/*
- * Return which encoder is currently attached for connector.
- */
-struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
-{
-   return _attached_encoder(connector)->base;
-}
-
 void intel_connector_attach_encoder(struct intel_connector *connector,
struct intel_encoder *encoder)
 {
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f192f58..21b2833 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4935,7 +4935,6 @@ static const struct drm_connector_funcs 
intel_dp_connector_funcs = {
 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs 
= {
.get_modes = intel_dp_get_modes,
.mode_valid = intel_dp_mode_valid,
-   .best_encoder = intel_best_encoder,
 };
 
 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a28b4aa..79a4d6b 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1128,7 +1128,6 @@ struct intel_connector *intel_connector_alloc(void);
 bool intel_connector_get_hw_state(struct intel_connector *connector);
 void intel_connector_attach_encoder(struct intel_connector *connector,
struct intel_encoder *encoder);
-struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
 struct drm_crtc *crtc);
 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 366ad6c..ec51952 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -1378,7 +1378,6 @@ static const struct drm_encoder_funcs intel_dsi_funcs = {
 static const struct drm_connector_helper_funcs 
intel_dsi_connector_helper_funcs = {
.get_modes = intel_dsi_get_modes,
.mode_valid = intel_dsi_mode_valid,
-   .best_encoder = intel_best_encoder,
 };
 
 static const struct drm_connector_funcs intel_dsi_connector_funcs = {
diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
index 286baec..34b7e3f 100644
--- a/drivers/gpu/drm/i915/intel_dvo.c
+++ b/drivers/gpu/drm/i915/intel_dvo.c
@@ -351,7 +351,6 @@ static const struct drm_connector_funcs 
intel_dvo_connector_funcs = {
 static const struct drm_connector_helper_funcs 
intel_dvo_connector_helper_funcs = {
.mode_valid = intel_dvo_mode_valid,
.get_modes = intel_dvo_get_modes,
-   .best_encoder = intel_best_encoder,
 };
 
 static void intel_dvo_enc_destroy(struct drm_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
b/drivers/gpu/drm/i915/intel_hdmi.c
index 2c3bd9c..aef4bc8 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -2114,7 +2114,6 @@ static const struct drm_connector_funcs 
intel_hdmi_connector_funcs = {
 static const struct drm_connector_helper_funcs 
intel_hdmi_connector_helper_funcs = {
.get_modes = intel_hdmi_get_modes,
.mode_valid = intel_hdmi_mode_valid,
-   .best_encoder = 

[Intel-gfx] [PATCH 10/20] drm: rockchip: Rely on the default ->best_encoder() behavior

[Boris Brezillon]

All outputss have a 1:1 relationship between connectors and encoders
and the driver is relying on the atomic helpers: we can drop the custom
->best_encoder() implementations  and let the core call
drm_atomic_helper_best_encoder() for us.

Signed-off-by: Boris Brezillon 
---
 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 9 -
 drivers/gpu/drm/rockchip/inno_hdmi.c   | 9 -
 2 files changed, 18 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c 
b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index dedc65b..ca22e5e 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -964,18 +964,9 @@ static enum drm_mode_status dw_mipi_dsi_mode_valid(
return mode_status;
 }
 
-static struct drm_encoder *dw_mipi_dsi_connector_best_encoder(
-   struct drm_connector *connector)
-{
-   struct dw_mipi_dsi *dsi = con_to_dsi(connector);
-
-   return >encoder;
-}
-
 static struct drm_connector_helper_funcs dw_mipi_dsi_connector_helper_funcs = {
.get_modes = dw_mipi_dsi_connector_get_modes,
.mode_valid = dw_mipi_dsi_mode_valid,
-   .best_encoder = dw_mipi_dsi_connector_best_encoder,
 };
 
 static enum drm_connector_status
diff --git a/drivers/gpu/drm/rockchip/inno_hdmi.c 
b/drivers/gpu/drm/rockchip/inno_hdmi.c
index f8b4feb..006260d 100644
--- a/drivers/gpu/drm/rockchip/inno_hdmi.c
+++ b/drivers/gpu/drm/rockchip/inno_hdmi.c
@@ -579,14 +579,6 @@ inno_hdmi_connector_mode_valid(struct drm_connector 
*connector,
return MODE_OK;
 }
 
-static struct drm_encoder *
-inno_hdmi_connector_best_encoder(struct drm_connector *connector)
-{
-   struct inno_hdmi *hdmi = to_inno_hdmi(connector);
-
-   return >encoder;
-}
-
 static int
 inno_hdmi_probe_single_connector_modes(struct drm_connector *connector,
   uint32_t maxX, uint32_t maxY)
@@ -613,7 +605,6 @@ static struct drm_connector_funcs inno_hdmi_connector_funcs 
= {
 static struct drm_connector_helper_funcs inno_hdmi_connector_helper_funcs = {
.get_modes = inno_hdmi_connector_get_modes,
.mode_valid = inno_hdmi_connector_mode_valid,
-   .best_encoder = inno_hdmi_connector_best_encoder,
 };
 
 static int inno_hdmi_register(struct drm_device *drm, struct inno_hdmi *hdmi)
-- 
2.7.4

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[Intel-gfx] [PATCH 09/20] drm: rcar-du: Rely on the default ->best_encoder() behavior

[Boris Brezillon]

All outputs have a 1:1 relationship between connectors and encoders,
and the driver is relying on the atomic helpers: we can drop the custom
->best_encoder() implementations and let the core call
drm_atomic_helper_best_encoder() for us.

Signed-off-by: Boris Brezillon 
---
 drivers/gpu/drm/rcar-du/rcar_du_encoder.c | 12 
 drivers/gpu/drm/rcar-du/rcar_du_encoder.h |  3 ---
 drivers/gpu/drm/rcar-du/rcar_du_hdmicon.c |  1 -
 drivers/gpu/drm/rcar-du/rcar_du_lvdscon.c |  1 -
 drivers/gpu/drm/rcar-du/rcar_du_vgacon.c  |  1 -
 5 files changed, 18 deletions(-)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_encoder.c 
b/drivers/gpu/drm/rcar-du/rcar_du_encoder.c
index 4e939e4..55149e9 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_encoder.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_encoder.c
@@ -27,18 +27,6 @@
 #include "rcar_du_vgacon.h"
 
 /* 
-
- * Common connector functions
- */
-
-struct drm_encoder *
-rcar_du_connector_best_encoder(struct drm_connector *connector)
-{
-   struct rcar_du_connector *rcon = to_rcar_connector(connector);
-
-   return rcar_encoder_to_drm_encoder(rcon->encoder);
-}
-
-/* 
-
  * Encoder
  */
 
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_encoder.h 
b/drivers/gpu/drm/rcar-du/rcar_du_encoder.h
index 719b6f2a..a8669c3 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_encoder.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_encoder.h
@@ -49,9 +49,6 @@ struct rcar_du_connector {
 #define to_rcar_connector(c) \
container_of(c, struct rcar_du_connector, connector)
 
-struct drm_encoder *
-rcar_du_connector_best_encoder(struct drm_connector *connector);
-
 int rcar_du_encoder_init(struct rcar_du_device *rcdu,
 enum rcar_du_encoder_type type,
 enum rcar_du_output output,
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_hdmicon.c 
b/drivers/gpu/drm/rcar-du/rcar_du_hdmicon.c
index 6c92714..612b4d5 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_hdmicon.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_hdmicon.c
@@ -52,7 +52,6 @@ static int rcar_du_hdmi_connector_mode_valid(struct 
drm_connector *connector,
 static const struct drm_connector_helper_funcs connector_helper_funcs = {
.get_modes = rcar_du_hdmi_connector_get_modes,
.mode_valid = rcar_du_hdmi_connector_mode_valid,
-   .best_encoder = rcar_du_connector_best_encoder,
 };
 
 static enum drm_connector_status
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_lvdscon.c 
b/drivers/gpu/drm/rcar-du/rcar_du_lvdscon.c
index e905f5d..6afd0af 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_lvdscon.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_lvdscon.c
@@ -59,7 +59,6 @@ static int rcar_du_lvds_connector_get_modes(struct 
drm_connector *connector)
 
 static const struct drm_connector_helper_funcs connector_helper_funcs = {
.get_modes = rcar_du_lvds_connector_get_modes,
-   .best_encoder = rcar_du_connector_best_encoder,
 };
 
 static enum drm_connector_status
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vgacon.c 
b/drivers/gpu/drm/rcar-du/rcar_du_vgacon.c
index 9d7e5c9..68f7ffa 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_vgacon.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vgacon.c
@@ -28,7 +28,6 @@ static int rcar_du_vga_connector_get_modes(struct 
drm_connector *connector)
 
 static const struct drm_connector_helper_funcs connector_helper_funcs = {
.get_modes = rcar_du_vga_connector_get_modes,
-   .best_encoder = rcar_du_connector_best_encoder,
 };
 
 static enum drm_connector_status
-- 
2.7.4

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[Intel-gfx] [PATCH 17/20] drm/bridge: anx78xx: Rely on the default ->best_encoder() behavior

[Boris Brezillon]

We have a 1:1 relationship between connectors and encoders, and the driver
is relying on the atomic helpers: we can drop the custom ->best_encoder(),
and let the core call drm_atomic_helper_best_encoder() for us.

Signed-off-by: Boris Brezillon 
---
 drivers/gpu/drm/bridge/analogix-anx78xx.c | 8 
 1 file changed, 8 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix-anx78xx.c 
b/drivers/gpu/drm/bridge/analogix-anx78xx.c
index d087b05..f9f03bc 100644
--- a/drivers/gpu/drm/bridge/analogix-anx78xx.c
+++ b/drivers/gpu/drm/bridge/analogix-anx78xx.c
@@ -986,16 +986,8 @@ unlock:
return num_modes;
 }
 
-static struct drm_encoder *anx78xx_best_encoder(struct drm_connector 
*connector)
-{
-   struct anx78xx *anx78xx = connector_to_anx78xx(connector);
-
-   return anx78xx->bridge.encoder;
-}
-
 static const struct drm_connector_helper_funcs anx78xx_connector_helper_funcs 
= {
.get_modes = anx78xx_get_modes,
-   .best_encoder = anx78xx_best_encoder,
 };
 
 static enum drm_connector_status anx78xx_detect(struct drm_connector 
*connector,
-- 
2.7.4

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[Intel-gfx] [PATCH 08/20] drm: msm: Rely on the default ->best_encoder() behavior where appropriate

[Boris Brezillon]

For all outputs except DSI we have a 1:1 relationship between connectors
and encoders and the driver is relying on the atomic helpers: we can
drop the custom ->best_encoder() and let the core call
drm_atomic_helper_best_encoder() for us.

Signed-off-by: Boris Brezillon 
---
 drivers/gpu/drm/msm/edp/edp_connector.c| 10 --
 drivers/gpu/drm/msm/hdmi/hdmi_connector.c  |  8 
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_lvds_connector.c |  9 -
 3 files changed, 27 deletions(-)

diff --git a/drivers/gpu/drm/msm/edp/edp_connector.c 
b/drivers/gpu/drm/msm/edp/edp_connector.c
index 72360cd..5960628 100644
--- a/drivers/gpu/drm/msm/edp/edp_connector.c
+++ b/drivers/gpu/drm/msm/edp/edp_connector.c
@@ -91,15 +91,6 @@ static int edp_connector_mode_valid(struct drm_connector 
*connector,
return MODE_OK;
 }
 
-static struct drm_encoder *
-edp_connector_best_encoder(struct drm_connector *connector)
-{
-   struct edp_connector *edp_connector = to_edp_connector(connector);
-
-   DBG("");
-   return edp_connector->edp->encoder;
-}
-
 static const struct drm_connector_funcs edp_connector_funcs = {
.dpms = drm_atomic_helper_connector_dpms,
.detect = edp_connector_detect,
@@ -113,7 +104,6 @@ static const struct drm_connector_funcs edp_connector_funcs 
= {
 static const struct drm_connector_helper_funcs edp_connector_helper_funcs = {
.get_modes = edp_connector_get_modes,
.mode_valid = edp_connector_mode_valid,
-   .best_encoder = edp_connector_best_encoder,
 };
 
 /* initialize connector */
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_connector.c 
b/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
index b15d726..a2515b4 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
@@ -406,13 +406,6 @@ static int msm_hdmi_connector_mode_valid(struct 
drm_connector *connector,
return 0;
 }
 
-static struct drm_encoder *
-msm_hdmi_connector_best_encoder(struct drm_connector *connector)
-{
-   struct hdmi_connector *hdmi_connector = to_hdmi_connector(connector);
-   return hdmi_connector->hdmi->encoder;
-}
-
 static const struct drm_connector_funcs hdmi_connector_funcs = {
.dpms = drm_atomic_helper_connector_dpms,
.detect = hdmi_connector_detect,
@@ -426,7 +419,6 @@ static const struct drm_connector_funcs 
hdmi_connector_funcs = {
 static const struct drm_connector_helper_funcs msm_hdmi_connector_helper_funcs 
= {
.get_modes = msm_hdmi_connector_get_modes,
.mode_valid = msm_hdmi_connector_mode_valid,
-   .best_encoder = msm_hdmi_connector_best_encoder,
 };
 
 /* initialize connector */
diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_lvds_connector.c 
b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_lvds_connector.c
index 2648cd7..353429b 100644
--- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_lvds_connector.c
+++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_lvds_connector.c
@@ -90,14 +90,6 @@ static int mdp4_lvds_connector_mode_valid(struct 
drm_connector *connector,
return MODE_OK;
 }
 
-static struct drm_encoder *
-mdp4_lvds_connector_best_encoder(struct drm_connector *connector)
-{
-   struct mdp4_lvds_connector *mdp4_lvds_connector =
-   to_mdp4_lvds_connector(connector);
-   return mdp4_lvds_connector->encoder;
-}
-
 static const struct drm_connector_funcs mdp4_lvds_connector_funcs = {
.dpms = drm_atomic_helper_connector_dpms,
.detect = mdp4_lvds_connector_detect,
@@ -111,7 +103,6 @@ static const struct drm_connector_funcs 
mdp4_lvds_connector_funcs = {
 static const struct drm_connector_helper_funcs 
mdp4_lvds_connector_helper_funcs = {
.get_modes = mdp4_lvds_connector_get_modes,
.mode_valid = mdp4_lvds_connector_mode_valid,
-   .best_encoder = mdp4_lvds_connector_best_encoder,
 };
 
 /* initialize connector */
-- 
2.7.4

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[Intel-gfx] [PATCH 14/20] drm: vc4: Rely on the default ->best_encoder() behavior

[Boris Brezillon]

All outputs have a 1:1 relationship between connectors and encoders and
the driver is relying on the atomic helpers: we can drop the custom
->best_encoder() implementations and let the core call
drm_atomic_helper_best_encoder() for us.

Signed-off-by: Boris Brezillon 
---
 drivers/gpu/drm/vc4/vc4_dpi.c  | 9 -
 drivers/gpu/drm/vc4/vc4_hdmi.c | 9 -
 2 files changed, 18 deletions(-)

diff --git a/drivers/gpu/drm/vc4/vc4_dpi.c b/drivers/gpu/drm/vc4/vc4_dpi.c
index 9817dbf..dba1114 100644
--- a/drivers/gpu/drm/vc4/vc4_dpi.c
+++ b/drivers/gpu/drm/vc4/vc4_dpi.c
@@ -208,14 +208,6 @@ static int vc4_dpi_connector_get_modes(struct 
drm_connector *connector)
return 0;
 }
 
-static struct drm_encoder *
-vc4_dpi_connector_best_encoder(struct drm_connector *connector)
-{
-   struct vc4_dpi_connector *dpi_connector =
-   to_vc4_dpi_connector(connector);
-   return dpi_connector->encoder;
-}
-
 static const struct drm_connector_funcs vc4_dpi_connector_funcs = {
.dpms = drm_atomic_helper_connector_dpms,
.detect = vc4_dpi_connector_detect,
@@ -228,7 +220,6 @@ static const struct drm_connector_funcs 
vc4_dpi_connector_funcs = {
 
 static const struct drm_connector_helper_funcs vc4_dpi_connector_helper_funcs 
= {
.get_modes = vc4_dpi_connector_get_modes,
-   .best_encoder = vc4_dpi_connector_best_encoder,
 };
 
 static struct drm_connector *vc4_dpi_connector_init(struct drm_device *dev,
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index fd2644d..68df91c 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -208,14 +208,6 @@ static int vc4_hdmi_connector_get_modes(struct 
drm_connector *connector)
return ret;
 }
 
-static struct drm_encoder *
-vc4_hdmi_connector_best_encoder(struct drm_connector *connector)
-{
-   struct vc4_hdmi_connector *hdmi_connector =
-   to_vc4_hdmi_connector(connector);
-   return hdmi_connector->encoder;
-}
-
 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
.dpms = drm_atomic_helper_connector_dpms,
.detect = vc4_hdmi_connector_detect,
@@ -228,7 +220,6 @@ static const struct drm_connector_funcs 
vc4_hdmi_connector_funcs = {
 
 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs 
= {
.get_modes = vc4_hdmi_connector_get_modes,
-   .best_encoder = vc4_hdmi_connector_best_encoder,
 };
 
 static struct drm_connector *vc4_hdmi_connector_init(struct drm_device *dev,
-- 
2.7.4

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[Intel-gfx] [PATCH 16/20] drm: omap: Rely on the default ->best_encoder() behavior

[Boris Brezillon]

We have a 1:1 relationship between connectors and encoders and the
driver is relying on the atomic helpers: we can drop the custom
->best_encoder() implementation and let the core call
drm_atomic_helper_best_encoder() for us.

Signed-off-by: Boris Brezillon 
---
 drivers/gpu/drm/omapdrm/omap_connector.c | 8 
 1 file changed, 8 deletions(-)

diff --git a/drivers/gpu/drm/omapdrm/omap_connector.c 
b/drivers/gpu/drm/omapdrm/omap_connector.c
index ce2d67b..80af5e1 100644
--- a/drivers/gpu/drm/omapdrm/omap_connector.c
+++ b/drivers/gpu/drm/omapdrm/omap_connector.c
@@ -256,13 +256,6 @@ static int omap_connector_mode_valid(struct drm_connector 
*connector,
return ret;
 }
 
-struct drm_encoder *omap_connector_attached_encoder(
-   struct drm_connector *connector)
-{
-   struct omap_connector *omap_connector = to_omap_connector(connector);
-   return omap_connector->encoder;
-}
-
 static const struct drm_connector_funcs omap_connector_funcs = {
.dpms = drm_atomic_helper_connector_dpms,
.reset = drm_atomic_helper_connector_reset,
@@ -276,7 +269,6 @@ static const struct drm_connector_funcs 
omap_connector_funcs = {
 static const struct drm_connector_helper_funcs omap_connector_helper_funcs = {
.get_modes = omap_connector_get_modes,
.mode_valid = omap_connector_mode_valid,
-   .best_encoder = omap_connector_attached_encoder,
 };
 
 /* initialize connector */
-- 
2.7.4

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[Intel-gfx] [PATCH 03/20] drm: atmel-hlcdc: Rely on the default ->best_encoder() behavior

[Boris Brezillon]

We have a 1:1 relationship between connectors and encoders and the
driver is relying on the atomic helpers: we can drop the custom
->best_encoder() and let the core call drm_atomic_helper_best_encoder()
for us.

Signed-off-by: Boris Brezillon 
---
 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c | 12 
 1 file changed, 12 deletions(-)

diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c 
b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c
index 39802c0..473a475 100644
--- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c
+++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c
@@ -113,21 +113,9 @@ static int atmel_hlcdc_rgb_mode_valid(struct drm_connector 
*connector,
return atmel_hlcdc_dc_mode_valid(rgb->dc, mode);
 }
 
-
-
-static struct drm_encoder *
-atmel_hlcdc_rgb_best_encoder(struct drm_connector *connector)
-{
-   struct atmel_hlcdc_rgb_output *rgb =
-   drm_connector_to_atmel_hlcdc_rgb_output(connector);
-
-   return >encoder;
-}
-
 static const struct drm_connector_helper_funcs 
atmel_hlcdc_panel_connector_helper_funcs = {
.get_modes = atmel_hlcdc_panel_get_modes,
.mode_valid = atmel_hlcdc_rgb_mode_valid,
-   .best_encoder = atmel_hlcdc_rgb_best_encoder,
 };
 
 static enum drm_connector_status
-- 
2.7.4

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[Intel-gfx] [PATCH 01/20] drm/atomic: Fix remaining places where !funcs->best_encoder is valid

[Boris Brezillon]

Adapt drm_pick_crtcs() and update_connector_routing() to fallback to
drm_atomic_helper_best_encoder() if funcs->best_encoder() is NULL so
that DRM drivers can leave this hook unassigned if they know they want
to use drm_atomic_helper_best_encoder().

Signed-off-by: Boris Brezillon 
---
 drivers/gpu/drm/drm_atomic_helper.c |  4 +++-
 drivers/gpu/drm/drm_fb_helper.c | 13 -
 2 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/drm_atomic_helper.c 
b/drivers/gpu/drm/drm_atomic_helper.c
index f6a3350..849d029 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -300,8 +300,10 @@ update_connector_routing(struct drm_atomic_state *state,
if (funcs->atomic_best_encoder)
new_encoder = funcs->atomic_best_encoder(connector,
 connector_state);
-   else
+   else if (funcs->best_encoder)
new_encoder = funcs->best_encoder(connector);
+   else
+   new_encoder = drm_atomic_helper_best_encoder(connector);
 
if (!new_encoder) {
DRM_DEBUG_ATOMIC("No suitable encoder found for 
[CONNECTOR:%d:%s]\n",
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 7c2eb75..d44389a 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -2000,7 +2000,18 @@ static int drm_pick_crtcs(struct drm_fb_helper 
*fb_helper,
my_score++;
 
connector_funcs = connector->helper_private;
-   encoder = connector_funcs->best_encoder(connector);
+
+   /*
+* If the DRM device implements atomic hooks and ->best_encoder() is
+* NULL we fallback to the default drm_atomic_helper_best_encoder()
+* helper.
+*/
+   if (fb_helper->dev->mode_config.funcs->atomic_commit &&
+   !connector_funcs->best_encoder)
+   encoder = drm_atomic_helper_best_encoder(connector);
+   else
+   encoder = connector_funcs->best_encoder(connector);
+
if (!encoder)
goto out;
 
-- 
2.7.4

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[Intel-gfx] [PATCH 00/20] drm/atomic: Provide default ->best_encoder() behavior

[Boris Brezillon]

Hello,

This patch series aims at replacing all dummy ->best_encoder()
implementations where we have a 1:1 relationship between encoders
and connectors.
The core already provides the drm_atomic_helper_best_encoder()
function which is taking the first encoder attached to the
connector (after making sure only one encoder was attached to the
connector), but it's not automatically used, and drivers wanting
to rely on this default behavior have to explicitly assign their
->best_encoder() hook to drm_atomic_helper_best_encoder().

The first patch fixes remaining places where
drm_atomic_helper_best_encoder() should be called when ->best_encoder()
is NULL, so that drivers using the atomic helpers can get rid of the
explicit ->best_encoder assignment if they need to rely on the default
drm_atomic_helper_best_encoder() implementation.

The following patches are killing all open coded ->best_encoder()
implementations that could be replaced by
drm_atomic_helper_best_encoder().

All modifications have been compile tested except for the changed on
the intel driver.
I've also tested on an atmel board, but I recommend waiting for DRM
driver maintainers feedback before applying the associated changes.

Note that once patch 1 is applied, the other patches can be applied
independently.

Best Regards,

Boris 

Boris Brezillon (20):
  drm/atomic: Fix remaining places where !funcs->best_encoder is valid
  drm: arc: Rely on the default ->best_encoder() behavior
  drm: atmel-hlcdc: Rely on the default ->best_encoder() behavior
  drm: exynos: Rely on the default ->best_encoder() behavior
  drm: fsl-dcu: Rely on the default ->best_encoder() behavior
  drm: i915: Rely on the default ->best_encoder() behavior where
appropriate
  drm: mediatek: Rely on the default ->best_encoder() behavior
  drm: msm: Rely on the default ->best_encoder() behavior where
appropriate
  drm: rcar-du: Rely on the default ->best_encoder() behavior
  drm: rockchip: Rely on the default ->best_encoder() behavior
  drm: sti: Rely on the default ->best_encoder() behavior
  drm: sun4i: Rely on the default ->best_encoder() behavior
  drm: tegra: Rely on the default ->best_encoder() behavior
  drm: vc4: Rely on the default ->best_encoder() behavior
  drm: virtgpu: Rely on the default ->best_encoder() behavior
  drm: omap: Rely on the default ->best_encoder() behavior
  drm/bridge: anx78xx: Rely on the default ->best_encoder() behavior
  drm/bridge: ptn3460: Rely on the default ->best_encoder() behavior
  drm/bridge: ps8622: Rely on the default ->best_encoder() behavior
  drm/bridge: dw-hdmi: Use drm_atomic_helper_best_encoder()

 drivers/gpu/drm/arc/arcpgu_hdmi.c  | 18 --
 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c   | 12 
 drivers/gpu/drm/bridge/analogix-anx78xx.c  |  8 
 drivers/gpu/drm/bridge/dw-hdmi.c   | 11 +--
 drivers/gpu/drm/bridge/nxp-ptn3460.c   |  8 
 drivers/gpu/drm/bridge/parade-ps8622.c | 10 --
 drivers/gpu/drm/drm_atomic_helper.c|  4 +++-
 drivers/gpu/drm/drm_fb_helper.c| 13 -
 drivers/gpu/drm/exynos/exynos_drm_dpi.c|  9 -
 drivers/gpu/drm/exynos/exynos_drm_dsi.c|  9 -
 drivers/gpu/drm/exynos/exynos_drm_vidi.c   |  8 
 drivers/gpu/drm/exynos/exynos_hdmi.c   |  8 
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c  |  9 -
 drivers/gpu/drm/i915/intel_crt.c   |  1 -
 drivers/gpu/drm/i915/intel_display.c   |  8 
 drivers/gpu/drm/i915/intel_dp.c|  1 -
 drivers/gpu/drm/i915/intel_drv.h   |  1 -
 drivers/gpu/drm/i915/intel_dsi.c   |  1 -
 drivers/gpu/drm/i915/intel_dvo.c   |  1 -
 drivers/gpu/drm/i915/intel_hdmi.c  |  1 -
 drivers/gpu/drm/i915/intel_lvds.c  |  1 -
 drivers/gpu/drm/i915/intel_sdvo.c  |  1 -
 drivers/gpu/drm/i915/intel_tv.c|  1 -
 drivers/gpu/drm/mediatek/mtk_dsi.c |  9 -
 drivers/gpu/drm/msm/edp/edp_connector.c| 10 --
 drivers/gpu/drm/msm/hdmi/hdmi_connector.c  |  8 
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_lvds_connector.c |  9 -
 drivers/gpu/drm/omapdrm/omap_connector.c   |  8 
 drivers/gpu/drm/rcar-du/rcar_du_encoder.c  | 12 
 drivers/gpu/drm/rcar-du/rcar_du_encoder.h  |  3 ---
 drivers/gpu/drm/rcar-du/rcar_du_hdmicon.c  |  1 -
 drivers/gpu/drm/rcar-du/rcar_du_lvdscon.c  |  1 -
 drivers/gpu/drm/rcar-du/rcar_du_vgacon.c   |  1 -
 drivers/gpu/drm/rockchip/dw-mipi-dsi.c |  9 -
 drivers/gpu/drm/rockchip/inno_hdmi.c   |  9 -
 drivers/gpu/drm/sti/sti_dvo.c  | 10 --
 drivers/gpu/drm/sti/sti_hda.c  

[Intel-gfx] [PATCH 04/20] drm: exynos: Rely on the default ->best_encoder() behavior

[Boris Brezillon]

We have 1:1 relationship between connectors and encoders and the driver
is relying on the atomic helpers: we can drop the custom ->best_encoder()
implementations and let the core call drm_atomic_helper_best_encoder()
for us.

Signed-off-by: Boris Brezillon 
---
 drivers/gpu/drm/exynos/exynos_drm_dpi.c  | 9 -
 drivers/gpu/drm/exynos/exynos_drm_dsi.c  | 9 -
 drivers/gpu/drm/exynos/exynos_drm_vidi.c | 8 
 drivers/gpu/drm/exynos/exynos_hdmi.c | 8 
 4 files changed, 34 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_dpi.c 
b/drivers/gpu/drm/exynos/exynos_drm_dpi.c
index 5e38e74..ad6b73c 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dpi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dpi.c
@@ -93,17 +93,8 @@ static int exynos_dpi_get_modes(struct drm_connector 
*connector)
return 0;
 }
 
-static struct drm_encoder *
-exynos_dpi_best_encoder(struct drm_connector *connector)
-{
-   struct exynos_dpi *ctx = connector_to_dpi(connector);
-
-   return >encoder;
-}
-
 static const struct drm_connector_helper_funcs 
exynos_dpi_connector_helper_funcs = {
.get_modes = exynos_dpi_get_modes,
-   .best_encoder = exynos_dpi_best_encoder,
 };
 
 static int exynos_dpi_create_connector(struct drm_encoder *encoder)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c 
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 601ecf8..e07cb1f 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -1566,17 +1566,8 @@ static int exynos_dsi_get_modes(struct drm_connector 
*connector)
return 0;
 }
 
-static struct drm_encoder *
-exynos_dsi_best_encoder(struct drm_connector *connector)
-{
-   struct exynos_dsi *dsi = connector_to_dsi(connector);
-
-   return >encoder;
-}
-
 static const struct drm_connector_helper_funcs 
exynos_dsi_connector_helper_funcs = {
.get_modes = exynos_dsi_get_modes,
-   .best_encoder = exynos_dsi_best_encoder,
 };
 
 static int exynos_dsi_create_connector(struct drm_encoder *encoder)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_vidi.c 
b/drivers/gpu/drm/exynos/exynos_drm_vidi.c
index 608b0af..e8f6c92 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_vidi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_vidi.c
@@ -378,16 +378,8 @@ static int vidi_get_modes(struct drm_connector *connector)
return drm_add_edid_modes(connector, edid);
 }
 
-static struct drm_encoder *vidi_best_encoder(struct drm_connector *connector)
-{
-   struct vidi_context *ctx = ctx_from_connector(connector);
-
-   return >encoder;
-}
-
 static const struct drm_connector_helper_funcs vidi_connector_helper_funcs = {
.get_modes = vidi_get_modes,
-   .best_encoder = vidi_best_encoder,
 };
 
 static int vidi_create_connector(struct drm_encoder *encoder)
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c 
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 58de5a4..1625d7c 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -937,17 +937,9 @@ static int hdmi_mode_valid(struct drm_connector *connector,
return MODE_OK;
 }
 
-static struct drm_encoder *hdmi_best_encoder(struct drm_connector *connector)
-{
-   struct hdmi_context *hdata = connector_to_hdmi(connector);
-
-   return >encoder;
-}
-
 static const struct drm_connector_helper_funcs hdmi_connector_helper_funcs = {
.get_modes = hdmi_get_modes,
.mode_valid = hdmi_mode_valid,
-   .best_encoder = hdmi_best_encoder,
 };
 
 static int hdmi_create_connector(struct drm_encoder *encoder)
-- 
2.7.4

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[Intel-gfx] [PATCH 02/20] drm: arc: Rely on the default ->best_encoder() behavior

[Boris Brezillon]

We have a 1:1 relationship between connectors and encoders and the
driver is relying on the atomic helpers: we can drop the custom
->best_encoder(), and let the core call drm_atomic_helper_best_encoder()
for us.

Signed-off-by: Boris Brezillon 
---
 drivers/gpu/drm/arc/arcpgu_hdmi.c | 18 --
 1 file changed, 18 deletions(-)

diff --git a/drivers/gpu/drm/arc/arcpgu_hdmi.c 
b/drivers/gpu/drm/arc/arcpgu_hdmi.c
index 08b6bae..b7a8b2a 100644
--- a/drivers/gpu/drm/arc/arcpgu_hdmi.c
+++ b/drivers/gpu/drm/arc/arcpgu_hdmi.c
@@ -46,23 +46,6 @@ static int arcpgu_drm_connector_get_modes(struct 
drm_connector *connector)
return sfuncs->get_modes(>base, connector);
 }
 
-struct drm_encoder *
-arcpgu_drm_connector_best_encoder(struct drm_connector *connector)
-{
-   struct drm_encoder_slave *slave;
-   struct arcpgu_drm_connector *con =
-   container_of(connector, struct arcpgu_drm_connector, connector);
-
-   slave = con->encoder_slave;
-   if (slave == NULL) {
-   dev_err(connector->dev->dev,
-   "connector_best_encoder: cannot find slave encoder for 
connector\n");
-   return NULL;
-   }
-
-   return >base;
-}
-
 static enum drm_connector_status
 arcpgu_drm_connector_detect(struct drm_connector *connector, bool force)
 {
@@ -97,7 +80,6 @@ static void arcpgu_drm_connector_destroy(struct drm_connector 
*connector)
 static const struct drm_connector_helper_funcs
 arcpgu_drm_connector_helper_funcs = {
.get_modes = arcpgu_drm_connector_get_modes,
-   .best_encoder = arcpgu_drm_connector_best_encoder,
 };
 
 static const struct drm_connector_funcs arcpgu_drm_connector_funcs = {
-- 
2.7.4

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[Intel-gfx] [PATCH] drm/atomic: Add __drm_atomic_get_current_plane_state

[Daniel Vetter]

... and use it in msm Again just want to encapsulate
drm_atomic_state internals a bit.

The const threading is a bit awkward in vc4 since C sucks, but I still
think it's worth to enforce this. Eventually I want to make all the
obj->state pointers const too, but that's a lot more work ...

v2: Provide safe macro to wrap up the unsafe helper better, suggested
by Maarten.

Cc: Eric Anholt 
Cc: Rob Clark 
Cc: Maarten Lankhorst 
Signed-off-by: Daniel Vetter 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 10 ++---
 drivers/gpu/drm/vc4/vc4_crtc.c   | 13 ++--
 drivers/gpu/drm/vc4/vc4_drv.h|  2 +-
 drivers/gpu/drm/vc4/vc4_plane.c  |  5 +++--
 include/drm/drm_atomic.h | 36 
 include/drm/drm_atomic_helper.h  | 24 +++--
 6 files changed, 66 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
index 88fe256c1931..4e8ed739f558 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
@@ -374,6 +374,7 @@ static int mdp5_crtc_atomic_check(struct drm_crtc *crtc,
struct drm_device *dev = crtc->dev;
struct plane_state pstates[STAGE_MAX + 1];
const struct mdp5_cfg_hw *hw_cfg;
+   const struct drm_plane_state *pstate;
int cnt = 0, i;
 
DBG("%s: check", mdp5_crtc->name);
@@ -382,20 +383,13 @@ static int mdp5_crtc_atomic_check(struct drm_crtc *crtc,
 * and that we don't have conflicting mixer stages:
 */
hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
-   drm_atomic_crtc_state_for_each_plane(plane, state) {
-   struct drm_plane_state *pstate;
+   drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
if (cnt >= (hw_cfg->lm.nb_stages)) {
dev_err(dev->dev, "too many planes!\n");
return -EINVAL;
}
 
-   pstate = state->state->plane_states[drm_plane_index(plane)];
 
-   /* plane might not have changed, in which case take
-* current state:
-*/
-   if (!pstate)
-   pstate = plane->state;
pstates[cnt].plane = plane;
pstates[cnt].state = to_mdp5_plane_state(pstate);
 
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index 904d0754ad78..ba2e373ec901 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -395,6 +395,7 @@ static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
struct vc4_dev *vc4 = to_vc4_dev(dev);
struct drm_plane *plane;
unsigned long flags;
+   const struct drm_plane_state *plane_state;
u32 dlist_count = 0;
int ret;
 
@@ -404,18 +405,8 @@ static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
if (hweight32(state->connector_mask) > 1)
return -EINVAL;
 
-   drm_atomic_crtc_state_for_each_plane(plane, state) {
-   struct drm_plane_state *plane_state =
-   state->state->plane_states[drm_plane_index(plane)];
-
-   /* plane might not have changed, in which case take
-* current state:
-*/
-   if (!plane_state)
-   plane_state = plane->state;
-
+   drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, state)
dlist_count += vc4_plane_dlist_size(plane_state);
-   }
 
dlist_count++; /* Account for SCALER_CTL0_END. */
 
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index 37cac59401d7..c799baabc008 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -469,7 +469,7 @@ int vc4_kms_load(struct drm_device *dev);
 struct drm_plane *vc4_plane_init(struct drm_device *dev,
 enum drm_plane_type type);
 u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist);
-u32 vc4_plane_dlist_size(struct drm_plane_state *state);
+u32 vc4_plane_dlist_size(const struct drm_plane_state *state);
 void vc4_plane_async_set_fb(struct drm_plane *plane,
struct drm_framebuffer *fb);
 
diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c
index 4037b52fde31..5d2c3d9fd17a 100644
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
@@ -690,9 +690,10 @@ u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 
__iomem *dlist)
return vc4_state->dlist_count;
 }
 
-u32 vc4_plane_dlist_size(struct drm_plane_state *state)
+u32 vc4_plane_dlist_size(const struct drm_plane_state *state)
 {
-   struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
+   const struct vc4_plane_state 

[Intel-gfx] ✗ Ro.CI.BAT: warning for kbl and gen9 workarounds (rev10)

[Patchwork]

== Series Details ==

Series: kbl and gen9 workarounds (rev10)
URL   : https://patchwork.freedesktop.org/series/7824/
State : warning

== Summary ==

Series 7824v10 kbl and gen9 workarounds
http://patchwork.freedesktop.org/api/1.0/series/7824/revisions/10/mbox

Test core_auth:
Subgroup basic-auth:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Test gem_cs_tlb:
Subgroup basic-default:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Test gem_exec_flush:
Subgroup basic-uc-pro-default:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Subgroup basic-uc-prw-default:
pass   -> DMESG-WARN (ro-skl-i7-6700hq)
Subgroup basic-uc-ro-default:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Subgroup basic-wb-rw-default:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Test gem_mmap_gtt:
Subgroup basic-copy:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Subgroup basic-small-copy:
pass   -> DMESG-WARN (ro-skl-i7-6700hq)
Subgroup basic-small-copy-xy:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Subgroup basic-write-cpu-read-gtt:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Subgroup basic-write-gtt:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Subgroup basic-write-no-prefault:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Test kms_addfb_basic:
Subgroup bad-pitch-1024:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Subgroup bad-pitch-256:
pass   -> DMESG-WARN (ro-skl-i7-6700hq)
Test kms_frontbuffer_tracking:
Subgroup basic:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)
Test kms_psr_sink_crc:
Subgroup psr_basic:
dmesg-warn -> PASS   (ro-skl-i7-6700hq)

fi-bdw-i7-5557u  total:102  pass:93   dwarn:0   dfail:0   fail:0   skip:8  
fi-hsw-i7-4770k  total:209  pass:190  dwarn:0   dfail:0   fail:0   skip:19 
fi-skl-i5-6260u  total:209  pass:198  dwarn:0   dfail:0   fail:0   skip:11 
fi-skl-i7-6700k  total:209  pass:184  dwarn:0   dfail:0   fail:0   skip:25 
fi-snb-i7-2600   total:209  pass:170  dwarn:0   dfail:0   fail:0   skip:39 
ro-bdw-i5-5250u  total:102  pass:93   dwarn:0   dfail:0   fail:0   skip:8  
ro-bdw-i7-5600u  total:102  pass:75   dwarn:0   dfail:0   fail:0   skip:26 
ro-bsw-n3050 total:209  pass:168  dwarn:0   dfail:0   fail:2   skip:39 
ro-byt-n2820 total:209  pass:169  dwarn:0   dfail:0   fail:3   skip:37 
ro-hsw-i3-4010u  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
ro-hsw-i7-4770r  total:82   pass:64   dwarn:0   dfail:0   fail:0   skip:17 
ro-ilk-i7-620lm  total:1pass:0dwarn:0   dfail:0   fail:0   skip:0  
ro-ilk1-i5-650   total:204  pass:146  dwarn:0   dfail:0   fail:1   skip:57 
ro-ivb-i7-3770   total:102  pass:75   dwarn:0   dfail:0   fail:0   skip:26 
ro-skl-i7-6700hq total:204  pass:179  dwarn:4   dfail:0   fail:0   skip:21 
ro-snb-i7-2620M  total:102  pass:72   dwarn:0   dfail:0   fail:0   skip:29 
ro-bdw-i7-5557U failed to connect after reboot
ro-hsw-i7-4770r failed to connect after reboot
ro-ivb2-i7-3770 failed to connect after reboot

Results at /archive/results/CI_IGT_test/RO_Patchwork_1081/

4e3459b drm-intel-nightly: 2016y-06m-02d-13h-13m-15s UTC integration manifest
7e89439 drm/i915/kbl: Add WaClearSlmSpaceAtContextSwitch
0aa2541 drm/i915/skl: Extend WaDisableChickenBitTSGBarrierAckForFFSliceCS
7546564 drm/i195/fbc: Add WaFbcNukeOnHostModify
0b2bb0b drm/i915/gen9: Add WaFbcWakeMemOn
c2f3d1a drm/i915/gen9: Add WaFbcTurnOffFbcWatermark
3f274e4 drm/i915/gen9: Add WaEnableChickenDCPR
1afd252 drm/i915/kbl: Add WaDisableSbeCacheDispatchPortSharing
80f10d3 drm/i915: Add WaDisableGafsUnitClkGating for skl and kbl
d56bd66 drm/i915/kbl: Add WaForGAMHang
08e79fb drm/i915/skl: Add WAC6entrylatency
6d9fe0b drm/i915/gen9: Add WaDisableSkipCaching
c366d38 drm/i915: Add WaInsertDummyPushConstP for bxt and kbl
06fe4e4 drm/i915/kbl: Add WaDisableDynamicCreditSharing
91f49b1 drm/i915/kbl: Add WaDisableGamClockGating
5212c7d drm/i915/gen9: Enable must set chicken bits in config0 reg
2857496 drm/i915/kbl: Add WaDisableLSQCROPERFforOCL
c584a14 drm/i915/edp: Add WaKVMNotificationOnConfigChange:bdw
7b07109 drm/i915/kbl: Add WaDisableSDEUnitClockGating
31a2da0 drm/i915/kbl: Add WaDisableFenceDestinationToSLM for A0
49a8ed3 drm/i915/kbl: Add WaEnableGapsTsvCreditFix
84b17d8 drm/i915: Mimic skl with WaForceEnableNonCoherent
cf79504 drm/i915/gen9: Always apply WaForceContextSaveRestoreNonCoherent
6757b15 drm/i915/kbl: Add WaSkipStolenMemoryFirstPage for A0
dbf3c22 drm/i915/kbl: Add REVID macro
55d9b47 drm/i915/kbl: Init gen9 workarounds

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Re: [Intel-gfx] [PATCH 08/38] drm/atomic: Add __drm_atomic_get_current_plane_state

[Maarten Lankhorst]

Op 02-06-16 om 00:06 schreef Daniel Vetter:
> ... and use it in msm Again just want to encapsulate
> drm_atomic_state internals a bit.
>
> The const threading is a bit awkward in vc4 since C sucks, but I still
> think it's worth to enforce this. Eventually I want to make all the
> obj->state pointers const too, but that's a lot more work ...
>
Maybe instead of exposing such a dangerous function, wrap it in something like

drm_atomic_crtc_state_for_each_plane_state, which returns either 
get_current_plane_state or plane->state?

The only times this function is used is when iterating over all plane states a 
anyway, and it would be useful for i915 too.

~Maarten

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Re: [Intel-gfx] [PATCH 06/38] drm/omap: Use for_each_plane_in_state

[Daniel Vetter]

On Thu, Jun 02, 2016 at 03:23:18PM +0200, Maarten Lankhorst wrote:
> Op 02-06-16 om 00:06 schreef Daniel Vetter:
> > We want to hide drm_atomic_stat internals a bit better.
> >
> > Cc: Laurent Pinchart 
> > Cc: Tomi Valkeinen 
> > Signed-off-by: Daniel Vetter 
> > ---
> >  drivers/gpu/drm/omapdrm/omap_drv.c | 11 +--
> >  1 file changed, 5 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/omapdrm/omap_drv.c 
> > b/drivers/gpu/drm/omapdrm/omap_drv.c
> > index d86f5479345b..4798ba43ff5b 100644
> > --- a/drivers/gpu/drm/omapdrm/omap_drv.c
> > +++ b/drivers/gpu/drm/omapdrm/omap_drv.c
> > @@ -142,8 +142,9 @@ static int omap_atomic_commit(struct drm_device *dev,
> >  {
> > struct omap_drm_private *priv = dev->dev_private;
> > struct omap_atomic_state_commit *commit;
> > -   unsigned int i;
> > -   int ret;
> > +   struct drm_crtc *crtc;
> > +   struct drm_crtc_state *crtc_state;
> > +   int i, ret;
> >  
> > ret = drm_atomic_helper_prepare_planes(dev, state);
> > if (ret)
> > @@ -163,10 +164,8 @@ static int omap_atomic_commit(struct drm_device *dev,
> > /* Wait until all affected CRTCs have completed previous commits and
> >  * mark them as pending.
> >  */
> > -   for (i = 0; i < dev->mode_config.num_crtc; ++i) {
> > -   if (state->crtcs[i])
> > -   commit->crtcs |= 1 << drm_crtc_index(state->crtcs[i]);
> > -   }
> > +   for_each_crtc_in_state(state, crtc, crtc_state, i)
> > +   commit->crtcs |= 1 << drm_crtc_index(crtc);
> >  
> > wait_event(priv->commit.wait, !omap_atomic_is_pending(priv, commit));
> >  
> 
> (again 1 << index -> crtc_mask)
> 
> Reviewed-by: Maarten Lankhorst 

Again fixed up, thanks for the review.
-Daniel
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Re: [Intel-gfx] [PATCH 04/38] drm/rcar-du: Use for_each_*_in_state

[Daniel Vetter]

On Thu, Jun 02, 2016 at 03:14:30PM +0200, Maarten Lankhorst wrote:
> Op 02-06-16 om 00:06 schreef Daniel Vetter:
> > We want to hide drm_atomic_state internals better.
> >
> > Cc: Laurent Pinchart 
> > Signed-off-by: Daniel Vetter 
> > ---
> >  drivers/gpu/drm/rcar-du/rcar_du_kms.c   |  8 
> >  drivers/gpu/drm/rcar-du/rcar_du_plane.c | 20 
> >  2 files changed, 12 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c 
> > b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> > index e70a4f33d970..f315c55c1f65 100644
> > --- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> > +++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> > @@ -288,6 +288,8 @@ static int rcar_du_atomic_commit(struct drm_device *dev,
> >  {
> > struct rcar_du_device *rcdu = dev->dev_private;
> > struct rcar_du_commit *commit;
> > +   struct drm_crtc *crtc;
> > +   struct drm_crtc_state *crtc_state;
> > unsigned int i;
> > int ret;
> >  
> > @@ -309,10 +311,8 @@ static int rcar_du_atomic_commit(struct drm_device 
> > *dev,
> > /* Wait until all affected CRTCs have completed previous commits and
> >  * mark them as pending.
> >  */
> > -   for (i = 0; i < dev->mode_config.num_crtc; ++i) {
> > -   if (state->crtcs[i])
> > -   commit->crtcs |= 1 << drm_crtc_index(state->crtcs[i]);
> > -   }
> > +   for_each_crtc_in_state(state, crtc, crtc_state, i)
> > +   commit->crtcs |= 1 << drm_crtc_index(crtc);
> >  
> Maybe also change this one to _mask,
> either way.
> 
> Reviewed-by: Maarten Lankhorst 

Fixed up, thanks for the review.
-Daniel
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Re: [Intel-gfx] [PATCH 02/38] drm/i915: Use drm_atomic_get_existing_plane_state

[Daniel Vetter]

On Thu, Jun 02, 2016 at 01:25:46PM +0200, Maarten Lankhorst wrote:
> Op 02-06-16 om 00:06 schreef Daniel Vetter:
> > We want to encapsulate the drm_atomic_state internals.
> >
> > Signed-off-by: Daniel Vetter 
> > ---
> >  drivers/gpu/drm/i915/intel_atomic.c | 4 +++-
> >  1 file changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_atomic.c 
> > b/drivers/gpu/drm/i915/intel_atomic.c
> > index 50ff90aea721..3e6d9ff8840a 100644
> > --- a/drivers/gpu/drm/i915/intel_atomic.c
> > +++ b/drivers/gpu/drm/i915/intel_atomic.c
> > @@ -223,7 +223,9 @@ int intel_atomic_setup_scalers(struct drm_device *dev,
> > continue;
> > }
> >  
> > -   plane_state = 
> > to_intel_plane_state(drm_state->plane_states[i]);
> > +   plane_state = to_intel_plane_state(
> > +   drm_atomic_get_existing_plane_state(drm_state,
> > +   plane));
> > scaler_id = _state->scaler_id;
> > }
> >  
> intel_plane_get_atomic_state(drm_state, intel_plane); ?
> 
> If fixed,
> 
> Reviewed-by: Maarten Lankhorst 

Fixed to drm-misc, thanks for the review.
-Daniel
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Re: [Intel-gfx] [PATCH 07/38] drm/exynos: Use for_each_crtc_in_state

[Maarten Lankhorst]

Op 02-06-16 om 00:06 schreef Daniel Vetter:
> We want to hide drm_atomic_state internals better.
>
> Cc: Inki Dae 
> Acked-by: Inki Dae 
> Signed-off-by: Daniel Vetter 
> ---
>  drivers/gpu/drm/exynos/exynos_drm_drv.c | 8 
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.c 
> b/drivers/gpu/drm/exynos/exynos_drm_drv.c
> index 2dd820e23b0c..cabc5fd0246d 100644
> --- a/drivers/gpu/drm/exynos/exynos_drm_drv.c
> +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.c
> @@ -267,6 +267,8 @@ int exynos_atomic_commit(struct drm_device *dev, struct 
> drm_atomic_state *state,
>  {
>   struct exynos_drm_private *priv = dev->dev_private;
>   struct exynos_atomic_commit *commit;
> + struct drm_crtc *crtc;
> + struct drm_crtc_state *crtc_state;
>   int i, ret;
>  
>   commit = kzalloc(sizeof(*commit), GFP_KERNEL);
> @@ -288,10 +290,8 @@ int exynos_atomic_commit(struct drm_device *dev, struct 
> drm_atomic_state *state,
>   /* Wait until all affected CRTCs have completed previous commits and
>* mark them as pending.
>*/
> - for (i = 0; i < dev->mode_config.num_crtc; ++i) {
> - if (state->crtcs[i])
> - commit->crtcs |= 1 << drm_crtc_index(state->crtcs[i]);
> - }
> + for_each_crtc_in_state(state, crtc, crtc_state, i)
> + commit->crtcs |= 1 << drm_crtc_index(crtc);
>  
>   wait_event(priv->wait, !commit_is_pending(priv, commit->crtcs));
>  

Reviewed-by: Maarten Lankhorst 

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Re: [Intel-gfx] [PATCH 16/38] drm/hdlcd: Clean up crtc hooks

[Daniel Vetter]

On Thu, Jun 02, 2016 at 12:06:39AM +0200, Daniel Vetter wrote:
> Those are all no longer needed for a pure atomic driver.
> 
> Cc: Liviu Dudau 
> Tested-by: Liviu Dudau 
> Acked-by: Liviu Dudau 
> Signed-off-by: Daniel Vetter 

Applied this one to drm-misc, since Liviua already acked it. The other
prep patch is already in a -fixes pull request.
-Daniel

> ---
>  drivers/gpu/drm/arm/hdlcd_crtc.c | 19 ---
>  1 file changed, 19 deletions(-)
> 
> diff --git a/drivers/gpu/drm/arm/hdlcd_crtc.c 
> b/drivers/gpu/drm/arm/hdlcd_crtc.c
> index fef1b04c2aab..b44f72722764 100644
> --- a/drivers/gpu/drm/arm/hdlcd_crtc.c
> +++ b/drivers/gpu/drm/arm/hdlcd_crtc.c
> @@ -196,30 +196,11 @@ static void hdlcd_crtc_atomic_begin(struct drm_crtc 
> *crtc,
>   }
>  }
>  
> -static void hdlcd_crtc_atomic_flush(struct drm_crtc *crtc,
> - struct drm_crtc_state *state)
> -{
> -}
> -
> -static bool hdlcd_crtc_mode_fixup(struct drm_crtc *crtc,
> - const struct drm_display_mode *mode,
> - struct drm_display_mode *adjusted_mode)
> -{
> - return true;
> -}
> -
>  static const struct drm_crtc_helper_funcs hdlcd_crtc_helper_funcs = {
> - .mode_fixup = hdlcd_crtc_mode_fixup,
> - .mode_set   = drm_helper_crtc_mode_set,
> - .mode_set_base  = drm_helper_crtc_mode_set_base,
> - .mode_set_nofb  = hdlcd_crtc_mode_set_nofb,
>   .enable = hdlcd_crtc_enable,
>   .disable= hdlcd_crtc_disable,
> - .prepare= hdlcd_crtc_disable,
> - .commit = hdlcd_crtc_enable,
>   .atomic_check   = hdlcd_crtc_atomic_check,
>   .atomic_begin   = hdlcd_crtc_atomic_begin,
> - .atomic_flush   = hdlcd_crtc_atomic_flush,
>  };
>  
>  static int hdlcd_plane_atomic_check(struct drm_plane *plane,
> -- 
> 2.8.1
> 

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Re: [Intel-gfx] [PATCH 05/38] drm/vc4: Use for_each_plane_in_state

[Maarten Lankhorst]

Op 02-06-16 om 00:06 schreef Daniel Vetter:
> We want to hide drm_atomic_stat internals a bit better.
>
> Cc: Eric Anholt 
> Signed-off-by: Daniel Vetter 
Reviewed-by: Maarten Lankhorst 
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Re: [Intel-gfx] [PATCH v9 4/6] drm/i915: Interrupt driven fences

[Tvrtko Ursulin]

On 01/06/16 18:07, john.c.harri...@intel.com wrote:

From: John Harrison 

The intended usage model for struct fence is that the signalled status
should be set on demand rather than polled. That is, there should not
be a need for a 'signaled' function to be called everytime the status
is queried. Instead, 'something' should be done to enable a signal
callback from the hardware which will update the state directly. In
the case of requests, this is the seqno update interrupt. The idea is
that this callback will only be enabled on demand when something
actually tries to wait on the fence.

This change removes the polling test and replaces it with the callback
scheme. Each fence is added to a 'please poke me' list at the start of
i915_add_request(). The interrupt handler then scans through the 'poke
me' list when a new seqno pops out and signals any matching
fence/request. The fence is then removed from the list so the entire
request stack does not need to be scanned every time. Note that the
fence is added to the list before the commands to generate the seqno
interrupt are added to the ring. Thus the sequence is guaranteed to be
race free if the interrupt is already enabled.

Note that the interrupt is only enabled on demand (i.e. when
__wait_request() is called). Thus there is still a potential race when
enabling the interrupt as the request may already have completed.
However, this is simply solved by calling the interrupt processing
code immediately after enabling the interrupt and thereby checking for
already completed requests.

Lastly, the ring clean up code has the possibility to cancel
outstanding requests (e.g. because TDR has reset the ring). These
requests will never get signalled and so must be removed from the
signal list manually. This is done by setting a 'cancelled' flag and
then calling the regular notify/retire code path rather than
attempting to duplicate the list manipulatation and clean up code in
multiple places. This also avoid any race condition where the
cancellation request might occur after/during the completion interrupt
actually arriving.

v2: Updated to take advantage of the request unreference no longer
requiring the mutex lock.

v3: Move the signal list processing around to prevent unsubmitted
requests being added to the list. This was occurring on Android
because the native sync implementation calls the
fence->enable_signalling API immediately on fence creation.

Updated after review comments by Tvrtko Ursulin. Renamed list nodes to
'link' instead of 'list'. Added support for returning an error code on
a cancelled fence. Update list processing to be more efficient/safer
with respect to spinlocks.

v5: Made i915_gem_request_submit a static as it is only ever called
from one place.

Fixed up the low latency wait optimisation. The time delay between the
seqno value being to memory and the drive's ISR running can be
significant, at least for the wait request micro-benchmark. This can
be greatly improved by explicitly checking for seqno updates in the
pre-wait busy poll loop. Also added some documentation comments to the
busy poll code.

Fixed up support for the faking of lost interrupts
(test_irq_rings/missed_irq_rings). That is, there is an IGT test that
tells the driver to loose interrupts deliberately and then check that
everything still works as expected (albeit much slower).

Updates from review comments: use non IRQ-save spinlocking, early exit
on WARN and improved comments (Tvrtko Ursulin).

v6: Updated to newer nigthly and resolved conflicts around the
wait_request busy spin optimisation. Also fixed a race condition
between this early exit path and the regular completion path.

v7: Updated to newer nightly - lots of ring -> engine renaming plus an
interface change on get_seqno(). Also added a list_empty() check
before acquring spinlocks and doing list processing.

v8: Updated to newer nightly - changes to request clean up code mean
non of the deferred free mess is needed any more.

v9: Moved the request completion processing out of the interrupt
handler and into a worker thread (Chris Wilson).

For: VIZ-5190
Signed-off-by: John Harrison 
Cc: Tvrtko Ursulin 
Cc: Maarten Lankhorst 
---
  drivers/gpu/drm/i915/i915_dma.c |   9 +-
  drivers/gpu/drm/i915/i915_drv.h |  11 ++
  drivers/gpu/drm/i915/i915_gem.c | 248 +---
  drivers/gpu/drm/i915/i915_irq.c |   2 +
  drivers/gpu/drm/i915/intel_lrc.c|   5 +
  drivers/gpu/drm/i915/intel_ringbuffer.c |   5 +
  drivers/gpu/drm/i915/intel_ringbuffer.h |   3 +
  7 files changed, 260 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 07edaed..f8f60bb 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1019,9 +1019,13 @@ static int i915_workqueues_init(struct 

Re: [Intel-gfx] [PATCH 06/38] drm/omap: Use for_each_plane_in_state

[Maarten Lankhorst]

Op 02-06-16 om 00:06 schreef Daniel Vetter:
> We want to hide drm_atomic_stat internals a bit better.
>
> Cc: Laurent Pinchart 
> Cc: Tomi Valkeinen 
> Signed-off-by: Daniel Vetter 
> ---
>  drivers/gpu/drm/omapdrm/omap_drv.c | 11 +--
>  1 file changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/omapdrm/omap_drv.c 
> b/drivers/gpu/drm/omapdrm/omap_drv.c
> index d86f5479345b..4798ba43ff5b 100644
> --- a/drivers/gpu/drm/omapdrm/omap_drv.c
> +++ b/drivers/gpu/drm/omapdrm/omap_drv.c
> @@ -142,8 +142,9 @@ static int omap_atomic_commit(struct drm_device *dev,
>  {
>   struct omap_drm_private *priv = dev->dev_private;
>   struct omap_atomic_state_commit *commit;
> - unsigned int i;
> - int ret;
> + struct drm_crtc *crtc;
> + struct drm_crtc_state *crtc_state;
> + int i, ret;
>  
>   ret = drm_atomic_helper_prepare_planes(dev, state);
>   if (ret)
> @@ -163,10 +164,8 @@ static int omap_atomic_commit(struct drm_device *dev,
>   /* Wait until all affected CRTCs have completed previous commits and
>* mark them as pending.
>*/
> - for (i = 0; i < dev->mode_config.num_crtc; ++i) {
> - if (state->crtcs[i])
> - commit->crtcs |= 1 << drm_crtc_index(state->crtcs[i]);
> - }
> + for_each_crtc_in_state(state, crtc, crtc_state, i)
> + commit->crtcs |= 1 << drm_crtc_index(crtc);
>  
>   wait_event(priv->commit.wait, !omap_atomic_is_pending(priv, commit));
>  

(again 1 << index -> crtc_mask)

Reviewed-by: Maarten Lankhorst 

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Re: [Intel-gfx] [PATCH 24/24] drm/i915/skl: Extend WaDisableChickenBitTSGBarrierAckForFFSliceCS

[Matthew Auld]

Reviewed-by: Matthew Auld 
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Re: [Intel-gfx] [PATCH 19/24] drm/i915/kbl: Add WaDisableSbeCacheDispatchPortSharing

[Matthew Auld]

Reviewed-by: Matthew Auld 
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Re: [Intel-gfx] [PATCH 04/38] drm/rcar-du: Use for_each_*_in_state

[Maarten Lankhorst]

Op 02-06-16 om 00:06 schreef Daniel Vetter:
> We want to hide drm_atomic_state internals better.
>
> Cc: Laurent Pinchart 
> Signed-off-by: Daniel Vetter 
> ---
>  drivers/gpu/drm/rcar-du/rcar_du_kms.c   |  8 
>  drivers/gpu/drm/rcar-du/rcar_du_plane.c | 20 
>  2 files changed, 12 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c 
> b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> index e70a4f33d970..f315c55c1f65 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> @@ -288,6 +288,8 @@ static int rcar_du_atomic_commit(struct drm_device *dev,
>  {
>   struct rcar_du_device *rcdu = dev->dev_private;
>   struct rcar_du_commit *commit;
> + struct drm_crtc *crtc;
> + struct drm_crtc_state *crtc_state;
>   unsigned int i;
>   int ret;
>  
> @@ -309,10 +311,8 @@ static int rcar_du_atomic_commit(struct drm_device *dev,
>   /* Wait until all affected CRTCs have completed previous commits and
>* mark them as pending.
>*/
> - for (i = 0; i < dev->mode_config.num_crtc; ++i) {
> - if (state->crtcs[i])
> - commit->crtcs |= 1 << drm_crtc_index(state->crtcs[i]);
> - }
> + for_each_crtc_in_state(state, crtc, crtc_state, i)
> + commit->crtcs |= 1 << drm_crtc_index(crtc);
>  
Maybe also change this one to _mask,
either way.

Reviewed-by: Maarten Lankhorst 
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Re: [Intel-gfx] [PATCH 03/38] drm/msm: Use for_each_*_in_state

[Maarten Lankhorst]

Op 02-06-16 om 00:06 schreef Daniel Vetter:
> We want to hide drm_atomic_state internals
>
> Cc: Rob Clark 
> Signed-off-by: Daniel Vetter 
> ---
>  drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c| 20 +++--
>  drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c| 12 +++---
>  drivers/gpu/drm/msm/msm_atomic.c   | 35 
> ++
>  drivers/gpu/drm/rockchip/rockchip_drm_fb.c |  1 +
>  4 files changed, 23 insertions(+), 45 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c 
> b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c
> index 67442d50a6c2..f145d256e332 100644
> --- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c
> +++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c
> @@ -106,31 +106,27 @@ out:
>  static void mdp4_prepare_commit(struct msm_kms *kms, struct drm_atomic_state 
> *state)
>  {
>   struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
> - int i, ncrtcs = state->dev->mode_config.num_crtc;
> + int i;
> + struct drm_crtc *crtc;
> + struct drm_crtc_state *crtc_state;
>  
>   mdp4_enable(mdp4_kms);
>  
>   /* see 119ecb7fd */
> - for (i = 0; i < ncrtcs; i++) {
> - struct drm_crtc *crtc = state->crtcs[i];
> - if (!crtc)
> - continue;
> + for_each_crtc_in_state(state, crtc, crtc_state, i)
>   drm_crtc_vblank_get(crtc);
> - }
>  }
>  
>  static void mdp4_complete_commit(struct msm_kms *kms, struct 
> drm_atomic_state *state)
>  {
>   struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
> - int i, ncrtcs = state->dev->mode_config.num_crtc;
> + int i;
> + struct drm_crtc *crtc;
> + struct drm_crtc_state *crtc_state;
>  
>   /* see 119ecb7fd */
> - for (i = 0; i < ncrtcs; i++) {
> - struct drm_crtc *crtc = state->crtcs[i];
> - if (!crtc)
> - continue;
> + for_each_crtc_in_state(state, crtc, crtc_state, i)
>   drm_crtc_vblank_put(crtc);
> - }
>  
>   mdp4_disable(mdp4_kms);
>  }
> diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c 
> b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
> index 484b4d15e71d..f0c285b1c027 100644
> --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
> +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
> @@ -78,17 +78,11 @@ static void mdp5_complete_commit(struct msm_kms *kms, 
> struct drm_atomic_state *s
>  {
>   int i;
>   struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
> - int nplanes = mdp5_kms->dev->mode_config.num_total_plane;
> -
> - for (i = 0; i < nplanes; i++) {
> - struct drm_plane *plane = state->planes[i];
> - struct drm_plane_state *plane_state = state->plane_states[i];
> -
> - if (!plane)
> - continue;
> + struct drm_plane *plane;
> + struct drm_plane_state *plane_state;
>  
> + for_each_plane_in_state(state, plane, plane_state, i)
>   mdp5_plane_complete_commit(plane, plane_state);
> - }
>  
>   mdp5_disable(mdp5_kms);
>  }
> diff --git a/drivers/gpu/drm/msm/msm_atomic.c 
> b/drivers/gpu/drm/msm/msm_atomic.c
> index e3892c263f27..9c0e4261dbba 100644
> --- a/drivers/gpu/drm/msm/msm_atomic.c
> +++ b/drivers/gpu/drm/msm/msm_atomic.c
> @@ -84,17 +84,12 @@ static void msm_atomic_wait_for_commit_done(struct 
> drm_device *dev,
>   struct drm_atomic_state *old_state)
>  {
>   struct drm_crtc *crtc;
> + struct drm_crtc_state *crtc_state;
>   struct msm_drm_private *priv = old_state->dev->dev_private;
>   struct msm_kms *kms = priv->kms;
> - int ncrtcs = old_state->dev->mode_config.num_crtc;
>   int i;
>  
> - for (i = 0; i < ncrtcs; i++) {
> - crtc = old_state->crtcs[i];
> -
> - if (!crtc)
> - continue;
> -
> + for_each_crtc_in_state(old_state, crtc, crtc_state, i) {
>   if (!crtc->state->enable)
>   continue;
>  
> @@ -192,9 +187,11 @@ int msm_atomic_commit(struct drm_device *dev,
>   struct drm_atomic_state *state, bool nonblock)
>  {
>   struct msm_drm_private *priv = dev->dev_private;
> - int nplanes = dev->mode_config.num_total_plane;
> - int ncrtcs = dev->mode_config.num_crtc;
>   struct msm_commit *c;
> + struct drm_crtc *crtc;
> + struct drm_crtc_state *crtc_state;
> + struct drm_plane *plane;
> + struct drm_plane_state *plane_state;
>   int i, ret;
>  
>   ret = drm_atomic_helper_prepare_planes(dev, state);
> @@ -210,28 +207,18 @@ int msm_atomic_commit(struct drm_device *dev,
>   /*
>* Figure out what crtcs we have:
>*/
> - for (i = 0; i < ncrtcs; i++) {
> - struct drm_crtc *crtc = state->crtcs[i];
> - if (!crtc)
> - continue;
> + for_each_crtc_in_state(state, crtc, crtc_state, i)
>   c->crtc_mask |= (1 << drm_crtc_index(crtc));
Maybe also 

[Intel-gfx] ✗ Ro.CI.BAT: failure for nonblocking atomic commits for everyone!

[Patchwork]

== Series Details ==

Series: nonblocking atomic commits for everyone!
URL   : https://patchwork.freedesktop.org/series/8119/
State : failure

== Summary ==

Applying: drm/atomic-helper: use for_each_*_in_state more
Applying: drm/i915: Use drm_atomic_get_existing_plane_state
Applying: drm/msm: Use for_each_*_in_state
Applying: drm/rcar-du: Use for_each_*_in_state
Applying: drm/vc4: Use for_each_plane_in_state
Applying: drm/omap: Use for_each_plane_in_state
Applying: drm/exynos: Use for_each_crtc_in_state
Applying: drm/atomic: Add __drm_atomic_get_current_plane_state
Applying: drm: Consolidate connector arrays in drm_atomic_state
Applying: drm: Consolidate plane arrays in drm_atomic_state
Applying: drm: Consolidate crtc arrays in drm_atomic_state
Applying: drm/fence: add fence to drm_pending_event
Applying: drm/atomic-helper: Massage swap_state signature somewhat
Applying: drm/arc: Nuke event_list
Applying: drm/arc: Actually bother with handling atomic events.
Applying: drm/hdlcd: Clean up crtc hooks
Applying: drm/hdlcd: Fix up crtc_state->event handling
Applying: drm/fsl-du: Implement some semblance of vblank event handling
Applying: drm/hisilicon: Implement some semblance of vblank event handling
Applying: drm/sun4i: Implement some semblance of vblank event handling
Applying: drm/atomic: kerneldoc for drm_atomic_crtc_needs_modeset
Applying: drm/atomic-helper: nonblocking commit support
Applying: drm/hdlcd: Use helper support for nonblocking commits
Applying: drm/arc: Implement nonblocking commit correctly
Applying: drm/i915: Signal drm events for atomic
Applying: drm/i915: Roll out the helper nonblock tracking
Applying: drm/i915: nonblocking commit
Applying: drm/i915: Use atomic commits for legacy page_flips
Applying: drm/i915: Move fb_bits updating later in atomic_commit
Applying: drm/rockchip: Disarm vop->is_enabled
Applying: drm/rockchip: Fix crtc_state->event signalling
Applying: drm/rockchip: convert to helper nonblocking atomic commit
Applying: drm/rockchip: Nuke pending event handling in preclose
Applying: drm/virtio: Don't reinvent a flipping wheel
Applying: drm: Replace fb_helper->atomic with mode_config->atomic_commit
Applying: drm: Resurrect atomic rmfb code
Patch failed at 0036 drm: Resurrect atomic rmfb code
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

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Re: [Intel-gfx] [PATCH 16/24] drm/i915/skl: Add WAC6entrylatency

[Matthew Auld]

Reviewed-by: Matthew Auld 
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Re: [Intel-gfx] [PATCH v4 1/1] drm/i915: Update GEN6_PMINTRMSK setup with GuC enabled

[Chris Wilson]

On Thu, Jun 02, 2016 at 05:42:08PM +0530, Kamble, Sagar A wrote:
> On 6/1/2016 7:59 PM, Matt Roper wrote:
> >Hmm, I guess is misunderstood the message thread flow here and didn't
> >realize there was another patch necessary as well.  I did find that just
> >this one patch caused the IGT to start passing where it had failed
> >before (on BXT), so not sure why I didn't run into problems.  I did
> >merge in a couple un-related TSC patches (required to keep my BXT stable
> >in general) before testing, but I don't think that would have changed
> >the behavior here.
> Testcase did not catch it because guc loading/submission is disabled
> by default.

That's the unspoken question, to make sure that the testcase is
sufficient (in case we needed a new test).

> I have submitted BAT request with guc loading/submission enabled on trybot.
> Waiting for the results.

Ah, you need to send the patches as a single series. Pull them into a
local branch, then git send-email -4 --to trybot.

Fwiw, this is the script I use:

#!/bin/bash

COMMIT=$1
INTEL=intel
DIN=${INTEL}/drm-intel-nightly

git fetch ${INTEL}
git merge-base --is-ancestor ${DIN} ${COMMIT:-HEAD} || {
echo Tree is out of date
exit 1
}

git send-email --to intel-gfx-try...@lists.freedesktop.org --suppress-cc=all 
${DIN}..${COMMIT}

Definitely not fool^Wmeproof!
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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