Re: [Intel-gfx] Skylake / (EE) modeset(0): present flip failed loop

[Marc MERLIN]

Is this the right place to send this?
Can anyone help?

On Wed, Jul 05, 2017 at 11:33:01PM -0700, Marc MERLIN wrote:
> Howdy,
> 
> I have a thinkpad P70 with debian testing and 4.11.6 kernel.
> A recent-ish upgrade broke something and now I'm getting loads of spam
> in my Xorg.log
> 
> [  5031.435] (WW) modeset(0): flip queue failed: Invalid argument
> [  5031.435] (WW) modeset(0): Page flip failed: Invalid argument
> [  5031.435] (EE) modeset(0): present flip failed
> [  5031.519] (WW) modeset(0): flip queue failed: Invalid argument
> [  5031.519] (WW) modeset(0): Page flip failed: Invalid argument
> [  5031.519] (EE) modeset(0): present flip failed
> (...)
> 
> system info:
> ii  libdrm-intel1:amd642.4.74-1   
> ii  xserver-xorg-core  2:1.19.2-1  
> ii  xserver-xorg-video-intel   2:2.99.917+git20161206-1
> 
> 4.11.6-amd64-preempt
> 
> saruman:~$ xrandr --listproviders
> Providers: number : 2
> Provider 0: id: 0x7a cap: 0xf, Source Output, Sink Output, Source Offload, 
> Sink Offload crtcs: 3 outputs: 1 associated providers: 0 name:modesetting
> Provider 1: id: 0x46 cap: 0xf, Source Output, Sink Output, Source Offload, 
> Sink Offload crtcs: 4 outputs: 3 associated providers: 0 name:modesetting
> 
> [73.575] (II) xfree86: Adding drm device (/dev/dri/card1)
> [73.576] (II) xfree86: Adding drm device (/dev/dri/card0)
> [73.588] (--) PCI:*(0:0:2:0) 8086:191b:17aa:222d rev 6, Mem @ 
> 0xd200/16777216, 0x6000/536870912, I/O @ 0x6000/64, BIOS @ 
> 0x/131072
> [73.588] (--) PCI: (0:1:0:0) 10de:13b2:17aa:222d rev 162, Mem @ 
> 0xd300/16777216, 0xc000/268435456, 0xd000/33554432, I/O @ 
> 0x5000/128, BIOS @ 0x/524288
> [73.597] (II) LoadModule: "modesetting"
> [73.597] (II) Loading /usr/lib/xorg/modules/drivers/modesetting_drv.so
> [73.598] (II) Module modesetting: vendor="X.Org Foundation"
> [73.598]compiled for 1.19.2, module version = 1.19.2
> [73.598]Module class: X.Org Video Driver
> [73.598]ABI class: X.Org Video Driver, version 23.0
> [73.598] (II) LoadModule: "fbdev"
> [73.598] (II) Loading /usr/lib/xorg/modules/drivers/fbdev_drv.so
> [73.598] (II) Module fbdev: vendor="X.Org Foundation"
> [73.598]compiled for 1.19.0, module version = 0.4.4
> [73.598]Module class: X.Org Video Driver
> [73.598]ABI class: X.Org Video Driver, version 23.0
> [73.598] (II) LoadModule: "vesa"
> [73.598] (II) Loading /usr/lib/xorg/modules/drivers/vesa_drv.so
> [73.599] (II) Module vesa: vendor="X.Org Foundation"
> [73.599]compiled for 1.19.0, module version = 2.3.4
> [73.599]Module class: X.Org Video Driver
> [73.599]ABI class: X.Org Video Driver, version 23.0
> [73.599] (II) modesetting: Driver for Modesetting Kernel Drivers: kms
> [73.599] (II) FBDEV: driver for framebuffer: fbdev
> [73.599] (II) VESA: driver for VESA chipsets: vesa
> [73.637] (II) modeset(0): using drv /dev/dri/card0
> [73.637] (II) modeset(G0): using drv /dev/dri/card1
> 
> In case it helps:
> saruman:~#  grep . /sys/module/i915/parameters/*
> /sys/module/i915/parameters/alpha_support:0
> /sys/module/i915/parameters/disable_display:N
> /sys/module/i915/parameters/disable_power_well:1
> /sys/module/i915/parameters/edp_vswing:0
> /sys/module/i915/parameters/enable_cmd_parser:Y
> /sys/module/i915/parameters/enable_dc:-1
> /sys/module/i915/parameters/enable_dpcd_backlight:N
> /sys/module/i915/parameters/enable_dp_mst:Y
> /sys/module/i915/parameters/enable_execlists:1
> /sys/module/i915/parameters/enable_fbc:1
> /sys/module/i915/parameters/enable_guc_loading:0
> /sys/module/i915/parameters/enable_guc_submission:0
> /sys/module/i915/parameters/enable_gvt:N
> /sys/module/i915/parameters/enable_hangcheck:Y
> /sys/module/i915/parameters/enable_ips:1
> /sys/module/i915/parameters/enable_ppgtt:3
> /sys/module/i915/parameters/enable_psr:0
> /sys/module/i915/parameters/enable_rc6:1
> /sys/module/i915/parameters/error_capture:Y
> /sys/module/i915/parameters/fastboot:N
> /sys/module/i915/parameters/force_reset_modeset_test:N
> /sys/module/i915/parameters/guc_log_level:-1
> /sys/module/i915/parameters/inject_load_failure:0
> /sys/module/i915/parameters/invert_brightness:0
> /sys/module/i915/parameters/load_detect_test:N
> /sys/module/i915/parameters/lvds_channel_mode:0
> /sys/module/i915/parameters/lvds_use_ssc:-1
> /sys/module/i915/parameters/mmio_debug:0
> /sys/module/i915/parameters/modeset:1
> /sys/module/i915/parameters/nuclear_pageflip:N
> /sys/module/i915/parameters/panel_ignore_lid:1
> /sys/module/i915/parameters/prefault_disable:N
> /sys/module/i915/parameters/reset:Y
> /sys/module/i915/parameters/semaphores:0
> /sys/module/i915/parameters/use_mmio_flip:0
> /sys/module/i915/parameters/vbt_sdvo_panel_type:-1
> /sys/module/i915/parameters/verbose_state_checks:Y
> 
> Any idea what to do?
> 
> Thanks,
> Marc
> -- 
> "A mouse is a device used to 

Re: [Intel-gfx] [PATCH 7/8] drm/i915: Add NV12 as supported format for sprite plane

[Srinivas, Vidya]

> -Original Message-
> From: Taylor, Clinton A
> Sent: Friday, July 7, 2017 4:20 AM
> To: Srinivas, Vidya ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 7/8] drm/i915: Add NV12 as supported
> format for sprite plane
> 
> 
> 
> On 06/19/2017 11:10 PM, Vidya Srinivas wrote:
> > From: Chandra Konduru 
> >
> > This patch adds NV12 to list of supported formats for sprite plane.
> >
> > v2: Rebased (me)
> >
> > v3: Review comments by Ville addressed
> > - Removed skl_plane_formats_with_nv12 and added
> > NV12 case in existing skl_plane_formats
> > - Added the 10bpc RGB formats
> >
> > Signed-off-by: Chandra Konduru 
> > Signed-off-by: Nabendu Maiti 
> > Signed-off-by: Vidya Srinivas 
> > ---
> >   drivers/gpu/drm/i915/intel_sprite.c | 3 +++
> >   1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> > b/drivers/gpu/drm/i915/intel_sprite.c
> > index d4665d2..2a388b6f 100644
> > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > @@ -1074,10 +1074,13 @@ int intel_sprite_set_colorkey(struct
> drm_device *dev, void *data,
> > DRM_FORMAT_ARGB,
> > DRM_FORMAT_XBGR,
> > DRM_FORMAT_XRGB,
> > +   DRM_FORMAT_XBGR2101010,
> > +   DRM_FORMAT_ABGR2101010,
> 
> Why are we adding 10 bit RGB formats with the NV12 series patches?
> Trying to set XR30 or AB30 results in error returned even though the modes
> are advertised for the planes.

Thank you. I will address the review comments and re-send the patches after 
rebasing.

Regards
Vidya
> 
> -Clint
> 
> > DRM_FORMAT_YUYV,
> > DRM_FORMAT_YVYU,
> > DRM_FORMAT_UYVY,
> > DRM_FORMAT_VYUY,
> > +   DRM_FORMAT_NV12,
> >   };
> >
> >   struct intel_plane *

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Re: [Intel-gfx] [PATCH 8/8] drm/i915: Add NV12 support to intel_framebuffer_init

[Srinivas, Vidya]

> -Original Message-
> From: Taylor, Clinton A
> Sent: Friday, July 7, 2017 4:26 AM
> To: Srinivas, Vidya ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 8/8] drm/i915: Add NV12 support to
> intel_framebuffer_init
> 
> 
> 
> On 06/19/2017 11:10 PM, Vidya Srinivas wrote:
> > From: Chandra Konduru 
> >
> > This patch adds NV12 as supported format to intel_framebuffer_init and
> > performs various checks.
> >
> > v2:
> > -Fix an issue in checks added (Chandra Konduru)
> >
> > v3: rebased (me)
> >
> > v4: Review comments by Ville addressed
> > Added platform check for NV12 in intel_framebuffer_init
> > Removed offset checks for NV12 case
> >
> > Signed-off-by: Chandra Konduru 
> > Signed-off-by: Nabendu Maiti 
> > Signed-off-by: Vidya Srinivas 
> > ---
> >   drivers/gpu/drm/i915/intel_display.c | 4 
> >   1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 83b20fd..56fd9ae 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -14765,6 +14765,10 @@ static int intel_framebuffer_init(struct
> intel_framebuffer *intel_fb,
> > goto err;
> > }
> > break;
> > +   case DRM_FORMAT_NV12:
> > +   if (INTEL_GEN(dev_priv) >= 9)
> > +   break;
> > +   goto err;
> This NV12 support only correctly works on SKL. Plane color space conversion
> is different on GLK and later platforms causing the colors to display
> incorrectly. Ville's plane color space property patch series in review will 
> fix
> this issue.
> 
Thank you. I will address the review comments and re-send the patches after 
rebasing.
> Tested-by: Clinton Taylor 
> Reviewed-by: Clinton Taylor 
> 
> -Clint
> 
> > default:
> > DRM_DEBUG_KMS("unsupported pixel format: %s\n",
> >   drm_get_format_name(mode_cmd-
> >pixel_format, _name));

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[Intel-gfx] [PATCH 15/15] drm/i915/glk: set HDMI 2.0 identifier

[Shashank Sharma]

This patch sets the is_hdmi2_src identifier in drm connector
for GLK platform. GLK contains a native HDMI 2.0 controller.
This identifier will help the EDID handling functions to save
lot of work which is specific to HDMI 2.0 sources.

V3: Added this patch
V4: Rebase
V4: Rebase
V5: Added r-b from Ander
V6: Rebase

Cc: Ville Syrjala 
Cc: Ander Conselvan de Oliveira 

Reviewed-by: Ander Conselvan de Oliveira 
Signed-off-by: Shashank Sharma 
---
 drivers/gpu/drm/i915/intel_hdmi.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
b/drivers/gpu/drm/i915/intel_hdmi.c
index 2524ac4..d1b1efc 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1922,6 +1922,9 @@ void intel_hdmi_init_connector(struct intel_digital_port 
*intel_dig_port,
connector->doublescan_allowed = 0;
connector->stereo_allowed = 1;
 
+   if (IS_GEMINILAKE(dev_priv))
+   connector->ycbcr_420_allowed = true;
+
intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
 
switch (port) {
-- 
2.7.4

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[Intel-gfx] [PATCH 12/15] drm/i915: prepare pipe for YCBCR420 output

[Shashank Sharma]

To get HDMI YCBCR420 output, the PIPEMISC register should be
programmed to:
- Generate YCBCR output (bit 11)
- In case of YCBCR420 outputs, it should be programmed in full
  blend mode to use the scaler in 5x3 ratio (bits 26 and 27)

This patch:
- Adds definition of these bits.
- Programs PIPEMISC for YCBCR420 outputs.

V2: rebase
V3: rebase
V4: rebase
V5: added r-b from Ander
V6: Handle only YCBCR420 outputs (ville)

Cc: Ville Syrjala 
Cc: Ander Conselvan de Oliveira 
Cc: Daniel Vetter 

Reviewed-by: Ander Conselvan de Oliveira 
Signed-off-by: Shashank Sharma 
---
 drivers/gpu/drm/i915/i915_reg.h  | 3 +++
 drivers/gpu/drm/i915/intel_display.c | 7 +++
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 64cc674..5aea2a9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5227,6 +5227,9 @@ enum {
 
 #define _PIPE_MISC_A   0x70030
 #define _PIPE_MISC_B   0x71030
+#define   PIPEMISC_YCBCR420_ENABLE (1<<27)
+#define   PIPEMISC_YCBCR420_MODE_BLEND (1<<26)
+#define   PIPEMISC_OUTPUT_YCBCR(1<<11)
 #define   PIPEMISC_DITHER_BPC_MASK (7<<5)
 #define   PIPEMISC_DITHER_8_BPC(0<<5)
 #define   PIPEMISC_DITHER_10_BPC   (1<<5)
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index c56081e..b4a6415 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8081,6 +8081,7 @@ static void haswell_set_pipemisc(struct drm_crtc *crtc)
 {
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+   struct intel_crtc_state *config = intel_crtc->config;
 
if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
u32 val = 0;
@@ -8106,6 +8107,12 @@ static void haswell_set_pipemisc(struct drm_crtc *crtc)
if (intel_crtc->config->dither)
val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
 
+   if (config->ycbcr420) {
+   val |= PIPEMISC_OUTPUT_YCBCR |
+   PIPEMISC_YCBCR420_ENABLE |
+   PIPEMISC_YCBCR420_MODE_BLEND;
+   }
+
I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
}
 }
-- 
2.7.4

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[Intel-gfx] [PATCH 14/15] drm/i915: set colorspace for YCBCR420 outputs

[Shashank Sharma]

When output colorspace is YCBCR420, we have to load the
corresponding colorspace in AVI infoframe. This patch fills
the colorspace of AVI infoframe as per the output mode.

V2: Rebase
V3: Rebase
V4: Rebase
V5: Added r-b from Ander
V6: Checking RGB/YCBCR420 output only (Ville)

Cc: Ville Syrjala 
Cc: Ander Conselvan de Oliveira 

Reviewed-by: Ander Conselvan de Oliveira 
Signed-off-by: Shashank Sharma 
---
 drivers/gpu/drm/i915/intel_hdmi.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
b/drivers/gpu/drm/i915/intel_hdmi.c
index 9e8d784..2524ac4 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -461,6 +461,7 @@ static void intel_hdmi_set_avi_infoframe(struct drm_encoder 
*encoder,
_state->base.adjusted_mode;
struct drm_connector *connector = _hdmi->attached_connector->base;
bool is_hdmi2_sink = connector->display_info.hdmi.scdc.supported;
+   enum hdmi_colorspace colorspace = HDMI_COLORSPACE_RGB;
union hdmi_infoframe frame;
int ret;
 
@@ -472,6 +473,17 @@ static void intel_hdmi_set_avi_infoframe(struct 
drm_encoder *encoder,
return;
}
 
+   if (crtc_state->ycbcr420)
+   colorspace = HDMI_COLORSPACE_YUV420;
+
+   ret = drm_hdmi_avi_infoframe_set_colorspace(,
+   adjusted_mode,
+   colorspace);
+   if (ret < 0) {
+   DRM_ERROR("couldn't fill AVI colorspace\n");
+   return;
+   }
+
drm_hdmi_avi_infoframe_quant_range(, adjusted_mode,
   crtc_state->limited_color_range ?
   HDMI_QUANTIZATION_RANGE_LIMITED :
-- 
2.7.4

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[Intel-gfx] [PATCH 13/15] drm/i915: prepare csc unit for YCBCR420 output

[Shashank Sharma]

To support ycbcr output, we need a pipe CSC block to do
RGB->YCBCR conversion.

Current Intel platforms have only one pipe CSC unit, so
we can either do color correction using it, or we can perform
RGB->YCBCR conversion.

This function adds a csc handler, which uses recommended bspec
values to perform RGB->YCBCR conversion (target color space BT709)

V2: Rebase
V3: Rebase
V4: Rebase
V5: Addressed review comments from Ander
- Remove extra line added in the patch
- Add the spec details in the commit message
- Combine two if(cond) while calling intel_crtc_compute_config
V6: Handle YCBCR420 outputs only (Ville)

Cc: Ville Syrjala 
Cc: Daniel Vetter 
Cc: Ander Conselvan de Oliveira 

Signed-off-by: Shashank Sharma 
---
 drivers/gpu/drm/i915/intel_color.c   | 47 +++-
 drivers/gpu/drm/i915/intel_display.c | 17 +
 2 files changed, 63 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_color.c 
b/drivers/gpu/drm/i915/intel_color.c
index 306c6b0..8a5d211 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -41,6 +41,19 @@
 
 #define LEGACY_LUT_LENGTH  (sizeof(struct drm_color_lut) * 256)
 
+/* Post offset values for RGB->YCBCR conversion */
+#define POSTOFF_RGB_TO_YUV_HI 0x800
+#define POSTOFF_RGB_TO_YUV_ME 0x100
+#define POSTOFF_RGB_TO_YUV_LO 0x800
+
+/* Direct spec values for RGB->YUV conversion matrix */
+#define CSC_RGB_TO_YUV_RU_GU 0x2ba809d8
+#define CSC_RGB_TO_YUV_BU 0x37e8
+#define CSC_RGB_TO_YUV_RY_GY 0x1e089cc0
+#define CSC_RGB_TO_YUV_BY 0xb528
+#define CSC_RGB_TO_YUV_RV_GV 0xbce89ad8
+#define CSC_RGB_TO_YUV_BV 0x1e08
+
 /*
  * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
  * format). This macro takes the coefficient we want transformed and the
@@ -91,6 +104,35 @@ static void ctm_mult_by_limited(uint64_t *result, int64_t 
*input)
}
 }
 
+void i9xx_load_ycbcr_conversion_matrix(struct intel_crtc *intel_crtc)
+{
+   int pipe = intel_crtc->pipe;
+   struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
+
+   /* We don't use high values for conversion */
+   I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
+   I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
+   I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
+
+   /* Program direct spec values for RGB to YCBCR conversion matrix */
+   I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), CSC_RGB_TO_YUV_RU_GU);
+   I915_WRITE(PIPE_CSC_COEFF_BU(pipe), CSC_RGB_TO_YUV_BU);
+
+   I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), CSC_RGB_TO_YUV_RY_GY);
+   I915_WRITE(PIPE_CSC_COEFF_BY(pipe), CSC_RGB_TO_YUV_BY);
+
+   I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), CSC_RGB_TO_YUV_RV_GV);
+   I915_WRITE(PIPE_CSC_COEFF_BV(pipe), CSC_RGB_TO_YUV_BV);
+
+   /* Spec postoffset values */
+   I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), POSTOFF_RGB_TO_YUV_HI);
+   I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), POSTOFF_RGB_TO_YUV_ME);
+   I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), POSTOFF_RGB_TO_YUV_LO);
+
+   /* CSC mode before gamma */
+   I915_WRITE(PIPE_CSC_MODE(pipe), 0);
+}
+
 /* Set up the pipe CSC unit. */
 static void i9xx_load_csc_matrix(struct drm_crtc_state *crtc_state)
 {
@@ -101,7 +143,10 @@ static void i9xx_load_csc_matrix(struct drm_crtc_state 
*crtc_state)
uint16_t coeffs[9] = { 0, };
struct intel_crtc_state *intel_crtc_state = 
to_intel_crtc_state(crtc_state);
 
-   if (crtc_state->ctm) {
+   if (intel_crtc_state->ycbcr420) {
+   i9xx_load_ycbcr_conversion_matrix(intel_crtc);
+   return;
+   } else if (crtc_state->ctm) {
struct drm_color_ctm *ctm =
(struct drm_color_ctm *)crtc_state->ctm->data;
uint64_t input[9] = { 0, };
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index b4a6415..c5ff568 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6288,6 +6288,23 @@ static int intel_crtc_compute_config(struct intel_crtc 
*crtc,
return -EINVAL;
}
 
+   /* YCBCR420 feasibility check */
+   if (pipe_config->ycbcr420) {
+   struct drm_crtc_state *drm_state = _config->base;
+
+   /*
+* There is only one pipe CSC unit per pipe, and we need that
+* for output conversion from RGB->YCBCR. So if CTM is already
+* applied we can't support YCBCR420 output.
+*/
+   if (drm_state->ctm) {
+   DRM_ERROR("YCBCR420 and CTM is not possible\n");
+   return -EINVAL;
+   }
+
+   DRM_DEBUG_KMS("YCBCR420 output is possible from CRTC\n");
+   }
+
/*
 * Pipe horizontal size must be even in:
 * 

[Intel-gfx] [PATCH 08/15] drm: set output colorspace in AVI infoframe

[Shashank Sharma]

A source must set output colorspace information in AVI
infoframes, so that the sink can decode upcoming frames
accordingly.

This patch adds a function to add the output colorspace
information in the AVI infoframes.

V2: Rebase
V3: Rebase
V4: Rebase
V5: Rebase
V6: Made patch independent of HDMI output type.

Cc: Ville Syrjala 
Cc: Jose Abreu 
Signed-off-by: Shashank Sharma 
---
 drivers/gpu/drm/drm_edid.c | 29 +
 include/drm/drm_edid.h |  5 +
 2 files changed, 34 insertions(+)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 944a28f..cede86e 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -4796,6 +4796,35 @@ drm_hdmi_avi_infoframe_from_display_mode(struct 
hdmi_avi_infoframe *frame,
 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
 
 /**
+ * drm_hdmi_avi_infoframe_set_colorspace - fill an HDMI AVI infoframe with
+ * colorspace data of the output type
+ *
+ * @frame: HDMI AVI infoframe
+ * @mode: DRM display mode
+ * @hdmi_output: HDMI output colorspace
+ *
+ * Return: 0 on success or a negative error code on failure.
+ */
+int
+drm_hdmi_avi_infoframe_set_colorspace(struct hdmi_avi_infoframe *frame,
+ const struct drm_display_mode *mode,
+ enum hdmi_colorspace colorspace)
+{
+   if (colorspace > HDMI_COLORSPACE_YUV420 ||
+   colorspace < HDMI_COLORSPACE_RGB) {
+   DRM_ERROR("Invalid color space type\n");
+   return -EINVAL;
+   }
+
+   frame->colorspace = colorspace;
+   if (colorspace == HDMI_COLORSPACE_YUV420)
+   frame->pixel_repeat = 0;
+
+   return 0;
+}
+EXPORT_SYMBOL(drm_hdmi_avi_infoframe_set_colorspace);
+
+/**
  * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
  *quantization range information
  * @frame: HDMI AVI infoframe
diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
index aa58146..b79e0cb 100644
--- a/include/drm/drm_edid.h
+++ b/include/drm/drm_edid.h
@@ -332,6 +332,7 @@ struct cea_sad {
 struct drm_encoder;
 struct drm_connector;
 struct drm_display_mode;
+enum drm_hdmi_output_type;
 
 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid);
 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads);
@@ -354,6 +355,10 @@ drm_hdmi_avi_infoframe_from_display_mode(struct 
hdmi_avi_infoframe *frame,
 const struct drm_display_mode *mode,
 bool is_hdmi2_sink);
 int
+drm_hdmi_avi_infoframe_set_colorspace(struct hdmi_avi_infoframe *frame,
+const struct drm_display_mode *mode,
+enum hdmi_colorspace colorspace);
+int
 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe 
*frame,
const struct drm_display_mode 
*mode);
 void
-- 
2.7.4

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[Intel-gfx] [PATCH 10/15] drm/i915: add config function for YCBCR420 outputs

[Shashank Sharma]

This patch checks encoder level support for YCBCR420 outputs.
The logic goes as simple as this:
If the input mode is YCBCR420-only mode: prepare HDMI for
YCBCR420 output, else continue with RGB output mode.

It checks if the mode is YCBCR420 and source can support this
output then it marks the ycbcr_420 output indicator into crtc
state, for further staging in driver.

V2: Split the patch into two, kept helper functions in DRM layer.
V3: Changed the compute_config function based on new DRM API.
V4: Rebase
V5: Rebase
V6: Check and handle YCBCR420-only modes, discard the property
based approach (Ville)

Cc: Ville Syrjala 
Cc: Daniel Vetter 
Cc: Ander Conselvan de Oliveira 

Signed-off-by: Shashank Sharma 
---
 drivers/gpu/drm/i915/intel_display.c |  1 +
 drivers/gpu/drm/i915/intel_drv.h |  3 +++
 drivers/gpu/drm/i915/intel_hdmi.c| 42 +---
 3 files changed, 43 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 4e03ca6..01900e1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11930,6 +11930,7 @@ intel_pipe_config_compare(struct drm_i915_private 
*dev_priv,
PIPE_CONF_CHECK_I(hdmi_scrambling);
PIPE_CONF_CHECK_I(hdmi_high_tmds_clock_ratio);
PIPE_CONF_CHECK_I(has_infoframe);
+   PIPE_CONF_CHECK_I(ycbcr420);
 
PIPE_CONF_CHECK_I(has_audio);
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d17a324..592243b 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -780,6 +780,9 @@ struct intel_crtc_state {
 
/* HDMI High TMDS char rate ratio */
bool hdmi_high_tmds_clock_ratio;
+
+   /* HDMI output type */
+   bool ycbcr420;
 };
 
 struct intel_crtc {
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
b/drivers/gpu/drm/i915/intel_hdmi.c
index cc0d100..276d916 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1305,7 +1305,8 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
return status;
 }
 
-static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
+static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state,
+   bool output_ycbcr420)
 {
struct drm_i915_private *dev_priv =
to_i915(crtc_state->base.crtc->dev);
@@ -1330,6 +1331,13 @@ static bool hdmi_12bpc_possible(struct intel_crtc_state 
*crtc_state)
if (connector_state->crtc != crtc_state->base.crtc)
continue;
 
+   if (output_ycbcr420) {
+   const struct drm_hdmi_info *hdmi = >hdmi;
+
+   if (!(hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36))
+   return false;
+   }
+
if ((info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_36) == 0)
return false;
}
@@ -1342,6 +1350,25 @@ static bool hdmi_12bpc_possible(struct intel_crtc_state 
*crtc_state)
return true;
 }
 
+static bool
+intel_hdmi_ycbcr420_config(struct drm_connector *connector,
+  struct intel_crtc_state *config,
+  int *clock_12bpc, int *clock_8bpc)
+{
+
+   if (!connector->ycbcr_420_allowed) {
+   DRM_ERROR("Platform doesn't support YCBCR420 output\n");
+   return false;
+   }
+
+   /* YCBCR420 TMDS rate requirement is half the pixel clock */
+   config->port_clock /= 2;
+   *clock_12bpc /= 2;
+   *clock_8bpc /= 2;
+   config->ycbcr420 = true;
+   return true;
+}
+
 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
   struct intel_crtc_state *pipe_config,
   struct drm_connector_state *conn_state)
@@ -1349,7 +1376,8 @@ bool intel_hdmi_compute_config(struct intel_encoder 
*encoder,
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(>base);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct drm_display_mode *adjusted_mode = 
_config->base.adjusted_mode;
-   struct drm_scdc *scdc = _state->connector->display_info.hdmi.scdc;
+   struct drm_connector *connector = conn_state->connector;
+   struct drm_scdc *scdc = >display_info.hdmi.scdc;
struct intel_digital_connector_state *intel_conn_state =
to_intel_digital_connector_state(conn_state);
int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
@@ -1379,6 +1407,14 @@ bool intel_hdmi_compute_config(struct intel_encoder 
*encoder,
clock_12bpc *= 2;
}
 
+   if (drm_mode_is_420_only(>display_info, adjusted_mode)) {
+   if (!intel_hdmi_ycbcr420_config(connector, 

[Intel-gfx] [PATCH 11/15] drm/i915: prepare scaler for YCBCR420 modeset

[Shashank Sharma]

To get a YCBCR420 output from intel platforms, we need one
scaler to scale down YCBCR444 samples to YCBCR420 samples.

This patch:
- Does scaler allocation for HDMI ycbcr420 outputs.
- Programs PIPE_MISC register for ycbcr420 output.
- Adds a new scaler user "HDMI output" to plug-into existing
  scaler framework. This output type is identified using bit
  30 of the scaler users bitmap.

V2: rebase
V3: rebase
V4: rebase
V5: addressed review comments from Ander:
- No need to check both scaler_user && hdmi_output.
  Check for scaler_user is enough.

Cc: Ville Syrjala 
Cc: Ander Conselvan De Oliveira 

Signed-off-by: Shashank Sharma 
---
 drivers/gpu/drm/i915/intel_atomic.c  |  6 ++
 drivers/gpu/drm/i915/intel_display.c | 23 +++
 drivers/gpu/drm/i915/intel_drv.h | 10 +-
 drivers/gpu/drm/i915/intel_hdmi.c| 12 
 drivers/gpu/drm/i915/intel_panel.c   |  3 ++-
 5 files changed, 52 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_atomic.c 
b/drivers/gpu/drm/i915/intel_atomic.c
index 36d4e63..040d111 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -264,6 +264,12 @@ int intel_atomic_setup_scalers(struct drm_i915_private 
*dev_priv,
 
/* panel fitter case: assign as a crtc scaler */
scaler_id = _state->scaler_id;
+   } else if (i == SKL_420_OUTPUT_INDEX) {
+   name = "YCBCR420-OUTPUT";
+   idx = intel_crtc->base.base.id;
+
+   /* YCBCR420 case: needs a pipe scaler */
+   scaler_id = _state->scaler_id;
} else {
name = "PLANE";
 
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 01900e1..c56081e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4621,6 +4621,9 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, 
bool force_detach,
 */
need_scaling = src_w != dst_w || src_h != dst_h;
 
+   if (scaler_user == SKL_420_OUTPUT_INDEX)
+   need_scaling = true;
+
/*
 * if plane is being disabled or scaler is no more required or force 
detach
 *  - free scaler binded to this plane/crtc
@@ -4668,6 +4671,26 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, 
bool force_detach,
 }
 
 /**
+ * skl_update_scaler_crtc_420_output - Stages update to scaler state
+ * for YCBCR420 which needs a scaler, for downsampling.
+ *
+ * @state: crtc's scaler state
+ *
+ * Return
+ * 0 - scaler_usage updated successfully
+ *error - requested scaling cannot be supported or other error condition
+ */
+int skl_update_scaler_crtc_420_output(struct intel_crtc_state *state)
+{
+   const struct drm_display_mode *mode = >base.adjusted_mode;
+
+   return skl_update_scaler(state, !state->base.active,
+   SKL_420_OUTPUT_INDEX, >scaler_state.scaler_id,
+   state->pipe_src_w, state->pipe_src_h,
+   mode->crtc_hdisplay, mode->crtc_vdisplay);
+}
+
+/**
  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
  *
  * @state: crtc's scaler state
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 592243b..68b4fba 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -471,7 +471,8 @@ struct intel_crtc_scaler_state {
 *
 * If a bit is set, a user is using a scaler.
 * Here user can be a plane or crtc as defined below:
-*   bits 0-30 - plane (bit position is index from drm_plane_index)
+*   bits 0-29 - plane (bit position is index from drm_plane_index)
+*   bit 30- hdmi output
 *   bit 31- crtc
 *
 * Instead of creating a new index to cover planes and crtc, using
@@ -484,6 +485,12 @@ struct intel_crtc_scaler_state {
 * avilability.
 */
 #define SKL_CRTC_INDEX 31
+
+   /*
+* YCBCR 420 output consume a scaler. So adding a user
+* for 420 output requirement.
+*/
+#define SKL_420_OUTPUT_INDEX 30
unsigned scaler_users;
 
/* scaler used by crtc for panel fitting purpose */
@@ -1483,6 +1490,7 @@ void intel_mode_from_pipe_config(struct drm_display_mode 
*mode,
 struct intel_crtc_state *pipe_config);
 
 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
+int skl_update_scaler_crtc_420_output(struct intel_crtc_state *state);
 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state 
*crtc_state);
 
 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state 
*state)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
b/drivers/gpu/drm/i915/intel_hdmi.c
index 276d916..9e8d784 

[Intel-gfx] [PATCH 07/15] drm/edid: parse ycbcr 420 deep color information

[Shashank Sharma]

CEA-861-F spec adds ycbcr420 deep color support information
in hf-vsdb block. This patch extends the existing hf-vsdb parsing
function by adding parsing of ycbcr420 deep color support from the
EDID and adding it into display information stored.

V2: Rebase
V3: Rebase
V4: Moved definition of y420_dc_modes into this patch, where its used
(Ville)
V5: Optimize function, if(conditions) not reqd (Ville)
V6: Rebase

Cc: Ville Syrjälä 
Cc: Jose Abreu 
Signed-off-by: Shashank Sharma 
---
 drivers/gpu/drm/drm_edid.c  | 12 
 include/drm/drm_connector.h |  3 +++
 include/drm/drm_edid.h  |  8 
 3 files changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 44be128..944a28f 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -4199,6 +4199,16 @@ drm_default_rgb_quant_range(const struct 
drm_display_mode *mode)
 }
 EXPORT_SYMBOL(drm_default_rgb_quant_range);
 
+static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
+const u8 *db)
+{
+   u8 dc_mask;
+   struct drm_hdmi_info *hdmi = >display_info.hdmi;
+
+   dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
+   hdmi->y420_dc_modes |= dc_mask;
+}
+
 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
 const u8 *hf_vsdb)
 {
@@ -4239,6 +4249,8 @@ static void drm_parse_hdmi_forum_vsdb(struct 
drm_connector *connector,
scdc->scrambling.low_rates = true;
}
}
+
+   drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
 }
 
 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 225e092..4bc0882 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -154,6 +154,9 @@ struct drm_hdmi_info {
 
/** @y420_cmdb_map: bitmap of SVD index, to extraxt vcb modes */
u64 y420_cmdb_map;
+
+   /** @y420_dc_modes: bitmap of deep color support index */
+   u8 y420_dc_modes;
 };
 
 /**
diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
index b55b2a7..aa58146 100644
--- a/include/drm/drm_edid.h
+++ b/include/drm/drm_edid.h
@@ -213,6 +213,14 @@ struct detailed_timing {
 #define DRM_EDID_HDMI_DC_30   (1 << 4)
 #define DRM_EDID_HDMI_DC_Y444 (1 << 3)
 
+/* YCBCR 420 deep color modes */
+#define DRM_EDID_YCBCR420_DC_48  (1 << 6)
+#define DRM_EDID_YCBCR420_DC_36  (1 << 5)
+#define DRM_EDID_YCBCR420_DC_30  (1 << 4)
+#define DRM_EDID_YCBCR420_DC_MASK (DRM_EDID_YCBCR420_DC_48 | \
+   DRM_EDID_YCBCR420_DC_36 | \
+   DRM_EDID_YCBCR420_DC_30)
+
 /* ELD Header Block */
 #define DRM_ELD_HEADER_BLOCK_SIZE  4
 
-- 
2.7.4

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[Intel-gfx] [PATCH 04/15] drm/edid: cleanup patch for CEA extended-tag macro

[Shashank Sharma]

CEA-861-F introduces extended tag codes for EDID extension blocks,
which indicates the actual type of the data block. The code for
using exteded tag is 0x7, whereas in the existing code, the
corresponding macro is named as "VIDEO_CAPABILITY_BLOCK"

This patch renames the macro and usages from "VIDEO_CAPABILITY_BLOCK"
to "USE_EXTENDED_TAG"

V2: Add extended tag code check for video capabilitiy block (ville)
V3: Ville:
- Use suggested names for macros
- Check the block length first, before checking the extended tag
V4: Fix commit message (David)
V5: Introduced this patch into HDMI-YCBCR-output series
V6: Rebase

Cc: Ville Syrjala 
Signed-off-by: Shashank Sharma 
---
 drivers/gpu/drm/drm_edid.c | 15 ---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 274356d..9a07f42 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -2781,7 +2781,8 @@ add_detailed_modes(struct drm_connector *connector, 
struct edid *edid,
 #define VIDEO_BLOCK 0x02
 #define VENDOR_BLOCK0x03
 #define SPEAKER_BLOCK  0x04
-#define VIDEO_CAPABILITY_BLOCK 0x07
+#define USE_EXTENDED_TAG 0x07
+#define EXT_VIDEO_CAPABILITY_BLOCK 0x00
 #define EDID_BASIC_AUDIO   (1 << 6)
 #define EDID_CEA_YCRCB444  (1 << 5)
 #define EDID_CEA_YCRCB422  (1 << 4)
@@ -3443,6 +3444,12 @@ cea_db_payload_len(const u8 *db)
 }
 
 static int
+cea_db_extended_tag(const u8 *db)
+{
+   return db[1];
+}
+
+static int
 cea_db_tag(const u8 *db)
 {
return db[0] >> 5;
@@ -4018,8 +4025,10 @@ bool drm_rgb_quant_range_selectable(struct edid *edid)
return false;
 
for_each_cea_db(edid_ext, i, start, end) {
-   if (cea_db_tag(_ext[i]) == VIDEO_CAPABILITY_BLOCK &&
-   cea_db_payload_len(_ext[i]) == 2) {
+   if (cea_db_tag(_ext[i]) == USE_EXTENDED_TAG &&
+   cea_db_payload_len(_ext[i]) == 2 &&
+   cea_db_extended_tag(_ext[i]) ==
+   EXT_VIDEO_CAPABILITY_BLOCK) {
DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]);
return edid_ext[i + 2] & EDID_CEA_VCDB_QS;
}
-- 
2.7.4

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[Intel-gfx] [PATCH 09/15] drm: add helper functions for YCBCR420 handling

[Shashank Sharma]

This patch adds helper functions for YCBCR 420 handling.
These functions do:
- check if a given video mode is YCBCR 420 only mode.
- check if a given video mode is YCBCR 420 also mode.

V2: Added YCBCR functions as helpers in DRM layer, instead of
keeping it in I915 layer.
V3: Added handling for YCBCR-420 only modes too.
V4: EXPORT_SYMBOL(drm_find_hdmi_output_type)
V5: Addressed review comments from Danvet:
- %s/drm_find_hdmi_output_type/drm_display_info_hdmi_output_type
- %s/drm_can_support_ycbcr_output/drm_display_supports_ycbcr_output
- %s/drm_can_support_this_ycbcr_output/
drm_display_supports_this_ycbcr_output
- pass drm_display_info instead of drm_connector for consistency
- For drm_get_highest_quality_ycbcr_supported doc, move the variable
  description above, and then the function description.
V6: Add only YCBCR420 helpers (Ville)

Cc: Ville Syrjala 
Cc: Jose Abreu 
Cc: Daniel Vetter 
Signed-off-by: Shashank Sharma 
---
 drivers/gpu/drm/drm_modes.c | 74 +
 include/drm/drm_modes.h |  6 
 2 files changed, 80 insertions(+)

diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index 3b53c8e3..61c82a38 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -1604,3 +1604,77 @@ int drm_mode_convert_umode(struct drm_display_mode *out,
 out:
return ret;
 }
+
+/**
+ * drm_mode_is_420_only - if a given videomode can be only supported in 
YCBCR420
+ * output format
+ *
+ * @connector: drm connector under action.
+ * @mode: video mode to be tested.
+ *
+ * Returns:
+ * true if the mode can be supported in YCBCR420 format
+ * false if not.
+ */
+bool drm_mode_is_420_only(struct drm_display_info *display,
+   struct drm_display_mode *mode)
+{
+   u8 vic = drm_match_cea_mode(mode);
+
+   /*
+* Requirements of a 420_only mode:
+* must be a valid cea mode
+* entry in 420_only bitmap
+*/
+   if (!drm_valid_cea_vic(vic))
+   return false;
+
+   return test_bit(vic, display->hdmi.y420_vdb_modes);
+}
+EXPORT_SYMBOL(drm_mode_is_420_only);
+
+/**
+ * drm_mode_is_420_also - if a given videomode can be supported in YCBCR420
+ * output format also (along with RGB/YCBCR444/422)
+ *
+ * @display: display under action.
+ * @mode: video mode to be tested.
+ *
+ * Returns:
+ * true if the mode can be support YCBCR420 format
+ * false if not.
+ */
+bool drm_mode_is_420_also(struct drm_display_info *display,
+   struct drm_display_mode *mode)
+{
+   u8 vic = drm_match_cea_mode(mode);
+
+   /*
+* Requirements of a 420_also mode:
+* must be a valid cea mode
+* entry in 420_also bitmap
+*/
+   if (!drm_valid_cea_vic(vic))
+   return false;
+
+   return test_bit(vic, display->hdmi.y420_cmdb_modes);
+}
+EXPORT_SYMBOL(drm_mode_is_420_also);
+/**
+ * drm_mode_is_420 - if a given videomode can be supported in YCBCR420
+ * output format
+ *
+ * @display: display under action.
+ * @mode: video mode to be tested.
+ *
+ * Returns:
+ * true if the mode can be supported in YCBCR420 format
+ * false if not.
+ */
+bool drm_mode_is_420(struct drm_display_info *display,
+   struct drm_display_mode *mode)
+{
+   return drm_mode_is_420_only(display, mode) ||
+   drm_mode_is_420_also(display, mode);
+}
+EXPORT_SYMBOL(drm_mode_is_420);
diff --git a/include/drm/drm_modes.h b/include/drm/drm_modes.h
index f8a1268..980db27 100644
--- a/include/drm/drm_modes.h
+++ b/include/drm/drm_modes.h
@@ -452,6 +452,12 @@ int drm_mode_convert_umode(struct drm_display_mode *out,
   const struct drm_mode_modeinfo *in);
 void drm_mode_probed_add(struct drm_connector *connector, struct 
drm_display_mode *mode);
 void drm_mode_debug_printmodeline(const struct drm_display_mode *mode);
+bool drm_mode_is_420_only(struct drm_display_info *display,
+   struct drm_display_mode *mode);
+bool drm_mode_is_420_also(struct drm_display_info *display,
+   struct drm_display_mode *mode);
+bool drm_mode_is_420(struct drm_display_info *display,
+   struct drm_display_mode *mode);
 
 struct drm_display_mode *drm_cvt_mode(struct drm_device *dev,
  int hdisplay, int vdisplay, int vrefresh,
-- 
2.7.4

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[Intel-gfx] [PATCH 02/15] drm/edid: complete CEA modedb(VIC 1-107)

[Shashank Sharma]

CEA-861-F specs defines new video modes to be used with
HDMI 2.0 EDIDs. The VIC range has been extended from 1-64 to
1-107.

Our existing CEA modedb contains only 64 modes (VIC=1 to VIC=64). Now
to be able to parse new CEA modes using the existing methods, we have
to complete the modedb (VIC=65 onwards).

This patch adds:
- Timings for existing CEA video modes (from VIC=65 till VIC=92)
- Newly added 4k modes (from VIC=93 to VIC=107).

The patch was originaly discussed and reviewed here:
https://patchwork.freedesktop.org/patch/135810/

Cc: Ville Syrjala 
Cc: Jose Abreu 
Cc: Andrzej Hajda 
Cc: Alex Deucher 
Cc: Harry Wentland 

V2: Rebase
V3: Rebase
V4: Added native bit handling as per CEA-861-F spec (Ville)
V5: Fix timings for VIC 77:1920x1080 and 104:3840x2160p (Ville)
Remove unnecessary paranthesis from function svd_to_vic (Ville)
Added r-b (Neil)

Reviewed-by: Jose Abreu 
Reviewed-by: Alex Deucher 
Reviewed-by: Neil Armstrong 
Acked-by: Harry Wentland 
Signed-off-by: Shashank Sharma 
---
 drivers/gpu/drm/drm_edid.c | 227 -
 1 file changed, 226 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 0667b07..b879662 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1006,6 +1006,221 @@ static const struct drm_display_mode edid_cea_modes[] = 
{
   2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
+   /* 65 - 1280x720@24Hz */
+   { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
+  3080, 3300, 0, 720, 725, 730, 750, 0,
+  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
+   /* 66 - 1280x720@25Hz */
+   { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
+  3740, 3960, 0, 720, 725, 730, 750, 0,
+  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
+   /* 67 - 1280x720@30Hz */
+   { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
+  3080, 3300, 0, 720, 725, 730, 750, 0,
+  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
+   /* 68 - 1280x720@50Hz */
+   { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
+  1760, 1980, 0, 720, 725, 730, 750, 0,
+  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
+   /* 69 - 1280x720@60Hz */
+   { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
+  1430, 1650, 0, 720, 725, 730, 750, 0,
+  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
+   /* 70 - 1280x720@100Hz */
+   { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
+  1760, 1980, 0, 720, 725, 730, 750, 0,
+  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
+   /* 71 - 1280x720@120Hz */
+   { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
+  1430, 1650, 0, 720, 725, 730, 750, 0,
+  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
+   /* 72 - 1920x1080@24Hz */
+   { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
+  2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
+  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
+   /* 73 - 1920x1080@25Hz */
+   { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
+  2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
+  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
+   /* 74 - 1920x1080@30Hz */
+   { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
+  2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
+  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
+   /* 75 - 1920x1080@50Hz */
+   { 

[Intel-gfx] [PATCH 06/15] drm: add helper to validate YCBCR420 modes

[Shashank Sharma]

YCBCR420 modes are supported only on HDMI 2.0 capable sources.
This patch adds:
- A drm helper to validate YCBCR420-only mode on a particular
  connector. This function will help pruning the YCBCR420-only
  modes from the connector's modelist.
- A bool variable (ycbcr_420_allowed) in the drm connector structure.
  While handling the EDID from HDMI 2.0 sinks, its important to know
  if the source is capable of handling YCBCR420 output, so that no
  YCBCR 420 modes will be listed for sources which can't handle it.
  A driver should set this variable if it wants to see YCBCR420 modes
  in the modedb.

V5: Introduced the patch in series.
V5-resend: Squashed two patches (validate YCBCR420 and add YCBCR420
   identifier)

Cc: Ville Syrjala 
Signed-off-by: Shashank Sharma 
---
 drivers/gpu/drm/drm_edid.c |  3 ++-
 drivers/gpu/drm/drm_modes.c| 28 
 drivers/gpu/drm/drm_probe_helper.c |  4 
 include/drm/drm_connector.h|  9 +
 include/drm/drm_edid.h |  1 +
 include/drm/drm_modes.h|  5 +
 6 files changed, 49 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 10dab62..44be128 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -2950,10 +2950,11 @@ u8 drm_match_cea_mode(const struct drm_display_mode 
*to_match)
 }
 EXPORT_SYMBOL(drm_match_cea_mode);
 
-static bool drm_valid_cea_vic(u8 vic)
+bool drm_valid_cea_vic(u8 vic)
 {
return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes);
 }
+EXPORT_SYMBOL(drm_valid_cea_vic);
 
 /**
  * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index f2493b9..3b53c8e3 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -1083,6 +1083,34 @@ drm_mode_validate_size(const struct drm_display_mode 
*mode,
 }
 EXPORT_SYMBOL(drm_mode_validate_size);
 
+/**
+ * drm_mode_ycbcr420_only - add 'ycbcr420-only' modes only when allowed
+ * @mode: mode to check
+ * @connector: drm connector under action
+ *
+ * This function is a helper which can be used to filter out any YCBCR420
+ * only mode, when the source doesn't support it.
+ *
+ * Returns:
+ * The mode status
+ */
+enum drm_mode_status
+drm_mode_validate_ycbcr420(const struct drm_display_mode *mode,
+  struct drm_connector *connector)
+{
+   u8 vic = drm_match_cea_mode(mode);
+   enum drm_mode_status status = MODE_OK;
+   struct drm_hdmi_info *hdmi = >display_info.hdmi;
+
+   if (drm_valid_cea_vic(vic) && test_bit(vic, hdmi->y420_vdb_modes)) {
+   if (!connector->ycbcr_420_allowed)
+   status = MODE_NO_420;
+   }
+
+   return status;
+}
+EXPORT_SYMBOL(drm_mode_validate_ycbcr420);
+
 #define MODE_STATUS(status) [MODE_ ## status + 3] = #status
 
 static const char * const drm_mode_status_names[] = {
diff --git a/drivers/gpu/drm/drm_probe_helper.c 
b/drivers/gpu/drm/drm_probe_helper.c
index 00e6832..904966c 100644
--- a/drivers/gpu/drm/drm_probe_helper.c
+++ b/drivers/gpu/drm/drm_probe_helper.c
@@ -528,6 +528,10 @@ int drm_helper_probe_single_connector_modes(struct 
drm_connector *connector,
if (mode->status == MODE_OK)
mode->status = drm_mode_validate_pipeline(mode,
  connector);
+
+   if (mode->status == MODE_OK)
+   mode->status = drm_mode_validate_ycbcr420(mode,
+ connector);
}
 
 prune:
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index b3af8e3..225e092 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -746,6 +746,15 @@ struct drm_connector {
bool interlace_allowed;
bool doublescan_allowed;
bool stereo_allowed;
+
+   /**
+* @ycbcr_420_allowed : This bool indicates if this connector is
+* capable of handling YCBCR 420 output. While parsing the EDID
+* blocks, its very helpful to know, if the source is capable of
+* handling YCBCR 420 outputs.
+*/
+   bool ycbcr_420_allowed;
+
/**
 * @registered: Is this connector exposed (registered) with userspace?
 * Protected by @mutex.
diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
index 89c0062..b55b2a7 100644
--- a/include/drm/drm_edid.h
+++ b/include/drm/drm_edid.h
@@ -477,4 +477,5 @@ void drm_edid_get_monitor_name(struct edid *edid, char 
*name,
 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
   int hsize, int vsize, int fresh,
   bool rb);
+bool drm_valid_cea_vic(u8 vic);
 #endif /* __DRM_EDID_H__ */
diff 

[Intel-gfx] [PATCH 03/15] drm/edid: parse sink information before CEA blocks

[Shashank Sharma]

CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
This block contains a map of indexes of CEA modes, which can
support YCBCR 420 output also. To avoid multiple parsing of same
CEA block, let's parse the sink information and get this map, before
parsing CEA modes.

This patch moves the call to drm_add_display_info function, before the
mode parsing block.

V4: Introduced new patch in the series
V5: Move this patch before 4:2:0 parsing patch (ville)
Added r-b from Ville

Reviewed-by: Ville Syrjälä 
Signed-off-by: Shashank Sharma 
---
 drivers/gpu/drm/drm_edid.c | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index b879662..274356d 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -4440,6 +4440,13 @@ int drm_add_edid_modes(struct drm_connector *connector, 
struct edid *edid)
quirks = edid_get_quirks(edid);
 
/*
+* CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
+* To avoid multiple parsing of same block, lets parse that map
+* from sink info, before parsing CEA modes.
+*/
+   drm_add_display_info(connector, edid);
+
+   /*
 * EDID spec says modes should be preferred in this order:
 * - preferred detailed mode
 * - other detailed modes from base block
@@ -4466,8 +4473,6 @@ int drm_add_edid_modes(struct drm_connector *connector, 
struct edid *edid)
if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
edid_fixup_preferred(connector, quirks);
 
-   drm_add_display_info(connector, edid);
-
if (quirks & EDID_QUIRK_FORCE_6BPC)
connector->display_info.bpc = 6;
 
-- 
2.7.4

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[Intel-gfx] [PATCH 05/15] drm/edid: parse YCBCR420 videomodes from EDID

[Shashank Sharma]

HDMI 2.0 spec adds support for YCBCR420 sub-sampled output.
CEA-861-F adds two new blocks in EDID's CEA extension blocks,
to provide information about sink's YCBCR420 output capabilities.

These blocks are:

- YCBCR420vdb(YCBCR 420 video data block):
This block contains VICs of video modes, which can be sopported only
in YCBCR420 output mode (Not in RGB/YCBCR444/422. Its like a normal
SVD block, valid for YCBCR420 modes only.

- YCBCR420cmdb(YCBCR 420 capability map data block):
This block gives information about video modes which can support
YCBCR420 output mode also (along with RGB,YCBCR444/422 etc) This
block contains a bitmap index of normal svd videomodes, which can
support YCBCR420 output too.
So if bit 0 from first vcb byte is set, first video mode in the svd
list can support YCBCR420 output too. Bit 1 means second video mode
from svd list can support YCBCR420 output too, and so on.

This patch adds two bitmaps in display's hdmi_info structure, one each
for VCB and VDB modes. If the source is HDMI 2.0 capable, this patch
adds:
- VDB modes (YCBCR 420 only modes) in connector's mode list, also makes
  an entry in the vdb_bitmap per vic.
- VCB modes (YCBCR 420 also modes) only entry in the vcb_bitmap.

Cc: Ville Syrjala 
Cc: Jose Abreu 
Cc: Emil Velikov 

V2: Addressed
Review comments from Emil:
- Use 1ULL< 64 modes in capability map block.
- Use y420cmdb in function names and macros while dealing with vcb
  to be aligned with spec.
- Move the display information parsing block ahead of mode parsing
  blocks.

V3: Addressed design/review comments from Ville
- Do not add flags in video modes, else we have to expose them to user
- There should not be a UABI change, and kernel should detect the
  choice of the output based on type of mode, and the bitmaps.
- Use standard bitops from kernel bitmap header, instead of calculating
  bit positions manually.

V4: Addressed review comments from Ville:
- s/ycbcr_420_vdb/y420vdb
- s/ycbcr_420_vcb/y420cmdb
- Be less verbose on description of do_y420vdb_modes
- Move newmode variable in the loop scope.
- Use svd_to_vic() to get a VIC, instead of 0x7f
- Remove bitmap description for CMDB modes & VDB modes
- Dont add connector->ycbcr_420_allowed check for cmdb modes
- Remove 'len' variable, in is_y420cmdb function, which is used
  only once
- Add length check in is_y420vdb function
- Remove unnecessary if (!db) check in function parse_y420cmdb_bitmap
- Do not add print about YCBCR 420 modes
- Fix indentation in few places
- Move ycbcr420_dc_modes in next patch, where its used
- Add a separate patch for movement of drm_add_display_info()

V5: Addressed review comments from Ville:
- Add the patch which cleans up the current EXTENDED_TAG usage
- Make y420_cmdb_map u64
- Do not block ycbcr420 modes while parsing the EDID, rather
  add a separate helper function to prune ycbcr420-only modes from
  connector's probed modes.

V6: Rebase

Signed-off-by: Shashank Sharma 
---
 drivers/gpu/drm/drm_edid.c  | 148 +++-
 include/drm/drm_connector.h |  20 ++
 2 files changed, 166 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 9a07f42..10dab62 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -2783,6 +2783,8 @@ add_detailed_modes(struct drm_connector *connector, 
struct edid *edid,
 #define SPEAKER_BLOCK  0x04
 #define USE_EXTENDED_TAG 0x07
 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00
+#define EXT_VIDEO_DATA_BLOCK_420   0x0E
+#define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
 #define EDID_BASIC_AUDIO   (1 << 6)
 #define EDID_CEA_YCRCB444  (1 << 5)
 #define EDID_CEA_YCRCB422  (1 << 4)
@@ -3154,15 +3156,79 @@ drm_display_mode_from_vic_index(struct drm_connector 
*connector,
return newmode;
 }
 
+/*
+ * do_y420vdb_modes - Parse YCBCR 420 only modes
+ * @connector: connector corresponding to the HDMI sink
+ * @svds: start of the data block of CEA YCBCR 420 VDB
+ * @len: length of the CEA YCBCR 420 VDB
+ *
+ * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
+ * which contains modes which can be supported in YCBCR 420
+ * output format only.
+ */
+static int do_y420vdb_modes(struct drm_connector *connector,
+  const u8 *svds, u8 svds_len)
+{
+   int modes = 0, i;
+   struct drm_device *dev = connector->dev;
+   struct drm_display_info *info = >display_info;
+   struct drm_hdmi_info *hdmi = >hdmi;
+
+   for (i = 0; i < svds_len; i++) {
+   u8 vic = svd_to_vic(svds[i]);
+   struct drm_display_mode *newmode;
+
+   newmode = drm_mode_duplicate(dev, _cea_modes[vic]);
+   if (!newmode)
+   break;
+  

[Intel-gfx] [PATCH 00/15] YCBCR 4:2:0 handling in DRM layer

[Shashank Sharma]

Following YCBCR 4:4:4 and 4:2:2, YCBCR 4:2:0 is a new output format,
which is currently supported on HDMI 2.0 sources/sinks. Due to lower
chroma sub-sampling rate, YCBCR 4:2:0 can drive the video modes at half
the pixel clock than YCBCR 4:4:4 or RGB 8:8:8 outputs. For example, a CEA
4K@60, RGB 8:8:8 mode needs a clock of appx 594Mhz, but it can be driven at
297Mhz using YCBCR 4:2:0 output.

Of course, the lower rate of chroma subsampling, causes the quality of YCBCR
4:2:0 to be lower than YCBCR 4:4:4 or RGB 8:8:8.

This patch series adds support for YCBCR 4:2:0 output in DRM layer.

- First 2 patches, complete the CEA mode-db in drm driver, by adding
  new 4k modes. Current CEA mode-db contains 64 modes only (VIC 1-64),
  whereas CEA-861-F defined VICs up to 107, including 4k modes, from VIC
  range 93-107. First patch makes sure that inclusion of these modes doesn't
  break existing HDMI 1.4 monitors, across various drivers.

- Next 5 patches focus on parsing new YCBCR 4:2:0 EDID blocks, and adding
  YCBCR 4:2:0 modes in connector. They also contain a prune function, which
  will cleanup the YCBCR 4:2:0 modes from list, if the connector doesn't
  declare them supported.

- Next 2 patches add helper functions for identifing YCBCR 4:2:0 modes and
  setup the color space in AVI infoframes.

- Next 6 patches add code for I915 layer handling of YCBCR 4:2:0 output.

This patch series was initially published as a complete framework to handle
all YCBCR outputs (4:4:4, 4:2:2, 4:2:0), but based on the code reviews, now
its been published as YCBCR 4:2:0 handling series only.

The previous discussion and reviews can be found here:
V5: https://patchwork.freedesktop.org/series/26815/
V1-V4: https://patchwork.freedesktop.org/series/22683/

Now re-publishing this patch series as YCBCR 4:2:0 handling series here.
This series has been tested with drm-tip code with following setup:
Source: Intel Geminilake device.
Sink: ACER S277HK HDMI 2.0 monitor.
Protocol testing: Astro VA-1844A HDMI analyzer.

Shashank Sharma (15):
  drm: handle HDMI 2.0 VICs in AVI info-frames
  drm/edid: complete CEA modedb(VIC 1-107)
  drm/edid: parse sink information before CEA blocks
  drm/edid: cleanup patch for CEA extended-tag macro
  drm/edid: parse YCBCR420 videomodes from EDID
  drm: add helper to validate YCBCR420 modes
  drm/edid: parse ycbcr 420 deep color information
  drm: set output colorspace in AVI infoframe
  drm: add helper functions for YCBCR420 handling
  drm/i915: add config function for YCBCR420 outputs
  drm/i915: prepare scaler for YCBCR420 modeset
  drm/i915: prepare pipe for YCBCR420 output
  drm/i915: prepare csc unit for YCBCR420 output
  drm/i915: set colorspace for YCBCR420 outputs
  drm/i915/glk: set HDMI 2.0 identifier

 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c|   2 +-
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c|   2 +-
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c |   2 +-
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c |   2 +-
 drivers/gpu/drm/bridge/analogix-anx78xx.c |   3 +-
 drivers/gpu/drm/bridge/sii902x.c  |   2 +-
 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c |   2 +-
 drivers/gpu/drm/drm_edid.c| 469 +-
 drivers/gpu/drm/drm_modes.c   | 102 +++
 drivers/gpu/drm/drm_probe_helper.c|   4 +
 drivers/gpu/drm/exynos/exynos_hdmi.c  |   2 +-
 drivers/gpu/drm/i2c/tda998x_drv.c |   2 +-
 drivers/gpu/drm/i915/i915_reg.h   |   3 +
 drivers/gpu/drm/i915/intel_atomic.c   |   6 +
 drivers/gpu/drm/i915/intel_color.c|  47 ++-
 drivers/gpu/drm/i915/intel_display.c  |  48 +++
 drivers/gpu/drm/i915/intel_drv.h  |  13 +-
 drivers/gpu/drm/i915/intel_hdmi.c |  74 -
 drivers/gpu/drm/i915/intel_panel.c|   3 +-
 drivers/gpu/drm/i915/intel_sdvo.c |   3 +-
 drivers/gpu/drm/mediatek/mtk_hdmi.c   |   2 +-
 drivers/gpu/drm/msm/hdmi/hdmi_bridge.c|   2 +-
 drivers/gpu/drm/nouveau/nv50_display.c|   3 +-
 drivers/gpu/drm/omapdrm/omap_encoder.c|   3 +-
 drivers/gpu/drm/radeon/radeon_audio.c |   2 +-
 drivers/gpu/drm/rockchip/inno_hdmi.c  |   2 +-
 drivers/gpu/drm/sti/sti_hdmi.c|   2 +-
 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c|   2 +-
 drivers/gpu/drm/tegra/hdmi.c  |   2 +-
 drivers/gpu/drm/tegra/sor.c   |   2 +-
 drivers/gpu/drm/vc4/vc4_hdmi.c|   2 +-
 drivers/gpu/drm/zte/zx_hdmi.c |   2 +-
 include/drm/drm_connector.h   |  32 ++
 include/drm/drm_edid.h|  17 +-
 include/drm/drm_modes.h   |  11 +
 35 files changed, 837 insertions(+), 40 deletions(-)

-- 
2.7.4

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[Intel-gfx] [PATCH 01/15] drm: handle HDMI 2.0 VICs in AVI info-frames

[Shashank Sharma]

HDMI 1.4b support the CEA video modes as per range of CEA-861-D (VIC 1-64).
For any other mode, the VIC filed in AVI infoframes should be 0.
HDMI 2.0 sinks, support video modes range as per CEA-861-F spec, which is
extended to (VIC 1-107).

This patch adds a bool input variable, which indicates if the connected
sink is a HDMI 2.0 sink or not. This will make sure that we don't pass a
HDMI 2.0 VIC to a HDMI 1.4 sink.

This patch touches all drm drivers, who are callers of this function
drm_hdmi_avi_infoframe_from_display_mode but to make sure there is
no change in current behavior, is_hdmi2 is kept as false.

In case of I915 driver, this patch:
- checks if the connected display is HDMI 2.0.
- HDMI infoframes carry one of this two type of information:
- VIC for 4K modes for HDMI 1.4 sinks
- S3D information for S3D modes
  As CEA-861-F has already defined VICs for 4K videomodes, this
  patch doesn't allow sending HDMI infoframes for HDMI 2.0 sinks,
  until the mode is 3D.

Cc: Ville Syrjala 
Cc: Jose Abreu 
Cc: Andrzej Hajda 
Cc: Alex Deucher 
Cc: Daniel Vetter 

PS: This patch touches a few lines in few files, which were
already above 80 char, so checkpatch gives 80 char warning again.
- gpu/drm/omapdrm/omap_encoder.c
- gpu/drm/i915/intel_sdvo.c

V2: Rebase, Added r-b from Andrzej
V3: Addressed review comment from Ville:
- Do not send VICs in both AVI-IF and HDMI-IF
  send only one of it.
V4: Rebase
V5: Added r-b from Neil.
Addressed review comments from Ville
- Do not block HDMI vendor IF, instead check for VIC while
  handling AVI infoframes
V6: Rebase

Reviewed-by: Andrzej Hajda 
Reviewed-by: Neil Armstrong 
Signed-off-by: Shashank Sharma 
---
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c|  2 +-
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c|  2 +-
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c |  2 +-
 drivers/gpu/drm/bridge/analogix-anx78xx.c |  3 ++-
 drivers/gpu/drm/bridge/sii902x.c  |  2 +-
 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c |  2 +-
 drivers/gpu/drm/drm_edid.c| 26 +-
 drivers/gpu/drm/exynos/exynos_hdmi.c  |  2 +-
 drivers/gpu/drm/i2c/tda998x_drv.c |  2 +-
 drivers/gpu/drm/i915/intel_hdmi.c |  5 -
 drivers/gpu/drm/i915/intel_sdvo.c |  3 ++-
 drivers/gpu/drm/mediatek/mtk_hdmi.c   |  2 +-
 drivers/gpu/drm/msm/hdmi/hdmi_bridge.c|  2 +-
 drivers/gpu/drm/nouveau/nv50_display.c|  3 ++-
 drivers/gpu/drm/omapdrm/omap_encoder.c|  3 ++-
 drivers/gpu/drm/radeon/radeon_audio.c |  2 +-
 drivers/gpu/drm/rockchip/inno_hdmi.c  |  2 +-
 drivers/gpu/drm/sti/sti_hdmi.c|  2 +-
 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c|  2 +-
 drivers/gpu/drm/tegra/hdmi.c  |  2 +-
 drivers/gpu/drm/tegra/sor.c   |  2 +-
 drivers/gpu/drm/vc4/vc4_hdmi.c|  2 +-
 drivers/gpu/drm/zte/zx_hdmi.c |  2 +-
 include/drm/drm_edid.h|  3 ++-
 25 files changed, 57 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 9f78c03..aff1f48 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -1867,7 +1867,7 @@ static void dce_v10_0_afmt_setmode(struct drm_encoder 
*encoder,
dce_v10_0_audio_write_sad_regs(encoder);
dce_v10_0_audio_write_latency_fields(encoder, mode);
 
-   err = drm_hdmi_avi_infoframe_from_display_mode(, mode);
+   err = drm_hdmi_avi_infoframe_from_display_mode(, mode, false);
if (err < 0) {
DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
return;
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 4bcf01d..2df650d 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -1851,7 +1851,7 @@ static void dce_v11_0_afmt_setmode(struct drm_encoder 
*encoder,
dce_v11_0_audio_write_sad_regs(encoder);
dce_v11_0_audio_write_latency_fields(encoder, mode);
 
-   err = drm_hdmi_avi_infoframe_from_display_mode(, mode);
+   err = drm_hdmi_avi_infoframe_from_display_mode(, mode, false);
if (err < 0) {
DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
return;
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index fd134a4..0c3891f 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -1597,7 +1597,7 @@ static void dce_v6_0_audio_set_avi_infoframe(struct 
drm_encoder *encoder,
ssize_t err;
u32 tmp;
 
-   err = 

Re: [Intel-gfx] [PATCH] drm/i915/cnl: Gen10 render context size.

[Ben Widawsky]

On 17-07-06 14:06:24, Vivi, Rodrigo wrote:

No change on render context size is required for Gen10.

So this patch doesn't change the default behaviour,
but only avoid the missing_case message.

Cc: Ben Widawsky 
Signed-off-by: Rodrigo Vivi 


Reviewed-by: Ben Widawsky 

[snip]


--
Ben Widawsky, Intel Open Source Technology Center
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Re: [Intel-gfx] [PATCH i-g-t v2 2/2] tests/gem_reset_stats: Enforce full chip reset mode before run

[Michel Thierry]

On 06/07/17 15:50, Antonio Argenziano wrote:

+
+igt_fixture {
+int fd;
+
+fd = drm_open_driver(DRIVER_INTEL);
+igt_assert(igt_sysfs_set_parameter
+   (fd, "reset", "%d", INT_MAX /* any reset method */));


I would still suggest that we restore the reset value we had at the 
beginning of the test. I think that since we disabled single engine, 
this would actually set the parameter to an unsafe value.


I talked with Antonio offline about it, but long story short, it doesn't 
matter much.


Writing INT_MAX to i915.reset is safe; a platform without reset-engine 
support will still only do (and most important, report via the get-param 
ioctl) that it can only do full-gpu-reset, even though i915.reset > 1.


-Michel
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Re: [Intel-gfx] [PATCH i-g-t 0/5] igt/kms: Make fence waiting explicit.

[Gustavo Padovan]

Hi Maarten,

2017-07-06 Maarten Lankhorst :

> I wanted to make kms_atomic_transition pass, but the nonblocking modeset
> fencing tests were bogus.
> 
> This series changes the semantics for fencing slightly. It only keeps the out 
> fences
> in pipe_obj->out_fence_fd, it's up to the test to decide what to do with it, 
> which
> is probably just waiting on the fd or checking if it completed.
> 
> Maarten Lankhorst (5):
>   tests/kms_atomic_transition: Add test for plane completion ordering.
>   lib/kms: Handle fence interaction correctly WRT TEST_ONLY.
>   tests/kms_atomic_transition: Only request fence on enabled pipes
>   tests/kms_atomic_transition: Do not clear in-fences after atomic
> commit.
>   igt/kms: Do not wait for fence completion during commit
> 
>  lib/igt_kms.c | 41 --
>  tests/kms_atomic_transition.c | 99 
> +--
>  2 files changed, 95 insertions(+), 45 deletions(-)

This make fencing a lot cleaner.

For the whole series:

Acked-by: Gustavo Padovan 

Gustavo

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[Intel-gfx] [PATCH 0/3] MOCS versioning

[Ben Widawsky]

Copying the kernel commit message:

Starting with GEN9, Memory Object Control State (MOCS) becomes an index
into a table as opposed to the direct programming within the command.
The table has 62 usable entries (ie 6 bits can represent all settings),
and each buffer type may use one of these 62 entries to describe
cacheability type, and age (and some other less useful fields).

Because we hadn't dealt with MOCS settings like this, we didn't think
ahead too well and have ended up with a mess for GEN9 (and soon GEN10)
platform. The plan for for future platforms is that the ideal MOCS
settings will be determined, defined, and written in the public PRMs.
After this point, the i915.ko will absorb these settings and sometime
afterwards flip the alpha switch. All driver releases without the final
MOCS table must be considered alpha. Here on, userspace can assume the
MOCS table is definitively done. There will be some reserved entries for
'oh shit' scenarios. This avoids versioning the MOCS table which leaves
somewhat of a mess in userspace trying to handle arbitrarily many MOCS
versions.

But we do have a mess on GEN9. In the beginning, the MOCS table entries
were pre-populated by the hardware based on estimations made prior to
tapeout and we could just use that. Subsequently much performance tuning
was done to determine optimal settings that the i915 driver should load
on top of the hardware defaults. That was posted last as v6 of the
original per-engine MOCS settings:
https://patchwork.freedesktop.org/patch/53237/. Since the MOCS table is
not context saved/restored, it isn't feasible to let userspace upload
its own MOCS table. After a good amount of debate, it was decided that
we'd utilize only the minimal set of entires in mesa anyway, and so we
took only those entries for our MOCS entries.

Now we've come to the realization that indeed there are other MOCS
entries which are more optimal for various buffer types and workloads.
The problem is that the meaning of the indices is ABI (we assume index 0
is the uncached entry, and that there are only 3 entries total).

What this patch [simply] aims to do is expose a parameter to inform
userspace which "version" of the table was loaded by i915. Upon
sufficient data, new entries can be added, and the version can be
bumped. For example, from my original mesa mocs branch:

commit c9b0481bce24af032386701de0266eb5bc24e988
Author: Ben Widawsky 
Date:   Fri Apr 8 10:21:16 2016 -0700

i965: Use PTE mocs

Signed-off-by: Ben Widawsky 

diff --git a/src/mesa/drivers/dri/i965/brw_mocs.c 
b/src/mesa/drivers/dri/i965/brw_mocs.c
index 5df154eb86..b7bfdab671 100644
--- a/src/mesa/drivers/dri/i965/brw_mocs.c
+++ b/src/mesa/drivers/dri/i965/brw_mocs.c
@@ -14,6 +14,9 @@
 /* Skylake: MOCS is now an index into an array of 62 different caching
  * configurations programmed by the kernel.
  */
+
+/* TC=PTE, LeCC=PTE, LRUM=3, L3CC=WB */
+#define SKL_MOCS_PTE_PTE (3 << 1)
 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
 #define SKL_MOCS_WB  (2 << 1)
 /* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
@@ -26,6 +29,9 @@ brw_mocs_get_control_state(const struct brw_context *brw,
switch (brw->gen) {
default:
case 9:
+  if (brw->intelScreen->mocs_version > 1)
+ return SKL_MOCS_PTE_PTE;
+
   return type == INTEL_MOCS_PTE ? SKL_MOCS_PTE : SKL_MOCS_WB;
case 8:
   return type == INTEL_MOCS_PTE ? BDW_MOCS_PTE : BDW_MOCS_WB;

tl;dr: A versioned MOCS table will allow userspace to be aware of new
and potentially interesting cacheability settings. Next GEN platforms
will not be considered production worthy until the MOCS table is
finalized.

Ben Widawsky (1):
  drm/i915: Version the MOCS settings

 drivers/gpu/drm/i915/i915_drv.c |  3 +++
 drivers/gpu/drm/i915/i915_drv.h |  2 ++
 drivers/gpu/drm/i915/i915_pci.c | 13 +
 include/uapi/drm/i915_drm.h |  8 
 4 files changed, 22 insertions(+), 4 deletions(-)

Ben Widawsky (2):
  intel: Merge latest i915 uapi
  intel: Make driver aware of MOCS table version

 src/intel/drm/i915_drm.h  |  8 
 src/intel/vulkan/anv_device.c | 12 
 src/intel/vulkan/anv_private.h|  2 ++
 src/mesa/drivers/dri/i915/intel_context.c |  7 ++-
 src/mesa/drivers/dri/i965/intel_screen.c  | 14 ++
 src/mesa/drivers/dri/i965/intel_screen.h  |  2 ++
 6 files changed, 44 insertions(+), 1 deletion(-)

-- 
2.13.2
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[Intel-gfx] [PATCH 1/1] drm/i915: Version the MOCS settings

[Ben Widawsky]

From: Ben Widawsky 

Starting with GEN9, Memory Object Control State (MOCS) becomes an index
into a table as opposed to the direct programming within the command.
The table has 62 usable entries (ie 6 bits can represent all settings),
and each buffer type may use one of these 62 entries to describe
cacheability type, and age (and some other less useful fields).

Because we hadn't dealt with MOCS settings like this, we didn't think
ahead too well and have ended up with a mess for GEN9 (and soon GEN10)
platform. The plan for for future platforms is that the ideal MOCS
settings will be determined, defined, and written in the public PRMs.
After this point, the i915.ko will absorb these settings and sometime
afterwards flip the alpha switch. All driver releases without the final
MOCS table must be considered alpha. Here on, userspace can assume the
MOCS table is definitively done. There will be some reserved entries for
'oh shit' scenarios. This avoids versioning the MOCS table which leaves
somewhat of a mess in userspace trying to handle arbitrarily many MOCS
versions.

But we do have a mess on GEN9. In the beginning, the MOCS table entries
were pre-populated by the hardware based on estimations made prior to
tapeout and we could just use that. Subsequently much performance tuning
was done to determine optimal settings that the i915 driver should load
on top of the hardware defaults. That was posted last as v6 of the
original per-engine MOCS settings:
https://patchwork.freedesktop.org/patch/53237/. Since the MOCS table is
not context saved/restored, it isn't feasible to let userspace upload
its own MOCS table. After a good amount of debate, it was decided that
we'd utilize only the minimal set of entires in mesa anyway, and so we
took only those entries for our MOCS entries.

Now we've come to the realization that indeed there are other MOCS
entries which are more optimal for various buffer types and workloads.
The problem is that the meaning of the indices is ABI (we assume index 0
is the uncached entry, and that there are only 3 entries total).

What this patch [simply] aims to do is expose a parameter to inform
userspace which "version" of the table was loaded by i915. Upon
sufficient data, new entries can be added, and the version can be
bumped. For example, from my original mesa mocs branch:

commit c9b0481bce24af032386701de0266eb5bc24e988
Author: Ben Widawsky 
Date:   Fri Apr 8 10:21:16 2016 -0700

i965: Use PTE mocs

Signed-off-by: Ben Widawsky 

diff --git a/src/mesa/drivers/dri/i965/brw_mocs.c 
b/src/mesa/drivers/dri/i965/brw_mocs.c
index 5df154eb86..b7bfdab671 100644
--- a/src/mesa/drivers/dri/i965/brw_mocs.c
+++ b/src/mesa/drivers/dri/i965/brw_mocs.c
@@ -14,6 +14,9 @@
 /* Skylake: MOCS is now an index into an array of 62 different caching
  * configurations programmed by the kernel.
  */
+
+/* TC=PTE, LeCC=PTE, LRUM=3, L3CC=WB */
+#define SKL_MOCS_PTE_PTE (3 << 1)
 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
 #define SKL_MOCS_WB  (2 << 1)
 /* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
@@ -26,6 +29,9 @@ brw_mocs_get_control_state(const struct brw_context *brw,
switch (brw->gen) {
default:
case 9:
+  if (brw->intelScreen->mocs_version > 1)
+ return SKL_MOCS_PTE_PTE;
+
   return type == INTEL_MOCS_PTE ? SKL_MOCS_PTE : SKL_MOCS_WB;
case 8:
   return type == INTEL_MOCS_PTE ? BDW_MOCS_PTE : BDW_MOCS_WB;

tl;dr: A versioned MOCS table will allow userspace to be aware of new
and potentially interesting cacheability settings. Next GEN platforms
will not be considered production worthy until the MOCS table is
finalized.

v2: Update 1.5 year old patch. Add comments. Update commit message.

Signed-off-by: Ben Widawsky 
---
 drivers/gpu/drm/i915/i915_drv.c |  3 +++
 drivers/gpu/drm/i915/i915_drv.h |  2 ++
 drivers/gpu/drm/i915/i915_pci.c | 13 +
 include/uapi/drm/i915_drm.h |  8 
 4 files changed, 22 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9167a73f3c69..26c27b6ae814 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -401,6 +401,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
if (!value)
return -ENODEV;
break;
+   case I915_PARAM_MOCS_TABLE_VERSION:
+   value = INTEL_INFO(dev_priv)->mocs_version;
+   break;
default:
DRM_DEBUG("Unknown parameter %d\n", param->param);
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index effbe4f72a64..9b30f6e6ef9b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -859,6 +859,8 @@ struct intel_device_info {
u16 degamma_lut_size;
u16 

[Intel-gfx] [PATCH 3/3] intel: Make driver aware of MOCS table version

[Ben Widawsky]

We don't yet have optimal MOCS settings, but we have enough to know how
to at least determine when we might have non-optimal settings within our
driver.

Signed-off-by: Ben Widawsky 
---
 src/intel/vulkan/anv_device.c | 12 
 src/intel/vulkan/anv_private.h|  2 ++
 src/mesa/drivers/dri/i915/intel_context.c |  7 ++-
 src/mesa/drivers/dri/i965/intel_screen.c  | 14 ++
 src/mesa/drivers/dri/i965/intel_screen.h  |  2 ++
 5 files changed, 36 insertions(+), 1 deletion(-)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 3dc55dbb8d..8e180dbf18 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -368,6 +368,18 @@ anv_physical_device_init(struct anv_physical_device 
*device,
  device->info.max_cs_threads = max_cs_threads;
}
 
+   if (device->info.gen >= 9) {
+  device->mocs_version = anv_gem_get_param(fd,
+   I915_PARAM_MOCS_TABLE_VERSION);
+  switch (device->mocs_version) {
+  default:
+ anv_perf_warn("Kernel exposes newer MOCS table\n");
+  case 1:
+  case 0:
+ device->mocs_version = MOCS_TABLE_VERSION;
+  }
+   }
+
brw_process_intel_debug_variable();
 
device->compiler = brw_compiler_create(NULL, >info);
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 573778dad5..b8241a9b22 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -684,6 +684,8 @@ struct anv_physical_device {
 uint32_teu_total;
 uint32_tsubslice_total;
 
+uint8_t mocs_version;
+
 struct {
   uint32_t  type_count;
   struct anv_memory_typetypes[VK_MAX_MEMORY_TYPES];
diff --git a/src/mesa/drivers/dri/i915/intel_context.c 
b/src/mesa/drivers/dri/i915/intel_context.c
index e0766a0e3f..9169ea650e 100644
--- a/src/mesa/drivers/dri/i915/intel_context.c
+++ b/src/mesa/drivers/dri/i915/intel_context.c
@@ -521,8 +521,13 @@ intelInitContext(struct intel_context *intel,
INTEL_DEBUG = parse_debug_string(getenv("INTEL_DEBUG"), debug_control);
if (INTEL_DEBUG & DEBUG_BUFMGR)
   dri_bufmgr_set_debug(intel->bufmgr, true);
-   if (INTEL_DEBUG & DEBUG_PERF)
+   if (INTEL_DEBUG & DEBUG_PERF) {
   intel->perf_debug = true;
+  if (screen->mocs_version > MOCS_TABLE_VERSION) {
+ fprintf(stderr, "Kernel exposes newer MOCS table\n");
+ screen->mocs_version = MOCS_TABLE_VERSION;
+  }
+   }
 
if (INTEL_DEBUG & DEBUG_AUB)
   drm_intel_bufmgr_gem_set_aub_dump(intel->bufmgr, true);
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index c75f2125d4..c53f133d49 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -2301,6 +2301,20 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen)
  (ret != -1 || errno != EINVAL);
}
 
+   if (devinfo->gen >= 9) {
+  screen->mocs_version = intel_get_integer(screen,
+   I915_PARAM_MOCS_TABLE_VERSION);
+  switch (screen->mocs_version) {
+  case 1:
+  case 0:
+ screen->mocs_version = MOCS_TABLE_VERSION;
+ break;
+  default:
+ /* We want to perf debug, but we can't yet */
+ break;
+  }
+   }
+
dri_screen->extensions = !screen->has_context_reset_notification
   ? screenExtensions : intelRobustScreenExtensions;
 
diff --git a/src/mesa/drivers/dri/i965/intel_screen.h 
b/src/mesa/drivers/dri/i965/intel_screen.h
index f78b3e8f74..eb801f8155 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.h
+++ b/src/mesa/drivers/dri/i965/intel_screen.h
@@ -112,6 +112,8 @@ struct intel_screen
bool mesa_format_supports_texture[MESA_FORMAT_COUNT];
bool mesa_format_supports_render[MESA_FORMAT_COUNT];
enum isl_format mesa_to_isl_render_format[MESA_FORMAT_COUNT];
+
+   unsigned mocs_version;
 };
 
 extern void intelDestroyContext(__DRIcontext * driContextPriv);
-- 
2.13.2

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[Intel-gfx] [PATCH 2/3] intel: Merge latest i915 uapi

[Ben Widawsky]

Signed-off-by: Ben Widawsky 
---
 src/intel/drm/i915_drm.h | 8 
 1 file changed, 8 insertions(+)

diff --git a/src/intel/drm/i915_drm.h b/src/intel/drm/i915_drm.h
index c26bf7c125..69e38ce89f 100644
--- a/src/intel/drm/i915_drm.h
+++ b/src/intel/drm/i915_drm.h
@@ -431,6 +431,14 @@ typedef struct drm_i915_irq_wait {
  */
 #define I915_PARAM_HAS_EXEC_BATCH_FIRST 48
 
+/* What version of the MOCS table we have. For GEN9 GPUs, the PRM defined
+ * non-optimal settings for the MOCS table. As a result, we were required to 
use a
+ * small subset, and later add new settings. This param allows userspace to
+ * determine which settings are there.
+ */
+#define MOCS_TABLE_VERSION   1 /* Build time MOCS table version */
+#define I915_PARAM_MOCS_TABLE_VERSION   49
+
 typedef struct drm_i915_getparam {
__s32 param;
/*
-- 
2.13.2

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cnl: Gen10 render context size.

[Patchwork]

== Series Details ==

Series: drm/i915/cnl: Gen10 render context size.
URL   : https://patchwork.freedesktop.org/series/26955/
State : success

== Summary ==

Series 26955v1 drm/i915/cnl: Gen10 render context size.
https://patchwork.freedesktop.org/api/1.0/series/26955/revisions/1/mbox/

Test kms_force_connector_basic:
Subgroup force-connector-state:
skip   -> PASS   (fi-ivb-3520m) fdo#101048 +3
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> DMESG-WARN (fi-byt-j1900) fdo#101705 +1

fdo#101048 https://bugs.freedesktop.org/show_bug.cgi?id=101048
fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:443s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:433s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:348s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:534s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:505s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:496s
fi-byt-n2820 total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:496s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:591s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:429s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:415s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:419s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:488s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:473s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:470s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:569s
fi-kbl-r total:279  pass:260  dwarn:1   dfail:0   fail:0   skip:18  
time:591s
fi-pnv-d510  total:279  pass:221  dwarn:3   dfail:0   fail:0   skip:55  
time:563s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:461s
fi-skl-6700hqtotal:279  pass:262  dwarn:0   dfail:0   fail:0   skip:17  
time:592s
fi-skl-6700k total:279  pass:257  dwarn:4   dfail:0   fail:0   skip:18  
time:466s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:473s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:443s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:542s
fi-snb-2600  total:279  pass:250  dwarn:0   dfail:0   fail:0   skip:29  
time:408s

2132c198e6afd4ed75e89eee86c40c7def49c1dc drm-tip: 2017y-07m-06d-20h-24m-04s UTC 
integration manifest
6a788d0 drm/i915/cnl: Gen10 render context size.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_5135/
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Re: [Intel-gfx] [PATCH] drm/i915/cnl: Cannonlake color init.

[Rodrigo Vivi]

merged to dinq. thanks for the review.

On Thu, Jul 6, 2017 at 2:46 PM, Clint Taylor  wrote:
>
> Reviewed-by: Clinton Taylor 
>
> -Clint
>
>
> On 07/06/2017 02:01 PM, Rodrigo Vivi wrote:
>>
>> Cannonlake has same color setup as Geminilake.
>> Legacy color load luts doesn't work anymore on Cannonlake+.
>>
>> Cc: Clint Taylor 
>> Cc: Ander Conselvan de Oliveira 
>> Signed-off-by: Rodrigo Vivi 
>> ---
>>   drivers/gpu/drm/i915/i915_pci.c  | 1 +
>>   drivers/gpu/drm/i915/intel_color.c   | 2 +-
>>   drivers/gpu/drm/i915/intel_display.c | 4 ++--
>>   drivers/gpu/drm/i915/intel_sprite.c  | 2 +-
>>   4 files changed, 5 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_pci.c
>> b/drivers/gpu/drm/i915/i915_pci.c
>> index 04aaf55..a1e6b69 100644
>> --- a/drivers/gpu/drm/i915/i915_pci.c
>> +++ b/drivers/gpu/drm/i915/i915_pci.c
>> @@ -449,6 +449,7 @@
>> .gen = 10,
>> .ddb_size = 1024,
>> .has_csr = 1,
>> +   .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
>>   };
>> /*
>> diff --git a/drivers/gpu/drm/i915/intel_color.c
>> b/drivers/gpu/drm/i915/intel_color.c
>> index 306c6b0..f85d575 100644
>> --- a/drivers/gpu/drm/i915/intel_color.c
>> +++ b/drivers/gpu/drm/i915/intel_color.c
>> @@ -615,7 +615,7 @@ void intel_color_init(struct drm_crtc *crtc)
>>IS_BROXTON(dev_priv)) {
>> dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
>> dev_priv->display.load_luts = broadwell_load_luts;
>> -   } else if (IS_GEMINILAKE(dev_priv)) {
>> +   } else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
>> dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
>> dev_priv->display.load_luts = glk_load_luts;
>> } else {
>> diff --git a/drivers/gpu/drm/i915/intel_display.c
>> b/drivers/gpu/drm/i915/intel_display.c
>> index 0648fd7..2144adc 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -3311,7 +3311,7 @@ u32 skl_plane_ctl(const struct intel_crtc_state
>> *crtc_state,
>> plane_ctl = PLANE_CTL_ENABLE;
>>   - if (!IS_GEMINILAKE(dev_priv)) {
>> +   if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) {
>> plane_ctl |=
>> PLANE_CTL_PIPE_GAMMA_ENABLE |
>> PLANE_CTL_PIPE_CSC_ENABLE |
>> @@ -3367,7 +3367,7 @@ static void skylake_update_primary_plane(struct
>> intel_plane *plane,
>> spin_lock_irqsave(_priv->uncore.lock, irqflags);
>>   - if (IS_GEMINILAKE(dev_priv)) {
>> +   if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
>> I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
>>   PLANE_COLOR_PIPE_GAMMA_ENABLE |
>>   PLANE_COLOR_PIPE_CSC_ENABLE |
>> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
>> b/drivers/gpu/drm/i915/intel_sprite.c
>> index 0c650c2..94f9a13 100644
>> --- a/drivers/gpu/drm/i915/intel_sprite.c
>> +++ b/drivers/gpu/drm/i915/intel_sprite.c
>> @@ -262,7 +262,7 @@ void intel_pipe_update_end(struct intel_crtc *crtc,
>> struct intel_flip_work *work
>> spin_lock_irqsave(_priv->uncore.lock, irqflags);
>>   - if (IS_GEMINILAKE(dev_priv)) {
>> +   if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
>> I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
>>   PLANE_COLOR_PIPE_GAMMA_ENABLE |
>>   PLANE_COLOR_PIPE_CSC_ENABLE |
>
>
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Re: [Intel-gfx] ✓ Fi.CI.BAT: success for x86/gpu: CNL uses the same GMS values as SKL

[Rodrigo Vivi]

Merged to dinq.

On Wed, Jul 5, 2017 at 6:32 PM, Patchwork
 wrote:
> == Series Details ==
>
> Series: x86/gpu: CNL uses the same GMS values as SKL
> URL   : https://patchwork.freedesktop.org/series/26880/
> State : success
>
> == Summary ==
>
> Series 26880v1 x86/gpu: CNL uses the same GMS values as SKL
> https://patchwork.freedesktop.org/api/1.0/series/26880/revisions/1/mbox/
>
> Test gem_exec_flush:
> Subgroup basic-batch-kernel-default-uc:
> fail   -> PASS   (fi-snb-2600) fdo#17
> Test gem_exec_suspend:
> Subgroup basic-s4-devices:
> pass   -> DMESG-WARN (fi-kbl-7560u) fdo#100125
> Test kms_pipe_crc_basic:
> Subgroup suspend-read-crc-pipe-b:
> dmesg-warn -> PASS   (fi-byt-n2820) fdo#101516
>
> fdo#17 https://bugs.freedesktop.org/show_bug.cgi?id=17
> fdo#100125 https://bugs.freedesktop.org/show_bug.cgi?id=100125
> fdo#101516 https://bugs.freedesktop.org/show_bug.cgi?id=101516
>
> fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
> time:445s
> fi-bdw-gvtdvmtotal:279  pass:257  dwarn:8   dfail:0   fail:0   skip:14  
> time:434s
> fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
> time:355s
> fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
> time:528s
> fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
> time:508s
> fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
> time:488s
> fi-byt-n2820 total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
> time:486s
> fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
> time:594s
> fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
> time:434s
> fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
> time:409s
> fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
> time:426s
> fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
> time:474s
> fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
> time:465s
> fi-kbl-7560u total:279  pass:268  dwarn:1   dfail:0   fail:0   skip:10  
> time:580s
> fi-kbl-r total:279  pass:260  dwarn:1   dfail:0   fail:0   skip:18  
> time:584s
> fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
> time:453s
> fi-skl-6700hqtotal:279  pass:262  dwarn:0   dfail:0   fail:0   skip:17  
> time:589s
> fi-skl-6700k total:279  pass:257  dwarn:4   dfail:0   fail:0   skip:18  
> time:465s
> fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
> time:478s
> fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
> time:438s
> fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
> time:539s
> fi-snb-2600  total:279  pass:250  dwarn:0   dfail:0   fail:0   skip:29  
> time:405s
> fi-ivb-3520m failed to collect. IGT log at Patchwork_5121/fi-ivb-3520m/igt.log
>
> cefc82aab8bb8ec201e922cf23d227c47845094c drm-tip: 2017y-07m-05d-20h-21m-17s 
> UTC integration manifest
> 3dbe9f4 x86/gpu: CNL uses the same GMS values as SKL
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_5121/
> ___
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Re: [Intel-gfx] [PATCH] drm/i915/cnl: Add force wake for gen10+.

[Rodrigo Vivi]

Merged to dinq. Thanks for review.

On Wed, Jul 5, 2017 at 6:00 PM, Rodrigo Vivi  wrote:
> By spec there is no change on force wake registers
> for Cannonlake. Let's reuse gen9 one.
>
> v2: Adding missing case for the write part. (Tvrtko)
> v3: Rebase on recent tree.
> v4: Make it for gen9+ instead adding gen10 only. (by Joonas).
>
> Cc: Tvrtko Ursulin 
> Signed-off-by: Rodrigo Vivi 
> Reviewed-by: Joonas Lahtinen 
> ---
>  drivers/gpu/drm/i915/intel_uncore.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
> b/drivers/gpu/drm/i915/intel_uncore.c
> index 1ed3dd8..deb4430 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -643,7 +643,7 @@ static int fw_range_cmp(u32 offset, const struct 
> intel_forcewake_range *entry)
> { .start = (s), .end = (e), .domains = (d) }
>
>  #define HAS_FWTABLE(dev_priv) \
> -   (IS_GEN9(dev_priv) || \
> +   (INTEL_GEN(dev_priv) >= 9 || \
>  IS_CHERRYVIEW(dev_priv) || \
>  IS_VALLEYVIEW(dev_priv))
>
> @@ -1072,7 +1072,7 @@ static void intel_uncore_fw_domains_init(struct 
> drm_i915_private *dev_priv)
> dev_priv->uncore.fw_clear = 
> _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
> }
>
> -   if (IS_GEN9(dev_priv)) {
> +   if (INTEL_GEN(dev_priv) >= 9) {
> dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
> dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
> fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
> --
> 1.9.1
>
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cnl: Enable Audio Pin Buffer.

[Patchwork]

== Series Details ==

Series: drm/i915/cnl: Enable Audio Pin Buffer.
URL   : https://patchwork.freedesktop.org/series/26954/
State : success

== Summary ==

Series 26954v1 drm/i915/cnl: Enable Audio Pin Buffer.
https://patchwork.freedesktop.org/api/1.0/series/26954/revisions/1/mbox/

Test gem_exec_suspend:
Subgroup basic-s4-devices:
pass   -> DMESG-WARN (fi-kbl-7560u) fdo#100125 +1
Test kms_force_connector_basic:
Subgroup force-connector-state:
skip   -> PASS   (fi-ivb-3520m) fdo#101048 +3
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-a:
dmesg-warn -> PASS   (fi-pnv-d510) fdo#101597 +1
Subgroup suspend-read-crc-pipe-b:
pass   -> DMESG-WARN (fi-byt-j1900) fdo#101705

fdo#100125 https://bugs.freedesktop.org/show_bug.cgi?id=100125
fdo#101048 https://bugs.freedesktop.org/show_bug.cgi?id=101048
fdo#101597 https://bugs.freedesktop.org/show_bug.cgi?id=101597
fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:450s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:427s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:352s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:523s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:513s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:489s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:487s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:590s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:437s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:416s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:421s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:489s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:481s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:459s
fi-kbl-7560u total:279  pass:268  dwarn:1   dfail:0   fail:0   skip:10  
time:576s
fi-kbl-r total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:582s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:562s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:456s
fi-skl-6700hqtotal:279  pass:262  dwarn:0   dfail:0   fail:0   skip:17  
time:582s
fi-skl-6700k total:279  pass:257  dwarn:4   dfail:0   fail:0   skip:18  
time:468s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:482s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:437s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:540s
fi-snb-2600  total:279  pass:250  dwarn:0   dfail:0   fail:0   skip:29  
time:404s

2132c198e6afd4ed75e89eee86c40c7def49c1dc drm-tip: 2017y-07m-06d-20h-24m-04s UTC 
integration manifest
35df82f4 drm/i915/cnl: Enable Audio Pin Buffer.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_5134/
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Re: [Intel-gfx] [PATCH 8/8] drm/i915: Add NV12 support to intel_framebuffer_init

[Clint Taylor]

On 06/19/2017 11:10 PM, Vidya Srinivas wrote:

From: Chandra Konduru 

This patch adds NV12 as supported format
to intel_framebuffer_init and performs various checks.

v2:
-Fix an issue in checks added (Chandra Konduru)

v3: rebased (me)

v4: Review comments by Ville addressed
Added platform check for NV12 in intel_framebuffer_init
Removed offset checks for NV12 case

Signed-off-by: Chandra Konduru 
Signed-off-by: Nabendu Maiti 
Signed-off-by: Vidya Srinivas 
---
  drivers/gpu/drm/i915/intel_display.c | 4 
  1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 83b20fd..56fd9ae 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14765,6 +14765,10 @@ static int intel_framebuffer_init(struct 
intel_framebuffer *intel_fb,
goto err;
}
break;
+   case DRM_FORMAT_NV12:
+   if (INTEL_GEN(dev_priv) >= 9)
+   break;
+   goto err;
This NV12 support only correctly works on SKL. Plane color space 
conversion is different on GLK and later platforms causing the colors to 
display incorrectly. Ville's plane color space property patch series in 
review will fix this issue.


Tested-by: Clinton Taylor 
Reviewed-by: Clinton Taylor 

-Clint


default:
DRM_DEBUG_KMS("unsupported pixel format: %s\n",
  drm_get_format_name(mode_cmd->pixel_format, 
_name));


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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cnl: Cannonlake color init.

[Patchwork]

== Series Details ==

Series: drm/i915/cnl: Cannonlake color init.
URL   : https://patchwork.freedesktop.org/series/26953/
State : success

== Summary ==

Series 26953v1 drm/i915/cnl: Cannonlake color init.
https://patchwork.freedesktop.org/api/1.0/series/26953/revisions/1/mbox/

Test gem_exec_flush:
Subgroup basic-batch-kernel-default-uc:
pass   -> FAIL   (fi-snb-2600) fdo#17
Test gem_exec_suspend:
Subgroup basic-s4-devices:
pass   -> DMESG-WARN (fi-kbl-7560u) fdo#100125
Test kms_force_connector_basic:
Subgroup force-connector-state:
skip   -> PASS   (fi-ivb-3520m) fdo#101048 +3
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-a:
dmesg-warn -> PASS   (fi-pnv-d510) fdo#101597
Subgroup suspend-read-crc-pipe-b:
pass   -> DMESG-WARN (fi-byt-j1900) fdo#101705

fdo#17 https://bugs.freedesktop.org/show_bug.cgi?id=17
fdo#100125 https://bugs.freedesktop.org/show_bug.cgi?id=100125
fdo#101048 https://bugs.freedesktop.org/show_bug.cgi?id=101048
fdo#101597 https://bugs.freedesktop.org/show_bug.cgi?id=101597
fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:442s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:427s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:355s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:537s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:510s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:491s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:488s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:595s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:433s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:415s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:423s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:487s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:484s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:462s
fi-kbl-7560u total:279  pass:268  dwarn:1   dfail:0   fail:0   skip:10  
time:572s
fi-kbl-r total:279  pass:260  dwarn:1   dfail:0   fail:0   skip:18  
time:591s
fi-pnv-d510  total:279  pass:222  dwarn:2   dfail:0   fail:0   skip:55  
time:557s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:467s
fi-skl-6700hqtotal:279  pass:262  dwarn:0   dfail:0   fail:0   skip:17  
time:585s
fi-skl-6700k total:279  pass:257  dwarn:4   dfail:0   fail:0   skip:18  
time:472s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:482s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:435s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:540s
fi-snb-2600  total:279  pass:249  dwarn:0   dfail:0   fail:1   skip:29  
time:406s

2132c198e6afd4ed75e89eee86c40c7def49c1dc drm-tip: 2017y-07m-06d-20h-24m-04s UTC 
integration manifest
6a2cc77 drm/i915/cnl: Cannonlake color init.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_5133/
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Re: [Intel-gfx] [PATCH i-g-t v2 2/2] tests/gem_reset_stats: Enforce full chip reset mode before run

[Antonio Argenziano]

On 28/06/17 11:37, Michel Thierry wrote:

Platforms with per-engine reset enabled (i915.reset=2) are unlikely to
perform a full chip reset, keeping the reset_count unmodified. In order
to keep the expectations of this test, enforce that full GPU reset is
enabled (i915.reset=1).

Later on, we can expand the reset_stats ioctl to also return the number
of per-engine resets and use reset_count + reset_engine_count when
checking for the updated reset count.

v2: Rebase, don't use gem_gpu_reset_type directly, since we now have
additional helpers.

Cc: Arkadiusz Hiler 
Signed-off-by: Michel Thierry 
---
  tests/gem_reset_stats.c | 20 
  1 file changed, 20 insertions(+)

diff --git a/tests/gem_reset_stats.c b/tests/gem_reset_stats.c
index 73afeeb2..9ac08aab 100644
--- a/tests/gem_reset_stats.c
+++ b/tests/gem_reset_stats.c
@@ -27,6 +27,8 @@
  
  #define _GNU_SOURCE

  #include "igt.h"
+#include "igt_sysfs.h"
+#include 
  #include 
  #include 
  #include 
@@ -777,15 +779,24 @@ igt_main
int fd;
  
  		bool has_reset_stats;

+   bool using_full_reset;
fd = drm_open_driver(DRIVER_INTEL);
devid = intel_get_drm_devid(fd);
  
  		has_reset_stats = gem_has_reset_stats(fd);
  
+		igt_assert(igt_sysfs_set_parameter

+  (fd, "reset", "%d", 1 /* only global reset */));
+
+   using_full_reset = !gem_engine_reset_enabled(fd) &&
+  gem_gpu_reset_enabled(fd);
+
close(fd);
  
  		igt_require_f(has_reset_stats,

  "No reset stats ioctl support. Too old 
kernel?\n");
+   igt_require_f(using_full_reset,
+ "Full GPU reset is not enabled. Is enable_hangcheck 
set?\n");
}
  
  	igt_subtest("params")

@@ -831,4 +842,13 @@ igt_main
igt_subtest_f("defer-hangcheck-%s", e->name)
RUN_TEST(defer_hangcheck(e));
}
+
+   igt_fixture {
+   int fd;
+
+   fd = drm_open_driver(DRIVER_INTEL);
+   igt_assert(igt_sysfs_set_parameter
+  (fd, "reset", "%d", INT_MAX /* any reset method */));


I would still suggest that we restore the reset value we had at the 
beginning of the test. I think that since we disabled single engine, 
this would actually set the parameter to an unsafe value.


Thanks,
Antonio


+   close(fd);
+   }
  }


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Re: [Intel-gfx] [PATCH 7/8] drm/i915: Add NV12 as supported format for sprite plane

[Clint Taylor]

On 06/19/2017 11:10 PM, Vidya Srinivas wrote:

From: Chandra Konduru 

This patch adds NV12 to list of supported formats for sprite plane.

v2: Rebased (me)

v3: Review comments by Ville addressed
- Removed skl_plane_formats_with_nv12 and added
NV12 case in existing skl_plane_formats
- Added the 10bpc RGB formats

Signed-off-by: Chandra Konduru 
Signed-off-by: Nabendu Maiti 
Signed-off-by: Vidya Srinivas 
---
  drivers/gpu/drm/i915/intel_sprite.c | 3 +++
  1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
b/drivers/gpu/drm/i915/intel_sprite.c
index d4665d2..2a388b6f 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1074,10 +1074,13 @@ int intel_sprite_set_colorkey(struct drm_device *dev, 
void *data,
DRM_FORMAT_ARGB,
DRM_FORMAT_XBGR,
DRM_FORMAT_XRGB,
+   DRM_FORMAT_XBGR2101010,
+   DRM_FORMAT_ABGR2101010,


Why are we adding 10 bit RGB formats with the NV12 series patches? 
Trying to set XR30 or AB30 results in error returned even though the 
modes are advertised for the planes.


-Clint


DRM_FORMAT_YUYV,
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
+   DRM_FORMAT_NV12,
  };
  
  struct intel_plane *


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Re: [Intel-gfx] [PATCH 6/8] drm/i915: Add NV12 as supported format for primary plane

[Clint Taylor]

On 06/19/2017 11:10 PM, Vidya Srinivas wrote:

From: Chandra Konduru 

This patch adds NV12 to list of supported formats for
primary plane

v2: Rebased (Chandra Konduru)

v3: Rebased (me)

v4: Review comments by Ville addressed
Removed the skl_primary_formats_with_nv12 and
added NV12 case in existing skl_primary_formats


Tested-by: Clinton Taylor 
Reviewed-by: Clinton Taylor 

-Clint



Signed-off-by: Chandra Konduru 
Signed-off-by: Nabendu Maiti 
Signed-off-by: Vidya Srinivas 
---
  drivers/gpu/drm/i915/intel_display.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 9de836e..83b20fd 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -85,6 +85,7 @@ static bool is_mmio_work(struct intel_flip_work *work)
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
+   DRM_FORMAT_NV12,
  };
  
  /* Cursor formats */

@@ -13984,7 +13985,6 @@ void intel_plane_destroy(struct drm_plane *plane)
if (INTEL_GEN(dev_priv) >= 9) {
intel_primary_formats = skl_primary_formats;
num_formats = ARRAY_SIZE(skl_primary_formats);
-
primary->update_plane = skylake_update_primary_plane;
primary->disable_plane = skylake_disable_primary_plane;
} else if (INTEL_GEN(dev_priv) >= 4) {


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Re: [Intel-gfx] [PATCH 5/8] drm/i915: Upscale scaler max scale for NV12

[Clint Taylor]

On 06/19/2017 11:10 PM, Vidya Srinivas wrote:

From: Chandra Konduru 

This patch updates scaler max limit support for NV12

v2: Rebased (me)


Needs rebase again.

Tested-by: Clinton Taylor 
Reviewed-by: Clinton Taylor 


Signed-off-by: Chandra Konduru 
Signed-off-by: Nabendu Maiti 
Signed-off-by: Vidya Srinivas 
---
  drivers/gpu/drm/i915/intel_display.c | 28 
  drivers/gpu/drm/i915/intel_drv.h |  3 ++-
  drivers/gpu/drm/i915/intel_sprite.c  |  3 ++-
  3 files changed, 24 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 18559c8..9de836e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3438,6 +3438,8 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
case DRM_FORMAT_VYUY:
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
+   case DRM_FORMAT_NV12:
+   return PLANE_CTL_FORMAT_NV12;
default:
MISSING_CASE(pixel_format);
}
@@ -4801,7 +4803,8 @@ static void cpt_verify_modeset(struct drm_device *dev, 
int pipe)
  static int
  skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
  unsigned int scaler_user, int *scaler_id,
- int src_w, int src_h, int dst_w, int dst_h)
+ int src_w, int src_h, int dst_w, int dst_h,
+ uint32_t pixel_format)
  {
struct intel_crtc_scaler_state *scaler_state =
_state->scaler_state;
@@ -4814,7 +4817,8 @@ static void cpt_verify_modeset(struct drm_device *dev, 
int pipe)
 * the 90/270 degree plane rotation cases (to match the
 * GTT mapping), hence no need to account for rotation here.
 */
-   need_scaling = src_w != dst_w || src_h != dst_h;
+   need_scaling = src_w != dst_w || src_h != dst_h ||
+   (pixel_format == DRM_FORMAT_NV12);
  
  	/*

 * if plane is being disabled or scaler is no more required or force 
detach
@@ -4878,7 +4882,7 @@ int skl_update_scaler_crtc(struct intel_crtc_state *state)
return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
>scaler_state.scaler_id,
state->pipe_src_w, state->pipe_src_h,
-   adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
+   adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay, 0);
  }
  
  /**

@@ -4908,7 +4912,8 @@ static int skl_update_scaler_plane(struct 
intel_crtc_state *crtc_state,
drm_rect_width(_state->base.src) >> 16,
drm_rect_height(_state->base.src) >> 16,
drm_rect_width(_state->base.dst),
-   drm_rect_height(_state->base.dst));
+   drm_rect_height(_state->base.dst),
+   fb ? fb->format->format : 0);
  
  	if (ret || plane_state->scaler_id < 0)

return ret;
@@ -4934,6 +4939,7 @@ static int skl_update_scaler_plane(struct 
intel_crtc_state *crtc_state,
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
+   case DRM_FORMAT_NV12:
break;
default:
DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 
0x%x\n",
@@ -13641,7 +13647,8 @@ static int intel_atomic_commit(struct drm_device *dev,
  }
  
  int

-skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state 
*crtc_state)
+skl_max_scale(struct intel_crtc *intel_crtc,
+   struct intel_crtc_state *crtc_state, uint32_t pixel_format)
  {
struct drm_i915_private *dev_priv;
int max_scale;
@@ -13667,8 +13674,9 @@ static int intel_atomic_commit(struct drm_device *dev,
 *or
 *cdclk/crtc_clock
 */
-   max_scale = min((1 << 16) * 3 - 1,
-   (1 << 8) * ((max_dotclk << 8) / crtc_clock));
+   max_scale = min((1 << 16) *
+   (pixel_format == DRM_FORMAT_NV12 ? 2 : 3) - 1,
+   (1 << 8) * ((max_dotclk << 8) / crtc_clock));
  
  	return max_scale;

  }
@@ -13689,7 +13697,11 @@ static int intel_atomic_commit(struct drm_device *dev,
/* use scaler when colorkey is not required */
if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
min_scale = 1;
-   max_scale = skl_max_scale(to_intel_crtc(crtc), 
crtc_state);
+   max_scale = skl_max_scale(to_intel_crtc(crtc),
+   crtc_state,
+  

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/cnl: Add allowed DP rates for Cannonlake.

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915/cnl: Add allowed DP rates for 
Cannonlake.
URL   : https://patchwork.freedesktop.org/series/26952/
State : success

== Summary ==

Series 26952v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/26952/revisions/1/mbox/

Test gem_exec_suspend:
Subgroup basic-s4-devices:
pass   -> DMESG-WARN (fi-kbl-7560u) fdo#100125
Test kms_force_connector_basic:
Subgroup force-connector-state:
skip   -> PASS   (fi-ivb-3520m) fdo#101048 +3
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-c:
pass   -> FAIL   (fi-skl-6700k) fdo#100367

fdo#100125 https://bugs.freedesktop.org/show_bug.cgi?id=100125
fdo#101048 https://bugs.freedesktop.org/show_bug.cgi?id=101048
fdo#100367 https://bugs.freedesktop.org/show_bug.cgi?id=100367

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:438s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:425s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:355s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:530s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:512s
fi-byt-j1900 total:279  pass:255  dwarn:0   dfail:0   fail:0   skip:24  
time:492s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:481s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:593s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:439s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:413s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:425s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:507s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:478s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:459s
fi-kbl-7560u total:279  pass:268  dwarn:1   dfail:0   fail:0   skip:10  
time:572s
fi-kbl-r total:279  pass:260  dwarn:1   dfail:0   fail:0   skip:18  
time:579s
fi-pnv-d510  total:279  pass:221  dwarn:3   dfail:0   fail:0   skip:55  
time:560s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:454s
fi-skl-6700hqtotal:279  pass:262  dwarn:0   dfail:0   fail:0   skip:17  
time:591s
fi-skl-6700k total:279  pass:256  dwarn:4   dfail:0   fail:1   skip:18  
time:469s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:477s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:436s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:542s
fi-snb-2600  total:279  pass:250  dwarn:0   dfail:0   fail:0   skip:29  
time:404s

2132c198e6afd4ed75e89eee86c40c7def49c1dc drm-tip: 2017y-07m-06d-20h-24m-04s UTC 
integration manifest
7fa9ba8 drm/i915/cnl: Avoid old DDI translation functions on Cannonlake.
c7942ac drm/i915/cnl: Dump the right pll registers when dumping pipe config.
23b05f2 drm/i915/cnl: Add allowed DP rates for Cannonlake.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_5132/
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Re: [Intel-gfx] [PATCH i-g-t v3 1/4] chamelium: Calculate CRC from framebuffer instead of hardcoding it

[Lyude Paul]

On Thu, 2017-07-06 at 16:14 +0300, Paul Kocialkowski wrote:
> On Wed, 2017-07-05 at 16:34 -0400, Lyude Paul wrote:
> > So a couple of notes here that will make it a lot easier for me to
> > review these in the future
> > 
> >  * When you're doing a new revision of a patch series, it's helpful
> > to
> >    keep it in the same email thread as the original v1 so it's
> > easier
> >    to keep track of in people's mail clients (as well as avoiding
> >    accidentally reviewing older patch versions. I usually do
> > something
> >    like this (other projects might request you do this slightly
> >    differently, but this should be fine here):
> > * [PATCH 0/2] Cleaning up the alignment of various foos
> >    * [PATCH 1/2] Foo the bar, not the baz
> >    * [PATCH 2/2] Introduce the amazing new foo_bar
> >    * [PATCH v2 0/2] Cleaning up the alignment of various foos
> >   * [PATCH v2 1/2] Foo the bar, not the baz
> >   * [PATCH v2 2/2] Introduce the amazing new foo_bar
> >    * [PATCH v3 0/2] Cleaning up the alignment of various foos
> >   * [PATCH v3 1/2] Foo the bar, not the baz
> >   * [PATCH v3 2/2] Introduce the amazing new foo_bar
> >  * Try not to group unrelated patches together in the same thread.
> > This
> >    also makes sorting through all of them a little more difficult.
> >  * When you make new revisions of patches, it's very useful if you
> > also
> >    include a list of changes you made to the patch since the last
> >    revision. It doesn't need to be very finely detailed, something
> > like
> >    this would suffice:
> > * Various style fixes
> > * Rename baz to moo, add cow noises
> > * Split init_cow() into init_white_cow() and init_black_cow()
> >   instead of handling both kinds of cows in the same function
> > * Fix documentation
> > For intel-gpu-tools, it's fine to just stick this in the commit
> > message. Other projects may request you put the changelog below
> > the
> > - right above the diff stats (this allows the comments not
> > to
> > get included in the final commit message)
> >  * Unless they are all very small and less important fixes,
> > including
> >    cover letters helps as well since it lets patchwork group
> > together
> >    patch series like this.
> 
> What would you prefer that I do regarding follow-up versions to this
> patchset (and the other one that is still under review)?
Don't worry about that, I went through all the other patches and
reviewed them anyway so there shouldn't be anything left to do :). just
use the guidelines for the future.
> 
> I could split the series per-topic (crc, frame save, time
> improvements)
> and keep those in the same parent thread as their v1.
> 
> > Anyway, back to the actual patch:
> > A good start! Will need a couple of changes though
> > 
> > On Wed, 2017-07-05 at 11:04 +0300, Paul Kocialkowski wrote:
> > > This introduces CRC calculation for reference frames, instead of
> > > using
> > > hardcoded values for them. The rendering of reference frames may
> > > differ
> > > from machine to machine, especially due to font rendering, and
> > > the
> > > frame itself may change with subsequent IGT changes.
> > > 
> > > These differences would cause the CRC checks to fail on different
> > > setups. This allows them to pass regardless of the setup.
> > > 
> > > Signed-off-by: Paul Kocialkowski  > > om>
> > > ---
> > >  lib/igt_chamelium.c | 160
> > > 
> > >  lib/igt_chamelium.h |   5 ++
> > >  tests/chamelium.c   |  76 ++---
> > >  3 files changed, 183 insertions(+), 58 deletions(-)
> > > 
> > > diff --git a/lib/igt_chamelium.c b/lib/igt_chamelium.c
> > > index bff08c0e..b9d80b6b 100644
> > > --- a/lib/igt_chamelium.c
> > > +++ b/lib/igt_chamelium.c
> > > @@ -94,6 +94,14 @@ struct chamelium_frame_dump {
> > >   struct chamelium_port *port;
> > >  };
> > >  
> > > +struct chamelium_fb_crc {
> > > + int fd;
> > > + struct igt_fb *fb;
> > > +
> > > + pthread_t thread_id;
> > > + igt_crc_t *ret;
> > > +};
> > > +
> > 
> > The name of this structure is a little misleading, because now we
> > have
> > an API that exposes both a struct chamelium_fb_crc struct in
> > addition
> > to the igt_crc_t struct. Rename this to something like struct
> > chamelium_fb_crc_work
> > 
> > >  struct chamelium {
> > >   xmlrpc_env env;
> > >   xmlrpc_client *client;
> > > @@ -1003,6 +1011,158 @@ int chamelium_get_frame_limit(struct
> > > chamelium *chamelium,
> > >   return ret;
> > >  }
> > >  
> > > +static uint32_t chamelium_xrgb_hash16(unsigned char *buffer, int
> > > width,
> > > +   int height, int k, int m)
> > > +{
> > 
> > We're not modifying buffer, so make it a const. As well, feel free
> > to
> > mark this function as inline.
> > 
> > > + unsigned char r, g, b;
> > > + uint64_t sum = 0;
> > > + uint64_t count = 0;
> > > + 

Re: [Intel-gfx] [PATCH 4/8] drm/i915: Update format_is_yuv() to include NV12

[Clint Taylor]

On 06/19/2017 11:10 PM, Vidya Srinivas wrote:

From: Chandra Konduru 

This patch adds NV12 to format_is_yuv() function and
made it available for both primary and sprite planes

small nit on the commit message:
 static function in intel_sprite.c is not available to the primary 
plane functions.


Tested-by: Clinton Taylor 
Reviewed-by: Clinton Taylor 

-Clint



v2:
-Use intel_ prefix for format_is_yuv (Ville)

v3: Rebased (me)

Signed-off-by: Chandra Konduru 
Signed-off-by: Nabendu Maiti 
Signed-off-by: Vidya Srinivas 
---
  drivers/gpu/drm/i915/intel_sprite.c | 7 ---
  1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
b/drivers/gpu/drm/i915/intel_sprite.c
index 3e4549a..fba8f02 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -41,13 +41,14 @@
  #include "i915_drv.h"
  
  static bool

-format_is_yuv(uint32_t format)
+intel_format_is_yuv(uint32_t format)
  {
switch (format) {
case DRM_FORMAT_YUYV:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_YVYU:
+   case DRM_FORMAT_NV12:
return true;
default:
return false;
@@ -336,7 +337,7 @@ void intel_pipe_update_end(struct intel_crtc *crtc, struct 
intel_flip_work *work
enum plane_id plane_id = plane->id;
  
  	/* Seems RGB data bypasses the CSC always */

-   if (!format_is_yuv(format))
+   if (!intel_format_is_yuv(format))
return;
  
  	/*

@@ -900,7 +901,7 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state 
*crtc_state,
src_y = src->y1 >> 16;
src_h = drm_rect_height(src) >> 16;
  
-		if (format_is_yuv(fb->format->format)) {

+   if (intel_format_is_yuv(fb->format->format)) {
src_x &= ~1;
src_w &= ~1;
  


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Re: [Intel-gfx] [PATCH 3/8] drm/i915: Set scaler mode for NV12

[Clint Taylor]

Tested-by: Clinton Taylor 
Reviewed-by: Clinton Taylor 

-Clint


On 06/19/2017 11:10 PM, Vidya Srinivas wrote:

From: Chandra Konduru 

This patch sets appropriate scaler mode for NV12 format.
In this mode, skylake scaler does either chroma-upsampling or
chroma-upsampling and resolution scaling

v2: Review comments from Ville addressed
NV12 case to be checked first for setting
the scaler

v3: Rebased (me)

Signed-off-by: Chandra Konduru 
Signed-off-by: Nabendu Maiti 
Signed-off-by: Vidya Srinivas 
---
  drivers/gpu/drm/i915/i915_reg.h | 1 +
  drivers/gpu/drm/i915/intel_atomic.c | 8 +++-
  2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 41ddd25..5c3b120 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6390,6 +6390,7 @@ enum {
  #define PS_SCALER_MODE_MASK (3 << 28)
  #define PS_SCALER_MODE_DYN  (0 << 28)
  #define PS_SCALER_MODE_HQ  (1 << 28)
+#define PS_SCALER_MODE_NV12 (2 << 28)
  #define PS_PLANE_SEL_MASK  (7 << 25)
  #define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
  #define PS_FILTER_MASK (3 << 23)
diff --git a/drivers/gpu/drm/i915/intel_atomic.c 
b/drivers/gpu/drm/i915/intel_atomic.c
index 36d4e63..808f8e6 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -325,7 +325,13 @@ int intel_atomic_setup_scalers(struct drm_i915_private 
*dev_priv,
}
  
  		/* set scaler mode */

-   if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
+   if (plane_state && plane_state->base.fb &&
+   plane_state->base.fb->format->format ==
+   DRM_FORMAT_NV12) {
+   DRM_ERROR("NV12 format setting scaler mode\n");
+   scaler_state->scalers[*scaler_id].mode =
+   PS_SCALER_MODE_NV12;
+   } else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
scaler_state->scalers[*scaler_id].mode = 0;
} else if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) 
{
/*


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Re: [Intel-gfx] [PATCH i-g-t v3 4/4] chamelium: Dump obtained and reference frames to png on crc error

[Lyude Paul]

On Thu, 2017-07-06 at 14:35 +0300, Paul Kocialkowski wrote:
> On Thu, 2017-07-06 at 10:41 +0300, Martin Peres wrote:
> > On 06/07/17 00:44, Lyude Paul wrote:
> > > On Wed, 2017-07-05 at 11:04 +0300, Paul Kocialkowski wrote:
> > > > When a CRC comparison error occurs, it is quite useful to get a
> > > > dump
> > > > of both the frame obtained from the chamelium and the reference
> > > > in
> > > > order
> > > > to compare them.
> > > > 
> > > > This implements the frame dump, with a configurable path that
> > > > enables
> > > > the use of this feature.
> > > > 
> > > > Signed-off-by: Paul Kocialkowski  > > > .com>
> > > > ---
> > > >   lib/igt_chamelium.c |  21 +++
> > > >   lib/igt_chamelium.h |   1 +
> > > >   lib/igt_debugfs.c   |  20 ++
> > > >   lib/igt_debugfs.h   |   1 +
> > > >   tests/chamelium.c   | 104 ---
> > > > -
> > > > 
> > > >   5 files changed, 82 insertions(+), 65 deletions(-)
> > > > 
> > > > diff --git a/lib/igt_chamelium.c b/lib/igt_chamelium.c
> > > > index ef51ef68..9aca6842 100644
> > > > --- a/lib/igt_chamelium.c
> > > > +++ b/lib/igt_chamelium.c
> > > > @@ -57,6 +57,7 @@
> > > >    * |[
> > > >    *[Chamelium]
> > > >    *URL=http://chameleon:9992 # The URL used for
> > > > connecting to
> > > > the Chamelium's RPC server
> > > > + * FrameDumpPath=/tmp # The path to dump frames that
> > > > fail
> > > > comparison checks
> > > 
> > > While no one else really cares about creating frame dumps yet,
> > > it's
> > > possible someone else may in the future if we ever end up taking
> > > more
> > > advantage of automated testing systems like this. So I'd stick
> > > this in
> > > the generic non-chamelium specific section in the config file
> > > 
> > > >    *
> > > >    *# The rest of the sections are used for defining
> > > > connector
> > > > mappings.
> > > >    *# This is required so any tests using the Chamelium
> > > > know
> > > > which connector
> > > > @@ -115,11 +116,26 @@ struct chamelium {
> > > >     struct chamelium_edid *edids;
> > > >     struct chamelium_port *ports;
> > > >     int port_count;
> > > > +
> > > > +   char *frame_dump_path;
> > > >   };
> > > >   
> > > >   static struct chamelium *cleanup_instance;
> > > >   
> > > >   /**
> > > > + * chamelium_get_frame_dump_path:
> > > > + * @chamelium: The Chamelium instance to use
> > > > + *
> > > > + * Retrieves the path to dump frames to.
> > > > + *
> > > > + * Returns: a string with the frame dump path
> > > > + */
> > > > +char *chamelium_get_frame_dump_path(struct chamelium
> > > > *chamelium)
> > > > +{
> > > > +   return chamelium->frame_dump_path;
> > > > +}
> > > > +
> > > > +/**
> > > >    * chamelium_get_ports:
> > > >    * @chamelium: The Chamelium instance to use
> > > >    * @count: Where to store the number of ports
> > > > @@ -1338,6 +1354,11 @@ static bool chamelium_read_config(struct
> > > > chamelium *chamelium, int drm_fd)
> > > >     return false;
> > > >     }
> > > >   
> > > > +   chamelium->frame_dump_path =
> > > > g_key_file_get_string(igt_key_file,
> > > > +      "Ch
> > > > ameliu
> > > > m",
> > > > +      "Fr
> > > > ameDum
> > > > pPath",
> > > > +   
> > > > rror);
> > > > +
> > > >     return chamelium_read_port_mappings(chamelium,
> > > > drm_fd);
> > > >   }
> > > >   
> > > > diff --git a/lib/igt_chamelium.h b/lib/igt_chamelium.h
> > > > index 908e03d1..aa881971 100644
> > > > --- a/lib/igt_chamelium.h
> > > > +++ b/lib/igt_chamelium.h
> > > > @@ -42,6 +42,7 @@ struct chamelium *chamelium_init(int drm_fd);
> > > >   void chamelium_deinit(struct chamelium *chamelium);
> > > >   void chamelium_reset(struct chamelium *chamelium);
> > > >   
> > > > +char *chamelium_get_frame_dump_path(struct chamelium
> > > > *chamelium);
> > > >   struct chamelium_port **chamelium_get_ports(struct chamelium
> > > > *chamelium,
> > > >     int *count);
> > > >   unsigned int chamelium_port_get_type(const struct
> > > > chamelium_port
> > > > *port);
> > > > diff --git a/lib/igt_debugfs.c b/lib/igt_debugfs.c
> > > > index 80f25c61..dcb4e0a7 100644
> > > > --- a/lib/igt_debugfs.c
> > > > +++ b/lib/igt_debugfs.c
> > > > @@ -282,6 +282,26 @@ bool igt_debugfs_search(int device, const
> > > > char
> > > > *filename, const char *substring)
> > > >    */
> > > >   
> > > >   /**
> > > > + * igt_check_crc_equal:
> > > > + * @a: first pipe CRC value
> > > > + * @b: second pipe CRC value
> > > > + *
> > > > + * Compares two CRC values and return whether they match.
> > > > + *
> > > > + * Returns: A boolean indicating whether the CRC values match
> > > > + */
> > > > +bool igt_check_crc_equal(const igt_crc_t *a, const igt_crc_t
> > > > *b)
> > > > +{
> 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cnl: Get DDI clock based on PLLs.

[Patchwork]

== Series Details ==

Series: drm/i915/cnl: Get DDI clock based on PLLs.
URL   : https://patchwork.freedesktop.org/series/26950/
State : success

== Summary ==

Series 26950v1 drm/i915/cnl: Get DDI clock based on PLLs.
https://patchwork.freedesktop.org/api/1.0/series/26950/revisions/1/mbox/

Test kms_force_connector_basic:
Subgroup force-connector-state:
skip   -> PASS   (fi-ivb-3520m) fdo#101048 +3
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-a:
dmesg-warn -> PASS   (fi-pnv-d510) fdo#101597

fdo#101048 https://bugs.freedesktop.org/show_bug.cgi?id=101048
fdo#101597 https://bugs.freedesktop.org/show_bug.cgi?id=101597

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:438s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:431s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:356s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:532s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:511s
fi-byt-j1900 total:279  pass:255  dwarn:0   dfail:0   fail:0   skip:24  
time:483s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:483s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:594s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:434s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:414s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:424s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:499s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:474s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:458s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:573s
fi-kbl-r total:279  pass:260  dwarn:1   dfail:0   fail:0   skip:18  
time:579s
fi-pnv-d510  total:279  pass:222  dwarn:2   dfail:0   fail:0   skip:55  
time:559s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:454s
fi-skl-6700hqtotal:279  pass:262  dwarn:0   dfail:0   fail:0   skip:17  
time:582s
fi-skl-6700k total:279  pass:257  dwarn:4   dfail:0   fail:0   skip:18  
time:468s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:473s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:440s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:544s
fi-snb-2600  total:279  pass:250  dwarn:0   dfail:0   fail:0   skip:29  
time:400s

2132c198e6afd4ed75e89eee86c40c7def49c1dc drm-tip: 2017y-07m-06d-20h-24m-04s UTC 
integration manifest
7983d23 drm/i915/cnl: Get DDI clock based on PLLs.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_5131/
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cnl: Add max allowed Cannonlake DC.

[Patchwork]

== Series Details ==

Series: drm/i915/cnl: Add max allowed Cannonlake DC.
URL   : https://patchwork.freedesktop.org/series/26949/
State : success

== Summary ==

Series 26949v1 drm/i915/cnl: Add max allowed Cannonlake DC.
https://patchwork.freedesktop.org/api/1.0/series/26949/revisions/1/mbox/

Test gem_exec_flush:
Subgroup basic-batch-kernel-default-uc:
pass   -> FAIL   (fi-snb-2600) fdo#17
Test gem_exec_suspend:
Subgroup basic-s4-devices:
pass   -> DMESG-WARN (fi-kbl-7560u) fdo#100125
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-legacy:
pass   -> FAIL   (fi-snb-2600) fdo#100215
Test kms_force_connector_basic:
Subgroup force-connector-state:
skip   -> PASS   (fi-ivb-3520m) fdo#101048 +3
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-b:
dmesg-warn -> PASS   (fi-pnv-d510) fdo#101597

fdo#17 https://bugs.freedesktop.org/show_bug.cgi?id=17
fdo#100125 https://bugs.freedesktop.org/show_bug.cgi?id=100125
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101048 https://bugs.freedesktop.org/show_bug.cgi?id=101048
fdo#101597 https://bugs.freedesktop.org/show_bug.cgi?id=101597

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:436s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:431s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:355s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:533s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:506s
fi-byt-j1900 total:279  pass:255  dwarn:0   dfail:0   fail:0   skip:24  
time:493s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:486s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:599s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:435s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:417s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:419s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:494s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:481s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:464s
fi-kbl-7560u total:279  pass:268  dwarn:1   dfail:0   fail:0   skip:10  
time:569s
fi-kbl-r total:279  pass:260  dwarn:1   dfail:0   fail:0   skip:18  
time:580s
fi-pnv-d510  total:279  pass:222  dwarn:2   dfail:0   fail:0   skip:55  
time:562s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:455s
fi-skl-6700hqtotal:279  pass:262  dwarn:0   dfail:0   fail:0   skip:17  
time:585s
fi-skl-6700k total:279  pass:257  dwarn:4   dfail:0   fail:0   skip:18  
time:468s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:471s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:439s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:545s
fi-snb-2600  total:279  pass:248  dwarn:0   dfail:0   fail:2   skip:29  
time:407s

2132c198e6afd4ed75e89eee86c40c7def49c1dc drm-tip: 2017y-07m-06d-20h-24m-04s UTC 
integration manifest
86c4697 drm/i915/cnl: Add max allowed Cannonlake DC.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_5130/
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Re: [Intel-gfx] [PATCH i-g-t v3 4/4] chamelium: Dump obtained and reference frames to png on crc error

[Lyude Paul]

--snip--
(also sorry this one took a while to get to, had to do a lot of
thinking because I never really solved the problems mentioned here when
I tried working on this...)

On Thu, 2017-07-06 at 16:33 +0300, Paul Kocialkowski wrote:
> On Thu, 2017-07-06 at 14:31 +0300, Paul Kocialkowski wrote:
> > > 
> > > There's lots of potential here for copy pasta to form in the
> > > future,
> > > since the API here puts a lot of work on the caller to set things
> > > up
> > > for frame dumping. IMO, it would be worth it to teach the CRC
> > > checking
> > > functions to automatically do frame dumps on mismatch if the CRC
> > > source
> > > supports it. This will save us from having to have separate frame
> > > dump
> > > APIs in the future if we ever end up adding support for other
> > > kinds
> > > of
> > > automated test equipment.
> > 
> > I don't think it makes so much sense to do this in the CRC checking
> > functions,
> > just because they are semantically expected to do one thing: CRC
> > checking, and
> > doing frame dumps seems like going overboard.
> > 
> > On the other hand, I do agree that the dumping and saving part can
> > and
> > should be
> > made common, but maybe as a separate function. So that would be two
> > calls for
> > the tests: one to check the crc and one to dump and save the frame.
> 
> A strong case to support this vision: in VGA frame testing, we have
> already dumped the frame and don't do CRC checking, yet we also need
> to
> save the frames if there is a mismatch.
> 
> It would be a shame that the dumping logic becomes part of the CRC
> functions, since that would mean duplicating that logic for VGA
> testing
> (as it's currently done in the version I just sent out).
That is a good point, but there's some things I think you might want to
consider. Mainly that in a test that passes, we of course don't write
any framedumps back to the disk since nothing failed. IMO, I would
-think- that we care a bit more about the performance hit that happens
on passing tests vs. failing tests, since tests aren't really supposed
to fail under ideal conditions anyway. Might be better to verify with
the mupuf and the other people actually running Intel's CI though,
since I'm not one of them.

As well, one advantage we do have here from the chamelium end is that
you can only really be screen grabbing from one port at a time. So you
could actually just track stuff internally in the igt_chamelium API and
when a user tries to download a framedump that we've already
downloaded, we can just hand them back a cached copy of it.

> 
> In spite of that, I think having a common function, called from the
> test
> itself is probably the best approach here.
Not sure if I misspoke here but I didn't mean to imply that I'm against
having functions for doing frame dumping exposed to the callers. I had
already figured there'd probably be situations where just having the
CRC checking do the frame dumping wouldn't be enough.

This being said though, your viewpoint does make me realize it might
not be a great idea to do autoframe dumping in -all- crc checking
functions necessarily, but also makes me realize that this might even
be a requirement if we still want to try keeping around
igt_assert_crc_equal() and not just replace it outright with a function
that doesn't fail the whole test (if we fail the test, there isn't
really a way we can do a framedump from it afterwards). So I would
think we can at least exclude igt_check_crc_equal() from doing
automatic framedumping, but I still think it would be a good idea to
implement igt_assert_crc_equal().

As for the what you're talking about, e.g. doing frame dump comparisons
on VGA, I think the solution might be not to make any of the code for
doing the actual frame comparisons chamelium specific either (except
maybe for the part where we trim the framebuffer we get so it only
contains the actual image dump).

So how about this: let's introduce a generic frame comparison API using
the code you've already written for doing this on VGA with the
chamelium. Make it part of the igt library, and have it just accept
normal pixman images and perform fuzzy comparisons between them. In
doing that, we can introduce a generic dump-frames-on-error API through
there much more easily.

My big aim here is just to make it so that people using igt don't have
to do anything to get frame dumping in their tests, it just "works".

> 
> > I have also duplicated that logic in upcoming VGA frame testing, so
> > there is definitely a need for less duplication.
> > 
> > > As well, I like how you removed the redundancy between
> > > test_display_crc_single() and test_display_crc_multiple().
> > > However
> > > since those are somewhat unrelated changes to the code path for
> > > these
> > > tests it would be better to have that re-factoring as a separate
> > > patch
> > > so as to make it easier for anyone who might need to bisect this
> > > code
> > > in the future.
> > 
> > Fair enough, it just felt weird 

Re: [Intel-gfx] [PATCH] drm/i915/cnl: Don't trust VBT's alternate pin for port D for now.

[Clint Taylor]

On 07/06/2017 02:08 PM, Rodrigo Vivi wrote:

Cannon Lake's VBT that is currently available for B0 stepping
states that port D uses alternate pin 3 messing up with the
default pin-port mapping table. Using that information we cannot
get HDMI working properly. So for now we don't relly on VBT for
this information.

Cc: Clint Taylor 
Signed-off-by: Rodrigo Vivi 
---
  drivers/gpu/drm/i915/intel_bios.c | 9 +
  1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_bios.c 
b/drivers/gpu/drm/i915/intel_bios.c
index 639d45c..82b144c 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -1187,6 +1187,15 @@ static void parse_ddi_port(struct drm_i915_private 
*dev_priv, enum port port,
if (is_dvi) {
info->alternate_ddc_pin = ddc_pin;
  
+		/*

+* All VBTs that we got so far for B Stepping has this
+* information wrong for Port D. So, let's just ignore for now.
+*/
+   if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0) &&
+   port == PORT_D) {
+   info->alternate_ddc_pin = 0;
+   }
+


Reviewed-by: Clinton Taylor 

-Clint


sanitize_ddc_pin(dev_priv, port);
}
  


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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cnl: Inherit RPS stuff from previous platforms.

[Patchwork]

== Series Details ==

Series: drm/i915/cnl: Inherit RPS stuff from previous platforms.
URL   : https://patchwork.freedesktop.org/series/26948/
State : success

== Summary ==

Series 26948v1 drm/i915/cnl: Inherit RPS stuff from previous platforms.
https://patchwork.freedesktop.org/api/1.0/series/26948/revisions/1/mbox/

Test gem_exec_flush:
Subgroup basic-batch-kernel-default-uc:
pass   -> FAIL   (fi-snb-2600) fdo#17
Test kms_force_connector_basic:
Subgroup force-connector-state:
skip   -> PASS   (fi-ivb-3520m) fdo#101048 +3
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-a:
dmesg-warn -> PASS   (fi-pnv-d510) fdo#101597 +1
Subgroup suspend-read-crc-pipe-b:
pass   -> DMESG-WARN (fi-byt-j1900) fdo#101705

fdo#17 https://bugs.freedesktop.org/show_bug.cgi?id=17
fdo#101048 https://bugs.freedesktop.org/show_bug.cgi?id=101048
fdo#101597 https://bugs.freedesktop.org/show_bug.cgi?id=101597
fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:438s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:427s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:360s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:528s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:507s
fi-byt-j1900 total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  
time:498s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:480s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:594s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:437s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:419s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:426s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:507s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:472s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:465s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:570s
fi-kbl-r total:279  pass:260  dwarn:1   dfail:0   fail:0   skip:18  
time:583s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:566s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:458s
fi-skl-6700hqtotal:279  pass:262  dwarn:0   dfail:0   fail:0   skip:17  
time:587s
fi-skl-6700k total:279  pass:257  dwarn:4   dfail:0   fail:0   skip:18  
time:463s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:479s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:432s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:536s
fi-snb-2600  total:279  pass:249  dwarn:0   dfail:0   fail:1   skip:29  
time:412s

2132c198e6afd4ed75e89eee86c40c7def49c1dc drm-tip: 2017y-07m-06d-20h-24m-04s UTC 
integration manifest
a9fecce drm/i915/cnl: Inherit RPS stuff from previous platforms.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_5129/
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Re: [Intel-gfx] [PATCH] drm/i915/cnl: Cannonlake color init.

[Clint Taylor]

Reviewed-by: Clinton Taylor 

-Clint

On 07/06/2017 02:01 PM, Rodrigo Vivi wrote:

Cannonlake has same color setup as Geminilake.
Legacy color load luts doesn't work anymore on Cannonlake+.

Cc: Clint Taylor 
Cc: Ander Conselvan de Oliveira 
Signed-off-by: Rodrigo Vivi 
---
  drivers/gpu/drm/i915/i915_pci.c  | 1 +
  drivers/gpu/drm/i915/intel_color.c   | 2 +-
  drivers/gpu/drm/i915/intel_display.c | 4 ++--
  drivers/gpu/drm/i915/intel_sprite.c  | 2 +-
  4 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 04aaf55..a1e6b69 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -449,6 +449,7 @@
.gen = 10,
.ddb_size = 1024,
.has_csr = 1,
+   .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
  };
  
  /*

diff --git a/drivers/gpu/drm/i915/intel_color.c 
b/drivers/gpu/drm/i915/intel_color.c
index 306c6b0..f85d575 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -615,7 +615,7 @@ void intel_color_init(struct drm_crtc *crtc)
   IS_BROXTON(dev_priv)) {
dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
dev_priv->display.load_luts = broadwell_load_luts;
-   } else if (IS_GEMINILAKE(dev_priv)) {
+   } else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
dev_priv->display.load_luts = glk_load_luts;
} else {
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 0648fd7..2144adc 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3311,7 +3311,7 @@ u32 skl_plane_ctl(const struct intel_crtc_state 
*crtc_state,
  
  	plane_ctl = PLANE_CTL_ENABLE;
  
-	if (!IS_GEMINILAKE(dev_priv)) {

+   if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) {
plane_ctl |=
PLANE_CTL_PIPE_GAMMA_ENABLE |
PLANE_CTL_PIPE_CSC_ENABLE |
@@ -3367,7 +3367,7 @@ static void skylake_update_primary_plane(struct 
intel_plane *plane,
  
  	spin_lock_irqsave(_priv->uncore.lock, irqflags);
  
-	if (IS_GEMINILAKE(dev_priv)) {

+   if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
  PLANE_COLOR_PIPE_GAMMA_ENABLE |
  PLANE_COLOR_PIPE_CSC_ENABLE |
diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
b/drivers/gpu/drm/i915/intel_sprite.c
index 0c650c2..94f9a13 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -262,7 +262,7 @@ void intel_pipe_update_end(struct intel_crtc *crtc, struct 
intel_flip_work *work
  
  	spin_lock_irqsave(_priv->uncore.lock, irqflags);
  
-	if (IS_GEMINILAKE(dev_priv)) {

+   if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
  PLANE_COLOR_PIPE_GAMMA_ENABLE |
  PLANE_COLOR_PIPE_CSC_ENABLE |


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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix pre-g4x GPU reset, again (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Fix pre-g4x GPU reset, again (rev3)
URL   : https://patchwork.freedesktop.org/series/26554/
State : success

== Summary ==

Series 26554v3 drm/i915: Fix pre-g4x GPU reset, again
https://patchwork.freedesktop.org/api/1.0/series/26554/revisions/3/mbox/

Test gem_exec_flush:
Subgroup basic-batch-kernel-default-uc:
pass   -> FAIL   (fi-snb-2600) fdo#17
Test gem_ringfill:
Subgroup basic-default-hang:
dmesg-warn -> PASS   (fi-blb-e6850) fdo#101600 +1
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-legacy:
pass   -> FAIL   (fi-snb-2600) fdo#100215
Test kms_force_connector_basic:
Subgroup force-connector-state:
skip   -> PASS   (fi-ivb-3520m) fdo#101048 +3
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-b:
dmesg-warn -> PASS   (fi-pnv-d510) fdo#101597

fdo#17 https://bugs.freedesktop.org/show_bug.cgi?id=17
fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101048 https://bugs.freedesktop.org/show_bug.cgi?id=101048
fdo#101597 https://bugs.freedesktop.org/show_bug.cgi?id=101597

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:443s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:435s
fi-blb-e6850 total:279  pass:225  dwarn:0   dfail:0   fail:0   skip:54  
time:350s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:519s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:508s
fi-byt-j1900 total:279  pass:255  dwarn:0   dfail:0   fail:0   skip:24  
time:489s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:483s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:597s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:429s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:414s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:427s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:503s
fi-ivb-3770  total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:475s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:461s
fi-kbl-7560u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:572s
fi-kbl-r total:279  pass:260  dwarn:1   dfail:0   fail:0   skip:18  
time:583s
fi-pnv-d510  total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  
time:559s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:453s
fi-skl-6700hqtotal:279  pass:262  dwarn:0   dfail:0   fail:0   skip:17  
time:591s
fi-skl-6700k total:279  pass:257  dwarn:4   dfail:0   fail:0   skip:18  
time:466s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:481s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:438s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:551s
fi-snb-2600  total:279  pass:248  dwarn:0   dfail:0   fail:2   skip:29  
time:405s

2132c198e6afd4ed75e89eee86c40c7def49c1dc drm-tip: 2017y-07m-06d-20h-24m-04s UTC 
integration manifest
930113b drm/i915: Solve the GPU reset vs. modeset deadlocks with an rw_semaphore
b0a0c5b drm/atomic: Introduce drm_atomic_helper_duplicate_commited_state()
82f3025 drm/i915: Refactor __intel_atomic_commit_tail()
0884964 drm/i915% Store vma gtt offset in plane state
da1e405 drm: Return the connector from drm_connector_get()
516db75 drm/atomic: Fix up the kernel docs for the state duplication functions
03827dc drm/atomic: Pass old state explicitly to .atomic_duplicate_state()
5b79edc drm/mediatek: s/old_state/old_mtk_state/
69c7aad drm/arm: s/old_state/old_mali_state/
0e095a7 drm/atomic: Pass old state to 
__drm_atomic_helper_crtc_duplicate_state() & co. explicitly
b2f0028 drm/atomic: Make private objs proper objects
6d37c2c drm/atomic: Convert private_objs to drm_dynarray
d8aac39 drm/atomic: Remove pointless private object NULL state check
92bb160 drm/atomic: Convert state->connectors to drm_dynarray
d82b0d4 drm: Add drm_dynarray
53b9d91 drm/i915: Eliminate crtc->state usage from intel_atomic_commit_tail and 
.crtc_update()
93c8095 drm/i915: Eliminate crtc->state usage from intel_update_pipe_config()
bc502b0 drm/i915: Eliminate obj->state usage from pre/post plane update
a8c8790 drm/i915: Pass proper old/new states to 
intel_plane_atomic_check_with_state()
5f52268 drm/i915: Eliminate obj->state usage in g4x/vlv/chv wm computation
10977db drm/i915: Pass the crtc state explicitly to 
intel_pipe_update_start/end()
9f9f8e9 drm/i915: Pass the new crtc state to color management code

== Logs ==

For 

[Intel-gfx] [PATCH] drm/i915/cnl: Don't trust VBT's alternate pin for port D for now.

[Rodrigo Vivi]

Cannon Lake's VBT that is currently available for B0 stepping
states that port D uses alternate pin 3 messing up with the
default pin-port mapping table. Using that information we cannot
get HDMI working properly. So for now we don't relly on VBT for
this information.

Cc: Clint Taylor 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_bios.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_bios.c 
b/drivers/gpu/drm/i915/intel_bios.c
index 639d45c..82b144c 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -1187,6 +1187,15 @@ static void parse_ddi_port(struct drm_i915_private 
*dev_priv, enum port port,
if (is_dvi) {
info->alternate_ddc_pin = ddc_pin;
 
+   /*
+* All VBTs that we got so far for B Stepping has this
+* information wrong for Port D. So, let's just ignore for now.
+*/
+   if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0) &&
+   port == PORT_D) {
+   info->alternate_ddc_pin = 0;
+   }
+
sanitize_ddc_pin(dev_priv, port);
}
 
-- 
1.9.1

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[Intel-gfx] [PATCH] drm/i915/cnl: Gen10 render context size.

[Rodrigo Vivi]

No change on render context size is required for Gen10.

So this patch doesn't change the default behaviour,
but only avoid the missing_case message.

Cc: Ben Widawsky 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_engine_cs.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index a55cd72..24db316 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -149,6 +149,7 @@ struct engine_info {
switch (INTEL_GEN(dev_priv)) {
default:
MISSING_CASE(INTEL_GEN(dev_priv));
+   case 10:
case 9:
return GEN9_LR_CONTEXT_RENDER_SIZE;
case 8:
-- 
1.9.1

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[Intel-gfx] [PATCH] drm/i915/cnl: Enable Audio Pin Buffer.

[Rodrigo Vivi]

Starting on CNL, we need to enable Audio Pin Buffer.

By the spec it seems that this is part of audio programming,
so let's give them the hability to set/unset this as needed.

v2: With a hook so audio driver can control it.
v3: Put back reg definition lost on v2.

Cc: Dhinakaran Pandiyan 
Cc: Jani Nikula 
Cc: Sanyog Kale 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/i915_reg.h|  3 +++
 drivers/gpu/drm/i915/intel_audio.c | 16 
 include/drm/i915_component.h   |  6 ++
 3 files changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 64cc674..aab38da 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2643,6 +2643,9 @@ enum skl_disp_power_wells {
 #define I915_HDMI_LPE_AUDIO_BASE   (VLV_DISPLAY_BASE + 0x65000)
 #define I915_HDMI_LPE_AUDIO_SIZE   0x1000
 
+#define AUDIO_PIN_BUF_CTL  _MMIO(0x48414)
+#define AUDIO_PIN_BUF_ENABLE   (1 << 31)
+
 /* DisplayPort Audio w/ LPE */
 #define VLV_AUD_CHICKEN_BIT_REG_MMIO(VLV_DISPLAY_BASE + 
0x62F38)
 #define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0)
diff --git a/drivers/gpu/drm/i915/intel_audio.c 
b/drivers/gpu/drm/i915/intel_audio.c
index d805b6e..0c83254 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -865,6 +865,21 @@ static int i915_audio_component_get_eld(struct device 
*kdev, int port,
return ret;
 }
 
+static void i915_audio_component_pin_buf(struct device *kdev, bool enable)
+{
+   struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
+
+   if (!IS_CANNONLAKE(dev_priv))
+   return;
+
+   if (enable)
+   I915_WRITE(AUDIO_PIN_BUF_CTL, I915_READ(AUDIO_PIN_BUF_CTL) |
+  AUDIO_PIN_BUF_ENABLE);
+   else
+   I915_WRITE(AUDIO_PIN_BUF_CTL, I915_READ(AUDIO_PIN_BUF_CTL) &
+  ~AUDIO_PIN_BUF_ENABLE);
+}
+
 static const struct i915_audio_component_ops i915_audio_component_ops = {
.owner  = THIS_MODULE,
.get_power  = i915_audio_component_get_power,
@@ -873,6 +888,7 @@ static int i915_audio_component_get_eld(struct device 
*kdev, int port,
.get_cdclk_freq = i915_audio_component_get_cdclk_freq,
.sync_audio_rate = i915_audio_component_sync_audio_rate,
.get_eld= i915_audio_component_get_eld,
+   .pin_buf= i915_audio_component_pin_buf,
 };
 
 static int i915_audio_component_bind(struct device *i915_kdev,
diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h
index 545c6e0..b8875d4 100644
--- a/include/drm/i915_component.h
+++ b/include/drm/i915_component.h
@@ -79,6 +79,12 @@ struct i915_audio_component_ops {
 */
int (*get_eld)(struct device *, int port, int pipe, bool *enabled,
   unsigned char *buf, int max_bytes);
+   /**
+* @pin_buf: Enable or disable pin buffer.
+*
+* Allow audio driver the toggle pin buffer.
+*/
+   void (*pin_buf)(struct device *, bool enable);
 };
 
 /**
-- 
1.9.1

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[Intel-gfx] [PATCH] drm/i915/cnl: Cannonlake color init.

[Rodrigo Vivi]

Cannonlake has same color setup as Geminilake.
Legacy color load luts doesn't work anymore on Cannonlake+.

Cc: Clint Taylor 
Cc: Ander Conselvan de Oliveira 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/i915_pci.c  | 1 +
 drivers/gpu/drm/i915/intel_color.c   | 2 +-
 drivers/gpu/drm/i915/intel_display.c | 4 ++--
 drivers/gpu/drm/i915/intel_sprite.c  | 2 +-
 4 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 04aaf55..a1e6b69 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -449,6 +449,7 @@
.gen = 10,
.ddb_size = 1024,
.has_csr = 1,
+   .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
 };
 
 /*
diff --git a/drivers/gpu/drm/i915/intel_color.c 
b/drivers/gpu/drm/i915/intel_color.c
index 306c6b0..f85d575 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -615,7 +615,7 @@ void intel_color_init(struct drm_crtc *crtc)
   IS_BROXTON(dev_priv)) {
dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
dev_priv->display.load_luts = broadwell_load_luts;
-   } else if (IS_GEMINILAKE(dev_priv)) {
+   } else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
dev_priv->display.load_luts = glk_load_luts;
} else {
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 0648fd7..2144adc 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3311,7 +3311,7 @@ u32 skl_plane_ctl(const struct intel_crtc_state 
*crtc_state,
 
plane_ctl = PLANE_CTL_ENABLE;
 
-   if (!IS_GEMINILAKE(dev_priv)) {
+   if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) {
plane_ctl |=
PLANE_CTL_PIPE_GAMMA_ENABLE |
PLANE_CTL_PIPE_CSC_ENABLE |
@@ -3367,7 +3367,7 @@ static void skylake_update_primary_plane(struct 
intel_plane *plane,
 
spin_lock_irqsave(_priv->uncore.lock, irqflags);
 
-   if (IS_GEMINILAKE(dev_priv)) {
+   if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
  PLANE_COLOR_PIPE_GAMMA_ENABLE |
  PLANE_COLOR_PIPE_CSC_ENABLE |
diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
b/drivers/gpu/drm/i915/intel_sprite.c
index 0c650c2..94f9a13 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -262,7 +262,7 @@ void intel_pipe_update_end(struct intel_crtc *crtc, struct 
intel_flip_work *work
 
spin_lock_irqsave(_priv->uncore.lock, irqflags);
 
-   if (IS_GEMINILAKE(dev_priv)) {
+   if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
  PLANE_COLOR_PIPE_GAMMA_ENABLE |
  PLANE_COLOR_PIPE_CSC_ENABLE |
-- 
1.9.1

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[Intel-gfx] [PATCH 3/3] drm/i915/cnl: Avoid old DDI translation functions on Cannonlake.

[Rodrigo Vivi]

Cannonlake uses a different swing voltage initalization
sequence scheme that doesn't require these old functions.

All other DDI, voltage swing and PLLs initialialization
and configuration are already in place for Cannonlake.
This patch only removes unecessary steps probably saving
us from some useless warnings.

Cc: Clint Taylor 
Cc: Mika Kahola 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_ddi.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 80e96f1..9e9bfbe 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -596,7 +596,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private 
*dev_priv, enum port por
 
hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 
-   if (IS_GEN9_LP(dev_priv))
+   if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10)
return hdmi_level;
 
if (IS_GEN9_BC(dev_priv)) {
@@ -688,7 +688,7 @@ static void intel_prepare_dp_ddi_buffers(struct 
intel_encoder *encoder)
enum port port = intel_ddi_get_encoder_port(encoder);
const struct ddi_buf_trans *ddi_translations;
 
-   if (IS_GEN9_LP(dev_priv))
+   if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10)
return;
 
switch (encoder->type) {
@@ -741,7 +741,7 @@ static void intel_prepare_hdmi_ddi_buffers(struct 
intel_encoder *encoder)
enum port port = intel_ddi_get_encoder_port(encoder);
const struct ddi_buf_trans *ddi_translations_hdmi;
 
-   if (IS_GEN9_LP(dev_priv))
+   if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10)
return;
 
hdmi_level = intel_ddi_hdmi_level(dev_priv, port);
-- 
1.9.1

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[Intel-gfx] [PATCH 2/3] drm/i915/cnl: Dump the right pll registers when dumping pipe config.

[Rodrigo Vivi]

Different from SKL we don't need ctrl1 and cfgcr2, but
we need to dump cfgcr0 amd cfgcr1 instead.

v2: rebase and commit message

Cc: Clint Taylor 
Cc: Mika Kahola 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 2f7b0e6..a2a3d93 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2379,6 +2379,15 @@ static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc 
*crtc,
return pll;
 }
 
+static void cnl_dump_hw_state(struct drm_i915_private *dev_priv,
+ struct intel_dpll_hw_state *hw_state)
+{
+   DRM_DEBUG_KMS("dpll_hw_state: "
+ "cfgcr0: 0x%x, cfgcr1: 0x%x\n",
+ hw_state->cfgcr0,
+ hw_state->cfgcr1);
+}
+
 static const struct intel_shared_dpll_funcs cnl_ddi_pll_funcs = {
.enable = cnl_ddi_pll_enable,
.disable = cnl_ddi_pll_disable,
@@ -2395,7 +2404,7 @@ static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc 
*crtc,
 static const struct intel_dpll_mgr cnl_pll_mgr = {
.dpll_info = cnl_plls,
.get_dpll = cnl_get_dpll,
-   .dump_hw_state = skl_dump_hw_state,
+   .dump_hw_state = cnl_dump_hw_state,
 };
 
 /**
-- 
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[Intel-gfx] [PATCH 1/3] drm/i915/cnl: Add allowed DP rates for Cannonlake.

[Rodrigo Vivi]

One warning is that in order to get DPLL Link rates
3240 and 4050 that allows 648000 and 81 is that:
"Some SKUs may require elevated I/O voltage to support
this."

v2: Rebase on top of source_rates changes.

Cc: Clint Taylor 
Cc: Mika Kahola 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_dp.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 2d42d09..4355bdf 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -97,6 +97,9 @@ struct dp_link_dpll {
  324000, 432000, 54 };
 static const int skl_rates[] = { 162000, 216000, 27,
  324000, 432000, 54 };
+static const int cnl_rates[] = { 162000, 216000, 27,
+324000, 432000, 54,
+648000, 81 };
 static const int default_rates[] = { 162000, 27, 54 };
 
 /**
@@ -238,6 +241,9 @@ int intel_dp_max_lane_count(struct intel_dp *intel_dp)
if (IS_GEN9_LP(dev_priv)) {
source_rates = bxt_rates;
size = ARRAY_SIZE(bxt_rates);
+   } else if (IS_CANNONLAKE(dev_priv)) {
+   source_rates = cnl_rates;
+   size = ARRAY_SIZE(cnl_rates);
} else if (IS_GEN9_BC(dev_priv)) {
source_rates = skl_rates;
size = ARRAY_SIZE(skl_rates);
-- 
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[Intel-gfx] [PATCH] drm/i915/cnl: Get DDI clock based on PLLs.

[Rodrigo Vivi]

PLLs are the source clocks for the DDIs so in order
to determine the ddi clock we need to check the PLL
configuration.

v2: Mika pointed out that 24 was hardcoded while it
should consider ref clock that can be either 24KHz
or 19.2KHz on CNL.

Reviewed-by: Mika Kahola 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/i915_reg.h  |   2 +
 drivers/gpu/drm/i915/intel_ddi.c | 111 +++
 2 files changed, 113 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 64cc674..d6b537e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8343,6 +8343,7 @@ enum {
 #define  DPLL_CFGCR0_LINK_RATE_3240(6 << 25)
 #define  DPLL_CFGCR0_LINK_RATE_4050(7 << 25)
 #define  DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10)
+#define  DPLL_CFGCR0_DCO_FRAC_SHIFT(10)
 #define  DPLL_CFGCR0_DCO_FRACTION(x)   ((x) << 10)
 #define  DPLL_CFGCR0_DCO_INTEGER_MASK  (0x3ff)
 #define CNL_DPLL_CFGCR0(pll)   _MMIO_PLL(pll, _CNL_DPLL0_CFGCR0, 
_CNL_DPLL1_CFGCR0)
@@ -8350,6 +8351,7 @@ enum {
 #define _CNL_DPLL0_CFGCR1  0x6C004
 #define _CNL_DPLL1_CFGCR1  0x6C084
 #define  DPLL_CFGCR1_QDIV_RATIO_MASK   (0xff << 10)
+#define  DPLL_CFGCR1_QDIV_RATIO_SHIFT  (10)
 #define  DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10)
 #define  DPLL_CFGCR1_QDIV_MODE(x)  ((x) << 9)
 #define  DPLL_CFGCR1_KDIV_MASK (7 << 6)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 80e96f1..241decf 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1103,6 +1103,62 @@ static int skl_calc_wrpll_link(struct drm_i915_private 
*dev_priv,
return dco_freq / (p0 * p1 * p2 * 5);
 }
 
+static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
+  uint32_t pll_id)
+{
+   uint32_t cfgcr0, cfgcr1;
+   uint32_t p0, p1, p2, dco_freq, ref_clock;
+
+   cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
+   cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
+
+   p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
+   p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
+
+   if (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
+   p1 = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
+   DPLL_CFGCR1_QDIV_RATIO_SHIFT;
+   else
+   p1 = 1;
+
+
+   switch (p0) {
+   case DPLL_CFGCR1_PDIV_2:
+   p0 = 2;
+   break;
+   case DPLL_CFGCR1_PDIV_3:
+   p0 = 3;
+   break;
+   case DPLL_CFGCR1_PDIV_5:
+   p0 = 5;
+   break;
+   case DPLL_CFGCR1_PDIV_7:
+   p0 = 7;
+   break;
+   }
+
+   switch (p2) {
+   case DPLL_CFGCR1_KDIV_1:
+   p2 = 1;
+   break;
+   case DPLL_CFGCR1_KDIV_2:
+   p2 = 2;
+   break;
+   case DPLL_CFGCR1_KDIV_4:
+   p2 = 4;
+   break;
+   }
+
+   ref_clock = dev_priv->cdclk.hw.ref;
+
+   dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
+
+   dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
+ DPLL_CFGCR0_DCO_FRAC_SHIFT) * ref_clock) / 0x8000;
+
+   return dco_freq / (p0 * p1 * p2 * 5);
+}
+
 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
 {
int dotclock;
@@ -1124,6 +1180,59 @@ static void ddi_dotclock_get(struct intel_crtc_state 
*pipe_config)
pipe_config->base.adjusted_mode.crtc_clock = dotclock;
 }
 
+static void cnl_ddi_clock_get(struct intel_encoder *encoder,
+ struct intel_crtc_state *pipe_config)
+{
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+   int link_clock = 0;
+   uint32_t cfgcr0, pll_id;
+
+   pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
+
+   cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
+
+   if (cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
+   link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
+   } else {
+   link_clock = cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
+
+   switch (link_clock) {
+   case DPLL_CFGCR0_LINK_RATE_810:
+   link_clock = 81000;
+   break;
+   case DPLL_CFGCR0_LINK_RATE_1080:
+   link_clock = 108000;
+   break;
+   case DPLL_CFGCR0_LINK_RATE_1350:
+   link_clock = 135000;
+   break;
+   case DPLL_CFGCR0_LINK_RATE_1620:
+   link_clock = 162000;
+   break;
+   case DPLL_CFGCR0_LINK_RATE_2160:
+   link_clock = 216000;
+   break;
+   case DPLL_CFGCR0_LINK_RATE_2700:
+   link_clock = 27;
+   

[Intel-gfx] [PATCH] drm/i915/cnl: Add max allowed Cannonlake DC.

[Rodrigo Vivi]

This is a follow-up after enabling DC states with
commit: "drm/i915/DMC/CNL: Load DMC on CNL".

Cc: Anusha Srivatsa 
Cc: Imre Deak 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 5eb9c5e..f630d63 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2492,7 +2492,7 @@ static uint32_t get_allowed_dc_mask(const struct 
drm_i915_private *dev_priv,
int requested_dc;
int max_dc;
 
-   if (IS_GEN9_BC(dev_priv)) {
+   if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
max_dc = 2;
mask = 0;
} else if (IS_GEN9_LP(dev_priv)) {
-- 
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[Intel-gfx] [PATCH] drm/i915/cnl: Inherit RPS stuff from previous platforms.

[Rodrigo Vivi]

Apparently no change on RPS stuff from previous platforms.

v2: Merging to rps related patches in one and also adding
missed cases.

Cc: David Weinehall 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 20 
 drivers/gpu/drm/i915/i915_reg.h |  4 ++--
 drivers/gpu/drm/i915/i915_sysfs.c   |  2 +-
 drivers/gpu/drm/i915/intel_pm.c | 18 +-
 4 files changed, 24 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 643f56b..ca2e34b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1159,7 +1159,7 @@ static int i915_frequency_info(struct seq_file *m, void 
*unused)
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 
reqf = I915_READ(GEN6_RPNSWREQ);
-   if (IS_GEN9(dev_priv))
+   if (INTEL_GEN(dev_priv) >= 9)
reqf >>= 23;
else {
reqf &= ~GEN6_TURBO_DISABLE;
@@ -1181,7 +1181,7 @@ static int i915_frequency_info(struct seq_file *m, void 
*unused)
rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & 
GEN6_CURBSYTAVG_MASK;
-   if (IS_GEN9(dev_priv))
+   if (INTEL_GEN(dev_priv) >= 9)
cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
@@ -1210,7 +1210,7 @@ static int i915_frequency_info(struct seq_file *m, void 
*unused)
   dev_priv->rps.pm_intrmsk_mbz);
seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
seq_printf(m, "Render p-state ratio: %d\n",
-  (gt_perf_status & (IS_GEN9(dev_priv) ? 0x1ff00 : 
0xff00)) >> 8);
+  (gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ? 
0x1ff00 : 0xff00)) >> 8);
seq_printf(m, "Render p-state VID: %d\n",
   gt_perf_status & 0xff);
seq_printf(m, "Render p-state limit: %d\n",
@@ -1241,18 +1241,21 @@ static int i915_frequency_info(struct seq_file *m, void 
*unused)
 
max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
rp_state_cap >> 16) & 0xff;
-   max_freq *= (IS_GEN9_BC(dev_priv) ? GEN9_FREQ_SCALER : 1);
+   max_freq *= (IS_GEN9_BC(dev_priv) ||
+IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
   intel_gpu_freq(dev_priv, max_freq));
 
max_freq = (rp_state_cap & 0xff00) >> 8;
-   max_freq *= (IS_GEN9_BC(dev_priv) ? GEN9_FREQ_SCALER : 1);
+   max_freq *= (IS_GEN9_BC(dev_priv) ||
+IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
   intel_gpu_freq(dev_priv, max_freq));
 
max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
rp_state_cap >> 0) & 0xff;
-   max_freq *= (IS_GEN9_BC(dev_priv) ? GEN9_FREQ_SCALER : 1);
+   max_freq *= (IS_GEN9_BC(dev_priv) ||
+IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
   intel_gpu_freq(dev_priv, max_freq));
seq_printf(m, "Max overclocked frequency: %dMHz\n",
@@ -1855,7 +1858,7 @@ static int i915_ring_freq_table(struct seq_file *m, void 
*unused)
if (ret)
goto out;
 
-   if (IS_GEN9_BC(dev_priv)) {
+   if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
/* Convert GT frequency to 50 HZ units */
min_gpu_freq =
dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
@@ -1875,7 +1878,8 @@ static int i915_ring_freq_table(struct seq_file *m, void 
*unused)
   _freq);
seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
   intel_gpu_freq(dev_priv, (gpu_freq *
-(IS_GEN9_BC(dev_priv) ?
+(IS_GEN9_BC(dev_priv) ||
+ IS_CANNONLAKE(dev_priv) ?
  GEN9_FREQ_SCALER : 1))),
   ((ia_freq >> 0) & 0xff) * 100,
   ((ia_freq >> 8) & 0xff) * 100);
diff --git 

[Intel-gfx] [PATCH 20/22] drm/i915: Refactor __intel_atomic_commit_tail()

[ville . syrjala]

From: Ville Syrjälä 

Split intel_atomic_commit_tail() into a lower level function that does
the actual commit, and a higher level one that waits for the
dependencies and signals the commit as done. We'll reuse the lower
level function to perform commits during GPU resets.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_display.c | 18 +-
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 0ff3f254ee58..e9c85d7cbb3e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13021,7 +13021,7 @@ static void 
intel_atomic_helper_free_state_worker(struct work_struct *work)
intel_atomic_helper_free_state(dev_priv);
 }
 
-static void intel_atomic_commit_tail(struct drm_atomic_state *state)
+static void __intel_atomic_commit_tail(struct drm_atomic_state *state)
 {
struct drm_device *dev = state->dev;
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
@@ -13034,8 +13034,6 @@ static void intel_atomic_commit_tail(struct 
drm_atomic_state *state)
unsigned crtc_vblank_mask = 0;
int i;
 
-   drm_atomic_helper_wait_for_dependencies(state);
-
if (intel_state->modeset)
intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
 
@@ -13160,8 +13158,6 @@ static void intel_atomic_commit_tail(struct 
drm_atomic_state *state)
if (intel_state->modeset && intel_can_enable_sagv(state))
intel_enable_sagv(dev_priv);
 
-   drm_atomic_helper_commit_hw_done(state);
-
if (intel_state->modeset) {
/* As one of the primary mmio accessors, KMS has a high
 * likelihood of triggering bugs in unclaimed access. After we
@@ -13172,6 +13168,18 @@ static void intel_atomic_commit_tail(struct 
drm_atomic_state *state)
intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
}
+}
+
+static void intel_atomic_commit_tail(struct drm_atomic_state *state)
+{
+   struct drm_device *dev = state->dev;
+   struct drm_i915_private *dev_priv = to_i915(dev);
+
+   drm_atomic_helper_wait_for_dependencies(state);
+
+   __intel_atomic_commit_tail(state);
+
+   drm_atomic_helper_commit_hw_done(state);
 
mutex_lock(>struct_mutex);
drm_atomic_helper_cleanup_planes(dev, state);
-- 
2.13.0

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[Intel-gfx] [PATCH v3 21/22] drm/atomic: Introduce drm_atomic_helper_duplicate_commited_state()

[ville . syrjala]

From: Ville Syrjälä 

For i915 GPU reset handling we'll want to be able to duplicate the state
that was last commited to the hardware. For that purpose let's start to
track the commited state for each object and provide a way to duplicate
the commmited state into a new drm_atomic_state. The locking for
.commited_state must to be provided by the driver.

drm_atomic_helper_duplicate_commited_state() duplicates the state
to both old_state and new_state. For the purposes of i915 GPU reset we
would only need one of them, but we actually need two top level states;
one for disabling everything (which would need the duplicated state to
be old_state), and another to reenable everything (which would need the
duplicated state to be new_state). So to make it less comples I figured
I'd just always duplicate both. Might want to rethink this if for no
other reason that reducing the chances of memory allocation failure.
Due to the double state duplication we need
drm_atomic_helper_clean_commited_state() to clean up the duplicated
old_state since that's not handled by the normal drm_atomic_state
cleanup code.

TODO: do we want this in the helper, or maybe it should be just in i915?

v2: s/commited/committed/ everywhere (checkpatch)
Handle state duplication errors better
v3: Even more care in dealing with memory allocation errors
Handle private objs too
Deal with the potential ordering issues between swap_state()
and hw_done() by keeping track of which state was swapped in
last

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/drm_atomic.c|   1 +
 drivers/gpu/drm/drm_atomic_helper.c | 231 
 include/drm/drm_atomic.h|   4 +
 include/drm/drm_atomic_helper.h |   8 ++
 include/drm/drm_connector.h |  11 ++
 include/drm/drm_crtc.h  |  11 ++
 include/drm/drm_plane.h |  11 ++
 7 files changed, 277 insertions(+)

diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 56925b93f598..e1578d50d66f 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -1020,6 +1020,7 @@ drm_atomic_private_obj_init(struct drm_private_obj *obj,
memset(obj, 0, sizeof(*obj));
 
obj->state = state;
+   obj->committed_state = state;
obj->funcs = funcs;
 }
 EXPORT_SYMBOL(drm_atomic_private_obj_init);
diff --git a/drivers/gpu/drm/drm_atomic_helper.c 
b/drivers/gpu/drm/drm_atomic_helper.c
index f0887f231fb8..c3d02f12cd5d 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -1815,6 +1815,11 @@ void drm_atomic_helper_wait_for_dependencies(struct 
drm_atomic_state *old_state)
 }
 EXPORT_SYMBOL(drm_atomic_helper_wait_for_dependencies);
 
+static bool state_seqno_after(unsigned int a, unsigned int b)
+{
+   return (int)(b - a) < 0;
+}
+
 /**
  * drm_atomic_helper_commit_hw_done - setup possible nonblocking commit
  * @old_state: atomic state object with old state structures
@@ -1833,11 +1838,39 @@ EXPORT_SYMBOL(drm_atomic_helper_wait_for_dependencies);
 void drm_atomic_helper_commit_hw_done(struct drm_atomic_state *old_state)
 {
struct drm_crtc *crtc;
+   struct drm_plane *plane;
+   struct drm_connector *connector;
+   struct drm_private_obj *obj;
struct drm_crtc_state *new_crtc_state;
+   struct drm_plane_state *new_plane_state;
+   struct drm_connector_state *new_connector_state;
+   struct drm_private_state *new_obj_state;
struct drm_crtc_commit *commit;
int i;
+   static DEFINE_SPINLOCK(committed_state_lock);
+
+   spin_lock(_state_lock);
+
+   for_each_new_plane_in_state(old_state, plane, new_plane_state, i) {
+   if (plane->committed_state &&
+   state_seqno_after(new_plane_state->seqno,
+ plane->committed_state->seqno))
+   plane->committed_state = new_plane_state;
+   }
+
+   for_each_new_connector_in_state(old_state, connector, 
new_connector_state, i) {
+   if (connector->committed_state &&
+   state_seqno_after(new_connector_state->seqno,
+ connector->committed_state->seqno))
+   connector->committed_state = new_connector_state;
+   }
 
for_each_new_crtc_in_state(old_state, crtc, new_crtc_state, i) {
+   if (crtc->committed_state &&
+   state_seqno_after(new_crtc_state->seqno,
+ crtc->committed_state->seqno))
+   crtc->committed_state = new_crtc_state;
+
commit = old_state->crtcs[i].commit;
if (!commit)
continue;
@@ -1846,6 +1879,15 @@ void drm_atomic_helper_commit_hw_done(struct 
drm_atomic_state *old_state)
WARN_ON(new_crtc_state->event);

[Intel-gfx] [PATCH 17/22] drm/atomic: Fix up the kernel docs for the state duplication functions

[ville . syrjala]

From: Ville Syrjälä 

Coccinelle doesn't fix up the docs for us, so let's do it manually.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/drm_atomic_helper.c | 12 +---
 include/drm/drm_connector.h |  2 +-
 include/drm/drm_crtc.h  |  2 +-
 include/drm/drm_plane.h |  2 +-
 4 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/drm_atomic_helper.c 
b/drivers/gpu/drm/drm_atomic_helper.c
index c60fb6289276..f0887f231fb8 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -3368,7 +3368,8 @@ EXPORT_SYMBOL(drm_atomic_helper_crtc_reset);
 /**
  * __drm_atomic_helper_crtc_duplicate_state - copy atomic CRTC state
  * @crtc: CRTC object
- * @state: atomic CRTC state
+ * @state: new CRTC state
+ * @old_state: old CRTC state
  *
  * Copies atomic state from a CRTC's current state and resets inferred values.
  * This is useful for drivers that subclass the CRTC state.
@@ -3401,6 +3402,7 @@ EXPORT_SYMBOL(__drm_atomic_helper_crtc_duplicate_state);
 /**
  * drm_atomic_helper_crtc_duplicate_state - default state duplicate hook
  * @crtc: drm CRTC
+ * @old_state: old CRTC state
  *
  * Default CRTC state duplicate hook for drivers which don't have their own
  * subclassed CRTC state structure.
@@ -3481,7 +3483,8 @@ EXPORT_SYMBOL(drm_atomic_helper_plane_reset);
 /**
  * __drm_atomic_helper_plane_duplicate_state - copy atomic plane state
  * @plane: plane object
- * @state: atomic plane state
+ * @state: new plane state
+ * @old_state: old plane state
  *
  * Copies atomic state from a plane's current state. This is useful for
  * drivers that subclass the plane state.
@@ -3502,6 +3505,7 @@ EXPORT_SYMBOL(__drm_atomic_helper_plane_duplicate_state);
 /**
  * drm_atomic_helper_plane_duplicate_state - default state duplicate hook
  * @plane: drm plane
+ * @old_state: old plane state
  *
  * Default plane state duplicate hook for drivers which don't have their own
  * subclassed plane state structure.
@@ -3605,7 +3609,8 @@ EXPORT_SYMBOL(drm_atomic_helper_connector_reset);
 /**
  * __drm_atomic_helper_connector_duplicate_state - copy atomic connector state
  * @connector: connector object
- * @state: atomic connector state
+ * @state: new connector state
+ * @old_state: old connector state
  *
  * Copies atomic state from a connector's current state. This is useful for
  * drivers that subclass the connector state.
@@ -3624,6 +3629,7 @@ 
EXPORT_SYMBOL(__drm_atomic_helper_connector_duplicate_state);
 /**
  * drm_atomic_helper_connector_duplicate_state - default state duplicate hook
  * @connector: drm connector
+ * @old_state: old connector state
  *
  * Default connector state duplicate hook for drivers which don't have their 
own
  * subclassed connector state structure.
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index ee9a15a87db5..a0d862d23082 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -514,7 +514,7 @@ struct drm_connector_funcs {
/**
 * @atomic_duplicate_state:
 *
-* Duplicate the current atomic state for this connector and return it.
+* Duplicate the passed in atomic state for this connector and return 
it.
 * The core and helpers guarantee that any atomic state duplicated with
 * this hook and still owned by the caller (i.e. not transferred to the
 * driver by calling _mode_config_funcs.atomic_commit) will be
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 1d187331fe5d..8bfbc54660ab 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -497,7 +497,7 @@ struct drm_crtc_funcs {
/**
 * @atomic_duplicate_state:
 *
-* Duplicate the current atomic state for this CRTC and return it.
+* Duplicate the passed in atomic state for this CRTC and return it.
 * The core and helpers guarantee that any atomic state duplicated with
 * this hook and still owned by the caller (i.e. not transferred to the
 * driver by calling _mode_config_funcs.atomic_commit) will be
diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h
index f01023ed1c7b..08ad4b58adbe 100644
--- a/include/drm/drm_plane.h
+++ b/include/drm/drm_plane.h
@@ -249,7 +249,7 @@ struct drm_plane_funcs {
/**
 * @atomic_duplicate_state:
 *
-* Duplicate the current atomic state for this plane and return it.
+* Duplicate the passed in atomic state for this plane and return it.
 * The core and helpers guarantee that any atomic state duplicated with
 * this hook and still owned by the caller (i.e. not transferred to the
 * driver by calling _mode_config_funcs.atomic_commit) will be
-- 
2.13.0

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[Intel-gfx] [PATCH 19/22] drm/i915% Store vma gtt offset in plane state

[ville . syrjala]

From: Ville Syrjälä 

To avoid having to deference plane_state->vma during the commit phase of
plane updates, let's store the vma gtt offset (or the bus address when
we need it) in the plane state. This is crucial for doing the modeset
operations during GPU reset as as plane_state->vma gets cleared when we
duplicate the state and we won't be calling .prepare_fb() during GPU
reset plane commits.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_display.c | 38 +---
 drivers/gpu/drm/i915/intel_drv.h |  6 +-
 drivers/gpu/drm/i915/intel_sprite.c  |  8 
 3 files changed, 27 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 1016afebef27..0ff3f254ee58 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2744,7 +2744,7 @@ intel_find_initial_plane_obj(struct intel_crtc 
*intel_crtc,
if (!state->vma)
continue;
 
-   if (intel_plane_ggtt_offset(state) == plane_config->base) {
+   if (state->gtt_offset == plane_config->base) {
fb = c->primary->fb;
drm_framebuffer_reference(fb);
goto valid_fb;
@@ -2771,6 +2771,8 @@ intel_find_initial_plane_obj(struct intel_crtc 
*intel_crtc,
mutex_lock(>struct_mutex);
intel_state->vma =
intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
+   intel_state->gtt_offset = i915_ggtt_offset(intel_state->vma);
+
mutex_unlock(>struct_mutex);
if (IS_ERR(intel_state->vma)) {
DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
@@ -3122,19 +3124,16 @@ static void i9xx_update_primary_plane(struct 
intel_plane *primary,
I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
I915_WRITE_FW(DSPSURF(plane),
- intel_plane_ggtt_offset(plane_state) +
- crtc->dspaddr_offset);
+ plane_state->gtt_offset + crtc->dspaddr_offset);
I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
} else if (INTEL_GEN(dev_priv) >= 4) {
I915_WRITE_FW(DSPSURF(plane),
- intel_plane_ggtt_offset(plane_state) +
- crtc->dspaddr_offset);
+ plane_state->gtt_offset + crtc->dspaddr_offset);
I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
} else {
I915_WRITE_FW(DSPADDR(plane),
- intel_plane_ggtt_offset(plane_state) +
- crtc->dspaddr_offset);
+ plane_state->gtt_offset + crtc->dspaddr_offset);
}
POSTING_READ_FW(reg);
 
@@ -3395,7 +3394,7 @@ static void skylake_update_primary_plane(struct 
intel_plane *plane,
}
 
I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
- intel_plane_ggtt_offset(plane_state) + surf_addr);
+ plane_state->gtt_offset + surf_addr);
 
POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
 
@@ -9202,15 +9201,9 @@ static u32 intel_cursor_base(const struct 
intel_plane_state *plane_state)
struct drm_i915_private *dev_priv =
to_i915(plane_state->base.plane->dev);
const struct drm_framebuffer *fb = plane_state->base.fb;
-   const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
u32 base;
 
-   if (INTEL_INFO(dev_priv)->cursor_needs_physical)
-   base = obj->phys_handle->busaddr;
-   else
-   base = intel_plane_ggtt_offset(plane_state);
-
-   base += plane_state->main.offset;
+   base = plane_state->gtt_offset + plane_state->main.offset;
 
/* ILK+ do this automagically */
if (HAS_GMCH_DISPLAY(dev_priv) &&
@@ -10863,8 +10856,11 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
 
work->old_vma = to_intel_plane_state(primary->state)->vma;
to_intel_plane_state(primary->state)->vma = vma;
+   to_intel_plane_state(primary->state)->gtt_offset =
+   i915_ggtt_offset(vma);
 
-   work->gtt_offset = i915_ggtt_offset(vma) + intel_crtc->dspaddr_offset;
+   work->gtt_offset = to_intel_plane_state(primary->state)->gtt_offset +
+   intel_crtc->dspaddr_offset;
work->rotation = crtc->primary->state->rotation;
 
/*
@@ -10920,6 +10916,8 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
i915_add_request(request);
 cleanup_unpin:
to_intel_plane_state(primary->state)->vma = work->old_vma;
+   to_intel_plane_state(primary->state)->gtt_offset =
+   

[Intel-gfx] [PATCH v5 22/22] drm/i915: Solve the GPU reset vs. modeset deadlocks with an rw_semaphore

[ville . syrjala]

From: Ville Syrjälä 

Introduce an rw_semaphore to protect the display commits. All normal
commits use down_read() and hence can proceed in parallel, but GPU reset
will use down_write() making sure no other commits are in progress when
we have to pull the plug on the display engine on pre-g4x platforms.
There are no modeset/gem locks taken inside __intel_atomic_commit_tail()
itself, and we wait for all dependencies before the down_read(), and
thus there is no chance of deadlocks with this scheme.

During reset we will recommit the state that was commited last. Hence we
require tracking which state that was, and we need a way to duplicate
that state. That is now handled by the atomic core and helpers. We also
have to be sure that none of the commit codepaths look up
plane->state, crtc->state, etc. as that would lead us to pontetially
commit some future state prematurely. crtc->config is actually fine
since that gets update during the commit as well (although eventually
we do want to rid ourselves of crtc->config).

I left out the state readout from the post-reset display
reinitialization as that still likes to clobber crtc->state etc.
If we make it use a free standing atomic state and mke sure it doesn't
need any locks we could reintroduce it. For now I just mark the
post-reset display state as dirty as possible to make sure we
reinitialize everything.

One potential issue remains in the form of display detection. Either
we need to protect that with the same rw_semaphore as well, or perhaps
it would be enough to force gmbus into bitbanging mode while the reset
is happening and we don't have interrupts, and just across the actual
hardware GPU reset we could hold the gmbus mutex.

v2: Keep intel_prepare/finish_reset() outside struct_mutex (Chris)
v3: Drop all the committed_state refactoring to make this less
obnoxious to backport (Daniel)
v4: Preserve the wedge timeout mechanism (Chris)
v5: Go back to the full committed state tracking since it actually
is needed

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_drv.h  |   2 +
 drivers/gpu/drm/i915/intel_display.c | 220 ---
 drivers/gpu/drm/i915/intel_sprite.c  |   1 +
 3 files changed, 157 insertions(+), 66 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index baec61b078f5..432b356017ba 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2247,6 +2247,8 @@ struct drm_i915_private {
struct drm_atomic_state *modeset_restore_state;
struct drm_modeset_acquire_ctx reset_ctx;
 
+   struct rw_semaphore commit_sem;
+
struct list_head vm_list; /* Global list of all address spaces */
struct i915_ggtt ggtt; /* VM representing the global address space */
 
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index e9c85d7cbb3e..e8ff5095ede3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -123,6 +123,7 @@ static void ironlake_pfit_enable(struct intel_crtc *crtc);
 static void intel_modeset_setup_hw_state(struct drm_device *dev,
 struct drm_modeset_acquire_ctx *ctx);
 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
+static void __intel_atomic_commit_tail(struct drm_atomic_state *state, bool 
is_reset);
 
 struct intel_limit {
struct {
@@ -3432,15 +3433,15 @@ static void intel_update_primary_planes(struct 
drm_device *dev)
 
for_each_crtc(dev, crtc) {
struct intel_plane *plane = to_intel_plane(crtc->primary);
-   struct intel_plane_state *plane_state =
-   to_intel_plane_state(plane->base.state);
+   const struct intel_plane_state *plane_state =
+   to_intel_plane_state(plane->base.committed_state);
 
if (plane_state->base.visible) {
trace_intel_update_plane(>base,
 to_intel_crtc(crtc));
 
plane->update_plane(plane,
-   to_intel_crtc_state(crtc->state),
+   
to_intel_crtc_state(crtc->committed_state),
plane_state);
}
}
@@ -3491,27 +3492,97 @@ static bool gpu_reset_clobbers_display(struct 
drm_i915_private *dev_priv)
INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
 }
 
-void intel_prepare_reset(struct drm_i915_private *dev_priv)
+static void init_intel_state(struct intel_atomic_state *state)
+{
+   struct drm_crtc *crtc;
+   struct drm_crtc_state *old_crtc_state, *new_crtc_state;
+   int i;
+
+   state->modeset = true;
+
+   for_each_oldnew_crtc_in_state(>base, crtc, old_crtc_state, 
new_crtc_state, i) {
+ 

[Intel-gfx] [PATCH 18/22] drm: Return the connector from drm_connector_get()

[ville . syrjala]

From: Ville Syrjälä 

Make drm_connector_get() return the connector. This allows the nice
pattern of 'foo->connector = drm_connector_get(connector)'

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/drm_atomic.c| 3 +--
 drivers/gpu/drm/drm_fb_helper.c | 7 +++
 include/drm/drm_connector.h | 7 ++-
 3 files changed, 10 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index b1983e7b65d2..56925b93f598 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -1139,11 +1139,10 @@ drm_atomic_get_connector_state(struct drm_atomic_state 
*state,
if (!connector_state)
return ERR_PTR(-ENOMEM);
 
-   drm_connector_get(connector);
c->state = connector_state;
c->old_state = connector->state;
c->new_state = connector_state;
-   c->ptr = connector;
+   c->ptr = drm_connector_get(connector);
connector_state->state = state;
 
state->num_connector = state->connectors.num_elems;
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 721511da4de6..f520c235a6fb 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -138,8 +138,7 @@ static int __drm_fb_helper_add_one_connector(struct 
drm_fb_helper *fb_helper,
if (!fb_conn)
return -ENOMEM;
 
-   drm_connector_get(connector);
-   fb_conn->connector = connector;
+   fb_conn->connector = drm_connector_get(connector);
fb_helper->connector_info[fb_helper->connector_count++] = fb_conn;
 
return 0;
@@ -2338,8 +2337,8 @@ static void drm_setup_crtcs(struct drm_fb_helper 
*fb_helper,
fb_crtc->y = offset->y;
modeset->mode = drm_mode_duplicate(dev,
   
fb_crtc->desired_mode);
-   drm_connector_get(connector);
-   modeset->connectors[modeset->num_connectors++] = 
connector;
+   modeset->connectors[modeset->num_connectors++] =
+   drm_connector_get(connector);
modeset->fb = fb_helper->fb;
modeset->x = offset->x;
modeset->y = offset->y;
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index a0d862d23082..8f26166f78b4 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -916,10 +916,15 @@ static inline struct drm_connector 
*drm_connector_lookup(struct drm_device *dev,
  * @connector: DRM connector
  *
  * This function increments the connector's refcount.
+
+ * Returns:
+ *
+ * The connector.
  */
-static inline void drm_connector_get(struct drm_connector *connector)
+static inline struct drm_connector *drm_connector_get(struct drm_connector 
*connector)
 {
drm_mode_object_get(>base);
+   return connector;
 }
 
 /**
-- 
2.13.0

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[Intel-gfx] [PATCH 14/22] drm/arm: s/old_state/old_mali_state/

[ville . syrjala]

From: Ville Syrjälä 

Rename the local 'old_state' variable to 'old_mali_state' to get it
out of the way of some cocci refactoring.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/arm/malidp_crtc.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/arm/malidp_crtc.c 
b/drivers/gpu/drm/arm/malidp_crtc.c
index 037514f42a83..2a92cb066bea 100644
--- a/drivers/gpu/drm/arm/malidp_crtc.c
+++ b/drivers/gpu/drm/arm/malidp_crtc.c
@@ -417,23 +417,23 @@ static const struct drm_crtc_helper_funcs 
malidp_crtc_helper_funcs = {
 
 static struct drm_crtc_state *malidp_crtc_duplicate_state(struct drm_crtc 
*crtc)
 {
-   struct malidp_crtc_state *state, *old_state;
+   struct malidp_crtc_state *state, *old_mali_state;
 
if (WARN_ON(!crtc->state))
return NULL;
 
-   old_state = to_malidp_crtc_state(crtc->state);
+   old_mali_state = to_malidp_crtc_state(crtc->state);
state = kmalloc(sizeof(*state), GFP_KERNEL);
if (!state)
return NULL;
 
__drm_atomic_helper_crtc_duplicate_state(crtc, >base,
 crtc->state);
-   memcpy(state->gamma_coeffs, old_state->gamma_coeffs,
+   memcpy(state->gamma_coeffs, old_mali_state->gamma_coeffs,
   sizeof(state->gamma_coeffs));
-   memcpy(state->coloradj_coeffs, old_state->coloradj_coeffs,
+   memcpy(state->coloradj_coeffs, old_mali_state->coloradj_coeffs,
   sizeof(state->coloradj_coeffs));
-   memcpy(>scaler_config, _state->scaler_config,
+   memcpy(>scaler_config, _mali_state->scaler_config,
   sizeof(state->scaler_config));
state->scaled_planes_mask = 0;
 
-- 
2.13.0

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[Intel-gfx] [PATCH 12/22] drm/atomic: Make private objs proper objects

[ville . syrjala]

From: Ville Syrjälä 

Make the atomic private object stuff less special by introducing proper
base classes for the object and its state. Drivers can embed these in
their own appropriate objects, after which these things will work
exactly like the plane/crtc/connector states during atomic operations.

Cc: Dhinakaran Pandiyan 
Reviewed-by: Daniel Vetter 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/drm_atomic.c  |  78 +++--
 drivers/gpu/drm/drm_atomic_helper.c   |  30 +++--
 drivers/gpu/drm/drm_dp_mst_topology.c |  63 +
 include/drm/drm_atomic.h  | 123 +-
 include/drm/drm_atomic_helper.h   |   4 ++
 include/drm/drm_dp_mst_helper.h   |  10 +++
 6 files changed, 206 insertions(+), 102 deletions(-)

diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 5eb14c73c0fb..da7752230e4c 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -197,12 +197,14 @@ void drm_atomic_state_default_clear(struct 
drm_atomic_state *state)
for (i = 0; i < state->num_private_objs; i++) {
struct __drm_private_objs_state *p =
__drm_atomic_state_private_obj(state, i);
-   void *obj_state = p->obj_state;
+   struct drm_private_obj *obj = p->ptr;
 
-   p->funcs->destroy_state(obj_state);
-   p->obj = NULL;
-   p->obj_state = NULL;
-   p->funcs = NULL;
+   if (WARN_ON(!obj))
+   continue;
+
+   obj->funcs->atomic_destroy_state(obj, p->state);
+   p->ptr = NULL;
+   p->state = NULL;
}
state->num_private_objs = 0;
 
@@ -1000,11 +1002,44 @@ static void drm_atomic_plane_print_state(struct 
drm_printer *p,
 }
 
 /**
+ * drm_atomic_private_obj_init - initialize private object
+ * @obj: private object
+ * @state: initial private object state
+ * @funcs: pointer to the struct of function pointers that identify the object
+ * type
+ *
+ * Initialize the private object, which can be embedded into any
+ * driver private object that needs its own atomic state.
+ */
+void
+drm_atomic_private_obj_init(struct drm_private_obj *obj,
+   struct drm_private_state *state,
+   const struct drm_private_state_funcs *funcs)
+{
+   memset(obj, 0, sizeof(*obj));
+
+   obj->state = state;
+   obj->funcs = funcs;
+}
+EXPORT_SYMBOL(drm_atomic_private_obj_init);
+
+/**
+ * drm_atomic_private_obj_fini - finalize private object
+ * @obj: private object
+ *
+ * Finalize the private object.
+ */
+void
+drm_atomic_private_obj_fini(struct drm_private_obj *obj)
+{
+   obj->funcs->atomic_destroy_state(obj, obj->state);
+}
+EXPORT_SYMBOL(drm_atomic_private_obj_fini);
+
+/**
  * drm_atomic_get_private_obj_state - get private object state
  * @state: global atomic state
  * @obj: private object to get the state for
- * @funcs: pointer to the struct of function pointers that identify the object
- * type
  *
  * This function returns the private object state for the given private object,
  * allocating the state if needed. It does not grab any locks as the caller is
@@ -1014,19 +1049,21 @@ static void drm_atomic_plane_print_state(struct 
drm_printer *p,
  *
  * Either the allocated state or the error code encoded into a pointer.
  */
-void *
-drm_atomic_get_private_obj_state(struct drm_atomic_state *state, void *obj,
- const struct drm_private_state_funcs *funcs)
+struct drm_private_state *
+drm_atomic_get_private_obj_state(struct drm_atomic_state *state,
+struct drm_private_obj *obj)
 {
+   const struct drm_private_state_funcs *funcs = obj->funcs;
struct __drm_private_objs_state *p;
+   struct drm_private_state *obj_state;
int index = state->num_private_objs;
int ret, i;
 
for (i = 0; i < state->num_private_objs; i++) {
p = __drm_atomic_state_private_obj(state, i);
 
-   if (obj == p->obj)
-   return p->obj_state;
+   if (obj == p->ptr)
+   return p->state;
}
 
ret = drm_dynarray_reserve(>private_objs, index);
@@ -1035,19 +1072,22 @@ drm_atomic_get_private_obj_state(struct 
drm_atomic_state *state, void *obj,
 
p = __drm_atomic_state_private_obj(state, index);
 
-   p->obj_state = funcs->duplicate_state(state, obj);
-   if (!p->obj_state)
+   obj_state = funcs->atomic_duplicate_state(obj);
+   if (!obj_state)
return ERR_PTR(-ENOMEM);
 
-   p->obj = obj;
-   p->funcs = funcs;
+   p->state = obj_state;
+   p->old_state = obj->state;
+   p->new_state = obj_state;
+   p->ptr = obj;
+   

[Intel-gfx] [PATCH 15/22] drm/mediatek: s/old_state/old_mtk_state/

[ville . syrjala]

From: Ville Syrjälä 

Rename the local 'old_state' variable to 'old_mtk_state' to get it
out of the way of some cocci refactoring.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/mediatek/mtk_drm_plane.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.c 
b/drivers/gpu/drm/mediatek/mtk_drm_plane.c
index 9ecc23f67cc7..67c7bd17e350 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_plane.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.c
@@ -52,7 +52,7 @@ static void mtk_plane_reset(struct drm_plane *plane)
 
 static struct drm_plane_state *mtk_plane_duplicate_state(struct drm_plane 
*plane)
 {
-   struct mtk_plane_state *old_state = to_mtk_plane_state(plane->state);
+   struct mtk_plane_state *old_mtk_state = 
to_mtk_plane_state(plane->state);
struct mtk_plane_state *state;
 
state = kzalloc(sizeof(*state), GFP_KERNEL);
@@ -64,7 +64,7 @@ static struct drm_plane_state 
*mtk_plane_duplicate_state(struct drm_plane *plane
 
WARN_ON(state->base.plane != plane);
 
-   state->pending = old_state->pending;
+   state->pending = old_mtk_state->pending;
 
return >base;
 }
-- 
2.13.0

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[Intel-gfx] [PATCH 16/22] drm/atomic: Pass old state explicitly to .atomic_duplicate_state()

[ville . syrjala]

From: Ville Syrjälä 

We'll be wanting to duplicate other states besides the one pointed to
by crtc->state & co., so pass the duplicated state in explicitly.

I wanted to make the old_state const, but that would have results in
tons of new warnings because some drivers have their to_foo_state()s
as static inlines. So I decided to leave old_state as non-const in
the end.

@r@
identifier F =~ "^[^_].*duplicate_.*state$";
identifier I;
type TO, TS;
@@
TS F(TO I
+   ,TS old_state
)
{
<...
- I->state
+ old_state
...>
}

@@
identifier r.F;
expression E;
@@
F(E
+ ,E->state
  )

@@
type r.TO;
type r.TS;
type TF;
identifier I;
@@
TF {
...
TS (*atomic_duplicate_state)(TO I
+,TS old_state
 );
...
};

@@
expression X, E;
@@
X->atomic_duplicate_state(E
+ ,E->state
  )

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/arm/malidp_crtc.c   |  9 +
 drivers/gpu/drm/arm/malidp_planes.c |  9 +
 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c  |  9 +
 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c |  5 +++--
 drivers/gpu/drm/drm_atomic.c| 10 ++
 drivers/gpu/drm/drm_atomic_helper.c | 21 -
 drivers/gpu/drm/drm_crtc_helper.c   | 12 
 drivers/gpu/drm/drm_dp_mst_topology.c   |  7 ---
 drivers/gpu/drm/drm_plane_helper.c  | 12 
 drivers/gpu/drm/exynos/exynos_drm_plane.c   |  7 ---
 drivers/gpu/drm/i915/intel_atomic.c | 14 --
 drivers/gpu/drm/i915/intel_atomic_plane.c   |  7 ---
 drivers/gpu/drm/i915/intel_display.c|  2 +-
 drivers/gpu/drm/i915/intel_drv.h|  9 ++---
 drivers/gpu/drm/i915/intel_sdvo.c   |  7 ---
 drivers/gpu/drm/imx/ipuv3-crtc.c|  5 +++--
 drivers/gpu/drm/imx/ipuv3-plane.c   |  7 ---
 drivers/gpu/drm/mediatek/mtk_drm_crtc.c |  5 +++--
 drivers/gpu/drm/mediatek/mtk_drm_plane.c|  7 ---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c|  9 +
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c   | 13 +++--
 drivers/gpu/drm/nouveau/nouveau_connector.c |  7 ---
 drivers/gpu/drm/nouveau/nouveau_connector.h |  3 ++-
 drivers/gpu/drm/nouveau/nv50_display.c  | 14 --
 drivers/gpu/drm/rcar-du/rcar_du_plane.c |  9 +
 drivers/gpu/drm/rcar-du/rcar_du_vsp.c   |  9 +
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c |  5 +++--
 drivers/gpu/drm/tegra/dc.c  | 14 --
 drivers/gpu/drm/tegra/dsi.c |  7 ---
 drivers/gpu/drm/tegra/sor.c |  7 ---
 drivers/gpu/drm/vc4/vc4_crtc.c  |  5 +++--
 drivers/gpu/drm/vc4/vc4_plane.c |  9 +
 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c | 25 ++---
 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h |  9 ++---
 include/drm/drm_atomic.h|  3 ++-
 include/drm/drm_atomic_helper.h |  9 ++---
 include/drm/drm_connector.h |  3 ++-
 include/drm/drm_crtc.h  |  3 ++-
 include/drm/drm_plane.h |  3 ++-
 39 files changed, 194 insertions(+), 136 deletions(-)

diff --git a/drivers/gpu/drm/arm/malidp_crtc.c 
b/drivers/gpu/drm/arm/malidp_crtc.c
index 2a92cb066bea..8c78cb13b23b 100644
--- a/drivers/gpu/drm/arm/malidp_crtc.c
+++ b/drivers/gpu/drm/arm/malidp_crtc.c
@@ -415,20 +415,21 @@ static const struct drm_crtc_helper_funcs 
malidp_crtc_helper_funcs = {
.atomic_disable = malidp_crtc_atomic_disable,
 };
 
-static struct drm_crtc_state *malidp_crtc_duplicate_state(struct drm_crtc 
*crtc)
+static struct drm_crtc_state *malidp_crtc_duplicate_state(struct drm_crtc 
*crtc,
+ struct drm_crtc_state 
*old_state)
 {
struct malidp_crtc_state *state, *old_mali_state;
 
-   if (WARN_ON(!crtc->state))
+   if (WARN_ON(!old_state))
return NULL;
 
-   old_mali_state = to_malidp_crtc_state(crtc->state);
+   old_mali_state = to_malidp_crtc_state(old_state);
state = kmalloc(sizeof(*state), GFP_KERNEL);
if (!state)
return NULL;
 
__drm_atomic_helper_crtc_duplicate_state(crtc, >base,
-crtc->state);
+old_state);
memcpy(state->gamma_coeffs, old_mali_state->gamma_coeffs,
   sizeof(state->gamma_coeffs));
memcpy(state->coloradj_coeffs, old_mali_state->coloradj_coeffs,
diff --git a/drivers/gpu/drm/arm/malidp_planes.c 
b/drivers/gpu/drm/arm/malidp_planes.c
index fe744396bc99..33b0c07ad3a3 

[Intel-gfx] [PATCH 11/22] drm/atomic: Convert private_objs to drm_dynarray

[ville . syrjala]

From: Ville Syrjälä 

state->private_objs grows dynamically, so switch it over to use
the new drm_dynarray helper.

Cc: Dhinakaran Pandiyan 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/drm_atomic.c| 64 -
 drivers/gpu/drm/drm_atomic_helper.c |  2 +-
 include/drm/drm_atomic.h| 15 ++---
 3 files changed, 46 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index a61e396b11a8..5eb14c73c0fb 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -57,7 +57,7 @@ void drm_atomic_state_default_release(struct drm_atomic_state 
*state)
drm_dynarray_fini(>connectors);
kfree(state->crtcs);
kfree(state->planes);
-   kfree(state->private_objs);
+   drm_dynarray_fini(>private_objs);
 }
 EXPORT_SYMBOL(drm_atomic_state_default_release);
 
@@ -90,6 +90,8 @@ drm_atomic_state_init(struct drm_device *dev, struct 
drm_atomic_state *state)
 
drm_dynarray_init(>connectors,
  sizeof(struct __drm_connectors_state));
+   drm_dynarray_init(>private_objs,
+ sizeof(struct __drm_private_objs_state));
 
state->dev = dev;
 
@@ -193,12 +195,14 @@ void drm_atomic_state_default_clear(struct 
drm_atomic_state *state)
}
 
for (i = 0; i < state->num_private_objs; i++) {
-   void *obj_state = state->private_objs[i].obj_state;
-
-   state->private_objs[i].funcs->destroy_state(obj_state);
-   state->private_objs[i].obj = NULL;
-   state->private_objs[i].obj_state = NULL;
-   state->private_objs[i].funcs = NULL;
+   struct __drm_private_objs_state *p =
+   __drm_atomic_state_private_obj(state, i);
+   void *obj_state = p->obj_state;
+
+   p->funcs->destroy_state(obj_state);
+   p->obj = NULL;
+   p->obj_state = NULL;
+   p->funcs = NULL;
}
state->num_private_objs = 0;
 
@@ -1014,36 +1018,36 @@ void *
 drm_atomic_get_private_obj_state(struct drm_atomic_state *state, void *obj,
  const struct drm_private_state_funcs *funcs)
 {
-   int index, num_objs, i;
-   size_t size;
-   struct __drm_private_objs_state *arr;
-
-   for (i = 0; i < state->num_private_objs; i++)
-   if (obj == state->private_objs[i].obj)
-   return state->private_objs[i].obj_state;
-
-   num_objs = state->num_private_objs + 1;
-   size = sizeof(*state->private_objs) * num_objs;
-   arr = krealloc(state->private_objs, size, GFP_KERNEL);
-   if (!arr)
-   return ERR_PTR(-ENOMEM);
+   struct __drm_private_objs_state *p;
+   int index = state->num_private_objs;
+   int ret, i;
+
+   for (i = 0; i < state->num_private_objs; i++) {
+   p = __drm_atomic_state_private_obj(state, i);
+
+   if (obj == p->obj)
+   return p->obj_state;
+   }
 
-   state->private_objs = arr;
-   index = state->num_private_objs;
-   memset(>private_objs[index], 0, sizeof(*state->private_objs));
+   ret = drm_dynarray_reserve(>private_objs, index);
+   if (ret)
+   return ERR_PTR(ret);
 
-   state->private_objs[index].obj_state = funcs->duplicate_state(state, 
obj);
-   if (!state->private_objs[index].obj_state)
+   p = __drm_atomic_state_private_obj(state, index);
+
+   p->obj_state = funcs->duplicate_state(state, obj);
+   if (!p->obj_state)
return ERR_PTR(-ENOMEM);
 
-   state->private_objs[index].obj = obj;
-   state->private_objs[index].funcs = funcs;
-   state->num_private_objs = num_objs;
+   p->obj = obj;
+   p->funcs = funcs;
+
+   state->num_private_objs = index + 1;
 
DRM_DEBUG_ATOMIC("Added new private object state %p to %p\n",
-state->private_objs[index].obj_state, state);
+p->obj_state, state);
 
-   return state->private_objs[index].obj_state;
+   return p->obj_state;
 }
 EXPORT_SYMBOL(drm_atomic_get_private_obj_state);
 
diff --git a/drivers/gpu/drm/drm_atomic_helper.c 
b/drivers/gpu/drm/drm_atomic_helper.c
index 2d747ac35ecf..77b57cdf0460 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -2331,7 +2331,7 @@ void drm_atomic_helper_swap_state(struct drm_atomic_state 
*state,
}
 
__for_each_private_obj(state, obj, obj_state, i, funcs)
-   funcs->swap_state(obj, >private_objs[i].obj_state);
+   funcs->swap_state(obj, &__drm_atomic_state_private_obj(state, 
i)->obj_state);
 }
 EXPORT_SYMBOL(drm_atomic_helper_swap_state);
 
diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h

[Intel-gfx] [PATCH 13/22] drm/atomic: Pass old state to __drm_atomic_helper_crtc_duplicate_state() & co. explicitly

[ville . syrjala]

From: Ville Syrjälä 

We'll be wanting to duplicate other states besides the one pointed to
by crtc->state & co., so pass the duplicated state in explicitly.

@r@
identifier F =~ "^__drm_atomic_helper_.*_duplicate_state$";
identifier O, S;
type T, TS;
@@
F(T O, TS *S
+ ,const TS *old_state
  )
{
<...
- O->state
+ old_state
...>
}

@@
identifier r.F;
expression E;
@@
F(E, ...
+ ,E->state
  )

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/arm/malidp_crtc.c  |  3 ++-
 drivers/gpu/drm/arm/malidp_planes.c|  3 ++-
 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c |  3 ++-
 drivers/gpu/drm/drm_atomic_helper.c| 30 --
 drivers/gpu/drm/drm_dp_mst_topology.c  |  3 ++-
 drivers/gpu/drm/exynos/exynos_drm_plane.c  |  3 ++-
 drivers/gpu/drm/i915/intel_atomic.c|  6 --
 drivers/gpu/drm/i915/intel_atomic_plane.c  |  2 +-
 drivers/gpu/drm/i915/intel_sdvo.c  |  4 +++-
 drivers/gpu/drm/imx/ipuv3-crtc.c   |  3 ++-
 drivers/gpu/drm/imx/ipuv3-plane.c  |  3 ++-
 drivers/gpu/drm/mediatek/mtk_drm_crtc.c|  3 ++-
 drivers/gpu/drm/mediatek/mtk_drm_plane.c   |  3 ++-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c   |  3 ++-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c  |  3 ++-
 drivers/gpu/drm/nouveau/nouveau_connector.c|  3 ++-
 drivers/gpu/drm/nouveau/nv50_display.c |  6 --
 drivers/gpu/drm/rcar-du/rcar_du_plane.c|  3 ++-
 drivers/gpu/drm/rcar-du/rcar_du_vsp.c  |  3 ++-
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c|  3 ++-
 drivers/gpu/drm/tegra/dc.c |  6 --
 drivers/gpu/drm/tegra/dsi.c|  3 ++-
 drivers/gpu/drm/tegra/sor.c|  3 ++-
 drivers/gpu/drm/vc4/vc4_crtc.c |  3 ++-
 drivers/gpu/drm/vc4/vc4_plane.c|  3 ++-
 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c|  7 +++---
 include/drm/drm_atomic_helper.h| 12 +++
 27 files changed, 85 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/arm/malidp_crtc.c 
b/drivers/gpu/drm/arm/malidp_crtc.c
index 3615d18a7ddf..037514f42a83 100644
--- a/drivers/gpu/drm/arm/malidp_crtc.c
+++ b/drivers/gpu/drm/arm/malidp_crtc.c
@@ -427,7 +427,8 @@ static struct drm_crtc_state 
*malidp_crtc_duplicate_state(struct drm_crtc *crtc)
if (!state)
return NULL;
 
-   __drm_atomic_helper_crtc_duplicate_state(crtc, >base);
+   __drm_atomic_helper_crtc_duplicate_state(crtc, >base,
+crtc->state);
memcpy(state->gamma_coeffs, old_state->gamma_coeffs,
   sizeof(state->gamma_coeffs));
memcpy(state->coloradj_coeffs, old_state->coloradj_coeffs,
diff --git a/drivers/gpu/drm/arm/malidp_planes.c 
b/drivers/gpu/drm/arm/malidp_planes.c
index 600fa7bd7f52..fe744396bc99 100644
--- a/drivers/gpu/drm/arm/malidp_planes.c
+++ b/drivers/gpu/drm/arm/malidp_planes.c
@@ -98,7 +98,8 @@ drm_plane_state *malidp_duplicate_plane_state(struct 
drm_plane *plane)
return NULL;
 
m_state = to_malidp_plane_state(plane->state);
-   __drm_atomic_helper_plane_duplicate_state(plane, >base);
+   __drm_atomic_helper_plane_duplicate_state(plane, >base,
+ plane->state);
state->rotmem_size = m_state->rotmem_size;
state->format = m_state->format;
state->n_planes = m_state->n_planes;
diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c 
b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
index 441769c5bcd4..bb7c5eb9526a 100644
--- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
+++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
@@ -385,7 +385,8 @@ atmel_hlcdc_crtc_duplicate_state(struct drm_crtc *crtc)
state = kmalloc(sizeof(*state), GFP_KERNEL);
if (!state)
return NULL;
-   __drm_atomic_helper_crtc_duplicate_state(crtc, >base);
+   __drm_atomic_helper_crtc_duplicate_state(crtc, >base,
+crtc->state);
 
cur = drm_crtc_state_to_atmel_hlcdc_crtc_state(crtc->state);
state->output_mode = cur->output_mode;
diff --git a/drivers/gpu/drm/drm_atomic_helper.c 
b/drivers/gpu/drm/drm_atomic_helper.c
index bc7d3a5a50f7..0745a08a6cc2 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -3374,9 +3374,10 @@ EXPORT_SYMBOL(drm_atomic_helper_crtc_reset);
  * This is useful for drivers that subclass the CRTC state.
  */
 void __drm_atomic_helper_crtc_duplicate_state(struct drm_crtc *crtc,
- struct drm_crtc_state *state)
+ struct drm_crtc_state *state,
+ const struct drm_crtc_state 
*old_state)
 {
-   memcpy(state, crtc->state, 

[Intel-gfx] [PATCH 09/22] drm/atomic: Convert state->connectors to drm_dynarray

[ville . syrjala]

From: Ville Syrjälä 

state->connectors[] can grows dynamically, so we can switch over to
using the new drm_dynarray.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/drm_atomic.c| 49 +++--
 drivers/gpu/drm/drm_atomic_helper.c |  4 +--
 include/drm/drm_atomic.h| 42 ++-
 3 files changed, 52 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 09ca662fcd35..1663ec3626a1 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -28,6 +28,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -53,7 +54,7 @@ EXPORT_SYMBOL(__drm_crtc_commit_free);
  */
 void drm_atomic_state_default_release(struct drm_atomic_state *state)
 {
-   kfree(state->connectors);
+   drm_dynarray_fini(>connectors);
kfree(state->crtcs);
kfree(state->planes);
kfree(state->private_objs);
@@ -87,6 +88,9 @@ drm_atomic_state_init(struct drm_device *dev, struct 
drm_atomic_state *state)
if (!state->planes)
goto fail;
 
+   drm_dynarray_init(>connectors,
+ sizeof(struct __drm_connectors_state));
+
state->dev = dev;
 
DRM_DEBUG_ATOMIC("Allocated atomic state %p\n", state);
@@ -142,15 +146,17 @@ void drm_atomic_state_default_clear(struct 
drm_atomic_state *state)
DRM_DEBUG_ATOMIC("Clearing atomic state %p\n", state);
 
for (i = 0; i < state->num_connector; i++) {
-   struct drm_connector *connector = state->connectors[i].ptr;
+   struct __drm_connectors_state *c =
+   __drm_atomic_state_connector(state, i);
+   struct drm_connector *connector = c->ptr;
 
if (!connector)
continue;
 
connector->funcs->atomic_destroy_state(connector,
-  
state->connectors[i].state);
-   state->connectors[i].ptr = NULL;
-   state->connectors[i].state = NULL;
+  c->state);
+   c->ptr = NULL;
+   c->state = NULL;
drm_connector_put(connector);
}
 
@@ -1064,6 +1070,7 @@ drm_atomic_get_connector_state(struct drm_atomic_state 
*state,
int ret, index;
struct drm_mode_config *config = >dev->mode_config;
struct drm_connector_state *connector_state;
+   struct __drm_connectors_state *c;
 
WARN_ON(!state->acquire_ctx);
 
@@ -1073,35 +1080,29 @@ drm_atomic_get_connector_state(struct drm_atomic_state 
*state,
 
index = drm_connector_index(connector);
 
-   if (index >= state->num_connector) {
-   struct __drm_connnectors_state *c;
-   int alloc = max(index + 1, config->num_connector);
-
-   c = krealloc(state->connectors, alloc * 
sizeof(*state->connectors), GFP_KERNEL);
-   if (!c)
-   return ERR_PTR(-ENOMEM);
-
-   state->connectors = c;
-   memset(>connectors[state->num_connector], 0,
-  sizeof(*state->connectors) * (alloc - 
state->num_connector));
+   ret = drm_dynarray_reserve(>connectors,
+  max(index, config->num_connector - 1));
+   if (ret)
+   return ERR_PTR(ret);
 
-   state->num_connector = alloc;
-   }
+   c = __drm_atomic_state_connector(state, index);
 
-   if (state->connectors[index].state)
-   return state->connectors[index].state;
+   if (c->state)
+   return c->state;
 
connector_state = connector->funcs->atomic_duplicate_state(connector);
if (!connector_state)
return ERR_PTR(-ENOMEM);
 
drm_connector_get(connector);
-   state->connectors[index].state = connector_state;
-   state->connectors[index].old_state = connector->state;
-   state->connectors[index].new_state = connector_state;
-   state->connectors[index].ptr = connector;
+   c->state = connector_state;
+   c->old_state = connector->state;
+   c->new_state = connector_state;
+   c->ptr = connector;
connector_state->state = state;
 
+   state->num_connector = state->connectors.num_elems;
+
DRM_DEBUG_ATOMIC("Added [CONNECTOR:%d:%s] %p state to %p\n",
 connector->base.id, connector->name,
 connector_state, state);
diff --git a/drivers/gpu/drm/drm_atomic_helper.c 
b/drivers/gpu/drm/drm_atomic_helper.c
index 667ec97d4efb..2d747ac35ecf 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -2297,7 +2297,7 @@ void drm_atomic_helper_swap_state(struct drm_atomic_state 
*state,
old_conn_state->state = state;

[Intel-gfx] [PATCH 10/22] drm/atomic: Remove pointless private object NULL state check

[ville . syrjala]

From: Ville Syrjälä 

We will never add private objects with a NULL state into the atomic
state, hence checking for that is pointless.

Cc: Dhinakaran Pandiyan 
Reviewed-by: Daniel Vetter 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/drm_atomic.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 1663ec3626a1..a61e396b11a8 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -1019,8 +1019,7 @@ drm_atomic_get_private_obj_state(struct drm_atomic_state 
*state, void *obj,
struct __drm_private_objs_state *arr;
 
for (i = 0; i < state->num_private_objs; i++)
-   if (obj == state->private_objs[i].obj &&
-   state->private_objs[i].obj_state)
+   if (obj == state->private_objs[i].obj)
return state->private_objs[i].obj_state;
 
num_objs = state->num_private_objs + 1;
-- 
2.13.0

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[Intel-gfx] [PATCH 07/22] drm/i915: Eliminate crtc->state usage from intel_atomic_commit_tail and .crtc_update()

[ville . syrjala]

From: Ville Syrjälä 

We already have the correct new crtc state so just use that instead of
crtc->state.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_display.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 0c18e3e7c6a5..791204c8621c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12970,7 +12970,7 @@ static void skl_update_crtcs(struct drm_atomic_state 
*state,
unsigned int cmask = drm_crtc_mask(crtc);
 
intel_crtc = to_intel_crtc(crtc);
-   cstate = to_intel_crtc_state(crtc->state);
+   cstate = to_intel_crtc_state(new_crtc_state);
pipe = intel_crtc->pipe;
 
if (updated & cmask || !cstate->base.active)
@@ -13073,7 +13073,7 @@ static void intel_atomic_commit_tail(struct 
drm_atomic_state *state)
intel_check_cpu_fifo_underruns(dev_priv);
intel_check_pch_fifo_underruns(dev_priv);
 
-   if (!crtc->state->active) {
+   if (!new_crtc_state->active) {
/*
 * Make sure we don't call initial_watermarks
 * for ILK-style watermark updates.
@@ -13082,7 +13082,7 @@ static void intel_atomic_commit_tail(struct 
drm_atomic_state *state)
 */
if (INTEL_GEN(dev_priv) >= 9)

dev_priv->display.initial_watermarks(intel_state,
-
to_intel_crtc_state(crtc->state));
+
to_intel_crtc_state(new_crtc_state));
}
}
}
-- 
2.13.0

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[Intel-gfx] [PATCH 06/22] drm/i915: Eliminate crtc->state usage from intel_update_pipe_config()

[ville . syrjala]

From: Ville Syrjälä 

Pass the correct new crtc state to intel_update_pipe_config() instead
of using crtc->state.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_display.c | 19 +--
 1 file changed, 9 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 182881c4d6d3..0c18e3e7c6a5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3633,15 +3633,14 @@ static bool intel_crtc_has_pending_flip(struct drm_crtc 
*crtc)
return pending;
 }
 
-static void intel_update_pipe_config(struct intel_crtc *crtc,
-struct intel_crtc_state *old_crtc_state)
+static void intel_update_pipe_config(const struct intel_crtc_state 
*old_crtc_state,
+const struct intel_crtc_state 
*new_crtc_state)
 {
+   struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-   struct intel_crtc_state *pipe_config =
-   to_intel_crtc_state(crtc->base.state);
 
/* drm_atomic_helper_update_legacy_modeset_state might not be called. */
-   crtc->base.mode = crtc->base.state->mode;
+   crtc->base.mode = new_crtc_state->base.mode;
 
/*
 * Update pipe size and adjust fitter if needed: the reason for this is
@@ -3653,17 +3652,17 @@ static void intel_update_pipe_config(struct intel_crtc 
*crtc,
 */
 
I915_WRITE(PIPESRC(crtc->pipe),
-  ((pipe_config->pipe_src_w - 1) << 16) |
-  (pipe_config->pipe_src_h - 1));
+  ((new_crtc_state->pipe_src_w - 1) << 16) |
+  (new_crtc_state->pipe_src_h - 1));
 
/* on skylake this is done by detaching scalers */
if (INTEL_GEN(dev_priv) >= 9) {
skl_detach_scalers(crtc);
 
-   if (pipe_config->pch_pfit.enabled)
+   if (new_crtc_state->pch_pfit.enabled)
skylake_pfit_enable(crtc);
} else if (HAS_PCH_SPLIT(dev_priv)) {
-   if (pipe_config->pch_pfit.enabled)
+   if (new_crtc_state->pch_pfit.enabled)
ironlake_pfit_enable(crtc);
else if (old_crtc_state->pch_pfit.enabled)
ironlake_pfit_disable(crtc, true);
@@ -13560,7 +13559,7 @@ static void intel_begin_crtc_commit(struct drm_crtc 
*crtc,
goto out;
 
if (intel_cstate->update_pipe)
-   intel_update_pipe_config(intel_crtc, old_intel_cstate);
+   intel_update_pipe_config(old_intel_cstate, intel_cstate);
else if (INTEL_GEN(dev_priv) >= 9)
skl_detach_scalers(intel_crtc);
 
-- 
2.13.0

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[Intel-gfx] [PATCH 08/22] drm: Add drm_dynarray

[ville . syrjala]

From: Ville Syrjälä 

Add a small helper that gives us dynamically growing arrays. We have a
couple hand rolled implementations of this in the atomic code, which we
can unify to use a common implementation.

Signed-off-by: Ville Syrjälä 
---
 Documentation/gpu/drm-utils.rst | 15 +++
 Documentation/gpu/index.rst |  1 +
 drivers/gpu/drm/Makefile|  2 +-
 drivers/gpu/drm/drm_dynarray.c  | 97 +
 include/drm/drm_dynarray.h  | 54 +++
 5 files changed, 168 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/gpu/drm-utils.rst
 create mode 100644 drivers/gpu/drm/drm_dynarray.c
 create mode 100644 include/drm/drm_dynarray.h

diff --git a/Documentation/gpu/drm-utils.rst b/Documentation/gpu/drm-utils.rst
new file mode 100644
index ..bff8c899d7cd
--- /dev/null
+++ b/Documentation/gpu/drm-utils.rst
@@ -0,0 +1,15 @@
+=
+DRM Utilities
+=
+
+Dynamic arrays
+--
+
+.. kernel-doc:: drivers/gpu/drm/drm_dynarray.c
+   :doc: Dynamic arrays
+
+.. kernel-doc:: drivers/gpu/drm/drm_dynarray.c
+   :export:
+
+.. kernel-doc:: include/drm/drm_dynarray.h
+   :internal:
diff --git a/Documentation/gpu/index.rst b/Documentation/gpu/index.rst
index 35d673bf9b56..b7d196e5c70d 100644
--- a/Documentation/gpu/index.rst
+++ b/Documentation/gpu/index.rst
@@ -10,6 +10,7 @@ Linux GPU Driver Developer's Guide
drm-kms
drm-kms-helpers
drm-uapi
+   drm-utils
i915
meson
pl111
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 24a066e1841c..b637a34df388 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -3,7 +3,7 @@
 # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
 
 drm-y   := drm_auth.o drm_bufs.o drm_cache.o \
-   drm_context.o drm_dma.o \
+   drm_context.o drm_dma.o drm_dynarray.o \
drm_file.o drm_gem.o drm_ioctl.o drm_irq.o \
drm_lock.o drm_memory.o drm_drv.o \
drm_scatter.o drm_pci.o \
diff --git a/drivers/gpu/drm/drm_dynarray.c b/drivers/gpu/drm/drm_dynarray.c
new file mode 100644
index ..69a8819ecb62
--- /dev/null
+++ b/drivers/gpu/drm/drm_dynarray.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2017 Intel Corp.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include 
+#include 
+#include 
+
+/**
+ * DOC: Dynamic arrays
+ *
+ * Helper that provides dynamically growing arrays. The array
+ * must be initilaized to specify the size of each element, and
+ * space can be reserved in the array by specifying the element
+ * index to be used.
+ */
+
+/**
+ * drm_dynarray_init - Initialize the dynamic array
+ * @dynarr: the dynamic array
+ * @elem_size: size of each element in bytes
+ *
+ * Initialize the dynamic array and specify the size of
+ * each element of the array.
+ */
+void drm_dynarray_init(struct drm_dynarray *dynarr,
+  unsigned int elem_size)
+{
+   memset(dynarr, 0, sizeof(*dynarr));
+   dynarr->elem_size = elem_size;
+}
+EXPORT_SYMBOL(drm_dynarray_init);
+
+/**
+ * drm_dynarray_fini - Finalize the dynamic array
+ * @dynarr: the dynamic array
+ *
+ * Finalize the dynamic array, ie. free the memory
+ * used by the array.
+ */
+void drm_dynarray_fini(struct drm_dynarray *dynarr)
+{
+   kfree(dynarr->elems);
+   memset(dynarr, 0, sizeof(*dynarr));
+}
+EXPORT_SYMBOL(drm_dynarray_fini);
+
+/**
+ * drm_dynarray_reserve - Reserve space in the dynamic array
+ * @dynarr: the dynamic array
+ * @index: the index of the element to reserve
+ *
+ * Grow the array sufficiently to make sure @index points
+ * to a valid memory location within the array.
+ */
+int drm_dynarray_reserve(struct drm_dynarray *dynarr,
+unsigned int index)
+{
+   unsigned int num_elems = index + 1;
+   unsigned int 

[Intel-gfx] [PATCH 05/22] drm/i915: Eliminate obj->state usage from pre/post plane update

[ville . syrjala]

From: Ville Syrjälä 

Dig up the appropriate new crtc and plane states from the top level
atomic state in intel_pre_plane_update() and intel_post_plane_update().

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_display.c | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 6440479d6fe2..182881c4d6d3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4994,7 +4994,8 @@ static void intel_post_plane_update(struct 
intel_crtc_state *old_crtc_state)
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
struct drm_atomic_state *old_state = old_crtc_state->base.state;
struct intel_crtc_state *pipe_config =
-   to_intel_crtc_state(crtc->base.state);
+   
intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state),
+   crtc);
struct drm_plane *primary = crtc->base.primary;
struct drm_plane_state *old_pri_state =
drm_atomic_get_existing_plane_state(old_state, primary);
@@ -5006,7 +5007,8 @@ static void intel_post_plane_update(struct 
intel_crtc_state *old_crtc_state)
 
if (old_pri_state) {
struct intel_plane_state *primary_state =
-   to_intel_plane_state(primary->state);
+   
intel_atomic_get_new_plane_state(to_intel_atomic_state(old_state),
+
to_intel_plane(primary));
struct intel_plane_state *old_primary_state =
to_intel_plane_state(old_pri_state);
 
@@ -5035,7 +5037,8 @@ static void intel_pre_plane_update(struct 
intel_crtc_state *old_crtc_state,
 
if (old_pri_state) {
struct intel_plane_state *primary_state =
-   to_intel_plane_state(primary->state);
+   intel_atomic_get_new_plane_state(old_intel_state,
+
to_intel_plane(primary));
struct intel_plane_state *old_primary_state =
to_intel_plane_state(old_pri_state);
 
-- 
2.13.0

___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 01/22] drm/i915: Pass the new crtc state to color management code

[ville . syrjala]

From: Ville Syrjälä 

In an effort to eliminate the obj->state usage let's pass on the
new crtc state pointer (which we already have!) to the color management
code.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_display.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 0648fd74be87..90fba8a44630 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13546,8 +13546,8 @@ static void intel_begin_crtc_commit(struct drm_crtc 
*crtc,
if (!modeset &&
(intel_cstate->base.color_mgmt_changed ||
 intel_cstate->update_pipe)) {
-   intel_color_set_csc(crtc->state);
-   intel_color_load_luts(crtc->state);
+   intel_color_set_csc(_cstate->base);
+   intel_color_load_luts(_cstate->base);
}
 
/* Perform vblank evasion around commit operation */
-- 
2.13.0

___
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[Intel-gfx] [PATCH 03/22] drm/i915: Eliminate obj->state usage in g4x/vlv/chv wm computation

[ville . syrjala]

From: Ville Syrjälä 

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_drv.h  |  9 +
 drivers/gpu/drm/i915/intel_drv.h |  8 
 drivers/gpu/drm/i915/intel_pm.c  | 30 +++---
 3 files changed, 32 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 81cd21ecfa7d..baec61b078f5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -563,6 +563,15 @@ struct i915_hotplug {
 (__i)++) \
for_each_if (plane_state)
 
+#define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, 
new_plane_state, __i) \
+   for ((__i) = 0; \
+(__i) < (__state)->base.dev->mode_config.num_total_plane && \
+((plane) = 
to_intel_plane((__state)->base.planes[__i].ptr), \
+ (old_plane_state) = 
to_intel_plane_state((__state)->base.planes[__i].old_state), \
+ (new_plane_state) = 
to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
+(__i)++) \
+   for_each_if (plane)
+
 struct drm_i915_private;
 struct i915_mm_struct;
 struct i915_mmu_object;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d22ca42f35da..e9d61a03c46e 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1208,6 +1208,14 @@ hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
 }
 
 static inline struct intel_crtc_state *
+intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
+   struct intel_crtc *crtc)
+{
+   return to_intel_crtc_state(drm_atomic_get_old_crtc_state(>base,
+>base));
+}
+
+static inline struct intel_crtc_state *
 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
struct intel_crtc *crtc)
 {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c3fcadfa0ae7..62320d70dc6f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1302,21 +1302,21 @@ static int g4x_compute_pipe_wm(struct intel_crtc_state 
*crtc_state)
int num_active_planes = hweight32(crtc_state->active_planes &
  ~BIT(PLANE_CURSOR));
const struct g4x_pipe_wm *raw;
-   struct intel_plane_state *plane_state;
+   const struct intel_plane_state *old_plane_state;
+   const struct intel_plane_state *new_plane_state;
struct intel_plane *plane;
enum plane_id plane_id;
int i, level;
unsigned int dirty = 0;
 
-   for_each_intel_plane_in_state(state, plane, plane_state, i) {
-   const struct intel_plane_state *old_plane_state =
-   to_intel_plane_state(plane->base.state);
-
-   if (plane_state->base.crtc != >base &&
+   for_each_oldnew_intel_plane_in_state(state, plane,
+old_plane_state,
+new_plane_state, i) {
+   if (new_plane_state->base.crtc != >base &&
old_plane_state->base.crtc != >base)
continue;
 
-   if (g4x_raw_plane_wm_compute(crtc_state, plane_state))
+   if (g4x_raw_plane_wm_compute(crtc_state, new_plane_state))
dirty |= BIT(plane->id);
}
 
@@ -1811,21 +1811,21 @@ static int vlv_compute_pipe_wm(struct intel_crtc_state 
*crtc_state)
int num_active_planes = hweight32(crtc_state->active_planes &
  ~BIT(PLANE_CURSOR));
bool needs_modeset = drm_atomic_crtc_needs_modeset(_state->base);
-   struct intel_plane_state *plane_state;
+   const struct intel_plane_state *old_plane_state;
+   const struct intel_plane_state *new_plane_state;
struct intel_plane *plane;
enum plane_id plane_id;
int level, ret, i;
unsigned int dirty = 0;
 
-   for_each_intel_plane_in_state(state, plane, plane_state, i) {
-   const struct intel_plane_state *old_plane_state =
-   to_intel_plane_state(plane->base.state);
-
-   if (plane_state->base.crtc != >base &&
+   for_each_oldnew_intel_plane_in_state(state, plane,
+old_plane_state,
+new_plane_state, i) {
+   if (new_plane_state->base.crtc != >base &&
old_plane_state->base.crtc != >base)
continue;
 
-   if (vlv_raw_plane_wm_compute(crtc_state, plane_state))
+   if (vlv_raw_plane_wm_compute(crtc_state, new_plane_state))
dirty |= BIT(plane->id);
}
 
@@ 

[Intel-gfx] [PATCH 04/22] drm/i915: Pass proper old/new states to intel_plane_atomic_check_with_state()

[ville . syrjala]

From: Ville Syrjälä 

Eliminate plane->state and crtc->state usage from
intel_plane_atomic_check_with_state() and its callers. Instead pass the
proper states in or dig them up from the top level atomic state.

Note that intel_plane_atomic_check_with_state() itself isn't allowed to
use the top level atomic state as there is none when it gets called from
the legacy cursor short circuit path.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_atomic_plane.c | 40 +++
 drivers/gpu/drm/i915/intel_display.c  | 12 ++
 drivers/gpu/drm/i915/intel_drv.h  | 16 +++--
 3 files changed, 46 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c 
b/drivers/gpu/drm/i915/intel_atomic_plane.c
index ee76fab7bb6f..7cdbe9ae2c96 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -107,7 +107,9 @@ intel_plane_destroy_state(struct drm_plane *plane,
drm_atomic_helper_plane_destroy_state(plane, state);
 }
 
-int intel_plane_atomic_check_with_state(struct intel_crtc_state *crtc_state,
+int intel_plane_atomic_check_with_state(const struct intel_crtc_state 
*old_crtc_state,
+   struct intel_crtc_state *crtc_state,
+   const struct intel_plane_state 
*old_plane_state,
struct intel_plane_state *intel_state)
 {
struct drm_plane *plane = intel_state->base.plane;
@@ -124,7 +126,7 @@ int intel_plane_atomic_check_with_state(struct 
intel_crtc_state *crtc_state,
 * anything driver-specific we need to test in that case, so
 * just return success.
 */
-   if (!intel_state->base.crtc && !plane->state->crtc)
+   if (!intel_state->base.crtc && !old_plane_state->base.crtc)
return 0;
 
/* Clip all planes to CRTC size, or 0x0 if CRTC is disabled */
@@ -194,17 +196,21 @@ int intel_plane_atomic_check_with_state(struct 
intel_crtc_state *crtc_state,
else
crtc_state->active_planes &= ~BIT(intel_plane->id);
 
-   return intel_plane_atomic_calc_changes(_state->base, state);
+   return intel_plane_atomic_calc_changes(old_crtc_state,
+  _state->base,
+  old_plane_state,
+  state);
 }
 
 static int intel_plane_atomic_check(struct drm_plane *plane,
struct drm_plane_state *state)
 {
-   struct drm_crtc *crtc = state->crtc;
+   const struct drm_plane_state *old_plane_state =
+   drm_atomic_get_old_plane_state(state->state, plane);
+   struct drm_crtc *crtc = state->crtc ?: old_plane_state->crtc;
+   const struct drm_crtc_state *old_crtc_state;
struct drm_crtc_state *drm_crtc_state;
 
-   crtc = crtc ? crtc : plane->state->crtc;
-
/*
 * Both crtc and plane->crtc could be NULL if we're updating a
 * property while the plane is disabled.  We don't actually have
@@ -214,29 +220,33 @@ static int intel_plane_atomic_check(struct drm_plane 
*plane,
if (!crtc)
return 0;
 
-   drm_crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
-   if (WARN_ON(!drm_crtc_state))
-   return -EINVAL;
+   old_crtc_state = drm_atomic_get_old_crtc_state(state->state, crtc);
+   drm_crtc_state = drm_atomic_get_new_crtc_state(state->state, crtc);
 
-   return 
intel_plane_atomic_check_with_state(to_intel_crtc_state(drm_crtc_state),
+   return 
intel_plane_atomic_check_with_state(to_intel_crtc_state(old_crtc_state),
+  
to_intel_crtc_state(drm_crtc_state),
+  
to_intel_plane_state(old_plane_state),
   to_intel_plane_state(state));
 }
 
 static void intel_plane_atomic_update(struct drm_plane *plane,
  struct drm_plane_state *old_state)
 {
+   struct intel_atomic_state *state = 
to_intel_atomic_state(old_state->state);
struct intel_plane *intel_plane = to_intel_plane(plane);
-   struct intel_plane_state *intel_state =
-   to_intel_plane_state(plane->state);
-   struct drm_crtc *crtc = plane->state->crtc ?: old_state->crtc;
+   const struct intel_plane_state *intel_state =
+   intel_atomic_get_new_plane_state(state, intel_plane);
+   struct drm_crtc *crtc = intel_state->base.crtc ?: old_state->crtc;
 
if (intel_state->base.visible) {
+   const struct intel_crtc_state *intel_crtc_state =
+   intel_atomic_get_new_crtc_state(state, 
to_intel_crtc(crtc));
+
trace_intel_update_plane(plane,

[Intel-gfx] [PATCH 02/22] drm/i915: Pass the crtc state explicitly to intel_pipe_update_start/end()

[ville . syrjala]

From: Ville Syrjälä 

Pass the appropriate new crtc state explicitly to
intel_pipe_update_start/end() instead of of mucking around with
crtc->state.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_display.c | 18 +++---
 drivers/gpu/drm/i915/intel_drv.h | 13 +++--
 drivers/gpu/drm/i915/intel_sprite.c  | 28 ++--
 3 files changed, 36 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 90fba8a44630..cdfa95be4b8e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10645,7 +10645,7 @@ static void intel_mmio_flip_work_func(struct 
work_struct *w)
 
WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0);
 
-   intel_pipe_update_start(crtc);
+   intel_pipe_update_start(crtc->config);
 
if (INTEL_GEN(dev_priv) >= 9)
skl_do_mmio_flip(crtc, work->rotation, work);
@@ -10653,7 +10653,7 @@ static void intel_mmio_flip_work_func(struct 
work_struct *w)
/* use_mmio_flip() retricts MMIO flips to ilk+ */
ilk_do_mmio_flip(crtc, work);
 
-   intel_pipe_update_end(crtc, work);
+   intel_pipe_update_end(crtc->config, work);
 }
 
 static int intel_default_queue_flip(struct drm_device *dev,
@@ -13535,13 +13535,13 @@ static void intel_begin_crtc_commit(struct drm_crtc 
*crtc,
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-   struct intel_crtc_state *intel_cstate =
-   to_intel_crtc_state(crtc->state);
struct intel_crtc_state *old_intel_cstate =
to_intel_crtc_state(old_crtc_state);
struct intel_atomic_state *old_intel_state =
to_intel_atomic_state(old_crtc_state->state);
-   bool modeset = needs_modeset(crtc->state);
+   struct intel_crtc_state *intel_cstate =
+   intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
+   bool modeset = needs_modeset(_cstate->base);
 
if (!modeset &&
(intel_cstate->base.color_mgmt_changed ||
@@ -13551,7 +13551,7 @@ static void intel_begin_crtc_commit(struct drm_crtc 
*crtc,
}
 
/* Perform vblank evasion around commit operation */
-   intel_pipe_update_start(intel_crtc);
+   intel_pipe_update_start(intel_cstate);
 
if (modeset)
goto out;
@@ -13571,8 +13571,12 @@ static void intel_finish_crtc_commit(struct drm_crtc 
*crtc,
 struct drm_crtc_state *old_crtc_state)
 {
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+   struct intel_atomic_state *old_intel_state =
+   to_intel_atomic_state(old_crtc_state->state);
+   struct intel_crtc_state *new_crtc_state =
+   intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
 
-   intel_pipe_update_end(intel_crtc, NULL);
+   intel_pipe_update_end(new_crtc_state, NULL);
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d17a32437f07..d22ca42f35da 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1207,6 +1207,14 @@ hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
return container_of(intel_hdmi, struct intel_digital_port, hdmi);
 }
 
+static inline struct intel_crtc_state *
+intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
+   struct intel_crtc *crtc)
+{
+   return to_intel_crtc_state(drm_atomic_get_new_crtc_state(>base,
+>base));
+}
+
 /* intel_fifo_underrun.c */
 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
   enum pipe pipe, bool enable);
@@ -1900,8 +1908,9 @@ struct intel_plane *intel_sprite_plane_create(struct 
drm_i915_private *dev_priv,
  enum pipe pipe, int plane);
 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
  struct drm_file *file_priv);
-void intel_pipe_update_start(struct intel_crtc *crtc);
-void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work 
*work);
+void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state);
+void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state,
+  struct intel_flip_work *work);
 
 /* intel_tv.c */
 void intel_tv_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
b/drivers/gpu/drm/i915/intel_sprite.c
index 0c650c2cbca8..697b95016c7a 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -69,8 +69,7 @@ int 

[Intel-gfx] [PATCH v2 00/22] drm/i915: Fix pre-g4x GPU reset, again (v2)

[ville . syrjala]

From: Ville Syrjälä 

OK, so here's the full version of my rw_semaphore GPU vs. display reset
fix.

The only issue I'm aware of is that SKL watermark code still uses
obj->state and thus I have no clue what would happen if one tries to
run this on SKL. Untangling that would likely mean making the SKL wm
code more in line with the g4x/vlv/chv code (ie. track things in the
crtc state). I decided not to embark on that quest at this time.

Entire series available here:
git://github.com/vsyrjala/linux.git reset_commit_rwsem_4

Ville Syrjälä (22):
  drm/i915: Pass the new crtc state to color management code
  drm/i915: Pass the crtc state explicitly to
intel_pipe_update_start/end()
  drm/i915: Eliminate obj->state usage in g4x/vlv/chv wm computation
  drm/i915: Pass proper old/new states to
intel_plane_atomic_check_with_state()
  drm/i915: Eliminate obj->state usage from pre/post plane update
  drm/i915: Eliminate crtc->state usage from intel_update_pipe_config()
  drm/i915: Eliminate crtc->state usage from intel_atomic_commit_tail
and .crtc_update()
  drm: Add drm_dynarray
  drm/atomic: Convert state->connectors to drm_dynarray
  drm/atomic: Remove pointless private object NULL state check
  drm/atomic: Convert private_objs to drm_dynarray
  drm/atomic: Make private objs proper objects
  drm/atomic: Pass old state to
__drm_atomic_helper_crtc_duplicate_state() & co. explicitly
  drm/arm: s/old_state/old_mali_state/
  drm/mediatek: s/old_state/old_mtk_state/
  drm/atomic: Pass old state explicitly to .atomic_duplicate_state()
  drm/atomic: Fix up the kernel docs for the state duplication functions
  drm: Return the connector from drm_connector_get()
  drm/i915% Store vma gtt offset in plane state
  drm/i915: Refactor __intel_atomic_commit_tail()
  drm/atomic: Introduce drm_atomic_helper_duplicate_commited_state()
  drm/i915: Solve the GPU reset vs. modeset deadlocks with an
rw_semaphore

 Documentation/gpu/drm-utils.rst |  15 ++
 Documentation/gpu/index.rst |   1 +
 drivers/gpu/drm/Makefile|   2 +-
 drivers/gpu/drm/arm/malidp_crtc.c   |  18 +-
 drivers/gpu/drm/arm/malidp_planes.c |  10 +-
 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c  |  10 +-
 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c |   5 +-
 drivers/gpu/drm/drm_atomic.c| 174 +++-
 drivers/gpu/drm/drm_atomic_helper.c | 318 --
 drivers/gpu/drm/drm_crtc_helper.c   |  12 +-
 drivers/gpu/drm/drm_dp_mst_topology.c   |  65 +++--
 drivers/gpu/drm/drm_dynarray.c  |  97 +++
 drivers/gpu/drm/drm_fb_helper.c |   7 +-
 drivers/gpu/drm/drm_plane_helper.c  |  12 +-
 drivers/gpu/drm/exynos/exynos_drm_plane.c   |   8 +-
 drivers/gpu/drm/i915/i915_drv.h |  11 +
 drivers/gpu/drm/i915/intel_atomic.c |  16 +-
 drivers/gpu/drm/i915/intel_atomic_plane.c   |  47 ++--
 drivers/gpu/drm/i915/intel_display.c| 342 
 drivers/gpu/drm/i915/intel_drv.h|  52 +++-
 drivers/gpu/drm/i915/intel_pm.c |  30 +--
 drivers/gpu/drm/i915/intel_sdvo.c   |   9 +-
 drivers/gpu/drm/i915/intel_sprite.c |  37 +--
 drivers/gpu/drm/imx/ipuv3-crtc.c|   6 +-
 drivers/gpu/drm/imx/ipuv3-plane.c   |   8 +-
 drivers/gpu/drm/mediatek/mtk_drm_crtc.c |   6 +-
 drivers/gpu/drm/mediatek/mtk_drm_plane.c|  10 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c|  10 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c   |  14 +-
 drivers/gpu/drm/nouveau/nouveau_connector.c |   8 +-
 drivers/gpu/drm/nouveau/nouveau_connector.h |   3 +-
 drivers/gpu/drm/nouveau/nv50_display.c  |  16 +-
 drivers/gpu/drm/rcar-du/rcar_du_plane.c |  10 +-
 drivers/gpu/drm/rcar-du/rcar_du_vsp.c   |  10 +-
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c |   6 +-
 drivers/gpu/drm/tegra/dc.c  |  16 +-
 drivers/gpu/drm/tegra/dsi.c |   8 +-
 drivers/gpu/drm/tegra/sor.c |   8 +-
 drivers/gpu/drm/vc4/vc4_crtc.c  |   6 +-
 drivers/gpu/drm/vc4/vc4_plane.c |  10 +-
 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c |  26 +-
 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h |   9 +-
 include/drm/drm_atomic.h| 179 -
 include/drm/drm_atomic_helper.h |  31 ++-
 include/drm/drm_connector.h |  23 +-
 include/drm/drm_crtc.h  |  16 +-
 include/drm/drm_dp_mst_helper.h |  10 +
 include/drm/drm_dynarray.h  |  54 
 include/drm/drm_plane.h |  16 +-
 49 files changed, 1324 insertions(+), 493 deletions(-)
 create mode 100644 Documentation/gpu/drm-utils.rst
 create 

[Intel-gfx] [maintainer-tools RFC PATCH] drm-intel: Link to .html instead of .rst

[Rodrigo Vivi]

Ideally .rst would referrence .rst with :ref:`` but since
these documentation are different repository we cannot link
like this. However I believe the main usage is through the
compiled html pages and since we already reference another
.html here I believe we should use our daily compiled doc.

Signed-off-by: Rodrigo Vivi 
---
 drm-intel.rst | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drm-intel.rst b/drm-intel.rst
index 5dcb7d8..fa1e9bc 100644
--- a/drm-intel.rst
+++ b/drm-intel.rst
@@ -189,7 +189,7 @@ the appropriate branches.
 
 If possible, the commit message should also contain a Fixes: tag as described 
in
 `Documentation/process/submitting-patches
-`_
+  `_
 to aid the maintainers in identifying the right branch.
 
 Requesting Fixes Cherry-Pick Afterwards
@@ -199,7 +199,7 @@ It's not uncommon for a patch to have been committed before 
it's identified as a
 fix needing to be backported.
 
 If the patch is already in Linus' tree, please follow `stable kernel rules
-`_.
+`_.
 
 Otherwise, send an email to intel-gfx@lists.freedesktop.org and
 drm-intel-fi...@lists.freedesktop.org containing the subject of the patch, the
@@ -361,7 +361,7 @@ An inexhaustive list of details to check:
 
 * The patch conforms to `Documentation/process/submitting-patches
 
-  
`_
+  `_
 
 * The commit message is sensible, and includes adequate details and references.
 
@@ -411,7 +411,7 @@ On Confidence, Complexity, and Transparency
 
 * Reviewed-by. All patches must be reviewed, no exceptions. Please see
   "Reviewer's statement of oversight" in 
`Documentation/process/submitting-patches
-  
`_
+  `_
   and `review training
   `_.
 
-- 
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[Intel-gfx] [maintainer-tools PATCH] drm-intel: Fix links to torvalds documentation.

[Rodrigo Vivi]

All process related docs has moved to the new "process" folder,
but also all .txt migrated to .rst as well.

Signed-off-by: Rodrigo Vivi 
---
 drm-intel.rst | 15 ---
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/drm-intel.rst b/drm-intel.rst
index 4699171..5dcb7d8 100644
--- a/drm-intel.rst
+++ b/drm-intel.rst
@@ -188,8 +188,8 @@ The maintainers will cherry-pick labeled patches from 
drm-intel-next-queued to
 the appropriate branches.
 
 If possible, the commit message should also contain a Fixes: tag as described 
in
-`Documentation/SubmittingPatches
-`_
+`Documentation/process/submitting-patches
+`_
 to aid the maintainers in identifying the right branch.
 
 Requesting Fixes Cherry-Pick Afterwards
@@ -199,7 +199,7 @@ It's not uncommon for a patch to have been committed before 
it's identified as a
 fix needing to be backported.
 
 If the patch is already in Linus' tree, please follow `stable kernel rules
-`_.
+`_.
 
 Otherwise, send an email to intel-gfx@lists.freedesktop.org and
 drm-intel-fi...@lists.freedesktop.org containing the subject of the patch, the
@@ -359,8 +359,9 @@ Detail Check List
 
 An inexhaustive list of details to check:
 
-* The patch conforms to `Documentation/SubmittingPatches
-  
`_.
+* The patch conforms to `Documentation/process/submitting-patches
+
+  
`_
 
 * The commit message is sensible, and includes adequate details and references.
 
@@ -409,8 +410,8 @@ On Confidence, Complexity, and Transparency
   list, IRC, in person, in a meeting) but must be added to the commit.
 
 * Reviewed-by. All patches must be reviewed, no exceptions. Please see
-  "Reviewer's statement of oversight" in `Documentation/SubmittingPatches
-  
`_
+  "Reviewer's statement of oversight" in 
`Documentation/process/submitting-patches
+  
`_
   and `review training
   `_.
 
-- 
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Re: [Intel-gfx] [PATCH] drm/i915: Disable per-engine reset for Broxton

[Chris Wilson]

Quoting Michel Thierry (2017-07-06 18:02:13)
> On Thu, Jul 6, 2017 at 12:11 AM, Chris Wilson 
>  wrote:
> > Quoting Michel Thierry (2017-07-06 02:24:26)
> >>  On 04/07/17 09:09, Chris Wilson wrote:
> >>  > Triggering a GPU reset for one engine affects another, notably
> >>  > corrupting the context status buffer (CSB) effectively losing 
> >> track of
> >>  > inflight requests.
> >>  >
> >>  > Adding a few printks:
> >>  > diff --git a/drivers/gpu/drm/i915/i915_drv.c 
> >> b/drivers/gpu/drm/i915/i915_drv.c
> >>  > index ad41836fa5e5..a969456bc0fa 100644
> >>  > --- a/drivers/gpu/drm/i915/i915_drv.c
> >>  > +++ b/drivers/gpu/drm/i915/i915_drv.c
> >>  > @@ -1953,6 +1953,7 @@ int i915_reset_engine(struct 
> >> intel_engine_cs *engine)
> >>  > goto out;
> >>  > }
> >>  >
> >>  > +   pr_err("Resetting %s\n", engine->name);
> >>  > ret = intel_gpu_reset(engine->i915, 
> >> intel_engine_flag(engine));
> >>  > if (ret) {
> >>  > /* If we fail here, we expect to fallback to a 
> >> global reset */
> >>  > diff --git a/drivers/gpu/drm/i915/intel_lrc.c 
> >> b/drivers/gpu/drm/i915/intel_lrc.c
> >>  > index 716e5c9ea222..a72bc35d0870 100644
> >>  > --- a/drivers/gpu/drm/i915/intel_lrc.c
> >>  > +++ b/drivers/gpu/drm/i915/intel_lrc.c
> >>  > @@ -355,6 +355,7 @@ static void execlists_submit_ports(struct 
> >> intel_engine_cs *engine)
> >>  > 
> >> execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN);
> >>  > port_set([n], port_pack(rq, count));
> >>  > desc = execlists_update_context(rq);
> >>  > +   pr_err("%s: in (rq=%x) ctx=%d\n", 
> >> engine->name, rq->global_seqno, upper_32_bits(desc));
> >>  > GEM_DEBUG_EXEC(port[n].context_id = 
> >> upper_32_bits(desc));
> >>  > } else {
> >>  > GEM_BUG_ON(!n);
> >>  > @@ -594,9 +595,23 @@ static void intel_lrc_irq_handler(unsigned 
> >> long data)
> >>  > if (!(status & 
> >> GEN8_CTX_STATUS_COMPLETED_MASK))
> >>  > continue;
> >>  >
> >>  > +   pr_err("%s: out CSB (%x head=%d, 
> >> tail=%d), ctx=%d, rq=%d\n",
> >>  > +   engine->name,
> >>  > +   readl(csb_mmio),
> >>  > +   head, tail,
> >>  > +   readl(buf+2*head+1),
> >>  > +   port->context_id);
> >>  > +
> >>  > /* Check the context/desc id for this 
> >> event matches */
> >>  > -   GEM_DEBUG_BUG_ON(readl(buf + 2 * head + 
> >> 1) !=
> >>  > -port->context_id);
> >>  > +   if (readl(buf + 2 * head + 1) != 
> >> port->context_id) {
> >>  > +   pr_err("%s: BUG CSB (%x head=%d, 
> >> tail=%d), ctx=%d, rq=%d\n",
> >>  > +   engine->name,
> >>  > +   readl(csb_mmio),
> >>  > +   head, tail,
> >>  > +   
> >> readl(buf+2*head+1),
> >>  > +   port->context_id);
> >>  > +   BUG();
> >>  > +   }
> >>  >
> >>  > rq = port_unpack(port, );
> >>  > GEM_BUG_ON(count == 0);
> >>  >
> >>  > Results in:
> >>  >
> >>  > [ 6423.006602] Resetting rcs0
> >>  > [ 6423.009080] rcs0: in (rq=fe70) ctx=1
> >>  > [ 6423.009216] rcs0: in (rq=fe6f) ctx=3
> >>  > [ 6423.009542] rcs0: out CSB (2 head=1, tail=2), ctx=3, rq=3
> >>  > [ 6423.009619] Resetting bcs0
> >>  > [ 6423.009980] rcs0: BUG CSB (0 head=1, tail=2), ctx=0, rq=3
> >>  >
> >>  
> >>  It took me a while, but  I was able to replicate this (with your 
> >>  igt_reset_active_engines) a couple of times. I also captured the 
> >> value 
> >>  of the CSB events at that point and it looked like this.
> > 
> > Ah, that's a separate issue that definitely isn't limited to bxt. In 
> > the
> > bug on my machine the CSB is distinctly zeroed.
> 
> Oh, if you saw them being zeroed, then there's not much I can argue (do 
> you remember if the CSB write pointer was reset to '7' too?).

I didn't look at the pointer actually on reset (tried manually writing
to it, just in case it stuck across the power context reloads) then
realised that the fault was always due to the CSB reads returning 0 and
then pin-pointed it to the concurrent reset on the other engine.
 
> Hopefully is only limited to bxt, so sadly 

Broadwell has survived over a day so far (so back to the earlier
stability, -tip is decidedly unstable for resets atm), need to get around
to 

[Intel-gfx] [PATCH v2 3/4] drm/i915: Call uncore_suspend before platform suspend handlers

[Hans de Goede]

Quoting Ville: "the forcewake timer might still be active until the uncore
suspend, and having active forcewakes while we've already told the GT wake
stuff to stop acting normally doesn't seem quite right to me."

Reported-by: Ville Syrjälä 
Suggested-by: Imre Deak 
Signed-off-by: Hans de Goede 
---
Changes in v2:
-Rebase on current (July 6th 2017) drm-next
---
 drivers/gpu/drm/i915/i915_drv.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index ce31d9ed23dc..4a6cd3176e0a 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2415,6 +2415,8 @@ static int intel_runtime_suspend(struct device *kdev)
 
intel_runtime_pm_disable_interrupts(dev_priv);
 
+   intel_uncore_suspend(dev_priv);
+
ret = 0;
if (IS_GEN9_LP(dev_priv)) {
bxt_display_core_uninit(dev_priv);
@@ -2427,6 +2429,8 @@ static int intel_runtime_suspend(struct device *kdev)
 
if (ret) {
DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
+   intel_uncore_runtime_resume(dev_priv);
+
intel_runtime_pm_enable_interrupts(dev_priv);
 
enable_rpm_wakeref_asserts(dev_priv);
@@ -2434,8 +2438,6 @@ static int intel_runtime_suspend(struct device *kdev)
return ret;
}
 
-   intel_uncore_suspend(dev_priv);
-
enable_rpm_wakeref_asserts(dev_priv);
WARN_ON_ONCE(atomic_read(_priv->pm.wakeref_count));
 
-- 
2.13.0

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[Intel-gfx] [PATCH v2 2/4] drm/i915: Re-register PMIC bus access notifier on runtime resume

[Hans de Goede]

intel_uncore_suspend() unregisters the uncore code's PMIC bus access
notifier and gets called on both normal and runtime suspend.

intel_uncore_resume_early() re-registers the notifier, but only on
normal resume. Add a new intel_uncore_runtime_resume() function which
only re-registers the notifier and call that on runtime resume.

Reported-by: Imre Deak 
Signed-off-by: Hans de Goede 
---
Changes in v2:
-Rebase on current (July 6th 2017) drm-next
---
 drivers/gpu/drm/i915/i915_drv.c | 2 ++
 drivers/gpu/drm/i915/intel_uncore.c | 6 ++
 drivers/gpu/drm/i915/intel_uncore.h | 1 +
 3 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index ee2325b180e7..ce31d9ed23dc 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2510,6 +2510,8 @@ static int intel_runtime_resume(struct device *kdev)
ret = vlv_resume_prepare(dev_priv, true);
}
 
+   intel_uncore_runtime_resume(dev_priv);
+
/*
 * No point of rolling back things in case of an error, as the best
 * we can do is to hope that things will still work (and disable RPM).
diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index 168b28a87f76..4a547cdfafa9 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -434,6 +434,12 @@ void intel_uncore_resume_early(struct drm_i915_private 
*dev_priv)
i915_check_and_clear_faults(dev_priv);
 }
 
+void intel_uncore_runtime_resume(struct drm_i915_private *dev_priv)
+{
+   iosf_mbi_register_pmic_bus_access_notifier(
+   _priv->uncore.pmic_bus_access_nb);
+}
+
 void intel_uncore_sanitize(struct drm_i915_private *dev_priv)
 {
i915.enable_rc6 = sanitize_rc6_option(dev_priv, i915.enable_rc6);
diff --git a/drivers/gpu/drm/i915/intel_uncore.h 
b/drivers/gpu/drm/i915/intel_uncore.h
index 5f90278da461..0bdc3fcc0e64 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -121,6 +121,7 @@ bool intel_uncore_arm_unclaimed_mmio_detection(struct 
drm_i915_private *dev_priv
 void intel_uncore_fini(struct drm_i915_private *dev_priv);
 void intel_uncore_suspend(struct drm_i915_private *dev_priv);
 void intel_uncore_resume_early(struct drm_i915_private *dev_priv);
+void intel_uncore_runtime_resume(struct drm_i915_private *dev_priv);
 
 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
-- 
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[Intel-gfx] [PATCH v2 4/4] drm/i915: Acquire PUNIT->PMIC bus for intel_uncore_forcewake_reset()

[Hans de Goede]

intel_uncore_forcewake_reset() does forcewake puts and gets as such
we need to make sure that no-one tries to access the PUNIT->PMIC bus
(on systems where this bus is shared) while it runs, otherwise bad
things happen.

Normally this is taken care of by the i915_pmic_bus_access_notifier()
which does an intel_uncore_forcewake_get(FORCEWAKE_ALL) when some other
driver tries to access the PMIC bus, so that later forcewake gets are
no-ops (for the duration of the bus access).

But intel_uncore_forcewake_reset gets called in 3 cases:
1) Before registering the pmic_bus_access_notifier
2) After unregistering the pmic_bus_access_notifier
3) To reset forcewake state on a GPU reset

In all 3 cases the i915_pmic_bus_access_notifier() protection is
insufficient. This commit fixes the pmic bus access race this causes
by making intel_uncore_forcewake_reset() call iosf_mbi_punit_acquire()
(and iosf_mbi_punit_release() when done).

Note that iosf_mbi_punit_acquire() locks a mutex and thus
intel_uncore_forcewake_reset() may sleep after this commit. I've checked
all callers and they all already take other mutexes, so this is not a
problem.

Signed-off-by: Hans de Goede 
---
Changes in v2:
-Rebase on current (July 6th 2017) drm-next
---
 drivers/gpu/drm/i915/intel_uncore.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index 4a547cdfafa9..f9441c9ae226 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -237,6 +237,9 @@ static void intel_uncore_forcewake_reset(struct 
drm_i915_private *dev_priv,
int retry_count = 100;
enum forcewake_domains fw, active_domains;
 
+   /* Acquire the PUNIT->PMIC bus before modifying forcewake settings */
+   iosf_mbi_punit_acquire();
+
/* Hold uncore.lock across reset to prevent any register access
 * with forcewake not set correctly. Wait until all pending
 * timers are run before holding.
@@ -294,6 +297,7 @@ static void intel_uncore_forcewake_reset(struct 
drm_i915_private *dev_priv,
assert_forcewakes_inactive(dev_priv);
 
spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
+   iosf_mbi_punit_release();
 }
 
 static u64 gen9_edram_size(struct drm_i915_private *dev_priv)
-- 
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[Intel-gfx] [PATCH v2 1/4] drm/i915: Fix false-positive assert_rpm_wakelock_held in i915_pmic_bus_access_notifier

[Hans de Goede]

assert_rpm_wakelock_held is triggered from i915_pmic_bus_access_notifier
even though it gets unregistered on (runtime) suspend, this is caused
by a race happening under the following circumstances:

intel_runtime_pm_put does:

   atomic_dec(_priv->pm.wakeref_count);

   pm_runtime_mark_last_busy(kdev);
   pm_runtime_put_autosuspend(kdev);

And pm_runtime_put_autosuspend calls intel_runtime_suspend from
a workqueue, so there is ample of time between the atomic_dec() and
intel_runtime_suspend() unregistering the notifier. If the notifier
gets called in this windowd assert_rpm_wakelock_held falsely triggers
(at this point we're not runtime-suspended yet).

This commit adds disable_rpm_wakeref_asserts and
enable_rpm_wakeref_asserts calls around the
intel_uncore_forcewake_get(FORCEWAKE_ALL) call in
i915_pmic_bus_access_notifier fixing the false-positive WARN_ON.

Reported-by: FKr 
Signed-off-by: Hans de Goede 
---
Changes in v2:
-Rebase on current (July 6th 2017) drm-next
---
 drivers/gpu/drm/i915/intel_uncore.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index 9882724bc2b6..168b28a87f76 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1171,8 +1171,15 @@ static int i915_pmic_bus_access_notifier(struct 
notifier_block *nb,
 * bus, which will be busy after this notification, leading to:
 * "render: timed out waiting for forcewake ack request."
 * errors.
+*
+* This notifier may get called between intel_runtime_pm_put()
+* doing atomic_dec(wakeref_count) and intel_runtime_resume()
+* unregistering this notifier, which leads to false-positive
+* assert_rpm_wakelock_held() triggering.
 */
+   disable_rpm_wakeref_asserts(dev_priv);
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+   enable_rpm_wakeref_asserts(dev_priv);
break;
case MBI_PMIC_BUS_ACCESS_END:
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
-- 
2.13.0

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Re: [Intel-gfx] [RFC] drm/i915/lrc: allocate separate page for HWSP

[Michel Thierry]

On 7/6/2017 10:59 AM, Chris Wilson wrote:
> If there are no conflicts, then just skip the patch, and really there
> shouldn't be since the writes we care about are ordered and the writes
> we don't, we don't. We will need to move to per-context hwsp in the near
> future which should alleviate these concerns.

It helped me explain the strange data I was seeing in the HSWP during 
driver load came from (that random data wasn't really random, I was 
looking at the PPHWSP which later became the HWSP).


Just a comment/fix for GuC submission below, because as it is, this will 
break it.


-Michel

On 06/07/17 09:10, Daniele Ceraolo Spurio wrote:

On gen8+ we're currently using the PPHWSP of the kernel ctx as the
global HWSP. However, when the kernel ctx gets submitted (e.g. from
__intel_autoenable_gt_powersave) the HW will use that page as both
HWSP and PPHWSP. Currently we're not seeing any problem because the
conflict happens at offsets below 0x30 in an area we don't access,
but that is not guaranteed to be true for future platform.

To avoid the conflict, instead of re-using the PPHWSP of the kernel
ctx we can allocate a separate page for the HWSP like what happens for
pre-execlists platform.

Signed-off-by: Daniele Ceraolo Spurio 
Cc: Michel Thierry  > ---
  drivers/gpu/drm/i915/intel_engine_cs.c  | 123 +++
  drivers/gpu/drm/i915/intel_lrc.c|  42 +--
  drivers/gpu/drm/i915/intel_ringbuffer.c | 125 +---
  3 files changed, 127 insertions(+), 163 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index a55cd72..70e9d88 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -444,6 +444,114 @@ static void intel_engine_cleanup_scratch(struct 
intel_engine_cs *engine)
i915_vma_unpin_and_release(>scratch);
  }
  
+static void cleanup_phys_status_page(struct intel_engine_cs *engine)

+{
+   struct drm_i915_private *dev_priv = engine->i915;
+
+   if (!dev_priv->status_page_dmah)
+   return;
+
+   drm_pci_free(_priv->drm, dev_priv->status_page_dmah);
+   engine->status_page.page_addr = NULL;
+}
+
+static void cleanup_status_page(struct intel_engine_cs *engine)
+{
+   struct i915_vma *vma;
+   struct drm_i915_gem_object *obj;
+
+   vma = fetch_and_zero(>status_page.vma);
+   if (!vma)
+   return;
+
+   obj = vma->obj;
+
+   i915_vma_unpin(vma);
+   i915_vma_close(vma);
+
+   i915_gem_object_unpin_map(obj);
+   __i915_gem_object_release_unless_active(obj);
+}
+
+static int init_status_page(struct intel_engine_cs *engine)
+{
+   struct drm_i915_gem_object *obj;
+   struct i915_vma *vma;
+   unsigned int flags;
+   void *vaddr;
+   int ret;
+
+   obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
+   if (IS_ERR(obj)) {
+   DRM_ERROR("Failed to allocate status page\n");
+   return PTR_ERR(obj);
+   }
+
+   ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
+   if (ret)
+   goto err;
+
+   vma = i915_vma_instance(obj, >i915->ggtt.base, NULL);
+   if (IS_ERR(vma)) {
+   ret = PTR_ERR(vma);
+   goto err;
+   }
+
+   flags = PIN_GLOBAL;
+   if (!HAS_LLC(engine->i915))
+   /* On g33, we cannot place HWS above 256MiB, so
+* restrict its pinning to the low mappable arena.
+* Though this restriction is not documented for
+* gen4, gen5, or byt, they also behave similarly
+* and hang if the HWS is placed at the top of the
+* GTT. To generalise, it appears that all !llc
+* platforms have issues with us placing the HWS
+* above the mappable region (even though we never
+* actualy map it).


Chance to fix a typo ("actualy"), and proof that it's really just 
reusing code.



+*/
+   flags |= PIN_MAPPABLE;
+   ret = i915_vma_pin(vma, 0, 4096, flags);
+   if (ret)
+   goto err;


This will break GuC submission, the HWSP will be allocated correctly,

[ ] [drm:intel_engine_init_common [i915]] rcs0 hws offset: 0x1000
[ ] [drm:intel_engine_init_common [i915]] bcs0 hws offset: 0x2000
[ ] [drm:intel_engine_init_common [i915]] vcs0 hws offset: 0x3000
[ ] [drm:intel_engine_init_common [i915]] vcs1 hws offset: 0x4000
[ ] [drm:intel_engine_init_common [i915]] vecs0 hws offset: 0x5000

But these are below GUC_WOPCM_TOP (0x8), and our _beloved_ fw must 
be having problems accessing them, because this causes:


[ ] [drm:intel_guc_init_hw [i915]] GuC fw status: fetch SUCCESS, load 
PENDING

[ ] [drm:guc_ucode_xfer_dma [i915]] DMA status 0x10, GuC status 0x800071ec
[ ] [drm:guc_ucode_xfer_dma 

Re: [Intel-gfx] [RFC] drm/i915/lrc: allocate separate page for HWSP

[Chris Wilson]

Quoting Daniele Ceraolo Spurio (2017-07-06 17:10:40)
> On gen8+ we're currently using the PPHWSP of the kernel ctx as the
> global HWSP. However, when the kernel ctx gets submitted (e.g. from
> __intel_autoenable_gt_powersave) the HW will use that page as both
> HWSP and PPHWSP. Currently we're not seeing any problem because the
> conflict happens at offsets below 0x30 in an area we don't access,
> but that is not guaranteed to be true for future platform.
> 
> To avoid the conflict, instead of re-using the PPHWSP of the kernel
> ctx we can allocate a separate page for the HWSP like what happens for
> pre-execlists platform.

If there are no conflicts, then just skip the patch, and really there
shouldn't be since the writes we care about are ordered and the writes
we don't, we don't. We will need to move to per-context hwsp in the near
future which should alleviate these concerns.
-Chris
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Re: [Intel-gfx] [PATCH i-g-t 3/3] tests/gem_reset_stats: Enforce full chip reset mode before run

[Michel Thierry]

On 06/07/17 04:12, Arkadiusz Hiler wrote:

On Tue, Jun 20, 2017 at 11:25:02AM -0700, Michel Thierry wrote:

Platforms with per-engine reset enabled (i915.reset=2) are unlikely to
perform a full chip reset, keeping the reset_count unmodified. In order
to keep the expectations of this test, enforce that full GPU reset is
enabled (i915.reset=1).

Later on, we can expand the reset_stats ioctl to also return the number
of per-engine resets and use reset_count + reset_engine_count when
checking for the updated reset count.

Signed-off-by: Michel Thierry 


This no longer applies due to changes in the context. It would be nice
if you would send rebased version as well :-)


Hi Arek,

I think the v2 of these patches still apply cleanly,

https://patchwork.freedesktop.org/patch/164248/ and
https://patchwork.freedesktop.org/patch/164249/



@Antonio: any optionion on the patches? They LGTM, but an opinion of
someone more informed wouldn't hurt.



Indeed.

-Michel
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Re: [Intel-gfx] [PATCH] drm/i915/selftests: Exercise independence of per-engine resets

[Michel Thierry]

On 05/07/17 04:48, Chris Wilson wrote:

If all goes well, resetting one engine should not affect the operation of
any others. So to test this, we setup a continuous stream of requests
onto to each of the "innocent" engines whilst constantly resetting our
target engine.

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Michel Thierry 


Reviewed-by: Michel Thierry 


---
  drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 165 +++
  drivers/gpu/drm/i915/selftests/mock_context.c|   8 ++
  drivers/gpu/drm/i915/selftests/mock_context.h|   3 +
  3 files changed, 176 insertions(+)

diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c 
b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
index 7096c3911cd3..dbfcb31ba9f4 100644
--- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
@@ -22,8 +22,13 @@
   *
   */
  
+#include 

+
  #include "../i915_selftest.h"
  
+#include "mock_context.h"

+#include "mock_drm.h"
+
  struct hang {
struct drm_i915_private *i915;
struct drm_i915_gem_object *hws;
@@ -372,6 +377,165 @@ static int igt_reset_engine(void *arg)
return err;
  }
  
+static int active_engine(void *data)

+{
+   struct intel_engine_cs *engine = data;
+   struct drm_i915_gem_request *rq[2] = {};
+   struct i915_gem_context *ctx[2];
+   struct drm_file *file;
+   unsigned long count = 0;
+   int err = 0;
+
+   file = mock_file(engine->i915);
+   if (IS_ERR(file))
+   return PTR_ERR(file);
+
+   mutex_lock(>i915->drm.struct_mutex);
+   ctx[0] = live_context(engine->i915, file);
+   mutex_unlock(>i915->drm.struct_mutex);
+   if (IS_ERR(ctx[0])) {
+   err = PTR_ERR(ctx[0]);
+   goto err_file;
+   }
+
+   mutex_lock(>i915->drm.struct_mutex);
+   ctx[1] = live_context(engine->i915, file);
+   mutex_unlock(>i915->drm.struct_mutex);
+   if (IS_ERR(ctx[1])) {
+   err = PTR_ERR(ctx[1]);
+   i915_gem_context_put(ctx[0]);
+   goto err_file;
+   }
+
+   while (!kthread_should_stop()) {
+   unsigned int idx = count++ & 1;
+   struct drm_i915_gem_request *old = rq[idx];
+   struct drm_i915_gem_request *new;
+
+   mutex_lock(>i915->drm.struct_mutex);
+   new = i915_gem_request_alloc(engine, ctx[idx]);
+   if (IS_ERR(new)) {
+   mutex_unlock(>i915->drm.struct_mutex);
+   err = PTR_ERR(new);
+   break;
+   }
+
+   rq[idx] = i915_gem_request_get(new);
+   i915_add_request(new);
+   mutex_unlock(>i915->drm.struct_mutex);
+
+   if (old) {
+   i915_wait_request(old, 0, MAX_SCHEDULE_TIMEOUT);
+   i915_gem_request_put(old);
+   }
+   }
+
+   for (count = 0; count < ARRAY_SIZE(rq); count++)
+   i915_gem_request_put(rq[count]);
+
+err_file:
+   mock_file_free(engine->i915, file);
+   return err;
+}
+
+static int igt_reset_active_engines(void *arg)
+{
+   struct drm_i915_private *i915 = arg;
+   struct intel_engine_cs *engine, *active;
+   enum intel_engine_id id, tmp;
+   int err = 0;
+
+   /* Check that issuing a reset on one engine does not interfere
+* with any other engine.
+*/
+
+   if (!intel_has_reset_engine(i915))
+   return 0;
+
+   for_each_engine(engine, i915, id) {
+   struct task_struct *threads[I915_NUM_ENGINES];
+   unsigned long resets[I915_NUM_ENGINES];
+   unsigned long global = i915_reset_count(>gpu_error);
+   IGT_TIMEOUT(end_time);
+
+   memset(threads, 0, sizeof(threads));
+   for_each_engine(active, i915, tmp) {
+   struct task_struct *tsk;
+
+   if (active == engine)
+   continue;
+
+   resets[tmp] = i915_reset_engine_count(>gpu_error,
+ active);
+
+   tsk = kthread_run(active_engine, active,
+ "igt/%s", active->name);
+   if (IS_ERR(tsk)) {
+   err = PTR_ERR(tsk);
+   goto unwind;
+   }
+
+   threads[tmp] = tsk;
+   get_task_struct(tsk);
+
+   }
+
+   set_bit(I915_RESET_ENGINE + engine->id, >gpu_error.flags);
+   do {
+   err = i915_reset_engine(engine);
+   if (err) {
+   pr_err("i915_reset_engine(%s) failed, 

Re: [Intel-gfx] [PATCH] drm/i915: Disable per-engine reset for Broxton

[Michel Thierry]

On Thu, Jul 6, 2017 at 12:11 AM, Chris Wilson 
 wrote:

Quoting Michel Thierry (2017-07-06 02:24:26)

 On 04/07/17 09:09, Chris Wilson wrote:
 > Triggering a GPU reset for one engine affects another, notably
 > corrupting the context status buffer (CSB) effectively losing 
track of

 > inflight requests.
 >
 > Adding a few printks:
 > diff --git a/drivers/gpu/drm/i915/i915_drv.c 
b/drivers/gpu/drm/i915/i915_drv.c

 > index ad41836fa5e5..a969456bc0fa 100644
 > --- a/drivers/gpu/drm/i915/i915_drv.c
 > +++ b/drivers/gpu/drm/i915/i915_drv.c
 > @@ -1953,6 +1953,7 @@ int i915_reset_engine(struct 
intel_engine_cs *engine)

 > goto out;
 > }
 >
 > +   pr_err("Resetting %s\n", engine->name);
 > ret = intel_gpu_reset(engine->i915, 
intel_engine_flag(engine));

 > if (ret) {
 > /* If we fail here, we expect to fallback to a 
global reset */
 > diff --git a/drivers/gpu/drm/i915/intel_lrc.c 
b/drivers/gpu/drm/i915/intel_lrc.c

 > index 716e5c9ea222..a72bc35d0870 100644
 > --- a/drivers/gpu/drm/i915/intel_lrc.c
 > +++ b/drivers/gpu/drm/i915/intel_lrc.c
 > @@ -355,6 +355,7 @@ static void execlists_submit_ports(struct 
intel_engine_cs *engine)
 > 
execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN);

 > port_set([n], port_pack(rq, count));
 > desc = execlists_update_context(rq);
 > +   pr_err("%s: in (rq=%x) ctx=%d\n", 
engine->name, rq->global_seqno, upper_32_bits(desc));
 > GEM_DEBUG_EXEC(port[n].context_id = 
upper_32_bits(desc));

 > } else {
 > GEM_BUG_ON(!n);
 > @@ -594,9 +595,23 @@ static void intel_lrc_irq_handler(unsigned 
long data)
 > if (!(status & 
GEN8_CTX_STATUS_COMPLETED_MASK))

 > continue;
 >
 > +   pr_err("%s: out CSB (%x head=%d, 
tail=%d), ctx=%d, rq=%d\n",

 > +   engine->name,
 > +   readl(csb_mmio),
 > +   head, tail,
 > +   readl(buf+2*head+1),
 > +   port->context_id);
 > +
 > /* Check the context/desc id for this 
event matches */
 > -   GEM_DEBUG_BUG_ON(readl(buf + 2 * head + 
1) !=

 > -port->context_id);
 > +   if (readl(buf + 2 * head + 1) != 
port->context_id) {
 > +   pr_err("%s: BUG CSB (%x head=%d, 
tail=%d), ctx=%d, rq=%d\n",

 > +   engine->name,
 > +   readl(csb_mmio),
 > +   head, tail,
 > +   
readl(buf+2*head+1),

 > +   port->context_id);
 > +   BUG();
 > +   }
 >
 > rq = port_unpack(port, );
 > GEM_BUG_ON(count == 0);
 >
 > Results in:
 >
 > [ 6423.006602] Resetting rcs0
 > [ 6423.009080] rcs0: in (rq=fe70) ctx=1
 > [ 6423.009216] rcs0: in (rq=fe6f) ctx=3
 > [ 6423.009542] rcs0: out CSB (2 head=1, tail=2), ctx=3, rq=3
 > [ 6423.009619] Resetting bcs0
 > [ 6423.009980] rcs0: BUG CSB (0 head=1, tail=2), ctx=0, rq=3
 >
 
 It took me a while, but  I was able to replicate this (with your 
 igt_reset_active_engines) a couple of times. I also captured the 
value 
 of the CSB events at that point and it looked like this.


Ah, that's a separate issue that definitely isn't limited to bxt. In 
the

bug on my machine the CSB is distinctly zeroed.


Oh, if you saw them being zeroed, then there's not much I can argue (do 
you remember if the CSB write pointer was reset to '7' too?).


Hopefully is only limited to bxt, so sadly 


Reviewed-by: Michel Thierry 



 

 [   55.134393] Resetting rcs0
 [   55.134747] bcs0: BUG CSB (3 head=1, tail=2), ctx=10, rq=4
 [   55.134755]  bcs0: HWSP[16-17] Execlist CSB[0]:   0x0018 _ 
0x000a
 [   55.134759]  bcs0: HWSP[18-19] Execlist CSB[1]:   0x0012 _ 
0x000a
 [   55.134762]  bcs0: HWSP[20-21] Execlist CSB[2]:   0x8002 _ 
0x0004
 [   55.134765]  bcs0: HWSP[22-23] Execlist CSB[3]:   0x0014 _ 
0x0004
 [   55.134767]  bcs0: HWSP[24-25] Execlist CSB[4]:   0x0018 _ 
0x000a
 [   55.134770]  bcs0: HWSP[26-27] Execlist CSB[5]: 0x0001 _ 
0x
 
 The problem is ctx 10 finished in CSB[0] (ctx_complete & 
 active_to_idle), but then somehow CSB[1] has the same ctx 10 with 
 'preempted' & ctx_complete.
 
 To make things worse, in CSB[2], the hw claims to have 
lite-restored ctx 4.
 
 So it seems, we could ignore events like CSB[1], i.e. 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/lrc: allocate separate page for HWSP

[Patchwork]

== Series Details ==

Series: drm/i915/lrc: allocate separate page for HWSP
URL   : https://patchwork.freedesktop.org/series/26927/
State : success

== Summary ==

Series 26927v1 drm/i915/lrc: allocate separate page for HWSP
https://patchwork.freedesktop.org/api/1.0/series/26927/revisions/1/mbox/

Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-a:
dmesg-warn -> PASS   (fi-pnv-d510) fdo#101597 +1
Subgroup suspend-read-crc-pipe-b:
dmesg-warn -> PASS   (fi-byt-j1900) fdo#101705

fdo#101597 https://bugs.freedesktop.org/show_bug.cgi?id=101597
fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705

fi-bdw-5557u total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  
time:448s
fi-bdw-gvtdvmtotal:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  
time:428s
fi-blb-e6850 total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  
time:357s
fi-bsw-n3050 total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  
time:529s
fi-bxt-j4205 total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:511s
fi-byt-j1900 total:279  pass:255  dwarn:0   dfail:0   fail:0   skip:24  
time:497s
fi-byt-n2820 total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  
time:485s
fi-glk-2atotal:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  
time:590s
fi-hsw-4770  total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:435s
fi-hsw-4770r total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  
time:417s
fi-ilk-650   total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  
time:426s
fi-ivb-3520m total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:498s
fi-kbl-7500u total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  
time:462s
fi-kbl-7560u total:279  pass:268  dwarn:1   dfail:0   fail:0   skip:10  
time:566s
fi-kbl-r total:279  pass:260  dwarn:1   dfail:0   fail:0   skip:18  
time:574s
fi-pnv-d510  total:279  pass:222  dwarn:2   dfail:0   fail:0   skip:55  
time:559s
fi-skl-6260u total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:458s
fi-skl-6700hqtotal:279  pass:262  dwarn:0   dfail:0   fail:0   skip:17  
time:589s
fi-skl-6700k total:279  pass:257  dwarn:4   dfail:0   fail:0   skip:18  
time:462s
fi-skl-6770hqtotal:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  
time:487s
fi-skl-gvtdvmtotal:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  
time:434s
fi-snb-2520m total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  
time:533s
fi-snb-2600  total:279  pass:250  dwarn:0   dfail:0   fail:0   skip:29  
time:406s

13173bea86ebf8643a32b8373eeadd3fdcd1cc4d drm-tip: 2017y-07m-06d-14h-15m-52s UTC 
integration manifest
67f523e drm/i915/lrc: allocate separate page for HWSP

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_5127/
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[Intel-gfx] [PATCH i-g-t 0/7] igt: Add support for testing writeback connectors

[Liviu Dudau]

We're trying to introduce support for writeback connectors, a way to
expose in DRM the hardware functionality from display engines that
allows to write back into memory the result of the DE's composition
of supported planes.

Generic DRM support is available here [1] and will be merged once
this patchset gets approved for inclusion into igt. VC4 support
for writeback is added here [2] and for mali-dp is added here [3].

[1] https://lists.freedesktop.org/archives/dri-devel/2017-May/141796.html
[2] https://lists.freedesktop.org/archives/dri-devel/2017-June/143337.html
[3] https://lists.freedesktop.org/archives/dri-devel/2017-May/141799.html

Many thanks,
Liviu

Brian Starkey (7):
  igt: lib/igt_crc: Split out CRC functionality
  lib/igt_kms: Add writeback support in lib/
  kms_writeback: Add initial writeback tests
  lib: Add function to hash a framebuffer
  kms_writeback: Add writeback-check-output
  lib/igt_kms: Add igt_output_clone_pipe for cloning
  kms_writeback: Add tests using a cloned output

 lib/Makefile.sources  |   2 +
 lib/igt_aux.c |   1 +
 lib/igt_chamelium.h   |   1 +
 lib/igt_crc.c | 563 ++
 lib/igt_crc.h | 125 +
 lib/igt_debugfs.c | 547 
 lib/igt_debugfs.h |  81 --
 lib/igt_fb.c  |  65 +
 lib/igt_fb.h  |   5 +
 lib/igt_kms.c | 172 +---
 lib/igt_kms.h |  26 ++
 tests/Makefile.sources|   1 +
 tests/chamelium.c |   1 +
 tests/kms_atomic_transition.c |   1 +
 tests/kms_ccs.c   |   1 +
 tests/kms_chv_cursor_fail.c   |   1 +
 tests/kms_crtc_background_color.c |   1 +
 tests/kms_cursor_crc.c|   1 +
 tests/kms_cursor_legacy.c |   1 +
 tests/kms_draw_crc.c  |   1 +
 tests/kms_fbc_crc.c   |   1 +
 tests/kms_flip_tiling.c   |   1 +
 tests/kms_frontbuffer_tracking.c  |   1 +
 tests/kms_mmap_write_crc.c|   1 +
 tests/kms_mmio_vs_cs_flip.c   |   1 +
 tests/kms_pipe_color.c|   1 +
 tests/kms_pipe_crc_basic.c|   1 +
 tests/kms_plane.c |   1 +
 tests/kms_plane_lowres.c  |   1 +
 tests/kms_plane_multiple.c|   1 +
 tests/kms_plane_scaling.c |   1 +
 tests/kms_pwrite_crc.c|   1 +
 tests/kms_rotation_crc.c  |   1 +
 tests/kms_universal_plane.c   |   1 +
 tests/kms_writeback.c | 541 
 tools/intel_display_crc.c |   1 +
 36 files changed, 1487 insertions(+), 666 deletions(-)
 create mode 100644 lib/igt_crc.c
 create mode 100644 lib/igt_crc.h
 create mode 100644 tests/kms_writeback.c

-- 
2.13.1

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[Intel-gfx] [PATCH i-g-t 5/7] kms_writeback: Add writeback-check-output

[Liviu Dudau]

From: Brian Starkey 

Add a test which makes commits using the writeback connector, and
checks the output buffer hash to make sure it is/isn't written as
appropriate.

Signed-off-by: Brian Starkey 
Signed-off-by: Liviu Dudau 

---
 tests/kms_writeback.c | 123 ++
 1 file changed, 123 insertions(+)

diff --git a/tests/kms_writeback.c b/tests/kms_writeback.c
index d2066482..8201a81c 100644
--- a/tests/kms_writeback.c
+++ b/tests/kms_writeback.c
@@ -29,6 +29,7 @@
 
 #include "igt.h"
 #include "igt_fb.h"
+#include "sw_sync.h"
 
 /* We need to define these ourselves until we get an updated libdrm */
 #ifndef DRM_MODE_CONNECTOR_WRITEBACK
@@ -278,6 +279,115 @@ static void writeback_fb_id(igt_output_t *output, 
igt_fb_t *valid_fb, igt_fb_t *
igt_assert(ret == 0);
 }
 
+static void fill_fb(igt_fb_t *fb, double color[3])
+{
+   cairo_t *cr = igt_get_cairo_ctx(fb->fd, fb);
+   igt_assert(cr);
+
+   igt_paint_color(cr, 0, 0, fb->width, fb->height,
+   color[0], color[1], color[2]);
+}
+
+static void get_and_wait_out_fence(igt_output_t *output)
+{
+   int ret, out_fence = out_fence = 
igt_output_get_last_writeback_out_fence(output);
+   igt_assert(out_fence >= 0);
+
+   ret = sync_fence_wait(out_fence, 1000);
+   igt_assert(ret == 0);
+   close(out_fence);
+}
+
+static void writeback_seqence(igt_output_t *output, igt_plane_t *plane,
+ igt_fb_t *in_fb, igt_fb_t *out_fbs[], int 
n_commits)
+{
+   int i, color_idx = 0;
+   double in_fb_colors[2][3] = {
+   { 1.0, 0.0, 0.0 },
+   { 0.0, 1.0, 0.0 },
+   };
+   double clear_color[3] = { 1.0, 1.0, 1.0 };
+   igt_crc_t cleared_crc, out_expected;
+
+   for (i = 0; i < n_commits; i++, color_idx++) {
+   /* Change the input color each time */
+   fill_fb(in_fb, in_fb_colors[color_idx % 2]);
+
+   if (out_fbs[i]) {
+   igt_crc_t out_before;
+
+   /* Get the expected CRC */
+   fill_fb(out_fbs[i], in_fb_colors[color_idx % 2]);
+   igt_fb_get_crc(out_fbs[i], _expected);
+
+   fill_fb(out_fbs[i], clear_color);
+   if (i == 0)
+   igt_fb_get_crc(out_fbs[i], _crc);
+   igt_fb_get_crc(out_fbs[i], _before);
+   igt_assert_crc_equal(_crc, _before);
+   }
+
+   /* Commit */
+   igt_plane_set_fb(plane, in_fb);
+   igt_output_set_writeback_fb(output, out_fbs[i]);
+   if (out_fbs[i])
+   igt_output_request_writeback_out_fence(output);
+   igt_display_commit_atomic(output->display,
+ DRM_MODE_ATOMIC_ALLOW_MODESET,
+ NULL);
+   if (out_fbs[i])
+   get_and_wait_out_fence(output);
+
+   /* Make sure the old output buffer is untouched */
+   if (i > 0 && out_fbs[i - 1] && (out_fbs[i] != out_fbs[i - 1])) {
+   igt_crc_t out_prev;
+   igt_fb_get_crc(out_fbs[i - 1], _prev);
+   igt_assert_crc_equal(_crc, _prev);
+   }
+
+   /* Make sure this output buffer is written */
+   if (out_fbs[i]) {
+   igt_crc_t out_after;
+   igt_fb_get_crc(out_fbs[i], _after);
+   igt_assert_crc_equal(_expected, _after);
+
+   /* And clear it, for the next time */
+   fill_fb(out_fbs[i], clear_color);
+   }
+   }
+}
+
+static void writeback_check_output(igt_output_t *output, igt_plane_t *plane,
+  igt_fb_t *input_fb, igt_fb_t *output_fb)
+{
+   igt_fb_t *out_fbs[2] = { 0 };
+   igt_fb_t second_out_fb;
+   int ret;
+
+   /* One commit, with a writeback. */
+   writeback_seqence(output, plane, input_fb, _fb, 1);
+
+   /* Two commits, the second with no writeback */
+   out_fbs[0] = output_fb;
+   writeback_seqence(output, plane, input_fb, out_fbs, 2);
+
+   /* Two commits, both with writeback */
+   out_fbs[1] = output_fb;
+   writeback_seqence(output, plane, input_fb, out_fbs, 2);
+
+   ret = igt_create_fb(output_fb->fd, output_fb->width, output_fb->height,
+   DRM_FORMAT_XRGB,
+   igt_fb_mod_to_tiling(0),
+   _out_fb);
+   igt_require(ret > 0);
+
+   /* Two commits, with different writeback buffers */
+   out_fbs[1] = _out_fb;
+   writeback_seqence(output, plane, input_fb, out_fbs, 2);
+
+   igt_remove_fb(output_fb->fd, _out_fb);
+}
+
 igt_main
 {
  

[Intel-gfx] [PATCH i-g-t 2/7] lib/igt_kms: Add writeback support in lib/

[Liviu Dudau]

From: Brian Starkey 

Add support in igt_kms for Writeback connectors, with the ability to
attach framebuffers and retrieve fences.

Signed-off-by: Brian Starkey 
Signed-off-by: Liviu Dudau 

---
 lib/igt_aux.c |  1 +
 lib/igt_kms.c | 76 ++-
 lib/igt_kms.h | 16 +
 3 files changed, 92 insertions(+), 1 deletion(-)

diff --git a/lib/igt_aux.c b/lib/igt_aux.c
index 882dba06..945c1248 100644
--- a/lib/igt_aux.c
+++ b/lib/igt_aux.c
@@ -1087,6 +1087,7 @@ static const struct type_name connector_type_names[] = {
{ DRM_MODE_CONNECTOR_eDP, "eDP" },
{ DRM_MODE_CONNECTOR_VIRTUAL, "Virtual" },
{ DRM_MODE_CONNECTOR_DSI, "DSI" },
+   { DRM_MODE_CONNECTOR_WRITEBACK, "Writeback" },
{}
 };
 
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index faf9df2f..c86a2a63 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -186,7 +186,10 @@ const char *igt_crtc_prop_names[IGT_NUM_CRTC_PROPS] = {
 
 const char *igt_connector_prop_names[IGT_NUM_CONNECTOR_PROPS] = {
"scaling mode",
-   "CRTC_ID"
+   "CRTC_ID",
+   "WRITEBACK_PIXEL_FORMATS",
+   "WRITEBACK_FB_ID",
+   "WRITEBACK_OUT_FENCE_PTR"
 };
 
 /*
@@ -1831,6 +1834,7 @@ void igt_display_init(igt_display_t *display, int drm_fd)
output->pending_crtc_idx_mask = 0;
output->id = resources->connectors[i];
output->display = display;
+   output->writeback_out_fence_fd = -1;
 
igt_output_refresh(output);
 
@@ -1898,6 +1902,42 @@ igt_output_t *igt_output_from_connector(igt_display_t 
*display,
return found;
 }
 
+void igt_output_set_writeback_fb(igt_output_t *output, struct igt_fb *fb)
+{
+   igt_display_t *display = output->display;
+   struct kmstest_connector_config *config = >config;
+
+   if (config->connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK)
+   return;
+
+   LOG(display, "%s: output_set_writeback_fb(%d)\n", output->name,
+   fb ? fb->fb_id : 0);
+
+   output->writeback_fb = fb;
+}
+
+static void igt_output_reset_writeback_out_fence(igt_output_t *output)
+{
+   if (output->writeback_out_fence_fd >= 0) {
+   close(output->writeback_out_fence_fd);
+   output->writeback_out_fence_fd = -1;
+   }
+}
+
+void igt_output_request_writeback_out_fence(igt_output_t *output)
+{
+   igt_output_reset_writeback_out_fence(output);
+   output->writeback_out_fence_requested = true;
+}
+
+int igt_output_get_last_writeback_out_fence(igt_output_t *output)
+{
+   int fd = output->writeback_out_fence_fd;
+   output->writeback_out_fence_fd = -1;
+
+   return fd;
+}
+
 static void igt_pipe_fini(igt_pipe_t *pipe)
 {
int i;
@@ -1918,6 +1958,8 @@ static void igt_pipe_fini(igt_pipe_t *pipe)
 static void igt_output_fini(igt_output_t *output)
 {
kmstest_free_connector_config(>config);
+   if (output->writeback_out_fence_fd >= 0)
+   close(output->writeback_out_fence_fd);
free(output->name);
output->name = NULL;
 }
@@ -2534,10 +2576,41 @@ static void 
igt_atomic_prepare_connector_commit(igt_output_t *output, drmModeAto
 
igt_atomic_populate_connector_req(req, output, 
IGT_CONNECTOR_CRTC_ID, crtc_id);
}
+
+   if (output->writeback_fb) {
+   igt_atomic_populate_connector_req(req, output, 
IGT_CONNECTOR_WRITEBACK_FB_ID, output->writeback_fb->fb_id);
+   output->writeback_fb = NULL;
+   }
+
+   igt_output_reset_writeback_out_fence(output);
+   if (output->writeback_out_fence_requested) {
+   igt_atomic_populate_connector_req(req, output, 
IGT_CONNECTOR_WRITEBACK_OUT_FENCE_PTR,
+ 
(uint64_t)(uintptr_t)>writeback_out_fence_fd);
+   }
+
/*
 *  TODO: Add all other connector level properties here
 */
+}
+
+static void handle_writeback_out_fences(igt_display_t *display, uint32_t 
flags, int ret)
+{
+   int i;
 
+   for (i = 0; i < display->n_outputs; i++) {
+   igt_output_t *output = >outputs[i];
+
+   if (!output->config.connector)
+   continue;
+
+   if (!output->writeback_out_fence_requested)
+   continue;
+
+   output->writeback_out_fence_requested = false;
+
+   if (ret || (flags & DRM_MODE_ATOMIC_TEST_ONLY))
+   igt_assert(output->writeback_out_fence_fd == -1);
+   }
 }
 
 /*
@@ -2586,6 +2659,7 @@ static int igt_atomic_commit(igt_display_t *display, 
uint32_t flags, void *user_
}
 
ret = drmModeAtomicCommit(display->drm_fd, req, flags, user_data);
+   handle_writeback_out_fences(display, flags, ret);
if (!ret) {
 
for_each_pipe(display, pipe) {
diff --git a/lib/igt_kms.h 

[Intel-gfx] [PATCH i-g-t 3/7] kms_writeback: Add initial writeback tests

[Liviu Dudau]

From: Brian Starkey 

Add tests for the WRITEBACK_PIXEL_FORMATS, WRITEBACK_OUT_FENCE_PTR and
WRITEBACK_FB_ID properties on writeback connectors, ensuring their
behaviour is correct.

Signed-off-by: Brian Starkey 
Signed-off-by: Liviu Dudau 

---
 lib/igt_kms.c  |   6 +-
 lib/igt_kms.h  |   7 +
 tests/Makefile.sources |   1 +
 tests/kms_writeback.c  | 371 +
 4 files changed, 382 insertions(+), 3 deletions(-)
 create mode 100644 tests/kms_writeback.c

diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index c86a2a63..de50d421 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -2133,7 +2133,7 @@ static uint32_t igt_plane_get_fb_gem_handle(igt_plane_t 
*plane)
 /*
  * Add position and fb changes of a plane to the atomic property set
  */
-static void
+void
 igt_atomic_prepare_plane_commit(igt_plane_t *plane, igt_pipe_t *pipe,
drmModeAtomicReq *req)
 {
@@ -2511,7 +2511,7 @@ igt_pipe_replace_blob(igt_pipe_t *pipe, uint64_t *blob, 
void *ptr, size_t length
 /*
  * Add crtc property changes to the atomic property set
  */
-static void igt_atomic_prepare_crtc_commit(igt_pipe_t *pipe_obj, 
drmModeAtomicReq *req)
+void igt_atomic_prepare_crtc_commit(igt_pipe_t *pipe_obj, drmModeAtomicReq 
*req)
 {
if (pipe_obj->background_changed)
igt_atomic_populate_crtc_req(req, pipe_obj, 
IGT_CRTC_BACKGROUND, pipe_obj->background);
@@ -2560,7 +2560,7 @@ static void igt_atomic_prepare_crtc_commit(igt_pipe_t 
*pipe_obj, drmModeAtomicRe
 /*
  * Add connector property changes to the atomic property set
  */
-static void igt_atomic_prepare_connector_commit(igt_output_t *output, 
drmModeAtomicReq *req)
+void igt_atomic_prepare_connector_commit(igt_output_t *output, 
drmModeAtomicReq *req)
 {
 
struct kmstest_connector_config *config = >config;
diff --git a/lib/igt_kms.h b/lib/igt_kms.h
index ce9a35ef..ab8ec764 100644
--- a/lib/igt_kms.h
+++ b/lib/igt_kms.h
@@ -533,6 +533,8 @@ static inline bool igt_output_is_connected(igt_output_t 
*output)
 #define igt_atomic_populate_plane_req(req, plane, prop, value) \
igt_assert_lt(0, drmModeAtomicAddProperty(req, 
plane->drm_plane->plane_id,\
  
plane->atomic_props_plane[prop], value))
+void igt_atomic_prepare_plane_commit(igt_plane_t *plane, igt_pipe_t *pipe,
+   drmModeAtomicReq *req);
 
 /**
  * igt_atomic_populate_crtc_req:
@@ -544,6 +546,9 @@ static inline bool igt_output_is_connected(igt_output_t 
*output)
 #define igt_atomic_populate_crtc_req(req, pipe, prop, value) \
igt_assert_lt(0, drmModeAtomicAddProperty(req, pipe->crtc_id,\
  
pipe->atomic_props_crtc[prop], value))
+
+void igt_atomic_prepare_crtc_commit(igt_pipe_t *pipe_obj, drmModeAtomicReq 
*req);
+
 /**
  * igt_atomic_populate_connector_req:
  * @req: A pointer to drmModeAtomicReq
@@ -555,6 +560,8 @@ static inline bool igt_output_is_connected(igt_output_t 
*output)
igt_assert_lt(0, drmModeAtomicAddProperty(req, 
output->config.connector->connector_id,\
  
output->config.atomic_props_connector[prop], value))
 
+void igt_atomic_prepare_connector_commit(igt_output_t *output, 
drmModeAtomicReq *req);
+
 void igt_enable_connectors(void);
 void igt_reset_connectors(void);
 
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 5b98a5a3..7318855d 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -213,6 +213,7 @@ TESTS_progs = \
kms_tv_load_detect \
kms_universal_plane \
kms_vblank \
+   kms_writeback \
meta_test \
perf \
pm_backlight \
diff --git a/tests/kms_writeback.c b/tests/kms_writeback.c
new file mode 100644
index ..d2066482
--- /dev/null
+++ b/tests/kms_writeback.c
@@ -0,0 +1,371 @@
+/*
+ * (C) COPYRIGHT 2017 ARM Limited. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF 

[Intel-gfx] [PATCH i-g-t 7/7] kms_writeback: Add tests using a cloned output

[Liviu Dudau]

From: Brian Starkey 

Update the connector search to also optionally attempt to find a
non-writeback connector to clone to.

Add a subtest which is the same as writeback-check-output, but also
clones to the second connector.

Signed-off-by: Brian Starkey 
Signed-off-by: Liviu Dudau 

---
 tests/kms_writeback.c | 63 ---
 1 file changed, 55 insertions(+), 8 deletions(-)

diff --git a/tests/kms_writeback.c b/tests/kms_writeback.c
index 8201a81c..9a34bca0 100644
--- a/tests/kms_writeback.c
+++ b/tests/kms_writeback.c
@@ -81,7 +81,8 @@ static uint32_t pick_writeback_format(igt_output_t *output)
return format;
 }
 
-static bool check_writeback_config(igt_display_t *display, igt_output_t 
*output)
+static bool check_writeback_config(igt_display_t *display, igt_output_t 
*output,
+  int pipe, igt_output_t **clone)
 {
igt_fb_t input_fb, output_fb;
igt_plane_t *plane;
@@ -123,6 +124,27 @@ static bool check_writeback_config(igt_display_t *display, 
igt_output_t *output)
 
ret = igt_display_try_commit_atomic(display, DRM_MODE_ATOMIC_TEST_ONLY |
DRM_MODE_ATOMIC_ALLOW_MODESET, 
NULL);
+   if (!ret && clone) {
+   /* Try and find a clone */
+   int i, newret;
+   *clone = NULL;
+
+   for (i = 0; i < display->n_outputs; i++) {
+   igt_output_t *second_output = >outputs[i];
+   if (output != second_output &&
+   igt_pipe_connector_valid(pipe, second_output)) {
+
+   igt_output_clone_pipe(second_output, pipe);
+   newret = igt_display_try_commit_atomic(display, 
DRM_MODE_ATOMIC_TEST_ONLY |
+   
DRM_MODE_ATOMIC_ALLOW_MODESET, NULL);
+   igt_output_set_pipe(second_output, PIPE_NONE);
+   if (!newret) {
+   *clone = second_output;
+   break;
+   }
+   }
+   }
+   }
igt_plane_set_fb(plane, NULL);
igt_remove_fb(display->drm_fd, _fb);
igt_remove_fb(display->drm_fd, _fb);
@@ -130,7 +152,8 @@ static bool check_writeback_config(igt_display_t *display, 
igt_output_t *output)
return !ret;
 }
 
-static igt_output_t *kms_writeback_get_output(igt_display_t *display)
+static igt_output_t *kms_writeback_get_output(igt_display_t *display, enum 
pipe *pipe,
+ igt_output_t **clone)
 {
int i;
 
@@ -146,10 +169,16 @@ static igt_output_t 
*kms_writeback_get_output(igt_display_t *display)
for (j = 0; j < igt_display_get_n_pipes(display); j++) {
igt_output_set_pipe(output, j);
 
-   if (check_writeback_config(display, output)) {
+   if (check_writeback_config(display, output, j, clone)) {
igt_debug("Using connector %u:%s on pipe %d\n",
  
output->config.connector->connector_id,
  output->name, j);
+   if (clone && *clone)
+   igt_debug("Cloning to connector 
%u:%s\n",
+ 
(*clone)->config.connector->connector_id,
+ (*clone)->name);
+   if (pipe)
+   *pipe = j;
return output;
}
}
@@ -190,9 +219,6 @@ static int do_writeback_test(igt_output_t *output, uint32_t 
flags,
igt_pipe_t *pipe_obj = >pipes[pipe];
igt_plane_t *plane;
 
-   /*
-* Add CRTC Properties to the property set
-*/
igt_atomic_prepare_crtc_commit(pipe_obj, req);
 
for_each_plane_on_pipe(display, pipe, plane) {
@@ -391,10 +417,11 @@ static void writeback_check_output(igt_output_t *output, 
igt_plane_t *plane,
 igt_main
 {
igt_display_t display;
-   igt_output_t *output;
+   igt_output_t *output, *clone;
igt_plane_t *plane;
igt_fb_t input_fb;
drmModeModeInfo mode;
+   enum pipe pipe;
int ret;
 
memset(, 0, sizeof(display));
@@ -409,7 +436,7 @@ igt_main
 
igt_require(display.is_atomic);
 
-   output = kms_writeback_get_output();
+   output = kms_writeback_get_output(, , );
igt_require(output);
 
if (output->use_override_mode)
@@ -487,6 +514,26 @@ igt_main