[Intel-gfx] ✓ Fi.CI.BAT: success for GuC Fixes and change for v9+ Firmwares

[Patchwork]

== Series Details ==

Series: GuC Fixes and change for v9+ Firmwares
URL   : https://patchwork.freedesktop.org/series/29651/
State : success

== Summary ==

Series 29651v1 GuC Fixes and change for v9+ Firmwares
https://patchwork.freedesktop.org/api/1.0/series/29651/revisions/1/mbox/

Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
pass   -> FAIL   (fi-snb-2600) fdo#100215 +1
Subgroup basic-flip-after-cursor-varying-size:
fail   -> PASS   (fi-hsw-4770) fdo#102402 +1

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#102402 https://bugs.freedesktop.org/show_bug.cgi?id=102402

fi-bdw-5557u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:461s
fi-bdw-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:444s
fi-blb-e6850 total:288  pass:224  dwarn:1   dfail:0   fail:0   skip:63  
time:360s
fi-bsw-n3050 total:288  pass:243  dwarn:0   dfail:0   fail:0   skip:45  
time:557s
fi-bwr-2160  total:288  pass:184  dwarn:0   dfail:0   fail:0   skip:104 
time:253s
fi-bxt-j4205 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:526s
fi-byt-j1900 total:288  pass:254  dwarn:1   dfail:0   fail:0   skip:33  
time:522s
fi-byt-n2820 total:288  pass:250  dwarn:1   dfail:0   fail:0   skip:37  
time:514s
fi-elk-e7500 total:288  pass:230  dwarn:0   dfail:0   fail:0   skip:58  
time:431s
fi-glk-2atotal:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:614s
fi-hsw-4770  total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  
time:458s
fi-hsw-4770r total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  
time:425s
fi-ilk-650   total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:423s
fi-ivb-3520m total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:505s
fi-ivb-3770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:474s
fi-kbl-7500u total:288  pass:264  dwarn:1   dfail:0   fail:0   skip:23  
time:515s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:599s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:598s
fi-pnv-d510  total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:525s
fi-skl-6260u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:473s
fi-skl-6700k total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:532s
fi-skl-6770hqtotal:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:501s
fi-skl-gvtdvmtotal:288  pass:266  dwarn:0   dfail:0   fail:0   skip:22  
time:441s
fi-skl-x1585ltotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:486s
fi-snb-2520m total:288  pass:251  dwarn:0   dfail:0   fail:0   skip:37  
time:549s
fi-snb-2600  total:288  pass:249  dwarn:0   dfail:0   fail:1   skip:38  
time:404s

ccf4ca2d93383fe1a234aba83df9c21400216433 drm-tip: 2017y-08m-31d-18h-37m-46s UTC 
integration manifest
4599587b12e5 drm/i915/guc: Enable default/critical logging in GuC by default 
from GuC v9
d4e54028 drm/i915/guc: Fix GuC HW/SW state cleanup in unload path
9b7ae898972f drm/i915/guc: Fix GuC interaction in reset/suspend scenarios
31f4b546abf3 drm/i915: Separate GuC/HuC specific functionality from intel_uc

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5556/
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[Intel-gfx] [PATCH 4/4] drm/i915/guc: Enable default/critical logging in GuC by default from GuC v9

[Sagar Arun Kamble]

With GuC v9, new type of Default/critical logging in GuC to enable
capturing minimal important logs in production systems efficiently.
This patch enables this logging in GuC by default always. It should
be noted that streaming support with half-full interrupt mechanism
that is present for normal logging is not present for this type of
logging.

v2: Emulating GuC critical logging through i915.guc_log_level. Setting
this to 0 will make GuC critical logging ON and setting it to 1-4 will
communicate log level of 0-3 to GuC.

v3: Commit message update. Enable default/critical logging in GuC always.
Fixed RPM wake during guc_log_unregister in the unload path.

Cc: Chheda Harsh J 
Cc: Fry Gregory P 
Cc: Arkadiusz Hiler 
Cc: Spotswood John A 
Cc: Anusha Srivatsa 
Signed-off-by: Jeff McGee 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/intel_guc_fwif.h   | 14 +-
 drivers/gpu/drm/i915/intel_guc_loader.c | 10 ++
 drivers/gpu/drm/i915/intel_guc_log.c|  7 ++-
 3 files changed, 29 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h 
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 5fa2860..353b081 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -132,6 +132,7 @@
 #define   GUC_WQ_TRACK_ENABLED (1 << 8)
 #define   GUC_ADS_ENABLED  (1 << 9)
 #define   GUC_DEBUG_RESERVED   (1 << 10)
+#define   GUC_V9_CRITICAL_LOGGING_DISABLED (1 << 10)
 #define   GUC_ADS_ADDR_SHIFT   11
 #define   GUC_ADS_ADDR_MASK0xf800
 
@@ -139,6 +140,16 @@
 
 #define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2) /* [1..14] */
 
+/*
+ * Critical logging in GuC is to be enabled always from GuC v9+.
+ * (for KBL - v9.39+)
+ */
+#define NEEDS_GUC_CRITICAL_LOGGING(dev_priv, guc_fw)   \
+   (((IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv)) && \
+   guc_fw->major_ver_found >= 9) || \
+ (IS_KABYLAKE(dev_priv) && guc_fw->major_ver_found >= 9 && \
+   guc_fw->minor_ver_found >= 39))
+
 /**
  * DOC: GuC Firmware Layout
  *
@@ -539,7 +550,8 @@ struct guc_log_buffer_state {
u32 logging_enabled:1;
u32 reserved1:3;
u32 verbosity:4;
-   u32 reserved2:24;
+   u32 critical_logging_enabled:1;
+   u32 reserved2:23;
};
u32 value;
 } __packed;
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c 
b/drivers/gpu/drm/i915/intel_guc_loader.c
index 81e03a6..d2b027c 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -106,6 +106,7 @@ static u32 get_core_family(struct drm_i915_private 
*dev_priv)
 static void guc_params_init(struct drm_i915_private *dev_priv)
 {
struct intel_guc *guc = _priv->guc;
+   struct intel_uc_fw *guc_fw = _priv->guc.fw;
u32 params[GUC_CTL_MAX_DWORDS];
int i;
 
@@ -136,6 +137,15 @@ static void guc_params_init(struct drm_i915_private 
*dev_priv)
} else
params[GUC_CTL_DEBUG] = GUC_LOG_DISABLED;
 
+   /*
+* GuC has critical/default logging level which is to be enabled
+* always from GuC v9 onwards.
+*/
+   if (NEEDS_GUC_CRITICAL_LOGGING(dev_priv, guc_fw)) {
+   params[GUC_CTL_DEBUG] &=
+   ~GUC_V9_CRITICAL_LOGGING_DISABLED;
+   }
+
/* If GuC submission is enabled, set up additional parameters here */
if (i915.enable_guc_submission) {
u32 ads = guc_ggtt_offset(guc->ads_vma) >> PAGE_SHIFT;
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c
index 16d3b87..6877e34 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -589,7 +589,7 @@ void intel_guc_log_destroy(struct intel_guc *guc)
 int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val)
 {
struct intel_guc *guc = _priv->guc;
-
+   struct intel_uc_fw *guc_fw = _priv->guc.fw;
union guc_log_control log_param;
int ret;
 
@@ -603,6 +603,9 @@ int i915_guc_log_control(struct drm_i915_private *dev_priv, 
u64 control_val)
if (!log_param.logging_enabled && (i915.guc_log_level < 0))
return 0;
 
+   if (NEEDS_GUC_CRITICAL_LOGGING(dev_priv, guc_fw))
+   log_param.critical_logging_enabled = 1;
+
ret = guc_log_control(guc, log_param.value);
if (ret < 0) {
DRM_DEBUG_DRIVER("guc_logging_control action failed %d\n", ret);
@@ -655,8 +658,10 @@ void i915_guc_log_unregister(struct drm_i915_private 
*dev_priv)
return;
 
mutex_lock(_priv->drm.struct_mutex);
+   

[Intel-gfx] [PATCH 3/4] drm/i915/guc: Fix GuC HW/SW state cleanup in unload path

[Sagar Arun Kamble]

Teardown of GuC HW/SW state was not properly done in unload path.
During unload, we can rely on intel_guc_reset_prepare being done
as part of i915_gem_suspend for disabling GuC interfaces.
We will have to disable GuC submission prior to suspend as that involves
communication with GuC to destroy doorbell. So intel_uc_fini_hw has to
be called as part of i915_gem_suspend during unload as that really
takes care of finishing the GuC operations. Created new parameter for
i915_gem_suspend to handle unload/suspend path w.r.t gem and GuC suspend.
GuC related allocations are cleaned up as part of intel_uc_cleanup_hw.

v2: Prepared i915_gem_unload. (Michal)

Cc: Chris Wilson 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_drv.c|  6 +--
 drivers/gpu/drm/i915/i915_drv.h|  1 +
 drivers/gpu/drm/i915/i915_gem.c| 79 ++
 drivers/gpu/drm/i915/intel_guc.c   | 13 ++
 drivers/gpu/drm/i915/intel_guc.h   |  1 +
 drivers/gpu/drm/i915/intel_uc.c| 14 +++---
 drivers/gpu/drm/i915/intel_uc_common.h |  1 +
 7 files changed, 103 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index b2e8f95..b6cc2fe 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -601,7 +601,7 @@ static void i915_gem_fini(struct drm_i915_private *dev_priv)
i915_gem_drain_workqueue(dev_priv);
 
mutex_lock(_priv->drm.struct_mutex);
-   intel_uc_fini_hw(dev_priv);
+   intel_uc_cleanup_hw(dev_priv);
i915_gem_cleanup_engines(dev_priv);
i915_gem_contexts_fini(dev_priv);
i915_gem_cleanup_userptr(dev_priv);
@@ -682,7 +682,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
return 0;
 
 cleanup_gem:
-   if (i915_gem_suspend(dev_priv))
+   if (i915_gem_unload(dev_priv))
DRM_ERROR("failed to idle hardware; continuing to unload!\n");
i915_gem_fini(dev_priv);
 cleanup_uc:
@@ -1375,7 +1375,7 @@ void i915_driver_unload(struct drm_device *dev)
 
i915_driver_unregister(dev_priv);
 
-   if (i915_gem_suspend(dev_priv))
+   if (i915_gem_unload(dev_priv))
DRM_ERROR("failed to idle hardware; continuing to unload!\n");
 
intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 064bf0f..570e71e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3628,6 +3628,7 @@ void i915_gem_reset_engine(struct intel_engine_cs *engine,
 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
   unsigned int flags);
 int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
+int __must_check i915_gem_unload(struct drm_i915_private *dev_priv);
 void i915_gem_resume(struct drm_i915_private *dev_priv);
 int i915_gem_fault(struct vm_fault *vmf);
 int i915_gem_object_wait(struct drm_i915_gem_object *obj,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 977500f..24cefe9 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4624,6 +4624,85 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
return ret;
 }
 
+int i915_gem_unload(struct drm_i915_private *dev_priv)
+{
+   struct drm_device *dev = _priv->drm;
+   int ret;
+
+   intel_runtime_pm_get(dev_priv);
+   intel_suspend_gt_powersave(dev_priv);
+
+   mutex_lock(>struct_mutex);
+
+   /* We have to flush all the executing contexts to main memory so
+* that they can saved in the hibernation image. To ensure the last
+* context image is coherent, we have to switch away from it. That
+* leaves the dev_priv->kernel_context still active when
+* we actually suspend, and its image in memory may not match the GPU
+* state. Fortunately, the kernel_context is disposable and we do
+* not rely on its state.
+*/
+   ret = i915_gem_switch_to_kernel_context(dev_priv);
+   if (ret)
+   goto err_unlock;
+
+   ret = i915_gem_wait_for_idle(dev_priv,
+I915_WAIT_INTERRUPTIBLE |
+I915_WAIT_LOCKED);
+   if (ret)
+   goto err_unlock;
+
+   assert_kernel_context_is_current(dev_priv);
+   i915_gem_contexts_lost(dev_priv);
+   mutex_unlock(>struct_mutex);
+
+   cancel_delayed_work_sync(_priv->gpu_error.hangcheck_work);
+   cancel_delayed_work_sync(_priv->gt.retire_work);
+
+   /* As the idle_work is rearming if it detects a race, play safe and
+* repeat the flush until it is definitely idle.
+*/
+   while 

[Intel-gfx] [PATCH 0/4] GuC Fixes and change for v9+ Firmwares

[Sagar Arun Kamble]

This series fixes bugs in suspend/unload/reset path with GuC enabled.
With v9+ firmware new type of fast (Default/Critical) logging is to
be enabled by default. A patch enables that logging by default.
Once GuC v9+ firmwares are posted to 01.org, change to update the
default firmware version and if needed change to enabled GuC submission
will be added later.

Cc: Spotswood John A 
Cc: Anusha Srivatsa 
Cc: Michał Winiarski 

Sagar Arun Kamble (4):
  drm/i915: Separate GuC/HuC specific functionality from intel_uc
  drm/i915/guc: Fix GuC interaction in reset/suspend scenarios
  drm/i915/guc: Fix GuC HW/SW state cleanup in unload path
  drm/i915/guc: Enable default/critical logging in GuC by default from
GuC v9

 drivers/gpu/drm/i915/Makefile  |   1 +
 drivers/gpu/drm/i915/i915_drv.c|  13 +-
 drivers/gpu/drm/i915/i915_drv.h|   1 +
 drivers/gpu/drm/i915/i915_gem.c|  85 ++-
 drivers/gpu/drm/i915/i915_guc_submission.c |  53 -
 drivers/gpu/drm/i915/intel_guc.c   | 358 +
 drivers/gpu/drm/i915/intel_guc.h   | 206 +
 drivers/gpu/drm/i915/intel_guc_fwif.h  |  14 +-
 drivers/gpu/drm/i915/intel_guc_loader.c|  11 +-
 drivers/gpu/drm/i915/intel_guc_log.c   |   7 +-
 drivers/gpu/drm/i915/intel_huc.c   |  50 +---
 drivers/gpu/drm/i915/intel_huc.h   |  38 +++
 drivers/gpu/drm/i915/intel_uc.c| 169 ++
 drivers/gpu/drm/i915/intel_uc.h| 254 +---
 drivers/gpu/drm/i915/intel_uc_common.h | 102 
 15 files changed, 843 insertions(+), 519 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_guc.c
 create mode 100644 drivers/gpu/drm/i915/intel_guc.h
 create mode 100644 drivers/gpu/drm/i915/intel_huc.h
 create mode 100644 drivers/gpu/drm/i915/intel_uc_common.h

-- 
1.9.1

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[Intel-gfx] [PATCH 2/4] drm/i915/guc: Fix GuC interaction in reset/suspend scenarios

[Sagar Arun Kamble]

Tearing down of guc_ggtt_invalidate/guc_interrupts/guc_communication
setup should happen towards end of reset/suspend as these are
setup back again during recovery/resume.

Prepared helpers intel_guc_pause and intel_guc_unpause that will do
teardown/bringup of this setup along with suspension/resumption of GuC if
loaded. Moved intel_guc_suspend, intel_guc_resume to intel_guc.c.

Cc: Chris Wilson 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_drv.c|   6 +-
 drivers/gpu/drm/i915/i915_gem.c|   6 +-
 drivers/gpu/drm/i915/i915_guc_submission.c |  52 --
 drivers/gpu/drm/i915/intel_guc.c   | 152 +
 drivers/gpu/drm/i915/intel_guc.h   |   9 +-
 drivers/gpu/drm/i915/intel_uc.c|  29 +-
 6 files changed, 169 insertions(+), 85 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 2ae730c..b2e8f95 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1690,8 +1690,6 @@ static int i915_drm_resume(struct drm_device *dev)
}
mutex_unlock(>struct_mutex);
 
-   intel_guc_resume(dev_priv);
-
intel_modeset_init_hw(dev);
 
spin_lock_irq(_priv->irq_lock);
@@ -2486,7 +2484,7 @@ static int intel_runtime_suspend(struct device *kdev)
 */
i915_gem_runtime_suspend(dev_priv);
 
-   intel_guc_suspend(dev_priv);
+   intel_guc_runtime_suspend(_priv->guc);
 
intel_runtime_pm_disable_interrupts(dev_priv);
 
@@ -2571,7 +2569,7 @@ static int intel_runtime_resume(struct device *kdev)
if (intel_uncore_unclaimed_mmio(dev_priv))
DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
 
-   intel_guc_resume(dev_priv);
+   intel_guc_runtime_resume(_priv->guc);
 
if (IS_GEN9_LP(dev_priv)) {
bxt_disable_dc9(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e4cc08b..977500f 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2846,6 +2846,8 @@ int i915_gem_reset_prepare(struct drm_i915_private 
*dev_priv)
 
i915_gem_revoke_fences(dev_priv);
 
+   intel_guc_reset_prepare(_priv->guc);
+
return err;
 }
 
@@ -4574,8 +4576,6 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
i915_gem_contexts_lost(dev_priv);
mutex_unlock(>struct_mutex);
 
-   intel_guc_suspend(dev_priv);
-
cancel_delayed_work_sync(_priv->gpu_error.hangcheck_work);
cancel_delayed_work_sync(_priv->gt.retire_work);
 
@@ -4592,6 +4592,8 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
if (WARN_ON(!intel_engines_are_idle(dev_priv)))
i915_gem_set_wedged(dev_priv); /* no hope, discard everything */
 
+   intel_guc_system_suspend(_priv->guc);
+
/*
 * Neither the BIOS, ourselves or any other kernel
 * expects the system to be in execlists mode on startup,
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 602ae8a..2f977ab 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1287,55 +1287,3 @@ void i915_guc_submission_disable(struct drm_i915_private 
*dev_priv)
guc_client_free(guc->execbuf_client);
guc->execbuf_client = NULL;
 }
-
-/**
- * intel_guc_suspend() - notify GuC entering suspend state
- * @dev_priv:  i915 device private
- */
-int intel_guc_suspend(struct drm_i915_private *dev_priv)
-{
-   struct intel_guc *guc = _priv->guc;
-   struct i915_gem_context *ctx;
-   u32 data[3];
-
-   if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
-   return 0;
-
-   gen9_disable_guc_interrupts(dev_priv);
-
-   ctx = dev_priv->kernel_context;
-
-   data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
-   /* any value greater than GUC_POWER_D0 */
-   data[1] = GUC_POWER_D1;
-   /* first page is shared data with GuC */
-   data[2] = guc_ggtt_offset(ctx->engine[RCS].state);
-
-   return intel_guc_send(guc, data, ARRAY_SIZE(data));
-}
-
-/**
- * intel_guc_resume() - notify GuC resuming from suspend state
- * @dev_priv:  i915 device private
- */
-int intel_guc_resume(struct drm_i915_private *dev_priv)
-{
-   struct intel_guc *guc = _priv->guc;
-   struct i915_gem_context *ctx;
-   u32 data[3];
-
-   if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
-   return 0;
-
-   if (i915.guc_log_level >= 0)
-   gen9_enable_guc_interrupts(dev_priv);
-
-   ctx = dev_priv->kernel_context;
-
-   data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
-   data[1] = GUC_POWER_D0;
-   /* first page is shared data with GuC */
- 

[Intel-gfx] [PATCH 1/4] drm/i915: Separate GuC/HuC specific functionality from intel_uc

[Sagar Arun Kamble]

Removed unnecessary intel_uc.h includes as it is present in i915_drv.h.
Created intel_guc.c and intel_guc.h for placing GuC specific code.
Created intel_huc.h to refer to HuC specific functions.

v2: Prepared intel_uc_common.h. huc_auth code declaration adjusted.
Moved enable/disable_communication to intel_uc.c (Michal)

Cc: Chris Wilson 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/Makefile  |   1 +
 drivers/gpu/drm/i915/i915_drv.c|   1 -
 drivers/gpu/drm/i915/i915_guc_submission.c |   1 -
 drivers/gpu/drm/i915/intel_guc.c   | 193 ++
 drivers/gpu/drm/i915/intel_guc.h   | 200 +++
 drivers/gpu/drm/i915/intel_guc_loader.c|   1 -
 drivers/gpu/drm/i915/intel_huc.c   |  50 +-
 drivers/gpu/drm/i915/intel_huc.h   |  38 +
 drivers/gpu/drm/i915/intel_uc.c| 128 +--
 drivers/gpu/drm/i915/intel_uc.h| 254 +
 drivers/gpu/drm/i915/intel_uc_common.h | 101 
 11 files changed, 545 insertions(+), 423 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_guc.c
 create mode 100644 drivers/gpu/drm/i915/intel_guc.h
 create mode 100644 drivers/gpu/drm/i915/intel_huc.h
 create mode 100644 drivers/gpu/drm/i915/intel_uc_common.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 892f52b..efc5b30 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -59,6 +59,7 @@ i915-y += i915_cmd_parser.o \
 
 # general-purpose microcontroller (GuC) support
 i915-y += intel_uc.o \
+ intel_guc.o \
  intel_guc_ct.o \
  intel_guc_log.o \
  intel_guc_loader.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index f10a078..2ae730c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -50,7 +50,6 @@
 #include "i915_trace.h"
 #include "i915_vgpu.h"
 #include "intel_drv.h"
-#include "intel_uc.h"
 
 static struct drm_driver driver;
 
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 48a1e93..602ae8a 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -23,7 +23,6 @@
  */
 #include 
 #include "i915_drv.h"
-#include "intel_uc.h"
 
 #include 
 
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
new file mode 100644
index 000..978a0e3
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -0,0 +1,193 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "i915_drv.h"
+
+int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len)
+{
+   WARN(1, "Unexpected send: action=%#x\n", *action);
+   return -ENODEV;
+}
+
+static void gen8_guc_raise_irq(struct intel_guc *guc)
+{
+   struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
+   I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
+}
+
+void intel_guc_init_early(struct intel_guc *guc)
+{
+   intel_guc_ct_init_early(>ct);
+
+   mutex_init(>send_mutex);
+   guc->send = intel_guc_send_nop;
+   guc->notify = gen8_guc_raise_irq;
+}
+
+static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
+{
+   GEM_BUG_ON(!guc->send_regs.base);
+   GEM_BUG_ON(!guc->send_regs.count);
+   GEM_BUG_ON(i >= guc->send_regs.count);
+
+   return _MMIO(guc->send_regs.base + 4 * i);
+}
+
+void intel_guc_init_send_regs(struct intel_guc *guc)
+{
+   struct drm_i915_private *dev_priv = guc_to_i915(guc);
+   enum forcewake_domains fw_domains = 0;
+   unsigned int i;
+
+   

Re: [Intel-gfx] [PATCH 4/7] drm/i915: Pass proper old/new states to intel_plane_atomic_check_with_state()

[Maarten Lankhorst]

Op 31-08-17 om 20:50 schreef Ville Syrjälä:
> On Wed, Aug 23, 2017 at 06:22:23PM +0300, ville.syrj...@linux.intel.com wrote:
>> From: Ville Syrjälä 
>>
>> Eliminate plane->state and crtc->state usage from
>> intel_plane_atomic_check_with_state() and its callers. Instead pass the
>> proper states in or dig them up from the top level atomic state.
>>
>> Note that intel_plane_atomic_check_with_state() itself isn't allowed to
>> use the top level atomic state as there is none when it gets called from
>> the legacy cursor short circuit path.
>>
>> v2: Rename some variables for easier comprehension (Maarten)
>>
>> Cc: Maarten Lankhorst 
>> Signed-off-by: Ville Syrjälä 
> This patch would still need some review love... In the meantime I
> pushed the first three patches from the series. Thanks for the reviews
> thus far.
I love it.

Reviewed-by: Maarten Lankhorst 
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Re: [Intel-gfx] [PATCH 2/2] drm/i915: Fail addfb ioctl if color and CCS buffers overlap

[Gabriel Krisman Bertazi]

Ben Widawsky  writes:

> On 17-08-31 16:52:15, Gabriel Krisman Bertazi wrote:
>>With this patch the new testcase igt@kms_ccs@pipe-X-invalid-ccs-offset
>>succeeds.
>>
>>Signed-off-by: Gabriel Krisman Bertazi 
>>---
>> drivers/gpu/drm/i915/intel_display.c | 5 +
>> 1 file changed, 5 insertions(+)
>>
>>diff --git a/drivers/gpu/drm/i915/intel_display.c 
>>b/drivers/gpu/drm/i915/intel_display.c
>>index b28f076f98bc..ff1ed67a9eff 100644
>>--- a/drivers/gpu/drm/i915/intel_display.c
>>+++ b/drivers/gpu/drm/i915/intel_display.c
>>@@ -13989,6 +13989,11 @@ static int intel_framebuffer_init(struct 
>>intel_framebuffer *intel_fb,
>>  DRM_DEBUG_KMS("RC supported only with RGB 
>> formats\n");
>>  goto err;
>>  }
>>+
>>+ if (mode_cmd->offsets[1] < mode_cmd->pitches[0]) {
>>+ DRM_DEBUG_KMS("CCS and color buffers overlap\n");
>>+ return -EINVAL;
>>+ }
>
> This check doesn't look nearly strict enough to determine overlap. All it's
> checking is that the aux buffer isn't in the first row of the main buffer.
> Second of all, while today our requirement is that the aux buffer always come
> after the main buffer, that may not be the case forever.

Right.  Thanks for catching it.  I'll re-spin with a more strict (and
correct) test for overlapping.

-- 
Gabriel Krisman Bertazi
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/cnl: Add support slice/subslice/eu configs

[Patchwork]

== Series Details ==

Series: drm/i915/cnl: Add support slice/subslice/eu configs
URL   : https://patchwork.freedesktop.org/series/29644/
State : success

== Summary ==

shard-hswtotal:2265 pass:1232 dwarn:0   dfail:0   fail:17  skip:1016 
time:9591s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_/shards.html
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[Intel-gfx] ✓ Fi.CI.IGT: success for tests/gem_flink_basic: Add documentation for subtests (rev2)

[Patchwork]

== Series Details ==

Series: tests/gem_flink_basic: Add documentation for subtests (rev2)
URL   : https://patchwork.freedesktop.org/series/29499/
State : success

== Summary ==

Test perf:
Subgroup polling:
fail   -> PASS   (shard-hsw) fdo#102252

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hswtotal:2265 pass:1233 dwarn:0   dfail:0   fail:16  skip:1016 
time:9611s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_135/shards.html
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: implement NOA mux reprogramming at ctx-switch (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: implement NOA mux reprogramming at ctx-switch (rev2)
URL   : https://patchwork.freedesktop.org/series/29564/
State : success

== Summary ==

Test perf:
Subgroup polling:
fail   -> PASS   (shard-hsw) fdo#102252
Test kms_setmode:
Subgroup basic:
fail   -> PASS   (shard-hsw) fdo#99912

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912

shard-hswtotal:2265 pass:1234 dwarn:0   dfail:0   fail:15  skip:1016 
time:9589s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5554/shards.html
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[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915: Disable DRRS when PSR is enabled (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Disable DRRS when PSR is enabled (rev2)
URL   : https://patchwork.freedesktop.org/series/29577/
State : warning

== Summary ==

Test kms_setmode:
Subgroup basic:
fail   -> PASS   (shard-hsw) fdo#99912
Test perf:
Subgroup polling:
fail   -> PASS   (shard-hsw) fdo#102252 +1
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-primscrn-spr-indfb-move:
pass   -> SKIP   (shard-hsw)
Test kms_chv_cursor_fail:
Subgroup pipe-C-256x256-right-edge:
pass   -> SKIP   (shard-hsw)
Subgroup pipe-C-128x128-top-edge:
pass   -> SKIP   (shard-hsw)
Test pm_rpm:
Subgroup legacy-planes:
pass   -> SKIP   (shard-hsw)
Test kms_plane:
Subgroup plane-position-hole-dpms-pipe-A-planes:
pass   -> SKIP   (shard-hsw)
Test kms_cursor_legacy:
Subgroup basic-flip-after-cursor-legacy:
pass   -> SKIP   (shard-hsw)

fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hswtotal:2265 pass:1229 dwarn:0   dfail:0   fail:14  skip:1022 
time:9618s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5553/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cnl: Add support slice/subslice/eu configs

[Patchwork]

== Series Details ==

Series: drm/i915/cnl: Add support slice/subslice/eu configs
URL   : https://patchwork.freedesktop.org/series/29644/
State : success

== Summary ==

Series 29644v1 drm/i915/cnl: Add support slice/subslice/eu configs
https://patchwork.freedesktop.org/api/1.0/series/29644/revisions/1/mbox/

Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
pass   -> FAIL   (fi-snb-2600) fdo#100215 +1
Subgroup basic-flip-after-cursor-varying-size:
fail   -> PASS   (fi-hsw-4770) fdo#102402 +1

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#102402 https://bugs.freedesktop.org/show_bug.cgi?id=102402

fi-bdw-5557u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:455s
fi-bdw-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:443s
fi-blb-e6850 total:288  pass:224  dwarn:1   dfail:0   fail:0   skip:63  
time:359s
fi-bsw-n3050 total:288  pass:243  dwarn:0   dfail:0   fail:0   skip:45  
time:564s
fi-bwr-2160  total:288  pass:184  dwarn:0   dfail:0   fail:0   skip:104 
time:254s
fi-bxt-j4205 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:521s
fi-byt-j1900 total:288  pass:254  dwarn:1   dfail:0   fail:0   skip:33  
time:525s
fi-byt-n2820 total:288  pass:250  dwarn:1   dfail:0   fail:0   skip:37  
time:518s
fi-elk-e7500 total:288  pass:230  dwarn:0   dfail:0   fail:0   skip:58  
time:438s
fi-glk-2atotal:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:614s
fi-hsw-4770  total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  
time:455s
fi-hsw-4770r total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  
time:423s
fi-ilk-650   total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:425s
fi-ivb-3520m total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:498s
fi-ivb-3770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:476s
fi-kbl-7500u total:288  pass:264  dwarn:1   dfail:0   fail:0   skip:23  
time:514s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:597s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:596s
fi-pnv-d510  total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:520s
fi-skl-6260u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:470s
fi-skl-6700k total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:537s
fi-skl-6770hqtotal:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:487s
fi-skl-gvtdvmtotal:288  pass:266  dwarn:0   dfail:0   fail:0   skip:22  
time:441s
fi-skl-x1585ltotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:489s
fi-snb-2520m total:288  pass:251  dwarn:0   dfail:0   fail:0   skip:37  
time:556s
fi-snb-2600  total:288  pass:249  dwarn:0   dfail:0   fail:1   skip:38  
time:407s

ccf4ca2d93383fe1a234aba83df9c21400216433 drm-tip: 2017y-08m-31d-18h-37m-46s UTC 
integration manifest
668e5b837d83 drm/i915/cnl: Add support slice/subslice/eu configs

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_/
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Re: [Intel-gfx] [PATCH] drm/i915/cnl: Add support slice/subslice/eu configs

[Rodrigo Vivi]

quick extra note on this:
with this the SSEU Device Info is right and matching spec..
But SSEU Device Status needs a rework that I will do in a follow-up patch:

CNL-Y (2x8):

SSEU Device Info
  Available Slice Mask: 0001
  Available Slice Total: 1
  Available Subslice Total: 2
  Available Subslice Mask: 0006
  Available Subslice Per Slice: 2
  Available EU Total: 16
  Available EU Per Subslice: 8
  Has Pooled EU: no
  Has Slice Power Gating: yes
  Has Subslice Power Gating: yes
  Has EU Power Gating: yes
SSEU Device Status
  Enabled Slice Mask: 0001
  Enabled Slice Total: 1
  Enabled Subslice Total: 2
  Enabled Subslice Mask: 0006
  Enabled Subslice Per Slice: 2
  Enabled EU Total: 20
  Enabled EU Per Subslice: 8

On Thu, Aug 31, 2017 at 4:59 PM, Rodrigo Vivi  wrote:
> From: Ben Widawsky 
>
> Cannonlake Slice and Subslice information has changed.
> This Patch provided by Ben adds the proper sseu
> initialization.
>
> v2: This v2 done by Rodrigo includes:
> - Fix on Total slices count by avoiding [1][2] and [2][2].
> - Inclusion of EU Per Subslice.
> - Commit message.
>
> Cc: Oscar Mateo 
> Signed-off-by: Ben Widawsky 
> Signed-off-by: Rodrigo Vivi 
> ---
>  drivers/gpu/drm/i915/i915_drv.h  |  5 +++-
>  drivers/gpu/drm/i915/i915_reg.h  | 20 +
>  drivers/gpu/drm/i915/intel_device_info.c | 50 
> +++-
>  3 files changed, 73 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 0383e879a315..2fdd59e85189 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -786,7 +786,10 @@ struct sseu_dev_info {
> u8 slice_mask;
> u8 subslice_mask;
> u8 eu_total;
> -   u8 eu_per_subslice;
> +   union {
> +   u8 per_subslice_eu_disable_mask[3][3];
> +   u8 eu_per_subslice;
> +   };
> u8 min_eu_in_pool;
> /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
> u8 subslice_7eu[3];
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5651081ff789..7f71007baa94 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2730,6 +2730,11 @@ enum i915_power_well_id {
>  #define   GEN9_F2_SS_DIS_SHIFT 20
>  #define   GEN9_F2_SS_DIS_MASK  (0xf << GEN9_F2_SS_DIS_SHIFT)
>
> +#define   GEN10_F2_S_ENA_SHIFT 22
> +#define   GEN10_F2_S_ENA_MASK  (0x7 << GEN10_F2_S_ENA_SHIFT)
> +#define   GEN10_F2_SS_DIS_SHIFT18
> +#define   GEN10_F2_SS_DIS_MASK (0x7 << GEN10_F2_SS_DIS_SHIFT)
> +
>  #define GEN8_EU_DISABLE0   _MMIO(0x9134)
>  #define   GEN8_EU_DIS0_S0_MASK 0xff
>  #define   GEN8_EU_DIS0_S1_SHIFT24
> @@ -2745,6 +2750,21 @@ enum i915_power_well_id {
>
>  #define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice)*0x4)
>
> +#define GEN10_EU_DIS0_S0_SHIFT 0
> +#define GEN10_EU_DIS0_S0_MASK  (0xff << GEN10_EU_DIS0_S0_SHIFT)
> +#define GEN10_EU_DIS0_S1_SHIFT 8
> +#define GEN10_EU_DIS0_S1_MASK  (0xff << GEN10_EU_DIS0_S1_SHIFT)
> +#define GEN10_EU_DIS0_S2_SHIFT 16
> +#define GEN10_EU_DIS0_S2_MASK  (0xff << GEN10_EU_DIS0_S2_SHIFT)
> +#define GEN10_EU_DIS1_S0_SHIFT 24
> +#define GEN10_EU_DIS1_S0_MASK  (0xff << GEN10_EU_DIS1_S0_SHIFT)
> +#define GEN10_EU_DIS1_S1_SHIFT 0
> +#define GEN10_EU_DIS1_S1_MASK  (0xff << GEN10_EU_DIS1_S1_SHIFT)
> +#define GEN10_EU_DIS2_S0_SHIFT 8
> +#define GEN10_EU_DIS2_S0_MASK  (0xff << GEN10_EU_DIS2_S0_SHIFT)
> +#define GEN10_EU_DIS2_S1_SHIFT 16
> +#define GEN10_EU_DIS2_S1_MASK  (0xff << GEN10_EU_DIS2_S1_SHIFT)
> +
>  #define GEN6_BSD_SLEEP_PSMI_CONTROL_MMIO(0x12050)
>  #define   GEN6_BSD_SLEEP_MSG_DISABLE   (1 << 0)
>  #define   GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
> b/drivers/gpu/drm/i915/intel_device_info.c
> index 5f91ddc78c7a..da13becf97f1 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -82,6 +82,52 @@ void intel_device_info_dump(struct drm_i915_private 
> *dev_priv)
>  #undef PRINT_FLAG
>  }
>
> +static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
> +{
> +   struct sseu_dev_info *sseu = _device_info(dev_priv)->sseu;
> +   const u32 fuse2 = I915_READ(GEN8_FUSE2);
> +   u32 temp, i, j;
> +
> +   sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >> 
> GEN10_F2_S_ENA_SHIFT;
> +   sseu->subslice_mask = (1 << 3) - 1;
> +   sseu->subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
> +GEN10_F2_SS_DIS_SHIFT);
> +
> +   temp = I915_READ(GEN8_EU_DISABLE0);
> +   

Re: [Intel-gfx] [PATCH 00/12] drm/i915: Fix up the CCS code

[Rodrigo Vivi]

Hi Ville,

On Wed, Aug 30, 2017 at 10:09 AM, Ville Syrjälä
 wrote:
> On Wed, Aug 30, 2017 at 11:31:16AM +0300, Jani Nikula wrote:
>> On Mon, 28 Aug 2017, Ville Syrjälä  wrote:
>> > On Mon, Aug 28, 2017 at 02:35:54PM +0100, Daniel Stone wrote:
>> >> Hi Daniel,
>> >>
>> >> On 25 August 2017 at 18:17, Daniel Vetter  wrote:
>> >> > Which of these do we need to cherry-pick over to -next-fixes? There's no
>> >> > annotations about that. If the answer is "most" I'm leaning towards
>> >> > disabling CCS for 4.14, minimal set would be ideal (and first in the 
>> >> > patch
>> >> > series).
>> >>
>> >> My opinion below; tl;dr is that I don't think most of them are
>> >> super-critical. Ville obviously has a far stronger opinion than me on
>> >> the shape of the code, so I'm fine with this series, which seems to
>> >> mostly be a merge back of the delta between whatever Ville's latest
>> >> branch was, and whatever the last patchset Ben sent out was.
>> >>
>> >> >> Ville Syrjälä (12):
>> >> >>   drm/i915: Treat fb->offsets[] as a raw byte offset instead of a 
>> >> >> linear
>> >> >> offset
>> >>
>> >> This should land into -fixes. I trust Ville that it has no UABI
>> >> impact, but seems like something to be very consistent on.
>> >
>> > It does change the uabi. That's the whole point. What was merged doesn't
>> > agree with what userspace wants. So this we want in definitely so that
>> > we don't end up exposing the wrong uabi in any released kernel.
>> >
>> >>
>> >> >>   drm/i915: Skip fence alignemnt check for the CCS plane
>> >>
>> >> Not sure if this is -fixes material really, just a cleanup?
>> >
>> > It makes the kernel less likely to reject the fb entirely. So
>> > without this userspace has to be rather careful where it places
>> > the aux surface. I would include this as well.
>> >
>> >>
>> >> >>   drm/i915: Switch over to the LLC/eLLC hotspot avoidance hash mode for
>> >> >> CCS
>> >>
>> >> Not -fixes, performance optimisation.
>> >
>> > We hope. It does change the layout of the compressed data though so if
>> > our testcases try to generate compressed data with the CPU it'll not go
>> > well if the test assumes the wrong hash mode. I would include this as
>> > well so that we don't end up in any kind of a mess later when we try to
>> > change it.
>> >
>> > So the patches were more or less sorted in priority order, and we want
>> > at least 01,02 and maybe 03.
>>
>> When you decide what to apply, please *please* add the appropriate
>> Fixes: tags for the ones you want to show up in v4.14.
>
> I just pushed 01 and 02 to dinq with the approriage Fixes: tags.
> I'd still prefer to get 03 in as well, but that would need an
> r-b/ack.
>
>>
>> BR,
>> Jani.
>>
>>
>> >
>> >>
>> >> >>   drm/i915: Add a comment exlaining CCS hsub/vsub
>> >>
>> >> Seems harmless to land to -fixes.
>> >>
>> >> >>   drm/i915: Nuke a pointless unreachable()
>> >>
>> >> Ditto.
>> >>
>> >> >>   drm/i915: Add the missing Y/Yf modifiers for SKL+ sprites
>> >>
>> >> Per my previous reply, NAK to landing at all, since DDB/WM allocation
>> >> seems too broken for it to work.
>> >>
>> >> >>   drm/i915: Clean up the sprite modifier checks
>> >>
>> >> Fine with this, but doesn't seem like -fixes material.
>> >>
>> >> >>   drm/i915: Add CCS capability for sprites
>> >>
>> >> NAK, same reason as Y/Yf.
>> >>
>> >> >>   drm/i915: Allow up to 32KB stride on SKL+ "sprites"
>> >>
>> >> Again doesn't seem like -fixes necessarily?
>> >>
>> >> >>   drm: Fix modifiers_property kernel doc
>> >>
>> >> Good for -fixes.
>> >>
>> >> >>   drm: Check that the plane supports the request format+modifier combo
>> >>
>> >> Good for core (not Intel) -fixes.
>> >>
>> >> >>   drm/i915: Remove the pipe/plane ID checks from
>> >> >> skl_check_ccs_aux_surface()
>> >>
>> >> Seems fine but probably not -fixes material; land in Intel after a merge?
>> >>
>> >> Cheers,
>> >> Daniel

Should I wait any more of this for drm-intel-next-fixes?

Otherwise I will move with the pull request.

Thanks,
Rodrigo.

>>
>> --
>> Jani Nikula, Intel Open Source Technology Center
>
> --
> Ville Syrjälä
> Intel OTC
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-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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[Intel-gfx] [PATCH] drm/i915/cnl: Add support slice/subslice/eu configs

[Rodrigo Vivi]

From: Ben Widawsky 

Cannonlake Slice and Subslice information has changed.
This Patch provided by Ben adds the proper sseu
initialization.

v2: This v2 done by Rodrigo includes:
- Fix on Total slices count by avoiding [1][2] and [2][2].
- Inclusion of EU Per Subslice.
- Commit message.

Cc: Oscar Mateo 
Signed-off-by: Ben Widawsky 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/i915_drv.h  |  5 +++-
 drivers/gpu/drm/i915/i915_reg.h  | 20 +
 drivers/gpu/drm/i915/intel_device_info.c | 50 +++-
 3 files changed, 73 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0383e879a315..2fdd59e85189 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -786,7 +786,10 @@ struct sseu_dev_info {
u8 slice_mask;
u8 subslice_mask;
u8 eu_total;
-   u8 eu_per_subslice;
+   union {
+   u8 per_subslice_eu_disable_mask[3][3];
+   u8 eu_per_subslice;
+   };
u8 min_eu_in_pool;
/* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
u8 subslice_7eu[3];
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5651081ff789..7f71007baa94 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2730,6 +2730,11 @@ enum i915_power_well_id {
 #define   GEN9_F2_SS_DIS_SHIFT 20
 #define   GEN9_F2_SS_DIS_MASK  (0xf << GEN9_F2_SS_DIS_SHIFT)
 
+#define   GEN10_F2_S_ENA_SHIFT 22
+#define   GEN10_F2_S_ENA_MASK  (0x7 << GEN10_F2_S_ENA_SHIFT)
+#define   GEN10_F2_SS_DIS_SHIFT18
+#define   GEN10_F2_SS_DIS_MASK (0x7 << GEN10_F2_SS_DIS_SHIFT)
+
 #define GEN8_EU_DISABLE0   _MMIO(0x9134)
 #define   GEN8_EU_DIS0_S0_MASK 0xff
 #define   GEN8_EU_DIS0_S1_SHIFT24
@@ -2745,6 +2750,21 @@ enum i915_power_well_id {
 
 #define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice)*0x4)
 
+#define GEN10_EU_DIS0_S0_SHIFT 0
+#define GEN10_EU_DIS0_S0_MASK  (0xff << GEN10_EU_DIS0_S0_SHIFT)
+#define GEN10_EU_DIS0_S1_SHIFT 8
+#define GEN10_EU_DIS0_S1_MASK  (0xff << GEN10_EU_DIS0_S1_SHIFT)
+#define GEN10_EU_DIS0_S2_SHIFT 16
+#define GEN10_EU_DIS0_S2_MASK  (0xff << GEN10_EU_DIS0_S2_SHIFT)
+#define GEN10_EU_DIS1_S0_SHIFT 24
+#define GEN10_EU_DIS1_S0_MASK  (0xff << GEN10_EU_DIS1_S0_SHIFT)
+#define GEN10_EU_DIS1_S1_SHIFT 0
+#define GEN10_EU_DIS1_S1_MASK  (0xff << GEN10_EU_DIS1_S1_SHIFT)
+#define GEN10_EU_DIS2_S0_SHIFT 8
+#define GEN10_EU_DIS2_S0_MASK  (0xff << GEN10_EU_DIS2_S0_SHIFT)
+#define GEN10_EU_DIS2_S1_SHIFT 16
+#define GEN10_EU_DIS2_S1_MASK  (0xff << GEN10_EU_DIS2_S1_SHIFT)
+
 #define GEN6_BSD_SLEEP_PSMI_CONTROL_MMIO(0x12050)
 #define   GEN6_BSD_SLEEP_MSG_DISABLE   (1 << 0)
 #define   GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
b/drivers/gpu/drm/i915/intel_device_info.c
index 5f91ddc78c7a..da13becf97f1 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -82,6 +82,52 @@ void intel_device_info_dump(struct drm_i915_private 
*dev_priv)
 #undef PRINT_FLAG
 }
 
+static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
+{
+   struct sseu_dev_info *sseu = _device_info(dev_priv)->sseu;
+   const u32 fuse2 = I915_READ(GEN8_FUSE2);
+   u32 temp, i, j;
+
+   sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >> 
GEN10_F2_S_ENA_SHIFT;
+   sseu->subslice_mask = (1 << 3) - 1;
+   sseu->subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
+GEN10_F2_SS_DIS_SHIFT);
+
+   temp = I915_READ(GEN8_EU_DISABLE0);
+   sseu->per_subslice_eu_disable_mask[0][0] =
+   (temp & GEN10_EU_DIS0_S0_MASK) >> GEN10_EU_DIS0_S0_SHIFT;
+   sseu->per_subslice_eu_disable_mask[0][1] =
+   (temp & GEN10_EU_DIS0_S1_MASK) >> GEN10_EU_DIS0_S1_SHIFT;
+   sseu->per_subslice_eu_disable_mask[0][2] =
+   (temp & GEN10_EU_DIS0_S2_MASK) >> GEN10_EU_DIS0_S2_SHIFT;
+   sseu->per_subslice_eu_disable_mask[1][0] =
+   (temp & GEN10_EU_DIS1_S0_MASK) >> GEN10_EU_DIS1_S0_SHIFT;
+
+   temp = I915_READ(GEN8_EU_DISABLE1);
+   sseu->per_subslice_eu_disable_mask[1][1] =
+   (temp & GEN10_EU_DIS1_S1_MASK) >> GEN10_EU_DIS1_S1_SHIFT;
+   sseu->per_subslice_eu_disable_mask[2][0] =
+   (temp & GEN10_EU_DIS2_S0_MASK) >> GEN10_EU_DIS2_S0_SHIFT;
+   sseu->per_subslice_eu_disable_mask[2][1] =
+   (temp & GEN10_EU_DIS2_S1_MASK) >> GEN10_EU_DIS2_S1_SHIFT;
+
+   for (i = 0; i < 3; i++)
+   for (j = 0; j < (i == 0 ? 3 : 2); j++)
+

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm: Fix example comment of format modifier blob

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm: Fix example comment of format modifier 
blob
URL   : https://patchwork.freedesktop.org/series/29627/
State : success

== Summary ==

shard-hswtotal:2265 pass:1232 dwarn:0   dfail:0   fail:17  skip:1016 
time:9651s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5552/shards.html
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Re: [Intel-gfx] [PATCH 00/13] mmu_notifier kill invalidate_page callback

[Jerome Glisse]

On Thu, Aug 31, 2017 at 07:19:19PM -0400, Felix Kuehling wrote:
> On 2017-08-31 03:00 PM, Jerome Glisse wrote:
> > I was not saying you should not use mmu_notifier. For achieving B you need
> > mmu_notifier. Note that if you do like ODP/KVM then you do not need to
> > pin page.
> I would like that. I've thought about it before. The one problem I
> couldn't figure out is, where to set the accessed and dirty bits for the
> pages. Now we do it when we unpin. If we don't pin the pages in the
> first place, we don't have a good place for this.
> 
> Our hardware doesn't give us notifications or accessed/dirty bits, so we
> have to assume the worst case that the pages are continuously
> accessed/dirty.
> 
> I'd appreciate any advice how to handle that. (Sorry, I realize this is
> going a bit off topic.) A pointer to a document or source code would be
> great. :)

In invalidate_range_start() ie same place as where you unpin but instead
of unpining you would just call set_page_dirty()

Jérôme
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/4] drm/i915: Fix the missing PPAT cache attributes on CNL

[Patchwork]

== Series Details ==

Series: series starting with [1/4] drm/i915: Fix the missing PPAT cache 
attributes on CNL
URL   : https://patchwork.freedesktop.org/series/29625/
State : success

== Summary ==

Test perf:
Subgroup polling:
fail   -> PASS   (shard-hsw) fdo#102252

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hswtotal:2265 pass:1233 dwarn:0   dfail:0   fail:16  skip:1016 
time:9628s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5551/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for tests/gem_flink_basic: Add documentation for subtests (rev2)

[Patchwork]

== Series Details ==

Series: tests/gem_flink_basic: Add documentation for subtests (rev2)
URL   : https://patchwork.freedesktop.org/series/29499/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
5ce65a9a51f17e0183e3e4f8943981ee7b96cadd pm_rps: Changes in waitboost scenario

with latest DRM-Tip kernel build CI_DRM_3023
ccf4ca2d9338 drm-tip: 2017y-08m-31d-18h-37m-46s UTC integration manifest

Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-legacy:
fail   -> PASS   (fi-snb-2600) fdo#100215

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215

fi-bdw-5557u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:458s
fi-bdw-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:444s
fi-blb-e6850 total:288  pass:224  dwarn:1   dfail:0   fail:0   skip:63  
time:364s
fi-bsw-n3050 total:288  pass:243  dwarn:0   dfail:0   fail:0   skip:45  
time:568s
fi-bwr-2160  total:288  pass:184  dwarn:0   dfail:0   fail:0   skip:104 
time:255s
fi-bxt-j4205 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:528s
fi-byt-j1900 total:288  pass:254  dwarn:1   dfail:0   fail:0   skip:33  
time:522s
fi-byt-n2820 total:288  pass:250  dwarn:1   dfail:0   fail:0   skip:37  
time:521s
fi-elk-e7500 total:288  pass:230  dwarn:0   dfail:0   fail:0   skip:58  
time:435s
fi-glk-2atotal:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:612s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:2   skip:25  
time:464s
fi-hsw-4770r total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  
time:425s
fi-ilk-650   total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:424s
fi-ivb-3520m total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:505s
fi-ivb-3770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:481s
fi-kbl-7500u total:288  pass:264  dwarn:1   dfail:0   fail:0   skip:23  
time:518s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:600s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:599s
fi-pnv-d510  total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:528s
fi-skl-6260u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:469s
fi-skl-6700k total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:538s
fi-skl-6770hqtotal:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:496s
fi-skl-gvtdvmtotal:288  pass:266  dwarn:0   dfail:0   fail:0   skip:22  
time:444s
fi-skl-x1585ltotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:496s
fi-snb-2520m total:288  pass:251  dwarn:0   dfail:0   fail:0   skip:37  
time:551s
fi-snb-2600  total:288  pass:250  dwarn:0   dfail:0   fail:0   skip:38  
time:405s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_135/
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: implement NOA mux reprogramming at ctx-switch (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: implement NOA mux reprogramming at ctx-switch (rev2)
URL   : https://patchwork.freedesktop.org/series/29564/
State : success

== Summary ==

Series 29564v2 drm/i915: implement NOA mux reprogramming at ctx-switch
https://patchwork.freedesktop.org/api/1.0/series/29564/revisions/2/mbox/

Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
pass   -> FAIL   (fi-snb-2600) fdo#100215 +1

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215

fi-bdw-5557u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:455s
fi-bdw-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:441s
fi-blb-e6850 total:288  pass:224  dwarn:1   dfail:0   fail:0   skip:63  
time:359s
fi-bsw-n3050 total:288  pass:243  dwarn:0   dfail:0   fail:0   skip:45  
time:556s
fi-bwr-2160  total:288  pass:184  dwarn:0   dfail:0   fail:0   skip:104 
time:254s
fi-bxt-j4205 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:521s
fi-byt-j1900 total:288  pass:254  dwarn:1   dfail:0   fail:0   skip:33  
time:525s
fi-byt-n2820 total:288  pass:250  dwarn:1   dfail:0   fail:0   skip:37  
time:520s
fi-elk-e7500 total:288  pass:230  dwarn:0   dfail:0   fail:0   skip:58  
time:436s
fi-glk-2atotal:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:610s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:2   skip:25  
time:464s
fi-hsw-4770r total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  
time:423s
fi-ilk-650   total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:426s
fi-ivb-3520m total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:496s
fi-ivb-3770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:475s
fi-kbl-7500u total:288  pass:264  dwarn:1   dfail:0   fail:0   skip:23  
time:518s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:596s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:596s
fi-pnv-d510  total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:527s
fi-skl-6260u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:471s
fi-skl-6700k total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:529s
fi-skl-6770hqtotal:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:489s
fi-skl-gvtdvmtotal:288  pass:266  dwarn:0   dfail:0   fail:0   skip:22  
time:448s
fi-skl-x1585ltotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:490s
fi-snb-2520m total:288  pass:251  dwarn:0   dfail:0   fail:0   skip:37  
time:546s
fi-snb-2600  total:288  pass:249  dwarn:0   dfail:0   fail:1   skip:38  
time:405s

ccf4ca2d93383fe1a234aba83df9c21400216433 drm-tip: 2017y-08m-31d-18h-37m-46s UTC 
integration manifest
8a67e4baccf0 drm/i915: reprogram NOA muxes on context switch when using perf
f2ef57f51836 drm/i915: pass wa_ctx as argument
9b60e084f9b4 drm/i915: extract per-ctx/indirect bb programming
23ac9b987219 drm/i915: don't specify pinned size for wa_bb pin/allocation

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5554/
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Disable DRRS when PSR is enabled (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Disable DRRS when PSR is enabled (rev2)
URL   : https://patchwork.freedesktop.org/series/29577/
State : success

== Summary ==

Series 29577v2 drm/i915: Disable DRRS when PSR is enabled
https://patchwork.freedesktop.org/api/1.0/series/29577/revisions/2/mbox/

Test gem_exec_flush:
Subgroup basic-batch-kernel-default-uc:
pass   -> FAIL   (fi-snb-2600) fdo#17
Test kms_cursor_legacy:
Subgroup basic-flip-after-cursor-varying-size:
fail   -> PASS   (fi-hsw-4770) fdo#102402 +1

fdo#17 https://bugs.freedesktop.org/show_bug.cgi?id=17
fdo#102402 https://bugs.freedesktop.org/show_bug.cgi?id=102402

fi-bdw-5557u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:453s
fi-bdw-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:443s
fi-blb-e6850 total:288  pass:224  dwarn:1   dfail:0   fail:0   skip:63  
time:364s
fi-bsw-n3050 total:288  pass:243  dwarn:0   dfail:0   fail:0   skip:45  
time:556s
fi-bwr-2160  total:288  pass:184  dwarn:0   dfail:0   fail:0   skip:104 
time:253s
fi-bxt-j4205 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:525s
fi-byt-j1900 total:288  pass:254  dwarn:1   dfail:0   fail:0   skip:33  
time:522s
fi-byt-n2820 total:288  pass:250  dwarn:1   dfail:0   fail:0   skip:37  
time:518s
fi-elk-e7500 total:288  pass:230  dwarn:0   dfail:0   fail:0   skip:58  
time:437s
fi-glk-2atotal:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:619s
fi-hsw-4770  total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  
time:456s
fi-hsw-4770r total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  
time:423s
fi-ilk-650   total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:430s
fi-ivb-3520m total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:508s
fi-ivb-3770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:476s
fi-kbl-7500u total:288  pass:264  dwarn:1   dfail:0   fail:0   skip:23  
time:517s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:599s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:598s
fi-pnv-d510  total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:526s
fi-skl-6260u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:469s
fi-skl-6700k total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:535s
fi-skl-6770hqtotal:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:486s
fi-skl-gvtdvmtotal:288  pass:266  dwarn:0   dfail:0   fail:0   skip:22  
time:446s
fi-skl-x1585ltotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:489s
fi-snb-2520m total:288  pass:251  dwarn:0   dfail:0   fail:0   skip:37  
time:552s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:2   skip:38  
time:407s

ccf4ca2d93383fe1a234aba83df9c21400216433 drm-tip: 2017y-08m-31d-18h-37m-46s UTC 
integration manifest
cba2ebe39662 drm/i915: Disable DRRS when PSR is enabled

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5553/
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[Intel-gfx] [PATCH i-g-t v2] tests/gem_flink_basic: Add documentation for subtests

[Vinay Belgaumkar]

Added the missing IGT_TEST_DESCRIPTION and some subtest
descriptions. Trying to establish a method to document
subtests, it should describe the feature being tested
rather than how. The HOW part can, if needed, be
described in the test code.

Documenting subtests will give us a good way to trace
feature test coverage, and also help a faster ramp
for understanding the test code.

v2: Removed duplication, addressed comments, cc'd test author

Cc: Michał Winiarski 
Cc: Eric Anholt 

Signed-off-by: Vinay Belgaumkar 
---
 tests/gem_flink_basic.c | 36 ++--
 1 file changed, 26 insertions(+), 10 deletions(-)

diff --git a/tests/gem_flink_basic.c b/tests/gem_flink_basic.c
index 26ae7d6..9c8c4c3 100644
--- a/tests/gem_flink_basic.c
+++ b/tests/gem_flink_basic.c
@@ -36,6 +36,8 @@
 #include 
 #include "drm.h"
 
+IGT_TEST_DESCRIPTION("Tests for flink - a way to export a gem object by name");
+
 static void
 test_flink(int fd)
 {
@@ -44,8 +46,6 @@ test_flink(int fd)
struct drm_gem_open open_struct;
int ret;
 
-   igt_info("Testing flink and open.\n");
-
memset(, 0, sizeof(create));
create.size = 16 * 1024;
ret = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE, );
@@ -69,8 +69,6 @@ test_double_flink(int fd)
struct drm_gem_flink flink2;
int ret;
 
-   igt_info("Testing repeated flink.\n");
-
memset(, 0, sizeof(create));
create.size = 16 * 1024;
ret = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE, );
@@ -92,8 +90,6 @@ test_bad_flink(int fd)
struct drm_gem_flink flink;
int ret;
 
-   igt_info("Testing error return on bad flink ioctl.\n");
-
flink.handle = 0x10101010;
ret = ioctl(fd, DRM_IOCTL_GEM_FLINK, );
igt_assert(ret == -1 && errno == ENOENT);
@@ -105,8 +101,6 @@ test_bad_open(int fd)
struct drm_gem_open open_struct;
int ret;
 
-   igt_info("Testing error return on bad open ioctl.\n");
-
open_struct.name = 0x10101010;
ret = ioctl(fd, DRM_IOCTL_GEM_OPEN, _struct);
 
@@ -121,8 +115,6 @@ test_flink_lifetime(int fd)
struct drm_gem_open open_struct;
int ret, fd2;
 
-   igt_info("Testing flink lifetime.\n");
-
fd2 = drm_open_driver(DRIVER_INTEL);
 
memset(, 0, sizeof(create));
@@ -134,11 +126,13 @@ test_flink_lifetime(int fd)
ret = ioctl(fd2, DRM_IOCTL_GEM_FLINK, );
igt_assert_eq(ret, 0);
 
+   /* Open another reference to the gem object */
open_struct.name = flink.name;
ret = ioctl(fd, DRM_IOCTL_GEM_OPEN, _struct);
igt_assert_eq(ret, 0);
igt_assert(open_struct.handle != 0);
 
+   /* Before closing the previous one */
close(fd2);
fd2 = drm_open_driver(DRIVER_INTEL);
 
@@ -155,14 +149,36 @@ igt_main
igt_fixture
fd = drm_open_driver(DRIVER_INTEL);
 
+   /**
+* basic:
+* Test creation and use of flink.
+*/
igt_subtest("basic")
test_flink(fd);
+
+   /**
+* double-flink:
+* This test validates the ability to create multiple flinks
+* for the same gem object. They should obtain the same name.
+*/
igt_subtest("double-flink")
test_double_flink(fd);
+
+   /**
+* bad-flink:
+* Negative test for invalid flink usage.
+*/
igt_subtest("bad-flink")
test_bad_flink(fd);
+
igt_subtest("bad-open")
test_bad_open(fd);
+
+   /**
+* flink-lifetime:
+* Flink lifetime is limited to that of the gem object it
+* points to.
+*/
igt_subtest("flink-lifetime")
test_flink_lifetime(fd);
 }
-- 
1.9.1

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[Intel-gfx] [PATCH v2 2/4] drm/i915: extract per-ctx/indirect bb programming

[Lionel Landwerlin]

Let's put this in its own function to reuse it later.

v2: Pull in condition in the extracted function (Chris)

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/intel_lrc.c | 37 +++--
 1 file changed, 23 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 09fb2b29a739..9ea5a56956e3 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1906,6 +1906,28 @@ static u32 intel_lr_indirect_ctx_offset(struct 
intel_engine_cs *engine)
return indirect_ctx_offset;
 }
 
+static void execlists_init_reg_state_wa_bb(u32 *regs,
+  struct intel_engine_cs *engine)
+{
+   struct i915_ctx_workarounds *wa_ctx = >wa_ctx;
+   u32 ggtt_offset;
+
+   if (!wa_ctx->vma)
+   return;
+
+   ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
+
+   regs[CTX_RCS_INDIRECT_CTX + 1] =
+   (ggtt_offset + wa_ctx->indirect_ctx.offset) |
+   (wa_ctx->indirect_ctx.size / CACHELINE_BYTES);
+
+   regs[CTX_RCS_INDIRECT_CTX_OFFSET + 1] =
+   intel_lr_indirect_ctx_offset(engine) << 6;
+
+   regs[CTX_BB_PER_CTX_PTR + 1] =
+   (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01;
+}
+
 static void execlists_init_reg_state(u32 *regs,
 struct i915_gem_context *ctx,
 struct intel_engine_cs *engine,
@@ -1948,20 +1970,7 @@ static void execlists_init_reg_state(u32 *regs,
CTX_REG(regs, CTX_RCS_INDIRECT_CTX_OFFSET,
RING_INDIRECT_CTX_OFFSET(base), 0);
 
-   if (engine->wa_ctx.vma) {
-   struct i915_ctx_workarounds *wa_ctx = >wa_ctx;
-   u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
-
-   regs[CTX_RCS_INDIRECT_CTX + 1] =
-   (ggtt_offset + wa_ctx->indirect_ctx.offset) |
-   (wa_ctx->indirect_ctx.size / CACHELINE_BYTES);
-
-   regs[CTX_RCS_INDIRECT_CTX_OFFSET + 1] =
-   intel_lr_indirect_ctx_offset(engine) << 6;
-
-   regs[CTX_BB_PER_CTX_PTR + 1] =
-   (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01;
-   }
+   execlists_init_reg_state_wa_bb(regs, engine);
}
 
regs[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
-- 
2.14.1

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[Intel-gfx] [PATCH v2 4/4] drm/i915: reprogram NOA muxes on context switch when using perf

[Lionel Landwerlin]

If some of the contexts submitting workloads to the GPU have been
configured to shutdown slices/subslices, we might loose the NOA
configurations written in the NOA muxes. We need to reprogram them at
context switch.

v2: Do reprogramming in indirect-ctx batchbuffer (Chris)
Simplify emission by reusing i915_oa_get_perctx_bb_size() (Chris)

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/i915_drv.h  |   2 +
 drivers/gpu/drm/i915/i915_perf.c | 130 ---
 drivers/gpu/drm/i915/intel_lrc.c |  61 +-
 drivers/gpu/drm/i915/intel_lrc.h |   1 +
 4 files changed, 156 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 43d83ffae2d3..5157bf68323e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3706,6 +3706,8 @@ int i915_perf_remove_config_ioctl(struct drm_device *dev, 
void *data,
 void i915_oa_init_reg_state(struct intel_engine_cs *engine,
struct i915_gem_context *ctx,
uint32_t *reg_state);
+u32 i915_oa_get_perctx_bb_size(struct intel_engine_cs *engine);
+u32 *i915_oa_emit_perctx_bb(struct intel_engine_cs *engine, u32 *batch);
 
 /* i915_gem_evict.c */
 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 1b753c53abfa..0e049567c7a1 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1688,6 +1688,67 @@ static int gen8_emit_oa_config(struct 
drm_i915_gem_request *req,
return 0;
 }
 
+#define MAX_LRI_SIZE (125U)
+
+u32 i915_oa_get_perctx_bb_size(struct intel_engine_cs *engine)
+{
+   struct drm_i915_private *dev_priv = engine->i915;
+   struct i915_perf_stream *stream = dev_priv->perf.oa.exclusive_stream;
+   struct i915_oa_config *oa_config;
+   u32 n_lri;
+
+   /* We only care about RCS. */
+   if (engine->id != RCS)
+   return 0;
+
+   /* Perf not supported. */
+   if (!dev_priv->perf.initialized)
+   return 0;
+
+   /* OA not currently configured. */
+   if (!stream)
+   return 0;
+
+   oa_config = stream->oa_config;
+
+   /* Very unlikely but possible that we have no muxes to configure. */
+   if (!oa_config->mux_regs_len)
+   return 0;
+
+   n_lri = (oa_config->mux_regs_len / MAX_LRI_SIZE) +
+   (oa_config->mux_regs_len % MAX_LRI_SIZE) != 0;
+
+   /* Return the size of MI_LOAD_REGISTER_IMMs. */
+   return n_lri * 4 + oa_config->mux_regs_len * 8;
+}
+
+u32 *i915_oa_emit_perctx_bb(struct intel_engine_cs *engine, u32 *batch)
+{
+   struct drm_i915_private *dev_priv = engine->i915;
+   struct i915_oa_config *oa_config;
+   u32 i, n_loaded_regs;
+
+   if (i915_oa_get_perctx_bb_size(engine) == 0)
+   return batch;
+
+   oa_config = dev_priv->perf.oa.exclusive_stream->oa_config;
+
+   n_loaded_regs = 0;
+   for (i = 0; i < oa_config->mux_regs_len; i++) {
+   if ((n_loaded_regs % MAX_LRI_SIZE) == 0) {
+   u32 n_lri = min(oa_config->mux_regs_len - n_loaded_regs,
+   MAX_LRI_SIZE);
+   *batch++ = MI_LOAD_REGISTER_IMM(n_lri);
+   }
+
+   *batch++ = i915_mmio_reg_offset(oa_config->mux_regs[i].addr);
+   *batch++ = oa_config->mux_regs[i].value;
+   n_loaded_regs++;
+   }
+
+   return batch;
+}
+
 static int gen8_switch_to_updated_kernel_context(struct drm_i915_private 
*dev_priv,
 const struct i915_oa_config 
*oa_config)
 {
@@ -1754,28 +1815,17 @@ static int gen8_switch_to_updated_kernel_context(struct 
drm_i915_private *dev_pr
  *
  * Note: it's only the RCS/Render context that has any OA state.
  */
-static int gen8_configure_all_contexts(struct drm_i915_private *dev_priv,
-  const struct i915_oa_config *oa_config,
-  bool interruptible)
+static int gen8_configure_all_contexts_unlocked(struct drm_i915_private 
*dev_priv,
+   const struct i915_oa_config 
*oa_config,
+   unsigned int wait_flags)
 {
struct i915_gem_context *ctx;
int ret;
-   unsigned int wait_flags = I915_WAIT_LOCKED;
-
-   if (interruptible) {
-   ret = i915_mutex_lock_interruptible(_priv->drm);
-   if (ret)
-   return ret;
-
-   wait_flags |= I915_WAIT_INTERRUPTIBLE;
-   } else {
-   mutex_lock(_priv->drm.struct_mutex);
-   }
 
/* Switch away from any user context. */
ret = gen8_switch_to_updated_kernel_context(dev_priv, oa_config);
   

[Intel-gfx] [PATCH v2 3/4] drm/i915: pass wa_ctx as argument

[Lionel Landwerlin]

Rather than accessing it from the engine structure. This will be used
for reprogramming later.

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/intel_lrc.c | 13 +++--
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 9ea5a56956e3..1cb67f8c0ff9 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1125,7 +1125,8 @@ static u32 *gen9_init_perctx_bb(struct intel_engine_cs 
*engine, u32 *batch)
 
 #define CTX_WA_BB_OBJ_SIZE (PAGE_SIZE)
 
-static int lrc_setup_wa_ctx(struct intel_engine_cs *engine)
+static int lrc_setup_wa_ctx(struct intel_engine_cs *engine,
+   struct i915_ctx_workarounds *wa_ctx)
 {
struct drm_i915_gem_object *obj;
struct i915_vma *vma;
@@ -1145,7 +1146,7 @@ static int lrc_setup_wa_ctx(struct intel_engine_cs 
*engine)
if (err)
goto err;
 
-   engine->wa_ctx.vma = vma;
+   wa_ctx->vma = vma;
return 0;
 
 err:
@@ -1160,9 +1161,9 @@ static void lrc_destroy_wa_ctx(struct intel_engine_cs 
*engine)
 
 typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch);
 
-static int intel_init_workaround_bb(struct intel_engine_cs *engine)
+static int intel_init_workaround_bb(struct intel_engine_cs *engine,
+   struct i915_ctx_workarounds *wa_ctx)
 {
-   struct i915_ctx_workarounds *wa_ctx = >wa_ctx;
struct i915_wa_ctx_bb *wa_bb[2] = { _ctx->indirect_ctx,
_ctx->per_ctx };
wa_bb_func_t wa_bb_fn[2];
@@ -1190,7 +1191,7 @@ static int intel_init_workaround_bb(struct 
intel_engine_cs *engine)
return 0;
}
 
-   ret = lrc_setup_wa_ctx(engine);
+   ret = lrc_setup_wa_ctx(engine, wa_ctx);
if (ret) {
DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
return ret;
@@ -1829,7 +1830,7 @@ int logical_render_ring_init(struct intel_engine_cs 
*engine)
if (ret)
return ret;
 
-   ret = intel_init_workaround_bb(engine);
+   ret = intel_init_workaround_bb(engine, >wa_ctx);
if (ret) {
/*
 * We continue even if we fail to initialize WA batch
-- 
2.14.1

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[Intel-gfx] [PATCH v2 0/4] drm/i915: implement NOA mux reprogramming at ctx-switch

[Lionel Landwerlin]

Some pertinent changes suggested by Chris. The most important one
being using the indirect-ctx batchbuffer.

Cheers,

Lionel Landwerlin (4):
  drm/i915: don't specify pinned size for wa_bb pin/allocation
  drm/i915: extract per-ctx/indirect bb programming
  drm/i915: pass wa_ctx as argument
  drm/i915: reprogram NOA muxes on context switch when using perf

 drivers/gpu/drm/i915/i915_drv.h  |   2 +
 drivers/gpu/drm/i915/i915_perf.c | 130 ---
 drivers/gpu/drm/i915/intel_lrc.c | 113 ++
 drivers/gpu/drm/i915/intel_lrc.h |   1 +
 4 files changed, 187 insertions(+), 59 deletions(-)

--
2.14.1
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[Intel-gfx] [PATCH v2 1/4] drm/i915: don't specify pinned size for wa_bb pin/allocation

[Lionel Landwerlin]

We can rely on the i915_vma_pin() to use vma->size instead.

v2: Actually set the pin size to 0 to vma->size is used implicitly
(Chris)

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/intel_lrc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 3758ff81928d..09fb2b29a739 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1141,7 +1141,7 @@ static int lrc_setup_wa_ctx(struct intel_engine_cs 
*engine)
goto err;
}
 
-   err = i915_vma_pin(vma, 0, PAGE_SIZE, PIN_GLOBAL | PIN_HIGH);
+   err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
if (err)
goto err;
 
-- 
2.14.1

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[Intel-gfx] [PATCH v2] drm/i915: Disable DRRS when PSR is enabled

[Radhakrishna Sripada]

Some platforms donot support PSR and DRRS simultaneously.
Visual artifacts and flickering were reported on BDW HP Spectre
x360 Convertible. Deferring to PSR when both PSR and DRRS are
supported by the panel.

V2: Minor code-style changes suggested by Rodrigo

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=10
Cc: Nicholas Stommel 
Cc: Dhinakaran Pandiyan 
Cc: Jani Nikula 
Cc: Clinton Taylor 
Cc: Rodrigo Vivi 
Signed-off-by: Radhakrishna Sripada 
---
 drivers/gpu/drm/i915/intel_dp.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 887953c0f495..aa5a69301257 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5467,11 +5467,6 @@ static void intel_dp_set_drrs_state(struct 
drm_i915_private *dev_priv,
return;
}
 
-   /*
-* FIXME: This needs proper synchronization with psr state for some
-* platforms that cannot have PSR and DRRS enabled at the same time.
-*/
-
dig_port = dp_to_dig_port(intel_dp);
encoder = _port->base;
intel_crtc = to_intel_crtc(encoder->base.crtc);
@@ -,6 +5550,11 @@ void intel_edp_drrs_enable(struct intel_dp *intel_dp,
return;
}
 
+   if (dev_priv->psr.enabled) {
+   DRM_DEBUG_KMS("PSR enabled. Disabling DRRS.\n");
+   return;
+   }
+
mutex_lock(_priv->drrs.mutex);
if (WARN_ON(dev_priv->drrs.dp)) {
DRM_ERROR("DRRS already enabled\n");
-- 
2.9.3

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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm: Fix example comment of format modifier blob

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm: Fix example comment of format modifier 
blob
URL   : https://patchwork.freedesktop.org/series/29627/
State : success

== Summary ==

Series 29627v1 series starting with [1/2] drm: Fix example comment of format 
modifier blob
https://patchwork.freedesktop.org/api/1.0/series/29627/revisions/1/mbox/

Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
pass   -> FAIL   (fi-snb-2600) fdo#100215
Subgroup basic-flip-after-cursor-varying-size:
fail   -> PASS   (fi-hsw-4770) fdo#102402 +1

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#102402 https://bugs.freedesktop.org/show_bug.cgi?id=102402

fi-bdw-5557u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:455s
fi-bdw-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:448s
fi-blb-e6850 total:288  pass:224  dwarn:1   dfail:0   fail:0   skip:63  
time:357s
fi-bsw-n3050 total:288  pass:243  dwarn:0   dfail:0   fail:0   skip:45  
time:561s
fi-bwr-2160  total:288  pass:184  dwarn:0   dfail:0   fail:0   skip:104 
time:253s
fi-bxt-j4205 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:523s
fi-byt-j1900 total:288  pass:254  dwarn:1   dfail:0   fail:0   skip:33  
time:522s
fi-byt-n2820 total:288  pass:250  dwarn:1   dfail:0   fail:0   skip:37  
time:521s
fi-elk-e7500 total:288  pass:230  dwarn:0   dfail:0   fail:0   skip:58  
time:440s
fi-glk-2atotal:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:610s
fi-hsw-4770  total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  
time:460s
fi-hsw-4770r total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  
time:426s
fi-ilk-650   total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:424s
fi-ivb-3520m total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:499s
fi-ivb-3770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:477s
fi-kbl-7500u total:288  pass:264  dwarn:1   dfail:0   fail:0   skip:23  
time:512s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:601s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:607s
fi-pnv-d510  total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:529s
fi-skl-6260u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:473s
fi-skl-6700k total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:536s
fi-skl-6770hqtotal:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:489s
fi-skl-gvtdvmtotal:288  pass:266  dwarn:0   dfail:0   fail:0   skip:22  
time:444s
fi-skl-x1585ltotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:495s
fi-snb-2520m total:288  pass:251  dwarn:0   dfail:0   fail:0   skip:37  
time:551s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:2   skip:38  
time:404s

ccf4ca2d93383fe1a234aba83df9c21400216433 drm-tip: 2017y-08m-31d-18h-37m-46s UTC 
integration manifest
ead24675c00f drm/i915: Fail addfb ioctl if color and CCS buffers overlap
2371d5210288 drm: Fix example comment of format modifier blob

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5552/
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Re: [Intel-gfx] [PATCH 2/2] drm/i915: Fail addfb ioctl if color and CCS buffers overlap

[Ben Widawsky]

On 17-08-31 16:52:15, Gabriel Krisman Bertazi wrote:

With this patch the new testcase igt@kms_ccs@pipe-X-invalid-ccs-offset
succeeds.

Signed-off-by: Gabriel Krisman Bertazi 
---
drivers/gpu/drm/i915/intel_display.c | 5 +
1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index b28f076f98bc..ff1ed67a9eff 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13989,6 +13989,11 @@ static int intel_framebuffer_init(struct 
intel_framebuffer *intel_fb,
DRM_DEBUG_KMS("RC supported only with RGB 
formats\n");
goto err;
}
+
+   if (mode_cmd->offsets[1] < mode_cmd->pitches[0]) {
+   DRM_DEBUG_KMS("CCS and color buffers overlap\n");
+   return -EINVAL;
+   }


This check doesn't look nearly strict enough to determine overlap. All it's
checking is that the aux buffer isn't in the first row of the main buffer.
Second of all, while today our requirement is that the aux buffer always come
after the main buffer, that may not be the case forever.


/* fall through */
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Yf_TILED:
--
2.11.0


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[Intel-gfx] ✓ Fi.CI.IGT: success for Improve robustness of the i915 perf tests (rev3)

[Patchwork]

== Series Details ==

Series: Improve robustness of the i915 perf tests (rev3)
URL   : https://patchwork.freedesktop.org/series/28373/
State : success

== Summary ==

Test perf:
Subgroup polling:
fail   -> PASS   (shard-hsw) fdo#102252
Subgroup oa-exponents:
fail   -> PASS   (shard-hsw) fdo#102254
Test kms_flip:
Subgroup plain-flip-fb-recreate:
fail   -> PASS   (shard-hsw)
Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-hsw) fdo#99912

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#102254 https://bugs.freedesktop.org/show_bug.cgi?id=102254
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912

shard-hswtotal:2266 pass:1233 dwarn:0   dfail:0   fail:16  skip:1017 
time:9702s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_132/shards.html
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Re: [Intel-gfx] [PATCH 1/2] drm: Fix example comment of format modifier blob

[Ben Widawsky]

On 17-08-31 16:52:14, Gabriel Krisman Bertazi wrote:

To represent formats 98-102, the supported formats mask must be
0x7c and not 0x3c.

Signed-off-by: Gabriel Krisman Bertazi 
---
include/uapi/drm/drm_mode.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 54fc38c3c3f1..34b6bb34b002 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -749,9 +749,9 @@ struct drm_format_modifier {
 * If the number formats grew to 128, and formats 98-102 are
 * supported with the modifier:
 *
-* 0x003c 
+* 0x007c 
 *^
-*|__offset = 64, formats = 0x3c
+*|__offset = 64, formats = 0x7c
 *
 */
__u64 formats;
--



hex(0x1f << 98)

'0x7c'
Reviewed-by: Ben Widawsky 
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Fix the missing PPAT cache attributes on CNL

[Patchwork]

== Series Details ==

Series: series starting with [1/4] drm/i915: Fix the missing PPAT cache 
attributes on CNL
URL   : https://patchwork.freedesktop.org/series/29625/
State : success

== Summary ==

Series 29625v1 series starting with [1/4] drm/i915: Fix the missing PPAT cache 
attributes on CNL
https://patchwork.freedesktop.org/api/1.0/series/29625/revisions/1/mbox/

Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-legacy:
fail   -> PASS   (fi-snb-2600) fdo#100215

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215

fi-bdw-5557u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:454s
fi-bdw-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:444s
fi-blb-e6850 total:288  pass:224  dwarn:1   dfail:0   fail:0   skip:63  
time:360s
fi-bsw-n3050 total:288  pass:243  dwarn:0   dfail:0   fail:0   skip:45  
time:565s
fi-bwr-2160  total:288  pass:184  dwarn:0   dfail:0   fail:0   skip:104 
time:255s
fi-bxt-j4205 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:520s
fi-byt-j1900 total:288  pass:254  dwarn:1   dfail:0   fail:0   skip:33  
time:519s
fi-byt-n2820 total:288  pass:250  dwarn:1   dfail:0   fail:0   skip:37  
time:513s
fi-elk-e7500 total:288  pass:230  dwarn:0   dfail:0   fail:0   skip:58  
time:440s
fi-glk-2atotal:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:612s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:2   skip:25  
time:462s
fi-hsw-4770r total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  
time:425s
fi-ilk-650   total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:430s
fi-ivb-3520m total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:498s
fi-ivb-3770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:475s
fi-kbl-7500u total:288  pass:264  dwarn:1   dfail:0   fail:0   skip:23  
time:512s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:598s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:596s
fi-pnv-d510  total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:534s
fi-skl-6260u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:476s
fi-skl-6700k total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:531s
fi-skl-6770hqtotal:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:492s
fi-skl-gvtdvmtotal:288  pass:266  dwarn:0   dfail:0   fail:0   skip:22  
time:440s
fi-skl-x1585ltotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:492s
fi-snb-2520m total:288  pass:251  dwarn:0   dfail:0   fail:0   skip:37  
time:552s
fi-snb-2600  total:288  pass:250  dwarn:0   dfail:0   fail:0   skip:38  
time:400s

ccf4ca2d93383fe1a234aba83df9c21400216433 drm-tip: 2017y-08m-31d-18h-37m-46s UTC 
integration manifest
ab2d80605ded drm/i915: Do not allocate unused PPAT entries
28bf9054fe62 drm/i915: Introduce private PAT management
9158415d66aa drm/i915: Factor out setup_private_pat()
32d0d72d1732 drm/i915: Fix the missing PPAT cache attributes on CNL

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5551/
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[Intel-gfx] [PATCH 2/2] drm/i915: Fail addfb ioctl if color and CCS buffers overlap

[Gabriel Krisman Bertazi]

With this patch the new testcase igt@kms_ccs@pipe-X-invalid-ccs-offset
succeeds.

Signed-off-by: Gabriel Krisman Bertazi 
---
 drivers/gpu/drm/i915/intel_display.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index b28f076f98bc..ff1ed67a9eff 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13989,6 +13989,11 @@ static int intel_framebuffer_init(struct 
intel_framebuffer *intel_fb,
DRM_DEBUG_KMS("RC supported only with RGB 
formats\n");
goto err;
}
+
+   if (mode_cmd->offsets[1] < mode_cmd->pitches[0]) {
+   DRM_DEBUG_KMS("CCS and color buffers overlap\n");
+   return -EINVAL;
+   }
/* fall through */
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Yf_TILED:
-- 
2.11.0

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[Intel-gfx] [PATCH 1/2] drm: Fix example comment of format modifier blob

[Gabriel Krisman Bertazi]

To represent formats 98-102, the supported formats mask must be
0x7c and not 0x3c.

Signed-off-by: Gabriel Krisman Bertazi 
---
 include/uapi/drm/drm_mode.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 54fc38c3c3f1..34b6bb34b002 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -749,9 +749,9 @@ struct drm_format_modifier {
 * If the number formats grew to 128, and formats 98-102 are
 * supported with the modifier:
 *
-* 0x003c 
+* 0x007c 
 *^
-*|__offset = 64, formats = 0x3c
+*|__offset = 64, formats = 0x7c
 *
 */
__u64 formats;
-- 
2.11.0

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[Intel-gfx] [PATCH 4/4] drm/i915: Do not allocate unused PPAT entries

[Zhi Wang]

Only PPAT entries 0/2/3/4 are using. Remove extra PPAT entry allocation
during initialization.

Cc: Ben Widawsky 
Cc: Rodrigo Vivi 
Cc: Chris Wilson 
Suggested-by: Joonas Lahtinen 
Signed-off-by: Zhi Wang 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 46 -
 drivers/gpu/drm/i915/i915_gem_gtt.h |  7 ++
 2 files changed, 27 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 51bb382..57f719d 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2988,18 +2988,15 @@ static void cnl_setup_private_ppat(struct intel_ppat 
*ppat)
 
/* XXX: spec is unclear if this is still needed for CNL+ */
if (!USES_PPGTT(ppat->i915)) {
-   __alloc_ppat_entry(ppat, 0, GEN8_PPAT_UC);
+   __alloc_ppat_entry(ppat, 
ppat_bits_to_index(PPAT_CACHED_PDE_INDEX), GEN8_PPAT_UC);
return;
}
 
-   __alloc_ppat_entry(ppat, 0, GEN8_PPAT_WB | GEN8_PPAT_LLC);
-   __alloc_ppat_entry(ppat, 1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC);
-   __alloc_ppat_entry(ppat, 2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);
-   __alloc_ppat_entry(ppat, 3, GEN8_PPAT_UC);
-   __alloc_ppat_entry(ppat, 4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | 
GEN8_PPAT_AGE(0));
-   __alloc_ppat_entry(ppat, 5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | 
GEN8_PPAT_AGE(1));
-   __alloc_ppat_entry(ppat, 6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | 
GEN8_PPAT_AGE(2));
-   __alloc_ppat_entry(ppat, 7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | 
GEN8_PPAT_AGE(3));
+   /* See gen8_pte_encode() for the mapping from cache-level to PPAT */
+   __alloc_ppat_entry(ppat, ppat_bits_to_index(PPAT_CACHED_PDE_INDEX), 
GEN8_PPAT_WB | GEN8_PPAT_LLC);
+   __alloc_ppat_entry(ppat, ppat_bits_to_index(PPAT_DISPLAY_ELLC_INDEX), 
GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);
+   __alloc_ppat_entry(ppat, ppat_bits_to_index(PPAT_UNCACHED_INDEX), 
GEN8_PPAT_UC);
+   __alloc_ppat_entry(ppat, ppat_bits_to_index(PPAT_CACHED_INDEX), 
GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0));
 }
 
 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
@@ -3026,18 +3023,18 @@ static void bdw_setup_private_ppat(struct intel_ppat 
*ppat)
 * So we can still hold onto all our assumptions wrt cpu
 * clflushing on LLC machines.
 */
-   __alloc_ppat_entry(ppat, 0, GEN8_PPAT_UC);
+   __alloc_ppat_entry(ppat, 
ppat_bits_to_index(PPAT_CACHED_PDE_INDEX), GEN8_PPAT_UC);
return;
}
 
-   __alloc_ppat_entry(ppat, 0, GEN8_PPAT_WB | GEN8_PPAT_LLC);  /* for 
normal objects, no eLLC */
-   __alloc_ppat_entry(ppat, 1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC);  /* for 
something pointing to ptes? */
-   __alloc_ppat_entry(ppat, 2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);  /* for 
scanout with eLLC */
-   __alloc_ppat_entry(ppat, 3, GEN8_PPAT_UC);  /* 
Uncached objects, mostly for scanout */
-   __alloc_ppat_entry(ppat, 4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | 
GEN8_PPAT_AGE(0));
-   __alloc_ppat_entry(ppat, 5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | 
GEN8_PPAT_AGE(1));
-   __alloc_ppat_entry(ppat, 6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | 
GEN8_PPAT_AGE(2));
-   __alloc_ppat_entry(ppat, 7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | 
GEN8_PPAT_AGE(3));
+   /* See gen8_pte_encode() for the mapping from cache-level to PPAT */
+   /* for normal objects, no eLLC */
+   __alloc_ppat_entry(ppat, ppat_bits_to_index(PPAT_CACHED_PDE_INDEX), 
GEN8_PPAT_WB | GEN8_PPAT_LLC);
+   /* for scanout with eLLC */
+   __alloc_ppat_entry(ppat, ppat_bits_to_index(PPAT_DISPLAY_ELLC_INDEX), 
GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);
+   /* Uncached objects, mostly for scanout */
+   __alloc_ppat_entry(ppat, ppat_bits_to_index(PPAT_UNCACHED_INDEX), 
GEN8_PPAT_UC);
+   __alloc_ppat_entry(ppat, ppat_bits_to_index(PPAT_CACHED_INDEX), 
GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0));
 }
 
 static void chv_setup_private_ppat(struct intel_ppat *ppat)
@@ -3066,14 +3063,11 @@ static void chv_setup_private_ppat(struct intel_ppat 
*ppat)
 * in order to keep the global status page working.
 */
 
-   __alloc_ppat_entry(ppat, 0, CHV_PPAT_SNOOP);
-   __alloc_ppat_entry(ppat, 1, 0);
-   __alloc_ppat_entry(ppat, 2, 0);
-   __alloc_ppat_entry(ppat, 3, 0);
-   __alloc_ppat_entry(ppat, 4, CHV_PPAT_SNOOP);
-   __alloc_ppat_entry(ppat, 5, CHV_PPAT_SNOOP);
-   __alloc_ppat_entry(ppat, 6, CHV_PPAT_SNOOP);
-   __alloc_ppat_entry(ppat, 7, CHV_PPAT_SNOOP);
+   /* See gen8_pte_encode() for the mapping from cache-level to PPAT */
+   __alloc_ppat_entry(ppat, ppat_bits_to_index(PPAT_CACHED_PDE_INDEX), 
CHV_PPAT_SNOOP);
+   

[Intel-gfx] [PATCH 2/4] drm/i915: Factor out setup_private_pat()

[Zhi Wang]

Factor out setup_private_pat() for introducing the following patches.

Cc: Ben Widawsky 
Cc: Rodrigo Vivi 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Signed-off-by: Zhi Wang 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 20 
 1 file changed, 12 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index f18b1ec..d643648 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2915,6 +2915,16 @@ static void gen6_gmch_remove(struct i915_address_space 
*vm)
cleanup_scratch_page(vm);
 }
 
+static void setup_private_pat(struct drm_i915_private *dev_priv)
+{
+   if (INTEL_GEN(dev_priv) >= 10)
+   cnl_setup_private_ppat(dev_priv);
+   else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
+   chv_setup_private_ppat(dev_priv);
+   else
+   bdw_setup_private_ppat(dev_priv);
+}
+
 static int gen8_gmch_probe(struct i915_ggtt *ggtt)
 {
struct drm_i915_private *dev_priv = ggtt->base.i915;
@@ -2947,14 +2957,6 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
}
 
ggtt->base.total = (size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
-
-   if (INTEL_GEN(dev_priv) >= 10)
-   cnl_setup_private_ppat(dev_priv);
-   else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
-   chv_setup_private_ppat(dev_priv);
-   else
-   bdw_setup_private_ppat(dev_priv);
-
ggtt->base.cleanup = gen6_gmch_remove;
ggtt->base.bind_vma = ggtt_bind_vma;
ggtt->base.unbind_vma = ggtt_unbind_vma;
@@ -2975,6 +2977,8 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
 
ggtt->invalidate = gen6_ggtt_invalidate;
 
+   setup_private_pat(dev_priv);
+
return ggtt_probe_common(ggtt, size);
 }
 
-- 
2.7.4

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[Intel-gfx] [PATCH 3/4] drm/i915: Introduce private PAT management

[Zhi Wang]

The private PAT management is to support PPAT entry manipulation. Two
APIs are introduced for dynamically managing PPAT entries: intel_ppat_get
and intel_ppat_put.

intel_ppat_get will search for an existing PPAT entry which perfectly
matches the required PPAT value. If not, it will try to allocate or
return a partially matched PPAT entry if there is any available PPAT
indexes or not.

intel_ppat_put will put back the PPAT entry which comes from
intel_ppat_get. If it's dynamically allocated, the reference count will
be decreased. If the reference count turns into zero, the PPAT index is
freed again.

Besides, another two callbacks are introduced to support the private PAT
management framework. One is ppat->update_hw(), which writes the PPAT
configurations in ppat->entries into HW. Another one is ppat->match, which
will return a score to show how two PPAT values match with each other.

v7:

- Keep all the register writes unchanged in this patch. (Joonas)

v6:

- Address all comments from Chris:
http://www.spinics.net/lists/intel-gfx/msg136850.html

- Address all comments from Joonas:
http://www.spinics.net/lists/intel-gfx/msg136845.html

v5:

- Add check and warnnings for those platforms which don't have PPAT.

v3:

- Introduce dirty bitmap for PPAT registers. (Chris)
- Change the name of the pointer "dev_priv" to "i915". (Chris)
- intel_ppat_{get, put} returns/takes a const intel_ppat_entry *. (Chris)

v2:

- API re-design. (Chris)

Cc: Ben Widawsky 
Cc: Rodrigo Vivi 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Signed-off-by: Zhi Wang 
---
 drivers/gpu/drm/i915/i915_drv.h |   2 +
 drivers/gpu/drm/i915/i915_gem_gtt.c | 279 +---
 drivers/gpu/drm/i915/i915_gem_gtt.h |  36 +
 3 files changed, 268 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7587ef5..5ffde10 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2312,6 +2312,8 @@ struct drm_i915_private {
DECLARE_HASHTABLE(mm_structs, 7);
struct mutex mm_lock;
 
+   struct intel_ppat ppat;
+
/* Kernel Modesetting */
 
struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index d643648..51bb382 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2816,41 +2816,203 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, 
u64 size)
return 0;
 }
 
-static void cnl_setup_private_ppat(struct drm_i915_private *dev_priv)
+static struct intel_ppat_entry *
+__alloc_ppat_entry(struct intel_ppat *ppat, unsigned int index, u8 value)
 {
+   struct intel_ppat_entry *entry = >entries[index];
+
+   GEM_BUG_ON(index >= ppat->max_entries);
+   GEM_BUG_ON(test_bit(index, ppat->used));
+
+   entry->ppat = ppat;
+   entry->value = value;
+   kref_init(>ref);
+   set_bit(index, ppat->used);
+   set_bit(index, ppat->dirty);
+
+   return entry;
+}
+
+static void __free_ppat_entry(struct intel_ppat_entry *entry)
+{
+   struct intel_ppat *ppat = entry->ppat;
+   unsigned int index = entry - ppat->entries;
+
+   GEM_BUG_ON(index >= ppat->max_entries);
+   GEM_BUG_ON(!test_bit(index, ppat->used));
+
+   entry->value = ppat->clear_value;
+   clear_bit(index, ppat->used);
+   set_bit(index, ppat->dirty);
+}
+
+/**
+ * intel_ppat_get - get a usable PPAT entry
+ * @i915: i915 device instance
+ * @value: the PPAT value required by the caller
+ *
+ * The function tries to search if there is an existing PPAT entry which
+ * matches with the required value. If perfectly matched, the existing PPAT
+ * entry will be used. If only partially matched, it will try to check if
+ * there is any available PPAT index. If yes, it will allocate a new PPAT
+ * index for the required entry and update the HW. If not, the partially
+ * matched entry will be used.
+ */
+const struct intel_ppat_entry *
+intel_ppat_get(struct drm_i915_private *i915, u8 value)
+{
+   struct intel_ppat *ppat = >ppat;
+   struct intel_ppat_entry *entry;
+   unsigned int scanned, best_score;
+   int i;
+
+   GEM_BUG_ON(!ppat->max_entries);
+
+   scanned = best_score = 0;
+
+   for_each_set_bit(i, ppat->used, ppat->max_entries) {
+   unsigned int score;
+
+   entry = >entries[i];
+   score = ppat->match(entry->value, value);
+   if (score > best_score) {
+   if (score == INTEL_PPAT_PERFECT_MATCH) {
+   kref_get(>ref);
+   return entry;
+   }
+   best_score = score;
+   }
+   scanned++;
+   }
+
+   if (scanned == 

[Intel-gfx] [PATCH 1/4] drm/i915: Fix the missing PPAT cache attributes on CNL

[Zhi Wang]

Add back the GEN8_PPAT_WB cache attributes in cnl_setup_private_ppat(),
which are missed on CNL.

Fixes: e34935 ("drm/i915/cnl: Setup PAT Index")
Cc: Ben Widawsky 
Cc: Rodrigo Vivi 
Cc: Chris Wilson 
Suggested-by: Joonas Lahtinen 
Signed-off-by: Zhi Wang 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 708b95c..f18b1ec 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2828,10 +2828,10 @@ static void cnl_setup_private_ppat(struct 
drm_i915_private *dev_priv)
I915_WRITE(GEN10_PAT_INDEX(1), GEN8_PPAT_WC | GEN8_PPAT_LLCELLC);
I915_WRITE(GEN10_PAT_INDEX(2), GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);
I915_WRITE(GEN10_PAT_INDEX(3), GEN8_PPAT_UC);
-   I915_WRITE(GEN10_PAT_INDEX(4), GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0));
-   I915_WRITE(GEN10_PAT_INDEX(5), GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1));
-   I915_WRITE(GEN10_PAT_INDEX(6), GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2));
-   I915_WRITE(GEN10_PAT_INDEX(7), GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
+   I915_WRITE(GEN10_PAT_INDEX(4), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | 
GEN8_PPAT_AGE(0));
+   I915_WRITE(GEN10_PAT_INDEX(5), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | 
GEN8_PPAT_AGE(1));
+   I915_WRITE(GEN10_PAT_INDEX(6), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | 
GEN8_PPAT_AGE(2));
+   I915_WRITE(GEN10_PAT_INDEX(7), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | 
GEN8_PPAT_AGE(3));
 }
 
 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
-- 
2.7.4

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[Intel-gfx] ✗ Fi.CI.IGT: failure for lib/tests: Add audio selftest (rev2)

[Patchwork]

== Series Details ==

Series: lib/tests: Add audio selftest (rev2)
URL   : https://patchwork.freedesktop.org/series/29550/
State : failure

== Summary ==

Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-hsw) fdo#99912
Test kms_flip:
Subgroup plain-flip-fb-recreate:
fail   -> PASS   (shard-hsw)
Subgroup plain-flip-ts-check-interruptible:
pass   -> FAIL   (shard-hsw)
Test perf:
Subgroup polling:
fail   -> PASS   (shard-hsw) fdo#102252 +1

fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hswtotal:2265 pass:1230 dwarn:0   dfail:0   fail:19  skip:1016 
time:9632s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_131/shards.html
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Re: [Intel-gfx] [PATCH 00/13] mmu_notifier kill invalidate_page callback

[Jerome Glisse]

On Thu, Aug 31, 2017 at 02:39:17PM -0400, Felix Kuehling wrote:
> On 2017-08-31 09:59 AM, Jerome Glisse wrote:
> > [Adding Intel folks as they might be interested in this discussion]
> >
> > On Wed, Aug 30, 2017 at 05:51:52PM -0400, Felix Kuehling wrote:
> >> Hi Jérôme,
> >>
> >> I have some questions about the potential range-start-end race you
> >> mentioned.
> >>
> >> On 2017-08-29 07:54 PM, Jérôme Glisse wrote:
> >>> Note that a lot of existing user feels broken in respect to range_start/
> >>> range_end. Many user only have range_start() callback but there is nothing
> >>> preventing them to undo what was invalidated in their range_start() 
> >>> callback
> >>> after it returns but before any CPU page table update take place.
> >>>
> >>> The code pattern use in kvm or umem odp is an example on how to properly
> >>> avoid such race. In a nutshell use some kind of sequence number and active
> >>> range invalidation counter to block anything that might undo what the
> >>> range_start() callback did.
> >> What happens when we start monitoring an address range after
> >> invaligate_range_start was called? Sounds like we have to keep track of
> >> all active invalidations for just such a case, even in address ranges
> >> that we don't currently care about.
> >>
> >> What are the things we cannot do between invalidate_range_start and
> >> invalidate_range_end? amdgpu calls get_user_pages to re-validate our
> >> userptr mappings after the invalidate_range_start notifier invalidated
> >> it. Do we have to wait for invalidate_range_end before we can call
> >> get_user_pages safely?
> > Well the whole userptr bo object is somewhat broken from the start.
> > You never defined the semantic of it ie what is expected. I can
> > think of 2 differents semantics:
> >   A) a uptr buffer object is a snapshot of a memory at the time of
> >  uptr buffer object creation
> >   B) a uptr buffer object allow GPU to access a range of virtual
> >  address of a process an share coherent view of that range
> >  between CPU and GPU
> >
> > As it was implemented it is more inline with B but it is not defined
> > anywhere AFAICT.
> 
> Yes, we're trying to achieve B, that's why we have an MMU notifier in
> the first place. But it's been a struggle getting it to work properly,
> and we're still dealing with some locking issues and now this one.
> 
> >
> > Anyway getting back to your questions, it kind of doesn't matter as
> > you are using GUP ie you are pinning pages except for one scenario
> > (at least i can only think of one).
> >
> > Problematic case is race between CPU write to zero page or COW and
> > GPU driver doing read only GUP:
> [...]
> 
> Thanks, I was aware of COW but not of the zero-page case. I believe in
> most practical cases our userptr mappings are read-write, so this is
> probably not causing us any real trouble at the moment.
> 
> > So i would first define the semantic of uptr bo and then i would fix
> > accordingly the code. Semantic A is easier to implement and you could
> > just drop the whole mmu_notifier. Maybe it is better to create uptr
> > buffer object everytime you want to snapshot a range of address. I
> > don't think the overhead of buffer creation would matter.
> 
> That doesn't work for KFD and our compute memory model where CPU and GPU
> expect to share the same address space.
> 
> >
> > If you want to close the race for COW and zero page in case of read
> > only GUP there is no other way than what KVM or ODP is doing. I had
> > patchset to simplify all this but i need to bring it back to life.
> 
> OK. I'll look at these to get an idea.
> 
> > Note that other thing might race but as you pin the pages they do
> > not matter. It just mean that if you GUP after range_start() but
> > before range_end() and before CPU page table update then you pinned
> > the same old page again and nothing will happen (migrate will fail,
> > MADV_FREE will nop, ...). So you just did the range_start() callback
> > for nothing in those cases.
> 
> We pin the memory because the GPU wants to access it. So this is
> probably OK if the migration fails. However, your statement that we
> "just did the range_start() callback for nothing" implies that we could
> as well have ignored the range_start callback. But I don't think that's
> true. That way we'd keep a page pinned that is no longer mapped in the
> CPU address space. So the GPU mapping would be out of sync with the CPU
> mapping.

Here is an example of "for nothing":
CPU0CPU1
> migrate page at addr A
  > invalidate_start addr A
> unbind_ttm(for addr A)
> use ttm object for addr A
> GUP addr A
  > page table update
  > invalidate_end addr A
  > refcount check fails because
of GUP
  > restore page table to A

This is what i meant by range_start() for nothing on CPU0 you invalidated
ttm object for nothing 

Re: [Intel-gfx] [PATCH 4/7] drm/i915: Pass proper old/new states to intel_plane_atomic_check_with_state()

[Ville Syrjälä]

On Wed, Aug 23, 2017 at 06:22:23PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä 
> 
> Eliminate plane->state and crtc->state usage from
> intel_plane_atomic_check_with_state() and its callers. Instead pass the
> proper states in or dig them up from the top level atomic state.
> 
> Note that intel_plane_atomic_check_with_state() itself isn't allowed to
> use the top level atomic state as there is none when it gets called from
> the legacy cursor short circuit path.
> 
> v2: Rename some variables for easier comprehension (Maarten)
> 
> Cc: Maarten Lankhorst 
> Signed-off-by: Ville Syrjälä 

This patch would still need some review love... In the meantime I
pushed the first three patches from the series. Thanks for the reviews
thus far.

> ---
>  drivers/gpu/drm/i915/intel_atomic_plane.c | 49 
> +++
>  drivers/gpu/drm/i915/intel_display.c  | 12 
>  drivers/gpu/drm/i915/intel_drv.h  | 16 --
>  3 files changed, 51 insertions(+), 26 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c 
> b/drivers/gpu/drm/i915/intel_atomic_plane.c
> index ee76fab7bb6f..8e6dc159f64d 100644
> --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
> @@ -107,7 +107,9 @@ intel_plane_destroy_state(struct drm_plane *plane,
>   drm_atomic_helper_plane_destroy_state(plane, state);
>  }
>  
> -int intel_plane_atomic_check_with_state(struct intel_crtc_state *crtc_state,
> +int intel_plane_atomic_check_with_state(const struct intel_crtc_state 
> *old_crtc_state,
> + struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state 
> *old_plane_state,
>   struct intel_plane_state *intel_state)
>  {
>   struct drm_plane *plane = intel_state->base.plane;
> @@ -124,7 +126,7 @@ int intel_plane_atomic_check_with_state(struct 
> intel_crtc_state *crtc_state,
>* anything driver-specific we need to test in that case, so
>* just return success.
>*/
> - if (!intel_state->base.crtc && !plane->state->crtc)
> + if (!intel_state->base.crtc && !old_plane_state->base.crtc)
>   return 0;
>  
>   /* Clip all planes to CRTC size, or 0x0 if CRTC is disabled */
> @@ -194,16 +196,21 @@ int intel_plane_atomic_check_with_state(struct 
> intel_crtc_state *crtc_state,
>   else
>   crtc_state->active_planes &= ~BIT(intel_plane->id);
>  
> - return intel_plane_atomic_calc_changes(_state->base, state);
> + return intel_plane_atomic_calc_changes(old_crtc_state,
> +_state->base,
> +old_plane_state,
> +state);
>  }
>  
>  static int intel_plane_atomic_check(struct drm_plane *plane,
> - struct drm_plane_state *state)
> + struct drm_plane_state *new_plane_state)
>  {
> - struct drm_crtc *crtc = state->crtc;
> - struct drm_crtc_state *drm_crtc_state;
> -
> - crtc = crtc ? crtc : plane->state->crtc;
> + struct drm_atomic_state *state = new_plane_state->state;
> + const struct drm_plane_state *old_plane_state =
> + drm_atomic_get_old_plane_state(state, plane);
> + struct drm_crtc *crtc = new_plane_state->crtc ?: old_plane_state->crtc;
> + const struct drm_crtc_state *old_crtc_state;
> + struct drm_crtc_state *new_crtc_state;
>  
>   /*
>* Both crtc and plane->crtc could be NULL if we're updating a
> @@ -214,29 +221,33 @@ static int intel_plane_atomic_check(struct drm_plane 
> *plane,
>   if (!crtc)
>   return 0;
>  
> - drm_crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
> - if (WARN_ON(!drm_crtc_state))
> - return -EINVAL;
> + old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc);
> + new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
>  
> - return 
> intel_plane_atomic_check_with_state(to_intel_crtc_state(drm_crtc_state),
> -to_intel_plane_state(state));
> + return 
> intel_plane_atomic_check_with_state(to_intel_crtc_state(old_crtc_state),
> +
> to_intel_crtc_state(new_crtc_state),
> +
> to_intel_plane_state(old_plane_state),
> +
> to_intel_plane_state(new_plane_state));
>  }
>  
>  static void intel_plane_atomic_update(struct drm_plane *plane,
> struct drm_plane_state *old_state)
>  {
> + struct intel_atomic_state *state = 
> to_intel_atomic_state(old_state->state);
>   struct 

Re: [Intel-gfx] [PATCH v4 1/2] drm/i915: Track minimum acceptable cdclk instead of "minimum dotclock"

[Ville Syrjälä]

On Wed, Aug 30, 2017 at 09:57:03PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä 
> 
> Make the min_pixclk thing less confusing by changing it to track
> the minimum acceptable cdclk frequency instead. This means moving
> the application of the guardbands to a slightly higher level from
> the low level platform specific calc_cdclk() functions.
> 
> The immediate benefit is elimination of the confusing 2x factors
> on GLK/CNL+ in the audio workarounds (which stems from the fact
> that the pipes produce two pixels per clock).
> 
> v2: Keep cdclk higher on CNL to workaround missing DDI clock voltage handling
> v3: Squash with the CNL cdclk limits patch (DK)
> v4: s/intel_min_cdclk/intel_pixel_rate_to_cdclk/ (DK)
> 
> Cc: Paulo Zanoni 
> Cc: Rodrigo Vivi 
> Cc: Dhinakaran Pandiyan 
> Cc: Maarten Lankhorst 
> Reviewed-by: Dhinakaran Pandiyan 
> Signed-off-by: Ville Syrjälä 

I didn't get any objections from the CNL camp, so I went ahead and
pushed the series. Thanks for the reviews.

-- 
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Intel OTC
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Re: [Intel-gfx] [PATCH] drm/i915/edp: Increase T12 panel delay to 900 ms to fix DP AUX CH timeouts

[Ville Syrjälä]

On Tue, Aug 15, 2017 at 11:59:51AM -0700, Manasi Navare wrote:
> This patch fixes the DP AUX CH timeouts observed during CI runs causing
> CI Failures on a specific PCI device. This issue was fixed previously
> by adding a quirk but looks like we need to increase this delay even more
> in order to get rid all the DP AUX CH timeouts.
> 
> Fixes: c99a259b4b5192ba ("drm/i915/edp: Add a T12 panel delay quirk to fix
> DP AUX CH timeouts")
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101144
> Signed-off-by: Manasi Navare 
> Cc: Clinton Taylor 
> Cc: Daniel Vetter 
> Cc: Tomi Sarvela 

I pushed this to dinq. Let's hope the errors stay away this time. Thanks
for the patch.


> ---
>  drivers/gpu/drm/i915/intel_dp.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 5ba8366..c4d8afa 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -5246,7 +5246,7 @@ intel_dp_init_panel_power_sequencer(struct drm_device 
> *dev,
>* seems sufficient to avoid this problem.
>*/
>   if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
> - vbt.t11_t12 = max_t(u16, vbt.t11_t12, 800 * 10);
> + vbt.t11_t12 = max_t(u16, vbt.t11_t12, 900 * 10);
>   DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to 
> %d\n",
> vbt.t11_t12);
>   }
> -- 
> 2.1.4
> 
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Re: [Intel-gfx] [RFCv6 2/2] drm/i915: Introduce private PAT management

[Wang, Zhi A]

I see why that is going wrong. I take Chris' comments directly like:

__alloc_ppat_entry(ppat, PPAT_CACHE_PDE_INDEX,), but 0 != 
PPAT_CACHE_PDE_INDEX actually. Wait my update.

Thanks,
Zhi.

-Original Message-
From: Rodrigo Vivi [mailto:rodrigo.v...@gmail.com] 
Sent: Thursday, August 31, 2017 8:15 AM
To: Wang, Zhi A 
Cc: Vivi, Rodrigo ; intel-gfx@lists.freedesktop.org; 
Widawsky, Benjamin ; 
intel-gvt-...@lists.freedesktop.org
Subject: Re: [Intel-gfx] [RFCv6 2/2] drm/i915: Introduce private PAT management

On Wed, Aug 30, 2017 at 9:49 PM, Zhi Wang  wrote:
> Hi Vivi:
> Thanks for the reply! The register are written in ppat->update_hw() now.

oh, I saw now...
I hadden noticed that interation.

But something seems really odd yet...
My CNL with these 2 patches applied hangs on any execution...

>
>
> +static void cnl_private_pat_update_hw(struct drm_i915_private 
> +*dev_priv) {
> +   struct intel_ppat *ppat = _priv->ppat;
> +   int i;
> +
> +   for_each_set_bit(i, ppat->dirty, ppat->max_entries) {
> +   I915_WRITE(GEN10_PAT_INDEX(i), ppat->entries[i].value);
> +   clear_bit(i, ppat->dirty);
> +   }
> +}
> +
> +static void bdw_private_pat_update_hw(struct drm_i915_private 
> +*dev_priv) {
> +   struct intel_ppat *ppat = _priv->ppat;
> +   u64 pat = 0;
> +   int i;
> +
> +   for (i = 0; i < ppat->max_entries; i++)
> +   pat |= GEN8_PPAT(i, ppat->entries[i].value);
> +
> +   bitmap_clear(ppat->dirty, 0, ppat->max_entries);
> +
> +   I915_WRITE(GEN8_PRIVATE_PAT_LO, lower_32_bits(pat));
> +   I915_WRITE(GEN8_PRIVATE_PAT_HI, upper_32_bits(pat)); }
>
> On 08/31/17 06:00, Vivi, Rodrigo wrote:
>>
>> On Wed, 2017-08-30 at 02:14 +0800, Zhi Wang wrote:
>>>
>>> The private PAT management is to support PPAT entry manipulation. 
>>> Two APIs are introduced for dynamically managing PPAT entries: 
>>> intel_ppat_get and intel_ppat_put.
>>>
>>> intel_ppat_get will search for an existing PPAT entry which 
>>> perfectly matches the required PPAT value. If not, it will try to 
>>> allocate or return a partially matched PPAT entry if there is any 
>>> available PPAT indexes or not.
>>>
>>> intel_ppat_put will put back the PPAT entry which comes from 
>>> intel_ppat_get. If it's dynamically allocated, the reference count 
>>> will be decreased. If the reference count turns into zero, the PPAT 
>>> index is freed again.
>>>
>>> Besides, another two callbacks are introduced to support the private 
>>> PAT management framework. One is ppat->update_hw(), which writes the 
>>> PPAT configurations in ppat->entries into HW. Another one is 
>>> ppat->match, which will return a score to show how two PPAT values 
>>> match with each other.
>>>
>>> v6:
>>>
>>> - Address all comments from Chris:
>>> http://www.spinics.net/lists/intel-gfx/msg136850.html
>>>
>>> - Address all comments from Joonas:
>>> http://www.spinics.net/lists/intel-gfx/msg136845.html
>>>
>>> v5:
>>>
>>> - Add check and warnnings for those platforms which don't have PPAT.
>>>
>>> v3:
>>>
>>> - Introduce dirty bitmap for PPAT registers. (Chris)
>>> - Change the name of the pointer "dev_priv" to "i915". (Chris)
>>> - intel_ppat_{get, put} returns/takes a const intel_ppat_entry *. 
>>> (Chris)
>>>
>>> v2:
>>>
>>> - API re-design. (Chris)
>>>
>>> Cc: Ben Widawsky 
>>> Cc: Rodrigo Vivi 
>>> Cc: Chris Wilson 
>>> Cc: Joonas Lahtinen 
>>> Signed-off-by: Zhi Wang 
>>> ---
>>>   drivers/gpu/drm/i915/i915_drv.h |   2 +
>>>   drivers/gpu/drm/i915/i915_gem_gtt.c | 273
>>> +---
>>>   drivers/gpu/drm/i915/i915_gem_gtt.h |  36 +
>>>   3 files changed, 262 insertions(+), 49 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h 
>>> b/drivers/gpu/drm/i915/i915_drv.h index 7587ef5..5ffde10 100644
>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>> @@ -2312,6 +2312,8 @@ struct drm_i915_private {
>>> DECLARE_HASHTABLE(mm_structs, 7);
>>> struct mutex mm_lock;
>>>   + struct intel_ppat ppat;
>>> +
>>> /* Kernel Modesetting */
>>> struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
>>> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
>>> b/drivers/gpu/drm/i915/i915_gem_gtt.c
>>> index b74fa9d..3106142 100644
>>> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
>>> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
>>> @@ -2816,41 +2816,200 @@ static int ggtt_probe_common(struct 
>>> i915_ggtt *ggtt, u64 size)
>>> return 0;
>>>   }
>>>   -static void cnl_setup_private_ppat(struct drm_i915_private 
>>> *dev_priv)
>>> +static struct intel_ppat_entry *
>>> +__alloc_ppat_entry(struct intel_ppat *ppat, unsigned int index, u8
>>> value)
>>>   {
>>> +   struct 

[Intel-gfx] ✓ Fi.CI.IGT: success for kms_ccs testcase improvements

[Patchwork]

== Series Details ==

Series: kms_ccs testcase improvements
URL   : https://patchwork.freedesktop.org/series/29585/
State : success

== Summary ==

Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-hsw) fdo#99912
Test kms_flip:
Subgroup plain-flip-fb-recreate-interruptible:
pass   -> FAIL   (shard-hsw) fdo#100368
Subgroup plain-flip-fb-recreate:
fail   -> PASS   (shard-hsw)
Test perf:
Subgroup polling:
fail   -> PASS   (shard-hsw) fdo#102252

fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hswtotal:2289 pass:1231 dwarn:0   dfail:0   fail:18  skip:1040 
time:9619s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_129/shards.html
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Re: [Intel-gfx] [PATCH] drm/i915: Disable DRRS when PSR is enabled

[Sripada, Radhakrishna]

> -Original Message-
> From: Vivi, Rodrigo
> Sent: Wednesday, August 30, 2017 5:59 PM
> To: Sripada, Radhakrishna 
> Cc: intel-gfx@lists.freedesktop.org; Pandiyan, Dhinakaran
> ; Nikula, Jani ;
> Taylor, Clinton A ; nicholas.stom...@gmail.com
> Subject: Re: [PATCH] drm/i915: Disable DRRS when PSR is enabled
> 
> On Wed, 2017-08-30 at 17:32 -0700, Radhakrishna Sripada wrote:
> > Some platforms donot support PSR and DRRS simultaneously. Deferring to
> > PSR when both PSR and DRRS are supported by the panel.
> >
> > Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=10
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=10
> 
> "Fixes: " is only used to -fixes cherry-picks. Not a case for this
> patch.
Got it. Will update in the next revision of the patch.
> 
> > Cc: Nicholas Stommel 
> > Cc: Dhinakaran Pandiyan 
> > Cc: Jani Nikula 
> > Cc: Clinton Taylor 
> > Cc: Rodrigo Vivi 
> > Signed-off-by: Radhakrishna Sripada 
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c | 10 +-
> >  1 file changed, 5 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c index d3e5fdf0d2fa..dc7a6721e0dd
> > 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -5469,11 +5469,6 @@ static void intel_dp_set_drrs_state(struct
> drm_i915_private *dev_priv,
> > return;
> > }
> >
> > -   /*
> > -* FIXME: This needs proper synchronization with psr state for some
> > -* platforms that cannot have PSR and DRRS enabled at the same
> time.
> > -*/
> > -
> > dig_port = dp_to_dig_port(intel_dp);
> > encoder = _port->base;
> > intel_crtc = to_intel_crtc(encoder->base.crtc);
> > @@ -5557,6 +5552,11 @@ void intel_edp_drrs_enable(struct intel_dp
> *intel_dp,
> > return;
> > }
> >
> > +   if (dev_priv->psr.enabled != NULL) {
> 
>   if (dev_priv->psr.enabled) {
> ?
This looks cleaner will use this in the follow up patch.
> 
> > +   DRM_DEBUG_KMS("PSR active. Disabling DRRS.\n");
> > +   return;
> > +   }
> > +
> > mutex_lock(_priv->drrs.mutex);
> > if (WARN_ON(dev_priv->drrs.dp)) {
> > DRM_ERROR("DRRS already enabled\n");

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[Intel-gfx] ✓ Fi.CI.IGT: success for tests/perf_pmu: test i915 RFC PMU (rev2)

[Patchwork]

== Series Details ==

Series: tests/perf_pmu: test i915 RFC PMU (rev2)
URL   : https://patchwork.freedesktop.org/series/29313/
State : success

== Summary ==

Test perf:
Subgroup blocking:
pass   -> FAIL   (shard-hsw) fdo#102252
Test kms_flip:
Subgroup plain-flip-fb-recreate:
fail   -> PASS   (shard-hsw)

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hswtotal:2270 pass:1231 dwarn:0   dfail:0   fail:22  skip:1017 
time:9623s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_128/shards.html
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Re: [Intel-gfx] [PATCH] drm/i915/cnl: Fix DP max voltage

[Vivi, Rodrigo]

On Thu, 2017-08-31 at 18:06 +0300, Ville Syrjälä wrote:
> On Thu, Aug 31, 2017 at 07:53:56AM -0700, Rodrigo Vivi wrote:
> > From: "Vivi, Rodrigo" 
> > 
> > On clock recovery this function is called to find out
> > the max voltage swing level that we could go.
> > 
> > However gen 9 functions use the old buffer translation tables
> > to figure that out. That table is not valid for CNL
> > causing an invalid number of entries and an invalid selection
> > on the max voltage swing level.
> > 
> > v2: Let's use same approach that previous platforms.
> > v3: Actually use n_entries and avoid duplicated -1.
> > v4: Avoid cnl_max_level and use current style.
> > 
> > Cc: Ville Syrjälä 
> > Cc: Clint Taylor 
> > Signed-off-by: Rodrigo Vivi 
> 
> Reviewed-by: Ville Syrjälä 

Thanks for the quick review.
Series merged to dinq. Hopefully we will be able to get CI happier
with drm-tip.


> > ---
> >  drivers/gpu/drm/i915/intel_ddi.c | 15 +++
> >  1 file changed, 11 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> > b/drivers/gpu/drm/i915/intel_ddi.c
> > index f1757a8e481a..1da3bb2cc4b4 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -1879,10 +1879,17 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder 
> > *encoder)
> > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > int n_entries;
> >  
> > -   if (encoder->type == INTEL_OUTPUT_EDP)
> > -   intel_ddi_get_buf_trans_edp(dev_priv, _entries);
> > -   else
> > -   intel_ddi_get_buf_trans_dp(dev_priv, _entries);
> > +   if (IS_CANNONLAKE(dev_priv)) {
> > +   if (encoder->type == INTEL_OUTPUT_EDP)
> > +   cnl_get_buf_trans_edp(dev_priv, _entries);
> > +   else
> > +   cnl_get_buf_trans_dp(dev_priv, _entries);
> > +   } else {
> > +   if (encoder->type == INTEL_OUTPUT_EDP)
> > +   intel_ddi_get_buf_trans_edp(dev_priv, _entries);
> > +   else
> > +   intel_ddi_get_buf_trans_dp(dev_priv, _entries);
> > +   }
> >  
> > if (WARN_ON(n_entries < 1))
> > n_entries = 1;
> > -- 
> > 2.13.2
> 

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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/cnp: Wa 1181: Fix Backlight issue (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/cnp: Wa 1181: Fix Backlight issue (rev2)
URL   : https://patchwork.freedesktop.org/series/29452/
State : success

== Summary ==

Test perf:
Subgroup blocking:
pass   -> FAIL   (shard-hsw) fdo#102252
Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-hsw) fdo#99912
Test kms_flip:
Subgroup plain-flip-fb-recreate:
fail   -> PASS   (shard-hsw)

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912

shard-hswtotal:2265 pass:1230 dwarn:0   dfail:0   fail:19  skip:1016 
time:9632s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5547/shards.html
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Re: [Intel-gfx] [PATCH] drm/i915/cnl: Avoid ioremap_wc on Cannonlake as well.

[Vivi, Rodrigo]

On Thu, 2017-08-31 at 11:27 +0300, Joonas Lahtinen wrote:
> On Wed, 2017-08-30 at 17:58 +, Vivi, Rodrigo wrote:
> > On Wed, 2017-08-30 at 14:38 +0300, Joonas Lahtinen wrote:
> > > On Wed, 2017-08-30 at 12:26 +0100, Chris Wilson wrote:
> > > > Quoting Joonas Lahtinen (2017-08-30 12:13:29)
> > > > > On Tue, 2017-08-29 at 16:09 -0700, Rodrigo Vivi wrote:
> > > > > > Driver’s CPU access to GTT is via the GTTMMADR BAR.
> > > > > > 
> > > > > > The current HW implementation of that BAR is to only
> > > > > > support <= DW (and maybe QW) writes—not 16/32/64B writes
> > > > > > that could occur with WC and/or SSE/AVX moves.
> > > > > > 
> > > > > > GTTMMADR must be marked uncacheable (UC).
> > > > > > Accesses to GTTMMADR(GTT), must be 64 bits or less (ie. 1 GTT 
> > > > > > entry).
> > > > > > 
> > > > > > v2: Get clarification on the reasons and spec is getting
> > > > > > updated to reflect it now.
> > > > > > 
> > > > > > Cc: Joonas Lahtinen 
> > > > > > Suggested-by: Ben Widawsky 
> > > > > > Signed-off-by: Rodrigo Vivi 
> > > > > 
> > > > > Rodrigo, can you double-check how this interacts with the patch from
> > > > > Zhi that adds the WB flag to PPAT_CACHE_INDEX on CNL.
> > > > 
> > > > Different issue (or should be). The ioremap concerns access through the
> > > > PCI BAR, affecting how fast we insert entries into the GGTT (so
> > > > establishing new mmaps following frequent runtime pm, loading of new
> > > > contexts + rings, as well as the stressful GGTT thrashing). PPAT affects
> > > > how the device accesses the physical pages, not the PTE themselves.
> > > 
> > > Yes, I know it should be :) But Rodrigo also described pretty random
> > > hangs, IIRC not much was pinpointing to either of the issues. With
> > > these two bugs present, device could be operating without write-back on
> > > certain pages, or could be operating on wrong pages altogether.
> > > 
> > > I'd just like one round of testing to try to avoid this change if we
> > > can.
> > 
> > I had tried already put PAT to non-cached, but I will double check Zhi's
> > work just in case.
> > 
> > I wish we could avoid this patch here, but it seems by definition this
> > BAR should be uncached. By BAR's non-Prefetchable attribute.
> > 
> > So probably the ioremap_wc should check that attribute and fail to
> > allocate that with wc so we would try wc and fallback to uncached.
> > 
> > But since we know this is uncached only for this case and this handle
> > don't exist yet the best is to move along with this patch.
> 
> Right, you can have the R-b.

thanks. merged to dinq.

> 
> Regards, Joonas

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[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: Fix the missing PPAT cache attributes on CNL

[Patchwork]

== Series Details ==

Series: drm/i915: Fix the missing PPAT cache attributes on CNL
URL   : https://patchwork.freedesktop.org/series/29618/
State : warning

== Summary ==

Series 29618v1 drm/i915: Fix the missing PPAT cache attributes on CNL
https://patchwork.freedesktop.org/api/1.0/series/29618/revisions/1/mbox/

Test chamelium:
Subgroup dp-hpd-fast:
skip   -> PASS   (fi-kbl-7500u)
Subgroup dp-edid-read:
skip   -> PASS   (fi-kbl-7500u)
Subgroup dp-crc-fast:
skip   -> PASS   (fi-kbl-7500u)
Subgroup common-hpd-after-suspend:
skip   -> DMESG-WARN (fi-kbl-7500u)
Test gem_exec_flush:
Subgroup basic-batch-kernel-default-uc:
pass   -> FAIL   (fi-snb-2600) fdo#17
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
pass   -> FAIL   (fi-snb-2600) fdo#100215
Subgroup basic-flip-after-cursor-varying-size:
pass   -> FAIL   (fi-hsw-4770) fdo#102402 +1

fdo#17 https://bugs.freedesktop.org/show_bug.cgi?id=17
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#102402 https://bugs.freedesktop.org/show_bug.cgi?id=102402

fi-bdw-5557u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:461s
fi-bdw-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:437s
fi-blb-e6850 total:288  pass:224  dwarn:1   dfail:0   fail:0   skip:63  
time:365s
fi-bsw-n3050 total:288  pass:243  dwarn:0   dfail:0   fail:0   skip:45  
time:562s
fi-bwr-2160  total:288  pass:184  dwarn:0   dfail:0   fail:0   skip:104 
time:253s
fi-bxt-j4205 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:525s
fi-byt-j1900 total:288  pass:254  dwarn:1   dfail:0   fail:0   skip:33  
time:524s
fi-byt-n2820 total:288  pass:250  dwarn:1   dfail:0   fail:0   skip:37  
time:521s
fi-elk-e7500 total:288  pass:230  dwarn:0   dfail:0   fail:0   skip:58  
time:440s
fi-glk-2atotal:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:616s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:2   skip:25  
time:466s
fi-hsw-4770r total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  
time:428s
fi-ilk-650   total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:424s
fi-ivb-3520m total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:509s
fi-ivb-3770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:485s
fi-kbl-7500u total:288  pass:264  dwarn:1   dfail:0   fail:0   skip:23  
time:520s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:597s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:594s
fi-pnv-d510  total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:529s
fi-skl-6260u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:470s
fi-skl-6700k total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:532s
fi-skl-6770hqtotal:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:497s
fi-skl-gvtdvmtotal:288  pass:266  dwarn:0   dfail:0   fail:0   skip:22  
time:457s
fi-skl-x1585ltotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:494s
fi-snb-2520m total:288  pass:251  dwarn:0   dfail:0   fail:0   skip:37  
time:552s
fi-snb-2600  total:288  pass:247  dwarn:0   dfail:0   fail:3   skip:38  
time:408s

c399d43adc55a49d028d24ce7cdacc1823a4f159 drm-tip: 2017y-08m-31d-07h-25m-28s UTC 
integration manifest
111b230fc9fe drm/i915: Fix the missing PPAT cache attributes on CNL

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5550/
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[Intel-gfx] [PATCH] drm/i915: Fix the missing PPAT cache attributes on CNL

[Zhi Wang]

Add back the GEN8_PPAT_WB cache attributes in cnl_setup_private_ppat(),
which are missed on CNL.

Signed-off-by: Zhi Wang 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 708b95c..f18b1ec 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2828,10 +2828,10 @@ static void cnl_setup_private_ppat(struct 
drm_i915_private *dev_priv)
I915_WRITE(GEN10_PAT_INDEX(1), GEN8_PPAT_WC | GEN8_PPAT_LLCELLC);
I915_WRITE(GEN10_PAT_INDEX(2), GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);
I915_WRITE(GEN10_PAT_INDEX(3), GEN8_PPAT_UC);
-   I915_WRITE(GEN10_PAT_INDEX(4), GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0));
-   I915_WRITE(GEN10_PAT_INDEX(5), GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1));
-   I915_WRITE(GEN10_PAT_INDEX(6), GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2));
-   I915_WRITE(GEN10_PAT_INDEX(7), GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
+   I915_WRITE(GEN10_PAT_INDEX(4), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | 
GEN8_PPAT_AGE(0));
+   I915_WRITE(GEN10_PAT_INDEX(5), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | 
GEN8_PPAT_AGE(1));
+   I915_WRITE(GEN10_PAT_INDEX(6), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | 
GEN8_PPAT_AGE(2));
+   I915_WRITE(GEN10_PAT_INDEX(7), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | 
GEN8_PPAT_AGE(3));
 }
 
 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
-- 
2.7.4

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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Disable DRRS when PSR is enabled

[Patchwork]

== Series Details ==

Series: drm/i915: Disable DRRS when PSR is enabled
URL   : https://patchwork.freedesktop.org/series/29577/
State : success

== Summary ==

Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-hsw) fdo#99912
Test perf:
Subgroup blocking:
pass   -> FAIL   (shard-hsw) fdo#102252

fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hswtotal:2175 pass:1185 dwarn:0   dfail:0   fail:19  skip:971 
time:9455s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5546/shards.html
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Re: [Intel-gfx] [PATCH 00/13] mmu_notifier kill invalidate_page callback

[Christian König]

Am 31.08.2017 um 15:59 schrieb Jerome Glisse:

[Adding Intel folks as they might be interested in this discussion]

On Wed, Aug 30, 2017 at 05:51:52PM -0400, Felix Kuehling wrote:

Hi Jérôme,

I have some questions about the potential range-start-end race you
mentioned.

On 2017-08-29 07:54 PM, Jérôme Glisse wrote:

Note that a lot of existing user feels broken in respect to range_start/
range_end. Many user only have range_start() callback but there is nothing
preventing them to undo what was invalidated in their range_start() callback
after it returns but before any CPU page table update take place.

The code pattern use in kvm or umem odp is an example on how to properly
avoid such race. In a nutshell use some kind of sequence number and active
range invalidation counter to block anything that might undo what the
range_start() callback did.

What happens when we start monitoring an address range after
invaligate_range_start was called? Sounds like we have to keep track of
all active invalidations for just such a case, even in address ranges
that we don't currently care about.

What are the things we cannot do between invalidate_range_start and
invalidate_range_end? amdgpu calls get_user_pages to re-validate our
userptr mappings after the invalidate_range_start notifier invalidated
it. Do we have to wait for invalidate_range_end before we can call
get_user_pages safely?

Well the whole userptr bo object is somewhat broken from the start.
You never defined the semantic of it ie what is expected. I can
think of 2 differents semantics:
   A) a uptr buffer object is a snapshot of a memory at the time of
  uptr buffer object creation
   B) a uptr buffer object allow GPU to access a range of virtual
  address of a process an share coherent view of that range
  between CPU and GPU

As it was implemented it is more inline with B but it is not defined
anywhere AFAICT.


Well it is not documented, but the userspace APIs build on top of that 
require semantics B.


Essentially you could have cases where the GPU or the CPU is waiting in 
a busy loop for the other one to change some memory address.



Anyway getting back to your questions, it kind of doesn't matter as
you are using GUP ie you are pinning pages except for one scenario
(at least i can only think of one).

Problematic case is race between CPU write to zero page or COW and
GPU driver doing read only GUP:

 CPU thread 1   | CPU thread 2
 -
|
| uptr covering addr A read only
|  do stuff with A
 write fault to addr A  |
 invalidate_range_start([A, A+1])   | unbind_ttm -> unpin
| validate bo -> GUP -> zero page
 lock page table|
 replace zero pfn/COW with new page |
 unlock page table  |
 invalidate_range_end([A, A+1]) |

So here the GPU would be using wrong page for the address. How bad
is it is undefined as the semantic of uptr is undefine. Given how it
as been use so far this race is unlikely (i don't think we have many
userspace that use that feature and do fork).


So i would first define the semantic of uptr bo and then i would fix
accordingly the code. Semantic A is easier to implement and you could
just drop the whole mmu_notifier. Maybe it is better to create uptr
buffer object everytime you want to snapshot a range of address. I
don't think the overhead of buffer creation would matter.


We do support creating userptr without mmu_notifier for exactly that 
purpose, e.g. uploads of snapshots what user space address space looked 
like in a certain moment.


Unfortunately we found that the overhead of buffer creation (and the 
related gup) is way to high to be useful as a throw away object. Just 
memcpy into a BO has just less latency over all.


And yeah, at least I'm perfectly aware of the problems with fork() and 
COW. BTW: It becomes really really ugly if you think about what happens 
when the parent writes to a page first and the GPU then has the child copy.


Regards,
Christian.


If you want to close the race for COW and zero page in case of read
only GUP there is no other way than what KVM or ODP is doing. I had
patchset to simplify all this but i need to bring it back to life.


Note that other thing might race but as you pin the pages they do
not matter. It just mean that if you GUP after range_start() but
before range_end() and before CPU page table update then you pinned
the same old page again and nothing will happen (migrate will fail,
MADV_FREE will nop, ...). So you just did the range_start() callback
for nothing in those cases.

(Sorry for taking so long to answer i forgot your mail yesterday with
  all the other discussion going on).

Cheers,
Jérôme

Re: [Intel-gfx] [RFCv6 2/2] drm/i915: Introduce private PAT management

[Wang, Zhi A]

I see. Thanks for the explanation! :)

-Original Message-
From: Joonas Lahtinen [mailto:joonas.lahti...@linux.intel.com] 
Sent: Thursday, August 31, 2017 5:20 PM
To: Wang, Zhi A ; Vivi, Rodrigo 
Cc: intel-gfx@lists.freedesktop.org; zhen...@linux.intel.com; 
intel-gvt-...@lists.freedesktop.org; ch...@chris-wilson.co.uk; Widawsky, 
Benjamin 
Subject: Re: [RFCv6 2/2] drm/i915: Introduce private PAT management

On Thu, 2017-08-31 at 08:28 +, Wang, Zhi A wrote:
> Do you mean I still keep I915_WRITE(x) in _setup_private_pat() like 
> before? Then changed them in a new patch? 

No, I mean use the new code structure, but make sure all register writes are 
equal to what they were before (and please send a separate patch for the CNL 
caching issue before that).

Regards, Joonas
--
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Re: [Intel-gfx] [RFC PATCH 1/5] drm/i915: Always wait for flip_done

[Maarten Lankhorst]

Op 30-08-17 om 15:40 schreef Daniel Vetter:
> On Wed, Aug 30, 2017 at 02:54:28PM +0200, Maarten Lankhorst wrote:
>> Op 30-08-17 om 14:43 schreef Daniel Vetter:
>>> On Wed, Aug 30, 2017 at 02:17:48PM +0200, Maarten Lankhorst wrote:
 The next commit removes the wait for flip_done in in
 drm_atomic_helper_commit_cleanup_done, but we need it for the tests
 to pass. Instead of using complicated vblank tracking which ends
 up being ignored anyway, call the correct atomic helper. :)

 RFC because I'm not completely sure what we want to do with the vblank 
 waiting,
 I think for now this patch is the right way to go until we decide because 
 it
 preserves the status quo when drm_crtc_commit was introduced.

 Signed-off-by: Maarten Lankhorst 
 ---
  drivers/gpu/drm/i915/i915_drv.h  |  3 +-
  drivers/gpu/drm/i915/intel_display.c | 83 
 +++-
  2 files changed, 8 insertions(+), 78 deletions(-)

 diff --git a/drivers/gpu/drm/i915/i915_drv.h 
 b/drivers/gpu/drm/i915/i915_drv.h
 index cbbafbfb0a55..de19621864a9 100644
 --- a/drivers/gpu/drm/i915/i915_drv.h
 +++ b/drivers/gpu/drm/i915/i915_drv.h
 @@ -707,8 +707,7 @@ struct drm_i915_display_funcs {
struct drm_atomic_state *old_state);
void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
 struct drm_atomic_state *old_state);
 -  void (*update_crtcs)(struct drm_atomic_state *state,
 -   unsigned int *crtc_vblank_mask);
 +  void (*update_crtcs)(struct drm_atomic_state *state);
void (*audio_codec_enable)(struct drm_connector *connector,
   struct intel_encoder *encoder,
   const struct drm_display_mode 
 *adjusted_mode);
 diff --git a/drivers/gpu/drm/i915/intel_display.c 
 b/drivers/gpu/drm/i915/intel_display.c
 index 52c73b4dabaa..3f3cb96aa11e 100644
 --- a/drivers/gpu/drm/i915/intel_display.c
 +++ b/drivers/gpu/drm/i915/intel_display.c
 @@ -12114,73 +12114,10 @@ u32 intel_crtc_get_vblank_counter(struct 
 intel_crtc *crtc)
return dev->driver->get_vblank_counter(dev, crtc->pipe);
  }
  
 -static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
 -struct drm_i915_private *dev_priv,
 -unsigned crtc_mask)
 -{
 -  unsigned last_vblank_count[I915_MAX_PIPES];
 -  enum pipe pipe;
 -  int ret;
 -
 -  if (!crtc_mask)
 -  return;
 -
 -  for_each_pipe(dev_priv, pipe) {
 -  struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
 -pipe);
 -
 -  if (!((1 << pipe) & crtc_mask))
 -  continue;
 -
 -  ret = drm_crtc_vblank_get(>base);
 -  if (WARN_ON(ret != 0)) {
 -  crtc_mask &= ~(1 << pipe);
 -  continue;
 -  }
 -
 -  last_vblank_count[pipe] = drm_crtc_vblank_count(>base);
 -  }
 -
 -  for_each_pipe(dev_priv, pipe) {
 -  struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
 -pipe);
 -  long lret;
 -
 -  if (!((1 << pipe) & crtc_mask))
 -  continue;
 -
 -  lret = wait_event_timeout(dev->vblank[pipe].queue,
 -  last_vblank_count[pipe] !=
 -  drm_crtc_vblank_count(>base),
 -  msecs_to_jiffies(50));
 -
 -  WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
 -
 -  drm_crtc_vblank_put(>base);
 -  }
 -}
 -
 -static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
 -{
 -  /* fb updated, need to unpin old fb */
 -  if (crtc_state->fb_changed)
 -  return true;
 -
 -  /* wm changes, need vblank before final wm's */
 -  if (crtc_state->update_wm_post)
 -  return true;
 -
 -  if (crtc_state->wm.need_postvbl_update)
 -  return true;
 -
 -  return false;
 -}
 -
  static void intel_update_crtc(struct drm_crtc *crtc,
  struct drm_atomic_state *state,
  struct drm_crtc_state *old_crtc_state,
 -struct drm_crtc_state *new_crtc_state,
 -unsigned int *crtc_vblank_mask)
 +struct drm_crtc_state *new_crtc_state)
  {
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
 @@ -12203,13 +12140,9 

Re: [Intel-gfx] [PATCH] drm/i915/cnl: Fix DP max voltage

[Ville Syrjälä]

On Thu, Aug 31, 2017 at 07:53:56AM -0700, Rodrigo Vivi wrote:
> From: "Vivi, Rodrigo" 
> 
> On clock recovery this function is called to find out
> the max voltage swing level that we could go.
> 
> However gen 9 functions use the old buffer translation tables
> to figure that out. That table is not valid for CNL
> causing an invalid number of entries and an invalid selection
> on the max voltage swing level.
> 
> v2: Let's use same approach that previous platforms.
> v3: Actually use n_entries and avoid duplicated -1.
> v4: Avoid cnl_max_level and use current style.
> 
> Cc: Ville Syrjälä 
> Cc: Clint Taylor 
> Signed-off-by: Rodrigo Vivi 

Reviewed-by: Ville Syrjälä 

> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 15 +++
>  1 file changed, 11 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index f1757a8e481a..1da3bb2cc4b4 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1879,10 +1879,17 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder 
> *encoder)
>   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>   int n_entries;
>  
> - if (encoder->type == INTEL_OUTPUT_EDP)
> - intel_ddi_get_buf_trans_edp(dev_priv, _entries);
> - else
> - intel_ddi_get_buf_trans_dp(dev_priv, _entries);
> + if (IS_CANNONLAKE(dev_priv)) {
> + if (encoder->type == INTEL_OUTPUT_EDP)
> + cnl_get_buf_trans_edp(dev_priv, _entries);
> + else
> + cnl_get_buf_trans_dp(dev_priv, _entries);
> + } else {
> + if (encoder->type == INTEL_OUTPUT_EDP)
> + intel_ddi_get_buf_trans_edp(dev_priv, _entries);
> + else
> + intel_ddi_get_buf_trans_dp(dev_priv, _entries);
> + }
>  
>   if (WARN_ON(n_entries < 1))
>   n_entries = 1;
> -- 
> 2.13.2

-- 
Ville Syrjälä
Intel OTC
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v4,1/2] drm/i915: Track minimum acceptable cdclk instead of "minimum dotclock" (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [v4,1/2] drm/i915: Track minimum acceptable cdclk 
instead of "minimum dotclock" (rev2)
URL   : https://patchwork.freedesktop.org/series/27078/
State : success

== Summary ==

Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-hsw) fdo#99912
Test kms_flip:
Subgroup plain-flip-fb-recreate:
fail   -> PASS   (shard-hsw)

fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912

shard-hswtotal:2265 pass:1231 dwarn:0   dfail:0   fail:18  skip:1016 
time:9699s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5544/shards.html
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[Intel-gfx] [PATCH] drm/i915/cnl: Fix DP max voltage

[Rodrigo Vivi]

From: "Vivi, Rodrigo" 

On clock recovery this function is called to find out
the max voltage swing level that we could go.

However gen 9 functions use the old buffer translation tables
to figure that out. That table is not valid for CNL
causing an invalid number of entries and an invalid selection
on the max voltage swing level.

v2: Let's use same approach that previous platforms.
v3: Actually use n_entries and avoid duplicated -1.
v4: Avoid cnl_max_level and use current style.

Cc: Ville Syrjälä 
Cc: Clint Taylor 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_ddi.c | 15 +++
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index f1757a8e481a..1da3bb2cc4b4 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1879,10 +1879,17 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder 
*encoder)
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
int n_entries;
 
-   if (encoder->type == INTEL_OUTPUT_EDP)
-   intel_ddi_get_buf_trans_edp(dev_priv, _entries);
-   else
-   intel_ddi_get_buf_trans_dp(dev_priv, _entries);
+   if (IS_CANNONLAKE(dev_priv)) {
+   if (encoder->type == INTEL_OUTPUT_EDP)
+   cnl_get_buf_trans_edp(dev_priv, _entries);
+   else
+   cnl_get_buf_trans_dp(dev_priv, _entries);
+   } else {
+   if (encoder->type == INTEL_OUTPUT_EDP)
+   intel_ddi_get_buf_trans_edp(dev_priv, _entries);
+   else
+   intel_ddi_get_buf_trans_dp(dev_priv, _entries);
+   }
 
if (WARN_ON(n_entries < 1))
n_entries = 1;
-- 
2.13.2

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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Keep the device awake whilst in the GTT write domain (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Keep the device awake whilst in the GTT write domain (rev3)
URL   : https://patchwork.freedesktop.org/series/29594/
State : failure

== Summary ==

Series 29594v3 drm/i915: Keep the device awake whilst in the GTT write domain
https://patchwork.freedesktop.org/api/1.0/series/29594/revisions/3/mbox/

Test chamelium:
Subgroup dp-hpd-fast:
skip   -> PASS   (fi-kbl-7500u)
Subgroup dp-edid-read:
skip   -> PASS   (fi-kbl-7500u)
Subgroup dp-crc-fast:
skip   -> PASS   (fi-kbl-7500u)
Subgroup hdmi-crc-fast:
skip   -> INCOMPLETE (fi-snb-2520m)
Subgroup vga-hpd-fast:
skip   -> INCOMPLETE (fi-byt-j1900)
Subgroup vga-edid-read:
skip   -> INCOMPLETE (fi-byt-n2820)
Subgroup common-hpd-after-suspend:
pass   -> DMESG-WARN (fi-skl-6700k)
skip   -> DMESG-WARN (fi-kbl-7500u)
Test core_auth:
Subgroup basic-auth:
pass   -> INCOMPLETE (fi-ivb-3770)
Test debugfs_test:
Subgroup read_all_entries:
pass   -> INCOMPLETE (fi-ivb-3520m)
pass   -> INCOMPLETE (fi-hsw-4770r)
Test drv_getparams_basic:
Subgroup basic-subslice-total:
pass   -> INCOMPLETE (fi-hsw-4770)
Test gem_basic:
Subgroup bad-close:
pass   -> INCOMPLETE (fi-snb-2600)
Test gem_busy:
Subgroup basic-hang-default:
pass   -> INCOMPLETE (fi-blb-e6850)
pass   -> INCOMPLETE (fi-pnv-d510)
pass   -> INCOMPLETE (fi-elk-e7500)
pass   -> INCOMPLETE (fi-ilk-650)
pass   -> INCOMPLETE (fi-bdw-5557u)
pass   -> INCOMPLETE (fi-bdw-gvtdvm)
pass   -> INCOMPLETE (fi-bsw-n3050)
pass   -> INCOMPLETE (fi-skl-6260u)
pass   -> DMESG-WARN (fi-skl-6700k)
pass   -> INCOMPLETE (fi-skl-6770hq)
pass   -> INCOMPLETE (fi-skl-gvtdvm)
pass   -> INCOMPLETE (fi-skl-x1585l)
pass   -> INCOMPLETE (fi-bxt-j4205)
pass   -> DMESG-WARN (fi-kbl-7500u)
pass   -> INCOMPLETE (fi-kbl-7560u)
pass   -> INCOMPLETE (fi-kbl-r)
pass   -> INCOMPLETE (fi-glk-2a)
Test gem_close_race:
Subgroup basic-process:
pass   -> DMESG-WARN (fi-skl-6700k)
pass   -> DMESG-WARN (fi-kbl-7500u)
Subgroup basic-threads:
pass   -> DMESG-WARN (fi-skl-6700k)
pass   -> DMESG-WARN (fi-kbl-7500u)
Test gem_cpu_reloc:
Subgroup basic:
pass   -> DMESG-WARN (fi-skl-6700k)
pass   -> DMESG-WARN (fi-kbl-7500u)
Test gem_cs_tlb:
Subgroup basic-default:
pass   -> INCOMPLETE (fi-bwr-2160)
pass   -> DMESG-WARN (fi-skl-6700k)
pass   -> DMESG-WARN (fi-kbl-7500u)
Test gem_ctx_basic:
pass   -> DMESG-WARN (fi-skl-6700k)
pass   -> DMESG-WARN (fi-kbl-7500u)
Test gem_ctx_create:
Subgroup basic:
pass   -> DMESG-WARN (fi-skl-6700k)
pass   -> DMESG-WARN (fi-kbl-7500u)
Subgroup basic-files:
pass   -> INCOMPLETE (fi-skl-6700k)
pass   -> DMESG-WARN (fi-kbl-7500u)
Test gem_ctx_exec:
Subgroup basic:
pass   -> DMESG-WARN (fi-kbl-7500u)
Test gem_ctx_param:
Subgroup basic:
pass   -> DMESG-WARN (fi-kbl-7500u)
Subgroup basic-default:
pass   -> DMESG-WARN (fi-kbl-7500u)
Test gem_ctx_switch:
Subgroup basic-default:
pass   -> DMESG-WARN (fi-kbl-7500u)
Subgroup basic-default-heavy:
pass   -> DMESG-WARN (fi-kbl-7500u)
Test gem_exec_basic:
Subgroup basic-blt:
pass   -> DMESG-WARN (fi-kbl-7500u)
Subgroup basic-bsd:
pass   -> DMESG-WARN (fi-kbl-7500u)
Subgroup basic-default:
pass   -> DMESG-WARN (fi-kbl-7500u)
Subgroup basic-render:
pass   -> DMESG-WARN (fi-kbl-7500u)
Subgroup basic-vebox:
WARNING: Long output truncated

c399d43adc55a49d028d24ce7cdacc1823a4f159 drm-tip: 2017y-08m-31d-07h-25m-28s UTC 
integration manifest
03541656a674 drm/i915: Keep the device awake whilst in the GTT domain

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5549/
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Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for pm_rps: Changes in waitboost scenario (rev10)

[Arkadiusz Hiler]

On Thu, Aug 31, 2017 at 01:03:24PM +, Patchwork wrote:
> == Series Details ==
> 
> Series: pm_rps: Changes in waitboost scenario (rev10)
> URL   : https://patchwork.freedesktop.org/series/28966/
> State : failure
> 
> == Summary ==
> 
> IGT patchset tested on top of latest successful build
> c2159678d283fea5615ec8e846a51cf4954ac82d tests/perf: add Geminilake support
> 
> with latest DRM-Tip kernel build CI_DRM_3021
> c399d43adc55 drm-tip: 2017y-08m-31d-07h-25m-28s UTC integration manifest
> 
> Test kms_busy:
> Subgroup basic-flip-a:
> pass   -> FAIL   (fi-bwr-2160)

That's not caused by the series (PW's rev10 == PATCH v8).

v7 and v8 do not change anything in the code, only comments and commit
messages are amended.

Filtering the CI noise from all the runs the patch had - it healthy and
it also gets rid of a flipflop we had.

Merged with minor commit message reformatting.

Thanks for the patch and reviews!

-- 
Cheers,
Arek

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Re: [Intel-gfx] [RFCv6 2/2] drm/i915: Introduce private PAT management

[Joonas Lahtinen]

On Thu, 2017-08-31 at 08:28 +, Wang, Zhi A wrote:
> Do you mean I still keep I915_WRITE(x) in _setup_private_pat() like 
> before? Then changed them in a new patch? 

No, I mean use the new code structure, but make sure all register
writes are equal to what they were before (and please send a separate
patch for the CNL caching issue before that).

Regards, Joonas
-- 
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Open Source Technology Center
Intel Corporation
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[Intel-gfx] [PATCH v3] drm/i915: Keep the device awake whilst in the GTT domain

[Chris Wilson]

Since runtime suspend is very harsh on GTT mmappings (they all get
zapped on suspend) keep the device awake while the buffer remains in
the GTT domain. However, userspace can control the domain and
although there is a soft contract that writes must be flushed (for e.g.
flushing scanouts and fbc), we are intentionally lax with respect to read
domains, allowing them to persist for as long as is feasible. To ensure
that the device can eventually suspend, we install a timer. So in effect
we have just a fancy pm autosuspend that tries to estimate the cost of
restoring actively used GTT mmappings.
---
 drivers/gpu/drm/i915/i915_debugfs.c  |  2 +
 drivers/gpu/drm/i915/i915_drv.h  |  8 +++
 drivers/gpu/drm/i915/i915_gem.c  | 88 
 drivers/gpu/drm/i915/i915_gem_object.h   |  5 ++
 drivers/gpu/drm/i915/i915_gem_shrinker.c |  4 +-
 drivers/gpu/drm/i915/intel_lrc.c |  1 +
 drivers/gpu/drm/i915/intel_ringbuffer.c  |  3 ++
 7 files changed, 100 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 48572b157222..1432392fb2f8 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2812,6 +2812,8 @@ static int i915_runtime_pm_status(struct seq_file *m, 
void *unused)
seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
seq_printf(m, "IRQs disabled: %s\n",
   yesno(!intel_irqs_enabled(dev_priv)));
+   seq_printf(m, "GTT wakeref count: %d\n",
+  atomic_read(_priv->mm.wakeref_count));
 #ifdef CONFIG_PM
seq_printf(m, "Usage count: %d\n",
   atomic_read(_priv->drm.dev->power.usage_count));
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0383e879a315..799ab57cf040 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1460,6 +1460,14 @@ struct i915_gem_mm {
 */
struct list_head userfault_list;
 
+   /** List of all objects in gtt domain, holding a wakeref.
+* The list is reaped periodically.
+*/
+   struct list_head wakeref_list;
+   struct timer_list wakeref_timer;
+   spinlock_t wakeref_lock;
+   atomic_t wakeref_count;
+
/**
 * List of objects which are pending destruction.
 */
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e4cc08bc518c..659fda483f7e 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -235,6 +235,7 @@ i915_gem_object_get_pages_phys(struct drm_i915_gem_object 
*obj)
 
 static void __start_cpu_write(struct drm_i915_gem_object *obj)
 {
+   GEM_BUG_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
obj->base.read_domains = I915_GEM_DOMAIN_CPU;
obj->base.write_domain = I915_GEM_DOMAIN_CPU;
if (cpu_write_needs_clflush(obj))
@@ -667,11 +668,13 @@ fb_write_origin(struct drm_i915_gem_object *obj, unsigned 
int domain)
obj->frontbuffer_ggtt_origin : ORIGIN_CPU);
 }
 
-static void
+void
 flush_write_domain(struct drm_i915_gem_object *obj, unsigned int flush_domains)
 {
struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 
+   lockdep_assert_held(_priv->drm.struct_mutex);
+
if (!(obj->base.write_domain & flush_domains))
return;
 
@@ -694,16 +697,20 @@ flush_write_domain(struct drm_i915_gem_object *obj, 
unsigned int flush_domains)
 
switch (obj->base.write_domain) {
case I915_GEM_DOMAIN_GTT:
-   if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv)) {
-   intel_runtime_pm_get(dev_priv);
-   spin_lock_irq(_priv->uncore.lock);
-   
POSTING_READ_FW(RING_ACTHD(dev_priv->engine[RCS]->mmio_base));
-   spin_unlock_irq(_priv->uncore.lock);
-   intel_runtime_pm_put(dev_priv);
-   }
+   spin_lock_bh(_priv->mm.wakeref_lock);
+   if (!list_empty(>mm.wakeref_link)) {
+   if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv)) {
+   spin_lock_irq(_priv->uncore.lock);
+   
POSTING_READ_FW(RING_ACTHD(dev_priv->engine[RCS]->mmio_base));
+   spin_unlock_irq(_priv->uncore.lock);
+   }
+
+   intel_fb_obj_flush(obj,
+   fb_write_origin(obj, 
I915_GEM_DOMAIN_GTT));
 
-   intel_fb_obj_flush(obj,
-  fb_write_origin(obj, I915_GEM_DOMAIN_GTT));
+   list_del_init(>mm.wakeref_link);
+   }
+   spin_unlock_bh(_priv->mm.wakeref_lock);
break;
 
case I915_GEM_DOMAIN_CPU:
@@ -3425,6 +3432,7 @@ static void __i915_gem_object_flush_for_display(struct 

[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915: implement NOA mux reprogramming at ctx-switch

[Patchwork]

== Series Details ==

Series: drm/i915: implement NOA mux reprogramming at ctx-switch
URL   : https://patchwork.freedesktop.org/series/29564/
State : warning

== Summary ==

Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-hsw) fdo#99912
Test kms_atomic_transition:
Subgroup plane-all-modeset-transition:
pass   -> DMESG-WARN (shard-hsw)
Test perf:
Subgroup blocking:
pass   -> FAIL   (shard-hsw) fdo#102252
Test kms_flip:
Subgroup plain-flip-fb-recreate:
fail   -> PASS   (shard-hsw)

fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hswtotal:2265 pass:1229 dwarn:1   dfail:0   fail:19  skip:1016 
time:9658s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5543/shards.html
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Re: [Intel-gfx] [PATCH 00/13] mmu_notifier kill invalidate_page callback

[Jerome Glisse]

[Adding Intel folks as they might be interested in this discussion]

On Wed, Aug 30, 2017 at 05:51:52PM -0400, Felix Kuehling wrote:
> Hi Jérôme,
> 
> I have some questions about the potential range-start-end race you
> mentioned.
> 
> On 2017-08-29 07:54 PM, Jérôme Glisse wrote:
> > Note that a lot of existing user feels broken in respect to range_start/
> > range_end. Many user only have range_start() callback but there is nothing
> > preventing them to undo what was invalidated in their range_start() callback
> > after it returns but before any CPU page table update take place.
> >
> > The code pattern use in kvm or umem odp is an example on how to properly
> > avoid such race. In a nutshell use some kind of sequence number and active
> > range invalidation counter to block anything that might undo what the
> > range_start() callback did.
> What happens when we start monitoring an address range after
> invaligate_range_start was called? Sounds like we have to keep track of
> all active invalidations for just such a case, even in address ranges
> that we don't currently care about.
> 
> What are the things we cannot do between invalidate_range_start and
> invalidate_range_end? amdgpu calls get_user_pages to re-validate our
> userptr mappings after the invalidate_range_start notifier invalidated
> it. Do we have to wait for invalidate_range_end before we can call
> get_user_pages safely?

Well the whole userptr bo object is somewhat broken from the start.
You never defined the semantic of it ie what is expected. I can
think of 2 differents semantics:
  A) a uptr buffer object is a snapshot of a memory at the time of
 uptr buffer object creation
  B) a uptr buffer object allow GPU to access a range of virtual
 address of a process an share coherent view of that range
 between CPU and GPU

As it was implemented it is more inline with B but it is not defined
anywhere AFAICT.

Anyway getting back to your questions, it kind of doesn't matter as
you are using GUP ie you are pinning pages except for one scenario
(at least i can only think of one).

Problematic case is race between CPU write to zero page or COW and
GPU driver doing read only GUP:

CPU thread 1   | CPU thread 2
-
   |
   | uptr covering addr A read only
   |  do stuff with A
write fault to addr A  |
invalidate_range_start([A, A+1])   | unbind_ttm -> unpin
   | validate bo -> GUP -> zero page
lock page table|
replace zero pfn/COW with new page |
unlock page table  |
invalidate_range_end([A, A+1]) |

So here the GPU would be using wrong page for the address. How bad
is it is undefined as the semantic of uptr is undefine. Given how it
as been use so far this race is unlikely (i don't think we have many
userspace that use that feature and do fork).


So i would first define the semantic of uptr bo and then i would fix
accordingly the code. Semantic A is easier to implement and you could
just drop the whole mmu_notifier. Maybe it is better to create uptr
buffer object everytime you want to snapshot a range of address. I
don't think the overhead of buffer creation would matter.


If you want to close the race for COW and zero page in case of read
only GUP there is no other way than what KVM or ODP is doing. I had
patchset to simplify all this but i need to bring it back to life.


Note that other thing might race but as you pin the pages they do
not matter. It just mean that if you GUP after range_start() but
before range_end() and before CPU page table update then you pinned
the same old page again and nothing will happen (migrate will fail,
MADV_FREE will nop, ...). So you just did the range_start() callback
for nothing in those cases.

(Sorry for taking so long to answer i forgot your mail yesterday with
 all the other discussion going on).

Cheers,
Jérôme
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[Intel-gfx] ✗ Fi.CI.BAT: failure for chamelium: Add work in progress test for HDMI audio

[Patchwork]

== Series Details ==

Series: chamelium: Add work in progress test for HDMI audio
URL   : https://patchwork.freedesktop.org/series/29609/
State : failure

== Summary ==

IGT patchset build failed on latest successful build
c2159678d283fea5615ec8e846a51cf4954ac82d tests/perf: add Geminilake support

/bin/bash ./config.status --recheck
running CONFIG_SHELL=/bin/bash /bin/bash ./configure --prefix=/opt/igt 
--disable-amdgpu --disable-nouveau --disable-vc4 --enable-chamelium 
CPPFLAGS=-I/home/cidrm/kernel_headers/include 
PKG_CONFIG_PATH=/opt/igt/lib/pkgconfig:/usr/local/lib64/pkgconfig 
XMLRPC_CFLAGS=-I/usr/include  XMLRPC_LIBS=-L/usr/lib/x86_64-linux-gnu   
-lxmlrpc_client -lxmlrpc  -lxmlrpc_xmlparse -lxmlrpc_xmltok -lxmlrpc_util 
-lcurl  --no-create --no-recursion
checking for gcc... gcc
checking whether the C compiler works... yes
checking for C compiler default output file name... a.out
checking for suffix of executables... 
checking whether we are cross compiling... no
checking for suffix of object files... o
checking whether we are using the GNU C compiler... yes
checking whether gcc accepts -g... yes
checking for gcc option to accept ISO C89... none needed
checking whether gcc understands -c and -o together... yes
checking how to run the C preprocessor... gcc -E
checking for grep that handles long lines and -e... /bin/grep
checking for egrep... /bin/grep -E
checking for ANSI C header files... yes
checking for sys/types.h... yes
checking for sys/stat.h... yes
checking for stdlib.h... yes
checking for string.h... yes
checking for memory.h... yes
checking for strings.h... yes
checking for inttypes.h... yes
checking for stdint.h... yes
checking for unistd.h... yes
checking minix/config.h usability... no
checking minix/config.h presence... no
checking for minix/config.h... no
checking whether it is safe to define __EXTENSIONS__... yes
checking for special C compiler options needed for large files... no
checking for _FILE_OFFSET_BITS value needed for large files... no
checking build system type... x86_64-pc-linux-gnu
checking host system type... x86_64-pc-linux-gnu
checking target system type... x86_64-pc-linux-gnu
checking for a BSD-compatible install... /usr/bin/install -c
checking whether build environment is sane... yes
checking for a thread-safe mkdir -p... /bin/mkdir -p
checking for gawk... gawk
checking whether make sets $(MAKE)... yes
checking for style of include used by make... GNU
checking whether make supports nested variables... yes
checking dependency style of gcc... gcc3
checking for a Python interpreter with version >= 3... python3
checking for python3... /usr/bin/python3
checking for python3 version... 3.5
checking for python3 platform... linux
checking for python3 script directory... ${prefix}/lib/python3.5/site-packages
checking for python3 extension module directory... 
${exec_prefix}/lib/python3.5/site-packages
checking for gcc... (cached) gcc
checking whether we are using the GNU C compiler... (cached) yes
checking whether gcc accepts -g... (cached) yes
checking for gcc option to accept ISO C89... (cached) none needed
checking whether gcc understands -c and -o together... (cached) yes
checking for flex... flex
checking lex output file root... lex.yy
checking lex library... -lfl
checking whether yytext is a pointer... yes
checking for bison... bison -y
checking for pkg-config... /usr/bin/pkg-config
checking pkg-config is at least version 0.9.0... yes
checking for gtk-doc... yes
checking for gtkdoc-check... gtkdoc-check.test
checking for gtkdoc-check... /usr/bin/gtkdoc-check
checking for gtkdoc-rebase... /usr/bin/gtkdoc-rebase
checking for gtkdoc-mkpdf... /usr/bin/gtkdoc-mkpdf
checking whether to build gtk-doc documentation... no
checking for GTKDOC_DEPS... yes
checking for rst2man... yes
checking for ANSI C header files... (cached) yes
checking termios.h usability... yes
checking termios.h presence... yes
checking for termios.h... yes
checking linux/kd.h usability... yes
checking linux/kd.h presence... yes
checking for linux/kd.h... yes
checking sys/kd.h usability... yes
checking sys/kd.h presence... yes
checking for sys/kd.h... yes
checking libgen.h usability... yes
checking libgen.h presence... yes
checking for libgen.h... yes
checking sys/io.h usability... yes
checking sys/io.h presence... yes
checking for sys/io.h... yes
checking for struct sysinfo.totalram... yes
checking for sighandler_t... yes
checking for swapctl... no
checking for asprintf... yes
checking for __attribute__((constructor))... yes
checking for timer_create... no
checking for timer_create in -lrt... yes
checking how to print strings... printf
checking for a sed that does not truncate output... /bin/sed
checking for fgrep... /bin/grep -F
checking for ld used by gcc... /usr/bin/ld
checking if the linker (/usr/bin/ld) is GNU ld... yes
checking for BSD- or MS-compatible name lister (nm)... /usr/bin/nm -B
checking the name lister (/usr/bin/nm -B) interface... BSD nm
checking whether ln -s works... yes
checking the 

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] lib: rename to libigt

[Patchwork]

== Series Details ==

Series: series starting with [1/2] lib: rename to libigt
URL   : https://patchwork.freedesktop.org/series/29603/
State : failure

== Summary ==

IGT patchset build failed on latest successful build
c2159678d283fea5615ec8e846a51cf4954ac82d tests/perf: add Geminilake support

make  all-recursive
Making all in lib
make  all-recursive
Making all in .
Making all in tests
make[4]: Nothing to be done for 'all'.
Making all in man
make[2]: Nothing to be done for 'all'.
Making all in tools
Making all in null_state_gen
make[3]: Nothing to be done for 'all'.
Making all in registers
make[3]: Nothing to be done for 'all'.
  CCLD intel_aubdump.la
ar: `u' modifier ignored since `D' is the default (see `U')
  CCLD intel_audio_dump
  CCLD intel_reg
  CCLD intel_bios_dumper
intel_bios_dumper.o: In function `main':
/home/cidrm/intel-gpu-tools/tools/intel_bios_dumper.c:58: undefined reference 
to `pci_system_init'
/home/cidrm/intel-gpu-tools/tools/intel_bios_dumper.c:66: undefined reference 
to `pci_device_find_by_slot'
/home/cidrm/intel-gpu-tools/tools/intel_bios_dumper.c:70: undefined reference 
to `pci_device_probe'
/home/cidrm/intel-gpu-tools/tools/intel_bios_dumper.c:89: undefined reference 
to `pci_device_read_rom'
/home/cidrm/intel-gpu-tools/tools/intel_bios_dumper.c:109: undefined reference 
to `pci_system_cleanup'
collect2: error: ld returned 1 exit status
Makefile:893: recipe for target 'intel_bios_dumper' failed
make[3]: *** [intel_bios_dumper] Error 1
Makefile:1193: recipe for target 'all-recursive' failed
make[2]: *** [all-recursive] Error 1
Makefile:530: recipe for target 'all-recursive' failed
make[1]: *** [all-recursive] Error 1
Makefile:462: recipe for target 'all' failed
make: *** [all] Error 2

   intel-gpu-tools 1.19: lib/tests/test-suite.log


# TOTAL: 17
# PASS:  11
# SKIP:  0
# XFAIL: 6
# FAIL:  0
# XPASS: 0
# ERROR: 0

.. contents:: :depth: 2

XFAIL: igt_no_exit
==

IGT-Version: 1.19-gba75a8bd (x86_64) (Linux: 4.10.0-28-generic x86_64)
Subtest A: SUCCESS (0.000s)
igt_no_exit: igt_core.c:573: common_exit_handler: Assertion `sig != 0 || 
igt_exit_called' failed.
XFAIL igt_no_exit (exit status: 134)

XFAIL: igt_no_exit_list_only


igt_no_exit_list_only: igt_core.c:573: common_exit_handler: Assertion `sig != 0 
|| igt_exit_called' failed.
A
XFAIL igt_no_exit_list_only (exit status: 134)

XFAIL: igt_no_subtest
=

igt_no_subtest: igt_core.c:1474: igt_exit: Assertion `!test_with_subtests || 
skipped_one || succeeded_one || failed_one' failed.
IGT-Version: 1.19-gba75a8bd (x86_64) (Linux: 4.10.0-28-generic x86_64)
Received signal SIGABRT.
XFAIL igt_no_subtest (exit status: 134)

XFAIL: igt_simple_test_subtests
===

igt_simple_test_subtests: igt_core.c:949: __igt_run_subtest: Assertion 
`test_with_subtests' failed.
IGT-Version: 1.19-gba75a8bd (x86_64) (Linux: 4.10.0-28-generic x86_64)
Received signal SIGABRT.
XFAIL igt_simple_test_subtests (exit status: 134)

XFAIL: igt_timeout
==

Test igt_timeout failed.
 DEBUG 
(igt_timeout:1099) igt-core-INFO: IGT-Version: 1.19-gba75a8bd (x86_64) (Linux: 
4.10.0-28-generic x86_64)
(igt_timeout:1099) igt-core-INFO: Timed out: Testcase
  END  
IGT-Version: 1.19-gba75a8bd (x86_64) (Linux: 4.10.0-28-generic x86_64)
Timed out: Testcase
FAIL (1.000s)
XFAIL igt_timeout (exit status: 99)

XFAIL: igt_invalid_subtest_name
===

IGT-Version: 1.19-gba75a8bd (x86_64) (Linux: 4.10.0-28-generic x86_64)
(igt_invalid_subtest_name:1117) igt-core-CRITICAL: Invalid subtest name "# 
invalid name !".
igt_invalid_subtest_name: igt_core.c:1474: igt_exit: Assertion 
`!test_with_subtests || skipped_one || succeeded_one || failed_one' failed.
Received signal SIGABRT.
XFAIL igt_invalid_subtest_name (exit status: 134)


   intel-gpu-tools 1.19: assembler/test-suite.log


# TOTAL: 10
# PASS:  10
# SKIP:  0
# XFAIL: 0
# FAIL:  0
# XPASS: 0
# ERROR: 0

.. contents:: :depth: 2


   intel-gpu-tools 1.19: tests/test-suite.log


# TOTAL: 1
# PASS:  1
# SKIP:  0
# XFAIL: 0
# FAIL:  0
# XPASS: 0
# ERROR: 0

.. contents:: :depth: 2


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[Intel-gfx] ✓ Fi.CI.BAT: success for Improve robustness of the i915 perf tests (rev3)

[Patchwork]

== Series Details ==

Series: Improve robustness of the i915 perf tests (rev3)
URL   : https://patchwork.freedesktop.org/series/28373/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
c2159678d283fea5615ec8e846a51cf4954ac82d tests/perf: add Geminilake support

with latest DRM-Tip kernel build CI_DRM_3021
c399d43adc55 drm-tip: 2017y-08m-31d-07h-25m-28s UTC integration manifest

Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
pass   -> FAIL   (fi-snb-2600) fdo#100215
Subgroup basic-flip-after-cursor-varying-size:
pass   -> FAIL   (fi-hsw-4770) fdo#102402 +1

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#102402 https://bugs.freedesktop.org/show_bug.cgi?id=102402

fi-bdw-5557u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:460s
fi-bdw-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:437s
fi-blb-e6850 total:288  pass:224  dwarn:1   dfail:0   fail:0   skip:63  
time:361s
fi-bsw-n3050 total:288  pass:243  dwarn:0   dfail:0   fail:0   skip:45  
time:554s
fi-bwr-2160  total:288  pass:184  dwarn:0   dfail:0   fail:0   skip:104 
time:256s
fi-bxt-j4205 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:528s
fi-byt-j1900 total:288  pass:254  dwarn:1   dfail:0   fail:0   skip:33  
time:529s
fi-byt-n2820 total:288  pass:250  dwarn:1   dfail:0   fail:0   skip:37  
time:519s
fi-elk-e7500 total:288  pass:230  dwarn:0   dfail:0   fail:0   skip:58  
time:444s
fi-glk-2atotal:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:614s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:2   skip:25  
time:466s
fi-hsw-4770r total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  
time:425s
fi-ilk-650   total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:430s
fi-ivb-3520m total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:519s
fi-ivb-3770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:474s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:602s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:601s
fi-pnv-d510  total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:524s
fi-skl-6260u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:469s
fi-skl-6700k total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:534s
fi-skl-6770hqtotal:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:497s
fi-skl-gvtdvmtotal:288  pass:266  dwarn:0   dfail:0   fail:0   skip:22  
time:442s
fi-skl-x1585ltotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:490s
fi-snb-2520m total:288  pass:251  dwarn:0   dfail:0   fail:0   skip:37  
time:559s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:2   skip:38  
time:415s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_132/
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[Intel-gfx] ✓ Fi.CI.BAT: success for lib/tests: Add audio selftest (rev2)

[Patchwork]

== Series Details ==

Series: lib/tests: Add audio selftest (rev2)
URL   : https://patchwork.freedesktop.org/series/29550/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
c2159678d283fea5615ec8e846a51cf4954ac82d tests/perf: add Geminilake support

with latest DRM-Tip kernel build CI_DRM_3021
c399d43adc55 drm-tip: 2017y-08m-31d-07h-25m-28s UTC integration manifest

Test kms_cursor_legacy:
Subgroup basic-flip-after-cursor-varying-size:
pass   -> FAIL   (fi-hsw-4770) fdo#102402 +1
Test kms_force_connector_basic:
Subgroup force-connector-state:
pass   -> SKIP   (fi-snb-2520m) fdo#101048

fdo#102402 https://bugs.freedesktop.org/show_bug.cgi?id=102402
fdo#101048 https://bugs.freedesktop.org/show_bug.cgi?id=101048

fi-bdw-5557u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:457s
fi-bdw-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:447s
fi-blb-e6850 total:288  pass:224  dwarn:1   dfail:0   fail:0   skip:63  
time:364s
fi-bsw-n3050 total:288  pass:243  dwarn:0   dfail:0   fail:0   skip:45  
time:554s
fi-bwr-2160  total:288  pass:184  dwarn:0   dfail:0   fail:0   skip:104 
time:253s
fi-bxt-j4205 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:523s
fi-byt-j1900 total:288  pass:254  dwarn:1   dfail:0   fail:0   skip:33  
time:527s
fi-byt-n2820 total:288  pass:250  dwarn:1   dfail:0   fail:0   skip:37  
time:522s
fi-elk-e7500 total:288  pass:230  dwarn:0   dfail:0   fail:0   skip:58  
time:439s
fi-glk-2atotal:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:619s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:2   skip:25  
time:470s
fi-hsw-4770r total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  
time:427s
fi-ilk-650   total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:421s
fi-ivb-3520m total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:507s
fi-ivb-3770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:491s
fi-kbl-7500u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:483s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:595s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:607s
fi-pnv-d510  total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:536s
fi-skl-6260u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:474s
fi-skl-6700k total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:535s
fi-skl-6770hqtotal:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:491s
fi-skl-gvtdvmtotal:288  pass:266  dwarn:0   dfail:0   fail:0   skip:22  
time:445s
fi-skl-x1585ltotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:492s
fi-snb-2520m total:288  pass:250  dwarn:0   dfail:0   fail:0   skip:38  
time:551s
fi-snb-2600  total:288  pass:249  dwarn:0   dfail:0   fail:1   skip:38  
time:410s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_131/
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[Intel-gfx] [PATCH i-g-t 1/1] chamelium: Add work in progress test for HDMI audio integrity testing

[Paul Kocialkowski]

This adds preliminary support for testing HDMI audio integrity with the
Chamelium. It aims to use the ALSA and audio IGT libraries to generate a
signal with a list of given frequencies, output it through HDMI and check
that the correct frequencies (and only those) are detected.

The test is currently work in progress and is not working. It is sent
only for reference and should not be merged.

Signed-off-by: Paul Kocialkowski 
---
 configure.ac|  9 +++--
 lib/igt_chamelium.c | 18 --
 lib/igt_chamelium.h |  6 +++-
 tests/Makefile.am   |  4 +--
 tests/chamelium.c   | 95 +++--
 5 files changed, 121 insertions(+), 11 deletions(-)

diff --git a/configure.ac b/configure.ac
index 41ec4d26..dd5d68b6 100644
--- a/configure.ac
+++ b/configure.ac
@@ -184,6 +184,9 @@ fi
 PKG_CHECK_MODULES(GSL, [gsl], [gsl=yes], [gsl=no])
 AM_CONDITIONAL(HAVE_GSL, [test "x$gsl" = xyes])
 
+PKG_CHECK_MODULES(ALSA, [alsa], [alsa=yes], [alsa=no])
+AM_CONDITIONAL(HAVE_ALSA, [test "x$alsa" = xyes])
+
 # for chamelium
 AC_ARG_ENABLE(chamelium, AS_HELP_STRING([--enable-chamelium],
  [Enable building of chamelium libraries and tests (default: no)]),
@@ -215,13 +218,13 @@ if test "x$enable_chamelium" = xyes; then
if test x"$gsl" != xyes; then
AC_MSG_ERROR([Failed to find gsl, required by chamelium.])
fi
+   if test x"$alsa" != xyes; then
+   AC_MSG_ERROR([Failed to find ALSA, required by chamelium.])
+   fi
 
AC_DEFINE(HAVE_CHAMELIUM, 1, [Enable Chamelium support])
 fi
 
-PKG_CHECK_MODULES(ALSA, [alsa], [alsa=yes], [alsa=no])
-AM_CONDITIONAL(HAVE_ALSA, [test "x$alsa" = xyes])
-
 # for audio
 AC_ARG_ENABLE(audio, AS_HELP_STRING([--enable-audio],
  [Enable building of audio tests (default: no)]),
diff --git a/lib/igt_chamelium.c b/lib/igt_chamelium.c
index dcd8855f..b4d98cd6 100644
--- a/lib/igt_chamelium.c
+++ b/lib/igt_chamelium.c
@@ -484,14 +484,14 @@ void chamelium_schedule_hpd_toggle(struct chamelium 
*chamelium,
  *
  * Returns: The ID of the EDID uploaded to the chamelium.
  */
-int chamelium_new_edid(struct chamelium *chamelium, const unsigned char *edid)
+int chamelium_new_edid(struct chamelium *chamelium, const unsigned char *edid, 
int size)
 {
xmlrpc_value *res;
struct chamelium_edid *allocated_edid;
int edid_id;
 
res = chamelium_rpc(chamelium, NULL, "CreateEdid", "(6)",
-   edid, EDID_LENGTH);
+   edid, size);
 
xmlrpc_read_int(>env, res, _id);
xmlrpc_DECREF(res);
@@ -1376,6 +1376,20 @@ igt_crc_t 
*chamelium_calculate_fb_crc_async_finish(struct chamelium_fb_crc_async
return ret;
 }
 
+void chamelium_start_capturing_audio(struct chamelium *chamelium,
+struct chamelium_port *port)
+{
+   xmlrpc_DECREF(chamelium_rpc(chamelium, port, "StartCapturingAudio",
+   "(ib)", port->id, true));
+}
+
+void chamelium_stop_capturing_audio(struct chamelium *chamelium,
+   struct chamelium_port *port)
+{
+   xmlrpc_DECREF(chamelium_rpc(chamelium, port, "StopCapturingAudio",
+   "(i)", port->id));
+}
+
 static unsigned int chamelium_get_port_type(struct chamelium *chamelium,
struct chamelium_port *port)
 {
diff --git a/lib/igt_chamelium.h b/lib/igt_chamelium.h
index 2a0fa234..c71a8620 100644
--- a/lib/igt_chamelium.h
+++ b/lib/igt_chamelium.h
@@ -65,7 +65,7 @@ void chamelium_fire_hpd_pulses(struct chamelium *chamelium,
 void chamelium_schedule_hpd_toggle(struct chamelium *chamelium,
   struct chamelium_port *port, int delay_ms,
   bool rising_edge);
-int chamelium_new_edid(struct chamelium *chamelium, const unsigned char *edid);
+int chamelium_new_edid(struct chamelium *chamelium, const unsigned char *edid, 
int size);
 void chamelium_port_set_edid(struct chamelium *chamelium,
 struct chamelium_port *port, int edid_id);
 bool chamelium_port_get_ddc_state(struct chamelium *chamelium,
@@ -115,5 +115,9 @@ void chamelium_assert_analog_frame_match_or_dump(struct 
chamelium *chamelium,
 void chamelium_crop_analog_frame(struct chamelium_frame_dump *dump, int width,
 int height);
 void chamelium_destroy_frame_dump(struct chamelium_frame_dump *dump);
+void chamelium_start_capturing_audio(struct chamelium *chamelium,
+struct chamelium_port *port);
+void chamelium_stop_capturing_audio(struct chamelium *chamelium,
+   struct chamelium_port *port);
 
 #endif /* IGT_CHAMELIUM_H */
diff --git a/tests/Makefile.am b/tests/Makefile.am
index 726e2b27..82ca5159 100644
--- a/tests/Makefile.am
+++ b/tests/Makefile.am
@@ 

[Intel-gfx] [PATCH i-g-t 0/1] chamelium: Add work in progress test for HDMI audio

[Paul Kocialkowski]

This patch contains a work in progress test for HDMI audio integrity
testing. It is currently not working and should not be merged.

It is sent as-is for reference, in hope that work in this area will be
resumed later on. It is the latest version at the time of my final
summer internship day at Intel, after which I will not have access to a
Chamelium anymore.

The test is currently failing as the Chamelium does not detect any audio,
failing with the following:
No audio data was captured. Perhaps this input is not plugged

The Chamelium logs indicate that no audio page is received:
Current page count: 0x0. Last page count: 0x0. Page count in this period: 0x0

It was checked that the EDID used properly contains the CEA block
indicating audio support.

The audio test in IGT, that involves a HDMI-VGA adapter with audio-out
implements HDMI audio integrity checking and can be used as a working
reference to debug the problem.

Once the problem is resolved, this test could be derived in different
fashions, including a suspend/resume test checking for audio integrity
before and after suspend/resume and a hotplug test checking for audio
integrity after a sequence of hotplug toggles.

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[Intel-gfx] ✗ Fi.CI.BAT: failure for pm_rps: Changes in waitboost scenario (rev10)

[Patchwork]

== Series Details ==

Series: pm_rps: Changes in waitboost scenario (rev10)
URL   : https://patchwork.freedesktop.org/series/28966/
State : failure

== Summary ==

IGT patchset tested on top of latest successful build
c2159678d283fea5615ec8e846a51cf4954ac82d tests/perf: add Geminilake support

with latest DRM-Tip kernel build CI_DRM_3021
c399d43adc55 drm-tip: 2017y-08m-31d-07h-25m-28s UTC integration manifest

Test kms_busy:
Subgroup basic-flip-a:
pass   -> FAIL   (fi-bwr-2160)
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
pass   -> FAIL   (fi-snb-2600) fdo#100215
Subgroup basic-flip-after-cursor-varying-size:
pass   -> FAIL   (fi-hsw-4770) fdo#102402 +1

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#102402 https://bugs.freedesktop.org/show_bug.cgi?id=102402

fi-bdw-5557u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:460s
fi-bdw-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:439s
fi-blb-e6850 total:288  pass:224  dwarn:1   dfail:0   fail:0   skip:63  
time:364s
fi-bsw-n3050 total:288  pass:243  dwarn:0   dfail:0   fail:0   skip:45  
time:567s
fi-bwr-2160  total:288  pass:183  dwarn:0   dfail:0   fail:1   skip:104 
time:254s
fi-bxt-j4205 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:527s
fi-byt-j1900 total:288  pass:254  dwarn:1   dfail:0   fail:0   skip:33  
time:526s
fi-byt-n2820 total:288  pass:250  dwarn:1   dfail:0   fail:0   skip:37  
time:525s
fi-elk-e7500 total:288  pass:230  dwarn:0   dfail:0   fail:0   skip:58  
time:438s
fi-glk-2atotal:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:616s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:2   skip:25  
time:469s
fi-hsw-4770r total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  
time:424s
fi-ilk-650   total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:429s
fi-ivb-3520m total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:509s
fi-ivb-3770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:476s
fi-kbl-7500u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:481s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:598s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:596s
fi-pnv-d510  total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:530s
fi-skl-6260u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:472s
fi-skl-6700k total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:538s
fi-skl-6770hqtotal:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:491s
fi-skl-gvtdvmtotal:288  pass:266  dwarn:0   dfail:0   fail:0   skip:22  
time:442s
fi-skl-x1585ltotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:490s
fi-snb-2520m total:288  pass:251  dwarn:0   dfail:0   fail:0   skip:37  
time:550s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:2   skip:38  
time:404s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_130/
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Re: [Intel-gfx] [PATCH i-g-t v2] lib/tests: Add audio selftest

[Paul Kocialkowski]

On Thu, 2017-08-31 at 11:02 +0300, Paul Kocialkowski wrote:
> This introduces a selftest for the audio library.
> 
> It consists of generating a signal from a list of frequencies and
> ensuring that the integrity checking function does detect these
> frequencies (and only these frequencies).

Looks like I forgot to CC Lyude on v2, sorry.

For reference, the patch is up at:
https://patchwork.freedesktop.org/series/29550/

> Signed-off-by: Paul Kocialkowski 
> ---
>  lib/tests/.gitignore   |  1 +
>  lib/tests/Makefile.am  |  4 ++--
>  lib/tests/Makefile.sources |  5 +
>  lib/tests/igt_audio.c  | 55
> ++
>  4 files changed, 63 insertions(+), 2 deletions(-)
>  create mode 100644 lib/tests/igt_audio.c
> 
> diff --git a/lib/tests/.gitignore b/lib/tests/.gitignore
> index ae11dd47..49bd5b01 100644
> --- a/lib/tests/.gitignore
> +++ b/lib/tests/.gitignore
> @@ -1,5 +1,6 @@
>  # Please keep sorted alphabetically
>  igt_assert
> +igt_audio
>  igt_fork_helper
>  igt_exit_handler
>  igt_invalid_subtest_name
> diff --git a/lib/tests/Makefile.am b/lib/tests/Makefile.am
> index 5d14194a..36c16124 100644
> --- a/lib/tests/Makefile.am
> +++ b/lib/tests/Makefile.am
> @@ -16,5 +16,5 @@ AM_CFLAGS = $(DRM_CFLAGS) $(CWARNFLAGS)
> $(DEBUG_CFLAGS) \
>  
>  LDADD = ../libintel_tools.la $(PCIACCESS_LIBS) $(DRM_LIBS)
> $(LIBUNWIND_LIBS) $(TIMER_LIBS)
>  
> -LDADD += $(CAIRO_LIBS) $(LIBUDEV_LIBS) $(GLIB_LIBS) -lm
> -AM_CFLAGS += $(CAIRO_CFLAGS) $(LIBUDEV_CFLAGS) $(GLIB_CFLAGS)
> +LDADD += $(CAIRO_LIBS) $(LIBUDEV_LIBS) $(GLIB_LIBS) $(GSL_LIBS) -lm
> +AM_CFLAGS += $(CAIRO_CFLAGS) $(LIBUDEV_CFLAGS) $(GLIB_CFLAGS)
> $(GSL_CFLAGS)
> diff --git a/lib/tests/Makefile.sources b/lib/tests/Makefile.sources
> index 8d1a8dea..eb702844 100644
> --- a/lib/tests/Makefile.sources
> +++ b/lib/tests/Makefile.sources
> @@ -18,6 +18,11 @@ check_prog_list = \
>   igt_can_fail_simple \
>   $(NULL)
>  
> +#if HAVE_GSL
> +check_prog_list += \
> + igt_audio
> +#endif
> +
>  TESTS = \
>   $(check_prog_list) \
>   $(check_script_list) \
> diff --git a/lib/tests/igt_audio.c b/lib/tests/igt_audio.c
> new file mode 100644
> index ..2f9d0492
> --- /dev/null
> +++ b/lib/tests/igt_audio.c
> @@ -0,0 +1,55 @@
> +/*
> + * Copyright © 2017 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person
> obtaining a
> + * copy of this software and associated documentation files (the
> "Software"),
> + * to deal in the Software without restriction, including without
> limitation
> + * the rights to use, copy, modify, merge, publish, distribute,
> sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom
> the
> + * Software is furnished to do so, subject to the following
> conditions:
> + *
> + * The above copyright notice and this permission notice (including
> the next
> + * paragraph) shall be included in all copies or substantial portions
> of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT
> SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES
> OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */
> +
> +#include "igt_core.h"
> +#include "igt_audio.h"
> +
> +static int test_frequencies[] = {
> + 300,
> + 600,
> + 1200,
> + 8,
> + 1,
> +};
> +
> +igt_simple_main
> +{
> + short buffer[2048];
> + struct audio_signal *signal;
> + int i;
> +
> + signal = audio_signal_init(2, 44800);
> + igt_assert(signal);
> +
> + for (i = 0; i < ARRAY_SIZE(test_frequencies); i++)
> + audio_signal_add_frequency(signal,
> test_frequencies[i]);
> +
> + audio_signal_synthesize(signal);
> + audio_signal_fill(signal, buffer, 1024);
> +
> + igt_assert(audio_signal_detect(signal, 2, 44800, buffer,
> 1024));
> +
> + audio_signal_clean(signal);
> + free(signal);
> +}
-- 
Paul Kocialkowski 
Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo, Finland
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[Intel-gfx] ✓ Fi.CI.BAT: success for kms_ccs testcase improvements

[Patchwork]

== Series Details ==

Series: kms_ccs testcase improvements
URL   : https://patchwork.freedesktop.org/series/29585/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
c2159678d283fea5615ec8e846a51cf4954ac82d tests/perf: add Geminilake support

with latest DRM-Tip kernel build CI_DRM_3021
c399d43adc55 drm-tip: 2017y-08m-31d-07h-25m-28s UTC integration manifest

Test kms_cursor_legacy:
Subgroup basic-flip-after-cursor-varying-size:
pass   -> FAIL   (fi-hsw-4770) fdo#102402 +1
Test kms_flip:
Subgroup basic-flip-vs-modeset:
skip   -> PASS   (fi-skl-x1585l) fdo#101781

fdo#102402 https://bugs.freedesktop.org/show_bug.cgi?id=102402
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781

fi-bdw-5557u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:457s
fi-bdw-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:438s
fi-blb-e6850 total:288  pass:224  dwarn:1   dfail:0   fail:0   skip:63  
time:364s
fi-bsw-n3050 total:288  pass:243  dwarn:0   dfail:0   fail:0   skip:45  
time:555s
fi-bwr-2160  total:288  pass:184  dwarn:0   dfail:0   fail:0   skip:104 
time:253s
fi-bxt-j4205 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:533s
fi-byt-j1900 total:288  pass:254  dwarn:1   dfail:0   fail:0   skip:33  
time:526s
fi-byt-n2820 total:288  pass:250  dwarn:1   dfail:0   fail:0   skip:37  
time:516s
fi-elk-e7500 total:288  pass:230  dwarn:0   dfail:0   fail:0   skip:58  
time:449s
fi-glk-2atotal:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:614s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:2   skip:25  
time:464s
fi-hsw-4770r total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  
time:423s
fi-ilk-650   total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:429s
fi-ivb-3520m total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:501s
fi-ivb-3770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:474s
fi-kbl-7500u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:481s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:597s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:595s
fi-pnv-d510  total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:528s
fi-skl-6260u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:470s
fi-skl-6700k total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:540s
fi-skl-6770hqtotal:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:489s
fi-skl-gvtdvmtotal:288  pass:266  dwarn:0   dfail:0   fail:0   skip:22  
time:449s
fi-skl-x1585ltotal:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:503s
fi-snb-2520m total:288  pass:251  dwarn:0   dfail:0   fail:0   skip:37  
time:548s
fi-snb-2600  total:288  pass:249  dwarn:0   dfail:0   fail:1   skip:38  
time:407s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_129/
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Re: [Intel-gfx] [PATCH] drm/i915/cnl: Fix DP max voltage

[Ville Syrjälä]

On Wed, Aug 30, 2017 at 05:00:50PM -0700, Rodrigo Vivi wrote:
> From: "Vivi, Rodrigo" 
> 
> On clock recovery this function is called to find out
> the max voltage swing level that we could go.
> 
> However gen 9 functions use the old buffer translation tables
> to figure that out. That table is not valid for CNL
> causing an invalid number of entries and an invalid selection
> on the max voltage swing level.
> 
> v2: Let's use same approach that previous platforms.
> v3: Actually use n_entries and avoid duplicated -1.
> 
> Cc: Ville Syrjälä 
> Cc: Clint Taylor 
> Signed-off-by: Rodrigo Vivi 
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 48 
> +++-
>  1 file changed, 38 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index d962552e2ccc..9aa508616284 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -649,6 +649,29 @@ cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, 
> int *n_entries)
>   }
>  }
>  
> +static int cnl_max_level(struct drm_i915_private *dev_priv,
> +  enum intel_output_type type)
> +{
> + int n_entries = 0;
> +
> + switch (type) {
> + case INTEL_OUTPUT_DP:
> + cnl_get_buf_trans_dp(dev_priv, _entries);
> + break;
> + case INTEL_OUTPUT_EDP:
> + cnl_get_buf_trans_edp(dev_priv, _entries);
> + break;
> + case INTEL_OUTPUT_HDMI:
> + cnl_get_buf_trans_hdmi(dev_priv, _entries);
> + break;
> + default:
> + MISSING_CASE(type);
> + return 0;
> + }
> +
> + return n_entries;
> +}
> +
>  static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port 
> port)
>  {
>   int n_hdmi_entries;
> @@ -1877,19 +1900,24 @@ static void bxt_ddi_vswing_sequence(struct 
> drm_i915_private *dev_priv,
>  u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
>  {
>   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - int n_entries;
> + int n_entries, level;
>  
> - if (encoder->type == INTEL_OUTPUT_EDP)
> - intel_ddi_get_buf_trans_edp(dev_priv, _entries);
> - else
> - intel_ddi_get_buf_trans_dp(dev_priv, _entries);
> + if (IS_CANNONLAKE(dev_priv)) {
> + level = cnl_max_level(dev_priv, encoder->type);
> + } else {
> + if (encoder->type == INTEL_OUTPUT_EDP)
> + intel_ddi_get_buf_trans_edp(dev_priv, _entries);
> + else
> + intel_ddi_get_buf_trans_dp(dev_priv, _entries);
> + level = n_entries - 1;

You removed the -1 from the cnl path but then added it to the other path?

In fact, I think to keep things looking a bit more consistent I'd just
open code the cnl stuff in intel_ddi_dp_voltage_max() the same way as
the other platforms are handled. And we don't even need to care about HDMI
here.

> + }
>  
> - if (WARN_ON(n_entries < 1))
> - n_entries = 1;
> - if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
> - n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
> + if (WARN_ON(level < 0))
> + level = 0;
> + if (WARN_ON(level > ARRAY_SIZE(index_to_dp_signal_levels) - 1))
> + level = ARRAY_SIZE(index_to_dp_signal_levels) - 1;
>  
> - return index_to_dp_signal_levels[n_entries - 1] &
> + return index_to_dp_signal_levels[level] &
>   DP_TRAIN_VOLTAGE_SWING_MASK;
>  }
>  
> -- 
> 2.13.2

-- 
Ville Syrjälä
Intel OTC
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[Intel-gfx] ✓ Fi.CI.BAT: success for tests/perf_pmu: test i915 RFC PMU (rev2)

[Patchwork]

== Series Details ==

Series: tests/perf_pmu: test i915 RFC PMU (rev2)
URL   : https://patchwork.freedesktop.org/series/29313/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
c2159678d283fea5615ec8e846a51cf4954ac82d tests/perf: add Geminilake support

with latest DRM-Tip kernel build CI_DRM_3021
c399d43adc55 drm-tip: 2017y-08m-31d-07h-25m-28s UTC integration manifest

Test gem_ringfill:
Subgroup basic-default-hang:
dmesg-warn -> PASS   (fi-pnv-d510) fdo#101600
Test kms_cursor_legacy:
Subgroup basic-flip-after-cursor-varying-size:
pass   -> FAIL   (fi-hsw-4770) fdo#102402 +1
Test kms_flip:
Subgroup basic-flip-vs-modeset:
skip   -> PASS   (fi-skl-x1585l) fdo#101781
Test kms_frontbuffer_tracking:
Subgroup basic:
pass   -> DMESG-WARN (fi-bdw-5557u) fdo#102473

fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600
fdo#102402 https://bugs.freedesktop.org/show_bug.cgi?id=102402
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781
fdo#102473 https://bugs.freedesktop.org/show_bug.cgi?id=102473

fi-bdw-5557u total:288  pass:267  dwarn:1   dfail:0   fail:0   skip:20  
time:458s
fi-bdw-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:439s
fi-blb-e6850 total:288  pass:224  dwarn:1   dfail:0   fail:0   skip:63  
time:366s
fi-bsw-n3050 total:288  pass:243  dwarn:0   dfail:0   fail:0   skip:45  
time:553s
fi-bwr-2160  total:288  pass:184  dwarn:0   dfail:0   fail:0   skip:104 
time:253s
fi-bxt-j4205 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:512s
fi-byt-j1900 total:288  pass:254  dwarn:1   dfail:0   fail:0   skip:33  
time:526s
fi-byt-n2820 total:288  pass:250  dwarn:1   dfail:0   fail:0   skip:37  
time:515s
fi-elk-e7500 total:288  pass:230  dwarn:0   dfail:0   fail:0   skip:58  
time:440s
fi-glk-2atotal:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:619s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:2   skip:25  
time:461s
fi-hsw-4770r total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  
time:427s
fi-ilk-650   total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:426s
fi-ivb-3520m total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:515s
fi-ivb-3770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:477s
fi-kbl-7500u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:482s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:597s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:602s
fi-pnv-d510  total:288  pass:224  dwarn:0   dfail:0   fail:0   skip:64  
time:529s
fi-skl-6260u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:473s
fi-skl-6700k total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:534s
fi-skl-6770hqtotal:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:489s
fi-skl-gvtdvmtotal:288  pass:266  dwarn:0   dfail:0   fail:0   skip:22  
time:442s
fi-skl-x1585ltotal:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:511s
fi-snb-2520m total:288  pass:251  dwarn:0   dfail:0   fail:0   skip:37  
time:549s
fi-snb-2600  total:288  pass:249  dwarn:0   dfail:0   fail:1   skip:38  
time:406s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_128/
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Keep the device awake whilst in the GTT write domain (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Keep the device awake whilst in the GTT write domain (rev2)
URL   : https://patchwork.freedesktop.org/series/29594/
State : failure

== Summary ==

Series 29594v2 drm/i915: Keep the device awake whilst in the GTT write domain
https://patchwork.freedesktop.org/api/1.0/series/29594/revisions/2/mbox/

Test gem_exec_flush:
Subgroup basic-batch-kernel-default-uc:
pass   -> FAIL   (fi-snb-2600) fdo#17
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-legacy:
fail   -> PASS   (fi-snb-2600) fdo#100215
Subgroup basic-flip-after-cursor-varying-size:
pass   -> FAIL   (fi-hsw-4770) fdo#102402 +1
Test kms_frontbuffer_tracking:
Subgroup basic:
pass   -> DMESG-WARN (fi-snb-2520m)
pass   -> DMESG-WARN (fi-snb-2600)
pass   -> DMESG-WARN (fi-ivb-3520m)
pass   -> DMESG-WARN (fi-ivb-3770)
pass   -> DMESG-WARN (fi-byt-j1900)
pass   -> DMESG-WARN (fi-bdw-gvtdvm) fdo#102374
pass   -> DMESG-WARN (fi-bsw-n3050) fdo#101707
pass   -> DMESG-WARN (fi-skl-6260u)
pass   -> DMESG-WARN (fi-skl-6700k)
pass   -> DMESG-WARN (fi-skl-6770hq)
pass   -> DMESG-WARN (fi-skl-gvtdvm)
pass   -> DMESG-WARN (fi-skl-x1585l)
pass   -> DMESG-WARN (fi-bxt-j4205)
pass   -> DMESG-WARN (fi-kbl-7500u)
pass   -> DMESG-WARN (fi-glk-2a) fdo#102457
Test pm_rpm:
Subgroup basic-pci-d3-state:
pass   -> FAIL   (fi-byt-j1900)
pass   -> FAIL   (fi-hsw-4770)
pass   -> FAIL   (fi-hsw-4770r)
pass   -> FAIL   (fi-bdw-5557u)
pass   -> FAIL   (fi-bsw-n3050)
pass   -> FAIL   (fi-skl-6260u)
pass   -> FAIL   (fi-skl-6700k)
pass   -> FAIL   (fi-skl-6770hq)
pass   -> FAIL   (fi-skl-x1585l)
pass   -> FAIL   (fi-bxt-j4205)
pass   -> FAIL   (fi-kbl-7500u)
pass   -> FAIL   (fi-kbl-7560u)
pass   -> FAIL   (fi-kbl-r)
pass   -> FAIL   (fi-glk-2a)
Subgroup basic-rte:
pass   -> FAIL   (fi-byt-j1900)
pass   -> FAIL   (fi-hsw-4770)
pass   -> FAIL   (fi-hsw-4770r)
pass   -> FAIL   (fi-bdw-5557u)
pass   -> FAIL   (fi-bsw-n3050)
pass   -> FAIL   (fi-skl-6260u)
pass   -> FAIL   (fi-skl-6700k)
pass   -> FAIL   (fi-skl-6770hq)
pass   -> FAIL   (fi-skl-x1585l)
pass   -> FAIL   (fi-bxt-j4205)
pass   -> FAIL   (fi-kbl-7500u)
pass   -> FAIL   (fi-kbl-7560u)
pass   -> FAIL   (fi-kbl-r)
pass   -> FAIL   (fi-glk-2a)

fdo#17 https://bugs.freedesktop.org/show_bug.cgi?id=17
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#102402 https://bugs.freedesktop.org/show_bug.cgi?id=102402
fdo#102374 https://bugs.freedesktop.org/show_bug.cgi?id=102374
fdo#101707 https://bugs.freedesktop.org/show_bug.cgi?id=101707
fdo#102457 https://bugs.freedesktop.org/show_bug.cgi?id=102457

fi-bdw-5557u total:288  pass:266  dwarn:0   dfail:0   fail:2   skip:20  
time:477s
fi-bdw-gvtdvmtotal:288  pass:264  dwarn:1   dfail:0   fail:0   skip:23  
time:439s
fi-blb-e6850 total:288  pass:224  dwarn:1   dfail:0   fail:0   skip:63  
time:364s
fi-bsw-n3050 total:288  pass:240  dwarn:1   dfail:0   fail:2   skip:45  
time:583s
fi-bwr-2160  total:288  pass:184  dwarn:0   dfail:0   fail:0   skip:104 
time:253s
fi-bxt-j4205 total:288  pass:257  dwarn:1   dfail:0   fail:2   skip:28  
time:546s
fi-byt-j1900 total:288  pass:251  dwarn:2   dfail:0   fail:2   skip:33  
time:544s
fi-elk-e7500 total:288  pass:230  dwarn:0   dfail:0   fail:0   skip:58  
time:441s
fi-glk-2atotal:288  pass:257  dwarn:1   dfail:0   fail:2   skip:28  
time:631s
fi-hsw-4770  total:288  pass:259  dwarn:0   dfail:0   fail:4   skip:25  
time:485s
fi-hsw-4770r total:288  pass:261  dwarn:0   dfail:0   fail:2   skip:25  
time:440s
fi-ilk-650   total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:425s
fi-ivb-3520m total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:501s
fi-ivb-3770  total:288  pass:260  dwarn:1   dfail:0   fail:0   skip:27  
time:478s
fi-kbl-7500u total:288  pass:258  dwarn:1   dfail:0   fail:2   skip:27  
time:501s

Re: [Intel-gfx] [RFC v2 2/3] drm/i915/pmu: serve global events and support perf stat

[Peter Zijlstra]

On Wed, Aug 30, 2017 at 05:24:30PM +, Rogozhkin, Dmitry V wrote:
> Ok... but they could register for just cpu0. Besides, it looks like on
> Linux cpu0 can't go offline at all at least of x86 architecture. Peter,
> could you, please, clarify the reasoning to register designated readers
> of uncore PMU for few CPUs?

arch/x86/Kconfig:config BOOTPARAM_HOTPLUG_CPU0

means we cannot rely on CPU0 being present, even on x86.
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Re: [Intel-gfx] [RFC v2 2/3] drm/i915/pmu: serve global events and support perf stat

[Peter Zijlstra]

On Wed, Aug 30, 2017 at 05:24:30PM +, Rogozhkin, Dmitry V wrote:
> I figured out how to track cpus online/offline status in PMU. Here is a
> question however. What is the reason for uncore PMUs (cstate.c for
> example) to register for cpus other than cpu0? I see it registers for
> first thread of each cpu, on my 8 logical-core systems it registers for
> cpu0-3 it seems.

The other answer is that on multi-socket, C-state needs more than 1 CPU.
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cnp: Wa 1181: Fix Backlight issue (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/cnp: Wa 1181: Fix Backlight issue (rev2)
URL   : https://patchwork.freedesktop.org/series/29452/
State : success

== Summary ==

Series 29452v2 drm/i915/cnp: Wa 1181: Fix Backlight issue
https://patchwork.freedesktop.org/api/1.0/series/29452/revisions/2/mbox/

Test kms_cursor_legacy:
Subgroup basic-flip-after-cursor-varying-size:
pass   -> FAIL   (fi-hsw-4770) fdo#102402 +1
Test kms_flip:
Subgroup basic-flip-vs-modeset:
skip   -> PASS   (fi-skl-x1585l) fdo#101781

fdo#102402 https://bugs.freedesktop.org/show_bug.cgi?id=102402
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781

fi-bdw-5557u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:461s
fi-bdw-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:442s
fi-blb-e6850 total:288  pass:224  dwarn:1   dfail:0   fail:0   skip:63  
time:365s
fi-bsw-n3050 total:288  pass:243  dwarn:0   dfail:0   fail:0   skip:45  
time:558s
fi-bwr-2160  total:288  pass:184  dwarn:0   dfail:0   fail:0   skip:104 
time:255s
fi-bxt-j4205 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:522s
fi-byt-j1900 total:288  pass:254  dwarn:1   dfail:0   fail:0   skip:33  
time:524s
fi-byt-n2820 total:288  pass:250  dwarn:1   dfail:0   fail:0   skip:37  
time:514s
fi-elk-e7500 total:288  pass:230  dwarn:0   dfail:0   fail:0   skip:58  
time:437s
fi-glk-2atotal:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:613s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:2   skip:25  
time:461s
fi-hsw-4770r total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  
time:426s
fi-ilk-650   total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:424s
fi-ivb-3520m total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:499s
fi-ivb-3770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:474s
fi-kbl-7500u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:480s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:597s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:597s
fi-pnv-d510  total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:524s
fi-skl-6260u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:471s
fi-skl-6700k total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:534s
fi-skl-6770hqtotal:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:491s
fi-skl-gvtdvmtotal:288  pass:266  dwarn:0   dfail:0   fail:0   skip:22  
time:445s
fi-skl-x1585ltotal:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:505s
fi-snb-2520m total:288  pass:251  dwarn:0   dfail:0   fail:0   skip:37  
time:553s
fi-snb-2600  total:288  pass:249  dwarn:0   dfail:0   fail:1   skip:38  
time:403s

c399d43adc55a49d028d24ce7cdacc1823a4f159 drm-tip: 2017y-08m-31d-07h-25m-28s UTC 
integration manifest
c1ab2232cf79 drm/i915/cnp: Wa 1181: Fix Backlight issue

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5547/
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Disable DRRS when PSR is enabled

[Patchwork]

== Series Details ==

Series: drm/i915: Disable DRRS when PSR is enabled
URL   : https://patchwork.freedesktop.org/series/29577/
State : success

== Summary ==

Series 29577v1 drm/i915: Disable DRRS when PSR is enabled
https://patchwork.freedesktop.org/api/1.0/series/29577/revisions/1/mbox/

Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-legacy:
fail   -> PASS   (fi-snb-2600) fdo#100215
Subgroup basic-flip-after-cursor-varying-size:
pass   -> FAIL   (fi-hsw-4770) fdo#102402 +1

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#102402 https://bugs.freedesktop.org/show_bug.cgi?id=102402

fi-bdw-5557u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:457s
fi-bdw-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:443s
fi-blb-e6850 total:288  pass:224  dwarn:1   dfail:0   fail:0   skip:63  
time:360s
fi-bsw-n3050 total:288  pass:243  dwarn:0   dfail:0   fail:0   skip:45  
time:561s
fi-bwr-2160  total:288  pass:184  dwarn:0   dfail:0   fail:0   skip:104 
time:255s
fi-bxt-j4205 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:518s
fi-byt-j1900 total:288  pass:254  dwarn:1   dfail:0   fail:0   skip:33  
time:515s
fi-elk-e7500 total:288  pass:230  dwarn:0   dfail:0   fail:0   skip:58  
time:429s
fi-glk-2atotal:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:615s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:2   skip:25  
time:464s
fi-hsw-4770r total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  
time:425s
fi-ilk-650   total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:424s
fi-ivb-3520m total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:509s
fi-ivb-3770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:476s
fi-kbl-7500u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:475s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:598s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:590s
fi-pnv-d510  total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:528s
fi-skl-6260u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:462s
fi-skl-6700k total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:533s
fi-skl-6770hqtotal:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:491s
fi-skl-gvtdvmtotal:288  pass:266  dwarn:0   dfail:0   fail:0   skip:22  
time:446s
fi-skl-x1585ltotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:488s
fi-snb-2520m total:288  pass:251  dwarn:0   dfail:0   fail:0   skip:37  
time:551s
fi-snb-2600  total:288  pass:250  dwarn:0   dfail:0   fail:0   skip:38  
time:404s
fi-byt-n2820 failed to connect after reboot

c399d43adc55a49d028d24ce7cdacc1823a4f159 drm-tip: 2017y-08m-31d-07h-25m-28s UTC 
integration manifest
948d3af7dff5 drm/i915: Disable DRRS when PSR is enabled

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5546/
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/cnl: Fix DP max voltage (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/cnl: Fix DP max voltage (rev2)
URL   : https://patchwork.freedesktop.org/series/27076/
State : failure

== Summary ==

  CHK include/config/kernel.release
  CHK include/generated/uapi/linux/version.h
  CHK include/generated/utsrelease.h
  CHK include/generated/bounds.h
  CHK include/generated/timeconst.h
  CHK include/generated/asm-offsets.h
  CALLscripts/checksyscalls.sh
  CHK scripts/mod/devicetable-offsets.h
  CHK include/generated/compile.h
  CHK kernel/config_data.h
  CC [M]  drivers/gpu/drm/i915/intel_ddi.o
drivers/gpu/drm/i915/intel_ddi.c: In function ‘cnl_max_level’:
drivers/gpu/drm/i915/intel_ddi.c:598:3: error: implicit declaration of function 
‘cnl_get_buf_trans_dp’ [-Werror=implicit-function-declaration]
   cnl_get_buf_trans_dp(dev_priv, _entries);
   ^~~~
drivers/gpu/drm/i915/intel_ddi.c:601:3: error: implicit declaration of function 
‘cnl_get_buf_trans_edp’ [-Werror=implicit-function-declaration]
   cnl_get_buf_trans_edp(dev_priv, _entries);
   ^
drivers/gpu/drm/i915/intel_ddi.c:604:3: error: implicit declaration of function 
‘cnl_get_buf_trans_hdmi’ [-Werror=implicit-function-declaration]
   cnl_get_buf_trans_hdmi(dev_priv, _entries);
   ^~
drivers/gpu/drm/i915/intel_ddi.c: At top level:
drivers/gpu/drm/i915/intel_ddi.c:1867:1: error: conflicting types for 
‘cnl_get_buf_trans_hdmi’
 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
 ^~
drivers/gpu/drm/i915/intel_ddi.c:604:3: note: previous implicit declaration of 
‘cnl_get_buf_trans_hdmi’ was here
   cnl_get_buf_trans_hdmi(dev_priv, _entries);
   ^~
drivers/gpu/drm/i915/intel_ddi.c:1884:1: error: conflicting types for 
‘cnl_get_buf_trans_dp’
 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv,
 ^~~~
drivers/gpu/drm/i915/intel_ddi.c:598:3: note: previous implicit declaration of 
‘cnl_get_buf_trans_dp’ was here
   cnl_get_buf_trans_dp(dev_priv, _entries);
   ^~~~
drivers/gpu/drm/i915/intel_ddi.c:1901:1: error: conflicting types for 
‘cnl_get_buf_trans_edp’
 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv,
 ^
drivers/gpu/drm/i915/intel_ddi.c:601:3: note: previous implicit declaration of 
‘cnl_get_buf_trans_edp’ was here
   cnl_get_buf_trans_edp(dev_priv, _entries);
   ^
cc1: all warnings being treated as errors
scripts/Makefile.build:302: recipe for target 
'drivers/gpu/drm/i915/intel_ddi.o' failed
make[4]: *** [drivers/gpu/drm/i915/intel_ddi.o] Error 1
scripts/Makefile.build:561: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:561: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:561: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1019: recipe for target 'drivers' failed
make: *** [drivers] Error 2

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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v4,1/2] drm/i915: Track minimum acceptable cdclk instead of "minimum dotclock" (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [v4,1/2] drm/i915: Track minimum acceptable cdclk 
instead of "minimum dotclock" (rev2)
URL   : https://patchwork.freedesktop.org/series/27078/
State : success

== Summary ==

Series 27078v2 series starting with [v4,1/2] drm/i915: Track minimum acceptable 
cdclk instead of "minimum dotclock"
https://patchwork.freedesktop.org/api/1.0/series/27078/revisions/2/mbox/

Test kms_cursor_legacy:
Subgroup basic-flip-after-cursor-varying-size:
pass   -> FAIL   (fi-hsw-4770) fdo#102402 +1

fdo#102402 https://bugs.freedesktop.org/show_bug.cgi?id=102402

fi-bdw-5557u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:464s
fi-bdw-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:441s
fi-blb-e6850 total:288  pass:224  dwarn:1   dfail:0   fail:0   skip:63  
time:360s
fi-bsw-n3050 total:288  pass:243  dwarn:0   dfail:0   fail:0   skip:45  
time:564s
fi-bwr-2160  total:288  pass:184  dwarn:0   dfail:0   fail:0   skip:104 
time:255s
fi-bxt-j4205 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:526s
fi-byt-j1900 total:288  pass:254  dwarn:1   dfail:0   fail:0   skip:33  
time:533s
fi-byt-n2820 total:288  pass:250  dwarn:1   dfail:0   fail:0   skip:37  
time:523s
fi-elk-e7500 total:288  pass:230  dwarn:0   dfail:0   fail:0   skip:58  
time:438s
fi-glk-2atotal:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:612s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:2   skip:25  
time:464s
fi-hsw-4770r total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  
time:433s
fi-ilk-650   total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:426s
fi-ivb-3520m total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:505s
fi-ivb-3770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:478s
fi-kbl-7500u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:483s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:594s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:595s
fi-pnv-d510  total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  
time:532s
fi-skl-6260u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:470s
fi-skl-6770hqtotal:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:492s
fi-skl-gvtdvmtotal:288  pass:266  dwarn:0   dfail:0   fail:0   skip:22  
time:439s
fi-skl-x1585ltotal:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:485s
fi-snb-2520m total:288  pass:251  dwarn:0   dfail:0   fail:0   skip:37  
time:551s
fi-snb-2600  total:288  pass:249  dwarn:0   dfail:0   fail:1   skip:38  
time:409s
fi-skl-6700k failed to connect after reboot

c399d43adc55a49d028d24ce7cdacc1823a4f159 drm-tip: 2017y-08m-31d-07h-25m-28s UTC 
integration manifest
a0e6c5492430 drm/i915: Consolidate max_cdclk_freq check in 
intel_crtc_compute_min_cdclk()
0a10b9ef9742 drm/i915: Track minimum acceptable cdclk instead of "minimum 
dotclock"

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5544/
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[Intel-gfx] [PATCH i-g-t 2/2] lib: Attemp at .so libraries

[Daniel Vetter]

I managed to get it built, but none of the executables is using it.

At least one version of this also needed the alsa lib/flags added, so
it'll build properly as an .so. No idea why it doesn't go boom when
only building the .la.

Signed-off-by: Daniel Vetter 
---
 configure.ac| 2 ++
 lib/Makefile.am | 6 --
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/configure.ac b/configure.ac
index 41ec4d26391a..97251883d11c 100644
--- a/configure.ac
+++ b/configure.ac
@@ -39,6 +39,8 @@ AC_CANONICAL_TARGET
 AM_INIT_AUTOMAKE([1.12 foreign subdir-objects dist-bzip2])
 AM_PATH_PYTHON([3],, [:])
 
+LT_INIT
+
 AC_PROG_CC
 AC_PROG_LEX
 AC_PROG_YACC
diff --git a/lib/Makefile.am b/lib/Makefile.am
index 0c26186132d1..40399be12da9 100644
--- a/lib/Makefile.am
+++ b/lib/Makefile.am
@@ -5,9 +5,10 @@ SUBDIRS = . tests
 
 include Makefile.sources
 
+lib_LTLIBRARIES = libigt.la
+
 libigt_la_SOURCES = $(lib_source_list)
 
-noinst_LTLIBRARIES = libigt.la
 noinst_HEADERS = check-ndebug.h
 
 if HAVE_LIBDRM_VC4
@@ -60,6 +61,7 @@ AM_CFLAGS = \
$(PIXMAN_CFLAGS) \
$(GLIB_CFLAGS) \
$(VALGRIND_CFLAGS) \
+   $(ALSA_CFLAGS) \
-DIGT_SRCDIR=\""$(abs_top_srcdir)/tests"\" \
-DIGT_DATADIR=\""$(pkgdatadir)"\" \
-DIGT_LOG_DOMAIN=\""$(subst _,-,$*)"\" \
@@ -81,5 +83,5 @@ libigt_la_LIBADD = \
$(LIBUDEV_LIBS) \
$(PIXMAN_LIBS) \
$(GLIB_LIBS) \
+   $(ALSA_LIBS) \
-lm
-
-- 
2.5.5

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[Intel-gfx] [PATCH i-g-t 1/2] lib: rename to libigt

[Daniel Vetter]

Just for ocd.

Signed-off-by: Daniel Vetter 
---
 benchmarks/Makefile.am |  2 +-
 debugger/Makefile.am   |  2 +-
 demos/Makefile.am  |  2 +-
 lib/Makefile.am| 10 +-
 lib/tests/Makefile.am  |  2 +-
 tests/Makefile.am  |  2 +-
 tools/Makefile.am  |  6 +++---
 7 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/benchmarks/Makefile.am b/benchmarks/Makefile.am
index 767731f7d18f..1232753917af 100644
--- a/benchmarks/Makefile.am
+++ b/benchmarks/Makefile.am
@@ -9,7 +9,7 @@ endif
 AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/lib
 AM_CFLAGS = $(DRM_CFLAGS) $(CWARNFLAGS) $(CAIRO_CFLAGS) $(LIBUNWIND_CFLAGS) \
$(WERROR_CFLAGS)
-LDADD = $(top_builddir)/lib/libintel_tools.la
+LDADD = $(top_builddir)/lib/libigt.la
 
 benchmarks_LTLIBRARIES = gem_exec_tracer.la
 gem_exec_tracer_la_LDFLAGS = -module -avoid-version -no-undefined
diff --git a/debugger/Makefile.am b/debugger/Makefile.am
index 9d231d3fffaf..8590c4c36492 100644
--- a/debugger/Makefile.am
+++ b/debugger/Makefile.am
@@ -15,4 +15,4 @@ AM_CFLAGS =   \
$(LIBUNWIND_CFLAGS) \
$(CWARNFLAGS)
 
-LDADD = $(top_builddir)/lib/libintel_tools.la
+LDADD = $(top_builddir)/lib/libigt.la
diff --git a/demos/Makefile.am b/demos/Makefile.am
index fe0ff1ff0120..031595c1f52f 100644
--- a/demos/Makefile.am
+++ b/demos/Makefile.am
@@ -9,4 +9,4 @@ endif
 AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/lib
 AM_CFLAGS = $(DRM_CFLAGS) $(PCIACCESS_CFLAGS) $(CWARNFLAGS) \
$(CAIRO_CFLAGS) $(LIBUNWIND_CFLAGS) $(WERROR_CFLAGS)
-LDADD = $(top_builddir)/lib/libintel_tools.la
+LDADD = $(top_builddir)/lib/libigt.la
diff --git a/lib/Makefile.am b/lib/Makefile.am
index 3ff14f66cdea..0c26186132d1 100644
--- a/lib/Makefile.am
+++ b/lib/Makefile.am
@@ -5,19 +5,19 @@ SUBDIRS = . tests
 
 include Makefile.sources
 
-libintel_tools_la_SOURCES = $(lib_source_list)
+libigt_la_SOURCES = $(lib_source_list)
 
-noinst_LTLIBRARIES = libintel_tools.la
+noinst_LTLIBRARIES = libigt.la
 noinst_HEADERS = check-ndebug.h
 
 if HAVE_LIBDRM_VC4
-libintel_tools_la_SOURCES +=   \
+libigt_la_SOURCES +=   \
 igt_vc4.c  \
 igt_vc4.h
 endif
 
 if !HAVE_LIBDRM_INTEL
-libintel_tools_la_SOURCES +=   \
+libigt_la_SOURCES +=   \
 stubs/drm/intel_bufmgr.c   \
 stubs/drm/intel_bufmgr.h
 endif
@@ -67,7 +67,7 @@ AM_CFLAGS = \
 
 AM_CFLAGS += $(CAIRO_CFLAGS)
 
-libintel_tools_la_LIBADD = \
+libigt_la_LIBADD = \
$(DRM_LIBS) \
$(PCIACCESS_LIBS) \
$(PROCPS_LIBS) \
diff --git a/lib/tests/Makefile.am b/lib/tests/Makefile.am
index 5d14194ada12..91440a27a5e8 100644
--- a/lib/tests/Makefile.am
+++ b/lib/tests/Makefile.am
@@ -14,7 +14,7 @@ AM_CFLAGS = $(DRM_CFLAGS) $(CWARNFLAGS) $(DEBUG_CFLAGS) \
-DIGT_DATADIR=\""$(abs_srcdir)"\" \
$(NULL)
 
-LDADD = ../libintel_tools.la $(PCIACCESS_LIBS) $(DRM_LIBS) $(LIBUNWIND_LIBS) 
$(TIMER_LIBS)
+LDADD = ../libigt.la $(PCIACCESS_LIBS) $(DRM_LIBS) $(LIBUNWIND_LIBS) 
$(TIMER_LIBS)
 
 LDADD += $(CAIRO_LIBS) $(LIBUDEV_LIBS) $(GLIB_LIBS) -lm
 AM_CFLAGS += $(CAIRO_CFLAGS) $(LIBUDEV_CFLAGS) $(GLIB_CFLAGS)
diff --git a/tests/Makefile.am b/tests/Makefile.am
index 726e2b277411..3d9ea87ef4ee 100644
--- a/tests/Makefile.am
+++ b/tests/Makefile.am
@@ -79,7 +79,7 @@ AM_CFLAGS = $(DRM_CFLAGS) $(CWARNFLAGS) -Wno-unused-result 
$(DEBUG_CFLAGS)\
$(LIBUNWIND_CFLAGS) $(WERROR_CFLAGS) \
$(NULL)
 
-LDADD = ../lib/libintel_tools.la $(XMLRPC_LIBS)
+LDADD = ../lib/libigt.la $(XMLRPC_LIBS)
 
 AM_CFLAGS += $(CAIRO_CFLAGS) $(LIBUDEV_CFLAGS)
 AM_LDFLAGS = -Wl,--as-needed
diff --git a/tools/Makefile.am b/tools/Makefile.am
index c40e75c73bef..5991b4988865 100644
--- a/tools/Makefile.am
+++ b/tools/Makefile.am
@@ -10,7 +10,7 @@ endif
 if HAVE_UDEV
 bin_PROGRAMS += intel_dp_compliance
 intel_dp_compliance_CFLAGS = $(AM_CFLAGS)
-intel_dp_compliance_LDADD = $(top_builddir)/lib/libintel_tools.la
+intel_dp_compliance_LDADD = $(top_builddir)/lib/libigt.la
 endif
 
 SUBDIRS = null_state_gen registers
@@ -19,7 +19,7 @@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/lib
 AM_CFLAGS = $(DEBUG_CFLAGS) $(DRM_CFLAGS) $(PCIACCESS_CFLAGS) $(CWARNFLAGS) \
$(CAIRO_CFLAGS) $(LIBUNWIND_CFLAGS) -DPKGDATADIR=\"$(pkgdatadir)\" \
$(WERROR_CFLAGS)
-LDADD = $(top_builddir)/lib/libintel_tools.la
+LDADD = $(top_builddir)/lib/libigt.la
 AM_LDFLAGS = -Wl,--as-needed
 
 # aubdumper
@@ -28,7 +28,7 @@ module_LTLIBRARIES = intel_aubdump.la
 moduledir = $(libdir)
 intel_aubdump_la_LDFLAGS = -module -avoid-version -no-undefined
 intel_aubdump_la_SOURCES = aubdump.c
-intel_aubdump_la_LIBADD = $(top_builddir)/lib/libintel_tools.la -ldl
+intel_aubdump_la_LIBADD = $(top_builddir)/lib/libigt.la -ldl
 
 bin_SCRIPTS = intel_aubdump
 CLEANFILES = $(bin_SCRIPTS)
-- 
2.5.5

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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Add a default case in gen7 hwsp switch-case (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Add a default case in gen7 hwsp switch-case (rev2)
URL   : https://patchwork.freedesktop.org/series/29494/
State : failure

== Summary ==

Test kms_ccs:
Subgroup pipe-D-crc-primary-basic:
skip   -> INCOMPLETE (shard-hsw)
Test perf:
Subgroup polling:
pass   -> FAIL   (shard-hsw) fdo#102252 +1
Test kms_setmode:
Subgroup basic:
fail   -> PASS   (shard-hsw) fdo#99912

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912

shard-hswtotal:2220 pass:1193 dwarn:0   dfail:0   fail:16  skip:966 
time:9333s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5542/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: implement NOA mux reprogramming at ctx-switch

[Patchwork]

== Series Details ==

Series: drm/i915: implement NOA mux reprogramming at ctx-switch
URL   : https://patchwork.freedesktop.org/series/29564/
State : success

== Summary ==

Series 29564v1 drm/i915: implement NOA mux reprogramming at ctx-switch
https://patchwork.freedesktop.org/api/1.0/series/29564/revisions/1/mbox/

Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
pass   -> FAIL   (fi-snb-2600) fdo#100215
Subgroup basic-flip-after-cursor-varying-size:
pass   -> FAIL   (fi-hsw-4770) fdo#102402 +1
Test kms_flip:
Subgroup basic-flip-vs-modeset:
skip   -> PASS   (fi-skl-x1585l) fdo#101781

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#102402 https://bugs.freedesktop.org/show_bug.cgi?id=102402
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781

fi-bdw-5557u total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  
time:454s
fi-bdw-gvtdvmtotal:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:440s
fi-blb-e6850 total:288  pass:224  dwarn:1   dfail:0   fail:0   skip:63  
time:360s
fi-bsw-n3050 total:288  pass:243  dwarn:0   dfail:0   fail:0   skip:45  
time:559s
fi-bwr-2160  total:288  pass:184  dwarn:0   dfail:0   fail:0   skip:104 
time:255s
fi-bxt-j4205 total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:522s
fi-byt-j1900 total:288  pass:254  dwarn:1   dfail:0   fail:0   skip:33  
time:521s
fi-byt-n2820 total:288  pass:250  dwarn:1   dfail:0   fail:0   skip:37  
time:512s
fi-elk-e7500 total:288  pass:230  dwarn:0   dfail:0   fail:0   skip:58  
time:447s
fi-glk-2atotal:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  
time:610s
fi-hsw-4770  total:288  pass:261  dwarn:0   dfail:0   fail:2   skip:25  
time:465s
fi-hsw-4770r total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  
time:425s
fi-ilk-650   total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  
time:419s
fi-ivb-3520m total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:507s
fi-ivb-3770  total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:478s
fi-kbl-7500u total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:477s
fi-kbl-7560u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:598s
fi-kbl-r total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  
time:598s
fi-skl-6260u total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:469s
fi-skl-6700k total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  
time:538s
fi-skl-6770hqtotal:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:491s
fi-skl-gvtdvmtotal:288  pass:266  dwarn:0   dfail:0   fail:0   skip:22  
time:446s
fi-skl-x1585ltotal:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  
time:507s
fi-snb-2520m total:288  pass:251  dwarn:0   dfail:0   fail:0   skip:37  
time:555s
fi-snb-2600  total:288  pass:248  dwarn:0   dfail:0   fail:2   skip:38  
time:411s
fi-pnv-d510 failed to connect after reboot

c399d43adc55a49d028d24ce7cdacc1823a4f159 drm-tip: 2017y-08m-31d-07h-25m-28s UTC 
integration manifest
64fc27dd0b93 drm/i915: reprogram NOA muxes on context switch when using perf
2714213be61c drm/i915: pass wa_ctx as argument
a66d0a2b9c18 drm/i915: extract per-ctx/indirect bb programming
91d1ad1d720f drm/i915: use same define size for wa_bb pin/allocation

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5543/
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[Intel-gfx] [PATCH v2] drm/i915: Keep the device awake whilst in the GTT write domain

[Chris Wilson]

Since runtime suspend is very harsh on GTT mmappings (they all get
zapped on suspend) keep the device awake while we the buffer remains in
the GTT write domain (as we expect subsequent writes). We special case
writes here, as the write domain is more bounded than the read domains;
a buffer may remain in multiple read domains until it is written to, but
a write from the GTT must be flushed prior to using it elsewhere (e.g.
on the GPU). However, userspace can control the write-domain and
although there is a soft contract that writes must be flushed (for e.g.
flushing scanouts and fbc), in the worst case an idle buffer may keep the
device alive until the buffer is destroyed.
---
 drivers/gpu/drm/i915/i915_gem.c| 12 +---
 drivers/gpu/drm/i915/i915_gem_execbuffer.c |  2 ++
 drivers/gpu/drm/i915/i915_gem_object.h |  3 +++
 drivers/gpu/drm/i915/i915_gem_shrinker.c   |  4 +++-
 drivers/gpu/drm/i915/intel_lrc.c   |  1 +
 drivers/gpu/drm/i915/intel_ringbuffer.c|  3 +++
 6 files changed, 21 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e4cc08bc518c..553cc09e9ab3 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -235,6 +235,7 @@ i915_gem_object_get_pages_phys(struct drm_i915_gem_object 
*obj)
 
 static void __start_cpu_write(struct drm_i915_gem_object *obj)
 {
+   GEM_BUG_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
obj->base.read_domains = I915_GEM_DOMAIN_CPU;
obj->base.write_domain = I915_GEM_DOMAIN_CPU;
if (cpu_write_needs_clflush(obj))
@@ -667,11 +668,13 @@ fb_write_origin(struct drm_i915_gem_object *obj, unsigned 
int domain)
obj->frontbuffer_ggtt_origin : ORIGIN_CPU);
 }
 
-static void
+void
 flush_write_domain(struct drm_i915_gem_object *obj, unsigned int flush_domains)
 {
struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 
+   lockdep_assert_held(_priv->drm.struct_mutex);
+
if (!(obj->base.write_domain & flush_domains))
return;
 
@@ -695,15 +698,14 @@ flush_write_domain(struct drm_i915_gem_object *obj, 
unsigned int flush_domains)
switch (obj->base.write_domain) {
case I915_GEM_DOMAIN_GTT:
if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv)) {
-   intel_runtime_pm_get(dev_priv);
spin_lock_irq(_priv->uncore.lock);

POSTING_READ_FW(RING_ACTHD(dev_priv->engine[RCS]->mmio_base));
spin_unlock_irq(_priv->uncore.lock);
-   intel_runtime_pm_put(dev_priv);
}
 
intel_fb_obj_flush(obj,
   fb_write_origin(obj, I915_GEM_DOMAIN_GTT));
+   intel_runtime_pm_put(dev_priv);
break;
 
case I915_GEM_DOMAIN_CPU:
@@ -3425,6 +3427,7 @@ static void __i915_gem_object_flush_for_display(struct 
drm_i915_gem_object *obj)
flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
if (obj->cache_dirty)
i915_gem_clflush_object(obj, I915_CLFLUSH_FORCE);
+   GEM_BUG_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
obj->base.write_domain = 0;
 }
 
@@ -3555,6 +3558,7 @@ i915_gem_object_set_to_gtt_domain(struct 
drm_i915_gem_object *obj, bool write)
GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
if (write) {
+   intel_runtime_pm_get_noresume(to_i915(obj->base.dev));
obj->base.read_domains = I915_GEM_DOMAIN_GTT;
obj->base.write_domain = I915_GEM_DOMAIN_GTT;
obj->mm.dirty = true;
@@ -4394,6 +4398,8 @@ static void __i915_gem_free_objects(struct 
drm_i915_private *i915,
 
trace_i915_gem_object_destroy(obj);
 
+   flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
+
GEM_BUG_ON(i915_gem_object_is_active(obj));
list_for_each_entry_safe(vma, vn,
 >vma_list, obj_link) {
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 8a9d37ac16d4..62c215eb38b7 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1865,6 +1865,8 @@ void i915_vma_move_to_active(struct i915_vma *vma,
i915_gem_active_set(>last_read[idx], req);
list_move_tail(>vm_link, >vm->active_list);
 
+   if (obj->base.write_domain & I915_GEM_DOMAIN_GTT)
+   intel_runtime_pm_put(to_i915(obj->base.dev));
obj->base.write_domain = 0;
if (flags & EXEC_OBJECT_WRITE) {
obj->base.write_domain = I915_GEM_DOMAIN_RENDER;
diff --git a/drivers/gpu/drm/i915/i915_gem_object.h 
b/drivers/gpu/drm/i915/i915_gem_object.h
index c30d8f808185..f5f52c4090b0 100644
--- 

[Intel-gfx] [PATCH i-g-t v5 11/11] tests/perf: add support for Coffeelake

[Lionel Landwerlin]

Using the same timestamp frequency as Skylake/Kabylake.

Signed-off-by: Lionel Landwerlin 
---
 tests/perf.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/tests/perf.c b/tests/perf.c
index 070dee97..a4d3f663 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -1145,6 +1145,9 @@ init_sys_info(void)
} else if (IS_GEMINILAKE(devid)) {
test_set_uuid = "dd3fd789-e783-4204-8cd0-b671bbccb0cf";
timestamp_frequency = 1920;
+   } else if (IS_COFFEELAKE(devid)) {
+   test_set_uuid = "74fb4902-d3d3-4237-9e90-cbdc68d0a446";
+   timestamp_frequency = 1200;
} else {
igt_debug("unsupported GT\n");
return false;
-- 
2.14.1

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[Intel-gfx] [PATCH i-g-t v5 10/11] tests/perf: prevent power management to kick in when necessary

[Lionel Landwerlin]

Some of our tests measure that the OA unit produces reports at
expected time intervals (as configured through the PERF_OPEN
ioctl). It turns out the power management plays a role in the decision
of the OA unit to write reports to memory. Under normal circumstances
we don't really mind if the unit misses one report here or there, but
for our tests it makes pretty difficult to verify whether we've made a
mistake in the configuration.

To work around this, let's prevent power management to kick in by
holding /dev/cpu_dma_latency opened for the following tests :

  - blocking
  - polling
  - buffer-fill
  - oa-exponents

Many thanks to Chris Wilson for suggesting this!

Signed-off-by: Lionel Landwerlin 
---
 tests/perf.c | 64 ++--
 1 file changed, 41 insertions(+), 23 deletions(-)

diff --git a/tests/perf.c b/tests/perf.c
index 6c062d20..070dee97 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -288,6 +288,7 @@ static bool hsw_undefined_a_counters[45] = {
 static bool gen8_undefined_a_counters[45];
 
 static int drm_fd = -1;
+static int pm_fd = -1;
 static int stream_fd = -1;
 static uint32_t devid;
 static int card = -1;
@@ -331,21 +332,38 @@ __perf_close(int fd)
 {
close(fd);
stream_fd = -1;
+
+   if (pm_fd >= 0) {
+   close(pm_fd);
+   pm_fd = -1;
+   }
 }
 
 static int
-__perf_open(int fd, struct drm_i915_perf_open_param *param)
+__perf_open(int fd, struct drm_i915_perf_open_param *param, bool prevent_pm)
 {
int ret;
+   int32_t pm_value = 0;
 
if (stream_fd >= 0)
__perf_close(stream_fd);
+   if (pm_fd >= 0) {
+   close(pm_fd);
+   pm_fd = -1;
+   }
 
ret = igt_ioctl(fd, DRM_IOCTL_I915_PERF_OPEN, param);
 
igt_assert(ret >= 0);
errno = 0;
 
+   if (prevent_pm) {
+   pm_fd = open("/dev/cpu_dma_latency", O_RDWR);
+   igt_assert(pm_fd >= 0);
+
+   igt_assert_eq(write(pm_fd, _value, sizeof(pm_value)), 
sizeof(pm_value));
+   }
+
return ret;
 }
 
@@ -1257,7 +1275,7 @@ test_system_wide_paranoid(void)
 
igt_drop_root();
 
-   stream_fd = __perf_open(drm_fd, );
+   stream_fd = __perf_open(drm_fd, , false);
__perf_close(stream_fd);
}
 
@@ -1314,7 +1332,7 @@ test_invalid_oa_metric_set_id(void)
 
/* Check that we aren't just seeing false positives... */
properties[ARRAY_SIZE(properties) - 1] = test_metric_set_id;
-   stream_fd = __perf_open(drm_fd, );
+   stream_fd = __perf_open(drm_fd, , false);
__perf_close(stream_fd);
 
/* There's no valid default OA metric set ID... */
@@ -1348,7 +1366,7 @@ test_invalid_oa_format_id(void)
 
/* Check that we aren't just seeing false positives... */
properties[ARRAY_SIZE(properties) - 1] = test_oa_format;
-   stream_fd = __perf_open(drm_fd, );
+   stream_fd = __perf_open(drm_fd, , false);
__perf_close(stream_fd);
 
/* There's no valid default OA format... */
@@ -1512,7 +1530,7 @@ open_and_read_2_oa_reports(int format_id,
.properties_ptr = to_user_pointer(properties),
};
 
-   stream_fd = __perf_open(drm_fd, );
+   stream_fd = __perf_open(drm_fd, , false);
 
read_2_oa_reports(format_id, exponent,
  oa_report0, oa_report1, timer_only);
@@ -1916,7 +1934,7 @@ test_oa_exponents(void)
  oa_exponent_to_ns(exponent) / 1000.0,
  oa_exponent_to_ns(exponent) / (1000.0 * 
1000.0));
 
-   stream_fd = __perf_open(drm_fd, );
+   stream_fd = __perf_open(drm_fd, , true /* 
prevent_pm */);
 
/* Right after opening the OA stream, read a
 * first timestamp as way to filter previously
@@ -2192,7 +2210,7 @@ test_invalid_oa_exponent(void)
.properties_ptr = to_user_pointer(properties),
};
 
-   stream_fd = __perf_open(drm_fd, );
+   stream_fd = __perf_open(drm_fd, , false);
 
__perf_close(stream_fd);
 
@@ -2246,7 +2264,7 @@ test_low_oa_exponent_permissions(void)
igt_fork(child, 1) {
igt_drop_root();
 
-   stream_fd = __perf_open(drm_fd, );
+   stream_fd = __perf_open(drm_fd, , false);
__perf_close(stream_fd);
}
 
@@ -2312,7 +2330,7 @@ test_per_context_mode_unprivileged(void)
 
properties[1] = ctx_id;
 
-   stream_fd = __perf_open(drm_fd, );
+   stream_fd = __perf_open(drm_fd, , false);
__perf_close(stream_fd);
 
drm_intel_gem_context_destroy(context);
@@ -2401,7 +2419,7 @@ test_blocking(void)
int64_t start, end;
int n = 0;
 
-   stream_fd = __perf_open(drm_fd, );
+   

[Intel-gfx] [PATCH i-g-t v5 09/11] tests/perf: estimate number of blocking/polling based on time spent

[Lionel Landwerlin]

Blocking & polling tests define an amount of time to spend in the test
and then estimate the number of syscalls that should successfully
return. The problem is that while running the test we might spend
slightly more time than initiallly planned. This change estimates the
number of syscalls based on time spent after the fact.

Signed-off-by: Lionel Landwerlin 
---
 tests/perf.c | 42 +-
 1 file changed, 33 insertions(+), 9 deletions(-)

diff --git a/tests/perf.c b/tests/perf.c
index 24df7c2a..6c062d20 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -2372,7 +2372,8 @@ test_blocking(void)
DRM_I915_PERF_PROP_OA_EXPONENT, oa_exponent,
};
struct drm_i915_perf_open_param param = {
-   .flags = I915_PERF_FLAG_FD_CLOEXEC,
+   .flags = I915_PERF_FLAG_FD_CLOEXEC |
+   I915_PERF_FLAG_DISABLED,
.num_properties = sizeof(properties) / 16,
.properties_ptr = to_user_pointer(properties),
};
@@ -2397,16 +2398,17 @@ test_blocking(void)
 */
int min_iterations = (test_duration_ns / (oa_period + 600ull));
 
-   int64_t start;
+   int64_t start, end;
int n = 0;
 
stream_fd = __perf_open(drm_fd, );
 
times(_times);
 
-   igt_debug("tick length = %dns, test duration = %"PRIu64"ns, min iter. = 
%d, max iter. = %d\n",
+   igt_debug("tick length = %dns, test duration = %"PRIu64"ns, min iter. = 
%d,"
+ " estimated max iter. = %d, oa_period = %"PRIu64"ns\n",
  (int)tick_ns, test_duration_ns,
- min_iterations, max_iterations);
+ min_iterations, max_iterations, oa_period);
 
/* In the loop we perform blocking polls while the HW is sampling at
 * ~25Hz, with the expectation that we spend most of our time blocked
@@ -2425,8 +2427,13 @@ test_blocking(void)
 * floor(real_stime)).
 *
 * We Loop for 1000 x tick_ns so one tick corresponds to 0.1%
+*
+* Also enable the stream just before poll/read to minimize
+* the error delta.
 */
-   for (start = get_time(); (get_time() - start) < test_duration_ns; /* 
nop */) {
+   start = get_time();
+   do_ioctl(stream_fd, I915_PERF_IOCTL_ENABLE, 0);
+   for (/* nop */; ((end = get_time()) - start) < test_duration_ns; /* nop 
*/) {
struct drm_i915_perf_record_header *header;
bool timer_report_read = false;
bool non_timer_report_read = false;
@@ -2468,6 +2475,12 @@ test_blocking(void)
n++;
}
 
+   /* Updated the maximum of iterations based on the time spent
+* in the loop.
+*/
+   max_iterations = (end - start) / oa_period + 1;
+   igt_debug("adjusted max iter. = %d\n", max_iterations);
+
times(_times);
 
/* Using nanosecond units is fairly silly here, given the tick in-
@@ -2524,6 +2537,7 @@ test_polling(void)
};
struct drm_i915_perf_open_param param = {
.flags = I915_PERF_FLAG_FD_CLOEXEC |
+   I915_PERF_FLAG_DISABLED |
I915_PERF_FLAG_FD_NONBLOCK,
.num_properties = sizeof(properties) / 16,
.properties_ptr = to_user_pointer(properties),
@@ -2548,7 +2562,7 @@ test_polling(void)
 * to check for data and giving some time to read().
 */
int min_iterations = (test_duration_ns / (oa_period + 600ull));
-   int64_t start;
+   int64_t start, end;
int n = 0;
 
stream_fd = __perf_open(drm_fd, );
@@ -2576,8 +2590,13 @@ test_polling(void)
 * floor(real_stime)).
 *
 * We Loop for 1000 x tick_ns so one tick corresponds to 0.1%
+*
+* Also enable the stream just before poll/read to minimize
+* the error delta.
 */
-   for (start = get_time(); (get_time() - start) < test_duration_ns; /* 
nop */) {
+   start = get_time();
+   do_ioctl(stream_fd, I915_PERF_IOCTL_ENABLE, 0);
+   for (/* nop */; ((end = get_time()) - start) < test_duration_ns; /* nop 
*/) {
struct pollfd pollfd = { .fd = stream_fd, .events = POLLIN };
struct drm_i915_perf_record_header *header;
bool timer_report_read = false;
@@ -2625,8 +2644,7 @@ test_polling(void)
if (header->type == 
DRM_I915_PERF_RECORD_SAMPLE) {
uint32_t *report = (void *)(header + 1);
 
-   if (oa_report_is_periodic(oa_exponent,
- report))
+   if (oa_report_is_periodic(oa_exponent, 
report))
timer_report_read = true;

[Intel-gfx] [PATCH i-g-t v5 05/11] tests/perf: remove frequency related changes

[Lionel Landwerlin]

Experience shows that most of the issues we face with periodicity of
the reports produced by the OA unit are related to power management,
not frequency.

Signed-off-by: Lionel Landwerlin 
---
 tests/perf.c | 141 ---
 1 file changed, 9 insertions(+), 132 deletions(-)

diff --git a/tests/perf.c b/tests/perf.c
index 5fe0a332..f256bac3 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -293,12 +293,9 @@ static int card = -1;
 static int n_eus;
 
 static uint64_t test_metric_set_id = UINT64_MAX;
-static uint64_t gt_min_freq_mhz_saved = 0;
-static uint64_t gt_max_freq_mhz_saved = 0;
-static uint64_t gt_min_freq_mhz = 0;
-static uint64_t gt_max_freq_mhz = 0;
 
 static uint64_t timestamp_frequency = 1250;
+static uint64_t gt_max_freq_mhz = 0;
 static enum drm_i915_oa_format test_oa_format;
 static bool *undefined_a_counters;
 static uint64_t oa_exp_1_millisec;
@@ -402,16 +399,6 @@ sysfs_read(const char *file)
return read_u64_file(buf);
 }
 
-static void
-sysfs_write(const char *file, uint64_t val)
-{
-   char buf[512];
-
-   snprintf(buf, sizeof(buf), "/sys/class/drm/card%d/%s", card, file);
-
-   write_u64_file(buf, val);
-}
-
 static char *
 read_debugfs_record(int device, const char *file, const char *key)
 {
@@ -1008,54 +995,6 @@ init_sys_info(void)
return try_read_u64_file(buf, _metric_set_id);
 }
 
-static void
-gt_frequency_range_save(void)
-{
-   gt_min_freq_mhz_saved = sysfs_read("gt_min_freq_mhz");
-   gt_max_freq_mhz_saved = sysfs_read("gt_max_freq_mhz");
-
-   gt_min_freq_mhz = gt_min_freq_mhz_saved;
-   gt_max_freq_mhz = gt_max_freq_mhz_saved;
-}
-
-static void
-gt_frequency_pin(int gt_freq_mhz)
-{
-   igt_debug("requesting pinned GT freq = %dmhz\n", gt_freq_mhz);
-
-   if (gt_freq_mhz > gt_max_freq_mhz) {
-   sysfs_write("gt_max_freq_mhz", gt_freq_mhz);
-   sysfs_write("gt_min_freq_mhz", gt_freq_mhz);
-   } else {
-   sysfs_write("gt_min_freq_mhz", gt_freq_mhz);
-   sysfs_write("gt_max_freq_mhz", gt_freq_mhz);
-   }
-   gt_min_freq_mhz = gt_freq_mhz;
-   gt_max_freq_mhz = gt_freq_mhz;
-}
-
-static void
-gt_frequency_range_restore(void)
-{
-   igt_debug("restoring GT frequency range: min = %dmhz, max =%dmhz, 
current: min=%dmhz, max=%dmhz\n",
- (int)gt_min_freq_mhz_saved,
- (int)gt_max_freq_mhz_saved,
- (int)gt_min_freq_mhz,
- (int)gt_max_freq_mhz);
-
-   /* Assume current min/max are the same */
-   if (gt_min_freq_mhz_saved > gt_max_freq_mhz) {
-   sysfs_write("gt_max_freq_mhz", gt_max_freq_mhz_saved);
-   sysfs_write("gt_min_freq_mhz", gt_min_freq_mhz_saved);
-   } else {
-   sysfs_write("gt_min_freq_mhz", gt_min_freq_mhz_saved);
-   sysfs_write("gt_max_freq_mhz", gt_max_freq_mhz_saved);
-   }
-
-   gt_min_freq_mhz = gt_min_freq_mhz_saved;
-   gt_max_freq_mhz = gt_max_freq_mhz_saved;
-}
-
 static int
 i915_read_reports_until_timestamp(enum drm_i915_oa_format oa_format,
  uint8_t *buf,
@@ -1632,33 +1571,9 @@ test_oa_formats(void)
 }
 
 static void
-test_oa_exponents(int gt_freq_mhz)
+test_oa_exponents(void)
 {
-   uint32_t freq_margin;
-
-   /* This test tries to use the sysfs interface for pinning the GT
-* frequency so we have another point of reference for comparing with
-* the clock frequency as derived from OA reports.
-*
-* This test has been finicky to stabilise while the
-* gt_min/max_freq_mhz files in sysfs don't seem to be a reliable
-* mechanism for fixing the gpu frequency.
-*
-* Since these unit tests are focused on the OA unit not the ability to
-* pin the frequency via sysfs we make the test account for pinning not
-* being reliable and read back the current frequency for each
-* iteration of this test to take this into account.
-*/
-   gt_frequency_pin(gt_freq_mhz);
-
-   igt_debug("Testing OA timer exponents with requested GT frequency = 
%dmhz\n",
- gt_freq_mhz);
-
-   /* allow a +- 10% error margin when checking that the frequency
-* calculated from the OA reports matches the frequency according to
-* sysfs.
-*/
-   freq_margin = gt_freq_mhz * 0.1;
+   igt_debug("Testing OA timer exponents\n");
 
/* It's asking a lot to sample with a 160 nanosecond period and the
 * test can fail due to buffer overflows if it wasn't possible to
@@ -1673,7 +1588,6 @@ test_oa_exponents(int gt_freq_mhz)
uint32_t clock_delta;
uint32_t freq;
int n_tested = 0;
-   int n_freq_matches = 0;
 
/* The exponent is effectively selecting a bit in the timestamp
 * to trigger 

[Intel-gfx] [PATCH i-g-t v5 01/11] tests/perf: make stream_fd a global variable

[Lionel Landwerlin]

When debugging unstable tests on new platforms we currently we don't
cleanup everything well in between different tests. Since only a
single OA stream fd can be opened at a time, having the stream_fd as a
global variable helps us cleanup the state between tests.

Signed-off-by: Lionel Landwerlin 
---
 tests/perf.c | 121 ---
 1 file changed, 65 insertions(+), 56 deletions(-)

diff --git a/tests/perf.c b/tests/perf.c
index a82a3da3..f89a235e 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -285,6 +285,7 @@ static bool hsw_undefined_a_counters[45] = {
 static bool gen8_undefined_a_counters[45];
 
 static int drm_fd = -1;
+static int stream_fd = -1;
 static uint32_t devid;
 static int card = -1;
 static int n_eus;
@@ -306,10 +307,22 @@ static uint32_t (*read_report_ticks)(uint32_t *report,
 static void (*sanity_check_reports)(uint32_t *oa_report0, uint32_t *oa_report1,
enum drm_i915_oa_format format);
 
+static void
+__perf_close(int fd)
+{
+   close(fd);
+   stream_fd = -1;
+}
+
 static int
 __perf_open(int fd, struct drm_i915_perf_open_param *param)
 {
-   int ret = igt_ioctl(fd, DRM_IOCTL_I915_PERF_OPEN, param);
+   int ret;
+
+   if (stream_fd >= 0)
+   __perf_close(stream_fd);
+
+   ret = igt_ioctl(fd, DRM_IOCTL_I915_PERF_OPEN, param);
 
igt_assert(ret >= 0);
errno = 0;
@@ -978,14 +991,12 @@ test_system_wide_paranoid(void)
.num_properties = sizeof(properties) / 16,
.properties_ptr = to_user_pointer(properties),
};
-   int stream_fd;
-
write_u64_file("/proc/sys/dev/i915/perf_stream_paranoid", 0);
 
igt_drop_root();
 
stream_fd = __perf_open(drm_fd, );
-   close(stream_fd);
+   __perf_close(stream_fd);
}
 
igt_waitchildren();
@@ -1033,7 +1044,6 @@ test_invalid_oa_metric_set_id(void)
.num_properties = sizeof(properties) / 16,
.properties_ptr = to_user_pointer(properties),
};
-   int stream_fd;
 
do_ioctl_err(drm_fd, DRM_IOCTL_I915_PERF_OPEN, , EINVAL);
 
@@ -1043,7 +1053,7 @@ test_invalid_oa_metric_set_id(void)
/* Check that we aren't just seeing false positives... */
properties[ARRAY_SIZE(properties) - 1] = test_metric_set_id;
stream_fd = __perf_open(drm_fd, );
-   close(stream_fd);
+   __perf_close(stream_fd);
 
/* There's no valid default OA metric set ID... */
param.num_properties--;
@@ -1068,7 +1078,6 @@ test_invalid_oa_format_id(void)
.num_properties = sizeof(properties) / 16,
.properties_ptr = to_user_pointer(properties),
};
-   int stream_fd;
 
do_ioctl_err(drm_fd, DRM_IOCTL_I915_PERF_OPEN, , EINVAL);
 
@@ -1078,7 +1087,7 @@ test_invalid_oa_format_id(void)
/* Check that we aren't just seeing false positives... */
properties[ARRAY_SIZE(properties) - 1] = test_oa_format;
stream_fd = __perf_open(drm_fd, );
-   close(stream_fd);
+   __perf_close(stream_fd);
 
/* There's no valid default OA format... */
param.num_properties--;
@@ -1106,8 +1115,7 @@ test_missing_sample_flags(void)
 }
 
 static void
-read_2_oa_reports(int stream_fd,
- int format_id,
+read_2_oa_reports(int format_id,
  int exponent,
  uint32_t *oa_report0,
  uint32_t *oa_report1,
@@ -1241,12 +1249,13 @@ open_and_read_2_oa_reports(int format_id,
.num_properties = sizeof(properties) / 16,
.properties_ptr = to_user_pointer(properties),
};
-   int stream_fd = __perf_open(drm_fd, );
 
-   read_2_oa_reports(stream_fd, format_id, exponent,
+   stream_fd = __perf_open(drm_fd, );
+
+   read_2_oa_reports(format_id, exponent,
  oa_report0, oa_report1, timer_only);
 
-   close(stream_fd);
+   __perf_close(stream_fd);
 }
 
 static void
@@ -1546,9 +1555,10 @@ test_invalid_oa_exponent(void)
.num_properties = sizeof(properties) / 16,
.properties_ptr = to_user_pointer(properties),
};
-   int stream_fd = __perf_open(drm_fd, );
 
-   close(stream_fd);
+   stream_fd = __perf_open(drm_fd, );
+
+   __perf_close(stream_fd);
 
for (int i = 32; i < 65; i++) {
properties[7] = i;
@@ -1598,12 +1608,10 @@ test_low_oa_exponent_permissions(void)
properties[7] = ok_exponent;
 
igt_fork(child, 1) {
-   int stream_fd;
-
igt_drop_root();
 
stream_fd = __perf_open(drm_fd, );
-   close(stream_fd);
+   __perf_close(stream_fd);
}
 
igt_waitchildren();
@@ -1652,7 +1660,6 @@ test_per_context_mode_unprivileged(void)

[Intel-gfx] [PATCH i-g-t v5 04/11] tests/perf: rc6: try to guess when rc6 is disabled

[Lionel Landwerlin]

Signed-off-by: Lionel Landwerlin 
---
 tests/perf.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/tests/perf.c b/tests/perf.c
index bd139bde..5fe0a332 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -3463,6 +3463,17 @@ gen8_test_single_ctx_render_target_writes_a_counter(void)
} while (WEXITSTATUS(child_ret) == EAGAIN);
 }
 
+static bool
+rc6_enabled(void)
+{
+   char *rc6_status = read_debugfs_record(drm_fd, "i915_drpc_info",
+  "RC6 Enabled");
+   bool enabled = strcmp(rc6_status, "yes") == 0;
+
+   free(rc6_status);
+   return enabled;
+}
+
 static void
 test_rc6_disable(void)
 {
@@ -3482,6 +3493,8 @@ test_rc6_disable(void)
};
uint64_t n_events_start, n_events_end;
 
+   igt_skip_on(!rc6_enabled());
+
stream_fd = __perf_open(drm_fd, );
 
n_events_start = read_debugfs_u64_record(drm_fd, "i915_drpc_info",
-- 
2.14.1

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[Intel-gfx] [PATCH i-g-t v5 06/11] tests/perf: rework oa-exponent test

[Lionel Landwerlin]

New issues that were discovered while making the tests work on Gen8+ :

 - we need to measure timings between periodic reports and discard all
   other kind of reports

 - it seems periodicity of the reports can be affected outside of RC6
   (frequency change), we can detect this by looking at the amount of
   clock cycles per timestamp deltas

v2: Drop some unused variables (Matthew)

Signed-off-by: Lionel Landwerlin 
---
 tests/perf.c | 733 ---
 1 file changed, 599 insertions(+), 134 deletions(-)

diff --git a/tests/perf.c b/tests/perf.c
index f256bac3..15a43cf8 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -28,6 +28,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -306,6 +307,25 @@ static uint32_t (*read_report_ticks)(uint32_t *report,
 static void (*sanity_check_reports)(uint32_t *oa_report0, uint32_t *oa_report1,
enum drm_i915_oa_format format);
 
+static bool
+timestamp_delta_within(uint32_t delta,
+  uint32_t expected_delta,
+  uint32_t margin)
+{
+   return delta >= (expected_delta - margin) &&
+  delta <= (expected_delta + margin);
+}
+
+static bool
+double_value_within(double value,
+   double expected,
+   double percent_margin)
+{
+   return value >= (expected - expected * percent_margin / 100.0) &&
+  value <= (expected + expected * percent_margin / 100.0);
+
+}
+
 static void
 __perf_close(int fd)
 {
@@ -472,6 +492,20 @@ gen8_read_report_ticks(uint32_t *report, enum 
drm_i915_oa_format format)
return report[3];
 }
 
+static void
+gen8_read_report_clock_ratios(uint32_t *report,
+ uint32_t *slice_freq_mhz,
+ uint32_t *unslice_freq_mhz)
+{
+   uint32_t unslice_freq = report[0] & 0x1ff;
+   uint32_t slice_freq_low = (report[0] >> 25) & 0x7f;
+   uint32_t slice_freq_high = (report[0] >> 9) & 0x3;
+   uint32_t slice_freq = slice_freq_low | (slice_freq_high << 7);
+
+   *slice_freq_mhz = (slice_freq * 1) / 1000;
+   *unslice_freq_mhz = (unslice_freq * 1) / 1000;
+}
+
 static const char *
 gen8_read_report_reason(const uint32_t *report)
 {
@@ -494,29 +528,6 @@ gen8_read_report_reason(const uint32_t *report)
return "unknown";
 }
 
-static bool
-oa_report_is_periodic(uint32_t oa_exponent, const uint32_t *report)
-{
-   if (IS_HASWELL(devid)) {
-   /* For Haswell we don't have a documented report reason field
-* (though empirically report[0] bit 10 does seem to correlate
-* with a timer trigger reason) so we instead infer which
-* reports are timer triggered by checking if the least
-* significant bits are zero and the exponent bit is set.
-*/
-   uint32_t oa_exponent_mask = (1 << (oa_exponent + 1)) - 1;
-
-   if ((report[1] & oa_exponent_mask) != (1 << oa_exponent))
-   return true;
-   } else {
-   if ((report[0] >> OAREPORT_REASON_SHIFT) &
-   OAREPORT_REASON_TIMER)
-   return true;
-   }
-
-   return false;
-}
-
 static uint64_t
 timebase_scale(uint32_t u32_delta)
 {
@@ -563,6 +574,29 @@ oa_exponent_to_ns(int exponent)
return 10ULL * (2ULL << exponent) / timestamp_frequency;
 }
 
+static bool
+oa_report_is_periodic(uint32_t oa_exponent, const uint32_t *report)
+{
+   if (IS_HASWELL(devid)) {
+   /* For Haswell we don't have a documented report reason field
+* (though empirically report[0] bit 10 does seem to correlate
+* with a timer trigger reason) so we instead infer which
+* reports are timer triggered by checking if the least
+* significant bits are zero and the exponent bit is set.
+*/
+   uint32_t oa_exponent_mask = (1 << (oa_exponent + 1)) - 1;
+
+   if ((report[1] & oa_exponent_mask) == (1 << oa_exponent))
+   return true;
+   } else {
+   if ((report[0] >> OAREPORT_REASON_SHIFT) &
+   OAREPORT_REASON_TIMER)
+   return true;
+   }
+
+   return false;
+}
+
 static bool
 oa_report_ctx_is_valid(uint32_t *report)
 {
@@ -578,6 +612,128 @@ oa_report_ctx_is_valid(uint32_t *report)
igt_assert(!"reached");
 }
 
+static uint32_t
+oa_report_get_ctx_id(uint32_t *report)
+{
+   if (!oa_report_ctx_is_valid(report))
+   return 0x;
+   return report[2];
+}
+
+static double
+oa_reports_tick_per_period(uint32_t *report0, uint32_t *report1)
+{
+   if (intel_gen(devid) < 8)
+   return 0.0;
+
+   /* Measure the number GPU tick delta to timestamp delta. */
+   return (double) 

[Intel-gfx] [PATCH i-g-t v5 02/11] tests/perf: add per context filtering test for gen8+

[Lionel Landwerlin]

From: Robert Bragg 

Signed-off-by: Robert Bragg 
Signed-off-by: Lionel Landwerlin 
---
 tests/perf.c | 777 ---
 1 file changed, 745 insertions(+), 32 deletions(-)

diff --git a/tests/perf.c b/tests/perf.c
index f89a235e..8644e252 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -48,7 +48,9 @@ IGT_TEST_DESCRIPTION("Test the i915 perf metrics streaming 
interface");
 #define OAREPORT_REASON_MASK   0x3f
 #define OAREPORT_REASON_SHIFT  19
 #define OAREPORT_REASON_TIMER  (1<<0)
+#define OAREPORT_REASON_INTERNAL   (3<<1)
 #define OAREPORT_REASON_CTX_SWITCH (1<<3)
+#define OAREPORT_REASON_GO (1<<4)
 #define OAREPORT_REASON_CLK_RATIO  (1<<5)
 
 #define GFX_OP_PIPE_CONTROL ((3 << 29) | (3 << 27) | (2 << 24))
@@ -574,6 +576,22 @@ oa_exponent_to_ns(int exponent)
return 10ULL * (2ULL << exponent) / timestamp_frequency;
 }
 
+static bool
+oa_report_ctx_is_valid(uint32_t *report)
+{
+   if (IS_HASWELL(devid)) {
+   return false; /* TODO */
+   } else if (IS_GEN8(devid)) {
+   return report[0] & (1ul << 25);
+   } else if (IS_GEN9(devid)) {
+   return report[0] & (1ul << 16);
+   }
+
+   /* Need to update this function for newer Gen. */
+   igt_assert(!"reached");
+}
+
+
 static void
 hsw_sanity_check_render_basic_reports(uint32_t *oa_report0, uint32_t 
*oa_report1,
  enum drm_i915_oa_format fmt)
@@ -678,6 +696,100 @@ gen8_40bit_a_delta(uint64_t value0, uint64_t value1)
return value1 - value0;
 }
 
+static void
+accumulate_uint32(size_t offset,
+ uint32_t *report0,
+  uint32_t *report1,
+  uint64_t *delta)
+{
+   uint32_t value0 = *(uint32_t *)(((uint8_t *)report0) + offset);
+   uint32_t value1 = *(uint32_t *)(((uint8_t *)report1) + offset);
+
+   *delta += (uint32_t)(value1 - value0);
+}
+
+static void
+accumulate_uint40(int a_index,
+  uint32_t *report0,
+  uint32_t *report1,
+ enum drm_i915_oa_format format,
+  uint64_t *delta)
+{
+   uint64_t value0 = gen8_read_40bit_a_counter(report0, format, a_index),
+value1 = gen8_read_40bit_a_counter(report1, format, a_index);
+
+   *delta += gen8_40bit_a_delta(value0, value1);
+}
+
+static void
+accumulate_reports(struct accumulator *accumulator,
+  uint32_t *start,
+  uint32_t *end)
+{
+   enum drm_i915_oa_format format = accumulator->format;
+   uint64_t *deltas = accumulator->deltas;
+   int idx = 0;
+
+   if (intel_gen(devid) >= 8) {
+   /* timestamp */
+   accumulate_uint32(4, start, end, deltas + idx++);
+
+   /* clock cycles */
+   accumulate_uint32(12, start, end, deltas + idx++);
+   } else {
+   /* timestamp */
+   accumulate_uint32(4, start, end, deltas + idx++);
+   }
+
+   for (int i = 0; i < oa_formats[format].n_a40; i++)
+   accumulate_uint40(i, start, end, format, deltas + idx++);
+
+   for (int i = 0; i < oa_formats[format].n_a; i++) {
+   accumulate_uint32(oa_formats[format].a_off + 4 * i,
+ start, end, deltas + idx++);
+   }
+
+   for (int i = 0; i < oa_formats[format].n_b; i++) {
+   accumulate_uint32(oa_formats[format].b_off + 4 * i,
+ start, end, deltas + idx++);
+   }
+
+   for (int i = 0; i < oa_formats[format].n_c; i++) {
+   accumulate_uint32(oa_formats[format].c_off + 4 * i,
+ start, end, deltas + idx++);
+   }
+}
+
+static void
+accumulator_print(struct accumulator *accumulator, const char *title)
+{
+   enum drm_i915_oa_format format = accumulator->format;
+   uint64_t *deltas = accumulator->deltas;
+   int idx = 0;
+
+   igt_debug("%s:\n", title);
+   if (intel_gen(devid) >= 8) {
+   igt_debug("\ttime delta = %lu\n", deltas[idx++]);
+   igt_debug("\tclock cycle delta = %lu\n", deltas[idx++]);
+
+   for (int i = 0; i < oa_formats[format].n_a40; i++)
+   igt_debug("\tA%u = %lu\n", i, deltas[idx++]);
+   } else {
+   igt_debug("\ttime delta = %lu\n", deltas[idx++]);
+   }
+
+   for (int i = 0; i < oa_formats[format].n_a; i++) {
+   int a_id = oa_formats[format].first_a + i;
+   igt_debug("\tA%u = %lu\n", a_id, deltas[idx++]);
+   }
+
+   for (int i = 0; i < oa_formats[format].n_a; i++)
+   igt_debug("\tB%u = %lu\n", i, deltas[idx++]);
+
+   for (int i = 0; i < oa_formats[format].n_c; i++)
+   igt_debug("\tC%u = %lu\n", i, deltas[idx++]);
+}
+
 /* 

[Intel-gfx] [PATCH i-g-t v5 03/11] tests/perf: update max buffer size for reading reports

[Lionel Landwerlin]

Signed-off-by: Lionel Landwerlin 
---
 tests/perf.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/tests/perf.c b/tests/perf.c
index 8644e252..bd139bde 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -1298,9 +1298,7 @@ read_2_oa_reports(int format_id,
/* Note: we allocate a large buffer so that each read() iteration
 * should scrape *all* pending records.
 *
-* The largest buffer the OA unit supports is 16MB and the smallest
-* OA report format is 64bytes allowing up to 262144 reports to
-* be buffered.
+* The largest buffer the OA unit supports is 16MB.
 *
 * Being sure we are fetching all buffered reports allows us to
 * potentially throw away / skip all reports whenever we see
@@ -1313,7 +1311,8 @@ read_2_oa_reports(int format_id,
 * to indicate that the OA unit may be over taxed if lots of reports
 * are being lost.
 */
-   int buf_size = 262144 * (64 + sizeof(struct 
drm_i915_perf_record_header));
+   int max_reports = (16 * 1024 * 1024) / format_size;
+   int buf_size = sample_size * max_reports * 1.5;
uint8_t *buf = malloc(buf_size);
int n = 0;
 
@@ -1325,6 +1324,7 @@ read_2_oa_reports(int format_id,
;
 
igt_assert(len > 0);
+   igt_debug("read %d bytes\n", (int)len);
 
for (size_t offset = 0; offset < len; offset += header->size) {
const uint32_t *report;
-- 
2.14.1

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[Intel-gfx] [PATCH i-g-t v5 00/11] Improve robustness of the i915 perf tests

[Lionel Landwerlin]

Hi,

I pushed the couple of patches that I could and that had a Rb by
Matthew (Kabylake/Geminilake support). Here is pretty much the same
series as v4 only adding Coffeelake support.

Cheers,

Lionel Landwerlin (10):
  tests/perf: make stream_fd a global variable
  tests/perf: update max buffer size for reading reports
  tests/perf: rc6: try to guess when rc6 is disabled
  tests/perf: remove frequency related changes
  tests/perf: rework oa-exponent test
  tests/perf: make enable-disable more reliable
  tests/perf: make buffer-fill more reliable
  tests/perf: estimate number of blocking/polling based on time spent
  tests/perf: prevent power management to kick in when necessary
  tests/perf: add support for Coffeelake

Robert Bragg (1):
  tests/perf: add per context filtering test for gen8+

 tests/perf.c | 2020 +++---
 1 file changed, 1656 insertions(+), 364 deletions(-)

--
2.14.1
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