[Intel-gfx] [GVT-g] [ANNOUNCE] 2017-Q3 release of XenGT (Intel GVT-g for Xen)

[Xu, Terrence]

Hi all,

We are pleased to announce an update of Intel GVT-g for Xen.

Intel GVT-g is a full GPU virtualization solution with mediated pass-through, 
starting from 4th generation Intel Core(TM) processors with Intel processor 
graphics. A virtual GPU instance is maintained for each VM, with part of 
performance critical resources directly assigned. The capability of running 
native graphics driver inside a VM, without hypervisor intervention in 
performance critical paths, achieves a good balance among performance, feature, 
and sharing capability. GVT-g for Xen hypervisor is XenGT.


Repositories
-    Xen :  https://github.com/01org/igvtg-xen (tag: 2017-q3-xengt-stable-4.9)
-    Kernel: https://github.com/01org/gvt-linux/ (tag: 2017-q3-gvt-stable-4.12)
-    Qemu: https://github.com/01org/igvtg-qemu (tag: 2017-q3-stable-2.9.0)


This update consists of:
-    Kernel version upgraded to 4.12 from 4.11.
-    Live migration feature preliminary supported.
-    QoS feature preliminary supported.
-    IOMMU feature supported.
-    OVMF feature supported.
-    VGPU reset feature optimization, with related issues be fixed.
-    Supported server platforms: Intel(r) Xeon(r) E3_v4, E3_v5 and E3_v6 with 
Intel Graphics processor, E3_v6 is new supported platform.
-    Supported client platforms: Intel(r) Core(tm) 5th generation (code name: 
Broadwell), 6th generation (code name: Skylake) and 7th generation (code name: 
Kabylake), 7th generation is new supported platform.
-    Validated Guest OS: Windows7 32bit, Window7 64bit, Windows8.1 64bit, 
Windows10 64bit and Linux.
-    GVT-g only supports remote display not local display by this release. 
-    Remote protocol: only guest-side remoting protocol is supported, host-side 
remoting connection like SPICE is working in progress. For example, user can 
use X11VNC for Guest Linux VM or TightVNC for Guest Windows VM.


Limitation or known issues:
-    GVT-g can support maximum 7 Guest VMs due to host graphics resource 
limitation. When user runs 7 VMs simultaneously, host OS can only run in text 
mode.
-    In order to support Guest Windows7 32bit VM, user is recommended to 
configure vgt_low_gm_sz=128 / 256 / 512 in HVM file because Guest Windows7 
32bit VM needs more graphics resource than other Guest VM.
-    In order to support Guest VM high resolution and screen resolution 
adjustable in Guest Windows8.1 64bit VM and Guest Windows10 64bit VM, user is 
recommended to configure vgt_low_gm_sz=64 / 128 / 256 / 512 in HVM file to get 
larger VM aperture size.
-    Some 3rd party applications/tools like 3DMark which including special 
DirectX12 feature test ,it will trigger Guest VM GPU reset.
-    In corner case, Guest Windows 7 32bit VM may be killed automatically by 
Xen when Guest VM runs into TDR. This issues happens only on Broadwell 
platform. The workaround is to disable part of viridian feature in Guest VM hvm 
file by adding viridian=["all", "!apic_assist"].
-    In corner case, Linux Guest VM may GPU hang while running special 
Intel-GPU-Tools test case on it.
-    For live migration feature, we cannot migrate Guest Windows VM when Guest 
VM memory is 2048M or 4096M, user is recommended to configure Guest VM memory 
to 1024MB.


Setup guide:
https://github.com/01org/gvt-linux/wiki/GVTg_Setup_Guide


This is the first GVT-g community release based on new Upstream architecture 
design, refer to the following document for new architecture introduction:
https://01.org/igvt-g/documentation/intel-gvt-g-new-architecture-introduction


Please subscribe to join the mailing list if you want to learn more about GVT-g 
project: 
https://lists.01.org/mailman/listinfo/igvt-g
Please subscribe to join the mailing list if you want to contribute/review 
latest GVT-g upstream patches:
https://lists.freedesktop.org/mailman/listinfo/intel-gvt-dev


Official GVT-g portal: 
https://01.org/igvt-g


More information about background, architecture and others about Intel GVT-g, 
can be found at:
https://01.org/igvt-g
https://www.usenix.org/conference/atc14/technical-sessions/presentation/tian
http://events.linuxfoundation.org/sites/events/files/slides/XenGT-Xen%20Summit-v7_0.pdf
http://events.linuxfoundation.org/sites/events/files/slides/XenGT-Xen%20Summit-REWRITE%203RD%20v4.pdf
https://01.org/xen/blogs/srclarkx/2013/graphics-virtualization-xengt


Note: 
The XenGT project should be considered a work in progress. As such it is not a 
complete product nor should it be considered one. Extra care should be taken 
when testing and configuring a system to use the XenGT project.



Thanks
Terrence
Tel: +86-21-6116 5390
MP: +86-1356 4367 024
Mail: terrence...@intel.com

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[Intel-gfx] ✗ Fi.CI.IGT: failure for igt/syncobj_wait: Avoid early close of timeline in test_wait_snapshot

[Patchwork]

== Series Details ==

Series: igt/syncobj_wait: Avoid early close of timeline in test_wait_snapshot
URL   : https://patchwork.freedesktop.org/series/31678/
State : failure

== Summary ==

Test syncobj_wait:
Subgroup wait-for-submit-snapshot:
fail   -> PASS   (shard-hsw) fdo#103188 +1
Test gem_eio:
Subgroup in-flight-contexts:
pass   -> DMESG-WARN (shard-hsw) fdo#102886 +2
Test drv_module_reload:
Subgroup basic-reload-inject:
pass   -> DMESG-WARN (shard-hsw) fdo#102707
Test kms_chv_cursor_fail:
Subgroup pipe-C-64x64-left-edge:
pass   -> SKIP   (shard-hsw)
Test kms_busy:
Subgroup extended-pageflip-hang-newfb-render-A:
pass   -> SKIP   (shard-hsw)
Test gem_exec_store:
Subgroup pages-default:
pass   -> FAIL   (shard-hsw)
Test kms_flip:
Subgroup flip-vs-absolute-wf_vblank-interruptible:
fail   -> PASS   (shard-hsw) fdo#100368
Subgroup flip-vs-rmfb-interruptible:
pass   -> DMESG-WARN (shard-hsw) fdo#102614

fdo#103188 https://bugs.freedesktop.org/show_bug.cgi?id=103188
fdo#102886 https://bugs.freedesktop.org/show_bug.cgi?id=102886
fdo#102707 https://bugs.freedesktop.org/show_bug.cgi?id=102707
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614

shard-hswtotal:2552 pass:1427 dwarn:8   dfail:0   fail:12  skip:1105 
time:9569s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_318/shards.html
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] tests/syncobj_wait: Replace open-coded calls to __syncobj_wait()

[Patchwork]

== Series Details ==

Series: series starting with [1/2] tests/syncobj_wait: Replace open-coded calls 
to __syncobj_wait()
URL   : https://patchwork.freedesktop.org/series/31672/
State : success

== Summary ==

Test syncobj_wait:
Subgroup wait-any-interrupted:
fail   -> PASS   (shard-hsw) fdo#103187 +1
Test drv_module_reload:
Subgroup basic-reload:
pass   -> DMESG-WARN (shard-hsw) fdo#102707
Test gem_eio:
Subgroup wait:
pass   -> DMESG-WARN (shard-hsw) fdo#102886 +3
Test kms_flip:
Subgroup flip-vs-absolute-wf_vblank-interruptible:
fail   -> PASS   (shard-hsw) fdo#100368
Test kms_vblank:
Subgroup accuracy-idle:
pass   -> FAIL   (shard-hsw) fdo#102583
Test gem_flink_race:
Subgroup flink_close:
pass   -> FAIL   (shard-hsw) fdo#102655

fdo#103187 https://bugs.freedesktop.org/show_bug.cgi?id=103187
fdo#102707 https://bugs.freedesktop.org/show_bug.cgi?id=102707
fdo#102886 https://bugs.freedesktop.org/show_bug.cgi?id=102886
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102583 https://bugs.freedesktop.org/show_bug.cgi?id=102583
fdo#102655 https://bugs.freedesktop.org/show_bug.cgi?id=102655

shard-hswtotal:2552 pass:1430 dwarn:6   dfail:0   fail:13  skip:1103 
time:9676s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_317/shards.html
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[Intel-gfx] [GVT-g] [ANNOUNCE] 2017-Q3 release of KVMGT (Intel GVT-g for KVM)

[Xu, Terrence]

Hi all,

We are pleased to announce an update of Intel GVT-g for KVM.

Intel GVT-g for KVM (a.k.a. KVMGT) is a full GPU virtualization solution with 
mediated pass-through, starting from 5th generation Intel Core(TM) processors 
with Intel processor graphics.  A virtual GPU instance is maintained for each 
VM, with part of performance critical resources directly assigned. The 
capability of running native graphics driver inside a VM, without hypervisor 
intervention in performance critical paths, achieves a good balance among 
performance, feature, and sharing capability.
    

Repositories:
-    Kernel: https://github.com/01org/gvt-linux/  (tag: 2017-q3-gvt-stable-4.12)
-    Qemu: https://github.com/01org/igvtg-qemu  (tag: 2017-q3-stable-2.9.0)


This update consists of:
-    Kernel version upgraded to 4.12 from 4.11.
-    Live migration feature preliminary supported.
-    QoS feature preliminary supported.
-    IOMMU feature supported.
-    OVMF feature supported.
-    VGPU reset feature optimization, with related issues be fixed.
-    Supported server platforms: Intel(r) Xeon(r) E3_v4, E3_v5 and E3_v6 with 
Intel Graphics processor, the E3_v6 is new supported platform.
-    Supported client platforms: Intel(r) Core(tm) 5th generation (code name: 
Broadwell), 6th generation (code name: Skylake) and 7th generation (code name: 
Kabylake), the 7th generation is new supported platform.
-    Validated Guest OS: Windows7 32bit, Window7 64bit, Windows8.1 64bit, 
Windows10 64bit and Linux.
-    GVT-g only supports remote display not local display by this release. 
-    Remote protocol: only guest-side remoting protocol is supported, host-side 
remoting connection like SPICE is working in progress. For example, user can 
use X11VNC for Guest Linux VM or TightVNC for Guest Windows VM.


Limitation or known issues:
-    GVT-g can support maximum 7 Guest VMs due to host graphics resource 
limitation. When user runs 7 VMs simultaneously, host OS can only run in text 
mode.
-    In order to support Guest Windows7 32bit VM, user can only uses vGPU 
type1, type2, type4 not type8 because Guest Windows7 32bit VM needs more 
graphics resource than other Guest VM.
-    Some 3rd party applications/tools like GPU_Z, Passmark 9.0 may read/write 
GPU MSR directly, it will trigger Guest VM BSOD since those MSRs are unhandled 
registers in KVMGT. The workaround is to set MSR read /write ignore flag to 1 
in host grub file by adding "kvm.ignore_msrs=1".
-    Some 3rd party applications/tools like 3DMark which including special 
DirectX12 feature test ,it will trigger Guest VM GPU reset.
-    In corner case, Linux Guest VM may GPU hang while running special 
Intel-GPU-Tools test case on it.
-    In corner case, for live migration feature, the fake GPU reset happening 
while migrating Linux Guest VM which Guest VM running 3D workload.  
-    Guest Windows VM often GPU hang while the IOMMU feature enabled. This 
issues happens only on a few Broadwell platforms due to the hardware problem. 
The workaround is to turn off the integrated graphics engine on IOMMU in hot 
grub file by adding "intel_iommu=igfx_off".


Setup guide:
https://github.com/01org/gvt-linux/wiki/GVTg_Setup_Guide


This is the first GVT-g community release based on new Upstream architecture 
design, refer to the following document for new architecture introduction:
https://01.org/igvt-g/documentation/intel-gvt-g-new-architecture-introduction 


Please subscribe to join the mailing list if you want to learn more about GVT-g 
project: 
https://lists.01.org/mailman/listinfo/igvt-g
Please subscribe to join the mailing list if you want to contribute/review 
latest GVT-g upstream patches:
https://lists.freedesktop.org/mailman/listinfo/intel-gvt-dev


Official GVT-g portal:
https://01.org/igvt-g


More information about background, architecture and others about Intel GVT-g, 
can be found at:
http://www.linux-kvm.org/images/f/f3/01x08b-KVMGT-a.pdf
https://www.usenix.org/conference/atc14/technical-sessions/presentation/tian


Note:
The KVMGT project should be considered a work in progress. As such it is not a 
complete product nor should it be considered one. Extra care should be taken 
when testing and configuring a system to use the KVMGT project.



Thanks
Terrence
Tel: +86-21-6116 5390
MP: +86-1356 4367 024
Mail: terrence...@intel.com

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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] tests/kms_setmode: Request the intiial vbl count with RELATIVE instead of ABSOLUTE

[Patchwork]

== Series Details ==

Series: series starting with [1/2] tests/kms_setmode: Request the intiial vbl 
count with RELATIVE instead of ABSOLUTE
URL   : https://patchwork.freedesktop.org/series/31600/
State : success

== Summary ==

Test kms_frontbuffer_tracking:
Subgroup fbc-1p-primscrn-cur-indfb-draw-render:
dmesg-warn -> PASS   (shard-hsw) fdo#102886 +3
Test kms_flip:
Subgroup flip-vs-absolute-wf_vblank-interruptible:
fail   -> PASS   (shard-hsw) fdo#100368
Test kms_setmode:
Subgroup basic:
fail   -> PASS   (shard-hsw) fdo#99912

fdo#102886 https://bugs.freedesktop.org/show_bug.cgi?id=102886
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912

shard-hswtotal:2552 pass:1432 dwarn:5   dfail:0   fail:12  skip:1103 
time:9622s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_316/shards.html
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Re: [Intel-gfx] [PATCH v15 4/7] drm/i915/gvt: Add opregion support

[Du, Changbin]

On Tue, Oct 10, 2017 at 05:50:04PM +0800, Tina Zhang wrote:
> Windows guest driver needs vbt in opregion, to configure the setting
> for display. Without opregion support, the display registers won't
> be set and this blocks display model to get the correct information
> of the guest display plane.
> 
> This patch is to provide a virtual opregion for guest. Current
> implementation is to fill the virtual opregion with the content in
> host's opregion. The original author of this patch is Xiaoguang Chen.
> 
> Signed-off-by: Bing Niu 
> Signed-off-by: Tina Zhang 
> ---
>  drivers/gpu/drm/i915/gvt/hypercall.h |   1 +
>  drivers/gpu/drm/i915/gvt/kvmgt.c | 109 
> ++-
>  drivers/gpu/drm/i915/gvt/mpt.h   |  15 +
>  drivers/gpu/drm/i915/gvt/opregion.c  |  26 +++--
>  drivers/gpu/drm/i915/gvt/vgpu.c  |   4 ++
>  5 files changed, 146 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/hypercall.h 
> b/drivers/gpu/drm/i915/gvt/hypercall.h
> index df7f33a..32c345c 100644
> --- a/drivers/gpu/drm/i915/gvt/hypercall.h
> +++ b/drivers/gpu/drm/i915/gvt/hypercall.h
> @@ -55,6 +55,7 @@ struct intel_gvt_mpt {
> unsigned long mfn, unsigned int nr, bool map);
>   int (*set_trap_area)(unsigned long handle, u64 start, u64 end,
>bool map);
> + int (*set_opregion)(void *vgpu);
Seems we try to hide struct intel_vgpu for kvmgt, but acctually kvmgt already
use it. So set type as struct intel_vgpu directly? I am not sure about xengt,
but the code shows that 'handle' is correct thing?

>  };
>  
>  extern struct intel_gvt_mpt xengt_mpt;
> diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c 
> b/drivers/gpu/drm/i915/gvt/kvmgt.c
> index fd0c85f..6b0a330 100644
> --- a/drivers/gpu/drm/i915/gvt/kvmgt.c
> +++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
> @@ -53,11 +53,23 @@ static const struct intel_gvt_ops *intel_gvt_ops;
>  #define VFIO_PCI_INDEX_TO_OFFSET(index) ((u64)(index) << 
> VFIO_PCI_OFFSET_SHIFT)
>  #define VFIO_PCI_OFFSET_MASK(((u64)(1) << VFIO_PCI_OFFSET_SHIFT) - 1)
>  
> +#define OPREGION_SIGNATURE "IntelGraphicsMem"
> +
> +struct vfio_region;
> +struct intel_vgpu_regops {
> + size_t (*rw)(struct intel_vgpu *vgpu, char *buf,
> + size_t count, loff_t *ppos, bool iswrite);
> + void (*release)(struct intel_vgpu *vgpu,
> + struct vfio_region *region);
> +};
> +
>  struct vfio_region {
>   u32 type;
>   u32 subtype;
>   size_t  size;
>   u32 flags;
> + const struct intel_vgpu_regops  *ops;
> + void*data;
>  };
>  
>  struct kvmgt_pgfn {
> @@ -430,6 +442,91 @@ static void kvmgt_protect_table_del(struct 
> kvmgt_guest_info *info,
>   }
>  }
>  
> +static size_t intel_vgpu_reg_rw_opregion(struct intel_vgpu *vgpu, char *buf,
> + size_t count, loff_t *ppos, bool iswrite)
Personally I think intel_vgpu_rw_opregion() is better. :)

> +{
> + unsigned int i = VFIO_PCI_OFFSET_TO_INDEX(*ppos) -
> + VFIO_PCI_NUM_REGIONS;
> + void *base = vgpu->vdev.region[i].data;
> + loff_t pos = *ppos & VFIO_PCI_OFFSET_MASK;
> +
> + if (pos >= vgpu->vdev.region[i].size || iswrite) {
> + gvt_vgpu_err("invalid op or offset for Intel vgpu OpRegion\n");
> + return -EINVAL;
> + }
> + count = min(count, (size_t)(vgpu->vdev.region[i].size - pos));
> + memcpy(buf, base + pos, count);
> +
> + return count;
> +}
> +
> +static void intel_vgpu_reg_release_opregion(struct intel_vgpu *vgpu,
> + struct vfio_region *region)
> +{
> + memunmap(region->data);
> +}
> +
> +static const struct intel_vgpu_regops intel_vgpu_regops_opregion = {
> + .rw = intel_vgpu_reg_rw_opregion,
> + .release = intel_vgpu_reg_release_opregion,
> +};
> +
> +static int intel_vgpu_register_reg(struct intel_vgpu *vgpu,
Maybe full name xx_register_region? coufusing between a register and region.

> + unsigned int type, unsigned int subtype,
> + const struct intel_vgpu_regops *ops,
> + size_t size, u32 flags, void *data)
> +{
> + struct vfio_region *region;
> +
> + region = krealloc(vgpu->vdev.region,
> + (vgpu->vdev.num_regions + 1) * sizeof(*region),
> + GFP_KERNEL);
> + if (!region)
> + return -ENOMEM;
> +
> + vgpu->vdev.region = region;
> + vgpu->vdev.region[vgpu->vdev.num_regions].type = type;
> + vgpu->vdev.region[vgpu->vdev.num_regions].subtype = subtype;
> + vgpu->vdev.region[vgpu->vdev.num_regions].ops = ops;
> + vgpu->vdev.region[vgpu->vdev.num_regions].size = size;
> + vgpu->vdev.region[vgpu->vdev.num_regions].flags = flags;
> + vgpu->vdev.region[vgpu->vdev.num_regions].data = data;
> 

Re: [Intel-gfx] [PATCH v15 5/7] vfio: ABI for mdev display dma-buf operation

[Alex Williamson]

On Wed, 11 Oct 2017 01:46:37 +
"Zhang, Tina"  wrote:

> > -Original Message-
> > From: Alex Williamson [mailto:alex.william...@redhat.com]
> > Sent: Wednesday, October 11, 2017 3:17 AM
> > To: Zhang, Tina 
> > Cc: kra...@redhat.com; ch...@chris-wilson.co.uk; zhen...@linux.intel.com;
> > Lv, Zhiyuan ; Wang, Zhi A ;
> > Tian, Kevin ; dan...@ffwll.ch; kwankh...@nvidia.com;
> > intel-gfx@lists.freedesktop.org; intel-gvt-...@lists.freedesktop.org; linux-
> > ker...@vger.kernel.org; Daniel Vetter 
> > Subject: Re: [PATCH v15 5/7] vfio: ABI for mdev display dma-buf operation
> > 
> > On Tue, 10 Oct 2017 17:50:05 +0800
> > Tina Zhang  wrote:
> >   
> > > Add VFIO_DEVICE_QUERY_GFX_PLANE ioctl command to let user mode query
> > > and get the plan and its related information. This ioctl can be invoked 
> > > with:  
> > 
> > s/plan/plane/  
> Sorry about this typo :).
> 
> >   
> > > 1) either flag DMABUF or REGION is set. Vendor driver returns success
> > > and the plane_info only when the specific kind of buffer is supported.
> > > 2) flag PROBE is set with either DMABUF or REGION. Vendor driver
> > > returns success only when the specific kind of buffer is supported.
> > >
> > > The dma-buf's life cycle is handled by user mode and tracked by kernel.
> > > The returned fd in struct vfio_device_query_gfx_plane can be a new fd
> > > or an old fd of a re-exported dma-buf. Host user mode can check the
> > > value of fd and to see if it needs to create new resource according to
> > > the new fd or just use the existed resource related to the old fd.
> > >
> > > v15:
> > > - add a ioctl to get a dmabuf for a given dmabuf id. (Gerd)
> > >
> > > v14:
> > > - add PROBE, DMABUF and REGION flags. (Alex)
> > >
> > > v12:
> > > - add drm_format_mod back. (Gerd and Zhenyu)
> > > - add region_index. (Gerd)
> > >
> > > v11:
> > > - rename plane_type to drm_plane_type. (Gerd)
> > > - move fields of vfio_device_query_gfx_plane to 
> > > vfio_device_gfx_plane_info.
> > >   (Gerd)
> > > - remove drm_format_mod, start fields. (Daniel)
> > > - remove plane_id.
> > >
> > > v10:
> > > - refine the ABI API VFIO_DEVICE_QUERY_GFX_PLANE. (Alex) (Gerd)
> > >
> > > v3:
> > > - add a field gvt_plane_info in the drm_i915_gem_obj structure to save
> > >   the decoded plane information to avoid look up while need the plane
> > >   info. (Gerd)
> > >
> > > Signed-off-by: Tina Zhang 
> > > Cc: Gerd Hoffmann 
> > > Cc: Alex Williamson 
> > > Cc: Daniel Vetter 
> > > ---
> > >  include/uapi/linux/vfio.h | 62
> > > +++
> > >  1 file changed, 62 insertions(+)
> > >
> > > diff --git a/include/uapi/linux/vfio.h b/include/uapi/linux/vfio.h
> > > index ae46105..fdf9a9c 100644
> > > --- a/include/uapi/linux/vfio.h
> > > +++ b/include/uapi/linux/vfio.h
> > > @@ -502,6 +502,68 @@ struct vfio_pci_hot_reset {
> > >
> > >  #define VFIO_DEVICE_PCI_HOT_RESET_IO(VFIO_TYPE, VFIO_BASE +  
> > 13)  
> > >
> > > +/**
> > > + * VFIO_DEVICE_QUERY_GFX_PLANE - _IOW(VFIO_TYPE, VFIO_BASE + 14,
> > > + *struct vfio_device_query_gfx_plane)
> > > + *
> > > + * Set the drm_plane_type and flags, then retrieve the gfx plane info.
> > > + *
> > > + * flags supported:
> > > + * - VFIO_GFX_PLANE_TYPE_PROBE and VFIO_GFX_PLANE_TYPE_DMABUF  
> > are set  
> > > + *   to ask if the mdev supports dma-buf. 0 on support, -EINVAL on no
> > > + *   support for dma-buf.
> > > + * - VFIO_GFX_PLANE_TYPE_PROBE and VFIO_GFX_PLANE_TYPE_REGION  
> > are set  
> > > + *   to ask if the mdev supports region. 0 on support, -EINVAL on no
> > > + *   support for region.
> > > + * - VFIO_GFX_PLANE_TYPE_DMABUF or VFIO_GFX_PLANE_TYPE_REGION  
> > is set  
> > > + *   with each call to query the plane info.  
> > 
> > So dmabuf_id is effectively just a token that can be fed into GET_GFX_DMABUF
> > to get the fd.  The implementation of the token is vendor specific, but can 
> > be
> > thought of as some sort of sequence ID or generation ID (but not necessarily
> > monotonically increasing), so GET_GFX_DMABUF may fail if the previously
> > provided dmabuf_id is no longer valid.  Do I have this correct?  
> Exactly. GET_GFX_DMABUF may fail if the dmabuf_id is no longer valid. -EINVAL 
> will be
> returned in that case. 
> And dmabuf_id is invalid when:
> 1) user space has closed all dma-buf fds which are exposed with the dmabuf_id,
> 2) or the dmabuf_id isn't returned from QUERY_GFX_PLANE.
> I will add the comments. Thanks.
> 
> >   
> > > + * - Others are invalid and return -EINVAL.  
> > 
> > And I see that in patch 7/7 that i915 is checking explicitly for only these 
> > flag
> > combinations, great!
> >   
> > > + *
> > > + * Return: 0 on success, -ENODEV with all 

Re: [Intel-gfx] [PATCH v15 6/7] drm/i915: Introduce GEM proxy

[Zhang, Tina]

> -Original Message-
> From: Joonas Lahtinen [mailto:joonas.lahti...@linux.intel.com]
> Sent: Tuesday, October 10, 2017 9:02 PM
> To: Zhang, Tina ; alex.william...@redhat.com;
> kra...@redhat.com; ch...@chris-wilson.co.uk; zhen...@linux.intel.com; Lv,
> Zhiyuan ; Wang, Zhi A ; Tian,
> Kevin ; dan...@ffwll.ch; kwankh...@nvidia.com
> Cc: Daniel Vetter ; intel-gfx@lists.freedesktop.org;
> intel-gvt-...@lists.freedesktop.org; linux-ker...@vger.kernel.org
> Subject: Re: [Intel-gfx] [PATCH v15 6/7] drm/i915: Introduce GEM proxy
> 
> On Tue, 2017-10-10 at 13:58 +0300, Joonas Lahtinen wrote:
> > On Tue, 2017-10-10 at 17:50 +0800, Tina Zhang wrote:
> > > GEM proxy is a kind of GEM, whose backing physical memory is pinned
> > > and produced by guest VM and is used by host as read only. With GEM
> > > proxy, host is able to access guest physical memory through GEM
> > > object interface. As GEM proxy is such a special kind of GEM, a new
> > > flag I915_GEM_OBJECT_IS_PROXY is introduced to ban host from
> > > changing the backing storage of GEM proxy.
> > >
> > > v14:
> > > - return -ENXIO when gem proxy object is banned by ioctl.
> > >   (Chris) (Daniel)
> > >
> > > v13:
> > > - add comments to GEM proxy. (Chris)
> > > - don't ban GEM proxy in i915_gem_sw_finish_ioctl. (Chris)
> > > - check GEM proxy bar after finishing i915_gem_object_wait. (Chris)
> > > - remove GEM proxy bar in i915_gem_madvise_ioctl.
> > >
> > > v6:
> > > - add gem proxy barrier in the following ioctls. (Chris)
> > >   i915_gem_set_caching_ioctl
> > >   i915_gem_set_domain_ioctl
> > >   i915_gem_sw_finish_ioctl
> > >   i915_gem_set_tiling_ioctl
> > >   i915_gem_madvise_ioctl
> > >
> > > Signed-off-by: Tina Zhang 
> > > Cc: Daniel Vetter 
> > > Cc: Chris Wilson 
> > > Cc: Joonas Lahtinen 
> >
> > 
> >
> > > +++ b/drivers/gpu/drm/i915/i915_gem_object.h
> > > @@ -39,6 +39,7 @@ struct drm_i915_gem_object_ops {
> > > unsigned int flags;
> > >  #define I915_GEM_OBJECT_HAS_STRUCT_PAGE BIT(0)
> > >  #define I915_GEM_OBJECT_IS_SHRINKABLE   BIT(1)
> > > +#define I915_GEM_OBJECT_IS_PROXY   BIT(2)
> >
> > Please fix the indent to match. Do convert the above two lines to use
> > TAB character too.
> >
> > 
> >
> > > @@ -1690,7 +1704,7 @@ i915_gem_mmap_ioctl(struct drm_device *dev,
> void *data,
> > >*/
> > >   if (!obj->base.filp) {
> > >   i915_gem_object_put(obj);
> > > - return -EINVAL;
> > > + return -ENXIO;
> > >   }
> >
> > This still needs to be a separate patch.
> >
> > With those fixes, this is;
> >
> > Reviewed-by: Joonas Lahtinen 
> 
> Also, send the produced two patches (this and the split patch) as a standalone
> series for easier testing and merging.
Got it. Thanks.

BR,
Tina
> 
> CI seems to have hard time applying the whole series.
> 
> Regards, Joonas
> --
> Joonas Lahtinen
> Open Source Technology Center
> Intel Corporation
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Re: [Intel-gfx] [PATCH v15 5/7] vfio: ABI for mdev display dma-buf operation

[Zhang, Tina]

> -Original Message-
> From: Alex Williamson [mailto:alex.william...@redhat.com]
> Sent: Wednesday, October 11, 2017 3:17 AM
> To: Zhang, Tina 
> Cc: kra...@redhat.com; ch...@chris-wilson.co.uk; zhen...@linux.intel.com;
> Lv, Zhiyuan ; Wang, Zhi A ;
> Tian, Kevin ; dan...@ffwll.ch; kwankh...@nvidia.com;
> intel-gfx@lists.freedesktop.org; intel-gvt-...@lists.freedesktop.org; linux-
> ker...@vger.kernel.org; Daniel Vetter 
> Subject: Re: [PATCH v15 5/7] vfio: ABI for mdev display dma-buf operation
> 
> On Tue, 10 Oct 2017 17:50:05 +0800
> Tina Zhang  wrote:
> 
> > Add VFIO_DEVICE_QUERY_GFX_PLANE ioctl command to let user mode query
> > and get the plan and its related information. This ioctl can be invoked 
> > with:
> 
> s/plan/plane/
Sorry about this typo :).

> 
> > 1) either flag DMABUF or REGION is set. Vendor driver returns success
> > and the plane_info only when the specific kind of buffer is supported.
> > 2) flag PROBE is set with either DMABUF or REGION. Vendor driver
> > returns success only when the specific kind of buffer is supported.
> >
> > The dma-buf's life cycle is handled by user mode and tracked by kernel.
> > The returned fd in struct vfio_device_query_gfx_plane can be a new fd
> > or an old fd of a re-exported dma-buf. Host user mode can check the
> > value of fd and to see if it needs to create new resource according to
> > the new fd or just use the existed resource related to the old fd.
> >
> > v15:
> > - add a ioctl to get a dmabuf for a given dmabuf id. (Gerd)
> >
> > v14:
> > - add PROBE, DMABUF and REGION flags. (Alex)
> >
> > v12:
> > - add drm_format_mod back. (Gerd and Zhenyu)
> > - add region_index. (Gerd)
> >
> > v11:
> > - rename plane_type to drm_plane_type. (Gerd)
> > - move fields of vfio_device_query_gfx_plane to vfio_device_gfx_plane_info.
> >   (Gerd)
> > - remove drm_format_mod, start fields. (Daniel)
> > - remove plane_id.
> >
> > v10:
> > - refine the ABI API VFIO_DEVICE_QUERY_GFX_PLANE. (Alex) (Gerd)
> >
> > v3:
> > - add a field gvt_plane_info in the drm_i915_gem_obj structure to save
> >   the decoded plane information to avoid look up while need the plane
> >   info. (Gerd)
> >
> > Signed-off-by: Tina Zhang 
> > Cc: Gerd Hoffmann 
> > Cc: Alex Williamson 
> > Cc: Daniel Vetter 
> > ---
> >  include/uapi/linux/vfio.h | 62
> > +++
> >  1 file changed, 62 insertions(+)
> >
> > diff --git a/include/uapi/linux/vfio.h b/include/uapi/linux/vfio.h
> > index ae46105..fdf9a9c 100644
> > --- a/include/uapi/linux/vfio.h
> > +++ b/include/uapi/linux/vfio.h
> > @@ -502,6 +502,68 @@ struct vfio_pci_hot_reset {
> >
> >  #define VFIO_DEVICE_PCI_HOT_RESET  _IO(VFIO_TYPE, VFIO_BASE +
> 13)
> >
> > +/**
> > + * VFIO_DEVICE_QUERY_GFX_PLANE - _IOW(VFIO_TYPE, VFIO_BASE + 14,
> > + *struct vfio_device_query_gfx_plane)
> > + *
> > + * Set the drm_plane_type and flags, then retrieve the gfx plane info.
> > + *
> > + * flags supported:
> > + * - VFIO_GFX_PLANE_TYPE_PROBE and VFIO_GFX_PLANE_TYPE_DMABUF
> are set
> > + *   to ask if the mdev supports dma-buf. 0 on support, -EINVAL on no
> > + *   support for dma-buf.
> > + * - VFIO_GFX_PLANE_TYPE_PROBE and VFIO_GFX_PLANE_TYPE_REGION
> are set
> > + *   to ask if the mdev supports region. 0 on support, -EINVAL on no
> > + *   support for region.
> > + * - VFIO_GFX_PLANE_TYPE_DMABUF or VFIO_GFX_PLANE_TYPE_REGION
> is set
> > + *   with each call to query the plane info.
> 
> So dmabuf_id is effectively just a token that can be fed into GET_GFX_DMABUF
> to get the fd.  The implementation of the token is vendor specific, but can be
> thought of as some sort of sequence ID or generation ID (but not necessarily
> monotonically increasing), so GET_GFX_DMABUF may fail if the previously
> provided dmabuf_id is no longer valid.  Do I have this correct?
Exactly. GET_GFX_DMABUF may fail if the dmabuf_id is no longer valid. -EINVAL 
will be
returned in that case. 
And dmabuf_id is invalid when:
1) user space has closed all dma-buf fds which are exposed with the dmabuf_id,
2) or the dmabuf_id isn't returned from QUERY_GFX_PLANE.
I will add the comments. Thanks.

> 
> > + * - Others are invalid and return -EINVAL.
> 
> And I see that in patch 7/7 that i915 is checking explicitly for only these 
> flag
> combinations, great!
> 
> > + *
> > + * Return: 0 on success, -ENODEV with all out fields zero on mdev
> > + * device initialization, -errno on other failure.
> > + */
> > +struct vfio_device_gfx_plane_info {
> > +   __u32 argsz;
> > +   __u32 flags;
> > +#define VFIO_GFX_PLANE_TYPE_PROBE (1 << 0) #define
> > +VFIO_GFX_PLANE_TYPE_DMABUF (1 << 1) #define
> > +VFIO_GFX_PLANE_TYPE_REGION (1 << 2)
> > +   /* in */
> > +   __u32 drm_plane_type;  

[Intel-gfx] ✓ Fi.CI.IGT: success for IGT PMU support (rev11)

[Patchwork]

== Series Details ==

Series: IGT PMU support (rev11)
URL   : https://patchwork.freedesktop.org/series/28253/
State : success

== Summary ==

Test kms_flip:
Subgroup flip-vs-fences-interruptible:
pass   -> FAIL   (shard-hsw) fdo#102946
Test drv_module_reload:
Subgroup basic-no-display:
pass   -> DMESG-WARN (shard-hsw) fdo#102707
Test gem_eio:
Subgroup in-flight-contexts:
pass   -> DMESG-WARN (shard-hsw) fdo#102886 +2
Test gem_flink_race:
Subgroup flink_close:
pass   -> FAIL   (shard-hsw) fdo#102655

fdo#102946 https://bugs.freedesktop.org/show_bug.cgi?id=102946
fdo#102707 https://bugs.freedesktop.org/show_bug.cgi?id=102707
fdo#102886 https://bugs.freedesktop.org/show_bug.cgi?id=102886
fdo#102655 https://bugs.freedesktop.org/show_bug.cgi?id=102655

shard-hswtotal:2634 pass:1427 dwarn:7   dfail:0   fail:15  skip:1185 
time:9631s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_314/shards.html
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[Intel-gfx] ✗ Fi.CI.IGT: warning for tests: Drop gem_bad_length as redundant

[Patchwork]

== Series Details ==

Series: tests: Drop gem_bad_length as redundant
URL   : https://patchwork.freedesktop.org/series/31655/
State : warning

== Summary ==

Test gem_eio:
Subgroup wait:
pass   -> DMESG-WARN (shard-hsw) fdo#102886 +4
Test kms_universal_plane:
Subgroup cursor-fb-leak-pipe-A:
pass   -> SKIP   (shard-hsw)
Test kms_flip:
Subgroup modeset-vs-vblank-race:
pass   -> FAIL   (shard-hsw) fdo#102919
Test kms_plane:
Subgroup plane-position-hole-pipe-C-planes:
pass   -> DMESG-WARN (shard-hsw)

fdo#102886 https://bugs.freedesktop.org/show_bug.cgi?id=102886
fdo#102919 https://bugs.freedesktop.org/show_bug.cgi?id=102919

shard-hswtotal:2551 pass:1428 dwarn:5   dfail:0   fail:14  skip:1104 
time:9567s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_313/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for Add new vblank and lease tests [v2]

[Patchwork]

== Series Details ==

Series: Add new vblank and lease tests [v2]
URL   : https://patchwork.freedesktop.org/series/31703/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
145f294d1404e86d06cd7dbfbb6e2034b764ea06 intel_aubdump: Default to 48-bit AUBs 
when the gen is unknown

with latest DRM-Tip kernel build CI_DRM_3208
c880c004bb05 drm-tip: 2017y-10m-10d-20h-31m-39s UTC integration manifest

Testlist changes:
+igt@kms_lease@lease_again
+igt@kms_lease@lease_get
+igt@kms_lease@lease_invalid_connector
+igt@kms_lease@lease_invalid_crtc
+igt@kms_lease@lease_revoke
+igt@kms_lease@lease_unleased_connector
+igt@kms_lease@lease_unleased_crtc
+igt@kms_lease@lessee_list
+igt@kms_lease@simple_lease
+igt@kms_sequence@get-busy
+igt@kms_sequence@get-forked
+igt@kms_sequence@get-forked-busy
+igt@kms_sequence@get-idle
+igt@kms_sequence@queue-busy
+igt@kms_sequence@queue-idle

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:464s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:475s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:395s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:582s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:285s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:529s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:531s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:541s
fi-byt-n2820 total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  
time:522s
fi-cfl-s total:289  pass:253  dwarn:4   dfail:0   fail:0   skip:32  
time:560s
fi-cnl-y total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:628s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:435s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:603s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:442s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:416s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:460s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:505s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:481s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:504s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:582s
fi-kbl-7567u total:289  pass:265  dwarn:4   dfail:0   fail:0   skip:20  
time:490s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:599s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:661s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:469s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:659s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:534s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:517s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:476s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:586s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:433s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_324/
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[Intel-gfx] ✗ Fi.CI.IGT: warning for Add support for NV12

[Patchwork]

== Series Details ==

Series: Add support for NV12
URL   : https://patchwork.freedesktop.org/series/31648/
State : warning

== Summary ==

Test gem_eio:
Subgroup wait:
pass   -> DMESG-WARN (shard-hsw) fdo#102886 +3
Test drv_module_reload:
Subgroup basic-reload-inject:
pass   -> DMESG-WARN (shard-hsw) fdo#102707
Test kms_cursor_legacy:
Subgroup flip-vs-cursor-busy-crc-atomic:
pass   -> DMESG-WARN (shard-hsw)

fdo#102886 https://bugs.freedesktop.org/show_bug.cgi?id=102886
fdo#102707 https://bugs.freedesktop.org/show_bug.cgi?id=102707

shard-hswtotal:2602 pass:1429 dwarn:7   dfail:0   fail:63  skip:1103 
time:9614s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_312/shards.html
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[Intel-gfx] [PATCH i-g-t 2/2] tests/kms_lease: add tests for lease ioctls [v2]

[Keith Packard]

Validate that the leasing API creates leases that allow access to a
subset of the available resources and that lease revocation works.

v2: from Dave Airlie 

 * Update ioctl numbers to latest proposed values.
 * Fix commit message
 * Add tests for get_lease and list_lessees

Signed-off-by: Keith Packard 
---
 tests/Makefile.sources |   1 +
 tests/kms_lease.c  | 597 +
 tests/meson.build  |   1 +
 3 files changed, 599 insertions(+)
 create mode 100644 tests/kms_lease.c

diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 9dc1d250..1ca6e104 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -193,6 +193,7 @@ TESTS_progs = \
kms_frontbuffer_tracking \
kms_hdmi_inject \
kms_invalid_dotclock \
+   kms_lease \
kms_legacy_colorkey \
kms_mmap_write_crc \
kms_mmio_vs_cs_flip \
diff --git a/tests/kms_lease.c b/tests/kms_lease.c
new file mode 100644
index ..49226163
--- /dev/null
+++ b/tests/kms_lease.c
@@ -0,0 +1,597 @@
+/*
+ * Copyright © 2017 Keith Packard
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+/** @file kms_lease.c
+ *
+ * This is a test of DRM leases
+ */
+
+
+#include "igt.h"
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+IGT_TEST_DESCRIPTION("Test of CreateLease.");
+
+struct local_drm_mode_create_lease {
+/** Pointer to array of object ids (__u32) */
+__u64 object_ids;
+/** Number of object ids */
+__u32 object_count;
+/** flags for new FD (O_CLOEXEC, etc) */
+__u32 flags;
+
+/** Return: unique identifier for lessee. */
+__u32 lessee_id;
+/** Return: file descriptor to new drm_master file */
+__u32 fd;
+};
+
+struct local_drm_mode_list_lessees {
+/** Number of lessees.
+ * On input, provides length of the array.
+ * On output, provides total number. No
+ * more than the input number will be written
+ * back, so two calls can be used to get
+ * the size and then the data.
+ */
+__u32 count_lessees;
+__u32 pad;
+
+/** Pointer to lessees.
+ * pointer to __u64 array of lessee ids
+ */
+__u64 lessees_ptr;
+};
+
+struct local_drm_mode_get_lease {
+/** Number of leased objects.
+ * On input, provides length of the array.
+ * On output, provides total number. No
+ * more than the input number will be written
+ * back, so two calls can be used to get
+ * the size and then the data.
+ */
+__u32 count_objects;
+__u32 pad;
+
+/** Pointer to objects.
+ * pointer to __u32 array of object ids
+ */
+__u64 objects_ptr;
+};
+
+/**
+ * Revoke lease
+ */
+struct local_drm_mode_revoke_lease {
+/** Unique ID of lessee
+ */
+__u32 lessee_id;
+};
+
+
+#define LOCAL_DRM_IOCTL_MODE_CREATE_LEASE DRM_IOWR(0xC6, struct 
local_drm_mode_create_lease)
+#define LOCAL_DRM_IOCTL_MODE_LIST_LESSEES DRM_IOWR(0xC7, struct 
local_drm_mode_list_lessees)
+#define LOCAL_DRM_IOCTL_MODE_GET_LEASEDRM_IOWR(0xC8, struct 
local_drm_mode_get_lease)
+#define LOCAL_DRM_IOCTL_MODE_REVOKE_LEASE DRM_IOWR(0xC9, struct 
local_drm_mode_revoke_lease)
+
+typedef struct {
+   int fd;
+   uint32_t lessee_id;
+   igt_display_t display;
+   struct igt_fb primary_fb;
+   igt_output_t *output;
+   drmModeModeInfo *mode;
+} lease_t;
+
+typedef struct {
+   lease_t master;
+   enum pipe pipe;
+   uint32_t crtc_id;
+   uint32_t connector_id;
+} data_t;
+
+static uint32_t pipe_to_crtc_id(igt_display_t *display, enum pipe pipe)
+{
+   return 

[Intel-gfx] [PATCH i-g-t 0/2] Add new vblank and lease tests [v2]

[Keith Packard]

Changes since last version:

 * Add local definitions of new ioctls to avoid dependency on proposed
   libdrm bits.

 * Remove FIRST_PIXEL_OUT as that has been removed from the proposed
   kernel interface

 * Add tests for get_lease and list_lessees

 * Fix commit message on the lease test patch

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[Intel-gfx] [PATCH i-g-t 1/2] tests/kms_sequence: Add tests for new CRTC get/queue sequence ioctls [v2]

[Keith Packard]

These ioctls replace drmWaitVBlank and add ns time resolution and
64-bit sequence numbers to comply with the Vulkan API specifications.

The tests were derived from the existing kms_vblank tests with the
'wait' variant elided as the new API doesn't provide a mechanism for
blocking in the kernel.

v2: from Dave Airlie 

 * Add local definitions of new ioctls to avoid requiring latest
   libdrm.

 * Remove FIRST_PIXEL_OUT as that has been removed from the proposed
   kernel patches.

Signed-off-by: Keith Packard 
---
 lib/igt_kms.c  |   2 +-
 lib/igt_kms.h  |   1 +
 tests/Makefile.sources |   1 +
 tests/kms_sequence.c   | 317 +
 tests/meson.build  |   1 +
 5 files changed, 321 insertions(+), 1 deletion(-)
 create mode 100644 tests/kms_sequence.c

diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 379bd0c3..44285baa 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -1983,7 +1983,7 @@ report_dup:
}
 }
 
-static igt_pipe_t *igt_output_get_driving_pipe(igt_output_t *output)
+igt_pipe_t *igt_output_get_driving_pipe(igt_output_t *output)
 {
igt_display_t *display = output->display;
enum pipe pipe;
diff --git a/lib/igt_kms.h b/lib/igt_kms.h
index 8dc118c9..92b66676 100644
--- a/lib/igt_kms.h
+++ b/lib/igt_kms.h
@@ -397,6 +397,7 @@ igt_plane_t *igt_output_get_plane(igt_output_t *output, int 
plane_idx);
 igt_plane_t *igt_output_get_plane_type(igt_output_t *output, int plane_type);
 igt_output_t *igt_output_from_connector(igt_display_t *display,
 drmModeConnector *connector);
+igt_pipe_t *igt_output_get_driving_pipe(igt_output_t *output);
 igt_plane_t *igt_pipe_get_plane_type(igt_pipe_t *pipe, int plane_type);
 bool igt_pipe_get_property(igt_pipe_t *pipe, const char *name,
   uint32_t *prop_id, uint64_t *value,
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index bb6652e2..9dc1d250 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -215,6 +215,7 @@ TESTS_progs = \
kms_tv_load_detect \
kms_universal_plane \
kms_vblank \
+   kms_sequence \
meta_test \
perf \
pm_backlight \
diff --git a/tests/kms_sequence.c b/tests/kms_sequence.c
new file mode 100644
index ..783dda25
--- /dev/null
+++ b/tests/kms_sequence.c
@@ -0,0 +1,317 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ * Copyright © 2017 Keith Packard
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+/** @file kms_sequence.c
+ *
+ * This is a test of drmCrtcGetSequence and drmCrtcQueueSequence
+ */
+
+#include "igt.h"
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include "intel_bufmgr.h"
+
+IGT_TEST_DESCRIPTION("Test CrtcGetSequence and CrtcQueueSequence.");
+
+typedef struct {
+   igt_display_t display;
+   struct igt_fb primary_fb;
+   igt_output_t *output;
+   uint32_t crtc_id;
+   enum pipe pipe;
+   unsigned int flags;
+#define IDLE 1
+#define BUSY 2
+#define FORKED 4
+} data_t;
+
+struct local_drm_crtc_get_sequence {
+   __u32 crtc_id;
+   __u32 active;
+   __u64 sequence;
+   __u64 sequence_ns;
+};
+
+struct local_drm_crtc_queue_sequence {
+   __u32 crtc_id;
+   __u32 flags;
+   __u64 sequence;
+   __u64 user_data;
+};
+
+#define LOCAL_DRM_IOCTL_CRTC_GET_SEQUENCE DRM_IOWR(0x3b, struct 
local_drm_crtc_get_sequence)
+#define LOCAL_DRM_IOCTL_CRTC_QUEUE_SEQUENCE   DRM_IOWR(0x3c, struct 
local_drm_crtc_queue_sequence)
+
+#define LOCAL_DRM_CRTC_SEQUENCE_RELATIVE  0x0001  /* 
sequence is relative to current */
+#define LOCAL_DRM_CRTC_SEQUENCE_NEXT_ON_MISS  0x0002  /* Use 
next sequence if we've missed */
+
+struct local_drm_event_crtc_sequence {
+struct drm_event  

Re: [Intel-gfx] [PATCH i-g-t] lib/igt_gt: Allow non-default contexts to hang non-render rings

[Chris Wilson]

Quoting Vinay Belgaumkar (2017-10-11 00:59:51)
> This limitation does not exist for gen8+.

Oh yes it did. "It did" being the operative phrase there. Read the
comment, find the commit that changed the ABI.
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for igt/drv_hangman: Convert from local recursive batch to igt_spin_t

[Patchwork]

== Series Details ==

Series: igt/drv_hangman: Convert from local recursive batch to igt_spin_t
URL   : https://patchwork.freedesktop.org/series/31694/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
145f294d1404e86d06cd7dbfbb6e2034b764ea06 intel_aubdump: Default to 48-bit AUBs 
when the gen is unknown

with latest DRM-Tip kernel build CI_DRM_3208
c880c004bb05 drm-tip: 2017y-10m-10d-20h-31m-39s UTC integration manifest

No testlist changes.

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:455s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:469s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:395s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:570s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:286s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:521s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:533s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:539s
fi-byt-n2820 total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  
time:521s
fi-cfl-s total:289  pass:253  dwarn:4   dfail:0   fail:0   skip:32  
time:563s
fi-cnl-y total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:637s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:445s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:604s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:446s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:425s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:461s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:508s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:476s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:506s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:587s
fi-kbl-7567u total:289  pass:265  dwarn:4   dfail:0   fail:0   skip:20  
time:496s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:594s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:662s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:466s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:657s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:535s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:520s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:471s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:586s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:439s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_323/
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[Intel-gfx] ✓ Fi.CI.BAT: success for lib/igt_gt: Allow non-default contexts to hang non-render rings

[Patchwork]

== Series Details ==

Series: lib/igt_gt: Allow non-default contexts to hang non-render rings
URL   : https://patchwork.freedesktop.org/series/31693/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
145f294d1404e86d06cd7dbfbb6e2034b764ea06 intel_aubdump: Default to 48-bit AUBs 
when the gen is unknown

with latest DRM-Tip kernel build CI_DRM_3208
c880c004bb05 drm-tip: 2017y-10m-10d-20h-31m-39s UTC integration manifest

No testlist changes.

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:458s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:464s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:398s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:570s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:287s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:524s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:522s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:541s
fi-byt-n2820 total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  
time:530s
fi-cfl-s total:289  pass:253  dwarn:4   dfail:0   fail:0   skip:32  
time:566s
fi-cnl-y total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:628s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:433s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:602s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:442s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:419s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:463s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:498s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:476s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:503s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:586s
fi-kbl-7567u total:289  pass:265  dwarn:4   dfail:0   fail:0   skip:20  
time:488s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:595s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:666s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:469s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:658s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:538s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:520s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:473s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:584s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:437s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_322/
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[Intel-gfx] [PATCH igt] igt/drv_hangman: Convert from local recursive batch to igt_spin_t

[Chris Wilson]

Replace the local recursive batch execbuf with the equivalent
igt_spin_t.

Signed-off-by: Chris Wilson 
---
 tests/drv_missed_irq.c | 79 --
 1 file changed, 18 insertions(+), 61 deletions(-)

diff --git a/tests/drv_missed_irq.c b/tests/drv_missed_irq.c
index 469be882..10328b2b 100644
--- a/tests/drv_missed_irq.c
+++ b/tests/drv_missed_irq.c
@@ -26,90 +26,41 @@
 
 #include "igt.h"
 #include "igt_debugfs.h"
+#include "igt_dummyload.h"
 #include "igt_sysfs.h"
 
 IGT_TEST_DESCRIPTION("Inject missed interrupts and make sure they are caught");
 
 static void trigger_missed_interrupt(int fd, unsigned ring)
 {
-   const int gen = intel_gen(intel_get_drm_devid(fd));
-   struct drm_i915_gem_exec_object2 obj;
-   struct drm_i915_gem_relocation_entry reloc;
-   struct drm_i915_gem_execbuffer2 execbuf;
-   uint32_t *batch;
-   int i;
-
-   memset(, 0, sizeof(obj));
-   obj.handle = gem_create(fd, 4096);
-   obj.relocs_ptr = (uintptr_t)
-   obj.relocation_count = 1;
-
-   memset(, 0, sizeof(reloc));
-   reloc.target_handle = obj.handle; /* recurse */
-   reloc.presumed_offset = 0;
-   reloc.offset = sizeof(uint32_t);
-   reloc.delta = 0;
-   reloc.read_domains = I915_GEM_DOMAIN_COMMAND;
-   reloc.write_domain = 0;
-
-   batch = gem_mmap__wc(fd, obj.handle, 0, 4096, PROT_WRITE);
-   gem_set_domain(fd, obj.handle,
-   I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
-
-   i = 0;
-   batch[i] = MI_BATCH_BUFFER_START;
-   if (gen >= 8) {
-   batch[i] |= 1 << 8 | 1;
-   batch[++i] = 0;
-   batch[++i] = 0;
-   } else if (gen >= 6) {
-   batch[i] |= 1 << 8;
-   batch[++i] = 0;
-   } else {
-   batch[i] |= 2 << 6;
-   batch[++i] = 0;
-   if (gen < 4) {
-   batch[i] |= 1;
-   reloc.delta = 1;
-   }
-   }
-   batch[1000] = 1;
-
-   memset(, 0, sizeof(execbuf));
-   execbuf.buffers_ptr = (uintptr_t)
-   execbuf.buffer_count = 1;
-   execbuf.flags = ring;
-
-   execbuf.flags = ring;
-   if (__gem_execbuf(fd, ))
-   goto out;
+   igt_spin_t *spin = __igt_spin_batch_new(fd, 0, ring, 0);
 
igt_fork(child, 1) {
/* We are now a low priority child on the *same* CPU as the
 * parent. We will have to wait for our parent to sleep
 * (gem_sync -> i915_wait_request) before we run.
 */
-   igt_assert(*((volatile uint32_t *)batch + 1000) == 0);
-   igt_assert(gem_bo_busy(fd, obj.handle));
-
-   *batch = MI_BATCH_BUFFER_END;
-   __sync_synchronize();
+   igt_assert(gem_bo_busy(fd, spin->handle));
+   igt_spin_batch_end(spin);
}
 
-   batch[1000] = 0;
-   gem_sync(fd, obj.handle);
+   gem_sync(fd, spin->handle);
igt_waitchildren();
 
-out:
-   gem_close(fd, obj.handle);
-   munmap(batch, 4096);
+   igt_spin_batch_free(fd, spin);
 }
 
 static void bind_to_cpu(int cpu)
 {
+   const int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
struct sched_param rt = {.sched_priority = 99 };
+   cpu_set_t allowed;
 
igt_assert(sched_setscheduler(getpid(), SCHED_RR | SCHED_RESET_ON_FORK, 
) == 0);
+
+   CPU_ZERO();
+   CPU_SET(cpu % ncpus, );
+   igt_assert(sched_setaffinity(getpid(), sizeof(cpu_set_t), ) == 
0);
 }
 
 static void enable_missed_irq(int dir)
@@ -162,6 +113,9 @@ igt_simple_main
if (expect_rings != -1 && e->exec_id == 0)
continue;
 
+   if (!gem_has_ring(device, e->exec_id | e->flags))
+   continue;
+
igt_debug("Clearing ring %s [%x]\n",
  e->name, e->exec_id | e->flags);
trigger_missed_interrupt(device, e->exec_id | e->flags);
@@ -177,6 +131,9 @@ igt_simple_main
if (expect_rings != -1 && e->exec_id == 0)
continue;
 
+   if (!gem_has_ring(device, e->exec_id | e->flags))
+   continue;
+
igt_debug("Executing on ring %s [%x]\n",
  e->name, e->exec_id | e->flags);
trigger_missed_interrupt(device, e->exec_id | e->flags);
-- 
2.15.0.rc0

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[Intel-gfx] [PATCH i-g-t] lib/igt_gt: Allow non-default contexts to hang non-render rings

[Vinay Belgaumkar]

This limitation does not exist for gen8+.

Cc: Michel Thierry 
Cc: Arkadiusz Hiler 
Cc: Petri Latvala 
Signed-off-by: Vinay Belgaumkar 
---
 lib/igt_gt.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/lib/igt_gt.c b/lib/igt_gt.c
index b3f3b38..abf789d 100644
--- a/lib/igt_gt.c
+++ b/lib/igt_gt.c
@@ -214,6 +214,7 @@ void igt_disallow_hang(int fd, igt_hang_t arg)
  * @ctx: the contxt specifier
  * @ring: execbuf ring flag
  * @flags: set of flags to control execution
+ * @offset: The resultant gtt offset of the exec obj
  *
  * This helper function injects a hanging batch associated with @ctx into 
@ring.
  * It returns a #igt_hang_t structure which must be passed to
@@ -239,8 +240,11 @@ igt_hang_t igt_hang_ctx(int fd,
 
igt_require_hang_ring(fd, ring);
 
-   /* One day the kernel ABI will be fixed! */
-   igt_require(ctx == 0 || ring == I915_EXEC_RENDER);
+   if (!(intel_gen(intel_get_drm_devid(fd)) >= 8))
+   {
+   /* One day the kernel ABI will be fixed! */
+   igt_require(ctx == 0 || ring == I915_EXEC_RENDER);
+   }
 
param.context = ctx;
param.size = 0;
-- 
1.9.1

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[Intel-gfx] ✓ Fi.CI.BAT: success for intel_aubdump: Default to 48-bit AUBs when the gen is unknown

[Patchwork]

== Series Details ==

Series: intel_aubdump: Default to 48-bit AUBs when the gen is unknown
URL   : https://patchwork.freedesktop.org/series/31689/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
d7c88290ab6a8393dc341b30c7fb5e27d2952901 syncobj: Add a test for 
SYNCOBJ_CREATE_SIGNALED

with latest DRM-Tip kernel build CI_DRM_3208
c880c004bb05 drm-tip: 2017y-10m-10d-20h-31m-39s UTC integration manifest

No testlist changes.

Test chamelium:
Subgroup dp-crc-fast:
pass   -> FAIL   (fi-kbl-7500u) fdo#102514

fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:458s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:473s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:395s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:571s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:285s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:525s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:529s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:537s
fi-byt-n2820 total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  
time:522s
fi-cfl-s total:289  pass:253  dwarn:4   dfail:0   fail:0   skip:32  
time:567s
fi-cnl-y total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:632s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:437s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:603s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:445s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:422s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:468s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:507s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:481s
fi-kbl-7500u total:289  pass:263  dwarn:1   dfail:0   fail:1   skip:24  
time:495s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:585s
fi-kbl-7567u total:289  pass:265  dwarn:4   dfail:0   fail:0   skip:20  
time:489s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:591s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:665s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:471s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:656s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:534s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:516s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:468s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:579s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:438s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_321/
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Re: [Intel-gfx] [PATCH i-g-t v2] intel_aubdump: Default to 48-bit AUBs when the gen is unknown

[Kenneth Graunke]

On Tuesday, October 10, 2017 4:05:17 PM PDT Jordan Justen wrote:
> v2:
>  * Use 48-bit rather than 64-bit (Ken)
>  * Use 'addr_bits' rather than 'use_64bit'
> 
> Signed-off-by: Jordan Justen 

Reviewed-by: Kenneth Graunke 

and pushed.


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[Intel-gfx] ✓ Fi.CI.BAT: success for intel_aubdump: Add device override names (from Mesa INTEL_DEVID_OVERRIDE)

[Patchwork]

== Series Details ==

Series: intel_aubdump: Add device override names (from Mesa 
INTEL_DEVID_OVERRIDE)
URL   : https://patchwork.freedesktop.org/series/31688/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
d7c88290ab6a8393dc341b30c7fb5e27d2952901 syncobj: Add a test for 
SYNCOBJ_CREATE_SIGNALED

with latest DRM-Tip kernel build CI_DRM_3208
c880c004bb05 drm-tip: 2017y-10m-10d-20h-31m-39s UTC integration manifest

No testlist changes.

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:454s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:476s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:393s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:571s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:286s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:524s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:526s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:546s
fi-byt-n2820 total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  
time:519s
fi-cfl-s total:289  pass:253  dwarn:4   dfail:0   fail:0   skip:32  
time:557s
fi-cnl-y total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:639s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:439s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:601s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:442s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:423s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:467s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:517s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:477s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:498s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:581s
fi-kbl-7567u total:289  pass:265  dwarn:4   dfail:0   fail:0   skip:20  
time:488s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:592s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:681s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:469s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:658s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:530s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:510s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:480s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:585s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:436s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_320/
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[Intel-gfx] [PATCH i-g-t v2] intel_aubdump: Default to 48-bit AUBs when the gen is unknown

[Jordan Justen]

v2:
 * Use 48-bit rather than 64-bit (Ken)
 * Use 'addr_bits' rather than 'use_64bit'

Cc: Kenneth Graunke 
Signed-off-by: Jordan Justen 
---
 tools/aubdump.c | 26 --
 1 file changed, 16 insertions(+), 10 deletions(-)

diff --git a/tools/aubdump.c b/tools/aubdump.c
index f3efb451..ee378a76 100644
--- a/tools/aubdump.c
+++ b/tools/aubdump.c
@@ -59,6 +59,7 @@ static int gen = 0;
 static int verbose = 0;
 static bool device_override;
 static uint32_t device;
+static int addr_bits = 0;
 
 static const struct {
const char *name;
@@ -190,7 +191,7 @@ data_out(const void *data, size_t size)
 static uint32_t
 gtt_entry_size(void)
 {
-   return gen >= 8 ? 8 : 4;
+   return addr_bits > 32 ? 8 : 4;
 }
 
 static uint32_t
@@ -229,17 +230,17 @@ write_header(void)
data_out(comment, comment_dwords * 4);
 
/* Set up the GTT. The max we can handle is 64M */
-   dword_out(CMD_AUB_TRACE_HEADER_BLOCK | ((gen >= 8 ? 6 : 5) - 2));
+   dword_out(CMD_AUB_TRACE_HEADER_BLOCK | ((addr_bits > 32 ? 6 : 5) - 2));
dword_out(AUB_TRACE_MEMTYPE_GTT_ENTRY |
  AUB_TRACE_TYPE_NOTYPE | AUB_TRACE_OP_DATA_WRITE);
dword_out(0); /* subtype */
dword_out(0); /* offset */
dword_out(gtt_size()); /* size */
-   if (gen >= 8)
+   if (addr_bits > 32)
dword_out(0);
for (uint32_t i = 0; i * gtt_entry_size() < gtt_size(); i++) {
dword_out(entry + 0x1000 * i);
-   if (gen >= 8)
+   if (addr_bits > 32)
dword_out(0);
}
 }
@@ -263,13 +264,13 @@ aub_write_trace_block(uint32_t type, void *virtual, 
uint32_t size, uint64_t gtt_
block_size = 8 * 4096;
 
dword_out(CMD_AUB_TRACE_HEADER_BLOCK |
- ((gen >= 8 ? 6 : 5) - 2));
+ ((addr_bits > 32 ? 6 : 5) - 2));
dword_out(AUB_TRACE_MEMTYPE_GTT |
  type | AUB_TRACE_OP_DATA_WRITE);
dword_out(subtype);
dword_out(gtt_offset + offset);
dword_out(align_u32(block_size, 4));
-   if (gen >= 8)
+   if (addr_bits > 32)
dword_out((gtt_offset + offset) >> 32);
 
if (virtual)
@@ -285,7 +286,7 @@ aub_write_trace_block(uint32_t type, void *virtual, 
uint32_t size, uint64_t gtt_
 static void
 write_reloc(void *p, uint64_t v)
 {
-   if (gen >= 8) {
+   if (addr_bits > 32) {
/* From the Broadwell PRM Vol. 2a,
 * MI_LOAD_REGISTER_MEM::MemoryAddress:
 *
@@ -324,7 +325,7 @@ aub_dump_ringbuffer(uint64_t batch_offset, uint64_t offset, 
int ring_flag)
/* Make a ring buffer to execute our batchbuffer. */
memset(ringbuffer, 0, sizeof(ringbuffer));
 
-   aub_mi_bbs_len = gen >= 8 ? 3 : 2;
+   aub_mi_bbs_len = addr_bits > 32 ? 3 : 2;
ringbuffer[ring_count] = AUB_MI_BATCH_BUFFER_START | (aub_mi_bbs_len - 
2);
write_reloc([ring_count + 1], batch_offset);
ring_count += aub_mi_bbs_len;
@@ -333,12 +334,12 @@ aub_dump_ringbuffer(uint64_t batch_offset, uint64_t 
offset, int ring_flag)
 * the ring in the simulator.
 */
dword_out(CMD_AUB_TRACE_HEADER_BLOCK |
- ((gen >= 8 ? 6 : 5) - 2));
+ ((addr_bits > 32 ? 6 : 5) - 2));
dword_out(AUB_TRACE_MEMTYPE_GTT | ring | AUB_TRACE_OP_COMMAND_WRITE);
dword_out(0); /* general/surface subtype */
dword_out(offset);
dword_out(ring_count * 4);
-   if (gen >= 8)
+   if (addr_bits > 32)
dword_out(offset >> 32);
 
data_out(ringbuffer, ring_count * 4);
@@ -441,6 +442,11 @@ dump_execbuffer2(int fd, struct drm_i915_gem_execbuffer2 
*execbuffer2)
   filename, device, gen);
}
 
+   /* If we don't know the device gen, then it probably is a
+* newer device which uses 48-bit addresses.
+*/
+   addr_bits = (gen >= 8 || gen == 0) ? 48 : 32;
+
if (verbose)
printf("Dumping execbuffer2:\n");
 
-- 
2.14.1

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[Intel-gfx] [PATCH i-g-t] intel_aubdump: Add device override names (from Mesa INTEL_DEVID_OVERRIDE)

[Jordan Justen]

This just lets you specify an override like --device=bdw for
broadwell.

Signed-off-by: Jordan Justen 
---
Resend with 'i-g-t' in subject line.

 tools/aubdump.c| 36 
 tools/intel_aubdump.in |  4 +++-
 2 files changed, 35 insertions(+), 5 deletions(-)

diff --git a/tools/aubdump.c b/tools/aubdump.c
index ee4d99b0..f3efb451 100644
--- a/tools/aubdump.c
+++ b/tools/aubdump.c
@@ -60,6 +60,24 @@ static int verbose = 0;
 static bool device_override;
 static uint32_t device;
 
+static const struct {
+   const char *name;
+   int pci_id;
+} name_map[] = {
+   { "brw", 0x2a02 },
+   { "g4x", 0x2a42 },
+   { "ilk", 0x0042 },
+   { "snb", 0x0126 },
+   { "ivb", 0x016a },
+   { "hsw", 0x0d2e },
+   { "byt", 0x0f33 },
+   { "bdw", 0x162e },
+   { "skl", 0x1912 },
+   { "kbl", 0x5912 },
+   { "cnl", 0x5a52 },
+   /* Note: also update list in intel_aubdump.in */
+};
+
 #define MAX_BO_COUNT 64 * 1024
 
 struct bo {
@@ -570,10 +588,20 @@ maybe_init(void)
if (!strcmp(key, "verbose")) {
verbose = 1;
} else if (!strcmp(key, "device")) {
-   fail_if(sscanf(value, "%i", ) != 1,
-   "intel_aubdump: failed to parse device id '%s'",
-   value);
-   device_override = true;
+   unsigned i;
+   for (i = 0; i < ARRAY_SIZE(name_map); i++) {
+   if (!strcmp(name_map[i].name, value)) {
+   device = name_map[i].pci_id;
+   device_override = true;
+   break;
+   }
+   }
+   if (i >= ARRAY_SIZE(name_map)) {
+   fail_if(sscanf(value, "%i", ) != 1,
+   "intel_aubdump: failed to parse device 
id '%s'",
+   value);
+   device_override = true;
+   }
} else if (!strcmp(key, "file")) {
filename = strdup(value);
files[0] = fopen(filename, "w+");
diff --git a/tools/intel_aubdump.in b/tools/intel_aubdump.in
index 977fe951..f9a92d86 100755
--- a/tools/intel_aubdump.in
+++ b/tools/intel_aubdump.in
@@ -13,7 +13,9 @@ contents and execution of the GEM application.
   -c, --command=CMD  Execute CMD and write the AUB file's content to its
  standard input
 
-  --device=IDOverride PCI ID of the reported device
+  --device=IDOverride PCI ID of the reported device. ID may be an
+ integer, or one of: brw, g4x, ilk, snb, ivb, hsw, byt,
+ bdw, skl, kbl or cnl
 
   -v Enable verbose output
 
-- 
2.14.1

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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Simplify intel_sanitize_enable_ppgtt

[Patchwork]

== Series Details ==

Series: drm/i915: Simplify intel_sanitize_enable_ppgtt
URL   : https://patchwork.freedesktop.org/series/31665/
State : success

== Summary ==

Test kms_atomic_transition:
Subgroup plane-all-transition:
skip   -> PASS   (shard-hsw)
Test kms_plane_multiple:
Subgroup legacy-pipe-B-tiling-x:
skip   -> PASS   (shard-hsw)
Test gem_userptr_blits:
Subgroup sync-unmap-cycles:
dmesg-warn -> PASS   (shard-hsw) fdo#102886

fdo#102886 https://bugs.freedesktop.org/show_bug.cgi?id=102886

shard-hswtotal:2552 pass:1431 dwarn:5   dfail:0   fail:13  skip:1103 
time:9650s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5977/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,01/12] drm/i915: Separate RPS and RC6 handling for gen6+

[Patchwork]

== Series Details ==

Series: series starting with [CI,01/12] drm/i915: Separate RPS and RC6 handling 
for gen6+
URL   : https://patchwork.freedesktop.org/series/31681/
State : success

== Summary ==

Series 31681v1 series starting with [CI,01/12] drm/i915: Separate RPS and RC6 
handling for gen6+
https://patchwork.freedesktop.org/api/1.0/series/31681/revisions/1/mbox/

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:456s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:476s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:398s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:577s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:286s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:528s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:524s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:543s
fi-byt-n2820 total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  
time:523s
fi-cfl-s total:289  pass:253  dwarn:4   dfail:0   fail:0   skip:32  
time:562s
fi-cnl-y total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:638s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:435s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:601s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:441s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:416s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:465s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:510s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:476s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:504s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:583s
fi-kbl-7567u total:289  pass:265  dwarn:4   dfail:0   fail:0   skip:20  
time:488s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:596s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:479s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:657s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:533s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:512s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:476s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:592s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:434s
fi-pnv-d510 failed to connect after reboot

c880c004bb05a4a530f1a07e65075743ad316f68 drm-tip: 2017y-10m-10d-20h-31m-39s UTC 
integration manifest
e61b78f2dcb2 drm/i915: Introduce separate status variable for RC6 and LLC ring 
frequency setup
d739399467a4 drm/i915: Create generic functions to control RC6, RPS
ad287fc0f4a8 drm/i915: Create generic function to setup LLC ring frequency table
141daab94bf4 drm/i915: Rename intel_enable_rc6 to intel_rc6_enabled
f850dbd72bd6 drm/i915: Name structure in dev_priv that contains RPS/RC6 state 
as "gt_pm"
1952fc0f508e drm/i915: Move rps.hw_lock to dev_priv and s/hw_lock/pcu_lock
33e517fec988 drm/i915: Name i915_runtime_pm structure in dev_priv as 
"runtime_pm"
fa56fbf912fa drm/i915: Separate RPS and RC6 handling for CHV
ba89b1407de6 drm/i915: Separate RPS and RC6 handling for VLV
e62fd5d3c6b4 drm/i915: Separate RPS and RC6 handling for BDW
95c06a3426cc drm/i915: Remove superfluous IS_BDW checks and non-BDW changes 
from gen8_enable_rps
5da71fb96f63 drm/i915: Separate RPS and RC6 handling for gen6+

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5984/
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[Intel-gfx] [PATCH v2 3/3] drm/i915/selftests: Exercise adding requests to a full GGTT

[Chris Wilson]

A bug recently encountered involved the issue where are we were
submitting requests to different ppGTT, each would pin a segment of the
GGTT for its logical context and ring. However, this is invisible to
eviction as we do not tie the context/ring VMA to a request and so do
not automatically wait upon it them (instead they are marked as pinned,
prevent eviction entirely). Instead the eviction code must flush those
contexts by switching to the kernel context. This selftest tries to
fill the GGTT with contexts to exercise a path where the
switch-to-kernel-context failed to make forward progress and we fail
with ENOSPC.

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/selftests/i915_gem_evict.c| 121 +
 .../gpu/drm/i915/selftests/i915_live_selftests.h   |   1 +
 drivers/gpu/drm/i915/selftests/mock_context.c  |   6 +-
 3 files changed, 123 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c 
b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
index 5ea373221f49..53df8926be7f 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
@@ -24,6 +24,8 @@
 
 #include "../i915_selftest.h"
 
+#include "mock_context.h"
+#include "mock_drm.h"
 #include "mock_gem_device.h"
 
 static int populate_ggtt(struct drm_i915_private *i915)
@@ -325,6 +327,116 @@ static int igt_evict_vm(void *arg)
return err;
 }
 
+static int igt_evict_contexts(void *arg)
+{
+   struct drm_i915_private *i915 = arg;
+   struct intel_engine_cs *engine;
+   enum intel_engine_id id;
+   struct reserved {
+   struct drm_mm_node node;
+   struct reserved *next;
+   } *reserved = NULL;
+   unsigned long count;
+   int err = 0;
+
+   /* Make the GGTT appear small (but leave just enough to function) */
+   count = 0;
+   mutex_lock(>drm.struct_mutex);
+   do {
+   struct reserved *r;
+
+   r = kcalloc(1, sizeof(*r), GFP_KERNEL);
+   if (!r) {
+   err = -ENOMEM;
+   goto out_locked;
+   }
+
+   if (i915_gem_gtt_insert(>ggtt.base, >node,
+   1ul << 20, 0, I915_COLOR_UNEVICTABLE,
+   16ul << 20, i915->ggtt.base.total,
+   PIN_NOEVICT)) {
+   kfree(r);
+   break;
+   }
+
+   r->next = reserved;
+   reserved = r;
+
+   count++;
+   } while (1);
+   mutex_unlock(>drm.struct_mutex);
+   pr_info("Filled GGTT with %lu 1MiB nodes\n", count);
+
+   /* Overfill the GGTT with context objects and so try to evict one. */
+   for_each_engine(engine, i915, id) {
+   struct i915_sw_fence *fence;
+   struct drm_file *file;
+   unsigned long count = 0;
+   unsigned long timeout;
+
+   file = mock_file(i915);
+   if (IS_ERR(file))
+   return PTR_ERR(file);
+
+   timeout = round_jiffies_up(jiffies + HZ/2);
+   fence = i915_sw_fence_create_timer(timeout, GFP_KERNEL);
+   if (IS_ERR(fence))
+   return PTR_ERR(fence);
+
+   count = 0;
+   mutex_lock(>drm.struct_mutex);
+   do {
+   struct drm_i915_gem_request *rq;
+   struct i915_gem_context *ctx;
+
+   ctx = live_context(i915, file);
+   if (!ctx)
+   break;
+
+   rq = i915_gem_request_alloc(engine, ctx);
+   if (IS_ERR(rq)) {
+   if (PTR_ERR(rq) != -ENOMEM) {
+   pr_err("Unexpected error from request 
alloc (ctx hw id %u, on %s): %d\n",
+  ctx->hw_id, engine->name,
+  (int)PTR_ERR(rq));
+   err = PTR_ERR(rq);
+   }
+   break;
+   }
+
+   i915_sw_fence_await_sw_fence_gfp(>submit, fence,
+GFP_KERNEL);
+
+   i915_add_request(rq);
+   count++;
+   } while(!i915_sw_fence_done(fence));
+   mutex_unlock(>drm.struct_mutex);
+
+   i915_sw_fence_timer_flush(fence);
+   pr_info("Submitted %lu contexts/requests on %s\n",
+   count, engine->name);
+
+   mock_file_free(i915, file);
+
+   if (err)
+   break;
+   }
+
+   

[Intel-gfx] [PATCH v2 1/3] drm/i915: Fix eviction when the GGTT is idle but full

[Chris Wilson]

In the full-ppgtt world, we can fill the GGTT full of context objects.
These context objects are currently implicitly tracked by the requests
that pin them i.e. they are only unpinned when the request is completed
and retired, but we do not have the link from the vma to the request
(anymore). In order to unpin those contexts, we have to issue another
request and wait upon the switch to the kernel context.

The bug during eviction was that we assumed that a full GGTT meant we
would have requests on the GGTT timeline, and so we missed situations
where those requests where merely in flight (and when even they have not
yet been submitted to hw yet). The fix employed here is to change the
already-is-idle test to no look at the execution timeline, but count the
outstanding requests and then check that we have switched to the kernel
context. Erring on the side of overkill here just means that we stall a
little longer than may be strictly required, but we only expect to hit
this path in extreme corner cases where returning an erroneous error is
worse than the delay.

v2: Logical inversion when swapping over branches.

Fixes: 80b204bce8f2 ("drm/i915: Enable multiple timelines")
Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_gem_evict.c | 63 ++-
 1 file changed, 39 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c 
b/drivers/gpu/drm/i915/i915_gem_evict.c
index a5a5b7e6daae..ee4811ffb7aa 100644
--- a/drivers/gpu/drm/i915/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/i915_gem_evict.c
@@ -33,21 +33,20 @@
 #include "intel_drv.h"
 #include "i915_trace.h"
 
-static bool ggtt_is_idle(struct drm_i915_private *dev_priv)
+static bool ggtt_is_idle(struct drm_i915_private *i915)
 {
-   struct i915_ggtt *ggtt = _priv->ggtt;
-   struct intel_engine_cs *engine;
-   enum intel_engine_id id;
+   struct intel_engine_cs *engine;
+   enum intel_engine_id id;
 
-   for_each_engine(engine, dev_priv, id) {
-   struct intel_timeline *tl;
+   if (i915->gt.active_requests)
+  return false;
 
-   tl = >base.timeline.engine[engine->id];
-   if (i915_gem_active_isset(>last_request))
-   return false;
-   }
+   for_each_engine(engine, i915, id) {
+  if (engine->last_retired_context != i915->kernel_context)
+  return false;
+   }
 
-   return true;
+   return true;
 }
 
 static int ggtt_flush(struct drm_i915_private *i915)
@@ -157,7 +156,8 @@ i915_gem_evict_something(struct i915_address_space *vm,
min_size, alignment, cache_level,
start, end, mode);
 
-   /* Retire before we search the active list. Although we have
+   /*
+* Retire before we search the active list. Although we have
 * reasonable accuracy in our retirement lists, we may have
 * a stray pin (preventing eviction) that can only be resolved by
 * retiring.
@@ -182,7 +182,8 @@ i915_gem_evict_something(struct i915_address_space *vm,
BUG_ON(ret);
}
 
-   /* Can we unpin some objects such as idle hw contents,
+   /*
+* Can we unpin some objects such as idle hw contents,
 * or pending flips? But since only the GGTT has global entries
 * such as scanouts, rinbuffers and contexts, we can skip the
 * purge when inspecting per-process local address spaces.
@@ -190,19 +191,33 @@ i915_gem_evict_something(struct i915_address_space *vm,
if (!i915_is_ggtt(vm) || flags & PIN_NONBLOCK)
return -ENOSPC;
 
-   if (ggtt_is_idle(dev_priv)) {
-   /* If we still have pending pageflip completions, drop
-* back to userspace to give our workqueues time to
-* acquire our locks and unpin the old scanouts.
-*/
-   return intel_has_pending_fb_unpin(dev_priv) ? -EAGAIN : -ENOSPC;
-   }
+   /*
+* Not everything in the GGTT is tracked via VMA using
+* i915_vma_move_to_active(), otherwise we could evict as required
+* with minimal stalling. Instead we are forced to idle the GPU and
+* explicitly retire outstanding requests which will then remove
+* the pinning for active objects such as contexts and ring,
+* enabling us to evict them on the next iteration.
+*
+* To ensure that all user contexts are evictable, we perform
+* a switch to the perma-pinned kernel context. This all also gives
+* us a termination condition, when the last retired context is
+* the kernel's there is no more we can evict.
+*/
+   if (!ggtt_is_idle(dev_priv)) {
+   ret = ggtt_flush(dev_priv);
+   if 

[Intel-gfx] [PATCH v2 2/3] drm/i915: Wrap a timer into a i915_sw_fence

[Chris Wilson]

For some selftests, we want to issue requests but delay them going to
hardware. Furthermore, we don't want those requests to block
indefinitely (or else we may hang the driver and block testing) so we
want to employ a timeout. So naturally we want a fence that is
automatically signaled by a timer.

v2: Add kselftests.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_sw_fence.c   | 64 ++
 drivers/gpu/drm/i915/i915_sw_fence.h   |  3 ++
 drivers/gpu/drm/i915/selftests/i915_sw_fence.c | 43 +
 3 files changed, 110 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_sw_fence.c 
b/drivers/gpu/drm/i915/i915_sw_fence.c
index 808ea4d5b962..388424a95ac9 100644
--- a/drivers/gpu/drm/i915/i915_sw_fence.c
+++ b/drivers/gpu/drm/i915/i915_sw_fence.c
@@ -506,6 +506,70 @@ int i915_sw_fence_await_reservation(struct i915_sw_fence 
*fence,
return ret;
 }
 
+struct timer_fence {
+   struct i915_sw_fence base;
+   struct timer_list timer;
+   struct kref ref;
+};
+
+static void timer_fence_wake(unsigned long data)
+{
+   struct timer_fence *tf = (struct timer_fence *)data;
+
+   i915_sw_fence_complete(>base);
+}
+
+static void i915_sw_fence_timer_free(struct kref *ref)
+{
+   struct timer_fence *tf = container_of(ref, typeof(*tf), ref);
+
+   kfree(tf);
+}
+
+static void i915_sw_fence_timer_put(struct i915_sw_fence *fence)
+{
+   struct timer_fence *tf = container_of(fence, typeof(*tf), base);
+
+   kref_put(>ref, i915_sw_fence_timer_free);
+}
+
+static int __i915_sw_fence_call
+timer_fence_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify 
state)
+{
+   if (state == FENCE_FREE)
+   i915_sw_fence_timer_put(fence);
+
+   return NOTIFY_DONE;
+}
+
+struct i915_sw_fence *i915_sw_fence_create_timer(long timeout, gfp_t gfp)
+{
+   struct timer_fence *tf;
+
+   tf = kmalloc(sizeof(*tf), gfp);
+   if (!tf)
+   return ERR_PTR(-ENOMEM);
+
+   i915_sw_fence_init(>base, timer_fence_notify);
+   kref_init(>ref);
+
+   setup_timer(>timer, timer_fence_wake, (unsigned long)tf);
+   mod_timer(>timer, timeout);
+
+   kref_get(>ref);
+   return >base;
+}
+
+void i915_sw_fence_timer_flush(struct i915_sw_fence *fence)
+{
+   struct timer_fence *tf = container_of(fence, typeof(*tf), base);
+
+   if (del_timer_sync(>timer))
+   i915_sw_fence_complete(>base);
+
+   i915_sw_fence_timer_put(fence);
+}
+
 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
 #include "selftests/i915_sw_fence.c"
 #endif
diff --git a/drivers/gpu/drm/i915/i915_sw_fence.h 
b/drivers/gpu/drm/i915/i915_sw_fence.h
index fe2ef4dadfc6..c111a89a927a 100644
--- a/drivers/gpu/drm/i915/i915_sw_fence.h
+++ b/drivers/gpu/drm/i915/i915_sw_fence.h
@@ -61,6 +61,9 @@ void i915_sw_fence_fini(struct i915_sw_fence *fence);
 static inline void i915_sw_fence_fini(struct i915_sw_fence *fence) {}
 #endif
 
+struct i915_sw_fence *i915_sw_fence_create_timer(long timeout, gfp_t gfp);
+void i915_sw_fence_timer_flush(struct i915_sw_fence *fence);
+
 void i915_sw_fence_commit(struct i915_sw_fence *fence);
 
 int i915_sw_fence_await_sw_fence(struct i915_sw_fence *fence,
diff --git a/drivers/gpu/drm/i915/selftests/i915_sw_fence.c 
b/drivers/gpu/drm/i915/selftests/i915_sw_fence.c
index 19d145d6bf52..e51ab4310e1e 100644
--- a/drivers/gpu/drm/i915/selftests/i915_sw_fence.c
+++ b/drivers/gpu/drm/i915/selftests/i915_sw_fence.c
@@ -24,6 +24,7 @@
 
 #include 
 #include 
+#include 
 
 #include "../i915_selftest.h"
 
@@ -565,6 +566,47 @@ static int test_ipc(void *arg)
return ret;
 }
 
+static int test_timer(void *arg)
+{
+   struct i915_sw_fence *fence;
+   unsigned long target, delay;
+
+   fence = i915_sw_fence_create_timer(target = jiffies, GFP_KERNEL);
+   if (!i915_sw_fence_done(fence)) {
+   pr_err("Fence with immediate expiration not signaled\n");
+   goto err;
+   }
+   i915_sw_fence_timer_flush(fence);
+
+   for_each_prime_number(delay, HZ/2) {
+   fence = i915_sw_fence_create_timer(target = jiffies + delay,
+  GFP_KERNEL);
+   if (i915_sw_fence_done(fence)) {
+   pr_err("Fence with future expiration (%lu jiffies) 
already signaled\n", delay);
+   goto err;
+   }
+
+   i915_sw_fence_wait(fence);
+   if (!i915_sw_fence_done(fence)) {
+   pr_err("Fence not signaled after wait\n");
+   goto err;
+   }
+   if (time_before(jiffies, target)) {
+   pr_err("Fence signaled too early, target=%lu, 
now=%lu\n",
+  target, jiffies);
+   goto err;
+   }
+
+   i915_sw_fence_timer_flush(fence);
+   }
+
+   return 0;
+
+err:
+   

Re: [Intel-gfx] [PATCH] i-g-t/tests: Drop gem_seqno_wrap, gem_pin, gem_hangcheck_forcewake

[Antonio Argenziano]

On 10/10/17 13:19, Chris Wilson wrote:

Quoting Antonio Argenziano (2017-10-10 18:12:17)



On 10/10/17 01:55, Abdiel Janulgue wrote:

This improves the GEM tests section of I-G-T to make it more
suitable for CI testing


Can you provide a little more details on what is the rationale behind
this choice. Are the tests being removed only because they do not fit
the CI guidelines or is it because they do not offer any valuable coverage?


Hear, hear.

gem_seqno_wrap is defunct as the debug API withered away. The
handling of wraparound under many different workloads is tested by
gem_exec_whisper. The intention is to may seqno wrap handling a
kselftest. That hasn't happened yet, gem_exec_whisper is not run wholy
by CI, but nevertheless gem_seqno_wrap is still defunct.

gem_pin is a useful ABI I still shed a tear over. But it's time has
passed and it's not coming back.

gem_hangcheck_forcewake has been superseded by drv_hangman, and a lot of
other very extensive hangchecking that is not run by CI. Something about
hang testing taking longer than the sun to go nova, and still will never
be completely reliable...
-Chris



Thanks for the explanation Chris.

This convinces me more that the commit needs to be split into three 
separate patches. One for each test with an explanation of why it goes away.


-Antonio
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[Intel-gfx] [CI 08/12] drm/i915: Name structure in dev_priv that contains RPS/RC6 state as "gt_pm"

[Chris Wilson]

From: Sagar Arun Kamble 

Prepared substructure rps for RPS related state. autoenable_work is
used for RC6 too hence it is defined outside rps structure. As we do
this lot many functions are refactored to use intel_rps *rps to access
rps related members. Hence renamed intel_rps_client pointer variables
to rps_client in various functions.

v2: Rebase.

v3: s/pm/gt_pm (Chris)
Refactored access to rps structure by declaring struct intel_rps * in
many functions.

Signed-off-by: Sagar Arun Kamble 
Cc: Chris Wilson 
Cc: Imre Deak 
Cc: Joonas Lahtinen 
Reviewed-by: Radoslaw Szwichtenberg  #1
Reviewed-by: Chris Wilson 
Link: 
https://patchwork.freedesktop.org/patch/msgid/1507360055-19948-9-git-send-email-sagar.a.kam...@intel.com
Acked-by: Imre Deak 
Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_debugfs.c|  99 -
 drivers/gpu/drm/i915/i915_drv.c|   2 +-
 drivers/gpu/drm/i915/i915_drv.h|  14 +-
 drivers/gpu/drm/i915/i915_gem.c|  21 +-
 drivers/gpu/drm/i915/i915_gem_request.c|   2 +-
 drivers/gpu/drm/i915/i915_guc_submission.c |  10 +-
 drivers/gpu/drm/i915/i915_irq.c|  87 
 drivers/gpu/drm/i915/i915_sysfs.c  |  54 ++---
 drivers/gpu/drm/i915/intel_drv.h   |   2 +-
 drivers/gpu/drm/i915/intel_pm.c| 315 -
 10 files changed, 330 insertions(+), 276 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index e733097fa647..0bb6e01121fc 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1080,6 +1080,7 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
 static int i915_frequency_info(struct seq_file *m, void *unused)
 {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
+   struct intel_rps *rps = _priv->gt_pm.rps;
int ret = 0;
 
intel_runtime_pm_get(dev_priv);
@@ -1116,20 +1117,20 @@ static int i915_frequency_info(struct seq_file *m, void 
*unused)
   intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
 
seq_printf(m, "current GPU freq: %d MHz\n",
-  intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
+  intel_gpu_freq(dev_priv, rps->cur_freq));
 
seq_printf(m, "max GPU freq: %d MHz\n",
-  intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
+  intel_gpu_freq(dev_priv, rps->max_freq));
 
seq_printf(m, "min GPU freq: %d MHz\n",
-  intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
+  intel_gpu_freq(dev_priv, rps->min_freq));
 
seq_printf(m, "idle GPU freq: %d MHz\n",
-  intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
+  intel_gpu_freq(dev_priv, rps->idle_freq));
 
seq_printf(m,
   "efficient (RPe) frequency: %d MHz\n",
-  intel_gpu_freq(dev_priv, 
dev_priv->rps.efficient_freq));
+  intel_gpu_freq(dev_priv, rps->efficient_freq));
mutex_unlock(_priv->pcu_lock);
} else if (INTEL_GEN(dev_priv) >= 6) {
u32 rp_state_limits;
@@ -1210,7 +1211,7 @@ static int i915_frequency_info(struct seq_file *m, void 
*unused)
seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, 
MASK=0x%08x\n",
   pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
-  dev_priv->rps.pm_intrmsk_mbz);
+  rps->pm_intrmsk_mbz);
seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
seq_printf(m, "Render p-state ratio: %d\n",
   (gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ? 
0x1ff00 : 0xff00)) >> 8);
@@ -1230,8 +1231,7 @@ static int i915_frequency_info(struct seq_file *m, void 
*unused)
   rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
seq_printf(m, "RP PREV UP: %d (%dus)\n",
   rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
-   seq_printf(m, "Up threshold: %d%%\n",
-  dev_priv->rps.up_threshold);
+   seq_printf(m, "Up threshold: %d%%\n", rps->up_threshold);
 
seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
   rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
@@ -1239,8 +1239,7 @@ static int i915_frequency_info(struct seq_file *m, void 
*unused)
   rpcurdown, 

[Intel-gfx] [CI 06/12] drm/i915: Name i915_runtime_pm structure in dev_priv as "runtime_pm"

[Chris Wilson]

From: Sagar Arun Kamble 

We were using dev_priv->pm for runtime power management related state.
This patch renames it to "runtime_pm" which looks more apt.

v2: s/rpm/runtime_pm (Chris)

Signed-off-by: Sagar Arun Kamble 
Cc: Imre Deak 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Reviewed-by: Radoslaw Szwichtenberg  #1
Reviewed-by: Chris Wilson 
Link: 
https://patchwork.freedesktop.org/patch/msgid/1507360055-19948-7-git-send-email-sagar.a.kam...@intel.com
Acked-by: Imre Deak 
Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_drv.c |  8 
 drivers/gpu/drm/i915/i915_drv.h |  2 +-
 drivers/gpu/drm/i915/i915_gpu_error.c   |  4 ++--
 drivers/gpu/drm/i915/i915_irq.c |  8 
 drivers/gpu/drm/i915/intel_drv.h| 10 +-
 drivers/gpu/drm/i915/intel_pm.c |  4 ++--
 drivers/gpu/drm/i915/intel_runtime_pm.c | 10 +-
 7 files changed, 23 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 66fc156b294a..9ebbb08dcf2d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2544,12 +2544,12 @@ static int intel_runtime_suspend(struct device *kdev)
intel_uncore_suspend(dev_priv);
 
enable_rpm_wakeref_asserts(dev_priv);
-   WARN_ON_ONCE(atomic_read(_priv->pm.wakeref_count));
+   WARN_ON_ONCE(atomic_read(_priv->runtime_pm.wakeref_count));
 
if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
DRM_ERROR("Unclaimed access detected prior to suspending\n");
 
-   dev_priv->pm.suspended = true;
+   dev_priv->runtime_pm.suspended = true;
 
/*
 * FIXME: We really should find a document that references the arguments
@@ -2595,11 +2595,11 @@ static int intel_runtime_resume(struct device *kdev)
 
DRM_DEBUG_KMS("Resuming device\n");
 
-   WARN_ON_ONCE(atomic_read(_priv->pm.wakeref_count));
+   WARN_ON_ONCE(atomic_read(_priv->runtime_pm.wakeref_count));
disable_rpm_wakeref_asserts(dev_priv);
 
intel_opregion_notify_adapter(dev_priv, PCI_D0);
-   dev_priv->pm.suspended = false;
+   dev_priv->runtime_pm.suspended = false;
if (intel_uncore_unclaimed_mmio(dev_priv))
DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 770305bdeabb..f44027f6e5e1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2533,7 +2533,7 @@ struct drm_i915_private {
bool distrust_bios_wm;
} wm;
 
-   struct i915_runtime_pm pm;
+   struct i915_runtime_pm runtime_pm;
 
struct {
bool initialized;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index dc91b32d699e..653fb69e7ecb 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1674,8 +1674,8 @@ static void i915_capture_gen_state(struct 
drm_i915_private *dev_priv,
   struct i915_gpu_state *error)
 {
error->awake = dev_priv->gt.awake;
-   error->wakelock = atomic_read(_priv->pm.wakeref_count);
-   error->suspended = dev_priv->pm.suspended;
+   error->wakelock = atomic_read(_priv->runtime_pm.wakeref_count);
+   error->suspended = dev_priv->runtime_pm.suspended;
 
error->iommu = -1;
 #ifdef CONFIG_INTEL_IOMMU
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 3736290f2d0c..915c5b9dc547 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4173,7 +4173,7 @@ int intel_irq_install(struct drm_i915_private *dev_priv)
 * interrupts as enabled _before_ actually enabling them to avoid
 * special cases in our ordering checks.
 */
-   dev_priv->pm.irqs_enabled = true;
+   dev_priv->runtime_pm.irqs_enabled = true;
 
return drm_irq_install(_priv->drm, dev_priv->drm.pdev->irq);
 }
@@ -4189,7 +4189,7 @@ void intel_irq_uninstall(struct drm_i915_private 
*dev_priv)
 {
drm_irq_uninstall(_priv->drm);
intel_hpd_cancel_work(dev_priv);
-   dev_priv->pm.irqs_enabled = false;
+   dev_priv->runtime_pm.irqs_enabled = false;
 }
 
 /**
@@ -4202,7 +4202,7 @@ void intel_irq_uninstall(struct drm_i915_private 
*dev_priv)
 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
 {
dev_priv->drm.driver->irq_uninstall(_priv->drm);
-   dev_priv->pm.irqs_enabled = false;
+   dev_priv->runtime_pm.irqs_enabled = false;
synchronize_irq(dev_priv->drm.irq);
 }
 
@@ -4215,7 +4215,7 @@ void 

[Intel-gfx] [CI 12/12] drm/i915: Introduce separate status variable for RC6 and LLC ring frequency setup

[Chris Wilson]

From: Sagar Arun Kamble 

Defined new struct intel_rc6 to hold RC6 specific state and
intel_ring_pstate to hold ring specific state.

v2: s/intel_ring_pstate/intel_llc_pstate. Removed checks from
autoenable_* functions. (Chris)

Signed-off-by: Sagar Arun Kamble 
Cc: Imre Deak 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Cc: Radoslaw Szwichtenberg 
Reviewed-by: Chris Wilson 
Link: 
https://patchwork.freedesktop.org/patch/msgid/1507360055-19948-13-git-send-email-sagar.a.kam...@intel.com
Acked-by: Imre Deak 
Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_drv.c |  2 +-
 drivers/gpu/drm/i915/i915_drv.h | 10 
 drivers/gpu/drm/i915/intel_pm.c | 54 -
 3 files changed, 43 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index f3ac1f45e154..f1e651703764 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2502,7 +2502,7 @@ static int intel_runtime_suspend(struct device *kdev)
struct drm_i915_private *dev_priv = to_i915(dev);
int ret;
 
-   if (WARN_ON_ONCE(!(dev_priv->gt_pm.rps.enabled && intel_rc6_enabled(
+   if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && intel_rc6_enabled(
return -ENODEV;
 
if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 521348ee7242..6bbc4b83aa0a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1365,8 +1365,18 @@ struct intel_rps {
struct intel_rps_ei ei;
 };
 
+struct intel_rc6 {
+   bool enabled;
+};
+
+struct intel_llc_pstate {
+   bool enabled;
+};
+
 struct intel_gen6_power_mgmt {
struct intel_rps rps;
+   struct intel_rc6 rc6;
+   struct intel_llc_pstate llc_pstate;
struct delayed_work autoenable_work;
 };
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a4d431d3980a..2fcff9788b6f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7964,7 +7964,8 @@ void intel_suspend_gt_powersave(struct drm_i915_private 
*dev_priv)
 
 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
 {
-   dev_priv->gt_pm.rps.enabled = true; /* force disabling */
+   dev_priv->gt_pm.rps.enabled = true; /* force RPS disabling */
+   dev_priv->gt_pm.rc6.enabled = true; /* force RC6 disabling */
intel_disable_gt_powersave(dev_priv);
 
gen6_reset_rps_interrupts(dev_priv);
@@ -7974,13 +7975,21 @@ static inline void intel_disable_llc_pstate(struct 
drm_i915_private *i915)
 {
lockdep_assert_held(>pcu_lock);
 
+   if (!i915->gt_pm.llc_pstate.enabled)
+   return;
+
/* Currently there is no HW configuration to be done to disable. */
+
+   i915->gt_pm.llc_pstate.enabled = false;
 }
 
 static void intel_disable_rc6(struct drm_i915_private *dev_priv)
 {
lockdep_assert_held(_priv->pcu_lock);
 
+   if (!dev_priv->gt_pm.rc6.enabled)
+   return;
+
if (INTEL_GEN(dev_priv) >= 9)
gen9_disable_rc6(dev_priv);
else if (IS_CHERRYVIEW(dev_priv))
@@ -7989,12 +7998,17 @@ static void intel_disable_rc6(struct drm_i915_private 
*dev_priv)
valleyview_disable_rc6(dev_priv);
else if (INTEL_GEN(dev_priv) >= 6)
gen6_disable_rc6(dev_priv);
+
+   dev_priv->gt_pm.rc6.enabled = false;
 }
 
 static void intel_disable_rps(struct drm_i915_private *dev_priv)
 {
lockdep_assert_held(_priv->pcu_lock);
 
+   if (!dev_priv->gt_pm.rps.enabled)
+   return;
+
if (INTEL_GEN(dev_priv) >= 9)
gen9_disable_rps(dev_priv);
else if (IS_CHERRYVIEW(dev_priv))
@@ -8005,15 +8019,12 @@ static void intel_disable_rps(struct drm_i915_private 
*dev_priv)
gen6_disable_rps(dev_priv);
else if (IS_IRONLAKE_M(dev_priv))
ironlake_disable_drps(dev_priv);
+
+   dev_priv->gt_pm.rps.enabled = false;
 }
 
 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
 {
-   struct intel_rps *rps = _priv->gt_pm.rps;
-
-   if (!READ_ONCE(rps->enabled))
-   return;
-
mutex_lock(_priv->pcu_lock);
 
intel_disable_rc6(dev_priv);
@@ -8021,7 +8032,6 @@ void intel_disable_gt_powersave(struct drm_i915_private 
*dev_priv)
if (HAS_LLC(dev_priv))
intel_disable_llc_pstate(dev_priv);
 
-   rps->enabled = false;
mutex_unlock(_priv->pcu_lock);
 }
 
@@ -8029,13 +8039,21 @@ static inline void intel_enable_llc_pstate(struct 
drm_i915_private *i915)
 {
lockdep_assert_held(>pcu_lock);
 
+  

[Intel-gfx] [CI 09/12] drm/i915: Rename intel_enable_rc6 to intel_rc6_enabled

[Chris Wilson]

From: Sagar Arun Kamble 

This function gives the status of RC6, whether disabled or if
enabled then which state. intel_enable_rc6 will be used for
enabling RC6 in the next patch.

v2: Rebase.

v3: Rebase.

Signed-off-by: Sagar Arun Kamble 
Cc: Chris Wilson 
Cc: Imre Deak 
Cc: Joonas Lahtinen 
Reviewed-by: Radoslaw Szwichtenberg  #1
Reviewed-by: Ewelina Musial  #1
Reviewed-by: Chris Wilson 
Link: 
https://patchwork.freedesktop.org/patch/msgid/1507360055-19948-10-git-send-email-sagar.a.kam...@intel.com
Acked-by: Imre Deak 
Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_drv.c   |  2 +-
 drivers/gpu/drm/i915/i915_sysfs.c |  2 +-
 drivers/gpu/drm/i915/intel_drv.h  |  2 +-
 drivers/gpu/drm/i915/intel_guc.c  |  3 ++-
 drivers/gpu/drm/i915/intel_pm.c   | 12 ++--
 5 files changed, 11 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9b8a19149154..f3ac1f45e154 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2502,7 +2502,7 @@ static int intel_runtime_suspend(struct device *kdev)
struct drm_i915_private *dev_priv = to_i915(dev);
int ret;
 
-   if (WARN_ON_ONCE(!(dev_priv->gt_pm.rps.enabled && intel_enable_rc6(
+   if (WARN_ON_ONCE(!(dev_priv->gt_pm.rps.enabled && intel_rc6_enabled(
return -ENODEV;
 
if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c 
b/drivers/gpu/drm/i915/i915_sysfs.c
index 0a57f9867f7f..791759f632e1 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -49,7 +49,7 @@ static u32 calc_residency(struct drm_i915_private *dev_priv,
 static ssize_t
 show_rc6_mask(struct device *kdev, struct device_attribute *attr, char *buf)
 {
-   return snprintf(buf, PAGE_SIZE, "%x\n", intel_enable_rc6());
+   return snprintf(buf, PAGE_SIZE, "%x\n", intel_rc6_enabled());
 }
 
 static ssize_t
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 53acfc475e35..cdda0a84babe 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1903,7 +1903,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc 
*intel_crtc,
  struct intel_crtc_state *cstate);
 void intel_init_ipc(struct drm_i915_private *dev_priv);
 void intel_enable_ipc(struct drm_i915_private *dev_priv);
-static inline int intel_enable_rc6(void)
+static inline int intel_rc6_enabled(void)
 {
return i915_modparams.enable_rc6;
 }
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index bbe4c328e9fd..9e18c4fb9909 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -137,7 +137,8 @@ int intel_guc_sample_forcewake(struct intel_guc *guc)
 
action[0] = INTEL_GUC_ACTION_SAMPLE_FORCEWAKE;
/* WaRsDisableCoarsePowerGating:skl,bxt */
-   if (!intel_enable_rc6() || NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
+   if (!intel_rc6_enabled() ||
+   NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
action[1] = 0;
else
/* bit 0 and 1 are for Render and Media domain separately */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9097489e1993..16f8afbbc5db 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6625,7 +6625,7 @@ static void gen9_enable_rc6(struct drm_i915_private 
*dev_priv)
I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
 
/* 3a: Enable RC6 */
-   if (intel_enable_rc6() & INTEL_RC6_ENABLE)
+   if (intel_rc6_enabled() & INTEL_RC6_ENABLE)
rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
@@ -6671,7 +6671,7 @@ static void gen8_enable_rc6(struct drm_i915_private 
*dev_priv)
I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
 
/* 3: Enable RC6 */
-   if (intel_enable_rc6() & INTEL_RC6_ENABLE)
+   if (intel_rc6_enabled() & INTEL_RC6_ENABLE)
rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
intel_print_rc6_info(dev_priv, rc6_mask);
 
@@ -6766,7 +6766,7 @@ static void gen6_enable_rc6(struct drm_i915_private 
*dev_priv)
I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
 
/* Check if we are enabling RC6 */
-   rc6_mode = intel_enable_rc6();
+   rc6_mode = intel_rc6_enabled();
if (rc6_mode & INTEL_RC6_ENABLE)
rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
 
@@ -7268,7 +7268,7 @@ static void 

[Intel-gfx] [CI 10/12] drm/i915: Create generic function to setup LLC ring frequency table

[Chris Wilson]

From: Sagar Arun Kamble 

Prepared intel_update_ring_freq function to setup ring frequency
for applicable platforms determined by macro HAS_LLC.

v2: Replaced NEEDS_RING_FREQ_UPDATE with HAS_LLC macro. (Chris)
Added check while calling from intel_enable_gt_powersave.

v3: s/intel_update_ring_freq/intel_enable_llc_pstate and created
new placeholder function intel_disable_llc_pstate. (Chris)

Signed-off-by: Sagar Arun Kamble 
Cc: Imre Deak 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Cc: Radoslaw Szwichtenberg 
Reviewed-by: Chris Wilson 
Link: 
https://patchwork.freedesktop.org/patch/msgid/1507360055-19948-11-git-send-email-sagar.a.kam...@intel.com
Acked-by: Imre Deak 
Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_pm.c | 24 
 1 file changed, 20 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 16f8afbbc5db..238d405e2fb2 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7982,6 +7982,13 @@ void intel_sanitize_gt_powersave(struct drm_i915_private 
*dev_priv)
gen6_reset_rps_interrupts(dev_priv);
 }
 
+static inline void intel_disable_llc_pstate(struct drm_i915_private *i915)
+{
+   lockdep_assert_held(>pcu_lock);
+
+   /* Currently there is no HW configuration to be done to disable. */
+}
+
 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
 {
struct intel_rps *rps = _priv->gt_pm.rps;
@@ -8007,10 +8014,20 @@ void intel_disable_gt_powersave(struct drm_i915_private 
*dev_priv)
ironlake_disable_drps(dev_priv);
}
 
+   if (HAS_LLC(dev_priv))
+   intel_disable_llc_pstate(dev_priv);
+
rps->enabled = false;
mutex_unlock(_priv->pcu_lock);
 }
 
+static inline void intel_enable_llc_pstate(struct drm_i915_private *i915)
+{
+   lockdep_assert_held(>pcu_lock);
+
+   gen6_update_ring_freq(i915);
+}
+
 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
 {
struct intel_rps *rps = _priv->gt_pm.rps;
@@ -8036,21 +8053,20 @@ void intel_enable_gt_powersave(struct drm_i915_private 
*dev_priv)
} else if (INTEL_GEN(dev_priv) >= 9) {
gen9_enable_rc6(dev_priv);
gen9_enable_rps(dev_priv);
-   if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
-   gen6_update_ring_freq(dev_priv);
} else if (IS_BROADWELL(dev_priv)) {
gen8_enable_rc6(dev_priv);
gen8_enable_rps(dev_priv);
-   gen6_update_ring_freq(dev_priv);
} else if (INTEL_GEN(dev_priv) >= 6) {
gen6_enable_rc6(dev_priv);
gen6_enable_rps(dev_priv);
-   gen6_update_ring_freq(dev_priv);
} else if (IS_IRONLAKE_M(dev_priv)) {
ironlake_enable_drps(dev_priv);
intel_init_emon(dev_priv);
}
 
+   if (HAS_LLC(dev_priv))
+   intel_enable_llc_pstate(dev_priv);
+
WARN_ON(rps->max_freq < rps->min_freq);
WARN_ON(rps->idle_freq > rps->max_freq);
 
-- 
2.15.0.rc0

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [CI 11/12] drm/i915: Create generic functions to control RC6, RPS

[Chris Wilson]

From: Sagar Arun Kamble 

Prepared generic functions intel_enable_rc6, intel_disable_rc6,
intel_enable_rps and intel_disable_rps functions to setup RC6/RPS
based on platforms.

v2: Make intel_enable/disable_rc6/rps static. (Chris)

v3: Added lockdep_assert_held(dev_priv->pcu_lock) in new generic
functions. (Chris)
Removed WARN_ON(_priv->pcu_lock) from lower level functions as generic
function now has lockdep_assert. Rebase.

Signed-off-by: Sagar Arun Kamble 
Cc: Imre Deak 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Cc: Radoslaw Szwichtenberg 
Reviewed-by: Chris Wilson 
Link: 
https://patchwork.freedesktop.org/patch/msgid/1507360055-19948-12-git-send-email-sagar.a.kam...@intel.com
Acked-by: Imre Deak 
Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_pm.c | 116 
 1 file changed, 70 insertions(+), 46 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 238d405e2fb2..a4d431d3980a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6731,8 +6731,6 @@ static void gen6_enable_rc6(struct drm_i915_private 
*dev_priv)
int rc6_mode;
int ret;
 
-   WARN_ON(!mutex_is_locked(_priv->pcu_lock));
-
I915_WRITE(GEN6_RC_STATE, 0);
 
/* Clear the DBG now so we don't confuse earlier errors */
@@ -6805,8 +6803,6 @@ static void gen6_enable_rc6(struct drm_i915_private 
*dev_priv)
 
 static void gen6_enable_rps(struct drm_i915_private *dev_priv)
 {
-   WARN_ON(!mutex_is_locked(_priv->pcu_lock));
-
/* Here begins a magic sequence of register writes to enable
 * auto-downclocking.
 *
@@ -7227,8 +7223,6 @@ static void cherryview_enable_rc6(struct drm_i915_private 
*dev_priv)
enum intel_engine_id id;
u32 gtfifodbg, rc6_mode = 0, pcbr;
 
-   WARN_ON(!mutex_is_locked(_priv->pcu_lock));
-
gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
 GT_FIFO_FREE_ENTRIES_CHV);
if (gtfifodbg) {
@@ -7281,8 +7275,6 @@ static void cherryview_enable_rps(struct drm_i915_private 
*dev_priv)
 {
u32 val;
 
-   WARN_ON(!mutex_is_locked(_priv->pcu_lock));
-
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 
/* 1: Program defaults and thresholds for RPS*/
@@ -7327,8 +7319,6 @@ static void valleyview_enable_rc6(struct drm_i915_private 
*dev_priv)
enum intel_engine_id id;
u32 gtfifodbg, rc6_mode = 0;
 
-   WARN_ON(!mutex_is_locked(_priv->pcu_lock));
-
valleyview_check_pctx(dev_priv);
 
gtfifodbg = I915_READ(GTFIFODBG);
@@ -7374,8 +7364,6 @@ static void valleyview_enable_rps(struct drm_i915_private 
*dev_priv)
 {
u32 val;
 
-   WARN_ON(!mutex_is_locked(_priv->pcu_lock));
-
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 
I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100);
@@ -7989,31 +7977,47 @@ static inline void intel_disable_llc_pstate(struct 
drm_i915_private *i915)
/* Currently there is no HW configuration to be done to disable. */
 }
 
-void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
+static void intel_disable_rc6(struct drm_i915_private *dev_priv)
 {
-   struct intel_rps *rps = _priv->gt_pm.rps;
+   lockdep_assert_held(_priv->pcu_lock);
 
-   if (!READ_ONCE(rps->enabled))
-   return;
+   if (INTEL_GEN(dev_priv) >= 9)
+   gen9_disable_rc6(dev_priv);
+   else if (IS_CHERRYVIEW(dev_priv))
+   cherryview_disable_rc6(dev_priv);
+   else if (IS_VALLEYVIEW(dev_priv))
+   valleyview_disable_rc6(dev_priv);
+   else if (INTEL_GEN(dev_priv) >= 6)
+   gen6_disable_rc6(dev_priv);
+}
 
-   mutex_lock(_priv->pcu_lock);
+static void intel_disable_rps(struct drm_i915_private *dev_priv)
+{
+   lockdep_assert_held(_priv->pcu_lock);
 
-   if (INTEL_GEN(dev_priv) >= 9) {
-   gen9_disable_rc6(dev_priv);
+   if (INTEL_GEN(dev_priv) >= 9)
gen9_disable_rps(dev_priv);
-   } else if (IS_CHERRYVIEW(dev_priv)) {
-   cherryview_disable_rc6(dev_priv);
+   else if (IS_CHERRYVIEW(dev_priv))
cherryview_disable_rps(dev_priv);
-   } else if (IS_VALLEYVIEW(dev_priv)) {
-   valleyview_disable_rc6(dev_priv);
+   else if (IS_VALLEYVIEW(dev_priv))
valleyview_disable_rps(dev_priv);
-   } else if (INTEL_GEN(dev_priv) >= 6) {
-   gen6_disable_rc6(dev_priv);
+   else if (INTEL_GEN(dev_priv) >= 6)
gen6_disable_rps(dev_priv);
-   }  else if (IS_IRONLAKE_M(dev_priv)) {
+   else if (IS_IRONLAKE_M(dev_priv))
  

[Intel-gfx] [CI 05/12] drm/i915: Separate RPS and RC6 handling for CHV

[Chris Wilson]

From: Sagar Arun Kamble 

This patch separates enable/disable of RC6 and RPS for CHV.

v2: Fixed comment.

Signed-off-by: Sagar Arun Kamble 
Cc: Imre Deak 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Reviewed-by: Radoslaw Szwichtenberg 
Reviewed-by: Chris Wilson 
Link: 
https://patchwork.freedesktop.org/patch/msgid/1507360055-19948-6-git-send-email-sagar.a.kam...@intel.com
Acked-by: Imre Deak 
Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_pm.c | 30 --
 1 file changed, 24 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5fb08271b91c..4843e88a7f35 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6345,11 +6345,16 @@ static void gen6_disable_rps(struct drm_i915_private 
*dev_priv)
I915_WRITE(GEN6_RP_CONTROL, 0);
 }
 
-static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
+static void cherryview_disable_rc6(struct drm_i915_private *dev_priv)
 {
I915_WRITE(GEN6_RC_CONTROL, 0);
 }
 
+static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
+{
+   I915_WRITE(GEN6_RP_CONTROL, 0);
+}
+
 static void valleyview_disable_rc6(struct drm_i915_private *dev_priv)
 {
/* We're doing forcewake before Disabling RC6,
@@ -7199,11 +7204,11 @@ static void valleyview_cleanup_gt_powersave(struct 
drm_i915_private *dev_priv)
valleyview_cleanup_pctx(dev_priv);
 }
 
-static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
+static void cherryview_enable_rc6(struct drm_i915_private *dev_priv)
 {
struct intel_engine_cs *engine;
enum intel_engine_id id;
-   u32 gtfifodbg, val, rc6_mode = 0, pcbr;
+   u32 gtfifodbg, rc6_mode = 0, pcbr;
 
WARN_ON(!mutex_is_locked(_priv->rps.hw_lock));
 
@@ -7236,7 +7241,7 @@ static void cherryview_enable_rps(struct drm_i915_private 
*dev_priv)
/* TO threshold set to 500 us ( 0x186 * 1.28 us) */
I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
 
-   /* allows RC6 residency counter to work */
+   /* Allows RC6 residency counter to work */
I915_WRITE(VLV_COUNTER_CONTROL,
   _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
  VLV_MEDIA_RC6_COUNT_EN |
@@ -7252,7 +7257,18 @@ static void cherryview_enable_rps(struct 
drm_i915_private *dev_priv)
 
I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
 
-   /* 4 Program defaults and thresholds for RPS*/
+   intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+}
+
+static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
+{
+   u32 val;
+
+   WARN_ON(!mutex_is_locked(_priv->rps.hw_lock));
+
+   intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+
+   /* 1: Program defaults and thresholds for RPS*/
I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100);
I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
@@ -7261,7 +7277,7 @@ static void cherryview_enable_rps(struct drm_i915_private 
*dev_priv)
 
I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
 
-   /* 5: Enable RPS */
+   /* 2: Enable RPS */
I915_WRITE(GEN6_RP_CONTROL,
   GEN6_RP_MEDIA_HW_NORMAL_MODE |
   GEN6_RP_MEDIA_IS_GFX |
@@ -7958,6 +7974,7 @@ void intel_disable_gt_powersave(struct drm_i915_private 
*dev_priv)
gen9_disable_rc6(dev_priv);
gen9_disable_rps(dev_priv);
} else if (IS_CHERRYVIEW(dev_priv)) {
+   cherryview_disable_rc6(dev_priv);
cherryview_disable_rps(dev_priv);
} else if (IS_VALLEYVIEW(dev_priv)) {
valleyview_disable_rc6(dev_priv);
@@ -7988,6 +8005,7 @@ void intel_enable_gt_powersave(struct drm_i915_private 
*dev_priv)
mutex_lock(_priv->rps.hw_lock);
 
if (IS_CHERRYVIEW(dev_priv)) {
+   cherryview_enable_rc6(dev_priv);
cherryview_enable_rps(dev_priv);
} else if (IS_VALLEYVIEW(dev_priv)) {
valleyview_enable_rc6(dev_priv);
-- 
2.15.0.rc0

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[Intel-gfx] [CI 04/12] drm/i915: Separate RPS and RC6 handling for VLV

[Chris Wilson]

From: Sagar Arun Kamble 

This patch separates enable/disable of RC6 and RPS for VLV.

v2: Removed unnecessary comments about forcewakes while enabling
RC6/RPS. Added changes to output turbo control status for VLV in
i915_frequency_info.

Signed-off-by: Sagar Arun Kamble 
Cc: Imre Deak 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Reviewed-by: Radoslaw Szwichtenberg 
Reviewed-by: Chris Wilson 
Link: 
https://patchwork.freedesktop.org/patch/msgid/1507360055-19948-5-git-send-email-sagar.a.kam...@intel.com
Acked-by: Imre Deak 
Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 24 +++
 drivers/gpu/drm/i915/intel_pm.c | 61 -
 2 files changed, 51 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index a904f4e69c66..31ab92eda45d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1095,9 +1095,19 @@ static int i915_frequency_info(struct seq_file *m, void 
*unused)
seq_printf(m, "Current P-state: %d\n",
   (rgvstat & MEMSTAT_PSTATE_MASK) >> 
MEMSTAT_PSTATE_SHIFT);
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
-   u32 freq_sts;
+   u32 rpmodectl, freq_sts;
 
mutex_lock(_priv->rps.hw_lock);
+
+   rpmodectl = I915_READ(GEN6_RP_CONTROL);
+   seq_printf(m, "Video Turbo Mode: %s\n",
+  yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
+   seq_printf(m, "HW control enabled: %s\n",
+  yesno(rpmodectl & GEN6_RP_ENABLE));
+   seq_printf(m, "SW control enabled: %s\n",
+  yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
+ GEN6_RP_MEDIA_SW_MODE));
+
freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
@@ -1508,21 +1518,11 @@ static void print_rc6_res(struct seq_file *m,
 static int vlv_drpc_info(struct seq_file *m)
 {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
-   u32 rpmodectl1, rcctl1, pw_status;
+   u32 rcctl1, pw_status;
 
pw_status = I915_READ(VLV_GTLC_PW_STATUS);
-   rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
rcctl1 = I915_READ(GEN6_RC_CONTROL);
 
-   seq_printf(m, "Video Turbo Mode: %s\n",
-  yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
-   seq_printf(m, "Turbo enabled: %s\n",
-  yesno(rpmodectl1 & GEN6_RP_ENABLE));
-   seq_printf(m, "HW control enabled: %s\n",
-  yesno(rpmodectl1 & GEN6_RP_ENABLE));
-   seq_printf(m, "SW control enabled: %s\n",
-  yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
- GEN6_RP_MEDIA_SW_MODE));
seq_printf(m, "RC6 Enabled: %s\n",
   yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
GEN6_RC_CTL_EI_MODE(1;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 540e23ab51df..5fb08271b91c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6350,9 +6350,9 @@ static void cherryview_disable_rps(struct 
drm_i915_private *dev_priv)
I915_WRITE(GEN6_RC_CONTROL, 0);
 }
 
-static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
+static void valleyview_disable_rc6(struct drm_i915_private *dev_priv)
 {
-   /* we're doing forcewake before Disabling RC6,
+   /* We're doing forcewake before Disabling RC6,
 * This what the BIOS expects when going into suspend */
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 
@@ -6361,6 +6361,11 @@ static void valleyview_disable_rps(struct 
drm_i915_private *dev_priv)
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 }
 
+static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
+{
+   I915_WRITE(GEN6_RP_CONTROL, 0);
+}
+
 static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
 {
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
@@ -7283,11 +7288,11 @@ static void cherryview_enable_rps(struct 
drm_i915_private *dev_priv)
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 }
 
-static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
+static void valleyview_enable_rc6(struct drm_i915_private *dev_priv)
 {
struct intel_engine_cs *engine;
enum intel_engine_id id;
-   u32 gtfifodbg, val, rc6_mode = 0;
+   u32 gtfifodbg, 

[Intel-gfx] [CI 03/12] drm/i915: Separate RPS and RC6 handling for BDW

[Chris Wilson]

From: Sagar Arun Kamble 

This patch separates RC6 and RPS enabling for BDW.
RC6/RPS Disabling are handled through gen6 functions.
PM Programming guide recommends a sequence within forcewakes to
configure RC6, RPS and ring frequencies in sequence. With this
patch the order is still maintained.

v2: Update sequence numbers in RC6 programming and comment about
intent of reset_rps during gen8_enable_rps. (Radoslaw)

v3: Rebase.

Signed-off-by: Sagar Arun Kamble 
Cc: Imre Deak 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Reviewed-by: Radoslaw Szwichtenberg 
Reviewed-by: Chris Wilson 
Link: 
https://patchwork.freedesktop.org/patch/msgid/1507360055-19948-4-git-send-email-sagar.a.kam...@intel.com
Acked-by: Imre Deak 
Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_pm.c | 18 --
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 21a72f660e0f..540e23ab51df 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6621,7 +6621,7 @@ static void gen9_enable_rc6(struct drm_i915_private 
*dev_priv)
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 }
 
-static void gen8_enable_rps(struct drm_i915_private *dev_priv)
+static void gen8_enable_rc6(struct drm_i915_private *dev_priv)
 {
struct intel_engine_cs *engine;
enum intel_engine_id id;
@@ -6630,7 +6630,7 @@ static void gen8_enable_rps(struct drm_i915_private 
*dev_priv)
/* 1a: Software RC state - RC0 */
I915_WRITE(GEN6_RC_STATE, 0);
 
-   /* 1c & 1d: Get forcewake during program sequence. Although the driver
+   /* 1b: Get forcewake during program sequence. Although the driver
 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 
@@ -6655,7 +6655,14 @@ static void gen8_enable_rps(struct drm_i915_private 
*dev_priv)
GEN7_RC_CTL_TO_MODE |
rc6_mask);
 
-   /* 4 Program defaults and thresholds for RPS*/
+   intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+}
+
+static void gen8_enable_rps(struct drm_i915_private *dev_priv)
+{
+   intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+
+   /* 1 Program defaults and thresholds for RPS*/
I915_WRITE(GEN6_RPNSWREQ,
   HSW_FREQUENCY(dev_priv->rps.rp1_freq));
I915_WRITE(GEN6_RC_VIDEO_FREQ,
@@ -6675,7 +6682,7 @@ static void gen8_enable_rps(struct drm_i915_private 
*dev_priv)
 
I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
 
-   /* 5: Enable RPS */
+   /* 2: Enable RPS */
I915_WRITE(GEN6_RP_CONTROL,
   GEN6_RP_MEDIA_TURBO |
   GEN6_RP_MEDIA_HW_NORMAL_MODE |
@@ -6684,8 +6691,6 @@ static void gen8_enable_rps(struct drm_i915_private 
*dev_priv)
   GEN6_RP_UP_BUSY_AVG |
   GEN6_RP_DOWN_IDLE_AVG);
 
-   /* 6: Ring frequency + overclocking (our driver does this later */
-
reset_rps(dev_priv, gen6_set_rps);
 
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
@@ -7976,6 +7981,7 @@ void intel_enable_gt_powersave(struct drm_i915_private 
*dev_priv)
if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
gen6_update_ring_freq(dev_priv);
} else if (IS_BROADWELL(dev_priv)) {
+   gen8_enable_rc6(dev_priv);
gen8_enable_rps(dev_priv);
gen6_update_ring_freq(dev_priv);
} else if (INTEL_GEN(dev_priv) >= 6) {
-- 
2.15.0.rc0

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[Intel-gfx] [CI 02/12] drm/i915: Remove superfluous IS_BDW checks and non-BDW changes from gen8_enable_rps

[Chris Wilson]

From: Sagar Arun Kamble 

This patch removes all IS_BROADWELL checks and non-BDW changes from
gen8_enable_rps as it is called only for BROADWELL.

Suggested-by: Chris Wilson 
Signed-off-by: Sagar Arun Kamble 
Cc: Imre Deak 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Cc: Radoslaw Szwichtenberg 
Reviewed-by: Chris Wilson 
Link: 
https://patchwork.freedesktop.org/patch/msgid/1507360055-19948-3-git-send-email-sagar.a.kam...@intel.com
Acked-by: Imre Deak 
Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_pm.c | 17 +
 1 file changed, 5 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index dfa9afe9cb61..21a72f660e0f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6644,23 +6644,16 @@ static void gen8_enable_rps(struct drm_i915_private 
*dev_priv)
for_each_engine(engine, dev_priv, id)
I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
I915_WRITE(GEN6_RC_SLEEP, 0);
-   if (IS_BROADWELL(dev_priv))
-   I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
-   else
-   I915_WRITE(GEN6_RC6_THRESHOLD, 5); /* 50/125ms per EI */
+   I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
 
/* 3: Enable RC6 */
if (intel_enable_rc6() & INTEL_RC6_ENABLE)
rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
intel_print_rc6_info(dev_priv, rc6_mask);
-   if (IS_BROADWELL(dev_priv))
-   I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
-   GEN7_RC_CTL_TO_MODE |
-   rc6_mask);
-   else
-   I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
-   GEN6_RC_CTL_EI_MODE(1) |
-   rc6_mask);
+
+   I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
+   GEN7_RC_CTL_TO_MODE |
+   rc6_mask);
 
/* 4 Program defaults and thresholds for RPS*/
I915_WRITE(GEN6_RPNSWREQ,
-- 
2.15.0.rc0

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[Intel-gfx] ✓ Fi.CI.BAT: success for igt/syncobj_wait: Don't close the timeline early in wait_snapshot

[Patchwork]

== Series Details ==

Series: igt/syncobj_wait: Don't close the timeline early in wait_snapshot
URL   : https://patchwork.freedesktop.org/series/31679/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
d7c88290ab6a8393dc341b30c7fb5e27d2952901 syncobj: Add a test for 
SYNCOBJ_CREATE_SIGNALED

with latest DRM-Tip kernel build CI_DRM_3208
c880c004bb05 drm-tip: 2017y-10m-10d-20h-31m-39s UTC integration manifest

No testlist changes.

Test chamelium:
Subgroup dp-crc-fast:
pass   -> DMESG-FAIL (fi-kbl-7500u) fdo#102514

fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:454s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:468s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:395s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:578s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:289s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:525s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:525s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:543s
fi-byt-n2820 total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  
time:534s
fi-cfl-s total:289  pass:253  dwarn:4   dfail:0   fail:0   skip:32  
time:571s
fi-cnl-y total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:642s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:435s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:602s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:439s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:421s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:465s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:499s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:474s
fi-kbl-7500u total:289  pass:263  dwarn:1   dfail:1   fail:0   skip:24  
time:502s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:588s
fi-kbl-7567u total:289  pass:265  dwarn:4   dfail:0   fail:0   skip:20  
time:489s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:594s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:480s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:656s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:514s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:477s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:586s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:440s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_319/
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[Intel-gfx] ✓ Fi.CI.BAT: success for Fix HDMI as dual display on CNL.

[Patchwork]

== Series Details ==

Series: Fix HDMI as dual display on CNL.
URL   : https://patchwork.freedesktop.org/series/31352/
State : success

== Summary ==

Series 31352v1 Fix HDMI as dual display on CNL.
https://patchwork.freedesktop.org/api/1.0/series/31352/revisions/1/mbox/

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> DMESG-WARN (fi-byt-j1900) fdo#101705 +1

fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:459s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:477s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:392s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:580s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:288s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:525s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:523s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:544s
fi-byt-n2820 total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  
time:530s
fi-cfl-s total:289  pass:253  dwarn:4   dfail:0   fail:0   skip:32  
time:564s
fi-cnl-y total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:628s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:430s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:597s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:442s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:419s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:462s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:512s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:474s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:501s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:584s
fi-kbl-7567u total:289  pass:265  dwarn:4   dfail:0   fail:0   skip:20  
time:491s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:596s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:662s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:480s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:662s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:534s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:520s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:476s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:582s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:437s

d82f454de90a5b0de9a40159ebda54ea4eeafce2 drm-tip: 2017y-10m-10d-18h-40m-34s UTC 
integration manifest
cd5c6e8b0aac drm/i915/cnl: Fix PLL initialization for HDMI.
49daa1cfe60d drm/i915/cnl: Fix PLL mapping.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5983/
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Re: [Intel-gfx] [RFC PATCH 00/11] Refactor HW workaround code

[Oscar Mateo]

On 10/10/2017 01:10 PM, Chris Wilson wrote:

Quoting Oscar Mateo (2017-10-10 19:24:18)

* Above method can be used to create a complete logical context with
engine context populated by the hardware. This Logical context can be
used as an Golden Context Image or template for subsequently created
contexts.

It's the template part we want (sending down a pair of contexts to be
executed in sequence is problematic).


Ahh, I see.

Notice that what the BSpec suggests is to send the null state BB only 
once (for the kernel default context image) and then copy (memcpy or 
DMA) that context image over all new contexts that get created. That 
takes care of the problem with nonpriv registers, because absolutely 
everything inside the context image get blasted with a clean copy everytime.



The current fire are the nonpriv registers that are leaking across the
proto-context, i.e. mesa does LRI that get inherited into a libva
context. Adding those to the context image requires approx a hundred
LRI, so a not impossible task to proofread (esp. as many are just
setting register groups, e.g. the 32 CS_GPR registers, to 0).

But it is still a task that we need to maintain that list of nonpriv
registers.


or, alternatively, follow the BSpec's "template" approach, with or 
without null state BB



(State outside of the nonpriv that doesn't have a defined
default, cannot be either modified by userspace or assume to have any
particular value.)
-Chris

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Re: [Intel-gfx] [PATCH 00/12] radix-tree: split out struct radix_tree_root out to

[Leon Romanovsky]

On Mon, Oct 09, 2017 at 01:10:01AM +0900, Masahiro Yamada wrote:

<...>
>
> By splitting out the radix_tree_root definition,
> we can reduce the header file dependency.
>
> Reducing the header dependency will help for speeding the kernel
> build, suppressing unnecessary recompile of objects during
> git-bisect'ing, etc.

If we judge by the diffstat of this series, there won't be any
visible change in anything mentioned above.

<...>

>
> Masahiro Yamada (12):
>   radix-tree: replace  with 
>   radix-tree: split struct radix_tree_root to 
>   irqdomain: replace  with 
>   writeback: replace  with 
>   iocontext.h: replace  with
> 
>   fs: replace  with 
>   blkcg: replace  with 
>   fscache: include 
>   sh: intc: replace  with 
>   net/mlx4: replace  with 
>   net/mlx5: replace  with 
>   drm/i915: replace  with 
>
>  drivers/gpu/drm/i915/i915_gem.c|  1 +
>  drivers/gpu/drm/i915/i915_gem_context.c|  1 +
>  drivers/gpu/drm/i915/i915_gem_context.h|  2 +-
>  drivers/gpu/drm/i915/i915_gem_execbuffer.c |  1 +
>  drivers/gpu/drm/i915/i915_gem_object.h |  1 +
>  drivers/net/ethernet/mellanox/mlx4/cq.c|  1 +
>  drivers/net/ethernet/mellanox/mlx4/mlx4.h  |  2 +-
>  drivers/net/ethernet/mellanox/mlx4/qp.c|  1 +
>  drivers/net/ethernet/mellanox/mlx4/srq.c   |  1 +
>  drivers/sh/intc/internals.h|  2 +-
>  include/linux/backing-dev-defs.h   |  2 +-
>  include/linux/blk-cgroup.h |  2 +-
>  include/linux/fs.h |  2 +-
>  include/linux/fscache.h|  1 +
>  include/linux/iocontext.h  |  2 +-
>  include/linux/irqdomain.h  |  2 +-
>  include/linux/mlx4/device.h|  2 +-
>  include/linux/mlx4/qp.h|  1 +
>  include/linux/mlx5/driver.h|  2 +-
>  include/linux/mlx5/qp.h|  1 +
>  include/linux/radix-tree-root.h| 24 
>  include/linux/radix-tree.h |  8 ++--
>  22 files changed, 46 insertions(+), 16 deletions(-)
>  create mode 100644 include/linux/radix-tree-root.h
>
> --
> 2.7.4
>


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Re: [Intel-gfx] [PATCH 00/12] radix-tree: split out struct radix_tree_root out to

[Matthew Wilcox]

On Tue, Oct 10, 2017 at 09:56:22PM +0900, Masahiro Yamada wrote:
> One refactoring alone does not produce much benefits,
> but making continuous efforts will disentangle the knotted threads.
> Of course, this might be a pipe dream...

A lot of people have had that dream, and some of those refactoring
efforts have proven worthwhile.  But it's not a dream without costs;
your refactoring will conflict with other changes.  I don't think the
benefit here is high enough to pursue this edition of the dream.
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Re: [Intel-gfx] [PATCH 00/12] radix-tree: split out struct radix_tree_root out to

[Leon Romanovsky]

On Mon, Oct 09, 2017 at 02:58:58PM +0900, Masahiro Yamada wrote:
> 2017-10-09 3:52 GMT+09:00 Leon Romanovsky :
> > On Mon, Oct 09, 2017 at 01:10:01AM +0900, Masahiro Yamada wrote:
> >
> > <...>
> >>
> >> By splitting out the radix_tree_root definition,
> >> we can reduce the header file dependency.
> >>
> >> Reducing the header dependency will help for speeding the kernel
> >> build, suppressing unnecessary recompile of objects during
> >> git-bisect'ing, etc.
> >
> > If we judge by the diffstat of this series, there won't be any
> > visible change in anything mentioned above.
>
>
> Of course, judging by the diffstat is wrong.
>

I'm more than happy to be wrong and you for sure can help me.
Can you provide any quantitative support of your claims?

Thanks

>
>
> --
> Best Regards
> Masahiro Yamada
> --
> To unsubscribe from this list: send the line "unsubscribe linux-rdma" in
> the body of a message to majord...@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


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Re: [Intel-gfx] [PATCH 00/12] radix-tree: split out struct radix_tree_root out to

[Matthew Wilcox]

On Mon, Oct 09, 2017 at 01:10:01AM +0900, Masahiro Yamada wrote:
> Reducing the header dependency will help for speeding the kernel
> build, suppressing unnecessary recompile of objects during
> git-bisect'ing, etc.

Well, does it?  You could provide measurements showing before/after
time to compile, or time to recompile after touching a header file that
is included by radix-tree.h and not by radix-tree-root.h.

Look at the files included (never mind the transitively included files):

#include 
#include 
#include 
#include 
#include 
#include 
#include 
#include 

These are not exactly rare files to be included.  My guess is that most
of the files in the kernel end up depending on these files *anyway*, either
directly or through some path that isn't the radix tree.
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Re: [Intel-gfx] [PATCH 11/14] drm/i915: Upscale scaler max scale for NV12

[Srinivas, Vidya]

> -Original Message-
> From: Kumar, Mahesh1
> Sent: Tuesday, October 10, 2017 7:35 PM
> To: Srinivas, Vidya ; intel-
> g...@lists.freedesktop.org
> Cc: Shankar, Uma ; Konduru, Chandra
> ; Kamath, Sunil ;
> Maiti, Nabendu Bikash 
> Subject: Re: [PATCH 11/14] drm/i915: Upscale scaler max scale for NV12
> 
> 
> 
> On Tuesday 10 October 2017 05:47 PM, Vidya Srinivas wrote:
> > From: Chandra Konduru 
> >
> > This patch updates scaler max limit support for NV12
> >
> > v2: Rebased (me)
> >
> > v3: Rebased (me)
> >
> > v4: Missed the Tested-by/Reviewed-by in the previous series
> > Adding the same to commit message in this version.
> >
> > v5: Addressed review comments from Ville and rebased
> > - calculation of max_scale to be made
> > less convoluted by splitting it up a bit
> > - Indentation errors to be fixed in the series
> >
> > v6: Rebased (me)
> > Fixed review comments from Paauwe, Bob J
> > Previous version, where a split of calculation
> > was done, was wrong. Fixed that issue here.
> >
> > v7: Rebased (me)
> >
> > v8: Rebased (me)
> >
> > Tested-by: Clinton Taylor 
> > Reviewed-by: Clinton Taylor 
> > Signed-off-by: Chandra Konduru 
> > Signed-off-by: Nabendu Maiti 
> > Signed-off-by: Vidya Srinivas 
> > ---
> >   drivers/gpu/drm/i915/intel_display.c | 33 +++---
> ---
> >   drivers/gpu/drm/i915/intel_drv.h |  3 ++-
> >   drivers/gpu/drm/i915/intel_sprite.c  |  3 ++-
> >   3 files changed, 27 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index a10bbe8..f71a704 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -3472,6 +3472,8 @@ static u32 skl_plane_ctl_format(uint32_t
> pixel_format)
> > return PLANE_CTL_FORMAT_YUV422 |
> PLANE_CTL_YUV422_UYVY;
> > case DRM_FORMAT_VYUY:
> > return PLANE_CTL_FORMAT_YUV422 |
> PLANE_CTL_YUV422_VYUY;
> > +   case DRM_FORMAT_NV12:
> > +   return PLANE_CTL_FORMAT_NV12;
> > default:
> > MISSING_CASE(pixel_format);
> > }
> > @@ -4727,7 +4729,8 @@ static void cpt_verify_modeset(struct
> drm_device *dev, int pipe)
> >   static int
> >   skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
> >   unsigned int scaler_user, int *scaler_id,
> > - int src_w, int src_h, int dst_w, int dst_h)
> > + int src_w, int src_h, int dst_w, int dst_h,
> > + uint32_t pixel_format)
> >   {
> > struct intel_crtc_scaler_state *scaler_state =
> > _state->scaler_state;
> > @@ -4743,7 +4746,8 @@ static void cpt_verify_modeset(struct
> drm_device *dev, int pipe)
> >  * the 90/270 degree plane rotation cases (to match the
> >  * GTT mapping), hence no need to account for rotation here.
> >  */
> > -   need_scaling = src_w != dst_w || src_h != dst_h;
> > +   need_scaling = src_w != dst_w || src_h != dst_h ||
> > +   (pixel_format == DRM_FORMAT_NV12);
> IMHO keep nv12 check separate from rest of src/dst_w/h checks.
> >
> > if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
> > need_scaling = true;
> > @@ -4822,7 +4826,7 @@ int skl_update_scaler_crtc(struct
> intel_crtc_state *state)
> > return skl_update_scaler(state, !state->base.active,
> SKL_CRTC_INDEX,
> > >scaler_state.scaler_id,
> > state->pipe_src_w, state->pipe_src_h,
> > -   adjusted_mode->crtc_hdisplay, adjusted_mode-
> >crtc_vdisplay);
> > +   adjusted_mode->crtc_hdisplay, adjusted_mode-
> >crtc_vdisplay, 0);
> >   }
> >
> >   /**
> > @@ -4852,7 +4856,8 @@ static int skl_update_scaler_plane(struct
> intel_crtc_state *crtc_state,
> > drm_rect_width(_state->base.src) >>
> 16,
> > drm_rect_height(_state->base.src) >>
> 16,
> > drm_rect_width(_state->base.dst),
> > -   drm_rect_height(_state->base.dst));
> > +   drm_rect_height(_state->base.dst),
> > +   fb ? fb->format->format : 0);
> >
> > if (ret || plane_state->scaler_id < 0)
> > return ret;
> > @@ -4878,6 +4883,7 @@ static int skl_update_scaler_plane(struct
> intel_crtc_state *crtc_state,
> > case DRM_FORMAT_YVYU:
> > case DRM_FORMAT_UYVY:
> > case DRM_FORMAT_VYUY:
> > +   case DRM_FORMAT_NV12:
> > break;
> > default:
> > DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported
> scaling format
> > 0x%x\n", @@ -12799,11 +12805,12 @@ static void
> 

Re: [Intel-gfx] [PATCH 12/14] drm/i915: Add NV12 as supported format for primary plane

[Srinivas, Vidya]

> -Original Message-
> From: Kumar, Mahesh1
> Sent: Tuesday, October 10, 2017 7:40 PM
> To: Srinivas, Vidya ; intel-
> g...@lists.freedesktop.org
> Cc: Shankar, Uma ; Konduru, Chandra
> ; Kamath, Sunil ;
> Maiti, Nabendu Bikash 
> Subject: Re: [PATCH 12/14] drm/i915: Add NV12 as supported format for
> primary plane
> 
> Hi,
> 
> 
> On Tuesday 10 October 2017 05:47 PM, Vidya Srinivas wrote:
> > From: Chandra Konduru 
> >
> > This patch adds NV12 to list of supported formats for primary plane
> >
> > v2: Rebased (Chandra Konduru)
> >
> > v3: Rebased (me)
> >
> > v4: Review comments by Ville addressed
> > Removed the skl_primary_formats_with_nv12 and
> > added NV12 case in existing skl_primary_formats
> >
> > v5: Rebased (me)
> >
> > v6: Missed the Tested-by/Reviewed-by in the previous series
> > Adding the same to commit message in this version.
> >
> > v7: Review comments by Ville addressed
> > Restricting the NV12 for BXT and on PIPE A and B
> > Rebased (me)
> >
> > v8: Rebased (me)
> > Modified restricting the NV12 support for both BXT and KBL.
> >
> > Tested-by: Clinton Taylor 
> > Reviewed-by: Clinton Taylor 
> > Signed-off-by: Chandra Konduru 
> > Signed-off-by: Nabendu Maiti 
> > Signed-off-by: Vidya Srinivas 
> > ---
> >   drivers/gpu/drm/i915/intel_display.c | 26 --
> >   1 file changed, 24 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index f71a704..e551f59 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -106,6 +106,22 @@
> > DRM_FORMAT_MOD_INVALID
> >   };
> >
> > +static const uint32_t nv12_primary_formats[] = {
> > +   DRM_FORMAT_C8,
> > +   DRM_FORMAT_RGB565,
> > +   DRM_FORMAT_XRGB,
> > +   DRM_FORMAT_XBGR,
> > +   DRM_FORMAT_ARGB,
> > +   DRM_FORMAT_ABGR,
> > +   DRM_FORMAT_XRGB2101010,
> > +   DRM_FORMAT_XBGR2101010,
> > +   DRM_FORMAT_YUYV,
> > +   DRM_FORMAT_YVYU,
> > +   DRM_FORMAT_UYVY,
> > +   DRM_FORMAT_VYUY,
> > +   DRM_FORMAT_NV12,
> > +};
> > +
> >   /* Cursor formats */
> >   static const uint32_t intel_cursor_formats[] = {
> > DRM_FORMAT_ARGB,
> > @@ -13256,8 +13272,14 @@ static bool
> intel_cursor_plane_format_mod_supported(struct drm_plane *plane,
> > primary->update_plane = skylake_update_primary_plane;
> > primary->disable_plane = skylake_disable_primary_plane;
> > } else if (INTEL_GEN(dev_priv) >= 9) {
> > -   intel_primary_formats = skl_primary_formats;
> > -   num_formats = ARRAY_SIZE(skl_primary_formats);
> > +   if ((IS_BROXTON(dev_priv) || IS_KABYLAKE(dev_priv)) &&
> > +   ((pipe == PIPE_A || pipe == PIPE_B))) {
> This will add support only for BXT & KBL, what about other platforms?
> Please mention that as comment or update the check.

Thank you. I tested the series currently only on BXT APL and the patches were 
also tested by other teams on KBL.
That’s why did not add changes for other platforms yet. Was planning to add 
them as enhancement.

> 
> -Mahesh
> > +   intel_primary_formats = nv12_primary_formats;
> > +   num_formats =
> ARRAY_SIZE(nv12_primary_formats);
> > +   } else {
> > +   intel_primary_formats = skl_primary_formats;
> > +   num_formats = ARRAY_SIZE(skl_primary_formats);
> > +   }
> > if (pipe < PIPE_C)
> > modifiers = skl_format_modifiers_ccs;
> > else

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Re: [Intel-gfx] [PATCH 09/14] drm/i915: Set scaler mode for NV12

[Srinivas, Vidya]

> -Original Message-
> From: Kumar, Mahesh1
> Sent: Tuesday, October 10, 2017 7:24 PM
> To: Srinivas, Vidya ; intel-
> g...@lists.freedesktop.org
> Cc: Shankar, Uma ; Konduru, Chandra
> ; Kamath, Sunil ;
> Maiti, Nabendu Bikash 
> Subject: Re: [PATCH 09/14] drm/i915: Set scaler mode for NV12
> 
> Hi,
> 
> 
> On Tuesday 10 October 2017 05:47 PM, Vidya Srinivas wrote:
> > From: Chandra Konduru 
> >
> > This patch sets appropriate scaler mode for NV12 format.
> > In this mode, skylake scaler does either chroma-upsampling or
> > chroma-upsampling and resolution scaling
> >
> > v2: Review comments from Ville addressed
> > NV12 case to be checked first for setting
> > the scaler
> >
> > v3: Rebased (me)
> >
> > v4: Rebased (me)
> >
> > v5: Missed the Tested-by/Reviewed-by in the previous series
> > Adding the same to commit message in this version.
> >
> > v6: Rebased (me)
> >
> > v7: Rebased (me)
> >
> > v8: Rebased (me)
> > Restricting the NV12 change for scaler to BXT and KBL
> > in this series.
> >
> > Tested-by: Clinton Taylor 
> > Reviewed-by: Clinton Taylor 
> > Signed-off-by: Chandra Konduru 
> > Signed-off-by: Nabendu Maiti 
> > Signed-off-by: Vidya Srinivas 
> > ---
> >   drivers/gpu/drm/i915/i915_reg.h | 1 +
> >   drivers/gpu/drm/i915/intel_atomic.c | 8 +++-
> >   2 files changed, 8 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 50e65c9..976b501 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -6607,6 +6607,7 @@ enum {
> >   #define PS_SCALER_MODE_MASK (3 << 28)
> >   #define PS_SCALER_MODE_DYN  (0 << 28)
> >   #define PS_SCALER_MODE_HQ  (1 << 28)
> > +#define PS_SCALER_MODE_NV12 (2 << 28)
> >   #define PS_PLANE_SEL_MASK  (7 << 25)
> >   #define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
> >   #define PS_FILTER_MASK (3 << 23)
> > diff --git a/drivers/gpu/drm/i915/intel_atomic.c
> > b/drivers/gpu/drm/i915/intel_atomic.c
> > index 36d4e63..606b5e3 100644
> > --- a/drivers/gpu/drm/i915/intel_atomic.c
> > +++ b/drivers/gpu/drm/i915/intel_atomic.c
> > @@ -325,7 +325,13 @@ int intel_atomic_setup_scalers(struct
> drm_i915_private *dev_priv,
> > }
> >
> > /* set scaler mode */
> > -   if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv))
> {
> > +   if ((IS_BROXTON(dev_priv) || IS_KABYLAKE(dev_priv)) &&
> > +   plane_state && plane_state->base.fb &&
> > +   plane_state->base.fb->format->format ==
> > +   DRM_FORMAT_NV12) {
> > +   scaler_state->scalers[*scaler_id].mode =
> > +   PS_SCALER_MODE_NV12;
> > +   } else if (IS_GEMINILAKE(dev_priv) ||
> IS_CANNONLAKE(dev_priv)) {
> > scaler_state->scalers[*scaler_id].mode = 0;
> IN CNL for NV12 (planar formats) bit 29 of PS_CTRL register should be set to
> 1b. This require respective change in skylake_update_primary_plane &
> skl_update_plane as well.
> please take care of that.
> better like plane_ctl calculate ps_ctl in advance only & write during
> plane_update.

Thank you. I tested the series currently only on BXT APL and the patches were 
also tested by other teams on KBL.
That’s why did not add changes for other platforms yet. Was planning to add 
them as enhancement.
> 
> -Mahesh
> > } else if (num_scalers_need == 1 && intel_crtc->pipe !=
> PIPE_C) {
> > /*

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[Intel-gfx] ✓ Fi.CI.BAT: success for igt/syncobj_wait: Avoid early close of timeline in test_wait_snapshot

[Patchwork]

== Series Details ==

Series: igt/syncobj_wait: Avoid early close of timeline in test_wait_snapshot
URL   : https://patchwork.freedesktop.org/series/31678/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
d7c88290ab6a8393dc341b30c7fb5e27d2952901 syncobj: Add a test for 
SYNCOBJ_CREATE_SIGNALED

with latest DRM-Tip kernel build CI_DRM_3207
d82f454de90a drm-tip: 2017y-10m-10d-18h-40m-34s UTC integration manifest

No testlist changes.

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> DMESG-WARN (fi-byt-j1900) fdo#101705 +1

fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:454s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:467s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:402s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:588s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:287s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:526s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:522s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:548s
fi-byt-n2820 total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  
time:524s
fi-cfl-s total:289  pass:253  dwarn:4   dfail:0   fail:0   skip:32  
time:557s
fi-cnl-y total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:647s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:441s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:599s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:439s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:418s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:464s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:511s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:483s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:504s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:581s
fi-kbl-7567u total:289  pass:265  dwarn:4   dfail:0   fail:0   skip:20  
time:485s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:591s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:662s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:472s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:659s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:536s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:577s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:478s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:580s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:437s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_318/
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Re: [Intel-gfx] [PATCH i-g-t] igt/syncobj_wait: Don't close the timeline early in wait_snapshot

[Chris Wilson]

Quoting Jason Ekstrand (2017-10-10 21:02:20)
> Closing the sw_sync timeline now signals any remaining fences upon it;
> but test_wait_snapshot requires the fence to continue to be busy so that
> the __syncobj_wait() will return with -ETIME.

Fwiw, you are not going mad as it did used to work. The change was
kernel commit ea4d5a270b57 ("dma-buf/sw_sync: force signal all
unsignaled fences on dying timeline")
-Chris
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Re: [Intel-gfx] [PATCH] i-g-t/tests: Drop gem_seqno_wrap, gem_pin, gem_hangcheck_forcewake

[Chris Wilson]

Quoting Antonio Argenziano (2017-10-10 18:12:17)
> 
> 
> On 10/10/17 01:55, Abdiel Janulgue wrote:
> > This improves the GEM tests section of I-G-T to make it more
> > suitable for CI testing
> 
> Can you provide a little more details on what is the rationale behind 
> this choice. Are the tests being removed only because they do not fit 
> the CI guidelines or is it because they do not offer any valuable coverage?

Hear, hear.

gem_seqno_wrap is defunct as the debug API withered away. The
handling of wraparound under many different workloads is tested by
gem_exec_whisper. The intention is to may seqno wrap handling a
kselftest. That hasn't happened yet, gem_exec_whisper is not run wholy
by CI, but nevertheless gem_seqno_wrap is still defunct.

gem_pin is a useful ABI I still shed a tear over. But it's time has
passed and it's not coming back.

gem_hangcheck_forcewake has been superseded by drv_hangman, and a lot of
other very extensive hangchecking that is not run by CI. Something about
hang testing taking longer than the sun to go nova, and still will never
be completely reliable...
-Chris
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Re: [Intel-gfx] [PATCH i-g-t 1/2] tests/debugfs_test: Try to light all outputs to increase chances of finding fails.

[Chris Wilson]

Quoting Maarten Lankhorst (2017-10-10 17:04:27)
> Make sure read_all_entries has all outputs possible enabled, but also
> add a test that runs with all outputs disabled.
> 
> This will maximize coverage of debugfs reading, and allows the test not
> to be dependent on fbcon for setup.
> 
> Signed-off-by: Maarten Lankhorst 

My only argument, but this is just one special case out of many, isn't
really an argument but an endorsement.

Reviewed-by: Chris Wilson 
-Chris
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Re: [Intel-gfx] [PATCH i-g-t] igt/syncobj_wait: Don't close the timeline early in wait_snapshot

[Chris Wilson]

Quoting Jason Ekstrand (2017-10-10 21:02:20)
> Closing the sw_sync timeline now signals any remaining fences upon it;
> but test_wait_snapshot requires the fence to continue to be busy so that
> the __syncobj_wait() will return with -ETIME.

Snap!

Reviewed-by: Chris Wilson 
Tested-by: Chris Wilson 
-Chris
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Re: [Intel-gfx] [RFC PATCH 00/11] Refactor HW workaround code

[Chris Wilson]

Quoting Oscar Mateo (2017-10-10 19:24:18)
> * Above method can be used to create a complete logical context with 
> engine context populated by the hardware. This Logical context can be 
> used as an Golden Context Image or template for subsequently created 
> contexts.

It's the template part we want (sending down a pair of contexts to be
executed in sequence is problematic).

The current fire are the nonpriv registers that are leaking across the
proto-context, i.e. mesa does LRI that get inherited into a libva
context. Adding those to the context image requires approx a hundred
LRI, so a not impossible task to proofread (esp. as many are just
setting register groups, e.g. the 32 CS_GPR registers, to 0).

But it is still a task that we need to maintain that list of nonpriv
registers. (State outside of the nonpriv that doesn't have a defined
default, cannot be either modified by userspace or assume to have any
particular value.)
-Chris
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: remove redundant check on has_aliasing_ppgtt

[Patchwork]

== Series Details ==

Series: drm/i915: remove redundant check on has_aliasing_ppgtt
URL   : https://patchwork.freedesktop.org/series/31661/
State : failure

== Summary ==

Test gem_flink_race:
Subgroup flink_close:
fail   -> PASS   (shard-hsw) fdo#102655
Test perf:
Subgroup polling:
pass   -> FAIL   (shard-hsw) fdo#102252
Test kms_flip:
Subgroup basic-flip-vs-wf_vblank:
pass   -> FAIL   (shard-hsw)
Test pm_rpm:
Subgroup modeset-non-lpsp:
pass   -> SKIP   (shard-hsw)
Test gem_userptr_blits:
Subgroup sync-unmap-cycles:
pass   -> DMESG-WARN (shard-hsw) fdo#102886

fdo#102655 https://bugs.freedesktop.org/show_bug.cgi?id=102655
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#102886 https://bugs.freedesktop.org/show_bug.cgi?id=102886

shard-hswtotal:2552 pass:1427 dwarn:6   dfail:0   fail:15  skip:1104 
time:9613s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5975/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] tests/syncobj_wait: Replace open-coded calls to __syncobj_wait()

[Patchwork]

== Series Details ==

Series: series starting with [1/2] tests/syncobj_wait: Replace open-coded calls 
to __syncobj_wait()
URL   : https://patchwork.freedesktop.org/series/31672/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
d7c88290ab6a8393dc341b30c7fb5e27d2952901 syncobj: Add a test for 
SYNCOBJ_CREATE_SIGNALED

with latest DRM-Tip kernel build CI_DRM_3207
d82f454de90a drm-tip: 2017y-10m-10d-18h-40m-34s UTC integration manifest

No testlist changes.

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> DMESG-WARN (fi-byt-j1900) fdo#101705 +1

fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:459s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:471s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:390s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:575s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:288s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:525s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:517s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:544s
fi-byt-n2820 total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  
time:529s
fi-cfl-s total:289  pass:253  dwarn:4   dfail:0   fail:0   skip:32  
time:566s
fi-cnl-y total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:634s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:433s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:603s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:443s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:427s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:464s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:502s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:478s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:506s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:583s
fi-kbl-7567u total:289  pass:265  dwarn:4   dfail:0   fail:0   skip:20  
time:497s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:593s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:659s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:473s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:653s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:538s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:509s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:474s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:578s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:430s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_317/
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[Intel-gfx] [PATCH i-g-t] igt/syncobj_wait: Don't close the timeline early in wait_snapshot

[Jason Ekstrand]

Closing the sw_sync timeline now signals any remaining fences upon it;
but test_wait_snapshot requires the fence to continue to be busy so that
the __syncobj_wait() will return with -ETIME.
---
 tests/syncobj_wait.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/tests/syncobj_wait.c b/tests/syncobj_wait.c
index 385d8cd..1842f9c 100644
--- a/tests/syncobj_wait.c
+++ b/tests/syncobj_wait.c
@@ -525,7 +525,7 @@ test_wait_snapshot(int fd, uint32_t test_flags)
 {
struct wait_thread_data wait = { 0 };
uint32_t syncobjs[2];
-   int timelines[2] = { -1, -1 };
+   int timelines[3] = { -1, -1, -1 };
pthread_t thread;
 
syncobjs[0] = syncobj_create(fd, 0);
@@ -570,8 +570,7 @@ test_wait_snapshot(int fd, uint32_t test_flags)
 * the kernel picks up on the new fence (it shouldn't), we'll get a
 * timeout.
 */
-   close(timelines[0]);
-   timelines[0] = syncobj_attach_sw_sync(fd, syncobjs[0]);
+   timelines[2] = syncobj_attach_sw_sync(fd, syncobjs[0]);
 
sleep_nsec(SHORT_TIME_NSEC / 5);
 
@@ -589,6 +588,7 @@ test_wait_snapshot(int fd, uint32_t test_flags)
 
close(timelines[0]);
close(timelines[1]);
+   close(timelines[2]);
syncobj_destroy(fd, syncobjs[0]);
syncobj_destroy(fd, syncobjs[1]);
 }
-- 
2.5.0.400.gff86faf

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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Parse DSI backlight/cabc ports.

[Chauhan, Madhav]

> -Original Message-
> From: Nikula, Jani
> Sent: Tuesday, October 10, 2017 11:27 PM
> To: Chauhan, Madhav ; intel-
> g...@lists.freedesktop.org
> Cc: Hiremath, Shashidhar ; Shankar, Uma
> 
> Subject: RE: [PATCH 1/2] drm/i915: Parse DSI backlight/cabc ports.
> 
> On Tue, 10 Oct 2017, "Chauhan, Madhav" 
> wrote:
> >> -Original Message-
> >> From: Nikula, Jani
> >> Sent: Tuesday, October 10, 2017 12:47 PM
> >> To: Chauhan, Madhav ; intel-
> >> g...@lists.freedesktop.org
> >> Cc: Hiremath, Shashidhar ; Shankar,
> >> Uma ; Chauhan, Madhav
> >> 
> >> Subject: Re: [PATCH 1/2] drm/i915: Parse DSI backlight/cabc ports.
> >>
> >> On Tue, 03 Oct 2017, Madhav Chauhan 
> >> wrote:
> >> > This patch parse DSI backlight/cabc ports info from VBT and save
> >> > them inside local strucutre. This saved info can be directly used
> >> > while initializing DSI for different platforms instead of parsing
> >> > for each platform.
> >> >
> >> > Signed-off-by: Madhav Chauhan 
> >> > ---
> >> >  drivers/gpu/drm/i915/i915_drv.h   |  2 ++
> >> >  drivers/gpu/drm/i915/intel_bios.c | 63
> >> > ---
> >> >  2 files changed, 55 insertions(+), 10 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> >> > b/drivers/gpu/drm/i915/i915_drv.h index b7cba89..fc472bb 100644
> >> > --- a/drivers/gpu/drm/i915/i915_drv.h
> >> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> >> > @@ -1751,6 +1751,8 @@ struct intel_vbt_data {
> >> >  u8 seq_version;
> >> >  u32 size;
> >> >  u8 *data;
> >> > +u16 bl_ports;
> >> > +u16 cabc_ports;
> >>
> >> This is right in the middle of the sequence data. Please move up e.g.
> >> between pps and seq_version.
> >
> > Ok.
> >
> >>
> >> >  const u8 *sequence[MIPI_SEQ_MAX];
> >> >  } dsi;
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/intel_bios.c
> >> > b/drivers/gpu/drm/i915/intel_bios.c
> >> > index 3747d8d..88a72cc 100644
> >> > --- a/drivers/gpu/drm/i915/intel_bios.c
> >> > +++ b/drivers/gpu/drm/i915/intel_bios.c
> >> > @@ -730,6 +730,56 @@ parse_psr(struct drm_i915_private *dev_priv,
> >> const struct bdb_header *bdb)
> >> >  dev_priv->vbt.psr.tp2_tp3_wakeup_time =
> >> > psr_table->tp2_tp3_wakeup_time;  }
> >> >
> >> > +static void parse_dsi_backlight_ports(struct drm_i915_private
> *dev_priv,
> >> > +  u16 version, enum port port) {
> >> > +if (dev_priv->vbt.dsi.config->dual_link && version < 197) {
> >> > +/*
> >> > + * These fields are introduced from the VBT version 197
> >> onwards,
> >> > + * so making sure that these bits are set zero in the 
> >> > previous
> >> > + * versions.
> >> > + */
> >> > +dev_priv->vbt.dsi.config->dl_dcs_cabc_ports = 0;
> >> > +dev_priv->vbt.dsi.config->dl_dcs_backlight_ports = 0;
> >>
> >> You could remove this in patch 2. Nobody should be looking at it
> anymore.
> >
> > Patch 2 means?? Next version of this patch or patch 2 of this series.
> > Patch 2 of this series doesn't use these variables. Please clarify.
> 
> After patch 2 of this series, the initialization of these two fields is
> unnecessary, so please remove the above lines in patch 2.

Ok. Thanks!!

Regards,
Madhav

> 
> >
> >>
> >> > +dev_priv->vbt.dsi.bl_ports = 0;
> >> > +dev_priv->vbt.dsi.cabc_ports = 0;
> >>
> >> This you don't have to do anyway, it's all zeros by default.
> >
> > Ok.
> >
> >>
> >> > +return;
> >> > +} else if (dev_priv->vbt.dsi.config->dual_link) {
> >> > +switch 
> >> > (dev_priv->vbt.dsi.config->dl_dcs_backlight_ports) {
> >> > +case DL_DCS_PORT_A:
> >> > +dev_priv->vbt.dsi.bl_ports = BIT(PORT_A);
> >> > +break;
> >> > +case DL_DCS_PORT_C:
> >> > +dev_priv->vbt.dsi.bl_ports = BIT(PORT_C);
> >> > +break;
> >> > +default:
> >> > +case DL_DCS_PORT_A_AND_C:
> >> > +dev_priv->vbt.dsi.bl_ports = BIT(PORT_A) |
> >> BIT(PORT_C);
> >> > +break;
> >> > +}
> >> > +
> >> > +switch (dev_priv->vbt.dsi.config->dl_dcs_cabc_ports) {
> >> > +case DL_DCS_PORT_A:
> >> > +dev_priv->vbt.dsi.cabc_ports = BIT(PORT_A);
> >> > +break;
> >> > +case DL_DCS_PORT_C:
> >> > +dev_priv->vbt.dsi.cabc_ports = BIT(PORT_C);
> >> > +

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] tests/kms_setmode: Request the intiial vbl count with RELATIVE instead of ABSOLUTE

[Patchwork]

== Series Details ==

Series: series starting with [1/2] tests/kms_setmode: Request the intiial vbl 
count with RELATIVE instead of ABSOLUTE
URL   : https://patchwork.freedesktop.org/series/31600/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
d7c88290ab6a8393dc341b30c7fb5e27d2952901 syncobj: Add a test for 
SYNCOBJ_CREATE_SIGNALED

with latest DRM-Tip kernel build CI_DRM_3207
d82f454de90a drm-tip: 2017y-10m-10d-18h-40m-34s UTC integration manifest

No testlist changes.

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> DMESG-WARN (fi-byt-j1900) fdo#101705 +1

fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:453s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:471s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:396s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:563s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:287s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:533s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:532s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:537s
fi-byt-n2820 total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  
time:524s
fi-cfl-s total:289  pass:253  dwarn:4   dfail:0   fail:0   skip:32  
time:563s
fi-cnl-y total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:629s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:435s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:600s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:442s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:419s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:465s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:506s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:476s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:507s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:581s
fi-kbl-7567u total:289  pass:265  dwarn:4   dfail:0   fail:0   skip:20  
time:485s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:594s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:668s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:474s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:658s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:534s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:516s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:472s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:576s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:435s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_316/
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[Intel-gfx] [PATCH igt] igt/syncobj_wait: Avoid early close of timeline in test_wait_snapshot

[Chris Wilson]

We want to keep the first timeline in an incomplete state as we replace
the syncobj's fence; so we need to defer the close() until the end of
the test.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103188
Signed-off-by: Chris Wilson 
Cc: Jason Ekstrand 
Cc: Dave Airlie 
---
 tests/syncobj_wait.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/tests/syncobj_wait.c b/tests/syncobj_wait.c
index 5fd37808..2d5328cc 100644
--- a/tests/syncobj_wait.c
+++ b/tests/syncobj_wait.c
@@ -525,7 +525,7 @@ test_wait_snapshot(int fd, uint32_t test_flags)
 {
struct wait_thread_data wait = { 0 };
uint32_t syncobjs[2];
-   int timelines[2] = { -1, -1 };
+   int timelines[3] = { -1, -1, -1 };
pthread_t thread;
 
syncobjs[0] = syncobj_create(fd, 0);
@@ -570,7 +570,7 @@ test_wait_snapshot(int fd, uint32_t test_flags)
 * the kernel picks up on the new fence (it shouldn't), we'll get a
 * timeout.
 */
-   close(timelines[0]);
+   timelines[2] = timelines[0];
timelines[0] = syncobj_attach_sw_sync(fd, syncobjs[0]);
 
sleep_nsec(SHORT_TIME_NSEC / 5);
@@ -589,6 +589,7 @@ test_wait_snapshot(int fd, uint32_t test_flags)
 
close(timelines[0]);
close(timelines[1]);
+   close(timelines[2]);
syncobj_destroy(fd, syncobjs[0]);
syncobj_destroy(fd, syncobjs[1]);
 }
-- 
2.15.0.rc0

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[Intel-gfx] ✗ Fi.CI.BAT: warning for tests/BAT: Reduce reliance on fbcon.

[Patchwork]

== Series Details ==

Series: tests/BAT: Reduce reliance on fbcon.
URL   : https://patchwork.freedesktop.org/series/31671/
State : warning

== Summary ==

IGT patchset tested on top of latest successful build
d7c88290ab6a8393dc341b30c7fb5e27d2952901 syncobj: Add a test for 
SYNCOBJ_CREATE_SIGNALED

with latest DRM-Tip kernel build CI_DRM_3207
d82f454de90a drm-tip: 2017y-10m-10d-18h-40m-34s UTC integration manifest

Testlist changes:
+igt@debugfs_test@read_all_entries_display_off

Test debugfs_test:
Subgroup read_all_entries:
pass   -> DMESG-WARN (fi-glk-1)
pass   -> DMESG-WARN (fi-cfl-s)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> DMESG-WARN (fi-byt-j1900) fdo#101705 +1

fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:457s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:469s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:390s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:573s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:288s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:527s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:529s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:542s
fi-byt-n2820 total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  
time:527s
fi-cfl-s total:289  pass:252  dwarn:5   dfail:0   fail:0   skip:32  
time:566s
fi-cnl-y total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:638s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:435s
fi-glk-1 total:289  pass:260  dwarn:1   dfail:0   fail:0   skip:28  
time:596s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:447s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:419s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:464s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:506s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:475s
fi-kbl-7500u total:289  pass:263  dwarn:1   dfail:0   fail:1   skip:24  
time:496s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:584s
fi-kbl-7567u total:289  pass:265  dwarn:4   dfail:0   fail:0   skip:20  
time:496s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:592s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:663s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:476s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:656s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:535s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:515s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:482s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:585s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:443s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_315/
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Re: [Intel-gfx] [PATCH v15 5/7] vfio: ABI for mdev display dma-buf operation

[Alex Williamson]

On Tue, 10 Oct 2017 17:50:05 +0800
Tina Zhang  wrote:

> Add VFIO_DEVICE_QUERY_GFX_PLANE ioctl command to let user mode query and
> get the plan and its related information. This ioctl can be invoked with:

s/plan/plane/

> 1) either flag DMABUF or REGION is set. Vendor driver returns success and
> the plane_info only when the specific kind of buffer is supported.
> 2) flag PROBE is set with either DMABUF or REGION. Vendor driver returns
> success only when the specific kind of buffer is supported.
> 
> The dma-buf's life cycle is handled by user mode and tracked by kernel.
> The returned fd in struct vfio_device_query_gfx_plane can be a new
> fd or an old fd of a re-exported dma-buf. Host user mode can check the
> value of fd and to see if it needs to create new resource according to
> the new fd or just use the existed resource related to the old fd.
> 
> v15:
> - add a ioctl to get a dmabuf for a given dmabuf id. (Gerd)
> 
> v14:
> - add PROBE, DMABUF and REGION flags. (Alex)
> 
> v12:
> - add drm_format_mod back. (Gerd and Zhenyu)
> - add region_index. (Gerd)
> 
> v11:
> - rename plane_type to drm_plane_type. (Gerd)
> - move fields of vfio_device_query_gfx_plane to vfio_device_gfx_plane_info.
>   (Gerd)
> - remove drm_format_mod, start fields. (Daniel)
> - remove plane_id.
> 
> v10:
> - refine the ABI API VFIO_DEVICE_QUERY_GFX_PLANE. (Alex) (Gerd)
> 
> v3:
> - add a field gvt_plane_info in the drm_i915_gem_obj structure to save
>   the decoded plane information to avoid look up while need the plane
>   info. (Gerd)
> 
> Signed-off-by: Tina Zhang 
> Cc: Gerd Hoffmann 
> Cc: Alex Williamson 
> Cc: Daniel Vetter 
> ---
>  include/uapi/linux/vfio.h | 62 
> +++
>  1 file changed, 62 insertions(+)
> 
> diff --git a/include/uapi/linux/vfio.h b/include/uapi/linux/vfio.h
> index ae46105..fdf9a9c 100644
> --- a/include/uapi/linux/vfio.h
> +++ b/include/uapi/linux/vfio.h
> @@ -502,6 +502,68 @@ struct vfio_pci_hot_reset {
>  
>  #define VFIO_DEVICE_PCI_HOT_RESET_IO(VFIO_TYPE, VFIO_BASE + 13)
>  
> +/**
> + * VFIO_DEVICE_QUERY_GFX_PLANE - _IOW(VFIO_TYPE, VFIO_BASE + 14,
> + *struct vfio_device_query_gfx_plane)
> + *
> + * Set the drm_plane_type and flags, then retrieve the gfx plane info.
> + *
> + * flags supported:
> + * - VFIO_GFX_PLANE_TYPE_PROBE and VFIO_GFX_PLANE_TYPE_DMABUF are set
> + *   to ask if the mdev supports dma-buf. 0 on support, -EINVAL on no
> + *   support for dma-buf.
> + * - VFIO_GFX_PLANE_TYPE_PROBE and VFIO_GFX_PLANE_TYPE_REGION are set
> + *   to ask if the mdev supports region. 0 on support, -EINVAL on no
> + *   support for region.
> + * - VFIO_GFX_PLANE_TYPE_DMABUF or VFIO_GFX_PLANE_TYPE_REGION is set
> + *   with each call to query the plane info.

So dmabuf_id is effectively just a token that can be fed into
GET_GFX_DMABUF to get the fd.  The implementation of the token is
vendor specific, but can be thought of as some sort of sequence ID or
generation ID (but not necessarily monotonically increasing), so
GET_GFX_DMABUF may fail if the previously provided dmabuf_id is no
longer valid.  Do I have this correct?

> + * - Others are invalid and return -EINVAL.

And I see that in patch 7/7 that i915 is checking explicitly for only
these flag combinations, great!

> + *
> + * Return: 0 on success, -ENODEV with all out fields zero on mdev
> + * device initialization, -errno on other failure.
> + */
> +struct vfio_device_gfx_plane_info {
> + __u32 argsz;
> + __u32 flags;
> +#define VFIO_GFX_PLANE_TYPE_PROBE (1 << 0)
> +#define VFIO_GFX_PLANE_TYPE_DMABUF (1 << 1)
> +#define VFIO_GFX_PLANE_TYPE_REGION (1 << 2)
> + /* in */
> + __u32 drm_plane_type;   /* type of plane: DRM_PLANE_TYPE_* */
> + /* out */
> + __u32 drm_format;   /* drm format of plane */
> + __u64 drm_format_mod;   /* tiled mode */
> + __u32 width;/* width of plane */
> + __u32 height;   /* height of plane */
> + __u32 stride;   /* stride of plane */
> + __u32 size; /* size of plane in bytes, align on page*/
> + __u32 x_pos;/* horizontal position of cursor plane */
> + __u32 y_pos;/* vertical position of cursor plane*/
> + union {
> + __u32 region_index; /* region index */
> + __s32 dmabuf_id;/* dma-buf fd */

"dma-buf fd", but it's not an fd.  Why is this signed since it's no
longer an fd?

> + };
> +};
> +
> +#define VFIO_DEVICE_QUERY_GFX_PLANE _IO(VFIO_TYPE, VFIO_BASE + 14)
> +
> +/**
> + * VFIO_DEVICE_GET_GFX_DMABUF - _IOW(VFIO_TYPE, VFIO_BASE + 15,
> + *   struct vfio_device_gfx_dmabuf_fd)
> + *
> + * Return: 0 on success, -errno on failure.
> + */

So given a dmabuf_id, return a dmabuf_fd, which may be the same as a
fd previously returned to the user.  In the latter case, can we assume

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/guc : Removing enable_guc_loading module and Decoupling logs and ADS from submission

[Patchwork]

== Series Details ==

Series: drm/i915/guc : Removing enable_guc_loading module and Decoupling logs 
and ADS from submission
URL   : https://patchwork.freedesktop.org/series/31677/
State : failure

== Summary ==

  CHK include/config/kernel.release
  CHK include/generated/uapi/linux/version.h
  CHK include/generated/utsrelease.h
  CHK include/generated/bounds.h
  CHK include/generated/timeconst.h
  CHK include/generated/asm-offsets.h
  CALLscripts/checksyscalls.sh
  CHK scripts/mod/devicetable-offsets.h
  CHK include/generated/compile.h
  CHK kernel/config_data.h
  CC [M]  drivers/gpu/drm/i915/i915_debugfs.o
drivers/gpu/drm/i915/i915_debugfs.c: In function ‘i915_huc_load_status_info’:
drivers/gpu/drm/i915/i915_debugfs.c:2393:2: error: this ‘if’ clause does not 
guard... [-Werror=misleading-indentation]
  if (!HAS_GUC(dev_priv))
  ^~
drivers/gpu/drm/i915/i915_debugfs.c:2395:3: note: ...this statement, but the 
latter is misleadingly indented as if it is guarded by the ‘if’
   return 0;
   ^~
drivers/gpu/drm/i915/i915_debugfs.c: In function ‘i915_guc_load_status_info’:
drivers/gpu/drm/i915/i915_debugfs.c:2427:2: error: this ‘if’ clause does not 
guard... [-Werror=misleading-indentation]
  if (!HAS_GUC(dev_priv))
  ^~
drivers/gpu/drm/i915/i915_debugfs.c:2429:3: note: ...this statement, but the 
latter is misleadingly indented as if it is guarded by the ‘if’
   return 0;
   ^~
cc1: all warnings being treated as errors
scripts/Makefile.build:313: recipe for target 
'drivers/gpu/drm/i915/i915_debugfs.o' failed
make[4]: *** [drivers/gpu/drm/i915/i915_debugfs.o] Error 1
scripts/Makefile.build:572: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:572: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:572: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1019: recipe for target 'drivers' failed
make: *** [drivers] Error 2

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[Intel-gfx] ✓ Fi.CI.BAT: success for IGT PMU support (rev11)

[Patchwork]

== Series Details ==

Series: IGT PMU support (rev11)
URL   : https://patchwork.freedesktop.org/series/28253/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
d7c88290ab6a8393dc341b30c7fb5e27d2952901 syncobj: Add a test for 
SYNCOBJ_CREATE_SIGNALED

with latest DRM-Tip kernel build CI_DRM_3206
cc58e6d2bc38 drm-tip: 2017y-10m-10d-15h-40m-22s UTC integration manifest

Testlist changes:
+igt@perf_pmu@all-busy-check-all
+igt@perf_pmu@busy-bcs0
+igt@perf_pmu@busy-check-all-bcs0
+igt@perf_pmu@busy-check-all-rcs0
+igt@perf_pmu@busy-check-all-vcs0
+igt@perf_pmu@busy-check-all-vcs1
+igt@perf_pmu@busy-check-all-vecs0
+igt@perf_pmu@busy-no-semaphores-bcs0
+igt@perf_pmu@busy-no-semaphores-rcs0
+igt@perf_pmu@busy-no-semaphores-vcs0
+igt@perf_pmu@busy-no-semaphores-vcs1
+igt@perf_pmu@busy-no-semaphores-vecs0
+igt@perf_pmu@busy-rcs0
+igt@perf_pmu@busy-vcs0
+igt@perf_pmu@busy-vcs1
+igt@perf_pmu@busy-vecs0
+igt@perf_pmu@cpu-hotplug
+igt@perf_pmu@event-wait-rcs0
+igt@perf_pmu@frequency
+igt@perf_pmu@idle-bcs0
+igt@perf_pmu@idle-no-semaphores-bcs0
+igt@perf_pmu@idle-no-semaphores-rcs0
+igt@perf_pmu@idle-no-semaphores-vcs0
+igt@perf_pmu@idle-no-semaphores-vcs1
+igt@perf_pmu@idle-no-semaphores-vecs0
+igt@perf_pmu@idle-rcs0
+igt@perf_pmu@idle-vcs0
+igt@perf_pmu@idle-vcs1
+igt@perf_pmu@idle-vecs0
+igt@perf_pmu@init-busy-bcs0
+igt@perf_pmu@init-busy-rcs0
+igt@perf_pmu@init-busy-vcs0
+igt@perf_pmu@init-busy-vcs1
+igt@perf_pmu@init-busy-vecs0
+igt@perf_pmu@init-sema-bcs0
+igt@perf_pmu@init-sema-rcs0
+igt@perf_pmu@init-sema-vcs0
+igt@perf_pmu@init-sema-vcs1
+igt@perf_pmu@init-sema-vecs0
+igt@perf_pmu@init-wait-bcs0
+igt@perf_pmu@init-wait-rcs0
+igt@perf_pmu@init-wait-vcs0
+igt@perf_pmu@init-wait-vcs1
+igt@perf_pmu@init-wait-vecs0
+igt@perf_pmu@interrupts
+igt@perf_pmu@invalid-init
+igt@perf_pmu@most-busy-check-all-bcs0
+igt@perf_pmu@most-busy-check-all-rcs0
+igt@perf_pmu@most-busy-check-all-vcs0
+igt@perf_pmu@most-busy-check-all-vcs1
+igt@perf_pmu@most-busy-check-all-vecs0
+igt@perf_pmu@multi-client-bcs0
+igt@perf_pmu@multi-client-rcs0
+igt@perf_pmu@multi-client-vcs0
+igt@perf_pmu@multi-client-vcs1
+igt@perf_pmu@multi-client-vecs0
+igt@perf_pmu@other-init-0
+igt@perf_pmu@other-init-1
+igt@perf_pmu@other-init-2
+igt@perf_pmu@other-init-3
+igt@perf_pmu@other-init-4
+igt@perf_pmu@other-init-5
+igt@perf_pmu@other-init-6
+igt@perf_pmu@other-read-0
+igt@perf_pmu@other-read-1
+igt@perf_pmu@other-read-2
+igt@perf_pmu@other-read-3
+igt@perf_pmu@other-read-4
+igt@perf_pmu@other-read-5
+igt@perf_pmu@other-read-6
+igt@perf_pmu@rc6
+igt@perf_pmu@rc6p
+igt@perf_pmu@render-node-busy-bcs0
+igt@perf_pmu@render-node-busy-rcs0
+igt@perf_pmu@render-node-busy-vcs0
+igt@perf_pmu@render-node-busy-vcs1
+igt@perf_pmu@render-node-busy-vecs0
+igt@perf_pmu@semaphore-wait-bcs0
+igt@perf_pmu@semaphore-wait-rcs0
+igt@perf_pmu@semaphore-wait-vcs0
+igt@perf_pmu@semaphore-wait-vcs1
+igt@perf_pmu@semaphore-wait-vecs0

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
incomplete -> PASS   (fi-kbl-7560u) fdo#102846 +1
Test drv_module_reload:
Subgroup basic-reload-inject:
dmesg-warn -> INCOMPLETE (fi-cfl-s) fdo#103022

fdo#102846 https://bugs.freedesktop.org/show_bug.cgi?id=102846
fdo#103022 https://bugs.freedesktop.org/show_bug.cgi?id=103022

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:458s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:478s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:396s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:578s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:284s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:529s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:527s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:537s
fi-byt-n2820 total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  
time:530s
fi-cfl-s total:288  pass:253  dwarn:3   dfail:0   fail:0   skip:31 
fi-cnl-y total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:634s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:436s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:606s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:440s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:421s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:464s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:508s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:476s
fi-kbl-7500u total:289  pass:263  dwarn:1   dfail:0   fail:1   skip:24  
time:495s
fi-kbl-7560u 

[Intel-gfx] [PATCH v6 3/3] drm/i915/guc : Decouple logs and ADS from submission

[Sujaritha Sundaresan]

The Additional Data Struct (ADS) contains objects that are required by
guc post FW load and are not necessarily submission-only (although that's
our current only use-case). If in the future we load GuC with submission
disabled to use some other GuC feature we might still end up requiring
something inside the ADS, so it makes more sense for them to be always
created if GuC is loaded.

Similarly, we still want to access GuC logs even if GuC submission is
disable to debug issues with GuC loading or with wathever we're using
GuC for.

To make a concrete example, the pages used by GuC to save state during
suspend are allocated as part of the ADS.

v3: Group initialization of GuC objects

v2: Decoupling ADS together with logs

v3: Re-factoring code as per review (Michal)

v4: Rebase

v5: Separating group object initialization into next patch
Clarifying commit message

v6: Reverting to goto err format (Michal)
Moved guc_ads functions to dedicated file
Rebase

Signed-off-by: Sujaritha Sundaresan 
Cc: Michal Wajdeczko 
Cc: Sagar Arun Kamble 
Cc: Daniele Ceraolo Spurio 
Cc: Anusha Srivatsa 
Cc: Oscar Mateo 
---
 drivers/gpu/drm/i915/Makefile  |   1 +
 drivers/gpu/drm/i915/i915_guc_submission.c | 105 +
 drivers/gpu/drm/i915/intel_guc.h   |   1 +
 drivers/gpu/drm/i915/intel_guc_ads.c   | 120 +
 drivers/gpu/drm/i915/intel_guc_ads.h   |  31 
 drivers/gpu/drm/i915/intel_guc_log.c   |   6 +-
 drivers/gpu/drm/i915/intel_uc.c|  40 +-
 7 files changed, 196 insertions(+), 108 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_guc_ads.c
 create mode 100644 drivers/gpu/drm/i915/intel_guc_ads.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 66d23b6..3aed5bf 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -62,6 +62,7 @@ i915-y += i915_cmd_parser.o \
 i915-y += intel_uc.o \
  intel_uc_fw.o \
  intel_guc.o \
+ intel_guc_ads.o \
  intel_guc_ct.o \
  intel_guc_log.o \
  intel_guc_loader.o \
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 31381a3..1ad1060 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -72,13 +72,6 @@
  * ELSP context descriptor dword into Work Item.
  * See guc_wq_item_append()
  *
- * ADS:
- * The Additional Data Struct (ADS) has pointers for different buffers used by
- * the GuC. One single gem object contains the ADS struct itself (guc_ads), the
- * scheduling policies (guc_policies), a structure describing a collection of
- * register sets (guc_mmio_reg_state) and some extra pages for the GuC to save
- * its internal state for sleep.
- *
  */
 
 static inline bool is_high_priority(struct i915_guc_client* client)
@@ -863,7 +856,7 @@ static void guc_policy_init(struct guc_policy *policy)
policy->policy_flags = 0;
 }
 
-static void guc_policies_init(struct guc_policies *policies)
+void i915_guc_policies_init(struct guc_policies *policies)
 {
struct guc_policy *policy;
u32 p, i;
@@ -883,88 +876,6 @@ static void guc_policies_init(struct guc_policies 
*policies)
 }
 
 /*
- * The first 80 dwords of the register state context, containing the
- * execlists and ppgtt registers.
- */
-#define LR_HW_CONTEXT_SIZE (80 * sizeof(u32))
-
-static int guc_ads_create(struct intel_guc *guc)
-{
-   struct drm_i915_private *dev_priv = guc_to_i915(guc);
-   struct i915_vma *vma;
-   struct page *page;
-   /* The ads obj includes the struct itself and buffers passed to GuC */
-   struct {
-   struct guc_ads ads;
-   struct guc_policies policies;
-   struct guc_mmio_reg_state reg_state;
-   u8 reg_state_buffer[GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE];
-   } __packed *blob;
-   struct intel_engine_cs *engine;
-   enum intel_engine_id id;
-   const u32 skipped_offset = LRC_HEADER_PAGES * PAGE_SIZE;
-   const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE;
-   u32 base;
-
-   GEM_BUG_ON(guc->ads_vma);
-
-   vma = intel_guc_allocate_vma(guc, PAGE_ALIGN(sizeof(*blob)));
-   if (IS_ERR(vma))
-   return PTR_ERR(vma);
-
-   guc->ads_vma = vma;
-
-   page = i915_vma_first_page(vma);
-   blob = kmap(page);
-
-   /* GuC scheduling policies */
-   guc_policies_init(>policies);
-
-   /* MMIO reg state */
-   for_each_engine(engine, dev_priv, id) {
-   blob->reg_state.white_list[engine->guc_id].mmio_start =
-   engine->mmio_base + GUC_MMIO_WHITE_LIST_START;
-
-   /* Nothing to be saved or 

[Intel-gfx] [PATCH v6 2/3] drm/i915/guc : Removing i915_modparams.enable_guc_loading module parameter

[Sujaritha Sundaresan]

We currently have two module parameters that control GuC: "enable_guc_loading" 
and "enable_guc_submission".
Whenever we need i915_modparams.enable_guc_submission=1, we also need 
enable_guc_loading=1.
We also need enable_guc_loading=1 when we want to verify the HuC,
which is every time we have a HuC (but all platforms with HuC have a GuC and 
viceversa).

v2: Clarifying the commit message (Anusha)

v3: Unify seq_puts messages, Re-factoring code as per review (Michal)

v4: Rebase

v5: Separating message unification into a separate patch

v6: Re-factoring code (Sagar, Michal)
Rebase

Suggested by: Oscar Mateo 
Signed-off-by: Sujaritha Sundaresan 
Cc: Michal Wajdeczko 
Cc: Sagar Arun Kamble 
Cc: Anusha Srivatsa 
Cc: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_debugfs.c |  6 +--
 drivers/gpu/drm/i915/i915_drv.h |  9 +++--
 drivers/gpu/drm/i915/i915_gem_context.c |  2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c |  2 +-
 drivers/gpu/drm/i915/i915_irq.c |  2 +-
 drivers/gpu/drm/i915/i915_params.c  |  4 --
 drivers/gpu/drm/i915/i915_params.h  |  1 -
 drivers/gpu/drm/i915/intel_guc.h|  2 +-
 drivers/gpu/drm/i915/intel_guc_loader.c |  9 ++---
 drivers/gpu/drm/i915/intel_huc.c|  4 +-
 drivers/gpu/drm/i915/intel_uc.c | 72 +
 drivers/gpu/drm/i915/intel_uncore.c |  3 +-
 12 files changed, 59 insertions(+), 57 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 9d0c27b..8abc47c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2390,7 +2390,7 @@ static int i915_huc_load_status_info(struct seq_file *m, 
void *data)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
struct intel_uc_fw *huc_fw = _priv->huc.fw;
 
-   if (!HAS_HUC_UCODE(dev_priv))
+   if (!HAS_GUC(dev_priv))
seq_puts(m, "not supported\n");
return 0;
 
@@ -2424,7 +2424,7 @@ static int i915_guc_load_status_info(struct seq_file *m, 
void *data)
struct intel_uc_fw *guc_fw = _priv->guc.fw;
u32 tmp, i;
 
-   if (!HAS_GUC_UCODE(dev_priv))
+   if (!HAS_GUC(dev_priv))
seq_puts(m, "not supported\n");
return 0;
 
@@ -2521,7 +2521,7 @@ static bool check_guc_submission(struct seq_file *m)
 
if (!guc->execbuf_client) {
seq_printf(m, "GuC submission %s\n",
-  HAS_GUC_SCHED(dev_priv) ?
+  HAS_GUC(dev_priv) ?
   "disabled" :
   "not supported");
return false;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 770305b..194cbc9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3182,9 +3182,12 @@ static inline unsigned int i915_sg_segment_size(void)
  */
 #define HAS_GUC(dev_priv)  ((dev_priv)->info.has_guc)
 #define HAS_GUC_CT(dev_priv)   ((dev_priv)->info.has_guc_ct)
-#define HAS_GUC_UCODE(dev_priv)(HAS_GUC(dev_priv))
-#define HAS_GUC_SCHED(dev_priv)(HAS_GUC(dev_priv))
-#define HAS_HUC_UCODE(dev_priv)(HAS_GUC(dev_priv))
+#define HAS_GUC_UCODE(dev_priv)((dev_priv)->guc.fw.path != NULL)
+#define HAS_HUC_UCODE(dev_priv)((dev_priv)->huc.fw.path != NULL)
+
+#define NEEDS_GUC_LOADING(dev_priv) \
+   (HAS_GUC(dev_priv) && \
+   (i915_modparams.enable_guc_submission || HAS_HUC_UCODE(dev_priv)))
 
 #define HAS_RESOURCE_STREAMER(dev_priv) 
((dev_priv)->info.has_resource_streamer)
 
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 5bf96a2..692d609 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -314,7 +314,7 @@ static u32 default_desc_template(const struct 
drm_i915_private *i915,
 * present or not in use we still need a small bias as ring wraparound
 * at offset 0 sometimes hangs. No idea why.
 */
-   if (HAS_GUC(dev_priv) && i915_modparams.enable_guc_loading)
+   if (NEEDS_GUC_LOADING(dev_priv))
ctx->ggtt_offset_bias = GUC_WOPCM_TOP;
else
ctx->ggtt_offset_bias = I915_GTT_PAGE_SIZE;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 4c60578..b71fd24 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3483,7 +3483,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv)
 * currently don't have any bits spare to pass in this upper
 * restriction!
 */
-   if (HAS_GUC(dev_priv) && i915_modparams.enable_guc_loading) {
+   if (NEEDS_GUC_LOADING(dev_priv)) {

[Intel-gfx] [PATCH v6 0/3] drm/i915/guc : Removing enable_guc_loading module and Decoupling logs and ADS from submission

[Sujaritha Sundaresan]

The first patch simply unifies different seq_puts messages found in debugfs.
Patch 2 focuses on replacing the enable_guc_loading module. Patch 3 deals with 
decoupling guc logs and ADS from submission. 

Cc: Joonas Lahtinen 
Cc: Michal Wajdeczko 
Cc: Sagar Arun Kamble 
Cc: Oscar Mateo 
Cc: Daniele Ceraolo Spurio 
Cc: Anusha Srivatsa 

Sujaritha Sundaresan (3):
  drm/i915/guc : Unifying seq_puts messages for feature support
  drm/i915/guc : Removing i915_modparams.enable_guc_loading module parameter
  drm/i915/guc : Decouple logs and ADS from submission

 drivers/gpu/drm/i915/Makefile  |   1 +
 drivers/gpu/drm/i915/i915_debugfs.c|  18 +++--
 drivers/gpu/drm/i915/i915_drv.h|   9 ++-
 drivers/gpu/drm/i915/i915_gem_context.c|   2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c|   2 +-
 drivers/gpu/drm/i915/i915_guc_submission.c | 105 +
 drivers/gpu/drm/i915/i915_irq.c|   2 +-
 drivers/gpu/drm/i915/i915_params.c |   4 -
 drivers/gpu/drm/i915/i915_params.h |   1 -
 drivers/gpu/drm/i915/intel_guc.h   |   3 +-
 drivers/gpu/drm/i915/intel_guc_ads.c   | 120 +
 drivers/gpu/drm/i915/intel_guc_ads.h   |  31 
 drivers/gpu/drm/i915/intel_guc_loader.c|   9 +--
 drivers/gpu/drm/i915/intel_guc_log.c   |   6 +-
 drivers/gpu/drm/i915/intel_huc.c   |   4 +-
 drivers/gpu/drm/i915/intel_uc.c| 112 ++-
 drivers/gpu/drm/i915/intel_uncore.c|   3 +-
 17 files changed, 262 insertions(+), 170 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_guc_ads.c
 create mode 100644 drivers/gpu/drm/i915/intel_guc_ads.h

-- 
1.9.1

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[Intel-gfx] [PATCH v6 1/3] drm/i915/guc : Unifying seq_puts messages for feature support

[Sujaritha Sundaresan]

Unifying the various seq_puts messages in debugfs to the simplest one for
feature support.

v2: Clarifying the commit message (Anusha)

v3: Re-factoring code as per review (Michal)

v4: Rebase

v5: Split from following patch

v6: Re-factoring code (Michal, Sagar)
Clarifying commit message (Sagar)

Suggested by: Michal Wajdeczko 
Signed-off-by: Sujaritha Sundaresan 
Cc: Michal Wajdeczko 
Cc: Anusha Srivatsa 
Cc: Oscar Mateo 
Cc: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 12 +++-
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 5b58d2b..9d0c27b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1670,7 +1670,7 @@ static int i915_fbc_status(struct seq_file *m, void 
*unused)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
 
if (!HAS_FBC(dev_priv)) {
-   seq_puts(m, "FBC unsupported on this chipset\n");
+   seq_puts(m, "not supported\n");
return 0;
}
 
@@ -1837,7 +1837,7 @@ static int i915_ring_freq_table(struct seq_file *m, void 
*unused)
unsigned int max_gpu_freq, min_gpu_freq;
 
if (!HAS_LLC(dev_priv)) {
-   seq_puts(m, "unsupported on this chipset\n");
+   seq_puts(m, "not supported\n");
return 0;
}
 
@@ -2391,6 +2391,7 @@ static int i915_huc_load_status_info(struct seq_file *m, 
void *data)
struct intel_uc_fw *huc_fw = _priv->huc.fw;
 
if (!HAS_HUC_UCODE(dev_priv))
+   seq_puts(m, "not supported\n");
return 0;
 
seq_puts(m, "HuC firmware status:\n");
@@ -2424,6 +2425,7 @@ static int i915_guc_load_status_info(struct seq_file *m, 
void *data)
u32 tmp, i;
 
if (!HAS_GUC_UCODE(dev_priv))
+   seq_puts(m, "not supported\n");
return 0;
 
seq_printf(m, "GuC firmware status:\n");
@@ -2708,7 +2710,7 @@ static int i915_edp_psr_status(struct seq_file *m, void 
*data)
bool enabled = false;
 
if (!HAS_PSR(dev_priv)) {
-   seq_puts(m, "PSR not supported\n");
+   seq_puts(m, "not supported\n");
return 0;
}
 
@@ -3565,7 +3567,7 @@ static void drrs_status_per_crtc(struct seq_file *m,
 
mutex_lock(>mutex);
/* DRRS Supported */
-   seq_puts(m, "\tDRRS Supported: Yes\n");
+   seq_puts(m, "supported\n");
 
/* disable_drrs() will make drrs->dp NULL */
if (!drrs->dp) {
@@ -3597,7 +3599,7 @@ static void drrs_status_per_crtc(struct seq_file *m,
mutex_unlock(>mutex);
} else {
/* DRRS not supported. Print the VBT parameter*/
-   seq_puts(m, "\tDRRS Supported : No");
+   seq_puts(m, "not supported\n");
}
seq_puts(m, "\n");
 }
-- 
1.9.1

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Re: [Intel-gfx] [PATCH 3/3] drm/i915/dp: limit sink rates based on rate

[Manasi Navare]

On Mon, Oct 09, 2017 at 12:29:59PM +0300, Jani Nikula wrote:
> Get rid of redundant intel_dp_num_rates(). We can simply look at the
> rate and limit based on that.
> 
> Cc: Manasi Navare 
> Signed-off-by: Jani Nikula 

Reviewed-by: 

Manasi

> ---
>  drivers/gpu/drm/i915/intel_dp.c | 26 +++---
>  1 file changed, 7 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 09d75df497c0..b0f446b68f42 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -137,32 +137,20 @@ static void vlv_steal_power_sequencer(struct drm_device 
> *dev,
> enum pipe pipe);
>  static void intel_dp_unset_edid(struct intel_dp *intel_dp);
>  
> -static int intel_dp_num_rates(u8 link_bw_code)
> -{
> - switch (link_bw_code) {
> - default:
> - WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
> -  link_bw_code);
> - case DP_LINK_BW_1_62:
> - return 1;
> - case DP_LINK_BW_2_7:
> - return 2;
> - case DP_LINK_BW_5_4:
> - return 3;
> - }
> -}
> -
>  /* update sink rates from dpcd */
>  static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
>  {
> - int i, num_rates;
> + int i, max_rate;
>  
> - num_rates = intel_dp_num_rates(intel_dp->dpcd[DP_MAX_LINK_RATE]);
> + max_rate = 
> drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
>  
> - for (i = 0; i < num_rates; i++)
> + for (i = 0; i < ARRAY_SIZE(default_rates); i++) {
> + if (default_rates[i] > max_rate)
> + break;
>   intel_dp->sink_rates[i] = default_rates[i];
> + }
>  
> - intel_dp->num_sink_rates = num_rates;
> + intel_dp->num_sink_rates = i;
>  }
>  
>  /* Theoretical max between source and sink */
> -- 
> 2.11.0
> 
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Re: [Intel-gfx] [PATCH 2/3] drm/i915/dp: centralize max source rate conditions more

[Manasi Navare]

On Mon, Oct 09, 2017 at 12:29:58PM +0300, Jani Nikula wrote:
> Turn intel_dp_source_supports_hbr2() into a simple helper to query the
> pre-filled source rates array, and move the conditions about which
> platforms support which rates to the single point of truth in
> intel_dp_set_source_rates().
> 
> This also reduces the code paths you have to think about in the source
> rates initialization in intel_dp_set_source_rates(), making it easier to
> grasp.
> 
> Cc: Manasi Navare 
> Signed-off-by: Jani Nikula 

Reviewed-by: Manasi Navare 

Manasi

> ---
>  drivers/gpu/drm/i915/intel_dp.c | 19 +++
>  1 file changed, 7 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index ca48bce23a6f..09d75df497c0 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -254,15 +254,15 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>   } else if (IS_GEN9_BC(dev_priv)) {
>   source_rates = skl_rates;
>   size = ARRAY_SIZE(skl_rates);
> - } else {
> + } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
> +IS_BROADWELL(dev_priv)) {
>   source_rates = default_rates;
>   size = ARRAY_SIZE(default_rates);
> + } else {
> + source_rates = default_rates;
> + size = ARRAY_SIZE(default_rates) - 1;
>   }
>  
> - /* This depends on the fact that 5.4 is last value in the array */
> - if (!intel_dp_source_supports_hbr2(intel_dp))
> - size--;
> -
>   intel_dp->source_rates = source_rates;
>   intel_dp->num_source_rates = size;
>  }
> @@ -1482,14 +1482,9 @@ intel_dp_aux_init(struct intel_dp *intel_dp)
>  
>  bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
>  {
> - struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> - struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> + int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
>  
> - if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
> - IS_BROADWELL(dev_priv) || (INTEL_GEN(dev_priv) >= 9))
> - return true;
> - else
> - return false;
> + return max_rate >= 54;
>  }
>  
>  static void
> -- 
> 2.11.0
> 
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Re: [Intel-gfx] [RFC PATCH 00/11] Refactor HW workaround code

[Oscar Mateo]

On 10/10/2017 10:37 AM, Oscar Mateo wrote:



On 10/09/2017 02:08 PM, Chris Wilson wrote:

Quoting Oscar Mateo (2017-10-09 21:58:15)
Currently, deciding how/where to apply new workarounds is 
challenging. Often,
workarounds end up applied incorrectly and get lost under certain 
circumstances
(e.g. a context switch or a GPU reset). This is a proposal to 
attempt to
eliminate some of this pain, by clarifying the current 
classification of
workarounds (context saved/restored, global registers, whitelisting, 
BB),
putting them together on the same file, and improving the existing 
validation

infrastructure (debugfs/i-g-t).

One thing I've been dreaming of is if we can have an external file for
importing the w/a (reg offset + corrected value) that we could source
directly from spec. (Hoping for some xml translation to C or DT.)


Hmmm... I'm afraid this is impossible at the moment, since many WAs in 
the BSpec are simply a link to the ticket where the workaround was 
devised (and there you have to parse the conversation to figure out 
what the WA should do).



We need something like this so that we can set all the nonpriv registers
to the default value in the proto-context. Or at least lots of patience
and careful proofreading.
-Chris


You mean applying the workarounds directly to the context image 
instead of the LRI commands we use now? That can be done (as you said, 
with *a lot* of patience and careful proofreading) but we would need 
to force the proto-context to be restored first (with 
CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT bit set), because the workarounds 
do not always give us the full default value for a register, only the 
fields that are wrong in the hardware.


H... I'm giving out conflicting information. Registers in the engine 
(those that live in the engine part of the context image) are not 
guaranteed to be initialized, so inhibit-restoring the context and then 
saving it is not enough. Yes, we would have to get the default values 
for them from the BSpec, either automatically or by hand, then apply the 
workarounds (either by modifying the default values or with the emission 
of LRIs we have now).


This is an insane amount of work (and sometimes the BSpec does not 
include all the information you need), that's why the recommendation in 
the BSpec is to force the engine to populate these registers for us (the 
infamous null state batchbuffer):


"[...] Engine context starts immediately following the logical ring 
context in memory. This state is very specific to an engine and differs 
from engine to engine. This part of the context consists of the state 
from all the units in the engine that needs to be save/restored across 
context switches. Engine restores the engine context following the 
logical ring context restore. It is tedious for software to populate the 
engine context as per the requirements, it is recommended to implicitly 
use engine to populate this portion of the context. Below method can be 
followed to achieve the same:


* When a context is submitted for the first time for execution, SW can 
inhibit engine from restoring engine context by setting the “Engine 
Context Restore Inhibit” bit in CTXT_SR_CTL register of the logical ring 
context. This will avoid software from populating the Engine Context. 
Software must program all the state required to initialize the engine in 
the ring buffer which would initialize the hardware state. On a 
subsequent context save engine will populate the engine context with 
appropriate values.


* Above method can be used to create a complete logical context with 
engine context populated by the hardware. This Logical context can be 
used as an Golden Context Image or template for subsequently created 
contexts.


Engine saves the engine context following the logical ring context on 
switching out a context."






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[Intel-gfx] ✓ Fi.CI.BAT: success for tests: Drop gem_bad_length as redundant

[Patchwork]

== Series Details ==

Series: tests: Drop gem_bad_length as redundant
URL   : https://patchwork.freedesktop.org/series/31655/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
d7c88290ab6a8393dc341b30c7fb5e27d2952901 syncobj: Add a test for 
SYNCOBJ_CREATE_SIGNALED

with latest DRM-Tip kernel build CI_DRM_3206
cc58e6d2bc38 drm-tip: 2017y-10m-10d-15h-40m-22s UTC integration manifest

Testlist changes:
-igt@gem_bad_length

Test chamelium:
Subgroup dp-crc-fast:
fail   -> PASS   (fi-kbl-7500u) fdo#102514
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
incomplete -> PASS   (fi-kbl-7560u) fdo#102846

fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514
fdo#102846 https://bugs.freedesktop.org/show_bug.cgi?id=102846

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:455s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:472s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:393s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:581s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:286s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:526s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:523s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:542s
fi-byt-n2820 total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  
time:517s
fi-cfl-s total:289  pass:253  dwarn:4   dfail:0   fail:0   skip:32  
time:562s
fi-cnl-y total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:633s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:431s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:599s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:436s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:425s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:465s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:507s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:476s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:505s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:582s
fi-kbl-7567u total:289  pass:265  dwarn:4   dfail:0   fail:0   skip:20  
time:492s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:596s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:663s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:472s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:661s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:535s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:508s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:474s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:583s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:433s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_313/
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Re: [Intel-gfx] [PATCH 1/3] drm/dp: WARN about invalid/unknown link rates and bw codes

[Manasi Navare]

On Mon, Oct 09, 2017 at 12:29:57PM +0300, Jani Nikula wrote:
> Falling back to the lowest value is likely the only thing we can do, but
> doing it silently seems like a bad thing to do. Catch it early and make
> loud noises.
> 
> Cc: Alex Deucher 
> Cc: Thierry Reding 
> Cc: Rob Clark 
> Cc: Sean Paul 
> Cc: Manasi Navare 
> Cc: dri-de...@lists.freedesktop.org
> Signed-off-by: Jani Nikula 

Reviewed-by: Manasi Navare 

> ---
>  drivers/gpu/drm/drm_dp_helper.c | 7 +--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index 08af8d6b844b..dca21b5a03ec 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -137,8 +137,10 @@ EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
>  u8 drm_dp_link_rate_to_bw_code(int link_rate)
>  {
>   switch (link_rate) {
> - case 162000:
>   default:
> + WARN(1, "unknown DP link rate %d, using %x\n", link_rate,
> +  DP_LINK_BW_1_62);
> + case 162000:
>   return DP_LINK_BW_1_62;
>   case 27:
>   return DP_LINK_BW_2_7;
> @@ -151,8 +153,9 @@ EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);
>  int drm_dp_bw_code_to_link_rate(u8 link_bw)
>  {
>   switch (link_bw) {
> - case DP_LINK_BW_1_62:
>   default:
> + WARN(1, "unknown DP link bw code %x, using 162000\n", link_bw);
> + case DP_LINK_BW_1_62:
>   return 162000;
>   case DP_LINK_BW_2_7:
>   return 27;
> -- 
> 2.11.0
> 
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[Intel-gfx] ✓ Fi.CI.BAT: success for Add support for NV12

[Patchwork]

== Series Details ==

Series: Add support for NV12
URL   : https://patchwork.freedesktop.org/series/31648/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
d7c88290ab6a8393dc341b30c7fb5e27d2952901 syncobj: Add a test for 
SYNCOBJ_CREATE_SIGNALED

with latest DRM-Tip kernel build CI_DRM_3206
cc58e6d2bc38 drm-tip: 2017y-10m-10d-15h-40m-22s UTC integration manifest

Testlist changes:
+igt@test_nv12@multi_pipe_sprite_nv12
+igt@test_nv12@multi_pipe_sprite_rgb
+igt@test_nv12@nv12-plane-tile-linear
+igt@test_nv12@nv12-plane-tile-linear_rot180
+igt@test_nv12@nv12-plane-tile-x
+igt@test_nv12@nv12-plane-tile-x_rot180
+igt@test_nv12@nv12-plane-tile-y
+igt@test_nv12@nv12-plane-tile-yf
+igt@test_nv12@nv12-plane-tile-yf_rot90
+igt@test_nv12@nv12-plane-tile-yf_rot180
+igt@test_nv12@nv12-plane-tile-yf_rot270
+igt@test_nv12@nv12-plane-tile-y_rot90
+igt@test_nv12@nv12-plane-tile-y_rot180
+igt@test_nv12@nv12-plane-tile-y_rot270
+igt@test_nv12@rgb-plane-tile-linear
+igt@test_nv12@rgb-plane-tile-linear_rot180
+igt@test_nv12@rgb-plane-tile-x
+igt@test_nv12@rgb-plane-tile-x_rot180
+igt@test_nv12@rgb-plane-tile-y
+igt@test_nv12@rgb-plane-tile-yf
+igt@test_nv12@rgb-plane-tile-yf_rot90
+igt@test_nv12@rgb-plane-tile-yf_rot180
+igt@test_nv12@rgb-plane-tile-yf_rot270
+igt@test_nv12@rgb-plane-tile-y_rot90
+igt@test_nv12@rgb-plane-tile-y_rot180
+igt@test_nv12@rgb-plane-tile-y_rot270
+igt@test_nv12@sprite_nv12-plane-tile-linear
+igt@test_nv12@sprite_nv12-plane-tile-linear_rot180
+igt@test_nv12@sprite_nv12-plane-tile-x
+igt@test_nv12@sprite_nv12-plane-tile-x_rot180
+igt@test_nv12@sprite_nv12-plane-tile-y
+igt@test_nv12@sprite_nv12-plane-tile-yf
+igt@test_nv12@sprite_nv12-plane-tile-yf_rot90
+igt@test_nv12@sprite_nv12-plane-tile-yf_rot180
+igt@test_nv12@sprite_nv12-plane-tile-yf_rot270
+igt@test_nv12@sprite_nv12-plane-tile-y_rot90
+igt@test_nv12@sprite_nv12-plane-tile-y_rot180
+igt@test_nv12@sprite_nv12-plane-tile-y_rot270
+igt@test_nv12@sprite_rgb-plane-tile-linear
+igt@test_nv12@sprite_rgb-plane-tile-linear_rot180
+igt@test_nv12@sprite_rgb-plane-tile-x
+igt@test_nv12@sprite_rgb-plane-tile-x_rot180
+igt@test_nv12@sprite_rgb-plane-tile-y
+igt@test_nv12@sprite_rgb-plane-tile-yf
+igt@test_nv12@sprite_rgb-plane-tile-yf_rot90
+igt@test_nv12@sprite_rgb-plane-tile-yf_rot180
+igt@test_nv12@sprite_rgb-plane-tile-yf_rot270
+igt@test_nv12@sprite_rgb-plane-tile-y_rot90
+igt@test_nv12@sprite_rgb-plane-tile-y_rot180
+igt@test_nv12@sprite_rgb-plane-tile-y_rot270

Test chamelium:
Subgroup dp-crc-fast:
fail   -> PASS   (fi-kbl-7500u) fdo#102514
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
incomplete -> PASS   (fi-kbl-7560u) fdo#102846

fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514
fdo#102846 https://bugs.freedesktop.org/show_bug.cgi?id=102846

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:454s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:473s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:393s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:576s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:286s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:525s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:526s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:535s
fi-byt-n2820 total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  
time:523s
fi-cfl-s total:289  pass:253  dwarn:4   dfail:0   fail:0   skip:32  
time:560s
fi-cnl-y total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:633s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:435s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:603s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:439s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:421s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:464s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:518s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:473s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:510s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:580s
fi-kbl-7567u total:289  pass:265  dwarn:4   dfail:0   fail:0   skip:20  
time:490s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:597s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:663s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:471s
fi-skl-6700hqtotal:289  pass:263  

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Parse DSI backlight/cabc ports.

[Jani Nikula]

On Tue, 10 Oct 2017, "Chauhan, Madhav"  wrote:
>> -Original Message-
>> From: Nikula, Jani
>> Sent: Tuesday, October 10, 2017 12:47 PM
>> To: Chauhan, Madhav ; intel-
>> g...@lists.freedesktop.org
>> Cc: Hiremath, Shashidhar ; Shankar, Uma
>> ; Chauhan, Madhav
>> 
>> Subject: Re: [PATCH 1/2] drm/i915: Parse DSI backlight/cabc ports.
>> 
>> On Tue, 03 Oct 2017, Madhav Chauhan 
>> wrote:
>> > This patch parse DSI backlight/cabc ports info from VBT and save them
>> > inside local strucutre. This saved info can be directly used while
>> > initializing DSI for different platforms instead of parsing for each
>> > platform.
>> >
>> > Signed-off-by: Madhav Chauhan 
>> > ---
>> >  drivers/gpu/drm/i915/i915_drv.h   |  2 ++
>> >  drivers/gpu/drm/i915/intel_bios.c | 63
>> > ---
>> >  2 files changed, 55 insertions(+), 10 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> > b/drivers/gpu/drm/i915/i915_drv.h index b7cba89..fc472bb 100644
>> > --- a/drivers/gpu/drm/i915/i915_drv.h
>> > +++ b/drivers/gpu/drm/i915/i915_drv.h
>> > @@ -1751,6 +1751,8 @@ struct intel_vbt_data {
>> >u8 seq_version;
>> >u32 size;
>> >u8 *data;
>> > +  u16 bl_ports;
>> > +  u16 cabc_ports;
>> 
>> This is right in the middle of the sequence data. Please move up e.g. between
>> pps and seq_version.
>
> Ok.
>
>> 
>> >const u8 *sequence[MIPI_SEQ_MAX];
>> >} dsi;
>> >
>> > diff --git a/drivers/gpu/drm/i915/intel_bios.c
>> > b/drivers/gpu/drm/i915/intel_bios.c
>> > index 3747d8d..88a72cc 100644
>> > --- a/drivers/gpu/drm/i915/intel_bios.c
>> > +++ b/drivers/gpu/drm/i915/intel_bios.c
>> > @@ -730,6 +730,56 @@ parse_psr(struct drm_i915_private *dev_priv,
>> const struct bdb_header *bdb)
>> >dev_priv->vbt.psr.tp2_tp3_wakeup_time =
>> > psr_table->tp2_tp3_wakeup_time;  }
>> >
>> > +static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv,
>> > +u16 version, enum port port) {
>> > +  if (dev_priv->vbt.dsi.config->dual_link && version < 197) {
>> > +  /*
>> > +   * These fields are introduced from the VBT version 197
>> onwards,
>> > +   * so making sure that these bits are set zero in the previous
>> > +   * versions.
>> > +   */
>> > +  dev_priv->vbt.dsi.config->dl_dcs_cabc_ports = 0;
>> > +  dev_priv->vbt.dsi.config->dl_dcs_backlight_ports = 0;
>> 
>> You could remove this in patch 2. Nobody should be looking at it anymore.
>
> Patch 2 means?? Next version of this patch or patch 2 of this series.
> Patch 2 of this series doesn't use these variables. Please clarify.

After patch 2 of this series, the initialization of these two fields is
unnecessary, so please remove the above lines in patch 2.

>
>> 
>> > +  dev_priv->vbt.dsi.bl_ports = 0;
>> > +  dev_priv->vbt.dsi.cabc_ports = 0;
>> 
>> This you don't have to do anyway, it's all zeros by default.
>
> Ok.
>
>> 
>> > +  return;
>> > +  } else if (dev_priv->vbt.dsi.config->dual_link) {
>> > +  switch (dev_priv->vbt.dsi.config->dl_dcs_backlight_ports) {
>> > +  case DL_DCS_PORT_A:
>> > +  dev_priv->vbt.dsi.bl_ports = BIT(PORT_A);
>> > +  break;
>> > +  case DL_DCS_PORT_C:
>> > +  dev_priv->vbt.dsi.bl_ports = BIT(PORT_C);
>> > +  break;
>> > +  default:
>> > +  case DL_DCS_PORT_A_AND_C:
>> > +  dev_priv->vbt.dsi.bl_ports = BIT(PORT_A) |
>> BIT(PORT_C);
>> > +  break;
>> > +  }
>> > +
>> > +  switch (dev_priv->vbt.dsi.config->dl_dcs_cabc_ports) {
>> > +  case DL_DCS_PORT_A:
>> > +  dev_priv->vbt.dsi.cabc_ports = BIT(PORT_A);
>> > +  break;
>> > +  case DL_DCS_PORT_C:
>> > +  dev_priv->vbt.dsi.cabc_ports = BIT(PORT_C);
>> > +  break;
>> > +  default:
>> > +  case DL_DCS_PORT_A_AND_C:
>> > +  dev_priv->vbt.dsi.cabc_ports =
>> > +  BIT(PORT_A) | BIT(PORT_C);
>> > +  break;
>> > +  }
>> > +  } else {
>> > +  dev_priv->vbt.dsi.bl_ports = BIT(port);
>> > +  dev_priv->vbt.dsi.cabc_ports = BIT(port);
>> > +  }
>> > +
>> > +  if (!dev_priv->vbt.dsi.config->cabc_supported)
>> > +  dev_priv->vbt.dsi.cabc_ports = 0;
>> 
>> Would seem reasonable to not initalize it in the first place if it's not
>> supported. 
>
> Agree. How about putting a check condition !cabc_supported
> before parsing dl_dcs_cabc_ports in switch case??
>
>>If you do a series of early returns starting with the bdb version
>> check, then !dual_link, then 

[Intel-gfx] ✗ Fi.CI.BAT: warning for gtt-cache-enable

[Patchwork]

== Series Details ==

Series: gtt-cache-enable
URL   : https://patchwork.freedesktop.org/series/31669/
State : warning

== Summary ==

Series 31669v1 gtt-cache-enable
https://patchwork.freedesktop.org/api/1.0/series/31669/revisions/1/mbox/

Test chamelium:
Subgroup dp-crc-fast:
fail   -> PASS   (fi-kbl-7500u) fdo#102514
Test kms_cursor_legacy:
Subgroup basic-flip-after-cursor-varying-size:
pass   -> SKIP   (fi-ivb-3770)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
incomplete -> PASS   (fi-kbl-7560u) fdo#102846

fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514
fdo#102846 https://bugs.freedesktop.org/show_bug.cgi?id=102846

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:452s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:471s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:390s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:558s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:283s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:519s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:521s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:534s
fi-cfl-s total:289  pass:253  dwarn:4   dfail:0   fail:0   skip:32  
time:558s
fi-cnl-y total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:619s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:433s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:598s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:437s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:418s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:458s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:502s
fi-ivb-3770  total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:477s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:501s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:581s
fi-kbl-7567u total:289  pass:265  dwarn:4   dfail:0   fail:0   skip:20  
time:487s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:592s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:655s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:469s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:656s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:537s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:549s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:468s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:583s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:428s
fi-byt-n2820 failed to connect after reboot

cc58e6d2bc38542af8f8031d4b79f4069bba6afc drm-tip: 2017y-10m-10d-15h-40m-22s UTC 
integration manifest
f046e02a1e2b gtt-cache-enable

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5981/
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[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915: Use enum pipe for PCH transcoders

[Patchwork]

== Series Details ==

Series: drm/i915: Use enum pipe for PCH transcoders
URL   : https://patchwork.freedesktop.org/series/31654/
State : warning

== Summary ==

Test kms_fbc_crc:
Subgroup page_flip_and_mmap_gtt:
pass   -> SKIP   (shard-hsw)

shard-hswtotal:2552 pass:1430 dwarn:5   dfail:0   fail:13  skip:1104 
time:9645s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5973/shards.html
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Re: [Intel-gfx] [RFC PATCH 00/11] Refactor HW workaround code

[Oscar Mateo]

On 10/09/2017 02:08 PM, Chris Wilson wrote:

Quoting Oscar Mateo (2017-10-09 21:58:15)

Currently, deciding how/where to apply new workarounds is challenging. Often,
workarounds end up applied incorrectly and get lost under certain circumstances
(e.g. a context switch or a GPU reset). This is a proposal to attempt to
eliminate some of this pain, by clarifying the current classification of
workarounds (context saved/restored, global registers, whitelisting, BB),
putting them together on the same file, and improving the existing validation
infrastructure (debugfs/i-g-t).

One thing I've been dreaming of is if we can have an external file for
importing the w/a (reg offset + corrected value) that we could source
directly from spec. (Hoping for some xml translation to C or DT.)


Hmmm... I'm afraid this is impossible at the moment, since many WAs in 
the BSpec are simply a link to the ticket where the workaround was 
devised (and there you have to parse the conversation to figure out what 
the WA should do).



We need something like this so that we can set all the nonpriv registers
to the default value in the proto-context. Or at least lots of patience
and careful proofreading.
-Chris


You mean applying the workarounds directly to the context image instead 
of the LRI commands we use now? That can be done (as you said, with *a 
lot* of patience and careful proofreading) but we would need to force 
the proto-context to be restored first (with 
CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT bit set), because the workarounds do 
not always give us the full default value for a register, only the 
fields that are wrong in the hardware.


-- Oscar

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Re: [Intel-gfx] [RFC PATCH 02/11] drm/i915: Move a bunch of workaround-related code to its own file

[Oscar Mateo]

On 10/09/2017 02:06 PM, Chris Wilson wrote:

Quoting Oscar Mateo (2017-10-09 21:58:17)

This has grown to be a sizable amount of code, so move it to
its own file before we try to refactor anything. For the moment,
we are leaving behind the WA BB code and the WAs that get applied
(incorrectly) in init_clock_gating, but we will deal with it later.

Signed-off-by: Oscar Mateo 
Cc: Chris Wilson 
Cc: Mika Kuoppala 
---
  drivers/gpu/drm/i915/Makefile   |   1 +
  drivers/gpu/drm/i915/i915_workarounds.c | 705 
  drivers/gpu/drm/i915/i915_workarounds.h |  31 ++

If we look at the filenames with rose-tinted glasses:

intel_* -> interaction with hw
i915_* -> interaction with user

(Let's not start on the mixup entailed when we use the i915 prefix to
mean to talking to gen2/gen3. Hopefully most gen2 mixups are history.)

i915_workarounds would imply w/a for the drm/i915 uABI, but we want
intel_workarounds to imply w/a for hw.

Now some are indeed workarounds to keep uABI constant (or otherwise
correct)... The line can be murky ;)
-Chris


I remembered file prefixes had a meaning, but I tried to recall it from 
memory and came up with the exact opposite (and I looked at 
i915_guc_submission.c as proof that I was recalling it correctly :P).


I'll rename the files, no problem.

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[Intel-gfx] [PATCH igt 1/2] tests/syncobj_wait: Replace open-coded calls to __syncobj_wait()

[Chris Wilson]

Remove the bare igt_ioctl(SYNCOBJ_WAIT) in favour of __syncobj_wait()
for tidier error reporting.

Signed-off-by: Chris Wilson 
Cc: Jason Ekstrand 
Cc: Dave Airlie 
---
 tests/syncobj_wait.c | 14 +-
 1 file changed, 5 insertions(+), 9 deletions(-)

diff --git a/tests/syncobj_wait.c b/tests/syncobj_wait.c
index 385d8cd8..78ed1fc5 100644
--- a/tests/syncobj_wait.c
+++ b/tests/syncobj_wait.c
@@ -713,7 +713,7 @@ test_wait_interrupted(int fd, uint32_t test_flags)
 {
struct local_syncobj_wait wait = { 0 };
uint32_t syncobj = syncobj_create(fd, 0);
-   int ret, timeline;
+   int timeline;
 
wait.handles = to_user_pointer();
wait.count_handles = 1;
@@ -721,20 +721,16 @@ test_wait_interrupted(int fd, uint32_t test_flags)
 
if (test_flags & WAIT_FOR_SUBMIT) {
wait.timeout_nsec = short_timeout();
-   igt_while_interruptible(true) {
-   ret = igt_ioctl(fd, LOCAL_IOCTL_SYNCOBJ_WAIT, );
-   igt_assert(ret == -1 && errno == ETIME);
-   }
+   igt_while_interruptible(true)
+   igt_assert_eq(__syncobj_wait(fd, ), -ETIME);
}
 
timeline = syncobj_attach_sw_sync(fd, syncobj);
close(timeline);
 
wait.timeout_nsec = short_timeout();
-   igt_while_interruptible(true) {
-   ret = igt_ioctl(fd, LOCAL_IOCTL_SYNCOBJ_WAIT, );
-   igt_assert(ret == -1 && errno == ETIME);
-   }
+   igt_while_interruptible(true)
+   igt_assert_eq(__syncobj_wait(fd, ), -ETIME);
 
syncobj_destroy(fd, syncobj);
 }
-- 
2.15.0.rc0

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[Intel-gfx] [PATCH igt 2/2] igt/syncobj_wait: Close the sw_sync timeline after the test

[Chris Wilson]

Closing the sw_sync timeline now signals any remaining fences upon it;
but test_wait_interrupted requires the fence to be busy for the
__syncobj_wait() not to immediately return with -ETIME (and so be
interrupted instead).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103187
Signed-off-by: Chris Wilson 
Cc: Jason Ekstrand 
Cc: Dave Airlie 

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915: Fix eviction when the GGTT is idle but full

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915: Fix eviction when the GGTT is idle 
but full
URL   : https://patchwork.freedesktop.org/series/31668/
State : failure

== Summary ==

Series 31668v1 series starting with [1/3] drm/i915: Fix eviction when the GGTT 
is idle but full
https://patchwork.freedesktop.org/api/1.0/series/31668/revisions/1/mbox/

Test chamelium:
Subgroup dp-crc-fast:
fail   -> PASS   (fi-kbl-7500u) fdo#102514
Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass   -> INCOMPLETE (fi-cfl-s)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
dmesg-warn -> PASS   (fi-byt-n2820) fdo#101705
incomplete -> PASS   (fi-kbl-7560u) fdo#102846

fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514
fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705
fdo#102846 https://bugs.freedesktop.org/show_bug.cgi?id=102846

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:455s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:469s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:390s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:564s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:284s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:520s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:521s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:539s
fi-byt-n2820 total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:524s
fi-cfl-s total:218  pass:195  dwarn:1   dfail:0   fail:0   skip:21 
fi-cnl-y total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:613s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:430s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:593s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:437s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:418s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:458s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:501s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:474s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:501s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:581s
fi-kbl-7567u total:289  pass:265  dwarn:4   dfail:0   fail:0   skip:20  
time:486s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:594s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:660s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:464s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:655s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:530s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:523s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:470s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:582s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:428s

cc58e6d2bc38542af8f8031d4b79f4069bba6afc drm-tip: 2017y-10m-10d-15h-40m-22s UTC 
integration manifest
cf103ee577c9 drm/i915/selftests: Exercise adding requests to a full GGTT
5a9b58d9ba25 drm/i915: Wrap a timer into a i915_sw_fence
54bc5228fed4 drm/i915: Fix eviction when the GGTT is idle but full

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5980/
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Re: [Intel-gfx] [PATCH] i-g-t/tests: Drop gem_seqno_wrap, gem_pin, gem_hangcheck_forcewake

[Antonio Argenziano]

On 10/10/17 01:55, Abdiel Janulgue wrote:

This improves the GEM tests section of I-G-T to make it more
suitable for CI testing


Can you provide a little more details on what is the rationale behind 
this choice. Are the tests being removed only because they do not fit 
the CI guidelines or is it because they do not offer any valuable coverage?


Maybe having three separate patches, one per test would be better in my 
opinion since the tests look to have not much in common.


-Antonio

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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,01/10] drm/i915: Extract intel_get_cagf

[Patchwork]

== Series Details ==

Series: series starting with [CI,01/10] drm/i915: Extract intel_get_cagf
URL   : https://patchwork.freedesktop.org/series/31667/
State : failure

== Summary ==

Series 31667v1 series starting with [CI,01/10] drm/i915: Extract intel_get_cagf
https://patchwork.freedesktop.org/api/1.0/series/31667/revisions/1/mbox/

Test chamelium:
Subgroup dp-crc-fast:
fail   -> PASS   (fi-kbl-7500u) fdo#102514
Test gem_exec_suspend:
Subgroup basic-s3:
pass   -> INCOMPLETE (fi-byt-j1900)
pass   -> INCOMPLETE (fi-glk-1)
pass   -> INCOMPLETE (fi-cnl-y) fdo#103070
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
incomplete -> PASS   (fi-kbl-7560u) fdo#102846

fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514
fdo#103070 https://bugs.freedesktop.org/show_bug.cgi?id=103070
fdo#102846 https://bugs.freedesktop.org/show_bug.cgi?id=102846

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:451s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:473s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:395s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:580s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:283s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:518s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:524s
fi-byt-j1900 total:118  pass:96   dwarn:0   dfail:0   fail:0   skip:21 
fi-byt-n2820 total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  
time:516s
fi-cfl-s total:289  pass:253  dwarn:4   dfail:0   fail:0   skip:32  
time:557s
fi-cnl-y total:118  pass:97   dwarn:0   dfail:0   fail:0   skip:20 
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:436s
fi-glk-1 total:118  pass:96   dwarn:0   dfail:0   fail:0   skip:21 
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:434s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:417s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:459s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:496s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:469s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:507s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:581s
fi-kbl-7567u total:289  pass:265  dwarn:4   dfail:0   fail:0   skip:20  
time:490s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:593s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:653s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:461s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:658s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:533s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:514s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:478s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:583s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:426s

cc58e6d2bc38542af8f8031d4b79f4069bba6afc drm-tip: 2017y-10m-10d-15h-40m-22s UTC 
integration manifest
295e2b3f602a drm/i915/pmu: Add RC6 residency metrics
61b3010492b3 drm/i915: Convert intel_rc6_residency_us to ns
44328c271e16 drm/i915/pmu: Add interrupt count metric
6a2b29848366 drm/i915: Gate engine stats collection with a static key
f2c2bb645669 drm/i915/pmu: Wire up engine busy stats to PMU
abd84e9b8fa3 drm/i915: Engine busy time tracking
5888f77f106e drm/i915: Wrap context schedule notification
2ac1945af3d7 drm/i915/pmu: Suspend sampling when GPU is idle
fe0d9bc497d8 drm/i915/pmu: Expose a PMU interface for perf queries
2fc0bc406db8 drm/i915: Extract intel_get_cagf

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5979/
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[Intel-gfx] ✓ Fi.CI.IGT: success for Adding NV12 support (rev3)

[Patchwork]

== Series Details ==

Series: Adding NV12 support (rev3)
URL   : https://patchwork.freedesktop.org/series/28103/
State : success

== Summary ==

shard-hswtotal:2552 pass:1431 dwarn:5   dfail:0   fail:13  skip:1103 
time:9650s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5971/shards.html
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Re: [Intel-gfx] [PATCH i-g-t v6 7/9] tests/perf_pmu: Tests for i915 PMU API

[Chris Wilson]

Quoting Tvrtko Ursulin (2017-10-10 15:17:54)
> +static void
> +busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
> +  const unsigned int num_engines)
> +{
> +   const struct intel_execution_engine2 *e_;
> +   uint64_t val[num_engines];
> +   int fd[num_engines];
> +   igt_spin_t *spin;
> +   unsigned int busy_idx, i;
> +
> +   i = 0;
> +   fd[0] = -1;
> +   for_each_engine_class_instance(fd, e_) {
> +   if (!gem_has_engine(gem_fd, e_->class, e_->instance))
> +   continue;
> +   else if (e == e_)
> +   busy_idx = i;
> +
> +   fd[i++] = open_group(I915_PMU_ENGINE_BUSY(e_->class,
> + e_->instance),
> +fd[0]);
> +   }
igt_assert(i == num_engines);

Feels like a bug waiting to happen; a trap.

> +static void
> +test_frequency(int gem_fd)
> +{
> +   const uint64_t duration_ns = 2e9;
> +   uint32_t min_freq, max_freq, boost_freq;
> +   uint64_t min[2], max[2], start[2];
> +   igt_spin_t *spin;
> +   int fd, sysfs;
> +
> +   sysfs = igt_sysfs_open(gem_fd, NULL);
> +   igt_require(sysfs >= 0);
> +
> +   min_freq = igt_sysfs_get_u32(sysfs, "gt_RPn_freq_mhz");
> +   max_freq = igt_sysfs_get_u32(sysfs, "gt_RP0_freq_mhz");
> +   boost_freq = igt_sysfs_get_u32(sysfs, "gt_boost_freq_mhz");
> +   igt_require(min_freq > 0 && max_freq > 0 && boost_freq > 0);
> +   igt_require(max_freq > min_freq);
> +   igt_require(boost_freq > min_freq);
> +
> +   fd = open_group(I915_PMU_REQUESTED_FREQUENCY, -1);
> +   open_group(I915_PMU_ACTUAL_FREQUENCY, fd);
> +
> +   /*
> +* Set GPU to min frequency and read PMU counters.
> +*/
> +   igt_require(igt_sysfs_set_u32(sysfs, "gt_max_freq_mhz", min_freq));
> +   igt_require(igt_sysfs_get_u32(sysfs, "gt_max_freq_mhz") == min_freq);
> +   igt_require(igt_sysfs_set_u32(sysfs, "gt_boost_freq_mhz", min_freq));
> +   igt_require(igt_sysfs_get_u32(sysfs, "gt_boost_freq_mhz") == 
> min_freq);
> +
> +   pmu_read_multi(fd, 2, start);
> +
> +   spin = igt_spin_batch_new(gem_fd, 0, I915_EXEC_RENDER, 0);
> +   igt_spin_batch_set_timeout(spin, duration_ns);
> +   gem_sync(gem_fd, spin->handle);
> +
> +   pmu_read_multi(fd, 2, min);
> +   min[0] -= start[0];
> +   min[1] -= start[1];
> +
> +   igt_spin_batch_free(gem_fd, spin);
> +
> +   usleep(1e6);
> +
> +   /*
> +* Set GPU to max frequency and read PMU counters.
> +*/
> +   igt_require(igt_sysfs_set_u32(sysfs, "gt_max_freq_mhz", max_freq));
> +   igt_require(igt_sysfs_get_u32(sysfs, "gt_max_freq_mhz") == max_freq);
> +   igt_require(igt_sysfs_set_u32(sysfs, "gt_boost_freq_mhz", 
> boost_freq));
> +   igt_require(igt_sysfs_get_u32(sysfs, "gt_boost_freq_mhz") == 
> boost_freq);
> +
> +   igt_require(igt_sysfs_set_u32(sysfs, "gt_min_freq_mhz", max_freq));
> +   igt_require(igt_sysfs_get_u32(sysfs, "gt_min_freq_mhz") == max_freq);
> +
> +   pmu_read_multi(fd, 2, start);
> +
> +   spin = igt_spin_batch_new(gem_fd, 0, I915_EXEC_RENDER, 0);
> +   igt_spin_batch_set_timeout(spin, duration_ns);
> +   gem_sync(gem_fd, spin->handle);
> +
> +   pmu_read_multi(fd, 2, max);
> +   max[0] -= start[0];
> +   max[1] -= start[1];
> +
> +   igt_spin_batch_free(gem_fd, spin);
> +
> +   /*
> +* Restore min/max.
> +*/
> +   igt_require(igt_sysfs_set_u32(sysfs, "gt_min_freq_mhz", min_freq));
> +   igt_require(igt_sysfs_get_u32(sysfs, "gt_min_freq_mhz") == min_freq);

The test is done at this point, and you are just being neat and tidy for
the next user. We don't need to do anything but warn:

igt_sysfs_set_u32(sysfs, "gt_min_freq_mhz");
if (igt_sysfs_get_u32(sysfs, "gt_min_freq_mhz") != min_freq)
igt_warn("Unable to restore min frequency to save value [%d MHz], now 
%d MHz\n",
 min_freq, igt_sysfs_get_u32(sysfs, "gt_min_freq_mhz"));
> +
> +   close(fd);

Add to the list of subtests that want a destructor (for clean error
paths).

Reviewed-by: Chris Wilson 
-Chris
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/uc: Firmware code reorg

[Patchwork]

== Series Details ==

Series: drm/i915/uc: Firmware code reorg
URL   : https://patchwork.freedesktop.org/series/31666/
State : failure

== Summary ==

Series 31666v1 drm/i915/uc: Firmware code reorg
https://patchwork.freedesktop.org/api/1.0/series/31666/revisions/1/mbox/

Test debugfs_test:
Subgroup read_all_entries:
pass   -> SKIP   (fi-glk-1)
Test drv_hangman:
Subgroup error-state-basic:
pass   -> SKIP   (fi-glk-1)
Test gem_busy:
Subgroup basic-busy-default:
pass   -> SKIP   (fi-glk-1)
Subgroup basic-hang-default:
pass   -> SKIP   (fi-glk-1)
Test gem_close_race:
Subgroup basic-process:
pass   -> SKIP   (fi-glk-1)
Subgroup basic-threads:
pass   -> SKIP   (fi-glk-1)
Test gem_cpu_reloc:
Subgroup basic:
pass   -> SKIP   (fi-glk-1)
Test gem_cs_tlb:
Subgroup basic-default:
pass   -> SKIP   (fi-glk-1)
Test gem_ctx_create:
Subgroup basic:
pass   -> SKIP   (fi-glk-1)
Subgroup basic-files:
pass   -> SKIP   (fi-glk-1)
Test gem_ctx_exec:
Subgroup basic:
pass   -> SKIP   (fi-glk-1)
Test gem_ctx_switch:
Subgroup basic-default:
pass   -> SKIP   (fi-glk-1)
Subgroup basic-default-heavy:
pass   -> SKIP   (fi-glk-1)
Test gem_exec_basic:
Subgroup basic-blt:
pass   -> SKIP   (fi-glk-1)
Subgroup basic-bsd:
pass   -> SKIP   (fi-glk-1)
Subgroup basic-default:
pass   -> SKIP   (fi-glk-1)
Subgroup basic-render:
pass   -> SKIP   (fi-glk-1)
Subgroup basic-vebox:
pass   -> SKIP   (fi-glk-1)
Subgroup gtt-blt:
pass   -> SKIP   (fi-glk-1)
Subgroup gtt-bsd:
pass   -> SKIP   (fi-glk-1)
Subgroup gtt-default:
pass   -> SKIP   (fi-glk-1)
Subgroup gtt-render:
pass   -> SKIP   (fi-glk-1)
Subgroup gtt-vebox:
pass   -> SKIP   (fi-glk-1)
Subgroup readonly-blt:
pass   -> SKIP   (fi-glk-1)
Subgroup readonly-bsd:
pass   -> SKIP   (fi-glk-1)
Subgroup readonly-default:
pass   -> SKIP   (fi-glk-1)
Subgroup readonly-render:
pass   -> SKIP   (fi-glk-1)
Subgroup readonly-vebox:
pass   -> SKIP   (fi-glk-1)
Test gem_exec_create:
Subgroup basic:
pass   -> SKIP   (fi-glk-1)
Test gem_exec_fence:
Subgroup basic-busy-default:
pass   -> SKIP   (fi-glk-1)
Subgroup basic-wait-default:
pass   -> SKIP   (fi-glk-1)
Subgroup basic-await-default:
pass   -> SKIP   (fi-glk-1)
Subgroup await-hang-default:
pass   -> SKIP   (fi-glk-1)
Subgroup nb-await-default:
pass   -> SKIP   (fi-glk-1)
Test gem_exec_flush:
Subgroup basic-batch-kernel-default-uc:
pass   -> SKIP   (fi-glk-1)
Subgroup basic-batch-kernel-default-wb:
pass   -> SKIP   (fi-glk-1)
Subgroup basic-uc-pro-default:
pass   -> SKIP   (fi-glk-1)
Subgroup basic-uc-prw-default:
pass   -> SKIP   (fi-glk-1)
Subgroup basic-uc-ro-default:
pass   -> SKIP   (fi-glk-1)
Subgroup basic-uc-rw-default:
pass   -> SKIP   (fi-glk-1)
Subgroup basic-uc-set-default:
pass   -> SKIP   (fi-glk-1)
Subgroup basic-wb-pro-default:
pass   -> SKIP   (fi-glk-1)
WARNING: Long output truncated

cc58e6d2bc38542af8f8031d4b79f4069bba6afc drm-tip: 2017y-10m-10d-15h-40m-22s UTC 
integration manifest
0c88fac6ee50 HAX enable GuC submission for CI
e0fbddca8865 drm/i915/huc: Move fw select function
60f6548efd03 drm/i915/uc: Unify firmware loading
95591d4be13e drm/i915/uc: Improve debug messages in firmware fetch
cfc9af96a481 drm/i915/guc: Pick better place for Guc final status message
4c019d8c6bf2 drm/i915/guc: Move firmware size check out of generic code
f36e7a27bed8 drm/i915/guc: Reorder functions in intel_guc_fw.c
37f173634576 drm/i915/guc: Rename intel_guc_loader.c to intel_guc_fw.c
235d82ecf4f4 drm/i915/guc: Move doc near related definitions
78302271ab2c drm/i915/guc: Move GuC boot param initialization out of xfer
401c66e2 drm/i915: Move intel_guc_wopcm_size to intel_guc.c

== Logs ==

For more details see: 

Re: [Intel-gfx] [PATCH i-g-t 2/2] tests/pm_backlight: Enable all possible outputs to allow tests to succeed.

[Maarten Lankhorst]

Op 10-10-17 om 18:14 schreef Ville Syrjälä:
> On Tue, Oct 10, 2017 at 06:04:28PM +0200, Maarten Lankhorst wrote:
>> If all outputs are disabled before this test is run, then the test
>> will fail because actual_brightness stays at 0 instead of the value
>> of the desired brightness. Fix this by enabling all outputs at the
>> start of this test.
>>
>> Sample failure:
>> IGT-Version: 1.20-g01c550a27986 (x86_64) (Linux: 4.14.0-rc3-fbconhax+ x86_64)
>> (pm_backlight:1203) CRITICAL: Test assertion failure function 
>> test_and_verify, file pm_backlight.c:111:
>> (pm_backlight:1203) CRITICAL: Failed assertion: ({ typeof(0) _a = (0); 
>> typeof(val - tolerance) _b = (val - tolerance); _a > _b ? _a : _b; }) <= 
>> result
>> (pm_backlight:1203) CRITICAL: error: 91200 > 0
>>
>> Signed-off-by: Maarten Lankhorst 
>> ---
>>  tests/pm_backlight.c | 27 +++
>>  1 file changed, 27 insertions(+)
>>
>> diff --git a/tests/pm_backlight.c b/tests/pm_backlight.c
>> index 8258d4e4c124..b365c7f6dc60 100644
>> --- a/tests/pm_backlight.c
>> +++ b/tests/pm_backlight.c
>> @@ -155,13 +155,37 @@ igt_main
>>  {
>>  struct context context = {0};
>>  int old;
>> +igt_display_t display;
>>  
>>  igt_skip_on_simulation();
>>  
>>  igt_fixture {
>> +enum pipe pipe;
>> +
>>  /* Get the max value and skip the whole test if sysfs interface 
>> not available */
>>  igt_skip_on(backlight_read(, "brightness"));
>>  igt_assert(backlight_read(, "max_brightness") > -1);
>> +
>> +/*
>> + * Backlight tests requires the output to be enabled,
>> + * try to enable all.
>> + */
>> +kmstest_set_vt_graphics_mode();
>> +igt_display_init(, drm_open_driver(DRIVER_INTEL));
>> +
>> +for_each_pipe(, pipe) {
>> +igt_output_t *output;
>> +
>> +for_each_valid_output_on_pipe(, pipe, output) {
>> +if (output->pending_pipe != PIPE_NONE)
>> +continue;
>> +
>> +igt_output_set_pipe(output, pipe);
>> +break;
>> +}
>> +}
> Since the test depends on intel_backlight I think we could even look up
> the correct backlight based on the connector. Would actually guarantee
> that we manage to light up the correct connector instead of wasting our
> precious pipes lighting up stuff we don't need.
Through readlink /sys/class/backlight/intel_backlight/device you mean? Should 
be doable, but feels hacky..
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Re: [Intel-gfx] [PATCH i-g-t 2/2] tests/pm_backlight: Enable all possible outputs to allow tests to succeed.

[Ville Syrjälä]

On Tue, Oct 10, 2017 at 06:04:28PM +0200, Maarten Lankhorst wrote:
> If all outputs are disabled before this test is run, then the test
> will fail because actual_brightness stays at 0 instead of the value
> of the desired brightness. Fix this by enabling all outputs at the
> start of this test.
> 
> Sample failure:
> IGT-Version: 1.20-g01c550a27986 (x86_64) (Linux: 4.14.0-rc3-fbconhax+ x86_64)
> (pm_backlight:1203) CRITICAL: Test assertion failure function 
> test_and_verify, file pm_backlight.c:111:
> (pm_backlight:1203) CRITICAL: Failed assertion: ({ typeof(0) _a = (0); 
> typeof(val - tolerance) _b = (val - tolerance); _a > _b ? _a : _b; }) <= 
> result
> (pm_backlight:1203) CRITICAL: error: 91200 > 0
> 
> Signed-off-by: Maarten Lankhorst 
> ---
>  tests/pm_backlight.c | 27 +++
>  1 file changed, 27 insertions(+)
> 
> diff --git a/tests/pm_backlight.c b/tests/pm_backlight.c
> index 8258d4e4c124..b365c7f6dc60 100644
> --- a/tests/pm_backlight.c
> +++ b/tests/pm_backlight.c
> @@ -155,13 +155,37 @@ igt_main
>  {
>   struct context context = {0};
>   int old;
> + igt_display_t display;
>  
>   igt_skip_on_simulation();
>  
>   igt_fixture {
> + enum pipe pipe;
> +
>   /* Get the max value and skip the whole test if sysfs interface 
> not available */
>   igt_skip_on(backlight_read(, "brightness"));
>   igt_assert(backlight_read(, "max_brightness") > -1);
> +
> + /*
> +  * Backlight tests requires the output to be enabled,
> +  * try to enable all.
> +  */
> + kmstest_set_vt_graphics_mode();
> + igt_display_init(, drm_open_driver(DRIVER_INTEL));
> +
> + for_each_pipe(, pipe) {
> + igt_output_t *output;
> +
> + for_each_valid_output_on_pipe(, pipe, output) {
> + if (output->pending_pipe != PIPE_NONE)
> + continue;
> +
> + igt_output_set_pipe(output, pipe);
> + break;
> + }
> + }

Since the test depends on intel_backlight I think we could even look up
the correct backlight based on the connector. Would actually guarantee
that we manage to light up the correct connector instead of wasting our
precious pipes lighting up stuff we don't need.

> +
> + igt_display_commit2(, display.is_atomic ? COMMIT_ATOMIC 
> : COMMIT_LEGACY);
>   }
>  
>   igt_subtest("basic-brightness")
> @@ -174,5 +198,8 @@ igt_main
>   igt_fixture {
>   /* Restore old brightness */
>   backlight_write(old, "brightness");
> +
> + igt_display_fini();
> + close(display.drm_fd);
>   }
>  }
> -- 
> 2.14.1
> 
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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[Intel-gfx] [PATCH i-g-t 2/2] tests/pm_backlight: Enable all possible outputs to allow tests to succeed.

[Maarten Lankhorst]

If all outputs are disabled before this test is run, then the test
will fail because actual_brightness stays at 0 instead of the value
of the desired brightness. Fix this by enabling all outputs at the
start of this test.

Sample failure:
IGT-Version: 1.20-g01c550a27986 (x86_64) (Linux: 4.14.0-rc3-fbconhax+ x86_64)
(pm_backlight:1203) CRITICAL: Test assertion failure function test_and_verify, 
file pm_backlight.c:111:
(pm_backlight:1203) CRITICAL: Failed assertion: ({ typeof(0) _a = (0); 
typeof(val - tolerance) _b = (val - tolerance); _a > _b ? _a : _b; }) <= result
(pm_backlight:1203) CRITICAL: error: 91200 > 0

Signed-off-by: Maarten Lankhorst 
---
 tests/pm_backlight.c | 27 +++
 1 file changed, 27 insertions(+)

diff --git a/tests/pm_backlight.c b/tests/pm_backlight.c
index 8258d4e4c124..b365c7f6dc60 100644
--- a/tests/pm_backlight.c
+++ b/tests/pm_backlight.c
@@ -155,13 +155,37 @@ igt_main
 {
struct context context = {0};
int old;
+   igt_display_t display;
 
igt_skip_on_simulation();
 
igt_fixture {
+   enum pipe pipe;
+
/* Get the max value and skip the whole test if sysfs interface 
not available */
igt_skip_on(backlight_read(, "brightness"));
igt_assert(backlight_read(, "max_brightness") > -1);
+
+   /*
+* Backlight tests requires the output to be enabled,
+* try to enable all.
+*/
+   kmstest_set_vt_graphics_mode();
+   igt_display_init(, drm_open_driver(DRIVER_INTEL));
+
+   for_each_pipe(, pipe) {
+   igt_output_t *output;
+
+   for_each_valid_output_on_pipe(, pipe, output) {
+   if (output->pending_pipe != PIPE_NONE)
+   continue;
+
+   igt_output_set_pipe(output, pipe);
+   break;
+   }
+   }
+
+   igt_display_commit2(, display.is_atomic ? COMMIT_ATOMIC 
: COMMIT_LEGACY);
}
 
igt_subtest("basic-brightness")
@@ -174,5 +198,8 @@ igt_main
igt_fixture {
/* Restore old brightness */
backlight_write(old, "brightness");
+
+   igt_display_fini();
+   close(display.drm_fd);
}
 }
-- 
2.14.1

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[Intel-gfx] [PATCH i-g-t 0/2] tests/BAT: Reduce reliance on fbcon.

[Maarten Lankhorst]

https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_1235/ shows what happens
in BAT if we make fbcon disable all outputs. debugfs_test.read_all_entries 
fails,
probably in a race with fbcon. I'm hoping to solve this by running the test 
twice,
once with all outputs enabled, other with all disabled. This should increase 
testing
coverage.

pm_backlight fails without output setup, and is fixed by simply attempting to 
enable
all outputs when we detect intel_backlight.

Maarten Lankhorst (2):
  tests/debugfs_test: Try to light all outputs to increase chances of finding 
fails.
  tests/pm_backlight: Enable all possible outputs to allow tests to succeed.

 tests/debugfs_test.c | 34 ++
 tests/pm_backlight.c | 27 +++
 2 files changed, 61 insertions(+)

-- 
2.14.1

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[Intel-gfx] [PATCH i-g-t 1/2] tests/debugfs_test: Try to light all outputs to increase chances of finding fails.

[Maarten Lankhorst]

Make sure read_all_entries has all outputs possible enabled, but also
add a test that runs with all outputs disabled.

This will maximize coverage of debugfs reading, and allows the test not
to be dependent on fbcon for setup.

Signed-off-by: Maarten Lankhorst 
---
 tests/debugfs_test.c | 34 ++
 1 file changed, 34 insertions(+)

diff --git a/tests/debugfs_test.c b/tests/debugfs_test.c
index 5e7805e1559e..bf1c5a1b5390 100644
--- a/tests/debugfs_test.c
+++ b/tests/debugfs_test.c
@@ -78,15 +78,48 @@ static void read_and_discard_sysfs_entries(int path_fd)
 igt_main
 {
int fd = -1, debugfs;
+   igt_display_t display;
+
igt_skip_on_simulation();
 
igt_fixture {
fd = drm_open_driver_master(DRIVER_INTEL);
igt_require_gem(fd);
debugfs = igt_debugfs_dir(fd);
+
+   kmstest_set_vt_graphics_mode();
+   igt_display_init(, fd);
}
 
igt_subtest("read_all_entries") {
+   enum pipe pipe;
+
+   /* try to light all pipes */
+   for_each_pipe(, pipe) {
+   igt_output_t *output;
+
+   for_each_valid_output_on_pipe(, pipe, output) {
+   if (output->pending_pipe != PIPE_NONE)
+   continue;
+
+   igt_output_set_pipe(output, pipe);
+   break;
+   }
+   }
+
+   igt_display_commit2(, display.is_atomic ? COMMIT_ATOMIC 
: COMMIT_LEGACY);
+
+   read_and_discard_sysfs_entries(debugfs);
+   }
+
+   igt_subtest("read_all_entries_display_off") {
+   igt_output_t *output;
+
+   for_each_connected_output(, output)
+   igt_output_set_pipe(output, PIPE_NONE);
+
+   igt_display_commit2(, display.is_atomic ? COMMIT_ATOMIC 
: COMMIT_LEGACY);
+
read_and_discard_sysfs_entries(debugfs);
}
 
@@ -112,6 +145,7 @@ igt_main
}
 
igt_fixture {
+   igt_display_fini();
close(debugfs);
close(fd);
}
-- 
2.14.1

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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Use execlists_num_ports instead of size of array

[Patchwork]

== Series Details ==

Series: drm/i915: Use execlists_num_ports instead of size of array
URL   : https://patchwork.freedesktop.org/series/31647/
State : failure

== Summary ==

Test perf:
Subgroup polling:
pass   -> FAIL   (shard-hsw) fdo#102252
Test kms_flip:
Subgroup modeset-vs-vblank-race-interruptible:
pass   -> FAIL   (shard-hsw)

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hswtotal:2552 pass:1428 dwarn:6   dfail:0   fail:15  skip:1103 
time:9651s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5970/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Simplify intel_sanitize_enable_ppgtt

[Patchwork]

== Series Details ==

Series: drm/i915: Simplify intel_sanitize_enable_ppgtt
URL   : https://patchwork.freedesktop.org/series/31665/
State : success

== Summary ==

Series 31665v1 drm/i915: Simplify intel_sanitize_enable_ppgtt
https://patchwork.freedesktop.org/api/1.0/series/31665/revisions/1/mbox/

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> DMESG-WARN (fi-byt-n2820) fdo#101705

fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:451s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:472s
fi-blb-e6850 total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:389s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:571s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 
time:284s
fi-bxt-dsi   total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  
time:518s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:521s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  
time:534s
fi-byt-n2820 total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  
time:517s
fi-cfl-s total:289  pass:256  dwarn:1   dfail:0   fail:0   skip:32  
time:559s
fi-cnl-y total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:619s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:424s
fi-glk-1 total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:597s
fi-hsw-4770  total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:434s
fi-hsw-4770r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:414s
fi-ilk-650   total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  
time:456s
fi-ivb-3520m total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:513s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:472s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:507s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:579s
fi-kbl-7567u total:289  pass:265  dwarn:4   dfail:0   fail:0   skip:20  
time:491s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:590s
fi-pnv-d510  total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  
time:658s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:464s
fi-skl-6700hqtotal:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:653s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:532s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:501s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:474s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:583s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  
time:431s

e30ce0d029c5b5483b51d9164cb5966a083af8de drm-tip: 2017y-10m-10d-15h-14m-09s UTC 
integration manifest
6394a1ed3cb9 drm/i915: Simplify intel_sanitize_enable_ppgtt

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5977/
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[Intel-gfx] [PATCH FOR-CI] gtt-cache-enable

[Matthew Auld]

Signed-off-by: Matthew Auld 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 12 
 drivers/gpu/drm/i915/intel_pm.c | 12 
 2 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 4c605785e2b3..87071d95845f 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2154,6 +2154,18 @@ static void gtt_write_workarounds(struct 
drm_i915_private *dev_priv)
I915_WRITE(GEN8_GAMW_ECO_DEV_RW_IA,
   I915_READ(GEN8_GAMW_ECO_DEV_RW_IA) |
   GAMW_ECO_ENABLE_64K_IPS_FIELD);
+
+   if (INTEL_GEN(dev_priv) >= 8) {
+   bool can_use_gtt_cache = true;
+
+   if (HAS_PAGE_SIZES(dev_priv, I915_GTT_PAGE_SIZE_2M) &&
+   IS_BROADWELL(dev_priv))
+   can_use_gtt_cache = false;
+
+   /* WaGttCachingOffByDefault */
+   I915_WRITE(HSW_GTT_CACHE_EN, can_use_gtt_cache ? 
GTT_CACHE_EN_ALL : 0);
+   WARN_ON_ONCE(can_use_gtt_cache && I915_READ(HSW_GTT_CACHE_EN) 
== 0);
+   }
 }
 
 int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9d0ca2656a23..cef8aa6bfc11 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8453,9 +8453,6 @@ static void skl_init_clock_gating(struct drm_i915_private 
*dev_priv)
 
 static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-   /* The GTT cache must be disabled if the system is using 2M pages. */
-   bool can_use_gtt_cache = !HAS_PAGE_SIZES(dev_priv,
-I915_GTT_PAGE_SIZE_2M);
enum pipe pipe;
 
ilk_init_lp_watermarks(dev_priv);
@@ -8490,9 +8487,6 @@ static void bdw_init_clock_gating(struct drm_i915_private 
*dev_priv)
/* WaProgramL3SqcReg1Default:bdw */
gen8_set_l3sqc_credits(dev_priv, 30, 2);
 
-   /* WaGttCachingOffByDefault:bdw */
-   I915_WRITE(HSW_GTT_CACHE_EN, can_use_gtt_cache ? GTT_CACHE_EN_ALL : 0);
-
/* WaKVMNotificationOnConfigChange:bdw */
I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
   | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
@@ -8765,12 +8759,6 @@ static void chv_init_clock_gating(struct 
drm_i915_private *dev_priv)
 * LSQC Setting Recommendations.
 */
gen8_set_l3sqc_credits(dev_priv, 38, 2);
-
-   /*
-* GTT cache may not work with big pages, so if those
-* are ever enabled GTT cache may need to be disabled.
-*/
-   I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
 }
 
 static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
-- 
2.13.6

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[Intel-gfx] [PATCH 3/3] drm/i915/selftests: Exercise adding requests to a full GGTT

[Chris Wilson]

A bug recently encountered involved the issue where are we were
submitting requests to different ppGTT, each would pin a segment of the
GGTT for its logical context and ring. However, this is invisible to
eviction as we do not tie the context/ring VMA to a request and so do
not automatically wait upon it them (instead they are marked as pinned,
prevent eviction entirely). Instead the eviction code must flush those
contexts by switching to the kernel context. This selftest tries to
fill the GGTT with contexts to exercise a path where the
switch-to-kernel-context failed to make forward progress and we fail
with ENOSPC.

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/selftests/i915_gem_evict.c| 122 +
 .../gpu/drm/i915/selftests/i915_live_selftests.h   |   1 +
 drivers/gpu/drm/i915/selftests/mock_context.c  |   6 +-
 3 files changed, 124 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c 
b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
index 5ea373221f49..c8cb5f562058 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
@@ -24,6 +24,8 @@
 
 #include "../i915_selftest.h"
 
+#include "mock_context.h"
+#include "mock_drm.h"
 #include "mock_gem_device.h"
 
 static int populate_ggtt(struct drm_i915_private *i915)
@@ -325,6 +327,117 @@ static int igt_evict_vm(void *arg)
return err;
 }
 
+static int igt_evict_contexts(void *arg)
+{
+   struct drm_i915_private *i915 = arg;
+   struct intel_engine_cs *engine;
+   enum intel_engine_id id;
+   struct reserved {
+   struct drm_mm_node node;
+   struct reserved *next;
+   } *reserved = NULL;
+   unsigned long count;
+   int err = 0;
+
+   /* Make the GGTT appear small (but leave just enough to function) */
+   count = 0;
+   mutex_lock(>drm.struct_mutex);
+   do {
+   struct reserved *r;
+
+   r = kcalloc(1, sizeof(*r), GFP_KERNEL);
+   if (!r) {
+   err = -ENOMEM;
+   goto out_locked;
+   }
+
+   if (i915_gem_gtt_insert(>ggtt.base, >node,
+   1ul << 20, 0, I915_COLOR_UNEVICTABLE,
+   16ul << 20, i915->ggtt.base.total,
+   PIN_NOEVICT)) {
+   kfree(r);
+   break;
+   }
+
+   r->next = reserved;
+   reserved = r;
+
+   count++;
+   } while (1);
+   mutex_unlock(>drm.struct_mutex);
+   pr_info("Filled GGTT with %lu 1MiB nodes\n", count);
+
+   /* Overfill the GGTT with context objects and so try to evict one. */
+   for_each_engine(engine, i915, id) {
+   struct i915_sw_fence *fence;
+   struct drm_file *file;
+   unsigned long count = 0;
+   unsigned long timeout;
+
+   file = mock_file(i915);
+   if (IS_ERR(file))
+   return PTR_ERR(file);
+
+   timeout = round_jiffies_up(jiffies + HZ/2);
+   fence = i915_sw_fence_create_timer(timeout, GFP_KERNEL);
+   if (IS_ERR(fence))
+   return PTR_ERR(fence);
+
+   count = 0;
+   mutex_lock(>drm.struct_mutex);
+   do {
+   struct drm_i915_gem_request *rq;
+   struct i915_gem_context *ctx;
+
+   ctx = live_context(i915, file);
+   if (!ctx)
+   break;
+
+   rq = i915_gem_request_alloc(engine, ctx);
+   if (IS_ERR(rq)) {
+   if (PTR_ERR(rq) != -ENOMEM) {
+   pr_err("Unexpected error from request 
alloc (ctx hw id %u, on %s): %d\n",
+  ctx->hw_id, engine->name,
+  (int)PTR_ERR(rq));
+   err = PTR_ERR(rq);
+   }
+   break;
+   }
+
+   i915_sw_fence_await_sw_fence_gfp(>submit, fence,
+GFP_KERNEL);
+
+   i915_add_request(rq);
+   count++;
+   } while(!i915_sw_fence_done(fence));
+   mutex_unlock(>drm.struct_mutex);
+
+   i915_sw_fence_timer_flush(fence);
+   i915_sw_fence_timer_put(fence);
+   pr_info("Submitted %lu contexts/requests on %s\n",
+   count, engine->name);
+
+   mock_file_free(i915, file);
+
+   if (err)
+