Re: [Intel-gfx] [PATCH v3 00/12] drm/i915: Separate RC6, RPS, LLC ring Frequency management
On 10/9/2017 8:39 PM, Imre Deak wrote: On Sat, Oct 07, 2017 at 09:33:09AM +0100, Chris Wilson wrote: Quoting Sagar Arun Kamble (2017-10-07 08:07:23) With GuC based SLPC, frequency control will be moved to GuC and Host will continue to control RC6 and LLC ring frequency setup. This needs separate handling of RPS, RC6 and LLC ring frequencies in i915 flows. We still continue use the *gt_powersave routines with separate status variables for RPS, RC6, ring frequency as pm.rps.enabled, pm.rc6.enabled and pm.llc_pstate.configured respectively in dev_priv. Post this, with SLPC changes integrated we can just skip the Host RPS path in i915 PM flows. v2: Added new patch 2. Addressed review comments. Pending review for last 3 patches and patch 2 currently. v3: Fixed checkpatch issue in patch 1. Updated patch 6 with new name for i915_runtime_pm structure variable as runtime_pm. Added new patch 7 to move hw_lock out of rps structure. Updated patch 8 to name rc6/rps/ring state as gt_pm. Updated patch 10 to change the llc pstate enable disable function names. Removed WARN_ON for pcu_lock from lower level functions in patch 11. Also addressed review comments on patch 12. It looks ready to go (as in I couldn't see any problems in this series). Since we are making changes a bit wider than rc6/rps internals (touching pcode and runtime_pm), we could do with an ack or two from other interested parties to make sure we are not digging ourselves into a hole. The changes look good and I haven't spotted any problem, so: Acked-by: Imre Deak In intel_runtime_suspend() what we want after these changes is to check if rc6 is enabled instead of rps, but that's a detail and can be done as a follow-up. Thanks Imre. intel_runtime_suspend change you suggested is done in patch 12. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Parse DSI backlight/cabc ports.
On Tue, 03 Oct 2017, Madhav Chauhan wrote:
> This patch parse DSI backlight/cabc ports info from
> VBT and save them inside local strucutre. This saved info
> can be directly used while initializing DSI for different
> platforms instead of parsing for each platform.
>
> Signed-off-by: Madhav Chauhan
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/intel_bios.c | 63
> ---
> 2 files changed, 55 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b7cba89..fc472bb 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1751,6 +1751,8 @@ struct intel_vbt_data {
> u8 seq_version;
> u32 size;
> u8 *data;
> + u16 bl_ports;
> + u16 cabc_ports;
This is right in the middle of the sequence data. Please move up
e.g. between pps and seq_version.
> const u8 *sequence[MIPI_SEQ_MAX];
> } dsi;
>
> diff --git a/drivers/gpu/drm/i915/intel_bios.c
> b/drivers/gpu/drm/i915/intel_bios.c
> index 3747d8d..88a72cc 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -730,6 +730,56 @@ parse_psr(struct drm_i915_private *dev_priv, const
> struct bdb_header *bdb)
> dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time;
> }
>
> +static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv,
> + u16 version, enum port port)
> +{
> + if (dev_priv->vbt.dsi.config->dual_link && version < 197) {
> + /*
> + * These fields are introduced from the VBT version 197 onwards,
> + * so making sure that these bits are set zero in the previous
> + * versions.
> + */
> + dev_priv->vbt.dsi.config->dl_dcs_cabc_ports = 0;
> + dev_priv->vbt.dsi.config->dl_dcs_backlight_ports = 0;
You could remove this in patch 2. Nobody should be looking at it
anymore.
> + dev_priv->vbt.dsi.bl_ports = 0;
> + dev_priv->vbt.dsi.cabc_ports = 0;
This you don't have to do anyway, it's all zeros by default.
> + return;
> + } else if (dev_priv->vbt.dsi.config->dual_link) {
> + switch (dev_priv->vbt.dsi.config->dl_dcs_backlight_ports) {
> + case DL_DCS_PORT_A:
> + dev_priv->vbt.dsi.bl_ports = BIT(PORT_A);
> + break;
> + case DL_DCS_PORT_C:
> + dev_priv->vbt.dsi.bl_ports = BIT(PORT_C);
> + break;
> + default:
> + case DL_DCS_PORT_A_AND_C:
> + dev_priv->vbt.dsi.bl_ports = BIT(PORT_A) | BIT(PORT_C);
> + break;
> + }
> +
> + switch (dev_priv->vbt.dsi.config->dl_dcs_cabc_ports) {
> + case DL_DCS_PORT_A:
> + dev_priv->vbt.dsi.cabc_ports = BIT(PORT_A);
> + break;
> + case DL_DCS_PORT_C:
> + dev_priv->vbt.dsi.cabc_ports = BIT(PORT_C);
> + break;
> + default:
> + case DL_DCS_PORT_A_AND_C:
> + dev_priv->vbt.dsi.cabc_ports =
> + BIT(PORT_A) | BIT(PORT_C);
> + break;
> + }
> + } else {
> + dev_priv->vbt.dsi.bl_ports = BIT(port);
> + dev_priv->vbt.dsi.cabc_ports = BIT(port);
> + }
> +
> + if (!dev_priv->vbt.dsi.config->cabc_supported)
> + dev_priv->vbt.dsi.cabc_ports = 0;
Would seem reasonable to not initalize it in the first place if it's not
supported. If you do a series of early returns starting with the bdb
version check, then !dual_link, then !cabc_supported, it might be
easiest.
> +}
> +
> static void
> parse_mipi_config(struct drm_i915_private *dev_priv,
> const struct bdb_header *bdb)
> @@ -738,9 +788,10 @@ parse_mipi_config(struct drm_i915_private *dev_priv,
> const struct mipi_config *config;
> const struct mipi_pps_data *pps;
> int panel_type = dev_priv->vbt.panel_type;
> + enum port port;
>
> /* parse MIPI blocks only if LFP type is MIPI */
> - if (!intel_bios_is_dsi_present(dev_priv, NULL))
> + if (!intel_bios_is_dsi_present(dev_priv, &port))
> return;
>
> /* Initialize this to undefined indicating no generic MIPI support */
> @@ -781,15 +832,7 @@ parse_mipi_config(struct drm_i915_private *dev_priv,
> return;
> }
>
> - /*
> - * These fields are introduced from the VBT version 197 onwards,
> - * so making sure that these bits are set zero in the previous
> - * versions.
> - */
> - if (dev_priv->vbt.dsi.config->dual_link && bdb->version < 197) {
> - dev_priv->vbt.dsi.config
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Use existing DSI backlight ports info
On Tue, 03 Oct 2017, Madhav Chauhan wrote:
> This patch re-use already parsed DSI backlight/cabc ports
> info for saving it inside struct intel_dsi rather than
> parsing it at the time of DSI initialization.
>
> Signed-off-by: Madhav Chauhan
With the initialization of dl_dcs_backlight_ports and dl_dcs_cabc_ports
removed, as mentioned in patch 1, this is
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_dsi.c | 37 -
> 1 file changed, 4 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> b/drivers/gpu/drm/i915/intel_dsi.c
> index 20a7b00..6d21ae8 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -1746,42 +1746,13 @@ void intel_dsi_init(struct drm_i915_private *dev_priv)
> else
> intel_encoder->crtc_mask = BIT(PIPE_B);
>
> - if (dev_priv->vbt.dsi.config->dual_link) {
> + if (dev_priv->vbt.dsi.config->dual_link)
> intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
> -
> - switch (dev_priv->vbt.dsi.config->dl_dcs_backlight_ports) {
> - case DL_DCS_PORT_A:
> - intel_dsi->dcs_backlight_ports = BIT(PORT_A);
> - break;
> - case DL_DCS_PORT_C:
> - intel_dsi->dcs_backlight_ports = BIT(PORT_C);
> - break;
> - default:
> - case DL_DCS_PORT_A_AND_C:
> - intel_dsi->dcs_backlight_ports = BIT(PORT_A) |
> BIT(PORT_C);
> - break;
> - }
> -
> - switch (dev_priv->vbt.dsi.config->dl_dcs_cabc_ports) {
> - case DL_DCS_PORT_A:
> - intel_dsi->dcs_cabc_ports = BIT(PORT_A);
> - break;
> - case DL_DCS_PORT_C:
> - intel_dsi->dcs_cabc_ports = BIT(PORT_C);
> - break;
> - default:
> - case DL_DCS_PORT_A_AND_C:
> - intel_dsi->dcs_cabc_ports = BIT(PORT_A) | BIT(PORT_C);
> - break;
> - }
> - } else {
> + else
> intel_dsi->ports = BIT(port);
> - intel_dsi->dcs_backlight_ports = BIT(port);
> - intel_dsi->dcs_cabc_ports = BIT(port);
> - }
>
> - if (!dev_priv->vbt.dsi.config->cabc_supported)
> - intel_dsi->dcs_cabc_ports = 0;
> + intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports;
> + intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports;
>
> /* Create a DSI host (and a device) for each port. */
> for_each_dsi_port(port, intel_dsi->ports) {
--
Jani Nikula, Intel Open Source Technology Center
___
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Re: [Intel-gfx] [PATCH i-g-t] tests/kms_sequence: Add tests for lease ioctls
On 10 October 2017 at 16:57, Dave Airlie wrote: > On 1 October 2017 at 13:52, wrote: >> From: Keith Packard >> >> Validate that the leasing API creates leases that allow access to a >> subset of the available resources and that lease revocation works. > > These don't test the GET and LIST_LEASES interfaces > > At least some basic test coverage for those would be good. This also probably needs the local treatment, though we have to renumber the ioctls from your lease kernel patches. Also subject should be tests/kms_lease: Dave. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Miscellaneous fixes to reduce dependency for I915_MAX_PIPES
== Series Details == Series: drm/i915: Miscellaneous fixes to reduce dependency for I915_MAX_PIPES URL : https://patchwork.freedesktop.org/series/30336/ State : success == Summary == Series 30336v1 drm/i915: Miscellaneous fixes to reduce dependency for I915_MAX_PIPES https://patchwork.freedesktop.org/api/1.0/series/30336/revisions/1/mbox/ Test chamelium: Subgroup dp-crc-fast: pass -> FAIL (fi-kbl-7500u) fdo#102514 Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-b: incomplete -> PASS (fi-kbl-r) Test pm_rpm: Subgroup basic-pci-d3-state: dmesg-warn -> PASS (fi-cfl-s) Test drv_module_reload: Subgroup basic-no-display: pass -> DMESG-WARN (fi-cfl-s) fdo#103022 +1 fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514 fdo#103022 https://bugs.freedesktop.org/show_bug.cgi?id=103022 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:460s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:468s fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:391s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:563s fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:285s fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:519s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:523s fi-byt-j1900 total:289 pass:253 dwarn:1 dfail:0 fail:0 skip:35 time:542s fi-byt-n2820 total:289 pass:249 dwarn:1 dfail:0 fail:0 skip:39 time:521s fi-cfl-s total:289 pass:253 dwarn:4 dfail:0 fail:0 skip:32 time:562s fi-cnl-y total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:616s fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:434s fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:599s fi-hsw-4770 total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:437s fi-hsw-4770r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:417s fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:458s fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:505s fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:475s fi-kbl-7500u total:289 pass:263 dwarn:1 dfail:0 fail:1 skip:24 time:493s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:582s fi-kbl-7567u total:289 pass:265 dwarn:4 dfail:0 fail:0 skip:20 time:486s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:589s fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:0 skip:66 time:657s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:468s fi-skl-6700hqtotal:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:651s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:536s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:508s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:469s fi-snb-2520m total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:578s fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:432s 6a08510077ad5bdbac044038138f217e413cdca2 drm-tip: 2017y-10m-10d-07h-48m-31s UTC integration manifest 22c124d1c731 drm/i915: Cleanup South Error Interrupts 0faa4f41fa42 drm/i915: Favor for_each_pipe() macro ccd126a01524 drm/i915: Fold IRQ pipe masks bf0c5021a39d drm/i915: Remove I915_MAX_PIPES dependency for DDB allocation ea13eae4f2c9 drm/i915: Don't relay on I915_MAX_PIPES == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5963/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Increase atomic update vblank evasion time with lockdep
All our mmio writes take forever with lockdep due to the constant lock acquire&dropping we do. Ville has some patches to only acquire the mmio spinlocks once instead for every single mmio, but those aren't ready yet. As an interim solution just extend our budget slightly when lockdep is enabled, to avoid the rare and sporadic noise in CI. Cc: Ville Syrjala References: https://bugs.freedesktop.org/show_bug.cgi?id=103169 References: https://bugs.freedesktop.org/show_bug.cgi?id=103124 References: https://bugs.freedesktop.org/show_bug.cgi?id=102403 References: https://bugs.freedesktop.org/show_bug.cgi?id=103020 References: https://bugs.freedesktop.org/show_bug.cgi?id=103019 References: https://bugs.freedesktop.org/show_bug.cgi?id=102723 References: https://bugs.freedesktop.org/show_bug.cgi?id=102544 References: https://bugs.freedesktop.org/show_bug.cgi?id=103180 Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_sprite.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index b0d6e3e28d07..65f1bffe295d 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -66,7 +66,11 @@ int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode, 1000 * adjusted_mode->crtc_htotal); } +#if IS_ENABLED(CONFIG_PROVE_LOCKING) +#define VBLANK_EVASION_TIME_US 250 +#else #define VBLANK_EVASION_TIME_US 100 +#endif /** * intel_pipe_update_start() - start update of a set of display registers -- 2.14.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Increase atomic update vblank evasion time with lockdep
On Tue, Oct 10, 2017 at 10:46:57AM +0200, Daniel Vetter wrote: > All our mmio writes take forever with lockdep due to the constant > lock acquire&dropping we do. Ville has some patches to only acquire > the mmio spinlocks once instead for every single mmio, but those > aren't ready yet. > > As an interim solution just extend our budget slightly when lockdep is > enabled, to avoid the rare and sporadic noise in CI. > > Cc: Ville Syrjala > References: https://bugs.freedesktop.org/show_bug.cgi?id=103169 > References: https://bugs.freedesktop.org/show_bug.cgi?id=103124 > References: https://bugs.freedesktop.org/show_bug.cgi?id=102403 > References: https://bugs.freedesktop.org/show_bug.cgi?id=103020 > References: https://bugs.freedesktop.org/show_bug.cgi?id=103019 > References: https://bugs.freedesktop.org/show_bug.cgi?id=102723 > References: https://bugs.freedesktop.org/show_bug.cgi?id=102544 > References: https://bugs.freedesktop.org/show_bug.cgi?id=103180 > Signed-off-by: Daniel Vetter Acked-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/intel_sprite.c | 4 > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_sprite.c > b/drivers/gpu/drm/i915/intel_sprite.c > index b0d6e3e28d07..65f1bffe295d 100644 > --- a/drivers/gpu/drm/i915/intel_sprite.c > +++ b/drivers/gpu/drm/i915/intel_sprite.c > @@ -66,7 +66,11 @@ int intel_usecs_to_scanlines(const struct drm_display_mode > *adjusted_mode, > 1000 * adjusted_mode->crtc_htotal); > } > > +#if IS_ENABLED(CONFIG_PROVE_LOCKING) > +#define VBLANK_EVASION_TIME_US 250 > +#else > #define VBLANK_EVASION_TIME_US 100 > +#endif > > /** > * intel_pipe_update_start() - start update of a set of display registers > -- > 2.14.1 -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] i-g-t/tests: Drop gem_seqno_wrap, gem_pin, gem_hangcheck_forcewake
This improves the GEM tests section of I-G-T to make it more
suitable for CI testing
Cc: Joonas Lahtinen
Signed-off-by: Abdiel Janulgue
---
tests/Makefile.sources | 3 -
tests/gem_hangcheck_forcewake.c | 123 --
tests/gem_pin.c | 248 -
tests/gem_seqno_wrap.c | 483
tests/meson.build | 3 -
5 files changed, 860 deletions(-)
delete mode 100644 tests/gem_hangcheck_forcewake.c
delete mode 100644 tests/gem_pin.c
delete mode 100644 tests/gem_seqno_wrap.c
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index bb6652e..7f52298 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -99,7 +99,6 @@ TESTS_progs = \
gem_gtt_cpu_tlb \
gem_gtt_hog \
gem_gtt_speed \
- gem_hangcheck_forcewake \
gem_largeobject \
gem_linear_blits \
gem_lut_handle \
@@ -112,7 +111,6 @@ TESTS_progs = \
gem_mocs_settings \
gem_partial_pwrite_pread \
gem_persistent_relocs \
- gem_pin \
gem_pipe_control_store_loop \
gem_ppgtt \
gem_pread \
@@ -134,7 +132,6 @@ TESTS_progs = \
gem_ring_sync_copy \
gem_ring_sync_loop \
gem_ringfill \
- gem_seqno_wrap \
gem_set_tiling_vs_blt \
gem_set_tiling_vs_gtt \
gem_set_tiling_vs_pwrite \
diff --git a/tests/gem_hangcheck_forcewake.c b/tests/gem_hangcheck_forcewake.c
deleted file mode 100644
index a3e7554..000
--- a/tests/gem_hangcheck_forcewake.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * Copyright © 2011 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- *Daniel Vetter
- *
- */
-
-#include "igt.h"
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include "drm.h"
-#include "intel_bufmgr.h"
-
-IGT_TEST_DESCRIPTION("Provoke the hangcheck timer on an otherwise idle"
-" system.");
-
-/*
- * Testcase: Provoke the hangcheck timer on an otherwise idle system
- *
- * This tries to hit forcewake locking bugs when the hangcheck runs. Somehow we
- * often luck out and the hangcheck runs while someone else is already holding
- * the dev->struct_mutex.
- *
- * It's imperative that nothing else runs while this test runs, i.e. kill your
X
- * session, please.
- */
-
-static drm_intel_bufmgr *bufmgr;
-struct intel_batchbuffer *batch;
-
-uint32_t blob[2048*2048];
-
-#define MAX_BLT_SIZE 128
-igt_simple_main
-{
- drm_intel_bo *bo = NULL;
- uint32_t tiling_mode = I915_TILING_X;
- unsigned long pitch, act_size;
- int fd, i, devid;
-
- igt_skip_on_simulation();
-
- memset(blob, 'A', sizeof(blob));
-
- fd = drm_open_driver(DRIVER_INTEL);
- igt_require_gem(fd);
-
- bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
- drm_intel_bufmgr_gem_enable_reuse(bufmgr);
- devid = intel_get_drm_devid(fd);
- batch = intel_batchbuffer_alloc(bufmgr, devid);
-
- act_size = 2048;
- igt_info("filling ring\n");
- drm_intel_bo_unreference(bo);
- bo = drm_intel_bo_alloc_tiled(bufmgr, "tiled bo", act_size, act_size,
- 4, &tiling_mode, &pitch, 0);
-
- drm_intel_bo_subdata(bo, 0, act_size*act_size*4, blob);
-
- if (IS_965(devid))
- pitch /= 4;
-
- for (i = 0; i < 1; i++) {
- BLIT_COPY_BATCH_START(XY_SRC_COPY_BLT_SRC_TILED |
- XY_SRC_COPY_BLT_DST_TILED);
- OUT_BATCH((3 << 24) | /* 32 bits */
- (0xcc << 16) | /* copy ROP */
- pitch);
- OUT_BATCH(0 << 16 | 1024);
- OUT_BATCH((2048) << 16 | (2048));
- OUT_RELOC_FENCED(bo, I915_GEM_DOMAIN_RENDER,
I915_GEM_DOMAIN_RENDER, 0);
-
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Increase atomic update vblank evasion time with lockdep
== Series Details == Series: drm/i915: Increase atomic update vblank evasion time with lockdep URL : https://patchwork.freedesktop.org/series/31630/ State : success == Summary == Series 31630v1 drm/i915: Increase atomic update vblank evasion time with lockdep https://patchwork.freedesktop.org/api/1.0/series/31630/revisions/1/mbox/ Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-b: incomplete -> PASS (fi-kbl-r) Test pm_rpm: Subgroup basic-pci-d3-state: dmesg-warn -> PASS (fi-cfl-s) Test drv_module_reload: Subgroup basic-reload: dmesg-warn -> PASS (fi-cfl-s) Subgroup basic-reload-inject: incomplete -> PASS (fi-cfl-s) fdo#103022 fdo#103022 https://bugs.freedesktop.org/show_bug.cgi?id=103022 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:450s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:468s fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:393s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:566s fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:283s fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:526s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:518s fi-byt-j1900 total:289 pass:253 dwarn:1 dfail:0 fail:0 skip:35 time:536s fi-byt-n2820 total:289 pass:249 dwarn:1 dfail:0 fail:0 skip:39 time:517s fi-cfl-s total:289 pass:256 dwarn:1 dfail:0 fail:0 skip:32 time:564s fi-cnl-y total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:614s fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:430s fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:595s fi-hsw-4770 total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:437s fi-hsw-4770r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:418s fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:459s fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:505s fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:480s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:507s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:581s fi-kbl-7567u total:289 pass:265 dwarn:4 dfail:0 fail:0 skip:20 time:486s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:592s fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:0 skip:66 time:665s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:467s fi-skl-6700hqtotal:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:651s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:530s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:518s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:468s fi-snb-2520m total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:580s fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:430s 6a08510077ad5bdbac044038138f217e413cdca2 drm-tip: 2017y-10m-10d-07h-48m-31s UTC integration manifest 230036ee9896 drm/i915: Increase atomic update vblank evasion time with lockdep == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5964/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/5] drm/i915: Remove I915_MAX_PIPES dependency for DDB allocation
On Thu, Sep 14, 2017 at 10:53:03AM +0300, Mika Kahola wrote:
> From: "Kahola, Mika"
>
> Remove dependency for I915_MAX_PIPES by replacing it with
> for_each_pipe() macro.
>
> Signed-off-by: Ramalingam C
> Signed-off-by: Kahola, Mika
> ---
> drivers/gpu/drm/i915/intel_display.c | 5 -
> drivers/gpu/drm/i915/intel_drv.h | 3 ++-
> drivers/gpu/drm/i915/intel_pm.c | 6 --
> 3 files changed, 10 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 8599e42..7811b65 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -12220,7 +12220,10 @@ static void skl_update_crtcs(struct drm_atomic_state
> *state)
> if (updated & cmask || !cstate->base.active)
> continue;
>
> - if (skl_ddb_allocation_overlaps(entries,
> &cstate->wm.skl.ddb, i))
> + if (skl_ddb_allocation_overlaps(dev_priv,
> + entries,
> + &cstate->wm.skl.ddb,
> + i))
> continue;
>
> updated |= cmask;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 3078076..bb61fd7 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1891,7 +1891,8 @@ int intel_enable_sagv(struct drm_i915_private
> *dev_priv);
> int intel_disable_sagv(struct drm_i915_private *dev_priv);
> bool skl_wm_level_equals(const struct skl_wm_level *l1,
>const struct skl_wm_level *l2);
> -bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,
> +bool skl_ddb_allocation_overlaps(struct drm_i915_private *dev_priv,
> + const struct skl_ddb_entry **entries,
>const struct skl_ddb_entry *ddb,
>int ignore);
> bool ilk_disable_lp_wm(struct drm_device *dev);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index fa9055a..7e66141 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4821,16 +4821,18 @@ static inline bool skl_ddb_entries_overlap(const
> struct skl_ddb_entry *a,
> return a->start < b->end && b->start < a->end;
> }
>
> -bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,
> +bool skl_ddb_allocation_overlaps(struct drm_i915_private *dev_priv,
> + const struct skl_ddb_entry **entries,
>const struct skl_ddb_entry *ddb,
>int ignore)
> {
> int i;
I would change this to 'enum pipe pipe' for a bit of extra clarity.
>
> - for (i = 0; i < I915_MAX_PIPES; i++)
> + for_each_pipe(dev_priv, i) {
> if (i != ignore && entries[i] &&
> skl_ddb_entries_overlap(ddb, entries[i]))
> return true;
> + }
>
> return false;
> }
> --
> 2.7.4
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t 1/2] tests/kms_setmode: Request the intiial vbl count with RELATIVE instead of ABSOLUTE
On Mon, Oct 09, 2017 at 07:33:49PM +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > Asking for the initial vblank count by specifying and absolute vblank count > of 0 > doesn't make much sense. Switch to a relative query instead. > > Signed-off-by: Ville Syrjälä > --- > tests/kms_setmode.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/tests/kms_setmode.c b/tests/kms_setmode.c > index 206d360607bb..ed5d97442255 100644 > --- a/tests/kms_setmode.c > +++ b/tests/kms_setmode.c > @@ -431,7 +431,7 @@ static void check_timings(int crtc_idx, const > drmModeModeInfo *kmode) > > memset(&wait, 0, sizeof(wait)); > wait.request.type = kmstest_get_vbl_flag(crtc_idx); > - wait.request.type |= DRM_VBLANK_ABSOLUTE | DRM_VBLANK_NEXTONMISS; > + wait.request.type |= DRM_VBLANK_RELATIVE | DRM_VBLANK_NEXTONMISS; Looking at drm_wait_vblank_is_query() in drm_vblank.c you also want to drop NEXTONMISS. With that: Reviewed-by: Daniel Vetter on both. Cheers, Daniel > do_or_die(drmWaitVBlank(drm_fd, &wait)); > > last_seq = wait.reply.sequence; > -- > 2.13.5 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/5] drm/i915: Favor for_each_pipe() macro
On Thu, Sep 14, 2017 at 10:53:05AM +0300, Mika Kahola wrote: > Favor for_each_pipe() macro when looping through pipes. > > Signed-off-by: Mika Kahola > --- > drivers/gpu/drm/i915/intel_pipe_crc.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c > b/drivers/gpu/drm/i915/intel_pipe_crc.c > index 24d781f..7efe3b7 100644 > --- a/drivers/gpu/drm/i915/intel_pipe_crc.c > +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c > @@ -208,7 +208,7 @@ static int display_crc_ctl_show(struct seq_file *m, void > *data) > struct drm_i915_private *dev_priv = m->private; > int i; Could also do the 'enum pipe pipe' change here. Looks like it shouldn't cause too much noise in the patch. > > - for (i = 0; i < I915_MAX_PIPES; i++) > + for_each_pipe(dev_priv, i) > seq_printf(m, "%c %s\n", pipe_name(i), > pipe_crc_source_name(dev_priv->pipe_crc[i].source)); > > -- > 2.7.4 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Increase atomic update vblank evasion time with lockdep
All our mmio writes take forever with lockdep due to the constant lock acquire&dropping we do. Ville has some patches to only acquire the mmio spinlocks once instead for every single mmio, but those aren't ready yet. As an interim solution just extend our budget slightly when lockdep is enabled, to avoid the rare and sporadic noise in CI. v2: I forgot to add the FIXME comment ... Cc: Ville Syrjala Acked-by: Ville Syrjälä References: https://bugs.freedesktop.org/show_bug.cgi?id=103169 References: https://bugs.freedesktop.org/show_bug.cgi?id=103124 References: https://bugs.freedesktop.org/show_bug.cgi?id=102403 References: https://bugs.freedesktop.org/show_bug.cgi?id=103020 References: https://bugs.freedesktop.org/show_bug.cgi?id=103019 References: https://bugs.freedesktop.org/show_bug.cgi?id=102723 References: https://bugs.freedesktop.org/show_bug.cgi?id=102544 References: https://bugs.freedesktop.org/show_bug.cgi?id=103180 Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_sprite.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index b0d6e3e28d07..f29369622d2c 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -66,7 +66,13 @@ int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode, 1000 * adjusted_mode->crtc_htotal); } +/* FIXME: We should instead only take spinlocks once for the entire update + * instead of once per mmio. */ +#if IS_ENABLED(CONFIG_PROVE_LOCKING) +#define VBLANK_EVASION_TIME_US 250 +#else #define VBLANK_EVASION_TIME_US 100 +#endif /** * intel_pipe_update_start() - start update of a set of display registers -- 2.14.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 0/5] drm/i915: Miscellaneous fixes to reduce dependency for I915_MAX_PIPES
On Thu, Sep 14, 2017 at 10:53:01AM +0300, Mika Kahola wrote: > This patch series introduces fixes to reduce dependency for > I915_MAX_PIPES and minor optimizations to reduce hardcoding. > > Kahola, Mika (1): > drm/i915: Remove I915_MAX_PIPES dependency for DDB allocation > > Mika Kahola (4): > drm/i915: Don't relay on I915_MAX_PIPES > drm/i915: Fold IRQ pipe masks > drm/i915: Favor for_each_pipe() macro > drm/i915: Cleanup South Error Interrupts I replied with a few minor nits to the individual patches. Ttoally up to you whether you want to do those changes or not. For the series Reviewed-by: Ville Syrjälä > > drivers/gpu/drm/i915/i915_irq.c | 19 +++ > drivers/gpu/drm/i915/i915_reg.h | 3 --- > drivers/gpu/drm/i915/intel_audio.c| 2 +- > drivers/gpu/drm/i915/intel_display.c | 5 - > drivers/gpu/drm/i915/intel_drv.h | 3 ++- > drivers/gpu/drm/i915/intel_pipe_crc.c | 9 + > drivers/gpu/drm/i915/intel_pm.c | 6 -- > 7 files changed, 23 insertions(+), 24 deletions(-) > > -- > 2.7.4 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 0/5] drm/i915: Miscellaneous fixes to reduce dependency for I915_MAX_PIPES
On Thursday, September 14, 2017 12:53:01 AM PDT Mika Kahola wrote: > This patch series introduces fixes to reduce dependency for > I915_MAX_PIPES and minor optimizations to reduce hardcoding. > > Kahola, Mika (1): > drm/i915: Remove I915_MAX_PIPES dependency for DDB allocation > > Mika Kahola (4): Looks like you've got two email addresses going on here. > drm/i915: Don't relay on I915_MAX_PIPES > drm/i915: Fold IRQ pipe masks > drm/i915: Favor for_each_pipe() macro > drm/i915: Cleanup South Error Interrupts > > drivers/gpu/drm/i915/i915_irq.c | 19 +++ > drivers/gpu/drm/i915/i915_reg.h | 3 --- > drivers/gpu/drm/i915/intel_audio.c| 2 +- > drivers/gpu/drm/i915/intel_display.c | 5 - > drivers/gpu/drm/i915/intel_drv.h | 3 ++- > drivers/gpu/drm/i915/intel_pipe_crc.c | 9 + > drivers/gpu/drm/i915/intel_pm.c | 6 -- > 7 files changed, 23 insertions(+), 24 deletions(-) Series is: Reviewed-by: Kenneth Graunke signature.asc Description: This is a digitally signed message part. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Use rcu instead of stop_machine in set_wedged
Quoting Daniel Vetter (2017-10-09 17:44:01) > stop_machine is not really a locking primitive we should use, except > when the hw folks tell us the hw is broken and that's the only way to > work around it. > > This patch tries to address the locking abuse of stop_machine() from > > commit 20e4933c478a1ca694b38fa4ac44d99e659941f5 > Author: Chris Wilson > Date: Tue Nov 22 14:41:21 2016 + > > drm/i915: Stop the machine as we install the wedged submit_request handler > > Chris said parts of the reasons for going with stop_machine() was that > it's no overhead for the fast-path. But these callbacks use irqsave > spinlocks and do a bunch of MMIO, and rcu_read_lock is _real_ fast. > > To stay as close as possible to the stop_machine semantics we first > update all the submit function pointers to the nop handler, then call > synchronize_rcu() to make sure no new requests can be submitted. This > should give us exactly the huge barrier we want. > > I pondered whether we should annotate engine->submit_request as __rcu > and use rcu_assign_pointer and rcu_dereference on it. But the reason > behind those is to make sure the compiler/cpu barriers are there for > when you have an actual data structure you point at, to make sure all > the writes are seen correctly on the read side. But we just have a > function pointer, and .text isn't changed, so no need for these > barriers and hence no need for annotations. > > Unfortunately there's a complication with the call to > intel_engine_init_global_seqno: This is still broken in the same way as nop_submit_request may execute while you sleep, breaking cancel_requests. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 0/5] drm/i915: Miscellaneous fixes to reduce dependency for I915_MAX_PIPES
On Tue, 2017-10-10 at 12:19 +0300, Ville Syrjälä wrote: > On Thu, Sep 14, 2017 at 10:53:01AM +0300, Mika Kahola wrote: > > > > This patch series introduces fixes to reduce dependency for > > I915_MAX_PIPES and minor optimizations to reduce hardcoding. > > > > Kahola, Mika (1): > > drm/i915: Remove I915_MAX_PIPES dependency for DDB allocation > > > > Mika Kahola (4): > > drm/i915: Don't relay on I915_MAX_PIPES > > drm/i915: Fold IRQ pipe masks > > drm/i915: Favor for_each_pipe() macro > > drm/i915: Cleanup South Error Interrupts > I replied with a few minor nits to the individual patches. Ttoally up > to > you whether you want to do those changes or not. > > For the series > Reviewed-by: Ville Syrjälä Thanks Ville for review. I will change it 'enum pipe pipe'. It's cleaner that way. > > > > > > > drivers/gpu/drm/i915/i915_irq.c | 19 +++ > > drivers/gpu/drm/i915/i915_reg.h | 3 --- > > drivers/gpu/drm/i915/intel_audio.c| 2 +- > > drivers/gpu/drm/i915/intel_display.c | 5 - > > drivers/gpu/drm/i915/intel_drv.h | 3 ++- > > drivers/gpu/drm/i915/intel_pipe_crc.c | 9 + > > drivers/gpu/drm/i915/intel_pm.c | 6 -- > > 7 files changed, 23 insertions(+), 24 deletions(-) > > > > -- > > 2.7.4 > > > > ___ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Mika Kahola - Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t 1/2] tests/kms_setmode: Request the intiial vbl count with RELATIVE instead of ABSOLUTE
On Tue, Oct 10, 2017 at 11:16:23AM +0200, Daniel Vetter wrote: > On Mon, Oct 09, 2017 at 07:33:49PM +0300, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > Asking for the initial vblank count by specifying and absolute vblank count > > of 0 > > doesn't make much sense. Switch to a relative query instead. > > > > Signed-off-by: Ville Syrjälä > > --- > > tests/kms_setmode.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/tests/kms_setmode.c b/tests/kms_setmode.c > > index 206d360607bb..ed5d97442255 100644 > > --- a/tests/kms_setmode.c > > +++ b/tests/kms_setmode.c > > @@ -431,7 +431,7 @@ static void check_timings(int crtc_idx, const > > drmModeModeInfo *kmode) > > > > memset(&wait, 0, sizeof(wait)); > > wait.request.type = kmstest_get_vbl_flag(crtc_idx); > > - wait.request.type |= DRM_VBLANK_ABSOLUTE | DRM_VBLANK_NEXTONMISS; > > + wait.request.type |= DRM_VBLANK_RELATIVE | DRM_VBLANK_NEXTONMISS; > > Looking at drm_wait_vblank_is_query() in drm_vblank.c you also want to > drop NEXTONMISS. Hmm. I think we may want to line things up to a vblank boundary here (but I'd have to re-read the code to confirm that). Without the NEXTONMISS we would just query the current count and continue immediately. Alternative I guess we could drop the NEXTONMISS but instead wait for seq+1. > With that: > > Reviewed-by: Daniel Vetter on both. > > Cheers, Daniel > > do_or_die(drmWaitVBlank(drm_fd, &wait)); > > > > last_seq = wait.reply.sequence; > > -- > > 2.13.5 > > > > ___ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Daniel Vetter > Software Engineer, Intel Corporation > http://blog.ffwll.ch -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 9/9] media-bench.pl: Add busy balancers to the list
From: Tvrtko Ursulin Signed-off-by: Tvrtko Ursulin --- scripts/media-bench.pl | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/scripts/media-bench.pl b/scripts/media-bench.pl index 0956ef0a0621..78f45199e95d 100755 --- a/scripts/media-bench.pl +++ b/scripts/media-bench.pl @@ -47,8 +47,9 @@ my $nop; my %opts; my @balancers = ( 'rr', 'rand', 'qd', 'qdr', 'qdavg', 'rt', 'rtr', 'rtavg', - 'context' ); -my %bal_skip_H = ( 'rr' => 1, 'rand' => 1, 'context' => 1 ); + 'context', 'busy', 'busy-avg' ); +my %bal_skip_H = ( 'rr' => 1, 'rand' => 1, 'context' => 1, , 'busy' => 1, + 'busy-avg' => 1 ); my %bal_skip_R = ( 'context' => 1 ); my @workloads = ( -- 2.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 i-g-t 0/7] IGT PMU support
From: Tvrtko Ursulin 1. Fixes for intel-gpu-overlay to work on top of the proposed i915 PMU perf API. 2. New test to exercise the same API. 3. Update to gem_wsim and media-bench.pl to be able to use engine busyness via PMU for making balancing decisions. v2: * Added gem_wsim and media-bench.pl patches. * Comments and fixes for the perf_pmu test. v3: * A bunch of review feedback implemented. v4: * Tests for semaphore waits and event waits. * Review feedabck. * RAPL PMU for intel-gpu-overlay. Tvrtko Ursulin (7): intel-gpu-overlay: Move local perf implementation to a library intel-gpu-overlay: Consolidate perf PMU access to library intel-gpu-overlay: Fix interrupts PMU readout intel-gpu-overlay: Catch-up to new i915 PMU tests/perf_pmu: Tests for i915 PMU API gem_wsim: Busy stats balancers media-bench.pl: Add busy balancers to the list benchmarks/Makefile.am | 2 +- benchmarks/gem_wsim.c| 142 +++ lib/Makefile.am | 6 +- lib/igt_gt.c | 50 +++ lib/igt_gt.h | 38 ++ lib/igt_perf.c | 58 +++ lib/igt_perf.h | 96 + overlay/Makefile.am | 6 +- overlay/gem-interrupts.c | 25 +- overlay/gpu-freq.c | 29 +- overlay/gpu-perf.c | 3 +- overlay/gpu-top.c| 87 ++--- overlay/perf.c | 26 -- overlay/perf.h | 64 overlay/power.c | 22 +- overlay/rc6.c| 41 +- scripts/media-bench.pl | 5 +- tests/Makefile.am| 1 + tests/Makefile.sources | 1 + tests/perf_pmu.c | 957 +++ 20 files changed, 1425 insertions(+), 234 deletions(-) create mode 100644 lib/igt_perf.c create mode 100644 lib/igt_perf.h delete mode 100644 overlay/perf.c delete mode 100644 overlay/perf.h create mode 100644 tests/perf_pmu.c -- 2.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 7/9] tests/perf_pmu: Tests for i915 PMU API
From: Tvrtko Ursulin
A bunch of tests for the new i915 PMU feature.
Parts of the code were initialy sketched by Dmitry Rogozhkin.
v2: (Most suggestions by Chris Wilson)
* Add new class/instance based engine list.
* Add gem_has_engine/gem_require_engine to work with class/instance.
* Use the above two throughout the test.
* Shorten tests to 100ms busy batches, seems enough.
* Add queued counter sanity checks.
* Use igt_nsec_elapsed.
* Skip on perf -ENODEV in some tests instead of embedding knowledge locally.
* Fix multi ordering for busy accounting.
* Use new guranteed_usleep when sleep time is asserted on.
* Check for no queued when idle/busy.
* Add queued counter init test.
* Add queued tests.
* Consolidate and increase multiple busy engines tests to most-busy and
all-busy tests.
* Guarantte interrupts by using fences.
* Test RC6 via forcewake.
v3:
* Tweak assert in interrupts subtest.
* Sprinkle of comments.
* Fix multi-client test which got broken in v2.
v4:
* Measured instead of guaranteed sleep.
* Missing sync in no_sema.
* Log busyness before asserts for debug.
* access(2) instead of open(2) to determine if cpu0 is hotpluggable.
* Test frequency reporting via min/max setting instead assuming.
^^ All above suggested by Chris Wilson. ^^
* Drop queued subtests to match i915.
* Use long batches with fences to ensure interrupts.
* Test render node as well.
v5:
* Add to meson build. (Petri Latvala)
* Use 1eN constants. (Chris Wilson)
* Add tests for semaphore and event waiting.
Signed-off-by: Tvrtko Ursulin
Cc: Chris Wilson
Cc: Dmitry Rogozhkin
---
lib/igt_gt.c | 50 ++
lib/igt_gt.h | 38 ++
lib/igt_perf.h |9 +-
tests/Makefile.am |1 +
tests/Makefile.sources |1 +
tests/meson.build |1 +
tests/perf_pmu.c | 1238
7 files changed, 1330 insertions(+), 8 deletions(-)
create mode 100644 tests/perf_pmu.c
diff --git a/lib/igt_gt.c b/lib/igt_gt.c
index b3f3b3809eee..4c75811fb1b3 100644
--- a/lib/igt_gt.c
+++ b/lib/igt_gt.c
@@ -568,3 +568,53 @@ bool gem_can_store_dword(int fd, unsigned int engine)
return true;
}
+
+const struct intel_execution_engine2 intel_execution_engines2[] = {
+ { "rcs0", I915_ENGINE_CLASS_RENDER, 0 },
+ { "bcs0", I915_ENGINE_CLASS_COPY, 0 },
+ { "vcs0", I915_ENGINE_CLASS_VIDEO, 0 },
+ { "vcs1", I915_ENGINE_CLASS_VIDEO, 1 },
+ { "vecs0", I915_ENGINE_CLASS_VIDEO_ENHANCE, 0 },
+};
+
+unsigned int
+gem_class_instance_to_eb_flags(int gem_fd,
+ enum drm_i915_gem_engine_class class,
+ unsigned int instance)
+{
+ if (class != I915_ENGINE_CLASS_VIDEO)
+ igt_assert(instance == 0);
+ else
+ igt_assert(instance >= 0 && instance <= 1);
+
+ switch (class) {
+ case I915_ENGINE_CLASS_RENDER:
+ return I915_EXEC_RENDER;
+ case I915_ENGINE_CLASS_COPY:
+ return I915_EXEC_BLT;
+ case I915_ENGINE_CLASS_VIDEO:
+ if (instance == 0) {
+ if (gem_has_bsd2(gem_fd))
+ return I915_EXEC_BSD | I915_EXEC_BSD_RING1;
+ else
+ return I915_EXEC_BSD;
+
+ } else {
+ return I915_EXEC_BSD | I915_EXEC_BSD_RING2;
+ }
+ case I915_ENGINE_CLASS_VIDEO_ENHANCE:
+ return I915_EXEC_VEBOX;
+ case I915_ENGINE_CLASS_OTHER:
+ default:
+ igt_assert(0);
+ };
+}
+
+bool gem_has_engine(int gem_fd,
+ enum drm_i915_gem_engine_class class,
+ unsigned int instance)
+{
+ return gem_has_ring(gem_fd,
+ gem_class_instance_to_eb_flags(gem_fd, class,
+ instance));
+}
diff --git a/lib/igt_gt.h b/lib/igt_gt.h
index 2579cbd37be7..fb67ae1a7d1f 100644
--- a/lib/igt_gt.h
+++ b/lib/igt_gt.h
@@ -25,6 +25,7 @@
#define IGT_GT_H
#include "igt_debugfs.h"
+#include "igt_core.h"
void igt_require_hang_ring(int fd, int ring);
@@ -80,4 +81,41 @@ extern const struct intel_execution_engine {
bool gem_can_store_dword(int fd, unsigned int engine);
+extern const struct intel_execution_engine2 {
+ const char *name;
+ int class;
+ int instance;
+} intel_execution_engines2[];
+
+#define for_each_engine_class_instance(fd__, e__) \
+ for ((e__) = intel_execution_engines2;\
+(e__)->name; \
+(e__)++)
+
+enum drm_i915_gem_engine_class {
+ I915_ENGINE_CLASS_OTHER = 0,
+ I915_ENGINE_CLASS_RENDER = 1,
+ I915_ENGINE_CLASS_COPY = 2,
+ I915_ENGINE_CLASS_VIDEO = 3,
+ I915_ENGINE_CLASS_VIDEO_ENHANCE = 4,
+ I915_ENGINE_CLASS_MAX /* non-ABI */
+};
+
+unsigned int
+gem_class_instance_to_eb_flags(int gem_fd,
+
[Intel-gfx] [PATCH i-g-t 8/9] gem_wsim: Busy stats balancers
From: Tvrtko Ursulin
Add busy and busy-avg balancers which make balancing decisions by looking
at engine busyness via the i915 PMU.
And thus are able to make decisions on the actual instantaneous load of
the system, and not use metrics that lag behind by a batch or two. In
doing so, each client should be able to greedily maximise their own
usage of the system, leading to improved load balancing even in the face
of other uncooperative clients. On the other hand, we are only using the
instantaneous load without coupling in the predictive factor for dispatch
and execution length.
v2:
* Commit text. (Chris Wilson)
* Rename get_stats to get_pmu_stats. (Chris Wilson)
* Fix PMU readout in VCS remap mode.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
benchmarks/Makefile.am | 2 +-
benchmarks/gem_wsim.c | 142 +
2 files changed, 143 insertions(+), 1 deletion(-)
diff --git a/benchmarks/Makefile.am b/benchmarks/Makefile.am
index d066112a32a2..a81a55e01697 100644
--- a/benchmarks/Makefile.am
+++ b/benchmarks/Makefile.am
@@ -21,7 +21,7 @@ gem_latency_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
gem_latency_LDADD = $(LDADD) -lpthread
gem_syslatency_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
gem_syslatency_LDADD = $(LDADD) -lpthread -lrt
-gem_wsim_LDADD = $(LDADD) -lpthread
+gem_wsim_LDADD = $(LDADD) $(top_builddir)/lib/libigt_perf.la -lpthread
EXTRA_DIST= \
README \
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index 82fe6ba9ec5f..8b2cd90659a9 100644
--- a/benchmarks/gem_wsim.c
+++ b/benchmarks/gem_wsim.c
@@ -50,6 +50,7 @@
#include "intel_io.h"
#include "igt_aux.h"
#include "igt_rand.h"
+#include "igt_perf.h"
#include "sw_sync.h"
#include "ewma.h"
@@ -188,6 +189,16 @@ struct workload
uint32_t last[NUM_ENGINES];
} rt;
};
+
+ struct busy_balancer {
+ int fd;
+ bool first;
+ unsigned int num_engines;
+ unsigned int engine_map[5];
+ uint64_t t_prev;
+ uint64_t prev[5];
+ double busy[5];
+ } busy_balancer;
};
static const unsigned int nop_calibration_us = 1000;
@@ -993,6 +1004,8 @@ struct workload_balancer {
unsigned int flags;
unsigned int min_gen;
+ int (*init)(const struct workload_balancer *balancer,
+ struct workload *wrk);
unsigned int (*get_qd)(const struct workload_balancer *balancer,
struct workload *wrk,
enum intel_engine_id engine);
@@ -1242,6 +1255,108 @@ context_balance(const struct workload_balancer
*balancer,
return get_vcs_engine(wrk->ctx_list[w->context].static_vcs);
}
+static unsigned int
+get_engine_busy(const struct workload_balancer *balancer,
+ struct workload *wrk, enum intel_engine_id engine)
+{
+ struct busy_balancer *bb = &wrk->busy_balancer;
+
+ if (engine == VCS2 && (wrk->flags & VCS2REMAP))
+ engine = BCS;
+
+ return bb->busy[bb->engine_map[engine]];
+}
+
+static void
+get_pmu_stats(const struct workload_balancer *b, struct workload *wrk)
+{
+ struct busy_balancer *bb = &wrk->busy_balancer;
+ uint64_t val[7];
+ unsigned int i;
+
+ igt_assert_eq(read(bb->fd, val, sizeof(val)),
+ (2 + bb->num_engines) * sizeof(uint64_t));
+
+ if (!bb->first) {
+ for (i = 0; i < bb->num_engines; i++) {
+ double d;
+
+ d = (val[2 + i] - bb->prev[i]) * 100;
+ d /= val[1] - bb->t_prev;
+ bb->busy[i] = d;
+ }
+ }
+
+ for (i = 0; i < bb->num_engines; i++)
+ bb->prev[i] = val[2 + i];
+
+ bb->t_prev = val[1];
+ bb->first = false;
+}
+
+static enum intel_engine_id
+busy_avg_balance(const struct workload_balancer *balancer,
+struct workload *wrk, struct w_step *w)
+{
+ get_pmu_stats(balancer, wrk);
+
+ return qdavg_balance(balancer, wrk, w);
+}
+
+static enum intel_engine_id
+busy_balance(const struct workload_balancer *balancer,
+struct workload *wrk, struct w_step *w)
+{
+ get_pmu_stats(balancer, wrk);
+
+ return qd_balance(balancer, wrk, w);
+}
+
+static int
+busy_init(const struct workload_balancer *balancer, struct workload *wrk)
+{
+ struct busy_balancer *bb = &wrk->busy_balancer;
+ struct engine_desc {
+ unsigned class, inst;
+ enum intel_engine_id id;
+ } *d, engines[] = {
+ { I915_ENGINE_CLASS_RENDER, 0, RCS },
+ { I915_ENGINE_CLASS_COPY, 0, BCS },
+ { I915_ENGINE_CLASS_VIDEO, 0, VCS1 },
+ { I915_ENGINE_CLASS_VIDEO, 1, VCS2 },
+ { I915_ENGINE_CLASS_VIDEO_ENHANCE, 0, VECS },
+ { 0, 0, VCS }
+ };
+
+ bb
[Intel-gfx] [PATCH i-g-t 5/9] intel-gpu-overlay: Catch-up to new i915 PMU
From: Tvrtko Ursulin
v2: Update for i915 changes.
v3: Use 1eN for large numbers. (Chris Wilson)
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
lib/igt_perf.h | 89 +---
overlay/gem-interrupts.c | 2 +-
overlay/gpu-freq.c | 8 ++---
overlay/gpu-top.c| 68
overlay/power.c | 4 +--
overlay/rc6.c| 20 +--
6 files changed, 116 insertions(+), 75 deletions(-)
diff --git a/lib/igt_perf.h b/lib/igt_perf.h
index cc10cb300aaf..285823786324 100644
--- a/lib/igt_perf.h
+++ b/lib/igt_perf.h
@@ -1,3 +1,27 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
#ifndef I915_PERF_H
#define I915_PERF_H
@@ -5,41 +29,52 @@
#include
-#define I915_SAMPLE_BUSY 0
-#define I915_SAMPLE_WAIT 1
-#define I915_SAMPLE_SEMA 2
+enum drm_i915_gem_engine_class {
+ I915_ENGINE_CLASS_OTHER = 0,
+ I915_ENGINE_CLASS_RENDER = 1,
+ I915_ENGINE_CLASS_COPY = 2,
+ I915_ENGINE_CLASS_VIDEO = 3,
+ I915_ENGINE_CLASS_VIDEO_ENHANCE = 4,
+ I915_ENGINE_CLASS_MAX /* non-ABI */
+};
+
+enum drm_i915_pmu_engine_sample {
+ I915_SAMPLE_BUSY = 0,
+ I915_SAMPLE_WAIT = 1,
+ I915_SAMPLE_SEMA = 2,
+ I915_ENGINE_SAMPLE_MAX /* non-ABI */
+};
-#define I915_SAMPLE_RCS0
-#define I915_SAMPLE_VCS1
-#define I915_SAMPLE_BCS2
-#define I915_SAMPLE_VECS 3
+#define I915_PMU_SAMPLE_BITS (4)
+#define I915_PMU_SAMPLE_MASK (0xf)
+#define I915_PMU_SAMPLE_INSTANCE_BITS (8)
+#define I915_PMU_CLASS_SHIFT \
+ (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS)
-#define __I915_PERF_COUNT(ring, id) ((ring) << 4 | (id))
+#define __I915_PMU_ENGINE(class, instance, sample) \
+ ((class) << I915_PMU_CLASS_SHIFT | \
+ (instance) << I915_PMU_SAMPLE_BITS | \
+ (sample))
-#define I915_PERF_COUNT_RCS_BUSY __I915_PERF_COUNT(I915_SAMPLE_RCS,
I915_SAMPLE_BUSY)
-#define I915_PERF_COUNT_RCS_WAIT __I915_PERF_COUNT(I915_SAMPLE_RCS,
I915_SAMPLE_WAIT)
-#define I915_PERF_COUNT_RCS_SEMA __I915_PERF_COUNT(I915_SAMPLE_RCS,
I915_SAMPLE_SEMA)
+#define I915_PMU_ENGINE_BUSY(class, instance) \
+ __I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY)
-#define I915_PERF_COUNT_VCS_BUSY __I915_PERF_COUNT(I915_SAMPLE_VCS,
I915_SAMPLE_BUSY)
-#define I915_PERF_COUNT_VCS_WAIT __I915_PERF_COUNT(I915_SAMPLE_VCS,
I915_SAMPLE_WAIT)
-#define I915_PERF_COUNT_VCS_SEMA __I915_PERF_COUNT(I915_SAMPLE_VCS,
I915_SAMPLE_SEMA)
+#define I915_PMU_ENGINE_WAIT(class, instance) \
+ __I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT)
-#define I915_PERF_COUNT_BCS_BUSY __I915_PERF_COUNT(I915_SAMPLE_BCS,
I915_SAMPLE_BUSY)
-#define I915_PERF_COUNT_BCS_WAIT __I915_PERF_COUNT(I915_SAMPLE_BCS,
I915_SAMPLE_WAIT)
-#define I915_PERF_COUNT_BCS_SEMA __I915_PERF_COUNT(I915_SAMPLE_BCS,
I915_SAMPLE_SEMA)
+#define I915_PMU_ENGINE_SEMA(class, instance) \
+ __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA)
-#define I915_PERF_COUNT_VECS_BUSY __I915_PERF_COUNT(I915_SAMPLE_VECS,
I915_SAMPLE_BUSY)
-#define I915_PERF_COUNT_VECS_WAIT __I915_PERF_COUNT(I915_SAMPLE_VECS,
I915_SAMPLE_WAIT)
-#define I915_PERF_COUNT_VECS_SEMA __I915_PERF_COUNT(I915_SAMPLE_VECS,
I915_SAMPLE_SEMA)
+#define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x))
-#define I915_PERF_ACTUAL_FREQUENCY 32
-#define I915_PERF_REQUESTED_FREQUENCY 33
-#define I915_PERF_ENERGY 34
-#define I915_PERF_INTERRUPTS 35
+#define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0)
+#define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1)
+#define I915_PMU_INTERRUPTS__I915_PMU_OTHER(2)
+#define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3)
+#define I915_PMU_RC6p_RESIDENCY__I915_PMU_OTHER(4)
+#defi
[Intel-gfx] [PATCH i-g-t 4/9] intel-gpu-overlay: Fix interrupts PMU readout
From: Tvrtko Ursulin
Signed-off-by: Tvrtko Ursulin
---
overlay/gem-interrupts.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/overlay/gem-interrupts.c b/overlay/gem-interrupts.c
index a84aef0398a7..3eda24f4d7eb 100644
--- a/overlay/gem-interrupts.c
+++ b/overlay/gem-interrupts.c
@@ -136,8 +136,12 @@ int gem_interrupts_update(struct gem_interrupts *irqs)
else
val = ret;
} else {
- if (read(irqs->fd, &val, sizeof(val)) < 0)
+ uint64_t data[2];
+
+ if (read(irqs->fd, &data, sizeof(data)) < 0)
return irqs->error = errno;
+
+ val = data[0];
}
update = irqs->last_count == 0;
--
2.9.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 2/9] intel-gpu-overlay: Consolidate perf PMU access to library
From: Tvrtko Ursulin
Various tool modules implement their owm PMU open wrapper which
can be replaced by calling the library one.
v2:
* Remove extra newline. (Chris Wilson)
* Commit msg.
Signed-off-by: Tvrtko Ursulin
---
lib/igt_perf.c | 32
lib/igt_perf.h | 2 ++
overlay/gem-interrupts.c | 16 +---
overlay/gpu-freq.c | 22 ++
overlay/gpu-top.c| 32
overlay/power.c | 17 +
overlay/rc6.c| 24 +++-
7 files changed, 49 insertions(+), 96 deletions(-)
diff --git a/lib/igt_perf.c b/lib/igt_perf.c
index 45cccff0ae53..961a858af9e3 100644
--- a/lib/igt_perf.c
+++ b/lib/igt_perf.c
@@ -2,6 +2,8 @@
#include
#include
#include
+#include
+#include
#include "igt_perf.h"
@@ -24,3 +26,33 @@ uint64_t i915_type_id(void)
return strtoull(buf, 0, 0);
}
+static int _perf_open(int config, int group, int format)
+{
+ struct perf_event_attr attr;
+
+ memset(&attr, 0, sizeof (attr));
+
+ attr.type = i915_type_id();
+ if (attr.type == 0)
+ return -ENOENT;
+
+ attr.config = config;
+
+ if (group >= 0)
+ format &= ~PERF_FORMAT_GROUP;
+
+ attr.read_format = format;
+
+ return perf_event_open(&attr, -1, 0, group, 0);
+}
+
+int perf_i915_open(int config)
+{
+ return _perf_open(config, -1, PERF_FORMAT_TOTAL_TIME_ENABLED);
+}
+
+int perf_i915_open_group(int config, int group)
+{
+ return _perf_open(config, group,
+ PERF_FORMAT_TOTAL_TIME_ENABLED | PERF_FORMAT_GROUP);
+}
diff --git a/lib/igt_perf.h b/lib/igt_perf.h
index a80b311cd1d1..8e674c3a3755 100644
--- a/lib/igt_perf.h
+++ b/lib/igt_perf.h
@@ -62,5 +62,7 @@ perf_event_open(struct perf_event_attr *attr,
}
uint64_t i915_type_id(void);
+int perf_i915_open(int config);
+int perf_i915_open_group(int config, int group);
#endif /* I915_PERF_H */
diff --git a/overlay/gem-interrupts.c b/overlay/gem-interrupts.c
index 7ba54fcd487d..a84aef0398a7 100644
--- a/overlay/gem-interrupts.c
+++ b/overlay/gem-interrupts.c
@@ -36,20 +36,6 @@
#include "gem-interrupts.h"
#include "debugfs.h"
-static int perf_open(void)
-{
- struct perf_event_attr attr;
-
- memset(&attr, 0, sizeof (attr));
-
- attr.type = i915_type_id();
- if (attr.type == 0)
- return -ENOENT;
- attr.config = I915_PERF_INTERRUPTS;
-
- return perf_event_open(&attr, -1, 0, -1, 0);
-}
-
static long long debugfs_read(void)
{
char buf[8192], *b;
@@ -127,7 +113,7 @@ int gem_interrupts_init(struct gem_interrupts *irqs)
{
memset(irqs, 0, sizeof(*irqs));
- irqs->fd = perf_open();
+ irqs->fd = perf_i915_open(I915_PERF_INTERRUPTS);
if (irqs->fd < 0 && interrupts_read() < 0)
irqs->error = ENODEV;
diff --git a/overlay/gpu-freq.c b/overlay/gpu-freq.c
index 7f29b1aa986e..76c5ed9acfd1 100644
--- a/overlay/gpu-freq.c
+++ b/overlay/gpu-freq.c
@@ -33,30 +33,12 @@
#include "gpu-freq.h"
#include "debugfs.h"
-static int perf_i915_open(int config, int group)
-{
- struct perf_event_attr attr;
-
- memset(&attr, 0, sizeof (attr));
-
- attr.type = i915_type_id();
- if (attr.type == 0)
- return -ENOENT;
- attr.config = config;
-
- attr.read_format = PERF_FORMAT_TOTAL_TIME_ENABLED;
- if (group == -1)
- attr.read_format |= PERF_FORMAT_GROUP;
-
- return perf_event_open(&attr, -1, 0, group, 0);
-}
-
static int perf_open(void)
{
int fd;
- fd = perf_i915_open(I915_PERF_ACTUAL_FREQUENCY, -1);
- if (perf_i915_open(I915_PERF_REQUESTED_FREQUENCY, fd) < 0) {
+ fd = perf_i915_open_group(I915_PERF_ACTUAL_FREQUENCY, -1);
+ if (perf_i915_open_group(I915_PERF_REQUESTED_FREQUENCY, fd) < 0) {
close(fd);
fd = -1;
}
diff --git a/overlay/gpu-top.c b/overlay/gpu-top.c
index 06f489dfdc83..812f47d5aced 100644
--- a/overlay/gpu-top.c
+++ b/overlay/gpu-top.c
@@ -48,24 +48,6 @@
#define I915_PERF_RING_WAIT(n) (__I915_PERF_RING(n) + 1)
#define I915_PERF_RING_SEMA(n) (__I915_PERF_RING(n) + 2)
-static int perf_i915_open(int config, int group)
-{
- struct perf_event_attr attr;
-
- memset(&attr, 0, sizeof (attr));
-
- attr.type = i915_type_id();
- if (attr.type == 0)
- return -ENOENT;
- attr.config = config;
-
- attr.read_format = PERF_FORMAT_TOTAL_TIME_ENABLED;
- if (group == -1)
- attr.read_format |= PERF_FORMAT_GROUP;
-
- return perf_event_open(&attr, -1, 0, group, 0);
-}
-
static int perf_init(struct gpu_top *gt)
{
const char *names[] = {
@@ -77,27 +59,29 @@ static int perf_init(struct gpu_top *gt)
};
int n;
- gt->fd = perf_i915_open(I915_PERF_RING_BUSY(0), -1);
+ gt->fd = perf_i915_
[Intel-gfx] [PATCH i-g-t 3/9] lib/perf: Fix data types and general tidy
From: Tvrtko Ursulin
Configuration and format are uint64_t in the perf API.
Tidy some other details as well.
Signed-off-by: Tvrtko Ursulin
---
lib/igt_perf.c | 40 +++-
lib/igt_perf.h | 4 ++--
2 files changed, 21 insertions(+), 23 deletions(-)
diff --git a/lib/igt_perf.c b/lib/igt_perf.c
index 961a858af9e3..208474302fcc 100644
--- a/lib/igt_perf.c
+++ b/lib/igt_perf.c
@@ -9,49 +9,47 @@
uint64_t i915_type_id(void)
{
- char buf[1024];
- int fd, n;
-
- fd = open("/sys/bus/event_source/devices/i915/type", 0);
- if (fd < 0) {
- n = -1;
- } else {
- n = read(fd, buf, sizeof(buf)-1);
- close(fd);
- }
- if (n < 0)
+ char buf[64];
+ ssize_t ret;
+ int fd;
+
+ fd = open("/sys/bus/event_source/devices/i915/type", O_RDONLY);
+ if (fd < 0)
+ return 0;
+
+ ret = read(fd, buf, sizeof(buf) - 1);
+ close(fd);
+ if (ret < 1)
return 0;
- buf[n] = '\0';
- return strtoull(buf, 0, 0);
+ buf[ret] = '\0';
+
+ return strtoull(buf, NULL, 0);
}
-static int _perf_open(int config, int group, int format)
+static int _perf_open(uint64_t config, int group, uint64_t format)
{
- struct perf_event_attr attr;
-
- memset(&attr, 0, sizeof (attr));
+ struct perf_event_attr attr = { };
attr.type = i915_type_id();
if (attr.type == 0)
return -ENOENT;
- attr.config = config;
-
if (group >= 0)
format &= ~PERF_FORMAT_GROUP;
attr.read_format = format;
+ attr.config = config;
return perf_event_open(&attr, -1, 0, group, 0);
}
-int perf_i915_open(int config)
+int perf_i915_open(uint64_t config)
{
return _perf_open(config, -1, PERF_FORMAT_TOTAL_TIME_ENABLED);
}
-int perf_i915_open_group(int config, int group)
+int perf_i915_open_group(uint64_t config, int group)
{
return _perf_open(config, group,
PERF_FORMAT_TOTAL_TIME_ENABLED | PERF_FORMAT_GROUP);
diff --git a/lib/igt_perf.h b/lib/igt_perf.h
index 8e674c3a3755..cc10cb300aaf 100644
--- a/lib/igt_perf.h
+++ b/lib/igt_perf.h
@@ -62,7 +62,7 @@ perf_event_open(struct perf_event_attr *attr,
}
uint64_t i915_type_id(void);
-int perf_i915_open(int config);
-int perf_i915_open_group(int config, int group);
+int perf_i915_open(uint64_t config);
+int perf_i915_open_group(uint64_t config, int group);
#endif /* I915_PERF_H */
--
2.9.5
___
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[Intel-gfx] [PATCH i-g-t 6/9] intel-gpu-overlay: Use RAPL PMU for power reading
From: Tvrtko Ursulin
Wire up to the RAPL PMU for GPU energy readings.
The only complication is that we have to add code to parse:
# cat /sys/devices/power/events/energy-gpu.scale
2.3283064365386962890625e-10
Signed-off-by: Tvrtko Ursulin
---
lib/igt_perf.c | 16 --
lib/igt_perf.h | 1 +
overlay/power.c | 156 ++--
overlay/power.h | 2 +
4 files changed, 133 insertions(+), 42 deletions(-)
diff --git a/lib/igt_perf.c b/lib/igt_perf.c
index 208474302fcc..0221461e918f 100644
--- a/lib/igt_perf.c
+++ b/lib/igt_perf.c
@@ -27,11 +27,12 @@ uint64_t i915_type_id(void)
return strtoull(buf, NULL, 0);
}
-static int _perf_open(uint64_t config, int group, uint64_t format)
+static int
+_perf_open(uint64_t type, uint64_t config, int group, uint64_t format)
{
struct perf_event_attr attr = { };
- attr.type = i915_type_id();
+ attr.type = type;
if (attr.type == 0)
return -ENOENT;
@@ -46,11 +47,18 @@ static int _perf_open(uint64_t config, int group, uint64_t
format)
int perf_i915_open(uint64_t config)
{
- return _perf_open(config, -1, PERF_FORMAT_TOTAL_TIME_ENABLED);
+ return _perf_open(i915_type_id(), config, -1,
+ PERF_FORMAT_TOTAL_TIME_ENABLED);
}
int perf_i915_open_group(uint64_t config, int group)
{
- return _perf_open(config, group,
+ return _perf_open(i915_type_id(), config, group,
PERF_FORMAT_TOTAL_TIME_ENABLED | PERF_FORMAT_GROUP);
}
+
+int igt_perf_open(uint64_t type, uint64_t config)
+{
+ return _perf_open(type, config, -1,
+ PERF_FORMAT_TOTAL_TIME_ENABLED);
+}
diff --git a/lib/igt_perf.h b/lib/igt_perf.h
index 285823786324..b1f525739c69 100644
--- a/lib/igt_perf.h
+++ b/lib/igt_perf.h
@@ -99,5 +99,6 @@ perf_event_open(struct perf_event_attr *attr,
uint64_t i915_type_id(void);
int perf_i915_open(uint64_t config);
int perf_i915_open_group(uint64_t config, int group);
+int igt_perf_open(uint64_t type, uint64_t config);
#endif /* I915_PERF_H */
diff --git a/overlay/power.c b/overlay/power.c
index 805f4ca7805c..35e446e6bce5 100644
--- a/overlay/power.c
+++ b/overlay/power.c
@@ -30,60 +30,138 @@
#include
#include
#include
+#include
+#include
#include "igt_perf.h"
#include "power.h"
#include "debugfs.h"
-/* XXX Is this exposed through RAPL? */
+static uint64_t filename_to_u64(const char *filename, int base)
+{
+ char buf[64], *b;
+ ssize_t ret;
+ int fd;
-int power_init(struct power *power)
+ fd = open(filename, O_RDONLY);
+ if (fd < 0)
+ return 0;
+
+ ret = read(fd, buf, sizeof(buf) - 1);
+ close(fd);
+ if (ret < 1)
+ return 0;
+
+ buf[ret] = '\0';
+
+ b = buf;
+ while (*b && !isdigit(*b))
+ b++;
+
+ return strtoull(b, NULL, base);
+}
+
+static uint64_t debugfs_file_to_u64(const char *name)
{
- char buf[4096];
- int fd, len;
+ char buf[1024];
- memset(power, 0, sizeof(*power));
+ snprintf(buf, sizeof(buf), "%s/%s", debugfs_dri_path, name);
+
+ return filename_to_u64(buf, 0);
+}
- power->fd = -1;
+static uint64_t rapl_type_id(void)
+{
+ return filename_to_u64("/sys/devices/power/type", 10);
+}
- sprintf(buf, "%s/i915_energy_uJ", debugfs_dri_path);
- fd = open(buf, 0);
+static uint64_t rapl_gpu_power(void)
+{
+ return filename_to_u64("/sys/devices/power/events/energy-gpu", 0);
+}
+
+static double filename_to_double(const char *filename)
+{
+ char *dot = NULL, *e = NULL;
+ unsigned long long int decimal;
+ char buf[64], *b;
+ long int val;
+ long int exponent;
+ double result;
+ ssize_t ret;
+ int fd;
+
+ fd = open(filename, O_RDONLY);
if (fd < 0)
- return power->error = errno;
+ return NAN;
- len = read(fd, buf, sizeof(buf));
+ ret = read(fd, buf, sizeof(buf) - 1);
close(fd);
+ if (ret < 1)
+ return NAN;
+
+ buf[ret] = '\0';
+
+ b = buf;
+ while (*b) {
+ if (*b == '.')
+ dot = b;
+ else if (*b == 'e')
+ e = b;
+ b++;
+ }
- if (len < 0)
- return power->error = errno;
+ if (!dot || !e)
+ return NAN;
- buf[len] = '\0';
- if (strtoull(buf, 0, 0) == 0)
- return power->error = EINVAL;
+ *dot = '\0';
+ *e = '\0';
- return 0;
+ /* Reduce precision to fit in long int. */
+ if ((e - dot) > 18)
+ dot[18] = '\0';
+
+ val = strtoll(buf, NULL, 10);
+ decimal = strtoull(++dot, NULL, 10);
+ exponent = strtoll(++e, NULL, 10);
+
+ result = (double)decimal;
+ result /= round(pow(10, strlen(dot)));
+ res
[Intel-gfx] [PATCH i-g-t 1/9] intel-gpu-overlay: Move local perf implementation to a library
From: Tvrtko Ursulin
Idea is to avoid duplication across multiple users in
upcoming patches.
v2: Commit message and use a separate library instead of piggy-
backing to libintel_tools. (Chris Wilson)
Signed-off-by: Tvrtko Ursulin
---
lib/Makefile.am | 6 +-
overlay/perf.c => lib/igt_perf.c | 2 +-
overlay/perf.h => lib/igt_perf.h | 2 ++
overlay/Makefile.am | 6 ++
overlay/gem-interrupts.c | 3 ++-
overlay/gpu-freq.c | 3 ++-
overlay/gpu-perf.c | 3 ++-
overlay/gpu-top.c| 3 ++-
overlay/power.c | 3 ++-
overlay/rc6.c| 3 ++-
10 files changed, 22 insertions(+), 12 deletions(-)
rename overlay/perf.c => lib/igt_perf.c (94%)
rename overlay/perf.h => lib/igt_perf.h (99%)
diff --git a/lib/Makefile.am b/lib/Makefile.am
index 30ddb92bd0bc..30423dbc8c21 100644
--- a/lib/Makefile.am
+++ b/lib/Makefile.am
@@ -7,7 +7,11 @@ include Makefile.sources
libintel_tools_la_SOURCES = $(lib_source_list)
-noinst_LTLIBRARIES = libintel_tools.la
+libigt_perf_la_SOURCES = \
+ igt_perf.c \
+ igt_perf.h
+
+noinst_LTLIBRARIES = libintel_tools.la libigt_perf.la
noinst_HEADERS = check-ndebug.h
if HAVE_LIBDRM_VC4
diff --git a/overlay/perf.c b/lib/igt_perf.c
similarity index 94%
rename from overlay/perf.c
rename to lib/igt_perf.c
index b8fdc675c587..45cccff0ae53 100644
--- a/overlay/perf.c
+++ b/lib/igt_perf.c
@@ -3,7 +3,7 @@
#include
#include
-#include "perf.h"
+#include "igt_perf.h"
uint64_t i915_type_id(void)
{
diff --git a/overlay/perf.h b/lib/igt_perf.h
similarity index 99%
rename from overlay/perf.h
rename to lib/igt_perf.h
index c44e65f9734c..a80b311cd1d1 100644
--- a/overlay/perf.h
+++ b/lib/igt_perf.h
@@ -1,6 +1,8 @@
#ifndef I915_PERF_H
#define I915_PERF_H
+#include
+
#include
#define I915_SAMPLE_BUSY 0
diff --git a/overlay/Makefile.am b/overlay/Makefile.am
index 39fbcc4ec3cf..cefde2d040f8 100644
--- a/overlay/Makefile.am
+++ b/overlay/Makefile.am
@@ -4,8 +4,8 @@ endif
AM_CPPFLAGS = -I.
AM_CFLAGS = $(DRM_CFLAGS) $(PCIACCESS_CFLAGS) $(CWARNFLAGS) \
- $(CAIRO_CFLAGS) $(OVERLAY_CFLAGS) $(WERROR_CFLAGS)
-LDADD = $(DRM_LIBS) $(PCIACCESS_LIBS) $(CAIRO_LIBS) $(OVERLAY_LIBS)
+ $(CAIRO_CFLAGS) $(OVERLAY_CFLAGS) $(WERROR_CFLAGS) -I$(srcdir)/../lib
+LDADD = $(DRM_LIBS) $(PCIACCESS_LIBS) $(CAIRO_LIBS) $(OVERLAY_LIBS)
$(top_builddir)/lib/libigt_perf.la
intel_gpu_overlay_SOURCES = \
chart.h \
@@ -29,8 +29,6 @@ intel_gpu_overlay_SOURCES = \
igfx.c \
overlay.h \
overlay.c \
- perf.h \
- perf.c \
power.h \
power.c \
rc6.h \
diff --git a/overlay/gem-interrupts.c b/overlay/gem-interrupts.c
index 0150a1d03825..7ba54fcd487d 100644
--- a/overlay/gem-interrupts.c
+++ b/overlay/gem-interrupts.c
@@ -31,9 +31,10 @@
#include
#include
+#include "igt_perf.h"
+
#include "gem-interrupts.h"
#include "debugfs.h"
-#include "perf.h"
static int perf_open(void)
{
diff --git a/overlay/gpu-freq.c b/overlay/gpu-freq.c
index 321c93882238..7f29b1aa986e 100644
--- a/overlay/gpu-freq.c
+++ b/overlay/gpu-freq.c
@@ -28,9 +28,10 @@
#include
#include
+#include "igt_perf.h"
+
#include "gpu-freq.h"
#include "debugfs.h"
-#include "perf.h"
static int perf_i915_open(int config, int group)
{
diff --git a/overlay/gpu-perf.c b/overlay/gpu-perf.c
index f557b9f06a17..3d4a9be91a94 100644
--- a/overlay/gpu-perf.c
+++ b/overlay/gpu-perf.c
@@ -34,7 +34,8 @@
#include
#include
-#include "perf.h"
+#include "igt_perf.h"
+
#include "gpu-perf.h"
#include "debugfs.h"
diff --git a/overlay/gpu-top.c b/overlay/gpu-top.c
index 891a7ea7c0b1..06f489dfdc83 100644
--- a/overlay/gpu-top.c
+++ b/overlay/gpu-top.c
@@ -31,7 +31,8 @@
#include
#include
-#include "perf.h"
+#include "igt_perf.h"
+
#include "igfx.h"
#include "gpu-top.h"
diff --git a/overlay/power.c b/overlay/power.c
index 2f1521b82cd6..84d860cae40c 100644
--- a/overlay/power.c
+++ b/overlay/power.c
@@ -31,7 +31,8 @@
#include
#include
-#include "perf.h"
+#include "igt_perf.h"
+
#include "power.h"
#include "debugfs.h"
diff --git a/overlay/rc6.c b/overlay/rc6.c
index d7047c2f4880..3175bb22308f 100644
--- a/overlay/rc6.c
+++ b/overlay/rc6.c
@@ -31,8 +31,9 @@
#include
#include
+#include "igt_perf.h"
+
#include "rc6.h"
-#include "perf.h"
static int perf_i915_open(int config, int group)
{
--
2.9.5
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Increase atomic update vblank evasion time with lockdep (rev2)
== Series Details == Series: drm/i915: Increase atomic update vblank evasion time with lockdep (rev2) URL : https://patchwork.freedesktop.org/series/31630/ State : success == Summary == Series 31630v2 drm/i915: Increase atomic update vblank evasion time with lockdep https://patchwork.freedesktop.org/api/1.0/series/31630/revisions/2/mbox/ Test chamelium: Subgroup dp-crc-fast: pass -> FAIL (fi-kbl-7500u) fdo#102514 Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-b: incomplete -> PASS (fi-kbl-r) Test pm_rpm: Subgroup basic-pci-d3-state: dmesg-warn -> PASS (fi-cfl-s) Test drv_module_reload: Subgroup basic-reload: dmesg-warn -> PASS (fi-cfl-s) Subgroup basic-reload-inject: incomplete -> PASS (fi-cfl-s) fdo#103022 fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514 fdo#103022 https://bugs.freedesktop.org/show_bug.cgi?id=103022 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:448s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:470s fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:392s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:563s fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:284s fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:525s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:523s fi-byt-j1900 total:289 pass:253 dwarn:1 dfail:0 fail:0 skip:35 time:536s fi-byt-n2820 total:289 pass:249 dwarn:1 dfail:0 fail:0 skip:39 time:519s fi-cfl-s total:289 pass:256 dwarn:1 dfail:0 fail:0 skip:32 time:561s fi-cnl-y total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:608s fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:426s fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:601s fi-hsw-4770 total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:434s fi-hsw-4770r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:417s fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:453s fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:502s fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:475s fi-kbl-7500u total:289 pass:263 dwarn:1 dfail:0 fail:1 skip:24 time:514s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:577s fi-kbl-7567u total:289 pass:265 dwarn:4 dfail:0 fail:0 skip:20 time:487s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:588s fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:0 skip:66 time:665s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:466s fi-skl-6700hqtotal:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:660s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:529s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:565s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:478s fi-snb-2520m total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:581s fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:426s 6a08510077ad5bdbac044038138f217e413cdca2 drm-tip: 2017y-10m-10d-07h-48m-31s UTC integration manifest ef503b2d26b9 drm/i915: Increase atomic update vblank evasion time with lockdep == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5965/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for IGT PMU support (rev7)
== Series Details == Series: IGT PMU support (rev7) URL : https://patchwork.freedesktop.org/series/28253/ State : failure == Summary == IGT patchset build failed on latest successful build d7c88290ab6a8393dc341b30c7fb5e27d2952901 syncobj: Add a test for SYNCOBJ_CREATE_SIGNALED make all-recursive Making all in lib make all-recursive Making all in . Making all in tests make[4]: Nothing to be done for 'all'. Making all in man make[2]: Nothing to be done for 'all'. Making all in tools Making all in null_state_gen make[3]: Nothing to be done for 'all'. Making all in registers make[3]: Nothing to be done for 'all'. make[3]: Nothing to be done for 'all-am'. Making all in scripts make[2]: Nothing to be done for 'all'. Making all in benchmarks Making all in wsim make[3]: Nothing to be done for 'all'. Making all in ezbench.d make[3]: Nothing to be done for 'all'. make[3]: Nothing to be done for 'all-am'. Making all in tests Making all in intel-ci make[3]: Nothing to be done for 'all'. make[3]: Nothing to be done for 'all-am'. Making all in assembler make all-recursive Making all in doc make[4]: Nothing to be done for 'all'. Making all in test make[4]: Nothing to be done for 'all'. make[4]: Nothing to be done for 'all-am'. Making all in overlay CCLD intel-gpu-overlay /usr/bin/ld: power.o: undefined reference to symbol 'llround@@GLIBC_2.2.5' //lib/x86_64-linux-gnu/libm.so.6: error adding symbols: DSO missing from command line collect2: error: ld returned 1 exit status Makefile:564: recipe for target 'intel-gpu-overlay' failed make[2]: *** [intel-gpu-overlay] Error 1 Makefile:533: recipe for target 'all-recursive' failed make[1]: *** [all-recursive] Error 1 Makefile:465: recipe for target 'all' failed make: *** [all] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Use rcu instead of stop_machine in set_wedged
Daniel Vetter writes:
> stop_machine is not really a locking primitive we should use, except
> when the hw folks tell us the hw is broken and that's the only way to
> work around it.
>
> This patch tries to address the locking abuse of stop_machine() from
>
> commit 20e4933c478a1ca694b38fa4ac44d99e659941f5
> Author: Chris Wilson
> Date: Tue Nov 22 14:41:21 2016 +
>
> drm/i915: Stop the machine as we install the wedged submit_request handler
>
> Chris said parts of the reasons for going with stop_machine() was that
> it's no overhead for the fast-path. But these callbacks use irqsave
> spinlocks and do a bunch of MMIO, and rcu_read_lock is _real_ fast.
>
> To stay as close as possible to the stop_machine semantics we first
> update all the submit function pointers to the nop handler, then call
> synchronize_rcu() to make sure no new requests can be submitted. This
> should give us exactly the huge barrier we want.
>
> I pondered whether we should annotate engine->submit_request as __rcu
> and use rcu_assign_pointer and rcu_dereference on it. But the reason
> behind those is to make sure the compiler/cpu barriers are there for
> when you have an actual data structure you point at, to make sure all
> the writes are seen correctly on the read side. But we just have a
> function pointer, and .text isn't changed, so no need for these
> barriers and hence no need for annotations.
>
> Unfortunately there's a complication with the call to
> intel_engine_init_global_seqno:
>
> - Without stop_machine we must hold the corresponding spinlock.
>
> - Without stop_machine we must ensure that all requests are marked as
> having failed with dma_fence_set_error() before we call it. That
> means we need to split the nop request submission into two phases,
> both synchronized with rcu:
>
> 1. Only stop submitting the requests to hw and mark them as failed.
>
> 2. After all pending requests in the scheduler/ring are suitably
> marked up as failed and we can force complete them all, also force
> complete by calling intel_engine_init_global_seqno().
>
> This should fix the followwing lockdep splat:
>
> ==
> WARNING: possible circular locking dependency detected
> 4.14.0-rc3-CI-CI_DRM_3179+ #1 Tainted: G U
> --
> kworker/3:4/562 is trying to acquire lock:
> (cpu_hotplug_lock.rw_sem){}, at: []
> stop_machine+0x1c/0x40
>
> but task is already holding lock:
> (&dev->struct_mutex){+.+.}, at: []
> i915_reset_device+0x1e8/0x260 [i915]
>
> which lock already depends on the new lock.
>
> the existing dependency chain (in reverse order) is:
>
> -> #6 (&dev->struct_mutex){+.+.}:
>__lock_acquire+0x1420/0x15e0
>lock_acquire+0xb0/0x200
>__mutex_lock+0x86/0x9b0
>mutex_lock_interruptible_nested+0x1b/0x20
>i915_mutex_lock_interruptible+0x51/0x130 [i915]
>i915_gem_fault+0x209/0x650 [i915]
>__do_fault+0x1e/0x80
>__handle_mm_fault+0xa08/0xed0
>handle_mm_fault+0x156/0x300
>__do_page_fault+0x2c5/0x570
>do_page_fault+0x28/0x250
>page_fault+0x22/0x30
>
> -> #5 (&mm->mmap_sem){}:
>__lock_acquire+0x1420/0x15e0
>lock_acquire+0xb0/0x200
>__might_fault+0x68/0x90
>_copy_to_user+0x23/0x70
>filldir+0xa5/0x120
>dcache_readdir+0xf9/0x170
>iterate_dir+0x69/0x1a0
>SyS_getdents+0xa5/0x140
>entry_SYSCALL_64_fastpath+0x1c/0xb1
>
> -> #4 (&sb->s_type->i_mutex_key#5){}:
>down_write+0x3b/0x70
>handle_create+0xcb/0x1e0
>devtmpfsd+0x139/0x180
>kthread+0x152/0x190
>ret_from_fork+0x27/0x40
>
> -> #3 ((complete)&req.done){+.+.}:
>__lock_acquire+0x1420/0x15e0
>lock_acquire+0xb0/0x200
>wait_for_common+0x58/0x210
>wait_for_completion+0x1d/0x20
>devtmpfs_create_node+0x13d/0x160
>device_add+0x5eb/0x620
>device_create_groups_vargs+0xe0/0xf0
>device_create+0x3a/0x40
>msr_device_create+0x2b/0x40
>cpuhp_invoke_callback+0xc9/0xbf0
>cpuhp_thread_fun+0x17b/0x240
>smpboot_thread_fn+0x18a/0x280
>kthread+0x152/0x190
>ret_from_fork+0x27/0x40
>
> -> #2 (cpuhp_state-up){+.+.}:
>__lock_acquire+0x1420/0x15e0
>lock_acquire+0xb0/0x200
>cpuhp_issue_call+0x133/0x1c0
>__cpuhp_setup_state_cpuslocked+0x139/0x2a0
>__cpuhp_setup_state+0x46/0x60
>page_writeback_init+0x43/0x67
>pagecache_init+0x3d/0x42
>start_kernel+0x3a8/0x3fc
>x86_64_start_reservations+0x2a/0x2c
>x86_64_start_kernel+0x6d/0x70
>verify_cpu+0x0/0xfb
>
> -> #1 (cpuhp_state_mutex){+.+.}:
>__lock_acquire+0x1420/0x15e0
>lock_acquire+0xb0/0x200
>__mutex_lock+0x86/0x9b0
>mutex_lock_nested+0x1b/0x20
>__cpuhp_setup_state_cpuslocked+0x53/0x2a0
>__cpuhp_s
[Intel-gfx] [PATCH v15 4/7] drm/i915/gvt: Add opregion support
Windows guest driver needs vbt in opregion, to configure the setting
for display. Without opregion support, the display registers won't
be set and this blocks display model to get the correct information
of the guest display plane.
This patch is to provide a virtual opregion for guest. Current
implementation is to fill the virtual opregion with the content in
host's opregion. The original author of this patch is Xiaoguang Chen.
Signed-off-by: Bing Niu
Signed-off-by: Tina Zhang
---
drivers/gpu/drm/i915/gvt/hypercall.h | 1 +
drivers/gpu/drm/i915/gvt/kvmgt.c | 109 ++-
drivers/gpu/drm/i915/gvt/mpt.h | 15 +
drivers/gpu/drm/i915/gvt/opregion.c | 26 +++--
drivers/gpu/drm/i915/gvt/vgpu.c | 4 ++
5 files changed, 146 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/hypercall.h
b/drivers/gpu/drm/i915/gvt/hypercall.h
index df7f33a..32c345c 100644
--- a/drivers/gpu/drm/i915/gvt/hypercall.h
+++ b/drivers/gpu/drm/i915/gvt/hypercall.h
@@ -55,6 +55,7 @@ struct intel_gvt_mpt {
unsigned long mfn, unsigned int nr, bool map);
int (*set_trap_area)(unsigned long handle, u64 start, u64 end,
bool map);
+ int (*set_opregion)(void *vgpu);
};
extern struct intel_gvt_mpt xengt_mpt;
diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index fd0c85f..6b0a330 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -53,11 +53,23 @@ static const struct intel_gvt_ops *intel_gvt_ops;
#define VFIO_PCI_INDEX_TO_OFFSET(index) ((u64)(index) << VFIO_PCI_OFFSET_SHIFT)
#define VFIO_PCI_OFFSET_MASK(((u64)(1) << VFIO_PCI_OFFSET_SHIFT) - 1)
+#define OPREGION_SIGNATURE "IntelGraphicsMem"
+
+struct vfio_region;
+struct intel_vgpu_regops {
+ size_t (*rw)(struct intel_vgpu *vgpu, char *buf,
+ size_t count, loff_t *ppos, bool iswrite);
+ void (*release)(struct intel_vgpu *vgpu,
+ struct vfio_region *region);
+};
+
struct vfio_region {
u32 type;
u32 subtype;
size_t size;
u32 flags;
+ const struct intel_vgpu_regops *ops;
+ void*data;
};
struct kvmgt_pgfn {
@@ -430,6 +442,91 @@ static void kvmgt_protect_table_del(struct
kvmgt_guest_info *info,
}
}
+static size_t intel_vgpu_reg_rw_opregion(struct intel_vgpu *vgpu, char *buf,
+ size_t count, loff_t *ppos, bool iswrite)
+{
+ unsigned int i = VFIO_PCI_OFFSET_TO_INDEX(*ppos) -
+ VFIO_PCI_NUM_REGIONS;
+ void *base = vgpu->vdev.region[i].data;
+ loff_t pos = *ppos & VFIO_PCI_OFFSET_MASK;
+
+ if (pos >= vgpu->vdev.region[i].size || iswrite) {
+ gvt_vgpu_err("invalid op or offset for Intel vgpu OpRegion\n");
+ return -EINVAL;
+ }
+ count = min(count, (size_t)(vgpu->vdev.region[i].size - pos));
+ memcpy(buf, base + pos, count);
+
+ return count;
+}
+
+static void intel_vgpu_reg_release_opregion(struct intel_vgpu *vgpu,
+ struct vfio_region *region)
+{
+ memunmap(region->data);
+}
+
+static const struct intel_vgpu_regops intel_vgpu_regops_opregion = {
+ .rw = intel_vgpu_reg_rw_opregion,
+ .release = intel_vgpu_reg_release_opregion,
+};
+
+static int intel_vgpu_register_reg(struct intel_vgpu *vgpu,
+ unsigned int type, unsigned int subtype,
+ const struct intel_vgpu_regops *ops,
+ size_t size, u32 flags, void *data)
+{
+ struct vfio_region *region;
+
+ region = krealloc(vgpu->vdev.region,
+ (vgpu->vdev.num_regions + 1) * sizeof(*region),
+ GFP_KERNEL);
+ if (!region)
+ return -ENOMEM;
+
+ vgpu->vdev.region = region;
+ vgpu->vdev.region[vgpu->vdev.num_regions].type = type;
+ vgpu->vdev.region[vgpu->vdev.num_regions].subtype = subtype;
+ vgpu->vdev.region[vgpu->vdev.num_regions].ops = ops;
+ vgpu->vdev.region[vgpu->vdev.num_regions].size = size;
+ vgpu->vdev.region[vgpu->vdev.num_regions].flags = flags;
+ vgpu->vdev.region[vgpu->vdev.num_regions].data = data;
+ vgpu->vdev.num_regions++;
+
+ return 0;
+}
+
+static int kvmgt_set_opregion(void *p_vgpu)
+{
+ struct intel_vgpu *vgpu = (struct intel_vgpu *)p_vgpu;
+ unsigned int addr;
+ void *base;
+ int ret;
+
+ addr = vgpu->gvt->opregion.opregion_pa;
+ if (!addr || !(~addr))
+ return -ENODEV;
+
+ base = memremap(addr, OPREGION_SIZE, MEMREMAP_WB);
+ if (!base)
+ return -ENOMEM;
+
+ if (memcmp(base, OPREGION_SIGNATURE, 16)) {
+ memunmap(base);
+ return -EINVAL;
+ }
+
+
[Intel-gfx] [PATCH v15 6/7] drm/i915: Introduce GEM proxy
GEM proxy is a kind of GEM, whose backing physical memory is pinned
and produced by guest VM and is used by host as read only. With GEM
proxy, host is able to access guest physical memory through GEM object
interface. As GEM proxy is such a special kind of GEM, a new flag
I915_GEM_OBJECT_IS_PROXY is introduced to ban host from changing the
backing storage of GEM proxy.
v14:
- return -ENXIO when gem proxy object is banned by ioctl.
(Chris) (Daniel)
v13:
- add comments to GEM proxy. (Chris)
- don't ban GEM proxy in i915_gem_sw_finish_ioctl. (Chris)
- check GEM proxy bar after finishing i915_gem_object_wait. (Chris)
- remove GEM proxy bar in i915_gem_madvise_ioctl.
v6:
- add gem proxy barrier in the following ioctls. (Chris)
i915_gem_set_caching_ioctl
i915_gem_set_domain_ioctl
i915_gem_sw_finish_ioctl
i915_gem_set_tiling_ioctl
i915_gem_madvise_ioctl
Signed-off-by: Tina Zhang
Cc: Daniel Vetter
Cc: Chris Wilson
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_gem.c| 24 +++-
drivers/gpu/drm/i915/i915_gem_object.h | 7 +++
drivers/gpu/drm/i915/i915_gem_tiling.c | 8
3 files changed, 38 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 000a764..7f1e7ab 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1584,6 +1584,16 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void
*data,
if (err)
goto out;
+ /* Proxy objects do not control access to the backing storage, ergo
+* they cannot be used as a means to manipulate the cache domain
+* tracking for that backing storage. The proxy object is always
+* considered to be outside of any cache domain.
+*/
+ if (i915_gem_object_is_proxy(obj)) {
+ err = -ENXIO;
+ goto out;
+ }
+
/* Flush and acquire obj->pages so that we are coherent through
* direct access in memory with previous cached writes through
* shmemfs and that our cache domain tracking remains valid.
@@ -1640,6 +1650,10 @@ i915_gem_sw_finish_ioctl(struct drm_device *dev, void
*data,
if (!obj)
return -ENOENT;
+ /* Proxy objects are barred from CPU access, so there is no
+* need to ban sw_finish as it is a nop.
+*/
+
/* Pinned buffers may be scanout, so flush the cache */
i915_gem_object_flush_if_display(obj);
i915_gem_object_put(obj);
@@ -1690,7 +1704,7 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
*/
if (!obj->base.filp) {
i915_gem_object_put(obj);
- return -EINVAL;
+ return -ENXIO;
}
addr = vm_mmap(obj->base.filp, 0, args->size,
@@ -3749,6 +3763,14 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev,
void *data,
if (!obj)
return -ENOENT;
+ /* The caching mode of proxy object is handled by its generator, and not
+* expected to be changed by user mode.
+*/
+ if (i915_gem_object_is_proxy(obj)) {
+ ret = -ENXIO;
+ goto out;
+ }
+
if (obj->cache_level == level)
goto out;
diff --git a/drivers/gpu/drm/i915/i915_gem_object.h
b/drivers/gpu/drm/i915/i915_gem_object.h
index 5b19a49..f3b382a 100644
--- a/drivers/gpu/drm/i915/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/i915_gem_object.h
@@ -39,6 +39,7 @@ struct drm_i915_gem_object_ops {
unsigned int flags;
#define I915_GEM_OBJECT_HAS_STRUCT_PAGE BIT(0)
#define I915_GEM_OBJECT_IS_SHRINKABLE BIT(1)
+#define I915_GEM_OBJECT_IS_PROXY BIT(2)
/* Interface between the GEM object and its backing storage.
* get_pages() is called once prior to the use of the associated set
@@ -300,6 +301,12 @@ i915_gem_object_is_shrinkable(const struct
drm_i915_gem_object *obj)
}
static inline bool
+i915_gem_object_is_proxy(const struct drm_i915_gem_object *obj)
+{
+ return obj->ops->flags & I915_GEM_OBJECT_IS_PROXY;
+}
+
+static inline bool
i915_gem_object_is_active(const struct drm_i915_gem_object *obj)
{
return obj->active_count;
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c
b/drivers/gpu/drm/i915/i915_gem_tiling.c
index fb5231f..f617012 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -345,6 +345,14 @@ i915_gem_set_tiling_ioctl(struct drm_device *dev, void
*data,
if (!obj)
return -ENOENT;
+ /* The tiling mode of proxy objects is handled by its generator, and not
+* expected to be changed by user mode.
+*/
+ if (i915_gem_object_is_proxy(obj)) {
+ err = -ENXIO;
+ goto err;
+ }
+
if (!i915_tiling_ok(obj, args->tiling_mode, args->stride)) {
err = -EINVAL;
goto err;
--
2.7.4
__
[Intel-gfx] [PATCH v15 3/7] drm/i915/gvt: Add RGB 64-bit 16:16:16:16 float format
The RGB 64-bit 16:16:16:16 float pixel format is needed by windows 10
guest VM. This patch is to add this pixel format support to gvt device
model. Without this patch, some Apps, e.g. "DXGIGammaVM.exe", will crash
and make guest screen black.
Signed-off-by: Tina Zhang
---
drivers/gpu/drm/i915/gvt/fb_decoder.c | 28 +---
1 file changed, 21 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c
b/drivers/gpu/drm/i915/gvt/fb_decoder.c
index d380ab8..49053f4 100644
--- a/drivers/gpu/drm/i915/gvt/fb_decoder.c
+++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
@@ -52,6 +52,8 @@ static struct pixel_format bdw_pixel_formats[] = {
{DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"},
{DRM_FORMAT_XBGR, 32, "32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"},
+ {DRM_FORMAT_XRGB161616F, 64,
+ "64-bit XRGB Floating Point (16:16:16:16 MSB-X:R:G:B)"},
/* non-supported format has bpp default to 0 */
{0, 0, NULL},
@@ -73,13 +75,18 @@ static struct pixel_format skl_pixel_formats[] = {
{DRM_FORMAT_XBGR2101010, 32, "32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"},
{DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"},
+ {DRM_FORMAT_XRGB161616F, 64,
+ "64-bit XRGB Floating Point (16:16:16:16 MSB-X:R:G:B)"},
+ {DRM_FORMAT_XBGR161616F, 64,
+ "64-bit XBGR Floating Point (16:16:16:16 MSB-X:B:G:R)"},
+
/* non-supported format has bpp default to 0 */
{0, 0, NULL},
};
static int bdw_format_to_drm(int format)
{
- int bdw_pixel_formats_index = 6;
+ int bdw_pixel_formats_index = 7;
switch (format) {
case DISPPLANE_8BPP:
@@ -100,7 +107,9 @@ static int bdw_format_to_drm(int format)
case DISPPLANE_RGBX888:
bdw_pixel_formats_index = 5;
break;
-
+ case DISPPLANE_RGBX161616:
+ bdw_pixel_formats_index = 6;
+ break;
default:
break;
}
@@ -111,7 +120,7 @@ static int bdw_format_to_drm(int format)
static int skl_format_to_drm(int format, bool rgb_order, bool alpha,
int yuv_order)
{
- int skl_pixel_formats_index = 12;
+ int skl_pixel_formats_index = 14;
switch (format) {
case PLANE_CTL_FORMAT_INDEXED:
@@ -129,6 +138,9 @@ static int skl_format_to_drm(int format, bool rgb_order,
bool alpha,
case PLANE_CTL_FORMAT_XRGB_2101010:
skl_pixel_formats_index = rgb_order ? 10 : 11;
break;
+ case PLANE_CTL_FORMAT_XRGB_16161616F:
+ skl_pixel_formats_index = rgb_order ? 12 : 13;
+ break;
case PLANE_CTL_FORMAT_YUV422:
skl_pixel_formats_index = yuv_order >> 16;
if (skl_pixel_formats_index > 3)
@@ -389,11 +401,13 @@ int intel_vgpu_decode_cursor_plane(struct intel_vgpu
*vgpu,
#define SPRITE_FORMAT_NUM (1 << 3)
static struct pixel_format sprite_pixel_formats[SPRITE_FORMAT_NUM] = {
- [0x0] = {DRM_FORMAT_YUV422, 16, "YUV 16-bit 4:2:2 packed"},
- [0x1] = {DRM_FORMAT_XRGB2101010, 32, "RGB 32-bit 2:10:10:10"},
- [0x2] = {DRM_FORMAT_XRGB, 32, "RGB 32-bit 8:8:8:8"},
+ [0x0] = {DRM_FORMAT_YUV422, 16, "16-bit YUV 4:2:2 packed"},
+ [0x1] = {DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10
MSB-X:R:G:B)"},
+ [0x2] = {DRM_FORMAT_XRGB, 32, "32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"},
+ [0x3] = {DRM_FORMAT_XRGB161616F, 64,
+ "64-bit XRGB Floating Point (16:16:16:16 MSB-X:R:G:B)"},
[0x4] = {DRM_FORMAT_AYUV, 32,
- "YUV 32-bit 4:4:4 packed (8:8:8:8 MSB-X:Y:U:V)"},
+ "32-bit YUV 4:4:4 packed (8:8:8:8 MSB-X:Y:U:V)"},
};
/**
--
2.7.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v15 2/7] drm: Introduce RGB 64-bit 16:16:16:16 float format
The RGB 64-bit 16:16:16:16 float pixel format is needed by some Apps in
windows. The float format in each component is 1:5:10 MSb-sign:exponent:
fraction.
This patch is to introduce the format to drm, so that the windows guest's
framebuffer in this kind of format can be recognized and used by linux
host.
v14:
- add some details about the float pixel format. (Daniel)
- add F suffix to the defined name. (Daniel)
v12:
- send to dri-devel at lists.freedesktop.org. (Ville)
v9:
- separated from framebuffer decoder patch. (Zhenyu) (Xiaoguang)
Signed-off-by: Tina Zhang
Cc: Ville Syrjälä
Cc: Dave Airlie
Cc: Daniel Vetter
---
include/uapi/drm/drm_fourcc.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 76c9101..575014f 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -113,6 +113,10 @@ extern "C" {
#define DRM_FORMAT_AYUVfourcc_code('A', 'Y', 'U', 'V') /*
[31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
+/* 64 bpp RGB 16:16:16:16 Floating Point */
+#define DRM_FORMAT_XRGB161616F fourcc_code('X', 'R', '3', 'F') /* [63:0]
x:R:G:B 16:16:16:16 little endian */
+#define DRM_FORMAT_XBGR161616F fourcc_code('X', 'B', '3', 'F') /* [63:0]
x:B:G:R 16:16:16:16 little endian */
+
/*
* 2 plane RGB + A
* index 0 = RGB plane, same format as the corresponding non _A8 format has
--
2.7.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v15 1/7] drm/i915/gvt: Add framebuffer decoder support
This patch is to introduce the framebuffer decoder which can decode guest
OS's framebuffer information, including primary, cursor and sprite plane.
v14:
- refine pixel format table. (Zhenyu)
v9:
- move drm format change to a separate patch. (Xiaoguang)
v8:
- fix a bug in decoding primary plane. (Tina)
v7:
- refine framebuffer decoder code. (Zhenyu)
Signed-off-by: Tina Zhang
Cc: Zhenyu Wang
---
drivers/gpu/drm/i915/gvt/Makefile | 3 +-
drivers/gpu/drm/i915/gvt/display.c| 2 +-
drivers/gpu/drm/i915/gvt/display.h| 2 +
drivers/gpu/drm/i915/gvt/fb_decoder.c | 507 ++
drivers/gpu/drm/i915/gvt/fb_decoder.h | 169
drivers/gpu/drm/i915/gvt/gvt.h| 1 +
6 files changed, 682 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gvt/fb_decoder.c
create mode 100644 drivers/gpu/drm/i915/gvt/fb_decoder.h
diff --git a/drivers/gpu/drm/i915/gvt/Makefile
b/drivers/gpu/drm/i915/gvt/Makefile
index f5486cb9..019d596 100644
--- a/drivers/gpu/drm/i915/gvt/Makefile
+++ b/drivers/gpu/drm/i915/gvt/Makefile
@@ -1,7 +1,8 @@
GVT_DIR := gvt
GVT_SOURCE := gvt.o aperture_gm.o handlers.o vgpu.o trace_points.o firmware.o \
interrupt.o gtt.o cfg_space.o opregion.o mmio.o display.o edid.o \
- execlist.o scheduler.o sched_policy.o render.o cmd_parser.o
+ execlist.o scheduler.o sched_policy.o render.o cmd_parser.o \
+ fb_decoder.o
ccflags-y += -I$(src) -I$(src)/$(GVT_DIR)
i915-y += $(addprefix $(GVT_DIR)/,
$(GVT_SOURCE))
diff --git a/drivers/gpu/drm/i915/gvt/display.c
b/drivers/gpu/drm/i915/gvt/display.c
index 3c31843..fb7fdba 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -67,7 +67,7 @@ static int edp_pipe_is_enabled(struct intel_vgpu *vgpu)
return 1;
}
-static int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
+int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
{
struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
diff --git a/drivers/gpu/drm/i915/gvt/display.h
b/drivers/gpu/drm/i915/gvt/display.h
index d73de22..b46b868 100644
--- a/drivers/gpu/drm/i915/gvt/display.h
+++ b/drivers/gpu/drm/i915/gvt/display.h
@@ -179,4 +179,6 @@ int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64
resolution);
void intel_vgpu_reset_display(struct intel_vgpu *vgpu);
void intel_vgpu_clean_display(struct intel_vgpu *vgpu);
+int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe);
+
#endif
diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c
b/drivers/gpu/drm/i915/gvt/fb_decoder.c
new file mode 100644
index 000..d380ab8
--- /dev/null
+++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
@@ -0,0 +1,507 @@
+/*
+ * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *Kevin Tian
+ *
+ * Contributors:
+ *Bing Niu
+ *Xu Han
+ *Ping Gao
+ *Xiaoguang Chen
+ *Yang Liu
+ *Tina Zhang
+ *
+ */
+
+#include
+#include "i915_drv.h"
+#include "gvt.h"
+
+#define PRIMARY_FORMAT_NUM 16
+struct pixel_format {
+ int drm_format; /* Pixel format in DRM definition */
+ int bpp;/* Bits per pixel, 0 indicates invalid */
+ char*desc; /* The description */
+};
+
+static struct pixel_format bdw_pixel_formats[] = {
+ {DRM_FORMAT_C8, 8, "8-bit Indexed"},
+ {DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"},
+ {DRM_FORMAT_XRGB, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"},
+ {DRM_FORMAT_XBGR2101010, 32, "32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"},
+
+ {DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"},
+ {DRM_FORMAT_XBGR, 32, "32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"},
+
+ /* non-supported format has bpp default to 0 */
+ {0, 0
[Intel-gfx] [PATCH v15 5/7] vfio: ABI for mdev display dma-buf operation
Add VFIO_DEVICE_QUERY_GFX_PLANE ioctl command to let user mode query and
get the plan and its related information. This ioctl can be invoked with:
1) either flag DMABUF or REGION is set. Vendor driver returns success and
the plane_info only when the specific kind of buffer is supported.
2) flag PROBE is set with either DMABUF or REGION. Vendor driver returns
success only when the specific kind of buffer is supported.
The dma-buf's life cycle is handled by user mode and tracked by kernel.
The returned fd in struct vfio_device_query_gfx_plane can be a new
fd or an old fd of a re-exported dma-buf. Host user mode can check the
value of fd and to see if it needs to create new resource according to
the new fd or just use the existed resource related to the old fd.
v15:
- add a ioctl to get a dmabuf for a given dmabuf id. (Gerd)
v14:
- add PROBE, DMABUF and REGION flags. (Alex)
v12:
- add drm_format_mod back. (Gerd and Zhenyu)
- add region_index. (Gerd)
v11:
- rename plane_type to drm_plane_type. (Gerd)
- move fields of vfio_device_query_gfx_plane to vfio_device_gfx_plane_info.
(Gerd)
- remove drm_format_mod, start fields. (Daniel)
- remove plane_id.
v10:
- refine the ABI API VFIO_DEVICE_QUERY_GFX_PLANE. (Alex) (Gerd)
v3:
- add a field gvt_plane_info in the drm_i915_gem_obj structure to save
the decoded plane information to avoid look up while need the plane
info. (Gerd)
Signed-off-by: Tina Zhang
Cc: Gerd Hoffmann
Cc: Alex Williamson
Cc: Daniel Vetter
---
include/uapi/linux/vfio.h | 62 +++
1 file changed, 62 insertions(+)
diff --git a/include/uapi/linux/vfio.h b/include/uapi/linux/vfio.h
index ae46105..fdf9a9c 100644
--- a/include/uapi/linux/vfio.h
+++ b/include/uapi/linux/vfio.h
@@ -502,6 +502,68 @@ struct vfio_pci_hot_reset {
#define VFIO_DEVICE_PCI_HOT_RESET _IO(VFIO_TYPE, VFIO_BASE + 13)
+/**
+ * VFIO_DEVICE_QUERY_GFX_PLANE - _IOW(VFIO_TYPE, VFIO_BASE + 14,
+ *struct vfio_device_query_gfx_plane)
+ *
+ * Set the drm_plane_type and flags, then retrieve the gfx plane info.
+ *
+ * flags supported:
+ * - VFIO_GFX_PLANE_TYPE_PROBE and VFIO_GFX_PLANE_TYPE_DMABUF are set
+ * to ask if the mdev supports dma-buf. 0 on support, -EINVAL on no
+ * support for dma-buf.
+ * - VFIO_GFX_PLANE_TYPE_PROBE and VFIO_GFX_PLANE_TYPE_REGION are set
+ * to ask if the mdev supports region. 0 on support, -EINVAL on no
+ * support for region.
+ * - VFIO_GFX_PLANE_TYPE_DMABUF or VFIO_GFX_PLANE_TYPE_REGION is set
+ * with each call to query the plane info.
+ * - Others are invalid and return -EINVAL.
+ *
+ * Return: 0 on success, -ENODEV with all out fields zero on mdev
+ * device initialization, -errno on other failure.
+ */
+struct vfio_device_gfx_plane_info {
+ __u32 argsz;
+ __u32 flags;
+#define VFIO_GFX_PLANE_TYPE_PROBE (1 << 0)
+#define VFIO_GFX_PLANE_TYPE_DMABUF (1 << 1)
+#define VFIO_GFX_PLANE_TYPE_REGION (1 << 2)
+ /* in */
+ __u32 drm_plane_type; /* type of plane: DRM_PLANE_TYPE_* */
+ /* out */
+ __u32 drm_format; /* drm format of plane */
+ __u64 drm_format_mod; /* tiled mode */
+ __u32 width;/* width of plane */
+ __u32 height; /* height of plane */
+ __u32 stride; /* stride of plane */
+ __u32 size; /* size of plane in bytes, align on page*/
+ __u32 x_pos;/* horizontal position of cursor plane */
+ __u32 y_pos;/* vertical position of cursor plane*/
+ union {
+ __u32 region_index; /* region index */
+ __s32 dmabuf_id;/* dma-buf fd */
+ };
+};
+
+#define VFIO_DEVICE_QUERY_GFX_PLANE _IO(VFIO_TYPE, VFIO_BASE + 14)
+
+/**
+ * VFIO_DEVICE_GET_GFX_DMABUF - _IOW(VFIO_TYPE, VFIO_BASE + 15,
+ * struct vfio_device_gfx_dmabuf_fd)
+ *
+ * Return: 0 on success, -errno on failure.
+ */
+struct vfio_device_gfx_dmabuf_fd {
+ __u32 argsz;
+ __u32 flags;
+ /* in */
+ __u32 dmabuf_id;
+ /* out */
+ __s32 dmabuf_fd;
+};
+
+#define VFIO_DEVICE_GET_GFX_DMABUF _IO(VFIO_TYPE, VFIO_BASE + 15)
+
/* API for Type1 VFIO IOMMU */
/**
--
2.7.4
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[Intel-gfx] [PATCH v15 0/7] drm/i915/gvt: Dma-buf support for GVT-g
v14->15: 1) Add VFIO_DEVICE_GET_GFX_DMABUF ABI. (Gerd) 2) Add intel_vgpu_dmabuf_cleanup() to clean up the vGPU's dmabuf. (Gerd) v13->v14: 1) add PROBE, DMABUF and REGION flags. (Alex) 2) return -ENXIO when gem proxy object is banned by ioctl. (Chris) (Daniel) 3) add some details about the float pixel format. (Daniel) 4) add F suffix to the defined name. (Daniel) 5) refine pixel format table. (Zhenyu) v12->v13: 1) add comments to GEM proxy. (Chris) 2) don't ban GEM proxy in i915_gem_sw_finish_ioctl. (Chris) 3) check GEM proxy bar after finishing i915_gem_object_wait. (Chris) 4) remove GEM proxy bar in i915_gem_madvise_ioctl. v11->v12: 1) add drm_format_mod back. (Gerd and Zhenyu) 2) add region_index. (Gerd) 3) refine the lifecycle of dmabuf. 4) send to dri-devel at lists.freedesktop.org. (Ville) v10->v11: 1) rename plane_type to drm_plane_type. (Gerd) 2) move fields of vfio_device_query_gfx_plane to vfio_device_gfx_plane_info. (Gerd) 3) remove drm_format_mod, start fields. (Daniel) 4) remove plane_id. v9->v10: 1) remove dma-buf management 2) refine the ABI API VFIO_DEVICE_QUERY_GFX_PLANE 3) track the dma-buf create and release in kernel mode v8->v9: 1) refine the dma-buf ioctl definition 2) add a lock to protect the dmabuf list 3) move drm format change to a separate patch 4) codes cleanup v7->v8: 1) refine framebuffer decoder code 2) fix a bug in decoding primary plane v6->v7: 1) release dma-buf related allocations in dma-buf's associated release function. 2) refine ioctl interface for querying plane info or create dma-buf 3) refine framebuffer decoder code 4) the patch series is based on 4.12.0-rc1 v5->v6: 1) align the dma-buf life cycle with the vfio device. 2) add the dma-buf related operations in a separate patch. 3) i915 releated changes. v4->v5: 1) fix bug while checking whether the gem obj is gvt's dma-buf when user change caching mode or domains. Add a helper function to do it. 2) add definition for the query plane and create dma-buf. v3->v4: 1) fix bug while checking whether the gem obj is gvt's dma-buf when set caching mode or doamins. v2->v3: 1) add a field gvt_plane_info in the drm_i915_gem_obj structure to save the decoded plane information to avoid look up while need the plane info. 2) declare a new flag I915_GEM_OBJECT_IS_GVT_DMABUF in drm_i915_gem_object to represent the gem obj for gvt's dma-buf. The tiling mode, caching mode and domains can not be changed for this kind of gem object. 3) change dma-buf related information to be more generic. So other vendor can use the same interface. v1->v2: 1) create a management fd for dma-buf operations. 2) alloc gem object's backing storage in gem obj's get_pages() callback. This patch set adds the dma-buf support for intel GVT-g. dma-buf is an uniform mechanism to share DMA buffers across different devices and subsystems. dma-buf for intel GVT-g is mainly used to share the vgpu's framebuffer to userspace to leverage userspace graphics stacks to render the framebuffer to the display monitor. The main idea is that we create a gem object and set vgpu's framebuffer as its backing storage. Then, export a dma-buf associated with this gem object. With the fd of this dma-buf, userspace can directly handle this buffer. This patch set can be tried with the following example: git://git.kraxel.org/qemu branch: work/intel-vgpu Tina Zhang (7): drm/i915/gvt: Add framebuffer decoder support drm: Introduce RGB 64-bit 16:16:16:16 float format drm/i915/gvt: Add RGB 64-bit 16:16:16:16 float format drm/i915/gvt: Add opregion support vfio: ABI for mdev display dma-buf operation drm/i915: Introduce GEM proxy drm/i915/gvt: Dmabuf support for GVT-g drivers/gpu/drm/i915/gvt/Makefile | 3 +- drivers/gpu/drm/i915/gvt/display.c | 2 +- drivers/gpu/drm/i915/gvt/display.h | 2 + drivers/gpu/drm/i915/gvt/dmabuf.c | 513 drivers/gpu/drm/i915/gvt/dmabuf.h | 65 drivers/gpu/drm/i915/gvt/fb_decoder.c | 521 + drivers/gpu/drm/i915/gvt/fb_decoder.h | 169 +++ drivers/gpu/drm/i915/gvt/gvt.c | 2 + drivers/gpu/drm/i915/gvt/gvt.h | 12 + drivers/gpu/drm/i915/gvt/hypercall.h | 3 + drivers/gpu/drm/i915/gvt/kvmgt.c | 169 ++- drivers/gpu/drm/i915/gvt/mpt.h | 45 +++ drivers/gpu/drm/i915/gvt/opregion.c| 26 +- drivers/gpu/drm/i915/gvt/vgpu.c| 9 +- drivers/gpu/drm/i915/i915_gem.c| 24 +- drivers/gpu/drm/i915/i915_gem_object.h | 9 + drivers/gpu/drm/i915/i915_gem_tiling.c | 8 + include/uapi/drm/drm_fourcc.h | 4 + include/uapi/linux/vfio.h | 62 19 files changed, 1635 insertions(+), 13 deletions(-) create mode 100644 drivers/gpu/drm/i915/gvt/dmabuf.c create mode 100644 drivers/gpu/drm/i915/gvt/dmabuf.h create mode 100644 drivers/gpu/drm/i915/gvt/fb_decoder.c create mode 100644 drivers/gpu/drm/i915/gvt/fb_decod
[Intel-gfx] [PATCH v15 7/7] drm/i915/gvt: Dmabuf support for GVT-g
This patch introduces a guest's framebuffer sharing mechanism based on
dma-buf subsystem. With this sharing mechanism, guest's framebuffer can
be shared between guest VM and host.
v15:
- Add VFIO_DEVICE_GET_GFX_DMABUF ABI. (Gerd)
- Add intel_vgpu_dmabuf_cleanup() to clean up the vGPU's dmabuf. (Gerd)
v14:
- add PROBE, DMABUF and REGION flags. (Alex)
v12:
- refine the lifecycle of dmabuf.
v9:
- remove dma-buf management. (Alex)
- track the dma-buf create and release in kernel mode. (Gerd) (Daniel)
v8:
- refine the dma-buf ioctl definition.(Alex)
- add a lock to protect the dmabuf list. (Alex)
v7:
- release dma-buf related allocations in dma-buf's associated release
function. (Alex)
- refine ioctl interface for querying plane info or create dma-buf.
(Alex)
v6:
- align the dma-buf life cycle with the vfio device. (Alex)
- add the dma-buf related operations in a separate patch. (Gerd)
- i915 related changes. (Chris)
v5:
- fix bug while checking whether the gem obj is gvt's dma-buf when user
change caching mode or domains. Add a helper function to do it.
(Xiaoguang)
- add definition for the query plane and create dma-buf. (Xiaoguang)
v4:
- fix bug while checking whether the gem obj is gvt's dma-buf when set
caching mode or doamins. (Xiaoguang)
v3:
- declare a new flag I915_GEM_OBJECT_IS_GVT_DMABUF in drm_i915_gem_object
to represent the gem obj for gvt's dma-buf. The tiling mode, caching
mode and domains can not be changed for this kind of gem object. (Alex)
- change dma-buf related information to be more generic. So other vendor
can use the same interface. (Alex)
v2:
- create a management fd for dma-buf operations. (Alex)
- alloc gem object's backing storage in gem obj's get_pages() callback.
(Chris)
Signed-off-by: Tina Zhang
Cc: Alex Williamson
Cc: Chris Wilson
Cc: Daniel Vetter
Cc: Gerd Hoffmann
---
drivers/gpu/drm/i915/gvt/Makefile | 2 +-
drivers/gpu/drm/i915/gvt/dmabuf.c | 513 +
drivers/gpu/drm/i915/gvt/dmabuf.h | 65 +
drivers/gpu/drm/i915/gvt/gvt.c | 2 +
drivers/gpu/drm/i915/gvt/gvt.h | 11 +
drivers/gpu/drm/i915/gvt/hypercall.h | 2 +
drivers/gpu/drm/i915/gvt/kvmgt.c | 60
drivers/gpu/drm/i915/gvt/mpt.h | 30 ++
drivers/gpu/drm/i915/gvt/vgpu.c| 5 +-
drivers/gpu/drm/i915/i915_gem_object.h | 2 +
10 files changed, 690 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gvt/dmabuf.c
create mode 100644 drivers/gpu/drm/i915/gvt/dmabuf.h
diff --git a/drivers/gpu/drm/i915/gvt/Makefile
b/drivers/gpu/drm/i915/gvt/Makefile
index 019d596..18f43cb 100644
--- a/drivers/gpu/drm/i915/gvt/Makefile
+++ b/drivers/gpu/drm/i915/gvt/Makefile
@@ -2,7 +2,7 @@ GVT_DIR := gvt
GVT_SOURCE := gvt.o aperture_gm.o handlers.o vgpu.o trace_points.o firmware.o \
interrupt.o gtt.o cfg_space.o opregion.o mmio.o display.o edid.o \
execlist.o scheduler.o sched_policy.o render.o cmd_parser.o \
- fb_decoder.o
+ fb_decoder.o dmabuf.o
ccflags-y += -I$(src) -I$(src)/$(GVT_DIR)
i915-y += $(addprefix $(GVT_DIR)/,
$(GVT_SOURCE))
diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.c
b/drivers/gpu/drm/i915/gvt/dmabuf.c
new file mode 100644
index 000..e97b3c7
--- /dev/null
+++ b/drivers/gpu/drm/i915/gvt/dmabuf.c
@@ -0,0 +1,513 @@
+/*
+ * Copyright 2017 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *Zhiyuan Lv
+ *
+ * Contributors:
+ *Xiaoguang Chen
+ *Tina Zhang
+ */
+
+#include
+#include
+#include
+
+#include "i915_drv.h"
+#include "gvt.h"
+
+#define GEN8_DECODE_PTE(pte) (pte & GENMASK_ULL(63, 12))
+
+static struct sg_table *vgpu_gem_get_pages(
+ struct drm_i915_gem_object *obj)
+{
+ struct drm_i915_private *dev_priv = to_i915(obj->b
Re: [Intel-gfx] [PATCH 0/5] drm/i915: Miscellaneous fixes to reduce dependency for I915_MAX_PIPES
On Tue, 2017-10-10 at 02:20 -0700, Kenneth Graunke wrote: > On Thursday, September 14, 2017 12:53:01 AM PDT Mika Kahola wrote: > > > > This patch series introduces fixes to reduce dependency for > > I915_MAX_PIPES and minor optimizations to reduce hardcoding. > > > > Kahola, Mika (1): > > drm/i915: Remove I915_MAX_PIPES dependency for DDB allocation > > > > Mika Kahola (4): > Looks like you've got two email addresses going on here. True. That's a legacy I will fix. Thanks for the review! > > > > > drm/i915: Don't relay on I915_MAX_PIPES > > drm/i915: Fold IRQ pipe masks > > drm/i915: Favor for_each_pipe() macro > > drm/i915: Cleanup South Error Interrupts > > > > drivers/gpu/drm/i915/i915_irq.c | 19 +++ > > drivers/gpu/drm/i915/i915_reg.h | 3 --- > > drivers/gpu/drm/i915/intel_audio.c| 2 +- > > drivers/gpu/drm/i915/intel_display.c | 5 - > > drivers/gpu/drm/i915/intel_drv.h | 3 ++- > > drivers/gpu/drm/i915/intel_pipe_crc.c | 9 + > > drivers/gpu/drm/i915/intel_pm.c | 6 -- > > 7 files changed, 23 insertions(+), 24 deletions(-) > Series is: > Reviewed-by: Kenneth Graunke -- Mika Kahola - Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 1/3] drm: Add retries for lspcon mode detection
From the CI builds, its been observed that during a driver
reload/insert, dp dual mode read function sometimes fails to
read from LSPCON device over i2c-over-aux channel.
This patch:
- adds some delay and few retries, allowing a scope for these
devices to settle down and respond.
- changes one error log's level from ERROR->DEBUG as we want
to call it an error only after all the retries are exhausted.
V2: Addressed review comments from Jani (for loop for retry)
V3: Addressed review comments from Imre (break on partial read too)
V3: Addressed review comments from Ville/Imre (Add the retries
exclusively for LSPCON, not for all dp_dual_mode devices)
Cc: Ville Syrjala
Cc: Imre Deak
Cc: Jani Nikula
Signed-off-by: Shashank Sharma
---
drivers/gpu/drm/drm_dp_dual_mode_helper.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_dual_mode_helper.c
b/drivers/gpu/drm/drm_dp_dual_mode_helper.c
index 0ef9011..02a5092 100644
--- a/drivers/gpu/drm/drm_dp_dual_mode_helper.c
+++ b/drivers/gpu/drm/drm_dp_dual_mode_helper.c
@@ -410,6 +410,7 @@ int drm_lspcon_get_mode(struct i2c_adapter *adapter,
{
u8 data;
int ret = 0;
+ int retry;
if (!mode) {
DRM_ERROR("NULL input\n");
@@ -417,10 +418,19 @@ int drm_lspcon_get_mode(struct i2c_adapter *adapter,
}
/* Read Status: i2c over aux */
- ret = drm_dp_dual_mode_read(adapter, DP_DUAL_MODE_LSPCON_CURRENT_MODE,
- &data, sizeof(data));
+ for (retry = 0; retry < 6; retry++) {
+ if (retry)
+ usleep_range(500, 1000);
+
+ ret = drm_dp_dual_mode_read(adapter,
+ DP_DUAL_MODE_LSPCON_CURRENT_MODE,
+ &data, sizeof(data));
+ if (!ret)
+ break;
+ }
+
if (ret < 0) {
- DRM_ERROR("LSPCON read(0x80, 0x41) failed\n");
+ DRM_DEBUG_KMS("LSPCON read(0x80, 0x41) failed\n");
return -EFAULT;
}
--
2.7.4
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[Intel-gfx] [PATCH v3 2/3] drm/i915: Don't give up waiting on INVALID_MODE
Our current logic to read LSPCON's current mode, stops retries and
breaks wait-loop, if it gets LSPCON_MODE_INVALID as return from the
core function. This doesn't allow us to try reading the mode again.
This patch removes this condition and allows retries reading
the currnt mode until timeout.
This also fixes/prevents some of the noise in form of debug messages
while running IGT CI test cases.
V2: rebase, added r-b
V2: changed some debug message levels from debug->error and
error->debug in lspcon_get_current_mode function.
V3: Rebase
Cc: Imre Deak
Cc: Daniel Vetter
Reviewed-by: Imre Deak
Signed-off-by: Shashank Sharma
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/intel_lspcon.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lspcon.c
b/drivers/gpu/drm/i915/intel_lspcon.c
index beb9baa..7688254 100644
--- a/drivers/gpu/drm/i915/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/intel_lspcon.c
@@ -56,7 +56,7 @@ static enum drm_lspcon_mode lspcon_get_current_mode(struct
intel_lspcon *lspcon)
struct i2c_adapter *adapter = &lspcon_to_intel_dp(lspcon)->aux.ddc;
if (drm_lspcon_get_mode(adapter, ¤t_mode)) {
- DRM_ERROR("Error reading LSPCON mode\n");
+ DRM_DEBUG_KMS("Error reading LSPCON mode\n");
return DRM_LSPCON_MODE_INVALID;
}
return current_mode;
@@ -68,16 +68,15 @@ static enum drm_lspcon_mode lspcon_wait_mode(struct
intel_lspcon *lspcon,
enum drm_lspcon_mode current_mode;
current_mode = lspcon_get_current_mode(lspcon);
- if (current_mode == mode || current_mode == DRM_LSPCON_MODE_INVALID)
+ if (current_mode == mode)
goto out;
DRM_DEBUG_KMS("Waiting for LSPCON mode %s to settle\n",
lspcon_mode_name(mode));
- wait_for((current_mode = lspcon_get_current_mode(lspcon)) == mode ||
-current_mode == DRM_LSPCON_MODE_INVALID, 100);
+ wait_for((current_mode = lspcon_get_current_mode(lspcon)) == mode, 100);
if (current_mode != mode)
- DRM_DEBUG_KMS("LSPCON mode hasn't settled\n");
+ DRM_ERROR("LSPCON mode hasn't settled\n");
out:
DRM_DEBUG_KMS("Current LSPCON mode %s\n",
--
2.7.4
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[Intel-gfx] [PATCH v3 0/3] Various retries for LSPCON
This patch series adds various retries and delays in DRM and I915 layer, to handle some of the read failures while dealing with LSPCON devices. LSPCON devices are sometimes slow to respond and the vendores expect us to retry while probing the device. The typical scenarios are getting fixed / handled with this patch series are look like this failure during LSPCON suspend/resume: [drm:drm_lspcon_get_mode] *ERROR* LSPCON read(0x80, 0x41) failed [drm:lspcon_wait_mode [i915]] *ERROR* Error reading LSPCON mode [drm:drm_lspcon_get_mode] *ERROR* LSPCON read(0x80, 0x41) failed [drm:lspcon_change_mode.constprop.4 [i915]] *ERROR* Error reading LSPCON mode [drm:lspcon_resume [i915]] *ERROR* LSPCON resume failed Setting dangerous option reset - tainting kernel Shashank Sharma (3): drm: Add retries for lspcon mode detection drm/i915: Don't give up waiting on INVALID_MODE drm/i915: Add retries for LSPCON detection drivers/gpu/drm/drm_dp_dual_mode_helper.c | 16 +--- drivers/gpu/drm/i915/intel_lspcon.c | 22 +++--- 2 files changed, 28 insertions(+), 10 deletions(-) -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 3/3] drm/i915: Add retries for LSPCON detection
We read the dp dual mode Adapter identifier to detect the
LSPCON device. It's been observed from the CI testing that in
few cases, this read can get delayed or fail. For such scenarios,
LSPCON vendors suggest to retry the read operation.
This patch adds retry in the probe function, while reading
LSPCON identifier.
V3: added this patch in the series
Cc: Ville Syrjala
Cc: Imre Deak
Signed-off-by: Shashank Sharma
---
drivers/gpu/drm/i915/intel_lspcon.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lspcon.c
b/drivers/gpu/drm/i915/intel_lspcon.c
index 7688254..dcbc786 100644
--- a/drivers/gpu/drm/i915/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/intel_lspcon.c
@@ -132,6 +132,7 @@ static bool lspcon_wake_native_aux_ch(struct intel_lspcon
*lspcon)
static bool lspcon_probe(struct intel_lspcon *lspcon)
{
+ int retry;
enum drm_dp_dual_mode_type adaptor_type;
struct i2c_adapter *adapter = &lspcon_to_intel_dp(lspcon)->aux.ddc;
enum drm_lspcon_mode expected_mode;
@@ -140,10 +141,18 @@ static bool lspcon_probe(struct intel_lspcon *lspcon)
DRM_LSPCON_MODE_PCON : DRM_LSPCON_MODE_LS;
/* Lets probe the adaptor and check its type */
- adaptor_type = drm_dp_dual_mode_detect(adapter);
+ for (retry = 0; retry < 6; retry++) {
+ if (retry)
+ usleep_range(500, 1000);
+
+ adaptor_type = drm_dp_dual_mode_detect(adapter);
+ if (adaptor_type == DRM_DP_DUAL_MODE_LSPCON)
+ break;
+ }
+
if (adaptor_type != DRM_DP_DUAL_MODE_LSPCON) {
DRM_DEBUG_KMS("No LSPCON detected, found %s\n",
- drm_dp_get_dual_mode_type_name(adaptor_type));
+ drm_dp_get_dual_mode_type_name(adaptor_type));
return false;
}
--
2.7.4
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gvt: Dma-buf support for GVT-g
== Series Details == Series: drm/i915/gvt: Dma-buf support for GVT-g URL : https://patchwork.freedesktop.org/series/31638/ State : failure == Summary == CHK include/config/kernel.release CHK include/generated/uapi/linux/version.h CHK include/generated/utsrelease.h CHK include/generated/bounds.h CHK include/generated/timeconst.h CHK include/generated/asm-offsets.h CALLscripts/checksyscalls.sh CHK scripts/mod/devicetable-offsets.h CHK include/generated/compile.h CHK kernel/config_data.h CC [M] drivers/gpu/drm/i915/gvt/dmabuf.o drivers/gpu/drm/i915/gvt/dmabuf.c:132:15: error: initialization from incompatible pointer type [-Werror=incompatible-pointer-types] .get_pages = vgpu_gem_get_pages, ^~ drivers/gpu/drm/i915/gvt/dmabuf.c:132:15: note: (near initialization for ‘intel_vgpu_gem_ops.get_pages’) cc1: all warnings being treated as errors scripts/Makefile.build:313: recipe for target 'drivers/gpu/drm/i915/gvt/dmabuf.o' failed make[4]: *** [drivers/gpu/drm/i915/gvt/dmabuf.o] Error 1 scripts/Makefile.build:572: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:572: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:572: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1019: recipe for target 'drivers' failed make: *** [drivers] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Increase atomic update vblank evasion time with lockdep
== Series Details == Series: drm/i915: Increase atomic update vblank evasion time with lockdep URL : https://patchwork.freedesktop.org/series/31630/ State : success == Summary == shard-hswtotal:2552 pass:1412 dwarn:24 dfail:0 fail:13 skip:1103 time:9576s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5964/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC PATCH 01/11] drm/i915: No need for RING_MAX_NONPRIV_SLOTS space
Oscar Mateo writes:
> Now that we write RING_FORCE_TO_NONPRIV registers directly to hardware,
> there is no need to save space for them in the list of context workarounds.
>
> Signed-off-by: Oscar Mateo
> Cc: Chris Wilson
> Cc: Mika Kuoppala
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_drv.h | 8 +---
> 1 file changed, 1 insertion(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 799a90a..47a357c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1954,13 +1954,7 @@ struct i915_wa_reg {
> u32 mask;
> };
>
> -/*
> - * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
> - * allowing it for RCS as we don't foresee any requirement of having
> - * a whitelist for other engines. When it is really required for
> - * other engines then the limit need to be increased.
> - */
> -#define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
> +#define I915_MAX_WA_REGS 16
>
> struct i915_workarounds {
> struct i915_wa_reg reg[I915_MAX_WA_REGS];
> --
> 1.9.1
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Re: [Intel-gfx] [PATCH v3 0/3] Various retries for LSPCON
Hi, > -Original Message- > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf > Of Shashank Sharma > Sent: tiistai 10. lokakuuta 2017 13.08 > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH v3 0/3] Various retries for LSPCON > > This patch series adds various retries and delays in DRM and I915 layer, to > handle some of the read failures while dealing with LSPCON devices. Should we have reference to fdo bugs? https://bugs.freedesktop.org/show_bug.cgi?id=102294 https://bugs.freedesktop.org/show_bug.cgi?id=102295 and what about this? https://bugs.freedesktop.org/show_bug.cgi?id=102359 > > LSPCON devices are sometimes slow to respond and the vendores expect us > to retry while probing the device. > > The typical scenarios are getting fixed / handled with this patch series are > look like this failure during LSPCON > suspend/resume: > [drm:drm_lspcon_get_mode] *ERROR* LSPCON read(0x80, 0x41) failed > [drm:lspcon_wait_mode [i915]] *ERROR* Error reading LSPCON mode > [drm:drm_lspcon_get_mode] *ERROR* LSPCON read(0x80, 0x41) failed > [drm:lspcon_change_mode.constprop.4 [i915]] *ERROR* Error reading > LSPCON mode [drm:lspcon_resume [i915]] *ERROR* LSPCON resume failed > Setting dangerous option reset - tainting kernel > > Shashank Sharma (3): > drm: Add retries for lspcon mode detection > drm/i915: Don't give up waiting on INVALID_MODE > drm/i915: Add retries for LSPCON detection > > drivers/gpu/drm/drm_dp_dual_mode_helper.c | 16 +--- > drivers/gpu/drm/i915/intel_lspcon.c | 22 +++--- > 2 files changed, 28 insertions(+), 10 deletions(-) > > -- > 2.7.4 Jani Saarinen Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH FOR CI 0/5] drm/i915: Miscellaneous fixes to reduce dependency for I915_MAX_PIPES
This patch series introduces fixes to reduce dependency for I915_MAX_PIPES and minor optimizations to reduce hardcoding. Mika Kahola (5): drm/i915: Don't relay on I915_MAX_PIPES drm/i915: Remove I915_MAX_PIPES dependency for DDB allocation drm/i915: Fold IRQ pipe masks drm/i915: Favor for_each_pipe() macro drm/i915: Cleanup South Error Interrupts drivers/gpu/drm/i915/i915_irq.c | 19 +++ drivers/gpu/drm/i915/i915_reg.h | 3 --- drivers/gpu/drm/i915/intel_audio.c| 2 +- drivers/gpu/drm/i915/intel_display.c | 5 - drivers/gpu/drm/i915/intel_drv.h | 3 ++- drivers/gpu/drm/i915/intel_pipe_crc.c | 15 --- drivers/gpu/drm/i915/intel_pm.c | 12 +++- 7 files changed, 29 insertions(+), 30 deletions(-) -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH FOR CI 1/5] drm/i915: Don't relay on I915_MAX_PIPES
Let's remove the dependency on I915_MAX_PIPES. Instead, get the number
of pipes from platform information.
Reviewed-by: Ville Syrjälä
Signed-off-by: Ramalingam C
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/intel_audio.c| 2 +-
drivers/gpu/drm/i915/intel_pipe_crc.c | 7 ---
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_audio.c
b/drivers/gpu/drm/i915/intel_audio.c
index 27743be..0ddba16 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -754,7 +754,7 @@ static struct intel_encoder *get_saved_enc(struct
drm_i915_private *dev_priv,
{
struct intel_encoder *encoder;
- if (WARN_ON(pipe >= I915_MAX_PIPES))
+ if (WARN_ON(pipe >= INTEL_INFO(dev_priv)->num_pipes))
return NULL;
/* MST */
diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c
b/drivers/gpu/drm/i915/intel_pipe_crc.c
index 96043a5..24d781f 100644
--- a/drivers/gpu/drm/i915/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
@@ -775,11 +775,12 @@ display_crc_ctl_parse_object(const char *buf, enum
intel_pipe_crc_object *o)
return -EINVAL;
}
-static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
+static int display_crc_ctl_parse_pipe(struct drm_i915_private *dev_priv,
+ const char *buf, enum pipe *pipe)
{
const char name = buf[0];
- if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
+ if (name < 'A' || name >= pipe_name(INTEL_INFO(dev_priv)->num_pipes))
return -EINVAL;
*pipe = name - 'A';
@@ -828,7 +829,7 @@ static int display_crc_ctl_parse(struct drm_i915_private
*dev_priv,
return -EINVAL;
}
- if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
+ if (display_crc_ctl_parse_pipe(dev_priv, words[1], &pipe) < 0) {
DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
return -EINVAL;
}
--
2.7.4
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[Intel-gfx] [PATCH FOR CI 5/5] drm/i915: Cleanup South Error Interrupts
Cleanup and parametrize the handling of South Error Interrupts (SERR_INT).
Reviewed-by: Ville Syrjälä
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/i915_irq.c | 12
drivers/gpu/drm/i915/i915_reg.h | 3 ---
2 files changed, 4 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index a38ad60..3736290 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2252,18 +2252,14 @@ static void ivb_err_int_handler(struct drm_i915_private
*dev_priv)
static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
{
u32 serr_int = I915_READ(SERR_INT);
+ enum pipe pipe;
if (serr_int & SERR_INT_POISON)
DRM_ERROR("PCH poison interrupt\n");
- if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
- intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A);
-
- if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
- intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B);
-
- if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
- intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_C);
+ for_each_pipe(dev_priv, pipe)
+ if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe))
+ intel_pch_fifo_underrun_irq_handler(dev_priv, pipe);
I915_WRITE(SERR_INT, serr_int);
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 50e65c9..7483992 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7183,9 +7183,6 @@ enum {
#define SERR_INT _MMIO(0xc4040)
#define SERR_INT_POISON (1<<31)
-#define SERR_INT_TRANS_C_FIFO_UNDERRUN(1<<6)
-#define SERR_INT_TRANS_B_FIFO_UNDERRUN(1<<3)
-#define SERR_INT_TRANS_A_FIFO_UNDERRUN(1<<0)
#define SERR_INT_TRANS_FIFO_UNDERRUN(pipe)(1<<((pipe)*3))
/* digital port hotplug */
--
2.7.4
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[Intel-gfx] [PATCH FOR CI 2/5] drm/i915: Remove I915_MAX_PIPES dependency for DDB allocation
Remove dependency for I915_MAX_PIPES by replacing it with
for_each_pipe() macro.
v2: use 'enum pipe pipe' instead of 'i'
Reviewed-by: Ville Syrjälä
Signed-off-by: Ramalingam C
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/intel_display.c | 5 -
drivers/gpu/drm/i915/intel_drv.h | 3 ++-
drivers/gpu/drm/i915/intel_pm.c | 12 +++-
3 files changed, 13 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 45d6e57..69b501a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12223,7 +12223,10 @@ static void skl_update_crtcs(struct drm_atomic_state
*state)
if (updated & cmask || !cstate->base.active)
continue;
- if (skl_ddb_allocation_overlaps(entries,
&cstate->wm.skl.ddb, i))
+ if (skl_ddb_allocation_overlaps(dev_priv,
+ entries,
+ &cstate->wm.skl.ddb,
+ i))
continue;
updated |= cmask;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0cab667..ceb3b82 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1893,7 +1893,8 @@ int intel_enable_sagv(struct drm_i915_private *dev_priv);
int intel_disable_sagv(struct drm_i915_private *dev_priv);
bool skl_wm_level_equals(const struct skl_wm_level *l1,
const struct skl_wm_level *l2);
-bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,
+bool skl_ddb_allocation_overlaps(struct drm_i915_private *dev_priv,
+const struct skl_ddb_entry **entries,
const struct skl_ddb_entry *ddb,
int ignore);
bool ilk_disable_lp_wm(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9d0ca26..39acfad 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4820,16 +4820,18 @@ static inline bool skl_ddb_entries_overlap(const struct
skl_ddb_entry *a,
return a->start < b->end && b->start < a->end;
}
-bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,
+bool skl_ddb_allocation_overlaps(struct drm_i915_private *dev_priv,
+const struct skl_ddb_entry **entries,
const struct skl_ddb_entry *ddb,
int ignore)
{
- int i;
+ enum pipe pipe;
- for (i = 0; i < I915_MAX_PIPES; i++)
- if (i != ignore && entries[i] &&
- skl_ddb_entries_overlap(ddb, entries[i]))
+ for_each_pipe(dev_priv, pipe) {
+ if (pipe != ignore && entries[pipe] &&
+ skl_ddb_entries_overlap(ddb, entries[pipe]))
return true;
+ }
return false;
}
--
2.7.4
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[Intel-gfx] [PATCH FOR CI 3/5] drm/i915: Fold IRQ pipe masks
Fold IRQ pipe masks into one loop instead of hardcoding per pipe.
Reviewed-by: Ville Syrjälä
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/i915_irq.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index de77713..a38ad60 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3610,16 +3610,15 @@ static void gen8_de_irq_postinstall(struct
drm_i915_private *dev_priv)
else if (IS_BROADWELL(dev_priv))
de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
- dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
- dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
- dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
+ for_each_pipe(dev_priv, pipe) {
+ dev_priv->de_irq_mask[pipe] = ~de_pipe_masked;
- for_each_pipe(dev_priv, pipe)
if (intel_display_power_is_enabled(dev_priv,
POWER_DOMAIN_PIPE(pipe)))
GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
dev_priv->de_irq_mask[pipe],
de_pipe_enables);
+ }
GEN3_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
GEN3_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
--
2.7.4
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[Intel-gfx] [PATCH FOR CI 4/5] drm/i915: Favor for_each_pipe() macro
Favor for_each_pipe() macro when looping through pipes.
v2: use 'enum pipe pipe' instead of 'i'
Reviewed-by: Ville Syrjälä
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/intel_pipe_crc.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c
b/drivers/gpu/drm/i915/intel_pipe_crc.c
index 24d781f..899839f 100644
--- a/drivers/gpu/drm/i915/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
@@ -206,11 +206,11 @@ static const char *pipe_crc_source_name(enum
intel_pipe_crc_source source)
static int display_crc_ctl_show(struct seq_file *m, void *data)
{
struct drm_i915_private *dev_priv = m->private;
- int i;
+ enum pipe pipe;
- for (i = 0; i < I915_MAX_PIPES; i++)
- seq_printf(m, "%c %s\n", pipe_name(i),
- pipe_crc_source_name(dev_priv->pipe_crc[i].source));
+ for_each_pipe(dev_priv, pipe)
+ seq_printf(m, "%c %s\n", pipe_name(pipe),
+
pipe_crc_source_name(dev_priv->pipe_crc[pipe].source));
return 0;
}
--
2.7.4
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Re: [Intel-gfx] [PATCH 1/8] drm/i915/bios: parse DDI ports also for CHV for HDMI DDC pin and DP AUX channel
On Mon, 09 Oct 2017, Ville Syrjälä wrote:
> On Thu, Sep 28, 2017 at 11:21:57AM +0300, Jani Nikula wrote:
>> While technically CHV isn't DDI, we do look at the VBT based DDI port
>> info for HDMI DDC pin and DP AUX channel. (We call these "alternate",
>> but they're really just something that aren't platform defaults.)
>>
>> In commit e4ab73a13291 ("drm/i915: Respect alternate_ddc_pin for all DDI
>> ports") Ville writes, "IIRC there may be CHV system that might actually
>> need this."
>>
>> I'm not sure why there couldn't be even more platforms that need this,
>> but start conservative, and parse the info for CHV in addition to DDI.
>
> Going back as far as VLV might make some sense since it came out at around
> the same time as HSW, and IIRC the VBT versions seen on VLV and HSW are
> more less the same.
Let's do that later as needed.
> Series lgtm
> Reviewed-by: Ville Syrjälä
Pushed all to dinq, thanks for the review.
BR,
Jani.
>
>>
>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100553
>> Reported-by: Marek Wilczewski
>> Cc: sta...@vger.kernel.org
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/intel_bios.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_bios.c
>> b/drivers/gpu/drm/i915/intel_bios.c
>> index 3747d8df0175..6b8d396ab605 100644
>> --- a/drivers/gpu/drm/i915/intel_bios.c
>> +++ b/drivers/gpu/drm/i915/intel_bios.c
>> @@ -1247,7 +1247,7 @@ static void parse_ddi_ports(struct drm_i915_private
>> *dev_priv,
>> {
>> enum port port;
>>
>> -if (!HAS_DDI(dev_priv))
>> +if (!HAS_DDI(dev_priv) && !IS_CHERRYVIEW(dev_priv))
>> return;
>>
>> if (!dev_priv->vbt.child_dev_num)
>> --
>> 2.11.0
--
Jani Nikula, Intel Open Source Technology Center
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for Various retries for LSPCON
== Series Details == Series: Various retries for LSPCON URL : https://patchwork.freedesktop.org/series/31639/ State : success == Summary == Series 31639v1 Various retries for LSPCON https://patchwork.freedesktop.org/api/1.0/series/31639/revisions/1/mbox/ Test gem_exec_suspend: Subgroup basic-s4-devices: dmesg-warn -> PASS (fi-kbl-7567u) fdo#102294 +3 Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-b: incomplete -> PASS (fi-kbl-r) fdo#102846 Test pm_rpm: Subgroup basic-pci-d3-state: dmesg-warn -> PASS (fi-cfl-s) fdo#103169 Test drv_module_reload: Subgroup basic-reload: dmesg-warn -> PASS (fi-cfl-s) fdo#103186 Subgroup basic-reload-inject: incomplete -> PASS (fi-cfl-s) fdo#103022 fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294 fdo#102846 https://bugs.freedesktop.org/show_bug.cgi?id=102846 fdo#103169 https://bugs.freedesktop.org/show_bug.cgi?id=103169 fdo#103186 https://bugs.freedesktop.org/show_bug.cgi?id=103186 fdo#103022 https://bugs.freedesktop.org/show_bug.cgi?id=103022 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:456s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:470s fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:395s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:565s fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:284s fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:516s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:522s fi-byt-j1900 total:289 pass:253 dwarn:1 dfail:0 fail:0 skip:35 time:533s fi-byt-n2820 total:289 pass:249 dwarn:1 dfail:0 fail:0 skip:39 time:514s fi-cfl-s total:289 pass:256 dwarn:1 dfail:0 fail:0 skip:32 time:557s fi-cnl-y total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:621s fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:428s fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:598s fi-hsw-4770 total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:442s fi-hsw-4770r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:417s fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:459s fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:507s fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:471s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:504s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:572s fi-kbl-7567u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:486s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:593s fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:0 skip:66 time:665s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:478s fi-skl-6700hqtotal:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:652s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:534s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:518s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:475s fi-snb-2520m total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:576s fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:431s 6a08510077ad5bdbac044038138f217e413cdca2 drm-tip: 2017y-10m-10d-07h-48m-31s UTC integration manifest 0803f1bdb9cc drm/i915: Add retries for LSPCON detection 919f3410bdf7 drm/i915: Don't give up waiting on INVALID_MODE 714ba04dd953 drm: Add retries for lspcon mode detection == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5967/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Allow null render state batchbuffers bigger than one page
Quoting Rodrigo Vivi (2017-10-05 05:34:02) > On Thu, Aug 24, 2017 at 11:00:27PM +, Rodrigo Vivi wrote: > > On Thu, Aug 24, 2017 at 3:39 PM, Oscar Mateo wrote: > > > > > > > > > On 08/23/2017 05:01 PM, Rodrigo Vivi wrote: > > >> > > >> On Tue, Jul 18, 2017 at 8:15 AM, Oscar Mateo > > >> wrote: > > >>> > > >>> > > >>> > > >>> On 07/14/2017 08:08 AM, Chris Wilson wrote: > > > > Quoting Oscar Mateo (2017-07-14 15:52:59) > > > > > > > > > > > > On 07/13/2017 03:28 PM, Rodrigo Vivi wrote: > > >> > > >> On Wed, May 3, 2017 at 9:31 AM, Chris Wilson > > >> > > >> wrote: > > >>> > > >>> On Wed, May 03, 2017 at 09:12:18AM +, Oscar Mateo wrote: > > > > On 05/03/2017 08:52 AM, Mika Kuoppala wrote: > > > > Oscar Mateo [1] writes: > > > > > > On 05/02/2017 09:17 AM, Mika Kuoppala wrote: > > > > Chris Wilson [2] writes: > > > > > > On Fri, Apr 28, 2017 at 09:11:06AM +, Oscar Mateo wrote: > > > > The new batchbuffer for CNL surpasses the 4096 byte mark. > > > > Cc: Mika Kuoppala [3] > > Cc: Ben Widawsky [4] > > Signed-off-by: Oscar Mateo [5] > > > > Evil, 4k+ of nothing-ness that userspace then has to configure > > for > > itself > > for correctness anyway. > > > > Patch looks ok, but still question the sanity. > > > > Is there a requirement for CNL to init the renderstate? > > > > I would like to drop the render state init from CNL if > > we can't find evidence that it needs it. Bspec indicates > > that it doesnt. > > >> > > >> I'd like to drop as well, and I was hearing people around telling we > > >> didn't need anymore, > > >> however without this during power on I had bad failures... > > >> > > > The best I could get from architecture (+Raf) is that setting valid > > > and > > > coherent values for the whole render state is required as soon as the > > > context is created, no matter who does it. If you see failures when > > > the > > > KMD does not do it, that means the UMD must be missing something, > > > right? > > > > That is my initial response as well. The kernel does load one context, > > just so that the hardware always has space to write to on power saving. > > The only batch executed for it is the golden render state. Easy enough > > to only initialise that kernel context to isolate whether it is > > self-inflicted or that userspace overlooked something in its state > > management. (I have the view that even if userspace doesn't think it > > needs to use a particular bit of state today, tomorrow it will so will > > need it anyway!) > > -Chris > > >>> > > >>> > > >>> Rodrigo, you have access to a CNL: can you make this test? The idea is > > >>> to > > >>> find out if the root cause for the failures you were seeing is the > > >>> kernel > > >>> default context or in the UMD-created contexts. > > >> > > >> I'm sorry for the delay on this one. > > >> > > >> On the parts I have now I couldn't reproduce the issues I saw during > > >> power-on > > >> where null context helped. > > >> > > >> But anyways apparently we need this right?! > > >> > > >> What about the 4k+ sanity that Chris raised? Anything we should address > > >> first? > > > > > > > > > I don't think Chris had any problem with the batchbuffer being bigger than > > > 4k per se. His concern was: "why do we need to send this batchbuffer from > > > the KMD at all if the UMD has to send something very similar anyway?". > > > Even if this was true (I haven't found anybody to confirm or deny it) > > > there > > > is still the question of the kernel context (which would never get > > > initialized to valid values by the UMD). > > > > so, chris, rv-b? acked-by? > > chris, mika, oscar... > what should we do with this? > just discard, ignore and move on without the null context for gen10+? If there's no requirement for us to have it, then let's break the cargo cult. Certainly userspace does not expect 3DSTATE to have any default value, unlike the defaults specified for mmio state (which is currently causing a huge upset). It's only if the bspec has wording that makes certain valid 3DSTATE (or GPGPU or MEDIA) mandatory for powercontext etc do we have to worry. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Allow null render state batchbuffers bigger than one page
Quoting Chris Wilson (2017-10-10 11:25:38) > Quoting Rodrigo Vivi (2017-10-05 05:34:02) > > On Thu, Aug 24, 2017 at 11:00:27PM +, Rodrigo Vivi wrote: > > > On Thu, Aug 24, 2017 at 3:39 PM, Oscar Mateo > > > wrote: > > > > > > > > > > > > On 08/23/2017 05:01 PM, Rodrigo Vivi wrote: > > > >> > > > >> On Tue, Jul 18, 2017 at 8:15 AM, Oscar Mateo > > > >> wrote: > > > >>> > > > >>> > > > >>> > > > >>> On 07/14/2017 08:08 AM, Chris Wilson wrote: > > > > > > Quoting Oscar Mateo (2017-07-14 15:52:59) > > > > > > > > > > > > > > > > On 07/13/2017 03:28 PM, Rodrigo Vivi wrote: > > > >> > > > >> On Wed, May 3, 2017 at 9:31 AM, Chris Wilson > > > >> > > > >> wrote: > > > >>> > > > >>> On Wed, May 03, 2017 at 09:12:18AM +, Oscar Mateo wrote: > > > > > > On 05/03/2017 08:52 AM, Mika Kuoppala wrote: > > > > > > Oscar Mateo [1] writes: > > > > > > > > > On 05/02/2017 09:17 AM, Mika Kuoppala wrote: > > > > > > Chris Wilson [2] writes: > > > > > > > > > On Fri, Apr 28, 2017 at 09:11:06AM +, Oscar Mateo wrote: > > > > > > The new batchbuffer for CNL surpasses the 4096 byte mark. > > > > > > Cc: Mika Kuoppala [3] > > > Cc: Ben Widawsky [4] > > > Signed-off-by: Oscar Mateo [5] > > > > > > Evil, 4k+ of nothing-ness that userspace then has to > > > configure > > > for > > > itself > > > for correctness anyway. > > > > > > Patch looks ok, but still question the sanity. > > > > > > Is there a requirement for CNL to init the renderstate? > > > > > > I would like to drop the render state init from CNL if > > > we can't find evidence that it needs it. Bspec indicates > > > that it doesnt. > > > >> > > > >> I'd like to drop as well, and I was hearing people around telling > > > >> we > > > >> didn't need anymore, > > > >> however without this during power on I had bad failures... > > > >> > > > > The best I could get from architecture (+Raf) is that setting valid > > > > and > > > > coherent values for the whole render state is required as soon as > > > > the > > > > context is created, no matter who does it. If you see failures when > > > > the > > > > KMD does not do it, that means the UMD must be missing something, > > > > right? > > > > > > That is my initial response as well. The kernel does load one > > > context, > > > just so that the hardware always has space to write to on power > > > saving. > > > The only batch executed for it is the golden render state. Easy > > > enough > > > to only initialise that kernel context to isolate whether it is > > > self-inflicted or that userspace overlooked something in its state > > > management. (I have the view that even if userspace doesn't think it > > > needs to use a particular bit of state today, tomorrow it will so > > > will > > > need it anyway!) > > > -Chris > > > >>> > > > >>> > > > >>> Rodrigo, you have access to a CNL: can you make this test? The idea > > > >>> is to > > > >>> find out if the root cause for the failures you were seeing is the > > > >>> kernel > > > >>> default context or in the UMD-created contexts. > > > >> > > > >> I'm sorry for the delay on this one. > > > >> > > > >> On the parts I have now I couldn't reproduce the issues I saw during > > > >> power-on > > > >> where null context helped. > > > >> > > > >> But anyways apparently we need this right?! > > > >> > > > >> What about the 4k+ sanity that Chris raised? Anything we should address > > > >> first? > > > > > > > > > > > > I don't think Chris had any problem with the batchbuffer being bigger > > > > than > > > > 4k per se. His concern was: "why do we need to send this batchbuffer > > > > from > > > > the KMD at all if the UMD has to send something very similar anyway?". > > > > Even if this was true (I haven't found anybody to confirm or deny it) > > > > there > > > > is still the question of the kernel context (which would never get > > > > initialized to valid values by the UMD). > > > > > > so, chris, rv-b? acked-by? > > > > chris, mika, oscar... > > what should we do with this? > > just discard, ignore and move on without the null context for gen10+? > > If there's no requirement for us to have it, then let's break the cargo > cult. Certainly userspace does not expect 3DSTATE to have any default > value, unlike the defaults specified for mmio state (which is currently > causing a huge upset). It's only if the bspec has wording that makes > certain valid 3DSTATE (or GPGPU or MEDIA) mandatory for powercontext etc > do we have to worry. The other
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Miscellaneous fixes to reduce dependency for I915_MAX_PIPES (rev2)
== Series Details == Series: drm/i915: Miscellaneous fixes to reduce dependency for I915_MAX_PIPES (rev2) URL : https://patchwork.freedesktop.org/series/30336/ State : success == Summary == Series 30336v2 drm/i915: Miscellaneous fixes to reduce dependency for I915_MAX_PIPES https://patchwork.freedesktop.org/api/1.0/series/30336/revisions/2/mbox/ Test kms_frontbuffer_tracking: Subgroup basic: pass -> DMESG-WARN (fi-bdw-5557u) fdo#102473 Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-b: incomplete -> PASS (fi-kbl-r) fdo#102846 Test pm_rpm: Subgroup basic-pci-d3-state: dmesg-warn -> PASS (fi-cfl-s) fdo#103169 Test drv_module_reload: Subgroup basic-no-display: pass -> DMESG-WARN (fi-cfl-s) fdo#103022 +1 fdo#102473 https://bugs.freedesktop.org/show_bug.cgi?id=102473 fdo#102846 https://bugs.freedesktop.org/show_bug.cgi?id=102846 fdo#103169 https://bugs.freedesktop.org/show_bug.cgi?id=103169 fdo#103022 https://bugs.freedesktop.org/show_bug.cgi?id=103022 fi-bdw-5557u total:289 pass:267 dwarn:1 dfail:0 fail:0 skip:21 time:457s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:467s fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:390s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:563s fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:287s fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:522s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:522s fi-byt-j1900 total:289 pass:253 dwarn:1 dfail:0 fail:0 skip:35 time:532s fi-byt-n2820 total:289 pass:249 dwarn:1 dfail:0 fail:0 skip:39 time:522s fi-cfl-s total:289 pass:253 dwarn:4 dfail:0 fail:0 skip:32 time:564s fi-cnl-y total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:613s fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:434s fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:597s fi-hsw-4770 total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:439s fi-hsw-4770r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:417s fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:462s fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:509s fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:475s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:502s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:581s fi-kbl-7567u total:289 pass:265 dwarn:4 dfail:0 fail:0 skip:20 time:489s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:588s fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:0 skip:66 time:651s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:475s fi-skl-6700hqtotal:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:657s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:528s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:506s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:470s fi-snb-2520m total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:581s fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:427s 6a08510077ad5bdbac044038138f217e413cdca2 drm-tip: 2017y-10m-10d-07h-48m-31s UTC integration manifest 19cfe6fbc051 drm/i915: Cleanup South Error Interrupts ddcd3ac54ef1 drm/i915: Favor for_each_pipe() macro d3f2a5aad5e7 drm/i915: Fold IRQ pipe masks e751b00962fb drm/i915: Remove I915_MAX_PIPES dependency for DDB allocation ba0560b1b56e drm/i915: Don't relay on I915_MAX_PIPES == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5968/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Increase atomic update vblank evasion time with lockdep (rev2)
== Series Details == Series: drm/i915: Increase atomic update vblank evasion time with lockdep (rev2) URL : https://patchwork.freedesktop.org/series/31630/ State : failure == Summary == Test kms_flip: Subgroup modeset-vs-vblank-race-interruptible: pass -> FAIL (shard-hsw) Test gem_flink_race: Subgroup flink_close: pass -> FAIL (shard-hsw) fdo#102655 fdo#102655 https://bugs.freedesktop.org/show_bug.cgi?id=102655 shard-hswtotal:2552 pass:1410 dwarn:24 dfail:0 fail:15 skip:1103 time:9585s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5965/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Preallocate our mmu notifier workequeu to unbreak cpu hotplug deadlock
On Mon, Oct 09, 2017 at 06:44:00PM +0200, Daniel Vetter wrote:
> 4.14-rc1 gained the fancy new cross-release support in lockdep, which
> seems to have uncovered a few more rules about what is allowed and
> isn't.
>
> This one here seems to indicate that allocating a work-queue while
> holding mmap_sem is a no-go, so let's try to preallocate it.
>
> Of course another way to break this chain would be somewhere in the
> cpu hotplug code, since this isn't the only trace we're finding now
> which goes through msr_create_device.
>
> Full lockdep splat:
>
> ==
> WARNING: possible circular locking dependency detected
> 4.14.0-rc1-CI-CI_DRM_3118+ #1 Tainted: G U
> --
> prime_mmap/1551 is trying to acquire lock:
> (cpu_hotplug_lock.rw_sem){}, at: []
> apply_workqueue_attrs+0x17/0x50
>
> but task is already holding lock:
> (&dev_priv->mm_lock){+.+.}, at: []
> i915_gem_userptr_init__mmu_notifier+0x14a/0x270 [i915]
>
> which lock already depends on the new lock.
>
> the existing dependency chain (in reverse order) is:
>
> -> #6 (&dev_priv->mm_lock){+.+.}:
>__lock_acquire+0x1420/0x15e0
>lock_acquire+0xb0/0x200
>__mutex_lock+0x86/0x9b0
>mutex_lock_nested+0x1b/0x20
>i915_gem_userptr_init__mmu_notifier+0x14a/0x270 [i915]
>i915_gem_userptr_ioctl+0x222/0x2c0 [i915]
>drm_ioctl_kernel+0x69/0xb0
>drm_ioctl+0x2f9/0x3d0
>do_vfs_ioctl+0x94/0x670
>SyS_ioctl+0x41/0x70
>entry_SYSCALL_64_fastpath+0x1c/0xb1
>
> -> #5 (&mm->mmap_sem){}:
>__lock_acquire+0x1420/0x15e0
>lock_acquire+0xb0/0x200
>__might_fault+0x68/0x90
>_copy_to_user+0x23/0x70
>filldir+0xa5/0x120
>dcache_readdir+0xf9/0x170
>iterate_dir+0x69/0x1a0
>SyS_getdents+0xa5/0x140
>entry_SYSCALL_64_fastpath+0x1c/0xb1
>
> -> #4 (&sb->s_type->i_mutex_key#5){}:
>down_write+0x3b/0x70
>handle_create+0xcb/0x1e0
>devtmpfsd+0x139/0x180
>kthread+0x152/0x190
>ret_from_fork+0x27/0x40
>
> -> #3 ((complete)&req.done){+.+.}:
>__lock_acquire+0x1420/0x15e0
>lock_acquire+0xb0/0x200
>wait_for_common+0x58/0x210
>wait_for_completion+0x1d/0x20
>devtmpfs_create_node+0x13d/0x160
>device_add+0x5eb/0x620
>device_create_groups_vargs+0xe0/0xf0
>device_create+0x3a/0x40
>msr_device_create+0x2b/0x40
>cpuhp_invoke_callback+0xa3/0x840
>cpuhp_thread_fun+0x7a/0x150
>smpboot_thread_fn+0x18a/0x280
>kthread+0x152/0x190
>ret_from_fork+0x27/0x40
>
> -> #2 (cpuhp_state){+.+.}:
>__lock_acquire+0x1420/0x15e0
>lock_acquire+0xb0/0x200
>cpuhp_issue_call+0x10b/0x170
>__cpuhp_setup_state_cpuslocked+0x134/0x2a0
>__cpuhp_setup_state+0x46/0x60
>page_writeback_init+0x43/0x67
>pagecache_init+0x3d/0x42
>start_kernel+0x3a8/0x3fc
>x86_64_start_reservations+0x2a/0x2c
>x86_64_start_kernel+0x6d/0x70
>verify_cpu+0x0/0xfb
>
> -> #1 (cpuhp_state_mutex){+.+.}:
>__lock_acquire+0x1420/0x15e0
>lock_acquire+0xb0/0x200
>__mutex_lock+0x86/0x9b0
>mutex_lock_nested+0x1b/0x20
>__cpuhp_setup_state_cpuslocked+0x52/0x2a0
>__cpuhp_setup_state+0x46/0x60
>page_alloc_init+0x28/0x30
>start_kernel+0x145/0x3fc
>x86_64_start_reservations+0x2a/0x2c
>x86_64_start_kernel+0x6d/0x70
>verify_cpu+0x0/0xfb
>
> -> #0 (cpu_hotplug_lock.rw_sem){}:
>check_prev_add+0x430/0x840
>__lock_acquire+0x1420/0x15e0
>lock_acquire+0xb0/0x200
>cpus_read_lock+0x3d/0xb0
>apply_workqueue_attrs+0x17/0x50
>__alloc_workqueue_key+0x1d8/0x4d9
>i915_gem_userptr_init__mmu_notifier+0x1fb/0x270 [i915]
>i915_gem_userptr_ioctl+0x222/0x2c0 [i915]
>drm_ioctl_kernel+0x69/0xb0
>drm_ioctl+0x2f9/0x3d0
>do_vfs_ioctl+0x94/0x670
>SyS_ioctl+0x41/0x70
>entry_SYSCALL_64_fastpath+0x1c/0xb1
>
> other info that might help us debug this:
>
> Chain exists of:
> cpu_hotplug_lock.rw_sem --> &mm->mmap_sem --> &dev_priv->mm_lock
>
> Possible unsafe locking scenario:
>
>CPU0CPU1
>
> lock(&dev_priv->mm_lock);
>lock(&mm->mmap_sem);
>lock(&dev_priv->mm_lock);
> lock(cpu_hotplug_lock.rw_sem);
>
> *** DEADLOCK ***
>
> 2 locks held by prime_mmap/1551:
> #0: (&mm->mmap_sem){}, at: []
> i915_gem_userptr_init__mmu_notifier+0x138/0x270 [i915]
> #1: (&dev_priv->mm_lock){+.+.}, at: []
> i915_gem_userptr_init__mmu_notifier+0x14a/0x270 [i915]
>
> stack backtrace:
> CPU: 4 PID: 1551 Comm: prime_mmap Tainted: G U
> 4.14.0-rc1-CI-CI_DRM_3118+ #1
> Hardware
Re: [Intel-gfx] [PATCH v15 6/7] drm/i915: Introduce GEM proxy
On Tue, 2017-10-10 at 17:50 +0800, Tina Zhang wrote:
> GEM proxy is a kind of GEM, whose backing physical memory is pinned
> and produced by guest VM and is used by host as read only. With GEM
> proxy, host is able to access guest physical memory through GEM object
> interface. As GEM proxy is such a special kind of GEM, a new flag
> I915_GEM_OBJECT_IS_PROXY is introduced to ban host from changing the
> backing storage of GEM proxy.
>
> v14:
> - return -ENXIO when gem proxy object is banned by ioctl.
> (Chris) (Daniel)
>
> v13:
> - add comments to GEM proxy. (Chris)
> - don't ban GEM proxy in i915_gem_sw_finish_ioctl. (Chris)
> - check GEM proxy bar after finishing i915_gem_object_wait. (Chris)
> - remove GEM proxy bar in i915_gem_madvise_ioctl.
>
> v6:
> - add gem proxy barrier in the following ioctls. (Chris)
> i915_gem_set_caching_ioctl
> i915_gem_set_domain_ioctl
> i915_gem_sw_finish_ioctl
> i915_gem_set_tiling_ioctl
> i915_gem_madvise_ioctl
>
> Signed-off-by: Tina Zhang
> Cc: Daniel Vetter
> Cc: Chris Wilson
> Cc: Joonas Lahtinen
> +++ b/drivers/gpu/drm/i915/i915_gem_object.h
> @@ -39,6 +39,7 @@ struct drm_i915_gem_object_ops {
> unsigned int flags;
> #define I915_GEM_OBJECT_HAS_STRUCT_PAGE BIT(0)
> #define I915_GEM_OBJECT_IS_SHRINKABLE BIT(1)
> +#define I915_GEM_OBJECT_IS_PROXY BIT(2)
Please fix the indent to match. Do convert the above two lines to use
TAB character too.
> @@ -1690,7 +1704,7 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
>*/
> if (!obj->base.filp) {
> i915_gem_object_put(obj);
> - return -EINVAL;
> + return -ENXIO;
> }
This still needs to be a separate patch.
With those fixes, this is;
Reviewed-by: Joonas Lahtinen
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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Re: [Intel-gfx] [PATCH v3 0/3] Various retries for LSPCON
Regards Shashank On 10/10/2017 3:42 PM, Saarinen, Jani wrote: Hi, -Original Message- From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of Shashank Sharma Sent: tiistai 10. lokakuuta 2017 13.08 To: intel-gfx@lists.freedesktop.org Subject: [Intel-gfx] [PATCH v3 0/3] Various retries for LSPCON This patch series adds various retries and delays in DRM and I915 layer, to handle some of the read failures while dealing with LSPCON devices. Should we have reference to fdo bugs? https://bugs.freedesktop.org/show_bug.cgi?id=102294 https://bugs.freedesktop.org/show_bug.cgi?id=102295 Yes, sure seems like a good idea. and what about this? https://bugs.freedesktop.org/show_bug.cgi?id=102359 This seems like one probable candidate :) - Shashank LSPCON devices are sometimes slow to respond and the vendores expect us to retry while probing the device. The typical scenarios are getting fixed / handled with this patch series are look like this failure during LSPCON suspend/resume: [drm:drm_lspcon_get_mode] *ERROR* LSPCON read(0x80, 0x41) failed [drm:lspcon_wait_mode [i915]] *ERROR* Error reading LSPCON mode [drm:drm_lspcon_get_mode] *ERROR* LSPCON read(0x80, 0x41) failed [drm:lspcon_change_mode.constprop.4 [i915]] *ERROR* Error reading LSPCON mode [drm:lspcon_resume [i915]] *ERROR* LSPCON resume failed Setting dangerous option reset - tainting kernel Shashank Sharma (3): drm: Add retries for lspcon mode detection drm/i915: Don't give up waiting on INVALID_MODE drm/i915: Add retries for LSPCON detection drivers/gpu/drm/drm_dp_dual_mode_helper.c | 16 +--- drivers/gpu/drm/i915/intel_lspcon.c | 22 +++--- 2 files changed, 28 insertions(+), 10 deletions(-) -- 2.7.4 Jani Saarinen Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] i-g-t/tests: Drop gem_seqno_wrap, gem_pin, gem_hangcheck_forcewake
+ Chris and Mika for R-b's as they're the test authors + Arek, Tomi for CI blacklist reduction On Tue, 2017-10-10 at 11:55 +0300, Abdiel Janulgue wrote: > This improves the GEM tests section of I-G-T to make it more > suitable for CI testing > > Cc: Joonas Lahtinen > Signed-off-by: Abdiel Janulgue For future reference, lets have the tags in chronological order. (Suggested-by: if any) S-o-b, Cc, Reviewed-by etc... This checks with the test blacklisting TODO items. Reviewed-by: Joonas Lahtinen Arek, Tomi; After this is merged, the the following lines can be removed from CI blacklist. igt@gem_pin(@.*)? igt@gem_seqno_wrap(@.*)? igt@gem_hangcheck_forcewake(@.*)? Regards, Joonas -- Joonas Lahtinen Open Source Technology Center Intel Corporation ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Silently fallback to 4k scratch
If we fail to allocate a 64k hugepage for scratch, we try again with a
normal 4k page (with some loss of efficiency at runtime). As we handle
this gracefully, we do not need a noisy allocation failure warning.
Signed-off-by: Chris Wilson
Cc: Matthew Auld
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 4c605785e2b3..ca7fd34fbe8b 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -538,7 +538,7 @@ setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
if (i915_vm_is_48bit(vm) &&
HAS_PAGE_SIZES(vm->i915, I915_GTT_PAGE_SIZE_64K)) {
order = get_order(I915_GTT_PAGE_SIZE_64K);
- page = alloc_pages(gfp | __GFP_ZERO, order);
+ page = alloc_pages(gfp | __GFP_ZERO | __GFP_NOWARN, order);
if (page) {
addr = dma_map_page(vm->dma, page, 0,
I915_GTT_PAGE_SIZE_64K,
--
2.15.0.rc0
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Re: [Intel-gfx] [PATCH] drm/i915: Silently fallback to 4k scratch
On 10 October 2017 at 12:10, Chris Wilson wrote: > If we fail to allocate a 64k hugepage for scratch, we try again with a > normal 4k page (with some loss of efficiency at runtime). As we handle > this gracefully, we do not need a noisy allocation failure warning. > > Signed-off-by: Chris Wilson > Cc: Matthew Auld > Cc: Joonas Lahtinen Reviewed-by: Matthew Auld ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Silently fallback to 4k scratch
On Tue, 2017-10-10 at 12:10 +0100, Chris Wilson wrote: > If we fail to allocate a 64k hugepage for scratch, we try again with a > normal 4k page (with some loss of efficiency at runtime). As we handle > this gracefully, we do not need a noisy allocation failure warning. > > Signed-off-by: Chris Wilson > Cc: Matthew Auld > Cc: Joonas Lahtinen Do we want to maybe add a DRM_INFO to else branch? Reviewed-by: Joonas Lahtinen Regards, Joonas -- Joonas Lahtinen Open Source Technology Center Intel Corporation ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t v2 6/9] intel-gpu-overlay: Use RAPL PMU for power reading
From: Tvrtko Ursulin
Wire up to the RAPL PMU for GPU energy readings.
The only complication is that we have to add code to parse:
# cat /sys/devices/power/events/energy-gpu.scale
2.3283064365386962890625e-10
v2: Link with -lm.
Signed-off-by: Tvrtko Ursulin
---
lib/igt_perf.c | 16 --
lib/igt_perf.h | 1 +
overlay/Makefile.am | 2 +-
overlay/power.c | 156 +++-
overlay/power.h | 2 +
5 files changed, 134 insertions(+), 43 deletions(-)
diff --git a/lib/igt_perf.c b/lib/igt_perf.c
index 208474302fcc..0221461e918f 100644
--- a/lib/igt_perf.c
+++ b/lib/igt_perf.c
@@ -27,11 +27,12 @@ uint64_t i915_type_id(void)
return strtoull(buf, NULL, 0);
}
-static int _perf_open(uint64_t config, int group, uint64_t format)
+static int
+_perf_open(uint64_t type, uint64_t config, int group, uint64_t format)
{
struct perf_event_attr attr = { };
- attr.type = i915_type_id();
+ attr.type = type;
if (attr.type == 0)
return -ENOENT;
@@ -46,11 +47,18 @@ static int _perf_open(uint64_t config, int group, uint64_t
format)
int perf_i915_open(uint64_t config)
{
- return _perf_open(config, -1, PERF_FORMAT_TOTAL_TIME_ENABLED);
+ return _perf_open(i915_type_id(), config, -1,
+ PERF_FORMAT_TOTAL_TIME_ENABLED);
}
int perf_i915_open_group(uint64_t config, int group)
{
- return _perf_open(config, group,
+ return _perf_open(i915_type_id(), config, group,
PERF_FORMAT_TOTAL_TIME_ENABLED | PERF_FORMAT_GROUP);
}
+
+int igt_perf_open(uint64_t type, uint64_t config)
+{
+ return _perf_open(type, config, -1,
+ PERF_FORMAT_TOTAL_TIME_ENABLED);
+}
diff --git a/lib/igt_perf.h b/lib/igt_perf.h
index 285823786324..b1f525739c69 100644
--- a/lib/igt_perf.h
+++ b/lib/igt_perf.h
@@ -99,5 +99,6 @@ perf_event_open(struct perf_event_attr *attr,
uint64_t i915_type_id(void);
int perf_i915_open(uint64_t config);
int perf_i915_open_group(uint64_t config, int group);
+int igt_perf_open(uint64_t type, uint64_t config);
#endif /* I915_PERF_H */
diff --git a/overlay/Makefile.am b/overlay/Makefile.am
index cefde2d040f8..f49f54ac3590 100644
--- a/overlay/Makefile.am
+++ b/overlay/Makefile.am
@@ -63,7 +63,7 @@ intel_gpu_overlay_SOURCES += \
intel_gpu_overlay_SOURCES += $(both_x11_sources)
-intel_gpu_overlay_LDADD = $(LDADD) -lrt
+intel_gpu_overlay_LDADD = $(LDADD) -lrt -lm
EXTRA_DIST= \
README \
diff --git a/overlay/power.c b/overlay/power.c
index 805f4ca7805c..35e446e6bce5 100644
--- a/overlay/power.c
+++ b/overlay/power.c
@@ -30,60 +30,138 @@
#include
#include
#include
+#include
+#include
#include "igt_perf.h"
#include "power.h"
#include "debugfs.h"
-/* XXX Is this exposed through RAPL? */
+static uint64_t filename_to_u64(const char *filename, int base)
+{
+ char buf[64], *b;
+ ssize_t ret;
+ int fd;
-int power_init(struct power *power)
+ fd = open(filename, O_RDONLY);
+ if (fd < 0)
+ return 0;
+
+ ret = read(fd, buf, sizeof(buf) - 1);
+ close(fd);
+ if (ret < 1)
+ return 0;
+
+ buf[ret] = '\0';
+
+ b = buf;
+ while (*b && !isdigit(*b))
+ b++;
+
+ return strtoull(b, NULL, base);
+}
+
+static uint64_t debugfs_file_to_u64(const char *name)
{
- char buf[4096];
- int fd, len;
+ char buf[1024];
- memset(power, 0, sizeof(*power));
+ snprintf(buf, sizeof(buf), "%s/%s", debugfs_dri_path, name);
+
+ return filename_to_u64(buf, 0);
+}
- power->fd = -1;
+static uint64_t rapl_type_id(void)
+{
+ return filename_to_u64("/sys/devices/power/type", 10);
+}
- sprintf(buf, "%s/i915_energy_uJ", debugfs_dri_path);
- fd = open(buf, 0);
+static uint64_t rapl_gpu_power(void)
+{
+ return filename_to_u64("/sys/devices/power/events/energy-gpu", 0);
+}
+
+static double filename_to_double(const char *filename)
+{
+ char *dot = NULL, *e = NULL;
+ unsigned long long int decimal;
+ char buf[64], *b;
+ long int val;
+ long int exponent;
+ double result;
+ ssize_t ret;
+ int fd;
+
+ fd = open(filename, O_RDONLY);
if (fd < 0)
- return power->error = errno;
+ return NAN;
- len = read(fd, buf, sizeof(buf));
+ ret = read(fd, buf, sizeof(buf) - 1);
close(fd);
+ if (ret < 1)
+ return NAN;
+
+ buf[ret] = '\0';
+
+ b = buf;
+ while (*b) {
+ if (*b == '.')
+ dot = b;
+ else if (*b == 'e')
+ e = b;
+ b++;
+ }
- if (len < 0)
- return power->error = errno;
+ if (!dot || !e)
+ return NAN;
- buf[len] = '\0';
- if (strtoull(buf, 0, 0) == 0)
-
[Intel-gfx] ✓ Fi.CI.IGT: success for Various retries for LSPCON
== Series Details == Series: Various retries for LSPCON URL : https://patchwork.freedesktop.org/series/31639/ State : success == Summary == shard-hswtotal:2552 pass:1412 dwarn:24 dfail:0 fail:13 skip:1103 time:9584s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5967/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Silently fallback to 4k scratch
== Series Details == Series: drm/i915: Silently fallback to 4k scratch URL : https://patchwork.freedesktop.org/series/31646/ State : success == Summary == Series 31646v1 drm/i915: Silently fallback to 4k scratch https://patchwork.freedesktop.org/api/1.0/series/31646/revisions/1/mbox/ Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-b: pass -> DMESG-WARN (fi-byt-n2820) fdo#101705 fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:452s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:471s fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:391s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:559s fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:283s fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:520s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:529s fi-byt-j1900 total:289 pass:253 dwarn:1 dfail:0 fail:0 skip:35 time:530s fi-byt-n2820 total:289 pass:249 dwarn:1 dfail:0 fail:0 skip:39 time:512s fi-cfl-s total:289 pass:256 dwarn:1 dfail:0 fail:0 skip:32 time:552s fi-cnl-y total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:620s fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:430s fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:601s fi-hsw-4770 total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:435s fi-hsw-4770r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:416s fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:452s fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:498s fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:472s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:500s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:579s fi-kbl-7567u total:289 pass:265 dwarn:4 dfail:0 fail:0 skip:20 time:496s fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:589s fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:0 skip:66 time:657s fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:467s fi-skl-6700hqtotal:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:654s fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:530s fi-skl-6770hqtotal:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:512s fi-skl-gvtdvmtotal:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:466s fi-snb-2520m total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:576s fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:427s 6bcaf2275e52e258c737bc355e73072640be5ac3 drm-tip: 2017y-10m-10d-10h-57m-51s UTC integration manifest af83b9339850 drm/i915: Silently fallback to 4k scratch == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5969/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Silently fallback to 4k scratch
Quoting Joonas Lahtinen (2017-10-10 12:30:17) > On Tue, 2017-10-10 at 12:10 +0100, Chris Wilson wrote: > > If we fail to allocate a 64k hugepage for scratch, we try again with a > > normal 4k page (with some loss of efficiency at runtime). As we handle > > this gracefully, we do not need a noisy allocation failure warning. > > > > Signed-off-by: Chris Wilson > > Cc: Matthew Auld > > Cc: Joonas Lahtinen > > Do we want to maybe add a DRM_INFO to else branch? What do you want the user to do? Shutdown firefox and start again? Maybe debug, but then what do you expect us to do? The ultimate aide would be a diagnostic for slow runtime, for that we could do with a tracepoint to tell us how each binding went (page_sizes vs sg_sizes). -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Use execlists_num_ports instead of size of array
There is function to tell how many ports we have, so use it.
We still have direct relationship with array size and port count,
so no harm was done.
Fixes: 76e70087d360 ("drm/i915: Make execlist port count variable")
Cc: Mika Kuoppala
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_guc_submission.c | 2 +-
drivers/gpu/drm/i915/intel_lrc.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 31381a327347..f15de4dcefde 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -500,7 +500,7 @@ static void i915_guc_submit(struct intel_engine_cs *engine)
const unsigned int engine_id = engine->id;
unsigned int n;
- for (n = 0; n < ARRAY_SIZE(execlists->port); n++) {
+ for (n = 0; n < execlists_num_ports(execlists); n++) {
struct drm_i915_gem_request *rq;
unsigned int count;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 721432ddf403..fbfcf88d7fe3 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -691,7 +691,7 @@ static void
execlist_cancel_port_requests(struct intel_engine_execlists *execlists)
{
struct execlist_port *port = execlists->port;
- unsigned int num_ports = ARRAY_SIZE(execlists->port);
+ unsigned int num_ports = execlists_num_ports(execlists);
while (num_ports-- && port_isset(port)) {
struct drm_i915_gem_request *rq = port_request(port);
--
2.11.0
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[Intel-gfx] [PATCH i-g-t v3 6/9] intel-gpu-overlay: Use RAPL PMU for power reading
From: Tvrtko Ursulin
Wire up to the RAPL PMU for GPU energy readings.
The only complication is that we have to add code to parse:
# cat /sys/devices/power/events/energy-gpu.scale
2.3283064365386962890625e-10
v2: Link with -lm.
v3: strtod can handle scientific notation, even though my initial
reading of the man page did not spot that. (Chris Wilson)
Signed-off-by: Tvrtko Ursulin
---
lib/igt_perf.c | 16 +--
lib/igt_perf.h | 1 +
overlay/Makefile.am | 2 +-
overlay/power.c | 127
overlay/power.h | 2 +
5 files changed, 104 insertions(+), 44 deletions(-)
diff --git a/lib/igt_perf.c b/lib/igt_perf.c
index 208474302fcc..0221461e918f 100644
--- a/lib/igt_perf.c
+++ b/lib/igt_perf.c
@@ -27,11 +27,12 @@ uint64_t i915_type_id(void)
return strtoull(buf, NULL, 0);
}
-static int _perf_open(uint64_t config, int group, uint64_t format)
+static int
+_perf_open(uint64_t type, uint64_t config, int group, uint64_t format)
{
struct perf_event_attr attr = { };
- attr.type = i915_type_id();
+ attr.type = type;
if (attr.type == 0)
return -ENOENT;
@@ -46,11 +47,18 @@ static int _perf_open(uint64_t config, int group, uint64_t
format)
int perf_i915_open(uint64_t config)
{
- return _perf_open(config, -1, PERF_FORMAT_TOTAL_TIME_ENABLED);
+ return _perf_open(i915_type_id(), config, -1,
+ PERF_FORMAT_TOTAL_TIME_ENABLED);
}
int perf_i915_open_group(uint64_t config, int group)
{
- return _perf_open(config, group,
+ return _perf_open(i915_type_id(), config, group,
PERF_FORMAT_TOTAL_TIME_ENABLED | PERF_FORMAT_GROUP);
}
+
+int igt_perf_open(uint64_t type, uint64_t config)
+{
+ return _perf_open(type, config, -1,
+ PERF_FORMAT_TOTAL_TIME_ENABLED);
+}
diff --git a/lib/igt_perf.h b/lib/igt_perf.h
index 285823786324..b1f525739c69 100644
--- a/lib/igt_perf.h
+++ b/lib/igt_perf.h
@@ -99,5 +99,6 @@ perf_event_open(struct perf_event_attr *attr,
uint64_t i915_type_id(void);
int perf_i915_open(uint64_t config);
int perf_i915_open_group(uint64_t config, int group);
+int igt_perf_open(uint64_t type, uint64_t config);
#endif /* I915_PERF_H */
diff --git a/overlay/Makefile.am b/overlay/Makefile.am
index cefde2d040f8..f49f54ac3590 100644
--- a/overlay/Makefile.am
+++ b/overlay/Makefile.am
@@ -63,7 +63,7 @@ intel_gpu_overlay_SOURCES += \
intel_gpu_overlay_SOURCES += $(both_x11_sources)
-intel_gpu_overlay_LDADD = $(LDADD) -lrt
+intel_gpu_overlay_LDADD = $(LDADD) -lrt -lm
EXTRA_DIST= \
README \
diff --git a/overlay/power.c b/overlay/power.c
index 805f4ca7805c..9ac90fde8786 100644
--- a/overlay/power.c
+++ b/overlay/power.c
@@ -30,60 +30,107 @@
#include
#include
#include
+#include
+#include
#include "igt_perf.h"
#include "power.h"
#include "debugfs.h"
-/* XXX Is this exposed through RAPL? */
-
-int power_init(struct power *power)
+static int
+filename_to_buf(const char *filename, char *buf, unsigned int bufsize)
{
- char buf[4096];
- int fd, len;
-
- memset(power, 0, sizeof(*power));
-
- power->fd = -1;
+ int fd;
+ ssize_t ret;
- sprintf(buf, "%s/i915_energy_uJ", debugfs_dri_path);
- fd = open(buf, 0);
+ fd = open(filename, O_RDONLY);
if (fd < 0)
- return power->error = errno;
+ return -1;
- len = read(fd, buf, sizeof(buf));
+ ret = read(fd, buf, bufsize - 1);
close(fd);
+ if (ret < 1)
+ return -1;
- if (len < 0)
- return power->error = errno;
-
- buf[len] = '\0';
- if (strtoull(buf, 0, 0) == 0)
- return power->error = EINVAL;
+ buf[ret] = '\0';
return 0;
}
-static uint64_t file_to_u64(const char *name)
+static uint64_t filename_to_u64(const char *filename, int base)
{
- char buf[4096];
- int fd, len;
+ char buf[64], *b;
- sprintf(buf, "%s/%s", debugfs_dri_path, name);
- fd = open(buf, 0);
- if (fd < 0)
+ if (filename_to_buf(filename, buf, sizeof(buf)))
return 0;
- len = read(fd, buf, sizeof(buf)-1);
- close(fd);
+ /*
+* Handle both single integer and key=value formats by skipping
+* leading non-digits.
+*/
+ b = buf;
+ while (*b && !isdigit(*b))
+ b++;
+
+ return strtoull(b, NULL, base);
+}
+
+static uint64_t debugfs_file_to_u64(const char *name)
+{
+ char buf[1024];
+
+ snprintf(buf, sizeof(buf), "%s/%s", debugfs_dri_path, name);
+
+ return filename_to_u64(buf, 0);
+}
+
+static uint64_t rapl_type_id(void)
+{
+ return filename_to_u64("/sys/devices/power/type", 10);
+}
+
+static uint64_t rapl_gpu_power(void)
+{
+ return filename_to_u64("/sys/devices/power/events/energy-gpu", 0);
+}
-
[Intel-gfx] ✓ Fi.CI.BAT: success for IGT PMU support (rev8)
== Series Details == Series: IGT PMU support (rev8) URL : https://patchwork.freedesktop.org/series/28253/ State : success == Summary == IGT patchset tested on top of latest successful build d7c88290ab6a8393dc341b30c7fb5e27d2952901 syncobj: Add a test for SYNCOBJ_CREATE_SIGNALED with latest DRM-Tip kernel build CI_DRM_3202 6bcaf2275e52 drm-tip: 2017y-10m-10d-10h-57m-51s UTC integration manifest Testlist changes: +igt@perf_pmu@all-busy-check-all +igt@perf_pmu@busy-bcs0 +igt@perf_pmu@busy-check-all-bcs0 +igt@perf_pmu@busy-check-all-rcs0 +igt@perf_pmu@busy-check-all-vcs0 +igt@perf_pmu@busy-check-all-vcs1 +igt@perf_pmu@busy-check-all-vecs0 +igt@perf_pmu@busy-no-semaphores-bcs0 +igt@perf_pmu@busy-no-semaphores-rcs0 +igt@perf_pmu@busy-no-semaphores-vcs0 +igt@perf_pmu@busy-no-semaphores-vcs1 +igt@perf_pmu@busy-no-semaphores-vecs0 +igt@perf_pmu@busy-rcs0 +igt@perf_pmu@busy-vcs0 +igt@perf_pmu@busy-vcs1 +igt@perf_pmu@busy-vecs0 +igt@perf_pmu@cpu-hotplug +igt@perf_pmu@event-wait-rcs0 +igt@perf_pmu@frequency +igt@perf_pmu@idle-bcs0 +igt@perf_pmu@idle-no-semaphores-bcs0 +igt@perf_pmu@idle-no-semaphores-rcs0 +igt@perf_pmu@idle-no-semaphores-vcs0 +igt@perf_pmu@idle-no-semaphores-vcs1 +igt@perf_pmu@idle-no-semaphores-vecs0 +igt@perf_pmu@idle-rcs0 +igt@perf_pmu@idle-vcs0 +igt@perf_pmu@idle-vcs1 +igt@perf_pmu@idle-vecs0 +igt@perf_pmu@init-busy-bcs0 +igt@perf_pmu@init-busy-rcs0 +igt@perf_pmu@init-busy-vcs0 +igt@perf_pmu@init-busy-vcs1 +igt@perf_pmu@init-busy-vecs0 +igt@perf_pmu@init-sema-bcs0 +igt@perf_pmu@init-sema-rcs0 +igt@perf_pmu@init-sema-vcs0 +igt@perf_pmu@init-sema-vcs1 +igt@perf_pmu@init-sema-vecs0 +igt@perf_pmu@init-wait-bcs0 +igt@perf_pmu@init-wait-rcs0 +igt@perf_pmu@init-wait-vcs0 +igt@perf_pmu@init-wait-vcs1 +igt@perf_pmu@init-wait-vecs0 +igt@perf_pmu@interrupts +igt@perf_pmu@invalid-init +igt@perf_pmu@most-busy-check-all-bcs0 +igt@perf_pmu@most-busy-check-all-rcs0 +igt@perf_pmu@most-busy-check-all-vcs0 +igt@perf_pmu@most-busy-check-all-vcs1 +igt@perf_pmu@most-busy-check-all-vecs0 +igt@perf_pmu@multi-client-bcs0 +igt@perf_pmu@multi-client-rcs0 +igt@perf_pmu@multi-client-vcs0 +igt@perf_pmu@multi-client-vcs1 +igt@perf_pmu@multi-client-vecs0 +igt@perf_pmu@other-init-0 +igt@perf_pmu@other-init-1 +igt@perf_pmu@other-init-2 +igt@perf_pmu@other-init-3 +igt@perf_pmu@other-init-4 +igt@perf_pmu@other-init-5 +igt@perf_pmu@other-init-6 +igt@perf_pmu@other-read-0 +igt@perf_pmu@other-read-1 +igt@perf_pmu@other-read-2 +igt@perf_pmu@other-read-3 +igt@perf_pmu@other-read-4 +igt@perf_pmu@other-read-5 +igt@perf_pmu@other-read-6 +igt@perf_pmu@rc6 +igt@perf_pmu@rc6p +igt@perf_pmu@render-node-busy-bcs0 +igt@perf_pmu@render-node-busy-rcs0 +igt@perf_pmu@render-node-busy-vcs0 +igt@perf_pmu@render-node-busy-vcs1 +igt@perf_pmu@render-node-busy-vecs0 +igt@perf_pmu@semaphore-wait-bcs0 +igt@perf_pmu@semaphore-wait-rcs0 +igt@perf_pmu@semaphore-wait-vcs0 +igt@perf_pmu@semaphore-wait-vcs1 +igt@perf_pmu@semaphore-wait-vecs0 Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-b: pass -> DMESG-WARN (fi-byt-n2820) fdo#101705 fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705 fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:461s fi-bdw-gvtdvmtotal:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:479s fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:396s fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:570s fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:286s fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:523s fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:524s fi-byt-j1900 total:289 pass:253 dwarn:1 dfail:0 fail:0 skip:35 time:534s fi-byt-n2820 total:289 pass:249 dwarn:1 dfail:0 fail:0 skip:39 time:536s fi-cfl-s total:289 pass:256 dwarn:1 dfail:0 fail:0 skip:32 time:564s fi-cnl-y total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:634s fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:427s fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:600s fi-hsw-4770 total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:445s fi-hsw-4770r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:422s fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:466s fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:510s fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:478s fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:500s fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:584s fi-kbl-7567u total:289 pass:265 dwarn:4 dfail:0 fail:0 skip:20 time:490s fi-kbl-r total:289
[Intel-gfx] [PATCH i-g-t 0/2] Add support for NV12
This series adds NV12 support to IGT and a test case for checking NV12 functionality. The series is based on the initial version posted by Chandra Konduru during 2015 based on the IGT framework available then. Previous version reference links: https://patchwork.freedesktop.org/patch/57590/ https://patchwork.freedesktop.org/patch/59067/ chandra konduru (2): Prep work for adding NV12 testcase tests/test_nv12.c: Add test to cover NV12 format testing lib/igt_draw.c | 2 +- lib/igt_fb.c | 189 ++-- lib/igt_fb.h | 14 +- lib/igt_kms.c| 50 +++- lib/igt_kms.h| 2 + lib/intel_batchbuffer.c | 14 +- lib/intel_batchbuffer.h | 3 +- lib/intel_reg.h | 1 + lib/ioctl_wrappers.c | 9 + lib/ioctl_wrappers.h | 1 + tests/Makefile.sources | 1 + tests/NV12_Image0.png| Bin 0 -> 42502 bytes tests/NV12_Image1.png| Bin 0 -> 179559 bytes tests/NV12_Image2.png| Bin 0 -> 6385 bytes tests/kms_draw_crc.c | 2 +- tests/kms_frontbuffer_tracking.c | 6 +- tests/kms_render.c | 4 +- tests/kms_rotation_crc.c | 8 +- tests/prime_vgem.c | 2 +- tests/test_nv12.c| 621 +++ 20 files changed, 876 insertions(+), 53 deletions(-) create mode 100644 tests/NV12_Image0.png create mode 100644 tests/NV12_Image1.png create mode 100644 tests/NV12_Image2.png create mode 100644 tests/test_nv12.c -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 1/2] Prep work for adding NV12 testcase
From: chandra konduru
This patch adds necessary prep work for nv12 testcase:
- updated fb allocation functions to handle NV12 format
- igt helper function to return png image size
- igt helper function to calculate start of uv in a given NV12 buffer
- igt helper function to map buffer for host access
- igt helper function to return plane id based on plane type and num
- populates fb->...[4] parameters for NV12
- igt helper function to convert RGB data to NV12
- updated drm_format to bpp to handle NV12
- updated fast copy blit function to deal NV12 subplanes
- made an update to few tests due to above changes
v1: Reference https://patchwork.freedesktop.org/patch/57590/
initially floated by Chandra Konduru
on Aug 20 2015 based on the IGT
framework available at that time.
v2: Rebased as per the current IGT framework/changes (me)
v3: lib fixes for nv12 rotation
additional helper functions added to cover
multiple plane testing
Signed-off-by: Chandra Konduru
Signed-off-by: Vidya Srinivas
Signed-off-by: Mahesh Kumar
---
lib/igt_draw.c | 2 +-
lib/igt_fb.c | 189 ---
lib/igt_fb.h | 14 ++-
lib/igt_kms.c| 50 ++-
lib/igt_kms.h| 2 +
lib/intel_batchbuffer.c | 14 +--
lib/intel_batchbuffer.h | 3 +-
lib/intel_reg.h | 1 +
lib/ioctl_wrappers.c | 9 ++
lib/ioctl_wrappers.h | 1 +
tests/kms_draw_crc.c | 2 +-
tests/kms_frontbuffer_tracking.c | 6 +-
tests/kms_render.c | 4 +-
tests/kms_rotation_crc.c | 8 +-
tests/prime_vgem.c | 2 +-
15 files changed, 254 insertions(+), 53 deletions(-)
diff --git a/lib/igt_draw.c b/lib/igt_draw.c
index 76ffb6c..8a7dbea 100644
--- a/lib/igt_draw.c
+++ b/lib/igt_draw.c
@@ -723,7 +723,7 @@ void igt_draw_rect_fb(int fd, drm_intel_bufmgr *bufmgr,
{
igt_draw_rect(fd, bufmgr, context, fb->gem_handle, fb->size, fb->stride,
method, rect_x, rect_y, rect_w, rect_h, color,
- igt_drm_format_to_bpp(fb->drm_format));
+ igt_drm_format_to_bpp(fb->drm_format, 0));
}
/**
diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index d4eaed7..71317fd 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -141,6 +141,31 @@ void igt_get_fb_tile_size(int fd, uint64_t tiling, int
fb_bpp,
}
}
+void igt_fb_calc_uv(struct igt_fb *fb)
+{
+ if (fb->drm_format != DRM_FORMAT_NV12)
+ return;
+
+ switch (fb->tiling) {
+ case LOCAL_DRM_FORMAT_MOD_NONE:
+ fb->uv_y_start = fb->height;
+ break;
+ case LOCAL_I915_FORMAT_MOD_X_TILED:
+ fb->uv_y_start = fb->height;
+ break;
+ case LOCAL_I915_FORMAT_MOD_Y_TILED:
+ case LOCAL_I915_FORMAT_MOD_Yf_TILED:
+ if (fb->height % 64)
+ fb->uv_y_start = (fb->height + 63) & ~63;
+ else
+ fb->uv_y_start = fb->height;
+ break;
+ default:
+ igt_assert(0);
+ }
+ fb->uv_offset = fb->uv_y_start * fb->stride;
+}
+
/**
* igt_calc_fb_size:
* @fd: the DRM file descriptor
@@ -154,7 +179,7 @@ void igt_get_fb_tile_size(int fd, uint64_t tiling, int
fb_bpp,
* This function returns valid stride and size values for a framebuffer with
the
* specified parameters.
*/
-void igt_calc_fb_size(int fd, int width, int height, int bpp, uint64_t tiling,
+void igt_calc_fb_size(int fd, int width, int height, int bpp, uint32_t format,
uint64_t tiling,
unsigned *size_ret, unsigned *stride_ret)
{
unsigned int tile_width, tile_height, stride, size;
@@ -178,12 +203,16 @@ void igt_calc_fb_size(int fd, int width, int height, int
bpp, uint64_t tiling,
for (stride = 512; stride < v; stride *= 2)
;
- v = stride * height;
+ /* planar formats height is 1.5x */
+ v = stride * (format == DRM_FORMAT_NV12 ? (height * 3) / 2 :
height);
for (size = 1024*1024; size < v; size *= 2)
;
} else {
stride = ALIGN(byte_width, tile_width);
- size = stride * ALIGN(height, tile_height);
+ size = stride * (format == DRM_FORMAT_NV12 ? ALIGN((height * 3)
/ 2, tile_height) :
+ ALIGN(height, tile_height));
+ if (format == DRM_FORMAT_NV12)
+ size = ALIGN(size, 256 * 1024);
}
*stride_ret = stride;
@@ -248,13 +277,13 @@ static int create_bo_for_fb(int fd, int width, int
height, uint32_t format,
unsigned *size_ret,
[Intel-gfx] [PATCH 02/14] drm/i915/skl+: refactore WM calculation for NV12
From: Mahesh Kumar
Current code calculates DDB for planar formats in such a way that we
store DDB of plane-0 in plane 1 & vice-versa.
In order to make this clean this patch refactors WM/DDB calculation for
NV12 planar formats.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 120 +++
3 files changed, 62 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1b5cf18..090832c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1848,7 +1848,7 @@ static inline bool skl_ddb_entry_equal(const struct
skl_ddb_entry *e1,
struct skl_ddb_allocation {
struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /*
packed/uv */
- struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
+ struct skl_ddb_entry uv_plane[I915_MAX_PIPES][I915_MAX_PLANES];
};
struct skl_ddb_values {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 160fded..f897580 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -510,6 +510,7 @@ struct intel_pipe_wm {
struct skl_plane_wm {
struct skl_wm_level wm[8];
struct skl_wm_level trans_wm;
+ bool is_nv12;
};
struct skl_pipe_wm {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 029487d..b09d81b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3990,9 +3990,9 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc
*intel_crtc,
static unsigned int
skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
const struct drm_plane_state *pstate,
-int y)
+const int plane)
{
- struct intel_plane *plane = to_intel_plane(pstate->plane);
+ struct intel_plane *intel_plane = to_intel_plane(pstate->plane);
struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
uint32_t data_rate;
uint32_t width = 0, height = 0;
@@ -4006,9 +4006,9 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc
*intel_crtc,
fb = pstate->fb;
format = fb->format->format;
- if (plane->id == PLANE_CURSOR)
+ if (intel_plane->id == PLANE_CURSOR)
return 0;
- if (y && format != DRM_FORMAT_NV12)
+ if (plane == 1 && format != DRM_FORMAT_NV12)
return 0;
/*
@@ -4019,19 +4019,14 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc
*intel_crtc,
width = drm_rect_width(&intel_pstate->base.src) >> 16;
height = drm_rect_height(&intel_pstate->base.src) >> 16;
- /* for planar format */
- if (format == DRM_FORMAT_NV12) {
- if (y) /* y-plane data rate */
- data_rate = width * height *
- fb->format->cpp[0];
- else/* uv-plane data rate */
- data_rate = (width / 2) * (height / 2) *
- fb->format->cpp[1];
- } else {
- /* for packed formats */
- data_rate = width * height * fb->format->cpp[0];
+ /* UV plane does 1/2 pixel sub-sampling */
+ if (plane == 1 && format == DRM_FORMAT_NV12) {
+ width /= 2;
+ height /= 2;
}
+ data_rate = width * height * fb->format->cpp[plane];
+
down_scale_amount = skl_plane_downscale_amount(cstate, intel_pstate);
return mul_round_up_u32_fixed16(data_rate, down_scale_amount);
@@ -4044,8 +4039,8 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc
*intel_crtc,
*/
static unsigned int
skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
-unsigned *plane_data_rate,
-unsigned *plane_y_data_rate)
+unsigned int *plane_data_rate,
+unsigned int *uv_plane_data_rate)
{
struct drm_crtc_state *cstate = &intel_cstate->base;
struct drm_atomic_state *state = cstate->state;
@@ -4061,17 +4056,16 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc
*intel_crtc,
enum plane_id plane_id = to_intel_plane(plane)->id;
unsigned int rate;
- /* packed/uv */
rate = skl_plane_relative_data_rate(intel_cstate,
pstate, 0);
plane_data_rate[plane_id] = rate;
total_data_rate += rate;
- /* y-plane */
+ /* uv-plane */
rate = skl_plane_relative_data_rate(intel_cstate,
pstate, 1);
- plane_y_data_rate[plane_id]
[Intel-gfx] [PATCH 03/14] drm/i915/skl+: add NV12 in skl_format_to_fourcc
From: Mahesh Kumar
Add support of recognizing DRM_FORMAT_NV12 from plane_format
register value.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/intel_display.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 45d6e57..36c2640 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2708,6 +2708,8 @@ static int skl_format_to_fourcc(int format, bool
rgb_order, bool alpha)
switch (format) {
case PLANE_CTL_FORMAT_RGB_565:
return DRM_FORMAT_RGB565;
+ case PLANE_CTL_FORMAT_NV12:
+ return DRM_FORMAT_NV12;
default:
case PLANE_CTL_FORMAT_XRGB_:
if (rgb_order) {
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 06/14] drm/i915/skl+: pass skl_wm_level struct to wm compute func
From: Mahesh Kumar
This will reduce number of arguments required to be pass in
skl_compute_plane_wm function.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/intel_pm.c | 18 +++---
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7b3160c..e931e4a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4499,9 +4499,7 @@ static int skl_compute_plane_wm(const struct
drm_i915_private *dev_priv,
uint16_t ddb_allocation,
int level,
const struct skl_wm_params *wp,
- uint16_t *out_blocks, /* out */
- uint8_t *out_lines, /* out */
- bool *enabled /* out */)
+ struct skl_wm_level *result /* out */)
{
const struct drm_plane_state *pstate = &intel_pstate->base;
uint32_t latency = dev_priv->wm.skl_latency[level];
@@ -4514,7 +4512,7 @@ static int skl_compute_plane_wm(const struct
drm_i915_private *dev_priv,
if (latency == 0 ||
!intel_wm_plane_visible(cstate, intel_pstate)) {
- *enabled = false;
+ result->plane_en = false;
return 0;
}
@@ -4569,7 +4567,7 @@ static int skl_compute_plane_wm(const struct
drm_i915_private *dev_priv,
}
if (res_blocks >= ddb_allocation || res_lines > 31) {
- *enabled = false;
+ result->plane_en = false;
/*
* If there are no valid level 0 watermarks, then we can't
@@ -4588,9 +4586,9 @@ static int skl_compute_plane_wm(const struct
drm_i915_private *dev_priv,
}
}
- *out_blocks = res_blocks;
- *out_lines = res_lines;
- *enabled = true;
+ result->plane_res_b = res_blocks;
+ result->plane_res_l = res_lines;
+ result->plane_en = true;
return 0;
}
@@ -4631,9 +4629,7 @@ static int skl_compute_plane_wm(const struct
drm_i915_private *dev_priv,
ddb_blocks,
level,
wm_params,
- &result->plane_res_b,
- &result->plane_res_l,
- &result->plane_en);
+ result);
if (ret)
return ret;
}
--
1.9.1
___
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[Intel-gfx] [PATCH 05/14] drm/i915/skl+: NV12 related changes for WM
From: Mahesh Kumar
NV12 require WM calculation for UV plane as well.
UV plane WM should also fulfill all the WM related restrictions.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 54
3 files changed, 45 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 090832c..e697ead 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1866,6 +1866,7 @@ struct skl_wm_level {
struct skl_wm_params {
bool x_tiled, y_tiled;
bool rc_surface;
+ bool is_nv12;
uint32_t width;
uint8_t cpp;
uint32_t plane_pixel_rate;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 4f98684..51ae058 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -509,6 +509,7 @@ struct intel_pipe_wm {
struct skl_plane_wm {
struct skl_wm_level wm[8];
+ struct skl_wm_level uv_wm[8];
struct skl_wm_level trans_wm;
bool is_nv12;
};
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ac4bba1..7b3160c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4398,7 +4398,7 @@ static uint_fixed_16_16_t skl_wm_method2(uint32_t
pixel_rate,
skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
struct intel_crtc_state *cstate,
const struct intel_plane_state *intel_pstate,
- struct skl_wm_params *wp)
+ struct skl_wm_params *wp, int plane_num)
{
struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane);
const struct drm_plane_state *pstate = &intel_pstate->base;
@@ -4411,6 +4411,12 @@ static uint_fixed_16_16_t skl_wm_method2(uint32_t
pixel_rate,
if (!intel_wm_plane_visible(cstate, intel_pstate))
return 0;
+ /* only NV12 format has two planes */
+ if (plane_num == 1 && fb->format->format != DRM_FORMAT_NV12) {
+ DRM_DEBUG_KMS("Non NV12 format have single plane\n");
+ return -EINVAL;
+ }
+
wp->y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
@@ -4418,6 +4424,7 @@ static uint_fixed_16_16_t skl_wm_method2(uint32_t
pixel_rate,
wp->x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
wp->rc_surface = fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
+ wp->is_nv12 = fb->format->format == DRM_FORMAT_NV12;
if (plane->id == PLANE_CURSOR) {
wp->width = intel_pstate->base.crtc_w;
@@ -4430,7 +4437,10 @@ static uint_fixed_16_16_t skl_wm_method2(uint32_t
pixel_rate,
wp->width = drm_rect_width(&intel_pstate->base.src) >> 16;
}
- wp->cpp = fb->format->cpp[0];
+ if (plane_num == 1 && wp->is_nv12)
+ wp->width /= 2;
+
+ wp->cpp = fb->format->cpp[plane_num];
wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
intel_pstate);
@@ -4591,7 +4601,8 @@ static int skl_compute_plane_wm(const struct
drm_i915_private *dev_priv,
struct intel_crtc_state *cstate,
const struct intel_plane_state *intel_pstate,
const struct skl_wm_params *wm_params,
- struct skl_plane_wm *wm)
+ struct skl_plane_wm *wm,
+ int plane_num)
{
struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
struct drm_plane *plane = intel_pstate->base.plane;
@@ -4599,15 +4610,20 @@ static int skl_compute_plane_wm(const struct
drm_i915_private *dev_priv,
uint16_t ddb_blocks;
enum pipe pipe = intel_crtc->pipe;
int level, max_level = ilk_wm_max_level(dev_priv);
+ enum plane_id plane_id = intel_plane->id;
int ret;
if (WARN_ON(!intel_pstate->base.fb))
return -EINVAL;
- ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][intel_plane->id]);
+ if (plane_num == 0)
+ ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);
+ else
+ ddb_blocks = skl_ddb_entry_size(&ddb->uv_plane[pipe][plane_id]);
for (level = 0; level <= max_level; level++) {
- struct skl_wm_level *result = &wm->wm[level];
+ struct skl_wm_level *result = plane_num ? &wm->uv_wm[level] :
+ &wm->wm[level];
ret = skl_compute_plane_wm(dev_priv,
[Intel-gfx] [PATCH 01/14] drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
From: Mahesh Kumar
skl_wm_values struct contains values os pipe/plane DDB only.
so rename it for better readability of code.
s/skl_wm_values/skl_ddb_values
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
drivers/gpu/drm/i915/intel_drv.h | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 12 ++--
3 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 770305b..1b5cf18 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1851,7 +1851,7 @@ struct skl_ddb_allocation {
struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
};
-struct skl_wm_values {
+struct skl_ddb_values {
unsigned dirty_pipes;
struct skl_ddb_allocation ddb;
};
@@ -2511,7 +2511,7 @@ struct drm_i915_private {
/* current hardware state */
union {
struct ilk_wm_values hw;
- struct skl_wm_values skl_hw;
+ struct skl_ddb_values skl_hw;
struct vlv_wm_values vlv;
struct g4x_wm_values g4x;
};
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0cab667..160fded 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -396,7 +396,7 @@ struct intel_atomic_state {
bool skip_intermediate_wm;
/* Gen9+ only */
- struct skl_wm_values wm_results;
+ struct skl_ddb_values wm_results;
struct i915_sw_fence commit_ready;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9d0ca26..029487d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4981,8 +4981,8 @@ static int skl_update_pipe_wm(struct drm_crtc_state
*cstate,
}
static void
-skl_copy_wm_for_pipe(struct skl_wm_values *dst,
-struct skl_wm_values *src,
+skl_copy_wm_for_pipe(struct skl_ddb_values *dst,
+struct skl_ddb_values *src,
enum pipe pipe)
{
memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
@@ -5034,7 +5034,7 @@ static int skl_update_pipe_wm(struct drm_crtc_state
*cstate,
struct drm_crtc *crtc;
struct drm_crtc_state *cstate;
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
- struct skl_wm_values *results = &intel_state->wm_results;
+ struct skl_ddb_values *results = &intel_state->wm_results;
struct drm_device *dev = state->dev;
struct skl_pipe_wm *pipe_wm;
bool changed = false;
@@ -5136,8 +5136,8 @@ static void skl_initial_wm(struct intel_atomic_state
*state,
struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
struct drm_device *dev = intel_crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- struct skl_wm_values *results = &state->wm_results;
- struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
+ struct skl_ddb_values *results = &state->wm_results;
+ struct skl_ddb_values *hw_vals = &dev_priv->wm.skl_hw;
enum pipe pipe = intel_crtc->pipe;
if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
@@ -5280,7 +5280,7 @@ void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
void skl_wm_get_hw_state(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
+ struct skl_ddb_values *hw = &dev_priv->wm.skl_hw;
struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
struct drm_crtc *crtc;
struct intel_crtc *intel_crtc;
--
1.9.1
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[Intel-gfx] [PATCH 04/14] drm/i915/skl+: support varification of DDB HW state for NV12
From: Mahesh Kumar
NV12 formats have two registers for DDB. verify both the registers for
NV12 during verify_wm_state.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 50
3 files changed, 42 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 36c2640..a10bbe8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2703,7 +2703,7 @@ static int i9xx_format_to_fourcc(int format)
}
}
-static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
+int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
{
switch (format) {
case PLANE_CTL_FORMAT_RGB_565:
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f897580..4f98684 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1502,6 +1502,7 @@ u32 skl_plane_stride(const struct drm_framebuffer *fb,
int plane,
unsigned int rotation);
int skl_check_plane_surface(struct intel_plane_state *plane_state);
int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
+int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
/* intel_csr.c */
void intel_csr_ucode_init(struct drm_i915_private *);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b09d81b..ac4bba1 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3807,6 +3807,43 @@ static void skl_ddb_entry_init_from_hw(struct
skl_ddb_entry *entry, u32 reg)
entry->end += 1;
}
+static void
+skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
+ const enum pipe pipe,
+ const enum plane_id plane_id,
+ struct skl_ddb_allocation *ddb /* out */)
+{
+ u32 val, val2 = 0;
+ int fourcc, pixel_format;
+
+ /* Cursor doesn't support NV12, so no extra calculation needed */
+ if (plane_id == PLANE_CURSOR) {
+ val = I915_READ(CUR_BUF_CFG(pipe));
+ skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
+ return;
+ }
+
+ val = I915_READ(PLANE_CTL(pipe, plane_id));
+
+ /* No DDB allocated for disabled planes */
+ if (!(val & PLANE_CTL_ENABLE))
+ return;
+
+ pixel_format = val & PLANE_CTL_FORMAT_MASK;
+ fourcc = skl_format_to_fourcc(pixel_format,
+ val & PLANE_CTL_ORDER_RGBX,
+ val & PLANE_CTL_ALPHA_MASK);
+
+ val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
+ val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
+
+ if (fourcc == DRM_FORMAT_NV12) {
+ skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val2);
+ skl_ddb_entry_init_from_hw(&ddb->uv_plane[pipe][plane_id], val);
+ } else
+ skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
+}
+
void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
struct skl_ddb_allocation *ddb /* out */)
{
@@ -3823,16 +3860,9 @@ void skl_ddb_get_hw_state(struct drm_i915_private
*dev_priv,
if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
continue;
- for_each_plane_id_on_crtc(crtc, plane_id) {
- u32 val;
-
- if (plane_id != PLANE_CURSOR)
- val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
- else
- val = I915_READ(CUR_BUF_CFG(pipe));
-
- skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id],
val);
- }
+ for_each_plane_id_on_crtc(crtc, plane_id)
+ skl_ddb_get_hw_plane_state(dev_priv, pipe,
+ plane_id, ddb);
intel_display_power_put(dev_priv, power_domain);
}
--
1.9.1
___
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[Intel-gfx] [PATCH 00/14] Adding NV12 support
This patch series is adding NV12 support for Broxton display after rebasing on latest drm-tip. Initial series of the patches can be found here: https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html Previous revision history: The first version of patches were reviewed when floated by Chandra in 2015 but currently there was a design change with respect to - the way fb offset is handled - the way rotation is handled Current NV12 patch series has been ported as per the current changes on drm-tip Review comments from Ville (12th June 2017) have been addressed Review comments from Clinton A Taylor (7th July 2017) have been addressed Review comments from Clinton A Taylor (10th July 2017) have been addressed. Had missed out tested-by/reviewed-by in the patches. Fixed that error in this series. Review comments from Ville (11th July 2017) addressed. Review comments from Paauwe, Bob (29th July 2017) addressed. Update from last rev (28 Aug 2017) Rebased the series. Tested with IGT for rotation, sprite and tiling combinations. IGT Links: https://patchwork.kernel.org/patch/9995943/ https://patchwork.kernel.org/patch/9995945/ Patches are tested (dependent on) watermark necessary changes https://patchwork.freedesktop.org/series/31640/ Chandra Konduru (6): drm/i915: Set scaler mode for NV12 drm/i915: Update format_is_yuv() to include NV12 drm/i915: Upscale scaler max scale for NV12 drm/i915: Add NV12 as supported format for primary plane drm/i915: Add NV12 as supported format for sprite plane drm/i915: Add NV12 support to intel_framebuffer_init Mahesh Kumar (8): drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values drm/i915/skl+: refactore WM calculation for NV12 drm/i915/skl+: add NV12 in skl_format_to_fourcc drm/i915/skl+: support varification of DDB HW state for NV12 drm/i915/skl+: NV12 related changes for WM drm/i915/skl+: pass skl_wm_level struct to wm compute func drm/i915/skl+: make sure higher latency level has higher wm value drm/i915/skl+: nv12 workaround disable WM level 1-7 drivers/gpu/drm/i915/i915_drv.h | 7 +- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_atomic.c | 8 +- drivers/gpu/drm/i915/intel_display.c | 71 +++-- drivers/gpu/drm/i915/intel_drv.h | 8 +- drivers/gpu/drm/i915/intel_pm.c | 275 +++ drivers/gpu/drm/i915/intel_sprite.c | 34 - 7 files changed, 284 insertions(+), 120 deletions(-) -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 08/14] drm/i915/skl+: nv12 workaround disable WM level 1-7
From: Mahesh Kumar
Display Workaround #0826 (SKL:ALL BXT:ALL) & #1059(CNL:A)
Hardware sometimes fails to wake memory from pkg C states fetching the
last few lines of planar YUV 420 (NV12) planes. This causes
intermittent underflow and corruption.
WA: Disable package C states or do not enable latency levels 1 through 7
(WM1 - WM7) on NV12 planes.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/intel_pm.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c99639b..7117011 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4596,6 +4596,17 @@ static int skl_compute_plane_wm(const struct
drm_i915_private *dev_priv,
}
}
+ /*
+* Display WA #826 (SKL:ALL, BXT:ALL) & #1059 (CNL:A)
+* disable wm level 1-7 on NV12 planes
+*/
+ if (wp->is_nv12 && level && (IS_SKYLAKE(dev_priv) ||
+ IS_BROXTON(dev_priv) ||
+ IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))) {
+ result->plane_en = false;
+ return 0;
+ }
+
result->plane_res_b = res_blocks;
result->plane_res_l = res_lines;
result->plane_en = true;
--
1.9.1
___
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[Intel-gfx] [PATCH 07/14] drm/i915/skl+: make sure higher latency level has higher wm value
From: Mahesh Kumar
DDB allocation optimization algorithm require/assumes ddb allocation for
any memory C-state level DDB value to be as high as level below.
Render decompression require level WM to be as high as wm level-0.
This patch fulfils both the requirements.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/intel_pm.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e931e4a..c99639b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4499,6 +4499,7 @@ static int skl_compute_plane_wm(const struct
drm_i915_private *dev_priv,
uint16_t ddb_allocation,
int level,
const struct skl_wm_params *wp,
+ const struct skl_wm_level *result_prev,
struct skl_wm_level *result /* out */)
{
const struct drm_plane_state *pstate = &intel_pstate->base;
@@ -4564,6 +4565,15 @@ static int skl_compute_plane_wm(const struct
drm_i915_private *dev_priv,
} else {
res_blocks++;
}
+
+ /*
+* Make sure result blocks for higher latency levels are atleast
+* as high as level below.
+* Assumption in DDB algorithm optimization for special cases.
+* Also covers Display WA #1125 for RC.
+*/
+ if (result_prev->plane_res_b > res_blocks)
+ res_blocks = result_prev->plane_res_b;
}
if (res_blocks >= ddb_allocation || res_lines > 31) {
@@ -4622,6 +4632,13 @@ static int skl_compute_plane_wm(const struct
drm_i915_private *dev_priv,
for (level = 0; level <= max_level; level++) {
struct skl_wm_level *result = plane_num ? &wm->uv_wm[level] :
&wm->wm[level];
+ struct skl_wm_level *result_prev;
+
+ if (level)
+ result_prev = plane_num ? &wm->uv_wm[level - 1] :
+ &wm->wm[level - 1];
+ else
+ result_prev = plane_num ? &wm->uv_wm[0] : &wm->wm[0];
ret = skl_compute_plane_wm(dev_priv,
cstate,
@@ -4629,6 +4646,7 @@ static int skl_compute_plane_wm(const struct
drm_i915_private *dev_priv,
ddb_blocks,
level,
wm_params,
+ result_prev,
result);
if (ret)
return ret;
--
1.9.1
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[Intel-gfx] [PATCH 10/14] drm/i915: Update format_is_yuv() to include NV12
From: Chandra Konduru
This patch adds NV12 to format_is_yuv() function
for sprite planes.
v2:
-Use intel_ prefix for format_is_yuv (Ville)
v3: Rebased (me)
v4: Rebased and addressed review comments from Clinton A Taylor.
"static function in intel_sprite.c is not available
to the primary plane functions".
Changed commit message - function modified for
sprite planes.
v5: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.
v6: Rebased (me)
v7: Rebased (me)
v8: Rebased (me)
Tested-by: Clinton Taylor
Reviewed-by: Clinton Taylor
Signed-off-by: Chandra Konduru
Signed-off-by: Nabendu Maiti
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/intel_sprite.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index b0d6e3e..091bb42 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -42,13 +42,14 @@
#include "i915_drv.h"
static bool
-format_is_yuv(uint32_t format)
+intel_format_is_yuv(uint32_t format)
{
switch (format) {
case DRM_FORMAT_YUYV:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_YVYU:
+ case DRM_FORMAT_NV12:
return true;
default:
return false;
@@ -330,7 +331,7 @@ void intel_pipe_update_end(struct intel_crtc_state
*new_crtc_state)
enum plane_id plane_id = plane->id;
/* Seems RGB data bypasses the CSC always */
- if (!format_is_yuv(format))
+ if (!intel_format_is_yuv(format))
return;
/*
@@ -894,7 +895,7 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state
*crtc_state,
src_y = src->y1 >> 16;
src_h = drm_rect_height(src) >> 16;
- if (format_is_yuv(fb->format->format)) {
+ if (intel_format_is_yuv(fb->format->format)) {
src_x &= ~1;
src_w &= ~1;
--
1.9.1
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[Intel-gfx] [PATCH 09/14] drm/i915: Set scaler mode for NV12
From: Chandra Konduru
This patch sets appropriate scaler mode for NV12 format.
In this mode, skylake scaler does either chroma-upsampling or
chroma-upsampling and resolution scaling
v2: Review comments from Ville addressed
NV12 case to be checked first for setting
the scaler
v3: Rebased (me)
v4: Rebased (me)
v5: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.
v6: Rebased (me)
v7: Rebased (me)
v8: Rebased (me)
Restricting the NV12 change for scaler to BXT and KBL
in this series.
Tested-by: Clinton Taylor
Reviewed-by: Clinton Taylor
Signed-off-by: Chandra Konduru
Signed-off-by: Nabendu Maiti
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_atomic.c | 8 +++-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 50e65c9..976b501 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6607,6 +6607,7 @@ enum {
#define PS_SCALER_MODE_MASK (3 << 28)
#define PS_SCALER_MODE_DYN (0 << 28)
#define PS_SCALER_MODE_HQ (1 << 28)
+#define PS_SCALER_MODE_NV12 (2 << 28)
#define PS_PLANE_SEL_MASK (7 << 25)
#define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
#define PS_FILTER_MASK (3 << 23)
diff --git a/drivers/gpu/drm/i915/intel_atomic.c
b/drivers/gpu/drm/i915/intel_atomic.c
index 36d4e63..606b5e3 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -325,7 +325,13 @@ int intel_atomic_setup_scalers(struct drm_i915_private
*dev_priv,
}
/* set scaler mode */
- if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
+ if ((IS_BROXTON(dev_priv) || IS_KABYLAKE(dev_priv)) &&
+ plane_state && plane_state->base.fb &&
+ plane_state->base.fb->format->format ==
+ DRM_FORMAT_NV12) {
+ scaler_state->scalers[*scaler_id].mode =
+ PS_SCALER_MODE_NV12;
+ } else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
scaler_state->scalers[*scaler_id].mode = 0;
} else if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C)
{
/*
--
1.9.1
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[Intel-gfx] [PATCH 11/14] drm/i915: Upscale scaler max scale for NV12
From: Chandra Konduru
This patch updates scaler max limit support for NV12
v2: Rebased (me)
v3: Rebased (me)
v4: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.
v5: Addressed review comments from Ville and rebased
- calculation of max_scale to be made
less convoluted by splitting it up a bit
- Indentation errors to be fixed in the series
v6: Rebased (me)
Fixed review comments from Paauwe, Bob J
Previous version, where a split of calculation
was done, was wrong. Fixed that issue here.
v7: Rebased (me)
v8: Rebased (me)
Tested-by: Clinton Taylor
Reviewed-by: Clinton Taylor
Signed-off-by: Chandra Konduru
Signed-off-by: Nabendu Maiti
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/intel_display.c | 33 +++--
drivers/gpu/drm/i915/intel_drv.h | 3 ++-
drivers/gpu/drm/i915/intel_sprite.c | 3 ++-
3 files changed, 27 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index a10bbe8..f71a704 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3472,6 +3472,8 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
case DRM_FORMAT_VYUY:
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
+ case DRM_FORMAT_NV12:
+ return PLANE_CTL_FORMAT_NV12;
default:
MISSING_CASE(pixel_format);
}
@@ -4727,7 +4729,8 @@ static void cpt_verify_modeset(struct drm_device *dev,
int pipe)
static int
skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
unsigned int scaler_user, int *scaler_id,
- int src_w, int src_h, int dst_w, int dst_h)
+ int src_w, int src_h, int dst_w, int dst_h,
+ uint32_t pixel_format)
{
struct intel_crtc_scaler_state *scaler_state =
&crtc_state->scaler_state;
@@ -4743,7 +4746,8 @@ static void cpt_verify_modeset(struct drm_device *dev,
int pipe)
* the 90/270 degree plane rotation cases (to match the
* GTT mapping), hence no need to account for rotation here.
*/
- need_scaling = src_w != dst_w || src_h != dst_h;
+ need_scaling = src_w != dst_w || src_h != dst_h ||
+ (pixel_format == DRM_FORMAT_NV12);
if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
need_scaling = true;
@@ -4822,7 +4826,7 @@ int skl_update_scaler_crtc(struct intel_crtc_state *state)
return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
&state->scaler_state.scaler_id,
state->pipe_src_w, state->pipe_src_h,
- adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
+ adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay, 0);
}
/**
@@ -4852,7 +4856,8 @@ static int skl_update_scaler_plane(struct
intel_crtc_state *crtc_state,
drm_rect_width(&plane_state->base.src) >> 16,
drm_rect_height(&plane_state->base.src) >> 16,
drm_rect_width(&plane_state->base.dst),
- drm_rect_height(&plane_state->base.dst));
+ drm_rect_height(&plane_state->base.dst),
+ fb ? fb->format->format : 0);
if (ret || plane_state->scaler_id < 0)
return ret;
@@ -4878,6 +4883,7 @@ static int skl_update_scaler_plane(struct
intel_crtc_state *crtc_state,
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
+ case DRM_FORMAT_NV12:
break;
default:
DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format
0x%x\n",
@@ -12799,11 +12805,12 @@ static void add_rps_boost_after_vblank(struct
drm_crtc *crtc,
}
int
-skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state
*crtc_state)
+skl_max_scale(struct intel_crtc *intel_crtc,
+ struct intel_crtc_state *crtc_state, uint32_t pixel_format)
{
struct drm_i915_private *dev_priv;
- int max_scale;
- int crtc_clock, max_dotclk;
+ int max_scale, mult;
+ int crtc_clock, max_dotclk, tmpclk1, tmpclk2;
if (!intel_crtc || !crtc_state->base.enable)
return DRM_PLANE_HELPER_NO_SCALING;
@@ -12825,8 +12832,10 @@ static void add_rps_boost_after_vblank(struct drm_crtc
*crtc,
*or
*cdclk/crtc_clock
*/
- max_scale = min((1 << 16) * 3 - 1,
- (1 << 8) * ((max_dotclk << 8) / crtc_clock));
+ mult = pixel_format == DRM_FORMAT_NV12 ? 2 : 3;
+ tmpclk1 = (1 << 16) * mult - 1;
+ tmpclk2 = (1 << 8)
Re: [Intel-gfx] [PATCH] drm/i915: Use execlists_num_ports instead of size of array
Quoting Mika Kuoppala (2017-10-10 12:48:57)
> There is function to tell how many ports we have, so use it.
> We still have direct relationship with array size and port count,
> so no harm was done.
>
> Fixes: 76e70087d360 ("drm/i915: Make execlist port count variable")
> Cc: Mika Kuoppala
> Cc: Chris Wilson
> Signed-off-by: Mika Kuoppala
I had a sweepstake on how long that ARRAY_SIZE would last.
Reviewed-by: Chris Wilson
-Chris
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[Intel-gfx] [PATCH 12/14] drm/i915: Add NV12 as supported format for primary plane
From: Chandra Konduru
This patch adds NV12 to list of supported formats for
primary plane
v2: Rebased (Chandra Konduru)
v3: Rebased (me)
v4: Review comments by Ville addressed
Removed the skl_primary_formats_with_nv12 and
added NV12 case in existing skl_primary_formats
v5: Rebased (me)
v6: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.
v7: Review comments by Ville addressed
Restricting the NV12 for BXT and on PIPE A and B
Rebased (me)
v8: Rebased (me)
Modified restricting the NV12 support for both BXT and KBL.
Tested-by: Clinton Taylor
Reviewed-by: Clinton Taylor
Signed-off-by: Chandra Konduru
Signed-off-by: Nabendu Maiti
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/intel_display.c | 26 --
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index f71a704..e551f59 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -106,6 +106,22 @@
DRM_FORMAT_MOD_INVALID
};
+static const uint32_t nv12_primary_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_NV12,
+};
+
/* Cursor formats */
static const uint32_t intel_cursor_formats[] = {
DRM_FORMAT_ARGB,
@@ -13256,8 +13272,14 @@ static bool
intel_cursor_plane_format_mod_supported(struct drm_plane *plane,
primary->update_plane = skylake_update_primary_plane;
primary->disable_plane = skylake_disable_primary_plane;
} else if (INTEL_GEN(dev_priv) >= 9) {
- intel_primary_formats = skl_primary_formats;
- num_formats = ARRAY_SIZE(skl_primary_formats);
+ if ((IS_BROXTON(dev_priv) || IS_KABYLAKE(dev_priv)) &&
+ ((pipe == PIPE_A || pipe == PIPE_B))) {
+ intel_primary_formats = nv12_primary_formats;
+ num_formats = ARRAY_SIZE(nv12_primary_formats);
+ } else {
+ intel_primary_formats = skl_primary_formats;
+ num_formats = ARRAY_SIZE(skl_primary_formats);
+ }
if (pipe < PIPE_C)
modifiers = skl_format_modifiers_ccs;
else
--
1.9.1
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[Intel-gfx] [PATCH 14/14] drm/i915: Add NV12 support to intel_framebuffer_init
From: Chandra Konduru
This patch adds NV12 as supported format
to intel_framebuffer_init and performs various checks.
v2:
-Fix an issue in checks added (Chandra Konduru)
v3: rebased (me)
v4: Review comments by Ville addressed
Added platform check for NV12 in intel_framebuffer_init
Removed offset checks for NV12 case
v5: Addressed review comments by Clinton A Taylor
This NV12 support only correctly works on SKL.
Plane color space conversion is different on GLK and later platforms
causing the colors to display incorrectly.
Ville's plane color space property patch series
in review will fix this issue.
- Restricted the NV12 case in intel_framebuffer_init to
SKL and BXT only.
v6: Rebased (me)
v7: Addressed review comments by Ville
Restricting the NV12 to BXT for now.
v8: Rebased (me)
Restricting the NV12 changes to BXT and KBL for now.
Tested-by: Clinton Taylor
Reviewed-by: Clinton Taylor
Signed-off-by: Chandra Konduru
Signed-off-by: Nabendu Maiti
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/intel_display.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index e551f59..f66a73e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14071,6 +14071,14 @@ static int intel_framebuffer_init(struct
intel_framebuffer *intel_fb,
goto err;
}
break;
+ case DRM_FORMAT_NV12:
+ if (!IS_BROXTON(dev_priv) && !IS_KABYLAKE(dev_priv)) {
+ DRM_DEBUG_KMS("unsupported pixel format: %s\n",
+ drm_get_format_name(mode_cmd->pixel_format,
+ &format_name));
+ goto err;
+ }
+ break;
default:
DRM_DEBUG_KMS("unsupported pixel format: %s\n",
drm_get_format_name(mode_cmd->pixel_format,
&format_name));
--
1.9.1
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[Intel-gfx] [PATCH 13/14] drm/i915: Add NV12 as supported format for sprite plane
From: Chandra Konduru
This patch adds NV12 to list of supported formats for sprite plane.
v2: Rebased (me)
v3: Review comments by Ville addressed
- Removed skl_plane_formats_with_nv12 and added
NV12 case in existing skl_plane_formats
- Added the 10bpc RGB formats
v4: Addressed review comments from Clinton A Taylor
"Why are we adding 10 bit RGB formats with the NV12 series patches?
Trying to set XR30 or AB30 results in error returned even though
the modes are advertised for the planes"
- Removed 10bit RGB formats added previously with NV12 series
v5: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.
Addressed review comments from Clinton A Taylor
"Why are we adding 10 bit RGB formats with the NV12 series patches?
Trying to set XR30 or AB30 results in error returned even though
the modes are advertised for the planes"
- Previous version has 10bit RGB format removed from VLV formats
by mistake. Fixing that in this version.
Removed 10bit RGB formats added previously with NV12 series
for SKL.
v6: Addressed review comments by Ville
Restricting the NV12 to BXT and PIPE A and B
v7: Rebased (me)
v8: Rebased (me)
Restricting NV12 changes to BXT and KBL
Restricting NV12 changes for plane 0 (overlay)
Tested-by: Clinton Taylor
Reviewed-by: Clinton Taylor
Signed-off-by: Chandra Konduru
Signed-off-by: Nabendu Maiti
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/intel_sprite.c | 24 +---
1 file changed, 21 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 6f98bc5..7e9cfe1 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1196,6 +1196,19 @@ static bool
intel_sprite_plane_format_mod_supported(struct drm_plane *plane,
.format_mod_supported = intel_sprite_plane_format_mod_supported,
};
+static uint32_t nv12_plane_formats[] = {
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_NV12,
+};
+
struct intel_plane *
intel_sprite_plane_create(struct drm_i915_private *dev_priv,
enum pipe pipe, int plane)
@@ -1238,9 +1251,14 @@ struct intel_plane *
intel_plane->update_plane = skl_update_plane;
intel_plane->disable_plane = skl_disable_plane;
-
- plane_formats = skl_plane_formats;
- num_plane_formats = ARRAY_SIZE(skl_plane_formats);
+ if ((IS_BROXTON(dev_priv) || IS_KABYLAKE(dev_priv)) &&
+ (pipe == PIPE_A || pipe == PIPE_B) && plane == 0) {
+ plane_formats = nv12_plane_formats;
+ num_plane_formats = ARRAY_SIZE(nv12_plane_formats);
+ } else {
+ plane_formats = skl_plane_formats;
+ num_plane_formats = ARRAY_SIZE(skl_plane_formats);
+ }
modifiers = skl_plane_format_modifiers;
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
intel_plane->can_scale = false;
--
1.9.1
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[Intel-gfx] [PATCH 4/9] drm/i915: Inline the required bits of intel_ddi_post_disable() into intel_ddi_fdi_post_disable()
From: Ville Syrjälä To untangle the mess that is intel_ddi_post_disable() move the the bits needed by FDI into intel_ddi_fdi_post_disable(). This way we can stop worrying about FDI in intel_ddi_post_disable(). Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_ddi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index e4d1d934231b..7187aea75697 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -2349,7 +2349,8 @@ void intel_ddi_fdi_post_disable(struct intel_encoder *encoder, val &= ~FDI_RX_ENABLE; I915_WRITE(FDI_RX_CTL(PIPE_A), val); - intel_ddi_post_disable(encoder, old_crtc_state, old_conn_state); + intel_disable_ddi_buf(encoder); + intel_ddi_clk_disable(encoder); val = I915_READ(FDI_RX_MISC(PIPE_A)); val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); -- 2.13.6 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 9/9] drm/i915: Split intel_enable_ddi() into DP and HDMI variants
From: Ville Syrjälä
Untangle intel_enable_ddi() by splitting it into DP and HDMI specific
variants.
v2: Keep using intel_ddi_get_encoder_port() for now
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_ddi.c | 86 +++-
1 file changed, 49 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 49cf8d9d2bc1..18bf06c7e43f 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2369,45 +2369,57 @@ void intel_ddi_fdi_post_disable(struct intel_encoder
*encoder,
I915_WRITE(FDI_RX_CTL(PIPE_A), val);
}
-static void intel_enable_ddi(struct intel_encoder *intel_encoder,
-const struct intel_crtc_state *pipe_config,
+static void intel_enable_ddi_dp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+ enum port port = intel_ddi_get_encoder_port(encoder);
+
+ if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
+ intel_dp_stop_link_train(intel_dp);
+
+ intel_edp_backlight_on(crtc_state, conn_state);
+ intel_psr_enable(intel_dp, crtc_state);
+ intel_edp_drrs_enable(intel_dp, crtc_state);
+
+ if (crtc_state->has_audio)
+ intel_audio_codec_enable(encoder, crtc_state, conn_state);
+}
+
+static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
+ enum port port = intel_ddi_get_encoder_port(encoder);
+
+ intel_hdmi_handle_sink_scrambling(encoder,
+ conn_state->connector,
+
crtc_state->hdmi_high_tmds_clock_ratio,
+ crtc_state->hdmi_scrambling);
+
+ /* In HDMI/DVI mode, the port width, and swing/emphasis values
+* are ignored so nothing special needs to be done besides
+* enabling the port.
+*/
+ I915_WRITE(DDI_BUF_CTL(port),
+ dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
+
+ if (crtc_state->has_audio)
+ intel_audio_codec_enable(encoder, crtc_state, conn_state);
+}
+
+static void intel_enable_ddi(struct intel_encoder *encoder,
+const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
{
- struct drm_encoder *encoder = &intel_encoder->base;
- struct drm_i915_private *dev_priv = to_i915(encoder->dev);
- enum port port = intel_ddi_get_encoder_port(intel_encoder);
- int type = intel_encoder->type;
-
- if (type == INTEL_OUTPUT_HDMI) {
- struct intel_digital_port *intel_dig_port =
- enc_to_dig_port(encoder);
- bool clock_ratio = pipe_config->hdmi_high_tmds_clock_ratio;
- bool scrambling = pipe_config->hdmi_scrambling;
-
- intel_hdmi_handle_sink_scrambling(intel_encoder,
- conn_state->connector,
- clock_ratio, scrambling);
-
- /* In HDMI/DVI mode, the port width, and swing/emphasis values
-* are ignored so nothing special needs to be done besides
-* enabling the port.
-*/
- I915_WRITE(DDI_BUF_CTL(port),
- intel_dig_port->saved_port_bits |
- DDI_BUF_CTL_ENABLE);
- } else if (type == INTEL_OUTPUT_EDP) {
- struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
- if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
- intel_dp_stop_link_train(intel_dp);
-
- intel_edp_backlight_on(pipe_config, conn_state);
- intel_psr_enable(intel_dp, pipe_config);
- intel_edp_drrs_enable(intel_dp, pipe_config);
- }
-
- if (pipe_config->has_audio)
- intel_audio_codec_enable(intel_encoder, pipe_config,
conn_state);
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+ intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
+ else
+ intel_enable_ddi_dp(encoder, crtc_state, conn_state);
}
static void intel_disable_ddi_dp(struct intel_encoder *encoder,
--
2.13.6
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[Intel-gfx] [PATCH v2 2/9] drm/i915: Extract intel_ddi_clk_disable()
From: Ville Syrjälä
Pull the code to disable the port clock into a function. We already have
the intel_ddi_clk_select() counterpart.
v2: Keep using intel_ddi_get_encoder_port() for now (Chris)
Cc: Chris Wilson
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_ddi.c | 24
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index b307b6fe1ce3..1cc61ba48e3a 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2141,6 +2141,21 @@ static void intel_ddi_clk_select(struct intel_encoder
*encoder,
}
}
+static void intel_ddi_clk_disable(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum port port = intel_ddi_get_encoder_port(encoder);
+
+ if (IS_CANNONLAKE(dev_priv))
+ I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
+ DPCLKA_CFGCR0_DDI_CLK_OFF(port));
+ else if (IS_GEN9_BC(dev_priv))
+ I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
+ DPLL_CTRL2_DDI_CLK_OFF(port));
+ else if (INTEL_GEN(dev_priv) < 9)
+ I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
+}
+
static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
int link_rate, uint32_t lane_count,
struct intel_shared_dpll *pll,
@@ -2301,14 +2316,7 @@ static void intel_ddi_post_disable(struct intel_encoder
*intel_encoder,
if (dig_port)
intel_display_power_put(dev_priv,
dig_port->ddi_io_power_domain);
- if (IS_CANNONLAKE(dev_priv))
- I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
- DPCLKA_CFGCR0_DDI_CLK_OFF(port));
- else if (IS_GEN9_BC(dev_priv))
- I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
- DPLL_CTRL2_DDI_CLK_OFF(port)));
- else if (INTEL_GEN(dev_priv) < 9)
- I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
+ intel_ddi_clk_disable(intel_encoder);
if (type == INTEL_OUTPUT_HDMI) {
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
--
2.13.6
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[Intel-gfx] [PATCH v2 1/9] drm/i915: Dump 'output_types' in crtc state dump
From: Ville Syrjälä
To make it easier to debug things let's dump the output types bitmask in
the crtc state dump. And to make life that much better, let's pretty
print it as a a human reaadable string as well.
v2: Have the caller pass in the buffer (Chris)
#undef OUTPUT_TYPE (Jani)
Cc: Chris Wilson
Cc: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 51
1 file changed, 51 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 45d6e57fbe89..4938c23a3fc1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10674,6 +10674,52 @@ intel_dump_m_n_config(struct intel_crtc_state
*pipe_config, char *id,
m_n->link_m, m_n->link_n, m_n->tu);
}
+#define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
+
+static const char * const output_type_str[] = {
+ OUTPUT_TYPE(UNUSED),
+ OUTPUT_TYPE(ANALOG),
+ OUTPUT_TYPE(DVO),
+ OUTPUT_TYPE(SDVO),
+ OUTPUT_TYPE(LVDS),
+ OUTPUT_TYPE(TVOUT),
+ OUTPUT_TYPE(HDMI),
+ OUTPUT_TYPE(DP),
+ OUTPUT_TYPE(EDP),
+ OUTPUT_TYPE(DSI),
+ OUTPUT_TYPE(UNKNOWN),
+ OUTPUT_TYPE(DP_MST),
+};
+
+#undef OUTPUT_TYPE
+
+static void snprintf_output_types(char *buf, size_t len,
+ unsigned int output_types)
+{
+ char *str = buf;
+ int i;
+
+ str[0] = '\0';
+
+ for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
+ int r;
+
+ if ((output_types & BIT(i)) == 0)
+ continue;
+
+ r = snprintf(str, len, "%s%s",
+str != buf ? "," : "", output_type_str[i]);
+ if (r >= len)
+ break;
+ str += r;
+ len -= r;
+
+ output_types &= ~BIT(i);
+ }
+
+ WARN_ON_ONCE(output_types != 0);
+}
+
static void intel_dump_pipe_config(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config,
const char *context)
@@ -10684,10 +10730,15 @@ static void intel_dump_pipe_config(struct intel_crtc
*crtc,
struct intel_plane *intel_plane;
struct intel_plane_state *state;
struct drm_framebuffer *fb;
+ char buf[64];
DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
crtc->base.base.id, crtc->base.name, context);
+ snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
+ DRM_DEBUG_KMS("output_types: %s (0x%x)\n",
+ buf, pipe_config->output_types);
+
DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
transcoder_name(pipe_config->cpu_transcoder),
pipe_config->pipe_bpp, pipe_config->dither);
--
2.13.6
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[Intel-gfx] [PATCH v2 5/9] drm/i915: Split intel_ddi_post_disable() into DP vs. HDMI variants
From: Ville Syrjälä
To clean up the mess in intel_ddi_post_disable() split it into two
clean variants for HDMI and DP.
v2: Rebase due to MST DPMS changes
Reviewed-by: Jani Nikula #v1
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_ddi.c | 111 ++-
1 file changed, 64 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 7187aea75697..afe56bc6fce3 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2280,56 +2280,73 @@ static void intel_disable_ddi_buf(struct intel_encoder
*encoder)
intel_wait_ddi_buf_idle(dev_priv, port);
}
-static void intel_ddi_post_disable(struct intel_encoder *intel_encoder,
+static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
+ const struct intel_crtc_state
*old_crtc_state,
+ const struct drm_connector_state
*old_conn_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
+ struct intel_dp *intel_dp = &dig_port->dp;
+ /*
+* old_crtc_state and old_conn_state are NULL when called from
+* DP_MST. The main connector associated with this port is never
+* bound to a crtc for MST.
+*/
+ bool is_mst = !old_crtc_state;
+
+ /*
+* Power down sink before disabling the port, otherwise we end
+* up getting interrupts from the sink on detecting link loss.
+*/
+ if (!is_mst)
+ intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
+
+ intel_disable_ddi_buf(encoder);
+
+ intel_edp_panel_vdd_on(intel_dp);
+ intel_edp_panel_off(intel_dp);
+
+ intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
+
+ intel_ddi_clk_disable(encoder);
+}
+
+static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
+ const struct intel_crtc_state
*old_crtc_state,
+ const struct drm_connector_state
*old_conn_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
+ struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
+
+ intel_disable_ddi_buf(encoder);
+
+ dig_port->set_infoframes(&encoder->base, false,
+old_crtc_state, old_conn_state);
+
+ intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
+
+ intel_ddi_clk_disable(encoder);
+
+ intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
+}
+
+static void intel_ddi_post_disable(struct intel_encoder *encoder,
const struct intel_crtc_state
*old_crtc_state,
const struct drm_connector_state
*old_conn_state)
{
- struct drm_encoder *encoder = &intel_encoder->base;
- struct drm_i915_private *dev_priv = to_i915(encoder->dev);
- struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
- int type = intel_encoder->type;
-
- if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
- /*
-* old_crtc_state and old_conn_state are NULL when called from
-* DP_MST. The main connector associated with this port is never
-* bound to a crtc for MST.
-*/
- bool is_mst = !old_crtc_state;
- struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
- /*
-* Power down sink before disabling the port, otherwise we end
-* up getting interrupts from the sink on detecting link loss.
-*/
- if (!is_mst)
- intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
- }
-
- intel_disable_ddi_buf(intel_encoder);
-
- if (type == INTEL_OUTPUT_HDMI) {
- dig_port->set_infoframes(encoder, false,
-old_crtc_state, old_conn_state);
- }
-
- if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
- struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
- intel_edp_panel_vdd_on(intel_dp);
- intel_edp_panel_off(intel_dp);
- }
-
- if (dig_port)
- intel_display_power_put(dev_priv,
dig_port->ddi_io_power_domain);
-
- intel_ddi_clk_disable(intel_encoder);
-
- if (type == INTEL_OUTPUT_HDMI) {
- struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
-
- intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
- }
+ /*
+* old_crtc_state and old_conn_state are NULL when called from
+* DP_MST. The main connector associated with this port is never
+
[Intel-gfx] [PATCH v2 3/9] drm/i915: Extract intel_disable_ddi_buf()
From: Ville Syrjälä
Extract the code to disable the DDI_BUF_CTL into small helper. This
will allows us to detangle the encoder type mess in
intel_ddi_post_disable().
v2: Keep using intel_ddi_get_encoder_port() for now
Reviewed-by: Jani Nikula #v1
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_ddi.c | 41 +++-
1 file changed, 24 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 1cc61ba48e3a..e4d1d934231b 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2257,17 +2257,37 @@ static void intel_ddi_pre_enable(struct intel_encoder
*encoder,
}
}
+static void intel_disable_ddi_buf(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum port port = intel_ddi_get_encoder_port(encoder);
+ bool wait = false;
+ u32 val;
+
+ val = I915_READ(DDI_BUF_CTL(port));
+ if (val & DDI_BUF_CTL_ENABLE) {
+ val &= ~DDI_BUF_CTL_ENABLE;
+ I915_WRITE(DDI_BUF_CTL(port), val);
+ wait = true;
+ }
+
+ val = I915_READ(DP_TP_CTL(port));
+ val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
+ val |= DP_TP_CTL_LINK_TRAIN_PAT1;
+ I915_WRITE(DP_TP_CTL(port), val);
+
+ if (wait)
+ intel_wait_ddi_buf_idle(dev_priv, port);
+}
+
static void intel_ddi_post_disable(struct intel_encoder *intel_encoder,
const struct intel_crtc_state
*old_crtc_state,
const struct drm_connector_state
*old_conn_state)
{
struct drm_encoder *encoder = &intel_encoder->base;
struct drm_i915_private *dev_priv = to_i915(encoder->dev);
- enum port port = intel_ddi_get_encoder_port(intel_encoder);
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
int type = intel_encoder->type;
- uint32_t val;
- bool wait = false;
if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
/*
@@ -2286,20 +2306,7 @@ static void intel_ddi_post_disable(struct intel_encoder
*intel_encoder,
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
}
- val = I915_READ(DDI_BUF_CTL(port));
- if (val & DDI_BUF_CTL_ENABLE) {
- val &= ~DDI_BUF_CTL_ENABLE;
- I915_WRITE(DDI_BUF_CTL(port), val);
- wait = true;
- }
-
- val = I915_READ(DP_TP_CTL(port));
- val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
- val |= DP_TP_CTL_LINK_TRAIN_PAT1;
- I915_WRITE(DP_TP_CTL(port), val);
-
- if (wait)
- intel_wait_ddi_buf_idle(dev_priv, port);
+ intel_disable_ddi_buf(intel_encoder);
if (type == INTEL_OUTPUT_HDMI) {
dig_port->set_infoframes(encoder, false,
--
2.13.6
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[Intel-gfx] [PATCH 7/9] drm/i915: Split intel_disable_ddi() into DP vs. HDMI variants
From: Ville Syrjälä
Untangle intel_disable_ddi() by splitting it into DP and HDMI specific
variants.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_ddi.c | 51
1 file changed, 31 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 945980e71697..c930ef0338c5 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2424,29 +2424,40 @@ static void intel_enable_ddi(struct intel_encoder
*intel_encoder,
intel_audio_codec_enable(intel_encoder, pipe_config,
conn_state);
}
-static void intel_disable_ddi(struct intel_encoder *intel_encoder,
+static void intel_disable_ddi_dp(struct intel_encoder *encoder,
+const struct intel_crtc_state *old_crtc_state,
+const struct drm_connector_state
*old_conn_state)
+{
+ struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+
+ if (old_crtc_state->has_audio)
+ intel_audio_codec_disable(encoder);
+
+ intel_edp_drrs_disable(intel_dp, old_crtc_state);
+ intel_psr_disable(intel_dp, old_crtc_state);
+ intel_edp_backlight_off(old_conn_state);
+}
+
+static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
+ const struct intel_crtc_state
*old_crtc_state,
+ const struct drm_connector_state
*old_conn_state)
+{
+ if (old_crtc_state->has_audio)
+ intel_audio_codec_disable(encoder);
+
+ intel_hdmi_handle_sink_scrambling(encoder,
+ old_conn_state->connector,
+ false, false);
+}
+
+static void intel_disable_ddi(struct intel_encoder *encoder,
const struct intel_crtc_state *old_crtc_state,
const struct drm_connector_state *old_conn_state)
{
- struct drm_encoder *encoder = &intel_encoder->base;
- int type = intel_encoder->type;
-
- if (old_crtc_state->has_audio)
- intel_audio_codec_disable(intel_encoder);
-
- if (type == INTEL_OUTPUT_HDMI) {
- intel_hdmi_handle_sink_scrambling(intel_encoder,
- old_conn_state->connector,
- false, false);
- }
-
- if (type == INTEL_OUTPUT_EDP) {
- struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
- intel_edp_drrs_disable(intel_dp, old_crtc_state);
- intel_psr_disable(intel_dp, old_crtc_state);
- intel_edp_backlight_off(old_conn_state);
- }
+ if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
+ intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
+ else
+ intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
}
static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
--
2.13.6
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[Intel-gfx] [PATCH v2 0/9] drm/i915: Cleaner DDI DP vs. HDMI split
From: Ville Syrjälä
Here's a small selection of patches I extracted from my monster
DDI encoder->type drobbery series. These mostly split the encoder
hooks along the DP vs. HDMI lines. Hopefully it'll be a bit easier
to get these reviewed when they're not buried wihtin such a massive
series.
Ville Syrjälä (9):
drm/i915: Dump 'output_types' in crtc state dump
drm/i915: Extract intel_ddi_clk_disable()
drm/i915: Extract intel_disable_ddi_buf()
drm/i915: Inline the required bits of intel_ddi_post_disable() into
intel_ddi_fdi_post_disable()
drm/i915: Split intel_ddi_post_disable() into DP vs. HDMI variants
drm/i915: Remove useless eDP check from intel_ddi_pre_enable_dp()
drm/i915: Split intel_disable_ddi() into DP vs. HDMI variants
drm/i915: Plumb crtc_state etc. directly to
intel_ddi_pre_enable_{dp,hdmi}()
drm/i915: Split intel_enable_ddi() into DP and HDMI variants
drivers/gpu/drm/i915/intel_ddi.c | 318 ---
drivers/gpu/drm/i915/intel_display.c | 51 ++
2 files changed, 231 insertions(+), 138 deletions(-)
--
2.13.6
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