[Intel-gfx] [PULL] gvt-next-fixes for 4.17

[Zhenyu Wang]

Hi, Joonas

Here's gvt-next-fixes update for 4.17. One regression that
caused guest VM gpu hang has been fixed and with other changes
as details below.

Thanks
--
The following changes since commit 22de4e7a531b623962e62ee6d3a39a7e51bdf90e:

  drm/i915/pmu: Work around compiler warnings on some kernel configs 
(2018-03-16 14:35:41 +0200)

are available in the Git repository at:

  https://github.com/intel/gvt-linux.git tags/gvt-next-fixes-2018-03-20

for you to fetch changes up to d8303075699292008ae5b2c8fc728d455b994c26:

  drm/i915/gvt: force to set all context control bits from guest (2018-03-19 
17:33:30 +0800)


gvt-next-fixes-2018-03-20

- No need warning on untracked regs (Colin)
- Error handling fix for dma unmap (Changbin)
- invalidate shadow ppgtt for vGPU reset (Zhi)
- ensure to update shadow ppgtt after pinned (Zhi)
- force guest ctx ctrl update for sanity (Zhenyu/Xiong)
- one typo fix (Colin)


Changbin Du (1):
  drm/i915/kvmgt: Handle kzalloc failure

Colin Ian King (1):
  drm/i915/gvt: fix spelling mistake: "destoried" -> "destroyed"

Colin Xu (1):
  drm/i915/gvt: Remove reduntant printing of untracked mmio

Zhenyu Wang (1):
  drm/i915/gvt: force to set all context control bits from guest

Zhi Wang (2):
  drm/i915/gvt: Invalidate vGPU PPGTT mm objects during a vGPU reset.
  drm/i915/gvt: Update PDPs after a vGPU mm object is pinned.

 drivers/gpu/drm/i915/gvt/gtt.c   | 24 ++-
 drivers/gpu/drm/i915/gvt/gtt.h   |  1 +
 drivers/gpu/drm/i915/gvt/handlers.c  |  9 +
 drivers/gpu/drm/i915/gvt/kvmgt.c | 22 ++---
 drivers/gpu/drm/i915/gvt/scheduler.c | 37 
 drivers/gpu/drm/i915/gvt/vgpu.c  |  1 +
 6 files changed, 82 insertions(+), 12 deletions(-)


-- 
Open Source Technology Center, Intel ltd.

$gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827


signature.asc
Description: PGP signature
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/guc: enable guc interrupts unconditionally in uc_resume

[Patchwork]

== Series Details ==

Series: drm/i915/guc: enable guc interrupts unconditionally in uc_resume
URL   : https://patchwork.freedesktop.org/series/40242/
State : failure

== Summary ==

Series 40242v1 drm/i915/guc: enable guc interrupts unconditionally in uc_resume
https://patchwork.freedesktop.org/api/1.0/series/40242/revisions/1/mbox/

 Possible new issues:

Test kms_flip:
Subgroup basic-flip-vs-dpms:
pass   -> INCOMPLETE (fi-bxt-dsi)

 Known issues:

Test debugfs_test:
Subgroup read_all_entries:
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:435s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:441s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:385s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:535s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:296s
fi-bxt-dsi   total:216  pass:193  dwarn:0   dfail:0   fail:0   skip:22 
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:513s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:515s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:504s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:409s
fi-cfl-s2total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:572s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:511s
fi-cnl-drrs  total:285  pass:254  dwarn:3   dfail:0   fail:0   skip:28  
time:545s
fi-elk-e7500 total:285  pass:225  dwarn:1   dfail:0   fail:0   skip:59  
time:425s
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:318s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:537s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:406s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:423s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:480s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:429s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:475s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:469s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:514s
fi-pnv-d510  total:285  pass:219  dwarn:1   dfail:0   fail:0   skip:65  
time:651s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:436s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:529s
fi-skl-6700hqtotal:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:541s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:504s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:505s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:430s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:445s
fi-snb-2520m total:3pass:2dwarn:0   dfail:0   fail:0   skip:0  
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:403s

141def2a45f4a3ad7c7e9144cd26e97bb1298397 drm-tip: 2018y-03m-19d-23h-48m-43s UTC 
integration manifest
d0deedc3aab7 drm/i915/guc: enable guc interrupts unconditionally in uc_resume

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8407/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915: Add control flags to i915_handle_error()

[Patchwork]

== Series Details ==

Series: series starting with [1/5] drm/i915: Add control flags to 
i915_handle_error()
URL   : https://patchwork.freedesktop.org/series/40240/
State : success

== Summary ==

Series 40240v1 series starting with [1/5] drm/i915: Add control flags to 
i915_handle_error()
https://patchwork.freedesktop.org/api/1.0/series/40240/revisions/1/mbox/

 Known issues:

Test kms_chamelium:
Subgroup dp-crc-fast:
pass   -> DMESG-FAIL (fi-kbl-7500u) fdo#103841
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
incomplete -> PASS   (fi-snb-2520m) fdo#103713

fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:432s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:445s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:378s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:533s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:296s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:516s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:516s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:504s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:414s
fi-cfl-s2total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:585s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:512s
fi-cnl-drrs  total:285  pass:254  dwarn:3   dfail:0   fail:0   skip:28  
time:523s
fi-elk-e7500 total:285  pass:225  dwarn:1   dfail:0   fail:0   skip:59  
time:426s
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:317s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:536s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:400s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:422s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:473s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:428s
fi-kbl-7500u total:285  pass:259  dwarn:1   dfail:1   fail:0   skip:24  
time:478s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:467s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:514s
fi-pnv-d510  total:285  pass:219  dwarn:1   dfail:0   fail:0   skip:65  
time:655s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:439s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:530s
fi-skl-6700hqtotal:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:542s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:504s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:487s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:427s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:447s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:568s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:397s

141def2a45f4a3ad7c7e9144cd26e97bb1298397 drm-tip: 2018y-03m-19d-23h-48m-43s UTC 
integration manifest
2950e96e849d drm/i915/execlists: Flush pending preemption events during reset
597e8d4ae7a5 drm/i915: Split execlists/guc reset prepartions
fe83f1c114bf drm/i915: Move engine reset prepare/finish to backends
76088d3cc0fb drm/i915/execlists: Refactor out complete_preempt_context()
b279af513a73 drm/i915: Add control flags to i915_handle_error()

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8406/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/dp: Correctly mask DP_TRAINING_AUX_RD_INTERVAL values for DP 1.4

[kbuild test robot]

Hi Matt,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on v4.16-rc4]
[also build test ERROR on next-20180319]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/matthew-s-atwood-intel-com/drm-dp-Correctly-mask-DP_TRAINING_AUX_RD_INTERVAL-values-for-DP-1-4/20180319-073021
config: ia64-allyesconfig (attached as .config)
compiler: ia64-linux-gcc (GCC) 7.2.0
reproduce:
wget 
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O 
~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=ia64 

All errors (new ones prefixed by >>):

   In file included from 
drivers/gpu/drm/amd/amdgpu/../display/include/dpcd_defs.h:29:0,
from 
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link.c:42:
>> include/drm/drm_dp_helper.h:67:45: error: expected identifier before numeric 
>> constant
# define DPCD_REV_100x10
^
   drivers/gpu/drm/amd/amdgpu/../display/include/dpcd_defs.h:32:2: note: in 
expansion of macro 'DPCD_REV_10'
 DPCD_REV_10 = 0x10,
 ^~~

vim +67 include/drm/drm_dp_helper.h

63  
64  /* AUX CH addresses */
65  /* DPCD */
66  #define DP_DPCD_REV 0x000
  > 67  # define DPCD_REV_100x10
68  # define DPCD_REV_110x11
69  # define DPCD_REV_120x12
70  # define DPCD_REV_130x13
71  # define DPCD_REV_140x14
72  

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation


.config.gz
Description: application/gzip
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/5] drm/i915: Add control flags to i915_handle_error()

[Patchwork]

== Series Details ==

Series: series starting with [1/5] drm/i915: Add control flags to 
i915_handle_error()
URL   : https://patchwork.freedesktop.org/series/40240/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/i915: Add control flags to i915_handle_error()
+drivers/gpu/drm/i915/i915_request.c:1232:35: warning: Using plain integer as 
NULL pointer

Commit: drm/i915/execlists: Refactor out complete_preempt_context()
Okay!

Commit: drm/i915: Move engine reset prepare/finish to backends
Okay!

Commit: drm/i915: Split execlists/guc reset prepartions
Okay!

Commit: drm/i915/execlists: Flush pending preemption events during reset
Okay!

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/5] drm/i915: Add control flags to i915_handle_error()

[Patchwork]

== Series Details ==

Series: series starting with [1/5] drm/i915: Add control flags to 
i915_handle_error()
URL   : https://patchwork.freedesktop.org/series/40240/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
b279af513a73 drm/i915: Add control flags to i915_handle_error()
-:111: CHECK:AVOID_EXTERNS: extern prototypes should be avoided in .h files
#111: FILE: drivers/gpu/drm/i915/i915_drv.h:2703:
+extern void i915_reset(struct drm_i915_private *i915, const char *msg);

-:112: CHECK:AVOID_EXTERNS: extern prototypes should be avoided in .h files
#112: FILE: drivers/gpu/drm/i915/i915_drv.h:2704:
+extern int i915_reset_engine(struct intel_engine_cs *engine, const char *msg);

total: 0 errors, 0 warnings, 2 checks, 273 lines checked
76088d3cc0fb drm/i915/execlists: Refactor out complete_preempt_context()
fe83f1c114bf drm/i915: Move engine reset prepare/finish to backends
597e8d4ae7a5 drm/i915: Split execlists/guc reset prepartions
2950e96e849d drm/i915/execlists: Flush pending preemption events during reset
-:103: WARNING:LONG_LINE: line over 100 characters
#103: FILE: drivers/gpu/drm/i915/intel_lrc.c:879:
+ head, GEN8_CSB_READ_PTR(readl(i915->regs + 
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine, fw ? "" : "?",

-:104: WARNING:LONG_LINE: line over 100 characters
#104: FILE: drivers/gpu/drm/i915/intel_lrc.c:880:
+ tail, GEN8_CSB_WRITE_PTR(readl(i915->regs + 
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine, fw ? "" : "?");

-:159: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#159: FILE: drivers/gpu/drm/i915/intel_lrc.c:911:
+ status, buf[2*head + 1],
   ^

-:188: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#188: FILE: drivers/gpu/drm/i915/intel_lrc.c:929:
+   buf[2*head + 1] == execlists->preempt_complete_status) {
 ^

total: 0 errors, 2 warnings, 2 checks, 396 lines checked

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Don't try to enable GuC logging when we're not using GuC

[Patchwork]

== Series Details ==

Series: drm/i915/guc: Don't try to enable GuC logging when we're not using GuC
URL   : https://patchwork.freedesktop.org/series/40239/
State : success

== Summary ==

Series 40239v1 drm/i915/guc: Don't try to enable GuC logging when we're not 
using GuC
https://patchwork.freedesktop.org/api/1.0/series/40239/revisions/1/mbox/

 Known issues:

Test debugfs_test:
Subgroup read_all_entries:
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass   -> INCOMPLETE (fi-bdw-5557u) fdo#104944

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#104944 https://bugs.freedesktop.org/show_bug.cgi?id=104944

fi-bdw-5557u total:241  pass:223  dwarn:0   dfail:0   fail:0   skip:17 
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:439s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:379s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:531s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:296s
fi-bxt-dsi   total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  
time:509s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:518s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:515s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:501s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:409s
fi-cfl-s2total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:574s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:509s
fi-cnl-drrs  total:285  pass:254  dwarn:3   dfail:0   fail:0   skip:28  
time:533s
fi-elk-e7500 total:285  pass:225  dwarn:1   dfail:0   fail:0   skip:59  
time:422s
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:317s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:534s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:408s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:418s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:472s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:428s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:474s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:467s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:519s
fi-pnv-d510  total:285  pass:219  dwarn:1   dfail:0   fail:0   skip:65  
time:659s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:440s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:536s
fi-skl-6700hqtotal:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:541s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:506s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:488s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:430s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:446s
fi-snb-2520m total:3pass:2dwarn:0   dfail:0   fail:0   skip:0  
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:400s

141def2a45f4a3ad7c7e9144cd26e97bb1298397 drm-tip: 2018y-03m-19d-23h-48m-43s UTC 
integration manifest
430e544c2989 drm/i915/guc: Don't try to enable GuC logging when we're not using 
GuC

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8405/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 1/5] drm/i915: Add control flags to i915_handle_error()

[Chris Wilson]

Quoting Michel Thierry (2018-03-20 00:56:04)
> On 3/19/2018 5:44 PM, Chris Wilson wrote:
> > Quoting Michel Thierry (2018-03-20 00:39:35)
> >> On 3/19/2018 5:18 PM, Chris Wilson wrote:
> >>> Not all callers want the GPU error to handled in the same way, so expose
> >>> a control parameter. In the first instance, some callers do not want the
> >>> heavyweight error capture so add a bit to request the state to be
> >>> captured and saved.
> >>>
> >>> v2: Pass msg down to i915_reset/i915_reset_engine so that we include the
> >>> reason for the reset in the dev_notice(), superseding the earlier option
> >>> to not print that notice.
> >>>
> >>> Signed-off-by: Chris Wilson 
> >>> Cc: Jeff McGee 
> >>> Cc: Mika Kuoppala 
> >>> Cc: Michel Thierry 
> >>> ---
> >>>drivers/gpu/drm/i915/i915_debugfs.c  |  4 +--
> >>>drivers/gpu/drm/i915/i915_drv.c  | 17 +--
> >>>drivers/gpu/drm/i915/i915_drv.h  | 10 +++---
> >>>drivers/gpu/drm/i915/i915_irq.c  | 39 
> >>> +---
> >>>drivers/gpu/drm/i915/intel_hangcheck.c   | 13 
> >>>drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 13 +++-
> >>>6 files changed, 48 insertions(+), 48 deletions(-)
> >>>
> >> ...
> >>> diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c 
> >>> b/drivers/gpu/drm/i915/intel_hangcheck.c
> >>> index 42e45ae87393..fd0ffb8328d0 100644
> >>> --- a/drivers/gpu/drm/i915/intel_hangcheck.c
> >>> +++ b/drivers/gpu/drm/i915/intel_hangcheck.c
> >>> @@ -246,9 +246,8 @@ engine_stuck(struct intel_engine_cs *engine, u64 
> >>> acthd)
> >>> */
> >>>tmp = I915_READ_CTL(engine);
> >>>if (tmp & RING_WAIT) {
> >>> - i915_handle_error(dev_priv, 0,
> >>> -   "Kicking stuck wait on %s",
> >>> -   engine->name);
> >>> + i915_handle_error(dev_priv, BIT(engine->id), 0,
> >>> +   "stuck wait on %s", engine->name);
> >> Before we were not resetting anything here, is this change on purpose?
> >> (if it is, it's worth adding it to the commit msg since it's changing
> >> behavior).
> >>
> >>>I915_WRITE_CTL(engine, tmp);
> >>>return ENGINE_WAIT_KICK;
> >>>} > @@ -258,8 +257,8 @@ engine_stuck(struct intel_engine_cs 
> >>> *engine, u64
> >> acthd)
> >>>default:
> >>>return ENGINE_DEAD;
> >>>case 1:
> >>> - i915_handle_error(dev_priv, 0,
> >>> -   "Kicking stuck semaphore on %s",
> >>> + i915_handle_error(dev_priv, ALL_ENGINES, 0,
> >> Same here,
> > 
> > Both are functionally no-op changes, as they are only for !per-engine
> > platforms (unless someone manages to send just the wrong type of garbage
> > to the GPU). I just thought it interesting to document that wait-event
> > needs a local kick and the wait-sema needs to kick the other engines.
> i915_handle_error has this before full reset:
> 
> if (!engine_mask)
> goto out;
> 
> No reset at all was happening before.

We bugged out a while back then ;)
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] linux-next: manual merge of the drm-misc tree with Linus' tree

[Stephen Rothwell]

Hi all,

Today's linux-next merge of the drm-misc tree got a conflict in:

  drivers/gpu/drm/sun4i/sun4i_tcon.h

between commit:

  e742a17cd360 ("drm/sun4i: tcon: Reduce the scope of the LVDS error a bit")

from Linus' tree and commit:

  6664e9dc5383 ("drm/sun4i: Add support for A80 TCONs")

from the drm-misc tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc drivers/gpu/drm/sun4i/sun4i_tcon.h
index abdc6ad6b384,d3a945b7bb60..
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
@@@ -176,7 -176,7 +176,8 @@@ struct sun4i_tcon_quirks 
boolhas_channel_1;  /* a33 does not have channel 1 */
boolhas_lvds_alt;   /* Does the LVDS clock have a parent other than 
the TCON clock? */
boolneeds_de_be_mux; /* sun6i needs mux to select backend */
 +  boolsupports_lvds;   /* Does the TCON support an LVDS output? */
+   boolneeds_edp_reset; /* a80 edp reset needed for tcon0 access */
  
/* callback to handle tcon muxing options */
int (*set_mux)(struct sun4i_tcon *, const struct drm_encoder *);


pgpYuEuGCJeMg.pgp
Description: OpenPGP digital signature
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/dp: Correctly mask DP_TRAINING_AUX_RD_INTERVAL values for DP 1.4

[kbuild test robot]

Hi Matt,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on v4.16-rc4]
[also build test ERROR on next-20180319]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/matthew-s-atwood-intel-com/drm-dp-Correctly-mask-DP_TRAINING_AUX_RD_INTERVAL-values-for-DP-1-4/20180319-073021
config: i386-allyesconfig (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386 

All errors (new ones prefixed by >>):

   In file included from 
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link.c:42:0:
>> drivers/gpu/drm/amd/amdgpu/../display/include/dpcd_defs.h:32:2: error: 
>> expected identifier before numeric constant
 DPCD_REV_10 = 0x10,
 ^~~~

vim +32 drivers/gpu/drm/amd/amdgpu/../display/include/dpcd_defs.h

4562236b3b Harry Wentland 2017-09-12  30  
4562236b3b Harry Wentland 2017-09-12  31  enum dpcd_revision {
4562236b3b Harry Wentland 2017-09-12 @32DPCD_REV_10 = 0x10,
4562236b3b Harry Wentland 2017-09-12  33DPCD_REV_11 = 0x11,
4562236b3b Harry Wentland 2017-09-12  34DPCD_REV_12 = 0x12,
4562236b3b Harry Wentland 2017-09-12  35DPCD_REV_13 = 0x13,
4562236b3b Harry Wentland 2017-09-12  36DPCD_REV_14 = 0x14
4562236b3b Harry Wentland 2017-09-12  37  };
4562236b3b Harry Wentland 2017-09-12  38  

:: The code at line 32 was first introduced by commit
:: 4562236b3bc0a28aeb6ee93b2d8a849a4c4e1c7c drm/amd/dc: Add dc display 
driver (v2)

:: TO: Harry Wentland <harry.wentl...@amd.com>
:: CC: Alex Deucher <alexander.deuc...@amd.com>

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation


.config.gz
Description: application/gzip
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH] drm/i915/guc: enable guc interrupts unconditionally in uc_resume

[Michel Thierry]

Probably lost while rebasing commit eacd8391f977 ("drm/i915/guc: Keep GuC
interrupts enabled when using GuC").

Not really needed since i915_gem_init_hw is called before uc_resume, but
it brings symmetry to uc_suspend.

Signed-off-by: Michel Thierry 
Cc: Michał Winiarski 
---
 drivers/gpu/drm/i915/intel_uc.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 34e847d0ee4c..4d69d38a63ad 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -480,8 +480,7 @@ int intel_uc_resume(struct drm_i915_private *i915)
if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return 0;
 
-   if (i915_modparams.guc_log_level)
-   gen9_enable_guc_interrupts(i915);
+   gen9_enable_guc_interrupts(i915);
 
err = intel_guc_resume(guc);
if (err) {
-- 
2.16.2

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 1/5] drm/i915: Add control flags to i915_handle_error()

[Michel Thierry]

On 3/19/2018 5:44 PM, Chris Wilson wrote:

Quoting Michel Thierry (2018-03-20 00:39:35)

On 3/19/2018 5:18 PM, Chris Wilson wrote:

Not all callers want the GPU error to handled in the same way, so expose
a control parameter. In the first instance, some callers do not want the
heavyweight error capture so add a bit to request the state to be
captured and saved.

v2: Pass msg down to i915_reset/i915_reset_engine so that we include the
reason for the reset in the dev_notice(), superseding the earlier option
to not print that notice.

Signed-off-by: Chris Wilson 
Cc: Jeff McGee 
Cc: Mika Kuoppala 
Cc: Michel Thierry 
---
   drivers/gpu/drm/i915/i915_debugfs.c  |  4 +--
   drivers/gpu/drm/i915/i915_drv.c  | 17 +--
   drivers/gpu/drm/i915/i915_drv.h  | 10 +++---
   drivers/gpu/drm/i915/i915_irq.c  | 39 
+---
   drivers/gpu/drm/i915/intel_hangcheck.c   | 13 
   drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 13 +++-
   6 files changed, 48 insertions(+), 48 deletions(-)


...

diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c 
b/drivers/gpu/drm/i915/intel_hangcheck.c
index 42e45ae87393..fd0ffb8328d0 100644
--- a/drivers/gpu/drm/i915/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/intel_hangcheck.c
@@ -246,9 +246,8 @@ engine_stuck(struct intel_engine_cs *engine, u64 acthd)
*/
   tmp = I915_READ_CTL(engine);
   if (tmp & RING_WAIT) {
- i915_handle_error(dev_priv, 0,
-   "Kicking stuck wait on %s",
-   engine->name);
+ i915_handle_error(dev_priv, BIT(engine->id), 0,
+   "stuck wait on %s", engine->name);

Before we were not resetting anything here, is this change on purpose?
(if it is, it's worth adding it to the commit msg since it's changing
behavior).


   I915_WRITE_CTL(engine, tmp);
   return ENGINE_WAIT_KICK;
   } > @@ -258,8 +257,8 @@ engine_stuck(struct intel_engine_cs *engine, u64

acthd)

   default:
   return ENGINE_DEAD;
   case 1:
- i915_handle_error(dev_priv, 0,
-   "Kicking stuck semaphore on %s",
+ i915_handle_error(dev_priv, ALL_ENGINES, 0,

Same here,


Both are functionally no-op changes, as they are only for !per-engine
platforms (unless someone manages to send just the wrong type of garbage
to the GPU). I just thought it interesting to document that wait-event
needs a local kick and the wait-sema needs to kick the other engines.

i915_handle_error has this before full reset:

if (!engine_mask)
goto out;

No reset at all was happening before.
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 1/5] drm/i915: Add control flags to i915_handle_error()

[Chris Wilson]

Quoting Michel Thierry (2018-03-20 00:39:35)
> On 3/19/2018 5:18 PM, Chris Wilson wrote:
> > Not all callers want the GPU error to handled in the same way, so expose
> > a control parameter. In the first instance, some callers do not want the
> > heavyweight error capture so add a bit to request the state to be
> > captured and saved.
> > 
> > v2: Pass msg down to i915_reset/i915_reset_engine so that we include the
> > reason for the reset in the dev_notice(), superseding the earlier option
> > to not print that notice.
> > 
> > Signed-off-by: Chris Wilson 
> > Cc: Jeff McGee 
> > Cc: Mika Kuoppala 
> > Cc: Michel Thierry 
> > ---
> >   drivers/gpu/drm/i915/i915_debugfs.c  |  4 +--
> >   drivers/gpu/drm/i915/i915_drv.c  | 17 +--
> >   drivers/gpu/drm/i915/i915_drv.h  | 10 +++---
> >   drivers/gpu/drm/i915/i915_irq.c  | 39 
> > +---
> >   drivers/gpu/drm/i915/intel_hangcheck.c   | 13 
> >   drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 13 +++-
> >   6 files changed, 48 insertions(+), 48 deletions(-)
> > 
> ...
> > diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c 
> > b/drivers/gpu/drm/i915/intel_hangcheck.c
> > index 42e45ae87393..fd0ffb8328d0 100644
> > --- a/drivers/gpu/drm/i915/intel_hangcheck.c
> > +++ b/drivers/gpu/drm/i915/intel_hangcheck.c
> > @@ -246,9 +246,8 @@ engine_stuck(struct intel_engine_cs *engine, u64 acthd)
> >*/
> >   tmp = I915_READ_CTL(engine);
> >   if (tmp & RING_WAIT) {
> > - i915_handle_error(dev_priv, 0,
> > -   "Kicking stuck wait on %s",
> > -   engine->name);
> > + i915_handle_error(dev_priv, BIT(engine->id), 0,
> > +   "stuck wait on %s", engine->name);
> Before we were not resetting anything here, is this change on purpose? 
> (if it is, it's worth adding it to the commit msg since it's changing 
> behavior).
> 
> >   I915_WRITE_CTL(engine, tmp);
> >   return ENGINE_WAIT_KICK;
> >   } > @@ -258,8 +257,8 @@ engine_stuck(struct intel_engine_cs *engine, 
> > u64 
> acthd)
> >   default:
> >   return ENGINE_DEAD;
> >   case 1:
> > - i915_handle_error(dev_priv, 0,
> > -   "Kicking stuck semaphore on %s",
> > + i915_handle_error(dev_priv, ALL_ENGINES, 0,
> Same here,

Both are functionally no-op changes, as they are only for !per-engine
platforms (unless someone manages to send just the wrong type of garbage
to the GPU). I just thought it interesting to document that wait-event
needs a local kick and the wait-sema needs to kick the other engines.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 1/5] drm/i915: Add control flags to i915_handle_error()

[Michel Thierry]

On 3/19/2018 5:18 PM, Chris Wilson wrote:

Not all callers want the GPU error to handled in the same way, so expose
a control parameter. In the first instance, some callers do not want the
heavyweight error capture so add a bit to request the state to be
captured and saved.

v2: Pass msg down to i915_reset/i915_reset_engine so that we include the
reason for the reset in the dev_notice(), superseding the earlier option
to not print that notice.

Signed-off-by: Chris Wilson 
Cc: Jeff McGee 
Cc: Mika Kuoppala 
Cc: Michel Thierry 
---
  drivers/gpu/drm/i915/i915_debugfs.c  |  4 +--
  drivers/gpu/drm/i915/i915_drv.c  | 17 +--
  drivers/gpu/drm/i915/i915_drv.h  | 10 +++---
  drivers/gpu/drm/i915/i915_irq.c  | 39 +---
  drivers/gpu/drm/i915/intel_hangcheck.c   | 13 
  drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 13 +++-
  6 files changed, 48 insertions(+), 48 deletions(-)


...

diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c 
b/drivers/gpu/drm/i915/intel_hangcheck.c
index 42e45ae87393..fd0ffb8328d0 100644
--- a/drivers/gpu/drm/i915/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/intel_hangcheck.c
@@ -246,9 +246,8 @@ engine_stuck(struct intel_engine_cs *engine, u64 acthd)
 */
tmp = I915_READ_CTL(engine);
if (tmp & RING_WAIT) {
-   i915_handle_error(dev_priv, 0,
- "Kicking stuck wait on %s",
- engine->name);
+   i915_handle_error(dev_priv, BIT(engine->id), 0,
+ "stuck wait on %s", engine->name);
Before we were not resetting anything here, is this change on purpose? 
(if it is, it's worth adding it to the commit msg since it's changing 
behavior).



I915_WRITE_CTL(engine, tmp);
return ENGINE_WAIT_KICK;
  	} > @@ -258,8 +257,8 @@ engine_stuck(struct intel_engine_cs *engine, u64 

acthd)

default:
return ENGINE_DEAD;
case 1:
-   i915_handle_error(dev_priv, 0,
- "Kicking stuck semaphore on %s",
+   i915_handle_error(dev_priv, ALL_ENGINES, 0,

Same here,


+ "stuck semaphore on %s",
  engine->name);
I915_WRITE_CTL(engine, tmp);
return ENGINE_WAIT_KICK;


Everything else looks OK to me.

-Michel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 2/5] drm/i915/execlists: Refactor out complete_preempt_context()

[Chris Wilson]

As a complement to inject_preempt_context(), follow up with the function
to handle its completion. This will be useful should we wish to extend
the duties of the preempt-context for execlists.

Signed-off-by: Chris Wilson 
Cc: Jeff McGee 
Cc: Michał Winiarski 
---
 drivers/gpu/drm/i915/intel_lrc.c | 22 --
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 53f1c009ed7b..0bfaeb56b8c7 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -531,8 +531,17 @@ static void inject_preempt_context(struct intel_engine_cs 
*engine)
if (execlists->ctrl_reg)
writel(EL_CTRL_LOAD, execlists->ctrl_reg);
 
-   execlists_clear_active(>execlists, EXECLISTS_ACTIVE_HWACK);
-   execlists_set_active(>execlists, EXECLISTS_ACTIVE_PREEMPT);
+   execlists_clear_active(execlists, EXECLISTS_ACTIVE_HWACK);
+   execlists_set_active(execlists, EXECLISTS_ACTIVE_PREEMPT);
+}
+
+static void complete_preempt_context(struct intel_engine_execlists *execlists)
+{
+   execlists_cancel_port_requests(execlists);
+   execlists_unwind_incomplete_requests(execlists);
+
+   GEM_BUG_ON(!execlists_is_active(execlists, EXECLISTS_ACTIVE_PREEMPT));
+   execlists_clear_active(execlists, EXECLISTS_ACTIVE_PREEMPT);
 }
 
 static void execlists_dequeue(struct intel_engine_cs *engine)
@@ -939,14 +948,7 @@ static void execlists_submission_tasklet(unsigned long 
data)
if (status & GEN8_CTX_STATUS_COMPLETE &&
buf[2*head + 1] == 
execlists->preempt_complete_status) {
GEM_TRACE("%s preempt-idle\n", engine->name);
-
-   execlists_cancel_port_requests(execlists);
-   execlists_unwind_incomplete_requests(execlists);
-
-   GEM_BUG_ON(!execlists_is_active(execlists,
-   
EXECLISTS_ACTIVE_PREEMPT));
-   execlists_clear_active(execlists,
-  
EXECLISTS_ACTIVE_PREEMPT);
+   complete_preempt_context(execlists);
continue;
}
 
-- 
2.16.2

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 1/5] drm/i915: Add control flags to i915_handle_error()

[Chris Wilson]

Not all callers want the GPU error to handled in the same way, so expose
a control parameter. In the first instance, some callers do not want the
heavyweight error capture so add a bit to request the state to be
captured and saved.

v2: Pass msg down to i915_reset/i915_reset_engine so that we include the
reason for the reset in the dev_notice(), superseding the earlier option
to not print that notice.

Signed-off-by: Chris Wilson 
Cc: Jeff McGee 
Cc: Mika Kuoppala 
Cc: Michel Thierry 
---
 drivers/gpu/drm/i915/i915_debugfs.c  |  4 +--
 drivers/gpu/drm/i915/i915_drv.c  | 17 +--
 drivers/gpu/drm/i915/i915_drv.h  | 10 +++---
 drivers/gpu/drm/i915/i915_irq.c  | 39 +---
 drivers/gpu/drm/i915/intel_hangcheck.c   | 13 
 drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 13 +++-
 6 files changed, 48 insertions(+), 48 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 964ea1a12357..7816cd53100a 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4011,8 +4011,8 @@ i915_wedged_set(void *data, u64 val)
engine->hangcheck.stalled = true;
}
 
-   i915_handle_error(i915, val, "Manually set wedged engine mask = %llx",
- val);
+   i915_handle_error(i915, val, I915_ERROR_CAPTURE,
+ "Manually set wedged engine mask = %llx", val);
 
wait_on_bit(>gpu_error.flags,
I915_RESET_HANDOFF,
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1021bf40e236..204fa07e8f79 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1869,7 +1869,7 @@ static int i915_resume_switcheroo(struct drm_device *dev)
 /**
  * i915_reset - reset chip after a hang
  * @i915: #drm_i915_private to reset
- * @flags: Instructions
+ * @msg: reason for GPU reset; or NULL for no dev_notice()
  *
  * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
  * on failure.
@@ -1884,7 +1884,7 @@ static int i915_resume_switcheroo(struct drm_device *dev)
  *   - re-init interrupt state
  *   - re-init display
  */
-void i915_reset(struct drm_i915_private *i915, unsigned int flags)
+void i915_reset(struct drm_i915_private *i915, const char *msg)
 {
struct i915_gpu_error *error = >gpu_error;
int ret;
@@ -1901,8 +1901,8 @@ void i915_reset(struct drm_i915_private *i915, unsigned 
int flags)
if (!i915_gem_unset_wedged(i915))
goto wakeup;
 
-   if (!(flags & I915_RESET_QUIET))
-   dev_notice(i915->drm.dev, "Resetting chip after gpu hang\n");
+   if (msg)
+   dev_notice(i915->drm.dev, "Resetting chip for %s\n", msg);
error->reset_count++;
 
disable_irq(i915->drm.irq);
@@ -2003,7 +2003,7 @@ static inline int intel_gt_reset_engine(struct 
drm_i915_private *dev_priv,
 /**
  * i915_reset_engine - reset GPU engine to recover from a hang
  * @engine: engine to reset
- * @flags: options
+ * @msg: reason for GPU reset; or NULL for no dev_notice()
  *
  * Reset a specific GPU engine. Useful if a hang is detected.
  * Returns zero on successful reset or otherwise an error code.
@@ -2013,7 +2013,7 @@ static inline int intel_gt_reset_engine(struct 
drm_i915_private *dev_priv,
  *  - reset engine (which will force the engine to idle)
  *  - re-init/configure engine
  */
-int i915_reset_engine(struct intel_engine_cs *engine, unsigned int flags)
+int i915_reset_engine(struct intel_engine_cs *engine, const char *msg)
 {
struct i915_gpu_error *error = >i915->gpu_error;
struct i915_request *active_request;
@@ -2028,10 +2028,9 @@ int i915_reset_engine(struct intel_engine_cs *engine, 
unsigned int flags)
goto out;
}
 
-   if (!(flags & I915_RESET_QUIET)) {
+   if (msg)
dev_notice(engine->i915->drm.dev,
-  "Resetting %s after gpu hang\n", engine->name);
-   }
+  "Resetting %s for %s\n", engine->name, msg);
error->reset_engine_count[engine->id]++;
 
if (!engine->i915->guc.execbuf_client)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e27ba8fb64e6..29ef6c16bbe5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2700,10 +2700,8 @@ extern void i915_driver_unload(struct drm_device *dev);
 extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
 extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
 
-#define I915_RESET_QUIET BIT(0)
-extern void i915_reset(struct drm_i915_private *i915, unsigned int flags);
-extern int i915_reset_engine(struct intel_engine_cs *engine,
- 

[Intel-gfx] [PATCH 3/5] drm/i915: Move engine reset prepare/finish to backends

[Chris Wilson]

In preparation to more carefully handling incomplete preemption during
reset by execlists, we move the existing code wholesale to the backends
under a couple of new reset vfuncs.

Signed-off-by: Chris Wilson 
Cc: Michał Winiarski 
CC: Michel Thierry 
Cc: Jeff McGee 
---
 drivers/gpu/drm/i915/i915_gem.c | 42 --
 drivers/gpu/drm/i915/intel_lrc.c| 52 +++--
 drivers/gpu/drm/i915/intel_ringbuffer.c | 20 +++--
 drivers/gpu/drm/i915/intel_ringbuffer.h |  9 --
 4 files changed, 78 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 802df8e1a544..38f7160d99c9 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2917,7 +2917,7 @@ static bool engine_stalled(struct intel_engine_cs *engine)
 struct i915_request *
 i915_gem_reset_prepare_engine(struct intel_engine_cs *engine)
 {
-   struct i915_request *request = NULL;
+   struct i915_request *request;
 
/*
 * During the reset sequence, we must prevent the engine from
@@ -2940,40 +2940,7 @@ i915_gem_reset_prepare_engine(struct intel_engine_cs 
*engine)
 */
kthread_park(engine->breadcrumbs.signaler);
 
-   /*
-* Prevent request submission to the hardware until we have
-* completed the reset in i915_gem_reset_finish(). If a request
-* is completed by one engine, it may then queue a request
-* to a second via its execlists->tasklet *just* as we are
-* calling engine->init_hw() and also writing the ELSP.
-* Turning off the execlists->tasklet until the reset is over
-* prevents the race.
-*
-* Note that this needs to be a single atomic operation on the
-* tasklet (flush existing tasks, prevent new tasks) to prevent
-* a race between reset and set-wedged. It is not, so we do the best
-* we can atm and make sure we don't lock the machine up in the more
-* common case of recursively being called from set-wedged from inside
-* i915_reset.
-*/
-   if (!atomic_read(>execlists.tasklet.count))
-   tasklet_kill(>execlists.tasklet);
-   tasklet_disable(>execlists.tasklet);
-
-   /*
-* We're using worker to queue preemption requests from the tasklet in
-* GuC submission mode.
-* Even though tasklet was disabled, we may still have a worker queued.
-* Let's make sure that all workers scheduled before disabling the
-* tasklet are completed before continuing with the reset.
-*/
-   if (engine->i915->guc.preempt_wq)
-   flush_workqueue(engine->i915->guc.preempt_wq);
-
-   if (engine->irq_seqno_barrier)
-   engine->irq_seqno_barrier(engine);
-
-   request = i915_gem_find_active_request(engine);
+   request = engine->reset.prepare(engine);
if (request && request->fence.error == -EIO)
request = ERR_PTR(-EIO); /* Previous reset failed! */
 
@@ -3120,7 +3087,7 @@ void i915_gem_reset_engine(struct intel_engine_cs *engine,
}
 
/* Setup the CS to resume from the breadcrumb of the hung request */
-   engine->reset_hw(engine, request);
+   engine->reset.reset(engine, request);
 }
 
 void i915_gem_reset(struct drm_i915_private *dev_priv)
@@ -3172,7 +3139,8 @@ void i915_gem_reset(struct drm_i915_private *dev_priv)
 
 void i915_gem_reset_finish_engine(struct intel_engine_cs *engine)
 {
-   tasklet_enable(>execlists.tasklet);
+   engine->reset.finish(engine);
+
kthread_unpark(engine->breadcrumbs.signaler);
 
intel_uncore_forcewake_put(engine->i915, FORCEWAKE_ALL);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 0bfaeb56b8c7..f662a9524233 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1663,6 +1663,44 @@ static int gen9_init_render_ring(struct intel_engine_cs 
*engine)
return init_workarounds_ring(engine);
 }
 
+static struct i915_request *
+execlists_reset_prepare(struct intel_engine_cs *engine)
+{
+   struct intel_engine_execlists * const execlists = >execlists;
+
+   /*
+* Prevent request submission to the hardware until we have
+* completed the reset in i915_gem_reset_finish(). If a request
+* is completed by one engine, it may then queue a request
+* to a second via its execlists->tasklet *just* as we are
+* calling engine->init_hw() and also writing the ELSP.
+* Turning off the execlists->tasklet until the reset is over
+* prevents the race.
+*
+* Note that this needs to be a single atomic operation on the
+* tasklet (flush existing tasks, prevent new tasks) to prevent
+* a race between reset and 

[Intel-gfx] [PATCH 4/5] drm/i915: Split execlists/guc reset prepartions

[Chris Wilson]

In the next patch, we will make the execlists reset prepare callback
take into account preemption by flushing the context-switch handler.
This is not applicable to the GuC submission backend, so split the two
into their own backend callbacks.

Signed-off-by: Chris Wilson 
Cc: Michał Winiarski 
CC: Michel Thierry 
Cc: Jeff McGee 
---
 drivers/gpu/drm/i915/intel_guc_submission.c | 39 +
 drivers/gpu/drm/i915/intel_lrc.c| 11 +---
 2 files changed, 40 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c 
b/drivers/gpu/drm/i915/intel_guc_submission.c
index 207cda062626..779c8d3156e5 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -776,6 +776,44 @@ static void guc_submission_tasklet(unsigned long data)
guc_dequeue(engine);
 }
 
+static struct i915_request *
+guc_reset_prepare(struct intel_engine_cs *engine)
+{
+   struct intel_engine_execlists * const execlists = >execlists;
+
+   /*
+* Prevent request submission to the hardware until we have
+* completed the reset in i915_gem_reset_finish(). If a request
+* is completed by one engine, it may then queue a request
+* to a second via its execlists->tasklet *just* as we are
+* calling engine->init_hw() and also writing the ELSP.
+* Turning off the execlists->tasklet until the reset is over
+* prevents the race.
+*
+* Note that this needs to be a single atomic operation on the
+* tasklet (flush existing tasks, prevent new tasks) to prevent
+* a race between reset and set-wedged. It is not, so we do the best
+* we can atm and make sure we don't lock the machine up in the more
+* common case of recursively being called from set-wedged from inside
+* i915_reset.
+*/
+   if (!atomic_read(>tasklet.count))
+   tasklet_kill(>tasklet);
+   tasklet_disable(>tasklet);
+
+   /*
+* We're using worker to queue preemption requests from the tasklet in
+* GuC submission mode.
+* Even though tasklet was disabled, we may still have a worker queued.
+* Let's make sure that all workers scheduled before disabling the
+* tasklet are completed before continuing with the reset.
+*/
+   if (engine->i915->guc.preempt_wq)
+   flush_workqueue(engine->i915->guc.preempt_wq);
+
+   return i915_gem_find_active_request(engine);
+}
+
 /*
  * Everything below here is concerned with setup & teardown, and is
  * therefore not part of the somewhat time-critical batch-submission
@@ -1235,6 +1273,7 @@ int intel_guc_submission_enable(struct intel_guc *guc)
>execlists;
 
execlists->tasklet.func = guc_submission_tasklet;
+   engine->reset.prepare = guc_reset_prepare;
engine->park = guc_submission_park;
engine->unpark = guc_submission_unpark;
 
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index f662a9524233..e5a3ffbc273a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1688,16 +1688,6 @@ execlists_reset_prepare(struct intel_engine_cs *engine)
tasklet_kill(>tasklet);
tasklet_disable(>tasklet);
 
-   /*
-* We're using worker to queue preemption requests from the tasklet in
-* GuC submission mode.
-* Even though tasklet was disabled, we may still have a worker queued.
-* Let's make sure that all workers scheduled before disabling the
-* tasklet are completed before continuing with the reset.
-*/
-   if (engine->i915->guc.preempt_wq)
-   flush_workqueue(engine->i915->guc.preempt_wq);
-
return i915_gem_find_active_request(engine);
 }
 
@@ -2115,6 +2105,7 @@ static void execlists_set_default_submission(struct 
intel_engine_cs *engine)
engine->cancel_requests = execlists_cancel_requests;
engine->schedule = execlists_schedule;
engine->execlists.tasklet.func = execlists_submission_tasklet;
+   engine->reset.prepare = execlists_reset_prepare;
 
engine->park = NULL;
engine->unpark = NULL;
-- 
2.16.2

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 5/5] drm/i915/execlists: Flush pending preemption events during reset

[Chris Wilson]

Catch up with the inflight CSB events, after disabling the tasklet
before deciding which request was truly guilty of hanging the GPU.

Signed-off-by: Chris Wilson 
Cc: Michał Winiarski 
CC: Michel Thierry 
Cc: Jeff McGee 
---
 drivers/gpu/drm/i915/intel_lrc.c | 355 ++-
 1 file changed, 197 insertions(+), 158 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index e5a3ffbc273a..beb81f13a3cc 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -828,186 +828,192 @@ static void execlists_cancel_requests(struct 
intel_engine_cs *engine)
local_irq_restore(flags);
 }
 
-/*
- * Check the unread Context Status Buffers and manage the submission of new
- * contexts to the ELSP accordingly.
- */
-static void execlists_submission_tasklet(unsigned long data)
+static void process_csb(struct intel_engine_cs *engine)
 {
-   struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
struct intel_engine_execlists * const execlists = >execlists;
struct execlist_port * const port = execlists->port;
-   struct drm_i915_private *dev_priv = engine->i915;
+   struct drm_i915_private *i915 = engine->i915;
+   unsigned int head, tail;
+   const u32 *buf;
bool fw = false;
 
-   /* We can skip acquiring intel_runtime_pm_get() here as it was taken
-* on our behalf by the request (see i915_gem_mark_busy()) and it will
-* not be relinquished until the device is idle (see
-* i915_gem_idle_work_handler()). As a precaution, we make sure
-* that all ELSP are drained i.e. we have processed the CSB,
-* before allowing ourselves to idle and calling intel_runtime_pm_put().
-*/
-   GEM_BUG_ON(!dev_priv->gt.awake);
+   if (unlikely(execlists->csb_use_mmio)) {
+   buf = (u32 * __force)
+   (i915->regs + 
i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));
+   execlists->csb_head = -1; /* force mmio read of CSB ptrs */
+   } else {
+   /* The HWSP contains a (cacheable) mirror of the CSB */
+   buf = >status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
+   }
 
-   /* Prefer doing test_and_clear_bit() as a two stage operation to avoid
-* imposing the cost of a locked atomic transaction when submitting a
-* new request (outside of the context-switch interrupt).
+   /*
+* The write will be ordered by the uncached read (itself
+* a memory barrier), so we do not need another in the form
+* of a locked instruction. The race between the interrupt
+* handler and the split test/clear is harmless as we order
+* our clear before the CSB read. If the interrupt arrived
+* first between the test and the clear, we read the updated
+* CSB and clear the bit. If the interrupt arrives as we read
+* the CSB or later (i.e. after we had cleared the bit) the bit
+* is set and we do a new loop.
 */
-   while (test_bit(ENGINE_IRQ_EXECLIST, >irq_posted)) {
-   /* The HWSP contains a (cacheable) mirror of the CSB */
-   const u32 *buf =
-   >status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
-   unsigned int head, tail;
-
-   if (unlikely(execlists->csb_use_mmio)) {
-   buf = (u32 * __force)
-   (dev_priv->regs + 
i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));
-   execlists->csb_head = -1; /* force mmio read of CSB 
ptrs */
-   }
+   __clear_bit(ENGINE_IRQ_EXECLIST, >irq_posted);
+   if (unlikely(execlists->csb_head == -1)) { /* following a reset */
+   intel_uncore_forcewake_get(i915, execlists->fw_domains);
+   fw = true;
+
+   head = readl(i915->regs + 
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)));
+   tail = GEN8_CSB_WRITE_PTR(head);
+   head = GEN8_CSB_READ_PTR(head);
+   execlists->csb_head = head;
+   } else {
+   const int write_idx =
+   intel_hws_csb_write_index(i915) -
+   I915_HWS_CSB_BUF0_INDEX;
+
+   head = execlists->csb_head;
+   tail = READ_ONCE(buf[write_idx]);
+   }
+   GEM_TRACE("%s cs-irq head=%d [%d%s], tail=%d [%d%s]\n",
+ engine->name,
+ head, GEN8_CSB_READ_PTR(readl(i915->regs + 
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine, fw ? "" : "?",
+ tail, GEN8_CSB_WRITE_PTR(readl(i915->regs + 
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine, fw ? "" : "?");
+
+   while (head != tail) {
+   struct i915_request *rq;
+

Re: [Intel-gfx] [PATCH] drm/i915/guc: Don't try to enable GuC logging when we're not using GuC

[Chris Wilson]

Quoting Michał Winiarski (2018-03-20 00:13:37)
> When changing the default values for guc_log_level, we accidentally left
> the log enabled on non-guc platforms. Let's fix that.
> 
> Fixes: 9605d1ce7c6b ("drm/i915/guc: Default to non-verbose GuC logging")
> Reported-by: Chris Wilson 
> Signed-off-by: Michał Winiarski 
> Cc: Chris Wilson 
> Cc: Sagar Arun Kamble 
> Cc: Michal Wajdeczko 
> ---
>  drivers/gpu/drm/i915/intel_uc.c | 13 -
>  1 file changed, 8 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
> index 34e847d0ee4c..eb6667c7cd23 100644
> --- a/drivers/gpu/drm/i915/intel_uc.c
> +++ b/drivers/gpu/drm/i915/intel_uc.c
> @@ -69,14 +69,17 @@ static int __get_platform_enable_guc(struct 
> drm_i915_private *dev_priv)
>  
>  static int __get_default_guc_log_level(struct drm_i915_private *dev_priv)
>  {
> -   int guc_log_level = 1; /* non-verbose */
> +   int guc_log_level;
>  
> -   /* Enable if we're running on platform with GuC and debug config */
> -   if (HAS_GUC(dev_priv) && intel_uc_is_using_guc() &&
> -   (IS_ENABLED(CONFIG_DRM_I915_DEBUG) ||
> -IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)))
> +   if (!HAS_GUC(dev_priv) || !intel_uc_is_using_guc())
> +   guc_log_level = 0; /* disabled */
> +   else if (IS_ENABLED(CONFIG_DRM_I915_DEBUG) ||
> +IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
> +   /* Use full verbosity on platform with GuC and debug config */
> guc_log_level =
> GUC_VERBOSITY_TO_LOG_LEVEL(GUC_LOG_VERBOSITY_MAX);
guc_log_level = GUC_LOG_LEVEL_MAX;

#define GUC_LOG_LEVEL_MAX GUC_VERBOSITY_TO_LOG_LEVEL(GUC_LOG_VERBOSITY_MAX)

in passing?
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH] drm/i915/guc: Don't try to enable GuC logging when we're not using GuC

[Michał Winiarski]

When changing the default values for guc_log_level, we accidentally left
the log enabled on non-guc platforms. Let's fix that.

Fixes: 9605d1ce7c6b ("drm/i915/guc: Default to non-verbose GuC logging")
Reported-by: Chris Wilson 
Signed-off-by: Michał Winiarski 
Cc: Chris Wilson 
Cc: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
---
 drivers/gpu/drm/i915/intel_uc.c | 13 -
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 34e847d0ee4c..eb6667c7cd23 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -69,14 +69,17 @@ static int __get_platform_enable_guc(struct 
drm_i915_private *dev_priv)
 
 static int __get_default_guc_log_level(struct drm_i915_private *dev_priv)
 {
-   int guc_log_level = 1; /* non-verbose */
+   int guc_log_level;
 
-   /* Enable if we're running on platform with GuC and debug config */
-   if (HAS_GUC(dev_priv) && intel_uc_is_using_guc() &&
-   (IS_ENABLED(CONFIG_DRM_I915_DEBUG) ||
-IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)))
+   if (!HAS_GUC(dev_priv) || !intel_uc_is_using_guc())
+   guc_log_level = 0; /* disabled */
+   else if (IS_ENABLED(CONFIG_DRM_I915_DEBUG) ||
+IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
+   /* Use full verbosity on platform with GuC and debug config */
guc_log_level =
GUC_VERBOSITY_TO_LOG_LEVEL(GUC_LOG_VERBOSITY_MAX);
+   else
+   guc_log_level = 1; /* non-verbose */
 
/* Any platform specific fine-tuning can be done here */
 
-- 
2.14.3

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915: Disable some extra clang warnings (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Disable some extra clang warnings (rev2)
URL   : https://patchwork.freedesktop.org/series/40145/
State : warning

== Summary ==

 Possible new issues:

Test drv_suspend:
Subgroup forcewake:
pass   -> SKIP   (shard-snb)
Test kms_vblank:
Subgroup pipe-a-ts-continuation-suspend:
pass   -> SKIP   (shard-snb)

 Known issues:

Test kms_flip:
Subgroup 2x-flip-vs-expired-vblank-interruptible:
pass   -> FAIL   (shard-hsw) fdo#102887
Subgroup flip-vs-absolute-wf_vblank-interruptible:
fail   -> PASS   (shard-hsw) fdo#100368
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-primscrn-pri-shrfb-draw-render:
pass   -> FAIL   (shard-apl) fdo#101623
Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-hsw) fdo#99912 +1
Test kms_sysfs_edid_timing:
warn   -> PASS   (shard-apl) fdo#100047

fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047

shard-apltotal:3478 pass:1815 dwarn:1   dfail:0   fail:7   skip:1655 
time:13086s
shard-hswtotal:3478 pass:1767 dwarn:1   dfail:0   fail:2   skip:1707 
time:11721s
shard-snbtotal:3478 pass:1356 dwarn:1   dfail:0   fail:2   skip:2119 
time:7194s
Blacklisted hosts:
shard-kbltotal:3386 pass:1863 dwarn:31  dfail:0   fail:9   skip:1482 
time:9607s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8403/shards.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/cnl: Implement 
WaProgramMgsrForCorrectSliceSpecificMmioReads
URL   : https://patchwork.freedesktop.org/series/40233/
State : warning

== Summary ==

Series 40233v1 series starting with [1/2] drm/i915/cnl: Implement 
WaProgramMgsrForCorrectSliceSpecificMmioReads
https://patchwork.freedesktop.org/api/1.0/series/40233/revisions/1/mbox/

 Possible new issues:

Test gem_busy:
Subgroup basic-hang-default:
pass   -> DMESG-WARN (fi-cnl-drrs)
Test gem_exec_fence:
Subgroup await-hang-default:
pass   -> DMESG-WARN (fi-cnl-drrs)
Test gem_exec_suspend:
Subgroup basic-s4-devices:
pass   -> DMESG-WARN (fi-cnl-drrs)
Test gem_ringfill:
Subgroup basic-default-hang:
pass   -> DMESG-WARN (fi-cnl-drrs)

 Known issues:

Test debugfs_test:
Subgroup read_all_entries:
incomplete -> PASS   (fi-snb-2520m) fdo#103713
Test gem_exec_suspend:
Subgroup basic-s3:
pass   -> DMESG-WARN (fi-cnl-drrs) fdo#105086
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass   -> DMESG-WARN (fi-cnl-drrs) k.org#198519 +2

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#105086 https://bugs.freedesktop.org/show_bug.cgi?id=105086
k.org#198519 https://bugzilla.kernel.org/show_bug.cgi?id=198519

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:433s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:442s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:379s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:535s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:298s
fi-bxt-dsi   total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  
time:510s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:511s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:512s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:503s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:410s
fi-cfl-s2total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:582s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:511s
fi-cnl-drrs  total:285  pass:246  dwarn:11  dfail:0   fail:0   skip:28  
time:523s
fi-elk-e7500 total:285  pass:225  dwarn:1   dfail:0   fail:0   skip:59  
time:429s
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:320s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:533s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:400s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:419s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:464s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:429s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:475s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:465s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:516s
fi-pnv-d510  total:285  pass:219  dwarn:1   dfail:0   fail:0   skip:65  
time:657s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:444s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:528s
fi-skl-6700hqtotal:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:541s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:505s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:483s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:427s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:445s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:601s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:399s

9280bf159e350e78fb19db3d76deca4be7f083c8 drm-tip: 2018y-03m-19d-21h-23m-32s UTC 
integration manifest
254d3c903a5e drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads
e6a22b973125 drm/i915/cnl: Implement 
WaProgramMgsrForCorrectSliceSpecificMmioReads

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8404/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/cnl: Implement 
WaProgramMgsrForCorrectSliceSpecificMmioReads
URL   : https://patchwork.freedesktop.org/series/40233/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
e6a22b973125 drm/i915/cnl: Implement 
WaProgramMgsrForCorrectSliceSpecificMmioReads
-:39: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 
sseu->slice_mask
#39: FILE: drivers/gpu/drm/i915/intel_engine_cs.c:802:
+   u32 slice = find_last_bit((unsigned long *)&(sseu->slice_mask),

-:41: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 
sseu->subslice_mask[slice]
#41: FILE: drivers/gpu/drm/i915/intel_engine_cs.c:804:
+   u32 subslice = find_last_bit((unsigned long 
*)&(sseu->subslice_mask[slice]),

total: 0 errors, 0 warnings, 2 checks, 71 lines checked
254d3c903a5e drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads
-:55: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 
sseu->slice_mask
#55: FILE: drivers/gpu/drm/i915/intel_engine_cs.c:827:
+   slice = find_last_bit((unsigned long *)&(sseu->slice_mask),

-:56: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#56: FILE: drivers/gpu/drm/i915/intel_engine_cs.c:828:
+   slice = find_last_bit((unsigned long *)&(sseu->slice_mask),
+  sizeof(sseu->slice_mask));

-:60: CHECK:SPACING: spaces preferred around that '>>' (ctx:VxV)
#60: FILE: drivers/gpu/drm/i915/intel_engine_cs.c:832:
+  | 
sseu->subslice_mask[slice]>>GEN10_L3BANK_PAIR_COUNT)
   ^

total: 0 errors, 0 warnings, 3 checks, 36 lines checked

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: make GEM_WARN_ON less terrible

[Patchwork]

== Series Details ==

Series: drm/i915: make GEM_WARN_ON less terrible
URL   : https://patchwork.freedesktop.org/series/40215/
State : success

== Summary ==

 Known issues:

Test kms_flip:
Subgroup flip-vs-absolute-wf_vblank-interruptible:
fail   -> PASS   (shard-hsw) fdo#100368
Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-hsw) fdo#99912 +1
Test kms_sysfs_edid_timing:
warn   -> PASS   (shard-apl) fdo#100047

fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047

shard-apltotal:3478 pass:1816 dwarn:1   dfail:0   fail:6   skip:1655 
time:13013s
shard-hswtotal:3478 pass:1768 dwarn:1   dfail:0   fail:1   skip:1707 
time:11719s
shard-snbtotal:3478 pass:1358 dwarn:1   dfail:0   fail:2   skip:2117 
time:7253s
Blacklisted hosts:
shard-kbltotal:3478 pass:1911 dwarn:29  dfail:0   fail:8   skip:1530 
time:9843s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8401/shards.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915/gvt/scheduler: fix potential NULL pointer dereference

[Gustavo A. R. Silva]

On 03/19/2018 04:23 PM, Chris Wilson wrote:

Quoting Gustavo A. R. Silva (2018-03-19 20:50:12)

Hi Chris,

On 03/19/2018 03:38 PM, Chris Wilson wrote:

Quoting Gustavo A. R. Silva (2018-03-19 19:30:53)

_workload_ is being dereferenced before it is null checked, hence
there is a potential null pointer dereference.

Fix this by moving the pointer dereference after _workload_ has
been null checked.


The checks are misleading and not required.


All of them?

if (!workload || !reg_state || workload->ring_id != RCS)
 return;


workload can not be NULL (dereference in caller), reg_state can not be
NULL (by construct from kmap()).

It may be not an RCS ring through


I got it.

I'll send the following patch then:

--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -74,7 +74,7 @@ static void sr_oa_regs(struct intel_vgpu_workload 
*workload,

i915_mmio_reg_offset(EU_PERF_CNTL6),
};

-   if (!workload || !reg_state || workload->ring_id != RCS)
+   if(workload->ring_id != RCS)
return;

if (save) {


Thanks
--
Gustavo






___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads

[Chris Wilson]

Quoting Yunwei Zhang (2018-03-19 21:50:08)
> +   /* If more than one slice are enabled, L3Banks should be all enabled 
> */
> +   if (hweight8(sseu->slice_mask) == 1) {

if (is_power_of_two(sseu->slice_mask))
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

[Chris Wilson]

Quoting Yunwei Zhang (2018-03-19 21:50:07)
> WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
> read into Slice/Subslice specific registers, MCR packet control
> register(0xFDC) needs to be programmed to point to any enabled
> slice/subslice pair. Otherwise, incorrect value will be returned.
> 
> However, that means each subsequent MMIO read will be forwarded to a
> specific slice/subslice combination as read is unicast. This is OK since
> slice/subslice specific register values are consistent in almost all cases
> across slice/subslice. There are rare occasions such as INSTDONE that this
> value will be dependent on slice/subslice combo, in such cases, we need to
> program 0xFDC and recover this after. This is already covered by
> read_subslice_reg for INSTDONE.
> 
> Also, 0xFDC will lose its information after TDR/engine reset/power state
> change.
> 
> Signed-off-by: Yunwei Zhang 
> Cc: Oscar Mateo 
> Cc: Michel Thierry 
> Cc: Joonas Lahtinen 
> ---
>  drivers/gpu/drm/i915/intel_engine_cs.c | 43 
> --
>  1 file changed, 41 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
> b/drivers/gpu/drm/i915/intel_engine_cs.c
> index a2b1e9e..bc8fed7 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -781,6 +781,29 @@ const char *i915_cache_level_str(struct drm_i915_private 
> *i915, int type)
> }
>  }
>  
> +static u32 calculate_mcr(u32 mcr, struct drm_i915_private *dev_priv)
> +{
> +   const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);

INTEL_SSEU(dev_priv);

> +   u32 slice = find_last_bit((unsigned long *)&(sseu->slice_mask),
> +  sizeof(sseu->slice_mask));
> +   u32 subslice = find_last_bit((unsigned long 
> *)&(sseu->subslice_mask[slice]),
> + sizeof(sseu->subslice_mask[0]));

You seem to have mispelt fls().

Or send a patch to convert find_last_bit() into fls() for known small
sizes.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 1/2] drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

[Yunwei Zhang]

WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
read into Slice/Subslice specific registers, MCR packet control
register(0xFDC) needs to be programmed to point to any enabled
slice/subslice pair. Otherwise, incorrect value will be returned.

However, that means each subsequent MMIO read will be forwarded to a
specific slice/subslice combination as read is unicast. This is OK since
slice/subslice specific register values are consistent in almost all cases
across slice/subslice. There are rare occasions such as INSTDONE that this
value will be dependent on slice/subslice combo, in such cases, we need to
program 0xFDC and recover this after. This is already covered by
read_subslice_reg for INSTDONE.

Also, 0xFDC will lose its information after TDR/engine reset/power state
change.

Signed-off-by: Yunwei Zhang 
Cc: Oscar Mateo 
Cc: Michel Thierry 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/intel_engine_cs.c | 43 --
 1 file changed, 41 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index a2b1e9e..bc8fed7 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -781,6 +781,29 @@ const char *i915_cache_level_str(struct drm_i915_private 
*i915, int type)
}
 }
 
+static u32 calculate_mcr(u32 mcr, struct drm_i915_private *dev_priv)
+{
+   const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);
+   u32 slice = find_last_bit((unsigned long *)&(sseu->slice_mask),
+  sizeof(sseu->slice_mask));
+   u32 subslice = find_last_bit((unsigned long 
*)&(sseu->subslice_mask[slice]),
+ sizeof(sseu->subslice_mask[0]));
+
+   mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
+   mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
+
+   return mcr;
+}
+
+static void wa_init_mcr(struct drm_i915_private *dev_priv)
+{
+   u32 mcr;
+
+   mcr = I915_READ(GEN8_MCR_SELECTOR);
+   mcr = calculate_mcr(mcr, dev_priv);
+   I915_WRITE(GEN8_MCR_SELECTOR, mcr);
+}
+
 static inline uint32_t
 read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
  int subslice, i915_reg_t reg)
@@ -799,18 +822,31 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int 
slice,
intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
 
mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
+
/*
 * The HW expects the slice and sublice selectors to be reset to 0
 * after reading out the registers.
 */
-   WARN_ON_ONCE(mcr & (GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK));
+   if (INTEL_GEN(dev_priv) < 10)
+   WARN_ON_ONCE(mcr & (GEN8_MCR_SLICE_MASK |
+GEN8_MCR_SUBSLICE_MASK));
+
mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
 
ret = I915_READ_FW(reg);
 
-   mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
+   /*
+* WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl
+* expects mcr to be programed to a enabled slice/subslice pair
+* before any MMIO read into slice/subslice register
+*/
+   if (INTEL_GEN(dev_priv) < 10)
+   mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
+   else
+   mcr = calculate_mcr(mcr, dev_priv);
+
I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
 
intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
@@ -1278,6 +1314,9 @@ static int cnl_init_workarounds(struct intel_engine_cs 
*engine)
struct drm_i915_private *dev_priv = engine->i915;
int ret;
 
+   /* WaProgramMgsrForCorrectSliceSpecificMmioReads: cnl */
+   wa_init_mcr(dev_priv);
+
/* WaDisableI2mCycleOnWRPort:cnl (pre-prod) */
if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))
I915_WRITE(GAMT_CHKN_BIT_REG,
-- 
2.7.4

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 2/2] drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads

[Yunwei Zhang]

L3Bank could be fused off in hardware for debug purpose, and it
is possible that subslice is enabled while its corresponding L3Bank pairs
are disabled. In such case, if MCR packet control register(0xFDC) is
programed to point to a disabled bank pair, a MMIO read into L3Bank range
will return 0 instead of correct values.

However, this is not going to be the case in any production silicon.
Therefore, we only check at initialization and issue a warning should
this really happen.

Signed-off-by: Yunwei Zhang 
Cc: Oscar Mateo 
Cc: Michel Thierry 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_reg.h|  4 
 drivers/gpu/drm/i915/intel_engine_cs.c | 19 +++
 2 files changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index abdc513..b283427 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2849,6 +2849,10 @@ enum i915_power_well_id {
 #define   GEN10_F2_SS_DIS_SHIFT18
 #define   GEN10_F2_SS_DIS_MASK (0xf << GEN10_F2_SS_DIS_SHIFT)
 
+#defineGEN10_MIRROR_FUSE3  _MMIO(0x9118)
+#define GEN10_L3BANK_PAIR_COUNT 4
+#define GEN10_L3BANK_MASK   0x0F
+
 #define GEN8_EU_DISABLE0   _MMIO(0x9134)
 #define   GEN8_EU_DIS0_S0_MASK 0xff
 #define   GEN8_EU_DIS0_S1_SHIFT24
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index bc8fed7..c17d2d5 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -798,7 +798,26 @@ static u32 calculate_mcr(u32 mcr, struct drm_i915_private 
*dev_priv)
 static void wa_init_mcr(struct drm_i915_private *dev_priv)
 {
u32 mcr;
+   u32 fuse3;
+   const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu);
+   u32 slice;
 
+   /* If more than one slice are enabled, L3Banks should be all enabled */
+   if (hweight8(sseu->slice_mask) == 1) {
+   /*
+* WaProgramMgsrForL3BankSpecificMmioReads:
+* read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
+* enabled subslice, no need to redirect MCR packet
+*/
+   slice = find_last_bit((unsigned long *)&(sseu->slice_mask),
+  sizeof(sseu->slice_mask));
+   fuse3 = I915_READ(GEN10_MIRROR_FUSE3);
+   if (WARN_ON(!((fuse3 & GEN10_L3BANK_MASK)
+  & ((sseu->subslice_mask[slice]
+  | 
sseu->subslice_mask[slice]>>GEN10_L3BANK_PAIR_COUNT)
+  & GEN10_L3BANK_MASK
+   DRM_WARN("Real silicon should have matched L3Bank and 
subslice enabled\n");
+   }
mcr = I915_READ(GEN8_MCR_SELECTOR);
mcr = calculate_mcr(mcr, dev_priv);
I915_WRITE(GEN8_MCR_SELECTOR, mcr);
-- 
2.7.4

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Reword warning for missing cases (rev2)

[Lucas De Marchi]

CCing checkpatch maintainers

On Mon, Mar 19, 2018 at 06:36:16PM +, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915: Reword warning for missing cases (rev2)
> URL   : https://patchwork.freedesktop.org/series/39821/
> State : warning
> 
> == Summary ==
> 
> $ dim checkpatch origin/drm-tip
> 7cb94d2c3c47 drm/i915: Reword warning for missing cases
> -:40: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'x' - possible side-effects?
> #40: FILE: drivers/gpu/drm/i915/i915_utils.h:43:
> +#define MISSING_CASE(x) WARN(1, "Missing case (%s == %ld)\n", \
> +  __stringify(x), (long)(x))

checkpatch seems wrong here since __stringify() doesn't evaluate x. And
it looks similar to the one fixed by
e942e2c3f7e0 ("checkpatch: fix stringification macro defect")


Lucas De Marchi


> 
> total: 0 errors, 0 warnings, 1 checks, 10 lines checked
> 
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH v2] drm/i915: Reword warning for missing cases

[Chris Wilson]

Quoting Lucas De Marchi (2018-03-19 17:37:20)
> In some places we end up converting switch statements to a series of
> if/else, particularly when introducing helper functions to handle a
> group of cases. It's tempting to either leave a wrong warning (since now
> we don't have a switch case anymore) or to convert to WARN(1, ...),
> but we can just provide a better message and avoid the doubt when such
> conversions arrise.
> 
> Introducing a warning inside i915_driver_load() just for tests we get:
> 
> [ 4535.233717] Missing case (ret == 0)
> [ 4535.233868] WARNING: CPU: 1 PID: 795 at 
> drivers/gpu/drm/i915/i915_drv.c:1341 i915_driver_load+0x42/0x10e0 [i915]
> 
> which is clear enough.
> 
> v2: remove __func__ since this is already on the warning.
> 
> Cc: Chris Wilson 
> Cc: Ville Syrjälä 
> Cc: Daniel Vetter 
> Signed-off-by: Lucas De Marchi 
Reviewed-by: Chris Wilson 
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915/gvt/scheduler: fix potential NULL pointer dereference

[Gustavo A. R. Silva]

Hi Chris,

On 03/19/2018 03:38 PM, Chris Wilson wrote:

Quoting Gustavo A. R. Silva (2018-03-19 19:30:53)

_workload_ is being dereferenced before it is null checked, hence
there is a potential null pointer dereference.

Fix this by moving the pointer dereference after _workload_ has
been null checked.


The checks are misleading and not required.


All of them?

if (!workload || !reg_state || workload->ring_id != RCS)
return;

or just the null check on workload ?

Thanks for the feedback.
--
Gustavo

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915/gvt/scheduler: fix potential NULL pointer dereference

[Chris Wilson]

Quoting Gustavo A. R. Silva (2018-03-19 20:50:12)
> Hi Chris,
> 
> On 03/19/2018 03:38 PM, Chris Wilson wrote:
> > Quoting Gustavo A. R. Silva (2018-03-19 19:30:53)
> >> _workload_ is being dereferenced before it is null checked, hence
> >> there is a potential null pointer dereference.
> >>
> >> Fix this by moving the pointer dereference after _workload_ has
> >> been null checked.
> > 
> > The checks are misleading and not required.
> 
> All of them?
> 
> if (!workload || !reg_state || workload->ring_id != RCS)
> return;

workload can not be NULL (dereference in caller), reg_state can not be
NULL (by construct from kmap()).

It may be not an RCS ring through.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915: Promote .format_mod_supported() to the lead role

[Ville Syrjälä]

On Mon, Mar 19, 2018 at 09:17:16PM -, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915: Promote .format_mod_supported() to the lead role
> URL   : https://patchwork.freedesktop.org/series/40207/
> State : warning
> 
> == Summary ==
> 
>  Possible new issues:
> 
> Test kms_vblank:
> Subgroup pipe-a-ts-continuation-suspend:
> pass   -> SKIP   (shard-snb)

Test requirement not met in function suspend_via_rtcwake, file 
../lib/igt_aux.c:803:
Test requirement: ret == 0
rtcwake test failed with 1
This failure could mean that something is wrong with the rtcwake tool or how 
your distro is set up.
Last errno: 25, Inappropriate ioctl for device

> 
>  Known issues:
> 
> Test kms_flip:
> Subgroup dpms-vs-vblank-race:
> pass   -> FAIL   (shard-hsw) fdo#103060
> Subgroup flip-vs-absolute-wf_vblank-interruptible:
> fail   -> PASS   (shard-hsw) fdo#100368 +1
> Test kms_setmode:
> Subgroup basic:
> pass   -> FAIL   (shard-hsw) fdo#99912
> 
> fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
> fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
> fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
> 
> shard-apltotal:3478 pass:1814 dwarn:1   dfail:0   fail:7   skip:1655 
> time:13028s
> shard-hswtotal:3478 pass:1766 dwarn:1   dfail:0   fail:3   skip:1707 
> time:11744s
> shard-snbtotal:3478 pass:1357 dwarn:1   dfail:0   fail:2   skip:2118 
> time:7230s
> Blacklisted hosts:
> shard-kbltotal:3478 pass:1939 dwarn:1   dfail:0   fail:9   skip:1529 
> time:9804s
> 
> == Logs ==
> 
> For more details see: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8399/shards.html

-- 
Ville Syrjälä
Intel OTC
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915: Promote .format_mod_supported() to the lead role

[Patchwork]

== Series Details ==

Series: drm/i915: Promote .format_mod_supported() to the lead role
URL   : https://patchwork.freedesktop.org/series/40207/
State : warning

== Summary ==

 Possible new issues:

Test kms_vblank:
Subgroup pipe-a-ts-continuation-suspend:
pass   -> SKIP   (shard-snb)

 Known issues:

Test kms_flip:
Subgroup dpms-vs-vblank-race:
pass   -> FAIL   (shard-hsw) fdo#103060
Subgroup flip-vs-absolute-wf_vblank-interruptible:
fail   -> PASS   (shard-hsw) fdo#100368 +1
Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-hsw) fdo#99912

fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912

shard-apltotal:3478 pass:1814 dwarn:1   dfail:0   fail:7   skip:1655 
time:13028s
shard-hswtotal:3478 pass:1766 dwarn:1   dfail:0   fail:3   skip:1707 
time:11744s
shard-snbtotal:3478 pass:1357 dwarn:1   dfail:0   fail:2   skip:2118 
time:7230s
Blacklisted hosts:
shard-kbltotal:3478 pass:1939 dwarn:1   dfail:0   fail:9   skip:1529 
time:9804s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8399/shards.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH i-g-t 4/5] tests/perf_pmu: Add tests for engine queued/runnable/running stats

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-03-19 18:22:04)
> From: Tvrtko Ursulin 
> 
> Simple tests to check reported queue depths are correct.
> 
> Signed-off-by: Tvrtko Ursulin 
> ---
>  tests/perf_pmu.c | 224 
> +++
>  1 file changed, 224 insertions(+)
> 
> diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
> index 469b9becdbac..206c18960b7b 100644
> --- a/tests/perf_pmu.c
> +++ b/tests/perf_pmu.c
> @@ -966,6 +966,196 @@ multi_client(int gem_fd, const struct 
> intel_execution_engine2 *e)
> assert_within_epsilon(val[1], perf_slept[1], tolerance);
>  }
>  
> +static double calc_queued(uint64_t d_val, uint64_t d_ns)
> +{
> +   return (double)d_val * 1e9 / I915_SAMPLE_QUEUED_DIVISOR / d_ns;
> +}
> +
> +static void
> +queued(int gem_fd, const struct intel_execution_engine2 *e)
> +{
> +   const unsigned long engine = e2ring(gem_fd, e);
> +   const unsigned int max_rq = 10;
> +   double queued[max_rq + 1];
> +   uint32_t bo[max_rq + 1];
> +   unsigned int n, i;
> +   uint64_t val[2];
> +   uint64_t ts[2];
> +   int fd;

igt_require_sw_sync();

I guess we should do igt_require_cork(CORK_SYNC_FD) or something like
that.

> +
> +   memset(queued, 0, sizeof(queued));
> +   memset(bo, 0, sizeof(bo));
> +
> +   fd = open_pmu(I915_PMU_ENGINE_QUEUED(e->class, e->instance));
> +
> +   for (n = 0; n <= max_rq; n++) {
> +   int fence = -1;
> +   struct igt_cork cork = { .fd = fence, .type = CORK_SYNC_FD };

IGT_CORK_FENCE(cork); if you prefer

> +
> +   gem_quiescent_gpu(gem_fd);
> +
> +   if (n)
> +   fence = igt_cork_plug(, -1);
> +
> +   for (i = 0; i < n; i++) {
> +   struct drm_i915_gem_exec_object2 obj = { };
> +   struct drm_i915_gem_execbuffer2 eb = { };
> +
> +   if (!bo[i]) {
> +   const uint32_t bbe = MI_BATCH_BUFFER_END;
> +
> +   bo[i] = gem_create(gem_fd, 4096);
> +   gem_write(gem_fd, bo[i], 4092, ,
> + sizeof(bbe));
> +   }
> +
> +   obj.handle = bo[i];

Looks like you can use just the one handle multiple times?

> +
> +   eb.buffer_count = 1;
> +   eb.buffers_ptr = to_user_pointer();
> +
> +   eb.flags = engine | I915_EXEC_FENCE_IN;
> +   eb.rsvd2 = fence;

You do however also want to check with one context per execbuf.

if (flags & CONTEXTS)
eb.rsvd1 = gem_context_create(fd);
> +
> +   gem_execbuf(gem_fd, );

if (flags & CONTEXTS)
gem_context_destroy(fd, eb.rsvd1);
eb.rsvd1 = gem_context_create();

> +   }
> +
> +   val[0] = __pmu_read_single(fd, [0]);
> +   usleep(batch_duration_ns / 1000);
> +   val[1] = __pmu_read_single(fd, [1]);
> +
> +   queued[n] = calc_queued(val[1] - val[0], ts[1] - ts[0]);
> +   igt_info("n=%u queued=%.2f\n", n, queued[n]);
> +
> +   if (fence >= 0)
> +   igt_cork_unplug();

Maybe we should just make this a no-op when used on an unplugged cork.

> +
> +   for (i = 0; i < n; i++)
> +   gem_sync(gem_fd, bo[i]);
> +   }
> +
> +   close(fd);
> +
> +   for (i = 0; i < max_rq; i++) {
> +   if (bo[i])
> +   gem_close(gem_fd, bo[i]);
> +   }
> +
> +   for (i = 0; i <= max_rq; i++)
> +   assert_within_epsilon(queued[i], i, tolerance);
> +}
> +
> +static void
> +runnable(int gem_fd, const struct intel_execution_engine2 *e)
> +{
> +   const unsigned long engine = e2ring(gem_fd, e);
> +   const unsigned int max_rq = 10;
> +   igt_spin_t *spin[max_rq + 1];
> +   double runnable[max_rq + 1];
> +   uint32_t ctx[max_rq];
> +   unsigned int n, i;
> +   uint64_t val[2];
> +   uint64_t ts[2];
> +   int fd;
> +
> +   memset(runnable, 0, sizeof(runnable));
> +   memset(ctx, 0, sizeof(ctx));
> +
> +   fd = open_pmu(I915_PMU_ENGINE_RUNNABLE(e->class, e->instance));
> +
> +   for (n = 0; n <= max_rq; n++) {
> +   gem_quiescent_gpu(gem_fd);
> +
> +   for (i = 0; i < n; i++) {
> +   if (!ctx[i])
> +   ctx[i] = gem_context_create(gem_fd);
> +
> +   if (i == 0)
> +   spin[i] = __spin_poll(gem_fd, ctx[i], engine);
> +   else
> +   spin[i] = __igt_spin_batch_new(gem_fd, ctx[i],
> +  engine, 0);
> +   }
> +
> +   if (n)
> +   

[Intel-gfx] ✗ Fi.CI.IGT: warning for series starting with [v3,1/3] drm/i915/guc: Unify naming of private GuC action functions

[Patchwork]

== Series Details ==

Series: series starting with [v3,1/3] drm/i915/guc: Unify naming of private GuC 
action functions
URL   : https://patchwork.freedesktop.org/series/40204/
State : warning

== Summary ==

 Possible new issues:

Test drv_suspend:
Subgroup forcewake:
pass   -> SKIP   (shard-snb)

 Known issues:

Test kms_cursor_legacy:
Subgroup 2x-long-flip-vs-cursor-legacy:
pass   -> FAIL   (shard-hsw) fdo#104873
Test kms_flip:
Subgroup dpms-vs-vblank-race:
pass   -> FAIL   (shard-hsw) fdo#103060
Subgroup flip-vs-absolute-wf_vblank-interruptible:
fail   -> PASS   (shard-hsw) fdo#100368 +1
Subgroup flip-vs-expired-vblank-interruptible:
pass   -> FAIL   (shard-hsw) fdo#102887
Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-hsw) fdo#99912

fdo#104873 https://bugs.freedesktop.org/show_bug.cgi?id=104873
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912

shard-apltotal:3478 pass:1814 dwarn:1   dfail:0   fail:7   skip:1655 
time:13112s
shard-hswtotal:3478 pass:1764 dwarn:1   dfail:0   fail:5   skip:1707 
time:11708s
shard-snbtotal:3478 pass:1357 dwarn:1   dfail:0   fail:2   skip:2118 
time:7243s
Blacklisted hosts:
shard-kbltotal:3478 pass:1933 dwarn:1   dfail:0   fail:10  skip:1534 
time:9863s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8398/shards.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915/gvt/scheduler: fix potential NULL pointer dereference

[Chris Wilson]

Quoting Gustavo A. R. Silva (2018-03-19 19:30:53)
> _workload_ is being dereferenced before it is null checked, hence
> there is a potential null pointer dereference.
> 
> Fix this by moving the pointer dereference after _workload_ has
> been null checked.

The checks are misleading and not required.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915: make GEM_WARN_ON less terrible

[Jani Nikula]

On Mon, 19 Mar 2018, Matthew Auld  wrote:
> On 19 March 2018 at 18:17, Chris Wilson  wrote:
>> Quoting Matthew Auld (2018-03-19 18:08:54)
>>> GEM_WARN_ON() was originally intended to be used only as:
>>>
>>>if (GEM_WARN_ON(expr))
>>> ...
>>>
>>> but it just so happens to also work as simply:
>>>
>>>GEM_WARN_ON(expr);
>>>
>>> since it just wraps WARN_ON, which is a little misleading since for
>>> !DRM_I915_DEBUG_GEM builds the second case will actually break the
>>> build. Given that there are some patches floating around which seem to
>>> miss this, it probably makes sense to just make it work for both cases.
>>
>> That really was quite intentional. The only time to use GEM_WARN_ON() is
>> inside an if, otherwise what's the point?
>
> Why wouldn't we want it to behave like WARN_ON? That seems to be what
> people expect, since it does wrap WARN_ON, and we don't always use
> WARN_ON in an if...

Looking at this, I'm more baffled by GEM_WARN_ON() evaluating to expr on
CONFIG_DRM_I915_DEBUG_GEM=y and 0 otherwise. That's the seriously
misleading part here.

Are you sure all those if (GEM_WARN_ON(expr)) are to be ignored? I'm no
expert on gem code, but I could be easily persuaded to believe not.


BR,
Jani.

PS. On the original question, if you design GEM_WARN_ON() to be used
within if conditions only, I think you better squeeze in an inline
function with __must_check.


-- 
Jani Nikula, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Disable some extra clang warnings (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Disable some extra clang warnings (rev2)
URL   : https://patchwork.freedesktop.org/series/40145/
State : success

== Summary ==

Series 40145v2 drm/i915: Disable some extra clang warnings
https://patchwork.freedesktop.org/api/1.0/series/40145/revisions/2/mbox/

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:436s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:444s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:385s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:550s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:296s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:515s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:516s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:502s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:410s
fi-cfl-s2total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:586s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:509s
fi-cnl-drrs  total:285  pass:254  dwarn:3   dfail:0   fail:0   skip:28  
time:532s
fi-elk-e7500 total:285  pass:225  dwarn:1   dfail:0   fail:0   skip:59  
time:421s
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:312s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:536s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:406s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:420s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:462s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:429s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:475s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:468s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:514s
fi-pnv-d510  total:285  pass:219  dwarn:1   dfail:0   fail:0   skip:65  
time:653s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:438s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:533s
fi-skl-6700hqtotal:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:541s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:503s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:485s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:432s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:441s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:587s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:396s

260af42eeff094e4768265a6ec8bbcb29b87e9a0 drm-tip: 2018y-03m-19d-17h-15m-08s UTC 
integration manifest
6f7316e384a1 drm/i915: Disable some extra clang warnings

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8403/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Disable some extra clang warnings (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Disable some extra clang warnings (rev2)
URL   : https://patchwork.freedesktop.org/series/40145/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/i915: Disable some extra clang warnings
-
+drivers/gpu/drm/i915/gvt/gtt.c:661:9:expected void [noderef] **slot
+drivers/gpu/drm/i915/gvt/gtt.c:661:9:expected void **slot
+drivers/gpu/drm/i915/gvt/gtt.c:661:9:expected void **slot
+drivers/gpu/drm/i915/gvt/gtt.c:661:9:expected void **slot
+drivers/gpu/drm/i915/gvt/gtt.c:661:9:got void [noderef] **
+drivers/gpu/drm/i915/gvt/gtt.c:661:9:got void [noderef] **
+drivers/gpu/drm/i915/gvt/gtt.c:661:9:got void [noderef] **
+drivers/gpu/drm/i915/gvt/gtt.c:661:9:got void **slot
+drivers/gpu/drm/i915/gvt/gtt.c:661:9: warning: incorrect type in argument 1 
(different address spaces)
+drivers/gpu/drm/i915/gvt/gtt.c:661:9: warning: incorrect type in assignment 
(different address spaces)
+drivers/gpu/drm/i915/gvt/gtt.c:661:9: warning: incorrect type in assignment 
(different address spaces)
+drivers/gpu/drm/i915/gvt/gtt.c:661:9: warning: incorrect type in assignment 
(different address spaces)
+drivers/gpu/drm/i915/gvt/gtt.c:662:45:expected void [noderef] **slot
+drivers/gpu/drm/i915/gvt/gtt.c:662:45:got void **slot
+drivers/gpu/drm/i915/gvt/gtt.c:662:45: warning: incorrect type in argument 1 
(different address spaces)
+drivers/gpu/drm/i915/gvt/mmio.c:255:23: warning: memcpy with byte count of 
279040
+drivers/gpu/drm/i915/gvt/mmio.c:256:23: warning: memcpy with byte count of 
279040
+drivers/gpu/drm/i915/i915_perf.c:1365:15: warning: memset with byte count of 
16777216
+drivers/gpu/drm/i915/i915_perf.c:1423:15: warning: memset with byte count of 
16777216
+drivers/gpu/drm/i915/i915_request.c:304:13: error: undefined identifier 
'__builtin_add_overflow_p'
+drivers/gpu/drm/i915/i915_request.c:304:13: warning: call with no type!
+drivers/gpu/drm/i915/selftests/i915_syncmap.c:80:54: warning: dubious: x | !y
+./include/linux/relay.h:258:34:expected void const [noderef] 
*__vpp_verify
+./include/linux/relay.h:258:34:expected void const [noderef] 
*__vpp_verify
+./include/linux/relay.h:258:34:got struct rchan_buf **
+./include/linux/relay.h:258:34:got struct rchan_buf **
+./include/linux/relay.h:258:34: warning: incorrect type in initializer 
(different address spaces)
+./include/linux/relay.h:258:34: warning: incorrect type in initializer 
(different address spaces)
+./include/linux/relay.h:269:9: warning: dereference of noderef expression
+./include/linux/relay.h:269:9: warning: dereference of noderef expression

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.BAT: failure for Queued/runnable/running engine stats (rev3)

[Patchwork]

== Series Details ==

Series: Queued/runnable/running engine stats (rev3)
URL   : https://patchwork.freedesktop.org/series/36926/
State : failure

== Summary ==

Series 36926v3 Queued/runnable/running engine stats
https://patchwork.freedesktop.org/api/1.0/series/36926/revisions/3/mbox/

 Possible new issues:

Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-b-frame-sequence:
pass   -> FAIL   (fi-skl-6770hq)

 Known issues:

Test gem_ringfill:
Subgroup basic-default-hang:
dmesg-warn -> INCOMPLETE (fi-blb-e6850) fdo#101600 +1
Test kms_flip:
Subgroup basic-flip-vs-wf_vblank:
pass   -> FAIL   (fi-skl-6770hq) fdo#100368

fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:434s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:440s
fi-blb-e6850 total:146  pass:114  dwarn:0   dfail:0   fail:0   skip:31 
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:538s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:299s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:512s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:516s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:504s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:409s
fi-cfl-s2total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:579s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:511s
fi-cnl-drrs  total:285  pass:254  dwarn:3   dfail:0   fail:0   skip:28  
time:540s
fi-elk-e7500 total:285  pass:225  dwarn:1   dfail:0   fail:0   skip:59  
time:418s
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:316s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:535s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:403s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:418s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:463s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:428s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:472s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:463s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:514s
fi-pnv-d510  total:146  pass:113  dwarn:0   dfail:0   fail:0   skip:32 
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:438s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:541s
fi-skl-6700hqtotal:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:541s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:504s
fi-skl-6770hqtotal:285  pass:263  dwarn:0   dfail:0   fail:2   skip:20  
time:486s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:429s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:445s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:569s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:405s

260af42eeff094e4768265a6ec8bbcb29b87e9a0 drm-tip: 2018y-03m-19d-17h-15m-08s UTC 
integration manifest
8c6da3b6af57 drm/i915: Engine queues query
1ef4b561e79b drm/i915/pmu: Add running counter
104ead8a4564 drm/i915/pmu: Add runnable counter
a13ee0c03cb5 drm/i915/pmu: Add queued counter
e4892df27036 drm/i915: Keep a count of requests submitted from userspace
a9b33ccca2b6 drm/i915: Keep a count of requests waiting for a slot on GPU
76102c836a10 drm/i915/pmu: Fix enable count array size and bounds checking

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8402/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH] drm/i915/gvt/scheduler: fix potential NULL pointer dereference

[Gustavo A. R. Silva]

_workload_ is being dereferenced before it is null checked, hence
there is a potential null pointer dereference.

Fix this by moving the pointer dereference after _workload_ has
been null checked.

Addresses-Coverity-ID: 1430136 ("Dereference before null check")
Fixes: fa3dd623e559 ("drm/i915/gvt: keep oa config in shadow ctx")
Signed-off-by: Gustavo A. R. Silva 
---
 drivers/gpu/drm/i915/gvt/scheduler.c | 10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c 
b/drivers/gpu/drm/i915/gvt/scheduler.c
index 0681264..be1a297 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -60,9 +60,9 @@ static void set_context_pdp_root_pointer(
 static void sr_oa_regs(struct intel_vgpu_workload *workload,
u32 *reg_state, bool save)
 {
-   struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv;
-   u32 ctx_oactxctrl = dev_priv->perf.oa.ctx_oactxctrl_offset;
-   u32 ctx_flexeu0 = dev_priv->perf.oa.ctx_flexeu0_offset;
+   struct drm_i915_private *dev_priv;
+   u32 ctx_oactxctrl;
+   u32 ctx_flexeu0;
int i = 0;
u32 flex_mmio[] = {
i915_mmio_reg_offset(EU_PERF_CNTL0),
@@ -77,6 +77,10 @@ static void sr_oa_regs(struct intel_vgpu_workload *workload,
if (!workload || !reg_state || workload->ring_id != RCS)
return;
 
+   dev_priv = workload->vgpu->gvt->dev_priv;
+   ctx_oactxctrl = dev_priv->perf.oa.ctx_oactxctrl_offset;
+   ctx_flexeu0 = dev_priv->perf.oa.ctx_flexeu0_offset;
+
if (save) {
workload->oactxctrl = reg_state[ctx_oactxctrl + 1];
 
-- 
2.7.4

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: make GEM_WARN_ON less terrible

[Patchwork]

== Series Details ==

Series: drm/i915: make GEM_WARN_ON less terrible
URL   : https://patchwork.freedesktop.org/series/40215/
State : success

== Summary ==

Series 40215v1 drm/i915: make GEM_WARN_ON less terrible
https://patchwork.freedesktop.org/api/1.0/series/40215/revisions/1/mbox/

 Known issues:

Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail   -> PASS   (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:433s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:441s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:385s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:537s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:297s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:513s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:520s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:510s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:410s
fi-cfl-s2total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:579s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:512s
fi-cnl-drrs  total:285  pass:254  dwarn:3   dfail:0   fail:0   skip:28  
time:520s
fi-elk-e7500 total:285  pass:225  dwarn:1   dfail:0   fail:0   skip:59  
time:429s
fi-gdg-551   total:285  pass:177  dwarn:0   dfail:0   fail:0   skip:108 
time:321s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:538s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:411s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:420s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:475s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:428s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:472s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:465s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:518s
fi-pnv-d510  total:285  pass:219  dwarn:1   dfail:0   fail:0   skip:65  
time:652s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:444s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:533s
fi-skl-6700hqtotal:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:542s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:508s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:500s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:430s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:445s
fi-snb-2520m total:242  pass:208  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:403s

260af42eeff094e4768265a6ec8bbcb29b87e9a0 drm-tip: 2018y-03m-19d-17h-15m-08s UTC 
integration manifest
09aaab021f8c drm/i915: make GEM_WARN_ON less terrible

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8401/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v2,1/3] drm/i915/guc: Unify naming of private GuC action functions

[Patchwork]

== Series Details ==

Series: series starting with [v2,1/3] drm/i915/guc: Unify naming of private GuC 
action functions
URL   : https://patchwork.freedesktop.org/series/40190/
State : success

== Summary ==

 Possible new issues:

Test pm_rc6_residency:
Subgroup rc6-accuracy:
skip   -> PASS   (shard-snb)

 Known issues:

Test kms_flip:
Subgroup dpms-vs-vblank-race:
fail   -> PASS   (shard-hsw) fdo#103060
Test kms_sysfs_edid_timing:
warn   -> PASS   (shard-apl) fdo#100047

fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047

shard-apltotal:3442 pass:1815 dwarn:1   dfail:0   fail:7   skip:1619 
time:12953s
shard-hswtotal:3442 pass:1768 dwarn:1   dfail:0   fail:1   skip:1671 
time:11956s
shard-snbtotal:3442 pass:1359 dwarn:1   dfail:0   fail:2   skip:2080 
time:7220s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8394/shards.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915: make GEM_WARN_ON less terrible

[Matthew Auld]

On 19 March 2018 at 18:17, Chris Wilson  wrote:
> Quoting Matthew Auld (2018-03-19 18:08:54)
>> GEM_WARN_ON() was originally intended to be used only as:
>>
>>if (GEM_WARN_ON(expr))
>> ...
>>
>> but it just so happens to also work as simply:
>>
>>GEM_WARN_ON(expr);
>>
>> since it just wraps WARN_ON, which is a little misleading since for
>> !DRM_I915_DEBUG_GEM builds the second case will actually break the
>> build. Given that there are some patches floating around which seem to
>> miss this, it probably makes sense to just make it work for both cases.
>
> That really was quite intentional. The only time to use GEM_WARN_ON() is
> inside an if, otherwise what's the point?

Why wouldn't we want it to behave like WARN_ON? That seems to be what
people expect, since it does wrap WARN_ON, and we don't always use
WARN_ON in an if...
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: make GEM_WARN_ON less terrible

[Patchwork]

== Series Details ==

Series: drm/i915: make GEM_WARN_ON less terrible
URL   : https://patchwork.freedesktop.org/series/40215/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
09aaab021f8c drm/i915: make GEM_WARN_ON less terrible
-:32: ERROR:SPACING: space required after that ';' (ctx:VxV)
#32: FILE: drivers/gpu/drm/i915/i915_gem.h:47:
+#define GEM_WARN_ON(expr) ({BUILD_BUG_ON_INVALID(expr), 0;})
  ^

total: 1 errors, 0 warnings, 0 checks, 8 lines checked

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v2] drm/i915: Disable some extra clang warnings

[Matthias Kaehlcke]

Commit 39bf4de89ff7 ("drm/i915: Add -Wall -Wextra to our build, set
warnings to full") enabled extra warnings for i915 to spot possible
bugs in new code, and then disabled a subset of these warnings to keep
the current code building without warnings (with gcc). Enabling the
extra warnings also enabled some additional clang-only warnings, as a
result building i915 with clang currently is extremely noisy. For now
also disable the clang warnings sign-compare, sometimes-uninitialized,
unneeded-internal-declaration and initializer-overrides. If desired
they can be re-enabled after the code has been fixed.

Fixes: 39bf4de89ff7 ("drm/i915: Add -Wall -Wextra to our build, set
warnings to full")
Signed-off-by: Matthias Kaehlcke 
---
Changes in v2:
- rebased on drm-tip
- added comment indicating that disabled warnings are clang warnings

 drivers/gpu/drm/i915/Makefile | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 4eee91a3a236..9717c037b582 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -18,6 +18,11 @@ subdir-ccflags-y += $(call cc-disable-warning, type-limits)
 subdir-ccflags-y += $(call cc-disable-warning, missing-field-initializers)
 subdir-ccflags-y += $(call cc-disable-warning, implicit-fallthrough)
 subdir-ccflags-y += $(call cc-disable-warning, unused-but-set-variable)
+# clang warnings
+subdir-ccflags-y += $(call cc-disable-warning, sign-compare)
+subdir-ccflags-y += $(call cc-disable-warning, sometimes-uninitialized)
+subdir-ccflags-y += $(call cc-disable-warning, unneeded-internal-declaration)
+subdir-ccflags-y += $(call cc-disable-warning, initializer-overrides)
 subdir-ccflags-$(CONFIG_DRM_I915_WERROR) += -Werror
 
 # Fine grained warnings disable
-- 
2.16.2.804.g6dcf76e118-goog

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/dp: Correctly mask DP_TRAINING_AUX_RD_INTERVAL values for DP 1.4

[Jani Nikula]

On Fri, 16 Mar 2018, matthew.s.atw...@intel.com wrote:
> From: Matt Atwood 
>
> DP_TRAINING_AUX_RD_INTERVAL with DP 1.3 spec changed bit scheeme from 8
> bits to 7 in DPCD 0x000e. The 8th bit is used to identify extended
> receiver capabilities. For panels that use this new feature wait interval
> would be increased by 512 ms, when spec is max 16 ms. This behavior is
> described in table 2-158 of DP 1.4 spec address eh.
>
> With the introduction of DP 1.4 spec main link clock recovery was
> standardized to 100 us regardless of TRAINING_AUX_RD_INTERVAL value.
>
> To avoid breaking panels that are not spec compiant we now warn on
> invalid values.
>
> V2: commit title/message, masking all 7 bits, warn on out of spec values.
> V3: commit message, make link train clock recovery follow DP 1.4 spec.
> V4: style changes
> V5: typo
> V6: print statement revisions, DP_REV to DPCD_REV, comment correction
> V7: typo
> V8: Style
>
> Signed-off-by: Matt Atwood 
> ---
>  drivers/gpu/drm/drm_dp_helper.c | 22 ++
>  include/drm/drm_dp_helper.h |  6 ++

This should be sent to dri-devel. See scripts/get_maintainer.pl.

BR,
Jani.


-- 
Jani Nikula, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915: make edp optimize config

[Jani Nikula]

On Fri, 16 Mar 2018, matthew.s.atw...@intel.com wrote:
> From: Matt Atwood 
>
> Previously it was assumed that eDP panels would advertise the lowest link
> rate required for their singular mode to function. With the introduction
> of more advanced features there are advantages to a panel advertising a
> higher rate then it needs for a its given mode. For panels that did, the
> driver previously used a higher rate then necessary for that mode.

Makes me wonder if the check here should be for those features (that
should be mentioned, I guess you mean DSC, perhaps rate select) instead
of the spec version.

Please do send patches that compile, though. Gives you more
credibility. ;)

BR,
Jani.

>
> Signed-off-by: Matt Atwood 
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 6 --
>  1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index a2eeede..57b309c 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1766,8 +1766,10 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>* configuration, and typically these values correspond to the
>* native resolution of the panel.
>*/
> - min_lane_count = max_lane_count;
> - min_clock = max_clock;
> + if(dpcd[DP_DPCD_REV] < DPCD_REV_14){
> + min_lane_count = max_lane_count;
> + min_clock = max_clock;
> + }
>   }
>  
>   for (; bpp >= 6*3; bpp -= 2*3) {

-- 
Jani Nikula, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Reword warning for missing cases (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Reword warning for missing cases (rev2)
URL   : https://patchwork.freedesktop.org/series/39821/
State : failure

== Summary ==

Series 39821v2 drm/i915: Reword warning for missing cases
https://patchwork.freedesktop.org/api/1.0/series/39821/revisions/2/mbox/

 Possible new issues:

Test gem_exec_parallel:
Subgroup basic:
pass   -> INCOMPLETE (fi-snb-2600)

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:432s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:439s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:379s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:536s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:297s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:509s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:515s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:504s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:406s
fi-cfl-s2total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:581s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:510s
fi-cnl-drrs  total:285  pass:254  dwarn:3   dfail:0   fail:0   skip:28  
time:519s
fi-elk-e7500 total:285  pass:225  dwarn:1   dfail:0   fail:0   skip:59  
time:425s
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:316s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:535s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:401s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:419s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:470s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:437s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:473s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:464s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:513s
fi-pnv-d510  total:285  pass:219  dwarn:1   dfail:0   fail:0   skip:65  
time:652s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:435s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:534s
fi-skl-6700hqtotal:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:544s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:506s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:517s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:427s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:445s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:571s
fi-snb-2600  total:68   pass:57   dwarn:0   dfail:0   fail:0   skip:10 

260af42eeff094e4768265a6ec8bbcb29b87e9a0 drm-tip: 2018y-03m-19d-17h-15m-08s UTC 
integration manifest
7cb94d2c3c47 drm/i915: Reword warning for missing cases

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8400/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gvt: fix spelling mistake: "registeration" -> "registration"

[Patchwork]

== Series Details ==

Series: drm/i915/gvt: fix spelling mistake: "registeration" -> "registration"
URL   : https://patchwork.freedesktop.org/series/40185/
State : success

== Summary ==

 Known issues:

Test kms_flip:
Subgroup 2x-flip-vs-expired-vblank-interruptible:
pass   -> FAIL   (shard-hsw) fdo#102887
Subgroup 2x-flip-vs-wf_vblank:
pass   -> FAIL   (shard-hsw) fdo#100368
Subgroup dpms-vs-vblank-race:
fail   -> PASS   (shard-hsw) fdo#103060
Test kms_sysfs_edid_timing:
warn   -> PASS   (shard-apl) fdo#100047

fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047

shard-apltotal:3442 pass:1815 dwarn:1   dfail:0   fail:7   skip:1619 
time:13011s
shard-hswtotal:3442 pass:1766 dwarn:1   dfail:0   fail:3   skip:1671 
time:11896s
shard-snbtotal:3442 pass:1358 dwarn:1   dfail:0   fail:2   skip:2081 
time:7226s
Blacklisted hosts:
shard-kbltotal:3442 pass:1913 dwarn:26  dfail:1   fail:10  skip:1492 
time:9903s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8393/shards.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Reword warning for missing cases (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Reword warning for missing cases (rev2)
URL   : https://patchwork.freedesktop.org/series/39821/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
7cb94d2c3c47 drm/i915: Reword warning for missing cases
-:40: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'x' - possible side-effects?
#40: FILE: drivers/gpu/drm/i915/i915_utils.h:43:
+#define MISSING_CASE(x) WARN(1, "Missing case (%s == %ld)\n", \
+__stringify(x), (long)(x))

total: 0 errors, 0 warnings, 1 checks, 10 lines checked

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Promote .format_mod_supported() to the lead role

[Patchwork]

== Series Details ==

Series: drm/i915: Promote .format_mod_supported() to the lead role
URL   : https://patchwork.freedesktop.org/series/40207/
State : success

== Summary ==

Series 40207v1 drm/i915: Promote .format_mod_supported() to the lead role
https://patchwork.freedesktop.org/api/1.0/series/40207/revisions/1/mbox/

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:430s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:441s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:381s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:540s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:297s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:514s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:513s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:502s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:422s
fi-cfl-s2total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:577s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:518s
fi-cnl-drrs  total:285  pass:254  dwarn:3   dfail:0   fail:0   skip:28  
time:519s
fi-elk-e7500 total:285  pass:225  dwarn:1   dfail:0   fail:0   skip:59  
time:430s
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:317s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:536s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:407s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:425s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:472s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:429s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:475s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:466s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:519s
fi-pnv-d510  total:285  pass:219  dwarn:1   dfail:0   fail:0   skip:65  
time:648s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:437s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:548s
fi-skl-6700hqtotal:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:544s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:501s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:506s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:425s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:449s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:591s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:402s

260af42eeff094e4768265a6ec8bbcb29b87e9a0 drm-tip: 2018y-03m-19d-17h-15m-08s UTC 
integration manifest
bd9ae7d6edf8 drm/i915: Promote .format_mod_supported() to the lead role

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8399/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH i-g-t 5/5] tests/i915_query: Engine queues tests

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

...

Signed-off-by: Tvrtko Ursulin 
---
 tests/i915_query.c | 381 +
 1 file changed, 381 insertions(+)

diff --git a/tests/i915_query.c b/tests/i915_query.c
index c7de8cbd8371..94e7a3297ebd 100644
--- a/tests/i915_query.c
+++ b/tests/i915_query.c
@@ -477,8 +477,358 @@ test_query_topology_known_pci_ids(int fd, int devid)
free(topo_info);
 }
 
+#define DRM_I915_QUERY_ENGINE_QUEUES   2
+
+struct drm_i915_query_engine_queues {
+   /** Engine class as in enum drm_i915_gem_engine_class. */
+   __u16 class;
+
+   /** Engine instance number. */
+   __u16 instance;
+
+   /** Number of requests with unresolved fences and dependencies. */
+   __u32 queued;
+
+   /** Number of ready requests waiting on a slot on GPU. */
+   __u32 runnable;
+
+   /** Number of requests executing on the GPU. */
+   __u32 running;
+
+   __u32 rsvd[5];
+};
+
+static bool query_engine_queues_supported(int fd)
+{
+   struct drm_i915_query_item item = {
+   .query_id = DRM_I915_QUERY_ENGINE_QUEUES,
+   };
+
+   return __i915_query_items(fd, , 1) == 0 && item.length > 0;
+}
+
+static void engine_queues_invalid(int fd)
+{
+   struct drm_i915_query_engine_queues queues;
+   struct drm_i915_query_item item;
+   unsigned int len;
+   unsigned int i;
+
+   /* Flags is MBZ. */
+   memset(, 0, sizeof(item));
+   item.query_id = DRM_I915_QUERY_ENGINE_QUEUES;
+   item.flags = 1;
+   i915_query_items(fd, , 1);
+   igt_assert_eq(item.length, -EINVAL);
+
+   /* Length not zero and not greater or equal required size. */
+   memset(, 0, sizeof(item));
+   item.query_id = DRM_I915_QUERY_ENGINE_QUEUES;
+   item.length = 1;
+   i915_query_items(fd, , 1);
+   igt_assert_eq(item.length, -ENOSPC);
+
+   /* Query correct length. */
+   memset(, 0, sizeof(item));
+   item.query_id = DRM_I915_QUERY_ENGINE_QUEUES;
+   i915_query_items(fd, , 1);
+   igt_assert(item.length >= 0);
+   len = item.length;
+
+   /* Ivalid pointer. */
+   memset(, 0, sizeof(item));
+   item.query_id = DRM_I915_QUERY_ENGINE_QUEUES;
+   item.length = len;
+   i915_query_items(fd, , 1);
+   igt_assert_eq(item.length, -EFAULT);
+
+   /* Reserved fields are MBZ. */
+
+   for (i = 0; i < ARRAY_SIZE(queues.rsvd); i++) {
+   memset(, 0, sizeof(queues));
+   queues.rsvd[i] = 1;
+   memset(, 0, sizeof(item));
+   item.query_id = DRM_I915_QUERY_ENGINE_QUEUES;
+   item.length = len;
+   item.data_ptr = to_user_pointer();
+   i915_query_items(fd, , 1);
+   igt_assert_eq(item.length, -EINVAL);
+   }
+
+   memset(, 0, sizeof(queues));
+   queues.class = -1;
+   memset(, 0, sizeof(item));
+   item.query_id = DRM_I915_QUERY_ENGINE_QUEUES;
+   item.length = len;
+   item.data_ptr = to_user_pointer();
+   i915_query_items(fd, , 1);
+   igt_assert_eq(item.length, -ENOENT);
+
+   memset(, 0, sizeof(queues));
+   queues.instance = -1;
+   memset(, 0, sizeof(item));
+   item.query_id = DRM_I915_QUERY_ENGINE_QUEUES;
+   item.length = len;
+   item.data_ptr = to_user_pointer();
+   i915_query_items(fd, , 1);
+   igt_assert_eq(item.length, -ENOENT);
+}
+
+static void engine_queues(int fd, const struct intel_execution_engine2 *e)
+{
+   struct drm_i915_query_engine_queues queues;
+   struct drm_i915_query_item item;
+   unsigned int len;
+
+   /* Query required buffer length. */
+   memset(, 0, sizeof(queues));
+   memset(, 0, sizeof(item));
+   item.query_id = DRM_I915_QUERY_ENGINE_QUEUES;
+   item.data_ptr = to_user_pointer();
+   i915_query_items(fd, , 1);
+   igt_assert(item.length >= 0);
+   igt_assert(item.length <= sizeof(queues));
+   len = item.length;
+
+   /* Check length larger than required works and reports same length. */
+   memset(, 0, sizeof(queues));
+   memset(, 0, sizeof(item));
+   item.query_id = DRM_I915_QUERY_ENGINE_QUEUES;
+   item.data_ptr = to_user_pointer();
+   item.length = len + 1;
+   i915_query_items(fd, , 1);
+   igt_assert_eq(item.length, len);
+
+   /* Actual query. */
+   memset(, 0, sizeof(queues));
+   queues.class = e->class;
+   queues.instance = e->instance;
+   memset(, 0, sizeof(item));
+   item.query_id = DRM_I915_QUERY_ENGINE_QUEUES;
+   item.data_ptr = to_user_pointer();
+   item.length = len;
+   i915_query_items(fd, , 1);
+   igt_assert_eq(item.length, len);
+}
+
+static unsigned int e2ring(int gem_fd, const struct intel_execution_engine2 *e)
+{
+   return gem_class_instance_to_eb_flags(gem_fd, e->class, e->instance);
+}
+
+static void
+__query_queues(int fd, 

[Intel-gfx] [PATCH i-g-t 2/5] intel-gpu-overlay: Add engine queue stats

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Use new PMU engine queue stats (queued, runnable and running) and display
them per engine.

v2:
 * Compact per engine stats. (Chris Wilson)

Signed-off-by: Tvrtko Ursulin 
---
 overlay/gpu-top.c | 42 ++
 overlay/gpu-top.h | 11 +++
 overlay/overlay.c |  7 +++
 3 files changed, 60 insertions(+)

diff --git a/overlay/gpu-top.c b/overlay/gpu-top.c
index 61b8f62fd78c..22e9badb22c1 100644
--- a/overlay/gpu-top.c
+++ b/overlay/gpu-top.c
@@ -72,6 +72,18 @@ static int perf_init(struct gpu_top *gt)
 gt->fd) >= 0)
gt->have_sema = 1;
 
+   if (perf_i915_open_group(I915_PMU_ENGINE_QUEUED(d->class, d->inst),
+gt->fd) >= 0)
+   gt->have_queued = 1;
+
+   if (perf_i915_open_group(I915_PMU_ENGINE_RUNNABLE(d->class, d->inst),
+gt->fd) >= 0)
+   gt->have_runnable = 1;
+
+   if (perf_i915_open_group(I915_PMU_ENGINE_RUNNING(d->class, d->inst),
+gt->fd) >= 0)
+   gt->have_running = 1;
+
gt->ring[0].name = d->name;
gt->num_rings = 1;
 
@@ -93,6 +105,24 @@ static int perf_init(struct gpu_top *gt)
   gt->fd) < 0)
return -1;
 
+   if (gt->have_queued &&
+   perf_i915_open_group(I915_PMU_ENGINE_QUEUED(d->class,
+   d->inst),
+  gt->fd) < 0)
+   return -1;
+
+   if (gt->have_runnable &&
+   perf_i915_open_group(I915_PMU_ENGINE_RUNNABLE(d->class,
+ d->inst),
+  gt->fd) < 0)
+   return -1;
+
+   if (gt->have_running &&
+   perf_i915_open_group(I915_PMU_ENGINE_RUNNING(d->class,
+d->inst),
+  gt->fd) < 0)
+   return -1;
+
gt->ring[gt->num_rings++].name = d->name;
}
 
@@ -298,6 +328,12 @@ int gpu_top_update(struct gpu_top *gt)
s->wait[n] = sample[m++];
if (gt->have_sema)
s->sema[n] = sample[m++];
+   if (gt->have_queued)
+   s->queued[n] = sample[m++];
+   if (gt->have_runnable)
+   s->runnable[n] = sample[m++];
+   if (gt->have_running)
+   s->running[n] = sample[m++];
}
 
if (gt->count == 1)
@@ -310,6 +346,12 @@ int gpu_top_update(struct gpu_top *gt)
gt->ring[n].u.u.wait = (100 * (s->wait[n] - 
d->wait[n]) + d_time/2) / d_time;
if (gt->have_sema)
gt->ring[n].u.u.sema = (100 * (s->sema[n] - 
d->sema[n]) + d_time/2) / d_time;
+   if (gt->have_queued)
+   gt->ring[n].queued = (double)((s->queued[n] - 
d->queued[n])) / I915_SAMPLE_QUEUED_DIVISOR * 1e9 / d_time;
+   if (gt->have_runnable)
+   gt->ring[n].runnable = (double)((s->runnable[n] 
- d->runnable[n])) / I915_SAMPLE_RUNNABLE_DIVISOR  * 1e9 / d_time;
+   if (gt->have_running)
+   gt->ring[n].running = (double)((s->running[n] - 
d->running[n])) / I915_SAMPLE_RUNNING_DIVISOR * 1e9 / d_time;
 
/* in case of rounding + sampling errors, fudge */
if (gt->ring[n].u.u.busy > 100)
diff --git a/overlay/gpu-top.h b/overlay/gpu-top.h
index d3cdd779760f..cb4310c82a94 100644
--- a/overlay/gpu-top.h
+++ b/overlay/gpu-top.h
@@ -36,6 +36,9 @@ struct gpu_top {
int num_rings;
int have_wait;
int have_sema;
+   int have_queued;
+   int have_runnable;
+   int have_running;
 
struct gpu_top_ring {
const char *name;
@@ -47,6 +50,10 @@ struct gpu_top {
} u;
uint32_t payload;
} u;
+
+   double queued;
+   double runnable;
+   double running;
} ring[MAX_RINGS];
 
struct gpu_top_stat {
@@ -54,7 +61,11 @@ struct gpu_top {
uint64_t busy[MAX_RINGS];
uint64_t wait[MAX_RINGS];
uint64_t sema[MAX_RINGS];
+   uint64_t queued[MAX_RINGS];
+   uint64_t runnable[MAX_RINGS];
+   uint64_t running[MAX_RINGS];
} stat[2];
+
int count;
 };
 
diff --git a/overlay/overlay.c b/overlay/overlay.c
index 

[Intel-gfx] [PATCH i-g-t 3/5] intel-gpu-overlay: Show 1s, 30s and 15m GPU load

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Show total GPU loads in the window banner.

Engine load is defined as total of runnable and running requests on an
engine.

Total, non-normalized, load is display. In other words if N engines are
busy with exactly one request, the load will be shown as N.

v2:
 * Different flavour of load avg. (Chris Wilson)
 * Simplify code. (Chris Wilson)

Signed-off-by: Tvrtko Ursulin 
---
 overlay/gpu-top.c | 39 ++-
 overlay/gpu-top.h | 11 ++-
 overlay/overlay.c | 28 ++--
 3 files changed, 70 insertions(+), 8 deletions(-)

diff --git a/overlay/gpu-top.c b/overlay/gpu-top.c
index 22e9badb22c1..501429b86379 100644
--- a/overlay/gpu-top.c
+++ b/overlay/gpu-top.c
@@ -28,6 +28,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -126,6 +127,10 @@ static int perf_init(struct gpu_top *gt)
gt->ring[gt->num_rings++].name = d->name;
}
 
+   gt->have_load_avg = gt->have_queued &&
+   gt->have_runnable &&
+   gt->have_running;
+
return 0;
 }
 
@@ -290,17 +295,32 @@ static void mmio_init(struct gpu_top *gt)
}
 }
 
-void gpu_top_init(struct gpu_top *gt)
+void gpu_top_init(struct gpu_top *gt, unsigned int period_us)
 {
+   const double period = (double)period_us / 1e6;
+   const double load_period[NUM_LOADS] = { 1.0, 30.0, 900.0 };
+   const char *load_names[NUM_LOADS] = { "1s", "30s", "15m" };
+   unsigned int i;
+
memset(gt, 0, sizeof(*gt));
gt->fd = -1;
 
+   for (i = 0; i < NUM_LOADS; i++) {
+   gt->load_name[i] = load_names[i];
+   gt->exp[i] = exp(-period / load_period[i]);
+   }
+
if (perf_init(gt) == 0)
return;
 
mmio_init(gt);
 }
 
+static double update_load(double load, double exp, double val)
+{
+   return val + exp * (load - val);
+}
+
 int gpu_top_update(struct gpu_top *gt)
 {
uint32_t data[1024];
@@ -313,6 +333,8 @@ int gpu_top_update(struct gpu_top *gt)
struct gpu_top_stat *s = >stat[gt->count++&1];
struct gpu_top_stat *d = >stat[gt->count&1];
uint64_t *sample, d_time;
+   double gpu_qd = 0.0;
+   unsigned int i;
int n, m;
 
len = read(gt->fd, data, sizeof(data));
@@ -341,6 +363,8 @@ int gpu_top_update(struct gpu_top *gt)
 
d_time = s->time - d->time;
for (n = 0; n < gt->num_rings; n++) {
+   double qd = 0.0;
+
gt->ring[n].u.u.busy = (100 * (s->busy[n] - d->busy[n]) 
+ d_time/2) / d_time;
if (gt->have_wait)
gt->ring[n].u.u.wait = (100 * (s->wait[n] - 
d->wait[n]) + d_time/2) / d_time;
@@ -353,6 +377,14 @@ int gpu_top_update(struct gpu_top *gt)
if (gt->have_running)
gt->ring[n].running = (double)((s->running[n] - 
d->running[n])) / I915_SAMPLE_RUNNING_DIVISOR * 1e9 / d_time;
 
+   qd = gt->ring[n].runnable + gt->ring[n].running;
+   gpu_qd += qd;
+
+   for (i = 0; i < NUM_LOADS; i++)
+   gt->ring[n].load[i] =
+   update_load(gt->ring[n].load[i],
+   gt->exp[i], qd);
+
/* in case of rounding + sampling errors, fudge */
if (gt->ring[n].u.u.busy > 100)
gt->ring[n].u.u.busy = 100;
@@ -362,6 +394,11 @@ int gpu_top_update(struct gpu_top *gt)
gt->ring[n].u.u.sema = 100;
}
 
+   for (i = 0; i < NUM_LOADS; i++) {
+   gt->load[i] = update_load(gt->load[i], gt->exp[i],
+ gpu_qd);
+   gt->norm_load[i] = gt->load[i] / gt->num_rings;
+   }
update = 1;
} else {
while ((len = read(gt->fd, data, sizeof(data))) > 0) {
diff --git a/overlay/gpu-top.h b/overlay/gpu-top.h
index cb4310c82a94..115ce8c482c1 100644
--- a/overlay/gpu-top.h
+++ b/overlay/gpu-top.h
@@ -26,6 +26,7 @@
 #define GPU_TOP_H
 
 #define MAX_RINGS 16
+#define NUM_LOADS 3
 
 #include 
 
@@ -39,6 +40,12 @@ struct gpu_top {
int have_queued;
int have_runnable;
int have_running;
+   int have_load_avg;
+
+   double exp[NUM_LOADS];
+   double load[NUM_LOADS];
+   double norm_load[NUM_LOADS];
+   const char *load_name[NUM_LOADS];
 
struct gpu_top_ring {
const char *name;
@@ -54,6 +61,8 @@ struct gpu_top {
double queued;
double runnable;
double running;
+
+   double 

[Intel-gfx] [PATCH i-g-t 1/5] include: i915 uAPI headers

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Temporary up to date uAPI headers.

Signed-off-by: Tvrtko Ursulin 
---
 include/drm-uapi/i915_drm.h | 19 ++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index 16e452aa12d4..14c7e790f6ed 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -110,9 +110,17 @@ enum drm_i915_gem_engine_class {
 enum drm_i915_pmu_engine_sample {
I915_SAMPLE_BUSY = 0,
I915_SAMPLE_WAIT = 1,
-   I915_SAMPLE_SEMA = 2
+   I915_SAMPLE_SEMA = 2,
+   I915_SAMPLE_QUEUED = 3,
+   I915_SAMPLE_RUNNABLE = 4,
+   I915_SAMPLE_RUNNING = 5,
 };
 
+ /* Divide counter value by divisor to get the real value. */
+#define I915_SAMPLE_QUEUED_DIVISOR (1024)
+#define I915_SAMPLE_RUNNABLE_DIVISOR (1024)
+#define I915_SAMPLE_RUNNING_DIVISOR (1024)
+
 #define I915_PMU_SAMPLE_BITS (4)
 #define I915_PMU_SAMPLE_MASK (0xf)
 #define I915_PMU_SAMPLE_INSTANCE_BITS (8)
@@ -133,6 +141,15 @@ enum drm_i915_pmu_engine_sample {
 #define I915_PMU_ENGINE_SEMA(class, instance) \
__I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA)
 
+#define I915_PMU_ENGINE_QUEUED(class, instance) \
+   __I915_PMU_ENGINE(class, instance, I915_SAMPLE_QUEUED)
+
+#define I915_PMU_ENGINE_RUNNABLE(class, instance) \
+   __I915_PMU_ENGINE(class, instance, I915_SAMPLE_RUNNABLE)
+
+#define I915_PMU_ENGINE_RUNNING(class, instance) \
+   __I915_PMU_ENGINE(class, instance, I915_SAMPLE_RUNNING)
+
 #define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x))
 
 #define I915_PMU_ACTUAL_FREQUENCY  __I915_PMU_OTHER(0)
-- 
2.14.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH i-g-t 0/5] Queued/runnable/running engine stats

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

IGT patches for the identicaly named i915 series, including:

 * Engine queue depths for intel-gpu-overlay (including load average).
 * Tests for new PMU counters.
 * Tests for the query API.

Tests have been tested (!) only on Skylake so YMMV. Also they depend on one yet
unmerged IGT patch so won't compile in this form. Sending to show (most) of the
feature is close to ready.

Tvrtko Ursulin (5):
  include: i915 uAPI headers
  intel-gpu-overlay: Add engine queue stats
  intel-gpu-overlay: Show 1s, 30s and 15m GPU load
  tests/perf_pmu: Add tests for engine queued/runnable/running stats
  tests/i915_query: Engine queues tests

 include/drm-uapi/i915_drm.h |  19 ++-
 overlay/gpu-top.c   |  81 +-
 overlay/gpu-top.h   |  22 ++-
 overlay/overlay.c   |  35 +++-
 tests/i915_query.c  | 381 
 tests/perf_pmu.c| 224 ++
 6 files changed, 753 insertions(+), 9 deletions(-)

-- 
2.14.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH i-g-t 4/5] tests/perf_pmu: Add tests for engine queued/runnable/running stats

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Simple tests to check reported queue depths are correct.

Signed-off-by: Tvrtko Ursulin 
---
 tests/perf_pmu.c | 224 +++
 1 file changed, 224 insertions(+)

diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index 469b9becdbac..206c18960b7b 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -966,6 +966,196 @@ multi_client(int gem_fd, const struct 
intel_execution_engine2 *e)
assert_within_epsilon(val[1], perf_slept[1], tolerance);
 }
 
+static double calc_queued(uint64_t d_val, uint64_t d_ns)
+{
+   return (double)d_val * 1e9 / I915_SAMPLE_QUEUED_DIVISOR / d_ns;
+}
+
+static void
+queued(int gem_fd, const struct intel_execution_engine2 *e)
+{
+   const unsigned long engine = e2ring(gem_fd, e);
+   const unsigned int max_rq = 10;
+   double queued[max_rq + 1];
+   uint32_t bo[max_rq + 1];
+   unsigned int n, i;
+   uint64_t val[2];
+   uint64_t ts[2];
+   int fd;
+
+   memset(queued, 0, sizeof(queued));
+   memset(bo, 0, sizeof(bo));
+
+   fd = open_pmu(I915_PMU_ENGINE_QUEUED(e->class, e->instance));
+
+   for (n = 0; n <= max_rq; n++) {
+   int fence = -1;
+   struct igt_cork cork = { .fd = fence, .type = CORK_SYNC_FD };
+
+   gem_quiescent_gpu(gem_fd);
+
+   if (n)
+   fence = igt_cork_plug(, -1);
+
+   for (i = 0; i < n; i++) {
+   struct drm_i915_gem_exec_object2 obj = { };
+   struct drm_i915_gem_execbuffer2 eb = { };
+
+   if (!bo[i]) {
+   const uint32_t bbe = MI_BATCH_BUFFER_END;
+
+   bo[i] = gem_create(gem_fd, 4096);
+   gem_write(gem_fd, bo[i], 4092, ,
+ sizeof(bbe));
+   }
+
+   obj.handle = bo[i];
+
+   eb.buffer_count = 1;
+   eb.buffers_ptr = to_user_pointer();
+
+   eb.flags = engine | I915_EXEC_FENCE_IN;
+   eb.rsvd2 = fence;
+
+   gem_execbuf(gem_fd, );
+   }
+
+   val[0] = __pmu_read_single(fd, [0]);
+   usleep(batch_duration_ns / 1000);
+   val[1] = __pmu_read_single(fd, [1]);
+
+   queued[n] = calc_queued(val[1] - val[0], ts[1] - ts[0]);
+   igt_info("n=%u queued=%.2f\n", n, queued[n]);
+
+   if (fence >= 0)
+   igt_cork_unplug();
+
+   for (i = 0; i < n; i++)
+   gem_sync(gem_fd, bo[i]);
+   }
+
+   close(fd);
+
+   for (i = 0; i < max_rq; i++) {
+   if (bo[i])
+   gem_close(gem_fd, bo[i]);
+   }
+
+   for (i = 0; i <= max_rq; i++)
+   assert_within_epsilon(queued[i], i, tolerance);
+}
+
+static void
+runnable(int gem_fd, const struct intel_execution_engine2 *e)
+{
+   const unsigned long engine = e2ring(gem_fd, e);
+   const unsigned int max_rq = 10;
+   igt_spin_t *spin[max_rq + 1];
+   double runnable[max_rq + 1];
+   uint32_t ctx[max_rq];
+   unsigned int n, i;
+   uint64_t val[2];
+   uint64_t ts[2];
+   int fd;
+
+   memset(runnable, 0, sizeof(runnable));
+   memset(ctx, 0, sizeof(ctx));
+
+   fd = open_pmu(I915_PMU_ENGINE_RUNNABLE(e->class, e->instance));
+
+   for (n = 0; n <= max_rq; n++) {
+   gem_quiescent_gpu(gem_fd);
+
+   for (i = 0; i < n; i++) {
+   if (!ctx[i])
+   ctx[i] = gem_context_create(gem_fd);
+
+   if (i == 0)
+   spin[i] = __spin_poll(gem_fd, ctx[i], engine);
+   else
+   spin[i] = __igt_spin_batch_new(gem_fd, ctx[i],
+  engine, 0);
+   }
+
+   if (n)
+   __spin_wait(gem_fd, spin[0]);
+
+   val[0] = __pmu_read_single(fd, [0]);
+   usleep(batch_duration_ns / 1000);
+   val[1] = __pmu_read_single(fd, [1]);
+
+   runnable[n] = calc_queued(val[1] - val[0], ts[1] - ts[0]);
+   igt_info("n=%u runnable=%.2f\n", n, runnable[n]);
+
+   for (i = 0; i < n; i++) {
+   end_spin(gem_fd, spin[i], FLAG_SYNC);
+   igt_spin_batch_free(gem_fd, spin[i]);
+   }
+   }
+
+   for (i = 0; i < max_rq; i++) {
+   if (ctx[i])
+   gem_context_destroy(gem_fd, ctx[i]);
+   }
+
+   close(fd);
+
+   assert_within_epsilon(runnable[0], 0, tolerance);
+   igt_assert(runnable[max_rq] > 0.0);
+   

Re: [Intel-gfx] [PATCH] drm/i915: make GEM_WARN_ON less terrible

[Chris Wilson]

Quoting Matthew Auld (2018-03-19 18:08:54)
> GEM_WARN_ON() was originally intended to be used only as:
> 
>if (GEM_WARN_ON(expr))
> ...
> 
> but it just so happens to also work as simply:
> 
>GEM_WARN_ON(expr);
> 
> since it just wraps WARN_ON, which is a little misleading since for
> !DRM_I915_DEBUG_GEM builds the second case will actually break the
> build. Given that there are some patches floating around which seem to
> miss this, it probably makes sense to just make it work for both cases.

That really was quite intentional. The only time to use GEM_WARN_ON() is
inside an if, otherwise what's the point?
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 4/7] drm/i915/pmu: Add queued counter

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

We add a PMU counter to expose the number of requests which have been
submitted from userspace but are not yet runnable due dependencies and
unsignaled fences.

This is useful to analyze the overall load of the system.

v2:
 * Rebase for name change and re-order.
 * Drop floating point constant. (Chris Wilson)

v3:
 * Change scale to 1024 for faster arithmetics. (Chris Wilson)

Signed-off-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_pmu.c | 40 +
 drivers/gpu/drm/i915/intel_ringbuffer.h |  2 +-
 include/uapi/drm/i915_drm.h |  9 +++-
 3 files changed, 45 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index eb60943671b3..07f5cac97b56 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -15,7 +15,8 @@
 #define ENGINE_SAMPLE_MASK \
(BIT(I915_SAMPLE_BUSY) | \
 BIT(I915_SAMPLE_WAIT) | \
-BIT(I915_SAMPLE_SEMA))
+BIT(I915_SAMPLE_SEMA) | \
+BIT(I915_SAMPLE_QUEUED))
 
 #define ENGINE_SAMPLE_BITS (1 << I915_PMU_SAMPLE_BITS)
 
@@ -199,6 +200,11 @@ static void engines_sample(struct drm_i915_private 
*dev_priv)
 
update_sample(>pmu.sample[I915_SAMPLE_SEMA],
  PERIOD, !!(val & RING_WAIT_SEMAPHORE));
+
+   if (engine->pmu.enable & BIT(I915_SAMPLE_QUEUED))
+   update_sample(>pmu.sample[I915_SAMPLE_QUEUED],
+ I915_SAMPLE_QUEUED_DIVISOR,
+ 
atomic_read(>request_stats.queued));
}
 
if (fw)
@@ -296,6 +302,7 @@ engine_event_status(struct intel_engine_cs *engine,
switch (sample) {
case I915_SAMPLE_BUSY:
case I915_SAMPLE_WAIT:
+   case I915_SAMPLE_QUEUED:
break;
case I915_SAMPLE_SEMA:
if (INTEL_GEN(engine->i915) < 6)
@@ -497,6 +504,9 @@ static u64 __i915_pmu_event_read(struct perf_event *event)
} else {
val = engine->pmu.sample[sample].cur;
}
+
+   if (sample == I915_SAMPLE_QUEUED)
+   val = div_u64(val, FREQUENCY);
} else {
switch (event->attr.config) {
case I915_PMU_ACTUAL_FREQUENCY:
@@ -752,6 +762,16 @@ static const struct attribute_group 
*i915_pmu_attr_groups[] = {
 { \
.sample = (__sample), \
.name = (__name), \
+   .suffix = "unit", \
+   .value = "ns", \
+}
+
+#define __engine_event_scale(__sample, __name, __scale) \
+{ \
+   .sample = (__sample), \
+   .name = (__name), \
+   .suffix = "scale", \
+   .value = (__scale), \
 }
 
 static struct i915_ext_attribute *
@@ -779,6 +799,9 @@ add_pmu_attr(struct perf_pmu_events_attr *attr, const char 
*name,
return ++attr;
 }
 
+/* No brackets or quotes below please. */
+#define I915_SAMPLE_QUEUED_SCALE 0.0009765625
+
 static struct attribute **
 create_event_attributes(struct drm_i915_private *i915)
 {
@@ -795,10 +818,14 @@ create_event_attributes(struct drm_i915_private *i915)
static const struct {
enum drm_i915_pmu_engine_sample sample;
char *name;
+   char *suffix;
+   char *value;
} engine_events[] = {
__engine_event(I915_SAMPLE_BUSY, "busy"),
__engine_event(I915_SAMPLE_SEMA, "sema"),
__engine_event(I915_SAMPLE_WAIT, "wait"),
+   __engine_event_scale(I915_SAMPLE_QUEUED, "queued",
+__stringify(I915_SAMPLE_QUEUED_SCALE)),
};
unsigned int count = 0;
struct perf_pmu_events_attr *pmu_attr = NULL, *pmu_iter;
@@ -808,6 +835,9 @@ create_event_attributes(struct drm_i915_private *i915)
enum intel_engine_id id;
unsigned int i;
 
+   BUILD_BUG_ON(I915_SAMPLE_QUEUED_DIVISOR !=
+(1 / I915_SAMPLE_QUEUED_SCALE));
+
/* Count how many counters we will be exposing. */
for (i = 0; i < ARRAY_SIZE(events); i++) {
if (!config_status(i915, events[i].config))
@@ -885,13 +915,15 @@ create_event_attributes(struct drm_i915_private *i915)

engine->instance,

engine_events[i].sample));
 
-   str = kasprintf(GFP_KERNEL, "%s-%s.unit",
-   engine->name, engine_events[i].name);
+   str = kasprintf(GFP_KERNEL, "%s-%s.%s",
+   engine->name, engine_events[i].name,
+   engine_events[i].suffix);
if (!str)
goto err;
 
*attr_iter++ = 

[Intel-gfx] [PATCH 3/7] drm/i915: Keep a count of requests submitted from userspace

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Keep a count of requests submitted from userspace and not yet runnable due
unresolved dependencies.

v2: Rename and move under the container struct. (Chris Wilson)
v3: Rebase.

Signed-off-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_request.c | 3 +++
 drivers/gpu/drm/i915/intel_engine_cs.c  | 3 ++-
 drivers/gpu/drm/i915/intel_ringbuffer.h | 8 
 3 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_request.c 
b/drivers/gpu/drm/i915/i915_request.c
index 2052028c1d68..79bb26928263 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -634,6 +634,7 @@ submit_notify(struct i915_sw_fence *fence, enum 
i915_sw_fence_notify state)
rcu_read_lock();
request->engine->submit_request(request);
rcu_read_unlock();
+   atomic_dec(>engine->request_stats.queued);
break;
 
case FENCE_FREE:
@@ -1112,6 +1113,8 @@ void __i915_request_add(struct i915_request *request, 
bool flush_caches)
engine->schedule(request, request->ctx->priority);
rcu_read_unlock();
 
+   atomic_inc(>request_stats.queued);
+
local_bh_disable();
i915_sw_fence_commit(>submit);
local_bh_enable(); /* Kick the execlists tasklet if just scheduled */
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 3726544cfb00..fa9aceb076b4 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1917,12 +1917,13 @@ void intel_engine_dump(struct intel_engine_cs *engine,
if (i915_terminally_wedged(>i915->gpu_error))
drm_printf(m, "*** WEDGED ***\n");
 
-   drm_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [%d ms], 
inflight %d, runnable %u\n",
+   drm_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [%d ms], 
inflight %d, queued %u, runnable %u\n",
   intel_engine_get_seqno(engine),
   intel_engine_last_submit(engine),
   engine->hangcheck.seqno,
   jiffies_to_msecs(jiffies - 
engine->hangcheck.action_timestamp),
   engine->timeline->inflight_seqnos,
+  atomic_read(>request_stats.queued),
   engine->request_stats.runnable);
drm_printf(m, "\tReset count: %d (global %d)\n",
   i915_reset_engine_count(error, engine),
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h 
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index e98e007cb96b..810ef79959f2 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -339,6 +339,14 @@ struct intel_engine_cs {
struct drm_i915_gem_object *default_state;
 
struct {
+   /**
+* @queued: Number of submitted requests with dependencies.
+*
+* Count of requests waiting for dependencies before they can be
+* submitted to the backend.
+*/
+   atomic_t queued;
+
/**
 * @runnable: Number of runnable requests sent to the backend.
 *
-- 
2.14.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 7/7] drm/i915: Engine queues query

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

As well as exposing active requests on engines via PMU, we can also export
the current raw values (as tracked by i915 command submission) via a
dedicated query.

This is to satisfy customers who have userspace load balancing solutions
implemented on top of their custom kernel patches.

Userspace is now able to include DRM_I915_QUERY_ENGINE_QUEUES in their
query list, pointing to initialized struct drm_i915_query_engine_queues
entry. Fields describing engine class and instance userspace would like to
know about need to be filled in, and i915 will fill in the rest.

Multiple engines can be queried in one go by having multiple queries in
the query list.

Signed-off-by: Tvrtko Ursulin 
Cc: Dmitry Rogozhkin 
---
 drivers/gpu/drm/i915/i915_query.c | 43 +++
 include/uapi/drm/i915_drm.h   | 26 +++
 2 files changed, 69 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_query.c 
b/drivers/gpu/drm/i915/i915_query.c
index 3ace929dd90f..b3bc69e8deb7 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -82,9 +82,52 @@ static int query_topology_info(struct drm_i915_private 
*dev_priv,
return total_length;
 }
 
+static int
+query_engine_queues(struct drm_i915_private *i915,
+   struct drm_i915_query_item *query_item)
+{
+   struct drm_i915_query_engine_queues __user *query_ptr =
+   u64_to_user_ptr(query_item->data_ptr);
+   struct drm_i915_query_engine_queues query;
+   struct intel_engine_cs *engine;
+   const int len = sizeof(query);
+   unsigned int i;
+
+   if (query_item->flags)
+   return -EINVAL;
+
+   if (!query_item->length)
+   return len;
+   else if (query_item->length < len)
+   return -ENOSPC;
+
+   if (copy_from_user(, query_ptr, len))
+   return -EFAULT;
+
+   for (i = 0; i < ARRAY_SIZE(query.rsvd); i++) {
+   if (query.rsvd[i])
+   return -EINVAL;
+   }
+
+   engine = intel_engine_lookup_user(i915, query.class, query.instance);
+   if (!engine)
+   return -ENOENT;
+
+   query.queued = atomic_read(>request_stats.queued);
+   query.runnable = engine->request_stats.runnable;
+   query.running = intel_engine_last_submit(engine) -
+   intel_engine_get_seqno(engine);
+
+   if (copy_to_user(query_ptr, , len))
+   return -EFAULT;
+
+   return len;
+}
+
 static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,
struct drm_i915_query_item *query_item) 
= {
query_topology_info,
+   query_engine_queues,
 };
 
 int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 9a00c30e4071..064c3d620286 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1637,6 +1637,7 @@ struct drm_i915_perf_oa_config {
 struct drm_i915_query_item {
__u64 query_id;
 #define DRM_I915_QUERY_TOPOLOGY_INFO1
+#define DRM_I915_QUERY_ENGINE_QUEUES   2
 
/*
 * When set to zero by userspace, this is filled with the size of the
@@ -1734,6 +1735,31 @@ struct drm_i915_query_topology_info {
__u8 data[];
 };
 
+/**
+ * struct drm_i915_query_engine_queues
+ *
+ * Engine queues query enables userspace to query current counts of active
+ * requests in their different states.
+ */
+struct drm_i915_query_engine_queues {
+   /** Engine class as in enum drm_i915_gem_engine_class. */
+   __u16 class;
+
+   /** Engine instance number. */
+   __u16 instance;
+
+   /** Number of requests with unresolved fences and dependencies. */
+   __u32 queued;
+
+   /** Number of ready requests waiting on a slot on GPU. */
+   __u32 runnable;
+
+   /** Number of requests executing on the GPU. */
+   __u32 running;
+
+   __u32 rsvd[5];
+};
+
 #if defined(__cplusplus)
 }
 #endif
-- 
2.14.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 6/7] drm/i915/pmu: Add running counter

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

We add a PMU counter to expose the number of requests currently executing
on the GPU.

This is useful to analyze the overall load of the system.

v2:
 * Rebase.
 * Drop floating point constant. (Chris Wilson)

v3:
 * Change scale to 1024 for faster arithmetics. (Chris Wilson)

Signed-off-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_pmu.c | 18 --
 drivers/gpu/drm/i915/intel_ringbuffer.h |  2 +-
 include/uapi/drm/i915_drm.h |  5 +
 3 files changed, 22 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index afc561e1aa92..bd7e695fc663 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -17,7 +17,8 @@
 BIT(I915_SAMPLE_WAIT) | \
 BIT(I915_SAMPLE_SEMA) | \
 BIT(I915_SAMPLE_QUEUED) | \
-BIT(I915_SAMPLE_RUNNABLE))
+BIT(I915_SAMPLE_RUNNABLE) | \
+BIT(I915_SAMPLE_RUNNING))
 
 #define ENGINE_SAMPLE_BITS (1 << I915_PMU_SAMPLE_BITS)
 
@@ -211,6 +212,11 @@ static void engines_sample(struct drm_i915_private 
*dev_priv)
update_sample(>pmu.sample[I915_SAMPLE_RUNNABLE],
  I915_SAMPLE_RUNNABLE_DIVISOR,
  engine->request_stats.runnable);
+
+   if (engine->pmu.enable & BIT(I915_SAMPLE_RUNNING))
+   update_sample(>pmu.sample[I915_SAMPLE_RUNNING],
+ I915_SAMPLE_RUNNING_DIVISOR,
+ last_seqno - current_seqno);
}
 
if (fw)
@@ -310,6 +316,7 @@ engine_event_status(struct intel_engine_cs *engine,
case I915_SAMPLE_WAIT:
case I915_SAMPLE_QUEUED:
case I915_SAMPLE_RUNNABLE:
+   case I915_SAMPLE_RUNNING:
break;
case I915_SAMPLE_SEMA:
if (INTEL_GEN(engine->i915) < 6)
@@ -513,7 +520,8 @@ static u64 __i915_pmu_event_read(struct perf_event *event)
}
 
if (sample == I915_SAMPLE_QUEUED ||
-   sample == I915_SAMPLE_RUNNABLE)
+   sample == I915_SAMPLE_RUNNABLE ||
+   sample == I915_SAMPLE_RUNNING)
val = div_u64(val, FREQUENCY);
} else {
switch (event->attr.config) {
@@ -810,6 +818,7 @@ add_pmu_attr(struct perf_pmu_events_attr *attr, const char 
*name,
 /* No brackets or quotes below please. */
 #define I915_SAMPLE_QUEUED_SCALE 0.0009765625
 #define I915_SAMPLE_RUNNABLE_SCALE 0.0009765625
+#define I915_SAMPLE_RUNNING_SCALE 0.0009765625
 
 static struct attribute **
 create_event_attributes(struct drm_i915_private *i915)
@@ -837,6 +846,8 @@ create_event_attributes(struct drm_i915_private *i915)
 __stringify(I915_SAMPLE_QUEUED_SCALE)),
__engine_event_scale(I915_SAMPLE_RUNNABLE, "runnable",
 __stringify(I915_SAMPLE_RUNNABLE_SCALE)),
+   __engine_event_scale(I915_SAMPLE_RUNNING, "running",
+__stringify(I915_SAMPLE_RUNNING_SCALE)),
};
unsigned int count = 0;
struct perf_pmu_events_attr *pmu_attr = NULL, *pmu_iter;
@@ -852,6 +863,9 @@ create_event_attributes(struct drm_i915_private *i915)
BUILD_BUG_ON(I915_SAMPLE_RUNNABLE_DIVISOR !=
 (1 / I915_SAMPLE_RUNNABLE_SCALE));
 
+   BUILD_BUG_ON(I915_SAMPLE_RUNNING_DIVISOR !=
+(1 / I915_SAMPLE_RUNNING_SCALE));
+
/* Count how many counters we will be exposing. */
for (i = 0; i < ARRAY_SIZE(events); i++) {
if (!config_status(i915, events[i].config))
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h 
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 5d7532b185fe..fe1b7d0a94e9 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -414,7 +414,7 @@ struct intel_engine_cs {
 *
 * Our internal timer stores the current counters in this field.
 */
-#define I915_ENGINE_SAMPLE_MAX (I915_SAMPLE_RUNNABLE + 1)
+#define I915_ENGINE_SAMPLE_MAX (I915_SAMPLE_RUNNING + 1)
struct i915_pmu_sample sample[I915_ENGINE_SAMPLE_MAX];
} pmu;
 
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index cf0265b20e37..9a00c30e4071 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -113,11 +113,13 @@ enum drm_i915_pmu_engine_sample {
I915_SAMPLE_SEMA = 2,
I915_SAMPLE_QUEUED = 3,
I915_SAMPLE_RUNNABLE = 4,
+   I915_SAMPLE_RUNNING = 5,
 };
 
  /* Divide counter value by divisor to get the real value. */
 #define I915_SAMPLE_QUEUED_DIVISOR (1024)
 #define I915_SAMPLE_RUNNABLE_DIVISOR (1024)
+#define I915_SAMPLE_RUNNING_DIVISOR (1024)
 
 #define 

[Intel-gfx] [PATCH 5/7] drm/i915/pmu: Add runnable counter

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

We add a PMU counter to expose the number of requests with resolved
dependencies waiting for a slot on the GPU to run.

This is useful to analyze the overall load of the system.

v2: Don't limit to gen8+.

v3:
 * Rebase for dynamic sysfs.
 * Drop currently executing requests.

v4:
 * Sync with internal renaming.
 * Drop floating point constant. (Chris Wilson)

v5:
 * Change scale to 1024 for faster arithmetics. (Chris Wilson)

Signed-off-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_pmu.c | 18 --
 drivers/gpu/drm/i915/intel_ringbuffer.h |  2 +-
 include/uapi/drm/i915_drm.h |  7 ++-
 3 files changed, 23 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 07f5cac97b56..afc561e1aa92 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -16,7 +16,8 @@
(BIT(I915_SAMPLE_BUSY) | \
 BIT(I915_SAMPLE_WAIT) | \
 BIT(I915_SAMPLE_SEMA) | \
-BIT(I915_SAMPLE_QUEUED))
+BIT(I915_SAMPLE_QUEUED) | \
+BIT(I915_SAMPLE_RUNNABLE))
 
 #define ENGINE_SAMPLE_BITS (1 << I915_PMU_SAMPLE_BITS)
 
@@ -205,6 +206,11 @@ static void engines_sample(struct drm_i915_private 
*dev_priv)
update_sample(>pmu.sample[I915_SAMPLE_QUEUED],
  I915_SAMPLE_QUEUED_DIVISOR,
  
atomic_read(>request_stats.queued));
+
+   if (engine->pmu.enable & BIT(I915_SAMPLE_RUNNABLE))
+   update_sample(>pmu.sample[I915_SAMPLE_RUNNABLE],
+ I915_SAMPLE_RUNNABLE_DIVISOR,
+ engine->request_stats.runnable);
}
 
if (fw)
@@ -303,6 +309,7 @@ engine_event_status(struct intel_engine_cs *engine,
case I915_SAMPLE_BUSY:
case I915_SAMPLE_WAIT:
case I915_SAMPLE_QUEUED:
+   case I915_SAMPLE_RUNNABLE:
break;
case I915_SAMPLE_SEMA:
if (INTEL_GEN(engine->i915) < 6)
@@ -505,7 +512,8 @@ static u64 __i915_pmu_event_read(struct perf_event *event)
val = engine->pmu.sample[sample].cur;
}
 
-   if (sample == I915_SAMPLE_QUEUED)
+   if (sample == I915_SAMPLE_QUEUED ||
+   sample == I915_SAMPLE_RUNNABLE)
val = div_u64(val, FREQUENCY);
} else {
switch (event->attr.config) {
@@ -801,6 +809,7 @@ add_pmu_attr(struct perf_pmu_events_attr *attr, const char 
*name,
 
 /* No brackets or quotes below please. */
 #define I915_SAMPLE_QUEUED_SCALE 0.0009765625
+#define I915_SAMPLE_RUNNABLE_SCALE 0.0009765625
 
 static struct attribute **
 create_event_attributes(struct drm_i915_private *i915)
@@ -826,6 +835,8 @@ create_event_attributes(struct drm_i915_private *i915)
__engine_event(I915_SAMPLE_WAIT, "wait"),
__engine_event_scale(I915_SAMPLE_QUEUED, "queued",
 __stringify(I915_SAMPLE_QUEUED_SCALE)),
+   __engine_event_scale(I915_SAMPLE_RUNNABLE, "runnable",
+__stringify(I915_SAMPLE_RUNNABLE_SCALE)),
};
unsigned int count = 0;
struct perf_pmu_events_attr *pmu_attr = NULL, *pmu_iter;
@@ -838,6 +849,9 @@ create_event_attributes(struct drm_i915_private *i915)
BUILD_BUG_ON(I915_SAMPLE_QUEUED_DIVISOR !=
 (1 / I915_SAMPLE_QUEUED_SCALE));
 
+   BUILD_BUG_ON(I915_SAMPLE_RUNNABLE_DIVISOR !=
+(1 / I915_SAMPLE_RUNNABLE_SCALE));
+
/* Count how many counters we will be exposing. */
for (i = 0; i < ARRAY_SIZE(events); i++) {
if (!config_status(i915, events[i].config))
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h 
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 62a198f5ba80..5d7532b185fe 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -414,7 +414,7 @@ struct intel_engine_cs {
 *
 * Our internal timer stores the current counters in this field.
 */
-#define I915_ENGINE_SAMPLE_MAX (I915_SAMPLE_QUEUED + 1)
+#define I915_ENGINE_SAMPLE_MAX (I915_SAMPLE_RUNNABLE + 1)
struct i915_pmu_sample sample[I915_ENGINE_SAMPLE_MAX];
} pmu;
 
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 6094cc9ca6d9..cf0265b20e37 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -111,11 +111,13 @@ enum drm_i915_pmu_engine_sample {
I915_SAMPLE_BUSY = 0,
I915_SAMPLE_WAIT = 1,
I915_SAMPLE_SEMA = 2,
-   I915_SAMPLE_QUEUED = 3
+   I915_SAMPLE_QUEUED = 3,
+   I915_SAMPLE_RUNNABLE = 4,
 };
 
  /* Divide counter value by divisor to get the real value. */
 

[Intel-gfx] [PATCH 2/7] drm/i915: Keep a count of requests waiting for a slot on GPU

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Keep a per-engine number of runnable (waiting for GPU time) requests.

v2:
 * Move queued increment from insert_request to execlist_submit_request to
   avoid bumping when re-ordering for priority.
 * Support the counter on the ringbuffer submission path as well, albeit
   just notionally. (Chris Wilson)

v3:
 * Rebase.

v4:
 * Rename and move the stats into a container structure. (Chris Wilson)

v5:
 * Re-order fields in struct intel_engine_cs. (Chris Wilson)

v6-v8:
 * Rebases.

Signed-off-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_request.c | 7 +++
 drivers/gpu/drm/i915/intel_engine_cs.c  | 5 +++--
 drivers/gpu/drm/i915/intel_lrc.c| 1 +
 drivers/gpu/drm/i915/intel_ringbuffer.h | 9 +
 4 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_request.c 
b/drivers/gpu/drm/i915/i915_request.c
index 43c7134a9b93..2052028c1d68 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -525,6 +525,9 @@ void __i915_request_submit(struct i915_request *request)
engine->emit_breadcrumb(request,
request->ring->vaddr + request->postfix);
 
+   GEM_BUG_ON(engine->request_stats.runnable == 0);
+   engine->request_stats.runnable--;
+
spin_lock(>timeline->lock);
list_move_tail(>link, >requests);
spin_unlock(>timeline->lock);
@@ -542,6 +545,8 @@ void i915_request_submit(struct i915_request *request)
/* Will be called from irq-context when using foreign fences. */
spin_lock_irqsave(>timeline->lock, flags);
 
+   engine->request_stats.runnable++;
+
__i915_request_submit(request);
 
spin_unlock_irqrestore(>timeline->lock, flags);
@@ -581,6 +586,8 @@ void __i915_request_unsubmit(struct i915_request *request)
timeline = request->timeline;
GEM_BUG_ON(timeline == engine->timeline);
 
+   engine->request_stats.runnable++;
+
spin_lock(>lock);
list_move(>link, >requests);
spin_unlock(>lock);
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 337dfa56a738..3726544cfb00 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1917,12 +1917,13 @@ void intel_engine_dump(struct intel_engine_cs *engine,
if (i915_terminally_wedged(>i915->gpu_error))
drm_printf(m, "*** WEDGED ***\n");
 
-   drm_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [%d ms], 
inflight %d\n",
+   drm_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [%d ms], 
inflight %d, runnable %u\n",
   intel_engine_get_seqno(engine),
   intel_engine_last_submit(engine),
   engine->hangcheck.seqno,
   jiffies_to_msecs(jiffies - 
engine->hangcheck.action_timestamp),
-  engine->timeline->inflight_seqnos);
+  engine->timeline->inflight_seqnos,
+  engine->request_stats.runnable);
drm_printf(m, "\tReset count: %d (global %d)\n",
   i915_reset_engine_count(error, engine),
   i915_reset_count(error));
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 53f1c009ed7b..46bacd98a360 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1033,6 +1033,7 @@ static void execlists_submit_request(struct i915_request 
*request)
 
queue_request(engine, >priotree, rq_prio(request));
submit_queue(engine, rq_prio(request));
+   engine->request_stats.runnable++;
 
GEM_BUG_ON(!engine->execlists.first);
GEM_BUG_ON(list_empty(>priotree.link));
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h 
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 828a1f924405..e98e007cb96b 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -338,6 +338,15 @@ struct intel_engine_cs {
 
struct drm_i915_gem_object *default_state;
 
+   struct {
+   /**
+* @runnable: Number of runnable requests sent to the backend.
+*
+* Count of requests waiting for the GPU to execute them.
+*/
+   unsigned int runnable;
+   } request_stats;
+
atomic_t irq_count;
unsigned long irq_posted;
 #define ENGINE_IRQ_BREADCRUMB 0
-- 
2.14.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 1/7] drm/i915/pmu: Fix enable count array size and bounds checking

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Enable count array is supposed to have one counter for each possible
engine sampler. As such array sizing and bounds checking is not
correct when more engine samplers are added.

At the same time tidy the assert for readability and robustness.

Signed-off-by: Tvrtko Ursulin 
Fixes: b46a33e271ed ("drm/i915/pmu: Expose a PMU interface for perf queries")
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_pmu.c | 13 +
 drivers/gpu/drm/i915/intel_ringbuffer.h |  2 +-
 2 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 11fb76bd3860..eb60943671b3 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -549,7 +549,8 @@ static void i915_pmu_enable(struct perf_event *event)
 * Update the bitmask of enabled events and increment
 * the event reference counter.
 */
-   GEM_BUG_ON(bit >= I915_PMU_MASK_BITS);
+   BUILD_BUG_ON(ARRAY_SIZE(i915->pmu.enable_count) != I915_PMU_MASK_BITS);
+   GEM_BUG_ON(bit >= ARRAY_SIZE(i915->pmu.enable_count));
GEM_BUG_ON(i915->pmu.enable_count[bit] == ~0);
i915->pmu.enable |= BIT_ULL(bit);
i915->pmu.enable_count[bit]++;
@@ -573,7 +574,10 @@ static void i915_pmu_enable(struct perf_event *event)
GEM_BUG_ON(!engine);
engine->pmu.enable |= BIT(sample);
 
-   GEM_BUG_ON(sample >= I915_PMU_SAMPLE_BITS);
+   BUILD_BUG_ON(ARRAY_SIZE(engine->pmu.enable_count) !=
+(1 << I915_PMU_SAMPLE_BITS));
+   GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.enable_count));
+   GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.sample));
GEM_BUG_ON(engine->pmu.enable_count[sample] == ~0);
engine->pmu.enable_count[sample]++;
}
@@ -605,7 +609,8 @@ static void i915_pmu_disable(struct perf_event *event)
  engine_event_class(event),
  engine_event_instance(event));
GEM_BUG_ON(!engine);
-   GEM_BUG_ON(sample >= I915_PMU_SAMPLE_BITS);
+   GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.enable_count));
+   GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.sample));
GEM_BUG_ON(engine->pmu.enable_count[sample] == 0);
/*
 * Decrement the reference count and clear the enabled
@@ -615,7 +620,7 @@ static void i915_pmu_disable(struct perf_event *event)
engine->pmu.enable &= ~BIT(sample);
}
 
-   GEM_BUG_ON(bit >= I915_PMU_MASK_BITS);
+   GEM_BUG_ON(bit >= ARRAY_SIZE(i915->pmu.enable_count));
GEM_BUG_ON(i915->pmu.enable_count[bit] == 0);
/*
 * Decrement the reference count and clear the enabled
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h 
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 1f50727a5ddb..828a1f924405 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -391,7 +391,7 @@ struct intel_engine_cs {
 *
 * Index number corresponds to the bit number from @enable.
 */
-   unsigned int enable_count[I915_PMU_SAMPLE_BITS];
+   unsigned int enable_count[1 << I915_PMU_SAMPLE_BITS];
/**
 * @sample: Counter values for sampling events.
 *
-- 
2.14.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v4 0/7] Queued/runnable/running engine stats

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Per-engine queue depths are an interesting metric for analyzing the system load
and also for users who wish to use it to load balance their submissions based
on it.

In this version I have split the metrics into three separate counters:

1. QUEUED - From execbuf time to request being runnable - runnable meaning until
dependencies have been resolved and fences signaled.
2. RUNNABLE - From runnable to running on the GPU.
3. RUNNING - Running on the GPU.

When inspected with perf stat the output looks roughly like this:

#   time counts unit events
   201.160490145   0.01  i915/rcs0-queued/
   201.160490145  19.13  i915/rcs0-runnable/
   201.160490145   2.39  i915/rcs0-running/

The reported numbers are average queue depths for the last query period.

v2:
 * Review feedback (see patch changelogs).
 * Renamed the counters and re-ordered some patches.

v3:
 * Review feedback and rebase.

v4:
 * Addition of last patch in the series, which supports a customer requirement
   to expose instantaneous queue values via the i915 query API.

Tvrtko Ursulin (7):
  drm/i915/pmu: Fix enable count array size and bounds checking
  drm/i915: Keep a count of requests waiting for a slot on GPU
  drm/i915: Keep a count of requests submitted from userspace
  drm/i915/pmu: Add queued counter
  drm/i915/pmu: Add runnable counter
  drm/i915/pmu: Add running counter
  drm/i915: Engine queues query

 drivers/gpu/drm/i915/i915_pmu.c | 81 +
 drivers/gpu/drm/i915/i915_query.c   | 43 +
 drivers/gpu/drm/i915/i915_request.c | 10 
 drivers/gpu/drm/i915/intel_engine_cs.c  |  6 ++-
 drivers/gpu/drm/i915/intel_lrc.c|  1 +
 drivers/gpu/drm/i915/intel_ringbuffer.h | 21 -
 include/uapi/drm/i915_drm.h | 45 +-
 7 files changed, 194 insertions(+), 13 deletions(-)

-- 
2.14.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Promote .format_mod_supported() to the lead role

[Patchwork]

== Series Details ==

Series: drm/i915: Promote .format_mod_supported() to the lead role
URL   : https://patchwork.freedesktop.org/series/40207/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
bd9ae7d6edf8 drm/i915: Promote .format_mod_supported() to the lead role
-:19: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#19: 
References: 
https://lists.freedesktop.org/archives/dri-devel/2018-March/169782.html

total: 0 errors, 1 warnings, 0 checks, 552 lines checked

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH] drm/i915: make GEM_WARN_ON less terrible

[Matthew Auld]

GEM_WARN_ON() was originally intended to be used only as:

   if (GEM_WARN_ON(expr))
...

but it just so happens to also work as simply:

   GEM_WARN_ON(expr);

since it just wraps WARN_ON, which is a little misleading since for
!DRM_I915_DEBUG_GEM builds the second case will actually break the
build. Given that there are some patches floating around which seem to
miss this, it probably makes sense to just make it work for both cases.

Signed-off-by: Matthew Auld 
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_gem.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.h b/drivers/gpu/drm/i915/i915_gem.h
index 8922344fc21b..6a4375437b88 100644
--- a/drivers/gpu/drm/i915/i915_gem.h
+++ b/drivers/gpu/drm/i915/i915_gem.h
@@ -44,7 +44,7 @@
 
 #else
 #define GEM_BUG_ON(expr) BUILD_BUG_ON_INVALID(expr)
-#define GEM_WARN_ON(expr) (BUILD_BUG_ON_INVALID(expr), 0)
+#define GEM_WARN_ON(expr) ({BUILD_BUG_ON_INVALID(expr), 0;})
 
 #define GEM_DEBUG_DECL(var)
 #define GEM_DEBUG_EXEC(expr) do { } while (0)
-- 
2.14.3

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3,1/3] drm/i915/guc: Unify naming of private GuC action functions

[Patchwork]

== Series Details ==

Series: series starting with [v3,1/3] drm/i915/guc: Unify naming of private GuC 
action functions
URL   : https://patchwork.freedesktop.org/series/40204/
State : success

== Summary ==

Series 40204v1 series starting with [v3,1/3] drm/i915/guc: Unify naming of 
private GuC action functions
https://patchwork.freedesktop.org/api/1.0/series/40204/revisions/1/mbox/

 Known issues:

Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-c:
pass   -> FAIL   (fi-skl-guc) fdo#103191

fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:429s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:441s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:379s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:537s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:297s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:512s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:517s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:511s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:407s
fi-cfl-s2total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:579s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:514s
fi-cnl-drrs  total:285  pass:254  dwarn:3   dfail:0   fail:0   skip:28  
time:542s
fi-elk-e7500 total:285  pass:225  dwarn:1   dfail:0   fail:0   skip:59  
time:430s
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:321s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:537s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:403s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:422s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:472s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:429s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:474s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:464s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:512s
fi-pnv-d510  total:285  pass:219  dwarn:1   dfail:0   fail:0   skip:65  
time:653s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:446s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:528s
fi-skl-6700hqtotal:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:541s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:503s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:490s
fi-skl-guc   total:285  pass:256  dwarn:0   dfail:0   fail:1   skip:28  
time:426s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:444s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:585s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:400s

260af42eeff094e4768265a6ec8bbcb29b87e9a0 drm-tip: 2018y-03m-19d-17h-15m-08s UTC 
integration manifest
f98517410482 drm/i915/guc: Move enable/disable msg functions to GuC header
ed8c898fe51f drm/i915/guc: Drop union guc_log_control
bff16e4506e0 drm/i915/guc: Unify naming of private GuC action functions

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8398/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915/guc: Handle GuC log flush event in dedicated function

[Patchwork]

== Series Details ==

Series: drm/i915/guc: Handle GuC log flush event in dedicated function
URL   : https://patchwork.freedesktop.org/series/40183/
State : warning

== Summary ==

 Possible new issues:

Test kms_atomic_transition:
Subgroup plane-all-modeset-transition:
pass   -> SKIP   (shard-snb)
Test kms_properties:
Subgroup crtc-properties-legacy:
pass   -> SKIP   (shard-snb)
Test kms_vblank:
Subgroup pipe-b-query-forked-busy:
pass   -> SKIP   (shard-snb)

 Known issues:

Test kms_flip:
Subgroup dpms-vs-vblank-race:
fail   -> PASS   (shard-hsw) fdo#103060
Subgroup plain-flip-fb-recreate:
pass   -> FAIL   (shard-hsw) fdo#100368
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-render:
pass   -> SKIP   (shard-snb) fdo#101623 +1

fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623

shard-apltotal:3442 pass:1814 dwarn:1   dfail:0   fail:7   skip:1619 
time:13020s
shard-hswtotal:3442 pass:1767 dwarn:1   dfail:0   fail:2   skip:1671 
time:11869s
shard-snbtotal:3442 pass:1353 dwarn:1   dfail:0   fail:2   skip:2086 
time:7228s
Blacklisted hosts:
shard-kbltotal:3442 pass:1897 dwarn:42  dfail:0   fail:9   skip:1494 
time:9925s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8392/shards.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v2] drm/i915: Reword warning for missing cases

[Lucas De Marchi]

In some places we end up converting switch statements to a series of
if/else, particularly when introducing helper functions to handle a
group of cases. It's tempting to either leave a wrong warning (since now
we don't have a switch case anymore) or to convert to WARN(1, ...),
but we can just provide a better message and avoid the doubt when such
conversions arrise.

Introducing a warning inside i915_driver_load() just for tests we get:

[ 4535.233717] Missing case (ret == 0)
[ 4535.233868] WARNING: CPU: 1 PID: 795 at drivers/gpu/drm/i915/i915_drv.c:1341 
i915_driver_load+0x42/0x10e0 [i915]

which is clear enough.

v2: remove __func__ since this is already on the warning.

Cc: Chris Wilson 
Cc: Ville Syrjälä 
Cc: Daniel Vetter 
Signed-off-by: Lucas De Marchi 
---
 drivers/gpu/drm/i915/i915_utils.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_utils.h 
b/drivers/gpu/drm/i915/i915_utils.h
index 51dbfe5bb418..0695717522ea 100644
--- a/drivers/gpu/drm/i915/i915_utils.h
+++ b/drivers/gpu/drm/i915/i915_utils.h
@@ -40,8 +40,8 @@
 #undef WARN_ON_ONCE
 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) 
")")
 
-#define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
-(long)(x), __func__)
+#define MISSING_CASE(x) WARN(1, "Missing case (%s == %ld)\n", \
+__stringify(x), (long)(x))
 
 #if GCC_VERSION >= 7
 #define add_overflows(A, B) \
-- 
2.14.3

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.BAT: warning for drm: Restore planes after load detection

[Patchwork]

== Series Details ==

Series: drm: Restore planes after load detection
URL   : https://patchwork.freedesktop.org/series/40201/
State : warning

== Summary ==

Series 40201v1 drm: Restore planes after load detection
https://patchwork.freedesktop.org/api/1.0/series/40201/revisions/1/mbox/

 Possible new issues:

Test drv_module_reload:
Subgroup basic-reload:
pass   -> DMESG-WARN (fi-gdg-551)

 Known issues:

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> DMESG-WARN (fi-skl-6600u) fdo#104108
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713
Test prime_vgem:
Subgroup basic-fence-flip:
pass   -> FAIL   (fi-ilk-650) fdo#104008

fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:432s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:445s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:386s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:541s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:297s
fi-bxt-dsi   total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  
time:522s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:513s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:520s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:504s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:409s
fi-cfl-s2total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:579s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:508s
fi-cnl-drrs  total:285  pass:254  dwarn:3   dfail:0   fail:0   skip:28  
time:532s
fi-elk-e7500 total:285  pass:225  dwarn:1   dfail:0   fail:0   skip:59  
time:425s
fi-gdg-551   total:285  pass:175  dwarn:1   dfail:0   fail:1   skip:108 
time:318s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:534s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:402s
fi-ilk-650   total:285  pass:224  dwarn:0   dfail:0   fail:1   skip:60  
time:427s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:473s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:427s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:476s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:467s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:511s
fi-pnv-d510  total:285  pass:219  dwarn:1   dfail:0   fail:0   skip:65  
time:656s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:440s
fi-skl-6600u total:285  pass:257  dwarn:1   dfail:0   fail:0   skip:27  
time:536s
fi-skl-6700hqtotal:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:545s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:499s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:492s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:426s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:445s
fi-snb-2520m total:242  pass:208  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:400s

9b79492f331e36cf2e08d65ab3221abb66f67844 drm-tip: 2018y-03m-19d-14h-18m-12s UTC 
integration manifest
19cdc1ec412f drm: Restore planes after load detection

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8397/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm: Restore planes after load detection

[Maarten Lankhorst]

Op 19-03-18 om 16:39 schreef Ville Syrjala:
> From: Ville Syrjälä 
>
> Actually turn the planes back on after were done with
> the load detection.
>
> Fixes: 20bdc112bbe4 ("drm/i915: Disable all planes for load detection, v2.")
> Cc: Maarten Lankhorst 
> Cc: Daniel Vetter 
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/intel_display.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 3e7ab75e1b41..34e5a883e42e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -9976,6 +9976,8 @@ int intel_get_load_detect_pipe(struct drm_connector 
> *connector,
>   ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, 
> connector));
>   if (!ret)
>   ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, 
> crtc));
> + if (!ret)
> + ret = drm_atomic_add_affected_planes(restore_state, crtc);
>   if (ret) {
>   DRM_DEBUG_KMS("Failed to create a copy of old state to restore: 
> %i\n", ret);
>   goto fail;

If you r-b the igt counterpart, then:

Reviewed-by: Maarten Lankhorst 

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH v3 2/3] drm/i915/guc: Drop union guc_log_control

[Michał Winiarski]

On Mon, Mar 19, 2018 at 04:20:02PM +, Michal Wajdeczko wrote:
> Usually we use shift/mask macros for bit field definitions.
> Union guc_log_control was not following that pattern.
> 
> Additional bonus:
> 
> add/remove: 0/0 grow/shrink: 0/1 up/down: 0/-25 (-25)
> Function old new   delta
> intel_guc_log_level_set  388 363 -25
> 
> v2: prevent out-of-range verbosity (MichalWi)
> 
> Signed-off-by: Michal Wajdeczko 
> Cc: Michal Winiarski 
> Cc: Sagar Arun Kamble 

Reviewed-by: Michał Winiarski 

-Michał

> ---
>  drivers/gpu/drm/i915/intel_guc_fwif.h | 16 +---
>  drivers/gpu/drm/i915/intel_guc_log.c  | 13 +
>  2 files changed, 10 insertions(+), 19 deletions(-)
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Trim error mask to known engines

[Chris Wilson]

Quoting Michel Thierry (2018-03-19 16:31:05)
> On 19/03/18 06:12, Chris Wilson wrote:
> > Quoting Chris Wilson (2018-03-16 21:49:59)
> >> For the convenience of userspace passing in an arbitrary reset mask,
> >> remove unknown engines from the set of engines that are to be reset.
> >> This means that we always follow a per-engine reset with a full-device
> >> reset when userspace writes -1 into debugfs/i915_wedged.
> 
> I thought that was the desired behaviour...
> 
> >>
> >> Reported-by: Michał Winiarski 
> >> Signed-off-by: Chris Wilson 
> >> Cc: Mika Kuoppala 
> >> Cc: Michał Winiarski 
> > 
> > Please? It papers over the issue in gem_exec_capture...
> > -Chris
> > 
> 
> Reviewed-by: Michel Thierry 

Snaffled it up so that CI stops spuriously tripping over
gem_exec_capture. We should arrange some faultinjection testing for
live_hangcheck selftests.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Add control flags to i915_handle_error()

[Chris Wilson]

Quoting Michel Thierry (2018-03-19 16:48:01)
> On 16/03/18 14:50, Chris Wilson wrote:
> > Not all callers want the GPU error to handled in the same way, so expose
> > a control parameter. In the first instance, some callers do not want the
> > heavyweight error capture so add a bit to request the state to be
> > captured and saved.
> > 
> > Signed-off-by: Chris Wilson 
> > Cc: Jeff McGee 
> > Cc: Mika Kuoppala 
> > ---
> >   drivers/gpu/drm/i915/i915_debugfs.c  |  4 ++--
> >   drivers/gpu/drm/i915/i915_drv.h  |  4 +++-
> >   drivers/gpu/drm/i915/i915_irq.c  | 22 
> > ++
> >   drivers/gpu/drm/i915/intel_hangcheck.c   |  6 +++---
> >   drivers/gpu/drm/i915/selftests/intel_hangcheck.c |  2 +-
> >   5 files changed, 23 insertions(+), 15 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> > b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 5378863e3238..03b74a92caed 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -3952,8 +3952,8 @@ i915_wedged_set(void *data, u64 val)
> >   engine->hangcheck.stalled = true;
> >   }
> >   
> > - i915_handle_error(i915, val, "Manually set wedged engine mask = %llx",
> > -   val);
> > + i915_handle_error(i915, val, I915_ERROR_CAPTURE,
> > +   "Manually set wedged engine mask = %llx", val);
> >   
> >   wait_on_bit(>gpu_error.flags,
> >   I915_RESET_HANDOFF,
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h 
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index e27ba8fb64e6..53009ba50640 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -2751,10 +2751,12 @@ static inline void i915_queue_hangcheck(struct 
> > drm_i915_private *dev_priv)
> >  _priv->gpu_error.hangcheck_work, delay);
> >   }
> >   
> > -__printf(3, 4)
> > +__printf(4, 5)
> >   void i915_handle_error(struct drm_i915_private *dev_priv,
> >  u32 engine_mask,
> > +unsigned long flags,
> >  const char *fmt, ...);
> > +#define I915_ERROR_CAPTURE BIT(0)
> >   
> Should this be in the new i915_gpu_error.h?

And move it over from i915_irq.c to somewhere more useful? Probably
intel_hangcheck.c since i915_gpu_error.c is conditionally compiled.

> >   extern void intel_irq_init(struct drm_i915_private *dev_priv);
> >   extern void intel_irq_fini(struct drm_i915_private *dev_priv);
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c 
> > b/drivers/gpu/drm/i915/i915_irq.c
> > index 44eef355e12c..b3a4dc7cb26c 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -2955,6 +2955,7 @@ static void i915_clear_error_registers(struct 
> > drm_i915_private *dev_priv)
> >* i915_handle_error - handle a gpu error
> >* @dev_priv: i915 device private
> >* @engine_mask: mask representing engines that are hung
> > + * @flags: control flags
> >* @fmt: Error message format string
> >*
> >* Do some basic checking of register state at error time and
> > @@ -2965,16 +2966,11 @@ static void i915_clear_error_registers(struct 
> > drm_i915_private *dev_priv)
> >*/
> >   void i915_handle_error(struct drm_i915_private *dev_priv,
> >  u32 engine_mask,
> > +unsigned long flags,
> >  const char *fmt, ...)
> >   {
> >   struct intel_engine_cs *engine;
> >   unsigned int tmp;
> > - va_list args;
> > - char error_msg[80];
> > -
> > - va_start(args, fmt);
> > - vscnprintf(error_msg, sizeof(error_msg), fmt, args);
> > - va_end(args);
> >   
> >   /*
> >* In most cases it's guaranteed that we get here with an RPM
> > @@ -2986,8 +2982,18 @@ void i915_handle_error(struct drm_i915_private 
> > *dev_priv,
> >   intel_runtime_pm_get(dev_priv);
> >   
> >   engine_mask &= INTEL_INFO(dev_priv)->ring_mask;
> > - i915_capture_error_state(dev_priv, engine_mask, error_msg);
> > - i915_clear_error_registers(dev_priv);
> > +
> > + if (flags & I915_ERROR_CAPTURE) {
> > + char error_msg[80];
> > + va_list args;
> > +
> > + va_start(args, fmt);
> > + vscnprintf(error_msg, sizeof(error_msg), fmt, args);
> > + va_end(args);
> > +
> > + i915_capture_error_state(dev_priv, engine_mask, error_msg);
> > + i915_clear_error_registers(dev_priv);
> > + }
>  else
> DRM_INFO or DRM_NOTE the error_msg  ?
> 
> Otherwise the 'kicking wait/semaphore' text from below will never be 
> printed.

I liked it disappearing ;)

So we should feed it to i915_reset(const char *reason). That could then
probably replace I915_RESET_QUIET.
-Chris
___

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/guc: Unify parameters of public CT functions

[Patchwork]

== Series Details ==

Series: drm/i915/guc: Unify parameters of public CT functions
URL   : https://patchwork.freedesktop.org/series/40197/
State : failure

== Summary ==

Series 40197v1 drm/i915/guc: Unify parameters of public CT functions
https://patchwork.freedesktop.org/api/1.0/series/40197/revisions/1/mbox/

 Possible new issues:

Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass   -> INCOMPLETE (fi-bxt-dsi)

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:438s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:441s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:380s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:536s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:298s
fi-bxt-dsi   total:217  pass:194  dwarn:0   dfail:0   fail:0   skip:22 
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:513s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:513s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:503s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:407s
fi-cfl-s2total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:579s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:510s
fi-cnl-drrs  total:285  pass:254  dwarn:3   dfail:0   fail:0   skip:28  
time:539s
fi-elk-e7500 total:285  pass:225  dwarn:1   dfail:0   fail:0   skip:59  
time:419s
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:319s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:533s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:403s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:429s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:474s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:427s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:473s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:462s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:511s
fi-pnv-d510  total:285  pass:219  dwarn:1   dfail:0   fail:0   skip:65  
time:653s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:445s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:533s
fi-skl-6700hqtotal:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:541s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:505s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:493s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:425s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:445s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:578s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:398s

9b79492f331e36cf2e08d65ab3221abb66f67844 drm-tip: 2018y-03m-19d-14h-18m-12s UTC 
integration manifest
b6545a236eb7 drm/i915/guc: Unify parameters of public CT functions

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8396/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Trim error mask to known engines

[Chris Wilson]

Quoting Michel Thierry (2018-03-19 16:31:05)
> On 19/03/18 06:12, Chris Wilson wrote:
> > Quoting Chris Wilson (2018-03-16 21:49:59)
> >> For the convenience of userspace passing in an arbitrary reset mask,
> >> remove unknown engines from the set of engines that are to be reset.
> >> This means that we always follow a per-engine reset with a full-device
> >> reset when userspace writes -1 into debugfs/i915_wedged.
> 
> I thought that was the desired behaviour...

The name has been misleading for a few years, from since we actually had
working GPU reset.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH i-g-t v8] tests/perf_pmu: Improve accuracy by waiting on spinner to start

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

More than one test assumes that the spinner is running pretty much
immediately after we have create or submitted it.

In actuality there is a variable delay, especially on execlists platforms,
between submission and spin batch starting to run on the hardware.

To enable tests which care about this level of timing to account for this,
we add a new spin batch constructor which provides an output field which
can be polled to determine when the batch actually started running.

This is implemented via MI_STOREDW_IMM from the spin batch, writing into
memory mapped page shared with userspace.

Using this facility from perf_pmu, where applicable, should improve very
occasional test fails across the set and platforms.

v2:
 Chris Wilson:
 * Use caching mapping if available.
 * Handle old gens better.
 * Use gem_can_store_dword.
 * Cache exec obj array in spin_batch_t for easier resubmit.

v3:
 * Forgot I915_EXEC_NO_RELOC. (Chris Wilson)

v4:
 * Mask out all non-engine flags in gem_can_store_dword.
 * Added some debug logging.

v5:
 * Fix relocs and batch munmap. (Chris)
 * Added assert idle spinner batch looks as expected.

v6:
 * Skip accuracy tests when !gem_can_store_dword.

v7:
 * Fix batch recursion reloc address.

v8:
 Chris Wilson:
 * Pull up gem_can_store_dword check before we start submitting.
 * Build spinner batch in a way we can skip store dword when not
   needed so we can run on SandyBridge.

Signed-off-by: Tvrtko Ursulin 
Suggested-by: Chris Wilson 
---
 lib/igt_dummyload.c  | 192 ---
 lib/igt_dummyload.h  |  11 +++
 lib/igt_gt.c |   2 +-
 lib/ioctl_wrappers.c |   2 +-
 lib/ioctl_wrappers.h |   1 +
 tests/perf_pmu.c | 183 +---
 6 files changed, 293 insertions(+), 98 deletions(-)

diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
index 4b20f23dfe26..ce84628095b5 100644
--- a/lib/igt_dummyload.c
+++ b/lib/igt_dummyload.c
@@ -74,35 +74,48 @@ fill_reloc(struct drm_i915_gem_relocation_entry *reloc,
reloc->write_domain = write_domains;
 }
 
-static int emit_recursive_batch(igt_spin_t *spin,
-   int fd, uint32_t ctx, unsigned engine,
-   uint32_t dep, bool out_fence)
+#define OUT_FENCE  (1 << 0)
+#define POLL_RUN   (1 << 1)
+
+static int
+emit_recursive_batch(igt_spin_t *spin, int fd, uint32_t ctx, unsigned engine,
+uint32_t dep, unsigned int flags)
 {
 #define SCRATCH 0
 #define BATCH 1
const int gen = intel_gen(intel_get_drm_devid(fd));
-   struct drm_i915_gem_exec_object2 obj[2];
-   struct drm_i915_gem_relocation_entry relocs[2];
-   struct drm_i915_gem_execbuffer2 execbuf;
+   struct drm_i915_gem_relocation_entry relocs[2], *r;
+   struct drm_i915_gem_execbuffer2 *execbuf;
+   struct drm_i915_gem_exec_object2 *obj;
unsigned int engines[16];
unsigned int nengine;
int fence_fd = -1;
-   uint32_t *batch;
+   uint32_t *batch, *batch_start;
int i;
 
nengine = 0;
if (engine == -1) {
-   for_each_engine(fd, engine)
-   if (engine)
+   for_each_engine(fd, engine) {
+   if (engine) {
+   if (flags & POLL_RUN)
+   igt_require(!(flags & POLL_RUN) ||
+   gem_can_store_dword(fd, engine));
+
engines[nengine++] = engine;
+   }
+   }
} else {
gem_require_ring(fd, engine);
+   igt_require(!(flags & POLL_RUN) ||
+   gem_can_store_dword(fd, engine));
engines[nengine++] = engine;
}
igt_require(nengine);
 
-   memset(, 0, sizeof(execbuf));
-   memset(obj, 0, sizeof(obj));
+   memset(>execbuf, 0, sizeof(spin->execbuf));
+   execbuf = >execbuf;
+   memset(spin->obj, 0, sizeof(spin->obj));
+   obj = spin->obj;
memset(relocs, 0, sizeof(relocs));
 
obj[BATCH].handle = gem_create(fd, BATCH_SIZE);
@@ -113,19 +126,66 @@ static int emit_recursive_batch(igt_spin_t *spin,
BATCH_SIZE, PROT_WRITE);
gem_set_domain(fd, obj[BATCH].handle,
I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
-   execbuf.buffer_count++;
+   execbuf->buffer_count++;
+   batch_start = batch;
 
if (dep) {
+   igt_assert(!(flags & POLL_RUN));
+
/* dummy write to dependency */
obj[SCRATCH].handle = dep;
fill_reloc([obj[BATCH].relocation_count++],
   dep, 1020,
   I915_GEM_DOMAIN_RENDER,
   I915_GEM_DOMAIN_RENDER);
- 

[Intel-gfx] [PATCH libdrm 1/1] intel: allocate the requested size when reuse is disabled

[James Xiong]

From: "Xiong, James" 

1) fixed a bug: a bucket size instead of the requested
was allocated even when reuse is disabled. 2) set bo_reuse
explicitly

Signed-off-by: Xiong, James 
---
 intel/intel_bufmgr_gem.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 386da30..6fdb1ca 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -402,6 +402,9 @@ drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem 
*bufmgr_gem,
 {
int i;
 
+   if (!bufmgr_gem->bo_reuse)
+   return NULL;
+
for (i = 0; i < bufmgr_gem->num_buckets; i++) {
struct drm_intel_gem_bo_bucket *bucket =
_gem->cache_bucket[i];
@@ -1382,7 +1385,7 @@ drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, 
time_t time)
 
bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
/* Put the buffer into our internal cache for reuse if we can. */
-   if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL &&
+   if (bo_gem->reusable && bucket != NULL &&
drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem,
  I915_MADV_DONTNEED)) {
bo_gem->free_time = time;
@@ -3806,6 +3809,7 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
drm_intel_gem_get_pipe_from_crtc_id;
bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references;
 
+   bufmgr_gem->bo_reuse = false;
init_cache_buckets(bufmgr_gem);
 
DRMINITLISTHEAD(_gem->vma_cache);
-- 
2.7.4

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH] drm/i915: Promote .format_mod_supported() to the lead role

[Ville Syrjala]

From: Ville Syrjälä 

Up to now we've used the plane's modifier list as the primary
source of information for which modifiers are supported by a
given plane. In order to allow auxiliary metadata to be embedded
within the bits of the modifier we need to stop doing that.

Thus we have to make .format_mod_supported() aware of the plane's
capabilities and gracefully deal with any modifier being passed
in directly from userspace.

Cc: Eric Anholt 
References: 
https://lists.freedesktop.org/archives/dri-devel/2018-March/169782.html
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_display.c | 147 +++---
 drivers/gpu/drm/i915/intel_drv.h |   1 +
 drivers/gpu/drm/i915/intel_sprite.c  | 194 ++-
 3 files changed, 210 insertions(+), 132 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 3e7ab75e1b41..d717004be0b8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -88,15 +88,7 @@ static const uint32_t skl_primary_formats[] = {
DRM_FORMAT_VYUY,
 };
 
-static const uint64_t skl_format_modifiers_noccs[] = {
-   I915_FORMAT_MOD_Yf_TILED,
-   I915_FORMAT_MOD_Y_TILED,
-   I915_FORMAT_MOD_X_TILED,
-   DRM_FORMAT_MOD_LINEAR,
-   DRM_FORMAT_MOD_INVALID
-};
-
-static const uint64_t skl_format_modifiers_ccs[] = {
+static const uint64_t skl_format_modifiers[] = {
I915_FORMAT_MOD_Yf_TILED_CCS,
I915_FORMAT_MOD_Y_TILED_CCS,
I915_FORMAT_MOD_Yf_TILED,
@@ -12997,8 +12989,17 @@ void intel_plane_destroy(struct drm_plane *plane)
kfree(to_intel_plane(plane));
 }
 
-static bool i8xx_mod_supported(uint32_t format, uint64_t modifier)
+static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
+   u32 format, u64 modifier)
 {
+   switch (modifier) {
+   case DRM_FORMAT_MOD_LINEAR:
+   case I915_FORMAT_MOD_X_TILED:
+   break;
+   default:
+   return false;
+   }
+
switch (format) {
case DRM_FORMAT_C8:
case DRM_FORMAT_RGB565:
@@ -13011,8 +13012,17 @@ static bool i8xx_mod_supported(uint32_t format, 
uint64_t modifier)
}
 }
 
-static bool i965_mod_supported(uint32_t format, uint64_t modifier)
+static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
+   u32 format, u64 modifier)
 {
+   switch (modifier) {
+   case DRM_FORMAT_MOD_LINEAR:
+   case I915_FORMAT_MOD_X_TILED:
+   break;
+   default:
+   return false;
+   }
+
switch (format) {
case DRM_FORMAT_C8:
case DRM_FORMAT_RGB565:
@@ -13027,17 +13037,37 @@ static bool i965_mod_supported(uint32_t format, 
uint64_t modifier)
}
 }
 
-static bool skl_mod_supported(uint32_t format, uint64_t modifier)
+static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
+  u32 format, u64 modifier)
 {
+   struct intel_plane *plane = to_intel_plane(_plane);
+
+   switch (modifier) {
+   case DRM_FORMAT_MOD_LINEAR:
+   case I915_FORMAT_MOD_X_TILED:
+   case I915_FORMAT_MOD_Y_TILED:
+   case I915_FORMAT_MOD_Yf_TILED:
+   break;
+   case I915_FORMAT_MOD_Y_TILED_CCS:
+   case I915_FORMAT_MOD_Yf_TILED_CCS:
+   if (!plane->has_ccs)
+   return false;
+   break;
+   default:
+   return false;
+   }
+
switch (format) {
case DRM_FORMAT_XRGB:
case DRM_FORMAT_XBGR:
case DRM_FORMAT_ARGB:
case DRM_FORMAT_ABGR:
-   if (modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
-   modifier == I915_FORMAT_MOD_Y_TILED_CCS)
-   return true;
-   /* fall through */
+   return modifier == DRM_FORMAT_MOD_LINEAR ||
+   modifier == I915_FORMAT_MOD_X_TILED ||
+   modifier == I915_FORMAT_MOD_Y_TILED ||
+   modifier == I915_FORMAT_MOD_Yf_TILED ||
+   modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
+   modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
case DRM_FORMAT_RGB565:
case DRM_FORMAT_XRGB2101010:
case DRM_FORMAT_XBGR2101010:
@@ -13045,52 +13075,49 @@ static bool skl_mod_supported(uint32_t format, 
uint64_t modifier)
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
-   if (modifier == I915_FORMAT_MOD_Yf_TILED)
-   return true;
-   /* fall through */
+   return modifier == DRM_FORMAT_MOD_LINEAR ||
+   modifier == I915_FORMAT_MOD_X_TILED ||
+   modifier == 

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Add Exec param to control data port coherency.

[Patchwork]

== Series Details ==

Series: drm/i915: Add Exec param to control data port coherency.
URL   : https://patchwork.freedesktop.org/series/40181/
State : failure

== Summary ==

 Possible new issues:

Test gem_exec_params:
Subgroup invalid-flag:
pass   -> FAIL   (shard-apl)

 Known issues:

Test kms_flip:
Subgroup plain-flip-ts-check-interruptible:
pass   -> FAIL   (shard-hsw) fdo#100368 +1
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-primscrn-shrfb-msflip-blt:
fail   -> PASS   (shard-apl) fdo#104727
Test kms_sysfs_edid_timing:
warn   -> PASS   (shard-apl) fdo#100047

fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#104727 https://bugs.freedesktop.org/show_bug.cgi?id=104727
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047

shard-apltotal:3442 pass:1814 dwarn:1   dfail:0   fail:8   skip:1619 
time:13042s
shard-hswtotal:3442 pass:1767 dwarn:1   dfail:0   fail:2   skip:1671 
time:11899s
shard-snbtotal:3442 pass:1358 dwarn:1   dfail:0   fail:2   skip:2081 
time:7170s
Blacklisted hosts:
shard-kbltotal:3442 pass:1937 dwarn:1   dfail:0   fail:10  skip:1494 
time:9945s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8391/shards.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Add control flags to i915_handle_error()

[Michel Thierry]

On 16/03/18 14:50, Chris Wilson wrote:

Not all callers want the GPU error to handled in the same way, so expose
a control parameter. In the first instance, some callers do not want the
heavyweight error capture so add a bit to request the state to be
captured and saved.

Signed-off-by: Chris Wilson 
Cc: Jeff McGee 
Cc: Mika Kuoppala 
---
  drivers/gpu/drm/i915/i915_debugfs.c  |  4 ++--
  drivers/gpu/drm/i915/i915_drv.h  |  4 +++-
  drivers/gpu/drm/i915/i915_irq.c  | 22 ++
  drivers/gpu/drm/i915/intel_hangcheck.c   |  6 +++---
  drivers/gpu/drm/i915/selftests/intel_hangcheck.c |  2 +-
  5 files changed, 23 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 5378863e3238..03b74a92caed 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3952,8 +3952,8 @@ i915_wedged_set(void *data, u64 val)
engine->hangcheck.stalled = true;
}
  
-	i915_handle_error(i915, val, "Manually set wedged engine mask = %llx",

- val);
+   i915_handle_error(i915, val, I915_ERROR_CAPTURE,
+ "Manually set wedged engine mask = %llx", val);
  
  	wait_on_bit(>gpu_error.flags,

I915_RESET_HANDOFF,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e27ba8fb64e6..53009ba50640 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2751,10 +2751,12 @@ static inline void i915_queue_hangcheck(struct 
drm_i915_private *dev_priv)
   _priv->gpu_error.hangcheck_work, delay);
  }
  
-__printf(3, 4)

+__printf(4, 5)
  void i915_handle_error(struct drm_i915_private *dev_priv,
   u32 engine_mask,
+  unsigned long flags,
   const char *fmt, ...);
+#define I915_ERROR_CAPTURE BIT(0)
  

Should this be in the new i915_gpu_error.h?


  extern void intel_irq_init(struct drm_i915_private *dev_priv);
  extern void intel_irq_fini(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 44eef355e12c..b3a4dc7cb26c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2955,6 +2955,7 @@ static void i915_clear_error_registers(struct 
drm_i915_private *dev_priv)
   * i915_handle_error - handle a gpu error
   * @dev_priv: i915 device private
   * @engine_mask: mask representing engines that are hung
+ * @flags: control flags
   * @fmt: Error message format string
   *
   * Do some basic checking of register state at error time and
@@ -2965,16 +2966,11 @@ static void i915_clear_error_registers(struct 
drm_i915_private *dev_priv)
   */
  void i915_handle_error(struct drm_i915_private *dev_priv,
   u32 engine_mask,
+  unsigned long flags,
   const char *fmt, ...)
  {
struct intel_engine_cs *engine;
unsigned int tmp;
-   va_list args;
-   char error_msg[80];
-
-   va_start(args, fmt);
-   vscnprintf(error_msg, sizeof(error_msg), fmt, args);
-   va_end(args);
  
  	/*

 * In most cases it's guaranteed that we get here with an RPM
@@ -2986,8 +2982,18 @@ void i915_handle_error(struct drm_i915_private *dev_priv,
intel_runtime_pm_get(dev_priv);
  
  	engine_mask &= INTEL_INFO(dev_priv)->ring_mask;

-   i915_capture_error_state(dev_priv, engine_mask, error_msg);
-   i915_clear_error_registers(dev_priv);
+
+   if (flags & I915_ERROR_CAPTURE) {
+   char error_msg[80];
+   va_list args;
+
+   va_start(args, fmt);
+   vscnprintf(error_msg, sizeof(error_msg), fmt, args);
+   va_end(args);
+
+   i915_capture_error_state(dev_priv, engine_mask, error_msg);
+   i915_clear_error_registers(dev_priv);
+   }

else
DRM_INFO or DRM_NOTE the error_msg  ?

Otherwise the 'kicking wait/semaphore' text from below will never be 
printed.


  
  	/*

 * Try engine reset when available. We fall back to full reset if
diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c 
b/drivers/gpu/drm/i915/intel_hangcheck.c
index 42e45ae87393..13d1a269c771 100644
--- a/drivers/gpu/drm/i915/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/intel_hangcheck.c
@@ -246,7 +246,7 @@ engine_stuck(struct intel_engine_cs *engine, u64 acthd)
 */
tmp = I915_READ_CTL(engine);
if (tmp & RING_WAIT) {
-   i915_handle_error(dev_priv, 0,
+   i915_handle_error(dev_priv, 0, 0,
  "Kicking stuck wait on %s",
  engine->name);
I915_WRITE_CTL(engine, tmp);
@@ -258,7 +258,7 @@ 

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Some plane init cleanups (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Some plane init cleanups (rev2)
URL   : https://patchwork.freedesktop.org/series/39390/
State : failure

== Summary ==

Series 39390v2 drm/i915: Some plane init cleanups
https://patchwork.freedesktop.org/api/1.0/series/39390/revisions/2/mbox/

 Possible new issues:

Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-b-frame-sequence:
pass   -> FAIL   (fi-cfl-s2)

 Known issues:

Test kms_flip:
Subgroup basic-flip-vs-wf_vblank:
pass   -> FAIL   (fi-snb-2520m) fdo#100368

fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:434s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:439s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:378s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:533s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:299s
fi-bxt-dsi   total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  
time:511s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:517s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:517s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:502s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:411s
fi-cfl-s2total:285  pass:258  dwarn:0   dfail:0   fail:1   skip:26  
time:587s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:508s
fi-cnl-drrs  total:285  pass:254  dwarn:3   dfail:0   fail:0   skip:28  
time:548s
fi-elk-e7500 total:285  pass:225  dwarn:1   dfail:0   fail:0   skip:59  
time:425s
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:315s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:545s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:402s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:421s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:473s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:428s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:474s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:471s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:514s
fi-pnv-d510  total:285  pass:219  dwarn:1   dfail:0   fail:0   skip:65  
time:657s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:449s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:529s
fi-skl-6700hqtotal:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:542s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:503s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:502s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:427s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:447s
fi-snb-2520m total:285  pass:244  dwarn:0   dfail:0   fail:1   skip:40  
time:562s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:401s

9b79492f331e36cf2e08d65ab3221abb66f67844 drm-tip: 2018y-03m-19d-14h-18m-12s UTC 
integration manifest
9ea507414110 drm/i915: s/intel_plane/plane/ in sprite init
fe5713d56f26 drm/i915: Extract skl_universal_plane_init()
42ad56c05f29 drm/i915: Introduce intel_plane_alloc()
0a66981c7fe7 drm/i915: Move plane_state->scaler_id initialization into 
intel_create_plane_state()
610c08a0e466 drm/i915: Add missing pixel formats for skl+ "sprites"
8e40f86d8366 drm/i915: Disallow plane scaling with specific pixel formats
62cb16f1b486 drm/i915: Allow horizontal mirroring for cnl+ "sprite" planes
ef6ecafcd04e drm/i915: Don't populate plane->i9xx_plane for sprites
c49d4399e89a drm/i915: Populate possible_crtcs for primary/cursor planes
0893344e27de drm/i915: Fix tabs vs. spaces
910b99bff03f drm/i915: Constify intel_plane_funcs

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8395/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH igt 0/8] Non-Intel test suite fixes

[Ulrich Hecht]

On Fri, Mar 16, 2018 at 9:55 AM, Daniel Vetter  wrote:
> On Thu, Mar 15, 2018 at 03:45:36PM +0100, Ulrich Hecht wrote:
>> Hi!
>>
>> I have run the tests on a Renesas R-Car M3-W's DU device, and have found a
>> number of false negatives that mostly stem from use of Intel-specifics
>> without checking if that makes sense first. So here's a bunch of fixes for
>> those, hope they are generic enough for upstreaming.
>
> Nice, other people using this! Do you plan to maintain this actively going
> forward, or is this more a one-off effort?

For now, this is just an attempt at evaluating if this works for us.
It has caught a few things that look like legitimate bugs to me,
though...

CU
Uli
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Trim error mask to known engines

[Michel Thierry]

On 19/03/18 06:12, Chris Wilson wrote:

Quoting Chris Wilson (2018-03-16 21:49:59)

For the convenience of userspace passing in an arbitrary reset mask,
remove unknown engines from the set of engines that are to be reset.
This means that we always follow a per-engine reset with a full-device
reset when userspace writes -1 into debugfs/i915_wedged.


I thought that was the desired behaviour...



Reported-by: Michał Winiarski 
Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Michał Winiarski 


Please? It papers over the issue in gem_exec_capture...
-Chris



Reviewed-by: Michel Thierry 


---
  drivers/gpu/drm/i915/i915_irq.c | 1 +
  1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 828f3104488c..44eef355e12c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2985,6 +2985,7 @@ void i915_handle_error(struct drm_i915_private *dev_priv,
  */
 intel_runtime_pm_get(dev_priv);
  
+   engine_mask &= INTEL_INFO(dev_priv)->ring_mask;

 i915_capture_error_state(dev_priv, engine_mask, error_msg);
 i915_clear_error_registers(dev_priv);
  
--

2.16.2


___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx


___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/3] drm/i915/guc: Unify naming of private GuC action functions

[Patchwork]

== Series Details ==

Series: series starting with [v2,1/3] drm/i915/guc: Unify naming of private GuC 
action functions
URL   : https://patchwork.freedesktop.org/series/40190/
State : success

== Summary ==

Series 40190v1 series starting with [v2,1/3] drm/i915/guc: Unify naming of 
private GuC action functions
https://patchwork.freedesktop.org/api/1.0/series/40190/revisions/1/mbox/

 Known issues:

Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail   -> PASS   (fi-gdg-551) fdo#102575
Test kms_flip:
Subgroup basic-flip-vs-wf_vblank:
pass   -> FAIL   (fi-cfl-s2) fdo#100368
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> INCOMPLETE (fi-snb-2520m) fdo#103713

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:429s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:445s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:385s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:534s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:297s
fi-bxt-dsi   total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  
time:514s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:512s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:517s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:504s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:410s
fi-cfl-s2total:285  pass:258  dwarn:0   dfail:0   fail:1   skip:26  
time:573s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:510s
fi-cnl-drrs  total:285  pass:254  dwarn:3   dfail:0   fail:0   skip:28  
time:526s
fi-elk-e7500 total:285  pass:225  dwarn:1   dfail:0   fail:0   skip:59  
time:426s
fi-gdg-551   total:285  pass:177  dwarn:0   dfail:0   fail:0   skip:108 
time:317s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:536s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:406s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:427s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:473s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:428s
fi-kbl-7500u total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  
time:481s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:465s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:514s
fi-pnv-d510  total:285  pass:219  dwarn:1   dfail:0   fail:0   skip:65  
time:654s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:446s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:531s
fi-skl-6700hqtotal:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:540s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:508s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:498s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:430s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:445s
fi-snb-2520m total:242  pass:208  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:399s

9b79492f331e36cf2e08d65ab3221abb66f67844 drm-tip: 2018y-03m-19d-14h-18m-12s UTC 
integration manifest
2d92dd0eb2bc drm/i915/guc: Move enable/disable msg functions to GuC header
811b8a5cc50f drm/i915/guc: Drop union guc_log_control
47e7b038230a drm/i915/guc: Unify naming of private GuC action functions

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8394/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v3 2/3] drm/i915/guc: Drop union guc_log_control

[Michal Wajdeczko]

Usually we use shift/mask macros for bit field definitions.
Union guc_log_control was not following that pattern.

Additional bonus:

add/remove: 0/0 grow/shrink: 0/1 up/down: 0/-25 (-25)
Function old new   delta
intel_guc_log_level_set  388 363 -25

v2: prevent out-of-range verbosity (MichalWi)

Signed-off-by: Michal Wajdeczko 
Cc: Michal Winiarski 
Cc: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/intel_guc_fwif.h | 16 +---
 drivers/gpu/drm/i915/intel_guc_log.c  | 13 +
 2 files changed, 10 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h 
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 4971685..72941bd 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -534,17 +534,6 @@ struct guc_log_buffer_state {
u32 version;
 } __packed;
 
-union guc_log_control {
-   struct {
-   u32 logging_enabled:1;
-   u32 reserved1:3;
-   u32 verbosity:4;
-   u32 default_logging:1;
-   u32 reserved2:23;
-   };
-   u32 value;
-} __packed;
-
 struct guc_ctx_report {
u32 report_return_status;
u32 reserved1[64];
@@ -603,6 +592,11 @@ enum intel_guc_report_status {
INTEL_GUC_REPORT_STATUS_COMPLETE = 0x4,
 };
 
+#define GUC_LOG_CONTROL_LOGGING_ENABLED(1 << 0)
+#define GUC_LOG_CONTROL_VERBOSITY_SHIFT4
+#define GUC_LOG_CONTROL_VERBOSITY_MASK (0xF << GUC_LOG_CONTROL_VERBOSITY_SHIFT)
+#define GUC_LOG_CONTROL_DEFAULT_LOGGING(1 << 8)
+
 /*
  * The GuC sends its response to a command by overwriting the
  * command in SS0. The response is distinguishable from a command
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c
index 39928e6..5262bba 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -60,18 +60,15 @@ static int guc_action_flush_log(struct intel_guc *guc)
 static int guc_action_control_log(struct intel_guc *guc, bool enable,
  bool default_logging, u32 verbosity)
 {
-   union guc_log_control control_val = {
-   {
-   .logging_enabled = enable,
-   .verbosity = verbosity,
-   .default_logging = default_logging,
-   },
-   };
u32 action[] = {
INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING,
-   control_val.value
+   (enable ? GUC_LOG_CONTROL_LOGGING_ENABLED : 0) |
+   (verbosity << GUC_LOG_CONTROL_VERBOSITY_SHIFT) |
+   (default_logging ? GUC_LOG_CONTROL_DEFAULT_LOGGING : 0)
};
 
+   GEM_BUG_ON(verbosity > GUC_LOG_VERBOSITY_MAX);
+
return intel_guc_send(guc, action, ARRAY_SIZE(action));
 }
 
-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v3 3/3] drm/i915/guc: Move enable/disable msg functions to GuC header

[Michal Wajdeczko]

While today we are modifying GuC enabled msg mask only in GuC
log, this code should be defined as generic GuC to allow future
code reuse.

Signed-off-by: Michal Wajdeczko 
Cc: Michal Winiarski 
Cc: Sagar Arun Kamble 
Cc: Chris Wilson 
Reviewed-by: Michał Winiarski 
---
 drivers/gpu/drm/i915/intel_guc.h | 14 ++
 drivers/gpu/drm/i915/intel_guc_log.c | 26 --
 2 files changed, 26 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 9a95d15..13f3d1d 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -155,4 +155,18 @@ static inline int intel_guc_sanitize(struct intel_guc *guc)
return 0;
 }
 
+static inline void intel_guc_enable_msg(struct intel_guc *guc, u32 mask)
+{
+   spin_lock_irq(>irq_lock);
+   guc->msg_enabled_mask |= mask;
+   spin_unlock_irq(>irq_lock);
+}
+
+static inline void intel_guc_disable_msg(struct intel_guc *guc, u32 mask)
+{
+   spin_lock_irq(>irq_lock);
+   guc->msg_enabled_mask &= ~mask;
+   spin_unlock_irq(>irq_lock);
+}
+
 #endif
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c
index 5262bba..f5450bc 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -72,25 +72,23 @@ static int guc_action_control_log(struct intel_guc *guc, 
bool enable,
return intel_guc_send(guc, action, ARRAY_SIZE(action));
 }
 
-static void guc_flush_log_msg_enable(struct intel_guc *guc)
+static inline struct intel_guc *log_to_guc(struct intel_guc_log *log)
 {
-   spin_lock_irq(>irq_lock);
-   guc->msg_enabled_mask |= INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER |
-INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED;
-   spin_unlock_irq(>irq_lock);
+   return container_of(log, struct intel_guc, log);
 }
 
-static void guc_flush_log_msg_disable(struct intel_guc *guc)
+static void guc_log_enable_flush_events(struct intel_guc_log *log)
 {
-   spin_lock_irq(>irq_lock);
-   guc->msg_enabled_mask &= ~(INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER |
-  INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED);
-   spin_unlock_irq(>irq_lock);
+   intel_guc_enable_msg(log_to_guc(log),
+INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER |
+INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED);
 }
 
-static inline struct intel_guc *log_to_guc(struct intel_guc_log *log)
+static void guc_log_disable_flush_events(struct intel_guc_log *log)
 {
-   return container_of(log, struct intel_guc, log);
+   intel_guc_disable_msg(log_to_guc(log),
+ INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER |
+ INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED);
 }
 
 /*
@@ -577,7 +575,7 @@ int intel_guc_log_relay_open(struct intel_guc_log *log)
 
mutex_unlock(>relay.lock);
 
-   guc_flush_log_msg_enable(log_to_guc(log));
+   guc_log_enable_flush_events(log);
 
/*
 * When GuC is logging without us relaying to userspace, we're ignoring
@@ -617,7 +615,7 @@ void intel_guc_log_relay_flush(struct intel_guc_log *log)
 
 void intel_guc_log_relay_close(struct intel_guc_log *log)
 {
-   guc_flush_log_msg_disable(log_to_guc(log));
+   guc_log_disable_flush_events(log);
flush_work(>relay.flush_work);
 
mutex_lock(>relay.lock);
-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v3 1/3] drm/i915/guc: Unify naming of private GuC action functions

[Michal Wajdeczko]

We should avoid using guc_log prefix for functions that don't
operate on GuC log, but rather request action from the GuC.
Better to use guc_action prefix.

v2: rebase + naming compromise

Signed-off-by: Michal Wajdeczko 
Cc: Michal Winiarski 
Cc: Sagar Arun Kamble 
Reviewed-by: Michał Winiarski 
---
 drivers/gpu/drm/i915/intel_guc_log.c | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c
index 4cb422c..39928e6 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -38,7 +38,7 @@
  * registers value.
  */
 
-static int guc_log_flush_complete(struct intel_guc *guc)
+static int guc_action_flush_log_complete(struct intel_guc *guc)
 {
u32 action[] = {
INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE
@@ -47,7 +47,7 @@ static int guc_log_flush_complete(struct intel_guc *guc)
return intel_guc_send(guc, action, ARRAY_SIZE(action));
 }
 
-static int guc_log_flush(struct intel_guc *guc)
+static int guc_action_flush_log(struct intel_guc *guc)
 {
u32 action[] = {
INTEL_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH,
@@ -57,8 +57,8 @@ static int guc_log_flush(struct intel_guc *guc)
return intel_guc_send(guc, action, ARRAY_SIZE(action));
 }
 
-static int guc_log_control(struct intel_guc *guc, bool enable,
-  bool default_logging, u32 verbosity)
+static int guc_action_control_log(struct intel_guc *guc, bool enable,
+ bool default_logging, u32 verbosity)
 {
union guc_log_control control_val = {
{
@@ -449,7 +449,7 @@ static void guc_log_capture_logs(struct intel_guc_log *log)
 * time, so get/put should be really quick.
 */
intel_runtime_pm_get(dev_priv);
-   guc_log_flush_complete(guc);
+   guc_action_flush_log_complete(guc);
intel_runtime_pm_put(dev_priv);
 }
 
@@ -527,9 +527,9 @@ int intel_guc_log_level_set(struct intel_guc_log *log, u64 
val)
}
 
intel_runtime_pm_get(dev_priv);
-   ret = guc_log_control(guc, GUC_LOG_LEVEL_TO_VERBOSE(val),
- GUC_LOG_LEVEL_TO_ENABLED(val),
- GUC_LOG_LEVEL_TO_VERBOSITY(val));
+   ret = guc_action_control_log(guc, GUC_LOG_LEVEL_TO_VERBOSE(val),
+GUC_LOG_LEVEL_TO_ENABLED(val),
+GUC_LOG_LEVEL_TO_VERBOSITY(val));
intel_runtime_pm_put(dev_priv);
if (ret) {
DRM_DEBUG_DRIVER("guc_log_control action failed %d\n", ret);
@@ -611,7 +611,7 @@ void intel_guc_log_relay_flush(struct intel_guc_log *log)
flush_work(>relay.flush_work);
 
intel_runtime_pm_get(i915);
-   guc_log_flush(guc);
+   guc_action_flush_log(guc);
intel_runtime_pm_put(i915);
 
/* GuC would have updated log buffer by now, so capture it */
-- 
1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915: Split GPU commands definitions into separate header

[Jani Nikula]

On Tue, 13 Mar 2018, Chris Wilson  wrote:
> Quoting Michal Wajdeczko (2018-03-13 11:21:21)
>> We should not mix MMIO with MI_INSTR definitions.
>> 
>> Suggested-by: Chris Wilson 
>> Signed-off-by: Michal Wajdeczko 
>> Cc: Chris Wilson 
>> ---
>
>> +#define   MI_STORE_DWORD_INDEX_SHIFT 2
>> +/* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
>
> Sanitize "/*\n" while we are here ?

How about adding spaces around operators and replacing (1 << N) with
BIT(N) while at it? Or in an immediate follow-up patch. If you're going
to cause conflicts, you could fix this stuff at minimum extra
disturbance.

BR,
Jani.

>
>> + * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
>> + *   simply ignores the register load under certain conditions.
>> + * - One can actually load arbitrary many arbitrary registers: Simply issue 
>> x
>> + *   address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
>> + */
>> +#define MI_LOAD_REGISTER_IMM(x)MI_INSTR(0x22, 2*(x)-1)
>> +#define   MI_LRI_FORCE_POSTED  (1<<12)
>> +#define MI_STORE_REGISTER_MEMMI_INSTR(0x24, 1)
>> +#define MI_STORE_REGISTER_MEM_GEN8   MI_INSTR(0x24, 2)
>> +#define   MI_SRM_LRM_GLOBAL_GTT(1<<22)
>> +#define MI_FLUSH_DWMI_INSTR(0x26, 1) /* for GEN6 */
>> +#define   MI_FLUSH_DW_STORE_INDEX  (1<<21)
>> +#define   MI_INVALIDATE_TLB(1<<18)
>> +#define   MI_FLUSH_DW_OP_STOREDW   (1<<14)
>> +#define   MI_FLUSH_DW_OP_MASK  (3<<14)
>> +#define   MI_FLUSH_DW_NOTIFY   (1<<8)
>> +#define   MI_INVALIDATE_BSD(1<<7)
>> +#define   MI_FLUSH_DW_USE_GTT  (1<<2)
>> +#define   MI_FLUSH_DW_USE_PPGTT(0<<2)
>> +#define MI_LOAD_REGISTER_MEM  MI_INSTR(0x29, 1)
>> +#define MI_LOAD_REGISTER_MEM_GEN8  MI_INSTR(0x29, 2)
>> +#define MI_BATCH_BUFFERMI_INSTR(0x30, 1)
>> +#define   MI_BATCH_NON_SECURE  (1)
>> +/* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. 
>> */
>> +#define   MI_BATCH_NON_SECURE_I965 (1<<8)
>> +#define   MI_BATCH_PPGTT_HSW   (1<<8)
>> +#define   MI_BATCH_NON_SECURE_HSW  (1<<13)
>> +#define MI_BATCH_BUFFER_START  MI_INSTR(0x31, 0)
>> +#define   MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
>> +#define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
>> +#define   MI_BATCH_RESOURCE_STREAMER (1<<10)
>
>> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h 
>> b/drivers/gpu/drm/i915/intel_ringbuffer.h
>> index 81cdbbf..8f2c71a 100644
>> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
>> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
>> @@ -7,7 +7,8 @@
>>  #include "i915_gem_batch_pool.h"
>>  #include "i915_gem_timeline.h"
>>  
>> -#include "i915_reg.h" /* FIXME split out i915_gpu_commands.h */
>> +#include "intel_gpu_commands.h"
>
> Alphabetical?
>
> Reviewed-by: Chris Wilson 
> -Chris
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [RFC v1] Data port coherency control for UMDs.

[Lis, Tomasz]

On 2018-03-19 14:53, Joonas Lahtinen wrote:

+ Dave, as FYI

Quoting Tomasz Lis (2018-03-19 14:37:34)

The OpenCL driver develpers requested a functionality to control cache
coherency at data port level. Keeping the coherency at that level is disabled
by default due to its performance costs. OpenCL driver is planning to
enable it for a small subset of submissions, when such functionality is
required.

Can you please link to the corresponding OpenCL driver changes? I'm
assuming this relates to the new-driver-to-be-adopted, instead of
Beignet?

It is for the new driver; I will ask the OCL developers to provide a link.


How is the story/schedule looking for adopting the new driver to
distros?

I guess that's another question for OCL guys, I don't know.

Seeing the userspace counterpart and tests will help in assessing the
suggested changes.

Regards, Joonas
I prepared an IGT test for that, I will send it to a proper mailing list 
soon.

-Tomasz

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gvt: fix spelling mistake: "registeration" -> "registration"

[Patchwork]

== Series Details ==

Series: drm/i915/gvt: fix spelling mistake: "registeration" -> "registration"
URL   : https://patchwork.freedesktop.org/series/40185/
State : success

== Summary ==

Series 40185v1 drm/i915/gvt: fix spelling mistake: "registeration" -> 
"registration"
https://patchwork.freedesktop.org/api/1.0/series/40185/revisions/1/mbox/

 Known issues:

Test kms_chamelium:
Subgroup dp-crc-fast:
pass   -> DMESG-FAIL (fi-kbl-7500u) fdo#103841

fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841

fi-bdw-5557u total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  
time:433s
fi-bdw-gvtdvmtotal:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:441s
fi-blb-e6850 total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  
time:392s
fi-bsw-n3050 total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  
time:545s
fi-bwr-2160  total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 
time:299s
fi-bxt-dsi   total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  
time:514s
fi-bxt-j4205 total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:511s
fi-byt-j1900 total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  
time:521s
fi-byt-n2820 total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  
time:503s
fi-cfl-8700k total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:411s
fi-cfl-s2total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:582s
fi-cfl-u total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:508s
fi-cnl-drrs  total:285  pass:254  dwarn:3   dfail:0   fail:0   skip:28  
time:516s
fi-elk-e7500 total:285  pass:225  dwarn:1   dfail:0   fail:0   skip:59  
time:430s
fi-gdg-551   total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 
time:318s
fi-glk-1 total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:535s
fi-hsw-4770  total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:408s
fi-ilk-650   total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  
time:419s
fi-ivb-3520m total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  
time:472s
fi-ivb-3770  total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  
time:430s
fi-kbl-7500u total:285  pass:259  dwarn:1   dfail:1   fail:0   skip:24  
time:474s
fi-kbl-7567u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:467s
fi-kbl-r total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:518s
fi-pnv-d510  total:285  pass:219  dwarn:1   dfail:0   fail:0   skip:65  
time:652s
fi-skl-6260u total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:447s
fi-skl-6600u total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  
time:532s
fi-skl-6700hqtotal:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  
time:540s
fi-skl-6700k2total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  
time:505s
fi-skl-6770hqtotal:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  
time:499s
fi-skl-guc   total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  
time:430s
fi-skl-gvtdvmtotal:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  
time:447s
fi-snb-2520m total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:594s
fi-snb-2600  total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  
time:408s

9b79492f331e36cf2e08d65ab3221abb66f67844 drm-tip: 2018y-03m-19d-14h-18m-12s UTC 
integration manifest
cf5c89c5a32a drm/i915/gvt: fix spelling mistake: "registeration" -> 
"registration"

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8393/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH v2 2/3] drm/i915/guc: Drop union guc_log_control

[Michal Wajdeczko]

On Mon, 19 Mar 2018 16:32:05 +0100, Michał Winiarski  
 wrote:



On Mon, Mar 19, 2018 at 01:49:23PM +, Michal Wajdeczko wrote:

Usually we use shift/mask macros for bit field definitions.
Union guc_log_control was not following that pattern.

Additional bonus:

add/remove: 0/0 grow/shrink: 0/1 up/down: 0/-25 (-25)
Function old new   delta
intel_guc_log_level_set  388 363 -25

Signed-off-by: Michal Wajdeczko 
Cc: Michal Winiarski 
Cc: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/intel_guc_fwif.h | 16 +---
 drivers/gpu/drm/i915/intel_guc_log.c  | 11 +++
 2 files changed, 8 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h  
b/drivers/gpu/drm/i915/intel_guc_fwif.h

index 4971685..72941bd 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -534,17 +534,6 @@ struct guc_log_buffer_state {
u32 version;
 } __packed;

-union guc_log_control {
-   struct {
-   u32 logging_enabled:1;
-   u32 reserved1:3;
-   u32 verbosity:4;
-   u32 default_logging:1;
-   u32 reserved2:23;
-   };
-   u32 value;
-} __packed;
-
 struct guc_ctx_report {
u32 report_return_status;
u32 reserved1[64];
@@ -603,6 +592,11 @@ enum intel_guc_report_status {
INTEL_GUC_REPORT_STATUS_COMPLETE = 0x4,
 };

+#define GUC_LOG_CONTROL_LOGGING_ENABLED(1 << 0)
+#define GUC_LOG_CONTROL_VERBOSITY_SHIFT4
+#define GUC_LOG_CONTROL_VERBOSITY_MASK	(0xF <<  
GUC_LOG_CONTROL_VERBOSITY_SHIFT)


You're not using the mask anywhere. Is it just to describe the iface?


yep, only bit-field interface


Or was it supposed to be used in guc_action_control_log?
(there's a slight change in behavior here, which may lead to confusion  
when

passing out-of-range verbosity)


As you already check for out-of-range verbosity level passed by user:

if (val < GUC_LOG_LEVEL_DISABLED ||
val > GUC_VERBOSITY_TO_LOG_LEVEL(GUC_LOG_VERBOSITY_MAX))
return -EINVAL;

I can make my check in guc_action() more assertive:

GEM_BUG_ON(verbosity > GUC_LOG_VERBOSITY_MAX)

Thanks,
/m
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH] drm: Restore planes after load detection

[Ville Syrjala]

From: Ville Syrjälä 

Actually turn the planes back on after were done with
the load detection.

Fixes: 20bdc112bbe4 ("drm/i915: Disable all planes for load detection, v2.")
Cc: Maarten Lankhorst 
Cc: Daniel Vetter 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_display.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 3e7ab75e1b41..34e5a883e42e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9976,6 +9976,8 @@ int intel_get_load_detect_pipe(struct drm_connector 
*connector,
ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, 
connector));
if (!ret)
ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, 
crtc));
+   if (!ret)
+   ret = drm_atomic_add_affected_planes(restore_state, crtc);
if (ret) {
DRM_DEBUG_KMS("Failed to create a copy of old state to restore: 
%i\n", ret);
goto fail;
-- 
2.16.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH i-g-t v7] tests/perf_pmu: Improve accuracy by waiting on spinner to start

[Chris Wilson]

Quoting Chris Wilson (2018-03-19 15:29:21)
> Quoting Tvrtko Ursulin (2018-03-19 13:56:05)
> > @@ -443,15 +501,12 @@ most_busy_check_all(int gem_fd, const struct 
> > intel_execution_engine2 *e,
> > if (!gem_has_engine(gem_fd, e_->class, e_->instance))
> > continue;
> >  
> > -   if (e == e_) {
> > +   if (e == e_)
> > idle_idx = i;
> > -   } else if (spin) {
> > -   __submit_spin_batch(gem_fd, , e_);
> > -   } else {
> > -   spin = igt_spin_batch_new(gem_fd, 0,
> > - e2ring(gem_fd, e_), 0);
> > -   obj.handle = spin->handle;
> > -   }
> > +   else if (spin)
> > +   __submit_spin_batch(gem_fd, spin, e_);
> > +   else
> > +   spin = __spin_poll(gem_fd, 0, e2ring(gem_fd, e_));
> 
> So this is what is killing snb. We resubmit the spin-batch, with its
> MI_STORE_DWORD_IMM intact, onto each ring. Instant machine death for snb
> when we reach vcs.
> 
> If we tweak the spinner to jump to a location 64bytes past the start, we
> can opt out of the MI_STORE_DW when not required. Let me go an cook up a
> delta.

diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
index b7a89fd..2a3c3b5 100644
--- a/lib/igt_dummyload.c
+++ b/lib/igt_dummyload.c
@@ -84,7 +84,7 @@ emit_recursive_batch(igt_spin_t *spin, int fd, uint32_t ctx, 
unsigned engine,
 #define SCRATCH 0
 #define BATCH 1
const int gen = intel_gen(intel_get_drm_devid(fd));
-   struct drm_i915_gem_relocation_entry relocs[2];
+   struct drm_i915_gem_relocation_entry relocs[2], *r;
struct drm_i915_gem_execbuffer2 *execbuf;
struct drm_i915_gem_exec_object2 *obj;
unsigned int engines[16];
@@ -182,7 +182,7 @@ emit_recursive_batch(igt_spin_t *spin, int fd, uint32_t 
ctx, unsigned engine,
execbuf->buffer_count++;
}
 
-   spin->batch = batch;
+   spin->batch = batch_start + 64/sizeof(*batch);
spin->handle = obj[BATCH].handle;
 
/* Allow ourselves to be preempted */
@@ -202,26 +202,25 @@ emit_recursive_batch(igt_spin_t *spin, int fd, uint32_t 
ctx, unsigned engine,
batch += 1000;
 
/* recurse */
-   fill_reloc([obj[BATCH].relocation_count],
-  obj[BATCH].handle, (batch - batch_start) + 1,
-  I915_GEM_DOMAIN_COMMAND, 0);
+   r = [obj[BATCH].relocation_count++];
+   r->target_handle = obj[BATCH].handle;
+   r->offset = (batch + 1 - batch_start) * sizeof(*batch);
+   r->read_domains = I915_GEM_DOMAIN_COMMAND;
+   r->delta = 64;
if (gen >= 8) {
*batch++ = MI_BATCH_BUFFER_START | 1 << 8 | 1;
-   *batch++ = 0;
+   *batch++ = r->delta;
*batch++ = 0;
} else if (gen >= 6) {
*batch++ = MI_BATCH_BUFFER_START | 1 << 8;
-   *batch++ = 0;
+   *batch++ = r->delta;
} else {
*batch++ = MI_BATCH_BUFFER_START | 2 << 6;
-   *batch = 0;
-   if (gen < 4) {
-   *batch |= 1;
-   relocs[obj[BATCH].relocation_count].delta = 1;
-   }
+   if (gen < 4)
+   r->delta |= 1;
+   *batch = r->delta;
batch++;
}
-   obj[BATCH].relocation_count++;
obj[BATCH].relocs_ptr = to_user_pointer(relocs);
 
execbuf->buffers_ptr = to_user_pointer(obj +
diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index 87875fb..469b9be 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -474,12 +474,14 @@ busy_check_all(int gem_fd, const struct 
intel_execution_engine2 *e,
 
 static void
 __submit_spin_batch(int gem_fd, igt_spin_t *spin,
-   const struct intel_execution_engine2 *e)
+   const struct intel_execution_engine2 *e,
+   int offset)
 {
struct drm_i915_gem_execbuffer2 eb = spin->execbuf;
 
eb.flags &= ~(0x3f | I915_EXEC_BSD_MASK);
eb.flags |= e2ring(gem_fd, e) | I915_EXEC_NO_RELOC;
+   eb.batch_start_offset += offset;
 
gem_execbuf(gem_fd, );
 }
@@ -504,7 +506,7 @@ most_busy_check_all(int gem_fd, const struct 
intel_execution_engine2 *e,
if (e == e_)
idle_idx = i;
else if (spin)
-   __submit_spin_batch(gem_fd, spin, e_);
+   __submit_spin_batch(gem_fd, spin, e_, 64);
else
spin = __spin_poll(gem_fd, 0, e2ring(gem_fd, e_));
 
@@ -561,7 +563,7 @@ all_busy_check_all(int gem_fd, const unsigned int 
num_engines,
continue;
 
if (spin)
-   __submit_spin_batch(gem_fd, spin, e);
+