Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gvt: Enable KVMGT for BXT
On 2018.06.11 10:09:52 +0100, Chris Wilson wrote: > Quoting Patchwork (2018-06-11 10:05:46) > > == Series Details == > > > > Series: drm/i915/gvt: Enable KVMGT for BXT > > URL : https://patchwork.freedesktop.org/series/44551/ > > State : success > > > > == Summary == > > > > = CI Bug Log - changes from CI_DRM_4299 -> Patchwork_9253 = > > > > == Summary - SUCCESS == > > > > No regressions found. > > > > External URL: > > https://patchwork.freedesktop.org/api/1.0/series/44551/revisions/1/mbox/ > > While we have your attention, please note that all the gvtdvm machines > are failing on suspend. Could you please investigate as it means we have > no coverage at all for the impact on gvt of any patch? Chris, where can we check current gvt-d config on CI machine? -- Open Source Technology Center, Intel ltd. $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827 signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for Some checkpatch fixes for i915_reg.h
== Series Details == Series: Some checkpatch fixes for i915_reg.h URL : https://patchwork.freedesktop.org/series/44662/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4309_full -> Patchwork_9280_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9280_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9280_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9280_full: === IGT changes === Warnings igt@gem_exec_schedule@deep-blt: shard-kbl: PASS -> SKIP +2 igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render: shard-hsw: PASS -> SKIP == Known issues == Here are the changes found in Patchwork_9280_full that come from known issues: === IGT changes === Issues hit igt@gem_mmap_gtt@coherency: shard-glk: NOTRUN -> FAIL (fdo#100587) igt@gem_ppgtt@blt-vs-render-ctxn: shard-kbl: PASS -> INCOMPLETE (fdo#106023, fdo#103665) igt@kms_flip@plain-flip-fb-recreate-interruptible: shard-glk: PASS -> FAIL (fdo#100368) igt@kms_flip@plain-flip-ts-check-interruptible: shard-hsw: PASS -> FAIL (fdo#100368) igt@kms_setmode@basic: shard-glk: NOTRUN -> FAIL (fdo#99912) igt@kms_sysfs_edid_timing: shard-glk: NOTRUN -> WARN (fdo#100047) igt@perf@polling: shard-hsw: PASS -> FAIL (fdo#102252) igt@perf_pmu@busy-accuracy-50-vcs1: shard-snb: SKIP -> INCOMPLETE (fdo#105411) Possible fixes igt@drv_selftest@live_gtt: shard-kbl: FAIL (fdo#105347) -> PASS igt@gem_ppgtt@blt-vs-render-ctx0: shard-kbl: INCOMPLETE (fdo#106023, fdo#103665) -> PASS igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing: shard-glk: FAIL (fdo#105703) -> PASS igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: shard-hsw: FAIL (fdo#102887) -> PASS igt@kms_flip@flip-vs-expired-vblank-interruptible: shard-hsw: FAIL (fdo#102887, fdo#105363) -> PASS fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047 fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#100587 https://bugs.freedesktop.org/show_bug.cgi?id=100587 fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#105347 https://bugs.freedesktop.org/show_bug.cgi?id=105347 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703 fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4309 -> Patchwork_9280 CI_DRM_4309: 2740c5b0d0f40092355b329a62ede8cced7f64b9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4517: e94ce40798e35d2e3c4494f50b617908066bbf8b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9280: a1e3b46722bedf3718054217a0c0f1f1b6175e72 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9280/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] DRM Inquiry
Hi Jani, I like to understand how the DRM_DP_AUX_CHARDEV=y kick off. Regards,John On Monday, June 11, 2018, 7:36:51 PM GMT+8, Jani Nikula wrote: On Mon, 11 Jun 2018, John Sledge wrote: > Thanks for the help. I was able to manage your advice on the > drm_dp_aux_chardev. Though I still need to learn more about the DRM vs > kernel process flow. Like for example, upon changing/adding > DRM_DP_AUX_CHARDEV in kernel .config, How did DRM_DP_AUX_CHARDEV was > being invoke here? From the code, I notice character device will be > created under drm_dp_aux_register_devnode method. > For example I made two kernel 4.6 with DRM_DP_AUX_CHARDEV=y and > another kernel 4.6 with DRM_DP_AUX_CHARDEV=n. > So the steps was to build and install the kernel with > DRM_DP_AUX_CHARDEV=y. Once finish, I tried to reboot and verified the > /dev/drm_dp_aux_chardev* and it was there. > Now, I will change the .config DRM_DP_AUXCHARDEV=n then follow the > steps below to manual build the DRM module. I'm not really sure if I'm > correct on this one. Why are you disabling it again? Just enable the config, use the resulting kernel, and do the rest in userspace. > 1. rm /dev/drm_dp_aux_chardev* 2. make modules_prepare3. make > SUBDIRS=scripts/mod4. make SUBDIRS=drivers/gpu/drm modules5. cp > drivers/gpu/drm/i915/i915.ko > /lib/modules/4.6.0-94.11-default/kernel/drivers/gpu/drm6. ... I copy > all .ko under drm to the lib/modules/4.67. depmod8. modprobe > i9159. ... I also modprobe all modules10. reboot > The result was /dev/drm_dp_aux_chardev* was still there. My > expectation was it would disrepair or remove. Don't do this. I don't understand what you're trying to do. > Please have comments and advice. Please explain what you're trying to do to begin with. What's your end goal? BR, Jani. PS. Please prefer plain text instead of html on the list. -- Jani Nikula, Intel Open Source Graphics Center ___ dri-devel mailing list dri-de...@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for Some checkpatch fixes for i915_reg.h
== Series Details == Series: Some checkpatch fixes for i915_reg.h URL : https://patchwork.freedesktop.org/series/44662/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4309 -> Patchwork_9280 = == Summary - WARNING == Minor unknown changes coming with Patchwork_9280 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9280, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/44662/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9280: === IGT changes === Warnings igt@gem_exec_gttfill@basic: fi-pnv-d510:SKIP -> PASS == Known issues == Here are the changes found in Patchwork_9280 that come from known issues: === IGT changes === Issues hit igt@debugfs_test@read_all_entries: fi-snb-2520m: PASS -> INCOMPLETE (fdo#103713) igt@gem_exec_create@basic: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106745) igt@gem_exec_suspend@basic-s3: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106097) igt@gem_exec_suspend@basic-s4-devices: fi-hsw-peppy: PASS -> FAIL (fdo#105900) Possible fixes igt@gem_exec_suspend@basic-s4-devices: fi-kbl-7500u: DMESG-WARN (fdo#105128) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-c: fi-glk-j4005: DMESG-WARN (fdo#106097) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-cnl-psr: DMESG-WARN (fdo#104951) -> PASS fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951 fdo#105128 https://bugs.freedesktop.org/show_bug.cgi?id=105128 fdo#105900 https://bugs.freedesktop.org/show_bug.cgi?id=105900 fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097 fdo#106745 https://bugs.freedesktop.org/show_bug.cgi?id=106745 == Participating hosts (43 -> 38) == Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-skl-6700hq == Build changes == * Linux: CI_DRM_4309 -> Patchwork_9280 CI_DRM_4309: 2740c5b0d0f40092355b329a62ede8cced7f64b9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4517: e94ce40798e35d2e3c4494f50b617908066bbf8b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9280: a1e3b46722bedf3718054217a0c0f1f1b6175e72 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == a1e3b46722be drm/i915/i915_reg.h: fix the checkpatch MACRO_ARG_PRECEDENCE issues 349125104d4c drm/i915/i915_reg.h: fix the checkpatch SPACE_BEFORE_TAB issues fa21130f6a88 drm/i915/i915_reg.h: fix the checkpatch SPACING issues == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9280/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Some checkpatch fixes for i915_reg.h
== Series Details == Series: Some checkpatch fixes for i915_reg.h URL : https://patchwork.freedesktop.org/series/44662/ State : warning == Summary == $ dim checkpatch origin/drm-tip fa21130f6a88 drm/i915/i915_reg.h: fix the checkpatch SPACING issues -:4: WARNING:EMAIL_SUBJECT: A patch subject line should describe the change not the tool that found it #4: Subject: [PATCH] drm/i915/i915_reg.h: fix the checkpatch SPACING issues -:50: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'a' - possible side-effects? #50: FILE: drivers/gpu/drm/i915/i915_reg.h:144: +#define _PIPE(pipe, a, b) ((a) + (pipe) * ((b) - (a))) -:55: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'a' - possible side-effects? #55: FILE: drivers/gpu/drm/i915/i915_reg.h:148: +#define _TRANS(tran, a, b) ((a) + (tran) * ((b) - (a))) -:58: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'a' - possible side-effects? #58: FILE: drivers/gpu/drm/i915/i915_reg.h:150: +#define _PORT(port, a, b) ((a) + (port) * ((b) - (a))) -:63: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'a' - possible side-effects? #63: FILE: drivers/gpu/drm/i915/i915_reg.h:154: +#define _PLL(pll, a, b) ((a) + (pll) * ((b) - (a))) -:1065: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #1065: FILE: drivers/gpu/drm/i915/i915_reg.h:2415: +#define DERRMR_PIPEB_SCANLINE ^I(1 << 8)$ -:1633: WARNING:LONG_LINE: line over 100 characters #1633: FILE: drivers/gpu/drm/i915/i915_reg.h:3130: +#define PHY_STATUS_SPLINE_LDO(phy, ch, spline)(1 << (8 - (6 * (phy) + 3 * (ch) + (spline -:1845: WARNING:LONG_LINE_COMMENT: line over 100 characters #1845: FILE: drivers/gpu/drm/i915/i915_reg.h:3645: +#define IMPROMOEN(1 << 10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */ -:3186: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'a' - possible side-effects? #3186: FILE: drivers/gpu/drm/i915/i915_reg.h:6826: +#define _ID(id, a, b) ((a) + (id) * ((b) - (a))) total: 0 errors, 4 warnings, 5 checks, 4617 lines checked 349125104d4c drm/i915/i915_reg.h: fix the checkpatch SPACE_BEFORE_TAB issues -:4: WARNING:EMAIL_SUBJECT: A patch subject line should describe the change not the tool that found it #4: Subject: [PATCH] drm/i915/i915_reg.h: fix the checkpatch SPACE_BEFORE_TAB total: 0 errors, 1 warnings, 0 checks, 32 lines checked a1e3b46722be drm/i915/i915_reg.h: fix the checkpatch MACRO_ARG_PRECEDENCE issues -:4: WARNING:EMAIL_SUBJECT: A patch subject line should describe the change not the tool that found it #4: Subject: [PATCH] drm/i915/i915_reg.h: fix the checkpatch MACRO_ARG_PRECEDENCE total: 0 errors, 1 warnings, 0 checks, 138 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gtt: Only keep gen6 page directories pinned while active
== Series Details == Series: drm/i915/gtt: Only keep gen6 page directories pinned while active URL : https://patchwork.freedesktop.org/series/44649/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4308_full -> Patchwork_9278_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_9278_full that come from known issues: === IGT changes === Issues hit igt@drv_selftest@live_gtt: shard-glk: NOTRUN -> INCOMPLETE (k.org#198133, fdo#103359) igt@drv_selftest@mock_scatterlist: shard-glk: NOTRUN -> DMESG-WARN (fdo#103667) igt@gem_exec_schedule@pi-ringfull-bsd: shard-glk: NOTRUN -> FAIL (fdo#103158) +1 igt@gem_exec_suspend@basic-s4-devices: shard-hsw: PASS -> FAIL (fdo#105900) +1 igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic: shard-glk: NOTRUN -> FAIL (fdo#106509, fdo#105454) igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: shard-glk: PASS -> FAIL (fdo#105363) igt@kms_flip@dpms-vs-vblank-race-interruptible: shard-hsw: PASS -> FAIL (fdo#103060) igt@kms_flip@flip-vs-expired-vblank: shard-glk: NOTRUN -> FAIL (fdo#105189) igt@kms_flip@flip-vs-panning-vs-hang-interruptible: shard-snb: PASS -> DMESG-WARN (fdo#103821) igt@kms_rotation_crc@primary-rotation-270: shard-apl: PASS -> FAIL (fdo#103925, fdo#104724) +1 Possible fixes igt@drv_suspend@shrink: shard-kbl: INCOMPLETE (fdo#103665, fdo#106886) -> PASS igt@gem_ppgtt@blt-vs-render-ctxn: shard-kbl: INCOMPLETE (fdo#103665, fdo#106023) -> PASS igt@kms_atomic_transition@1x-modeset-transitions-nonblocking: shard-glk: FAIL (fdo#105703) -> PASS igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic: shard-hsw: FAIL (fdo#105767) -> PASS igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: shard-hsw: FAIL (fdo#102887) -> PASS fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887 fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060 fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#103667 https://bugs.freedesktop.org/show_bug.cgi?id=103667 fdo#103821 https://bugs.freedesktop.org/show_bug.cgi?id=103821 fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 fdo#105189 https://bugs.freedesktop.org/show_bug.cgi?id=105189 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454 fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703 fdo#105767 https://bugs.freedesktop.org/show_bug.cgi?id=105767 fdo#105900 https://bugs.freedesktop.org/show_bug.cgi?id=105900 fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023 fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509 fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4308 -> Patchwork_9278 CI_DRM_4308: 355cdcfec85bdd8bea927357789f53e4dec4f7b2 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4517: e94ce40798e35d2e3c4494f50b617908066bbf8b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9278: e8c416abf96f31a6541d5a052849db26eee8ef8b @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9278/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/3] drm/i915/i915_reg.h: fix the checkpatch MACRO_ARG_PRECEDENCE issues
While I don't see any issue with the way these macros are being called
today, let's protect them against operator precedence issues before
they happen.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_reg.h | 42 -
1 file changed, 21 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f9a7cc5da5d8..1803995db1ca 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1779,7 +1779,7 @@ enum i915_power_well_id {
#define CNL_PORT_TX_DW4_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 4))
#define CNL_PORT_TX_DW4_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 4))
#define CNL_PORT_TX_DW4_LN(port, ln) _MMIO(_CNL_PORT_TX_DW_LN0((port), 4) + \
-(ln * (_CNL_PORT_TX_DW4_LN1_AE - \
+ ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \
_CNL_PORT_TX_DW4_LN0_AE)))
#define _ICL_PORT_TX_DW4_GRP_A 0x162690
#define _ICL_PORT_TX_DW4_GRP_B 0x6C690
@@ -1792,8 +1792,8 @@ enum i915_power_well_id {
#define ICL_PORT_TX_DW4_LN(port, ln) _MMIO(_PORT(port, \
_ICL_PORT_TX_DW4_LN0_A, \
_ICL_PORT_TX_DW4_LN0_B) + \
- (ln * (_ICL_PORT_TX_DW4_LN1_A - \
-_ICL_PORT_TX_DW4_LN0_A)))
+((ln) * (_ICL_PORT_TX_DW4_LN1_A - \
+ _ICL_PORT_TX_DW4_LN0_A)))
#define LOADGEN_SELECT (1 << 31)
#define POST_CURSOR_1(x) ((x) << 12)
#define POST_CURSOR_1_MASK (0x3F << 12)
@@ -6070,8 +6070,8 @@ enum {
/* Display/Sprite base address macros */
#define DISP_BASEADDR_MASK (0xf000)
-#define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK)
-#define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK)
+#define I915_LO_DISPBASE(val) ((val) & ~DISP_BASEADDR_MASK)
+#define I915_HI_DISPBASE(val) ((val) & DISP_BASEADDR_MASK)
/*
* VBIOS flags
@@ -7085,7 +7085,7 @@ enum {
#define GEN11_VECS(x) (31 - (x))
#define GEN11_VCS(x) (x)
-#define GEN11_GT_INTR_DW(x)_MMIO(0x190018 + (x * 4))
+#define GEN11_GT_INTR_DW(x)_MMIO(0x190018 + ((x) * 4))
#define GEN11_INTR_IDENTITY_REG0 _MMIO(0x190060)
#define GEN11_INTR_IDENTITY_REG1 _MMIO(0x190064)
@@ -7094,12 +7094,12 @@ enum {
#define GEN11_INTR_ENGINE_INSTANCE(x) (((x) & GENMASK(25, 20)) >> 20)
#define GEN11_INTR_ENGINE_INTR(x) ((x) & 0x)
-#define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + (x * 4))
+#define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
#define GEN11_IIR_REG0_SELECTOR_MMIO(0x190070)
#define GEN11_IIR_REG1_SELECTOR_MMIO(0x190074)
-#define GEN11_IIR_REG_SELECTOR(x) _MMIO(0x190070 + (x * 4))
+#define GEN11_IIR_REG_SELECTOR(x) _MMIO(0x190070 + ((x) * 4))
#define GEN11_RENDER_COPY_INTR_ENABLE _MMIO(0x190030)
#define GEN11_VCS_VECS_INTR_ENABLE _MMIO(0x190034)
@@ -7491,15 +7491,15 @@ enum {
#define _PCH_DPLL_A 0xc6014
#define _PCH_DPLL_B 0xc6018
-#define PCH_DPLL(pll) _MMIO(pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
+#define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
#define _PCH_FPA00xc6040
#define FP_CB_TUNE(0x3 << 22)
#define _PCH_FPA10xc6044
#define _PCH_FPB00xc6048
#define _PCH_FPB10xc604c
-#define PCH_FP0(pll) _MMIO(pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
-#define PCH_FP1(pll) _MMIO(pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
+#define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0)
+#define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1)
#define PCH_DPLL_TEST _MMIO(0xc606c)
@@ -8331,11 +8331,11 @@ enum {
#define GEN7_L3CDERRST1_BANK_MASK(3 << 11)
#define GEN7_L3CDERRST1_SUBBANK_MASK (7 << 8)
#define GEN7_PARITY_ERROR_ROW(reg) \
- ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14)
+ (((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14)
#define GEN7_PARITY_ERROR_BANK(reg) \
- ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11)
+ (((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11)
#define GEN7_PARITY_ERROR_SUBBANK(reg) \
- ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
+ (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
#define GEN7_L3CDERRST1_ENABLE (1 << 7)
#define GEN7_L3LOG(slice, i) _MMIO(0xB070 + (slice) * 0x200 + (i) *
4)
@@ -8608,7 +8608,7 @@ enum skl_power_gate {
#define HDCP_SHA_V_PRIME_H2_MMIO(0x66d0C)
#define HDCP_SHA_V_PRIME_H3_MMIO(0x66d10)
#define HDCP_SHA_V_PRIME_H4
[Intel-gfx] [PATCH 2/3] drm/i915/i915_reg.h: fix the checkpatch SPACE_BEFORE_TAB issues
Since I'm touching the file I might as well fix this class of errors
since they are just a few. Also drive-by fix the styling of the
VLV_TURBO_SOC_OVERRIDE definitions instead of just the spaces before
the tabs.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_reg.h | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5e1d391b74db..f9a7cc5da5d8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1141,11 +1141,11 @@ enum i915_power_well_id {
#define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
#define FB_FMAX_VMIN_FREQ_LO_MASK0xf800
-#define VLV_TURBO_SOC_OVERRIDE 0x04
-#defineVLV_OVERRIDE_EN 1
-#defineVLV_SOC_TDP_EN (1 << 1)
-#defineVLV_BIAS_CPU_125_SOC_875 (6 << 2)
-#defineCHV_BIAS_CPU_50_SOC_50 (3 << 2)
+#define VLV_TURBO_SOC_OVERRIDE 0x04
+#define VLV_OVERRIDE_EN 1
+#define VLV_SOC_TDP_EN (1 << 1)
+#define VLV_BIAS_CPU_125_SOC_875 (6 << 2)
+#define CHV_BIAS_CPU_50_SOC_50 (3 << 2)
/* vlv2 north clock has */
#define CCK_FUSE_REG 0x8
@@ -2412,7 +2412,7 @@ enum i915_power_well_id {
#define DERRMR_PIPEA_SPR_FLIP_DONE (1 << 2)
#define DERRMR_PIPEA_VBLANK (1 << 3)
#define DERRMR_PIPEA_HBLANK (1 << 5)
-#define DERRMR_PIPEB_SCANLINE(1 << 8)
+#define DERRMR_PIPEB_SCANLINE(1 << 8)
#define DERRMR_PIPEB_PRI_FLIP_DONE (1 << 9)
#define DERRMR_PIPEB_SPR_FLIP_DONE (1 << 10)
#define DERRMR_PIPEB_VBLANK (1 << 11)
@@ -7567,7 +7567,7 @@ enum {
#define TRANS_VBLANK_END_SHIFT16
#define TRANS_VBLANK_START_SHIFT 0
#define _PCH_TRANS_VSYNC_A 0xe0014
-#define TRANS_VSYNC_END_SHIFT 16
+#define TRANS_VSYNC_END_SHIFT 16
#define TRANS_VSYNC_START_SHIFT 0
#define _PCH_TRANS_VSYNCSHIFT_A0xe0028
--
2.14.4
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Re: [Intel-gfx] [PATCH 1/4] drm/i915: fix guest virtual PCH detection on non-PCH systems
On Fri, Jun 8, 2018 at 5:34 AM Jani Nikula wrote:
>
> On Thu, 31 May 2018, Lucas De Marchi wrote:
> > On Thu, May 31, 2018 at 02:56:21PM +0300, Jani Nikula wrote:
> >> Virtualized non-PCH systems such as Broxton or Geminilake should use
> >> PCH_NONE to indicate no PCH rather than PCH_NOP. The latter is a
> >> specific case to indicate a PCH system without south display.
> >
> > Then let's go ahead and document it?
>
> Please avoid sending suggestion patches in-reply-to existing
> series. This confused patchwork and screwed up CI for the series, which
> was already a resend just to get CI. :(
ugh, sorry. Sometimes just adding a oneline diff is much better than
a hundred words explaining :( ... IMO pw is trying to be smarter than
it should here or not being smart enough. Nonetheless I won't do that
anymore.
Lucas De Marchi
>
> I'm resending the series, with your documentation patch added, but I'm
> keeping the extra explanatory text in the last patch. I think it's
> warranted.
>
> BR,
> Jani.
>
>
> >
> > -
> > Subject: [PATCH] drm/i915: document PCH_NOP
> >
> > There's a difference between PCH_NONE and PCH_NOP: the former means we
> > don't have a PCH while in the latter we do, but it doesn't have the
> > south display.
> >
> > Cc: Jani Nikula
> > Signed-off-by: Lucas De Marchi
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 72150f89f200..aa395a898258 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -631,7 +631,7 @@ enum intel_pch {
> > PCH_KBP,/* Kaby Lake PCH */
> > PCH_CNP,/* Cannon Lake PCH */
> > PCH_ICP,/* Ice Lake PCH */
> > - PCH_NOP,
> > + PCH_NOP,/* PCH without south display */
> > };
> >
> > enum intel_sbi_destination {
>
> --
> Jani Nikula, Intel Open Source Graphics Center
--
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Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled (rev3)
On 6/12/2018 11:09 AM, Saarinen, Jani wrote: HI, -Original Message- From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of Patchwork Sent: tiistai 12. kesäkuuta 2018 11.38 To: Kumar, Abhay Cc: intel-gfx@lists.freedesktop.org Subject: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled (rev3) == Series Details == Series: drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled (rev3) URL : https://patchwork.freedesktop.org/series/42459/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4304_full -> Patchwork_9268_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9268_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9268_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9268_full: === IGT changes === Warnings igt@gem_exec_schedule@deep-bsd2: shard-kbl: PASS -> SKIP igt@gem_exec_schedule@deep-vebox: shard-kbl: SKIP -> PASS == Known issues == Here are the changes found in Patchwork_9268_full that come from known issues: === IGT changes === Issues hit igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: shard-hsw: PASS -> FAIL (fdo#102887) igt@kms_setmode@basic: shard-kbl: PASS -> FAIL (fdo#99912) Possible fixes igt@drv_selftest@live_gtt: shard-kbl: FAIL (fdo#105347) -> PASS igt@drv_suspend@shrink: shard-hsw: INCOMPLETE (fdo#103540) -> PASS igt@kms_rotation_crc@sprite-rotation-180: shard-hsw: FAIL (fdo#103925, fdo#104724) -> PASS fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887 fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540 fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 fdo#105347 https://bugs.freedesktop.org/show_bug.cgi?id=105347 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (5 -> 4) == Missing(1): shard-glk There glk's are but some issues: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9268/shard-glk1/ https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9268/shard-glk2/run2.log etc... Worth to investigate... May be this is due to turning off and on Power well 2. Sent another patchset where we restart power well2 for any cdclk change only for glk. + Tomi too. == Build changes == * Linux: CI_DRM_4304 -> Patchwork_9268 CI_DRM_4304: 2313a1dc588ef63d9650ccbaaf576bc4b47dc255 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4515: a0f2d23b7d3d4226a0a7637a9240bfa86f08c1d3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9268: 7e66d7400ee9f80e00633e6cfdecc354dda8e049 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm- tip/Patchwork_9268/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/3] Some checkpatch fixes for i915_reg.h
Hi This is a follow-up on the discussion we recently had on "Re: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/2] drm/i915/icl: Add allowed DP rates for Icelake". Let's fix the spacing issues once and for all, so now we can simply block every new patch instead of having to either ask authors to submit a new version of ignore the checkpatch errors. Also drive-by fix some other easy and relevant issues on the file. There are still many checkpatch issues and many conding style issues in the file, but at least now we're fixing the problem that keeps appearing on the mailing list. Thanks, Paulo Paulo Zanoni (3): drm/i915/i915_reg.h: fix the checkpatch SPACING issues drm/i915/i915_reg.h: fix the checkpatch SPACE_BEFORE_TAB issues drm/i915/i915_reg.h: fix the checkpatch MACRO_ARG_PRECEDENCE issues drivers/gpu/drm/i915/i915_reg.h | 3236 +++ 1 file changed, 1618 insertions(+), 1618 deletions(-) -- 2.14.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 0/7] drm/i915: move towards kernel types
On Tue, Jun 12, 2018 at 3:15 AM Jani Nikula wrote: > > On Tue, 12 Jun 2018, Tvrtko Ursulin wrote: > > On 12/06/2018 10:19, Jani Nikula wrote: > >> Semi-RFC. Do we want to do this? Here's a batch of conversions that > >> shouldn't > >> conflict much with in-flight patches. > >> > >> The trouble with mixed use is that it's inconsistent, and any remaining C99 > >> types will encourage their use. We could at least do the low hanging fruit? > > > > Ack from me. Doesn't seem so big to cause much pain. > > > > When you say low-hanging fruit, that implies you only dealt with a > > particular class of occurrences? > > I meant the files which don't have massive amounts of C99 types and > aren't under active development right now. I just wanted to avoid > trouble for starters. ;) If using kernel types is where we want to go (which I agree with), maybe it would be better to have a single conversion rather than several small ones as we are doing with dev_priv -> i915? This allows in-flight-but-not-yet-sent patches to easily keep up with the changes rather than conflicting every other rebase. Lucas De Marchi > > > Also going forward we have to make sure we will be able to stop them > > creeping back in. Is checkpatch perhaps covering this? Or we could put > > something in dim? > > We can stop ignoring PREFER_KERNEL_TYPES in checkpatch (the ignores are > in dim). We don't even have to change everything for that, we just need > to change enough to make the S/N better. People tend to use the types > near the places they change. > > BR, > Jani. > > > > > > Regards, > > > > Tvrtko > > > >> $ git grep "uint\(8\|16\|32\|64\)_t" -- drivers/gpu/drm/i915/ | sed > >> 's/:.*//' | sort | uniq -c | sort -n > >> > >> BR, > >> Jani. > >> > >> > >> Jani Nikula (7): > >>drm/i915/vbt: switch to kernel unsigned int types > >>drm/i915/hdmi: switch to kernel unsigned int types > >>drm/i915/uncore: switch to kernel unsigned int types > >>drm/i915/dvo: switch to kernel unsigned int types > >>drm/i915/backlight: switch to kernel unsigned int types > >>drm/i915/audio: switch to kernel unsigned int types > >>drm/i915/lspcon: switch to kernel unsigned int types > >> > >> drivers/gpu/drm/i915/dvo_ch7017.c | 20 ++-- > >> drivers/gpu/drm/i915/dvo_ch7xxx.c | 22 +++--- > >> drivers/gpu/drm/i915/dvo_ivch.c | 26 > >> drivers/gpu/drm/i915/dvo_ns2501.c | 44 > >> +-- > >> drivers/gpu/drm/i915/dvo_sil164.c | 10 +++--- > >> drivers/gpu/drm/i915/dvo_tfp410.c | 16 +- > >> drivers/gpu/drm/i915/intel_audio.c| 36 +++--- > >> drivers/gpu/drm/i915/intel_bios.c | 4 +-- > >> drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 12 > >> drivers/gpu/drm/i915/intel_dvo.c | 2 +- > >> drivers/gpu/drm/i915/intel_hdmi.c | 14 - > >> drivers/gpu/drm/i915/intel_lspcon.c | 2 +- > >> drivers/gpu/drm/i915/intel_panel.c| 8 ++--- > >> drivers/gpu/drm/i915/intel_uncore.h | 22 +++--- > >> drivers/gpu/drm/i915/intel_vbt_defs.h | 2 +- > >> 15 files changed, 120 insertions(+), 120 deletions(-) > >> > > -- > Jani Nikula, Intel Open Source Graphics Center > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Lucas De Marchi ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: add support for perf configuration queries (rev2)
== Series Details == Series: drm/i915: add support for perf configuration queries (rev2) URL : https://patchwork.freedesktop.org/series/44290/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4308_full -> Patchwork_9277_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9277_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9277_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9277_full: === IGT changes === Warnings igt@gem_mocs_settings@mocs-rc6-bsd2: shard-kbl: SKIP -> PASS igt@gem_mocs_settings@mocs-rc6-ctx-render: shard-kbl: PASS -> SKIP == Known issues == Here are the changes found in Patchwork_9277_full that come from known issues: === IGT changes === Issues hit igt@drv_selftest@live_hangcheck: shard-apl: PASS -> DMESG-FAIL (fdo#106560) igt@drv_selftest@mock_scatterlist: shard-glk: NOTRUN -> DMESG-WARN (fdo#103667) igt@gem_exec_schedule@pi-ringfull-render: shard-glk: NOTRUN -> FAIL (fdo#103158) +1 igt@kms_available_modes_crc@available_mode_test_crc: shard-glk: NOTRUN -> FAIL (fdo#106641) igt@kms_flip@2x-plain-flip-ts-check-interruptible: shard-glk: PASS -> FAIL (fdo#100368) igt@kms_flip@flip-vs-expired-vblank: shard-glk: NOTRUN -> FAIL (fdo#102887) igt@kms_flip_tiling@flip-to-x-tiled: shard-glk: NOTRUN -> FAIL (fdo#103822, fdo#104724) igt@kms_setmode@basic: shard-apl: PASS -> FAIL (fdo#99912) Possible fixes igt@drv_suspend@shrink: shard-kbl: INCOMPLETE (fdo#106886, fdo#103665) -> PASS igt@gem_ppgtt@blt-vs-render-ctxn: shard-kbl: INCOMPLETE (fdo#106023, fdo#103665) -> PASS igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic: shard-hsw: FAIL (fdo#105767) -> PASS igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: shard-hsw: FAIL (fdo#102887) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887 fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#103667 https://bugs.freedesktop.org/show_bug.cgi?id=103667 fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 fdo#105767 https://bugs.freedesktop.org/show_bug.cgi?id=105767 fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023 fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560 fdo#106641 https://bugs.freedesktop.org/show_bug.cgi?id=106641 fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4308 -> Patchwork_9277 CI_DRM_4308: 355cdcfec85bdd8bea927357789f53e4dec4f7b2 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4517: e94ce40798e35d2e3c4494f50b617908066bbf8b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9277: 31b5046df85fcf24ed17b9d4d15e7c1164f9c324 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9277/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/psr : Add psr1 live status
On Fri, 2018-05-25 at 11:50 +0530, vathsala nagaraju wrote:
> From: Vathsala Nagaraju
>
> Prints live state of psr1.Extending the existing
> PSR2 live state function to cover psr1.
>
> Tested on KBL with psr2 and psr1 panel.
>
> v2: rebase
> v3: DK
> Rename psr2_live_status to psr_source_status.
> v4: DK
> Move EDP_PSR_STATUS_STATE_SHIFT below EDP_PSR_STATUS_STATE_MASK.
> Pass seq to psr_source_status, handle source status prints in
> psr_source_status.
> v5: Fixed CI warning messages
>
> Cc: Rodrigo Vivi
> Cc: Dhinakaran Pandiyan
>
nit: Noticed an extra space in the title before the colon.
Reviewed-by: Dhinakaran Pandiyan
> Signed-off-by: Vathsala Nagaraju
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 72 ---
> --
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 49 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 5251544..1d45cb9 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2596,27 +2596,55 @@ static int i915_guc_log_relay_release(struct
> inode *inode, struct file *file)
> .release = i915_guc_log_relay_release,
> };
>
> -static const char *psr2_live_status(u32 val)
> -{
> - static const char * const live_status[] = {
> - "IDLE",
> - "CAPTURE",
> - "CAPTURE_FS",
> - "SLEEP",
> - "BUFON_FW",
> - "ML_UP",
> - "SU_STANDBY",
> - "FAST_SLEEP",
> - "DEEP_SLEEP",
> - "BUF_ON",
> - "TG_ON"
> - };
> +static void
> +psr_source_status(struct drm_i915_private *dev_priv, struct seq_file
> *m)
> +{
> + u32 val, psr_status = 0;
>
> - val = (val & EDP_PSR2_STATUS_STATE_MASK) >>
> EDP_PSR2_STATUS_STATE_SHIFT;
> - if (val < ARRAY_SIZE(live_status))
> - return live_status[val];
> + if (dev_priv->psr.psr2_enabled) {
> + static const char * const live_status[] = {
> + "IDLE",
> + "CAPTURE",
> + "CAPTURE_FS",
> + "SLEEP",
> + "BUFON_FW",
> + "ML_UP",
> + "SU_STANDBY",
> + "FAST_SLEEP",
> + "DEEP_SLEEP",
> + "BUF_ON",
> + "TG_ON"
> + };
> + psr_status = I915_READ(EDP_PSR2_STATUS);
> + val = (psr_status & EDP_PSR2_STATUS_STATE_MASK) >>
> + EDP_PSR2_STATUS_STATE_SHIFT;
> + if (val < ARRAY_SIZE(live_status)) {
> + seq_printf(m, "Source PSR status: %x[%s]\n",
> psr_status,
> + live_status[val]);
> + return;
> + }
> + } else {
> + static const char * const live_status[] = {
> + "IDLE",
> + "SRDONACK",
> + "SRDENT",
> + "BUFOFF",
> + "BUFON",
> + "AUXACK",
> + "SRDOFFACK",
> + "SRDENT_ON",
> + };
> + psr_status = I915_READ(EDP_PSR_STATUS);
> + val = (psr_status & EDP_PSR_STATUS_STATE_MASK) >>
> + EDP_PSR_STATUS_STATE_SHIFT;
^alignment is different from the PSR2 block.
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[Intel-gfx] ✗ Fi.CI.IGT: failure for tests/i915-query: new tests for listing perf configurations
== Series Details == Series: tests/i915-query: new tests for listing perf configurations URL : https://patchwork.freedesktop.org/series/44644/ State : failure == Summary == = CI Bug Log - changes from IGT_4516_full -> IGTPW_1451_full = == Summary - FAILURE == Serious unknown changes coming with IGTPW_1451_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in IGTPW_1451_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/44644/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in IGTPW_1451_full: === IGT changes === Possible regressions igt@kms_cursor_legacy@flip-vs-cursor-varying-size: shard-hsw: PASS -> FAIL Warnings igt@gem_exec_schedule@deep-bsd2: shard-kbl: PASS -> SKIP igt@gem_mocs_settings@mocs-rc6-ctx-dirty-render: shard-kbl: SKIP -> PASS +1 == Known issues == Here are the changes found in IGTPW_1451_full that come from known issues: === IGT changes === Issues hit igt@drv_suspend@shrink: shard-hsw: PASS -> INCOMPLETE (fdo#103540) igt@gem_busy@basic-busy-default: shard-snb: PASS -> INCOMPLETE (fdo#105411) igt@gem_exec_schedule@pi-ringfull-bsd: shard-glk: NOTRUN -> FAIL (fdo#103158) igt@kms_atomic_transition@1x-modeset-transitions-nonblocking: shard-glk: NOTRUN -> FAIL (fdo#105703) igt@kms_available_modes_crc@available_mode_test_crc: shard-snb: PASS -> FAIL (fdo#106641) igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic: shard-glk: PASS -> FAIL (fdo#105454, fdo#106509) igt@kms_flip@flip-vs-expired-vblank: shard-hsw: PASS -> FAIL (fdo#105189) igt@kms_flip@plain-flip-fb-recreate-interruptible: shard-hsw: PASS -> FAIL (fdo#100368) igt@kms_flip_tiling@flip-to-x-tiled: shard-glk: NOTRUN -> FAIL (fdo#104724) igt@kms_flip_tiling@flip-x-tiled: shard-glk: NOTRUN -> FAIL (fdo#103822, fdo#104724) +1 igt@kms_setmode@basic: shard-apl: PASS -> FAIL (fdo#99912) igt@kms_sysfs_edid_timing: shard-glk: NOTRUN -> WARN (fdo#100047) Possible fixes igt@drv_selftest@live_hangcheck: shard-apl: DMESG-FAIL (fdo#106560) -> PASS igt@kms_cursor_legacy@cursor-vs-flip-toggle: shard-hsw: FAIL (fdo#103355) -> PASS igt@kms_flip@plain-flip-fb-recreate-interruptible: shard-glk: FAIL (fdo#100368) -> PASS +1 igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-wc: shard-snb: INCOMPLETE (fdo#105411) -> PASS igt@kms_plane_multiple@atomic-pipe-a-tiling-x: shard-snb: FAIL (fdo#103166, fdo#104724) -> PASS igt@perf_pmu@rc6-runtime-pm-long: shard-apl: FAIL (fdo#105010) -> PASS shard-kbl: FAIL (fdo#105010) -> PASS fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047 fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158 fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166 fdo#103355 https://bugs.freedesktop.org/show_bug.cgi?id=103355 fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540 fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 fdo#105010 https://bugs.freedesktop.org/show_bug.cgi?id=105010 fdo#105189 https://bugs.freedesktop.org/show_bug.cgi?id=105189 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454 fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703 fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509 fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560 fdo#106641 https://bugs.freedesktop.org/show_bug.cgi?id=106641 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * IGT: IGT_4516 -> IGTPW_1451 * Linux: CI_DRM_4306 -> CI_DRM_4307 CI_DRM_4306: 46ac5b5698d4aea58eb440f1ec47d734762259f7 @ git://anongit.freedesktop.org/gfx-ci/linux CI_DRM_4307: 0cf6f8f74cad691364d738d1607bc45945f3a5f9 @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_1451: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1451/ IGT_4516: 95bfb2902473b9f4e644c3eb831fdf110d87ed4f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools == Logs == For more details see:
[Intel-gfx] [PATCH v4 2/2] drm/i915: Shut off PW2 when changing cdclk on glk
From: Ville Syrjälä
Apparently the audio hardware gets confused if it's powered up when
change the cdclk frequency. Force PW2 (which is where audio lives)
off when we do the cdclk reprogramming.
This is a rather big hack. If something is using PW2 when we do this
things wil break. I don't think there should be anything active on
the display side since we've turned off all the pipes and we've locked
out gmbus and aux, but I may be overlooking something. The problem
is more on the audio side. If audio is active when we do this PW2
toggle I'm sure something "interesting" will happen. But presumably
something would also happen if we just changed cdclk without the PW2
toggle.
A better fix would involve somehow forcing everything to drop
their PW2 references, which isn't trivial. And to make the audio driver
participate in this scheme we'd definitely need some kind of pre/post
cdclk change notify hooks in the audio component so that i915 can
actually inform the audio driver that the cdclk is going to be changed.
Either that or the audio driver would have to promise never to touch
the hardware when the pipes are off (which is how the VLV/CHV LPE
audio driver works IIRC).
Even with this hacky scheme it would make more sense to me to have
the pre/post cdclk change hooks so that the audio driver is actually
informed when the cdclk change/pw2 toggle will occur. What the audio
driver would do to prepare itself I don't actually know.
Signed-off-by: Ville Syrjälä
Signed-off-by: Abhay Kumar
---
drivers/gpu/drm/i915/intel_cdclk.c | 14 ++
drivers/gpu/drm/i915/intel_drv.h| 5 +
drivers/gpu/drm/i915/intel_runtime_pm.c | 34 +
3 files changed, 53 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
b/drivers/gpu/drm/i915/intel_cdclk.c
index 0f0aea900ceb..6557f1e9cf9e 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1356,6 +1356,7 @@ static void bxt_set_cdclk(struct drm_i915_private
*dev_priv,
{
int cdclk = cdclk_state->cdclk;
int vco = cdclk_state->vco;
+ bool enable_pw2 = false;
u32 val, divider;
int ret;
@@ -1381,6 +1382,14 @@ static void bxt_set_cdclk(struct drm_i915_private
*dev_priv,
}
/*
+* On GLK HDA apparently gets confused if
+* cdclk is changed while PW2 is on
+*/
+ if (IS_GEMINILAKE(dev_priv))
+ enable_pw2 = intel_display_power_toggle_start(dev_priv,
+ SKL_DISP_PW_2);
+
+ /*
* Inform power controller of upcoming frequency change. BSpec
* requires us to wait up to 150usec, but that leads to timeouts;
* the 2ms used here is based on experiment.
@@ -1437,6 +1446,11 @@ static void bxt_set_cdclk(struct drm_i915_private
*dev_priv,
}
intel_update_cdclk(dev_priv);
+
+ if (IS_GEMINILAKE(dev_priv))
+ intel_display_power_toggle_end(dev_priv,
+ SKL_DISP_PW_2,
+ enable_pw2);
}
static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0da17ad056ec..c4fc107ad8cd 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1950,6 +1950,11 @@ bool intel_display_power_get_if_enabled(struct
drm_i915_private *dev_priv,
enum intel_display_power_domain domain);
void intel_display_power_put(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain);
+bool intel_display_power_toggle_start(struct drm_i915_private *dev_priv,
+ enum i915_power_well_id power_well_id);
+void intel_display_power_toggle_end(struct drm_i915_private *dev_priv,
+ enum i915_power_well_id power_well_id,
+ bool enable);
void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
u8 req_slices);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 53a6eaa9671a..86a4b788e224 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2809,6 +2809,40 @@ static void skl_display_core_uninit(struct
drm_i915_private *dev_priv)
usleep_range(10, 30); /* 10 us delay per Bspec */
}
+bool intel_display_power_toggle_start(struct drm_i915_private *dev_priv,
+ enum i915_power_well_id power_well_id)
+{
+ struct i915_power_domains *power_domains = _priv->power_domains;
+ struct i915_power_well *well = lookup_power_well(dev_priv,
power_well_id);
+ bool was_enabled;
+
+ mutex_lock(_domains->lock);
+
+ was_enabled =
[Intel-gfx] [PATCH v4 1/2] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
From: Ville Syrjälä
CDCLK has to be at least twice the BLCK regardless of audio. Audio
driver has to probe using this hook and increase the clock even in
absence of any display.
v2: Use atomic refcount for get_power, put_power so that we can
call each once(Abhay).
v3: Reset power well 2 to avoid any transaction on iDisp link
during cdclk change(Abhay).
v4: Remove Power well 2 reset workaround(Ville).
Signed-off-by: Ville Syrjälä
Signed-off-by: Abhay Kumar
---
drivers/gpu/drm/i915/i915_drv.h | 3 ++
drivers/gpu/drm/i915/i915_reg.h | 4 +++
drivers/gpu/drm/i915/intel_audio.c | 67 +---
drivers/gpu/drm/i915/intel_cdclk.c | 29 +---
drivers/gpu/drm/i915/intel_display.c | 7 +++-
drivers/gpu/drm/i915/intel_drv.h | 2 ++
6 files changed, 87 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6104d7115054..a4a386a5db69 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1702,6 +1702,7 @@ struct drm_i915_private {
unsigned int hpll_freq;
unsigned int fdi_pll_freq;
unsigned int czclk_freq;
+ u32 get_put_refcount;
struct {
/*
@@ -1719,6 +1720,8 @@ struct drm_i915_private {
struct intel_cdclk_state actual;
/* The current hardware cdclk state */
struct intel_cdclk_state hw;
+
+ int force_min_cdclk;
} cdclk;
/**
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 987def26ce82..cef770184245 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8869,6 +8869,10 @@ enum skl_power_gate {
* SKL Clocks
*/
+/* Power well 2 */
+#define POWER_WELL_2 _MMIO(0x45404)
+#define POWER_WELL_2_REQUEST (1<<31)
+
/* CDCLK_CTL */
#define CDCLK_CTL _MMIO(0x46000)
#define CDCLK_FREQ_SEL_MASK (3 << 26)
diff --git a/drivers/gpu/drm/i915/intel_audio.c
b/drivers/gpu/drm/i915/intel_audio.c
index 3ea566f99450..ca8f04c7cbb3 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -618,7 +618,6 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
if (!connector->eld[0])
return;
-
DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
connector->base.id,
connector->name,
@@ -713,14 +712,74 @@ void intel_init_audio_hooks(struct drm_i915_private
*dev_priv)
}
}
+static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
+ bool enable)
+{
+ struct drm_modeset_acquire_ctx ctx;
+ struct drm_atomic_state *state;
+ int ret;
+
+ drm_modeset_acquire_init(, 0);
+ state = drm_atomic_state_alloc(_priv->drm);
+ if (WARN_ON(!state))
+ return;
+
+ state->acquire_ctx =
+
+retry:
+ to_intel_atomic_state(state)->modeset = true;
+ to_intel_atomic_state(state)->cdclk.force_min_cdclk =
+ enable ? 2 * 96000 : 0;
+
+ /*
+* Protects dev_priv->cdclk.force_min_cdclk
+* Need to lock this here in case we have no active pipes
+* and thus wouldn't lock it during the commit otherwise.
+*/
+ ret = drm_modeset_lock(_priv->drm.mode_config.connection_mutex,
);
+ if (!ret)
+ ret = drm_atomic_commit(state);
+
+ if (ret == -EDEADLK) {
+ drm_atomic_state_clear(state);
+ drm_modeset_backoff();
+ goto retry;
+ }
+
+ WARN_ON(ret);
+
+ drm_atomic_state_put(state);
+
+ drm_modeset_drop_locks();
+ drm_modeset_acquire_fini();
+}
+
static void i915_audio_component_get_power(struct device *kdev)
{
- intel_display_power_get(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
+ struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
+
+ dev_priv->get_put_refcount++;
+
+ /* Force cdclk to 2*BCLK during first time get power call */
+ if (dev_priv->get_put_refcount == 1)
+ if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
+ glk_force_audio_cdclk(dev_priv, true);
+
+ intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
}
static void i915_audio_component_put_power(struct device *kdev)
{
- intel_display_power_put(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
+ struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
+
+ dev_priv->get_put_refcount--;
+
+ /* Force required cdclk during last time put power call */
+ if (dev_priv->get_put_refcount == 0)
+ if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
+ glk_force_audio_cdclk(dev_priv, false);
+
+ intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
}
[Intel-gfx] [PATCH v4 0/2] Enable Dynamic cdclk and HDA together on GLK
Patches needed to change cdclk to 2*BCLK before accessing HDA Codec. Ville Syrjälä (2): drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled drm/i915: Shut off PW2 when changing cdclk on glk drivers/gpu/drm/i915/i915_drv.h | 3 ++ drivers/gpu/drm/i915/i915_reg.h | 4 ++ drivers/gpu/drm/i915/intel_audio.c | 67 +++-- drivers/gpu/drm/i915/intel_cdclk.c | 43 +++-- drivers/gpu/drm/i915/intel_display.c| 7 +++- drivers/gpu/drm/i915/intel_drv.h| 7 drivers/gpu/drm/i915/intel_runtime_pm.c | 34 + 7 files changed, 140 insertions(+), 25 deletions(-) -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/2] drm/i915/icl: Add allowed DP rates for Icelake
On Tue, Jun 12, 2018 at 11:46:08AM +0300, Jani Nikula wrote: > On Mon, 11 Jun 2018, Paulo Zanoni wrote: > > Em Seg, 2018-06-11 às 22:35 +, Patchwork escreveu: > >> == Series Details == > >> > >> Series: series starting with [CI,1/2] drm/i915/icl: Add allowed DP > >> rates for Icelake > >> URL : https://patchwork.freedesktop.org/series/44595/ > >> State : warning > >> > >> == Summary == > >> > >> $ dim checkpatch origin/drm-tip > >> e6e6b2f7af58 drm/i915/icl: Add allowed DP rates for Icelake > >> 3fe43cb729fe drm/i915/dp: Add support for HBR3 and TPS4 during link > >> training > >> -:26: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) > >> #26: FILE: drivers/gpu/drm/i915/i915_reg.h:8694: > >> +#define DP_TP_CTL_LINK_TRAIN_PAT4(5<<8) > > > > Dear maintainers, > > > > I get this type of error way too often. What's the most desirable thing > > here? > > > > 1 - Make it "(5 << 8)" so checkpatch doesn't complain, which will leave > > the coding style inconsistent with the surrounding lines. > > I don't like the inconsistency. me neither... > > > 2 - Drive-by fix all the bits around it so everybody in the same > > definition has nice spaces, 2.a: in the same patch, 2.b: in a separate > > patch. > > Fine by me. Both a and b. I was kind of hoping this would have happened > more. > > > 3 - Just ignore the checkpatch message, push code as-is. > > Also fine by me. what I'm currently doing... > > > 4 - Blacklist this check from checkpatch. > > Unfortunately the SPACING class in checkpatch would silence much, much > more than just this specific thing, so it would be a net negative. Let's keep the style we want there even if this cause warnings while we haven't finished the standardization. > > > 5 - Submit a separate patch fixing all the spacing errors on i915_reg.h > > once and for all. Live happily ever after. > > It would be annoying for a while with conflicts, but I'd be fine. Not > sure if it would be better to do it in some arbitrary chunks rather than > mass change. I believe I prefer one mass commit. So we convert once for all and cause rebase conflict on internal branch only once. So we solve all at one and be happy... > > > 6 - Submit a separate patch converting everything to BIT() on > > i915_reg.h. > > Same as above. Do we really want BIT everywhere?! Thanks, Rodrigo. > > BR, > Jani. > > -- > Jani Nikula, Intel Open Source Graphics Center > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for Problems in intel_panel_fitter.1 (rev2)
== Series Details == Series: Problems in intel_panel_fitter.1 (rev2) URL : https://patchwork.freedesktop.org/series/3953/ State : failure == Summary == Applying: Problems in intel_panel_fitter.1 error: sha1 information is lacking or useless (intel_panel_fitter.1). error: could not build fake ancestor Patch failed at 0001 Problems in intel_panel_fitter.1 Use 'git am --show-current-patch' to see the failed patch When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] Problems in intel_panel_fitter.1
This is automatically generated email about markup problems in a man page for which you appear to be responsible. If you are not the right person or list, please tell me so I can correct my database. See http://catb.org/~esr/doclifter/bugs.html for details on how and why these patches were generated. Feel free to email me with any questions. Note: These patches do not change the modification date of any manual page. You may wish to do that by hand. I apologize if this message seems spammy or impersonal. The volume of markup bugs I am tracking is over five hundred - there is no real alternative to generating bugmail from a database and template. -- Eric S. Raymond Problems with intel_panel_fitter.1: My translator trips over a useless command in list markup. --- intel_panel_fitter.1-unpatched 2013-05-25 10:53:50.568627955 -0400 +++ intel_panel_fitter.12013-05-25 10:54:08.112627627 -0400 @@ -30,7 +30,6 @@ .TP .B -h prints the help message. -.SS .SH EXAMPLES .TP ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/3] drm: Print bad user modes
On 2018-06-11 03:34 PM, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Print out the modeline when we reject a bad user mode. Avoids having to
> guess why it was rejected.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Harry Wentland
Harry
> ---
> drivers/gpu/drm/drm_atomic.c| 20 +---
> drivers/gpu/drm/drm_crtc.c | 4 +++-
> drivers/gpu/drm/drm_crtc_internal.h | 3 +++
> drivers/gpu/drm/drm_modes.c | 2 +-
> 4 files changed, 24 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
> index d7de83a6c1c2..5fe5e06062a9 100644
> --- a/drivers/gpu/drm/drm_atomic.c
> +++ b/drivers/gpu/drm/drm_atomic.c
> @@ -400,10 +400,24 @@ int drm_atomic_set_mode_prop_for_crtc(struct
> drm_crtc_state *state,
> memset(>mode, 0, sizeof(state->mode));
>
> if (blob) {
> - if (blob->length != sizeof(struct drm_mode_modeinfo) ||
> - drm_mode_convert_umode(state->crtc->dev, >mode,
> -blob->data))
> + int ret;
> +
> + if (blob->length != sizeof(struct drm_mode_modeinfo)) {
> + DRM_DEBUG_ATOMIC("[CRTC:%d:%s] bad mode blob length:
> %zu\n",
> + crtc->base.id, crtc->name,
> + blob->length);
> + return -EINVAL;
> + }
> +
> + ret = drm_mode_convert_umode(crtc->dev,
> + >mode, blob->data);
> + if (ret) {
> + DRM_DEBUG_ATOMIC("[CRTC:%d:%s] invalid mode (ret=%d,
> status=%s):\n",
> + crtc->base.id, crtc->name,
> + ret,
> drm_get_mode_status_name(state->mode.status));
> + drm_mode_debug_printmodeline(>mode);
> return -EINVAL;
> + }
>
> state->mode_blob = drm_property_blob_get(blob);
> state->enable = true;
> diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
> index 53828fc8d911..163d82ac7d76 100644
> --- a/drivers/gpu/drm/drm_crtc.c
> +++ b/drivers/gpu/drm/drm_crtc.c
> @@ -649,7 +649,9 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data,
>
> ret = drm_mode_convert_umode(dev, mode, _req->mode);
> if (ret) {
> - DRM_DEBUG_KMS("Invalid mode\n");
> + DRM_DEBUG_KMS("Invalid mode (ret=%d, status=%s)\n",
> + ret,
> drm_get_mode_status_name(mode->status));
> + drm_mode_debug_printmodeline(mode);
> goto out;
> }
>
> diff --git a/drivers/gpu/drm/drm_crtc_internal.h
> b/drivers/gpu/drm/drm_crtc_internal.h
> index 5d307b23a4e6..34499800932a 100644
> --- a/drivers/gpu/drm/drm_crtc_internal.h
> +++ b/drivers/gpu/drm/drm_crtc_internal.h
> @@ -56,6 +56,9 @@ int drm_mode_setcrtc(struct drm_device *dev,
> int drm_modeset_register_all(struct drm_device *dev);
> void drm_modeset_unregister_all(struct drm_device *dev);
>
> +/* drm_modes.c */
> +const char *drm_get_mode_status_name(enum drm_mode_status status);
> +
> /* IOCTLs */
> int drm_mode_getresources(struct drm_device *dev,
> void *data, struct drm_file *file_priv);
> diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
> index c78ca0e84ffd..7f552d5fa88e 100644
> --- a/drivers/gpu/drm/drm_modes.c
> +++ b/drivers/gpu/drm/drm_modes.c
> @@ -1257,7 +1257,7 @@ static const char * const drm_mode_status_names[] = {
>
> #undef MODE_STATUS
>
> -static const char *drm_get_mode_status_name(enum drm_mode_status status)
> +const char *drm_get_mode_status_name(enum drm_mode_status status)
> {
> int index = status + 3;
>
>
___
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Re: [Intel-gfx] [PATCH 1/3] drm/atomic: Improve debug messages
On 2018-06-11 03:34 PM, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Print the id/name of the object we're dealing with. Makes it easier to
> figure out what's going on. Also toss in a few extra debug prints that
> might be useful.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Harry Wentland
Harry
> ---
> drivers/gpu/drm/drm_atomic.c | 88
> ++--
> 1 file changed, 61 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
> index ee4b43b9404e..d7de83a6c1c2 100644
> --- a/drivers/gpu/drm/drm_atomic.c
> +++ b/drivers/gpu/drm/drm_atomic.c
> @@ -339,6 +339,7 @@ static s32 __user *get_out_fence_for_crtc(struct
> drm_atomic_state *state,
> int drm_atomic_set_mode_for_crtc(struct drm_crtc_state *state,
>const struct drm_display_mode *mode)
> {
> + struct drm_crtc *crtc = state->crtc;
> struct drm_mode_modeinfo umode;
>
> /* Early return for no change. */
> @@ -359,13 +360,13 @@ int drm_atomic_set_mode_for_crtc(struct drm_crtc_state
> *state,
>
> drm_mode_copy(>mode, mode);
> state->enable = true;
> - DRM_DEBUG_ATOMIC("Set [MODE:%s] for CRTC state %p\n",
> - mode->name, state);
> + DRM_DEBUG_ATOMIC("Set [MODE:%s] for [CRTC:%d:%s] state %p\n",
> + mode->name, crtc->base.id, crtc->name, state);
> } else {
> memset(>mode, 0, sizeof(state->mode));
> state->enable = false;
> - DRM_DEBUG_ATOMIC("Set [NOMODE] for CRTC state %p\n",
> - state);
> + DRM_DEBUG_ATOMIC("Set [NOMODE] for [CRTC:%d:%s] state %p\n",
> + crtc->base.id, crtc->name, state);
> }
>
> return 0;
> @@ -388,6 +389,8 @@ EXPORT_SYMBOL(drm_atomic_set_mode_for_crtc);
> int drm_atomic_set_mode_prop_for_crtc(struct drm_crtc_state *state,
>struct drm_property_blob *blob)
> {
> + struct drm_crtc *crtc = state->crtc;
> +
> if (blob == state->mode_blob)
> return 0;
>
> @@ -404,12 +407,13 @@ int drm_atomic_set_mode_prop_for_crtc(struct
> drm_crtc_state *state,
>
> state->mode_blob = drm_property_blob_get(blob);
> state->enable = true;
> - DRM_DEBUG_ATOMIC("Set [MODE:%s] for CRTC state %p\n",
> - state->mode.name, state);
> + DRM_DEBUG_ATOMIC("Set [MODE:%s] for [CRTC:%d:%s] state %p\n",
> + state->mode.name, crtc->base.id, crtc->name,
> + state);
> } else {
> state->enable = false;
> - DRM_DEBUG_ATOMIC("Set [NOMODE] for CRTC state %p\n",
> - state);
> + DRM_DEBUG_ATOMIC("Set [NOMODE] for [CRTC:%d:%s] state %p\n",
> + crtc->base.id, crtc->name, state);
> }
>
> return 0;
> @@ -539,10 +543,14 @@ int drm_atomic_crtc_set_property(struct drm_crtc *crtc,
> return -EFAULT;
>
> set_out_fence_for_crtc(state->state, crtc, fence_ptr);
> - } else if (crtc->funcs->atomic_set_property)
> + } else if (crtc->funcs->atomic_set_property) {
> return crtc->funcs->atomic_set_property(crtc, state, property,
> val);
> - else
> + } else {
> + DRM_DEBUG_ATOMIC("[CRTC:%d:%s] unknown property
> [PROP:%d:%s]]\n",
> + crtc->base.id, crtc->name,
> + property->base.id, property->name);
> return -EINVAL;
> + }
>
> return 0;
> }
> @@ -799,8 +807,11 @@ static int drm_atomic_plane_set_property(struct
> drm_plane *plane,
> } else if (property == plane->alpha_property) {
> state->alpha = val;
> } else if (property == plane->rotation_property) {
> - if (!is_power_of_2(val & DRM_MODE_ROTATE_MASK))
> + if (!is_power_of_2(val & DRM_MODE_ROTATE_MASK)) {
> + DRM_DEBUG_ATOMIC("[PLANE:%d:%s] bad rotation bitmask:
> 0x%llx\n",
> + plane->base.id, plane->name, val);
> return -EINVAL;
> + }
> state->rotation = val;
> } else if (property == plane->zpos_property) {
> state->zpos = val;
> @@ -812,6 +823,9 @@ static int drm_atomic_plane_set_property(struct drm_plane
> *plane,
> return plane->funcs->atomic_set_property(plane, state,
> property, val);
> } else {
> + DRM_DEBUG_ATOMIC("[PLANE:%d:%s] unknown property
> [PROP:%d:%s]]\n",
> + plane->base.id, plane->name,
> + property->base.id, property->name);
> return -EINVAL;
> }
>
Re: [Intel-gfx] [CI 1/2] drm/i915/icl: Add allowed DP rates for Icelake
On Tue, Jun 12, 2018 at 03:15:53PM +0300, Ville Syrjälä wrote:
> On Mon, Jun 11, 2018 at 03:26:54PM -0700, Paulo Zanoni wrote:
> > From: Manasi Navare
> >
> > For ICL, on Combo PHY the allowed max rates are:
> > - HBR3 8.1 eDP (DDIA)
> > - HBR2 5.4 DisplayPort (DDIB)
> > and for MG PHY/TC DDI Ports allowed DP rates are:
> > - HBR3 8.1 DisplayPort (DP alternate mode, DP over TBT,
> > - DP on legacy connector - DDIC/D/E/F)
> >
> > Cc: Rodrigo Vivi
> > Cc: Jani Nikula
> > Reviewed-by: James Ausmus
> > Signed-off-by: Manasi Navare
> > Signed-off-by: James Ausmus
> > [Paulo: bikeshed to keep future platforms on "else".]
> > Signed-off-by: Paulo Zanoni
> > ---
> > drivers/gpu/drm/i915/intel_dp.c | 21 +++--
> > 1 file changed, 19 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 37b9f62aeb6e..8371159cc192 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -256,6 +256,20 @@ static int cnl_max_source_rate(struct intel_dp
> > *intel_dp)
> > return 81;
> > }
> >
> > +static int icl_max_source_rate(struct intel_dp *intel_dp)
> > +{
> > + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> > + enum port port = dig_port->base.port;
> > +
> > + /* On Combo PHY port A max speed is HBR3 for all Vccio voltages
> > +* and on Combo PHY Port B the maximum supported is HBR2.
> > +*/
>
> And what about the other ports? If port B is the only
> exception why are we even discussing port A specifically
> here?
All the MG PHY ports (C/D/E/F) support a max of HBR3 that is 81 but for
Combo PHY ports which is Port A or B, HBR3 only supported for Port A
but for Port B it is max of HBR2 which is 54 hence the comment for Combo PHY
ports and if port B then just return HBR2
Manasi
>
> > + if (port == PORT_B)
> > + return 54;
> > +
> > + return 81;
> > +}
> > +
> > static void
> > intel_dp_set_source_rates(struct intel_dp *intel_dp)
> > {
> > @@ -285,10 +299,13 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
> > /* This should only be done once */
> > WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
> >
> > - if (IS_CANNONLAKE(dev_priv)) {
> > + if (INTEL_GEN(dev_priv) >= 10) {
> > source_rates = cnl_rates;
> > size = ARRAY_SIZE(cnl_rates);
> > - max_rate = cnl_max_source_rate(intel_dp);
> > + if (INTEL_GEN(dev_priv) == 10)
> > + max_rate = cnl_max_source_rate(intel_dp);
> > + else
> > + max_rate = icl_max_source_rate(intel_dp);
> > } else if (IS_GEN9_LP(dev_priv)) {
> > source_rates = bxt_rates;
> > size = ARRAY_SIZE(bxt_rates);
> > --
> > 2.14.4
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled (rev3)
HI, > -Original Message- > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf > Of Patchwork > Sent: tiistai 12. kesäkuuta 2018 11.38 > To: Kumar, Abhay > Cc: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Force 2*96 MHz cdclk > on > glk/cnl when audio power is enabled (rev3) > > == Series Details == > > Series: drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is > enabled (rev3) > URL : https://patchwork.freedesktop.org/series/42459/ > State : success > > == Summary == > > = CI Bug Log - changes from CI_DRM_4304_full -> Patchwork_9268_full = > > == Summary - WARNING == > > Minor unknown changes coming with Patchwork_9268_full need to be > verified > manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_9268_full, please notify your bug team to allow > them > to document this new failure mode, which will reduce false positives in CI. > > > > == Possible new issues == > > Here are the unknown changes that may have been introduced in > Patchwork_9268_full: > > === IGT changes === > > Warnings > > igt@gem_exec_schedule@deep-bsd2: > shard-kbl: PASS -> SKIP > > igt@gem_exec_schedule@deep-vebox: > shard-kbl: SKIP -> PASS > > > == Known issues == > > Here are the changes found in Patchwork_9268_full that come from known > issues: > > === IGT changes === > > Issues hit > > igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: > shard-hsw: PASS -> FAIL (fdo#102887) > > igt@kms_setmode@basic: > shard-kbl: PASS -> FAIL (fdo#99912) > > > Possible fixes > > igt@drv_selftest@live_gtt: > shard-kbl: FAIL (fdo#105347) -> PASS > > igt@drv_suspend@shrink: > shard-hsw: INCOMPLETE (fdo#103540) -> PASS > > igt@kms_rotation_crc@sprite-rotation-180: > shard-hsw: FAIL (fdo#103925, fdo#104724) -> PASS > > > fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887 > fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540 > fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925 > fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 > fdo#105347 https://bugs.freedesktop.org/show_bug.cgi?id=105347 > fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 > > > == Participating hosts (5 -> 4) == > > Missing(1): shard-glk There glk's are but some issues: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9268/shard-glk1/ https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9268/shard-glk2/run2.log etc... Worth to investigate... + Tomi too. > > > == Build changes == > > * Linux: CI_DRM_4304 -> Patchwork_9268 > > CI_DRM_4304: 2313a1dc588ef63d9650ccbaaf576bc4b47dc255 @ > git://anongit.freedesktop.org/gfx-ci/linux > IGT_4515: a0f2d23b7d3d4226a0a7637a9240bfa86f08c1d3 @ > git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > Patchwork_9268: 7e66d7400ee9f80e00633e6cfdecc354dda8e049 @ > git://anongit.freedesktop.org/gfx-ci/linux > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ > git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm- > tip/Patchwork_9268/shards.html > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gtt: Only keep gen6 page directories pinned while active
== Series Details == Series: drm/i915/gtt: Only keep gen6 page directories pinned while active URL : https://patchwork.freedesktop.org/series/44649/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4308 -> Patchwork_9278 = == Summary - WARNING == Minor unknown changes coming with Patchwork_9278 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9278, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/44649/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9278: === IGT changes === Warnings igt@gem_exec_gttfill@basic: fi-pnv-d510:SKIP -> PASS == Known issues == Here are the changes found in Patchwork_9278 that come from known issues: === IGT changes === Issues hit igt@gem_exec_suspend@basic-s4-devices: fi-hsw-4770:PASS -> FAIL (fdo#105900) fi-hsw-4770r: PASS -> FAIL (fdo#105900) Possible fixes igt@drv_module_reload@basic-reload: fi-ilk-650: DMESG-WARN (fdo#106387) -> PASS igt@kms_flip@basic-flip-vs-dpms: fi-glk-j4005: DMESG-WARN (fdo#106000) -> PASS +1 igt@kms_flip@basic-flip-vs-wf_vblank: fi-glk-j4005: FAIL (fdo#100368) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-c: fi-glk-j4005: DMESG-WARN (fdo#105719) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#105719 https://bugs.freedesktop.org/show_bug.cgi?id=105719 fdo#105900 https://bugs.freedesktop.org/show_bug.cgi?id=105900 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106387 https://bugs.freedesktop.org/show_bug.cgi?id=106387 == Participating hosts (43 -> 38) == Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-skl-6700hq == Build changes == * Linux: CI_DRM_4308 -> Patchwork_9278 CI_DRM_4308: 355cdcfec85bdd8bea927357789f53e4dec4f7b2 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4517: e94ce40798e35d2e3c4494f50b617908066bbf8b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9278: e8c416abf96f31a6541d5a052849db26eee8ef8b @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == e8c416abf96f drm/i915/gtt: Only keep gen6 page directories pinned while active == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9278/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: add support for perf configuration queries (rev2)
== Series Details == Series: drm/i915: add support for perf configuration queries (rev2) URL : https://patchwork.freedesktop.org/series/44290/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4308 -> Patchwork_9277 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/44290/revisions/2/mbox/ == Known issues == Here are the changes found in Patchwork_9277 that come from known issues: === IGT changes === Issues hit igt@gem_ctx_create@basic-files: fi-glk-j4005: PASS -> DMESG-WARN (fdo#105719) igt@kms_busy@basic-flip-a: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106097) igt@kms_flip@basic-flip-vs-modeset: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106097, fdo#106000) igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: fi-cnl-psr: PASS -> FAIL (fdo#103481) Possible fixes igt@drv_module_reload@basic-reload: fi-ilk-650: DMESG-WARN (fdo#106387) -> PASS igt@kms_flip@basic-flip-vs-dpms: fi-glk-j4005: DMESG-WARN (fdo#106000) -> PASS +1 igt@kms_flip@basic-flip-vs-wf_vblank: fi-glk-j4005: FAIL (fdo#100368) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-c: fi-glk-j4005: DMESG-WARN (fdo#105719) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481 fdo#105719 https://bugs.freedesktop.org/show_bug.cgi?id=105719 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097 fdo#106387 https://bugs.freedesktop.org/show_bug.cgi?id=106387 == Participating hosts (43 -> 38) == Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-skl-6700hq == Build changes == * Linux: CI_DRM_4308 -> Patchwork_9277 CI_DRM_4308: 355cdcfec85bdd8bea927357789f53e4dec4f7b2 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4517: e94ce40798e35d2e3c4494f50b617908066bbf8b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9277: 31b5046df85fcf24ed17b9d4d15e7c1164f9c324 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 31b5046df85f drm/i915: add support for perf configuration queries == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9277/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: add support for perf configuration queries (rev2)
== Series Details == Series: drm/i915: add support for perf configuration queries (rev2) URL : https://patchwork.freedesktop.org/series/44290/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: add support for perf configuration queries -drivers/gpu/drm/i915/selftests/../i915_drv.h:3680:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3686:16: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for tests/i915-query: new tests for listing perf configurations
== Series Details == Series: tests/i915-query: new tests for listing perf configurations URL : https://patchwork.freedesktop.org/series/44644/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4307 -> IGTPW_1451 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/44644/revisions/1/mbox/ == Known issues == Here are the changes found in IGTPW_1451 that come from known issues: === IGT changes === Issues hit igt@gem_exec_suspend@basic-s3: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106097) igt@gem_exec_suspend@basic-s4-devices: fi-hsw-peppy: PASS -> FAIL (fdo#105900) igt@prime_vgem@basic-fence-flip: fi-ilk-650: PASS -> FAIL (fdo#104008) Possible fixes igt@debugfs_test@read_all_entries: fi-snb-2520m: INCOMPLETE (fdo#103713) -> PASS igt@gem_ctx_create@basic-files: fi-glk-j4005: DMESG-WARN (fdo#106000) -> PASS igt@kms_chamelium@dp-edid-read: fi-kbl-7500u: FAIL (fdo#103841) -> PASS igt@kms_pipe_crc_basic@hang-read-crc-pipe-a: fi-skl-guc: FAIL (fdo#104724, fdo#103191) -> PASS fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841 fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 fdo#105900 https://bugs.freedesktop.org/show_bug.cgi?id=105900 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097 == Participating hosts (42 -> 38) == Missing(4): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-skl-6700hq == Build changes == * IGT: IGT_4516 -> IGTPW_1451 CI_DRM_4307: 0cf6f8f74cad691364d738d1607bc45945f3a5f9 @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_1451: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1451/ IGT_4516: 95bfb2902473b9f4e644c3eb831fdf110d87ed4f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools == Testlist changes == +igt@i915_query@query-perf-configs +igt@i915_query@query-perf-config-data-invalid +igt@i915_query@query-perf-config-list-invalid == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1451/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI] drm/i915/gtt: Only keep gen6 page directories pinned while active
In order to be able to evict the gen6 ppgtt, we have to unpin it at some
point. We can simply use our context activity tracking to know when the
ppgtt is no longer in use by hardware, and so only keep it pinned while
being used a request.
For the kernel_context (and thus aliasing_ppgtt), it remains pinned at
all times, as the kernel_context itself is pinned at all times.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 36 ++---
drivers/gpu/drm/i915/i915_gem_gtt.h | 5
drivers/gpu/drm/i915/intel_ringbuffer.c | 28 +++
3 files changed, 54 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index c6949da3423f..317f27a9d78e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1912,7 +1912,6 @@ static void gen6_ppgtt_cleanup(struct i915_address_space
*vm)
{
struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(i915_vm_to_ppgtt(vm));
- i915_vma_unpin(ppgtt->vma);
i915_vma_destroy(ppgtt->vma);
gen6_ppgtt_free_pd(ppgtt);
@@ -1998,10 +1997,19 @@ static struct i915_vma *pd_vma_create(struct
gen6_hw_ppgtt *ppgtt, int size)
return vma;
}
-static int gen6_ppgtt_pin(struct i915_hw_ppgtt *base)
+int gen6_ppgtt_pin(struct i915_hw_ppgtt *base)
{
struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(base);
+ /*
+* Workaround the limited maximum vma->pin_count and the aliasing_ppgtt
+* which will be pinned into every active context.
+* (When vma->pin_count becomes atomic, I expect we will naturally
+* need a larger, unpacked, type and kill this redundancy.)
+*/
+ if (ppgtt->pin_count++)
+ return 0;
+
/*
* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
* allocator works in address space sizes, so it's multiplied by page
@@ -2012,6 +2020,17 @@ static int gen6_ppgtt_pin(struct i915_hw_ppgtt *base)
PIN_GLOBAL | PIN_HIGH);
}
+void gen6_ppgtt_unpin(struct i915_hw_ppgtt *base)
+{
+ struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(base);
+
+ GEM_BUG_ON(!ppgtt->pin_count);
+ if (--ppgtt->pin_count)
+ return;
+
+ i915_vma_unpin(ppgtt->vma);
+}
+
static struct i915_hw_ppgtt *gen6_ppgtt_create(struct drm_i915_private *i915)
{
struct i915_ggtt * const ggtt = >ggtt;
@@ -2053,21 +2072,8 @@ static struct i915_hw_ppgtt *gen6_ppgtt_create(struct
drm_i915_private *i915)
if (err)
goto err_vma;
- err = gen6_ppgtt_pin(>base);
- if (err)
- goto err_pd;
-
- DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
-ppgtt->vma->node.size >> 20,
-ppgtt->vma->node.start / PAGE_SIZE);
-
- DRM_DEBUG_DRIVER("Adding PPGTT at offset %x\n",
-ppgtt->base.pd.base.ggtt_offset << 10);
-
return >base;
-err_pd:
- gen6_ppgtt_free_pd(ppgtt);
err_vma:
i915_vma_destroy(ppgtt->vma);
err_scratch:
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 6e9acd99ecc6..d7b7b4afe060 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -412,6 +412,8 @@ struct gen6_hw_ppgtt {
struct i915_vma *vma;
gen6_pte_t __iomem *pd_addr;
+
+ unsigned int pin_count;
};
#define __to_gen6_ppgtt(base) container_of(base, struct gen6_hw_ppgtt, base)
@@ -625,6 +627,9 @@ static inline void i915_ppgtt_put(struct i915_hw_ppgtt
*ppgtt)
kref_put(>ref, i915_ppgtt_release);
}
+int gen6_ppgtt_pin(struct i915_hw_ppgtt *base);
+void gen6_ppgtt_unpin(struct i915_hw_ppgtt *base);
+
void i915_check_and_clear_faults(struct drm_i915_private *dev_priv);
void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv);
void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index dda671e0a680..ef3c76425843 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1181,6 +1181,27 @@ static void intel_ring_context_destroy(struct
intel_context *ce)
__i915_gem_object_release_unless_active(ce->state->obj);
}
+static int __context_pin_ppgtt(struct i915_gem_context *ctx)
+{
+ struct i915_hw_ppgtt *ppgtt;
+ int err = 0;
+
+ ppgtt = ctx->ppgtt ?: ctx->i915->mm.aliasing_ppgtt;
+ if (ppgtt)
+ err = gen6_ppgtt_pin(ppgtt);
+
+ return err;
+}
+
+static void __context_unpin_ppgtt(struct i915_gem_context *ctx)
+{
+ struct i915_hw_ppgtt *ppgtt;
+
+ ppgtt = ctx->ppgtt ?: ctx->i915->mm.aliasing_ppgtt;
+ if
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gtt: Make gen6 page directories evictable
== Series Details == Series: drm/i915/gtt: Make gen6 page directories evictable URL : https://patchwork.freedesktop.org/series/44623/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4306_full -> Patchwork_9275_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9275_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9275_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9275_full: === IGT changes === Warnings igt@gem_exec_schedule@deep-bsd2: shard-kbl: SKIP -> PASS +1 igt@gem_exec_schedule@deep-render: shard-kbl: PASS -> SKIP == Known issues == Here are the changes found in Patchwork_9275_full that come from known issues: === IGT changes === Issues hit igt@drv_selftest@live_gtt: shard-kbl: PASS -> FAIL (fdo#105347) igt@drv_suspend@shrink: shard-kbl: PASS -> INCOMPLETE (fdo#106886, fdo#103665) igt@kms_flip@plain-flip-ts-check-interruptible: shard-hsw: PASS -> FAIL (fdo#100368) Possible fixes igt@drv_selftest@live_gtt: shard-glk: INCOMPLETE (k.org#198133, fdo#103359) -> PASS igt@kms_atomic_transition@1x-modeset-transitions-nonblocking: shard-glk: FAIL (fdo#105703) -> PASS igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: shard-hsw: FAIL (fdo#105189) -> PASS igt@kms_flip@flip-vs-expired-vblank-interruptible: shard-glk: FAIL (fdo#105189) -> PASS igt@kms_flip@modeset-vs-vblank-race-interruptible: shard-glk: FAIL (fdo#103060) -> PASS igt@kms_flip@plain-flip-fb-recreate: shard-glk: FAIL (fdo#100368) -> PASS igt@kms_flip_tiling@flip-x-tiled: shard-glk: FAIL (fdo#103822, fdo#104724) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 fdo#105189 https://bugs.freedesktop.org/show_bug.cgi?id=105189 fdo#105347 https://bugs.freedesktop.org/show_bug.cgi?id=105347 fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703 fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4306 -> Patchwork_9275 CI_DRM_4306: 46ac5b5698d4aea58eb440f1ec47d734762259f7 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4515: a0f2d23b7d3d4226a0a7637a9240bfa86f08c1d3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9275: 903967c3061a798c8feef2c6c73c468481f86cc9 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9275/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915: add support for perf configuration queries
Listing configurations at the moment is supported only through sysfs.
This might cause issues for applications wanting to list
configurations from a container where sysfs isn't available.
This change adds a way to query the number of configurations and their
content through the i915 query uAPI.
v2: Fix sparse warnings (Lionel)
Add support to query configuration using uuid (Lionel)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 6 +
drivers/gpu/drm/i915/i915_perf.c | 4 +
drivers/gpu/drm/i915/i915_query.c | 285 ++
include/uapi/drm/i915_drm.h | 62 ++-
4 files changed, 356 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6104d7115054..ef03fffefc11 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1945,6 +1945,12 @@ struct drm_i915_private {
*/
struct idr metrics_idr;
+ /*
+* Number of dynamic configurations, you need to hold
+* dev_priv->perf.metrics_lock to access it.
+*/
+ u32 n_metrics;
+
/*
* Lock associated with anything below within this structure
* except exclusive_stream.
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 881a992305ec..c7a3721ae93e 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3357,6 +3357,8 @@ int i915_perf_add_config_ioctl(struct drm_device *dev,
void *data,
goto sysfs_err;
}
+ dev_priv->perf.n_metrics++;
+
mutex_unlock(_priv->perf.metrics_lock);
DRM_DEBUG("Added config %s id=%i\n", oa_config->uuid, oa_config->id);
@@ -3418,6 +3420,8 @@ int i915_perf_remove_config_ioctl(struct drm_device *dev,
void *data,
idr_remove(_priv->perf.metrics_idr, *arg);
+ dev_priv->perf.n_metrics--;
+
DRM_DEBUG("Removed config %s id=%i\n", oa_config->uuid, oa_config->id);
put_oa_config(dev_priv, oa_config);
diff --git a/drivers/gpu/drm/i915/i915_query.c
b/drivers/gpu/drm/i915/i915_query.c
index 3f502eef2431..06cc34d9cb4a 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -84,9 +84,294 @@ static int query_topology_info(struct drm_i915_private
*dev_priv,
return total_length;
}
+static int can_copy_perf_config_registers_or_number(u32 user_n_regs,
+ u64 user_regs_ptr,
+ u32 kernel_n_regs)
+{
+ /*
+* We'll just put the number of registers, and won't copy the
+* register.
+*/
+ if (user_n_regs == 0)
+ return 0;
+
+ if (user_n_regs < kernel_n_regs)
+ return -EINVAL;
+
+ if (!access_ok(VERIFY_WRITE, u64_to_user_ptr(user_regs_ptr),
+ 2 * sizeof(u32) * kernel_n_regs))
+ return -EFAULT;
+
+ return 0;
+}
+
+static int copy_perf_config_registers_or_number(const struct i915_oa_reg
*kernel_regs,
+ u32 kernel_n_regs,
+ u64 user_regs_ptr,
+ u32 *user_n_regs)
+{
+ u32 r;
+
+ if (*user_n_regs == 0) {
+ *user_n_regs = kernel_n_regs;
+ return 0;
+ }
+
+ *user_n_regs = kernel_n_regs;
+
+ for (r = 0; r < kernel_n_regs; r++) {
+ u32 __user *user_reg_ptr =
+ u64_to_user_ptr(user_regs_ptr + sizeof(u32) * r * 2);
+ u32 __user *user_val_ptr =
+ u64_to_user_ptr(user_regs_ptr + sizeof(u32) * r * 2 +
+ sizeof(u32));
+ int ret;
+
+ ret = __put_user(i915_mmio_reg_offset(kernel_regs[r].addr),
+user_reg_ptr);
+ if (ret)
+ return -EFAULT;
+
+ ret = __put_user(kernel_regs[r].value, user_val_ptr);
+ if (ret)
+ return -EFAULT;
+ }
+
+ return 0;
+}
+
+static int query_perf_config_data(struct drm_i915_private *i915,
+ struct drm_i915_query_item *query_item,
+ bool use_uuid)
+{
+ struct drm_i915_query_perf_config __user *user_query_config_ptr =
+ u64_to_user_ptr(query_item->data_ptr);
+ struct drm_i915_perf_oa_config __user *user_config_ptr =
+ u64_to_user_ptr(query_item->data_ptr +
+ sizeof(struct drm_i915_query_perf_config));
+ struct drm_i915_perf_oa_config user_config;
+ struct i915_oa_config *oa_config = NULL;
+ u32 flags, total_size;
+ int ret;
+
+ if
Re: [Intel-gfx] [PATCH i-g-t v2 0/2] tests/i915-query: new tests for listing perf configurations
On 12/06/18 17:37, Lionel Landwerlin wrote: Hi, A small update to add query based on configuration uuids. Cheers, Lionel Landwerlin (2): include: bump i915 header tests/i915-query: add new tests for perf configurations queries include/drm-uapi/i915_drm.h | 56 +++- tests/i915_query.c | 608 2 files changed, 663 insertions(+), 1 deletion(-) -- 2.17.1 Oops, wrong mailing list :( ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t v2 2/2] tests/i915-query: add new tests for perf configurations queries
These new tests allow to list the available configurations and also to
query the data that makes up a configuration.
v2: Verify uuid queries (Lionel)
Signed-off-by: Lionel Landwerlin
---
tests/i915_query.c | 608 +
1 file changed, 608 insertions(+)
diff --git a/tests/i915_query.c b/tests/i915_query.c
index c7de8cbd..fe2090cf 100644
--- a/tests/i915_query.c
+++ b/tests/i915_query.c
@@ -22,6 +22,7 @@
*/
#include "igt.h"
+#include "igt_sysfs.h"
#include
@@ -477,6 +478,598 @@ test_query_topology_known_pci_ids(int fd, int devid)
free(topo_info);
}
+static bool query_perf_config_supported(int fd)
+{
+ struct drm_i915_query_item item = {
+ .query_id = DRM_I915_QUERY_PERF_CONFIG,
+ .flags = DRM_I915_QUERY_PERF_CONFIG_LIST,
+ };
+
+ return __i915_query_items(fd, , 1) == 0 && item.length > 0;
+}
+
+/*
+ * Verify that perf configuration queries for list of configurations
+ * rejects invalid parameters.
+ */
+static void test_query_perf_config_list_invalid(int fd)
+{
+ struct drm_i915_query_perf_config *query_config_ptr;
+ struct drm_i915_query_item item;
+ size_t len;
+ void *data;
+
+ /* Verify invalid flags for perf config queries */
+ memset(, 0, sizeof(item));
+ item.query_id = DRM_I915_QUERY_PERF_CONFIG;
+ item.flags = 42; /* invalid */
+ i915_query_items(fd, , 1);
+ igt_assert_eq(item.length, -EINVAL);
+
+ /*
+* A too small data length is invalid. We should have at least
+* the test config list.
+*/
+ memset(, 0, sizeof(item));
+ item.query_id = DRM_I915_QUERY_PERF_CONFIG;
+ item.flags = DRM_I915_QUERY_PERF_CONFIG_LIST;
+ item.length = sizeof(struct drm_i915_query_perf_config); /* invalid */
+ i915_query_items(fd, , 1);
+ igt_assert_eq(item.length, -EINVAL);
+
+ /* Flags on the query config data are invalid. */
+ memset(, 0, sizeof(item));
+ item.query_id = DRM_I915_QUERY_PERF_CONFIG;
+ item.flags = DRM_I915_QUERY_PERF_CONFIG_LIST;
+ item.length = 0;
+ i915_query_items(fd, , 1);
+ igt_assert(item.length > sizeof(struct drm_i915_query_perf_config));
+
+ query_config_ptr = calloc(1, item.length);
+ query_config_ptr->flags = 1; /* invalid */
+ item.data_ptr = to_user_pointer(query_config_ptr);
+ i915_query_items(fd, , 1);
+ igt_assert_eq(item.length, -EINVAL);
+ free(query_config_ptr);
+
+ /*
+* A NULL data pointer is invalid when the length is long
+* enough for i915 to copy data into the pointed memory.
+*/
+ memset(, 0, sizeof(item));
+ item.query_id = DRM_I915_QUERY_PERF_CONFIG;
+ item.flags = DRM_I915_QUERY_PERF_CONFIG_LIST;
+ item.length = 0;
+ i915_query_items(fd, , 1);
+ igt_assert(item.length > sizeof(struct drm_i915_query_perf_config));
+
+ i915_query_items(fd, , 1); /* leaves data ptr to null */
+ igt_assert_eq(item.length, -EFAULT);
+
+ /* Trying to write into read only memory will fail. */
+ memset(, 0, sizeof(item));
+ item.query_id = DRM_I915_QUERY_PERF_CONFIG;
+ item.flags = DRM_I915_QUERY_PERF_CONFIG_LIST;
+ item.length = 0;
+ i915_query_items(fd, , 1);
+ igt_assert(item.length > sizeof(struct drm_i915_query_perf_config));
+
+ len = ALIGN(item.length, 4096);
+ data = mmap(0, len, PROT_WRITE, MAP_PRIVATE | MAP_ANON, -1, 0);
+ memset(data, 0, len);
+ mprotect(data, len, PROT_READ);
+ item.data_ptr = to_user_pointer(data); /* invalid with read only data */
+ i915_query_items(fd, , 1);
+ igt_assert_eq(item.length, -EFAULT);
+
+ munmap(data, len);
+}
+
+static int query_perf_config_id_data(int fd, int length,
+struct drm_i915_query_perf_config *query)
+{
+ struct drm_i915_query_item item;
+
+ memset(, 0, sizeof(item));
+ item.query_id = DRM_I915_QUERY_PERF_CONFIG;
+ item.flags = DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID;
+ item.length = length;
+ item.data_ptr = to_user_pointer(query);
+ i915_query_items(fd, , 1);
+
+ return item.length;
+}
+
+static int query_perf_config_uuid_data(int fd, int length,
+ struct drm_i915_query_perf_config *query)
+{
+ struct drm_i915_query_item item;
+
+ memset(, 0, sizeof(item));
+ item.query_id = DRM_I915_QUERY_PERF_CONFIG;
+ item.flags = DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID;
+ item.length = length;
+ item.data_ptr = to_user_pointer(query);
+ i915_query_items(fd, , 1);
+
+ return item.length;
+}
+
+/*
+ * Verify that perf configuration queries for configuration data
+ * rejects invalid parameters.
+ */
+static void test_query_perf_config_data_invalid(int fd)
+{
+ struct {
+ struct
[Intel-gfx] [PATCH i-g-t v2 0/2] tests/i915-query: new tests for listing perf configurations
Hi, A small update to add query based on configuration uuids. Cheers, Lionel Landwerlin (2): include: bump i915 header tests/i915-query: add new tests for perf configurations queries include/drm-uapi/i915_drm.h | 56 +++- tests/i915_query.c | 608 2 files changed, 663 insertions(+), 1 deletion(-) -- 2.17.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t v2 1/2] include: bump i915 header
---
include/drm-uapi/i915_drm.h | 56 -
1 file changed, 55 insertions(+), 1 deletion(-)
diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index 16e452aa..17f56dcd 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -1620,6 +1620,7 @@ struct drm_i915_perf_oa_config {
struct drm_i915_query_item {
__u64 query_id;
#define DRM_I915_QUERY_TOPOLOGY_INFO1
+#define DRM_I915_QUERY_PERF_CONFIG 2
/*
* When set to zero by userspace, this is filled with the size of the
@@ -1646,9 +1647,18 @@ struct drm_i915_query {
__u32 num_items;
/*
-* Unused for now. Must be cleared to zero.
+* When query_id == DRM_I915_QUERY_TOPOLOGY_INFO, must be 0.
+*
+* When query_id == DRM_I915_QUERY_PERF_CONFIG, must be one of the
+* following :
+* - DRM_I915_QUERY_PERF_CONFIG_LIST
+* - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
+* - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
*/
__u32 flags;
+#define DRM_I915_QUERY_PERF_CONFIG_LIST 1
+#define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 2
+#define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID 3
/*
* This points to an array of num_items drm_i915_query_item structures.
@@ -1717,6 +1727,50 @@ struct drm_i915_query_topology_info {
__u8 data[];
};
+/*
+ * Data written by the kernel with query DRM_I915_QUERY_PERF_CONFIG.
+ */
+struct drm_i915_query_perf_config {
+ union {
+ /*
+* When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST,
i915 sets
+* this fields to the number of configurations available.
+*/
+ __u64 n_configs;
+
+ /*
+* When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA, i915 will
+* use the value in this field as configuration identifier to
+* decide what data to write into config_ptr.
+*/
+ __u64 config;
+
+ /** String formatted like "%08x-%04x-%04x-%04x-%012x" */
+ char uuid[36];
+ };
+
+ /*
+* Unused for now. Must be cleared to zero.
+*/
+ __u32 flags;
+
+ /*
+* When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 will
+* write an array of __u64 of configuration identifiers.
+*
+* When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_DATA, i915 will
+* write a struct drm_i915_perf_oa_config. If the following fields of
+* drm_i915_perf_oa_config are set not set to 0, i915 will write into
+* the associated pointers the values of submitted when the
+* configuration was created :
+*
+* - n_mux_regs
+* - n_boolean_regs
+* - n_flex_regs
+*/
+ __u8 data[];
+};
+
#if defined(__cplusplus)
}
#endif
--
2.17.1
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Re: [Intel-gfx] [PATCH v3] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
On 6/12/2018 5:13 AM, Ville Syrjälä wrote:
On Tue, Jun 12, 2018 at 12:17:41AM -0700, Abhay Kumar wrote:
From: Ville Syrjälä
CDCLK has to be at least twice the BLCK regardless of audio. Audio
driver has to probe using this hook and increase the clock even in
absence of any display.
v2: Use atomic refcount for get_power, put_power so that we can
call each once(Abhay).
v3: Reset power well 2 to avoid any transaction on iDisp link
during cdclk change(Abhay).
Signed-off-by: Ville Syrjälä
Signed-off-by: Abhay Kumar
---
drivers/gpu/drm/i915/i915_drv.h | 3 ++
drivers/gpu/drm/i915/i915_reg.h | 4 ++
drivers/gpu/drm/i915/intel_audio.c | 87 ++--
drivers/gpu/drm/i915/intel_cdclk.c | 29
drivers/gpu/drm/i915/intel_display.c | 7 ++-
drivers/gpu/drm/i915/intel_drv.h | 2 +
6 files changed, 107 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6104d7115054..a4a386a5db69 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1702,6 +1702,7 @@ struct drm_i915_private {
unsigned int hpll_freq;
unsigned int fdi_pll_freq;
unsigned int czclk_freq;
+ u32 get_put_refcount;
struct {
/*
@@ -1719,6 +1720,8 @@ struct drm_i915_private {
struct intel_cdclk_state actual;
/* The current hardware cdclk state */
struct intel_cdclk_state hw;
+
+ int force_min_cdclk;
} cdclk;
/**
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 987def26ce82..cef770184245 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8869,6 +8869,10 @@ enum skl_power_gate {
* SKL Clocks
*/
+/* Power well 2 */
+#define POWER_WELL_2 _MMIO(0x45404)
+#define POWER_WELL_2_REQUEST (1<<31)
+
/* CDCLK_CTL */
#define CDCLK_CTL _MMIO(0x46000)
#define CDCLK_FREQ_SEL_MASK (3 << 26)
diff --git a/drivers/gpu/drm/i915/intel_audio.c
b/drivers/gpu/drm/i915/intel_audio.c
index 3ea566f99450..1f5a9af13ef0 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -618,7 +618,6 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
if (!connector->eld[0])
return;
-
DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
connector->base.id,
connector->name,
@@ -713,14 +712,94 @@ void intel_init_audio_hooks(struct drm_i915_private
*dev_priv)
}
}
+static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
+ bool enable)
+{
+ struct drm_modeset_acquire_ctx ctx;
+ struct drm_atomic_state *state;
+ int ret;
+
+ drm_modeset_acquire_init(, 0);
+ state = drm_atomic_state_alloc(_priv->drm);
+ if (WARN_ON(!state))
+ return;
+
+ state->acquire_ctx =
+
+retry:
+ to_intel_atomic_state(state)->modeset = true;
+ to_intel_atomic_state(state)->cdclk.force_min_cdclk =
+ enable ? 2 * 96000 : 0;
+
+ /*
+* Protects dev_priv->cdclk.force_min_cdclk
+* Need to lock this here in case we have no active pipes
+* and thus wouldn't lock it during the commit otherwise.
+*/
+ ret = drm_modeset_lock(_priv->drm.mode_config.connection_mutex,
);
+ if (!ret)
+ ret = drm_atomic_commit(state);
+
+ if (ret == -EDEADLK) {
+ drm_atomic_state_clear(state);
+ drm_modeset_backoff();
+ goto retry;
+ }
+
+ WARN_ON(ret);
+
+ drm_atomic_state_put(state);
+
+ drm_modeset_drop_locks();
+ drm_modeset_acquire_fini();
+}
+
static void i915_audio_component_get_power(struct device *kdev)
{
- intel_display_power_get(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
+ struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
+ u32 tmp;
+
+ dev_priv->get_put_refcount++;
+
+ /* Force cdclk to 2*BCLK during first time get power call */
+ if (dev_priv->get_put_refcount == 1) {
+ if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
+
+ /*FIXME: Make sure there is no transaction
+* on iDisp link while changing cdclk
+*/
+
+ /* Turn off power well 2*/
+ tmp = I915_READ(POWER_WELL_2);
+ tmp = tmp & ~POWER_WELL_2_REQUEST;
+ I915_WRITE(POWER_WELL_2, tmp);
+ tmp = I915_READ(POWER_WELL_2);
+
+ /* Turn on power well 2*/
+ tmp = I915_READ(POWER_WELL_2);
+ tmp = tmp | POWER_WELL_2_REQUEST;
+
[Intel-gfx] [PATCH xf86-video-intel] sna/uxa: Fix colormap handling at screen depth 30. (v2)
The various clut handling functions like a setup
consistent with the x-screen color depth. Otherwise
we observe improper sampling in the gamma tables
at depth 30.
Therefore replace hard-coded bitsPerRGB = 8 by actual
bits per channel scrn->rgbBits. Also use this for call
to xf86HandleColormaps().
Tested for uxa and sna at depths 8, 16, 24 and 30 on
IvyBridge, and tested at depth 24 and 30 that xgamma
and gamma table animations work, and with measurement
equipment to make sure identity gamma ramps actually
are identity mappings at the output.
v2: Also deal with X-Server 1.19 and earlier, which as of
v1.19.6 lack a fix to color palette handling and can
not deal with depths/bpc > 24/8 bpc. On < 1.20 we skip
xf86HandleColormaps() setup at > 8 bpc. This disables
color palette handling on such servers at > 8 bpc, but
still keeps RandR gamma table handling intact.
Tested on 1.19.6 and 1.20.0 to do the right thing.
Signed-off-by: Mario Kleiner
---
src/sna/sna_driver.c | 9 ++---
src/uxa/intel_driver.c | 6 +-
2 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/src/sna/sna_driver.c b/src/sna/sna_driver.c
index 2007e354..8c79d43b 100644
--- a/src/sna/sna_driver.c
+++ b/src/sna/sna_driver.c
@@ -1152,7 +1152,7 @@ sna_screen_init(SCREEN_INIT_ARGS_DECL)
if (!miInitVisuals(, , , , ,
,
((unsigned long)1 << (scrn->bitsPerPixel - 1)),
- 8, -1))
+ scrn->rgbBits, -1))
return FALSE;
if (!miScreenInit(screen, NULL,
@@ -1223,8 +1223,11 @@ sna_screen_init(SCREEN_INIT_ARGS_DECL)
if (!miCreateDefColormap(screen))
return FALSE;
- if (sna->mode.num_real_crtc &&
- !xf86HandleColormaps(screen, 256, 8, sna_load_palette, NULL,
+ /* X-Server < 1.20 mishandles > 256 slots / > 8 bpc color maps. */
+ if (sna->mode.num_real_crtc && (scrn->rgbBits <= 8 ||
+ XORG_VERSION_CURRENT >= XORG_VERSION_NUMERIC(1,20,0,0,0)) &&
+ !xf86HandleColormaps(screen, 1 << scrn->rgbBits, scrn->rgbBits,
+sna_load_palette, NULL,
CMAP_RELOAD_ON_MODE_SWITCH |
CMAP_PALETTED_TRUECOLOR))
return FALSE;
diff --git a/src/uxa/intel_driver.c b/src/uxa/intel_driver.c
index 3703c412..77c0dc00 100644
--- a/src/uxa/intel_driver.c
+++ b/src/uxa/intel_driver.c
@@ -991,7 +991,11 @@ I830ScreenInit(SCREEN_INIT_ARGS_DECL)
if (!miCreateDefColormap(screen))
return FALSE;
- if (!xf86HandleColormaps(screen, 256, 8, I830LoadPalette, NULL,
+ /* X-Server < 1.20 mishandles > 256 slots / > 8 bpc color maps. */
+ if ((scrn->rgbBits <= 8 ||
+ XORG_VERSION_CURRENT >= XORG_VERSION_NUMERIC(1,20,0,0,0)) &&
+ !xf86HandleColormaps(screen, 1 << scrn->rgbBits, scrn->rgbBits,
+I830LoadPalette, NULL,
CMAP_RELOAD_ON_MODE_SWITCH |
CMAP_PALETTED_TRUECOLOR)) {
return FALSE;
--
2.17.1
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[Intel-gfx] Depth 30 colormap handling fixes for servers 1.20+ and < 1.20
Hi, finally here's an updated patch that for depth 30 now works on both Server 1.20 with the full colormap + gamma table handling, and for servers < 1.20 with the RandR gamma tables working fine and the colormap processing skipped. This one successfully tested on sna and uxa with both server 1.20.0 and server 1.19.6. I assume this one will be replaced by Ville's ddx+kmswork anyway soonish, but until that is done, this one keeps things at least testable without crashes and other problems. I use it with my own intel-kms 10 bit lut poc hacks for measurements and to test that Mesa's depth 30 stuff doesn't break. Thanks, -mario ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [BUG] cc5b114dcf bpf, i40e: add meta data support
My server's i40e no longer obtains an IP address on linux mainline. Bisected to the following: commit cc5b114dcf986bfd8e4c37bf65d1b7b1e5290ac6 Author: Daniel Borkmann Date: Mon May 28 11:07:20 2018 +0200 bpf, i40e: add meta data support Reverting on mainline resolves the issue. Is there something wrong with my i40e adapter, or is the patch possibly doing something wrong? Or any other information I can get to help understand why it's stopped working with this feature? An excert from "journalctl -xe" on on the failing network adapter is below. Thanks, Keith --- Jun 12 10:04:35 localhost.localdomain dhclient[2632]: DHCPDISCOVER on eno1 to 255.255.255.255 port 67 interval 7 (xid=0x3b301712) Jun 12 10:04:42 localhost.localdomain dhclient[2632]: DHCPDISCOVER on eno1 to 255.255.255.255 port 67 interval 14 (xid=0x3b301712) Jun 12 10:04:56 localhost.localdomain dhclient[2632]: DHCPDISCOVER on eno1 to 255.255.255.255 port 67 interval 21 (xid=0x3b301712) Jun 12 10:05:03 localhost.localdomain NetworkManager[2215]: [1528819503.2274] dhcp4 (eno1): request timed out Jun 12 10:05:03 localhost.localdomain NetworkManager[2215]: [1528819503.2275] dhcp4 (eno1): state changed unknown -> timeout Jun 12 10:05:03 localhost.localdomain NetworkManager[2215]: [1528819503.2440] dhcp4 (eno1): canceled DHCP transaction, DHCP client pid 2632 Jun 12 10:05:03 localhost.localdomain NetworkManager[2215]: [1528819503.2441] dhcp4 (eno1): state changed timeout -> done Jun 12 10:05:03 localhost.localdomain NetworkManager[2215]: [1528819503.2445] device (eno1): state change: ip-config -> failed (reason 'ip-config-unavailable', internal state 'managed') Jun 12 10:05:03 localhost.localdomain NetworkManager[2215]: [1528819503.2448] manager: NetworkManager state is now DISCONNECTED Jun 12 10:05:03 localhost.localdomain NetworkManager[2215]: [1528819503.2452] device (eno1): Activation: failed for connection 'Wired connection 1' Jun 12 10:05:03 localhost.localdomain NetworkManager[2215]: [1528819503.2460] device (eno1): state change: failed -> disconnected (reason 'none', internal state 'managed') Jun 12 10:05:03 localhost.localdomain NetworkManager[2215]: [1528819503.2498] policy: auto-activating connection 'Wired connection 1' Jun 12 10:05:03 localhost.localdomain NetworkManager[2215]: [1528819503.2517] device (eno1): Activation: starting connection 'Wired connection 1' (16a13ab5-c51e-361b-90bc-b6fc6f84cbe9) Jun 12 10:05:03 localhost.localdomain NetworkManager[2215]: [1528819503.2520] device (eno1): state change: disconnected -> prepare (reason 'none', internal state 'managed') Jun 12 10:05:03 localhost.localdomain NetworkManager[2215]: [1528819503.2523] manager: NetworkManager state is now CONNECTING Jun 12 10:05:03 localhost.localdomain NetworkManager[2215]: [1528819503.2529] device (eno1): state change: prepare -> config (reason 'none', internal state 'managed') ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/7] drm/i915/guc: Don't store runtime GuC log level in modparam (rev3)
Quoting Piorkowski, Piotr (2018-06-12 14:12:34) > On Tue, 2018-06-05 at 21:56 +, Patchwork wrote: > > == Series Details == > > > > Series: series starting with [v2,1/7] drm/i915/guc: Don't store > > runtime GuC log level in modparam (rev3) > > URL : https://patchwork.freedesktop.org/series/44201/ > > State : failure > > > > == Summary == > > > > = CI Bug Log - changes from CI_DRM_4280_full -> Patchwork_9205_full = > > > > == Summary - FAILURE == > > > > Serious unknown changes coming with Patchwork_9205_full absolutely > > need to be > > verified manually. > > > > If you think the reported changes have nothing to do with the > > changes > > introduced in Patchwork_9205_full, please notify your bug team to > > allow them > > to document this new failure mode, which will reduce false > > positives in CI. > > > > External URL: https://patchwork.freedesktop.org/api/1.0/series/4420 > > 1/revisions/3/mbox/ > > > > == Possible new issues == > > > > Here are the unknown changes that may have been introduced in > > Patchwork_9205_full: > > > > === IGT changes === > > > > Possible regressions > > > > igt@drv_selftest@live_hangcheck: > > shard-kbl: PASS -> DMESG-FAIL > > > > > > Warnings > > > > igt@drv_selftest@live_guc: > > shard-kbl: PASS -> SKIP +1 > > > > These negative results do not relate to my changes. Applied, but note for the future, your authorname and s-o-b are not an exact match. Please fix so that the scripts don't complain (and let's hope upstream is also forgiving). -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for Enable P010, P012 and P016 formats for GLK/CNL (rev2)
== Series Details == Series: Enable P010, P012 and P016 formats for GLK/CNL (rev2) URL : https://patchwork.freedesktop.org/series/43891/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4305_full -> Patchwork_9274_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9274_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9274_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9274_full: === IGT changes === Warnings igt@gem_exec_schedule@deep-blt: shard-kbl: PASS -> SKIP igt@gem_exec_schedule@deep-bsd2: shard-kbl: SKIP -> PASS +2 igt@kms_ccs@pipe-a-crc-sprite-planes-basic: shard-glk: PASS -> SKIP +1 igt@kms_cursor_legacy@cursora-vs-flipa-legacy: shard-snb: SKIP -> PASS +3 == Known issues == Here are the changes found in Patchwork_9274_full that come from known issues: === IGT changes === Issues hit igt@drv_selftest@live_gtt: shard-apl: PASS -> FAIL (fdo#105347) igt@drv_selftest@live_hangcheck: shard-kbl: PASS -> DMESG-FAIL (fdo#106560) igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: shard-glk: PASS -> FAIL (fdo#105363) igt@kms_flip_tiling@flip-to-y-tiled: shard-glk: PASS -> FAIL (fdo#103822, fdo#104724) igt@perf@polling: shard-hsw: PASS -> FAIL (fdo#102252) Possible fixes igt@kms_flip@2x-dpms-vs-vblank-race-interruptible: shard-hsw: FAIL (fdo#103060) -> PASS igt@kms_flip@2x-flip-vs-expired-vblank: shard-hsw: FAIL (fdo#102887) -> PASS igt@kms_flip@2x-flip-vs-fences: shard-glk: INCOMPLETE (fdo#103359, k.org#198133) -> PASS igt@kms_flip@plain-flip-fb-recreate-interruptible: shard-glk: FAIL (fdo#100368) -> PASS +1 igt@kms_flip@plain-flip-ts-check-interruptible: shard-hsw: FAIL (fdo#100368) -> PASS igt@kms_flip_tiling@flip-y-tiled: shard-glk: FAIL (fdo#103822, fdo#104724) -> PASS igt@kms_setmode@basic: shard-kbl: FAIL (fdo#99912) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887 fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 fdo#105347 https://bugs.freedesktop.org/show_bug.cgi?id=105347 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4305 -> Patchwork_9274 CI_DRM_4305: d5ec1c93d19ce1fa4e23176828f4fb9a592f2609 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4515: a0f2d23b7d3d4226a0a7637a9240bfa86f08c1d3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9274: b9090703ea04fcf0b22830e7c083f329b194a1ea @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9274/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Make closing request flush mandatory
== Series Details == Series: drm/i915: Make closing request flush mandatory URL : https://patchwork.freedesktop.org/series/44614/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4305_full -> Patchwork_9273_full = == Summary - FAILURE == Serious unknown changes coming with Patchwork_9273_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9273_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9273_full: === IGT changes === Possible regressions igt@drv_suspend@forcewake: shard-snb: PASS -> DMESG-WARN Warnings igt@gem_exec_schedule@deep-bsd2: shard-kbl: SKIP -> PASS +2 igt@gem_exec_schedule@deep-vebox: shard-kbl: PASS -> SKIP igt@kms_cursor_legacy@cursora-vs-flipa-legacy: shard-snb: SKIP -> PASS +3 == Known issues == Here are the changes found in Patchwork_9273_full that come from known issues: === IGT changes === Issues hit igt@gem_exec_big: shard-hsw: PASS -> INCOMPLETE (fdo#103540) igt@kms_atomic_transition@1x-modeset-transitions-nonblocking: shard-glk: PASS -> FAIL (fdo#105703) igt@kms_flip@flip-vs-expired-vblank: shard-glk: PASS -> FAIL (fdo#105363, fdo#102887) igt@kms_flip_tiling@flip-to-y-tiled: shard-glk: PASS -> FAIL (fdo#104724) Possible fixes igt@drv_suspend@shrink: shard-hsw: INCOMPLETE (fdo#103540) -> PASS igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic: shard-glk: FAIL (fdo#105454, fdo#106509) -> PASS igt@kms_flip@2x-dpms-vs-vblank-race-interruptible: shard-hsw: FAIL (fdo#103060) -> PASS igt@kms_flip@2x-flip-vs-expired-vblank: shard-hsw: FAIL (fdo#102887) -> PASS igt@kms_flip@2x-flip-vs-fences: shard-glk: INCOMPLETE (fdo#103359, k.org#198133) -> PASS igt@kms_flip@plain-flip-fb-recreate-interruptible: shard-glk: FAIL (fdo#100368) -> PASS +1 igt@kms_flip@plain-flip-ts-check-interruptible: shard-hsw: FAIL (fdo#100368) -> PASS igt@kms_flip_tiling@flip-x-tiled: shard-glk: FAIL (fdo#104724, fdo#103822) -> PASS igt@kms_setmode@basic: shard-apl: FAIL (fdo#99912) -> PASS shard-kbl: FAIL (fdo#99912) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887 fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540 fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454 fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703 fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4305 -> Patchwork_9273 CI_DRM_4305: d5ec1c93d19ce1fa4e23176828f4fb9a592f2609 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4515: a0f2d23b7d3d4226a0a7637a9240bfa86f08c1d3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9273: f0774d6ad9407317c3b116b68be17d91c18b98ff @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9273/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 0/7] drm/i915: move towards kernel types
On Tue, Jun 12, 2018 at 12:19:28PM +0300, Jani Nikula wrote: > Semi-RFC. Do we want to do this? Here's a batch of conversions that shouldn't > conflict much with in-flight patches. > > The trouble with mixed use is that it's inconsistent, and any remaining C99 > types will encourage their use. We could at least do the low hanging fruit? > > $ git grep "uint\(8\|16\|32\|64\)_t" -- drivers/gpu/drm/i915/ | sed 's/:.*//' > | sort | uniq -c | sort -n > > BR, > Jani. > > > Jani Nikula (7): > drm/i915/vbt: switch to kernel unsigned int types > drm/i915/hdmi: switch to kernel unsigned int types > drm/i915/uncore: switch to kernel unsigned int types > drm/i915/dvo: switch to kernel unsigned int types > drm/i915/backlight: switch to kernel unsigned int types > drm/i915/audio: switch to kernel unsigned int types > drm/i915/lspcon: switch to kernel unsigned int types Did a quick once over and didn't spot anything wrong, so Reviewed-by: Ville Syrjälä > > drivers/gpu/drm/i915/dvo_ch7017.c | 20 ++-- > drivers/gpu/drm/i915/dvo_ch7xxx.c | 22 +++--- > drivers/gpu/drm/i915/dvo_ivch.c | 26 > drivers/gpu/drm/i915/dvo_ns2501.c | 44 > +-- > drivers/gpu/drm/i915/dvo_sil164.c | 10 +++--- > drivers/gpu/drm/i915/dvo_tfp410.c | 16 +- > drivers/gpu/drm/i915/intel_audio.c| 36 +++--- > drivers/gpu/drm/i915/intel_bios.c | 4 +-- > drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 12 > drivers/gpu/drm/i915/intel_dvo.c | 2 +- > drivers/gpu/drm/i915/intel_hdmi.c | 14 - > drivers/gpu/drm/i915/intel_lspcon.c | 2 +- > drivers/gpu/drm/i915/intel_panel.c| 8 ++--- > drivers/gpu/drm/i915/intel_uncore.h | 22 +++--- > drivers/gpu/drm/i915/intel_vbt_defs.h | 2 +- > 15 files changed, 120 insertions(+), 120 deletions(-) > > -- > 2.11.0 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for HACK: drm/i915: see what breaks with display disabled
== Series Details == Series: HACK: drm/i915: see what breaks with display disabled URL : https://patchwork.freedesktop.org/series/44485/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4306 -> Patchwork_9276 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_9276 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9276, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/44485/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9276: === IGT changes === Possible regressions igt@debugfs_test@read_all_entries: fi-byt-j1900: PASS -> DMESG-FAIL +1 fi-bsw-n3050: PASS -> DMESG-FAIL igt@gem_exec_flush@basic-wb-ro-before-default: fi-snb-2600:PASS -> INCOMPLETE igt@gem_exec_suspend@basic-s3: fi-bdw-5557u: PASS -> DMESG-WARN fi-bsw-n3050: PASS -> DMESG-WARN fi-hsw-4770:PASS -> DMESG-WARN fi-hsw-4200u: PASS -> DMESG-WARN igt@kms_addfb_basic@addfb25-bad-modifier: fi-bdw-gvtdvm: PASS -> FAIL +36 fi-gdg-551: PASS -> FAIL +36 igt@kms_addfb_basic@addfb25-modifier-no-flag: fi-cfl-guc: PASS -> FAIL +37 fi-skl-guc: PASS -> FAIL +37 igt@kms_addfb_basic@addfb25-y-tiled: fi-kbl-r: PASS -> FAIL +36 fi-byt-n2820: PASS -> FAIL +37 igt@kms_addfb_basic@addfb25-y-tiled-small: fi-bwr-2160:SKIP -> FAIL fi-bdw-5557u: SKIP -> FAIL fi-byt-n2820: SKIP -> FAIL fi-hsw-4200u: SKIP -> FAIL +1 fi-hsw-4770:SKIP -> FAIL fi-byt-j1900: SKIP -> FAIL fi-ivb-3770:SKIP -> FAIL fi-blb-e6850: SKIP -> FAIL fi-gdg-551: SKIP -> FAIL fi-elk-e7500: SKIP -> FAIL fi-ilk-650: SKIP -> FAIL fi-bdw-gvtdvm: SKIP -> FAIL fi-hsw-4770r: SKIP -> FAIL fi-pnv-d510:SKIP -> FAIL igt@kms_addfb_basic@addfb25-yf-tiled: fi-snb-2520m: NOTRUN -> FAIL +37 igt@kms_addfb_basic@bad-pitch-1024: fi-cfl-u2: PASS -> FAIL +36 fi-bxt-dsi: PASS -> FAIL +36 fi-ivb-3520m: PASS -> FAIL +35 igt@kms_addfb_basic@bad-pitch-128: fi-bxt-j4205: PASS -> FAIL +37 igt@kms_addfb_basic@bad-pitch-32: fi-pnv-d510:PASS -> FAIL +36 igt@kms_addfb_basic@bad-pitch-63: fi-kbl-7567u: PASS -> FAIL +37 igt@kms_addfb_basic@basic: fi-cnl-psr: PASS -> FAIL +36 fi-byt-j1900: PASS -> FAIL +37 fi-skl-6260u: PASS -> FAIL +37 igt@kms_addfb_basic@basic-y-tiled: fi-cfl-s3: PASS -> FAIL +36 igt@kms_addfb_basic@framebuffer-vs-set-tiling: fi-ilk-650: PASS -> FAIL +36 fi-skl-6770hq: PASS -> FAIL +37 igt@kms_addfb_basic@invalid-get-prop-any: fi-skl-6600u: PASS -> FAIL +36 fi-ivb-3770:PASS -> FAIL +36 fi-kbl-7560u: PASS -> FAIL +36 igt@kms_addfb_basic@invalid-set-prop: fi-hsw-4770:PASS -> FAIL +36 igt@kms_addfb_basic@no-handle: fi-cfl-8700k: PASS -> FAIL +37 igt@kms_addfb_basic@too-high: fi-glk-j4005: PASS -> FAIL +37 igt@kms_addfb_basic@unused-handle: fi-skl-6700k2: PASS -> FAIL +37 fi-elk-e7500: PASS -> FAIL +36 igt@kms_addfb_basic@unused-modifier: fi-bdw-5557u: PASS -> FAIL +36 fi-kbl-guc: PASS -> FAIL +36 igt@kms_addfb_basic@unused-offsets: fi-bwr-2160:PASS -> FAIL +36 fi-blb-e6850: PASS -> FAIL +36 fi-hsw-4200u: PASS -> FAIL +35 igt@kms_addfb_basic@unused-pitches: fi-hsw-peppy: PASS -> FAIL +35 fi-skl-gvtdvm: PASS -> FAIL +37 igt@pm_rps@basic-api: fi-byt-n2820: PASS -> DMESG-FAIL +1 igt@prime_vgem@basic-fence-flip: fi-hsw-4770r: PASS -> FAIL +36 fi-kbl-7500u: PASS -> FAIL +37 fi-cfl-u2: SKIP -> FAIL fi-bxt-dsi: SKIP -> FAIL fi-ivb-3520m: SKIP -> FAIL +1 fi-cnl-psr: SKIP -> FAIL fi-hsw-peppy: SKIP -> FAIL +1 fi-kbl-r: SKIP -> FAIL fi-skl-6600u: SKIP -> FAIL fi-kbl-7560u: SKIP -> FAIL fi-cfl-s3: SKIP -> FAIL fi-kbl-guc: SKIP -> FAIL Warnings igt@kms_busy@basic-flip-a: fi-kbl-7567u: PASS -> SKIP +36 igt@kms_chamelium@dp-crc-fast: fi-kbl-7500u: PASS -> SKIP +39 igt@kms_chamelium@hdmi-crc-fast: fi-skl-6700k2: PASS -> SKIP +40
Re: [Intel-gfx] [PATCH 6/7] drm/i915/audio: switch to kernel unsigned int types
On Tue, Jun 12, 2018 at 12:19:34PM +0300, Jani Nikula wrote:
> We have fairly mixed uintN_t vs. uN usage throughout the driver, but try
> to stick to kernel types at least where it's more prevalent.
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_audio.c | 36 ++--
> 1 file changed, 18 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_audio.c
> b/drivers/gpu/drm/i915/intel_audio.c
> index 3ea566f99450..4e4c0ec44f35 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -198,13 +198,13 @@ static int audio_config_hdmi_get_n(const struct
> intel_crtc_state *crtc_state,
> }
>
> static bool intel_eld_uptodate(struct drm_connector *connector,
> -i915_reg_t reg_eldv, uint32_t bits_eldv,
> -i915_reg_t reg_elda, uint32_t bits_elda,
> +i915_reg_t reg_eldv, u32 bits_eldv,
> +i915_reg_t reg_elda, u32 bits_elda,
> i915_reg_t reg_edid)
> {
> struct drm_i915_private *dev_priv = to_i915(connector->dev);
> - uint8_t *eld = connector->eld;
> - uint32_t tmp;
> + u8 *eld = connector->eld;
Drive by observation: could make all of these eld pointers const u32 *
> + u32 tmp;
> int i;
>
> tmp = I915_READ(reg_eldv);
> @@ -218,7 +218,7 @@ static bool intel_eld_uptodate(struct drm_connector
> *connector,
> I915_WRITE(reg_elda, tmp);
>
> for (i = 0; i < drm_eld_size(eld) / 4; i++)
> - if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
> + if (I915_READ(reg_edid) != *((u32 *)eld + i))
> return false;
>
> return true;
--
Ville Syrjälä
Intel
___
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Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/7] drm/i915/guc: Don't store runtime GuC log level in modparam (rev3)
On Tue, 2018-06-05 at 21:56 +, Patchwork wrote: > == Series Details == > > Series: series starting with [v2,1/7] drm/i915/guc: Don't store > runtime GuC log level in modparam (rev3) > URL : https://patchwork.freedesktop.org/series/44201/ > State : failure > > == Summary == > > = CI Bug Log - changes from CI_DRM_4280_full -> Patchwork_9205_full = > > == Summary - FAILURE == > > Serious unknown changes coming with Patchwork_9205_full absolutely > need to be > verified manually. > > If you think the reported changes have nothing to do with the > changes > introduced in Patchwork_9205_full, please notify your bug team to > allow them > to document this new failure mode, which will reduce false > positives in CI. > > External URL: https://patchwork.freedesktop.org/api/1.0/series/4420 > 1/revisions/3/mbox/ > > == Possible new issues == > > Here are the unknown changes that may have been introduced in > Patchwork_9205_full: > > === IGT changes === > > Possible regressions > > igt@drv_selftest@live_hangcheck: > shard-kbl: PASS -> DMESG-FAIL > > > Warnings > > igt@drv_selftest@live_guc: > shard-kbl: PASS -> SKIP +1 > These negative results do not relate to my changes. > > Here are the changes found in Patchwork_9205_full that come from > known issues: > > === IGT changes === > > Issues hit > > igt@gem_ctx_isolation@bcs0-s3: > shard-kbl: PASS -> INCOMPLETE (fdo#103665) +1 > > igt@gem_eio@suspend: > shard-snb: PASS -> FAIL (fdo#105957) > > igt@gem_ppgtt@blt-vs-render-ctxn: > shard-kbl: PASS -> INCOMPLETE (fdo#103665, fdo#106023) > > igt@kms_flip@2x-plain-flip-fb-recreate-interruptible: > shard-glk: PASS -> FAIL (fdo#100368) +2 > > igt@kms_flip@flip-vs-expired-vblank-interruptible: > shard-glk: PASS -> FAIL (fdo#102887, fdo#105363) > > igt@kms_flip_tiling@flip-y-tiled: > shard-glk: PASS -> FAIL (fdo#104724, fdo#103822) > > > Possible fixes > > igt@drv_selftest@live_gtt: > shard-glk: INCOMPLETE (k.org#198133, fdo#103359) -> > PASS > > igt@drv_selftest@live_hangcheck: > shard-apl: DMESG-FAIL (fdo#106560) -> PASS > > igt@kms_flip@2x-flip-vs-expired-vblank: > shard-glk: FAIL (fdo#105363) -> PASS > > > fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 > fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887 > fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 > fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 > fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822 > fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 > fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 > fdo#105957 https://bugs.freedesktop.org/show_bug.cgi?id=105957 > fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023 > fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560 > k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 > > > == Participating hosts (5 -> 5) == > > No changes in participating hosts > > > == Build changes == > > * Linux: CI_DRM_4280 -> Patchwork_9205 > > CI_DRM_4280: 967aa2f22752af3adc629b50e7d2ed2b7e061e44 @ > git://anongit.freedesktop.org/gfx-ci/linux > IGT_4507: 938135f033d7fd79c04a7a042d40f9d074489ffd @ > git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > Patchwork_9205: 2d8957f508dca1fd3b25f006a40388ea2a020080 @ > git://anongit.freedesktop.org/gfx-ci/linux > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchw > ork_9205/shards.html smime.p7s Description: S/MIME cryptographic signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gtt: Make gen6 page directories evictable
== Series Details == Series: drm/i915/gtt: Make gen6 page directories evictable URL : https://patchwork.freedesktop.org/series/44623/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4306 -> Patchwork_9275 = == Summary - WARNING == Minor unknown changes coming with Patchwork_9275 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9275, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/44623/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9275: === IGT changes === Warnings igt@gem_exec_gttfill@basic: fi-pnv-d510:PASS -> SKIP == Known issues == Here are the changes found in Patchwork_9275 that come from known issues: === IGT changes === Issues hit igt@gem_exec_basic@gtt-render: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106000) igt@gem_exec_gttfill@basic: fi-byt-n2820: PASS -> FAIL (fdo#106744) igt@gem_exec_suspend@basic-s3: fi-glk-j4005: PASS -> DMESG-WARN (fdo#105719) Possible fixes igt@debugfs_test@read_all_entries: fi-snb-2520m: INCOMPLETE (fdo#103713) -> PASS igt@kms_flip@basic-flip-vs-dpms: fi-glk-j4005: DMESG-WARN (fdo#106000) -> PASS fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 fdo#105719 https://bugs.freedesktop.org/show_bug.cgi?id=105719 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106744 https://bugs.freedesktop.org/show_bug.cgi?id=106744 == Participating hosts (43 -> 38) == Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-skl-6700hq == Build changes == * Linux: CI_DRM_4306 -> Patchwork_9275 CI_DRM_4306: 46ac5b5698d4aea58eb440f1ec47d734762259f7 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4515: a0f2d23b7d3d4226a0a7637a9240bfa86f08c1d3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9275: 903967c3061a798c8feef2c6c73c468481f86cc9 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 903967c3061a drm/i915/gtt: Make gen6 page directories evictable == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9275/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/gtt: Make gen6 page directories evictable
== Series Details == Series: drm/i915/gtt: Make gen6 page directories evictable URL : https://patchwork.freedesktop.org/series/44623/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915/gtt: Make gen6 page directories evictable -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1709:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1709:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1961:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1961:9: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: move towards kernel types (rev2)
== Series Details == Series: drm/i915: move towards kernel types (rev2) URL : https://patchwork.freedesktop.org/series/44610/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4305_full -> Patchwork_9272_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9272_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9272_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9272_full: === IGT changes === Warnings igt@gem_exec_schedule@deep-bsd2: shard-kbl: SKIP -> PASS +2 igt@gem_mocs_settings@mocs-rc6-vebox: shard-kbl: PASS -> SKIP +3 igt@gem_tiled_blits@normal: shard-glk: SKIP -> PASS igt@kms_cursor_legacy@cursora-vs-flipa-legacy: shard-snb: SKIP -> PASS +3 == Known issues == Here are the changes found in Patchwork_9272_full that come from known issues: === IGT changes === Issues hit igt@drv_selftest@live_gtt: shard-kbl: PASS -> INCOMPLETE (fdo#103665) shard-glk: PASS -> FAIL (fdo#105347) igt@kms_cursor_legacy@cursora-vs-flipa-toggle: shard-glk: PASS -> DMESG-WARN (fdo#105763) igt@kms_flip_tiling@flip-to-y-tiled: shard-glk: PASS -> FAIL (fdo#104724, fdo#103822) Possible fixes igt@drv_suspend@shrink: shard-hsw: INCOMPLETE (fdo#103540) -> PASS igt@kms_flip@2x-dpms-vs-vblank-race-interruptible: shard-hsw: FAIL (fdo#103060) -> PASS igt@kms_flip@2x-flip-vs-expired-vblank: shard-hsw: FAIL (fdo#102887) -> PASS igt@kms_flip@2x-flip-vs-fences: shard-glk: INCOMPLETE (k.org#198133, fdo#103359) -> PASS +1 igt@kms_flip@plain-flip-ts-check-interruptible: shard-glk: FAIL (fdo#100368) -> PASS shard-hsw: FAIL (fdo#100368) -> PASS igt@kms_flip_tiling@flip-x-tiled: shard-glk: FAIL (fdo#104724, fdo#103822) -> PASS +1 fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887 fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 fdo#105347 https://bugs.freedesktop.org/show_bug.cgi?id=105347 fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4305 -> Patchwork_9272 CI_DRM_4305: d5ec1c93d19ce1fa4e23176828f4fb9a592f2609 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4515: a0f2d23b7d3d4226a0a7637a9240bfa86f08c1d3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9272: 63e510d8cf5be48d1cd705797004da2b8cbf6ad9 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9272/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [CI 1/2] drm/i915/icl: Add allowed DP rates for Icelake
On Mon, Jun 11, 2018 at 03:26:54PM -0700, Paulo Zanoni wrote:
> From: Manasi Navare
>
> For ICL, on Combo PHY the allowed max rates are:
> - HBR3 8.1 eDP (DDIA)
> - HBR2 5.4 DisplayPort (DDIB)
> and for MG PHY/TC DDI Ports allowed DP rates are:
> - HBR3 8.1 DisplayPort (DP alternate mode, DP over TBT,
> - DP on legacy connector - DDIC/D/E/F)
>
> Cc: Rodrigo Vivi
> Cc: Jani Nikula
> Reviewed-by: James Ausmus
> Signed-off-by: Manasi Navare
> Signed-off-by: James Ausmus
> [Paulo: bikeshed to keep future platforms on "else".]
> Signed-off-by: Paulo Zanoni
> ---
> drivers/gpu/drm/i915/intel_dp.c | 21 +++--
> 1 file changed, 19 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 37b9f62aeb6e..8371159cc192 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -256,6 +256,20 @@ static int cnl_max_source_rate(struct intel_dp *intel_dp)
> return 81;
> }
>
> +static int icl_max_source_rate(struct intel_dp *intel_dp)
> +{
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + enum port port = dig_port->base.port;
> +
> + /* On Combo PHY port A max speed is HBR3 for all Vccio voltages
> + * and on Combo PHY Port B the maximum supported is HBR2.
> + */
And what about the other ports? If port B is the only
exception why are we even discussing port A specifically
here?
> + if (port == PORT_B)
> + return 54;
> +
> + return 81;
> +}
> +
> static void
> intel_dp_set_source_rates(struct intel_dp *intel_dp)
> {
> @@ -285,10 +299,13 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
> /* This should only be done once */
> WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
>
> - if (IS_CANNONLAKE(dev_priv)) {
> + if (INTEL_GEN(dev_priv) >= 10) {
> source_rates = cnl_rates;
> size = ARRAY_SIZE(cnl_rates);
> - max_rate = cnl_max_source_rate(intel_dp);
> + if (INTEL_GEN(dev_priv) == 10)
> + max_rate = cnl_max_source_rate(intel_dp);
> + else
> + max_rate = icl_max_source_rate(intel_dp);
> } else if (IS_GEN9_LP(dev_priv)) {
> source_rates = bxt_rates;
> size = ARRAY_SIZE(bxt_rates);
> --
> 2.14.4
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v3] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
On Tue, Jun 12, 2018 at 12:17:41AM -0700, Abhay Kumar wrote:
> From: Ville Syrjälä
>
> CDCLK has to be at least twice the BLCK regardless of audio. Audio
> driver has to probe using this hook and increase the clock even in
> absence of any display.
>
> v2: Use atomic refcount for get_power, put_power so that we can
> call each once(Abhay).
> v3: Reset power well 2 to avoid any transaction on iDisp link
> during cdclk change(Abhay).
>
> Signed-off-by: Ville Syrjälä
> Signed-off-by: Abhay Kumar
> ---
> drivers/gpu/drm/i915/i915_drv.h | 3 ++
> drivers/gpu/drm/i915/i915_reg.h | 4 ++
> drivers/gpu/drm/i915/intel_audio.c | 87
> ++--
> drivers/gpu/drm/i915/intel_cdclk.c | 29
> drivers/gpu/drm/i915/intel_display.c | 7 ++-
> drivers/gpu/drm/i915/intel_drv.h | 2 +
> 6 files changed, 107 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 6104d7115054..a4a386a5db69 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1702,6 +1702,7 @@ struct drm_i915_private {
> unsigned int hpll_freq;
> unsigned int fdi_pll_freq;
> unsigned int czclk_freq;
> + u32 get_put_refcount;
>
> struct {
> /*
> @@ -1719,6 +1720,8 @@ struct drm_i915_private {
> struct intel_cdclk_state actual;
> /* The current hardware cdclk state */
> struct intel_cdclk_state hw;
> +
> + int force_min_cdclk;
> } cdclk;
>
> /**
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 987def26ce82..cef770184245 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8869,6 +8869,10 @@ enum skl_power_gate {
> * SKL Clocks
> */
>
> +/* Power well 2 */
> +#define POWER_WELL_2 _MMIO(0x45404)
> +#define POWER_WELL_2_REQUEST (1<<31)
> +
> /* CDCLK_CTL */
> #define CDCLK_CTL_MMIO(0x46000)
> #define CDCLK_FREQ_SEL_MASK (3 << 26)
> diff --git a/drivers/gpu/drm/i915/intel_audio.c
> b/drivers/gpu/drm/i915/intel_audio.c
> index 3ea566f99450..1f5a9af13ef0 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -618,7 +618,6 @@ void intel_audio_codec_enable(struct intel_encoder
> *encoder,
>
> if (!connector->eld[0])
> return;
> -
> DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
>connector->base.id,
>connector->name,
> @@ -713,14 +712,94 @@ void intel_init_audio_hooks(struct drm_i915_private
> *dev_priv)
> }
> }
>
> +static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
> + bool enable)
> +{
> + struct drm_modeset_acquire_ctx ctx;
> + struct drm_atomic_state *state;
> + int ret;
> +
> + drm_modeset_acquire_init(, 0);
> + state = drm_atomic_state_alloc(_priv->drm);
> + if (WARN_ON(!state))
> + return;
> +
> + state->acquire_ctx =
> +
> +retry:
> + to_intel_atomic_state(state)->modeset = true;
> + to_intel_atomic_state(state)->cdclk.force_min_cdclk =
> + enable ? 2 * 96000 : 0;
> +
> + /*
> + * Protects dev_priv->cdclk.force_min_cdclk
> + * Need to lock this here in case we have no active pipes
> + * and thus wouldn't lock it during the commit otherwise.
> + */
> + ret = drm_modeset_lock(_priv->drm.mode_config.connection_mutex,
> );
> + if (!ret)
> + ret = drm_atomic_commit(state);
> +
> + if (ret == -EDEADLK) {
> + drm_atomic_state_clear(state);
> + drm_modeset_backoff();
> + goto retry;
> + }
> +
> + WARN_ON(ret);
> +
> + drm_atomic_state_put(state);
> +
> + drm_modeset_drop_locks();
> + drm_modeset_acquire_fini();
> +}
> +
> static void i915_audio_component_get_power(struct device *kdev)
> {
> - intel_display_power_get(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
> + struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
> + u32 tmp;
> +
> + dev_priv->get_put_refcount++;
> +
> + /* Force cdclk to 2*BCLK during first time get power call */
> + if (dev_priv->get_put_refcount == 1) {
> + if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
> +
> + /*FIXME: Make sure there is no transaction
> + * on iDisp link while changing cdclk
> + */
> +
> + /* Turn off power well 2*/
> + tmp = I915_READ(POWER_WELL_2);
> + tmp = tmp & ~POWER_WELL_2_REQUEST;
> + I915_WRITE(POWER_WELL_2, tmp);
> + tmp = I915_READ(POWER_WELL_2);
> +
> + /* Turn on power well 2*/
> + tmp =
Re: [Intel-gfx] [PATCH][V3] drm/i915/guc: fix GEM_BUG_ON check
On Tue, 12 Jun 2018 11:38:04 +0200, Colin King
wrote:
From: Colin Ian King
The check for level being less than zero always false because flags
is currently unsigned and can never be negative. Fix this by making
level a s32.
Detected by CoverityScan, CID#1468363 ("Macro compares unsigned to 0")
Fixes: cb5d64e9f13e ("drm/i915/guc: Allow user to control default GuC
logging")
Signed-off-by: Colin Ian King
---
V3: Make level s32 and add the missing Fixes: tag, thanks to Dan
Carpenter and
Jani Nikula for correcting my mistakes
---
drivers/gpu/drm/i915/intel_guc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_guc.c
b/drivers/gpu/drm/i915/intel_guc.c
index 116f4ccf1bbd..bdb1fab322bf 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -205,7 +205,7 @@ void intel_guc_fini(struct intel_guc *guc)
static u32 get_log_control_flags(void)
{
- u32 level = i915_modparams.guc_log_level;
+ s32 level = i915_modparams.guc_log_level;
s/s32 level/int level
to match modparam type as already suggested by others
u32 flags = 0;
GEM_BUG_ON(level < 0);
please note that this BUG_ON will go away with pending [1] so maybe
we can just merge series [2] instead ?
Thanks,
Michal
[1] https://patchwork.freedesktop.org/patch/227365/
[2] https://patchwork.freedesktop.org/series/44201/
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[Intel-gfx] [CI] drm/i915/gtt: Make gen6 page directories evictable
Currently all page directories are bound at creation using an
unevictable node in the GGTT. This severely limits us as we cannot
remove any inactive ppgtt for new contexts, or under aperture pressure.
To fix this we need to make the page directory into a first class and
unbindable vma. Hence, the creation of a custom vma to wrap the page
directory as opposed to a GEM object.
In this patch, we leave the page directories pinned upon creation.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 257
drivers/gpu/drm/i915/i915_gem_gtt.h | 2 +-
drivers/gpu/drm/i915/i915_vma.h | 7 +
3 files changed, 155 insertions(+), 111 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index e9fcc4370b1a..c6949da3423f 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1640,50 +1640,55 @@ static void gen6_dump_ppgtt(struct i915_hw_ppgtt *base,
struct seq_file *m)
{
struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(base);
struct i915_address_space *vm = >vm;
- struct i915_page_table *unused;
- gen6_pte_t scratch_pte;
- u32 pd_entry, pte, pde;
-
- scratch_pte = vm->pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC, 0);
-
- gen6_for_all_pdes(unused, >pd, pde) {
- u32 expected;
- gen6_pte_t *pt_vaddr;
- const dma_addr_t pt_addr = px_dma(base->pd.page_table[pde]);
- pd_entry = readl(ppgtt->pd_addr + pde);
- expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
-
- if (pd_entry != expected)
- seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x
Expected PDE: %x\n",
- pde,
- pd_entry,
- expected);
- seq_printf(m, "\tPDE: %x\n", pd_entry);
-
- pt_vaddr = kmap_atomic_px(base->pd.page_table[pde]);
-
- for (pte = 0; pte < GEN6_PTES; pte+=4) {
- unsigned long va =
- (pde * PAGE_SIZE * GEN6_PTES) +
- (pte * PAGE_SIZE);
+ const gen6_pte_t scratch_pte =
+ vm->pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC, 0);
+ struct i915_page_table *pt;
+ u32 pte, pde;
+
+ gen6_for_all_pdes(pt, >pd, pde) {
+ gen6_pte_t *vaddr;
+
+ if (pt == base->vm.scratch_pt)
+ continue;
+
+ if (i915_vma_is_bound(ppgtt->vma, I915_VMA_GLOBAL_BIND)) {
+ u32 expected =
+ GEN6_PDE_ADDR_ENCODE(px_dma(pt)) |
+ GEN6_PDE_VALID;
+ u32 pd_entry = readl(ppgtt->pd_addr + pde);
+
+ if (pd_entry != expected)
+ seq_printf(m,
+ "\tPDE #%d mismatch: Actual PDE: %x
Expected PDE: %x\n",
+ pde,
+ pd_entry,
+ expected);
+
+ seq_printf(m, "\tPDE: %x\n", pd_entry);
+ }
+
+ vaddr = kmap_atomic_px(base->pd.page_table[pde]);
+ for (pte = 0; pte < GEN6_PTES; pte += 4) {
int i;
- bool found = false;
+
for (i = 0; i < 4; i++)
- if (pt_vaddr[pte + i] != scratch_pte)
- found = true;
- if (!found)
+ if (vaddr[pte + i] != scratch_pte)
+ break;
+ if (i == 4)
continue;
- seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
+ seq_printf(m, "\t\t(%03d, %04d) %08lx: ",
+ pde, pte,
+ (pde * GEN6_PTES + pte) * PAGE_SIZE);
for (i = 0; i < 4; i++) {
- if (pt_vaddr[pte + i] != scratch_pte)
- seq_printf(m, " %08x", pt_vaddr[pte +
i]);
+ if (vaddr[pte + i] != scratch_pte)
+ seq_printf(m, " %08x", vaddr[pte + i]);
else
- seq_puts(m, " SCRATCH ");
+ seq_puts(m, " SCRATCH");
}
seq_puts(m, "\n");
}
- kunmap_atomic(pt_vaddr);
+ kunmap_atomic(vaddr);
}
}
@@ -1697,22 +1702,6 @@
Re: [Intel-gfx] [PATCH v9 7/7] drm/i915: add a sysfs entry to let users set sseu configs
Quoting Lionel Landwerlin (2018-06-12 11:52:10) > I'm looking forward to the definition of the greater good :) > Tvrtko wanted to avoid the heuristic territory, it seems like we're just > stepping into it. If we have to make any choice, we have not just stepped, but dived head first into it. Tbh, I quite like the idea of having BPF policy hooks. (Devil will definitely be in the details!) -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v9 7/7] drm/i915: add a sysfs entry to let users set sseu configs
On 12/06/2018 11:52, Lionel Landwerlin wrote:
On 12/06/18 11:37, Chris Wilson wrote:
Quoting Lionel Landwerlin (2018-06-12 11:33:34)
On 12/06/18 10:20, Joonas Lahtinen wrote:
Quoting Chris Wilson (2018-06-11 18:02:37)
Quoting Lionel Landwerlin (2018-06-11 14:46:07)
On 11/06/18 13:10, Tvrtko Ursulin wrote:
On 30/05/2018 15:33, Lionel Landwerlin wrote:
There are concerns about denial of service around the per
context sseu
configuration capability. In a previous commit introducing the
capability we allowed it only for capable users. This changes
adds a
new debugfs entry to let any user configure its own context
powergating setup.
As far as I understood it, Joonas' concerns here are:
1) That in the containers use case individual containers wouldn't be
able to turn on the sysfs toggle for them.
2) That also in the containers use case if box admin turns on the
feature, some containers would potentially start negatively
affecting
the others (via the accumulated cost of slice re-configuration on
context switching).
I am not familiar with typical container setups to be authoritative
here, but intuitively I find it reasonable that a low-level hardware
switch like this would be under the control of a master domain
administrator. ("If you are installing our product in the container
environment, make sure your system administrator enables this
hardware
feature.", "Note to system administrators: Enabling this features
may
negatively affect the performance of other containers.")
Alternative proposal is for the i915 to apply an "or" filter on all
requested masks and in that way ensure dynamic re-configuration
doesn't happen on context switches, but driven from userspace via
ioctls.
In other words, should _all_ userspace agree between themselves that
they want to turn off a slice, they would then need to send out a
concerted ioctl storm, where number of needed ioctls equals the
number
of currently active contexts. (This may have its own performance
consequences caused by the barriers needed to modify all context
images.)
This was deemed acceptable the the media use case, but my concern is
the approach is not elegant and will tie us with the "or" policy in
the ABI. (Performance concerns I haven't evaluated yet, but they
also
may be significant.)
If we go back thinking about the containers use case, then it
transpires that even though the "or" policy does prevent one
container
from affecting the other from one angle, it also prevents one
container from exercising the feature unless all containers
co-operate.
As such, we can view the original problem statement where we have an
issue if not everyone co-operates, as conceptually the same just
from
an opposite angle. (Rather than one container incurring the
increased
cost of context switches to the rest, we would have one container
preventing the optimized slice configuration to the other.)
From this follows that both proposals require complete
co-operation
from all running userspace to avoid complete control of the feature.
Since the balance between the benefit of optimized slice
configuration
(or penalty of suboptimal one), versus the penalty of increased
context switch times, cannot be know by the driver (barring
venturing
into the heuristics territory), that is another reason why I find
the
"or" policy in the driver questionable.
We can also ask a question of - If we go with the "or" policy, why
require N per-context ioctls to modify the global GPU configuration
and not instead add a global driver ioctl to modify the state?
If a future hardware requires, or enables, the per-context behaviour
in a more efficient way, we could then revisit the problem space.
In the mean time I see the "or" policy solution as adding some ABI
which doesn't do anything for many use cases without any way for the
sysadmin to enable it. At the same time master sysfs knob at least
enables the sysadmin to make a decision. Here I am thinking about a
random client environment where not all userspace co-operates,
but for
instance user is running the feature aware media stack, and
non-feature aware OpenCL/3d stack.
I guess the complete story boils down to - is the master sysfs knob
really a problem in container use cases.
Regards,
Tvrtko
Hey Tvrtko,
Thanks for summarizing a bunch of discussions.
Essentially I agree with every you wrote above.
If we have a global setting (determined by the OR policy), what's the
point of per context settings?
In Dmitry's scenario, all userspace applications will work
together to
reach the consensus so it sounds like we're reimplementing the policy
that is already existing in userspace.
Anyway, I'm implementing Joonas' suggestion. Hopefully somebody else
than me pick one or the other :)
I'll just mention the voting/consensus approach to see if anyone else
likes it.
Each context has a CONTEXT_PARAM_HINT_SSEU { small, dontcare, large }
(or some other abstract names).
Yeah, the param name should have the
[Intel-gfx] ✓ Fi.CI.BAT: success for Enable P010, P012 and P016 formats for GLK/CNL (rev2)
== Series Details == Series: Enable P010, P012 and P016 formats for GLK/CNL (rev2) URL : https://patchwork.freedesktop.org/series/43891/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4305 -> Patchwork_9274 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/43891/revisions/2/mbox/ == Known issues == Here are the changes found in Patchwork_9274 that come from known issues: === IGT changes === Issues hit igt@gem_wait@basic-busy-all: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106000) +1 igt@kms_flip@basic-flip-vs-wf_vblank: fi-glk-j4005: PASS -> FAIL (fdo#100368) Possible fixes igt@debugfs_test@read_all_entries: fi-snb-2520m: INCOMPLETE (fdo#103713) -> PASS igt@gem_exec_suspend@basic-s3: fi-skl-gvtdvm: INCOMPLETE (fdo#105600, fdo#104108) -> PASS igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: DMESG-WARN (fdo#106607) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108 fdo#105600 https://bugs.freedesktop.org/show_bug.cgi?id=105600 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106607 https://bugs.freedesktop.org/show_bug.cgi?id=106607 == Participating hosts (42 -> 37) == Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-bxt-dsi fi-bsw-cyan fi-skl-6700hq == Build changes == * Linux: CI_DRM_4305 -> Patchwork_9274 CI_DRM_4305: d5ec1c93d19ce1fa4e23176828f4fb9a592f2609 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4515: a0f2d23b7d3d4226a0a7637a9240bfa86f08c1d3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9274: b9090703ea04fcf0b22830e7c083f329b194a1ea @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == b9090703ea04 drm/i915: enable P010, P012, P016 formats for primary and sprite planes 13b5a18b2a3f drm/i915: preparations for enabling P010, P012, P016 formats ffaf900fc205 drm/i915: Add P010, P012, P016 plane control definitions c556cc92888f drm: Add P010, P012, P016 format definitions and fourcc == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9274/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable P010, P012 and P016 formats for GLK/CNL (rev2)
== Series Details == Series: Enable P010, P012 and P016 formats for GLK/CNL (rev2) URL : https://patchwork.freedesktop.org/series/43891/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm: Add P010, P012, P016 format definitions and fourcc Okay! Commit: drm/i915: Add P010, P012, P016 plane control definitions Okay! Commit: drm/i915: preparations for enabling P010, P012, P016 formats -O:drivers/gpu/drm/i915/intel_display.c:13099:21: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_display.c:13099:21: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_display.c:13113:21: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_display.c:13113:21: warning: expression using sizeof(void) Commit: drm/i915: enable P010, P012, P016 formats for primary and sprite planes Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/guc: fix GEM_BUG_ON check (rev2)
== Series Details == Series: drm/i915/guc: fix GEM_BUG_ON check (rev2) URL : https://patchwork.freedesktop.org/series/44578/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4305_full -> Patchwork_9271_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9271_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9271_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9271_full: === IGT changes === Warnings igt@gem_exec_schedule@deep-bsd2: shard-kbl: SKIP -> PASS +2 igt@gem_mocs_settings@mocs-rc6-vebox: shard-kbl: PASS -> SKIP igt@kms_cursor_legacy@cursora-vs-flipa-legacy: shard-snb: SKIP -> PASS +3 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt: shard-snb: PASS -> SKIP +2 == Known issues == Here are the changes found in Patchwork_9271_full that come from known issues: === IGT changes === Issues hit igt@drv_selftest@live_gtt: shard-kbl: PASS -> INCOMPLETE (fdo#103665) shard-glk: PASS -> INCOMPLETE (k.org#198133, fdo#103359) igt@gem_exec_big: shard-hsw: PASS -> INCOMPLETE (fdo#103540) igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size: shard-hsw: PASS -> FAIL (fdo#102670) igt@kms_flip@2x-flip-vs-absolute-wf_vblank: shard-hsw: PASS -> FAIL (fdo#103928) igt@kms_flip@modeset-vs-vblank-race: shard-glk: PASS -> FAIL (fdo#103060) igt@kms_flip_tiling@flip-to-y-tiled: shard-glk: PASS -> FAIL (fdo#104724) igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence: shard-hsw: PASS -> FAIL (fdo#103481) Possible fixes igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic: shard-glk: FAIL (fdo#106509, fdo#105454) -> PASS igt@kms_flip@2x-dpms-vs-vblank-race-interruptible: shard-hsw: FAIL (fdo#103060) -> PASS igt@kms_flip@2x-flip-vs-expired-vblank: shard-hsw: FAIL (fdo#102887) -> PASS igt@kms_flip@2x-flip-vs-fences: shard-glk: INCOMPLETE (k.org#198133, fdo#103359) -> PASS igt@kms_flip@plain-flip-ts-check-interruptible: shard-hsw: FAIL (fdo#100368) -> PASS igt@kms_setmode@basic: shard-apl: FAIL (fdo#99912) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#102670 https://bugs.freedesktop.org/show_bug.cgi?id=102670 fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887 fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481 fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454 fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4305 -> Patchwork_9271 CI_DRM_4305: d5ec1c93d19ce1fa4e23176828f4fb9a592f2609 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4515: a0f2d23b7d3d4226a0a7637a9240bfa86f08c1d3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9271: 41a63d5285996d98330dc484c08a6e93d6ae8ebc @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9271/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable P010, P012 and P016 formats for GLK/CNL (rev2)
== Series Details ==
Series: Enable P010, P012 and P016 formats for GLK/CNL (rev2)
URL : https://patchwork.freedesktop.org/series/43891/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c556cc92888f drm: Add P010, P012, P016 format definitions and fourcc
-:28: WARNING:LONG_LINE: line over 100 characters
#28: FILE: drivers/gpu/drm/drm_fourcc.c:176:
+ { .format = DRM_FORMAT_P010,.depth = 0,
.num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
-:29: WARNING:LONG_LINE: line over 100 characters
#29: FILE: drivers/gpu/drm/drm_fourcc.c:177:
+ { .format = DRM_FORMAT_P012,.depth = 0,
.num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
-:30: WARNING:LONG_LINE: line over 100 characters
#30: FILE: drivers/gpu/drm/drm_fourcc.c:178:
+ { .format = DRM_FORMAT_P016,.depth = 0,
.num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
-:48: WARNING:LONG_LINE_COMMENT: line over 100 characters
#48: FILE: include/uapi/drm/drm_fourcc.h:150:
+#define DRM_FORMAT_P010fourcc_code('P', '0', '1', '0') /* 2x2
subsampled Cr:Cb plane, 10 bit per channel */
-:49: WARNING:LONG_LINE_COMMENT: line over 100 characters
#49: FILE: include/uapi/drm/drm_fourcc.h:151:
+#define DRM_FORMAT_P012fourcc_code('P', '0', '1', '2') /* 2x2
subsampled Cr:Cb plane, 12 bit per channel */
-:50: WARNING:LONG_LINE_COMMENT: line over 100 characters
#50: FILE: include/uapi/drm/drm_fourcc.h:152:
+#define DRM_FORMAT_P016fourcc_code('P', '0', '1', '6') /* 2x2
subsampled Cr:Cb plane, 16 bit per channel */
total: 0 errors, 6 warnings, 0 checks, 25 lines checked
ffaf900fc205 drm/i915: Add P010, P012, P016 plane control definitions
-:19: ERROR:SPACING: space prohibited after that open parenthesis '('
#19: FILE: drivers/gpu/drm/i915/i915_reg.h:6381:
+#define PLANE_CTL_FORMAT_P010( 3 << 24)
-:21: ERROR:SPACING: space prohibited after that open parenthesis '('
#21: FILE: drivers/gpu/drm/i915/i915_reg.h:6383:
+#define PLANE_CTL_FORMAT_P012( 5 << 24)
-:23: ERROR:SPACING: space prohibited after that open parenthesis '('
#23: FILE: drivers/gpu/drm/i915/i915_reg.h:6385:
+#define PLANE_CTL_FORMAT_P016( 7 << 24)
total: 3 errors, 0 warnings, 0 checks, 11 lines checked
13b5a18b2a3f drm/i915: preparations for enabling P010, P012, P016 formats
-:136: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#136: FILE: drivers/gpu/drm/i915/intel_display.c:14492:
+
drm_get_format_name(mode_cmd->pixel_format,
+ _name));
-:142: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#142: FILE: drivers/gpu/drm/i915/intel_display.c:14498:
+
drm_get_format_name(mode_cmd->pixel_format,
+ _name));
total: 0 errors, 0 warnings, 2 checks, 236 lines checked
b9090703ea04 drm/i915: enable P010, P012, P016 formats for primary and sprite
planes
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Make closing request flush mandatory
== Series Details == Series: drm/i915: Make closing request flush mandatory URL : https://patchwork.freedesktop.org/series/44614/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4305 -> Patchwork_9273 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/44614/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_9273 that come from known issues: === IGT changes === Issues hit igt@gem_exec_gttfill@basic: fi-byt-n2820: PASS -> FAIL (fdo#106744) igt@gem_exec_suspend@basic-s4-devices: fi-hsw-peppy: PASS -> FAIL (fdo#105900) fi-kbl-7500u: PASS -> DMESG-WARN (fdo#105128) igt@kms_flip@basic-flip-vs-wf_vblank: fi-glk-j4005: PASS -> FAIL (fdo#100368) Possible fixes igt@gem_exec_suspend@basic-s3: fi-skl-gvtdvm: INCOMPLETE (fdo#105600, fdo#104108) -> PASS igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: DMESG-WARN (fdo#106607) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108 fdo#105128 https://bugs.freedesktop.org/show_bug.cgi?id=105128 fdo#105600 https://bugs.freedesktop.org/show_bug.cgi?id=105600 fdo#105900 https://bugs.freedesktop.org/show_bug.cgi?id=105900 fdo#106607 https://bugs.freedesktop.org/show_bug.cgi?id=106607 fdo#106744 https://bugs.freedesktop.org/show_bug.cgi?id=106744 == Participating hosts (42 -> 37) == Missing(5): fi-byt-j1900 fi-ctg-p8600 fi-ilk-m540 fi-bsw-cyan fi-skl-6700hq == Build changes == * Linux: CI_DRM_4305 -> Patchwork_9273 CI_DRM_4305: d5ec1c93d19ce1fa4e23176828f4fb9a592f2609 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4515: a0f2d23b7d3d4226a0a7637a9240bfa86f08c1d3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9273: f0774d6ad9407317c3b116b68be17d91c18b98ff @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == f0774d6ad940 drm/i915: Make closing request flush mandatory == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9273/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 1/4] drm: Add P010, P012, P016 format definitions and fourcc
Add P010 definition, semi-planar yuv format where each component
is 16 bits 10 msb containing color value. First come Y plane [10:6]
followed by 2x2 subsampled Cr:Cb plane [10:6:10:6]
Add P012 definition, semi-planar yuv format where each component
is 16 bits 12 msb containing color value. First come Y plane [12:4]
followed by 2x2 subsampled Cr:Cb plane [12:4:12:4]
Add P016 definition, semi-planar yuv format where each component
is 16 bits. First come Y plane followed by 2x2 subsampled Cr:Cb
plane [16:16]
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/drm_fourcc.c | 3 +++
include/uapi/drm/drm_fourcc.h | 10 ++
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 5ca6395..5bb2641 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -173,6 +173,9 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_UYVY,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
{ .format = DRM_FORMAT_VYUY,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
{ .format = DRM_FORMAT_AYUV,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
+ { .format = DRM_FORMAT_P010,.depth = 0,
.num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
+ { .format = DRM_FORMAT_P012,.depth = 0,
.num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
+ { .format = DRM_FORMAT_P016,.depth = 0,
.num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
};
unsigned int i;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 64bf67a..16f7dbd 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -142,6 +142,16 @@ extern "C" {
#define DRM_FORMAT_NV42fourcc_code('N', 'V', '4', '2') /*
non-subsampled Cb:Cr plane */
/*
+ * 2 plane YCbCr
+ * index 0 = Y plane, [15:0] Y little endian where Pxxx indicate
+ * component xxx msb Y [xxx:16-xxx]
+ * index 1 = Cr:Cb plane, [31:0] Cr:Cb little endian [xxx:16-xxx:xxx:16-xxx]
+ */
+#define DRM_FORMAT_P010fourcc_code('P', '0', '1', '0') /* 2x2
subsampled Cr:Cb plane, 10 bit per channel */
+#define DRM_FORMAT_P012fourcc_code('P', '0', '1', '2') /* 2x2
subsampled Cr:Cb plane, 12 bit per channel */
+#define DRM_FORMAT_P016fourcc_code('P', '0', '1', '6') /* 2x2
subsampled Cr:Cb plane, 16 bit per channel */
+
+/*
* 3 plane YCbCr
* index 0: Y plane, [7:0] Y
* index 1: Cb plane, [7:0] Cb
--
2.7.4
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[Intel-gfx] [PATCH v2 4/4] drm/i915: enable P010, P012, P016 formats for primary and sprite planes
Enabling of P010, P012 and P016 formats. These formats will
extend NV12 for larger bit depths.
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/intel_display.c | 24 +-
drivers/gpu/drm/i915/intel_sprite.c | 39 +++-
2 files changed, 61 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 728684c..84bdd39 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -104,6 +104,25 @@ static const uint32_t skl_pri_planar_formats[] = {
DRM_FORMAT_NV12,
};
+static const uint32_t glk_primary_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_NV12,
+ DRM_FORMAT_P010,
+ DRM_FORMAT_P012,
+ DRM_FORMAT_P016,
+};
+
static const uint64_t skl_format_modifiers_noccs[] = {
I915_FORMAT_MOD_Yf_TILED,
I915_FORMAT_MOD_Y_TILED,
@@ -13635,7 +13654,10 @@ intel_primary_plane_create(struct drm_i915_private
*dev_priv, enum pipe pipe)
primary->has_ccs = skl_plane_has_ccs(dev_priv, pipe,
PLANE_PRIMARY);
- if (skl_plane_has_planar(dev_priv, pipe, PLANE_PRIMARY)) {
+ if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
+ intel_primary_formats = glk_primary_formats;
+ num_formats = ARRAY_SIZE(glk_primary_formats);
+ } else if (skl_plane_has_planar(dev_priv, pipe, PLANE_PRIMARY))
{
intel_primary_formats = skl_pri_planar_formats;
num_formats = ARRAY_SIZE(skl_pri_planar_formats);
} else {
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 61b6bd7..c238017 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1297,6 +1297,22 @@ static uint32_t skl_planar_formats[] = {
DRM_FORMAT_NV12,
};
+static uint32_t glk_planar_formats[] = {
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_NV12,
+ DRM_FORMAT_P010,
+ DRM_FORMAT_P012,
+ DRM_FORMAT_P016,
+};
+
static const uint64_t skl_plane_format_modifiers_noccs[] = {
I915_FORMAT_MOD_Yf_TILED,
I915_FORMAT_MOD_Y_TILED,
@@ -1542,7 +1558,28 @@ intel_sprite_plane_create(struct drm_i915_private
*dev_priv,
}
intel_plane->base.state = >base;
- if (INTEL_GEN(dev_priv) >= 9) {
+ if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
+ intel_plane->can_scale = true;
+ state->scaler_id = -1;
+
+ intel_plane->update_plane = skl_update_plane;
+ intel_plane->disable_plane = skl_disable_plane;
+ intel_plane->get_hw_state = skl_plane_get_hw_state;
+
+ if (skl_plane_has_planar(dev_priv, pipe,
+PLANE_SPRITE0 + plane)) {
+ plane_formats = glk_planar_formats;
+ num_plane_formats = ARRAY_SIZE(glk_planar_formats);
+ } else {
+ plane_formats = skl_plane_formats;
+ num_plane_formats = ARRAY_SIZE(skl_plane_formats);
+ }
+
+ if (skl_plane_has_ccs(dev_priv, pipe, PLANE_SPRITE0 + plane))
+ modifiers = skl_plane_format_modifiers_ccs;
+ else
+ modifiers = skl_plane_format_modifiers_noccs;
+ } else if (INTEL_GEN(dev_priv) >= 9) {
intel_plane->can_scale = true;
state->scaler_id = -1;
--
2.7.4
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[Intel-gfx] [PATCH v2 3/4] drm/i915: preparations for enabling P010, P012, P016 formats
Preparations for enabling P010, P012 and P016 formats. These
formats will extend NV12 for larger bit depths.
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/intel_atomic.c | 3 +-
drivers/gpu/drm/i915/intel_atomic_plane.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 46 +++
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 19 ++---
drivers/gpu/drm/i915/intel_sprite.c | 21 +-
6 files changed, 72 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_atomic.c
b/drivers/gpu/drm/i915/intel_atomic.c
index 61ddb58..d42624b 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -332,8 +332,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private
*dev_priv,
/* set scaler mode */
if ((INTEL_GEN(dev_priv) >= 9) &&
plane_state && plane_state->base.fb &&
- plane_state->base.fb->format->format ==
- DRM_FORMAT_NV12) {
+ is_planar_yuv_format(plane_state->base.fb->format->format))
{
if (INTEL_GEN(dev_priv) == 9 &&
!IS_GEMINILAKE(dev_priv) &&
!IS_SKYLAKE(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c
b/drivers/gpu/drm/i915/intel_atomic_plane.c
index e8bf4cc..5b08d53 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -182,7 +182,7 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
else
crtc_state->active_planes &= ~BIT(intel_plane->id);
- if (state->visible && state->fb->format->format == DRM_FORMAT_NV12)
+ if (state->visible && is_planar_yuv_format(state->fb->format->format))
crtc_state->nv12_planes |= BIT(intel_plane->id);
else
crtc_state->nv12_planes &= ~BIT(intel_plane->id);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 2c16c3a..728684c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2667,6 +2667,12 @@ int skl_format_to_fourcc(int format, bool rgb_order,
bool alpha)
return DRM_FORMAT_RGB565;
case PLANE_CTL_FORMAT_NV12:
return DRM_FORMAT_NV12;
+ case PLANE_CTL_FORMAT_P010:
+ return DRM_FORMAT_P010;
+ case PLANE_CTL_FORMAT_P012:
+ return DRM_FORMAT_P012;
+ case PLANE_CTL_FORMAT_P016:
+ return DRM_FORMAT_P016;
default:
case PLANE_CTL_FORMAT_XRGB_:
if (rgb_order) {
@@ -3182,7 +3188,7 @@ int skl_check_plane_surface(const struct intel_crtc_state
*crtc_state,
* Handle the AUX surface first since
* the main surface setup depends on it.
*/
- if (fb->format->format == DRM_FORMAT_NV12) {
+ if (is_planar_yuv_format(fb->format->format)) {
ret = skl_check_nv12_surface(crtc_state, plane_state);
if (ret)
return ret;
@@ -3507,6 +3513,12 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
case DRM_FORMAT_NV12:
return PLANE_CTL_FORMAT_NV12;
+ case DRM_FORMAT_P010:
+ return PLANE_CTL_FORMAT_P010;
+ case DRM_FORMAT_P012:
+ return PLANE_CTL_FORMAT_P012;
+ case DRM_FORMAT_P016:
+ return PLANE_CTL_FORMAT_P016;
default:
MISSING_CASE(pixel_format);
}
@@ -4808,8 +4820,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state,
bool force_detach,
need_scaling = src_w != dst_w || src_h != dst_h;
if (plane_scaler_check)
- if (pixel_format == DRM_FORMAT_NV12)
- need_scaling = true;
+ need_scaling = is_planar_yuv_format(pixel_format);
if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
need_scaling = true;
@@ -4850,7 +4861,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state,
bool force_detach,
return 0;
}
- if (plane_scaler_check && pixel_format == DRM_FORMAT_NV12 &&
+ if (plane_scaler_check && is_planar_yuv_format(pixel_format) &&
(src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
DRM_DEBUG_KMS("NV12: src dimensions not met\n");
return -EINVAL;
@@ -4955,6 +4966,9 @@ static int skl_update_scaler_plane(struct
intel_crtc_state *crtc_state,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_P010:
+ case DRM_FORMAT_P012:
+ case DRM_FORMAT_P016:
break;
default:
[Intel-gfx] [PATCH v2 2/4] drm/i915: Add P010, P012, P016 plane control definitions
Add needed plane control flag definitions for P010, P012 and
P016 formats.
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 987def2..9add270 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6378,8 +6378,11 @@ enum {
#define PLANE_CTL_FORMAT_YUV422 ( 0 << 24)
#define PLANE_CTL_FORMAT_NV12( 1 << 24)
#define PLANE_CTL_FORMAT_XRGB_2101010( 2 << 24)
+#define PLANE_CTL_FORMAT_P010( 3 << 24)
#define PLANE_CTL_FORMAT_XRGB_ ( 4 << 24)
+#define PLANE_CTL_FORMAT_P012( 5 << 24)
#define PLANE_CTL_FORMAT_XRGB_16161616F ( 6 << 24)
+#define PLANE_CTL_FORMAT_P016( 7 << 24)
#define PLANE_CTL_FORMAT_AYUV( 8 << 24)
#define PLANE_CTL_FORMAT_INDEXED ( 12 << 24)
#define PLANE_CTL_FORMAT_RGB_565 ( 14 << 24)
--
2.7.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 0/4] Enable P010, P012 and P016 formats for GLK/CNL
v2: Rebase and add better comment for Pxxx formats into drm_fourcc.h These patches enable P010, P012 and P016 formats for GLK and CNL. These formats are similar to NV12 extending from 8 bits per channel to 10, 12 and 16 bits per channel. For user space components there is in IGT kms_available_modes_crc test which can test these new modes, test need to be recompiled with DRM_FORMAT_Pxxx definitions in place. For VLC media player I've made KMS video out plugin which will be able to show these new modes. This vout plugin is still work in progress, first version of my plugin can be seen here: https://mailman.videolan.org/pipermail/vlc-devel/2018-May/119013.html Juha-Pekka Heikkila (4): drm: Add P010, P012, P016 format definitions and fourcc drm/i915: Add P010, P012, P016 plane control definitions drm/i915: preparations for enabling P010, P012, P016 formats drm/i915: enable P010, P012, P016 formats for primary and sprite planes drivers/gpu/drm/drm_fourcc.c | 3 ++ drivers/gpu/drm/i915/i915_reg.h | 3 ++ drivers/gpu/drm/i915/intel_atomic.c | 3 +- drivers/gpu/drm/i915/intel_atomic_plane.c | 2 +- drivers/gpu/drm/i915/intel_display.c | 70 +++ drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 19 - drivers/gpu/drm/i915/intel_sprite.c | 60 +- include/uapi/drm/drm_fourcc.h | 10 + 9 files changed, 149 insertions(+), 22 deletions(-) -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/2] drm/i915/gtt: Subclass gen6_hw_ppgtt
== Series Details == Series: series starting with [CI,1/2] drm/i915/gtt: Subclass gen6_hw_ppgtt URL : https://patchwork.freedesktop.org/series/44608/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4305_full -> Patchwork_9269_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9269_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9269_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9269_full: === IGT changes === Warnings igt@gem_exec_schedule@deep-bsd2: shard-kbl: SKIP -> PASS +2 igt@kms_cursor_legacy@cursora-vs-flipa-legacy: shard-snb: SKIP -> PASS +3 igt@perf_pmu@rc6: shard-kbl: PASS -> SKIP == Known issues == Here are the changes found in Patchwork_9269_full that come from known issues: === IGT changes === Issues hit igt@drv_selftest@live_gtt: shard-glk: PASS -> FAIL (fdo#105347) igt@kms_flip@2x-plain-flip-fb-recreate-interruptible: shard-glk: PASS -> FAIL (fdo#100368) Possible fixes igt@drv_suspend@shrink: shard-hsw: INCOMPLETE (fdo#103540) -> PASS igt@kms_flip@2x-dpms-vs-vblank-race-interruptible: shard-hsw: FAIL (fdo#103060) -> PASS igt@kms_flip@2x-flip-vs-fences: shard-glk: INCOMPLETE (k.org#198133, fdo#103359) -> PASS igt@kms_flip@plain-flip-fb-recreate-interruptible: shard-glk: FAIL (fdo#100368) -> PASS igt@kms_flip@plain-flip-ts-check-interruptible: shard-hsw: FAIL (fdo#100368) -> PASS igt@kms_flip_tiling@flip-x-tiled: shard-glk: FAIL (fdo#103822, fdo#104724) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540 fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 fdo#105347 https://bugs.freedesktop.org/show_bug.cgi?id=105347 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4305 -> Patchwork_9269 CI_DRM_4305: d5ec1c93d19ce1fa4e23176828f4fb9a592f2609 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4515: a0f2d23b7d3d4226a0a7637a9240bfa86f08c1d3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9269: 54d2388afdb0286a63716eff571a7cc4122b9f78 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9269/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v9 7/7] drm/i915: add a sysfs entry to let users set sseu configs
On 12/06/18 11:37, Chris Wilson wrote:
Quoting Lionel Landwerlin (2018-06-12 11:33:34)
On 12/06/18 10:20, Joonas Lahtinen wrote:
Quoting Chris Wilson (2018-06-11 18:02:37)
Quoting Lionel Landwerlin (2018-06-11 14:46:07)
On 11/06/18 13:10, Tvrtko Ursulin wrote:
On 30/05/2018 15:33, Lionel Landwerlin wrote:
There are concerns about denial of service around the per context sseu
configuration capability. In a previous commit introducing the
capability we allowed it only for capable users. This changes adds a
new debugfs entry to let any user configure its own context
powergating setup.
As far as I understood it, Joonas' concerns here are:
1) That in the containers use case individual containers wouldn't be
able to turn on the sysfs toggle for them.
2) That also in the containers use case if box admin turns on the
feature, some containers would potentially start negatively affecting
the others (via the accumulated cost of slice re-configuration on
context switching).
I am not familiar with typical container setups to be authoritative
here, but intuitively I find it reasonable that a low-level hardware
switch like this would be under the control of a master domain
administrator. ("If you are installing our product in the container
environment, make sure your system administrator enables this hardware
feature.", "Note to system administrators: Enabling this features may
negatively affect the performance of other containers.")
Alternative proposal is for the i915 to apply an "or" filter on all
requested masks and in that way ensure dynamic re-configuration
doesn't happen on context switches, but driven from userspace via ioctls.
In other words, should _all_ userspace agree between themselves that
they want to turn off a slice, they would then need to send out a
concerted ioctl storm, where number of needed ioctls equals the number
of currently active contexts. (This may have its own performance
consequences caused by the barriers needed to modify all context images.)
This was deemed acceptable the the media use case, but my concern is
the approach is not elegant and will tie us with the "or" policy in
the ABI. (Performance concerns I haven't evaluated yet, but they also
may be significant.)
If we go back thinking about the containers use case, then it
transpires that even though the "or" policy does prevent one container
from affecting the other from one angle, it also prevents one
container from exercising the feature unless all containers co-operate.
As such, we can view the original problem statement where we have an
issue if not everyone co-operates, as conceptually the same just from
an opposite angle. (Rather than one container incurring the increased
cost of context switches to the rest, we would have one container
preventing the optimized slice configuration to the other.)
From this follows that both proposals require complete co-operation
from all running userspace to avoid complete control of the feature.
Since the balance between the benefit of optimized slice configuration
(or penalty of suboptimal one), versus the penalty of increased
context switch times, cannot be know by the driver (barring venturing
into the heuristics territory), that is another reason why I find the
"or" policy in the driver questionable.
We can also ask a question of - If we go with the "or" policy, why
require N per-context ioctls to modify the global GPU configuration
and not instead add a global driver ioctl to modify the state?
If a future hardware requires, or enables, the per-context behaviour
in a more efficient way, we could then revisit the problem space.
In the mean time I see the "or" policy solution as adding some ABI
which doesn't do anything for many use cases without any way for the
sysadmin to enable it. At the same time master sysfs knob at least
enables the sysadmin to make a decision. Here I am thinking about a
random client environment where not all userspace co-operates, but for
instance user is running the feature aware media stack, and
non-feature aware OpenCL/3d stack.
I guess the complete story boils down to - is the master sysfs knob
really a problem in container use cases.
Regards,
Tvrtko
Hey Tvrtko,
Thanks for summarizing a bunch of discussions.
Essentially I agree with every you wrote above.
If we have a global setting (determined by the OR policy), what's the
point of per context settings?
In Dmitry's scenario, all userspace applications will work together to
reach the consensus so it sounds like we're reimplementing the policy
that is already existing in userspace.
Anyway, I'm implementing Joonas' suggestion. Hopefully somebody else
than me pick one or the other :)
I'll just mention the voting/consensus approach to see if anyone else
likes it.
Each context has a CONTEXT_PARAM_HINT_SSEU { small, dontcare, large }
(or some other abstract names).
Yeah, the param name should have the word _HINT_ in it when it's not a
definitive set.
There's no global setter across
[Intel-gfx] [PATCH] drm/i915: Make closing request flush mandatory
For symmetry, simplicity and ensuring the request is always truly idle
upon its completion, always emit the closing flush prior to emitting the
request breadcrumb. Previously, we would only emit the flush if we had
started a user batch, but this just leaves all the other paths open to
speculation (do they affect the GPU caches or not?) With mm switching, a
key requirement is that the GPU is flushed and invalidated before hand,
so for absolute safety, we want that closing flush be mandatory.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c| 4 ++--
drivers/gpu/drm/i915/i915_gem_context.c| 9 +
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 4 ++--
drivers/gpu/drm/i915/i915_request.c| 18 ++
drivers/gpu/drm/i915/i915_request.h| 4 +---
drivers/gpu/drm/i915/selftests/huge_pages.c| 2 +-
.../drm/i915/selftests/i915_gem_coherency.c| 4 ++--
.../gpu/drm/i915/selftests/i915_gem_context.c | 4 ++--
drivers/gpu/drm/i915/selftests/i915_request.c | 2 +-
.../gpu/drm/i915/selftests/intel_hangcheck.c | 16
drivers/gpu/drm/i915/selftests/intel_lrc.c | 2 +-
.../gpu/drm/i915/selftests/intel_workarounds.c | 2 +-
12 files changed, 24 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 93efd92362db..8dd4d35655af 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3213,7 +3213,7 @@ void i915_gem_reset(struct drm_i915_private *dev_priv,
rq = i915_request_alloc(engine,
dev_priv->kernel_context);
if (!IS_ERR(rq))
- __i915_request_add(rq, false);
+ i915_request_add(rq);
}
}
@@ -5332,7 +5332,7 @@ static int __intel_engines_record_defaults(struct
drm_i915_private *i915)
if (engine->init_context)
err = engine->init_context(rq);
- __i915_request_add(rq, true);
+ i915_request_add(rq);
if (err)
goto err_active;
}
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index b2c7ac1b074d..ef6ea4bcd773 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -700,14 +700,7 @@ int i915_gem_switch_to_kernel_context(struct
drm_i915_private *i915)
i915_timeline_sync_set(rq->timeline, >fence);
}
- /*
-* Force a flush after the switch to ensure that all rendering
-* and operations prior to switching to the kernel context hits
-* memory. This should be guaranteed by the previous request,
-* but an extra layer of paranoia before we declare the system
-* idle (on suspend etc) is advisable!
-*/
- __i915_request_add(rq, true);
+ i915_request_add(rq);
}
return 0;
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 2d2eb3075960..60dc2a865f5f 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -921,7 +921,7 @@ static void reloc_gpu_flush(struct reloc_cache *cache)
i915_gem_object_unpin_map(cache->rq->batch->obj);
i915_gem_chipset_flush(cache->rq->i915);
- __i915_request_add(cache->rq, true);
+ i915_request_add(cache->rq);
cache->rq = NULL;
}
@@ -2438,7 +2438,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
trace_i915_request_queue(eb.request, eb.batch_flags);
err = eb_submit();
err_request:
- __i915_request_add(eb.request, err == 0);
+ i915_request_add(eb.request);
add_to_client(eb.request, file);
if (fences)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 9092f5464c24..e1dbb544046f 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -1018,14 +1018,13 @@ i915_request_await_object(struct i915_request *to,
* request is not being tracked for completion but the work itself is
* going to happen on the hardware. This would be a Bad Thing(tm).
*/
-void __i915_request_add(struct i915_request *request, bool flush_caches)
+void i915_request_add(struct i915_request *request)
{
struct intel_engine_cs *engine = request->engine;
struct i915_timeline *timeline = request->timeline;
struct intel_ring *ring = request->ring;
struct i915_request *prev;
u32 *cs;
- int err;
GEM_TRACE("%s fence %llx:%d\n",
engine->name, request->fence.context, request->fence.seqno);
@@ -1046,20 +1045,7 @@ void
Re: [Intel-gfx] [PATCH v9 7/7] drm/i915: add a sysfs entry to let users set sseu configs
Quoting Lionel Landwerlin (2018-06-12 11:33:34)
> On 12/06/18 10:20, Joonas Lahtinen wrote:
> > Quoting Chris Wilson (2018-06-11 18:02:37)
> >> Quoting Lionel Landwerlin (2018-06-11 14:46:07)
> >>> On 11/06/18 13:10, Tvrtko Ursulin wrote:
> On 30/05/2018 15:33, Lionel Landwerlin wrote:
> > There are concerns about denial of service around the per context sseu
> > configuration capability. In a previous commit introducing the
> > capability we allowed it only for capable users. This changes adds a
> > new debugfs entry to let any user configure its own context
> > powergating setup.
> As far as I understood it, Joonas' concerns here are:
>
> 1) That in the containers use case individual containers wouldn't be
> able to turn on the sysfs toggle for them.
>
> 2) That also in the containers use case if box admin turns on the
> feature, some containers would potentially start negatively affecting
> the others (via the accumulated cost of slice re-configuration on
> context switching).
>
> I am not familiar with typical container setups to be authoritative
> here, but intuitively I find it reasonable that a low-level hardware
> switch like this would be under the control of a master domain
> administrator. ("If you are installing our product in the container
> environment, make sure your system administrator enables this hardware
> feature.", "Note to system administrators: Enabling this features may
> negatively affect the performance of other containers.")
>
> Alternative proposal is for the i915 to apply an "or" filter on all
> requested masks and in that way ensure dynamic re-configuration
> doesn't happen on context switches, but driven from userspace via ioctls.
>
> In other words, should _all_ userspace agree between themselves that
> they want to turn off a slice, they would then need to send out a
> concerted ioctl storm, where number of needed ioctls equals the number
> of currently active contexts. (This may have its own performance
> consequences caused by the barriers needed to modify all context images.)
>
> This was deemed acceptable the the media use case, but my concern is
> the approach is not elegant and will tie us with the "or" policy in
> the ABI. (Performance concerns I haven't evaluated yet, but they also
> may be significant.)
>
> If we go back thinking about the containers use case, then it
> transpires that even though the "or" policy does prevent one container
> from affecting the other from one angle, it also prevents one
> container from exercising the feature unless all containers co-operate.
>
> As such, we can view the original problem statement where we have an
> issue if not everyone co-operates, as conceptually the same just from
> an opposite angle. (Rather than one container incurring the increased
> cost of context switches to the rest, we would have one container
> preventing the optimized slice configuration to the other.)
>
> From this follows that both proposals require complete co-operation
> from all running userspace to avoid complete control of the feature.
>
> Since the balance between the benefit of optimized slice configuration
> (or penalty of suboptimal one), versus the penalty of increased
> context switch times, cannot be know by the driver (barring venturing
> into the heuristics territory), that is another reason why I find the
> "or" policy in the driver questionable.
>
> We can also ask a question of - If we go with the "or" policy, why
> require N per-context ioctls to modify the global GPU configuration
> and not instead add a global driver ioctl to modify the state?
>
> If a future hardware requires, or enables, the per-context behaviour
> in a more efficient way, we could then revisit the problem space.
>
> In the mean time I see the "or" policy solution as adding some ABI
> which doesn't do anything for many use cases without any way for the
> sysadmin to enable it. At the same time master sysfs knob at least
> enables the sysadmin to make a decision. Here I am thinking about a
> random client environment where not all userspace co-operates, but for
> instance user is running the feature aware media stack, and
> non-feature aware OpenCL/3d stack.
>
> I guess the complete story boils down to - is the master sysfs knob
> really a problem in container use cases.
>
> Regards,
>
> Tvrtko
> >>> Hey Tvrtko,
> >>>
> >>> Thanks for summarizing a bunch of discussions.
> >>> Essentially I agree with every you wrote above.
> >>>
> >>> If we have a global setting (determined by the OR policy), what's the
> >>> point of per context settings?
> >>>
> >>> In Dmitry's scenario,
Re: [Intel-gfx] [PATCH v9 7/7] drm/i915: add a sysfs entry to let users set sseu configs
On 12/06/18 10:20, Joonas Lahtinen wrote:
Quoting Chris Wilson (2018-06-11 18:02:37)
Quoting Lionel Landwerlin (2018-06-11 14:46:07)
On 11/06/18 13:10, Tvrtko Ursulin wrote:
On 30/05/2018 15:33, Lionel Landwerlin wrote:
There are concerns about denial of service around the per context sseu
configuration capability. In a previous commit introducing the
capability we allowed it only for capable users. This changes adds a
new debugfs entry to let any user configure its own context
powergating setup.
As far as I understood it, Joonas' concerns here are:
1) That in the containers use case individual containers wouldn't be
able to turn on the sysfs toggle for them.
2) That also in the containers use case if box admin turns on the
feature, some containers would potentially start negatively affecting
the others (via the accumulated cost of slice re-configuration on
context switching).
I am not familiar with typical container setups to be authoritative
here, but intuitively I find it reasonable that a low-level hardware
switch like this would be under the control of a master domain
administrator. ("If you are installing our product in the container
environment, make sure your system administrator enables this hardware
feature.", "Note to system administrators: Enabling this features may
negatively affect the performance of other containers.")
Alternative proposal is for the i915 to apply an "or" filter on all
requested masks and in that way ensure dynamic re-configuration
doesn't happen on context switches, but driven from userspace via ioctls.
In other words, should _all_ userspace agree between themselves that
they want to turn off a slice, they would then need to send out a
concerted ioctl storm, where number of needed ioctls equals the number
of currently active contexts. (This may have its own performance
consequences caused by the barriers needed to modify all context images.)
This was deemed acceptable the the media use case, but my concern is
the approach is not elegant and will tie us with the "or" policy in
the ABI. (Performance concerns I haven't evaluated yet, but they also
may be significant.)
If we go back thinking about the containers use case, then it
transpires that even though the "or" policy does prevent one container
from affecting the other from one angle, it also prevents one
container from exercising the feature unless all containers co-operate.
As such, we can view the original problem statement where we have an
issue if not everyone co-operates, as conceptually the same just from
an opposite angle. (Rather than one container incurring the increased
cost of context switches to the rest, we would have one container
preventing the optimized slice configuration to the other.)
From this follows that both proposals require complete co-operation
from all running userspace to avoid complete control of the feature.
Since the balance between the benefit of optimized slice configuration
(or penalty of suboptimal one), versus the penalty of increased
context switch times, cannot be know by the driver (barring venturing
into the heuristics territory), that is another reason why I find the
"or" policy in the driver questionable.
We can also ask a question of - If we go with the "or" policy, why
require N per-context ioctls to modify the global GPU configuration
and not instead add a global driver ioctl to modify the state?
If a future hardware requires, or enables, the per-context behaviour
in a more efficient way, we could then revisit the problem space.
In the mean time I see the "or" policy solution as adding some ABI
which doesn't do anything for many use cases without any way for the
sysadmin to enable it. At the same time master sysfs knob at least
enables the sysadmin to make a decision. Here I am thinking about a
random client environment where not all userspace co-operates, but for
instance user is running the feature aware media stack, and
non-feature aware OpenCL/3d stack.
I guess the complete story boils down to - is the master sysfs knob
really a problem in container use cases.
Regards,
Tvrtko
Hey Tvrtko,
Thanks for summarizing a bunch of discussions.
Essentially I agree with every you wrote above.
If we have a global setting (determined by the OR policy), what's the
point of per context settings?
In Dmitry's scenario, all userspace applications will work together to
reach the consensus so it sounds like we're reimplementing the policy
that is already existing in userspace.
Anyway, I'm implementing Joonas' suggestion. Hopefully somebody else
than me pick one or the other :)
I'll just mention the voting/consensus approach to see if anyone else
likes it.
Each context has a CONTEXT_PARAM_HINT_SSEU { small, dontcare, large }
(or some other abstract names).
Yeah, the param name should have the word _HINT_ in it when it's not a
definitive set.
There's no global setter across containers, only a scenario when
everyone agrees or not. Tallying up the votes and going
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: move towards kernel types (rev2)
== Series Details == Series: drm/i915: move towards kernel types (rev2) URL : https://patchwork.freedesktop.org/series/44610/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4305 -> Patchwork_9272 = == Summary - WARNING == Minor unknown changes coming with Patchwork_9272 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9272, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/44610/revisions/2/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9272: === IGT changes === Warnings igt@gem_exec_gttfill@basic: fi-pnv-d510:PASS -> SKIP == Known issues == Here are the changes found in Patchwork_9272 that come from known issues: === IGT changes === Issues hit igt@gem_exec_gttfill@basic: fi-byt-n2820: PASS -> FAIL (fdo#106744) igt@gem_exec_nop@basic-parallel: fi-glk-j4005: PASS -> DMESG-WARN (fdo#105719) igt@kms_flip@basic-flip-vs-modeset: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106000) igt@kms_flip@basic-flip-vs-wf_vblank: fi-glk-j4005: PASS -> FAIL (fdo#100368) fi-cfl-s3: PASS -> FAIL (fdo#103928, fdo#100368) fi-cnl-psr: PASS -> FAIL (fdo#103928, fdo#100368) igt@prime_vgem@basic-fence-flip: fi-ilk-650: PASS -> FAIL (fdo#104008) Possible fixes igt@debugfs_test@read_all_entries: fi-snb-2520m: INCOMPLETE (fdo#103713) -> PASS igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: DMESG-WARN (fdo#106607) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928 fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008 fdo#105719 https://bugs.freedesktop.org/show_bug.cgi?id=105719 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106607 https://bugs.freedesktop.org/show_bug.cgi?id=106607 fdo#106744 https://bugs.freedesktop.org/show_bug.cgi?id=106744 == Participating hosts (42 -> 36) == Missing(6): fi-ilk-m540 fi-skl-gvtdvm fi-bdw-gvtdvm fi-bsw-cyan fi-ctg-p8600 fi-skl-6700hq == Build changes == * Linux: CI_DRM_4305 -> Patchwork_9272 CI_DRM_4305: d5ec1c93d19ce1fa4e23176828f4fb9a592f2609 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4515: a0f2d23b7d3d4226a0a7637a9240bfa86f08c1d3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9272: 63e510d8cf5be48d1cd705797004da2b8cbf6ad9 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 63e510d8cf5b drm/i915/lspcon: switch to kernel unsigned int types f8db0d41ba91 drm/i915/audio: switch to kernel unsigned int types 63849ccfe923 drm/i915/backlight: switch to kernel unsigned int types ec9c81f7b3c8 drm/i915/dvo: switch to kernel unsigned int types d68815c38f9a drm/i915/uncore: switch to kernel unsigned int types f22e9c3948d6 drm/i915/hdmi: switch to kernel unsigned int types 4a7207fae0c9 drm/i915/vbt: switch to kernel unsigned int types == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9272/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: move towards kernel types (rev2)
== Series Details == Series: drm/i915: move towards kernel types (rev2) URL : https://patchwork.freedesktop.org/series/44610/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915/vbt: switch to kernel unsigned int types Okay! Commit: drm/i915/hdmi: switch to kernel unsigned int types Okay! Commit: drm/i915/uncore: switch to kernel unsigned int types Okay! Commit: drm/i915/dvo: switch to kernel unsigned int types Okay! Commit: drm/i915/backlight: switch to kernel unsigned int types Okay! Commit: drm/i915/audio: switch to kernel unsigned int types -O:drivers/gpu/drm/i915/intel_audio.c:278:15: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_audio.c:278:15: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_audio.c:457:15: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_audio.c:576:15: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_audio.c:278:15: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_audio.c:278:15: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_audio.c:457:15: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_audio.c:576:15: warning: expression using sizeof(void) Commit: drm/i915/lspcon: switch to kernel unsigned int types Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 0/7] drm/i915: move towards kernel types
On Tue, 12 Jun 2018, Tvrtko Ursulin wrote: > On 12/06/2018 10:19, Jani Nikula wrote: >> Semi-RFC. Do we want to do this? Here's a batch of conversions that shouldn't >> conflict much with in-flight patches. >> >> The trouble with mixed use is that it's inconsistent, and any remaining C99 >> types will encourage their use. We could at least do the low hanging fruit? > > Ack from me. Doesn't seem so big to cause much pain. > > When you say low-hanging fruit, that implies you only dealt with a > particular class of occurrences? I meant the files which don't have massive amounts of C99 types and aren't under active development right now. I just wanted to avoid trouble for starters. ;) > Also going forward we have to make sure we will be able to stop them > creeping back in. Is checkpatch perhaps covering this? Or we could put > something in dim? We can stop ignoring PREFER_KERNEL_TYPES in checkpatch (the ignores are in dim). We don't even have to change everything for that, we just need to change enough to make the S/N better. People tend to use the types near the places they change. BR, Jani. > > Regards, > > Tvrtko > >> $ git grep "uint\(8\|16\|32\|64\)_t" -- drivers/gpu/drm/i915/ | sed >> 's/:.*//' | sort | uniq -c | sort -n >> >> BR, >> Jani. >> >> >> Jani Nikula (7): >>drm/i915/vbt: switch to kernel unsigned int types >>drm/i915/hdmi: switch to kernel unsigned int types >>drm/i915/uncore: switch to kernel unsigned int types >>drm/i915/dvo: switch to kernel unsigned int types >>drm/i915/backlight: switch to kernel unsigned int types >>drm/i915/audio: switch to kernel unsigned int types >>drm/i915/lspcon: switch to kernel unsigned int types >> >> drivers/gpu/drm/i915/dvo_ch7017.c | 20 ++-- >> drivers/gpu/drm/i915/dvo_ch7xxx.c | 22 +++--- >> drivers/gpu/drm/i915/dvo_ivch.c | 26 >> drivers/gpu/drm/i915/dvo_ns2501.c | 44 >> +-- >> drivers/gpu/drm/i915/dvo_sil164.c | 10 +++--- >> drivers/gpu/drm/i915/dvo_tfp410.c | 16 +- >> drivers/gpu/drm/i915/intel_audio.c| 36 +++--- >> drivers/gpu/drm/i915/intel_bios.c | 4 +-- >> drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 12 >> drivers/gpu/drm/i915/intel_dvo.c | 2 +- >> drivers/gpu/drm/i915/intel_hdmi.c | 14 - >> drivers/gpu/drm/i915/intel_lspcon.c | 2 +- >> drivers/gpu/drm/i915/intel_panel.c| 8 ++--- >> drivers/gpu/drm/i915/intel_uncore.h | 22 +++--- >> drivers/gpu/drm/i915/intel_vbt_defs.h | 2 +- >> 15 files changed, 120 insertions(+), 120 deletions(-) >> -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: fix GEM_BUG_ON check (rev2)
== Series Details == Series: drm/i915/guc: fix GEM_BUG_ON check (rev2) URL : https://patchwork.freedesktop.org/series/44578/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4305 -> Patchwork_9271 = == Summary - WARNING == Minor unknown changes coming with Patchwork_9271 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9271, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/44578/revisions/2/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9271: === IGT changes === Warnings igt@gem_exec_gttfill@basic: fi-pnv-d510:PASS -> SKIP == Known issues == Here are the changes found in Patchwork_9271 that come from known issues: === IGT changes === Issues hit igt@kms_flip@basic-flip-vs-wf_vblank: fi-glk-j4005: PASS -> FAIL (fdo#100368) igt@kms_flip@basic-plain-flip: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106000) +1 igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence: fi-glk-j4005: PASS -> FAIL (fdo#103481) igt@kms_pipe_crc_basic@read-crc-pipe-c: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106097) Possible fixes igt@debugfs_test@read_all_entries: fi-snb-2520m: INCOMPLETE (fdo#103713) -> PASS igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: DMESG-WARN (fdo#106607) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481 fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097 fdo#106607 https://bugs.freedesktop.org/show_bug.cgi?id=106607 == Participating hosts (42 -> 38) == Missing(4): fi-ctg-p8600 fi-ilk-m540 fi-bsw-cyan fi-skl-6700hq == Build changes == * Linux: CI_DRM_4305 -> Patchwork_9271 CI_DRM_4305: d5ec1c93d19ce1fa4e23176828f4fb9a592f2609 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4515: a0f2d23b7d3d4226a0a7637a9240bfa86f08c1d3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9271: 41a63d5285996d98330dc484c08a6e93d6ae8ebc @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 41a63d528599 drm/i915/guc: fix GEM_BUG_ON check == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9271/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 0/7] drm/i915: move towards kernel types
On 12/06/2018 10:19, Jani Nikula wrote: Semi-RFC. Do we want to do this? Here's a batch of conversions that shouldn't conflict much with in-flight patches. The trouble with mixed use is that it's inconsistent, and any remaining C99 types will encourage their use. We could at least do the low hanging fruit? Ack from me. Doesn't seem so big to cause much pain. When you say low-hanging fruit, that implies you only dealt with a particular class of occurrences? Also going forward we have to make sure we will be able to stop them creeping back in. Is checkpatch perhaps covering this? Or we could put something in dim? Regards, Tvrtko $ git grep "uint\(8\|16\|32\|64\)_t" -- drivers/gpu/drm/i915/ | sed 's/:.*//' | sort | uniq -c | sort -n BR, Jani. Jani Nikula (7): drm/i915/vbt: switch to kernel unsigned int types drm/i915/hdmi: switch to kernel unsigned int types drm/i915/uncore: switch to kernel unsigned int types drm/i915/dvo: switch to kernel unsigned int types drm/i915/backlight: switch to kernel unsigned int types drm/i915/audio: switch to kernel unsigned int types drm/i915/lspcon: switch to kernel unsigned int types drivers/gpu/drm/i915/dvo_ch7017.c | 20 ++-- drivers/gpu/drm/i915/dvo_ch7xxx.c | 22 +++--- drivers/gpu/drm/i915/dvo_ivch.c | 26 drivers/gpu/drm/i915/dvo_ns2501.c | 44 +-- drivers/gpu/drm/i915/dvo_sil164.c | 10 +++--- drivers/gpu/drm/i915/dvo_tfp410.c | 16 +- drivers/gpu/drm/i915/intel_audio.c| 36 +++--- drivers/gpu/drm/i915/intel_bios.c | 4 +-- drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 12 drivers/gpu/drm/i915/intel_dvo.c | 2 +- drivers/gpu/drm/i915/intel_hdmi.c | 14 - drivers/gpu/drm/i915/intel_lspcon.c | 2 +- drivers/gpu/drm/i915/intel_panel.c| 8 ++--- drivers/gpu/drm/i915/intel_uncore.h | 22 +++--- drivers/gpu/drm/i915/intel_vbt_defs.h | 2 +- 15 files changed, 120 insertions(+), 120 deletions(-) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 4/7] drm/i915/dvo: switch to kernel unsigned int types
We have fairly mixed uintN_t vs. uN usage throughout the driver, but try
to stick to kernel types at least where it's more prevalent.
v2: fix checkpatch warning on indentation
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/dvo_ch7017.c | 20 +-
drivers/gpu/drm/i915/dvo_ch7xxx.c | 22 ++--
drivers/gpu/drm/i915/dvo_ivch.c | 26 +++
drivers/gpu/drm/i915/dvo_ns2501.c | 44 +++
drivers/gpu/drm/i915/dvo_sil164.c | 10 -
drivers/gpu/drm/i915/dvo_tfp410.c | 16 +++---
drivers/gpu/drm/i915/intel_dvo.c | 2 +-
7 files changed, 70 insertions(+), 70 deletions(-)
diff --git a/drivers/gpu/drm/i915/dvo_ch7017.c
b/drivers/gpu/drm/i915/dvo_ch7017.c
index 80b3e16cf48c..caac9942e1e3 100644
--- a/drivers/gpu/drm/i915/dvo_ch7017.c
+++ b/drivers/gpu/drm/i915/dvo_ch7017.c
@@ -159,7 +159,7 @@
#define CH7017_BANG_LIMIT_CONTROL 0x7f
struct ch7017_priv {
- uint8_t dummy;
+ u8 dummy;
};
static void ch7017_dump_regs(struct intel_dvo_device *dvo);
@@ -186,7 +186,7 @@ static bool ch7017_read(struct intel_dvo_device *dvo, u8
addr, u8 *val)
static bool ch7017_write(struct intel_dvo_device *dvo, u8 addr, u8 val)
{
- uint8_t buf[2] = { addr, val };
+ u8 buf[2] = { addr, val };
struct i2c_msg msg = {
.addr = dvo->slave_addr,
.flags = 0,
@@ -258,11 +258,11 @@ static void ch7017_mode_set(struct intel_dvo_device *dvo,
const struct drm_display_mode *mode,
const struct drm_display_mode *adjusted_mode)
{
- uint8_t lvds_pll_feedback_div, lvds_pll_vco_control;
- uint8_t outputs_enable, lvds_control_2, lvds_power_down;
- uint8_t horizontal_active_pixel_input;
- uint8_t horizontal_active_pixel_output, vertical_active_line_output;
- uint8_t active_input_line_output;
+ u8 lvds_pll_feedback_div, lvds_pll_vco_control;
+ u8 outputs_enable, lvds_control_2, lvds_power_down;
+ u8 horizontal_active_pixel_input;
+ u8 horizontal_active_pixel_output, vertical_active_line_output;
+ u8 active_input_line_output;
DRM_DEBUG_KMS("Registers before mode setting\n");
ch7017_dump_regs(dvo);
@@ -333,7 +333,7 @@ static void ch7017_mode_set(struct intel_dvo_device *dvo,
/* set the CH7017 power state */
static void ch7017_dpms(struct intel_dvo_device *dvo, bool enable)
{
- uint8_t val;
+ u8 val;
ch7017_read(dvo, CH7017_LVDS_POWER_DOWN, );
@@ -361,7 +361,7 @@ static void ch7017_dpms(struct intel_dvo_device *dvo, bool
enable)
static bool ch7017_get_hw_state(struct intel_dvo_device *dvo)
{
- uint8_t val;
+ u8 val;
ch7017_read(dvo, CH7017_LVDS_POWER_DOWN, );
@@ -373,7 +373,7 @@ static bool ch7017_get_hw_state(struct intel_dvo_device
*dvo)
static void ch7017_dump_regs(struct intel_dvo_device *dvo)
{
- uint8_t val;
+ u8 val;
#define DUMP(reg) \
do { \
diff --git a/drivers/gpu/drm/i915/dvo_ch7xxx.c
b/drivers/gpu/drm/i915/dvo_ch7xxx.c
index 7aeeffd2428b..397ac5233726 100644
--- a/drivers/gpu/drm/i915/dvo_ch7xxx.c
+++ b/drivers/gpu/drm/i915/dvo_ch7xxx.c
@@ -85,7 +85,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
static struct ch7xxx_id_struct {
- uint8_t vid;
+ u8 vid;
char *name;
} ch7xxx_ids[] = {
{ CH7011_VID, "CH7011" },
@@ -96,7 +96,7 @@ static struct ch7xxx_id_struct {
};
static struct ch7xxx_did_struct {
- uint8_t did;
+ u8 did;
char *name;
} ch7xxx_dids[] = {
{ CH7xxx_DID, "CH7XXX" },
@@ -107,7 +107,7 @@ struct ch7xxx_priv {
bool quiet;
};
-static char *ch7xxx_get_id(uint8_t vid)
+static char *ch7xxx_get_id(u8 vid)
{
int i;
@@ -119,7 +119,7 @@ static char *ch7xxx_get_id(uint8_t vid)
return NULL;
}
-static char *ch7xxx_get_did(uint8_t did)
+static char *ch7xxx_get_did(u8 did)
{
int i;
@@ -132,7 +132,7 @@ static char *ch7xxx_get_did(uint8_t did)
}
/** Reads an 8 bit register */
-static bool ch7xxx_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch)
+static bool ch7xxx_readb(struct intel_dvo_device *dvo, int addr, u8 *ch)
{
struct ch7xxx_priv *ch7xxx = dvo->dev_priv;
struct i2c_adapter *adapter = dvo->i2c_bus;
@@ -170,11 +170,11 @@ static bool ch7xxx_readb(struct intel_dvo_device *dvo,
int addr, uint8_t *ch)
}
/** Writes an 8 bit register */
-static bool ch7xxx_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch)
+static bool ch7xxx_writeb(struct intel_dvo_device *dvo, int addr, u8 ch)
{
struct ch7xxx_priv *ch7xxx = dvo->dev_priv;
struct i2c_adapter *adapter = dvo->i2c_bus;
- uint8_t out_buf[2];
+ u8 out_buf[2];
struct i2c_msg msg = {
.addr = dvo->slave_addr,
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: move towards kernel types
== Series Details == Series: drm/i915: move towards kernel types URL : https://patchwork.freedesktop.org/series/44610/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4305 -> Patchwork_9270 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/44610/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_9270 that come from known issues: === IGT changes === Issues hit igt@kms_flip@basic-flip-vs-modeset: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106000) igt@kms_flip@basic-flip-vs-wf_vblank: fi-glk-j4005: PASS -> FAIL (fdo#106724) igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence: fi-glk-j4005: PASS -> FAIL (fdo#103481) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-cnl-psr: PASS -> DMESG-WARN (fdo#104951) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c: fi-bxt-dsi: PASS -> INCOMPLETE (fdo#103927) Possible fixes igt@debugfs_test@read_all_entries: fi-snb-2520m: INCOMPLETE (fdo#103713) -> PASS igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: DMESG-WARN (fdo#106607) -> PASS fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481 fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106607 https://bugs.freedesktop.org/show_bug.cgi?id=106607 fdo#106724 https://bugs.freedesktop.org/show_bug.cgi?id=106724 == Participating hosts (42 -> 37) == Missing(5): fi-ctg-p8600 fi-bsw-cyan fi-ilk-m540 fi-skl-gvtdvm fi-skl-6700hq == Build changes == * Linux: CI_DRM_4305 -> Patchwork_9270 CI_DRM_4305: d5ec1c93d19ce1fa4e23176828f4fb9a592f2609 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4515: a0f2d23b7d3d4226a0a7637a9240bfa86f08c1d3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9270: 62b5ce446f23712cf857ecec728470f8cab2cc78 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 62b5ce446f23 drm/i915/lspcon: switch to kernel unsigned int types cb02e7d6517d drm/i915/audio: switch to kernel unsigned int types 295e98774483 drm/i915/backlight: switch to kernel unsigned int types 592d209523eb drm/i915/dvo: switch to kernel unsigned int types b67a03bc35e4 drm/i915/uncore: switch to kernel unsigned int types ba755792a04b drm/i915/hdmi: switch to kernel unsigned int types 5e5d04a1d33d drm/i915/vbt: switch to kernel unsigned int types == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9270/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH][V3] drm/i915/guc: fix GEM_BUG_ON check
From: Colin Ian King
The check for level being less than zero always false because flags
is currently unsigned and can never be negative. Fix this by making
level a s32.
Detected by CoverityScan, CID#1468363 ("Macro compares unsigned to 0")
Fixes: cb5d64e9f13e ("drm/i915/guc: Allow user to control default GuC logging")
Signed-off-by: Colin Ian King
---
V3: Make level s32 and add the missing Fixes: tag, thanks to Dan Carpenter and
Jani Nikula for correcting my mistakes
---
drivers/gpu/drm/i915/intel_guc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 116f4ccf1bbd..bdb1fab322bf 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -205,7 +205,7 @@ void intel_guc_fini(struct intel_guc *guc)
static u32 get_log_control_flags(void)
{
- u32 level = i915_modparams.guc_log_level;
+ s32 level = i915_modparams.guc_log_level;
u32 flags = 0;
GEM_BUG_ON(level < 0);
--
2.17.0
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: move towards kernel types
== Series Details == Series: drm/i915: move towards kernel types URL : https://patchwork.freedesktop.org/series/44610/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915/vbt: switch to kernel unsigned int types Okay! Commit: drm/i915/hdmi: switch to kernel unsigned int types Okay! Commit: drm/i915/uncore: switch to kernel unsigned int types Okay! Commit: drm/i915/dvo: switch to kernel unsigned int types Okay! Commit: drm/i915/backlight: switch to kernel unsigned int types Okay! Commit: drm/i915/audio: switch to kernel unsigned int types -O:drivers/gpu/drm/i915/intel_audio.c:278:15: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_audio.c:278:15: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_audio.c:457:15: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_audio.c:576:15: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_audio.c:278:15: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_audio.c:278:15: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_audio.c:457:15: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_audio.c:576:15: warning: expression using sizeof(void) Commit: drm/i915/lspcon: switch to kernel unsigned int types Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: move towards kernel types
== Series Details == Series: drm/i915: move towards kernel types URL : https://patchwork.freedesktop.org/series/44610/ State : warning == Summary == $ dim checkpatch origin/drm-tip 5e5d04a1d33d drm/i915/vbt: switch to kernel unsigned int types ba755792a04b drm/i915/hdmi: switch to kernel unsigned int types b67a03bc35e4 drm/i915/uncore: switch to kernel unsigned int types 592d209523eb drm/i915/dvo: switch to kernel unsigned int types -:289: WARNING:TABSTOP: Statements should start on a tabstop #289: FILE: drivers/gpu/drm/i915/dvo_ns2501.c:194: +u8 offset; -:290: WARNING:TABSTOP: Statements should start on a tabstop #290: FILE: drivers/gpu/drm/i915/dvo_ns2501.c:195: +u8 value; total: 0 errors, 2 warnings, 0 checks, 407 lines checked 295e98774483 drm/i915/backlight: switch to kernel unsigned int types cb02e7d6517d drm/i915/audio: switch to kernel unsigned int types 62b5ce446f23 drm/i915/lspcon: switch to kernel unsigned int types ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH][V2] drm/i915/guc: fix GEM_BUG_ON check
On Tue, 12 Jun 2018, Dan Carpenter wrote:
> On Mon, Jun 11, 2018 at 05:46:53PM +0100, Colin King wrote:
>> From: Colin Ian King
>>
>> The check for level being less than zero always false because flags
>> is currently unsigned and can never be negative. Fix this by making
>> flags a s32.
>>
>> Detected by CoverityScan, CID#1468363 ("Macro compares unsigned to 0")
>>
>> Signed-off-by: Colin Ian King
>>
>> ---
>> V2: Make flags s32 rather than remove the GEM_BUG_ON check, thanks to
>> Ville Syrjälä for spotting the mistake in my first attempt.
>> ---
>> drivers/gpu/drm/i915/intel_guc.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_guc.c
>> b/drivers/gpu/drm/i915/intel_guc.c
>> index 116f4ccf1bbd..fb31f5004bcf 100644
>> --- a/drivers/gpu/drm/i915/intel_guc.c
>> +++ b/drivers/gpu/drm/i915/intel_guc.c
>> @@ -206,7 +206,7 @@ void intel_guc_fini(struct intel_guc *guc)
>> static u32 get_log_control_flags(void)
>> {
>> u32 level = i915_modparams.guc_log_level;
>> -u32 flags = 0;
>> +s32 flags = 0;
>>
>> GEM_BUG_ON(level < 0);
>
> Only insane people use "s32" when it's not part of the hardware spec and
> you changed the wrong variable...
Yeah, int level.
Also,
Fixes: cb5d64e9f13e ("drm/i915/guc: Allow user to control default GuC logging")
BR,
Jani.
>
> regards,
> dan carpenter
>
--
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Re: [Intel-gfx] [PATCH v9 7/7] drm/i915: add a sysfs entry to let users set sseu configs
Quoting Chris Wilson (2018-06-11 18:02:37)
> Quoting Lionel Landwerlin (2018-06-11 14:46:07)
> > On 11/06/18 13:10, Tvrtko Ursulin wrote:
> > >
> > > On 30/05/2018 15:33, Lionel Landwerlin wrote:
> > >> There are concerns about denial of service around the per context sseu
> > >> configuration capability. In a previous commit introducing the
> > >> capability we allowed it only for capable users. This changes adds a
> > >> new debugfs entry to let any user configure its own context
> > >> powergating setup.
> > >
> > > As far as I understood it, Joonas' concerns here are:
> > >
> > > 1) That in the containers use case individual containers wouldn't be
> > > able to turn on the sysfs toggle for them.
> > >
> > > 2) That also in the containers use case if box admin turns on the
> > > feature, some containers would potentially start negatively affecting
> > > the others (via the accumulated cost of slice re-configuration on
> > > context switching).
> > >
> > > I am not familiar with typical container setups to be authoritative
> > > here, but intuitively I find it reasonable that a low-level hardware
> > > switch like this would be under the control of a master domain
> > > administrator. ("If you are installing our product in the container
> > > environment, make sure your system administrator enables this hardware
> > > feature.", "Note to system administrators: Enabling this features may
> > > negatively affect the performance of other containers.")
> > >
> > > Alternative proposal is for the i915 to apply an "or" filter on all
> > > requested masks and in that way ensure dynamic re-configuration
> > > doesn't happen on context switches, but driven from userspace via ioctls.
> > >
> > > In other words, should _all_ userspace agree between themselves that
> > > they want to turn off a slice, they would then need to send out a
> > > concerted ioctl storm, where number of needed ioctls equals the number
> > > of currently active contexts. (This may have its own performance
> > > consequences caused by the barriers needed to modify all context images.)
> > >
> > > This was deemed acceptable the the media use case, but my concern is
> > > the approach is not elegant and will tie us with the "or" policy in
> > > the ABI. (Performance concerns I haven't evaluated yet, but they also
> > > may be significant.)
> > >
> > > If we go back thinking about the containers use case, then it
> > > transpires that even though the "or" policy does prevent one container
> > > from affecting the other from one angle, it also prevents one
> > > container from exercising the feature unless all containers co-operate.
> > >
> > > As such, we can view the original problem statement where we have an
> > > issue if not everyone co-operates, as conceptually the same just from
> > > an opposite angle. (Rather than one container incurring the increased
> > > cost of context switches to the rest, we would have one container
> > > preventing the optimized slice configuration to the other.)
> > >
> > > From this follows that both proposals require complete co-operation
> > > from all running userspace to avoid complete control of the feature.
> > >
> > > Since the balance between the benefit of optimized slice configuration
> > > (or penalty of suboptimal one), versus the penalty of increased
> > > context switch times, cannot be know by the driver (barring venturing
> > > into the heuristics territory), that is another reason why I find the
> > > "or" policy in the driver questionable.
> > >
> > > We can also ask a question of - If we go with the "or" policy, why
> > > require N per-context ioctls to modify the global GPU configuration
> > > and not instead add a global driver ioctl to modify the state?
> > >
> > > If a future hardware requires, or enables, the per-context behaviour
> > > in a more efficient way, we could then revisit the problem space.
> > >
> > > In the mean time I see the "or" policy solution as adding some ABI
> > > which doesn't do anything for many use cases without any way for the
> > > sysadmin to enable it. At the same time master sysfs knob at least
> > > enables the sysadmin to make a decision. Here I am thinking about a
> > > random client environment where not all userspace co-operates, but for
> > > instance user is running the feature aware media stack, and
> > > non-feature aware OpenCL/3d stack.
> > >
> > > I guess the complete story boils down to - is the master sysfs knob
> > > really a problem in container use cases.
> > >
> > > Regards,
> > >
> > > Tvrtko
> >
> > Hey Tvrtko,
> >
> > Thanks for summarizing a bunch of discussions.
> > Essentially I agree with every you wrote above.
> >
> > If we have a global setting (determined by the OR policy), what's the
> > point of per context settings?
> >
> > In Dmitry's scenario, all userspace applications will work together to
> > reach the consensus so it sounds like we're reimplementing the policy
> > that is
[Intel-gfx] [PATCH 6/7] drm/i915/audio: switch to kernel unsigned int types
We have fairly mixed uintN_t vs. uN usage throughout the driver, but try
to stick to kernel types at least where it's more prevalent.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_audio.c | 36 ++--
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_audio.c
b/drivers/gpu/drm/i915/intel_audio.c
index 3ea566f99450..4e4c0ec44f35 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -198,13 +198,13 @@ static int audio_config_hdmi_get_n(const struct
intel_crtc_state *crtc_state,
}
static bool intel_eld_uptodate(struct drm_connector *connector,
- i915_reg_t reg_eldv, uint32_t bits_eldv,
- i915_reg_t reg_elda, uint32_t bits_elda,
+ i915_reg_t reg_eldv, u32 bits_eldv,
+ i915_reg_t reg_elda, u32 bits_elda,
i915_reg_t reg_edid)
{
struct drm_i915_private *dev_priv = to_i915(connector->dev);
- uint8_t *eld = connector->eld;
- uint32_t tmp;
+ u8 *eld = connector->eld;
+ u32 tmp;
int i;
tmp = I915_READ(reg_eldv);
@@ -218,7 +218,7 @@ static bool intel_eld_uptodate(struct drm_connector
*connector,
I915_WRITE(reg_elda, tmp);
for (i = 0; i < drm_eld_size(eld) / 4; i++)
- if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
+ if (I915_READ(reg_edid) != *((u32 *)eld + i))
return false;
return true;
@@ -229,7 +229,7 @@ static void g4x_audio_codec_disable(struct intel_encoder
*encoder,
const struct drm_connector_state
*old_conn_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- uint32_t eldv, tmp;
+ u32 eldv, tmp;
DRM_DEBUG_KMS("Disable audio codec\n");
@@ -251,9 +251,9 @@ static void g4x_audio_codec_enable(struct intel_encoder
*encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct drm_connector *connector = conn_state->connector;
- uint8_t *eld = connector->eld;
- uint32_t eldv;
- uint32_t tmp;
+ u8 *eld = connector->eld;
+ u32 eldv;
+ u32 tmp;
int len, i;
DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", eld[2]);
@@ -278,7 +278,7 @@ static void g4x_audio_codec_enable(struct intel_encoder
*encoder,
len = min(drm_eld_size(eld) / 4, len);
DRM_DEBUG_DRIVER("ELD size %d\n", len);
for (i = 0; i < len; i++)
- I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
+ I915_WRITE(G4X_HDMIW_HDMIEDID, *((u32 *)eld + i));
tmp = I915_READ(G4X_AUD_CNTL_ST);
tmp |= eldv;
@@ -393,7 +393,7 @@ static void hsw_audio_codec_disable(struct intel_encoder
*encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
enum pipe pipe = crtc->pipe;
- uint32_t tmp;
+ u32 tmp;
DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe));
@@ -426,8 +426,8 @@ static void hsw_audio_codec_enable(struct intel_encoder
*encoder,
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_connector *connector = conn_state->connector;
enum pipe pipe = crtc->pipe;
- const uint8_t *eld = connector->eld;
- uint32_t tmp;
+ const u8 *eld = connector->eld;
+ u32 tmp;
int len, i;
DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
@@ -456,7 +456,7 @@ static void hsw_audio_codec_enable(struct intel_encoder
*encoder,
/* Up to 84 bytes of hw ELD buffer */
len = min(drm_eld_size(eld), 84);
for (i = 0; i < len / 4; i++)
- I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((uint32_t *)eld + i));
+ I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((u32 *)eld + i));
/* ELD valid */
tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
@@ -477,7 +477,7 @@ static void ilk_audio_codec_disable(struct intel_encoder
*encoder,
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
enum pipe pipe = crtc->pipe;
enum port port = encoder->port;
- uint32_t tmp, eldv;
+ u32 tmp, eldv;
i915_reg_t aud_config, aud_cntrl_st2;
DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n",
@@ -524,8 +524,8 @@ static void ilk_audio_codec_enable(struct intel_encoder
*encoder,
struct drm_connector *connector = conn_state->connector;
enum pipe pipe = crtc->pipe;
enum port port = encoder->port;
- uint8_t *eld = connector->eld;
- uint32_t tmp, eldv;
+ u8 *eld = connector->eld;
+ u32 tmp, eldv;
int len, i;
i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st,
[Intel-gfx] [PATCH 7/7] drm/i915/lspcon: switch to kernel unsigned int types
We have fairly mixed uintN_t vs. uN usage throughout the driver, but try
to stick to kernel types at least where it's more prevalent.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_lspcon.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_lspcon.c
b/drivers/gpu/drm/i915/intel_lspcon.c
index 8ae8f42f430a..5dae16ccd9f1 100644
--- a/drivers/gpu/drm/i915/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/intel_lspcon.c
@@ -116,7 +116,7 @@ static int lspcon_change_mode(struct intel_lspcon *lspcon,
static bool lspcon_wake_native_aux_ch(struct intel_lspcon *lspcon)
{
- uint8_t rev;
+ u8 rev;
if (drm_dp_dpcd_readb(_to_intel_dp(lspcon)->aux, DP_DPCD_REV,
) != 1) {
--
2.11.0
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[Intel-gfx] [PATCH 1/7] drm/i915/vbt: switch to kernel unsigned int types
We have fairly mixed uintN_t vs. uN usage throughout the driver, but try
to stick to kernel types at least where it's more prevalent.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_bios.c | 4 ++--
drivers/gpu/drm/i915/intel_vbt_defs.h | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index 18b9e0444116..62a53eb89b6b 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -652,7 +652,7 @@ parse_edp(struct drm_i915_private *dev_priv, const struct
bdb_header *bdb)
}
if (bdb->version >= 173) {
- uint8_t vswing;
+ u8 vswing;
/* Don't read from VBT if module parameter has valid value*/
if (i915_modparams.edp_vswing) {
@@ -964,7 +964,7 @@ static int goto_next_sequence_v3(const u8 *data, int index,
int total)
* includes MIPI_SEQ_ELEM_END byte, excludes the final MIPI_SEQ_END
* byte.
*/
- size_of_sequence = *((const uint32_t *)(data + index));
+ size_of_sequence = *((const u32 *)(data + index));
index += 4;
seq_end = index + size_of_sequence;
diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h
b/drivers/gpu/drm/i915/intel_vbt_defs.h
index c132d0c3a500..5f2a9052a190 100644
--- a/drivers/gpu/drm/i915/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
@@ -454,7 +454,7 @@ struct bdb_general_definitions {
* number = (block_size - sizeof(bdb_general_definitions))/
* defs->child_dev_size;
*/
- uint8_t devices[0];
+ u8 devices[0];
} __packed;
/* Mask for DRRS / Panel Channel / SSC / BLT control bits extraction */
--
2.11.0
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[Intel-gfx] [PATCH 2/7] drm/i915/hdmi: switch to kernel unsigned int types
We have fairly mixed uintN_t vs. uN usage throughout the driver, but try
to stick to kernel types at least where it's more prevalent.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_hdmi.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 0ca4cc877520..6e3c4e27c65a 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -51,7 +51,7 @@ assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
{
struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
struct drm_i915_private *dev_priv = to_i915(dev);
- uint32_t enabled_bits;
+ u32 enabled_bits;
enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
@@ -144,7 +144,7 @@ static void g4x_write_infoframe(struct drm_encoder *encoder,
unsigned int type,
const void *frame, ssize_t len)
{
- const uint32_t *data = frame;
+ const u32 *data = frame;
struct drm_device *dev = encoder->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
u32 val = I915_READ(VIDEO_DIP_CTL);
@@ -199,7 +199,7 @@ static void ibx_write_infoframe(struct drm_encoder *encoder,
unsigned int type,
const void *frame, ssize_t len)
{
- const uint32_t *data = frame;
+ const u32 *data = frame;
struct drm_device *dev = encoder->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
@@ -259,7 +259,7 @@ static void cpt_write_infoframe(struct drm_encoder *encoder,
unsigned int type,
const void *frame, ssize_t len)
{
- const uint32_t *data = frame;
+ const u32 *data = frame;
struct drm_device *dev = encoder->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
@@ -317,7 +317,7 @@ static void vlv_write_infoframe(struct drm_encoder *encoder,
unsigned int type,
const void *frame, ssize_t len)
{
- const uint32_t *data = frame;
+ const u32 *data = frame;
struct drm_device *dev = encoder->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
@@ -376,7 +376,7 @@ static void hsw_write_infoframe(struct drm_encoder *encoder,
unsigned int type,
const void *frame, ssize_t len)
{
- const uint32_t *data = frame;
+ const u32 *data = frame;
struct drm_device *dev = encoder->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
@@ -442,7 +442,7 @@ static void intel_write_infoframe(struct drm_encoder
*encoder,
union hdmi_infoframe *frame)
{
struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
- uint8_t buffer[VIDEO_DIP_DATA_SIZE];
+ u8 buffer[VIDEO_DIP_DATA_SIZE];
ssize_t len;
/* see comment above for the reason for this offset */
--
2.11.0
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[Intel-gfx] [PATCH 3/7] drm/i915/uncore: switch to kernel unsigned int types
We have fairly mixed uintN_t vs. uN usage throughout the driver, but try
to stick to kernel types at least where it's more prevalent.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_uncore.h | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.h
b/drivers/gpu/drm/i915/intel_uncore.h
index 47478d609630..2fbe93178fb2 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -67,21 +67,21 @@ struct intel_uncore_funcs {
void (*force_wake_put)(struct drm_i915_private *dev_priv,
enum forcewake_domains domains);
- uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv,
- i915_reg_t r, bool trace);
- uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv,
- i915_reg_t r, bool trace);
- uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv,
- i915_reg_t r, bool trace);
- uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv,
- i915_reg_t r, bool trace);
+ u8 (*mmio_readb)(struct drm_i915_private *dev_priv,
+i915_reg_t r, bool trace);
+ u16 (*mmio_readw)(struct drm_i915_private *dev_priv,
+ i915_reg_t r, bool trace);
+ u32 (*mmio_readl)(struct drm_i915_private *dev_priv,
+ i915_reg_t r, bool trace);
+ u64 (*mmio_readq)(struct drm_i915_private *dev_priv,
+ i915_reg_t r, bool trace);
void (*mmio_writeb)(struct drm_i915_private *dev_priv,
- i915_reg_t r, uint8_t val, bool trace);
+ i915_reg_t r, u8 val, bool trace);
void (*mmio_writew)(struct drm_i915_private *dev_priv,
- i915_reg_t r, uint16_t val, bool trace);
+ i915_reg_t r, u16 val, bool trace);
void (*mmio_writel)(struct drm_i915_private *dev_priv,
- i915_reg_t r, uint32_t val, bool trace);
+ i915_reg_t r, u32 val, bool trace);
};
struct intel_forcewake_range {
--
2.11.0
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[Intel-gfx] [PATCH 4/7] drm/i915/dvo: switch to kernel unsigned int types
We have fairly mixed uintN_t vs. uN usage throughout the driver, but try
to stick to kernel types at least where it's more prevalent.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/dvo_ch7017.c | 20 +-
drivers/gpu/drm/i915/dvo_ch7xxx.c | 22 ++--
drivers/gpu/drm/i915/dvo_ivch.c | 26 +++
drivers/gpu/drm/i915/dvo_ns2501.c | 44 +++
drivers/gpu/drm/i915/dvo_sil164.c | 10 -
drivers/gpu/drm/i915/dvo_tfp410.c | 16 +++---
drivers/gpu/drm/i915/intel_dvo.c | 2 +-
7 files changed, 70 insertions(+), 70 deletions(-)
diff --git a/drivers/gpu/drm/i915/dvo_ch7017.c
b/drivers/gpu/drm/i915/dvo_ch7017.c
index 80b3e16cf48c..caac9942e1e3 100644
--- a/drivers/gpu/drm/i915/dvo_ch7017.c
+++ b/drivers/gpu/drm/i915/dvo_ch7017.c
@@ -159,7 +159,7 @@
#define CH7017_BANG_LIMIT_CONTROL 0x7f
struct ch7017_priv {
- uint8_t dummy;
+ u8 dummy;
};
static void ch7017_dump_regs(struct intel_dvo_device *dvo);
@@ -186,7 +186,7 @@ static bool ch7017_read(struct intel_dvo_device *dvo, u8
addr, u8 *val)
static bool ch7017_write(struct intel_dvo_device *dvo, u8 addr, u8 val)
{
- uint8_t buf[2] = { addr, val };
+ u8 buf[2] = { addr, val };
struct i2c_msg msg = {
.addr = dvo->slave_addr,
.flags = 0,
@@ -258,11 +258,11 @@ static void ch7017_mode_set(struct intel_dvo_device *dvo,
const struct drm_display_mode *mode,
const struct drm_display_mode *adjusted_mode)
{
- uint8_t lvds_pll_feedback_div, lvds_pll_vco_control;
- uint8_t outputs_enable, lvds_control_2, lvds_power_down;
- uint8_t horizontal_active_pixel_input;
- uint8_t horizontal_active_pixel_output, vertical_active_line_output;
- uint8_t active_input_line_output;
+ u8 lvds_pll_feedback_div, lvds_pll_vco_control;
+ u8 outputs_enable, lvds_control_2, lvds_power_down;
+ u8 horizontal_active_pixel_input;
+ u8 horizontal_active_pixel_output, vertical_active_line_output;
+ u8 active_input_line_output;
DRM_DEBUG_KMS("Registers before mode setting\n");
ch7017_dump_regs(dvo);
@@ -333,7 +333,7 @@ static void ch7017_mode_set(struct intel_dvo_device *dvo,
/* set the CH7017 power state */
static void ch7017_dpms(struct intel_dvo_device *dvo, bool enable)
{
- uint8_t val;
+ u8 val;
ch7017_read(dvo, CH7017_LVDS_POWER_DOWN, );
@@ -361,7 +361,7 @@ static void ch7017_dpms(struct intel_dvo_device *dvo, bool
enable)
static bool ch7017_get_hw_state(struct intel_dvo_device *dvo)
{
- uint8_t val;
+ u8 val;
ch7017_read(dvo, CH7017_LVDS_POWER_DOWN, );
@@ -373,7 +373,7 @@ static bool ch7017_get_hw_state(struct intel_dvo_device
*dvo)
static void ch7017_dump_regs(struct intel_dvo_device *dvo)
{
- uint8_t val;
+ u8 val;
#define DUMP(reg) \
do { \
diff --git a/drivers/gpu/drm/i915/dvo_ch7xxx.c
b/drivers/gpu/drm/i915/dvo_ch7xxx.c
index 7aeeffd2428b..397ac5233726 100644
--- a/drivers/gpu/drm/i915/dvo_ch7xxx.c
+++ b/drivers/gpu/drm/i915/dvo_ch7xxx.c
@@ -85,7 +85,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
static struct ch7xxx_id_struct {
- uint8_t vid;
+ u8 vid;
char *name;
} ch7xxx_ids[] = {
{ CH7011_VID, "CH7011" },
@@ -96,7 +96,7 @@ static struct ch7xxx_id_struct {
};
static struct ch7xxx_did_struct {
- uint8_t did;
+ u8 did;
char *name;
} ch7xxx_dids[] = {
{ CH7xxx_DID, "CH7XXX" },
@@ -107,7 +107,7 @@ struct ch7xxx_priv {
bool quiet;
};
-static char *ch7xxx_get_id(uint8_t vid)
+static char *ch7xxx_get_id(u8 vid)
{
int i;
@@ -119,7 +119,7 @@ static char *ch7xxx_get_id(uint8_t vid)
return NULL;
}
-static char *ch7xxx_get_did(uint8_t did)
+static char *ch7xxx_get_did(u8 did)
{
int i;
@@ -132,7 +132,7 @@ static char *ch7xxx_get_did(uint8_t did)
}
/** Reads an 8 bit register */
-static bool ch7xxx_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch)
+static bool ch7xxx_readb(struct intel_dvo_device *dvo, int addr, u8 *ch)
{
struct ch7xxx_priv *ch7xxx = dvo->dev_priv;
struct i2c_adapter *adapter = dvo->i2c_bus;
@@ -170,11 +170,11 @@ static bool ch7xxx_readb(struct intel_dvo_device *dvo,
int addr, uint8_t *ch)
}
/** Writes an 8 bit register */
-static bool ch7xxx_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch)
+static bool ch7xxx_writeb(struct intel_dvo_device *dvo, int addr, u8 ch)
{
struct ch7xxx_priv *ch7xxx = dvo->dev_priv;
struct i2c_adapter *adapter = dvo->i2c_bus;
- uint8_t out_buf[2];
+ u8 out_buf[2];
struct i2c_msg msg = {
.addr = dvo->slave_addr,
.flags = 0,
@@ -201,7 +201,7 @@ static
[Intel-gfx] [PATCH 0/7] drm/i915: move towards kernel types
Semi-RFC. Do we want to do this? Here's a batch of conversions that shouldn't conflict much with in-flight patches. The trouble with mixed use is that it's inconsistent, and any remaining C99 types will encourage their use. We could at least do the low hanging fruit? $ git grep "uint\(8\|16\|32\|64\)_t" -- drivers/gpu/drm/i915/ | sed 's/:.*//' | sort | uniq -c | sort -n BR, Jani. Jani Nikula (7): drm/i915/vbt: switch to kernel unsigned int types drm/i915/hdmi: switch to kernel unsigned int types drm/i915/uncore: switch to kernel unsigned int types drm/i915/dvo: switch to kernel unsigned int types drm/i915/backlight: switch to kernel unsigned int types drm/i915/audio: switch to kernel unsigned int types drm/i915/lspcon: switch to kernel unsigned int types drivers/gpu/drm/i915/dvo_ch7017.c | 20 ++-- drivers/gpu/drm/i915/dvo_ch7xxx.c | 22 +++--- drivers/gpu/drm/i915/dvo_ivch.c | 26 drivers/gpu/drm/i915/dvo_ns2501.c | 44 +-- drivers/gpu/drm/i915/dvo_sil164.c | 10 +++--- drivers/gpu/drm/i915/dvo_tfp410.c | 16 +- drivers/gpu/drm/i915/intel_audio.c| 36 +++--- drivers/gpu/drm/i915/intel_bios.c | 4 +-- drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 12 drivers/gpu/drm/i915/intel_dvo.c | 2 +- drivers/gpu/drm/i915/intel_hdmi.c | 14 - drivers/gpu/drm/i915/intel_lspcon.c | 2 +- drivers/gpu/drm/i915/intel_panel.c| 8 ++--- drivers/gpu/drm/i915/intel_uncore.h | 22 +++--- drivers/gpu/drm/i915/intel_vbt_defs.h | 2 +- 15 files changed, 120 insertions(+), 120 deletions(-) -- 2.11.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/7] drm/i915/backlight: switch to kernel unsigned int types
We have fairly mixed uintN_t vs. uN usage throughout the driver, but try
to stick to kernel types at least where it's more prevalent.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 12 ++--
drivers/gpu/drm/i915/intel_panel.c| 8
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
index 2bb2ceb9d463..357136f17f85 100644
--- a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
@@ -26,7 +26,7 @@
static void set_aux_backlight_enable(struct intel_dp *intel_dp, bool enable)
{
- uint8_t reg_val = 0;
+ u8 reg_val = 0;
/* Early return when display use other mechanism to enable backlight. */
if (!(intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP))
@@ -54,11 +54,11 @@ static void set_aux_backlight_enable(struct intel_dp
*intel_dp, bool enable)
* Read the current backlight value from DPCD register(s) based
* on if 8-bit(MSB) or 16-bit(MSB and LSB) values are supported
*/
-static uint32_t intel_dp_aux_get_backlight(struct intel_connector *connector)
+static u32 intel_dp_aux_get_backlight(struct intel_connector *connector)
{
struct intel_dp *intel_dp = enc_to_intel_dp(>encoder->base);
- uint8_t read_val[2] = { 0x0 };
- uint16_t level = 0;
+ u8 read_val[2] = { 0x0 };
+ u16 level = 0;
if (drm_dp_dpcd_read(_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB,
_val, sizeof(read_val)) < 0) {
@@ -82,7 +82,7 @@ intel_dp_aux_set_backlight(const struct drm_connector_state
*conn_state, u32 lev
{
struct intel_connector *connector =
to_intel_connector(conn_state->connector);
struct intel_dp *intel_dp = enc_to_intel_dp(>encoder->base);
- uint8_t vals[2] = { 0x0 };
+ u8 vals[2] = { 0x0 };
vals[0] = level;
@@ -178,7 +178,7 @@ static void intel_dp_aux_enable_backlight(const struct
intel_crtc_state *crtc_st
{
struct intel_connector *connector =
to_intel_connector(conn_state->connector);
struct intel_dp *intel_dp = enc_to_intel_dp(>encoder->base);
- uint8_t dpcd_buf, new_dpcd_buf, edp_backlight_mode;
+ u8 dpcd_buf, new_dpcd_buf, edp_backlight_mode;
if (drm_dp_dpcd_readb(_dp->aux,
DP_EDP_BACKLIGHT_MODE_SET_REGISTER, _buf) != 1) {
diff --git a/drivers/gpu/drm/i915/intel_panel.c
b/drivers/gpu/drm/i915/intel_panel.c
index b443278e569c..14b827ec5427 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -406,11 +406,11 @@ intel_panel_detect(struct drm_i915_private *dev_priv)
* Return @source_val in range [@source_min..@source_max] scaled to range
* [@target_min..@target_max].
*/
-static uint32_t scale(uint32_t source_val,
- uint32_t source_min, uint32_t source_max,
- uint32_t target_min, uint32_t target_max)
+static u32 scale(u32 source_val,
+u32 source_min, u32 source_max,
+u32 target_min, u32 target_max)
{
- uint64_t target_val;
+ u64 target_val;
WARN_ON(source_min > source_max);
WARN_ON(target_min > target_max);
--
2.11.0
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915/gtt: Subclass gen6_hw_ppgtt
== Series Details == Series: series starting with [CI,1/2] drm/i915/gtt: Subclass gen6_hw_ppgtt URL : https://patchwork.freedesktop.org/series/44608/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4305 -> Patchwork_9269 = == Summary - WARNING == Minor unknown changes coming with Patchwork_9269 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9269, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/44608/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9269: === IGT changes === Warnings igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-glk-j4005: PASS -> SKIP == Known issues == Here are the changes found in Patchwork_9269 that come from known issues: === IGT changes === Issues hit igt@gem_exec_gttfill@basic: fi-byt-n2820: PASS -> FAIL (fdo#106744) igt@kms_flip@basic-flip-vs-modeset: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106000) igt@kms_flip@basic-flip-vs-wf_vblank: fi-glk-j4005: PASS -> FAIL (fdo#100368) igt@kms_flip@basic-plain-flip: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106097) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c: fi-cnl-psr: PASS -> DMESG-WARN (fdo#104951) Possible fixes igt@debugfs_test@read_all_entries: fi-snb-2520m: INCOMPLETE (fdo#103713) -> PASS igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: DMESG-WARN (fdo#106607) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097 fdo#106607 https://bugs.freedesktop.org/show_bug.cgi?id=106607 fdo#106744 https://bugs.freedesktop.org/show_bug.cgi?id=106744 == Participating hosts (42 -> 38) == Missing(4): fi-ctg-p8600 fi-ilk-m540 fi-bsw-cyan fi-skl-6700hq == Build changes == * Linux: CI_DRM_4305 -> Patchwork_9269 CI_DRM_4305: d5ec1c93d19ce1fa4e23176828f4fb9a592f2609 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4515: a0f2d23b7d3d4226a0a7637a9240bfa86f08c1d3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9269: 54d2388afdb0286a63716eff571a7cc4122b9f78 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 54d2388afdb0 drm/i915/gtt: Onionify error handling for gen6_ppgtt_create 07d34d2c2ba7 drm/i915/gtt: Subclass gen6_hw_ppgtt == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9269/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH][V2] drm/i915/guc: fix GEM_BUG_ON check
On Mon, Jun 11, 2018 at 05:46:53PM +0100, Colin King wrote:
> From: Colin Ian King
>
> The check for level being less than zero always false because flags
> is currently unsigned and can never be negative. Fix this by making
> flags a s32.
>
> Detected by CoverityScan, CID#1468363 ("Macro compares unsigned to 0")
>
> Signed-off-by: Colin Ian King
>
> ---
> V2: Make flags s32 rather than remove the GEM_BUG_ON check, thanks to
> Ville Syrjälä for spotting the mistake in my first attempt.
> ---
> drivers/gpu/drm/i915/intel_guc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_guc.c
> b/drivers/gpu/drm/i915/intel_guc.c
> index 116f4ccf1bbd..fb31f5004bcf 100644
> --- a/drivers/gpu/drm/i915/intel_guc.c
> +++ b/drivers/gpu/drm/i915/intel_guc.c
> @@ -206,7 +206,7 @@ void intel_guc_fini(struct intel_guc *guc)
> static u32 get_log_control_flags(void)
> {
> u32 level = i915_modparams.guc_log_level;
> - u32 flags = 0;
> + s32 flags = 0;
>
> GEM_BUG_ON(level < 0);
Only insane people use "s32" when it's not part of the hardware spec and
you changed the wrong variable...
regards,
dan carpenter
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[Intel-gfx] [PULL] drm-misc-fixes
Hey, Only the qxl fix by Jeremy Cline is new. The rest has landed in v4.17 already. drm-misc-fixes-2018-06-12: Only a small qxl fix that was queued for v4.17. The following changes since commit 9a0e9802217291e54c4dd1fc5462f189a4be14ec: drm/vc4: Fix scaling of uni-planar formats (2018-05-09 09:48:23 +0200) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-fixes-2018-06-12 for you to fetch changes up to 889ad63d41eea20184b0483e7e585e5b20fb6cfe: drm/qxl: Call qxl_bo_unref outside atomic context (2018-06-04 09:31:39 +0200) Only a small qxl fix that was queued for v4.17. Dan Carpenter (1): drm/dumb-buffers: Integer overflow in drm_mode_create_ioctl() Dhinakaran Pandiyan (1): drm/psr: Fix missed entry in PSR setup time table. Eric Anholt (1): drm/vc4: Fix leak of the file_priv that stored the perfmon. Haneen Mohammed (1): drm: Match sysfs name in link removal to link creation Jeremy Cline (1): drm/qxl: Call qxl_bo_unref outside atomic context Neil Armstrong (1): drm/bridge/synopsys: dw-hdmi: fix dw_hdmi_setup_rx_sense Tomi Valkeinen (1): drm/omap: fix NULL deref crash with SDI displays drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 15 --- drivers/gpu/drm/drm_dp_helper.c | 1 + drivers/gpu/drm/drm_drv.c | 2 +- drivers/gpu/drm/drm_dumb_buffers.c| 7 --- drivers/gpu/drm/meson/meson_dw_hdmi.c | 2 +- drivers/gpu/drm/omapdrm/dss/sdi.c | 5 - drivers/gpu/drm/qxl/qxl_display.c | 7 +-- drivers/gpu/drm/vc4/vc4_drv.c | 1 + include/drm/bridge/dw_hdmi.h | 2 +- 9 files changed, 22 insertions(+), 20 deletions(-) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/psr: Adds psrwake options for all platforms
On Tue, 12 Jun 2018, vathsala nagaraju wrote:
> From: Vathsala Nagaraju
>
> Adds new psrwake options defined in the below table.
> Platform PSR wake options vbt version
> KBL/CFL/WHL All
> SKL All PV releases (Check for 203+ might help but cannot be
> foolproof)
> BXT Uses old interpretation.
> CNL/ICL+ All
> GLK All
>
> For SKL, we will continue to use older interpretation for the above reason.
>
> Cc: Jani Nikula
> Cc: Rodrigo Vivi
> Cc: Puthikorn Voravootivat
> Cc: Dhinakaran Pandiyan
>
> Signed-off-by: Vathsala Nagaraju
> ---
> drivers/gpu/drm/i915/intel_bios.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_bios.c
> b/drivers/gpu/drm/i915/intel_bios.c
> index 465dff4..010ff68 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -710,7 +710,8 @@ static int intel_bios_ssc_frequency(struct
> drm_i915_private *dev_priv,
>* New psr options 0=500us, 1=100us, 2=2500us, 3=0us
>* Old decimal value is wake up time in multiples of 100 us.
>*/
> - if (bdb->version >= 209 && IS_GEN9_BC(dev_priv)) {
> + if ((INTEL_GEN(dev_priv) >= 10) ||
> + (IS_GEN9_BC(dev_priv) && !IS_SKYLAKE(dev_priv))) {
Please keep the version check.
Please tell anyone who asks, and also those who don't, that *all* of the
VBT changes should be based on the *version*, and *none* of them should
be based on the *platform*.
BR,
Jani.
> switch (psr_table->tp1_wakeup_time) {
> case 0:
> dev_priv->vbt.psr.tp1_wakeup_time_us = 500;
--
Jani Nikula, Intel Open Source Graphics Center
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/2] drm/i915/gtt: Subclass gen6_hw_ppgtt
== Series Details == Series: series starting with [CI,1/2] drm/i915/gtt: Subclass gen6_hw_ppgtt URL : https://patchwork.freedesktop.org/series/44608/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915/gtt: Subclass gen6_hw_ppgtt -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1649:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1649:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1708:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1708:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:1709:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:1709:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1852:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1852:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1970:9: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/i915_gem_gtt.c:1970:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:1853:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:1853:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:1970:9: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:1970:9: warning: expression using sizeof(void) Commit: drm/i915/gtt: Onionify error handling for gen6_ppgtt_create Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/2] drm/i915/gtt: Subclass gen6_hw_ppgtt
== Series Details == Series: series starting with [CI,1/2] drm/i915/gtt: Subclass gen6_hw_ppgtt URL : https://patchwork.freedesktop.org/series/44608/ State : warning == Summary == $ dim checkpatch origin/drm-tip 07d34d2c2ba7 drm/i915/gtt: Subclass gen6_hw_ppgtt -:290: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'base' - possible side-effects? #290: FILE: drivers/gpu/drm/i915/i915_gem_gtt.h:417: +#define __to_gen6_ppgtt(base) container_of(base, struct gen6_hw_ppgtt, base) total: 0 errors, 0 warnings, 1 checks, 294 lines checked 54d2388afdb0 drm/i915/gtt: Onionify error handling for gen6_ppgtt_create ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/2] drm/i915/icl: Add allowed DP rates for Icelake
On Mon, 11 Jun 2018, Paulo Zanoni wrote: > Em Seg, 2018-06-11 às 22:35 +, Patchwork escreveu: >> == Series Details == >> >> Series: series starting with [CI,1/2] drm/i915/icl: Add allowed DP >> rates for Icelake >> URL : https://patchwork.freedesktop.org/series/44595/ >> State : warning >> >> == Summary == >> >> $ dim checkpatch origin/drm-tip >> e6e6b2f7af58 drm/i915/icl: Add allowed DP rates for Icelake >> 3fe43cb729fe drm/i915/dp: Add support for HBR3 and TPS4 during link >> training >> -:26: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) >> #26: FILE: drivers/gpu/drm/i915/i915_reg.h:8694: >> +#define DP_TP_CTL_LINK_TRAIN_PAT4 (5<<8) > > Dear maintainers, > > I get this type of error way too often. What's the most desirable thing > here? > > 1 - Make it "(5 << 8)" so checkpatch doesn't complain, which will leave > the coding style inconsistent with the surrounding lines. I don't like the inconsistency. > 2 - Drive-by fix all the bits around it so everybody in the same > definition has nice spaces, 2.a: in the same patch, 2.b: in a separate > patch. Fine by me. Both a and b. I was kind of hoping this would have happened more. > 3 - Just ignore the checkpatch message, push code as-is. Also fine by me. > 4 - Blacklist this check from checkpatch. Unfortunately the SPACING class in checkpatch would silence much, much more than just this specific thing, so it would be a net negative. > 5 - Submit a separate patch fixing all the spacing errors on i915_reg.h > once and for all. Live happily ever after. It would be annoying for a while with conflicts, but I'd be fine. Not sure if it would be better to do it in some arbitrary chunks rather than mass change. > 6 - Submit a separate patch converting everything to BIT() on > i915_reg.h. Same as above. BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled (rev3)
== Series Details == Series: drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled (rev3) URL : https://patchwork.freedesktop.org/series/42459/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4304_full -> Patchwork_9268_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9268_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9268_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9268_full: === IGT changes === Warnings igt@gem_exec_schedule@deep-bsd2: shard-kbl: PASS -> SKIP igt@gem_exec_schedule@deep-vebox: shard-kbl: SKIP -> PASS == Known issues == Here are the changes found in Patchwork_9268_full that come from known issues: === IGT changes === Issues hit igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: shard-hsw: PASS -> FAIL (fdo#102887) igt@kms_setmode@basic: shard-kbl: PASS -> FAIL (fdo#99912) Possible fixes igt@drv_selftest@live_gtt: shard-kbl: FAIL (fdo#105347) -> PASS igt@drv_suspend@shrink: shard-hsw: INCOMPLETE (fdo#103540) -> PASS igt@kms_rotation_crc@sprite-rotation-180: shard-hsw: FAIL (fdo#103925, fdo#104724) -> PASS fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887 fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540 fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 fdo#105347 https://bugs.freedesktop.org/show_bug.cgi?id=105347 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (5 -> 4) == Missing(1): shard-glk == Build changes == * Linux: CI_DRM_4304 -> Patchwork_9268 CI_DRM_4304: 2313a1dc588ef63d9650ccbaaf576bc4b47dc255 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4515: a0f2d23b7d3d4226a0a7637a9240bfa86f08c1d3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9268: 7e66d7400ee9f80e00633e6cfdecc354dda8e049 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9268/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 2/2] drm/i915/gtt: Onionify error handling for gen6_ppgtt_create
Pull the empty stubs together into the top level gen6_ppgtt_create, and
tear each one down on error in proper onion order (rather than use
Joonas' pet hate of calling the cleanup function in indeterminable
state).
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
Reviewed-by: Matthew Auld
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 81 ++---
1 file changed, 39 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index cc0e747b9286..e9fcc4370b1a 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1875,7 +1875,7 @@ static int gen6_alloc_va_range(struct i915_address_space
*vm,
return -ENOMEM;
}
-static int gen6_init_scratch(struct i915_address_space *vm)
+static int gen6_ppgtt_init_scratch(struct i915_address_space *vm)
{
int ret;
@@ -1894,33 +1894,37 @@ static int gen6_init_scratch(struct i915_address_space
*vm)
return 0;
}
-static void gen6_free_scratch(struct i915_address_space *vm)
+static void gen6_ppgtt_free_scratch(struct i915_address_space *vm)
{
free_pt(vm, vm->scratch_pt);
cleanup_scratch_page(vm);
}
-static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
+static void gen6_ppgtt_free_pd(struct gen6_hw_ppgtt *ppgtt)
{
- struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(i915_vm_to_ppgtt(vm));
struct i915_page_table *pt;
u32 pde;
- drm_mm_remove_node(>node);
-
gen6_for_all_pdes(pt, >base.pd, pde)
- if (pt != vm->scratch_pt)
- free_pt(vm, pt);
+ if (pt != ppgtt->base.vm.scratch_pt)
+ free_pt(>base.vm, pt);
+}
- gen6_free_scratch(vm);
+static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
+{
+ struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(i915_vm_to_ppgtt(vm));
+
+ drm_mm_remove_node(>node);
+
+ gen6_ppgtt_free_pd(ppgtt);
+ gen6_ppgtt_free_scratch(vm);
}
static int gen6_ppgtt_allocate_page_directories(struct gen6_hw_ppgtt *ppgtt)
{
- struct i915_address_space *vm = >base.vm;
struct drm_i915_private *dev_priv = ppgtt->base.vm.i915;
struct i915_ggtt *ggtt = _priv->ggtt;
- int ret;
+ int err;
/* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
* allocator works in address space sizes, so it's multiplied by page
@@ -1928,17 +1932,13 @@ static int gen6_ppgtt_allocate_page_directories(struct
gen6_hw_ppgtt *ppgtt)
*/
BUG_ON(!drm_mm_initialized(>vm.mm));
- ret = gen6_init_scratch(vm);
- if (ret)
- return ret;
-
- ret = i915_gem_gtt_insert(>vm, >node,
+ err = i915_gem_gtt_insert(>vm, >node,
GEN6_PD_SIZE, GEN6_PD_ALIGN,
I915_COLOR_UNEVICTABLE,
0, ggtt->vm.total,
PIN_HIGH);
- if (ret)
- goto err_out;
+ if (err)
+ return err;
if (ppgtt->node.start < ggtt->mappable_end)
DRM_DEBUG("Forced to use aperture for PDEs\n");
@@ -1950,15 +1950,6 @@ static int gen6_ppgtt_allocate_page_directories(struct
gen6_hw_ppgtt *ppgtt)
ppgtt->base.pd.base.ggtt_offset / sizeof(gen6_pte_t);
return 0;
-
-err_out:
- gen6_free_scratch(vm);
- return ret;
-}
-
-static int gen6_ppgtt_alloc(struct gen6_hw_ppgtt *ppgtt)
-{
- return gen6_ppgtt_allocate_page_directories(ppgtt);
}
static void gen6_scratch_va_range(struct gen6_hw_ppgtt *ppgtt,
@@ -1984,21 +1975,8 @@ static struct i915_hw_ppgtt *gen6_ppgtt_create(struct
drm_i915_private *i915)
ppgtt->base.vm.i915 = i915;
ppgtt->base.vm.dma = >drm.pdev->dev;
- ppgtt->base.vm.pte_encode = ggtt->vm.pte_encode;
-
- err = gen6_ppgtt_alloc(ppgtt);
- if (err)
- goto err_free;
-
ppgtt->base.vm.total = I915_PDES * GEN6_PTES * PAGE_SIZE;
- gen6_scratch_va_range(ppgtt, 0, ppgtt->base.vm.total);
- gen6_write_page_range(>base, 0, ppgtt->base.vm.total);
-
- err = gen6_alloc_va_range(>base.vm, 0, ppgtt->base.vm.total);
- if (err)
- goto err_cleanup;
-
ppgtt->base.vm.clear_range = gen6_ppgtt_clear_range;
ppgtt->base.vm.insert_entries = gen6_ppgtt_insert_entries;
ppgtt->base.vm.cleanup = gen6_ppgtt_cleanup;
@@ -2009,6 +1987,23 @@ static struct i915_hw_ppgtt *gen6_ppgtt_create(struct
drm_i915_private *i915)
ppgtt->base.vm.vma_ops.set_pages = ppgtt_set_pages;
ppgtt->base.vm.vma_ops.clear_pages = clear_pages;
+ ppgtt->base.vm.pte_encode = ggtt->vm.pte_encode;
+
+ err = gen6_ppgtt_init_scratch(>base.vm);
+ if (err)
+ goto err_free;
+
+ err =
