Re: [Intel-gfx] [PATCH v2 13/23] drm/i915/dp: Do not enable PSR2 if DSC is enabled
On Tue, Jul 31, 2018 at 02:07:09PM -0700, Manasi Navare wrote:
> If a eDP panel supports both PSR2 and VDSC, our HW cannot
> support both at a time. Give priority to PSR2 if a requested
> resolution can be supported without compression else enable
> VDSC and keep PSR2 disabled.
what about PSR1 on PSR2 panels? could it be enabled with VSC?
or is there any restriction?
>
> Cc: Rodrigo Vivi
> Cc: Jani Nikula
> Cc: Ville Syrjälä
> Signed-off-by: Manasi Navare
> ---
> drivers/gpu/drm/i915/intel_psr.c | 10 ++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index 4bd5768..fdb028f 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -441,6 +441,16 @@ static bool intel_psr2_config_valid(struct intel_dp
> *intel_dp,
> if (!dev_priv->psr.sink_psr2_support)
> return false;
>
> + /*
> + * DSC and PSR2 cannot be enabled simultaneously. If a requested
> + * resolution requires DSC to be enabled, priority is given to DSC
> + * over PSR2.
> + */
> + if (crtc_state->dsc_params.compression_enable) {
> + DRM_DEBUG_KMS("PSR2 cannot be enabled since DSC is enabled\n");
> + return false;
> + }
one concern I had when I first saw this patch is the order, but
I saw that psr compute config is the last one inside dp compute config,
so we are good...
only "concern" now is about PSR1 restrictions.
But if not restriction with PSR1 and VSC:
Reviewed-by: Rodrigo Vivi
> +
> if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
> psr_max_h = 4096;
> psr_max_v = 2304;
> --
> 2.7.4
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/cfl: Add a new CFL PCI ID.
On Fri, Aug 03, 2018 at 04:40:56PM -0700, Souza, Jose wrote: > On Fri, 2018-08-03 at 16:27 -0700, Rodrigo Vivi wrote: > > One more CFL ID added to spec. > > > > Reviewed-by: José Roberto de Souza thanks, pushed... and patches to the rest of stack propagated. > > > Cc: José Roberto de Souza > > Signed-off-by: Rodrigo Vivi > > --- > > include/drm/i915_pciids.h | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h > > index fbf5cfc9b352..fd965ffbb92e 100644 > > --- a/include/drm/i915_pciids.h > > +++ b/include/drm/i915_pciids.h > > @@ -386,6 +386,7 @@ > > INTEL_VGA_DEVICE(0x3E91, info), /* SRV GT2 */ \ > > INTEL_VGA_DEVICE(0x3E92, info), /* SRV GT2 */ \ > > INTEL_VGA_DEVICE(0x3E96, info), /* SRV GT2 */ \ > > + INTEL_VGA_DEVICE(0x3E98, info), /* SRV GT2 */ \ > > INTEL_VGA_DEVICE(0x3E9A, info) /* SRV GT2 */ > > > > /* CFL H */ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [01/20] drm: Let userspace check if driver supports modeset
== Series Details == Series: series starting with [01/20] drm: Let userspace check if driver supports modeset URL : https://patchwork.freedesktop.org/series/47917/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4635_full -> Patchwork_9896_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9896_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9896_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9896_full: === IGT changes === Warnings igt@pm_rc6_residency@rc6-accuracy: shard-snb: SKIP -> PASS == Known issues == Here are the changes found in Patchwork_9896_full that come from known issues: === IGT changes === Issues hit igt@kms_rotation_crc@sprite-rotation-180: shard-hsw: PASS -> FAIL (fdo#103925) igt@perf_pmu@rc6-runtime-pm: shard-apl: PASS -> FAIL (fdo#105010) Possible fixes igt@gem_exec_await@wide-contexts: shard-apl: FAIL (fdo#106680, fdo#105900) -> PASS igt@gem_exec_reuse@single: shard-snb: INCOMPLETE (fdo#105411) -> PASS igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: shard-glk: FAIL (fdo#105363) -> PASS fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925 fdo#105010 https://bugs.freedesktop.org/show_bug.cgi?id=105010 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#105900 https://bugs.freedesktop.org/show_bug.cgi?id=105900 fdo#106680 https://bugs.freedesktop.org/show_bug.cgi?id=106680 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4635 -> Patchwork_9896 CI_DRM_4635: a9f34f7e3bab765e2b1320a1b154a76be38602a7 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4589: 779d2d42f9db6a2797d1ef50036af6fac4e62e73 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9896: b3ef168cf378f3302a530145c7f4aa5b9226e7c3 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9896/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gvt: fix memory leak in intel_vgpu_ioctl() (rev3)
== Series Details == Series: drm/i915/gvt: fix memory leak in intel_vgpu_ioctl() (rev3) URL : https://patchwork.freedesktop.org/series/47685/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4635_full -> Patchwork_9895_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9895_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9895_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9895_full: === IGT changes === Warnings igt@perf_pmu@rc6: shard-kbl: PASS -> SKIP == Known issues == Here are the changes found in Patchwork_9895_full that come from known issues: === IGT changes === Issues hit igt@kms_cursor_legacy@flip-vs-cursor-atomic: shard-glk: PASS -> FAIL (fdo#102670) igt@kms_rotation_crc@sprite-rotation-90: shard-apl: PASS -> FAIL (fdo#103925) Possible fixes igt@gem_exec_await@wide-contexts: shard-apl: FAIL (fdo#105900, fdo#106680) -> PASS igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: shard-glk: FAIL (fdo#105363) -> PASS fdo#102670 https://bugs.freedesktop.org/show_bug.cgi?id=102670 fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105900 https://bugs.freedesktop.org/show_bug.cgi?id=105900 fdo#106680 https://bugs.freedesktop.org/show_bug.cgi?id=106680 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4635 -> Patchwork_9895 CI_DRM_4635: a9f34f7e3bab765e2b1320a1b154a76be38602a7 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4589: 779d2d42f9db6a2797d1ef50036af6fac4e62e73 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9895: 0346e934b498e4ad48ea35e6465a2baa0e5fa8a3 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9895/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Re-apply "Perform link quality check, unconditionally during long pulse" (rev3)
== Series Details == Series: drm/i915: Re-apply "Perform link quality check, unconditionally during long pulse" (rev3) URL : https://patchwork.freedesktop.org/series/47694/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4635_full -> Patchwork_9894_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9894_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9894_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9894_full: === IGT changes === Warnings igt@perf_pmu@other-init-3: shard-kbl: PASS -> SKIP +5 == Known issues == Here are the changes found in Patchwork_9894_full that come from known issues: === IGT changes === Issues hit igt@drv_suspend@shrink: shard-kbl: PASS -> DMESG-WARN (fdo#106684) igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic: shard-glk: PASS -> FAIL (fdo#104873) igt@kms_setmode@basic: shard-apl: PASS -> FAIL (fdo#99912) igt@perf@enable-disable: shard-kbl: PASS -> DMESG-FAIL (fdo#106064, fdo#106684) igt@perf_pmu@rc6-runtime-pm: shard-glk: PASS -> FAIL (fdo#105010) Possible fixes igt@gem_exec_await@wide-contexts: shard-apl: FAIL (fdo#105900, fdo#106680) -> PASS igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: shard-glk: FAIL (fdo#105363) -> PASS fdo#104873 https://bugs.freedesktop.org/show_bug.cgi?id=104873 fdo#105010 https://bugs.freedesktop.org/show_bug.cgi?id=105010 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105900 https://bugs.freedesktop.org/show_bug.cgi?id=105900 fdo#106064 https://bugs.freedesktop.org/show_bug.cgi?id=106064 fdo#106680 https://bugs.freedesktop.org/show_bug.cgi?id=106680 fdo#106684 https://bugs.freedesktop.org/show_bug.cgi?id=106684 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4635 -> Patchwork_9894 CI_DRM_4635: a9f34f7e3bab765e2b1320a1b154a76be38602a7 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4589: 779d2d42f9db6a2797d1ef50036af6fac4e62e73 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9894: c8a6ddc5b49269876fdbda9f2d58f28d4694070a @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9894/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: remove the unnecessary restriction for NV12 in intel_framebuffer_init
== Series Details == Series: drm/i915: remove the unnecessary restriction for NV12 in intel_framebuffer_init URL : https://patchwork.freedesktop.org/series/47909/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4635_full -> Patchwork_9893_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9893_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9893_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9893_full: === IGT changes === Warnings igt@kms_cursor_crc@cursor-256x256-rapid-movement: shard-snb: PASS -> SKIP +2 igt@pm_rc6_residency@rc6-accuracy: shard-snb: SKIP -> PASS == Known issues == Here are the changes found in Patchwork_9893_full that come from known issues: === IGT changes === Issues hit igt@kms_setmode@basic: shard-apl: PASS -> FAIL (fdo#99912) igt@perf@polling: shard-hsw: PASS -> FAIL (fdo#102252) igt@perf_pmu@rc6-runtime-pm: shard-glk: PASS -> FAIL (fdo#105010) Possible fixes igt@gem_exec_await@wide-contexts: shard-apl: FAIL (fdo#106680, fdo#105900) -> PASS igt@kms_setmode@basic: shard-kbl: FAIL (fdo#99912) -> PASS fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 fdo#105010 https://bugs.freedesktop.org/show_bug.cgi?id=105010 fdo#105900 https://bugs.freedesktop.org/show_bug.cgi?id=105900 fdo#106680 https://bugs.freedesktop.org/show_bug.cgi?id=106680 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4635 -> Patchwork_9893 CI_DRM_4635: a9f34f7e3bab765e2b1320a1b154a76be38602a7 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4589: 779d2d42f9db6a2797d1ef50036af6fac4e62e73 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9893: b513210d05436fa3906e4d9258ceca693b6fe7ca @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9893/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/4] drm/i915: kill intel_display_power_well_is_enabled()
== Series Details == Series: series starting with [1/4] drm/i915: kill intel_display_power_well_is_enabled() URL : https://patchwork.freedesktop.org/series/47908/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4635_full -> Patchwork_9892_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9892_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9892_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9892_full: === IGT changes === Warnings igt@perf_pmu@rc6: shard-kbl: PASS -> SKIP igt@pm_rc6_residency@rc6-accuracy: shard-snb: SKIP -> PASS == Known issues == Here are the changes found in Patchwork_9892_full that come from known issues: === IGT changes === Issues hit igt@drv_suspend@shrink: shard-snb: PASS -> INCOMPLETE (fdo#106886, fdo#105411) igt@gem_render_linear_blits@basic: shard-kbl: PASS -> INCOMPLETE (fdo#103665) igt@kms_universal_plane@cursor-fb-leak-pipe-b: shard-apl: PASS -> FAIL (fdo#107241) Possible fixes igt@gem_exec_await@wide-contexts: shard-apl: FAIL (fdo#105900, fdo#106680) -> PASS igt@gem_exec_reuse@single: shard-snb: INCOMPLETE (fdo#105411) -> PASS igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: shard-glk: FAIL (fdo#105363) -> PASS fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#105900 https://bugs.freedesktop.org/show_bug.cgi?id=105900 fdo#106680 https://bugs.freedesktop.org/show_bug.cgi?id=106680 fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886 fdo#107241 https://bugs.freedesktop.org/show_bug.cgi?id=107241 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4635 -> Patchwork_9892 CI_DRM_4635: a9f34f7e3bab765e2b1320a1b154a76be38602a7 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4589: 779d2d42f9db6a2797d1ef50036af6fac4e62e73 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9892: 942f90859025412da524cfe6b53b2b5b05e84b9c @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9892/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/psr: Add debugfs support to force a downgrade to PSR1 mode.
On Wed, 2018-08-08 at 16:19 +0200, Maarten Lankhorst wrote:
> This will make it easier to test PSR1 on PSR2 capable eDP machines.
>
> Changes since v1:
> - Remove I915_PSR_DEBUG_FORCE_PSR2, it did nothing, not sure forcing
> PSR2 would even work.
> - Handle NULL crtc in intel_psr_set_debugfs_mode. (dhnkrn)
>
Reviewed-by: Dhinakaran Pandiyan
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_psr.c | 44
>
> 2 files changed, 40 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index a3ea48ce1811..14883614d9e6 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -616,6 +616,7 @@ struct i915_psr {
> #define I915_PSR_DEBUG_DEFAULT 0x00
> #define I915_PSR_DEBUG_DISABLE 0x01
> #define I915_PSR_DEBUG_ENABLE0x02
> +#define I915_PSR_DEBUG_FORCE_PSR10x03
> #define I915_PSR_DEBUG_IRQ 0x10
>
> u32 debug;
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index 12fbc59af5a4..a408faa16f90 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -68,6 +68,17 @@ static bool psr_global_enabled(u32 debug)
> }
> }
>
> +static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
> +const struct intel_crtc_state
> *crtc_state)
> +{
> + switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
> + case I915_PSR_DEBUG_FORCE_PSR1:
> + return false;
> + default:
> + return crtc_state->has_psr2;
> + }
> +}
> +
> void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool
> debug)
> {
> u32 debug_mask, mask;
> @@ -646,7 +657,7 @@ void intel_psr_enable(struct intel_dp *intel_dp,
> goto unlock;
> }
>
> - dev_priv->psr.psr2_enabled = crtc_state->has_psr2;
> + dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv,
> crtc_state);
> dev_priv->psr.busy_frontbuffer_bits = 0;
> dev_priv->psr.prepared = true;
>
> @@ -820,19 +831,38 @@ static bool __psr_wait_for_idle_locked(struct
> drm_i915_private *dev_priv)
> return err == 0 && dev_priv->psr.enabled;
> }
>
> +static bool switching_psr(struct drm_i915_private *dev_priv,
> + struct intel_crtc_state *crtc_state,
> + u32 mode)
> +{
> + /* Can't switch psr state anyway if PSR2 is not supported.
> */
> + if (!crtc_state || !crtc_state->has_psr2)
> + return false;
> +
> + if (dev_priv->psr.psr2_enabled && mode ==
> I915_PSR_DEBUG_FORCE_PSR1)
> + return true;
> +
> + if (!dev_priv->psr.psr2_enabled && mode !=
> I915_PSR_DEBUG_FORCE_PSR1)
> + return true;
> +
> + return false;
> +}
> +
> int intel_psr_set_debugfs_mode(struct drm_i915_private *dev_priv,
> struct drm_modeset_acquire_ctx *ctx,
> u64 val)
> {
> struct drm_device *dev = _priv->drm;
> struct drm_connector_state *conn_state;
> + struct intel_crtc_state *crtc_state = NULL;
> struct drm_crtc *crtc;
> struct intel_dp *dp;
> int ret;
> bool enable;
> + u32 mode = val & I915_PSR_DEBUG_MODE_MASK;
>
> if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK)
> ||
> - (val & I915_PSR_DEBUG_MODE_MASK) >
> I915_PSR_DEBUG_ENABLE) {
> + mode > I915_PSR_DEBUG_FORCE_PSR1) {
> DRM_DEBUG_KMS("Invalid debug mask %llx\n", val);
> return -EINVAL;
> }
> @@ -850,7 +880,8 @@ int intel_psr_set_debugfs_mode(struct
> drm_i915_private *dev_priv,
> if (ret)
> return ret;
>
> - ret = wait_for_completion_interruptible(
> >state->commit->hw_done);
> + crtc_state = to_intel_crtc_state(crtc->state);
> + ret = wait_for_completion_interruptible(_state-
> >base.commit->hw_done);
> } else
> ret = wait_for_completion_interruptible(_state-
> >commit->hw_done);
>
> @@ -863,14 +894,17 @@ int intel_psr_set_debugfs_mode(struct
> drm_i915_private *dev_priv,
>
> enable = psr_global_enabled(val);
>
> - if (!enable)
> + if (!enable || switching_psr(dev_priv, crtc_state, mode))
> intel_psr_disable_locked(dev_priv->psr.dp);
>
> dev_priv->psr.debug = val;
> + if (crtc)
> + dev_priv->psr.psr2_enabled =
> intel_psr2_enabled(dev_priv, crtc_state);
> +
> intel_psr_irq_control(dev_priv, dev_priv->psr.debug &
> I915_PSR_DEBUG_IRQ);
>
> if (dev_priv->psr.prepared && enable)
> - intel_psr_enable_locked(dev_priv,
> to_intel_crtc_state(crtc->state));
> + intel_psr_enable_locked(dev_priv, crtc_state);
>
> mutex_unlock(_priv->psr.lock);
>
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/20] drm: Let userspace check if driver supports modeset
== Series Details ==
Series: series starting with [01/20] drm: Let userspace check if driver
supports modeset
URL : https://patchwork.freedesktop.org/series/47917/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4635 -> Patchwork_9896 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/47917/revisions/1/mbox/
== Known issues ==
Here are the changes found in Patchwork_9896 that come from known issues:
=== IGT changes ===
Issues hit
igt@drv_module_reload@basic-reload:
fi-glk-j4005: PASS -> DMESG-WARN (fdo#106725, fdo#106248)
igt@drv_selftest@live_hangcheck:
fi-cfl-s3: PASS -> DMESG-FAIL (fdo#106560)
igt@drv_selftest@live_workarounds:
fi-skl-6700hq: PASS -> DMESG-FAIL (fdo#107292)
fi-cnl-psr: PASS -> DMESG-FAIL (fdo#107292)
igt@kms_chamelium@dp-edid-read:
fi-kbl-7500u: PASS -> FAIL (fdo#103841)
Possible fixes
igt@drv_selftest@live_hangcheck:
fi-cnl-psr: DMESG-FAIL (fdo#106560) -> PASS
fi-skl-guc: DMESG-FAIL (fdo#107174) -> PASS
igt@kms_pipe_crc_basic@read-crc-pipe-b:
{fi-byt-clapper}: FAIL (fdo#107362) -> PASS
Warnings
{igt@kms_psr@primary_page_flip}:
fi-cnl-psr: DMESG-FAIL (fdo#107372) -> DMESG-WARN (fdo#107372)
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
fdo#106248 https://bugs.freedesktop.org/show_bug.cgi?id=106248
fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
fdo#106725 https://bugs.freedesktop.org/show_bug.cgi?id=106725
fdo#107174 https://bugs.freedesktop.org/show_bug.cgi?id=107174
fdo#107292 https://bugs.freedesktop.org/show_bug.cgi?id=107292
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107372 https://bugs.freedesktop.org/show_bug.cgi?id=107372
== Participating hosts (50 -> 46) ==
Additional (1): fi-hsw-peppy
Missing(5): fi-byt-squawks fi-ilk-m540 fi-bxt-dsi fi-bsw-cyan
fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4635 -> Patchwork_9896
CI_DRM_4635: a9f34f7e3bab765e2b1320a1b154a76be38602a7 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4589: 779d2d42f9db6a2797d1ef50036af6fac4e62e73 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9896: b3ef168cf378f3302a530145c7f4aa5b9226e7c3 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
b3ef168cf378 drm/i915: Do not enable all power wells when display is disabled
f8d134458ced drm/i915: Warn when display irq functions is executed when display
is disabled
faeabdac7948 drm/i195: Do not initialize display core when display is disabled
5d3eacc063e0 drm/i915: Remove duplicated definition of intel_update_rawclk
37e3e80ae09a drm/i915: Do not initialize display clocks when display is disabled
38bab913e093 drm/i915: Do not reset display when display is disabled
bfb38e77a071 drm/i915: Keep overlay functions naming consistent
c79c34c7a7f4 drm/i915: Remove redundant checks for num_pipes == 0
6d193c6eaca8 drm/i915: Unset reset pch handshake when PCH is not present in one
place
4c68117a021e drm/i915: Grab a runtime pm reference before run live selftests
da72cc4a48be drm/i915: Do not call modeset related functions when display is
disabled
8f6838b45b9a drm/i915: Move intel_init_ipc() call to i915_load_modeset_init()
9e2ed46b2794 drm/i915: Do not modifiy reserved bit in gens that do not have IPC
b4186ea6f0c7 drm/i915: Move FBC init and cleanup calls to modeset functions
fe4a5e67d330 drm/i915: Move drm_vblank_init() to i915_load_modeset_init()
d2ec830c989d drm/i915: Release POWER_DOMAIN_INIT reference when display is
disabled
122c3ac9503e drm/i915: Move out non-display related calls from display/modeset
init/cleanup
598334e10538 drm/i915/runtime_pm: Share code to enable/disable PCH reset
handshake
9f0e7c79bc59 drm/i915: Set PCH as NOP when display is disabled
bf1ef1e800de drm: Let userspace check if driver supports modeset
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9896/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [01/20] drm: Let userspace check if driver supports modeset
== Series Details == Series: series starting with [01/20] drm: Let userspace check if driver supports modeset URL : https://patchwork.freedesktop.org/series/47917/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm: Let userspace check if driver supports modeset Okay! Commit: drm/i915: Set PCH as NOP when display is disabled Okay! Commit: drm/i915/runtime_pm: Share code to enable/disable PCH reset handshake Okay! Commit: drm/i915: Move out non-display related calls from display/modeset init/cleanup -drivers/gpu/drm/i915/selftests/../i915_drv.h:3675:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3676:16: warning: expression using sizeof(void) Commit: drm/i915: Release POWER_DOMAIN_INIT reference when display is disabled Okay! Commit: drm/i915: Move drm_vblank_init() to i915_load_modeset_init() Okay! Commit: drm/i915: Move FBC init and cleanup calls to modeset functions Okay! Commit: drm/i915: Do not modifiy reserved bit in gens that do not have IPC Okay! Commit: drm/i915: Move intel_init_ipc() call to i915_load_modeset_init() Okay! Commit: drm/i915: Do not call modeset related functions when display is disabled Okay! Commit: drm/i915: Grab a runtime pm reference before run live selftests Okay! Commit: drm/i915: Unset reset pch handshake when PCH is not present in one place Okay! Commit: drm/i915: Remove redundant checks for num_pipes == 0 Okay! Commit: drm/i915: Keep overlay functions naming consistent Okay! Commit: drm/i915: Do not reset display when display is disabled Okay! Commit: drm/i915: Do not initialize display clocks when display is disabled Okay! Commit: drm/i915: Remove duplicated definition of intel_update_rawclk Okay! Commit: drm/i195: Do not initialize display core when display is disabled Okay! Commit: drm/i915: Warn when display irq functions is executed when display is disabled Okay! Commit: drm/i915: Do not enable all power wells when display is disabled Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Restore user forcewake domains across suspend (rev2)
== Series Details == Series: drm/i915: Restore user forcewake domains across suspend (rev2) URL : https://patchwork.freedesktop.org/series/47894/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4635_full -> Patchwork_9891_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9891_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9891_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9891_full: === IGT changes === Warnings igt@pm_rc6_residency@rc6-accuracy: shard-snb: SKIP -> PASS == Known issues == Here are the changes found in Patchwork_9891_full that come from known issues: === IGT changes === Issues hit igt@kms_flip@flip-vs-expired-vblank-interruptible: shard-glk: PASS -> FAIL (fdo#105363) Possible fixes igt@gem_exec_await@wide-contexts: shard-apl: FAIL (fdo#106680, fdo#105900) -> PASS fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105900 https://bugs.freedesktop.org/show_bug.cgi?id=105900 fdo#106680 https://bugs.freedesktop.org/show_bug.cgi?id=106680 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4635 -> Patchwork_9891 CI_DRM_4635: a9f34f7e3bab765e2b1320a1b154a76be38602a7 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4589: 779d2d42f9db6a2797d1ef50036af6fac4e62e73 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9891: c326ef4365a9795ed7f4ab0565b51bb139a7d522 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9891/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/20] drm: Let userspace check if driver supports modeset
== Series Details == Series: series starting with [01/20] drm: Let userspace check if driver supports modeset URL : https://patchwork.freedesktop.org/series/47917/ State : warning == Summary == $ dim checkpatch origin/drm-tip bf1ef1e800de drm: Let userspace check if driver supports modeset 9f0e7c79bc59 drm/i915: Set PCH as NOP when display is disabled 598334e10538 drm/i915/runtime_pm: Share code to enable/disable PCH reset handshake 122c3ac9503e drm/i915: Move out non-display related calls from display/modeset init/cleanup d2ec830c989d drm/i915: Release POWER_DOMAIN_INIT reference when display is disabled fe4a5e67d330 drm/i915: Move drm_vblank_init() to i915_load_modeset_init() b4186ea6f0c7 drm/i915: Move FBC init and cleanup calls to modeset functions 9e2ed46b2794 drm/i915: Do not modifiy reserved bit in gens that do not have IPC 8f6838b45b9a drm/i915: Move intel_init_ipc() call to i915_load_modeset_init() da72cc4a48be drm/i915: Do not call modeset related functions when display is disabled -:349: CHECK:CAMELCASE: Avoid CamelCase: #349: FILE: drivers/gpu/drm/i915/i915_suspend.c:71: +_priv->regfile.saveGCDGMBUS); total: 0 errors, 0 warnings, 1 checks, 338 lines checked 4c68117a021e drm/i915: Grab a runtime pm reference before run live selftests 6d193c6eaca8 drm/i915: Unset reset pch handshake when PCH is not present in one place c79c34c7a7f4 drm/i915: Remove redundant checks for num_pipes == 0 bfb38e77a071 drm/i915: Keep overlay functions naming consistent 38bab913e093 drm/i915: Do not reset display when display is disabled 37e3e80ae09a drm/i915: Do not initialize display clocks when display is disabled 5d3eacc063e0 drm/i915: Remove duplicated definition of intel_update_rawclk faeabdac7948 drm/i195: Do not initialize display core when display is disabled f8d134458ced drm/i915: Warn when display irq functions is executed when display is disabled b3ef168cf378 drm/i915: Do not enable all power wells when display is disabled ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 13/20] drm/i915: Remove redundant checks for num_pipes == 0
This 'if's will always be false because of previous changes so let's
drop then.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.c | 12 +++-
drivers/gpu/drm/i915/intel_audio.c | 3 ---
drivers/gpu/drm/i915/intel_display.c | 3 ---
drivers/gpu/drm/i915/intel_i2c.c | 3 ---
4 files changed, 3 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e93be91a6701..7a3794e70187 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -645,12 +645,9 @@ static int i915_load_modeset_init(struct drm_device *dev)
if (i915_inject_load_failure())
return -ENODEV;
- if (INTEL_INFO(dev_priv)->num_pipes) {
- ret = drm_vblank_init(_priv->drm,
- INTEL_INFO(dev_priv)->num_pipes);
- if (ret)
- goto out;
- }
+ ret = drm_vblank_init(_priv->drm, INTEL_INFO(dev_priv)->num_pipes);
+ if (ret)
+ goto out;
intel_bios_init(dev_priv);
@@ -683,9 +680,6 @@ static int i915_load_modeset_init(struct drm_device *dev)
intel_setup_overlay(dev_priv);
- if (INTEL_INFO(dev_priv)->num_pipes == 0)
- return 0;
-
ret = intel_fbdev_init(dev);
if (ret)
goto cleanup_modeset;
diff --git a/drivers/gpu/drm/i915/intel_audio.c
b/drivers/gpu/drm/i915/intel_audio.c
index b725835b47ef..769f3f586661 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -962,9 +962,6 @@ void i915_audio_component_init(struct drm_i915_private
*dev_priv)
{
int ret;
- if (INTEL_INFO(dev_priv)->num_pipes == 0)
- return;
-
ret = component_add(dev_priv->drm.dev, _audio_component_bind_ops);
if (ret < 0) {
DRM_ERROR("failed to add audio component (%d)\n", ret);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 11f720f4228c..d3ce4cb4b2b5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15202,9 +15202,6 @@ int intel_modeset_init(struct drm_device *dev)
intel_init_pm(dev_priv);
- if (INTEL_INFO(dev_priv)->num_pipes == 0)
- return 0;
-
/*
* There may be no VBT; and if the BIOS enabled SSC we can
* just keep using it to avoid unnecessary flicker. Whereas if the
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index bef32b7c248e..2f941c5b2e8c 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -819,9 +819,6 @@ int intel_setup_gmbus(struct drm_i915_private *dev_priv)
unsigned int pin;
int ret;
- if (INTEL_INFO(dev_priv)->num_pipes == 0)
- return 0;
-
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
else if (!HAS_GMCH_DISPLAY(dev_priv))
--
2.18.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 16/20] drm/i915: Do not initialize display clocks when display is disabled
cdclk and rawclk are the 2 display clocks that can now be completed
not initialized when display is disabled.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.c | 9 ++---
drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +++
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 7e948bf30cdd..743b03d50abb 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -918,7 +918,8 @@ static int i915_driver_init_early(struct drm_i915_private
*dev_priv,
goto err_uc;
intel_irq_init(dev_priv);
intel_hangcheck_init(dev_priv);
- intel_init_display_hooks(dev_priv);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ intel_init_display_hooks(dev_priv);
intel_init_clock_gating_hooks(dev_priv);
if (INTEL_INFO(dev_priv)->num_pipes) {
intel_init_audio_hooks(dev_priv);
@@ -1390,7 +1391,8 @@ int i915_driver_load(struct pci_dev *pdev, const struct
pci_device_id *ent)
goto out_cleanup_mmio;
/* must happen before intel_power_domains_init_hw() on VLV/CHV */
- intel_update_rawclk(dev_priv);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ intel_update_rawclk(dev_priv);
/* i915_gem_init() call chain will call
* intel_display_power_put(i915, POWER_DOMAIN_GT_IRQ);
@@ -1800,7 +1802,8 @@ static int i915_drm_resume(struct drm_device *dev)
i915_gem_resume(dev_priv);
- intel_modeset_init_hw(dev);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ intel_modeset_init_hw(dev);
intel_init_clock_gating(dev_priv);
spin_lock_irq(_priv->irq_lock);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 43d7f9071ff4..01e0c8e82fcf 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -807,6 +807,9 @@ static void gen9_dc_off_power_well_enable(struct
drm_i915_private *dev_priv,
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
dev_priv->display.get_cdclk(dev_priv, _state);
/* Can't read out voltage_level so can't use intel_cdclk_changed() */
WARN_ON(intel_cdclk_needs_modeset(_priv->cdclk.hw, _state));
--
2.18.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 07/20] drm/i915: Move FBC init and cleanup calls to modeset functions
Although FBC helps save power it do not belongs to power management
also the cleanup was placed in i915_driver_unload() also not a good
place. intel_modeset_init()/intel_modeset_cleanup() are better places
also this will help make easy disable features that depends in
display being enabled in driver.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.c | 1 -
drivers/gpu/drm/i915/intel_display.c | 4
drivers/gpu/drm/i915/intel_pm.c | 2 --
3 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index bdb41511d375..22323d88734d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1495,7 +1495,6 @@ void i915_driver_unload(struct drm_device *dev)
i915_reset_error_state(dev_priv);
i915_gem_fini(dev_priv);
- intel_fbc_cleanup_cfb(dev_priv);
intel_power_domains_fini_hw(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 5f0426d6d360..11f720f4228c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15198,6 +15198,8 @@ int intel_modeset_init(struct drm_device *dev)
intel_init_quirks(dev);
+ intel_fbc_init(dev_priv);
+
intel_init_pm(dev_priv);
if (INTEL_INFO(dev_priv)->num_pipes == 0)
@@ -16009,6 +16011,8 @@ void intel_modeset_cleanup(struct drm_device *dev)
intel_teardown_gmbus(dev_priv);
destroy_workqueue(dev_priv->modeset_wq);
+
+ intel_fbc_cleanup_cfb(dev_priv);
}
void intel_connector_attach_encoder(struct intel_connector *connector,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 30ca77b81b0c..e45ab21e8566 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9309,8 +9309,6 @@ void intel_init_clock_gating_hooks(struct
drm_i915_private *dev_priv)
/* Set up chip specific power management-related functions */
void intel_init_pm(struct drm_i915_private *dev_priv)
{
- intel_fbc_init(dev_priv);
-
/* For cxsr */
if (IS_PINEVIEW(dev_priv))
i915_pineview_get_mem_freq(dev_priv);
--
2.18.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 15/20] drm/i915: Do not reset display when display is disabled
Display is disabled in the beginning of the reset and re-enabled
afterreset each engine needed but if the display is disabled we
should not do it.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_irq.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 8084e35b25c5..cb82f56cd7dc 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3182,7 +3182,8 @@ static void i915_reset_device(struct drm_i915_private
*dev_priv,
/* Use a watchdog to ensure that our reset completes */
i915_wedge_on_timeout(, dev_priv, 5*HZ) {
- intel_prepare_reset(dev_priv);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ intel_prepare_reset(dev_priv);
error->reason = reason;
error->stalled_mask = engine_mask;
@@ -3208,7 +3209,8 @@ static void i915_reset_device(struct drm_i915_private
*dev_priv,
error->stalled_mask = 0;
error->reason = NULL;
- intel_finish_reset(dev_priv);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ intel_finish_reset(dev_priv);
}
if (!test_bit(I915_WEDGED, >flags))
--
2.18.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 17/20] drm/i915: Remove duplicated definition of intel_update_rawclk
A few line above we have another definition of intel_update_rawclk() keeping that one as the function is implemented in intel_cdclk.c. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_drv.h | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 14545f51b885..e1f5605ea68c 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1477,7 +1477,6 @@ void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state, void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc); -void intel_update_rawclk(struct drm_i915_private *dev_priv); int vlv_get_hpll_vco(struct drm_i915_private *dev_priv); int vlv_get_cck_clock(struct drm_i915_private *dev_priv, const char *name, u32 reg, int ref_freq); -- 2.18.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 05/20] drm/i915: Release POWER_DOMAIN_INIT reference when display is disabled
When loading the driver
i915_load_modeset_init()->intel_modeset_setup_hw_state() do the
counter part call of intel_power_domains_init_hw() calling
intel_display_set_init_power(false).
The problem is i915_load_modeset_init() is not executed when display
is disabled, so moving it to i915_driver_load().
Also calling intel_display_set_init_power(false) in
__intel_display_resume() as it would be executed by calling
intel_modeset_setup_hw_state().
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.c | 4
drivers/gpu/drm/i915/intel_display.c | 8 +---
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1f784d71f274..9e2de6d1de3d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1407,6 +1407,10 @@ int i915_driver_load(struct pci_dev *pdev, const struct
pci_device_id *ent)
if (ret < 0)
goto cleanup_gem;
+ /* intel_power_domains_init_hw() counter part */
+ intel_display_set_init_power(dev_priv, false);
+ intel_power_domains_verify_state(dev_priv);
+
i915_driver_register(dev_priv);
intel_runtime_pm_enable(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 76d0d2bb3baa..5f0426d6d360 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3664,11 +3664,16 @@ __intel_display_resume(struct drm_device *dev,
struct drm_atomic_state *state,
struct drm_modeset_acquire_ctx *ctx)
{
+ struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_crtc_state *crtc_state;
struct drm_crtc *crtc;
int i, ret;
intel_modeset_setup_hw_state(dev, ctx);
+
+ intel_display_set_init_power(dev_priv, false);
+ intel_power_domains_verify_state(dev_priv);
+
i915_redisable_vga(to_i915(dev));
if (!state)
@@ -15888,9 +15893,6 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
if (WARN_ON(put_domains))
modeset_put_power_domains(dev_priv, put_domains);
}
- intel_display_set_init_power(dev_priv, false);
-
- intel_power_domains_verify_state(dev_priv);
intel_fbc_init_pipe_state(dev_priv);
}
--
2.18.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 20/20] drm/i915: Do not enable all power wells when display is disabled
POWER_DOMAIN_INIT is used when doing driver initialization or cleanup because driver will touch a lot of registers and using POWER_DOMAIN_INIT as a shortcut to power on or down every power well. So here skiping the call to the functions that actually power on or down power wells when domain is POWER_DOMAIN_INIT and display is disabled but it still grabs and releases the runtime pm reference to guarantee that hardware will be powered during initialization. This patch plus the changes in the previous patches is enough to not enable any power well when display is disabled, the only exception is POWER_DOMAIN_GT_IRQ that is used by gem to inhibits DC power savings while using GT. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.c | 8 +++- drivers/gpu/drm/i915/intel_runtime_pm.c | 10 ++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 743b03d50abb..5227cf0683f0 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1415,7 +1415,13 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent) /* intel_power_domains_init_hw() counter part */ intel_display_set_init_power(dev_priv, false); - intel_power_domains_verify_state(dev_priv); + /* FIXME: When display is disabled all the power wells enabled by +* BIOS/firmware will still be enabled at this point so skip the +* verify state for now, this will be fixed in future patch disabling +* all the power wells that BIOS/firmware enabled. +*/ + if (INTEL_INFO(dev_priv)->num_pipes) + intel_power_domains_verify_state(dev_priv); i915_driver_register(dev_priv); diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 8a84c77a1a88..7f0c10ee475a 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -1543,6 +1543,9 @@ __intel_display_power_get_domain(struct drm_i915_private *dev_priv, struct i915_power_domains *power_domains = _priv->power_domains; struct i915_power_well *power_well; + WARN_ON(!INTEL_INFO(dev_priv)->num_pipes && + domain != POWER_DOMAIN_GT_IRQ); + for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain)) intel_power_well_get(dev_priv, power_well); @@ -1568,6 +1571,9 @@ void intel_display_power_get(struct drm_i915_private *dev_priv, intel_runtime_pm_get(dev_priv); + if (domain == POWER_DOMAIN_INIT && !INTEL_INFO(dev_priv)->num_pipes) + return; + mutex_lock(_domains->lock); __intel_display_power_get_domain(dev_priv, domain); @@ -1628,6 +1634,9 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, struct i915_power_domains *power_domains; struct i915_power_well *power_well; + if (domain == POWER_DOMAIN_INIT && !INTEL_INFO(dev_priv)->num_pipes) + goto end; + power_domains = _priv->power_domains; mutex_lock(_domains->lock); @@ -1642,6 +1651,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, mutex_unlock(_domains->lock); +end: intel_runtime_pm_put(dev_priv); } -- 2.18.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 10/20] drm/i915: Do not call modeset related functions when display is disabled
No need to run i915_load_modeset_init() when num_pipes == 0 also
kms depends on things initialized in i915_load_modeset_init() so not
initializing it too. fbdev and audio have guards against
num_pipes == 0 but lets move it to the if block to make it explicit
to readers.
Also as planes, CRTCs, encoders and connectors are not being added
it is necessary to unset the MODESET driver feature otherwise it
will crash when registering driver in drm, also disabling ATOMIC as
do not make sense have ATOMIC and do not have MODESET.
There is more modeset/display calls that still needs to be removed,
this is a initial work.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.c | 157 +++-
drivers/gpu/drm/i915/i915_suspend.c | 24 ++--
drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +-
3 files changed, 114 insertions(+), 70 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e9a6cc7b3efd..e93be91a6701 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -917,7 +917,8 @@ static int i915_driver_init_early(struct drm_i915_private
*dev_priv,
intel_wopcm_init_early(_priv->wopcm);
intel_uc_init_early(dev_priv);
intel_pm_setup(dev_priv);
- intel_init_dpio(dev_priv);
+ if (INTEL_INFO(dev_priv)->num_pipes)
+ intel_init_dpio(dev_priv);
ret = intel_power_domains_init(dev_priv);
if (ret < 0)
goto err_uc;
@@ -925,8 +926,10 @@ static int i915_driver_init_early(struct drm_i915_private
*dev_priv,
intel_hangcheck_init(dev_priv);
intel_init_display_hooks(dev_priv);
intel_init_clock_gating_hooks(dev_priv);
- intel_init_audio_hooks(dev_priv);
- intel_display_crc_init(dev_priv);
+ if (INTEL_INFO(dev_priv)->num_pipes) {
+ intel_init_audio_hooks(dev_priv);
+ intel_display_crc_init(dev_priv);
+ }
intel_detect_preproduction_hw(dev_priv);
@@ -1258,23 +1261,26 @@ static void i915_driver_register(struct
drm_i915_private *dev_priv)
if (IS_GEN5(dev_priv))
intel_gpu_ips_init(dev_priv);
- intel_audio_init(dev_priv);
+ if (INTEL_INFO(dev_priv)->num_pipes) {
+ intel_audio_init(dev_priv);
- /*
-* Some ports require correctly set-up hpd registers for detection to
-* work properly (leading to ghost connected connector status), e.g. VGA
-* on gm45. Hence we can only set up the initial fbdev config after hpd
-* irqs are fully enabled. We do it last so that the async config
-* cannot run before the connectors are registered.
-*/
- intel_fbdev_initial_config_async(dev);
+ /*
+* Some ports require correctly set-up hpd registers for
+* detection to work properly (leading to ghost connected
+* connector status), e.g. VGA on gm45. Hence we can only set
+* up the initial fbdev config after hpd irqs are fully enabled.
+* We do it last so that the async config cannot run before the
+* connectors are registered.
+*/
+ intel_fbdev_initial_config_async(dev);
- /*
-* We need to coordinate the hotplugs with the asynchronous fbdev
-* configuration, for which we use the fbdev->async_cookie.
-*/
- if (INTEL_INFO(dev_priv)->num_pipes)
+ /*
+* We need to coordinate the hotplugs with the asynchronous
+* fbdev configuration, for which we use the
+* fbdev->async_cookie.
+*/
drm_kms_helper_poll_init(dev);
+ }
}
/**
@@ -1283,15 +1289,17 @@ static void i915_driver_register(struct
drm_i915_private *dev_priv)
*/
static void i915_driver_unregister(struct drm_i915_private *dev_priv)
{
- intel_fbdev_unregister(dev_priv);
- intel_audio_deinit(dev_priv);
+ if (INTEL_INFO(dev_priv)->num_pipes) {
+ intel_fbdev_unregister(dev_priv);
+ intel_audio_deinit(dev_priv);
- /*
-* After flushing the fbdev (incl. a late async config which will
-* have delayed queuing of a hotplug event), then flush the hotplug
-* events.
-*/
- drm_kms_helper_poll_fini(_priv->drm);
+ /*
+* After flushing the fbdev (incl. a late async config which
+* will have delayed queuing of a hotplug event), then flush the
+* hotplug events.
+*/
+ drm_kms_helper_poll_fini(_priv->drm);
+ }
intel_gpu_ips_teardown();
acpi_video_unregister();
@@ -1343,6 +1351,9 @@ int i915_driver_load(struct pci_dev *pdev, const struct
pci_device_id *ent)
if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
[Intel-gfx] [PATCH 09/20] drm/i915: Move intel_init_ipc() call to i915_load_modeset_init()
IPC(Isochronous Priority Control not Inter-process communication btw) is a display feature, so i915_load_modeset_init() is the right place to initialize it. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 22323d88734d..e9a6cc7b3efd 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -693,6 +693,8 @@ static int i915_load_modeset_init(struct drm_device *dev) /* Only enable hotplug handling once the fbdev is fully set up. */ intel_hpd_init(dev_priv); + intel_init_ipc(dev_priv); + return 0; cleanup_modeset: @@ -1410,8 +1412,6 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent) intel_runtime_pm_enable(dev_priv); - intel_init_ipc(dev_priv); - intel_runtime_pm_put(dev_priv); i915_welcome_messages(dev_priv); -- 2.18.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 12/20] drm/i915: Unset reset pch handshake when PCH is not present in one place
Right now RESET_PCH_HANDSHAKE_ENABLE is enabled all the times inside
of intel_power_domains_init_hw() and if PCH is NOP it is unsed in
i915_gem_init_hw().
So making skl_pch_reset_handshake() handle both cases and calling
it for the missing gens in intel_power_domains_init_hw().
Ivybridge have a different register and bits but with the same
objective so moving it too.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_gem.c | 12
drivers/gpu/drm/i915/intel_runtime_pm.c | 16 +++-
2 files changed, 15 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 71502512ac1f..49151d79e3b1 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5283,18 +5283,6 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
- if (HAS_PCH_NOP(dev_priv)) {
- if (IS_IVYBRIDGE(dev_priv)) {
- u32 temp = I915_READ(GEN7_MSG_CTL);
- temp &= ~(WAIT_FOR_PCH_FLR_ACK |
WAIT_FOR_PCH_RESET_ACK);
- I915_WRITE(GEN7_MSG_CTL, temp);
- } else if (INTEL_GEN(dev_priv) >= 7) {
- u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
- temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
- I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
- }
- }
-
intel_gt_workarounds_apply(dev_priv);
i915_gem_init_swizzling(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 97178d512852..43d7f9071ff4 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -3265,11 +3265,16 @@ static void icl_mbus_init(struct drm_i915_private
*dev_priv)
I915_WRITE(MBUS_ABOX_CTL, val);
}
+/* Actually it is hsw+ but until skl it was not required to set it */
static void skl_pch_reset_handshake(struct drm_i915_private *dev_priv)
{
u32 val = I915_READ(HSW_NDE_RSTWRN_OPT);
- val |= RESET_PCH_HANDSHAKE_ENABLE;
+ if (HAS_PCH_NOP(dev_priv))
+ val &= ~RESET_PCH_HANDSHAKE_ENABLE;
+ else
+ val |= RESET_PCH_HANDSHAKE_ENABLE;
+
I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
}
@@ -3773,6 +3778,15 @@ void intel_power_domains_init_hw(struct drm_i915_private
*dev_priv, bool resume)
mutex_lock(_domains->lock);
vlv_cmnlane_wa(dev_priv);
mutex_unlock(_domains->lock);
+ } else if (IS_IVYBRIDGE(dev_priv)) {
+ if (HAS_PCH_NOP(dev_priv)) {
+ u32 val = I915_READ(GEN7_MSG_CTL);
+
+ val &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
+ I915_WRITE(GEN7_MSG_CTL, val);
+ }
+ } else if (INTEL_GEN(dev_priv) >= 7) {
+ skl_pch_reset_handshake(dev_priv);
}
/* For now, we need the power well to be always enabled. */
--
2.18.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 18/20] drm/i195: Do not initialize display core when display is disabled
The only thing left from *_display_core_init when display is disabled
is the skl_pch_reset_handshake() that is already handling display
enabled and disabled. And *_display_core_uninit() also was left
to disable DC.
If more power savings is required, we could disable the power wells
that BIOS enable.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 32 +
1 file changed, 28 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 01e0c8e82fcf..8a84c77a1a88 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -3292,6 +3292,9 @@ static void skl_display_core_init(struct drm_i915_private
*dev_priv,
/* enable PCH reset handshake */
skl_pch_reset_handshake(dev_priv);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
/* enable PG1 and Misc I/O */
mutex_lock(_domains->lock);
@@ -3318,6 +3321,9 @@ static void skl_display_core_uninit(struct
drm_i915_private *dev_priv)
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
gen9_dbuf_disable(dev_priv);
skl_uninit_cdclk(dev_priv);
@@ -3357,6 +3363,9 @@ void bxt_display_core_init(struct drm_i915_private
*dev_priv,
*/
skl_pch_reset_handshake(dev_priv);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
/* Enable PG1 */
mutex_lock(_domains->lock);
@@ -3380,6 +3389,9 @@ void bxt_display_core_uninit(struct drm_i915_private
*dev_priv)
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
gen9_dbuf_disable(dev_priv);
bxt_uninit_cdclk(dev_priv);
@@ -3478,6 +3490,9 @@ static void cnl_display_core_init(struct drm_i915_private
*dev_priv, bool resume
/* 1. Enable PCH Reset Handshake */
skl_pch_reset_handshake(dev_priv);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
/* 2. Enable Comp */
val = I915_READ(CHICKEN_MISC_2);
val &= ~CNL_COMP_PWR_DOWN;
@@ -3522,7 +3537,10 @@ static void cnl_display_core_uninit(struct
drm_i915_private *dev_priv)
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
- /* 1. Disable all display engine functions -> aready done */
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
+ /* 1. Disable all display engine functions -> already done */
/* 2. Disable DBUF */
gen9_dbuf_disable(dev_priv);
@@ -3561,6 +3579,9 @@ static void icl_display_core_init(struct drm_i915_private
*dev_priv,
/* 1. Enable PCH reset handshake. */
skl_pch_reset_handshake(dev_priv);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
for (port = PORT_A; port <= PORT_B; port++) {
/* 2. Enable DDI combo PHY comp. */
val = I915_READ(ICL_PHY_MISC(port));
@@ -3607,7 +3628,10 @@ static void icl_display_core_uninit(struct
drm_i915_private *dev_priv)
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
- /* 1. Disable all display engine functions -> aready done */
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
+ /* 1. Disable all display engine functions -> already done */
/* 2. Disable DBUF */
icl_dbuf_disable(dev_priv);
@@ -3773,11 +3797,11 @@ void intel_power_domains_init_hw(struct
drm_i915_private *dev_priv, bool resume)
skl_display_core_init(dev_priv, resume);
} else if (IS_GEN9_LP(dev_priv)) {
bxt_display_core_init(dev_priv, resume);
- } else if (IS_CHERRYVIEW(dev_priv)) {
+ } else if (IS_CHERRYVIEW(dev_priv) && INTEL_INFO(dev_priv)->num_pipes) {
mutex_lock(_domains->lock);
chv_phy_control_init(dev_priv);
mutex_unlock(_domains->lock);
- } else if (IS_VALLEYVIEW(dev_priv)) {
+ } else if (IS_VALLEYVIEW(dev_priv) && INTEL_INFO(dev_priv)->num_pipes) {
mutex_lock(_domains->lock);
vlv_cmnlane_wa(dev_priv);
mutex_unlock(_domains->lock);
--
2.18.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 08/20] drm/i915: Do not modifiy reserved bit in gens that do not have IPC
IPC was only added in SKL+(actually we don't even enable for SKL due
WA) so without this change, driver was writing to a reserved bit.
Also check for the WA in intel_init_ipc() to avoid further writes to
ipc_enabled.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_pm.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e45ab21e8566..0ab10a974850 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6107,10 +6107,8 @@ void intel_enable_ipc(struct drm_i915_private *dev_priv)
u32 val;
/* Display WA #0477 WaDisableIPC: skl */
- if (IS_SKYLAKE(dev_priv)) {
- dev_priv->ipc_enabled = false;
+ if (!HAS_IPC(dev_priv) || IS_SKYLAKE(dev_priv))
return;
- }
val = I915_READ(DISP_ARB_CTL2);
@@ -6125,7 +6123,9 @@ void intel_enable_ipc(struct drm_i915_private *dev_priv)
void intel_init_ipc(struct drm_i915_private *dev_priv)
{
dev_priv->ipc_enabled = false;
- if (!HAS_IPC(dev_priv))
+
+ /* Display WA #0477 WaDisableIPC: skl */
+ if (!HAS_IPC(dev_priv) || IS_SKYLAKE(dev_priv))
return;
dev_priv->ipc_enabled = true;
--
2.18.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 06/20] drm/i915: Move drm_vblank_init() to i915_load_modeset_init()
i915_load_modeset_init() is a more suitable place than
i915_driver_load() as vblank is part of modeset.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.c | 20 +++-
1 file changed, 7 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9e2de6d1de3d..bdb41511d375 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -645,6 +645,13 @@ static int i915_load_modeset_init(struct drm_device *dev)
if (i915_inject_load_failure())
return -ENODEV;
+ if (INTEL_INFO(dev_priv)->num_pipes) {
+ ret = drm_vblank_init(_priv->drm,
+ INTEL_INFO(dev_priv)->num_pipes);
+ if (ret)
+ goto out;
+ }
+
intel_bios_init(dev_priv);
/* If we have > 1 VGA cards, then we need to arbitrate access
@@ -1375,18 +1382,6 @@ int i915_driver_load(struct pci_dev *pdev, const struct
pci_device_id *ent)
if (ret < 0)
goto out_cleanup_mmio;
- /*
-* TODO: move the vblank init and parts of modeset init steps into one
-* of the i915_driver_init_/i915_driver_register functions according
-* to the role/effect of the given init step.
-*/
- if (INTEL_INFO(dev_priv)->num_pipes) {
- ret = drm_vblank_init(_priv->drm,
- INTEL_INFO(dev_priv)->num_pipes);
- if (ret)
- goto out_cleanup_hw;
- }
-
/* must happen before intel_power_domains_init_hw() on VLV/CHV */
intel_update_rawclk(dev_priv);
@@ -1432,7 +1427,6 @@ int i915_driver_load(struct pci_dev *pdev, const struct
pci_device_id *ent)
drm_irq_uninstall(_priv->drm);
out_cleanup_power:
intel_power_domains_fini_hw(dev_priv);
-out_cleanup_hw:
i915_driver_cleanup_hw(dev_priv);
out_cleanup_mmio:
i915_driver_cleanup_mmio(dev_priv);
--
2.18.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 11/20] drm/i915: Grab a runtime pm reference before run live selftests
Now that modeset stuff is not being initialized when display is
disabled nothing is holding a power well or runtime pm reference
when running live selftests. And IGT runs live selftests with
display on and off, causing the below warning:
[ 473.586533] Setting dangerous option live_selftests - tainting kernel
[ 484.219068] [ cut here ]
[ 484.219070] RPM wakelock ref not held during HW access
[ 484.219126] WARNING: CPU: 3 PID: 4659 at
drivers/gpu/drm/i915/intel_drv.h:1986 intel_runtime_pm_get_noresume+0x6c/0x70
[i915]
[ 484.219128] Modules linked in: i915(+) amdgpu chash gpu_sched ttm vgem
snd_hda_codec_hdmi snd_hda_codec_realtek snd_hda_codec_generic btusb btrtl
btbcm x86_pkg_temp_thermal btintel coretemp snd_hda_codec asix crct10dif_pclmul
bluetooth crc32_pclmul usbnet snd_hwdep mii snd_hda_core ghash_clmulni_intel
e1000e snd_pcm ecdh_generic mei_me mei prime_numbers pinctrl_sunrisepoint
pinctrl_intel [last unloaded: i915]
[ 484.219173] CPU: 3 PID: 4659 Comm: drv_selftest Tainted: G U
4.18.0-rc8-CI-Trybot_2696+ #1
[ 484.219174] Hardware name: Intel Corporation Kabylake Client
platform/Kabylake R DDR4 RVP, BIOS KBLSE2R1.R00.X078.P02.1703030515 03/03/2017
[ 484.219205] RIP: 0010:intel_runtime_pm_get_noresume+0x6c/0x70 [i915]
[ 484.219206] Code: 94 77 20 00 01 e8 04 bf 53 e0 0f 0b eb c5 80 3d 83 77 20
00 00 75 c6 48 c7 c7 50 b4 ca a0 c6 05 73 77 20 00 01 e8 e4 be 53 e0 <0f> 0b eb
af 41 54 55 53 80 bf e4 ab 00 00 00 48 89 fb 48 8b af e0
[ 484.219277] RSP: 0018:c93bfa10 EFLAGS: 00010286
[ 484.219279] RAX: RBX: 88023c16 RCX: 0001
[ 484.219281] RDX: 8001 RSI: 820c708c RDI:
[ 484.219282] RBP: 8802b4ceb3f8 R08: afcc94fa R09:
[ 484.219284] R10: 8802b5820358 R11: R12: 88023c160068
[ 484.219285] R13: a0c80e30 R14: a0cce2a0 R15: 88023c16
[ 484.219287] FS: 7f4d95a83980() GS:8802becc()
knlGS:
[ 484.219288] CS: 0010 DS: ES: CR0: 80050033
[ 484.219290] CR2: 7f4d953257a0 CR3: 0001fa1d8001 CR4: 003606e0
[ 484.219291] DR0: DR1: DR2:
[ 484.219292] DR3: DR6: fffe0ff0 DR7: 0400
[ 484.219294] Call Trace:
[ 484.219328] i915_gem_unpark+0xb9/0x170 [i915]
[ 484.219361] igt_mmap_offset_exhaustion+0x365/0x6e0 [i915]
[ 484.219400] ? __i915_subtests+0x39/0xf0 [i915]
[ 484.219403] ? ring_buffer_unlock_commit+0x20/0xd0
[ 484.219406] ? trace_vbprintk+0x171/0x220
[ 484.219411] ? __trace_bprintk+0x57/0x80
[ 484.219450] __i915_subtests+0x5e/0xf0 [i915]
[ 484.219487] __run_selftests+0x10b/0x190 [i915]
[ 484.219522] i915_live_selftests+0x2c/0x60 [i915]
[ 484.219552] i915_pci_probe+0x50/0xa0 [i915]
[ 484.219556] pci_device_probe+0xa1/0x130
[ 484.219560] driver_probe_device+0x2f5/0x470
So now grabbing and releasing a runtime pm reference around
i915_live_selftests() call.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_pci.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index e931b48369dd..d43b950c2798 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -695,6 +695,7 @@ static void i915_pci_remove(struct pci_dev *pdev)
static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id
*ent)
{
+ struct drm_i915_private *dev_priv;
struct intel_device_info *intel_info =
(struct intel_device_info *) ent->driver_data;
int err;
@@ -730,7 +731,10 @@ static int i915_pci_probe(struct pci_dev *pdev, const
struct pci_device_id *ent)
return -ENODEV;
}
+ dev_priv = to_i915(pci_get_drvdata(pdev));
+ intel_runtime_pm_get(dev_priv);
err = i915_live_selftests(pdev);
+ intel_runtime_pm_put(dev_priv);
if (err) {
i915_pci_remove(pdev);
return err > 0 ? -ENOTTY : err;
--
2.18.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 04/20] drm/i915: Move out non-display related calls from display/modeset init/cleanup
i915_load_modeset_init() and intel_modeset_cleanup() was initializing
and cleaning up things that is not display only.
This will make easy initialize driver without display block.
Also moving VLV/CHV/BYT czclk as it is a core clock used as base by
several other GPU blocks not only display, including gem/GT.
Spec: 14370
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.c | 86 ++--
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 28 ++---
drivers/gpu/drm/i915/intel_pm.c | 10
4 files changed, 72 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 7952f5877402..1f784d71f274 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -664,28 +664,15 @@ static int i915_load_modeset_init(struct drm_device *dev)
if (ret)
goto cleanup_vga_client;
- /* must happen before intel_power_domains_init_hw() on VLV/CHV */
- intel_update_rawclk(dev_priv);
-
- intel_power_domains_init_hw(dev_priv, false);
-
intel_csr_ucode_init(dev_priv);
- ret = intel_irq_install(dev_priv);
- if (ret)
- goto cleanup_csr;
-
intel_setup_gmbus(dev_priv);
/* Important: The output setup functions called by modeset_init need
* working irqs for e.g. gmbus and dp aux transfers. */
ret = intel_modeset_init(dev);
if (ret)
- goto cleanup_irq;
-
- ret = i915_gem_init(dev_priv);
- if (ret)
- goto cleanup_modeset;
+ goto cleanup_gmbus;
intel_setup_overlay(dev_priv);
@@ -694,25 +681,18 @@ static int i915_load_modeset_init(struct drm_device *dev)
ret = intel_fbdev_init(dev);
if (ret)
- goto cleanup_gem;
+ goto cleanup_modeset;
/* Only enable hotplug handling once the fbdev is fully set up. */
intel_hpd_init(dev_priv);
return 0;
-cleanup_gem:
- if (i915_gem_suspend(dev_priv))
- DRM_ERROR("failed to idle hardware; continuing to unload!\n");
- i915_gem_fini(dev_priv);
cleanup_modeset:
intel_modeset_cleanup(dev);
-cleanup_irq:
- drm_irq_uninstall(dev);
+cleanup_gmbus:
intel_teardown_gmbus(dev_priv);
-cleanup_csr:
intel_csr_ucode_fini(dev_priv);
- intel_power_domains_fini_hw(dev_priv);
vga_switcheroo_unregister_client(pdev);
cleanup_vga_client:
vga_client_register(pdev, NULL, NULL, NULL);
@@ -1407,9 +1387,25 @@ int i915_driver_load(struct pci_dev *pdev, const struct
pci_device_id *ent)
goto out_cleanup_hw;
}
+ /* must happen before intel_power_domains_init_hw() on VLV/CHV */
+ intel_update_rawclk(dev_priv);
+
+ /* i915_gem_init() call chain will call
+* intel_display_power_put(i915, POWER_DOMAIN_GT_IRQ);
+*/
+ intel_power_domains_init_hw(dev_priv, false);
+
+ ret = intel_irq_install(dev_priv);
+ if (ret)
+ goto out_cleanup_power;
+
+ ret = i915_gem_init(dev_priv);
+ if (ret)
+ goto cleanup_irq;
+
ret = i915_load_modeset_init(_priv->drm);
if (ret < 0)
- goto out_cleanup_hw;
+ goto cleanup_gem;
i915_driver_register(dev_priv);
@@ -1423,6 +1419,15 @@ int i915_driver_load(struct pci_dev *pdev, const struct
pci_device_id *ent)
return 0;
+cleanup_gem:
+ if (i915_gem_suspend(dev_priv))
+ DRM_ERROR("failed to idle hardware; continuing to unload!\n");
+ intel_cleanup_gt_powersave(dev_priv);
+ i915_gem_fini(dev_priv);
+cleanup_irq:
+ drm_irq_uninstall(_priv->drm);
+out_cleanup_power:
+ intel_power_domains_fini_hw(dev_priv);
out_cleanup_hw:
i915_driver_cleanup_hw(dev_priv);
out_cleanup_mmio:
@@ -1441,11 +1446,24 @@ int i915_driver_load(struct pci_dev *pdev, const struct
pci_device_id *ent)
return ret;
}
-void i915_driver_unload(struct drm_device *dev)
+/* unload/cleanup the leftover of i915_load_modeset_init() */
+static void i915_modeset_unload(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
struct pci_dev *pdev = dev_priv->drm.pdev;
+ intel_bios_cleanup(dev_priv);
+
+ vga_switcheroo_unregister_client(pdev);
+ vga_client_register(pdev, NULL, NULL, NULL);
+
+ intel_csr_ucode_fini(dev_priv);
+}
+
+void i915_driver_unload(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = to_i915(dev);
+
i915_driver_unregister(dev_priv);
if (i915_gem_suspend(dev_priv))
@@ -1457,14 +1475,22 @@ void i915_driver_unload(struct drm_device *dev)
intel_gvt_cleanup(dev_priv);
- intel_modeset_cleanup(dev);
+ intel_modeset_cleanup_prepare(dev);
-
[Intel-gfx] [PATCH 19/20] drm/i915: Warn when display irq functions is executed when display is disabled
With previous patches any of this warnings shows up but lets add then
so any other patch that breaks that can be caught by CI tests.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_irq.c | 14 ++
drivers/gpu/drm/i915/intel_hotplug.c | 2 ++
2 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index cb82f56cd7dc..f785ec61fea8 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2511,6 +2511,8 @@ static void ilk_display_irq_handler(struct
drm_i915_private *dev_priv,
enum pipe pipe;
u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
+ WARN_ON_ONCE(!INTEL_INFO(dev_priv)->num_pipes);
+
if (hotplug_trigger)
ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk);
@@ -2557,6 +2559,8 @@ static void ivb_display_irq_handler(struct
drm_i915_private *dev_priv,
enum pipe pipe;
u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
+ WARN_ON_ONCE(!INTEL_INFO(dev_priv)->num_pipes);
+
if (hotplug_trigger)
ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb);
@@ -2725,6 +2729,8 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv,
u32 master_ctl)
u32 iir;
enum pipe pipe;
+ WARN_ON_ONCE(!INTEL_INFO(dev_priv)->num_pipes);
+
if (master_ctl & GEN8_DE_MISC_IRQ) {
iir = I915_READ(GEN8_DE_MISC_IIR);
if (iir) {
@@ -3867,6 +3873,8 @@ static void spt_hpd_irq_setup(struct drm_i915_private
*dev_priv)
{
u32 hotplug_irqs, enabled_irqs;
+ WARN_ON_ONCE(!INTEL_INFO(dev_priv)->num_pipes);
+
hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt);
@@ -3895,6 +3903,8 @@ static void ilk_hpd_irq_setup(struct drm_i915_private
*dev_priv)
{
u32 hotplug_irqs, enabled_irqs;
+ WARN_ON_ONCE(!INTEL_INFO(dev_priv)->num_pipes);
+
if (INTEL_GEN(dev_priv) >= 8) {
hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw);
@@ -3957,6 +3967,8 @@ static void bxt_hpd_irq_setup(struct drm_i915_private
*dev_priv)
{
u32 hotplug_irqs, enabled_irqs;
+ WARN_ON_ONCE(!INTEL_INFO(dev_priv)->num_pipes);
+
enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt);
hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
@@ -4674,6 +4686,8 @@ static void i915_hpd_irq_setup(struct drm_i915_private
*dev_priv)
{
u32 hotplug_en;
+ WARN_ON_ONCE(!INTEL_INFO(dev_priv)->num_pipes);
+
lockdep_assert_held(_priv->irq_lock);
/* Note HDMI and DP share hotplug bits */
diff --git a/drivers/gpu/drm/i915/intel_hotplug.c
b/drivers/gpu/drm/i915/intel_hotplug.c
index 648a13c6043c..908d8e589f9a 100644
--- a/drivers/gpu/drm/i915/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/intel_hotplug.c
@@ -399,6 +399,8 @@ void intel_hpd_irq_handler(struct drm_i915_private
*dev_priv,
if (!pin_mask)
return;
+ WARN_ON_ONCE(!INTEL_INFO(dev_priv)->num_pipes);
+
spin_lock(_priv->irq_lock);
for_each_intel_encoder(_priv->drm, encoder) {
enum hpd_pin pin = encoder->hpd_pin;
--
2.18.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 03/20] drm/i915/runtime_pm: Share code to enable/disable PCH reset handshake
Instead of have the same code spread into 4 platforms lets share it.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 25 -
1 file changed, 12 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index e209edbc561d..9575b7402172 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -3264,18 +3264,24 @@ static void icl_mbus_init(struct drm_i915_private
*dev_priv)
I915_WRITE(MBUS_ABOX_CTL, val);
}
+static void skl_pch_reset_handshake(struct drm_i915_private *dev_priv)
+{
+ u32 val = I915_READ(HSW_NDE_RSTWRN_OPT);
+
+ val |= RESET_PCH_HANDSHAKE_ENABLE;
+ I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
+}
+
static void skl_display_core_init(struct drm_i915_private *dev_priv,
bool resume)
{
struct i915_power_domains *power_domains = _priv->power_domains;
struct i915_power_well *well;
- uint32_t val;
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
/* enable PCH reset handshake */
- val = I915_READ(HSW_NDE_RSTWRN_OPT);
- I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
+ skl_pch_reset_handshake(dev_priv);
/* enable PG1 and Misc I/O */
mutex_lock(_domains->lock);
@@ -3331,7 +3337,6 @@ void bxt_display_core_init(struct drm_i915_private
*dev_priv,
{
struct i915_power_domains *power_domains = _priv->power_domains;
struct i915_power_well *well;
- uint32_t val;
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
@@ -3341,9 +3346,7 @@ void bxt_display_core_init(struct drm_i915_private
*dev_priv,
* Move the handshake programming to initialization sequence.
* Previously was left up to BIOS.
*/
- val = I915_READ(HSW_NDE_RSTWRN_OPT);
- val &= ~RESET_PCH_HANDSHAKE_ENABLE;
- I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
+ skl_pch_reset_handshake(dev_priv);
/* Enable PG1 */
mutex_lock(_domains->lock);
@@ -3464,9 +3467,7 @@ static void cnl_display_core_init(struct drm_i915_private
*dev_priv, bool resume
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
/* 1. Enable PCH Reset Handshake */
- val = I915_READ(HSW_NDE_RSTWRN_OPT);
- val |= RESET_PCH_HANDSHAKE_ENABLE;
- I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
+ skl_pch_reset_handshake(dev_priv);
/* 2. Enable Comp */
val = I915_READ(CHICKEN_MISC_2);
@@ -3549,9 +3550,7 @@ static void icl_display_core_init(struct drm_i915_private
*dev_priv,
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
/* 1. Enable PCH reset handshake. */
- val = I915_READ(HSW_NDE_RSTWRN_OPT);
- val |= RESET_PCH_HANDSHAKE_ENABLE;
- I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
+ skl_pch_reset_handshake(dev_priv);
for (port = PORT_A; port <= PORT_B; port++) {
/* 2. Enable DDI combo PHY comp. */
--
2.18.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 01/20] drm: Let userspace check if driver supports modeset
GPU accelerators usually don't have display block or the display
driver part can be disabled when building driver(for servers it saves
some resources) so it is important let userspace check this
capability too.
Right now we are checking
drmModeGetResources()/drm_mode_getresources() for a error to detect
if display is enabled but it is a hackish way as it can fail for
other reasons too.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/drm_ioctl.c | 3 +++
include/uapi/drm/drm.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
index ea10e9a26aad..3a8438ae9b51 100644
--- a/drivers/gpu/drm/drm_ioctl.c
+++ b/drivers/gpu/drm/drm_ioctl.c
@@ -244,6 +244,9 @@ static int drm_getcap(struct drm_device *dev, void *data,
struct drm_file *file_
case DRM_CAP_SYNCOBJ:
req->value = drm_core_check_feature(dev, DRIVER_SYNCOBJ);
return 0;
+ case DRM_CAP_MODESET:
+ req->value = drm_core_check_feature(dev, DRIVER_MODESET);
+ return 0;
}
/* Other caps only work with KMS drivers */
diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h
index 300f336633f2..85fae6ddbf48 100644
--- a/include/uapi/drm/drm.h
+++ b/include/uapi/drm/drm.h
@@ -649,6 +649,7 @@ struct drm_gem_open {
#define DRM_CAP_PAGE_FLIP_TARGET 0x11
#define DRM_CAP_CRTC_IN_VBLANK_EVENT 0x12
#define DRM_CAP_SYNCOBJ0x13
+#define DRM_CAP_MODESET0x14
/** DRM_IOCTL_GET_CAP ioctl argument type */
struct drm_get_cap {
--
2.18.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 02/20] drm/i915: Set PCH as NOP when display is disabled
num_pipes is set to 0 if disable_display is set inside
intel_device_info_runtime_init() but when that happen PCH will
already be set in intel_detect_pch().
i915_driver_load()
i915_driver_init_early()
...
intel_detect_pch()
...
...
i915_driver_init_hw()
intel_device_info_runtime_init()
So now setting num_pipes = 0 earlier to avoid this problem.
Cc: Jani Nikula
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.c | 5 +
drivers/gpu/drm/i915/intel_device_info.c | 8 ++--
2 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9dce55182c3a..7952f5877402 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -917,6 +917,11 @@ static int i915_driver_init_early(struct drm_i915_private
*dev_priv,
if (ret < 0)
goto err_workqueues;
+ if (i915_modparams.disable_display) {
+ DRM_INFO("Display disabled (module parameter)\n");
+ device_info->num_pipes = 0;
+ }
+
/* This must be called before any calls to HAS_PCH_* */
intel_detect_pch(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index 0ef0c6448d53..67102b481c8f 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -776,12 +776,8 @@ void intel_device_info_runtime_init(struct
intel_device_info *info)
info->num_sprites[pipe] = 1;
}
- if (i915_modparams.disable_display) {
- DRM_INFO("Display disabled (module parameter)\n");
- info->num_pipes = 0;
- } else if (info->num_pipes > 0 &&
- (IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) &&
- HAS_PCH_SPLIT(dev_priv)) {
+ if (info->num_pipes > 0 && (IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) &&
+ HAS_PCH_SPLIT(dev_priv)) {
u32 fuse_strap = I915_READ(FUSE_STRAP);
u32 sfuse_strap = I915_READ(SFUSE_STRAP);
--
2.18.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 14/20] drm/i915: Keep overlay functions naming consistent
All other overlay functions(almost all other functions in i915) follow
intel_overlay_verb, so renaming the ones that do not match that.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 2 +-
drivers/gpu/drm/i915/intel_drv.h | 4 ++--
drivers/gpu/drm/i915/intel_overlay.c | 4 ++--
4 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 7a3794e70187..7e948bf30cdd 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -678,7 +678,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
if (ret)
goto cleanup_gmbus;
- intel_setup_overlay(dev_priv);
+ intel_overlay_setup(dev_priv);
ret = intel_fbdev_init(dev);
if (ret)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index d3ce4cb4b2b5..266cd482325d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -16003,7 +16003,7 @@ void intel_modeset_cleanup(struct drm_device *dev)
drm_mode_config_cleanup(dev);
- intel_cleanup_overlay(dev_priv);
+ intel_overlay_cleanup(dev_priv);
intel_teardown_gmbus(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0601abb8c71f..14545f51b885 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1865,8 +1865,8 @@ void intel_attach_aspect_ratio_property(struct
drm_connector *connector);
/* intel_overlay.c */
-void intel_setup_overlay(struct drm_i915_private *dev_priv);
-void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
+void intel_overlay_setup(struct drm_i915_private *dev_priv);
+void intel_overlay_cleanup(struct drm_i915_private *dev_priv);
int intel_overlay_switch_off(struct intel_overlay *overlay);
int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
diff --git a/drivers/gpu/drm/i915/intel_overlay.c
b/drivers/gpu/drm/i915/intel_overlay.c
index c2f10d899329..a1daedefa0aa 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -1386,7 +1386,7 @@ int intel_overlay_attrs_ioctl(struct drm_device *dev,
void *data,
return ret;
}
-void intel_setup_overlay(struct drm_i915_private *dev_priv)
+void intel_overlay_setup(struct drm_i915_private *dev_priv)
{
struct intel_overlay *overlay;
struct drm_i915_gem_object *reg_bo;
@@ -1475,7 +1475,7 @@ void intel_setup_overlay(struct drm_i915_private
*dev_priv)
return;
}
-void intel_cleanup_overlay(struct drm_i915_private *dev_priv)
+void intel_overlay_cleanup(struct drm_i915_private *dev_priv)
{
if (!dev_priv->overlay)
return;
--
2.18.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Allow control of PSR at runtime through debugfs, v5
On Wed, 2018-08-08 at 16:19 +0200, Maarten Lankhorst wrote:
> Currently tests modify i915.enable_psr and then do a modeset cycle
> to change PSR. We can write a value to i915_edp_psr_debug to force
> a certain PSR mode without a modeset.
>
> To retain compatibility with older userspace, we also still allow
> the override through the module parameter, and add some tracking
> to check whether a debugfs mode is specified.
>
> Changes since v1:
> - Rename dev_priv->psr.enabled to .dp, and .hw_configured to
> .enabled.
> - Fix i915_psr_debugfs_mode to match the writes to debugfs.
> - Rename __i915_edp_psr_write to intel_psr_set_debugfs_mode, simplify
> it and move it to intel_psr.c. This keeps all internals in
> intel_psr.c
> - Perform an interruptible wait for hw completion outside of the psr
> lock, instead of being forced to trywait and return -EBUSY.
> Changes since v2:
> - Rebase on top of intel_psr changes.
> Changes since v3:
> - Assign psr.dp during init. (dhnkrn)
> - Add prepared bool, which should be used instead of relying on
> psr.dp. (dhnkrn)
> - Fix -EDEADLK handling in debugfs. (dhnkrn)
> - Clean up waiting for idle in intel_psr_set_debugfs_mode.
> - Print PSR mode when trying to enable PSR. (dhnkrn)
> - Move changing psr debug setting to i915_edp_psr_debug_set. (dhnkrn)
> Changes since v4:
> - Return error in _set() function.
> - Change flag values to make them easier to remember. (dhnkrn)
> - Only assign psr.dp once. (dhnkrn)
> - Only set crtc_state->has_psr on the crtc with psr.dp.
> - Fix typo. (dhnkrn)
>
> Signed-off-by: Maarten Lankhorst
> Cc: Rodrigo Vivi
> Cc: Dhinakaran Pandiyan
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 23 -
> drivers/gpu/drm/i915/i915_drv.h | 12 ++-
> drivers/gpu/drm/i915/i915_irq.c | 2 +-
> drivers/gpu/drm/i915/intel_drv.h| 5 +-
> drivers/gpu/drm/i915/intel_psr.c| 138 +++---
> --
> 5 files changed, 149 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index f9ce35da4123..3e81301a94ba 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2708,7 +2708,7 @@ static int i915_edp_psr_status(struct seq_file
> *m, void *data)
> intel_runtime_pm_get(dev_priv);
>
> mutex_lock(_priv->psr.lock);
> - seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv-
> >psr.enabled));
> + seq_printf(m, "Enabled: %s\n", yesno(dev_priv-
> >psr.enabled));
> seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
> dev_priv->psr.busy_frontbuffer_bits);
>
> @@ -2750,17 +2750,32 @@ static int
> i915_edp_psr_debug_set(void *data, u64 val)
> {
> struct drm_i915_private *dev_priv = data;
> + struct drm_modeset_acquire_ctx ctx;
> + int ret;
>
> if (!CAN_PSR(dev_priv))
> return -ENODEV;
>
> - DRM_DEBUG_KMS("PSR debug %s\n", enableddisabled(val));
> + DRM_DEBUG_KMS("Setting PSR debug to %llx\n", val);
>
> intel_runtime_pm_get(dev_priv);
> - intel_psr_irq_control(dev_priv, !!val);
> +
> + drm_modeset_acquire_init(,
> DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
> +
> +retry:
> + ret = intel_psr_set_debugfs_mode(dev_priv, , val);
> + if (ret == -EDEADLK) {
> + ret = drm_modeset_backoff();
> + if (!ret)
> + goto retry;
> + }
> +
> + drm_modeset_drop_locks();
> + drm_modeset_acquire_fini();
> +
> intel_runtime_pm_put(dev_priv);
>
> - return 0;
> + return ret;
> }
>
> static int
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index 657f46e0cae9..a3ea48ce1811 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -611,8 +611,17 @@ struct i915_drrs {
>
> struct i915_psr {
> struct mutex lock;
> +
> +#define I915_PSR_DEBUG_MODE_MASK 0x0f
> +#define I915_PSR_DEBUG_DEFAULT 0x00
> +#define I915_PSR_DEBUG_DISABLE 0x01
> +#define I915_PSR_DEBUG_ENABLE0x02
> +#define I915_PSR_DEBUG_IRQ 0x10
> +
> + u32 debug;
u16?
> bool sink_support;
> - struct intel_dp *enabled;
> + bool prepared, enabled;
> + struct intel_dp *dp;
> bool active;
> struct work_struct work;
> unsigned busy_frontbuffer_bits;
> @@ -622,7 +631,6 @@ struct i915_psr {
> bool alpm;
> bool psr2_enabled;
> u8 sink_sync_latency;
> - bool debug;
> ktime_t last_entry_attempt;
> ktime_t last_exit;
> };
> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> b/drivers/gpu/drm/i915/i915_irq.c
> index 8084e35b25c5..b2c9838442bc 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -4048,7 +4048,7 @@ static int ironlake_irq_postinstall(struct
> drm_device *dev)
>
> if (IS_HASWELL(dev_priv)) {
> gen3_assert_iir_is_zero(dev_priv,
Re: [Intel-gfx] [PATCH v1] Added max_bpp property to limit maximum bpp even if HDMI TV advertises higher limit.
On Thu, Jul 26, 2018 at 04:02:53PM +0300, StanLis wrote:
> From: Stanislav Lisovskiy
>
> This was inspired, by a bugs like this:
>
> Bugzilla: https://bugs.freedesktop.org/93361
>
> In short, when TV advertises 12bpc, the refresh
> rate might get inaccurate causing some playback
> issues.
>
> The temporary solution was to hack the EDID,
> so that it doesn't advertise deep color, so this
> new property makes it unnecessary.
>
> Long term solution would be to change clock frequency,
> however this affects all the clock tree and might not
> be doable, so this is the currently proposed fix.
It seems that the fix for this should be on the refresh rate side,
not providing an option to the user to workaround and hide the issue.
>
> Signed-off-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_atomic.c | 8
> drivers/gpu/drm/i915/intel_drv.h| 4
> drivers/gpu/drm/i915/intel_hdmi.c | 13 -
> drivers/gpu/drm/i915/intel_modes.c | 20
> 5 files changed, 41 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index eeb002a47032..823eccd29f70 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1817,6 +1817,7 @@ struct drm_i915_private {
> struct intel_fbdev *fbdev;
> struct work_struct fbdev_suspend_work;
>
> + struct drm_property *max_bpp_property;
> struct drm_property *broadcast_rgb_property;
> struct drm_property *force_audio_property;
>
> diff --git a/drivers/gpu/drm/i915/intel_atomic.c
> b/drivers/gpu/drm/i915/intel_atomic.c
> index b04952bacf77..ac890fda8029 100644
> --- a/drivers/gpu/drm/i915/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/intel_atomic.c
> @@ -58,6 +58,8 @@ int intel_digital_connector_atomic_get_property(struct
> drm_connector *connector,
> *val = intel_conn_state->force_audio;
> else if (property == dev_priv->broadcast_rgb_property)
> *val = intel_conn_state->broadcast_rgb;
> + else if (property == dev_priv->max_bpp_property)
> + *val = intel_conn_state->max_bpp;
> else {
> DRM_DEBUG_ATOMIC("Unknown property [PROP:%d:%s]\n",
>property->base.id, property->name);
> @@ -96,6 +98,11 @@ int intel_digital_connector_atomic_set_property(struct
> drm_connector *connector,
> return 0;
> }
>
> + if (property == dev_priv->max_bpp_property) {
> + intel_conn_state->max_bpp = val;
> + return 0;
> + }
> +
> DRM_DEBUG_ATOMIC("Unknown property [PROP:%d:%s]\n",
>property->base.id, property->name);
> return -EINVAL;
> @@ -126,6 +133,7 @@ int intel_digital_connector_atomic_check(struct
> drm_connector *conn,
> if (new_conn_state->force_audio != old_conn_state->force_audio ||
> new_conn_state->broadcast_rgb != old_conn_state->broadcast_rgb ||
> new_conn_state->base.picture_aspect_ratio !=
> old_conn_state->base.picture_aspect_ratio ||
> + new_conn_state->max_bpp != old_conn_state->max_bpp ||
> new_conn_state->base.content_type !=
> old_conn_state->base.content_type ||
> new_conn_state->base.scaling_mode !=
> old_conn_state->base.scaling_mode)
> crtc_state->mode_changed = true;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 61e715ddd0d5..38d1f430b44f 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -422,6 +422,7 @@ struct intel_digital_connector_state {
>
> enum hdmi_force_audio force_audio;
> int broadcast_rgb;
> + int max_bpp;
> };
>
> #define to_intel_digital_connector_state(x) container_of(x, struct
> intel_digital_connector_state, base)
> @@ -1837,9 +1838,12 @@ bool intel_is_dual_link_lvds(struct drm_device *dev);
> int intel_connector_update_modes(struct drm_connector *connector,
>struct edid *edid);
> int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter
> *adapter);
> +
> void intel_attach_force_audio_property(struct drm_connector *connector);
> void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
> void intel_attach_aspect_ratio_property(struct drm_connector *connector);
> +void intel_attach_force_max_bpp_property(struct drm_connector *connector);
> +
>
>
> /* intel_overlay.c */
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
> b/drivers/gpu/drm/i915/intel_hdmi.c
> index 8363fbd18ee8..323b96f5eac7 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1748,15 +1748,16 @@ bool intel_hdmi_compute_config(struct intel_encoder
> *encoder,
>*/
> if (hdmi_deep_color_possible(pipe_config, 12) &&
> hdmi_port_clock_valid(intel_hdmi, clock_12bpc,
> -
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gvt: fix memory leak in intel_vgpu_ioctl() (rev3)
== Series Details ==
Series: drm/i915/gvt: fix memory leak in intel_vgpu_ioctl() (rev3)
URL : https://patchwork.freedesktop.org/series/47685/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4635 -> Patchwork_9895 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/47685/revisions/3/mbox/
== Known issues ==
Here are the changes found in Patchwork_9895 that come from known issues:
=== IGT changes ===
Issues hit
{igt@amdgpu/amd_prime@amd-to-i915}:
{fi-kbl-8809g}: NOTRUN -> FAIL (fdo#107341)
Possible fixes
{igt@amdgpu/amd_basic@userptr}:
{fi-kbl-8809g}: INCOMPLETE (fdo#107402) -> PASS
igt@drv_selftest@live_hangcheck:
fi-cnl-psr: DMESG-FAIL (fdo#106560) -> PASS
fi-skl-guc: DMESG-FAIL (fdo#107174) -> PASS
igt@kms_pipe_crc_basic@read-crc-pipe-b:
{fi-byt-clapper}: FAIL (fdo#107362) -> PASS
Warnings
{igt@kms_psr@primary_page_flip}:
fi-cnl-psr: DMESG-FAIL (fdo#107372) -> DMESG-WARN (fdo#107372)
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
fdo#107174 https://bugs.freedesktop.org/show_bug.cgi?id=107174
fdo#107341 https://bugs.freedesktop.org/show_bug.cgi?id=107341
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107372 https://bugs.freedesktop.org/show_bug.cgi?id=107372
fdo#107402 https://bugs.freedesktop.org/show_bug.cgi?id=107402
== Participating hosts (50 -> 46) ==
Additional (1): fi-hsw-peppy
Missing(5): fi-byt-j1900 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4635 -> Patchwork_9895
CI_DRM_4635: a9f34f7e3bab765e2b1320a1b154a76be38602a7 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4589: 779d2d42f9db6a2797d1ef50036af6fac4e62e73 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9895: 0346e934b498e4ad48ea35e6465a2baa0e5fa8a3 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
0346e934b498 drm/i915/gvt: fix memory leak in intel_vgpu_ioctl()
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9895/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Re-apply "Perform link quality check, unconditionally during long pulse" (rev3)
== Series Details ==
Series: drm/i915: Re-apply "Perform link quality check, unconditionally during
long pulse" (rev3)
URL : https://patchwork.freedesktop.org/series/47694/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4635 -> Patchwork_9894 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/47694/revisions/3/mbox/
== Known issues ==
Here are the changes found in Patchwork_9894 that come from known issues:
=== IGT changes ===
Issues hit
{igt@amdgpu/amd_prime@amd-to-i915}:
{fi-kbl-8809g}: NOTRUN -> FAIL (fdo#107341)
igt@drv_selftest@live_hangcheck:
fi-kbl-7560u: PASS -> DMESG-FAIL (fdo#106560, fdo#106947)
igt@kms_frontbuffer_tracking@basic:
{fi-byt-clapper}: PASS -> FAIL (fdo#103167)
igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
{fi-byt-clapper}: PASS -> FAIL (fdo#107362)
Possible fixes
{igt@amdgpu/amd_basic@userptr}:
{fi-kbl-8809g}: INCOMPLETE (fdo#107402) -> PASS
igt@drv_selftest@live_hangcheck:
fi-cnl-psr: DMESG-FAIL (fdo#106560) -> PASS
fi-skl-guc: DMESG-FAIL (fdo#107174) -> PASS
igt@kms_pipe_crc_basic@read-crc-pipe-b:
{fi-byt-clapper}: FAIL (fdo#107362) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
fdo#106947 https://bugs.freedesktop.org/show_bug.cgi?id=106947
fdo#107174 https://bugs.freedesktop.org/show_bug.cgi?id=107174
fdo#107341 https://bugs.freedesktop.org/show_bug.cgi?id=107341
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107402 https://bugs.freedesktop.org/show_bug.cgi?id=107402
== Participating hosts (50 -> 47) ==
Additional (1): fi-hsw-peppy
Missing(4): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4635 -> Patchwork_9894
CI_DRM_4635: a9f34f7e3bab765e2b1320a1b154a76be38602a7 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4589: 779d2d42f9db6a2797d1ef50036af6fac4e62e73 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9894: c8a6ddc5b49269876fdbda9f2d58f28d4694070a @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
c8a6ddc5b492 v3 drm/i915: Re-apply "Perform link quality check, unconditionally
during long pulse"
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9894/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915: kill intel_display_power_well_is_enabled()
Em Qua, 2018-08-08 às 22:22 +, Patchwork escreveu: > == Series Details == > > Series: series starting with [1/4] drm/i915: kill > intel_display_power_well_is_enabled() > URL : https://patchwork.freedesktop.org/series/47908/ > State : warning > > == Summary == > > $ dim checkpatch origin/drm-tip > 94cddb6f9752 drm/i915: kill intel_display_power_well_is_enabled() > dfb09a8944b0 drm/i915: BUG() if we can't lookup_power_well() > -:31: WARNING:AVOID_BUG: Avoid crashing the kernel - try using > WARN_ON & recovery code rather than BUG() or BUG_ON() > #31: FILE: drivers/gpu/drm/i915/intel_runtime_pm.c:1124: > + BUG(); See the commit message of patch 2, Mr. Robot. I don't think it's worth adding checking code in the callers, and replacing the current null pointer dereference with a BUG() is an improvement IMHO. If anybody disagrees with this, please say so. > > total: 0 errors, 1 warnings, 0 checks, 9 lines checked > e5298551c379 drm/i915: use for_each_power_well in lookup_power_well() > 942f90859025 drm/i915: move lookup_power_well() up > -:40: WARNING:AVOID_BUG: Avoid crashing the kernel - try using > WARN_ON & recovery code rather than BUG() or BUG_ON() > #40: FILE: drivers/gpu/drm/i915/intel_runtime_pm.c:683: > + BUG(); > > total: 0 errors, 1 warnings, 0 checks, 50 lines checked > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: remove the unnecessary restriction for NV12 in intel_framebuffer_init
== Series Details ==
Series: drm/i915: remove the unnecessary restriction for NV12 in
intel_framebuffer_init
URL : https://patchwork.freedesktop.org/series/47909/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4635 -> Patchwork_9893 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/47909/revisions/1/mbox/
== Known issues ==
Here are the changes found in Patchwork_9893 that come from known issues:
=== IGT changes ===
Issues hit
{igt@amdgpu/amd_prime@amd-to-i915}:
{fi-kbl-8809g}: NOTRUN -> FAIL (fdo#107341)
igt@drv_selftest@live_coherency:
fi-gdg-551: PASS -> DMESG-FAIL (fdo#107164)
igt@drv_selftest@live_hangcheck:
{fi-cfl-8109u}: PASS -> DMESG-FAIL (fdo#106560)
igt@drv_selftest@live_workarounds:
fi-skl-6700hq: PASS -> DMESG-FAIL (fdo#107292)
Possible fixes
{igt@amdgpu/amd_basic@userptr}:
{fi-kbl-8809g}: INCOMPLETE (fdo#107402) -> PASS
igt@drv_selftest@live_hangcheck:
fi-cnl-psr: DMESG-FAIL (fdo#106560) -> PASS
fi-skl-guc: DMESG-FAIL (fdo#107174) -> PASS
igt@kms_pipe_crc_basic@read-crc-pipe-b:
{fi-byt-clapper}: FAIL (fdo#107362) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
fdo#107164 https://bugs.freedesktop.org/show_bug.cgi?id=107164
fdo#107174 https://bugs.freedesktop.org/show_bug.cgi?id=107174
fdo#107292 https://bugs.freedesktop.org/show_bug.cgi?id=107292
fdo#107341 https://bugs.freedesktop.org/show_bug.cgi?id=107341
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107402 https://bugs.freedesktop.org/show_bug.cgi?id=107402
== Participating hosts (50 -> 46) ==
Additional (1): fi-hsw-peppy
Missing(5): fi-byt-squawks fi-ilk-m540 fi-bxt-dsi fi-bsw-cyan
fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4635 -> Patchwork_9893
CI_DRM_4635: a9f34f7e3bab765e2b1320a1b154a76be38602a7 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4589: 779d2d42f9db6a2797d1ef50036af6fac4e62e73 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9893: b513210d05436fa3906e4d9258ceca693b6fe7ca @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
b513210d0543 drm/i915: remove the unnecessary restriction for NV12 in
intel_framebuffer_init
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9893/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/4] drm/i915: kill intel_display_power_well_is_enabled()
Em Qua, 2018-08-08 às 15:22 -0700, Souza, Jose escreveu:
> On Wed, 2018-08-08 at 15:16 -0700, Paulo Zanoni wrote:
> > Use the same coding pattern as we use in the other functions of the
> > same file: just call lookup_power_well() directly in the only
> > caller.
> >
> > Cc: Imre Deak
> > Signed-off-by: Paulo Zanoni
> > ---
> > drivers/gpu/drm/i915/intel_runtime_pm.c | 20 +++-
> > 1 file changed, 3 insertions(+), 17 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index e209edbc561d..e0947f662361 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -49,9 +49,6 @@
> > * present for a given platform.
> > */
> >
> > -bool intel_display_power_well_is_enabled(struct drm_i915_private
> > *dev_priv,
> > -enum i915_power_well_id
> > power_well_id);
> > -
> > static struct i915_power_well *
> > lookup_power_well(struct drm_i915_private *dev_priv,
> > enum i915_power_well_id power_well_id);
> > @@ -678,8 +675,9 @@ static void assert_csr_loaded(struct
> > drm_i915_private *dev_priv)
> >
> > static void assert_can_enable_dc5(struct drm_i915_private
> > *dev_priv)
> > {
> > - bool pg2_enabled =
> > intel_display_power_well_is_enabled(dev_priv,
> > - SKL_DISP_PW_2);
> > + struct i915_power_well *pg2 = lookup_power_well(dev_priv,
> > + SKL_DISP_P
> > W_2);
> > + bool pg2_enabled = pg2->desc->ops->is_enabled(dev_priv,
> > pg2);
>
> Why not trust our sync with hardware and use pg2->hw_enabled?
While that's a very reasonable thing and it sounds like something we
should do (as far as I have investigated in 5 minutes), it's a
functional change with a potential downside and should be in a separate
patch IMHO.
>
> >
> > WARN_ONCE(pg2_enabled, "PG2 not disabled to enable
> > DC5.\n");
> >
> > @@ -2302,18 +2300,6 @@ static const struct i915_power_well_desc
> > chv_power_wells[] = {
> > },
> > };
> >
> > -bool intel_display_power_well_is_enabled(struct drm_i915_private
> > *dev_priv,
> > -enum i915_power_well_id
> > power_well_id)
> > -{
> > - struct i915_power_well *power_well;
> > - bool ret;
> > -
> > - power_well = lookup_power_well(dev_priv, power_well_id);
> > - ret = power_well->desc->ops->is_enabled(dev_priv,
> > power_well);
> > -
> > - return ret;
> > -}
> > -
> > static const struct i915_power_well_desc skl_power_wells[] = {
> > {
> > .name = "always-on",
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/4] drm/i915: use for_each_power_well in lookup_power_well()
On Wed, 2018-08-08 at 15:16 -0700, Paulo Zanoni wrote:
> Use the nice helper function to make the implementation simpler.
>
Reviewed-by: José Roberto de Souza
> Cc: Imre Deak
> Signed-off-by: Paulo Zanoni
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 9 ++---
> 1 file changed, 2 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 2fdb1f4125c2..eabf98d153f7 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -1109,16 +1109,11 @@ static struct i915_power_well *
> lookup_power_well(struct drm_i915_private *dev_priv,
> enum i915_power_well_id power_well_id)
> {
> - struct i915_power_domains *power_domains = _priv-
> >power_domains;
> - int i;
> -
> - for (i = 0; i < power_domains->power_well_count; i++) {
> - struct i915_power_well *power_well;
> + struct i915_power_well *power_well;
>
> - power_well = _domains->power_wells[i];
> + for_each_power_well(dev_priv, power_well)
> if (power_well->desc->id == power_well_id)
> return power_well;
> - }
>
> /* Tried to lookup a power well that doesn't exist for the
> platform. */
> BUG();
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] v2 drm/i915: Re-apply "Perform link quality check, unconditionally during long pulse"
Am August 7, 2018 7:33:12 PM UTC schrieb Lyude Paul :
>On Mon, 2018-08-06 at 12:25 +0200, Jan-Marek Glogowski wrote:
>> This re-applies the workaround for "some DP sinks, [which] are a
>> little nuts" from commit 1a36147bb939 ("drm/i915: Perform link
>> quality check unconditionally during long pulse").
>> It makes the secondary AOC E2460P monitor connected via DP to an
>> acer Veriton N4640G usable again.
>>
>> This hunk was dropped in commit c85d200e8321 ("drm/i915: Move SST
>> DP link retraining into the ->post_hotplug() hook")
>>
>> Signed-off-by: Jan-Marek Glogowski
>> ---
>> drivers/gpu/drm/i915/intel_dp.c | 46
>
>> -
>> 1 file changed, 27 insertions(+), 19 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c
>> b/drivers/gpu/drm/i915/intel_dp.c
>> index 8e0e14b..7e6f8a5 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -4333,18 +4333,6 @@ intel_dp_needs_link_retrain(struct intel_dp
>> *intel_dp)
>> return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
>> }
>>
>> -/*
>> - * If display is now connected check links status,
>> - * there has been known issues of link loss triggering
>> - * long pulse.
>> - *
>> - * Some sinks (eg. ASUS PB287Q) seem to perform some
>> - * weird HPD ping pong during modesets. So we can apparently
>> - * end up with HPD going low during a modeset, and then
>> - * going back up soon after. And once that happens we must
>> - * retrain the link to get a picture. That's in case no
>> - * userspace component reacted to intermittent HPD dip.
>> - */
>> int intel_dp_retrain_link(struct intel_encoder *encoder,
>>struct drm_modeset_acquire_ctx *ctx)
>> {
>> @@ -4361,10 +4349,12 @@ int intel_dp_retrain_link(struct
>intel_encoder
>> *encoder,
>> if (!connector || connector->base.status !=
>> connector_status_connected)
>> return 0;
>>
>> -ret = drm_modeset_lock(_priv->drm.mode_config.connection_mutex,
>> - ctx);
>> -if (ret)
>> -return ret;
>> +if (ctx) {
>> +ret = drm_modeset_lock
>> +(_priv->drm.mode_config.connection_mutex, ctx);
>> +if (ret)
>> +return ret;
>> +}
>...why are we skipping locking anything if there isn't a
>drm_modeset_acquire_ctx passed to us? And additionally, why wouldn't
>there be
>an acquisition context passed to us? We always need to be holding the
>connection mutex and the respective CRTC lock whenever we're
>retraining.
The original patch added all the locking to intel_dp_retrain_link.
intel_dp_long_pulse is just called from intel_dp_detect, which takes the
drm_modeset_lock depending on a valid crtc. I just assumed this is still
sufficient, so for this case we don't need to acquire the lock again. If this
is not sufficient, we can forward the ctx, state etc. from intel_dp_detect. I
didn't check, if these values are the same values that intel_dp_retrain_link
collects using different calls.
There is also the
"WARN_ON(!drm_modeset_is_locked(_priv->drm.mode_config.connection_mutex));"
in intel_dp_long_pulse, which suggests we should also already have the
connection_mutex when calling intel_dp_retrain_link later.
All my assumptions are based on reading the original patch and a little bit of
the surrounding code.
This patch is just a minimal change, which "works for me". Not sure if all the
locking should be moved back to the retrain call sites, to make it more
explicit?
>>
>> conn_state = connector->base.state;
>>
>> @@ -4372,9 +4362,11 @@ int intel_dp_retrain_link(struct intel_encoder
>> *encoder,
>> if (!crtc)
>> return 0;
>>
>> -ret = drm_modeset_lock(>base.mutex, ctx);
>> -if (ret)
>> -return ret;
>> +if (ctx) {
>> +ret = drm_modeset_lock(>base.mutex, ctx);
>> +if (ret)
>> +return ret;
>> +}
>>
>> crtc_state = to_intel_crtc_state(crtc->base.state);
>>
>> @@ -4982,6 +4974,22 @@ intel_dp_long_pulse(struct intel_connector
>> *connector)
>> */
>> status = connector_status_disconnected;
>> goto out;
>> +} else {
>> +/*
>> + * If display is now connected check links status,
>> + * there has been known issues of link loss triggering
>> + * long pulse.
>> + *
>> + * Some sinks (eg. ASUS PB287Q) seem to perform some
>> + * weird HPD ping pong during modesets. So we can apparently
>> + * end up with HPD going low during a modeset, and then
>> + * going back up soon after. And once that happens we must
>> + * retrain the link to get a picture. That's in case no
>> + * userspace component reacted to intermittent HPD dip.
>> + */
>> +struct intel_encoder *encoder =
[Intel-gfx] [PATCH v2] drm/i915/gvt: fix memory leak in intel_vgpu_ioctl()
The 'sparse' variable may leak when return in function
intel_vgpu_ioctl(), and this patch fix this.
Signed-off-by: Yi Wang
Reviewed-by: Jiang Biao
---
v2: fix a double-free error. Thanks to Zhenyu Wang.
drivers/gpu/drm/i915/gvt/kvmgt.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index df4e4a0..bce60cc 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -1195,11 +1195,13 @@ static long intel_vgpu_ioctl(struct mdev_device *mdev,
unsigned int cmd,
>header, sizeof(*sparse) +
(sparse->nr_areas *
sizeof(*sparse->areas)));
- kfree(sparse);
- if (ret)
+ if (ret) {
+ kfree(sparse);
return ret;
+ }
break;
default:
+ kfree(sparse);
return -EINVAL;
}
}
@@ -1215,6 +1217,7 @@ static long intel_vgpu_ioctl(struct mdev_device *mdev,
unsigned int cmd,
sizeof(info), caps.buf,
caps.size)) {
kfree(caps.buf);
+ kfree(sparse);
return -EFAULT;
}
info.cap_offset = sizeof(info);
@@ -1223,6 +1226,7 @@ static long intel_vgpu_ioctl(struct mdev_device *mdev,
unsigned int cmd,
kfree(caps.buf);
}
+ kfree(sparse);
return copy_to_user((void __user *)arg, , minsz) ?
-EFAULT : 0;
} else if (cmd == VFIO_DEVICE_GET_IRQ_INFO) {
--
1.8.3.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/gvt: fix memory leak in intel_vgpu_ioctl()
> On 2018.08.03 08:41:19 +0800, Yi Wang wrote:
> > The 'sparse' variable may leak when return in function
> > intel_vgpu_ioctl(), and this patch fixes this.
> >
> > Signed-off-by: Yi Wang
> > Reviewed-by: Jiang Biao
> > ---
> > drivers/gpu/drm/i915/gvt/kvmgt.c | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c
> > b/drivers/gpu/drm/i915/gvt/kvmgt.c
> > index df4e4a0..6a6f199 100644
> > --- a/drivers/gpu/drm/i915/gvt/kvmgt.c
> > +++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
> > @@ -1200,6 +1200,7 @@ static long intel_vgpu_ioctl(struct mdev_device
> > *mdev, unsigned int cmd,
> > return ret;
> > break;
> > default:
> > +kfree(sparse);
> > return -EINVAL;
> > }
> > }
> > @@ -1215,6 +1216,7 @@ static long intel_vgpu_ioctl(struct mdev_device
> > *mdev, unsigned int cmd,
> >sizeof(info), caps.buf,
> >caps.size)) {
> > kfree(caps.buf);
> > +kfree(sparse);
> > return -EFAULT;
> > }
> > info.cap_offset = sizeof(info);
> > @@ -1223,6 +1225,7 @@ static long intel_vgpu_ioctl(struct mdev_device
> > *mdev, unsigned int cmd,
> > kfree(caps.buf);
> > }
> >
> > +kfree(sparse);
>
> Unfortunately this would cause a double-free error in normal path, as we
> tried to free sparse after use to add caps. So may be better to fix free
> in error path and move normal free of sparse in final point, e.g
Yeah, that's right! Thanks a lot for your advice. I will send a v2 patch.
---
Best wishes
Yi Wang___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v6 0/9] drm/i915: Implement HDCP
Hi Sean, In my work project, we have a requirement to play HDCP protected DASH streams on Chrome on Android phones which fails right now(presumably due to missing HDCP support, since we can reproduce this issue only on chrome on Linux, desktop as well as android) and was wondering if your patch or something like that needs to go in to get it supported. Was your patch or similar code merged to the master branch? Is there something similar present in the Android codebase to support HDCP on chrome that you know of? I am sorry if the questions are not more detailed, as I don't work at the system level and don't understand driver-level details. Would appreciate a quick reply, as the requirement is urgent. Thanks, Vivek ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] v3 drm/i915: Re-apply "Perform link quality check, unconditionally during long pulse"
This re-applies the workaround for "some DP sinks, [which] are a
little nuts" from commit 1a36147bb939 ("drm/i915: Perform link
quality check unconditionally during long pulse").
It makes the secondary AOC E2460P monitor connected via DP to an
acer Veriton N4640G usable again.
This hunk was dropped in commit c85d200e8321 ("drm/i915: Move SST
DP link retraining into the ->post_hotplug() hook")
Signed-off-by: Jan-Marek Glogowski
---
drivers/gpu/drm/i915/intel_dp.c | 33 +++--
1 file changed, 19 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8e0e14b..22b2452 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4333,18 +4333,6 @@ intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
}
-/*
- * If display is now connected check links status,
- * there has been known issues of link loss triggering
- * long pulse.
- *
- * Some sinks (eg. ASUS PB287Q) seem to perform some
- * weird HPD ping pong during modesets. So we can apparently
- * end up with HPD going low during a modeset, and then
- * going back up soon after. And once that happens we must
- * retrain the link to get a picture. That's in case no
- * userspace component reacted to intermittent HPD dip.
- */
int intel_dp_retrain_link(struct intel_encoder *encoder,
struct drm_modeset_acquire_ctx *ctx)
{
@@ -4923,7 +4911,8 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
}
static int
-intel_dp_long_pulse(struct intel_connector *connector)
+intel_dp_long_pulse(struct intel_connector *connector,
+ struct drm_modeset_acquire_ctx *ctx)
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_dp *intel_dp = intel_attached_dp(>base);
@@ -4982,6 +4971,22 @@ intel_dp_long_pulse(struct intel_connector *connector)
*/
status = connector_status_disconnected;
goto out;
+ } else {
+ /*
+* If display is now connected check links status,
+* there has been known issues of link loss triggering
+* long pulse.
+*
+* Some sinks (eg. ASUS PB287Q) seem to perform some
+* weird HPD ping pong during modesets. So we can apparently
+* end up with HPD going low during a modeset, and then
+* going back up soon after. And once that happens we must
+* retrain the link to get a picture. That's in case no
+* userspace component reacted to intermittent HPD dip.
+*/
+ struct intel_encoder *encoder = _to_dig_port(intel_dp)->base;
+
+ intel_dp_retrain_link(encoder, ctx);
}
/*
@@ -5043,7 +5048,7 @@ intel_dp_detect(struct drm_connector *connector,
return ret;
}
- status = intel_dp_long_pulse(intel_dp->attached_connector);
+ status = intel_dp_long_pulse(intel_dp->attached_connector, ctx);
}
intel_dp->detect_done = false;
--
2.1.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: remove the unnecessary restriction for NV12 in intel_framebuffer_init
== Series Details == Series: drm/i915: remove the unnecessary restriction for NV12 in intel_framebuffer_init URL : https://patchwork.freedesktop.org/series/47909/ State : warning == Summary == $ dim checkpatch origin/drm-tip b513210d0543 drm/i915: remove the unnecessary restriction for NV12 in intel_framebuffer_init -:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #10: framebuffer for NV12 requires the pitch to the multiplier of 4, instead of the total: 0 errors, 1 warnings, 0 checks, 8 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: kill intel_display_power_well_is_enabled()
== Series Details ==
Series: series starting with [1/4] drm/i915: kill
intel_display_power_well_is_enabled()
URL : https://patchwork.freedesktop.org/series/47908/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4635 -> Patchwork_9892 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/47908/revisions/1/mbox/
== Known issues ==
Here are the changes found in Patchwork_9892 that come from known issues:
=== IGT changes ===
Issues hit
{igt@amdgpu/amd_prime@amd-to-i915}:
{fi-kbl-8809g}: NOTRUN -> FAIL (fdo#107341)
igt@drv_selftest@live_coherency:
fi-gdg-551: PASS -> DMESG-FAIL (fdo#107164)
igt@drv_selftest@live_workarounds:
fi-whl-u: PASS -> DMESG-FAIL (fdo#107292)
fi-cnl-psr: PASS -> DMESG-FAIL (fdo#107292)
igt@kms_frontbuffer_tracking@basic:
{fi-byt-clapper}: PASS -> FAIL (fdo#103167)
{igt@kms_psr@primary_page_flip}:
fi-skl-6600u: PASS -> FAIL (fdo#107336)
Possible fixes
{igt@amdgpu/amd_basic@userptr}:
{fi-kbl-8809g}: INCOMPLETE (fdo#107402) -> PASS
igt@drv_selftest@live_hangcheck:
fi-cnl-psr: DMESG-FAIL (fdo#106560) -> PASS
igt@kms_pipe_crc_basic@read-crc-pipe-b:
{fi-byt-clapper}: FAIL (fdo#107362) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
fdo#107164 https://bugs.freedesktop.org/show_bug.cgi?id=107164
fdo#107292 https://bugs.freedesktop.org/show_bug.cgi?id=107292
fdo#107336 https://bugs.freedesktop.org/show_bug.cgi?id=107336
fdo#107341 https://bugs.freedesktop.org/show_bug.cgi?id=107341
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107402 https://bugs.freedesktop.org/show_bug.cgi?id=107402
== Participating hosts (50 -> 47) ==
Additional (1): fi-hsw-peppy
Missing(4): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4635 -> Patchwork_9892
CI_DRM_4635: a9f34f7e3bab765e2b1320a1b154a76be38602a7 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4589: 779d2d42f9db6a2797d1ef50036af6fac4e62e73 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9892: 942f90859025412da524cfe6b53b2b5b05e84b9c @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
942f90859025 drm/i915: move lookup_power_well() up
e5298551c379 drm/i915: use for_each_power_well in lookup_power_well()
dfb09a8944b0 drm/i915: BUG() if we can't lookup_power_well()
94cddb6f9752 drm/i915: kill intel_display_power_well_is_enabled()
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9892/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915: kill intel_display_power_well_is_enabled()
== Series Details == Series: series starting with [1/4] drm/i915: kill intel_display_power_well_is_enabled() URL : https://patchwork.freedesktop.org/series/47908/ State : warning == Summary == $ dim checkpatch origin/drm-tip 94cddb6f9752 drm/i915: kill intel_display_power_well_is_enabled() dfb09a8944b0 drm/i915: BUG() if we can't lookup_power_well() -:31: WARNING:AVOID_BUG: Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON() #31: FILE: drivers/gpu/drm/i915/intel_runtime_pm.c:1124: + BUG(); total: 0 errors, 1 warnings, 0 checks, 9 lines checked e5298551c379 drm/i915: use for_each_power_well in lookup_power_well() 942f90859025 drm/i915: move lookup_power_well() up -:40: WARNING:AVOID_BUG: Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON() #40: FILE: drivers/gpu/drm/i915/intel_runtime_pm.c:683: + BUG(); total: 0 errors, 1 warnings, 0 checks, 50 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/4] drm/i915: kill intel_display_power_well_is_enabled()
On Wed, 2018-08-08 at 15:16 -0700, Paulo Zanoni wrote:
> Use the same coding pattern as we use in the other functions of the
> same file: just call lookup_power_well() directly in the only caller.
>
> Cc: Imre Deak
> Signed-off-by: Paulo Zanoni
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 20 +++-
> 1 file changed, 3 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index e209edbc561d..e0947f662361 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -49,9 +49,6 @@
> * present for a given platform.
> */
>
> -bool intel_display_power_well_is_enabled(struct drm_i915_private
> *dev_priv,
> - enum i915_power_well_id
> power_well_id);
> -
> static struct i915_power_well *
> lookup_power_well(struct drm_i915_private *dev_priv,
> enum i915_power_well_id power_well_id);
> @@ -678,8 +675,9 @@ static void assert_csr_loaded(struct
> drm_i915_private *dev_priv)
>
> static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
> {
> - bool pg2_enabled =
> intel_display_power_well_is_enabled(dev_priv,
> - SKL_DISP_PW_2);
> + struct i915_power_well *pg2 = lookup_power_well(dev_priv,
> + SKL_DISP_PW_2);
> + bool pg2_enabled = pg2->desc->ops->is_enabled(dev_priv, pg2);
Why not trust our sync with hardware and use pg2->hw_enabled?
>
> WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n");
>
> @@ -2302,18 +2300,6 @@ static const struct i915_power_well_desc
> chv_power_wells[] = {
> },
> };
>
> -bool intel_display_power_well_is_enabled(struct drm_i915_private
> *dev_priv,
> - enum i915_power_well_id
> power_well_id)
> -{
> - struct i915_power_well *power_well;
> - bool ret;
> -
> - power_well = lookup_power_well(dev_priv, power_well_id);
> - ret = power_well->desc->ops->is_enabled(dev_priv, power_well);
> -
> - return ret;
> -}
> -
> static const struct i915_power_well_desc skl_power_wells[] = {
> {
> .name = "always-on",
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: remove the unnecessary restriction for NV12 in intel_framebuffer_init
framebuffer for NV12 requires the pitch to the multiplier of 4, instead of the
width. This patch corrects it.
For instance, a 480p video, whose width and pitch are 854 and 896 respectively,
is excluded for NV12 plane so far.
Signed-off-by: Dongseong Hwang
Cc: Chandra Konduru
Cc: Vidya Srinivas
Cc: Ville Syrjälä
Cc: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 53e7a7e..87c9a53 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14566,7 +14566,7 @@ static int intel_framebuffer_init(struct
intel_framebuffer *intel_fb,
if (fb->format->format == DRM_FORMAT_NV12 &&
(fb->width < SKL_MIN_YUV_420_SRC_W ||
fb->height < SKL_MIN_YUV_420_SRC_H ||
-(fb->width % 4) != 0 || (fb->height % 4) != 0)) {
+(fb->pitches[0] % 4) != 0 || (fb->height % 4) != 0)) {
DRM_DEBUG_KMS("src dimensions not correct for NV12\n");
return -EINVAL;
}
--
2.7.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/4] drm/i915: BUG() if we can't lookup_power_well()
None of the current lookup_power_well() callers are actually checking for NULL return values, they all just use the pointer right away. Replacing these theoretical segfaults with BUG()s at least makes our code a little more explicit to the reader. We can only hit this NULL/BUG() condition if we try to lookup a power well that isn't defined on a given platform. If that ever happens, we have to fix our code, making it lookup the correct power well. Because of this, I don't think it's worth trying to implement error checking in every caller. Improving our CI system will be a better use of our time once a bug is found in the wild. Cc: Imre Deak Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_runtime_pm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index e0947f662361..2fdb1f4125c2 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -1120,7 +1120,8 @@ lookup_power_well(struct drm_i915_private *dev_priv, return power_well; } - return NULL; + /* Tried to lookup a power well that doesn't exist for the platform. */ + BUG(); } #define BITS_SET(val, bits) (((val) & (bits)) == (bits)) -- 2.14.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/4] drm/i915: move lookup_power_well() up
There's no need for that forward declaration.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 32 ++--
1 file changed, 14 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index eabf98d153f7..d9c7062ffc95 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -49,10 +49,6 @@
* present for a given platform.
*/
-static struct i915_power_well *
-lookup_power_well(struct drm_i915_private *dev_priv,
- enum i915_power_well_id power_well_id);
-
const char *
intel_display_power_domain_str(enum intel_display_power_domain domain)
{
@@ -673,6 +669,20 @@ static void assert_csr_loaded(struct drm_i915_private
*dev_priv)
WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
}
+static struct i915_power_well *
+lookup_power_well(struct drm_i915_private *dev_priv,
+ enum i915_power_well_id power_well_id)
+{
+ struct i915_power_well *power_well;
+
+ for_each_power_well(dev_priv, power_well)
+ if (power_well->desc->id == power_well_id)
+ return power_well;
+
+ /* Tried to lookup a power well that doesn't exist for the platform. */
+ BUG();
+}
+
static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
{
struct i915_power_well *pg2 = lookup_power_well(dev_priv,
@@ -1105,20 +1115,6 @@ static void vlv_dpio_cmn_power_well_disable(struct
drm_i915_private *dev_priv,
#define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0))
-static struct i915_power_well *
-lookup_power_well(struct drm_i915_private *dev_priv,
- enum i915_power_well_id power_well_id)
-{
- struct i915_power_well *power_well;
-
- for_each_power_well(dev_priv, power_well)
- if (power_well->desc->id == power_well_id)
- return power_well;
-
- /* Tried to lookup a power well that doesn't exist for the platform. */
- BUG();
-}
-
#define BITS_SET(val, bits) (((val) & (bits)) == (bits))
static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
--
2.14.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/4] drm/i915: use for_each_power_well in lookup_power_well()
Use the nice helper function to make the implementation simpler.
Cc: Imre Deak
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 2fdb1f4125c2..eabf98d153f7 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -1109,16 +1109,11 @@ static struct i915_power_well *
lookup_power_well(struct drm_i915_private *dev_priv,
enum i915_power_well_id power_well_id)
{
- struct i915_power_domains *power_domains = _priv->power_domains;
- int i;
-
- for (i = 0; i < power_domains->power_well_count; i++) {
- struct i915_power_well *power_well;
+ struct i915_power_well *power_well;
- power_well = _domains->power_wells[i];
+ for_each_power_well(dev_priv, power_well)
if (power_well->desc->id == power_well_id)
return power_well;
- }
/* Tried to lookup a power well that doesn't exist for the platform. */
BUG();
--
2.14.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/4] drm/i915: kill intel_display_power_well_is_enabled()
Use the same coding pattern as we use in the other functions of the
same file: just call lookup_power_well() directly in the only caller.
Cc: Imre Deak
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 20 +++-
1 file changed, 3 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index e209edbc561d..e0947f662361 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -49,9 +49,6 @@
* present for a given platform.
*/
-bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
-enum i915_power_well_id power_well_id);
-
static struct i915_power_well *
lookup_power_well(struct drm_i915_private *dev_priv,
enum i915_power_well_id power_well_id);
@@ -678,8 +675,9 @@ static void assert_csr_loaded(struct drm_i915_private
*dev_priv)
static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
{
- bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
- SKL_DISP_PW_2);
+ struct i915_power_well *pg2 = lookup_power_well(dev_priv,
+ SKL_DISP_PW_2);
+ bool pg2_enabled = pg2->desc->ops->is_enabled(dev_priv, pg2);
WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n");
@@ -2302,18 +2300,6 @@ static const struct i915_power_well_desc
chv_power_wells[] = {
},
};
-bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
-enum i915_power_well_id power_well_id)
-{
- struct i915_power_well *power_well;
- bool ret;
-
- power_well = lookup_power_well(dev_priv, power_well_id);
- ret = power_well->desc->ops->is_enabled(dev_priv, power_well);
-
- return ret;
-}
-
static const struct i915_power_well_desc skl_power_wells[] = {
{
.name = "always-on",
--
2.14.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Restore user forcewake domains across suspend (rev2)
== Series Details ==
Series: drm/i915: Restore user forcewake domains across suspend (rev2)
URL : https://patchwork.freedesktop.org/series/47894/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4635 -> Patchwork_9891 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/47894/revisions/2/mbox/
== Known issues ==
Here are the changes found in Patchwork_9891 that come from known issues:
=== IGT changes ===
Issues hit
{igt@amdgpu/amd_prime@amd-to-i915}:
{fi-kbl-8809g}: NOTRUN -> FAIL (fdo#107341)
Possible fixes
{igt@amdgpu/amd_basic@userptr}:
{fi-kbl-8809g}: INCOMPLETE (fdo#107402) -> PASS
igt@drv_selftest@live_hangcheck:
fi-cnl-psr: DMESG-FAIL (fdo#106560) -> PASS
igt@kms_pipe_crc_basic@read-crc-pipe-b:
{fi-byt-clapper}: FAIL (fdo#107362) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
fdo#107341 https://bugs.freedesktop.org/show_bug.cgi?id=107341
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107402 https://bugs.freedesktop.org/show_bug.cgi?id=107402
== Participating hosts (50 -> 47) ==
Additional (1): fi-hsw-peppy
Missing(4): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4635 -> Patchwork_9891
CI_DRM_4635: a9f34f7e3bab765e2b1320a1b154a76be38602a7 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4589: 779d2d42f9db6a2797d1ef50036af6fac4e62e73 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9891: c326ef4365a9795ed7f4ab0565b51bb139a7d522 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
c326ef4365a9 drm/i915: Restore user forcewake domains across suspend
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9891/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Restore user forcewake domains across suspend
On suspend, we cancel the automatic forcewake and clear all other sources
of forcewake so the machine can sleep before we do suspend. However, we
expose the forcewake to userspace (only via debugfs, but nevertheless we
do) and want to restore that upon resume or else our accounting will be
off and we may not acquire the forcewake before we use it. So record
which domains we cleared on suspend and reacquire them early on resume.
v2: Hold the spinlock to appease our sanitychecks
Reported-by: Imre Deak
Fixes: b8473050805f ("drm/i915: Fix forcewake active domain tracking")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
Cc: Imre Deak
---
drivers/gpu/drm/i915/intel_uncore.c | 44 ++-
drivers/gpu/drm/i915/intel_uncore.h | 1 +
drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 +-
3 files changed, 26 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 284be151f645..cf40361fe181 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -369,8 +369,8 @@ intel_uncore_fw_release_timer(struct hrtimer *timer)
}
/* Note callers must have acquired the PUNIT->PMIC bus, before calling this. */
-static void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
-bool restore)
+static unsigned int
+intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv)
{
unsigned long irqflags;
struct intel_uncore_forcewake_domain *domain;
@@ -422,20 +422,11 @@ static void intel_uncore_forcewake_reset(struct
drm_i915_private *dev_priv,
dev_priv->uncore.funcs.force_wake_put(dev_priv, fw);
fw_domains_reset(dev_priv, dev_priv->uncore.fw_domains);
-
- if (restore) { /* If reset with a user forcewake, try to restore */
- if (fw)
- dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
-
- if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
- dev_priv->uncore.fifo_count =
- fifo_free_entries(dev_priv);
- }
-
- if (!restore)
- assert_forcewakes_inactive(dev_priv);
+ assert_forcewakes_inactive(dev_priv);
spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
+
+ return fw; /* track the lost user forcewake domains */
}
static u64 gen9_edram_size(struct drm_i915_private *dev_priv)
@@ -544,7 +535,7 @@ check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
}
static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
- bool restore_forcewake)
+ unsigned int restore_forcewake)
{
/* clear out unclaimed reg detection bit */
if (check_for_unclaimed_mmio(dev_priv))
@@ -559,7 +550,17 @@ static void __intel_uncore_early_sanitize(struct
drm_i915_private *dev_priv,
}
iosf_mbi_punit_acquire();
- intel_uncore_forcewake_reset(dev_priv, restore_forcewake);
+ intel_uncore_forcewake_reset(dev_priv);
+ if (restore_forcewake) {
+ spin_lock_irq(_priv->uncore.lock);
+ dev_priv->uncore.funcs.force_wake_get(dev_priv,
+ restore_forcewake);
+
+ if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
+ dev_priv->uncore.fifo_count =
+ fifo_free_entries(dev_priv);
+ spin_unlock_irq(_priv->uncore.lock);
+ }
iosf_mbi_punit_release();
}
@@ -568,13 +569,16 @@ void intel_uncore_suspend(struct drm_i915_private
*dev_priv)
iosf_mbi_punit_acquire();
iosf_mbi_unregister_pmic_bus_access_notifier_unlocked(
_priv->uncore.pmic_bus_access_nb);
- intel_uncore_forcewake_reset(dev_priv, false);
+ dev_priv->uncore.fw_domains_user =
+ intel_uncore_forcewake_reset(dev_priv);
iosf_mbi_punit_release();
}
void intel_uncore_resume_early(struct drm_i915_private *dev_priv)
{
- __intel_uncore_early_sanitize(dev_priv, true);
+ __intel_uncore_early_sanitize(dev_priv,
+ dev_priv->uncore.fw_domains_user);
+
iosf_mbi_register_pmic_bus_access_notifier(
_priv->uncore.pmic_bus_access_nb);
i915_check_and_clear_faults(dev_priv);
@@ -1555,7 +1559,7 @@ void intel_uncore_init(struct drm_i915_private *dev_priv)
intel_uncore_edram_detect(dev_priv);
intel_uncore_fw_domains_init(dev_priv);
- __intel_uncore_early_sanitize(dev_priv, false);
+ __intel_uncore_early_sanitize(dev_priv, 0);
dev_priv->uncore.unclaimed_mmio_check = 1;
dev_priv->uncore.pmic_bus_access_nb.notifier_call =
@@ -1642,7 +1646,7 @@ void intel_uncore_fini(struct drm_i915_private *dev_priv)
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Restore user forcewake domains across suspend
== Series Details == Series: drm/i915: Restore user forcewake domains across suspend URL : https://patchwork.freedesktop.org/series/47894/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4633_full -> Patchwork_9887_full = == Summary - FAILURE == Serious unknown changes coming with Patchwork_9887_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9887_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9887_full: === IGT changes === Possible regressions igt@drv_suspend@forcewake: shard-hsw: PASS -> DMESG-WARN shard-snb: PASS -> DMESG-WARN shard-kbl: PASS -> DMESG-WARN shard-apl: PASS -> DMESG-WARN shard-glk: PASS -> DMESG-WARN igt@pm_rpm@gem-pread: shard-kbl: PASS -> WARN shard-glk: PASS -> WARN == Known issues == Here are the changes found in Patchwork_9887_full that come from known issues: === IGT changes === Issues hit igt@drv_suspend@shrink: shard-glk: PASS -> FAIL (fdo#106886) igt@kms_draw_crc@draw-method-rgb565-mmap-wc-xtiled: shard-glk: PASS -> FAIL (fdo#103184) igt@kms_flip@2x-modeset-vs-vblank-race-interruptible: shard-glk: PASS -> FAIL (fdo#103060) Possible fixes igt@kms_setmode@basic: shard-apl: FAIL (fdo#99912) -> PASS shard-kbl: FAIL (fdo#99912) -> PASS fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060 fdo#103184 https://bugs.freedesktop.org/show_bug.cgi?id=103184 fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4633 -> Patchwork_9887 CI_DRM_4633: ea6e3f703e4d234c9c8eaec6c533355c7454ecb6 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4588: 7e5abbe4d9b2129bbbf02be77a70cad3da2ab941 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9887: 8f7ed83e1713847e6296b8fbd7f7a6e9f4474b9d @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9887/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915: Allow control of PSR at runtime through debugfs, v5
== Series Details == Series: series starting with [1/2] drm/i915: Allow control of PSR at runtime through debugfs, v5 URL : https://patchwork.freedesktop.org/series/47888/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4633_full -> Patchwork_9886_full = == Summary - FAILURE == Serious unknown changes coming with Patchwork_9886_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9886_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9886_full: === IGT changes === Possible regressions igt@pm_rpm@gem-pread: shard-kbl: PASS -> WARN == Known issues == Here are the changes found in Patchwork_9886_full that come from known issues: === IGT changes === Issues hit igt@drv_suspend@shrink: shard-snb: PASS -> INCOMPLETE (fdo#106886, fdo#105411) igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend: shard-snb: PASS -> INCOMPLETE (fdo#105411) igt@kms_vblank@pipe-c-wait-forked-busy-hang: shard-kbl: PASS -> DMESG-WARN (fdo#105602, fdo#103558) fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602 fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4633 -> Patchwork_9886 CI_DRM_4633: ea6e3f703e4d234c9c8eaec6c533355c7454ecb6 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4588: 7e5abbe4d9b2129bbbf02be77a70cad3da2ab941 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9886: a61846961762ac2ce6ac6b2c23411dd45b08b5cb @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9886/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/psr: Add PSR mode/revision to debugfs
== Series Details ==
Series: drm/i915/psr: Add PSR mode/revision to debugfs
URL : https://patchwork.freedesktop.org/series/47902/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4635 -> Patchwork_9890 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_9890 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_9890, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/47902/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_9890:
=== IGT changes ===
Possible regressions
igt@drv_selftest@live_hangcheck:
fi-cfl-guc: PASS -> DMESG-FAIL
== Known issues ==
Here are the changes found in Patchwork_9890 that come from known issues:
=== IGT changes ===
Issues hit
{igt@amdgpu/amd_prime@amd-to-i915}:
{fi-kbl-8809g}: NOTRUN -> FAIL (fdo#107341)
igt@drv_module_reload@basic-reload-inject:
fi-hsw-4770r: PASS -> DMESG-WARN (fdo#107425)
igt@drv_selftest@live_coherency:
fi-gdg-551: PASS -> DMESG-FAIL (fdo#107164)
igt@drv_selftest@live_workarounds:
{fi-bsw-kefka}: PASS -> DMESG-FAIL (fdo#107292)
fi-skl-6700hq: PASS -> DMESG-FAIL (fdo#107292)
fi-cnl-psr: PASS -> DMESG-FAIL (fdo#107292)
igt@kms_frontbuffer_tracking@basic:
{fi-byt-clapper}: PASS -> FAIL (fdo#103167)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
{fi-byt-clapper}: PASS -> FAIL (fdo#107362, fdo#103191)
Possible fixes
{igt@amdgpu/amd_basic@userptr}:
{fi-kbl-8809g}: INCOMPLETE (fdo#107402) -> PASS
igt@drv_selftest@live_hangcheck:
fi-cnl-psr: DMESG-FAIL (fdo#106560) -> PASS
fi-skl-guc: DMESG-FAIL (fdo#107174) -> PASS
igt@kms_pipe_crc_basic@read-crc-pipe-b:
{fi-byt-clapper}: FAIL (fdo#107362) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
fdo#107164 https://bugs.freedesktop.org/show_bug.cgi?id=107164
fdo#107174 https://bugs.freedesktop.org/show_bug.cgi?id=107174
fdo#107292 https://bugs.freedesktop.org/show_bug.cgi?id=107292
fdo#107341 https://bugs.freedesktop.org/show_bug.cgi?id=107341
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107402 https://bugs.freedesktop.org/show_bug.cgi?id=107402
fdo#107425 https://bugs.freedesktop.org/show_bug.cgi?id=107425
== Participating hosts (50 -> 47) ==
Additional (1): fi-hsw-peppy
Missing(4): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4635 -> Patchwork_9890
CI_DRM_4635: a9f34f7e3bab765e2b1320a1b154a76be38602a7 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4589: 779d2d42f9db6a2797d1ef50036af6fac4e62e73 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9890: 35d0453e2699c5e5627fee800bd3c641d928a906 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
35d0453e2699 drm/i915/psr: Add PSR mode/revision to debugfs
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9890/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915: Priority boost for new clients
Quoting Chris Wilson (2018-08-08 19:53:33)
> Quoting Tvrtko Ursulin (2018-08-08 13:40:41)
> >
> > On 07/08/2018 16:02, Chris Wilson wrote:
> > > Quoting Tvrtko Ursulin (2018-08-07 10:08:28)
> > >>
> > >> On 07/08/2018 08:29, Chris Wilson wrote:
> > >>> + /*
> > >>> + * The active request is now effectively the start of a new client
> > >>> + * stream, so give it the equivalent small priority bump to
> > >>> prevent
> > >>> + * it being gazumped a second time by another peer.
> > >>> + */
> > >>> + if (!(prio & I915_PRIORITY_NEWCLIENT)) {
> > >>> + list_move_tail(>sched.link,
> > >>> +lookup_priolist(engine,
> > >>> +prio |
> > >>> I915_PRIORITY_NEWCLIENT));
> > >>>}
> > >>>}
> > >>>
> > >>>
> > >>
> > >> This sounds fair, I think I'm okay with it. Does it still work well for
> > >> mixed media workloads?
> > >
> > > Grr. Current drm-tip is scoring much much higher in fairness than I
> > > remember, and there's no apparent improvement, even little room for
> > > possible improvement. When in doubt, blame ksoftirqd ;)
> >
> > Perhaps previous testing was before direct submission?
>
> I went back and checked that, unfortunately not that simple. The
> influencing factor appears to be the choice of workload. I am seeing
> some now that respond favourably (by pure chance selection) but I need
> to spend more time to ensure the results are stable, and see if there's
> any method to the madness in selection.
Early figures, suffering a bit from lack of transparency in the results.
(Using a pinned kbl gt4e)
TLDR;
w/o boosts:busy balancer ('-b busy -R'): Aggregate (normalized) 89.28%;
fairness 79.64%
w/ boosts:busy balancer ('-b busy -R'): Aggregate (normalized) 108.92%;
fairness 64.72%
Fairness went down (grumble) but that's a large increase in the
multiw-sim throughput.
Before:
ickle@kabylake:~/intel-gpu-tools$ sudo ./scripts/media-bench.pl -n 306765 -B
busy -m -W
media_nn_1080p_s1.wsim,media_nn_1080p_s2.wsim,media_nn_1080p_s3.wsim,media_nn_1080p.wsim,media_nn_480p.wsim
Workloads:
media_nn_1080p_s1.wsim
media_nn_1080p_s2.wsim
media_nn_1080p_s3.wsim
media_nn_1080p.wsim
media_nn_480p.wsim
Balancers: busy,
Target workload duration is 10s.
Calibration tolerance is 0.01.
Multi-workload mode.
Nop calibration is 306765.
Evaluating 'media_nn_1080p_s1.wsim'... 10s is 177 workloads.
(error=0.000311)
Finding saturation points for 'media_nn_1080p_s1.wsim'...
busy balancer ('-b busy -R'): 4 clients (31.844 wps, 17.671 wps single
client, score=49.515).
busy balancer ('-b busy -R -G'): 4 clients (31.957 wps, 17.667 wps single
client, score=49.624).
busy balancer ('-b busy -R -d'): 3 clients (31.904 wps, 17.677 wps single
client, score=49.581).
busy balancer ('-b busy -R -G -d'): 3 clients (32.046 wps, 17.624 wps
single client, score=49.67).
Evaluating 'media_nn_1080p_s2.wsim'... 10s is 183 workloads.
(error=0.00609)
Finding saturation points for 'media_nn_1080p_s2.wsim'...
busy balancer ('-b busy -R'): 3 clients (31.984 wps, 18.147 wps single
client, score=50.131).
busy balancer ('-b busy -R -G'): 3 clients (31.929 wps, 18.058 wps single
client, score=49.987).
busy balancer ('-b busy -R -d'): 2 clients (32.061 wps, 18.160 wps single
client, score=50.221).
busy balancer ('-b busy -R -G -d'): 3 clients (31.909 wps, 18.059 wps
single client, score=49.968).
Evaluating 'media_nn_1080p_s3.wsim'... 10s is 182 workloads.
(error=0.00712)
Finding saturation points for 'media_nn_1080p_s3.wsim'...
busy balancer ('-b busy -R'): 3 clients (31.957 wps, 18.044 wps single
client, score=50.001).
busy balancer ('-b busy -R -G'): 3 clients (31.930 wps, 18.134 wps single
client, score=50.064).
busy balancer ('-b busy -R -d'): 2 clients (32.047 wps, 18.054 wps single
client, score=50.101).
busy balancer ('-b busy -R -G -d'): 2 clients (31.972 wps, 18.040 wps
single client, score=50.012).
Evaluating 'media_nn_1080p.wsim'... 10s is 156 workloads.
(error=0.00476)
Finding saturation points for 'media_nn_1080p.wsim'...
busy balancer ('-b busy -R'): 4 clients (31.957 wps, 15.667 wps single
client, score=47.624).
busy balancer ('-b busy -R -G'): 4 clients (32.066 wps, 15.684 wps single
client, score=47.75).
busy balancer ('-b busy -R -d'): 5 clients (32.022 wps, 15.886 wps single
client, score=47.908).
busy balancer ('-b busy -R -G -d'): 4 clients (31.939 wps, 15.657 wps
single client, score=47.596).
Evaluating 'media_nn_480p.wsim'... 10s is 337 workloads.
(error=0.00827)
Finding saturation points for 'media_nn_480p.wsim'...
busy balancer ('-b busy -R'): 5 clients (74.077 wps, 33.412 wps single
client, score=107.489).
busy balancer ('-b busy -R -G'): 4 clients (73.849 wps, 33.415 wps single
client, score=107.264).
busy balancer
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/psr: Add PSR mode/revision to debugfs
== Series Details == Series: drm/i915/psr: Add PSR mode/revision to debugfs URL : https://patchwork.freedesktop.org/series/47902/ State : warning == Summary == $ dim checkpatch origin/drm-tip 35d0453e2699 drm/i915/psr: Add PSR mode/revision to debugfs -:21: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #21: FILE: drivers/gpu/drm/i915/i915_debugfs.c:2712: + seq_printf(m, "PSR mode: %s\n", + dev_priv->psr.psr2_enabled ? "PSR2" : "PSR1"); total: 0 errors, 0 warnings, 1 checks, 8 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/psr: Add PSR mode/revision to debugfs
Log the PSR mode/revision (PSR1 or PSR2) in the debugfs file i915_edp_psr_status. Suggested-by: Dhinakaran Pandiyan Signed-off-by: Azhar Shaikh --- drivers/gpu/drm/i915/i915_debugfs.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index f9ce35da4123..d6e3830fc513 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2708,6 +2708,8 @@ static int i915_edp_psr_status(struct seq_file *m, void *data) intel_runtime_pm_get(dev_priv); mutex_lock(_priv->psr.lock); + seq_printf(m, "PSR mode: %s\n", + dev_priv->psr.psr2_enabled ? "PSR2" : "PSR1"); seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled)); seq_printf(m, "Busy frontbuffer bits: 0x%03x\n", dev_priv->psr.busy_frontbuffer_bits); -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915: Priority boost for new clients
Quoting Tvrtko Ursulin (2018-08-08 13:40:41)
>
> On 07/08/2018 16:02, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-08-07 10:08:28)
> >>
> >> On 07/08/2018 08:29, Chris Wilson wrote:
> >>> + /*
> >>> + * The active request is now effectively the start of a new client
> >>> + * stream, so give it the equivalent small priority bump to prevent
> >>> + * it being gazumped a second time by another peer.
> >>> + */
> >>> + if (!(prio & I915_PRIORITY_NEWCLIENT)) {
> >>> + list_move_tail(>sched.link,
> >>> +lookup_priolist(engine,
> >>> +prio |
> >>> I915_PRIORITY_NEWCLIENT));
> >>>}
> >>>}
> >>>
> >>>
> >>
> >> This sounds fair, I think I'm okay with it. Does it still work well for
> >> mixed media workloads?
> >
> > Grr. Current drm-tip is scoring much much higher in fairness than I
> > remember, and there's no apparent improvement, even little room for
> > possible improvement. When in doubt, blame ksoftirqd ;)
>
> Perhaps previous testing was before direct submission?
I went back and checked that, unfortunately not that simple. The
influencing factor appears to be the choice of workload. I am seeing
some now that respond favourably (by pure chance selection) but I need
to spend more time to ensure the results are stable, and see if there's
any method to the madness in selection.
> > Quite surprising though, it was (at least if memory serves) a dramatic
> > improvement from this patch. Time to see if the metrics do resemble what
> > I think they should be, and to see if I can find a good example in
> > media-bench.pl
>
> I should maybe rename it to wsim-bench.pl with a switch to select
> workload groups per directory or something..
What I'm thinking is closer to the expression I want is
diff --git a/scripts/media-bench.pl b/scripts/media-bench.pl
index ddf9c0ec..f39b1bb1 100755
--- a/scripts/media-bench.pl
+++ b/scripts/media-bench.pl
@@ -339,7 +339,6 @@ sub find_saturation_point
} elsif ($c == 1) {
$swps = $wps;
return ($c, $wps, $swps, $wwps) if $wcnt > 1 or
- $multi_mode or
($wps_target_param <
0 and
$wps_target == 0);
}
We want to find the saturated peak of each wsim. We could use sim_wsim
for this.
@@ -553,7 +552,7 @@ foreach my $wrk (@saturation_workloads) {
# Normalize mixed sum with sum of
# individual runs.
- $w *= 100;
+ $w *= 100 * scalar(@multi_workloads);
$w /= $tot;
Knowing the saturation point of each wsim, we should be able to saturate
the engine running all simultaneous, each taking 1/N of the bw.
(Spherical cows and all that). Applying the factor of N here sets the
normalized target to 100%.
# Second metric is average of each
@@ -563,10 +562,11 @@ foreach my $wrk (@saturation_workloads) {
$s = 0;
$widx = 0;
foreach my $wrk (@multi_workloads) {
- $s += 100 * $bwwps->[$widx] /
-
$allwps{$wrk}->{$best_bid{$wrk}};
+ my $target =
$allwps{$wrk}->{$best_bid{$wrk}} / scalar(@multi_workloads);
+ $s += 1. - abs($target -
$bwwps->[$widx]) / $target;
$widx++;
}
+ $s *= 100;
$s /= scalar(@multi_workloads);
This is the challenge. My idea of fairness is that each wsim got 1/N of
the bw, so should see wps of its saturated max / N. Fairness is then how
close we get to our theoretical fair slice.
Problem is the spherical cows are multiplying. It's box packing (linear
optimisation) problem, probably best to quantify the ideal fair slice
using sim_wsim and then report how unfair reality was.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] RFC: drm: Restrict vblank ioctl to master
Hi Daniel,
We are in beta for v18. I expect release in September.
I don't think we have to consider users who run older Kodi versions on
systems with latest kernels. The feature the patch would disable won't
make Kodi completely unusable when absent. I'd say you can merge
the patch short after v18 has been released.
Cheers,
Rainer
On Wed, Aug 8, 2018 at 6:59 PM, Daniel Vetter wrote:
> Hi Rainer,
>
> Awesome, thanks a lot for doing this! Any idea for when this will ship
> in a release, and for how long your users are generally using older
> releases? Just to have a rough indication for when we could attempt to
> merge this patch here.
>
> Cheers, Daniel
>
> On Wed, Aug 8, 2018 at 5:35 PM, Rainer Hochecker wrote:
>> Finally we removed this code from Kodi.
>>
>> Regards,
>> Rainer
>>
>> On Tue, Jun 14, 2016 at 11:02 AM, Daniel Vetter
>> wrote:
>>> Somehow this escaped us, this is a KMS ioctl which should only be used
>>> by the master (which is the thing that's also in control of kms
>>> resources). Everything else is bound to result in fail.
>>>
>>> Clients shouldn't have a trouble coping with this, since a pile of
>>> drivers don't support vblank waits (or just randomly fall over when
>>> using them). Note that the big motivation for abusing this like mad
>>> seems to be that EGL doesn't have OML_sync, but somehow it didn't
>>> cross anyone's mind that adding OML_sync to EGL would be useful. This
>>> patch is meant to essentially start kicking that can from the back
>>> end.
>>>
>>> Cc: frit...@kodi.tv
>>> Cc: fernetme...@kodi.tv
>>> Signed-off-by: Daniel Vetter
>>> ---
>>> drivers/gpu/drm/drm_ioctl.c | 4 ++--
>>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
>>> index 0510675eec5d..6cc78d648393 100644
>>> --- a/drivers/gpu/drm/drm_ioctl.c
>>> +++ b/drivers/gpu/drm/drm_ioctl.c
>>> @@ -529,9 +529,9 @@ static const struct drm_ioctl_desc drm_ioctls[] = {
>>> DRM_IOCTL_DEF(DRM_IOCTL_SG_ALLOC, drm_legacy_sg_alloc,
>>> DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
>>> DRM_IOCTL_DEF(DRM_IOCTL_SG_FREE, drm_legacy_sg_free,
>>> DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
>>>
>>> - DRM_IOCTL_DEF(DRM_IOCTL_WAIT_VBLANK, drm_wait_vblank, DRM_UNLOCKED),
>>> + DRM_IOCTL_DEF(DRM_IOCTL_WAIT_VBLANK, drm_wait_vblank,
>>> DRM_MASTER|DRM_UNLOCKED),
>>>
>>> - DRM_IOCTL_DEF(DRM_IOCTL_MODESET_CTL, drm_modeset_ctl, 0),
>>> + DRM_IOCTL_DEF(DRM_IOCTL_MODESET_CTL, drm_modeset_ctl, DRM_MASTER),
>>>
>>> DRM_IOCTL_DEF(DRM_IOCTL_UPDATE_DRAW, drm_noop,
>>> DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
>>>
>>> --
>>> 2.8.1
>>>
>
>
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] RFC: drm: Restrict vblank ioctl to master
Hi Rainer,
Awesome, thanks a lot for doing this! Any idea for when this will ship
in a release, and for how long your users are generally using older
releases? Just to have a rough indication for when we could attempt to
merge this patch here.
Cheers, Daniel
On Wed, Aug 8, 2018 at 5:35 PM, Rainer Hochecker wrote:
> Finally we removed this code from Kodi.
>
> Regards,
> Rainer
>
> On Tue, Jun 14, 2016 at 11:02 AM, Daniel Vetter
> wrote:
>> Somehow this escaped us, this is a KMS ioctl which should only be used
>> by the master (which is the thing that's also in control of kms
>> resources). Everything else is bound to result in fail.
>>
>> Clients shouldn't have a trouble coping with this, since a pile of
>> drivers don't support vblank waits (or just randomly fall over when
>> using them). Note that the big motivation for abusing this like mad
>> seems to be that EGL doesn't have OML_sync, but somehow it didn't
>> cross anyone's mind that adding OML_sync to EGL would be useful. This
>> patch is meant to essentially start kicking that can from the back
>> end.
>>
>> Cc: frit...@kodi.tv
>> Cc: fernetme...@kodi.tv
>> Signed-off-by: Daniel Vetter
>> ---
>> drivers/gpu/drm/drm_ioctl.c | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
>> index 0510675eec5d..6cc78d648393 100644
>> --- a/drivers/gpu/drm/drm_ioctl.c
>> +++ b/drivers/gpu/drm/drm_ioctl.c
>> @@ -529,9 +529,9 @@ static const struct drm_ioctl_desc drm_ioctls[] = {
>> DRM_IOCTL_DEF(DRM_IOCTL_SG_ALLOC, drm_legacy_sg_alloc,
>> DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
>> DRM_IOCTL_DEF(DRM_IOCTL_SG_FREE, drm_legacy_sg_free,
>> DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
>>
>> - DRM_IOCTL_DEF(DRM_IOCTL_WAIT_VBLANK, drm_wait_vblank, DRM_UNLOCKED),
>> + DRM_IOCTL_DEF(DRM_IOCTL_WAIT_VBLANK, drm_wait_vblank,
>> DRM_MASTER|DRM_UNLOCKED),
>>
>> - DRM_IOCTL_DEF(DRM_IOCTL_MODESET_CTL, drm_modeset_ctl, 0),
>> + DRM_IOCTL_DEF(DRM_IOCTL_MODESET_CTL, drm_modeset_ctl, DRM_MASTER),
>>
>> DRM_IOCTL_DEF(DRM_IOCTL_UPDATE_DRAW, drm_noop,
>> DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
>>
>> --
>> 2.8.1
>>
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for igt/drv_missed_irq: Skip if the kernel reports no rings available to test
== Series Details == Series: igt/drv_missed_irq: Skip if the kernel reports no rings available to test URL : https://patchwork.freedesktop.org/series/47873/ State : success == Summary == = CI Bug Log - changes from IGT_4588_full -> IGTPW_1690_full = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/47873/revisions/1/mbox/ == Known issues == Here are the changes found in IGTPW_1690_full that come from known issues: === IGT changes === Issues hit igt@gem_workarounds@suspend-resume-fd: shard-kbl: PASS -> INCOMPLETE (fdo#103665) igt@kms_flip@2x-flip-vs-expired-vblank: shard-glk: PASS -> FAIL (fdo#105363) +1 igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: shard-snb: PASS -> INCOMPLETE (fdo#105411) igt@kms_setmode@basic: shard-kbl: PASS -> FAIL (fdo#99912) igt@kms_vblank@pipe-c-wait-busy: shard-kbl: PASS -> DMESG-WARN (fdo#105602, fdo#103558) +7 Possible fixes igt@drv_suspend@shrink: shard-snb: INCOMPLETE (fdo#106886, fdo#105411) -> PASS igt@gem_softpin@evict-snoop-interruptible: shard-snb: INCOMPLETE (fdo#105411) -> SKIP igt@kms_plane_multiple@atomic-pipe-a-tiling-x: shard-snb: FAIL (fdo#103166) -> PASS igt@kms_vblank@pipe-a-ts-continuation-modeset-rpm: shard-apl: FAIL (fdo#106539) -> PASS +1 igt@pm_rpm@gem-pread: shard-glk: WARN -> PASS igt@pm_rpm@modeset-non-lpsp-stress: shard-kbl: FAIL (fdo#106539) -> PASS +1 shard-hsw: FAIL (fdo#106539) -> PASS +1 shard-glk: FAIL (fdo#106539) -> PASS +1 fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166 fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602 fdo#106539 https://bugs.freedesktop.org/show_bug.cgi?id=106539 fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * IGT: IGT_4588 -> IGTPW_1690 * Linux: CI_DRM_4632 -> CI_DRM_4633 CI_DRM_4632: 648e2ff1094eabf43613f41d4d719c1a1f555dbb @ git://anongit.freedesktop.org/gfx-ci/linux CI_DRM_4633: ea6e3f703e4d234c9c8eaec6c533355c7454ecb6 @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_1690: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1690/ IGT_4588: 7e5abbe4d9b2129bbbf02be77a70cad3da2ab941 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1690/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915: Warn if we hit the timeout for wait-for-idle
== Series Details == Series: series starting with [1/3] drm/i915: Warn if we hit the timeout for wait-for-idle URL : https://patchwork.freedesktop.org/series/47876/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4633_full -> Patchwork_9884_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_9884_full that come from known issues: === IGT changes === Possible fixes igt@gem_eio@reset-stress: shard-hsw: FAIL (fdo#107500) -> PASS fdo#107500 https://bugs.freedesktop.org/show_bug.cgi?id=107500 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4633 -> Patchwork_9884 CI_DRM_4633: ea6e3f703e4d234c9c8eaec6c533355c7454ecb6 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4588: 7e5abbe4d9b2129bbbf02be77a70cad3da2ab941 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9884: 1497da1833471d54390845b7f7e3414652d6fbb2 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9884/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for Improve crc-core driver interface (rev10)
== Series Details ==
Series: Improve crc-core driver interface (rev10)
URL : https://patchwork.freedesktop.org/series/45246/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4633 -> Patchwork_9889 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_9889 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_9889, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/45246/revisions/10/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_9889:
=== IGT changes ===
Possible regressions
igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
fi-ivb-3520m: PASS -> FAIL +5
fi-skl-6700hq: PASS -> FAIL +5
fi-skl-guc: PASS -> FAIL +5
fi-blb-e6850: PASS -> FAIL +3
fi-byt-j1900: PASS -> FAIL +3
igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
fi-ilk-650: PASS -> FAIL +3
fi-elk-e7500: PASS -> FAIL +3
fi-byt-n2820: PASS -> FAIL +3
fi-snb-2520m: PASS -> FAIL +3
igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b:
fi-bdw-5557u: PASS -> FAIL +5
fi-pnv-d510:PASS -> FAIL +3
fi-skl-6600u: PASS -> FAIL +5
{fi-byt-clapper}: PASS -> FAIL +3
fi-bxt-dsi: NOTRUN -> FAIL +5
fi-hsw-4770:PASS -> FAIL +5
fi-ivb-3770:PASS -> FAIL +5
fi-bwr-2160:PASS -> FAIL +3
igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence:
{fi-bdw-samus}: PASS -> FAIL +5
fi-hsw-peppy: PASS -> FAIL +5
fi-bdw-gvtdvm: PASS -> FAIL +5
fi-gdg-551: PASS -> FAIL +3
fi-kbl-7500u: PASS -> FAIL +5
fi-snb-2600:PASS -> FAIL +3
fi-hsw-4770r: PASS -> FAIL +5
igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c:
fi-kbl-7567u: PASS -> FAIL +5
fi-skl-6260u: PASS -> FAIL +5
fi-skl-6700k2: PASS -> FAIL +5
fi-skl-gvtdvm: PASS -> FAIL +5
{fi-skl-iommu}: PASS -> FAIL +5
fi-skl-6770hq: PASS -> FAIL +5
fi-bxt-j4205: PASS -> FAIL +5
fi-kbl-7560u: PASS -> FAIL +5
fi-whl-u: PASS -> FAIL +5
fi-kbl-r: PASS -> FAIL +5
Warnings
igt@kms_pipe_crc_basic@bad-source:
{fi-kbl-8809g}: SKIP -> PASS
fi-kbl-x1275: SKIP -> PASS
fi-kbl-guc: SKIP -> PASS
fi-bsw-n3050: SKIP -> PASS
== Known issues ==
Here are the changes found in Patchwork_9889 that come from known issues:
=== IGT changes ===
Issues hit
igt@drv_selftest@live_coherency:
fi-gdg-551: PASS -> DMESG-FAIL (fdo#107164)
igt@drv_selftest@live_workarounds:
fi-cnl-psr: PASS -> DMESG-FAIL (fdo#107292)
igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
fi-cfl-s3: PASS -> FAIL (fdo#103481) +5
igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b:
{fi-bsw-kefka}: PASS -> FAIL (fdo#106211) +3
{fi-cfl-8109u}: PASS -> FAIL (fdo#103481) +5
fi-cfl-guc: PASS -> FAIL (fdo#103481) +5
igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence:
fi-cnl-psr: PASS -> FAIL (fdo#106211) +5
igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c:
fi-glk-j4005: PASS -> FAIL (fdo#106211) +5
fi-cfl-8700k: PASS -> FAIL (fdo#103481) +5
fi-bsw-n3050: PASS -> FAIL (fdo#106211) +1
igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c-frame-sequence:
fi-glk-dsi: PASS -> FAIL (fdo#106211) +5
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
fi-snb-2520m: PASS -> INCOMPLETE (fdo#103713)
Possible fixes
igt@drv_selftest@live_hangcheck:
fi-skl-guc: DMESG-FAIL (fdo#107174) -> PASS
igt@drv_selftest@live_workarounds:
fi-whl-u: DMESG-FAIL (fdo#107292) -> PASS
fi-kbl-x1275: DMESG-FAIL (fdo#107292) -> PASS
igt@kms_frontbuffer_tracking@basic:
{fi-byt-clapper}: FAIL (fdo#103167) -> PASS
Warnings
{igt@kms_psr@primary_page_flip}:
fi-cnl-psr: DMESG-FAIL (fdo#107372) -> DMESG-WARN (fdo#107372)
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#106211 https://bugs.freedesktop.org/show_bug.cgi?id=106211
fdo#107164
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Improve crc-core driver interface (rev10)
== Series Details == Series: Improve crc-core driver interface (rev10) URL : https://patchwork.freedesktop.org/series/45246/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm: crc: Introduce verify_crc_source callback Okay! Commit: drm: crc: Introduce get_crc_sources callback Okay! Commit: drm/rockchip/crc: Implement verify_crc_source callback Okay! Commit: drm/amdgpu_dm/crc: Implement verify_crc_source callback -drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:3028:6: warning: symbol 'dm_drm_plane_destroy_state' was not declared. Should it be static? -drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:3819:27: warning: expression using sizeof(void) -drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:3819:27: warning: expression using sizeof(void) -drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:3823:27: warning: expression using sizeof(void) -drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:3823:27: warning: expression using sizeof(void) -drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:3930:58: warning: Using plain integer as NULL pointer +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:3029:6: warning: symbol 'dm_drm_plane_destroy_state' was not declared. Should it be static? +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:3820:27: warning: expression using sizeof(void) +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:3820:27: warning: expression using sizeof(void) +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:3824:27: warning: expression using sizeof(void) +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:3824:27: warning: expression using sizeof(void) +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:3931:58: warning: Using plain integer as NULL pointer Commit: drm/rcar-du/crc: Implement verify_crc_source callback Okay! Commit: drm/i915/crc: implement verify_crc_source callback Okay! Commit: drm/i915/crc: implement get_crc_sources callback Okay! Commit: drm/crc: Cleanup crtc_crc_open function Okay! Commit: Revert "drm: crc: Wait for a frame before returning from open()" Okay! Commit: drm/rcar-du/crc: Implement get_crc_sources callback Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] RFC: drm: Restrict vblank ioctl to master
Finally we removed this code from Kodi.
Regards,
Rainer
On Tue, Jun 14, 2016 at 11:02 AM, Daniel Vetter wrote:
> Somehow this escaped us, this is a KMS ioctl which should only be used
> by the master (which is the thing that's also in control of kms
> resources). Everything else is bound to result in fail.
>
> Clients shouldn't have a trouble coping with this, since a pile of
> drivers don't support vblank waits (or just randomly fall over when
> using them). Note that the big motivation for abusing this like mad
> seems to be that EGL doesn't have OML_sync, but somehow it didn't
> cross anyone's mind that adding OML_sync to EGL would be useful. This
> patch is meant to essentially start kicking that can from the back
> end.
>
> Cc: frit...@kodi.tv
> Cc: fernetme...@kodi.tv
> Signed-off-by: Daniel Vetter
> ---
> drivers/gpu/drm/drm_ioctl.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
> index 0510675eec5d..6cc78d648393 100644
> --- a/drivers/gpu/drm/drm_ioctl.c
> +++ b/drivers/gpu/drm/drm_ioctl.c
> @@ -529,9 +529,9 @@ static const struct drm_ioctl_desc drm_ioctls[] = {
> DRM_IOCTL_DEF(DRM_IOCTL_SG_ALLOC, drm_legacy_sg_alloc,
> DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
> DRM_IOCTL_DEF(DRM_IOCTL_SG_FREE, drm_legacy_sg_free,
> DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
>
> - DRM_IOCTL_DEF(DRM_IOCTL_WAIT_VBLANK, drm_wait_vblank, DRM_UNLOCKED),
> + DRM_IOCTL_DEF(DRM_IOCTL_WAIT_VBLANK, drm_wait_vblank,
> DRM_MASTER|DRM_UNLOCKED),
>
> - DRM_IOCTL_DEF(DRM_IOCTL_MODESET_CTL, drm_modeset_ctl, 0),
> + DRM_IOCTL_DEF(DRM_IOCTL_MODESET_CTL, drm_modeset_ctl, DRM_MASTER),
>
> DRM_IOCTL_DEF(DRM_IOCTL_UPDATE_DRAW, drm_noop,
> DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
>
> --
> 2.8.1
>
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915/tracing: Enable user interrupts while intel_engine_notify is active
Quoting Tvrtko Ursulin (2018-08-08 16:14:24)
> From: Tvrtko Ursulin
>
> Keep the user interrupt enabled and emit intel_engine_notify tracepoint
> every time as long as it is enabled.
>
> Premise is that if someone is listening, they want to see interrupts
> logged.
>
> We use tracepoint (de)registration callbacks to enable user interrupts on
> all devices (future proofing and avoiding ugly global pointers) and all
> engines.
>
> For this to work we also have to add another call site of
> trace_intel_engine_notify, notably to the early return from notify_ring
> otherwise we still depend on waiters being present.
That confused me. "We use... For this to work" I took as meaning we
needed the tracepoint in the irq to enable the user interrupts. But what
you meant was that we always want to fire the irq tracepoint when it is
being traced, irrespective of clients waiting.
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 0b10a30b7d96..a15f8be0ece0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2141,6 +2141,8 @@ struct drm_i915_private {
>
> struct i915_pmu pmu;
>
> + struct list_head driver_list_link;
Nit: mostly we keep to _list being the list_head, and _link being the
node. Also link tends to indicate which list it is in, e.g
obj->vma_list and vma->obj_link -- but you'll be forgiven if that's
confusing and you have a better idea.
So i915_tracing_driver_list and tracing_link ?
> +
> /*
> * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your
> patch
> * will be rejected. Instead look for a better place.
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 8084e35b25c5..8cba798b666d 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1159,8 +1159,10 @@ static void notify_ring(struct intel_engine_cs *engine)
> struct task_struct *tsk = NULL;
> struct intel_wait *wait;
>
> - if (unlikely(!engine->breadcrumbs.irq_armed))
> + if (unlikely(!engine->breadcrumbs.irq_armed)) {
> + trace_intel_engine_notify(engine, false);
> return;
> + }
>
> rcu_read_lock();
>
> diff --git a/drivers/gpu/drm/i915/i915_trace.h
> b/drivers/gpu/drm/i915/i915_trace.h
> index c0352a1b036c..12555d2388fd 100644
> --- a/drivers/gpu/drm/i915/i915_trace.h
> +++ b/drivers/gpu/drm/i915/i915_trace.h
> @@ -8,6 +8,7 @@
>
> #include
> #include "i915_drv.h"
> +#include "i915_tracing.h"
> #include "intel_drv.h"
> #include "intel_ringbuffer.h"
>
> @@ -750,29 +751,32 @@ TRACE_EVENT(i915_request_out,
> __entry->global_seqno, __entry->completed)
> );
>
> -TRACE_EVENT(intel_engine_notify,
> - TP_PROTO(struct intel_engine_cs *engine, bool waiters),
> - TP_ARGS(engine, waiters),
> -
> - TP_STRUCT__entry(
> -__field(u32, dev)
> -__field(u16, class)
> -__field(u16, instance)
> -__field(u32, seqno)
> -__field(bool, waiters)
> -),
> -
> - TP_fast_assign(
> - __entry->dev = engine->i915->drm.primary->index;
> - __entry->class = engine->uabi_class;
> - __entry->instance = engine->instance;
> - __entry->seqno = intel_engine_get_seqno(engine);
> - __entry->waiters = waiters;
> - ),
> -
> - TP_printk("dev=%u, engine=%u:%u, seqno=%u, waiters=%u",
> - __entry->dev, __entry->class, __entry->instance,
> - __entry->seqno, __entry->waiters)
> +TRACE_EVENT_FN(intel_engine_notify,
> + TP_PROTO(struct intel_engine_cs *engine, bool waiters),
> + TP_ARGS(engine, waiters),
> +
> + TP_STRUCT__entry(
> + __field(u32, dev)
> + __field(u16, class)
> + __field(u16, instance)
> + __field(u32, seqno)
> + __field(bool, waiters)
> + ),
> +
> + TP_fast_assign(
> + __entry->dev = engine->i915->drm.primary->index;
> + __entry->class = engine->uabi_class;
> + __entry->instance = engine->instance;
> + __entry->seqno = intel_engine_get_seqno(engine);
> + __entry->waiters = waiters;
> + ),
> +
> + TP_printk("dev=%u, engine=%u:%u, seqno=%u, waiters=%u",
> +__entry->dev, __entry->class, __entry->instance,
> +
[Intel-gfx] [PATCH V6 10/10] drm/rcar-du/crc: Implement get_crc_sources callback
This patch implements get_crc_sources callback, which returns list of
all the crc sources supported by driver in current platform.
Changes Since V1:
- move sources list per-crtc
- init sources-list only for gen3
Changes Since V2:
- Adopt to driver style
- Address other review comments from Laurent Pinchart
Changes Since V3/4/5: (Laurent Pinchart review)
- s/rcar_du_crtc_crc_sources_list_init/rcar_du_crtc_crc_init
- s/rcar_du_crtc_crc_sources_list_uninit/rcar_du_crtc_crc_cleanup
- other cleanup
Signed-off-by: Mahesh Kumar
Cc: dri-de...@lists.freedesktop.org
Cc: Laurent Pinchart
Reviewed-by: Laurent Pinchart
---
drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 82 +-
drivers/gpu/drm/rcar-du/rcar_du_crtc.h | 3 ++
2 files changed, 84 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
index 43e67cffdee0..8a9e5e6f16b4 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
@@ -691,6 +691,65 @@ static const struct drm_crtc_helper_funcs
crtc_helper_funcs = {
.atomic_disable = rcar_du_crtc_atomic_disable,
};
+static void rcar_du_crtc_crc_init(struct rcar_du_crtc *rcrtc)
+{
+ struct rcar_du_device *rcdu = rcrtc->group->dev;
+ const char **sources;
+ unsigned int count;
+ int i = -1;
+
+ /* CRC available only on Gen3 HW. */
+ if (rcdu->info->gen < 3)
+ return;
+
+ /* Reserve 1 for "auto" source. */
+ count = rcrtc->vsp->num_planes + 1;
+
+ sources = kmalloc_array(count, sizeof(*sources), GFP_KERNEL);
+ if (!sources)
+ return;
+
+ sources[0] = kstrdup("auto", GFP_KERNEL);
+ if (!sources[0])
+ goto error;
+
+ for (i = 0; i < rcrtc->vsp->num_planes; ++i) {
+ struct drm_plane *plane = >vsp->planes[i].plane;
+ char name[16];
+
+ sprintf(name, "plane%u", plane->base.id);
+ sources[i + 1] = kstrdup(name, GFP_KERNEL);
+ if (!sources[i + 1])
+ goto error;
+ }
+
+ rcrtc->sources = sources;
+ rcrtc->sources_count = count;
+ return;
+
+error:
+ while (i >= 0) {
+ kfree(sources[i]);
+ i--;
+ }
+ kfree(sources);
+}
+
+static void rcar_du_crtc_crc_cleanup(struct rcar_du_crtc *rcrtc)
+{
+ unsigned int i;
+
+ if (!rcrtc->sources)
+ return;
+
+ for (i = 0; i < rcrtc->sources_count; i++)
+ kfree(rcrtc->sources[i]);
+ kfree(rcrtc->sources);
+
+ rcrtc->sources = NULL;
+ rcrtc->sources_count = 0;
+}
+
static struct drm_crtc_state *
rcar_du_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
{
@@ -717,6 +776,15 @@ static void rcar_du_crtc_atomic_destroy_state(struct
drm_crtc *crtc,
kfree(to_rcar_crtc_state(state));
}
+static void rcar_du_crtc_cleanup(struct drm_crtc *crtc)
+{
+ struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
+
+ rcar_du_crtc_crc_cleanup(rcrtc);
+
+ return drm_crtc_cleanup(crtc);
+}
+
static void rcar_du_crtc_reset(struct drm_crtc *crtc)
{
struct rcar_du_crtc_state *state;
@@ -809,6 +877,15 @@ static int rcar_du_crtc_verify_crc_source(struct drm_crtc
*crtc,
return 0;
}
+const char *const *rcar_du_crtc_get_crc_sources(struct drm_crtc *crtc,
+ size_t *count)
+{
+ struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
+
+ *count = rcrtc->sources_count;
+ return rcrtc->sources;
+}
+
static int rcar_du_crtc_set_crc_source(struct drm_crtc *crtc,
const char *source_name)
{
@@ -879,7 +956,7 @@ static const struct drm_crtc_funcs crtc_funcs_gen2 = {
static const struct drm_crtc_funcs crtc_funcs_gen3 = {
.reset = rcar_du_crtc_reset,
- .destroy = drm_crtc_cleanup,
+ .destroy = rcar_du_crtc_cleanup,
.set_config = drm_atomic_helper_set_config,
.page_flip = drm_atomic_helper_page_flip,
.atomic_duplicate_state = rcar_du_crtc_atomic_duplicate_state,
@@ -888,6 +965,7 @@ static const struct drm_crtc_funcs crtc_funcs_gen3 = {
.disable_vblank = rcar_du_crtc_disable_vblank,
.set_crc_source = rcar_du_crtc_set_crc_source,
.verify_crc_source = rcar_du_crtc_verify_crc_source,
+ .get_crc_sources = rcar_du_crtc_get_crc_sources,
};
/*
-
@@ -1026,5 +1104,7 @@ int rcar_du_crtc_create(struct rcar_du_group *rgrp,
unsigned int swindex,
return ret;
}
+ rcar_du_crtc_crc_init(rcrtc);
+
return 0;
}
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.h
b/drivers/gpu/drm/rcar-du/rcar_du_crtc.h
index 7680cb2636c8..592c79993e08 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.h
+++
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Restore user forcewake domains across suspend
== Series Details ==
Series: drm/i915: Restore user forcewake domains across suspend
URL : https://patchwork.freedesktop.org/series/47894/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4633 -> Patchwork_9887 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/47894/revisions/1/mbox/
== Known issues ==
Here are the changes found in Patchwork_9887 that come from known issues:
=== IGT changes ===
Issues hit
igt@drv_selftest@live_workarounds:
{fi-cfl-8109u}: PASS -> DMESG-FAIL (fdo#107292)
fi-bsw-n3050: PASS -> DMESG-FAIL (fdo#107292)
fi-cnl-psr: PASS -> DMESG-FAIL (fdo#107292)
fi-kbl-7560u: PASS -> DMESG-FAIL (fdo#107292)
igt@kms_chamelium@dp-edid-read:
fi-kbl-7500u: PASS -> FAIL (fdo#103841)
Possible fixes
igt@drv_selftest@live_hangcheck:
fi-skl-guc: DMESG-FAIL (fdo#107174) -> PASS
igt@drv_selftest@live_workarounds:
fi-whl-u: DMESG-FAIL (fdo#107292) -> PASS
fi-kbl-x1275: DMESG-FAIL (fdo#107292) -> PASS
igt@kms_frontbuffer_tracking@basic:
{fi-byt-clapper}: FAIL (fdo#103167) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
fdo#107174 https://bugs.freedesktop.org/show_bug.cgi?id=107174
fdo#107292 https://bugs.freedesktop.org/show_bug.cgi?id=107292
== Participating hosts (51 -> 47) ==
Additional (1): fi-bxt-dsi
Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4633 -> Patchwork_9887
CI_DRM_4633: ea6e3f703e4d234c9c8eaec6c533355c7454ecb6 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4588: 7e5abbe4d9b2129bbbf02be77a70cad3da2ab941 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9887: 8f7ed83e1713847e6296b8fbd7f7a6e9f4474b9d @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
8f7ed83e1713 drm/i915: Restore user forcewake domains across suspend
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9887/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/tracing: Enable user interrupts while intel_engine_notify is active
== Series Details == Series: drm/i915/tracing: Enable user interrupts while intel_engine_notify is active URL : https://patchwork.freedesktop.org/series/47897/ State : failure == Summary == Applying: drm/i915/tracing: Enable user interrupts while intel_engine_notify is active Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/i915_trace.h Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/i915_trace.h CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_trace.h error: Failed to merge in the changes. Patch failed at 0001 drm/i915/tracing: Enable user interrupts while intel_engine_notify is active Use 'git am --show-current-patch' to see the failed patch When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915/tracing: Enable user interrupts while intel_engine_notify is active
From: Tvrtko Ursulin
Keep the user interrupt enabled and emit intel_engine_notify tracepoint
every time as long as it is enabled.
Premise is that if someone is listening, they want to see interrupts
logged.
We use tracepoint (de)registration callbacks to enable user interrupts on
all devices (future proofing and avoiding ugly global pointers) and all
engines.
For this to work we also have to add another call site of
trace_intel_engine_notify, notably to the early return from notify_ring
otherwise we still depend on waiters being present.
v2:
* Improve makefile. (Chris Wilson)
* Simplify by dropping the pointeless global driver list. (Chris Wilson)
* Emit tracepoint when there are no waiters, not just the user interrupt.
* Commit message tidy.
Signed-off-by: Tvrtko Ursulin
Cc: Chris Wilson
Cc: Dmitry Rogozhkin
Cc: John Harrison
Cc: svetlana.kukan...@intel.com
---
drivers/gpu/drm/i915/Makefile | 3 +
drivers/gpu/drm/i915/i915_drv.c | 5 ++
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_irq.c | 4 +-
drivers/gpu/drm/i915/i915_trace.h | 50 ---
drivers/gpu/drm/i915/i915_tracing.c | 98 +
drivers/gpu/drm/i915/i915_tracing.h | 13
7 files changed, 151 insertions(+), 24 deletions(-)
create mode 100644 drivers/gpu/drm/i915/i915_tracing.c
create mode 100644 drivers/gpu/drm/i915/i915_tracing.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 5794f102f9b8..dfc940b32078 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -182,6 +182,9 @@ i915-y += i915_perf.o \
i915_oa_cnl.o \
i915_oa_icl.o
+# tracing
+i915-$(CONFIG_TRACEPOINTS) += i915_tracing.o
+
ifeq ($(CONFIG_DRM_I915_GVT),y)
i915-y += intel_gvt.o
include $(src)/gvt/Makefile
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9dce55182c3a..03e224ebc28c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1281,6 +1281,9 @@ static void i915_driver_register(struct drm_i915_private
*dev_priv)
*/
if (INTEL_INFO(dev_priv)->num_pipes)
drm_kms_helper_poll_init(dev);
+
+ /* Notify our tracepoints driver has been registered. */
+ i915_tracing_register(dev_priv);
}
/**
@@ -1292,6 +1295,8 @@ static void i915_driver_unregister(struct
drm_i915_private *dev_priv)
intel_fbdev_unregister(dev_priv);
intel_audio_deinit(dev_priv);
+ i915_tracing_unregister(dev_priv);
+
/*
* After flushing the fbdev (incl. a late async config which will
* have delayed queuing of a hotplug event), then flush the hotplug
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0b10a30b7d96..a15f8be0ece0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2141,6 +2141,8 @@ struct drm_i915_private {
struct i915_pmu pmu;
+ struct list_head driver_list_link;
+
/*
* NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
* will be rejected. Instead look for a better place.
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 8084e35b25c5..8cba798b666d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1159,8 +1159,10 @@ static void notify_ring(struct intel_engine_cs *engine)
struct task_struct *tsk = NULL;
struct intel_wait *wait;
- if (unlikely(!engine->breadcrumbs.irq_armed))
+ if (unlikely(!engine->breadcrumbs.irq_armed)) {
+ trace_intel_engine_notify(engine, false);
return;
+ }
rcu_read_lock();
diff --git a/drivers/gpu/drm/i915/i915_trace.h
b/drivers/gpu/drm/i915/i915_trace.h
index c0352a1b036c..12555d2388fd 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -8,6 +8,7 @@
#include
#include "i915_drv.h"
+#include "i915_tracing.h"
#include "intel_drv.h"
#include "intel_ringbuffer.h"
@@ -750,29 +751,32 @@ TRACE_EVENT(i915_request_out,
__entry->global_seqno, __entry->completed)
);
-TRACE_EVENT(intel_engine_notify,
- TP_PROTO(struct intel_engine_cs *engine, bool waiters),
- TP_ARGS(engine, waiters),
-
- TP_STRUCT__entry(
-__field(u32, dev)
-__field(u16, class)
-__field(u16, instance)
-__field(u32, seqno)
-__field(bool, waiters)
-),
-
- TP_fast_assign(
- __entry->dev = engine->i915->drm.primary->index;
- __entry->class = engine->uabi_class;
- __entry->instance = engine->instance;
- __entry->seqno =
[Intel-gfx] [PATCH i-g-t 2/2] igt/perf_pmu: Improve the presentation of the accuracy calibration
Normalize the variance to stddev, and remove some redundant steps in
computing the time from itself.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
tests/perf_pmu.c | 22 +-
1 file changed, 13 insertions(+), 9 deletions(-)
diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index 5a26d5272..4e8da3d94 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -1577,8 +1577,8 @@ accuracy(int gem_fd, const struct intel_execution_engine2
*e,
/* 1st pass is calibration, second pass is the test. */
for (int pass = 0; pass < ARRAY_SIZE(timeout); pass++) {
unsigned int target_idle_us = idle_us;
- uint64_t busy_ns = 0, idle_ns = 0;
struct timespec start = { };
+ uint64_t busy_ns = 0;
unsigned long pass_ns = 0;
double avg = 0.0, var = 0.0;
unsigned int n = 0;
@@ -1589,6 +1589,7 @@ accuracy(int gem_fd, const struct intel_execution_engine2
*e,
unsigned long loop_ns, loop_busy;
struct timespec _ts = { };
double err, tmp;
+ uint64_t now;
/* PWM idle sleep. */
_ts.tv_nsec = target_idle_us * 1000;
@@ -1605,14 +1606,13 @@ accuracy(int gem_fd, const struct
intel_execution_engine2 *e,
igt_spin_batch_end(spin);
/* Time accounting. */
- loop_ns = igt_nsec_elapsed();
- loop_busy = loop_ns - loop_busy;
- loop_ns -= pass_ns;
+ now = igt_nsec_elapsed();
+ loop_busy = now - loop_busy;
+ loop_ns = now - pass_ns;
+ pass_ns = now;
busy_ns += loop_busy;
total_busy_ns += loop_busy;
- idle_ns += loop_ns - loop_busy;
- pass_ns += loop_ns;
total_ns += loop_ns;
/* Re-calibrate. */
@@ -1628,10 +1628,14 @@ accuracy(int gem_fd, const struct
intel_execution_engine2 *e,
var += (err - avg) * (err - tmp);
} while (pass_ns < timeout[pass]);
+ pass_ns = igt_nsec_elapsed();
expected = (double)busy_ns / pass_ns;
- igt_info("%u: busy %"PRIu64"us, idle %"PRIu64"us ->
%.2f%% (target: %lu%%; average=%.2f, variance=%f)\n",
-pass, busy_ns / 1000, idle_ns / 1000,
-100 * expected, target_busy_pct, avg, var / n);
+
+ igt_info("%u: busy %"PRIu64"us, idle %"PRIu64"us ->
%.2f%% (target: %lu%%; average=%.2f±%.3f%%)\n",
+pass, busy_ns / 1000, (pass_ns - busy_ns) /
1000,
+100 * expected, target_busy_pct,
+avg, sqrt(var / n));
+
write(link[1], , sizeof(expected));
}
--
2.18.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 1/2] igt/perf_pmu: Aim for a fixed number of iterations for calibrating accuracy
Our observation is that the systematic error is proportional to the
number of iterations we perform; the suspicion is that it directly
correlates with the number of sleeps. Reduce the number of iterations,
to try and keep the error in check.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
tests/perf_pmu.c | 34 +-
1 file changed, 21 insertions(+), 13 deletions(-)
diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index 9a20abb6b..5a26d5272 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -1521,14 +1521,13 @@ static void __rearm_spin_batch(igt_spin_t *spin)
static void
accuracy(int gem_fd, const struct intel_execution_engine2 *e,
-unsigned long target_busy_pct)
+unsigned long target_busy_pct,
+unsigned long target_iters)
{
- unsigned long busy_us = 1 - 100 * (1 + abs(50 - target_busy_pct));
- unsigned long idle_us = 100 * (busy_us - target_busy_pct *
- busy_us / 100) / target_busy_pct;
const unsigned long min_test_us = 1e6;
- const unsigned long pwm_calibration_us = min_test_us;
- const unsigned long test_us = min_test_us;
+ unsigned long pwm_calibration_us;
+ unsigned long test_us;
+ unsigned long cycle_us, busy_us, idle_us;
double busy_r, expected;
uint64_t val[2];
uint64_t ts[2];
@@ -1538,18 +1537,27 @@ accuracy(int gem_fd, const struct
intel_execution_engine2 *e,
/* Sampling platforms cannot reach the high accuracy criteria. */
igt_require(gem_has_execlists(gem_fd));
- while (idle_us < 2500) {
+ /* Aim for approximately 100 iterations for calibration */
+ cycle_us = min_test_us / target_iters;
+ busy_us = cycle_us * target_busy_pct / 100;
+ idle_us = cycle_us - busy_us;
+
+ while (idle_us < 2500 || busy_us < 2500) {
busy_us *= 2;
idle_us *= 2;
}
+ cycle_us = busy_us + idle_us;
+ pwm_calibration_us = target_iters * cycle_us / 2;
+ test_us = target_iters * cycle_us;
- igt_info("calibration=%lums, test=%lums; ratio=%.2f%% (%luus/%luus)\n",
-pwm_calibration_us / 1000, test_us / 1000,
-(double)busy_us / (busy_us + idle_us) * 100.0,
+ igt_info("calibration=%lums, test=%lums, cycle=%lums; ratio=%.2f%%
(%luus/%luus)\n",
+pwm_calibration_us / 1000, test_us / 1000, cycle_us / 1000,
+(double)busy_us / cycle_us * 100.0,
busy_us, idle_us);
- assert_within_epsilon((double)busy_us / (busy_us + idle_us),
- (double)target_busy_pct / 100.0, tolerance);
+ assert_within_epsilon((double)busy_us / cycle_us,
+ (double)target_busy_pct / 100.0,
+ tolerance);
igt_assert(pipe(link) == 0);
@@ -1796,7 +1804,7 @@ igt_main
for (i = 0; i < ARRAY_SIZE(pct); i++) {
igt_subtest_f("busy-accuracy-%u-%s",
pct[i], e->name)
- accuracy(fd, e, pct[i]);
+ accuracy(fd, e, pct[i], 10);
}
igt_subtest_f("busy-hang-%s", e->name)
--
2.18.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Restore user forcewake domains across suspend
On suspend, we cancel the automatic forcewake and clear all other sources
of forcewake so the machine can sleep before we do suspend. However, we
expose the forcewake to userspace (only via debugfs, but nevertheless we
do) and want to restore that upon resume or else our accounting will be
off and we may not acquire the forcewake before we use it. So record
which domains we cleared on suspend and reacquire them early on resume.
Reported-by: Imre Deak
Fixes: b8473050805f ("drm/i915: Fix forcewake active domain tracking")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
Cc: Imre Deak
---
drivers/gpu/drm/i915/intel_uncore.c | 42 ++-
drivers/gpu/drm/i915/intel_uncore.h | 1 +
drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 +-
3 files changed, 24 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 284be151f645..74396a606444 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -369,8 +369,8 @@ intel_uncore_fw_release_timer(struct hrtimer *timer)
}
/* Note callers must have acquired the PUNIT->PMIC bus, before calling this. */
-static void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
-bool restore)
+static unsigned int
+intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv)
{
unsigned long irqflags;
struct intel_uncore_forcewake_domain *domain;
@@ -422,20 +422,11 @@ static void intel_uncore_forcewake_reset(struct
drm_i915_private *dev_priv,
dev_priv->uncore.funcs.force_wake_put(dev_priv, fw);
fw_domains_reset(dev_priv, dev_priv->uncore.fw_domains);
-
- if (restore) { /* If reset with a user forcewake, try to restore */
- if (fw)
- dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
-
- if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
- dev_priv->uncore.fifo_count =
- fifo_free_entries(dev_priv);
- }
-
- if (!restore)
- assert_forcewakes_inactive(dev_priv);
+ assert_forcewakes_inactive(dev_priv);
spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
+
+ return fw; /* track the lost user forcewake domains */
}
static u64 gen9_edram_size(struct drm_i915_private *dev_priv)
@@ -544,7 +535,7 @@ check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
}
static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
- bool restore_forcewake)
+ unsigned int restore_forcewake)
{
/* clear out unclaimed reg detection bit */
if (check_for_unclaimed_mmio(dev_priv))
@@ -559,7 +550,15 @@ static void __intel_uncore_early_sanitize(struct
drm_i915_private *dev_priv,
}
iosf_mbi_punit_acquire();
- intel_uncore_forcewake_reset(dev_priv, restore_forcewake);
+ intel_uncore_forcewake_reset(dev_priv);
+ if (restore_forcewake) {
+ dev_priv->uncore.funcs.force_wake_get(dev_priv,
+ restore_forcewake);
+
+ if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
+ dev_priv->uncore.fifo_count =
+ fifo_free_entries(dev_priv);
+ }
iosf_mbi_punit_release();
}
@@ -568,13 +567,16 @@ void intel_uncore_suspend(struct drm_i915_private
*dev_priv)
iosf_mbi_punit_acquire();
iosf_mbi_unregister_pmic_bus_access_notifier_unlocked(
_priv->uncore.pmic_bus_access_nb);
- intel_uncore_forcewake_reset(dev_priv, false);
+ dev_priv->uncore.fw_domains_user =
+ intel_uncore_forcewake_reset(dev_priv);
iosf_mbi_punit_release();
}
void intel_uncore_resume_early(struct drm_i915_private *dev_priv)
{
- __intel_uncore_early_sanitize(dev_priv, true);
+ __intel_uncore_early_sanitize(dev_priv,
+ dev_priv->uncore.fw_domains_user);
+
iosf_mbi_register_pmic_bus_access_notifier(
_priv->uncore.pmic_bus_access_nb);
i915_check_and_clear_faults(dev_priv);
@@ -1555,7 +1557,7 @@ void intel_uncore_init(struct drm_i915_private *dev_priv)
intel_uncore_edram_detect(dev_priv);
intel_uncore_fw_domains_init(dev_priv);
- __intel_uncore_early_sanitize(dev_priv, false);
+ __intel_uncore_early_sanitize(dev_priv, 0);
dev_priv->uncore.unclaimed_mmio_check = 1;
dev_priv->uncore.pmic_bus_access_nb.notifier_call =
@@ -1642,7 +1644,7 @@ void intel_uncore_fini(struct drm_i915_private *dev_priv)
iosf_mbi_punit_acquire();
iosf_mbi_unregister_pmic_bus_access_notifier_unlocked(
_priv->uncore.pmic_bus_access_nb);
-
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Allow control of PSR at runtime through debugfs, v5
== Series Details ==
Series: series starting with [1/2] drm/i915: Allow control of PSR at runtime
through debugfs, v5
URL : https://patchwork.freedesktop.org/series/47888/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4633 -> Patchwork_9886 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/47888/revisions/1/mbox/
== Known issues ==
Here are the changes found in Patchwork_9886 that come from known issues:
=== IGT changes ===
Issues hit
{igt@amdgpu/amd_basic@userptr}:
{fi-kbl-8809g}: PASS -> INCOMPLETE (fdo#107402)
igt@drv_selftest@live_coherency:
fi-gdg-551: PASS -> DMESG-FAIL (fdo#107164)
igt@drv_selftest@live_hangcheck:
fi-cfl-s3: PASS -> DMESG-FAIL (fdo#106560)
fi-bxt-j4205: PASS -> DMESG-FAIL (fdo#106560)
igt@drv_selftest@live_workarounds:
{fi-cfl-8109u}: PASS -> DMESG-FAIL (fdo#107292)
fi-cnl-psr: PASS -> DMESG-FAIL (fdo#107292)
igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
{fi-byt-clapper}: PASS -> FAIL (fdo#107362)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
fi-snb-2520m: PASS -> INCOMPLETE (fdo#103713)
Possible fixes
igt@drv_selftest@live_hangcheck:
fi-skl-guc: DMESG-FAIL (fdo#107174) -> PASS
igt@drv_selftest@live_workarounds:
fi-whl-u: DMESG-FAIL (fdo#107292) -> PASS
fi-kbl-x1275: DMESG-FAIL (fdo#107292) -> PASS
igt@kms_frontbuffer_tracking@basic:
{fi-byt-clapper}: FAIL (fdo#103167) -> PASS
Warnings
{igt@kms_psr@primary_page_flip}:
fi-cnl-psr: DMESG-FAIL (fdo#107372) -> DMESG-WARN (fdo#107372)
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
fdo#107164 https://bugs.freedesktop.org/show_bug.cgi?id=107164
fdo#107174 https://bugs.freedesktop.org/show_bug.cgi?id=107174
fdo#107292 https://bugs.freedesktop.org/show_bug.cgi?id=107292
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107372 https://bugs.freedesktop.org/show_bug.cgi?id=107372
fdo#107402 https://bugs.freedesktop.org/show_bug.cgi?id=107402
== Participating hosts (51 -> 47) ==
Additional (1): fi-bxt-dsi
Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4633 -> Patchwork_9886
CI_DRM_4633: ea6e3f703e4d234c9c8eaec6c533355c7454ecb6 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4588: 7e5abbe4d9b2129bbbf02be77a70cad3da2ab941 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9886: a61846961762ac2ce6ac6b2c23411dd45b08b5cb @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
a61846961762 drm/i915/psr: Add debugfs support to force a downgrade to PSR1
mode.
156e45d20493 drm/i915: Allow control of PSR at runtime through debugfs, v5
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9886/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915: Allow control of PSR at runtime through debugfs, v5
== Series Details == Series: series starting with [1/2] drm/i915: Allow control of PSR at runtime through debugfs, v5 URL : https://patchwork.freedesktop.org/series/47888/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: Allow control of PSR at runtime through debugfs, v5 -drivers/gpu/drm/i915/selftests/../i915_drv.h:3675:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3683:16: warning: expression using sizeof(void) Commit: drm/i915/psr: Add debugfs support to force a downgrade to PSR1 mode. -drivers/gpu/drm/i915/selftests/../i915_drv.h:3683:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3684:16: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Allow control of PSR at runtime through debugfs, v5
== Series Details ==
Series: series starting with [1/2] drm/i915: Allow control of PSR at runtime
through debugfs, v5
URL : https://patchwork.freedesktop.org/series/47888/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
156e45d20493 drm/i915: Allow control of PSR at runtime through debugfs, v5
-:25: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#25:
- Add prepared bool, which should be used instead of relying on psr.dp. (dhnkrn)
-:143: ERROR:TRAILING_WHITESPACE: trailing whitespace
#143: FILE: drivers/gpu/drm/i915/intel_drv.h:1927:
+// $
-:366: CHECK:BRACES: braces {} should be used on all arms of this statement
#366: FILE: drivers/gpu/drm/i915/intel_psr.c:848:
+ if (crtc) {
[...]
+ } else
[...]
-:372: CHECK:BRACES: Unbalanced braces around else statement
#372: FILE: drivers/gpu/drm/i915/intel_psr.c:854:
+ } else
total: 1 errors, 1 warnings, 2 checks, 351 lines checked
a61846961762 drm/i915/psr: Add debugfs support to force a downgrade to PSR1
mode.
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915: Allow control of PSR at runtime through debugfs, v5
Currently tests modify i915.enable_psr and then do a modeset cycle
to change PSR. We can write a value to i915_edp_psr_debug to force
a certain PSR mode without a modeset.
To retain compatibility with older userspace, we also still allow
the override through the module parameter, and add some tracking
to check whether a debugfs mode is specified.
Changes since v1:
- Rename dev_priv->psr.enabled to .dp, and .hw_configured to .enabled.
- Fix i915_psr_debugfs_mode to match the writes to debugfs.
- Rename __i915_edp_psr_write to intel_psr_set_debugfs_mode, simplify
it and move it to intel_psr.c. This keeps all internals in intel_psr.c
- Perform an interruptible wait for hw completion outside of the psr
lock, instead of being forced to trywait and return -EBUSY.
Changes since v2:
- Rebase on top of intel_psr changes.
Changes since v3:
- Assign psr.dp during init. (dhnkrn)
- Add prepared bool, which should be used instead of relying on psr.dp. (dhnkrn)
- Fix -EDEADLK handling in debugfs. (dhnkrn)
- Clean up waiting for idle in intel_psr_set_debugfs_mode.
- Print PSR mode when trying to enable PSR. (dhnkrn)
- Move changing psr debug setting to i915_edp_psr_debug_set. (dhnkrn)
Changes since v4:
- Return error in _set() function.
- Change flag values to make them easier to remember. (dhnkrn)
- Only assign psr.dp once. (dhnkrn)
- Only set crtc_state->has_psr on the crtc with psr.dp.
- Fix typo. (dhnkrn)
Signed-off-by: Maarten Lankhorst
Cc: Rodrigo Vivi
Cc: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/i915_debugfs.c | 23 -
drivers/gpu/drm/i915/i915_drv.h | 12 ++-
drivers/gpu/drm/i915/i915_irq.c | 2 +-
drivers/gpu/drm/i915/intel_drv.h| 5 +-
drivers/gpu/drm/i915/intel_psr.c| 138 +++-
5 files changed, 149 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index f9ce35da4123..3e81301a94ba 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2708,7 +2708,7 @@ static int i915_edp_psr_status(struct seq_file *m, void
*data)
intel_runtime_pm_get(dev_priv);
mutex_lock(_priv->psr.lock);
- seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
+ seq_printf(m, "Enabled: %s\n", yesno(dev_priv->psr.enabled));
seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
dev_priv->psr.busy_frontbuffer_bits);
@@ -2750,17 +2750,32 @@ static int
i915_edp_psr_debug_set(void *data, u64 val)
{
struct drm_i915_private *dev_priv = data;
+ struct drm_modeset_acquire_ctx ctx;
+ int ret;
if (!CAN_PSR(dev_priv))
return -ENODEV;
- DRM_DEBUG_KMS("PSR debug %s\n", enableddisabled(val));
+ DRM_DEBUG_KMS("Setting PSR debug to %llx\n", val);
intel_runtime_pm_get(dev_priv);
- intel_psr_irq_control(dev_priv, !!val);
+
+ drm_modeset_acquire_init(, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
+
+retry:
+ ret = intel_psr_set_debugfs_mode(dev_priv, , val);
+ if (ret == -EDEADLK) {
+ ret = drm_modeset_backoff();
+ if (!ret)
+ goto retry;
+ }
+
+ drm_modeset_drop_locks();
+ drm_modeset_acquire_fini();
+
intel_runtime_pm_put(dev_priv);
- return 0;
+ return ret;
}
static int
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 657f46e0cae9..a3ea48ce1811 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -611,8 +611,17 @@ struct i915_drrs {
struct i915_psr {
struct mutex lock;
+
+#define I915_PSR_DEBUG_MODE_MASK 0x0f
+#define I915_PSR_DEBUG_DEFAULT 0x00
+#define I915_PSR_DEBUG_DISABLE 0x01
+#define I915_PSR_DEBUG_ENABLE 0x02
+#define I915_PSR_DEBUG_IRQ 0x10
+
+ u32 debug;
bool sink_support;
- struct intel_dp *enabled;
+ bool prepared, enabled;
+ struct intel_dp *dp;
bool active;
struct work_struct work;
unsigned busy_frontbuffer_bits;
@@ -622,7 +631,6 @@ struct i915_psr {
bool alpm;
bool psr2_enabled;
u8 sink_sync_latency;
- bool debug;
ktime_t last_entry_attempt;
ktime_t last_exit;
};
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 8084e35b25c5..b2c9838442bc 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4048,7 +4048,7 @@ static int ironlake_irq_postinstall(struct drm_device
*dev)
if (IS_HASWELL(dev_priv)) {
gen3_assert_iir_is_zero(dev_priv, EDP_PSR_IIR);
- intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
+ intel_psr_irq_control(dev_priv, dev_priv->psr.debug &
I915_PSR_DEBUG_IRQ);
display_mask |= DE_EDP_PSR_INT_HSW;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h
Re: [Intel-gfx] [PATCH i-g-t] igt/gem_eio: Preserve batch between reset-stress iterations
Quoting Tvrtko Ursulin (2018-08-08 13:57:56)
>
> On 08/08/2018 13:47, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-08-08 13:38:53)
> >>
> >> On 08/08/2018 12:31, Chris Wilson wrote:
> >>>igt_until_timeout(5) {
> >>> - struct drm_i915_gem_execbuffer2 execbuf = { };
> >>> - struct drm_i915_gem_exec_object2 obj = { };
> >>> - uint32_t bbe = MI_BATCH_BUFFER_END;
> >>> + uint32_t ctx = context_create_safe(fd);
> >>
> >> There is still this per loop...
> >
> > I thought that was intentional :)
> >
> > It felt like the spirit of the test to try and mix up the contexts as
> > much as possible; one constant, one fresh.
>
> Yes definitely intentional (required), I was just puzzled why you are
> concerned with removing one gem_create when we have more ioctls in the
> loop anyway.
Low hanging fruit. Besides, I would cache the context objects if someone
would just turn a blind eye.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915/psr: Add debugfs support to force a downgrade to PSR1 mode.
This will make it easier to test PSR1 on PSR2 capable eDP machines.
Changes since v1:
- Remove I915_PSR_DEBUG_FORCE_PSR2, it did nothing, not sure forcing
PSR2 would even work.
- Handle NULL crtc in intel_psr_set_debugfs_mode. (dhnkrn)
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_psr.c | 44
2 files changed, 40 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a3ea48ce1811..14883614d9e6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -616,6 +616,7 @@ struct i915_psr {
#define I915_PSR_DEBUG_DEFAULT 0x00
#define I915_PSR_DEBUG_DISABLE 0x01
#define I915_PSR_DEBUG_ENABLE 0x02
+#define I915_PSR_DEBUG_FORCE_PSR1 0x03
#define I915_PSR_DEBUG_IRQ 0x10
u32 debug;
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 12fbc59af5a4..a408faa16f90 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -68,6 +68,17 @@ static bool psr_global_enabled(u32 debug)
}
}
+static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
+ const struct intel_crtc_state *crtc_state)
+{
+ switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
+ case I915_PSR_DEBUG_FORCE_PSR1:
+ return false;
+ default:
+ return crtc_state->has_psr2;
+ }
+}
+
void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool debug)
{
u32 debug_mask, mask;
@@ -646,7 +657,7 @@ void intel_psr_enable(struct intel_dp *intel_dp,
goto unlock;
}
- dev_priv->psr.psr2_enabled = crtc_state->has_psr2;
+ dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state);
dev_priv->psr.busy_frontbuffer_bits = 0;
dev_priv->psr.prepared = true;
@@ -820,19 +831,38 @@ static bool __psr_wait_for_idle_locked(struct
drm_i915_private *dev_priv)
return err == 0 && dev_priv->psr.enabled;
}
+static bool switching_psr(struct drm_i915_private *dev_priv,
+ struct intel_crtc_state *crtc_state,
+ u32 mode)
+{
+ /* Can't switch psr state anyway if PSR2 is not supported. */
+ if (!crtc_state || !crtc_state->has_psr2)
+ return false;
+
+ if (dev_priv->psr.psr2_enabled && mode == I915_PSR_DEBUG_FORCE_PSR1)
+ return true;
+
+ if (!dev_priv->psr.psr2_enabled && mode != I915_PSR_DEBUG_FORCE_PSR1)
+ return true;
+
+ return false;
+}
+
int intel_psr_set_debugfs_mode(struct drm_i915_private *dev_priv,
struct drm_modeset_acquire_ctx *ctx,
u64 val)
{
struct drm_device *dev = _priv->drm;
struct drm_connector_state *conn_state;
+ struct intel_crtc_state *crtc_state = NULL;
struct drm_crtc *crtc;
struct intel_dp *dp;
int ret;
bool enable;
+ u32 mode = val & I915_PSR_DEBUG_MODE_MASK;
if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) ||
- (val & I915_PSR_DEBUG_MODE_MASK) > I915_PSR_DEBUG_ENABLE) {
+ mode > I915_PSR_DEBUG_FORCE_PSR1) {
DRM_DEBUG_KMS("Invalid debug mask %llx\n", val);
return -EINVAL;
}
@@ -850,7 +880,8 @@ int intel_psr_set_debugfs_mode(struct drm_i915_private
*dev_priv,
if (ret)
return ret;
- ret =
wait_for_completion_interruptible(>state->commit->hw_done);
+ crtc_state = to_intel_crtc_state(crtc->state);
+ ret =
wait_for_completion_interruptible(_state->base.commit->hw_done);
} else
ret =
wait_for_completion_interruptible(_state->commit->hw_done);
@@ -863,14 +894,17 @@ int intel_psr_set_debugfs_mode(struct drm_i915_private
*dev_priv,
enable = psr_global_enabled(val);
- if (!enable)
+ if (!enable || switching_psr(dev_priv, crtc_state, mode))
intel_psr_disable_locked(dev_priv->psr.dp);
dev_priv->psr.debug = val;
+ if (crtc)
+ dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv,
crtc_state);
+
intel_psr_irq_control(dev_priv, dev_priv->psr.debug &
I915_PSR_DEBUG_IRQ);
if (dev_priv->psr.prepared && enable)
- intel_psr_enable_locked(dev_priv,
to_intel_crtc_state(crtc->state));
+ intel_psr_enable_locked(dev_priv, crtc_state);
mutex_unlock(_priv->psr.lock);
return ret;
--
2.18.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Missed interrupt simulation is no more, tell the world
== Series Details == Series: drm/i915: Missed interrupt simulation is no more, tell the world URL : https://patchwork.freedesktop.org/series/47875/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4632_full -> Patchwork_9883_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9883_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9883_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9883_full: === IGT changes === Warnings igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt: shard-hsw: SKIP -> PASS igt@pm_rc6_residency@rc6-accuracy: shard-kbl: PASS -> SKIP == Known issues == Here are the changes found in Patchwork_9883_full that come from known issues: === IGT changes === Issues hit igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing: shard-glk: PASS -> FAIL (fdo#107409, fdo#105703) igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-ytiled: shard-glk: PASS -> FAIL (fdo#103184) igt@kms_setmode@basic: shard-apl: PASS -> FAIL (fdo#99912) igt@kms_vblank@pipe-b-query-busy-hang: shard-kbl: PASS -> DMESG-WARN (fdo#106247) Possible fixes igt@drv_suspend@shrink: shard-snb: INCOMPLETE (fdo#106886, fdo#105411) -> PASS shard-kbl: FAIL (fdo#106886) -> PASS igt@kms_cursor_crc@cursor-128x128-suspend: shard-kbl: INCOMPLETE (fdo#103665) -> PASS igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-cpu: shard-hsw: DMESG-FAIL (fdo#103167) -> PASS fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103184 https://bugs.freedesktop.org/show_bug.cgi?id=103184 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703 fdo#106247 https://bugs.freedesktop.org/show_bug.cgi?id=106247 fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886 fdo#107409 https://bugs.freedesktop.org/show_bug.cgi?id=107409 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4632 -> Patchwork_9883 CI_DRM_4632: 648e2ff1094eabf43613f41d4d719c1a1f555dbb @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4587: 5d78c73d871525ec9caecd88ad7d9abe36637314 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9883: f5e65826bcc7ad3cdeaded1a2b6b77fe685e6a7d @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9883/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Warn if we hit the timeout for wait-for-idle (rev2)
== Series Details == Series: drm/i915: Warn if we hit the timeout for wait-for-idle (rev2) URL : https://patchwork.freedesktop.org/series/47869/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4632_full -> Patchwork_9882_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9882_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9882_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9882_full: === IGT changes === Warnings igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt: shard-hsw: SKIP -> PASS igt@pm_rc6_residency@rc6-accuracy: shard-kbl: PASS -> SKIP == Known issues == Here are the changes found in Patchwork_9882_full that come from known issues: === IGT changes === Issues hit igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing: shard-glk: PASS -> FAIL (fdo#107409) igt@kms_cursor_crc@cursor-128x128-suspend: shard-glk: PASS -> FAIL (fdo#103375) igt@kms_setmode@basic: shard-apl: PASS -> FAIL (fdo#99912) Possible fixes igt@drv_suspend@shrink: shard-snb: INCOMPLETE (fdo#105411, fdo#106886) -> PASS shard-kbl: FAIL (fdo#106886) -> PASS igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-cpu: shard-hsw: DMESG-FAIL (fdo#103167) -> PASS fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886 fdo#107409 https://bugs.freedesktop.org/show_bug.cgi?id=107409 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4632 -> Patchwork_9882 CI_DRM_4632: 648e2ff1094eabf43613f41d4d719c1a1f555dbb @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4587: 5d78c73d871525ec9caecd88ad7d9abe36637314 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9882: 640d2034f3f27d5e058f4b9ad25208cd367a7aef @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9882/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t] igt/gem_eio: Preserve batch between reset-stress iterations
On 08/08/2018 13:47, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-08-08 13:38:53)
On 08/08/2018 12:31, Chris Wilson wrote:
We can keep the original batch around and avoid recreating it between
reset iterations to focus on the impact of resets.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
tests/gem_eio.c | 30 +-
1 file changed, 17 insertions(+), 13 deletions(-)
diff --git a/tests/gem_eio.c b/tests/gem_eio.c
index de161332d..5250a414c 100644
--- a/tests/gem_eio.c
+++ b/tests/gem_eio.c
@@ -650,35 +650,38 @@ static void reset_stress(int fd,
uint32_t ctx0, unsigned int engine,
unsigned int flags)
{
+ const uint32_t bbe = MI_BATCH_BUFFER_END;
+ struct drm_i915_gem_exec_object2 obj = {
+ .handle = gem_create(fd, 4096)
+ };
+ struct drm_i915_gem_execbuffer2 execbuf = {
+ .buffers_ptr = to_user_pointer(),
+ .buffer_count = 1,
+ .flags = engine,
+ };
+ gem_write(fd, obj.handle, 0, , sizeof(bbe));
+
igt_until_timeout(5) {
- struct drm_i915_gem_execbuffer2 execbuf = { };
- struct drm_i915_gem_exec_object2 obj = { };
- uint32_t bbe = MI_BATCH_BUFFER_END;
+ uint32_t ctx = context_create_safe(fd);
There is still this per loop...
I thought that was intentional :)
It felt like the spirit of the test to try and mix up the contexts as
much as possible; one constant, one fresh.
Yes definitely intentional (required), I was just puzzled why you are
concerned with removing one gem_create when we have more ioctls in the
loop anyway.
igt_spin_t *hang;
unsigned int i;
- uint32_t ctx;
gem_quiescent_gpu(fd);
igt_require(i915_reset_control(flags & TEST_WEDGE ?
false : true));
- ctx = context_create_safe(fd);
-
/*
* Start executing a spin batch with some queued batches
* against a different context after it.
*/
hang = spin_sync(fd, ctx0, engine);
... and a ton of operations in this one, so I wonder why bother with one
batch?
Because I don't have spin_sync() in my pattern recognition matrix yet.
One excuse is that it doesn't have any create verb in its name, so easy
to forget its hidden costs.
Okay. :) I blame the poor name on it being local. :)
Regards,
Tvrtko
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/tracepoints: Remove DRM_I915_LOW_LEVEL_TRACEPOINTS Kconfig option
+Joonas On 08/08/2018 13:42, Chris Wilson wrote: Quoting Tvrtko Ursulin (2018-08-08 13:13:08) On 26/06/2018 12:48, Chris Wilson wrote: It's just that this about the third time this has been raised in the last couple of weeks with the other two requests being from a generic tooling pov (Eric Anholt for gnome-shell tweaking, and some one else looking for a gpuvis-like tool). So it seems like there is interest, even if I doubt that it'll help answer any questions beyond what you can just extract from looking at userspace. (Imo, the only people these tracepoints are useful for are people writing patches for the driver. For everyone else, you can just observe system behaviour and optimise your code for your workload. Otoh, can one trust a black box, argh.) Some of the things might be obtainable purely from userspace via heavily instrumented builds, which may be in the realm of possible for during development, but I don't think it is feasible in general both because it is too involved, and because it would preclude existence of tools which can trace any random client. To have a second set of nearly equivalent tracepoints, we need to have strong justification why we couldn't just use or extend the generic set. I was hoping that the conversation so far established that nearly equivalent is not close enough for intended use cases. And that is not possible to make the generic ones so. (I just don't see the point of those use cases. I trace the kernel to fix the kernel...) Yes and with virtual engine we will have a bigger reason to trace the kernel with a random client. Plus I feel a lot more comfortable exporting a set of generic tracepoints, than those where we may be leaking more knowledge of the HW than we can reasonably expect to support for the indefinite future. I think it is accepted we cannot guarantee low level tracepoints will be supportable in the future world of GuC scheduling. (How and what we will do there is yet unresolved.) But at least we get much better usability for platforms up to there, and for very small effort. The idea is not to mark these as ABI but just improve user experience. You are I suppose worried that if these tracepoints disappeared due being un-implementable someone will complain? They already do... I just want that anyone can run trace.pl and see how virtual engine behaves, without having to recompile the kernel. And VTune people want the same for their enterprise-level customers. Both tools are ready to adapt should it be required. Its I repeat just usability and user experience out of the box. The out-of-the-box user experience should not require the use of such tools in the first place! If they are trying to work around the kernel (and that's the only use of this information I see) we have bugs a plenty. [snip because I repeated myself] I think my issues boil down to: 1 - people will complain no matter what (when it changes, when it is no longer available) 2 - people will use it to workaround not fix; the information about kernel behaviour should only be used with a view to fixing that behaviour As such, I am quite happy to have it limited to driver developers that want to fix issues at source (OpenCL, I'm looking at you). There's tons of other user observable information out there for tuning userspace, why does the latency of runnable->queued matter if you will not do anything about it? Other things like dependency graphs, if you can't keep control of your own fences, you've already lost. This is true, no disagreement. My point simply was that we can provide this info easily to anyone. There is a little bit of analogy with perf scheduler tracing/map etc. I don't see any value in giving the information away, just the cost. If you can convince Joonas of its merit, and if we can define just exactly what ABI it constitutes, then I'd be happy to be the one who says "I told you so" in the future for a change. I think Joonas was okay in principle that we soft-commit to _trying_ to keep _some_ tracepoint stable-ish (where it makes sense and after some discussion for each) if IGT also materializes which auto-pings us (via CI) when we break one of them. But I may be misremembering so Joonas please comment. Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] igt/amd_prime: Link an amdgpu bo into i915 and try to shrink it
On 07/08/2018 16:57, Chris Wilson wrote:
Create and export an amdgpu bo into i915 so that we can try and
invalidate the i915_bo->pages from inside the shrinker, teaching lockdep
about that linkage.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Daniel Vetter
---
tests/amdgpu/amd_prime.c | 32
1 file changed, 32 insertions(+)
diff --git a/tests/amdgpu/amd_prime.c b/tests/amdgpu/amd_prime.c
index 9bf298a41..bda0ce83d 100644
--- a/tests/amdgpu/amd_prime.c
+++ b/tests/amdgpu/amd_prime.c
@@ -392,6 +392,35 @@ static void amd_to_i915(int i915, int amd,
amdgpu_device_handle device)
ib_result_mc_address, 4096);
}
+static void shrink(int i915, int amd, amdgpu_device_handle device)
+{
+ struct amdgpu_bo_alloc_request request = {
+ .alloc_size = 1024 * 1024 * 4,
+ .phys_alignment = 4096,
+ .preferred_heap = AMDGPU_GEM_DOMAIN_GTT,
+ };
+ amdgpu_bo_handle bo;
+ uint32_t handle;
+ int dmabuf;
+
+ igt_assert_eq(amdgpu_bo_alloc(device, , ), 0);
+ amdgpu_bo_export(bo,
+amdgpu_bo_handle_type_dma_buf_fd,
+(uint32_t *));
+ amdgpu_bo_free(bo);
+
+ handle = prime_fd_to_handle(i915, dmabuf);
+ close(dmabuf);
+
+ /* Populate the i915_bo->pages. */
+ gem_set_domain(i915, handle, I915_GEM_DOMAIN_GTT, 0);
+
+ /* Now evict them, establishing the link from i915:shrinker to amd. */
+ igt_drop_caches_set(i915, DROP_SHRINK_ALL);
+
+ gem_close(i915, handle);
+}
+
igt_main
{
amdgpu_device_handle device;
@@ -420,6 +449,9 @@ igt_main
igt_subtest("amd-to-i915")
amd_to_i915(i915, amd, device);
+ igt_subtest("shrink")
+ shrink(i915, amd, device);
+
igt_fixture {
amdgpu_device_deinitialize(device);
close(amd);
Well, I am not familiar with the admgpu API, but it looks believable and
knowing you got a Hades Canyon I trust it works.
Acked-by: Tvrtko Ursulin
Regards,
Tvrtko
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t] igt/gem_eio: Preserve batch between reset-stress iterations
Quoting Tvrtko Ursulin (2018-08-08 13:38:53)
>
> On 08/08/2018 12:31, Chris Wilson wrote:
> > We can keep the original batch around and avoid recreating it between
> > reset iterations to focus on the impact of resets.
> >
> > Signed-off-by: Chris Wilson
> > Cc: Tvrtko Ursulin
> > ---
> > tests/gem_eio.c | 30 +-
> > 1 file changed, 17 insertions(+), 13 deletions(-)
> >
> > diff --git a/tests/gem_eio.c b/tests/gem_eio.c
> > index de161332d..5250a414c 100644
> > --- a/tests/gem_eio.c
> > +++ b/tests/gem_eio.c
> > @@ -650,35 +650,38 @@ static void reset_stress(int fd,
> >uint32_t ctx0, unsigned int engine,
> >unsigned int flags)
> > {
> > + const uint32_t bbe = MI_BATCH_BUFFER_END;
> > + struct drm_i915_gem_exec_object2 obj = {
> > + .handle = gem_create(fd, 4096)
> > + };
> > + struct drm_i915_gem_execbuffer2 execbuf = {
> > + .buffers_ptr = to_user_pointer(),
> > + .buffer_count = 1,
> > + .flags = engine,
> > + };
> > + gem_write(fd, obj.handle, 0, , sizeof(bbe));
> > +
> > igt_until_timeout(5) {
> > - struct drm_i915_gem_execbuffer2 execbuf = { };
> > - struct drm_i915_gem_exec_object2 obj = { };
> > - uint32_t bbe = MI_BATCH_BUFFER_END;
> > + uint32_t ctx = context_create_safe(fd);
>
> There is still this per loop...
I thought that was intentional :)
It felt like the spirit of the test to try and mix up the contexts as
much as possible; one constant, one fresh.
> > igt_spin_t *hang;
> > unsigned int i;
> > - uint32_t ctx;
> >
> > gem_quiescent_gpu(fd);
> >
> > igt_require(i915_reset_control(flags & TEST_WEDGE ?
> > false : true));
> >
> > - ctx = context_create_safe(fd);
> > -
> > /*
> >* Start executing a spin batch with some queued batches
> >* against a different context after it.
> >*/
> > hang = spin_sync(fd, ctx0, engine);
>
> ... and a ton of operations in this one, so I wonder why bother with one
> batch?
Because I don't have spin_sync() in my pattern recognition matrix yet.
One excuse is that it doesn't have any create verb in its name, so easy
to forget its hidden costs.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] igt/prime_vgem: Ask the shrinker to purge a vgem bo from inside i915
On 07/08/2018 16:44, Chris Wilson wrote:
Link a vgem dmabuf into an i915 bo and then ask the i915 shrinker to
purge/invalidate its pages. This should establish the lockdep link from
the fs_reclaim shrinker section to whatever locks are used to
acquire/release dmabuf mappings; if any are required ofc.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Daniel Vetter
---
tests/prime_vgem.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/tests/prime_vgem.c b/tests/prime_vgem.c
index d886044a4..3b3dcc910 100644
--- a/tests/prime_vgem.c
+++ b/tests/prime_vgem.c
@@ -237,6 +237,32 @@ static void test_gtt(int vgem, int i915)
gem_close(vgem, scratch.handle);
}
+static void test_shrink(int vgem, int i915)
+{
+ struct vgem_bo scratch = {
+ .width = 1024,
+ .height = 1024,
+ .bpp = 32
+ };
+ int dmabuf;
+
+ vgem_create(vgem, );
+
+ dmabuf = prime_handle_to_fd(vgem, scratch.handle);
+ gem_close(vgem, scratch.handle);
+
+ scratch.handle = prime_fd_to_handle(i915, dmabuf);
+ close(dmabuf);
+
+ /* Populate the i915_bo->pages. */
+ gem_set_domain(i915, scratch.handle, I915_GEM_DOMAIN_GTT, 0);
+
+ /* Now evict them, establising the link from i915:shrinker to vgem. */
+ igt_drop_caches_set(i915, DROP_SHRINK_ALL);
+
+ gem_close(i915, scratch.handle);
+}
+
static bool is_coherent(int i915)
{
int val = 1; /* by default, we assume GTT is coherent, hence the test */
@@ -794,6 +820,9 @@ igt_main
igt_subtest("basic-gtt")
test_gtt(vgem, i915);
+ igt_subtest("shrink")
+ test_shrink(vgem, i915);
+
igt_subtest("coherency-gtt")
test_gtt_interleaved(vgem, i915);
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/tracepoints: Remove DRM_I915_LOW_LEVEL_TRACEPOINTS Kconfig option
Quoting Tvrtko Ursulin (2018-08-08 13:13:08) > > On 26/06/2018 12:48, Chris Wilson wrote: > > It's just that this about the third time this has been raised in the > > last couple of weeks with the other two requests being from a generic > > tooling pov (Eric Anholt for gnome-shell tweaking, and some one > > else looking for a gpuvis-like tool). So it seems like there is > > interest, even if I doubt that it'll help answer any questions beyond > > what you can just extract from looking at userspace. (Imo, the only > > people these tracepoints are useful for are people writing patches for > > the driver. For everyone else, you can just observe system behaviour and > > optimise your code for your workload. Otoh, can one trust a black > > box, argh.) > > Some of the things might be obtainable purely from userspace via heavily > instrumented builds, which may be in the realm of possible for during > development, but I don't think it is feasible in general both because it > is too involved, and because it would preclude existence of tools which > can trace any random client. > > > To have a second set of nearly equivalent tracepoints, we need to have > > strong justification why we couldn't just use or extend the generic set. > > I was hoping that the conversation so far established that nearly > equivalent is not close enough for intended use cases. And that is not > possible to make the generic ones so. (I just don't see the point of those use cases. I trace the kernel to fix the kernel...) > > Plus I feel a lot more comfortable exporting a set of generic > > tracepoints, than those where we may be leaking more knowledge of the HW > > than we can reasonably expect to support for the indefinite future. > > I think it is accepted we cannot guarantee low level tracepoints will be > supportable in the future world of GuC scheduling. (How and what we will > do there is yet unresolved.) But at least we get much better usability > for platforms up to there, and for very small effort. The idea is not to > mark these as ABI but just improve user experience. > > You are I suppose worried that if these tracepoints disappeared due > being un-implementable someone will complain? They already do... > I just want that anyone can run trace.pl and see how virtual engine > behaves, without having to recompile the kernel. And VTune people want > the same for their enterprise-level customers. Both tools are ready to > adapt should it be required. Its I repeat just usability and user > experience out of the box. The out-of-the-box user experience should not require the use of such tools in the first place! If they are trying to work around the kernel (and that's the only use of this information I see) we have bugs a plenty. [snip because I repeated myself] I think my issues boil down to: 1 - people will complain no matter what (when it changes, when it is no longer available) 2 - people will use it to workaround not fix; the information about kernel behaviour should only be used with a view to fixing that behaviour As such, I am quite happy to have it limited to driver developers that want to fix issues at source (OpenCL, I'm looking at you). There's tons of other user observable information out there for tuning userspace, why does the latency of runnable->queued matter if you will not do anything about it? Other things like dependency graphs, if you can't keep control of your own fences, you've already lost. I don't see any value in giving the information away, just the cost. If you can convince Joonas of its merit, and if we can define just exactly what ABI it constitutes, then I'd be happy to be the one who says "I told you so" in the future for a change. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for ICL DSI CMD MODE
== Series Details == Series: ICL DSI CMD MODE URL : https://patchwork.freedesktop.org/series/47885/ State : failure == Summary == Applying: drm/i915/icl: Define utility pin ctrl register bits Applying: drm/i915/icl: Config utility pin for DSI error: sha1 information is lacking or useless (drivers/gpu/drm/i915/icl_dsi.c). error: could not build fake ancestor Patch failed at 0002 drm/i915/icl: Config utility pin for DSI Use 'git am --show-current-patch' to see the failed patch When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915: Priority boost for new clients
On 07/08/2018 16:02, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-08-07 10:08:28)
On 07/08/2018 08:29, Chris Wilson wrote:
+ /*
+ * The active request is now effectively the start of a new client
+ * stream, so give it the equivalent small priority bump to prevent
+ * it being gazumped a second time by another peer.
+ */
+ if (!(prio & I915_PRIORITY_NEWCLIENT)) {
+ list_move_tail(>sched.link,
+lookup_priolist(engine,
+prio | I915_PRIORITY_NEWCLIENT));
}
}
This sounds fair, I think I'm okay with it. Does it still work well for
mixed media workloads?
Grr. Current drm-tip is scoring much much higher in fairness than I
remember, and there's no apparent improvement, even little room for
possible improvement. When in doubt, blame ksoftirqd ;)
Perhaps previous testing was before direct submission?
Quite surprising though, it was (at least if memory serves) a dramatic
improvement from this patch. Time to see if the metrics do resemble what
I think they should be, and to see if I can find a good example in
media-bench.pl
I should maybe rename it to wsim-bench.pl with a switch to select
workload groups per directory or something..
Regards,
Tvrtko
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t] igt/gem_eio: Preserve batch between reset-stress iterations
On 08/08/2018 12:31, Chris Wilson wrote:
We can keep the original batch around and avoid recreating it between
reset iterations to focus on the impact of resets.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
tests/gem_eio.c | 30 +-
1 file changed, 17 insertions(+), 13 deletions(-)
diff --git a/tests/gem_eio.c b/tests/gem_eio.c
index de161332d..5250a414c 100644
--- a/tests/gem_eio.c
+++ b/tests/gem_eio.c
@@ -650,35 +650,38 @@ static void reset_stress(int fd,
uint32_t ctx0, unsigned int engine,
unsigned int flags)
{
+ const uint32_t bbe = MI_BATCH_BUFFER_END;
+ struct drm_i915_gem_exec_object2 obj = {
+ .handle = gem_create(fd, 4096)
+ };
+ struct drm_i915_gem_execbuffer2 execbuf = {
+ .buffers_ptr = to_user_pointer(),
+ .buffer_count = 1,
+ .flags = engine,
+ };
+ gem_write(fd, obj.handle, 0, , sizeof(bbe));
+
igt_until_timeout(5) {
- struct drm_i915_gem_execbuffer2 execbuf = { };
- struct drm_i915_gem_exec_object2 obj = { };
- uint32_t bbe = MI_BATCH_BUFFER_END;
+ uint32_t ctx = context_create_safe(fd);
There is still this per loop...
igt_spin_t *hang;
unsigned int i;
- uint32_t ctx;
gem_quiescent_gpu(fd);
igt_require(i915_reset_control(flags & TEST_WEDGE ?
false : true));
- ctx = context_create_safe(fd);
-
/*
* Start executing a spin batch with some queued batches
* against a different context after it.
*/
hang = spin_sync(fd, ctx0, engine);
... and a ton of operations in this one, so I wonder why bother with one
batch?
- obj.handle = gem_create(fd, 4096);
- gem_write(fd, obj.handle, 0, , sizeof(bbe));
+ execbuf.rsvd1 = ctx;
+ for (i = 0; i < 10; i++)
+ gem_execbuf(fd, );
- execbuf.buffers_ptr = to_user_pointer();
- execbuf.buffer_count = 1;
execbuf.rsvd1 = ctx0;
- execbuf.flags = engine;
-
for (i = 0; i < 10; i++)
gem_execbuf(fd, );
@@ -706,8 +709,9 @@ static void reset_stress(int fd,
gem_sync(fd, obj.handle);
igt_spin_batch_free(fd, hang);
gem_context_destroy(fd, ctx);
- gem_close(fd, obj.handle);
}
+
+ gem_close(fd, obj.handle);
}
/*
But anyway - no technical complaints:
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 07/12] drm/i915/icl: Configure TE interrupts for DSI
This patch implements a helper function for enabling
or disabling TE interrupts.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/icl_dsi.c | 20
drivers/gpu/drm/i915/intel_drv.h | 2 ++
2 files changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index bf7ad5e..0ae62a1 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -46,6 +46,26 @@ struct intel_encoder *gen11_dsi_find_cmd_mode_encoder(struct
intel_crtc *crtc)
return NULL;
}
+void gen11_dsi_configure_te_interrupt(struct intel_encoder *encoder,
+ bool enable)
+{
+ struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
+ u32 tmp;
+ enum port port;
+
+ for_each_dsi_port(port, intel_dsi->ports) {
+ tmp = I915_READ(GEN8_DE_PORT_IMR);
+ if (enable)
+ tmp |= (port == PORT_A ? ICL_DSI0_TE : ICL_DSI1_TE);
+ else
+ tmp &= (port == PORT_A ? ~ICL_DSI0_TE : ~ICL_DSI1_TE);
+
+ I915_WRITE(GEN8_DE_PORT_IMR, tmp);
+ POSTING_READ(GEN8_DE_PORT_IMR);
+ }
+}
+
static void wait_for_dsi_hdr_credit_release(struct intel_dsi *intel_dsi,
enum transcoder dsi_trans)
{
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 7dadfc1..e39f812 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1757,6 +1757,8 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv);
/* icl_dsi.c */
void intel_gen11_dsi_init(struct drm_i915_private *dev_priv);
struct intel_encoder *gen11_dsi_find_cmd_mode_encoder(struct intel_crtc *crtc);
+void gen11_dsi_configure_te_interrupt(struct intel_encoder *encoder,
+ bool enable);
/* intel_dsi_dcs_backlight.c */
int intel_dsi_dcs_init_backlight_funcs(struct intel_connector
*intel_connector);
--
2.7.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 08/12] drm/i915/icl: Enable/disable TE interrupts
If DSI is operating in command mode, then display
engine won't be receiving VBLANK interrupt instead
of that Tearing Event(TE) interrupt will be received.
So in this scenario, we need to enable/disable TE interrupt
rather than VBLANK interrupts.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_irq.c | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 5dadefc..a24c670 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3398,10 +3398,18 @@ static int ironlake_enable_vblank(struct drm_device
*dev, unsigned int pipe)
static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe)
{
struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
+ struct intel_encoder *encoder;
unsigned long irqflags;
spin_lock_irqsave(_priv->irq_lock, irqflags);
- bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
+ encoder = gen11_dsi_find_cmd_mode_encoder(crtc);
+
+ if (IS_ICELAKE(dev_priv) && encoder)
+ gen11_dsi_configure_te_interrupt(encoder, true);
+ else
+ bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
+
spin_unlock_irqrestore(_priv->irq_lock, irqflags);
/* Even if there is no DMC, frame counter can get stuck when
@@ -3452,10 +3460,18 @@ static void ironlake_disable_vblank(struct drm_device
*dev, unsigned int pipe)
static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
{
struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
+ struct intel_encoder *encoder;
unsigned long irqflags;
spin_lock_irqsave(_priv->irq_lock, irqflags);
- bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
+ encoder = gen11_dsi_find_cmd_mode_encoder(crtc);
+
+ if (IS_ICELAKE(dev_priv) && encoder)
+ gen11_dsi_configure_te_interrupt(encoder, false);
+ else
+ bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
+
spin_unlock_irqrestore(_priv->irq_lock, irqflags);
}
--
2.7.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 12/12] drm/i915/icl: Transcoder timings for command mode
This patch calculate HOTAL and VTOTAL value to be programmed
when DSI is operating in command mode as per BSPEC.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/icl_dsi.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index af72b57..c93d02c 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -811,6 +811,12 @@ static void gen11_dsi_set_transcoder_timings(struct
intel_encoder *encoder,
htotal /= 2;
}
+ if (intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE) {
+ htotal = hactive + 160;
+ //TODO: Calculate VTOTAL = ceiling( 400us / Line Time)
+ //Info missing from BSPEC
+ }
+
/* minimum hactive as per bspec: 256 pixels */
if (adjusted_mode->crtc_hdisplay < 256)
DRM_ERROR("hactive is less then 256 pixels\n");
--
2.7.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 11/12] drm/i915/icl: Send frame to DSI panel
In DSI command mode, for sending the frame to panel
DSI controller need to issue the command unlike in
DSI video mode. This patch does the same.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/icl_dsi.c | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index bd3cdde..af72b57 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -117,6 +117,23 @@ static void gen11_dsi_clear_te_interrupt(struct
intel_encoder *encoder)
}
+static void gen11_dsi_initiate_frame_req(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
+ u32 tmp;
+ enum port port;
+ enum transcoder dsi_trans;
+
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+ tmp = I915_READ(DSI_CMD_FRMCTL(dsi_trans));
+ tmp |= PERIODIC_FRAME_UPDATE_ENABLE;
+ I915_WRITE(DSI_CMD_FRMCTL(dsi_trans), tmp);
+ }
+
+}
+
static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -900,6 +917,9 @@ static void gen11_dsi_enable_transcoder(struct
intel_encoder *encoder)
I965_PIPECONF_ACTIVE, 10))
DRM_ERROR("DSI transcoder not enabled\n");
}
+
+ /* For command mode, send a frame to panel */
+ gen11_dsi_initiate_frame_req(encoder);
}
static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder)
--
2.7.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 10/12] drm/i915/icl: Unmask/Clear DSI TE interrupts
While enabling DSI transcoder, TE interrupts need to
be unmasked also they need to be cleared when TE interrupts
are received. This patch does same by programming DSI interrupt
specific registers.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_irq.c | 2 ++
drivers/gpu/drm/i915/icl_dsi.c | 34 ++
2 files changed, 36 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 8ca2396..b1e836a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1897,6 +1897,8 @@ void gen11_dsi_te_interrupt_handler(struct
drm_i915_private *dev_priv,
DRM_ERROR("Invalid PIPE\n");
}
+ //TODO: Clear DSI interrupt here
+
drm_handle_vblank(_priv->drm, pipe);
}
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 0ae62a1..bd3cdde 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -66,6 +66,7 @@ void gen11_dsi_configure_te_interrupt(struct intel_encoder
*encoder,
}
}
+
static void wait_for_dsi_hdr_credit_release(struct intel_dsi *intel_dsi,
enum transcoder dsi_trans)
{
@@ -96,6 +97,26 @@ static enum transcoder dsi_port_to_transcoder(enum port port)
return TRANSCODER_DSI_1;
}
+static void gen11_dsi_clear_te_interrupt(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
+ u32 tmp;
+ enum port port;
+ enum transcoder dsi_trans;
+
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+ tmp = I915_READ(DSI_INTR_IDENT_REG(dsi_trans));
+ if (tmp & TE_EVENT) {
+ /* TE event received, clear it */
+ tmp |= TE_EVENT;
+ I915_WRITE(DSI_INTR_IDENT_REG(dsi_trans), tmp);
+ }
+ }
+
+}
+
static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -666,11 +687,24 @@ static void gen11_dsi_configure_transcoder(struct
intel_encoder *encoder,
tmp &= ~OP_MODE_MASK;
tmp |= OP_MODE(CMD_MODE_TE_GATE);
tmp |= TE_SOURCE_GPIO;
+
}
I915_WRITE(DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
}
+ if (intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE) {
+
+ /* unmask and clear DSI TE interrupt */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+ tmp = I915_READ(DSI_INTR_MASK_REG(dsi_trans));
+ tmp &= ~TE_EVENT;
+ I915_WRITE(DSI_INTR_MASK_REG(dsi_trans), tmp);
+ }
+ gen11_dsi_clear_te_interrupt(encoder);
+ }
+
/* enable port sync mode if dual link */
if (intel_dsi->dual_link) {
for_each_dsi_port(port, intel_dsi->ports) {
--
2.7.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
