Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for Load DMC v1.07 on Icelake (rev2)
Hi,
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Patchwork
> Sent: tiistai 28. elokuuta 2018 4.10
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] ✗ Fi.CI.BAT: failure for Load DMC v1.07 on Icelake (rev2)
>
> == Series Details ==
>
> Series: Load DMC v1.07 on Icelake (rev2)
> URL : https://patchwork.freedesktop.org/series/48773/
> State : failure
>
> == Summary ==
>
> = CI Bug Log - changes from CI_DRM_4713 -> Patchwork_10025 =
>
> == Summary - FAILURE ==
>
> Serious unknown changes coming with Patchwork_10025 absolutely need to
> be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_10025, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL:
> https://patchwork.freedesktop.org/api/1.0/series/48773/revisions/2/mbox/
>
> == Possible new issues ==
>
> Here are the unknown changes that may have been introduced in
> Patchwork_10025:
>
> === IGT changes ===
>
> Possible regressions
>
> igt@drv_module_reload@basic-reload:
> {fi-icl-u}: PASS -> DMESG-WARN +16
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10025/fi-icl-u/igt@drv_module_rel...@basic-reload.html
Dmesg
[ 395.430440] [drm:csr_load_work_fn [i915]] *ERROR* DMC firmware has wrong
dmc header length (1 bytes)
[ 395.430515] i915 :00:02.0: Failed to load DMC firmware
i915/icl_dmc_ver1_07.bin. Disabling runtime power management.
[ 395.430518] i915 :00:02.0: DMC firmware homepage:
https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/tree/i915
[ 396.682262] Setting dangerous option reset - tainting kernel
Sound like issue...Imre?
>
> igt@gem_exec_suspend@basic-s4-devices:
> fi-blb-e6850: PASS -> INCOMPLETE
>
>
> == Known issues ==
>
> Here are the changes found in Patchwork_10025 that come from known
> issues:
>
> === IGT changes ===
>
> Issues hit
>
> igt@drv_selftest@live_hangcheck:
> fi-skl-6700hq: PASS -> DMESG-FAIL (fdo#106560, fdo#107174)
>
> igt@kms_chamelium@dp-edid-read:
> fi-kbl-7500u: PASS -> FAIL (fdo#103841)
>
> igt@kms_frontbuffer_tracking@basic:
> {fi-byt-clapper}: PASS -> FAIL (fdo#103167)
>
> igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b:
> {fi-byt-clapper}: PASS -> FAIL (fdo#107362)
>
> {igt@kms_psr@primary_page_flip}:
> fi-cnl-psr: PASS -> FAIL (fdo#107336)
>
> igt@pm_rpm@basic-pci-d3-state:
> fi-glk-dsi: PASS -> INCOMPLETE (k.org#198133, fdo#103359)
>
> {igt@pm_rpm@module-reload}:
> fi-cnl-psr: PASS -> WARN (fdo#107602)
>
>
> Possible fixes
>
> igt@drv_selftest@live_hangcheck:
> fi-cfl-guc: DMESG-FAIL -> PASS
>
> igt@kms_pipe_crc_basic@read-crc-pipe-b:
> {fi-byt-clapper}: FAIL (fdo#107362) -> PASS
>
> igt@pm_rpm@basic-pci-d3-state:
> fi-skl-6770hq: WARN -> PASS +1
>
>
> {name}: This element is suppressed. This means it is ignored when
> computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
> fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
> fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
> fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
> fdo#107174 https://bugs.freedesktop.org/show_bug.cgi?id=107174
> fdo#107336 https://bugs.freedesktop.org/show_bug.cgi?id=107336
> fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
> fdo#107602 https://bugs.freedesktop.org/show_bug.cgi?id=107602
> k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133
>
>
> == Participating hosts (54 -> 49) ==
>
> Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-
> 4200u
>
>
> == Build changes ==
>
> * Linux: CI_DRM_4713 -> Patchwork_10025
>
> CI_DRM_4713: 9261175f56a1b035b9db12e959ba2e8c756924a6 @
> git://anongit.freedesktop.org/gfx-ci/linux
> IGT_4610: c40743d3fce5055682d31610519758dd7379c0f8 @
> git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> Patchwork_10025: 0b098dc6cfb59c4634719f51ea690ad133639f5e @
> git://anongit.freedesktop.org/gfx-ci/linux
>
>
> == Linux commits ==
>
> 0b098dc6cfb5 firmware/dmc/icl: load v1.07 on icelake.
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-
> tip/Patchwork_10025/issues.html
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v2] drm/i915: Clean up skl_plane_has_planar() (rev2)
== Series Details == Series: series starting with [v2] drm/i915: Clean up skl_plane_has_planar() (rev2) URL : https://patchwork.freedesktop.org/series/48687/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4713_full -> Patchwork_10024_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_10024_full that come from known issues: === IGT changes === Issues hit igt@drv_suspend@debugfs-reader: shard-apl: PASS -> INCOMPLETE (fdo#103927) igt@kms_flip@flip-vs-expired-vblank-interruptible: shard-glk: PASS -> FAIL (fdo#102887, fdo#105363) igt@kms_setmode@basic: shard-apl: PASS -> FAIL (fdo#99912) Possible fixes igt@drv_selftest@live_hangcheck: shard-kbl: DMESG-FAIL (fdo#106560, fdo#106947) -> PASS igt@drv_suspend@shrink: shard-glk: INCOMPLETE (k.org#198133, fdo#103359, fdo#106886) -> PASS igt@gem_eio@reset-stress: shard-kbl: FAIL -> PASS igt@gem_exec_await@wide-contexts: shard-kbl: FAIL (fdo#105900) -> PASS igt@gem_ppgtt@blt-vs-render-ctx0: shard-kbl: INCOMPLETE (fdo#103665, fdo#106023) -> PASS fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105900 https://bugs.freedesktop.org/show_bug.cgi?id=105900 fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023 fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560 fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886 fdo#106947 https://bugs.freedesktop.org/show_bug.cgi?id=106947 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4713 -> Patchwork_10024 CI_DRM_4713: 9261175f56a1b035b9db12e959ba2e8c756924a6 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4610: c40743d3fce5055682d31610519758dd7379c0f8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10024: 3bed945859e3c28fb1257c7d2cecae5121e60d8d @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10024/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for Load DMC v1.07 on Icelake (rev2)
== Series Details ==
Series: Load DMC v1.07 on Icelake (rev2)
URL : https://patchwork.freedesktop.org/series/48773/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4713 -> Patchwork_10025 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_10025 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10025, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/48773/revisions/2/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_10025:
=== IGT changes ===
Possible regressions
igt@drv_module_reload@basic-reload:
{fi-icl-u}: PASS -> DMESG-WARN +16
igt@gem_exec_suspend@basic-s4-devices:
fi-blb-e6850: PASS -> INCOMPLETE
== Known issues ==
Here are the changes found in Patchwork_10025 that come from known issues:
=== IGT changes ===
Issues hit
igt@drv_selftest@live_hangcheck:
fi-skl-6700hq: PASS -> DMESG-FAIL (fdo#106560, fdo#107174)
igt@kms_chamelium@dp-edid-read:
fi-kbl-7500u: PASS -> FAIL (fdo#103841)
igt@kms_frontbuffer_tracking@basic:
{fi-byt-clapper}: PASS -> FAIL (fdo#103167)
igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b:
{fi-byt-clapper}: PASS -> FAIL (fdo#107362)
{igt@kms_psr@primary_page_flip}:
fi-cnl-psr: PASS -> FAIL (fdo#107336)
igt@pm_rpm@basic-pci-d3-state:
fi-glk-dsi: PASS -> INCOMPLETE (k.org#198133, fdo#103359)
{igt@pm_rpm@module-reload}:
fi-cnl-psr: PASS -> WARN (fdo#107602)
Possible fixes
igt@drv_selftest@live_hangcheck:
fi-cfl-guc: DMESG-FAIL -> PASS
igt@kms_pipe_crc_basic@read-crc-pipe-b:
{fi-byt-clapper}: FAIL (fdo#107362) -> PASS
igt@pm_rpm@basic-pci-d3-state:
fi-skl-6770hq: WARN -> PASS +1
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
fdo#107174 https://bugs.freedesktop.org/show_bug.cgi?id=107174
fdo#107336 https://bugs.freedesktop.org/show_bug.cgi?id=107336
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107602 https://bugs.freedesktop.org/show_bug.cgi?id=107602
k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133
== Participating hosts (54 -> 49) ==
Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4713 -> Patchwork_10025
CI_DRM_4713: 9261175f56a1b035b9db12e959ba2e8c756924a6 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4610: c40743d3fce5055682d31610519758dd7379c0f8 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10025: 0b098dc6cfb59c4634719f51ea690ad133639f5e @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
0b098dc6cfb5 firmware/dmc/icl: load v1.07 on icelake.
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10025/issues.html
___
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Re: [Intel-gfx] [PATCH libdrm 1/4] intel: add IS_GENX() generic macro
On Sat, Aug 25, 2018 at 10:35:23AM +0100, Chris Wilson wrote:
> Quoting Lucas De Marchi (2018-08-25 00:56:46)
> > diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
> > index 4a34b7be..8a0e3e76 100644
> > --- a/intel/intel_chipset.h
> > +++ b/intel/intel_chipset.h
> > @@ -568,6 +568,26 @@
> >
> > #define IS_GEN11(devid)(IS_ICELAKE_11(devid))
> >
> > +/* New platforms use kernel pci ids */
> > +#include "i915_pciids.h"
> > +
> > +struct pci_device_id {
>
> Don't call it pci_device_id, depending on caller that name may already
> be taken by libpciaccess.
>
> > + uint32_t unused0, device;
> > + uint32_t unused1, unused2;
> > + uint32_t unused3, unused4;
> These are all uint16_t.
more on this:
I can make the first 2 uint16_t, but not the rest due to the way they
are declared in INTEL_VGA_DEVICE: (~0 has int type by default), unused3
and unused4 are clearly not uint16_t
>
> > + unsigned long unused5;
>
> Simply make the unused disappear from the macro.
that would mean defining macro hackery to get hid of them from
INTEL_VGA_DEVICE() by using macro recursion, but not worth IMO. If we
want to go this route, then I think we should at least use X Macro
to define the ids rather than the list we currently have. Something
along the lines (in i915_pciids.h):
#define _INTEL_ICL_IDS \
X(0x8A50) \
X(0x8A51) \
X(0x8A5C) \
X(0x8A5D) \
X(0x8A52) \
X(0x8A5A) \
X(0x8A5B) \
X(0x8A71) \
X(0x8A70)
...
#define X(id, info) INTEL_VGA_DEVICE(id, info),
#define INTEL_ICL_IDS(info) _INTEL_ICL_IDS
#undef X
Then here we would just define another X to transform the list into an
array:
#include "i915_pciids.h"
...
#define X(id, gen) { id, gen }
struct pci_device {
uint16_t id;
uint16_t gen;
} devices = {
_INTEL_ICL_IDS
}
We would be screwed if X is defined to something else, but we could change
the name.
Lucas De Marchi
>
> > +};
> > +
> > +#define IS_GENX(x, devid) ({ \
> > + struct pci_device_id __ids[] = { INTEL_ ## x ## _IDS(0) }; \
>
> While that's a neat trick it's instantiating the array for each caller,
> and it does appear that we repeat a few of the macros.
>
> The best I can offer to keep the change non-invasive (other than just
> switching to a platform bitmask and filling (devid, gen, platform) from
> the pci match data on initialisation) is a two pass approach.
>
> static inline int __find_in_pciid(uint16_t devid,
> const struct pci_device_id *ids, size_t count)
> {
> size_t i = 0; /* we should rethink this if we think there are more than
> 4B of them! */
> for (i = 0; i < count; i++) {
> if (ids[i].device == devid)
> return 1;
> }
> return 0;
> }
>
>
> #define __is_genx(x) \
> static inline int __is_gen##x(uint16_t devid) \
> { \
> static const struct pci_device_id __ids[] = { INTEL_ ## x ## _IDS(0) };
> \
> return __find_in_pciid(devid, __ids, sizeof(__ids)/sizeof(__ids[0]); \
> }
> __is_genx(3);
> __is_genx(4);
> __is_genx(5);
> __is_genx(6);
> __is_genx(7);
> __is_genx(8);
> __is_genx(9);
> __is_genx(10);
> __is_genx(11);
>
> #define IS_GENX(x, devid) __is_gen##x(devid)
>
> That should help cut down the object size expansion. But longer term I'd
> prefer if we moved to towards finding the match data once. Also we need
> to pull into the canonical header the friendly names for mesa.
> -Chris
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[Intel-gfx] [PATCH 1/1] firmware/dmc/icl: load v1.07 on icelake.
Add Support to load DMC on Icelake.
While at it, also add support to load the firmware
during system resume.
v2: load firmware during system resume.(Imre)
v3: enable has_csr for icelake.(Jyoti)
v4: Only load the firmware in this patch
Cc: Jyoti Yadav
Cc: Imre Deak
Cc: Rodrigo Vivi
Cc: Paulo Zanoni
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_csr.c| 7 +++
drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +++
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index 1ec4f09c61f6..6d9d47322405 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -34,6 +34,9 @@
* low-power state and comes back to normal.
*/
+#define I915_CSR_ICL "i915/icl_dmc_ver1_07.bin"
+#define ICL_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
+
#define I915_CSR_GLK "i915/glk_dmc_ver1_04.bin"
MODULE_FIRMWARE(I915_CSR_GLK);
#define GLK_CSR_VERSION_REQUIRED CSR_VERSION(1, 4)
@@ -301,6 +304,8 @@ static uint32_t *parse_csr_fw(struct drm_i915_private
*dev_priv,
if (csr->fw_path == i915_modparams.dmc_firmware_path) {
/* Bypass version check for firmware override. */
required_version = csr->version;
+ } else if (IS_ICELAKE(dev_priv)) {
+ required_version = ICL_CSR_VERSION_REQUIRED;
} else if (IS_CANNONLAKE(dev_priv)) {
required_version = CNL_CSR_VERSION_REQUIRED;
} else if (IS_GEMINILAKE(dev_priv)) {
@@ -458,6 +463,8 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
if (i915_modparams.dmc_firmware_path)
csr->fw_path = i915_modparams.dmc_firmware_path;
+ else if (IS_ICELAKE(dev_priv))
+ csr->fw_path = I915_CSR_ICL;
else if (IS_CANNONLAKE(dev_priv))
csr->fw_path = I915_CSR_CNL;
else if (IS_GEMINILAKE(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 2852395125cd..bd7da068e813 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -3563,6 +3563,9 @@ static void icl_display_core_init(struct drm_i915_private
*dev_priv,
/* 7. Setup MBUS. */
icl_mbus_init(dev_priv);
+
+ if (resume && dev_priv->csr.dmc_payload)
+ intel_csr_load_program(dev_priv);
}
static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
--
2.17.1
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[Intel-gfx] [PATCH 0/1] Load DMC v1.07 on Icelake
Adding PR for CI to pick: The following changes since commit fea76a04f25fd0a217c0d566ff5ff8f23ad3e648: amdgpu: sync up polaris10 firmware with 18.30 release (2018-08-25 15:43:50 -0400) are available in the git repository at: git://anongit.freedesktop.org/git/drm/drm-firmware.git/ master for you to fetch changes up to 50364020f96f8deb075830d9992899ba3a7babc7: Merge remote-tracking branch 'official/master' (2018-08-27 17:24:49 -0700) Anusha Srivatsa (7): Merge remote-tracking branch 'official/master' into drm-firmware linux-firmware: Add GuC v11.98 for geminilake linux-firmware: Add HuC v3.00.2225 for geminilake firmware/icl/dmc: Add DMC v1.07 for Icelake. Revert "firmware/icl/dmc: Add DMC v1.05 for Icelake." Fix commit. Merge remote-tracking branch 'official/master' WHENCE | 9 + i915/glk_guc_ver11_98.bin | Bin 0 -> 154240 bytes i915/glk_huc_ver03_00_2225.bin | Bin 0 -> 220032 bytes i915/icl_dmc_ver1_07.bin | Bin 0 -> 25716 bytes 4 files changed, 9 insertions(+) create mode 100644 i915/glk_guc_ver11_98.bin create mode 100644 i915/glk_huc_ver03_00_2225.bin create mode 100644 i915/icl_dmc_ver1_07.bin Anusha Srivatsa (1): firmware/dmc/icl: load v1.07 on icelake. drivers/gpu/drm/i915/intel_csr.c| 7 +++ drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +++ 2 files changed, 10 insertions(+) -- 2.17.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/4] drm/dp_mst: Pass entire connector to drm_dp_mst_topology_mgr_init()
There's no actual reason we pass the connector ID instead of a pointer
to the connector itself, and we're going to need the entire connector
(but only temporarily) in order to name MST debugfs folders properly
since connector IDs can't be looked up until the driver has been
registered with userspace which happens after debugfs init.
So, just pass the entire drm_connector struct instead of just it's id.
Signed-off-by: Lyude Paul
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +-
drivers/gpu/drm/drm_dp_mst_topology.c | 8 +---
drivers/gpu/drm/i915/intel_dp.c | 2 +-
drivers/gpu/drm/i915/intel_dp_mst.c | 6 --
drivers/gpu/drm/i915/intel_drv.h | 3 ++-
drivers/gpu/drm/nouveau/dispnv50/disp.c | 6 +++---
drivers/gpu/drm/radeon/radeon_dp_mst.c| 2 +-
include/drm/drm_dp_mst_helper.h | 3 ++-
8 files changed, 19 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 9a300732ba37..60da7e8fcca7 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -503,6 +503,6 @@ void amdgpu_dm_initialize_dp_connector(struct
amdgpu_display_manager *dm,
>dm_dp_aux.aux,
16,
4,
- aconnector->connector_id);
+ >base);
}
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
b/drivers/gpu/drm/drm_dp_mst_topology.c
index 7780567aa669..edba17073c7a 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -3166,9 +3166,11 @@ EXPORT_SYMBOL(drm_atomic_get_mst_topology_state);
* Return 0 for success, or negative error code on failure
*/
int drm_dp_mst_topology_mgr_init(struct drm_dp_mst_topology_mgr *mgr,
-struct drm_device *dev, struct drm_dp_aux *aux,
+struct drm_device *dev,
+struct drm_dp_aux *aux,
int max_dpcd_transaction_bytes,
-int max_payloads, int conn_base_id)
+int max_payloads,
+struct drm_connector *connector)
{
struct drm_dp_mst_topology_state *mst_state;
@@ -3186,7 +3188,7 @@ int drm_dp_mst_topology_mgr_init(struct
drm_dp_mst_topology_mgr *mgr,
mgr->aux = aux;
mgr->max_dpcd_transaction_bytes = max_dpcd_transaction_bytes;
mgr->max_payloads = max_payloads;
- mgr->conn_base_id = conn_base_id;
+ mgr->conn_base_id = connector->base.id;
if (max_payloads + 1 > sizeof(mgr->payload_mask) * 8 ||
max_payloads + 1 > sizeof(mgr->vcpi_mask) * 8)
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index cd0f649b57a5..3688df38dbe7 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -6247,7 +6247,7 @@ intel_dp_init_connector(struct intel_digital_port
*intel_dig_port,
(port == PORT_B || port == PORT_C ||
port == PORT_D || port == PORT_F))
intel_dp_mst_encoder_init(intel_dig_port,
- intel_connector->base.base.id);
+ _connector->base);
if (!intel_edp_init_connector(intel_dp, intel_connector)) {
intel_dp_aux_fini(intel_dp);
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
b/drivers/gpu/drm/i915/intel_dp_mst.c
index 7e3e01607643..6c07c29235df 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -583,7 +583,8 @@ intel_dp_create_fake_mst_encoders(struct intel_digital_port
*intel_dig_port)
}
int
-intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int
conn_base_id)
+intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port,
+ struct drm_connector *connector)
{
struct intel_dp *intel_dp = _dig_port->dp;
struct drm_device *dev = intel_dig_port->base.base.dev;
@@ -595,7 +596,8 @@ intel_dp_mst_encoder_init(struct intel_digital_port
*intel_dig_port, int conn_ba
/* create encoders */
intel_dp_create_fake_mst_encoders(intel_dig_port);
ret = drm_dp_mst_topology_mgr_init(_dp->mst_mgr, dev,
- _dp->aux, 16, 3, conn_base_id);
+ _dp->aux, 16, 3,
+ connector);
if (ret) {
intel_dp->can_mst = false;
return ret;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 8fc61e96754f..af7a6111ff74 100644
---
[Intel-gfx] [PATCH 0/4] drm/dp_mst: Add DP MST debugfs nodes for all drivers
This is the next version of my patch series for teaching DRM how to automatically create debugfs nodes for drivers with MST topologies. This was originally intended just for nouveau, but has since been expanded to all DRM drivers. Cc: Maarten Lankhorst Cc: Daniel Stone Lyude Paul (4): drm/debugfs: Add support for dynamic debugfs initialization drm/dp_mst: Pass entire connector to drm_dp_mst_topology_mgr_init() drm/dp_mst: Add dp_mst_status debugfs node for all drivers drm/i915: Remove i915_drm_dp_mst_status .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +- drivers/gpu/drm/drm_debugfs.c | 173 +- drivers/gpu/drm/drm_dp_mst_topology.c | 114 +++- drivers/gpu/drm/drm_drv.c | 3 + drivers/gpu/drm/drm_internal.h| 5 + drivers/gpu/drm/i915/i915_debugfs.c | 32 drivers/gpu/drm/i915/intel_dp.c | 2 +- drivers/gpu/drm/i915/intel_dp_mst.c | 6 +- drivers/gpu/drm/i915/intel_drv.h | 3 +- drivers/gpu/drm/nouveau/dispnv50/disp.c | 6 +- drivers/gpu/drm/radeon/radeon_dp_mst.c| 2 +- include/drm/drm_debugfs.h | 27 +++ include/drm/drm_dp_mst_helper.h | 17 +- include/drm/drm_file.h| 4 + 14 files changed, 342 insertions(+), 54 deletions(-) -- 2.17.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/4] drm/i915: Remove i915_drm_dp_mst_status
Now that DRM can create these debugfs nodes automatically; this isn't
needed.
Signed-off-by: Lyude Paul
Cc: Maarten Lankhorst
Cc: Daniel Stone
---
drivers/gpu/drm/i915/i915_debugfs.c | 32 -
1 file changed, 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index f9ce35da4123..5014828ca022 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3534,37 +3534,6 @@ static int i915_drrs_status(struct seq_file *m, void
*unused)
return 0;
}
-static int i915_dp_mst_info(struct seq_file *m, void *unused)
-{
- struct drm_i915_private *dev_priv = node_to_i915(m->private);
- struct drm_device *dev = _priv->drm;
- struct intel_encoder *intel_encoder;
- struct intel_digital_port *intel_dig_port;
- struct drm_connector *connector;
- struct drm_connector_list_iter conn_iter;
-
- drm_connector_list_iter_begin(dev, _iter);
- drm_for_each_connector_iter(connector, _iter) {
- if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
- continue;
-
- intel_encoder = intel_attached_encoder(connector);
- if (!intel_encoder || intel_encoder->type ==
INTEL_OUTPUT_DP_MST)
- continue;
-
- intel_dig_port = enc_to_dig_port(_encoder->base);
- if (!intel_dig_port->dp.can_mst)
- continue;
-
- seq_printf(m, "MST Source Port %c\n",
- port_name(intel_dig_port->base.port));
- drm_dp_mst_dump_topology(m, _dig_port->dp.mst_mgr);
- }
- drm_connector_list_iter_end(_iter);
-
- return 0;
-}
-
static ssize_t i915_displayport_test_active_write(struct file *file,
const char __user *ubuf,
size_t len, loff_t *offp)
@@ -4733,7 +4702,6 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_rcs_topology", i915_rcs_topology, 0},
{"i915_shrinker_info", i915_shrinker_info, 0},
{"i915_shared_dplls_info", i915_shared_dplls_info, 0},
- {"i915_dp_mst_info", i915_dp_mst_info, 0},
{"i915_wa_registers", i915_wa_registers, 0},
{"i915_ddb_info", i915_ddb_info, 0},
{"i915_sseu_status", i915_sseu_status, 0},
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: ring all doorbells in igt_guc_doorbells
== Series Details ==
Series: drm/i915/selftests: ring all doorbells in igt_guc_doorbells
URL : https://patchwork.freedesktop.org/series/48768/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4712_full -> Patchwork_10023_full =
== Summary - SUCCESS ==
No regressions found.
== Known issues ==
Here are the changes found in Patchwork_10023_full that come from known
issues:
=== IGT changes ===
Issues hit
igt@gem_ppgtt@blt-vs-render-ctx0:
shard-kbl: PASS -> INCOMPLETE (fdo#103665, fdo#106023)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
shard-apl: PASS -> INCOMPLETE (fdo#103927)
Possible fixes
igt@drv_selftest@live_hangcheck:
shard-kbl: DMESG-FAIL (fdo#106947, fdo#106560) -> PASS
{igt@gem_userptr_blits@readonly-unsync}:
shard-apl: INCOMPLETE (fdo#103927) -> PASS
igt@kms_flip@flip-vs-expired-vblank:
shard-glk: FAIL (fdo#105363) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023
fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
fdo#106947 https://bugs.freedesktop.org/show_bug.cgi?id=106947
== Participating hosts (5 -> 5) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_4712 -> Patchwork_10023
CI_DRM_4712: 7b245f2b1e25677a1f2b63fd69003e35731cedda @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4610: c40743d3fce5055682d31610519758dd7379c0f8 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10023: b370a2de90ed24f059085b7482f852e0efc0f1fd @
git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
git://anongit.freedesktop.org/piglit
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10023/shards.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2] drm/i915: Clean up skl_plane_has_planar() (rev2)
== Series Details ==
Series: series starting with [v2] drm/i915: Clean up skl_plane_has_planar()
(rev2)
URL : https://patchwork.freedesktop.org/series/48687/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4713 -> Patchwork_10024 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/48687/revisions/2/mbox/
== Known issues ==
Here are the changes found in Patchwork_10024 that come from known issues:
=== IGT changes ===
Issues hit
{igt@pm_rpm@module-reload}:
fi-cnl-psr: PASS -> WARN (fdo#107602)
Possible fixes
igt@drv_selftest@live_hangcheck:
fi-cfl-guc: DMESG-FAIL -> PASS
fi-cfl-s3: DMESG-FAIL (fdo#106560) -> PASS
igt@kms_pipe_crc_basic@read-crc-pipe-b:
{fi-byt-clapper}: FAIL (fdo#107362) -> PASS +1
igt@pm_rpm@basic-pci-d3-state:
fi-skl-6770hq: WARN -> PASS +1
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107602 https://bugs.freedesktop.org/show_bug.cgi?id=107602
== Participating hosts (54 -> 49) ==
Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4713 -> Patchwork_10024
CI_DRM_4713: 9261175f56a1b035b9db12e959ba2e8c756924a6 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4610: c40743d3fce5055682d31610519758dd7379c0f8 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10024: 3bed945859e3c28fb1257c7d2cecae5121e60d8d @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
3bed945859e3 drm/i915: Do not advertize support for NV12 on ICL yet.
cd298ba950fd drm/i915: Clean up skl_plane_has_planar()
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10024/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: introduce dp_to_i915() helper
== Series Details ==
Series: series starting with [1/2] drm/i915: introduce dp_to_i915() helper
URL : https://patchwork.freedesktop.org/series/48767/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4712_full -> Patchwork_10022_full =
== Summary - SUCCESS ==
No regressions found.
== Known issues ==
Here are the changes found in Patchwork_10022_full that come from known
issues:
=== IGT changes ===
Issues hit
igt@drv_suspend@shrink:
shard-glk: PASS -> INCOMPLETE (fdo#106886, k.org#198133,
fdo#103359)
igt@gem_ppgtt@blt-vs-render-ctx0:
shard-kbl: PASS -> INCOMPLETE (fdo#103665, fdo#106023)
Possible fixes
igt@drv_selftest@live_hangcheck:
shard-kbl: DMESG-FAIL (fdo#106560, fdo#106947) -> PASS
{igt@gem_userptr_blits@readonly-unsync}:
shard-apl: INCOMPLETE (fdo#103927) -> PASS
igt@kms_flip@flip-vs-expired-vblank:
shard-glk: FAIL (fdo#105363) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023
fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886
fdo#106947 https://bugs.freedesktop.org/show_bug.cgi?id=106947
k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133
== Participating hosts (5 -> 5) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_4712 -> Patchwork_10022
CI_DRM_4712: 7b245f2b1e25677a1f2b63fd69003e35731cedda @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4610: c40743d3fce5055682d31610519758dd7379c0f8 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10022: e2fddd13ea2e20989e0c2f203ddff21cca234ecc @
git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
git://anongit.freedesktop.org/piglit
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10022/shards.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/selftests: ring all doorbells in igt_guc_doorbells
On 8/27/2018 3:36 PM, Daniele Ceraolo Spurio wrote:
We currently verify that all doorbells can be registerd with GuC and
^registered
HW but don't check that all works as expected after a db ring.
Do a nop ring of all doorbells to make sure we haven't misprogrammed
any WQ or stage descriptor data. This will also help validating
upcoming changes in the db programming flow.
Cc: Michel Thierry
Cc: Michal Wajdeczko
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_guc_fwif.h | 1 +
drivers/gpu/drm/i915/intel_guc_submission.c | 25 +-
drivers/gpu/drm/i915/intel_guc_submission.h | 4 +++
drivers/gpu/drm/i915/selftests/intel_guc.c | 38 +
4 files changed, 59 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 1a0f2a39cef9..8382d591c784 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -49,6 +49,7 @@
#define WQ_TYPE_BATCH_BUF (0x1 << WQ_TYPE_SHIFT)
#define WQ_TYPE_PSEUDO (0x2 << WQ_TYPE_SHIFT)
#define WQ_TYPE_INORDER (0x3 << WQ_TYPE_SHIFT)
+#define WQ_TYPE_NOOP (0x4 << WQ_TYPE_SHIFT)
#define WQ_TARGET_SHIFT 10
#define WQ_LEN_SHIFT 16
#define WQ_NO_WCFLUSH_WAIT(1 << 27)
diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c
b/drivers/gpu/drm/i915/intel_guc_submission.c
index 195adbd0ebf7..07b9d313b019 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -456,6 +456,9 @@ static void guc_wq_item_append(struct intel_guc_client
*client,
*/
BUILD_BUG_ON(wqi_size != 16);
+ /* We expect the WQ to be active if we're appending items to it */
+ GEM_BUG_ON(desc->wq_status != WQ_STATUS_ACTIVE);
+
/* Free space is guaranteed. */
wq_off = READ_ONCE(desc->tail);
GEM_BUG_ON(CIRC_SPACE(wq_off, READ_ONCE(desc->head),
@@ -465,15 +468,19 @@ static void guc_wq_item_append(struct intel_guc_client
*client,
/* WQ starts from the page after doorbell / process_desc */
wqi = client->vaddr + wq_off + GUC_DB_SIZE;
- /* Now fill in the 4-word work queue item */
- wqi->header = WQ_TYPE_INORDER |
- (wqi_len << WQ_LEN_SHIFT) |
- (target_engine << WQ_TARGET_SHIFT) |
- WQ_NO_WCFLUSH_WAIT;
- wqi->context_desc = context_desc;
- wqi->submit_element_info = ring_tail << WQ_RING_TAIL_SHIFT;
- GEM_BUG_ON(ring_tail > WQ_RING_TAIL_MAX);
- wqi->fence_id = fence_id;
+ if (I915_SELFTEST_ONLY(client->use_nop_wqi)) {
+ wqi->header = WQ_TYPE_NOOP | (wqi_len << WQ_LEN_SHIFT);
Note to self, this is WQ_NOOP + three u32 with 0's
+ } else {
+ /* Now fill in the 4-word work queue item */
+ wqi->header = WQ_TYPE_INORDER |
+ (wqi_len << WQ_LEN_SHIFT) |
+ (target_engine << WQ_TARGET_SHIFT) |
+ WQ_NO_WCFLUSH_WAIT;
+ wqi->context_desc = context_desc;
+ wqi->submit_element_info = ring_tail << WQ_RING_TAIL_SHIFT;
+ GEM_BUG_ON(ring_tail > WQ_RING_TAIL_MAX);
+ wqi->fence_id = fence_id;
+ }
/* Make the update visible to GuC */
WRITE_ONCE(desc->tail, (wq_off + wqi_size) & (GUC_WQ_SIZE - 1));
diff --git a/drivers/gpu/drm/i915/intel_guc_submission.h
b/drivers/gpu/drm/i915/intel_guc_submission.h
index fb081cefef93..169c54568340 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.h
+++ b/drivers/gpu/drm/i915/intel_guc_submission.h
@@ -28,6 +28,7 @@
#include
#include "i915_gem.h"
+#include "i915_selftest.h"
struct drm_i915_private;
@@ -71,6 +72,9 @@ struct intel_guc_client {
spinlock_t wq_lock;
/* Per-engine counts of GuC submissions */
u64 submissions[I915_NUM_ENGINES];
+
+ /* For testing purposes, use nop WQ items instead of real ones */
+ I915_SELFTEST_DECLARE(bool use_nop_wqi);
};
int intel_guc_submission_init(struct intel_guc *guc);
diff --git a/drivers/gpu/drm/i915/selftests/intel_guc.c
b/drivers/gpu/drm/i915/selftests/intel_guc.c
index 407c98fb9170..3154fd2f625d 100644
--- a/drivers/gpu/drm/i915/selftests/intel_guc.c
+++ b/drivers/gpu/drm/i915/selftests/intel_guc.c
@@ -65,6 +65,40 @@ static int check_all_doorbells(struct intel_guc *guc)
return 0;
}
+static int ring_doorbell_nop(struct intel_guc_client *client)
+{
+ int err;
+ struct guc_process_desc *desc = __get_process_desc(client);
+
+ client->use_nop_wqi = true;
+
+ spin_lock_irq(>wq_lock);
+
+ guc_wq_item_append(client, 0, 0, 0, 0);
+ guc_ring_doorbell(client);
+
+ spin_unlock_irq(>wq_lock);
+
+
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: ring all doorbells in igt_guc_doorbells
== Series Details ==
Series: drm/i915/selftests: ring all doorbells in igt_guc_doorbells
URL : https://patchwork.freedesktop.org/series/48768/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4712 -> Patchwork_10023 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/48768/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_10023:
=== IGT changes ===
Warnings
{igt@kms_psr@primary_page_flip}:
fi-cnl-psr: DMESG-WARN -> DMESG-FAIL
{igt@pm_rpm@module-reload}:
fi-hsw-4770r: SKIP -> PASS
== Known issues ==
Here are the changes found in Patchwork_10023 that come from known issues:
=== IGT changes ===
Issues hit
{igt@amdgpu/amd_prime@amd-to-i915}:
{fi-kbl-8809g}: NOTRUN -> FAIL (fdo#107341)
igt@drv_selftest@live_hangcheck:
{fi-cfl-8109u}: PASS -> DMESG-FAIL (fdo#106560)
fi-cfl-s3: PASS -> DMESG-FAIL (fdo#106560)
fi-kbl-7567u: PASS -> DMESG-FAIL (fdo#106560, fdo#106947)
igt@gem_basic@bad-close:
fi-skl-6770hq: PASS -> DMESG-WARN (fdo#105541)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
{fi-byt-clapper}: PASS -> FAIL (fdo#103191, fdo#107362)
{igt@pm_rpm@module-reload}:
fi-cnl-psr: PASS -> WARN (fdo#107602)
Possible fixes
{igt@amdgpu/amd_basic@userptr}:
{fi-kbl-8809g}: INCOMPLETE (fdo#107402) -> PASS
igt@drv_module_reload@basic-reload-inject:
fi-hsw-4770r: DMESG-WARN (fdo#107425) -> PASS
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
fi-bxt-dsi: INCOMPLETE (fdo#103927) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#105541 https://bugs.freedesktop.org/show_bug.cgi?id=105541
fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
fdo#106947 https://bugs.freedesktop.org/show_bug.cgi?id=106947
fdo#107341 https://bugs.freedesktop.org/show_bug.cgi?id=107341
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107402 https://bugs.freedesktop.org/show_bug.cgi?id=107402
fdo#107425 https://bugs.freedesktop.org/show_bug.cgi?id=107425
fdo#107602 https://bugs.freedesktop.org/show_bug.cgi?id=107602
== Participating hosts (54 -> 49) ==
Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4712 -> Patchwork_10023
CI_DRM_4712: 7b245f2b1e25677a1f2b63fd69003e35731cedda @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4610: c40743d3fce5055682d31610519758dd7379c0f8 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10023: b370a2de90ed24f059085b7482f852e0efc0f1fd @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
b370a2de90ed drm/i915/selftests: ring all doorbells in igt_guc_doorbells
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10023/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH libdrm 1/4] intel: add IS_GENX() generic macro
On Mon, Aug 27, 2018 at 10:40:28PM +0100, Chris Wilson wrote: > Quoting Lucas De Marchi (2018-08-27 22:19:54) > > On Sat, Aug 25, 2018 at 10:35:23AM +0100, Chris Wilson wrote: > > > Quoting Lucas De Marchi (2018-08-25 00:56:46) > > > That should help cut down the object size expansion. But longer term I'd > > > > I'm not opposed to turning it into inline function, but if the goal is > > to reduce the object size expansion, just making the array static const > > should suffice... we do call the macros several times, but most of the > > size is for constructing the array, not to find the elements. > > It'll construct the array on the stack, painfully. I thought you were > trying for a minimal change :) the way I meant it it won't construct in the stack. > > > > prefer if we moved to towards finding the match data once. Also we need > > > to pull into the canonical header the friendly names for mesa. > > > > what do you mean by "friendly names for mesa". > > > > The other option that is actually my preferred is to let the kernel tell > > user space what it is. What do you think about having an ioctl that returns > > what is the gen + additional interesting info? Then user space could > > base its decisions on features and fallback to gen version when there > > isn't a way to discover if a feature/bug is present. This would allow > > to simply remove the pci ids from user space projects which IMO would be > > a good thing. > > There simply wasn't enough interest. The key point is selling it to > mesa, see include/pci_ids/i965_pci_ids.h > > The challenge with the centralised db of interesting info is that it > will always be out of date for userspace (think userspace having to cope > with a 5 year kernel, and a kernel having to cope with 10 year old > userspace) and never enough so they still have to supplement it without > their own db. > > That isn't to say that there isn't a lot of interesting hw properties > that userspace needs to know, but they are also tend to be the ones tied > to fuses and not pciid. > > What we do all duplicate are the pci-ids, so pulling those into a > central header containing the commonly used per-id information in a format > that can be embedded into any of the caller's structs is challenge > enough. I think kernel, igt and libdrm would be happy with either runtime or a common header. Checking now what mesa does, giving a friendly name and assigning the properties for each and every device is out of reach, at least for now. So fair enough regarding the runtime option. However I don't think that means we shouldn't try improve libdrm/igt just because it won't solve it for mesa (at least with the "common header approach"). I'll try to spin a new version to handle your comment. Lucas De Marchi ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: ring all doorbells in igt_guc_doorbells
== Series Details == Series: drm/i915/selftests: ring all doorbells in igt_guc_doorbells URL : https://patchwork.freedesktop.org/series/48768/ State : warning == Summary == $ dim checkpatch origin/drm-tip b370a2de90ed drm/i915/selftests: ring all doorbells in igt_guc_doorbells -:6: WARNING:TYPO_SPELLING: 'registerd' may be misspelled - perhaps 'registered'? #6: We currently verify that all doorbells can be registerd with GuC and total: 0 errors, 1 warnings, 0 checks, 110 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915: Clean up skl_plane_has_planar()
skl_plane_has_planar is hard to read, simplify the logic by checking for
support in the order of platform, pipe and plane.
No change in functionality intended.
v2: Fix logic for primary plane (Ville)
Cc: Ville Syrjälä
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/intel_display.c | 27 +--
1 file changed, 9 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 30fdfd1a3037..178552db1552 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13622,24 +13622,15 @@ static bool skl_plane_has_fbc(struct drm_i915_private
*dev_priv,
bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
enum pipe pipe, enum plane_id plane_id)
{
- if (plane_id == PLANE_PRIMARY) {
- if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
- return false;
- else if ((INTEL_GEN(dev_priv) == 9 && pipe == PIPE_C) &&
-!IS_GEMINILAKE(dev_priv))
- return false;
- } else if (plane_id >= PLANE_SPRITE0) {
- if (plane_id == PLANE_CURSOR)
- return false;
- if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) == 10) {
- if (plane_id != PLANE_SPRITE0)
- return false;
- } else {
- if (plane_id != PLANE_SPRITE0 || pipe == PIPE_C ||
- IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
- return false;
- }
- }
+ if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
+ return false;
+
+ if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv) && pipe ==
PIPE_C)
+ return false;
+
+ if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0)
+ return false;
+
return true;
}
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: introduce dp_to_i915() helper
== Series Details ==
Series: series starting with [1/2] drm/i915: introduce dp_to_i915() helper
URL : https://patchwork.freedesktop.org/series/48767/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4712 -> Patchwork_10022 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/48767/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_10022:
=== IGT changes ===
Warnings
{igt@pm_rpm@module-reload}:
fi-bsw-n3050: DMESG-WARN -> DMESG-FAIL
fi-hsw-4770r: SKIP -> PASS
== Known issues ==
Here are the changes found in Patchwork_10022 that come from known issues:
=== IGT changes ===
Issues hit
{igt@amdgpu/amd_prime@amd-to-i915}:
{fi-kbl-8809g}: NOTRUN -> FAIL (fdo#107341)
igt@drv_selftest@live_coherency:
fi-gdg-551: PASS -> DMESG-FAIL (fdo#107164)
igt@drv_selftest@live_hangcheck:
fi-skl-guc: PASS -> DMESG-FAIL (fdo#107174)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
{fi-byt-clapper}: PASS -> FAIL (fdo#107362, fdo#103191)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
fi-skl-guc: PASS -> FAIL (fdo#103191)
{igt@pm_rpm@module-reload}:
fi-cnl-psr: PASS -> WARN (fdo#107602)
Possible fixes
{igt@amdgpu/amd_basic@userptr}:
{fi-kbl-8809g}: INCOMPLETE (fdo#107402) -> PASS
igt@drv_module_reload@basic-reload-inject:
fi-hsw-4770r: DMESG-WARN (fdo#107425) -> PASS
igt@gem_exec_suspend@basic-s3:
fi-blb-e6850: INCOMPLETE -> PASS
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
fi-bxt-dsi: INCOMPLETE (fdo#103927) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#107164 https://bugs.freedesktop.org/show_bug.cgi?id=107164
fdo#107174 https://bugs.freedesktop.org/show_bug.cgi?id=107174
fdo#107341 https://bugs.freedesktop.org/show_bug.cgi?id=107341
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107402 https://bugs.freedesktop.org/show_bug.cgi?id=107402
fdo#107425 https://bugs.freedesktop.org/show_bug.cgi?id=107425
fdo#107602 https://bugs.freedesktop.org/show_bug.cgi?id=107602
== Participating hosts (54 -> 49) ==
Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4712 -> Patchwork_10022
CI_DRM_4712: 7b245f2b1e25677a1f2b63fd69003e35731cedda @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4610: c40743d3fce5055682d31610519758dd7379c0f8 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10022: e2fddd13ea2e20989e0c2f203ddff21cca234ecc @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
e2fddd13ea2e drm/i915: Use dp_to_i915 on intel_psr.c
5c18f353b8f2 drm/i915: introduce dp_to_i915() helper
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10022/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/selftests: ring all doorbells in igt_guc_doorbells
We currently verify that all doorbells can be registerd with GuC and
HW but don't check that all works as expected after a db ring.
Do a nop ring of all doorbells to make sure we haven't misprogrammed
any WQ or stage descriptor data. This will also help validating
upcoming changes in the db programming flow.
Cc: Michel Thierry
Cc: Michal Wajdeczko
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_guc_fwif.h | 1 +
drivers/gpu/drm/i915/intel_guc_submission.c | 25 +-
drivers/gpu/drm/i915/intel_guc_submission.h | 4 +++
drivers/gpu/drm/i915/selftests/intel_guc.c | 38 +
4 files changed, 59 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 1a0f2a39cef9..8382d591c784 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -49,6 +49,7 @@
#define WQ_TYPE_BATCH_BUF(0x1 << WQ_TYPE_SHIFT)
#define WQ_TYPE_PSEUDO (0x2 << WQ_TYPE_SHIFT)
#define WQ_TYPE_INORDER (0x3 << WQ_TYPE_SHIFT)
+#define WQ_TYPE_NOOP (0x4 << WQ_TYPE_SHIFT)
#define WQ_TARGET_SHIFT10
#define WQ_LEN_SHIFT 16
#define WQ_NO_WCFLUSH_WAIT (1 << 27)
diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c
b/drivers/gpu/drm/i915/intel_guc_submission.c
index 195adbd0ebf7..07b9d313b019 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -456,6 +456,9 @@ static void guc_wq_item_append(struct intel_guc_client
*client,
*/
BUILD_BUG_ON(wqi_size != 16);
+ /* We expect the WQ to be active if we're appending items to it */
+ GEM_BUG_ON(desc->wq_status != WQ_STATUS_ACTIVE);
+
/* Free space is guaranteed. */
wq_off = READ_ONCE(desc->tail);
GEM_BUG_ON(CIRC_SPACE(wq_off, READ_ONCE(desc->head),
@@ -465,15 +468,19 @@ static void guc_wq_item_append(struct intel_guc_client
*client,
/* WQ starts from the page after doorbell / process_desc */
wqi = client->vaddr + wq_off + GUC_DB_SIZE;
- /* Now fill in the 4-word work queue item */
- wqi->header = WQ_TYPE_INORDER |
- (wqi_len << WQ_LEN_SHIFT) |
- (target_engine << WQ_TARGET_SHIFT) |
- WQ_NO_WCFLUSH_WAIT;
- wqi->context_desc = context_desc;
- wqi->submit_element_info = ring_tail << WQ_RING_TAIL_SHIFT;
- GEM_BUG_ON(ring_tail > WQ_RING_TAIL_MAX);
- wqi->fence_id = fence_id;
+ if (I915_SELFTEST_ONLY(client->use_nop_wqi)) {
+ wqi->header = WQ_TYPE_NOOP | (wqi_len << WQ_LEN_SHIFT);
+ } else {
+ /* Now fill in the 4-word work queue item */
+ wqi->header = WQ_TYPE_INORDER |
+ (wqi_len << WQ_LEN_SHIFT) |
+ (target_engine << WQ_TARGET_SHIFT) |
+ WQ_NO_WCFLUSH_WAIT;
+ wqi->context_desc = context_desc;
+ wqi->submit_element_info = ring_tail << WQ_RING_TAIL_SHIFT;
+ GEM_BUG_ON(ring_tail > WQ_RING_TAIL_MAX);
+ wqi->fence_id = fence_id;
+ }
/* Make the update visible to GuC */
WRITE_ONCE(desc->tail, (wq_off + wqi_size) & (GUC_WQ_SIZE - 1));
diff --git a/drivers/gpu/drm/i915/intel_guc_submission.h
b/drivers/gpu/drm/i915/intel_guc_submission.h
index fb081cefef93..169c54568340 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.h
+++ b/drivers/gpu/drm/i915/intel_guc_submission.h
@@ -28,6 +28,7 @@
#include
#include "i915_gem.h"
+#include "i915_selftest.h"
struct drm_i915_private;
@@ -71,6 +72,9 @@ struct intel_guc_client {
spinlock_t wq_lock;
/* Per-engine counts of GuC submissions */
u64 submissions[I915_NUM_ENGINES];
+
+ /* For testing purposes, use nop WQ items instead of real ones */
+ I915_SELFTEST_DECLARE(bool use_nop_wqi);
};
int intel_guc_submission_init(struct intel_guc *guc);
diff --git a/drivers/gpu/drm/i915/selftests/intel_guc.c
b/drivers/gpu/drm/i915/selftests/intel_guc.c
index 407c98fb9170..3154fd2f625d 100644
--- a/drivers/gpu/drm/i915/selftests/intel_guc.c
+++ b/drivers/gpu/drm/i915/selftests/intel_guc.c
@@ -65,6 +65,40 @@ static int check_all_doorbells(struct intel_guc *guc)
return 0;
}
+static int ring_doorbell_nop(struct intel_guc_client *client)
+{
+ int err;
+ struct guc_process_desc *desc = __get_process_desc(client);
+
+ client->use_nop_wqi = true;
+
+ spin_lock_irq(>wq_lock);
+
+ guc_wq_item_append(client, 0, 0, 0, 0);
+ guc_ring_doorbell(client);
+
+ spin_unlock_irq(>wq_lock);
+
+ client->use_nop_wqi = false;
+
+ /* if there are no issues GuC will update the WQ head and keep the
+* WQ in active status
+*/
+ err =
[Intel-gfx] [PATCH 1/2] drm/i915: introduce dp_to_i915() helper
No functional change. But let's get first i915 pointer
directly from intel_dp so we can clean up a lot of code
later.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_dp.c | 109 +++
drivers/gpu/drm/i915/intel_drv.h | 6 ++
2 files changed, 57 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index db8515171270..436c22de33b6 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -107,13 +107,6 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
}
-static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
-{
- struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
-
- return intel_dig_port->base.base.dev;
-}
-
static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
{
return enc_to_intel_dp(_attached_encoder(connector)->base);
@@ -232,7 +225,7 @@ intel_dp_link_required(int pixel_clock, int bpp)
void icl_program_mg_dp_mode(struct intel_dp *intel_dp)
{
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
- struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
enum port port = intel_dig_port->base.port;
enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
u32 ln0, ln1, lane_info;
@@ -661,7 +654,7 @@ intel_dp_pps_init(struct intel_dp *intel_dp);
static void pps_lock(struct intel_dp *intel_dp)
{
- struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
/*
* See intel_power_sequencer_reset() why we need
@@ -674,7 +667,7 @@ static void pps_lock(struct intel_dp *intel_dp)
static void pps_unlock(struct intel_dp *intel_dp)
{
- struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
mutex_unlock(_priv->pps_mutex);
@@ -684,7 +677,7 @@ static void pps_unlock(struct intel_dp *intel_dp)
static void
vlv_power_sequencer_kick(struct intel_dp *intel_dp)
{
- struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
enum pipe pipe = intel_dp->pps_pipe;
bool pll_enabled, release_cl_override = false;
@@ -789,7 +782,7 @@ static enum pipe vlv_find_free_pps(struct drm_i915_private
*dev_priv)
static enum pipe
vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
{
- struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
enum pipe pipe;
@@ -836,7 +829,7 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
static int
bxt_power_sequencer_idx(struct intel_dp *intel_dp)
{
- struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
int backlight_controller = dev_priv->vbt.backlight.controller;
lockdep_assert_held(_priv->pps_mutex);
@@ -905,7 +898,7 @@ vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
static void
vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
{
- struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
enum port port = intel_dig_port->base.port;
@@ -982,7 +975,7 @@ struct pps_registers {
static void intel_pps_get_registers(struct intel_dp *intel_dp,
struct pps_registers *regs)
{
- struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
int pps_idx = 0;
memset(regs, 0, sizeof(*regs));
@@ -1028,7 +1021,7 @@ static int edp_notify_handler(struct notifier_block
*this, unsigned long code,
{
struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
edp_notifier);
- struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
return 0;
@@ -1058,7 +1051,7 @@ static int edp_notify_handler(struct notifier_block
*this, unsigned long code,
static bool edp_have_panel_power(struct intel_dp *intel_dp)
{
- struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
+
[Intel-gfx] [PATCH 2/2] drm/i915: Use dp_to_i915 on intel_psr.c
Now that we have a generic caller let's simplify it and
clean up the intel_psr.c code a bit.
Cc: Dhinakaran Pandiyan
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_psr.c | 50 +---
1 file changed, 14 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index da583a45e942..7acd84a150f7 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -270,7 +270,7 @@ static void intel_psr_setup_vsc(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
- struct drm_i915_private *dev_priv =
to_i915(intel_dig_port->base.base.dev);
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct edp_vsc_psr psr_vsc;
if (dev_priv->psr.psr2_enabled) {
@@ -300,8 +300,7 @@ static void intel_psr_setup_vsc(struct intel_dp *intel_dp,
static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
{
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u32 aux_clock_divider, aux_ctl;
int i;
static const uint8_t aux_msg[] = {
@@ -334,9 +333,7 @@ static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
static void intel_psr_enable_sink(struct intel_dp *intel_dp)
{
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- struct drm_device *dev = dig_port->base.base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u8 dpcd_val = DP_PSR_ENABLE;
/* Enable ALPM at sink for psr2 */
@@ -357,9 +354,7 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp)
static void hsw_activate_psr1(struct intel_dp *intel_dp)
{
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- struct drm_device *dev = dig_port->base.base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u32 max_sleep_time = 0x1f;
u32 val = EDP_PSR_ENABLE;
@@ -414,9 +409,7 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
static void hsw_activate_psr2(struct intel_dp *intel_dp)
{
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- struct drm_device *dev = dig_port->base.base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u32 val;
/* Let's use 6 as the minimum to cover all known cases including the
@@ -452,8 +445,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state)
{
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
int crtc_hdisplay = crtc_state->base.adjusted_mode.crtc_hdisplay;
int crtc_vdisplay = crtc_state->base.adjusted_mode.crtc_vdisplay;
int psr_max_h = 0, psr_max_v = 0;
@@ -488,7 +480,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
const struct drm_display_mode *adjusted_mode =
_state->base.adjusted_mode;
int psr_setup_time;
@@ -544,9 +536,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
static void intel_psr_activate(struct intel_dp *intel_dp)
{
- struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
- struct drm_device *dev = intel_dig_port->base.base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
if (INTEL_GEN(dev_priv) >= 9)
WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
@@ -566,9 +556,7 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
static void intel_psr_enable_source(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- struct drm_device *dev = dig_port->base.base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
enum transcoder cpu_transcoder =
Re: [Intel-gfx] [PATCH libdrm 1/4] intel: add IS_GENX() generic macro
Quoting Lucas De Marchi (2018-08-27 22:19:54) > On Sat, Aug 25, 2018 at 10:35:23AM +0100, Chris Wilson wrote: > > Quoting Lucas De Marchi (2018-08-25 00:56:46) > > That should help cut down the object size expansion. But longer term I'd > > I'm not opposed to turning it into inline function, but if the goal is > to reduce the object size expansion, just making the array static const > should suffice... we do call the macros several times, but most of the > size is for constructing the array, not to find the elements. It'll construct the array on the stack, painfully. I thought you were trying for a minimal change :) > > prefer if we moved to towards finding the match data once. Also we need > > to pull into the canonical header the friendly names for mesa. > > what do you mean by "friendly names for mesa". > > The other option that is actually my preferred is to let the kernel tell > user space what it is. What do you think about having an ioctl that returns > what is the gen + additional interesting info? Then user space could > base its decisions on features and fallback to gen version when there > isn't a way to discover if a feature/bug is present. This would allow > to simply remove the pci ids from user space projects which IMO would be > a good thing. There simply wasn't enough interest. The key point is selling it to mesa, see include/pci_ids/i965_pci_ids.h The challenge with the centralised db of interesting info is that it will always be out of date for userspace (think userspace having to cope with a 5 year kernel, and a kernel having to cope with 10 year old userspace) and never enough so they still have to supplement it without their own db. That isn't to say that there isn't a lot of interesting hw properties that userspace needs to know, but they are also tend to be the ones tied to fuses and not pciid. What we do all duplicate are the pci-ids, so pulling those into a central header containing the commonly used per-id information in a format that can be embedded into any of the caller's structs is challenge enough. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] linux-next: Signed-off-by missing for commit in the drm-misc-fixes tree
Hi all,
Commit
ccb748df0058 ("drm/vc4: Fix the "no scaling" case on multi-planar YUV
formats")
is missing a Signed-off-by from its committer.
It was rebased.
--
Cheers,
Stephen Rothwell
pgpuW2ZnMKi1K.pgp
Description: OpenPGP digital signature
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Re: [Intel-gfx] [PATCH libdrm 1/4] intel: add IS_GENX() generic macro
On Sat, Aug 25, 2018 at 10:35:23AM +0100, Chris Wilson wrote:
> Quoting Lucas De Marchi (2018-08-25 00:56:46)
> > diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
> > index 4a34b7be..8a0e3e76 100644
> > --- a/intel/intel_chipset.h
> > +++ b/intel/intel_chipset.h
> > @@ -568,6 +568,26 @@
> >
> > #define IS_GEN11(devid)(IS_ICELAKE_11(devid))
> >
> > +/* New platforms use kernel pci ids */
> > +#include "i915_pciids.h"
> > +
> > +struct pci_device_id {
>
> Don't call it pci_device_id, depending on caller that name may already
> be taken by libpciaccess.
ok. I can actually move it inside the function/macro and use an
autogenerated name.
>
> > + uint32_t unused0, device;
> > + uint32_t unused1, unused2;
> > + uint32_t unused3, unused4;
> These are all uint16_t.
kernel "document" them as uint32_t:
/*
* A pci_device_id struct {
* __u32 vendor, device;
* __u32 subvendor, subdevice;
* __u32 class, class_mask;
* kernel_ulong_t driver_data;
* };
* Don't use C99 here because "class" is reserved and we want to
* give userspace flexibility.
>
> > + unsigned long unused5;
>
> Simply make the unused disappear from the macro.
>
> > +};
> > +
> > +#define IS_GENX(x, devid) ({ \
> > + struct pci_device_id __ids[] = { INTEL_ ## x ## _IDS(0) }; \
>
> While that's a neat trick it's instantiating the array for each caller,
> and it does appear that we repeat a few of the macros.
>
> The best I can offer to keep the change non-invasive (other than just
> switching to a platform bitmask and filling (devid, gen, platform) from
> the pci match data on initialisation) is a two pass approach.
>
> static inline int __find_in_pciid(uint16_t devid,
> const struct pci_device_id *ids, size_t count)
> {
> size_t i = 0; /* we should rethink this if we think there are more than
> 4B of them! */
> for (i = 0; i < count; i++) {
> if (ids[i].device == devid)
> return 1;
> }
> return 0;
> }
>
>
> #define __is_genx(x) \
here I would name this DEFINE_IS_GENX, since it's a macro to define
the functions, not to be used in other places.
> static inline int __is_gen##x(uint16_t devid) \
> { \
> static const struct pci_device_id __ids[] = { INTEL_ ## x ## _IDS(0) };
> \
> return __find_in_pciid(devid, __ids, sizeof(__ids)/sizeof(__ids[0]); \
> }
> __is_genx(3);
> __is_genx(4);
> __is_genx(5);
> __is_genx(6);
> __is_genx(7);
> __is_genx(8);
> __is_genx(9);
> __is_genx(10);
> __is_genx(11);
>
> #define IS_GENX(x, devid) __is_gen##x(devid)
i915_pciids.h is not consistent with how the macros are called. See that
in my patch. So here I'd have:
#define DEFINE_IS_GENX(x, pfx) \
static inline int __is_gen##x(uint16_t devid) \
{ \
static const struct pci_device_id __ids[] = { INTEL_ ## pfx ## _IDS(0)
}; \
return __find_in_pciid(devid, __ids, sizeof(__ids)/sizeof(__ids[0]); \
}
#define IS_GEN10(devid) IS_GENX(10, CNL, devid)
For gen9 is more complicated as it needs several ids.
>
> That should help cut down the object size expansion. But longer term I'd
I'm not opposed to turning it into inline function, but if the goal is
to reduce the object size expansion, just making the array static const
should suffice... we do call the macros several times, but most of the
size is for constructing the array, not to find the elements.
> prefer if we moved to towards finding the match data once. Also we need
> to pull into the canonical header the friendly names for mesa.
what do you mean by "friendly names for mesa".
The other option that is actually my preferred is to let the kernel tell
user space what it is. What do you think about having an ioctl that returns
what is the gen + additional interesting info? Then user space could
base its decisions on features and fallback to gen version when there
isn't a way to discover if a feature/bug is present. This would allow
to simply remove the pci ids from user space projects which IMO would be
a good thing.
Lucas De Marchi
> -Chris
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Skip modeset for cdclk changes if possible
== Series Details ==
Series: drm/i915: Skip modeset for cdclk changes if possible
URL : https://patchwork.freedesktop.org/series/48763/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4709 -> Patchwork_10021 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_10021 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10021, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/48763/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_10021:
=== IGT changes ===
Possible regressions
igt@gem_basic@create-fd-close:
fi-kbl-7560u: PASS -> INCOMPLETE
igt@gem_exec_suspend@basic-s3:
fi-blb-e6850: PASS -> INCOMPLETE
{igt@kms_psr@primary_mmap_gtt}:
fi-cnl-psr: PASS -> DMESG-WARN
== Known issues ==
Here are the changes found in Patchwork_10021 that come from known issues:
=== IGT changes ===
Issues hit
igt@drv_selftest@live_guc:
fi-skl-guc: NOTRUN -> DMESG-WARN (fdo#107175, fdo#107258)
igt@drv_selftest@live_hangcheck:
fi-skl-guc: NOTRUN -> DMESG-FAIL (fdo#107174)
igt@kms_frontbuffer_tracking@basic:
{fi-byt-clapper}: PASS -> FAIL (fdo#103167)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
{fi-byt-clapper}: PASS -> FAIL (fdo#103191, fdo#107362) +1
{igt@pm_rpm@module-reload}:
fi-cnl-psr: PASS -> WARN (fdo#107602)
Possible fixes
igt@debugfs_test@read_all_entries:
{fi-icl-u}: DMESG-FAIL (fdo#107411) -> PASS
igt@gem_exec_reloc@basic-gtt-read-noreloc:
{fi-icl-u}: DMESG-WARN (fdo#107411) -> PASS +77
igt@gem_exec_suspend@basic-s3:
{fi-icl-u}: DMESG-WARN -> PASS
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
{fi-byt-clapper}: FAIL (fdo#103191, fdo#107362) -> PASS
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
fi-bxt-dsi: INCOMPLETE (fdo#103927) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#107174 https://bugs.freedesktop.org/show_bug.cgi?id=107174
fdo#107175 https://bugs.freedesktop.org/show_bug.cgi?id=107175
fdo#107258 https://bugs.freedesktop.org/show_bug.cgi?id=107258
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107411 https://bugs.freedesktop.org/show_bug.cgi?id=107411
fdo#107602 https://bugs.freedesktop.org/show_bug.cgi?id=107602
== Participating hosts (53 -> 48) ==
Additional (1): fi-skl-guc
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-byt-squawks
fi-bsw-cyan fi-ctg-p8600
== Build changes ==
* Linux: CI_DRM_4709 -> Patchwork_10021
CI_DRM_4709: f1c0fce7feaa69409ec8a379fc78ef792f168d28 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4610: c40743d3fce5055682d31610519758dd7379c0f8 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10021: ef26dd1114084a43f1366e2c3f729c0d0d2c4808 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
ef26dd111408 drm/i915: Skip modeset for cdclk changes if possible
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10021/issues.html
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Skip modeset for cdclk changes if possible
== Series Details == Series: drm/i915: Skip modeset for cdclk changes if possible URL : https://patchwork.freedesktop.org/series/48763/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: Skip modeset for cdclk changes if possible +drivers/gpu/drm/i915/intel_cdclk.c:2125:6: warning: symbol 'intel_cdclk_can_skip_modeset' was not declared. Should it be static? -drivers/gpu/drm/i915/selftests/../i915_drv.h:3685:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3686:16: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Skip modeset for cdclk changes if possible
== Series Details == Series: drm/i915: Skip modeset for cdclk changes if possible URL : https://patchwork.freedesktop.org/series/48763/ State : warning == Summary == $ dim checkpatch origin/drm-tip ef26dd111408 drm/i915: Skip modeset for cdclk changes if possible -:324: CHECK:LINE_SPACING: Please don't use multiple blank lines #324: FILE: drivers/gpu/drm/i915/intel_display.c:12256: + total: 0 errors, 0 warnings, 1 checks, 325 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v1] drm/i915: Skip modeset for cdclk changes if possible
From: Ville Syrjälä
If we have only a single active pipe and the cdclk change only requires
the cd2x divider to be updated bxt+ can do the update with forcing a full
modeset on the pipe. Try to hook that up.
Signed-off-by: Ville Syrjälä
Signed-off-by: Abhay Kumar
---
drivers/gpu/drm/i915/i915_drv.h | 3 +-
drivers/gpu/drm/i915/i915_reg.h | 3 +-
drivers/gpu/drm/i915/intel_cdclk.c | 105 +--
drivers/gpu/drm/i915/intel_display.c | 20 ++-
drivers/gpu/drm/i915/intel_drv.h | 9 ++-
5 files changed, 105 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e5b9d3c77139..1f0a6427e76c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -408,7 +408,8 @@ struct drm_i915_display_funcs {
void (*get_cdclk)(struct drm_i915_private *dev_priv,
struct intel_cdclk_state *cdclk_state);
void (*set_cdclk)(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_state *cdclk_state);
+ const struct intel_cdclk_state *cdclk_state,
+ enum pipe pipe);
int (*get_fifo_size)(struct drm_i915_private *dev_priv,
enum i9xx_plane_id i9xx_plane);
int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8534f88a60f6..7702cec70b0d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9262,7 +9262,8 @@ enum skl_power_gate {
#define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20)
#define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19)
#define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
-#define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19)
+#define ICL_CDCLK_CD2X_PIPE(pipe) ((pipe) << 19)
+#define ICL_CDCLK_CD2X_PIPE_NONE ICL_CDCLK_CD2X_PIPE(7)
#define BXT_CDCLK_SSA_PRECHARGE_ENABLE(1 << 16)
#define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
b/drivers/gpu/drm/i915/intel_cdclk.c
index 29075c763428..1955f6aa54e1 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -516,7 +516,8 @@ static void vlv_program_pfi_credits(struct drm_i915_private
*dev_priv)
}
static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_state *cdclk_state)
+ const struct intel_cdclk_state *cdclk_state,
+ enum pipe pipe)
{
int cdclk = cdclk_state->cdclk;
u32 val, cmd = cdclk_state->voltage_level;
@@ -597,7 +598,8 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
}
static void chv_set_cdclk(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_state *cdclk_state)
+ const struct intel_cdclk_state *cdclk_state,
+ enum pipe pipe)
{
int cdclk = cdclk_state->cdclk;
u32 val, cmd = cdclk_state->voltage_level;
@@ -695,7 +697,8 @@ static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
}
static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_state *cdclk_state)
+ const struct intel_cdclk_state *cdclk_state,
+ enum pipe pipe)
{
int cdclk = cdclk_state->cdclk;
uint32_t val;
@@ -985,7 +988,8 @@ static void skl_dpll0_disable(struct drm_i915_private
*dev_priv)
}
static void skl_set_cdclk(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_state *cdclk_state)
+ const struct intel_cdclk_state *cdclk_state,
+ enum pipe pipe)
{
int cdclk = cdclk_state->cdclk;
int vco = cdclk_state->vco;
@@ -1156,7 +1160,7 @@ void skl_init_cdclk(struct drm_i915_private *dev_priv)
cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco);
cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
- skl_set_cdclk(dev_priv, _state);
+ skl_set_cdclk(dev_priv, _state, INVALID_PIPE);
}
/**
@@ -1174,7 +1178,7 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
cdclk_state.vco = 0;
cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
- skl_set_cdclk(dev_priv, _state);
+ skl_set_cdclk(dev_priv, _state, INVALID_PIPE);
}
static int bxt_calc_cdclk(int min_cdclk)
@@ -1353,7 +1357,8 @@ static void bxt_de_pll_enable(struct drm_i915_private
*dev_priv, int vco)
}
static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_state *cdclk_state)
+ const struct intel_cdclk_state *cdclk_state,
+ enum pipe pipe)
{
Re: [Intel-gfx] [PATCH v4] drm/i915: Re-apply "Perform link quality check, unconditionally during long pulse"
On Mon, Aug 27, 2018 at 01:45:48PM -0400, Lyude Paul wrote:
> On Mon, 2018-08-27 at 15:08 +0300, Ville Syrjälä wrote:
> > On Sat, Aug 25, 2018 at 03:10:35PM -0400, Lyude Paul wrote:
> > > From: Jan-Marek Glogowski
> > >
> > > This re-applies the workaround for "some DP sinks, [which] are a
> > > little nuts" from commit 1a36147bb939 ("drm/i915: Perform link
> > > quality check unconditionally during long pulse").
> > > It makes the secondary AOC E2460P monitor connected via DP to an
> > > acer Veriton N4640G usable again.
> > >
> > > This hunk was dropped in commit c85d200e8321 ("drm/i915: Move SST
> > > DP link retraining into the ->post_hotplug() hook")
> > >
> > > Fixes: c85d200e8321 ("drm/i915: Move SST DP link retraining into the
> > > ->post_hotplug() hook")
> > > [Cleaned up commit message, added stable cc]
> > > Signed-off-by: Lyude Paul
> > > Signed-off-by: Jan-Marek Glogowski
> > > Cc: sta...@vger.kernel.org
> > > ---
> > > Resending this to update patchwork; will push in a little bit
> > >
> > > drivers/gpu/drm/i915/intel_dp.c | 33 +++--
> > > 1 file changed, 19 insertions(+), 14 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > > b/drivers/gpu/drm/i915/intel_dp.c
> > > index b3f6f04c3c7d..db8515171270 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -4333,18 +4333,6 @@ intel_dp_needs_link_retrain(struct intel_dp
> > > *intel_dp)
> > > return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
> > > }
> > >
> > > -/*
> > > - * If display is now connected check links status,
> > > - * there has been known issues of link loss triggering
> > > - * long pulse.
> > > - *
> > > - * Some sinks (eg. ASUS PB287Q) seem to perform some
> > > - * weird HPD ping pong during modesets. So we can apparently
> > > - * end up with HPD going low during a modeset, and then
> > > - * going back up soon after. And once that happens we must
> > > - * retrain the link to get a picture. That's in case no
> > > - * userspace component reacted to intermittent HPD dip.
> > > - */
> > > int intel_dp_retrain_link(struct intel_encoder *encoder,
> > > struct drm_modeset_acquire_ctx *ctx)
> > > {
> > > @@ -5031,7 +5019,8 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
> > > }
> > >
> > > static int
> > > -intel_dp_long_pulse(struct intel_connector *connector)
> > > +intel_dp_long_pulse(struct intel_connector *connector,
> > > + struct drm_modeset_acquire_ctx *ctx)
> > > {
> > > struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> > > struct intel_dp *intel_dp = intel_attached_dp(>base);
> > > @@ -5090,6 +5079,22 @@ intel_dp_long_pulse(struct intel_connector
> > > *connector)
> > >*/
> > > status = connector_status_disconnected;
> > > goto out;
> > > + } else {
> > > + /*
> > > + * If display is now connected check links status,
> > > + * there has been known issues of link loss triggering
> > > + * long pulse.
> > > + *
> > > + * Some sinks (eg. ASUS PB287Q) seem to perform some
> > > + * weird HPD ping pong during modesets. So we can apparently
> > > + * end up with HPD going low during a modeset, and then
> > > + * going back up soon after. And once that happens we must
> > > + * retrain the link to get a picture. That's in case no
> > > + * userspace component reacted to intermittent HPD dip.
> > > + */
> > > + struct intel_encoder *encoder = _to_dig_port(intel_dp)-
> > > >base;
> > > +
> > > + intel_dp_retrain_link(encoder, ctx);
> >
> > We should really have a comment here that this is purely duct tape for
> > sinks that fail to signal a hpd when the link goes bad (either that or
> > we fail to process the hpd correctly).
> I'm fine with adding another patch to clarify that comment as well
>
> >
> > I suppose a better way to do this hack would be to do the link quality
> > check at the end of modeset, or from a delayed work. As is this depends
> > on userspace/fbdev doing an explicit probe after the modeset which seems
> > pretty fragile.
> I think having that at the end of a modeset in addition to this would be a
> good idea as well, I don't see any harm in having an additional check in the
> long pulse handler in case something causes the link to become unstable at
> some point in the future after the initial modeset
We already have that via the hotplug hook. The problem here is that there
is apparently no hpd signalled by the sink.
Someone should probably rename intel_dp_long_pulse() to something
else so that people don't get the wrong impression that it's somehow
dedicated to handling long hpds. In fact just
s/intel_dp_long_pulse()/intel_dp_detect()/ and sucking the few lines of
extra code into the function might be the right way to go.
>
> Jan, do you think you could
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Clean up skl_plane_has_planar()
On Mon, 2018-08-27 at 14:56 +0300, Ville Syrjälä wrote:
> On Fri, Aug 24, 2018 at 01:38:55PM -0700, Dhinakaran Pandiyan wrote:
> > skl_plane_has_planar is hard to read, simplify the logic by
> > checking for
> > support in the order of platform, pipe and plane.
>
> I had a slightly different version of this somewhere. But this one
> might
> be even better.
>
> >
> > No change in functionality intended.
> >
> > Cc: Ville Syrjälä
> > Signed-off-by: Dhinakaran Pandiyan
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 27 +---
> > ---
> > 1 file changed, 9 insertions(+), 18 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 30fdfd1a3037..7e18bd8b21b8 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -13622,24 +13622,15 @@ static bool skl_plane_has_fbc(struct
> > drm_i915_private *dev_priv,
> > bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
> > enum pipe pipe, enum plane_id plane_id)
> > {
> > - if (plane_id == PLANE_PRIMARY) {
> > - if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
> > - return false;
> > - else if ((INTEL_GEN(dev_priv) == 9 && pipe ==
> > PIPE_C) &&
> > -!IS_GEMINILAKE(dev_priv))
> > - return false;
> > - } else if (plane_id >= PLANE_SPRITE0) {
> > - if (plane_id == PLANE_CURSOR)
> > - return false;
> > - if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv)
> > == 10) {
> > - if (plane_id != PLANE_SPRITE0)
> > - return false;
> > - } else {
> > - if (plane_id != PLANE_SPRITE0 || pipe ==
> > PIPE_C ||
> > - IS_SKYLAKE(dev_priv) ||
> > IS_BROXTON(dev_priv))
> > - return false;
> > - }
> > - }
> > + if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
> > + return false;
> > +
> > + if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)
> > && pipe == PIPE_C)
> > + return false;
> > +
> > + if (plane_id == PLANE_CURSOR || plane_id != PLANE_SPRITE0)
> > + return false;
>
> The cursor check is rather redundant here. IIRC I put it at the very
> start of the function to make it obvious that cursor never supports
> this. But we could just as well drop the check entirely.
>
> This also disables NV12 for the primary plane which isn't correct.
That's a good catch, thanks.
Switch the condition to
if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0)
return false;
?
>
> > +
> > return true;
> > }
> >
> > --
> > 2.17.1
>
>
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4] drm/i915: Re-apply "Perform link quality check, unconditionally during long pulse"
On Mon, 2018-08-27 at 15:08 +0300, Ville Syrjälä wrote:
> On Sat, Aug 25, 2018 at 03:10:35PM -0400, Lyude Paul wrote:
> > From: Jan-Marek Glogowski
> >
> > This re-applies the workaround for "some DP sinks, [which] are a
> > little nuts" from commit 1a36147bb939 ("drm/i915: Perform link
> > quality check unconditionally during long pulse").
> > It makes the secondary AOC E2460P monitor connected via DP to an
> > acer Veriton N4640G usable again.
> >
> > This hunk was dropped in commit c85d200e8321 ("drm/i915: Move SST
> > DP link retraining into the ->post_hotplug() hook")
> >
> > Fixes: c85d200e8321 ("drm/i915: Move SST DP link retraining into the
> > ->post_hotplug() hook")
> > [Cleaned up commit message, added stable cc]
> > Signed-off-by: Lyude Paul
> > Signed-off-by: Jan-Marek Glogowski
> > Cc: sta...@vger.kernel.org
> > ---
> > Resending this to update patchwork; will push in a little bit
> >
> > drivers/gpu/drm/i915/intel_dp.c | 33 +++--
> > 1 file changed, 19 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index b3f6f04c3c7d..db8515171270 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -4333,18 +4333,6 @@ intel_dp_needs_link_retrain(struct intel_dp
> > *intel_dp)
> > return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
> > }
> >
> > -/*
> > - * If display is now connected check links status,
> > - * there has been known issues of link loss triggering
> > - * long pulse.
> > - *
> > - * Some sinks (eg. ASUS PB287Q) seem to perform some
> > - * weird HPD ping pong during modesets. So we can apparently
> > - * end up with HPD going low during a modeset, and then
> > - * going back up soon after. And once that happens we must
> > - * retrain the link to get a picture. That's in case no
> > - * userspace component reacted to intermittent HPD dip.
> > - */
> > int intel_dp_retrain_link(struct intel_encoder *encoder,
> > struct drm_modeset_acquire_ctx *ctx)
> > {
> > @@ -5031,7 +5019,8 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
> > }
> >
> > static int
> > -intel_dp_long_pulse(struct intel_connector *connector)
> > +intel_dp_long_pulse(struct intel_connector *connector,
> > + struct drm_modeset_acquire_ctx *ctx)
> > {
> > struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> > struct intel_dp *intel_dp = intel_attached_dp(>base);
> > @@ -5090,6 +5079,22 @@ intel_dp_long_pulse(struct intel_connector
> > *connector)
> > */
> > status = connector_status_disconnected;
> > goto out;
> > + } else {
> > + /*
> > +* If display is now connected check links status,
> > +* there has been known issues of link loss triggering
> > +* long pulse.
> > +*
> > +* Some sinks (eg. ASUS PB287Q) seem to perform some
> > +* weird HPD ping pong during modesets. So we can apparently
> > +* end up with HPD going low during a modeset, and then
> > +* going back up soon after. And once that happens we must
> > +* retrain the link to get a picture. That's in case no
> > +* userspace component reacted to intermittent HPD dip.
> > +*/
> > + struct intel_encoder *encoder = _to_dig_port(intel_dp)-
> > >base;
> > +
> > + intel_dp_retrain_link(encoder, ctx);
>
> We should really have a comment here that this is purely duct tape for
> sinks that fail to signal a hpd when the link goes bad (either that or
> we fail to process the hpd correctly).
I'm fine with adding another patch to clarify that comment as well
>
> I suppose a better way to do this hack would be to do the link quality
> check at the end of modeset, or from a delayed work. As is this depends
> on userspace/fbdev doing an explicit probe after the modeset which seems
> pretty fragile.
I think having that at the end of a modeset in addition to this would be a
good idea as well, I don't see any harm in having an additional check in the
long pulse handler in case something causes the link to become unstable at
some point in the future after the initial modeset
Jan, do you think you could provide some dmesg logs for this issue?
>
> > }
> >
> > /*
> > @@ -5151,7 +5156,7 @@ intel_dp_detect(struct drm_connector *connector,
> > return ret;
> > }
> >
> > - status = intel_dp_long_pulse(intel_dp->attached_connector);
> > + status = intel_dp_long_pulse(intel_dp->attached_connector,
> > ctx);
> > }
> >
> > intel_dp->detect_done = false;
> > --
> > 2.17.1
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
--
Cheers,
Re: [Intel-gfx] [PATCH v4] drm/i915: Re-apply "Perform link quality check, unconditionally during long pulse"
On Mon, 2018-08-27 at 11:43 +0300, Jani Nikula wrote:
> On Sat, 25 Aug 2018, Lyude Paul wrote:
> > From: Jan-Marek Glogowski
> >
> > This re-applies the workaround for "some DP sinks, [which] are a
> > little nuts" from commit 1a36147bb939 ("drm/i915: Perform link
> > quality check unconditionally during long pulse").
> > It makes the secondary AOC E2460P monitor connected via DP to an
> > acer Veriton N4640G usable again.
> >
> > This hunk was dropped in commit c85d200e8321 ("drm/i915: Move SST
> > DP link retraining into the ->post_hotplug() hook")
> >
> > Fixes: c85d200e8321 ("drm/i915: Move SST DP link retraining into the
> > ->post_hotplug() hook")
> > [Cleaned up commit message, added stable cc]
> > Signed-off-by: Lyude Paul
> > Signed-off-by: Jan-Marek Glogowski
> > Cc: sta...@vger.kernel.org
> > ---
> > Resending this to update patchwork; will push in a little bit
>
> Is there a bugzilla? Reference to a list discussion? Something with a
> dmesg where someone can actually verify this is the right fix?
This patch has actually been on the list for a while now-I have had mdnavare
take a look at it as well (they said it looked fine with the only change being
in regards to the comment), and it'd been on the list for a while already.
>
> IMO needs an ack from Ville too. He should be in Cc: in the first place
> as the author of the regressing commit.
>
> 'dim fixes c85d200e8321' gives you the output:
aaah-I had thought it was just for generating the Fixes line, I will be more
careful about that in the future
>
> Fixes: c85d200e8321 ("drm/i915: Move SST DP link retraining into the
> ->post_hotplug() hook")
> Cc: Manasi Navare
> Cc: Maarten Lankhorst
> Cc: Ville Syrjälä
> Cc: Lyude Paul
> Cc: Jani Nikula
> Cc: Joonas Lahtinen
> Cc: Rodrigo Vivi
> Cc: intel-gfx@lists.freedesktop.org
> Cc: # v4.17+
>
> BR,
> Jani.
>
> >
> > drivers/gpu/drm/i915/intel_dp.c | 33 +++--
> > 1 file changed, 19 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index b3f6f04c3c7d..db8515171270 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -4333,18 +4333,6 @@ intel_dp_needs_link_retrain(struct intel_dp
> > *intel_dp)
> > return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
> > }
> >
> > -/*
> > - * If display is now connected check links status,
> > - * there has been known issues of link loss triggering
> > - * long pulse.
> > - *
> > - * Some sinks (eg. ASUS PB287Q) seem to perform some
> > - * weird HPD ping pong during modesets. So we can apparently
> > - * end up with HPD going low during a modeset, and then
> > - * going back up soon after. And once that happens we must
> > - * retrain the link to get a picture. That's in case no
> > - * userspace component reacted to intermittent HPD dip.
> > - */
> > int intel_dp_retrain_link(struct intel_encoder *encoder,
> > struct drm_modeset_acquire_ctx *ctx)
> > {
> > @@ -5031,7 +5019,8 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
> > }
> >
> > static int
> > -intel_dp_long_pulse(struct intel_connector *connector)
> > +intel_dp_long_pulse(struct intel_connector *connector,
> > + struct drm_modeset_acquire_ctx *ctx)
> > {
> > struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> > struct intel_dp *intel_dp = intel_attached_dp(>base);
> > @@ -5090,6 +5079,22 @@ intel_dp_long_pulse(struct intel_connector
> > *connector)
> > */
> > status = connector_status_disconnected;
> > goto out;
> > + } else {
> > + /*
> > +* If display is now connected check links status,
> > +* there has been known issues of link loss triggering
> > +* long pulse.
> > +*
> > +* Some sinks (eg. ASUS PB287Q) seem to perform some
> > +* weird HPD ping pong during modesets. So we can apparently
> > +* end up with HPD going low during a modeset, and then
> > +* going back up soon after. And once that happens we must
> > +* retrain the link to get a picture. That's in case no
> > +* userspace component reacted to intermittent HPD dip.
> > +*/
> > + struct intel_encoder *encoder = _to_dig_port(intel_dp)-
> > >base;
> > +
> > + intel_dp_retrain_link(encoder, ctx);
> > }
> >
> > /*
> > @@ -5151,7 +5156,7 @@ intel_dp_detect(struct drm_connector *connector,
> > return ret;
> > }
> >
> > - status = intel_dp_long_pulse(intel_dp->attached_connector);
> > + status = intel_dp_long_pulse(intel_dp->attached_connector,
> > ctx);
> > }
> >
> > intel_dp->detect_done = false;
>
>
--
Cheers,
Lyude Paul
___
Intel-gfx mailing list
[Intel-gfx] ✓ Fi.CI.IGT: success for Enable RGB565 rotation from gen11 onwards
== Series Details == Series: Enable RGB565 rotation from gen11 onwards URL : https://patchwork.freedesktop.org/series/48758/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4706_full -> Patchwork_10020_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_10020_full that come from known issues: === IGT changes === Possible fixes igt@gem_ctx_isolation@bcs0-s3: shard-kbl: INCOMPLETE (fdo#103665) -> PASS igt@kms_flip@flip-vs-expired-vblank-interruptible: shard-glk: FAIL (fdo#102887, fdo#105363) -> PASS fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4706 -> Patchwork_10020 CI_DRM_4706: 6d5687919f3a3426243041b99111b576dd0576d0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4609: 0bc9763af77bbb37f2ed65cc39c398e88db7d8e3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10020: 49a28a97f4718e3dc9d957c11af540afcc2a6024 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10020/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/tracepoints: Remove DRM_I915_LOW_LEVEL_TRACEPOINTS Kconfig option
> Once there is an actual request to have some metrics from vanilla kernels > through some end-user tools (not a developer tool, like here), I'll be glad > to discuss about how to provide the information the best for them in a stable > manner. Sorry for my ignorance, but looks like I don't understand what developer vs. end-user means here. With regard to GPU profiling VTune's end-user is somebody who develops gfx or media applications basing on MediaSDK, OpenCL, C for Media, etc. Or, more often it's an intel application engineer working with those people's code. AE in his\her turn may contact e.g. Dmitry's team if judging by VTune data he\she decides that the problem is on the deeper level of the gfx stack, not in the customer's code. Then Dmitry's team would be experimenting with VTune and deciding if the problem is in their code or it's deeper in i915. Don't think that i915 people use VTune (sadly:)) so here the chain is broken. Otherwise they could e.g. blame HW based on the same data. I'm wondering who in this chain (app developer, AE, Dmitry, i915) is an "end-user" and who's a "developer"? Or is a "developer" a kernel developer only? And e.g. Dmitry is an end-user and thus he is not supposed to use tools like gpuvis or VTune? Looks like all the chain before i915 is annoyed by the kernel-rebuilding requirement. >The interface discussion would probably start from a DRM subsystem level, so >that the tool would have an equivalent level of base experience from all >drivers. That sounds like a solution from an ideal world. I mean if DRM had a uAPI for scheduling observability and all the drivers had to implement this. And the drivers would require info from HW like GuC pointing to the necessity of uAPI support... Would be just great for all the tools (, developers and end-users). But I have no idea what kind of impulse should it be to bring this to reality. And if all the energy available to human kind at the given evolution point would be enough to at least start this. Or am I just too pessimistic? Are there some simple defined steps to be done to make it? Can we build a realistic plan? E.g. is this the first step? - > There's just no Open Source tool to first design and then validate the > interfaces against. There's just the debugging tool which happens to work > currently, without any guarantees that next kernel version would not cause a > substantial rework of the interfacing code. How does it usually work, I mean you can't have a widely shipped open-source consumer already using a non-existent feature that is to be requested? And I can't imagine what kind of existing tool should it be to decide suddenly that it needs to add GPU scheduling tracing to the list of its features. If you want to have a new tool for GPU scheduling timeline - and it sounds like a sane idea, looks like we agree on the use cases etc. - how can you make it open source first and then get the API to be based on from i915? Or am I just missing the point completely? If the open-sourced MediaSDK was shipped with some distro (isn't it, btw?) - would Dmitry be eligible to request observability features for tools? Thank you, Svetlana -Original Message- From: Joonas Lahtinen [mailto:joonas.lahti...@linux.intel.com] Sent: Tuesday, August 21, 2018 3:07 PM To: Intel-gfx@lists.freedesktop.org; Kukanova, Svetlana ; Chris Wilson ; Tvrtko Ursulin ; Tvrtko Ursulin Subject: RE: [Intel-gfx] [PATCH 2/2] drm/i915/tracepoints: Remove DRM_I915_LOW_LEVEL_TRACEPOINTS Kconfig option Quoting Kukanova, Svetlana (2018-08-13 16:44:49) > Joonas, sorry for interfering; could you please explain more regarding > the options for tracing scheduling events better than tracepoints? > After scheduling moves to GuC tools will have to switch to something > like GuC-logging; but while kmd does scheduling isn't kernel-tracing the best > solution? > I know gpuvis is not the only attempt to use tracepoints for the same purpose. > (there're trace.pl and S.E.A. and of course VTune though it probably > is not considered to be existing as it's not open source). > And assuming this movement towards GuC is it not too late to invent a > completely new way to provide tools with scheduling info from kmd? > Could we just improve the existing way and let it live its last years\months? Hi, You actually mentioned the prime reason why we should not go and hastily make tracepoints a stable uAPI with regards to scheduling information. The scheduler's nature will be evolving when some of the scheduling decisions are moved to GuC and the way how we get the information will be changing at that point, so tracepoints will indeed be a very bad mechanism for providing the information. The kernel scheduler is definitely not going anywhere with the introduction of more hardware scheduling capabilities, so it is a misconception to think that the interface would need to be completely different for when GuC is enabled. > >
Re: [Intel-gfx] [PATCH v3 1/2] drm: drm/i915: Add connector property to limit max bpc
On Fri, Aug 24, 2018 at 06:02:16PM -0700, Radhakrishna Sripada wrote:
> At times 12bpc HDMI cannot be driven due to faulty cables, dongles
> level shifters etc. To workaround them we may need to drive the output
> at a lower bpc. Currently the user space does not have a way to limit
> the bpc. The default bpc to be programmed is decided by the driver and
> is run against connector limitations.
>
> Creating a new connector property "max bpc" in order to limit the bpc
> with which the pixels are scanned out. xrandr can make use of this
> connector property to make sure that bpc does not exceed the configured value.
> This property can be used by userspace to set the bpc.
>
> V2: Initialize max_bpc to satisfy kms_properties
> V3: Move the property to drm_connector
>
> Cc: Ville Syrjälä
> Cc: Kishore Kadiyala
> Cc: Rodrigo Vivi
> Cc: Manasi Navare
> Cc: Stanislav Lisovskiy
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/drm_atomic.c| 4
> drivers/gpu/drm/drm_atomic_helper.c | 4
> drivers/gpu/drm/i915/intel_drv.h| 2 ++
> drivers/gpu/drm/i915/intel_hdmi.c | 11 +++
> drivers/gpu/drm/i915/intel_modes.c | 20
Pls move all the i915 stuff to the second patch.
> include/drm/drm_connector.h | 6 ++
> include/drm/drm_mode_config.h | 5 +
> 7 files changed, 52 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
> index 3eb061e11e2e..461dde0c2c10 100644
> --- a/drivers/gpu/drm/drm_atomic.c
> +++ b/drivers/gpu/drm/drm_atomic.c
> @@ -1416,6 +1416,8 @@ static int drm_atomic_connector_set_property(struct
> drm_connector *connector,
>
> return set_out_fence_for_connector(state->state, connector,
> fence_ptr);
> + } else if (property == config->max_bpc_property) {
> + state->max_bpc = val;
> } else if (connector->funcs->atomic_set_property) {
> return connector->funcs->atomic_set_property(connector,
> state, property, val);
> @@ -1511,6 +1513,8 @@ drm_atomic_connector_get_property(struct drm_connector
> *connector,
> *val = 0;
> } else if (property == config->writeback_out_fence_ptr_property) {
> *val = 0;
> + } else if (property == config->max_bpc_property) {
> + *val = state->max_bpc;
> } else if (connector->funcs->atomic_get_property) {
> return connector->funcs->atomic_get_property(connector,
> state, property, val);
> diff --git a/drivers/gpu/drm/drm_atomic_helper.c
> b/drivers/gpu/drm/drm_atomic_helper.c
> index 38ce9a375ffb..82caac8d1432 100644
> --- a/drivers/gpu/drm/drm_atomic_helper.c
> +++ b/drivers/gpu/drm/drm_atomic_helper.c
> @@ -638,6 +638,10 @@ drm_atomic_helper_check_modeset(struct drm_device *dev,
> if (old_connector_state->link_status !=
> new_connector_state->link_status)
> new_crtc_state->connectors_changed = true;
> +
> + if (old_connector_state->max_bpc !=
> + new_connector_state->max_bpc)
> + new_crtc_state->connectors_changed = true;
> }
>
> if (funcs->atomic_check)
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 1b78de838c18..209eb1798238 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1862,6 +1862,8 @@ int intel_ddc_get_modes(struct drm_connector *c, struct
> i2c_adapter *adapter);
> void intel_attach_force_audio_property(struct drm_connector *connector);
> void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
> void intel_attach_aspect_ratio_property(struct drm_connector *connector);
> +void intel_attach_max_bpc_property(struct drm_connector *connector, int min,
> int
> +max);
>
>
> /* intel_overlay.c */
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
> b/drivers/gpu/drm/i915/intel_hdmi.c
> index a1799b5c12bb..82739f342246 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -2097,11 +2097,22 @@ static const struct drm_encoder_funcs
> intel_hdmi_enc_funcs = {
> static void
> intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct
> drm_connector *connector)
> {
> + struct drm_i915_private *dev_priv = to_i915(connector->dev);
> +
> intel_attach_force_audio_property(connector);
> intel_attach_broadcast_rgb_property(connector);
> intel_attach_aspect_ratio_property(connector);
> drm_connector_attach_content_type_property(connector);
> connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
> +
> + if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
> + IS_CHERRYVIEW(dev_priv)) {
> +
[Intel-gfx] ✓ Fi.CI.BAT: success for Enable RGB565 rotation from gen11 onwards
== Series Details ==
Series: Enable RGB565 rotation from gen11 onwards
URL : https://patchwork.freedesktop.org/series/48758/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4706 -> Patchwork_10020 =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_10020 need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10020, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/48758/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_10020:
=== IGT changes ===
Warnings
igt@drv_selftest@live_execlists:
fi-whl-u: SKIP -> PASS +1
{igt@pm_rpm@module-reload}:
fi-cnl-psr: WARN (fdo#107602) -> FAIL
== Known issues ==
Here are the changes found in Patchwork_10020 that come from known issues:
=== IGT changes ===
Issues hit
igt@drv_selftest@live_guc:
fi-skl-guc: NOTRUN -> DMESG-WARN (fdo#107258, fdo#107175)
igt@drv_selftest@live_hangcheck:
fi-skl-guc: NOTRUN -> DMESG-FAIL (fdo#107174)
fi-skl-6600u: PASS -> DMESG-FAIL (fdo#106560, fdo#107174)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
{fi-byt-clapper}: PASS -> INCOMPLETE (fdo#102657)
Possible fixes
igt@drv_selftest@live_hangcheck:
fi-whl-u: DMESG-FAIL (fdo#106560) -> PASS
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
fi-bxt-dsi: INCOMPLETE (fdo#103927) -> PASS
{igt@kms_psr@primary_mmap_gtt}:
fi-cnl-psr: DMESG-WARN -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#102657 https://bugs.freedesktop.org/show_bug.cgi?id=102657
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
fdo#107174 https://bugs.freedesktop.org/show_bug.cgi?id=107174
fdo#107175 https://bugs.freedesktop.org/show_bug.cgi?id=107175
fdo#107258 https://bugs.freedesktop.org/show_bug.cgi?id=107258
fdo#107602 https://bugs.freedesktop.org/show_bug.cgi?id=107602
== Participating hosts (53 -> 48) ==
Additional (1): fi-skl-guc
Missing(6): fi-hsw-4770r fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-ctg-p8600
== Build changes ==
* Linux: CI_DRM_4706 -> Patchwork_10020
CI_DRM_4706: 6d5687919f3a3426243041b99111b576dd0576d0 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4609: 0bc9763af77bbb37f2ed65cc39c398e88db7d8e3 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10020: 49a28a97f4718e3dc9d957c11af540afcc2a6024 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
49a28a97f471 drm/i915: Enable RGB565 90/270 plane rotation for gen11 onwards.
44ee504222cb drm/i915: Move 90/270 rotation validity check into its own function
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10020/issues.html
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/4] drm/i915: preparations for enabling P010, P012, P016 formats
On 27.08.2018 14:28, Maarten Lankhorst wrote:
Op 16-08-18 om 14:55 schreef Juha-Pekka Heikkila:
Preparations for enabling P010, P012 and P016 formats. These
formats will extend NV12 for larger bit depths.
Signed-off-by: Juha-Pekka Heikkila
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_atomic.c | 3 +-
drivers/gpu/drm/i915/intel_atomic_plane.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 46 +++
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 19 ++---
drivers/gpu/drm/i915/intel_sprite.c | 18 +++-
6 files changed, 69 insertions(+), 20 deletions(-)
For patches 2, 3, 4:
Acked-by: Jani Nikula #irc, for merging through
drm-misc-next.
Are you ok with Swati Sharma's comment on patch 4? I can fix it up when
committing.
I'm all ok with Swati Sharma's comment.
/Juha-Pekka
diff --git a/drivers/gpu/drm/i915/intel_atomic.c
b/drivers/gpu/drm/i915/intel_atomic.c
index b04952b..ab76b72 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -334,8 +334,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private
*dev_priv,
/* set scaler mode */
if ((INTEL_GEN(dev_priv) >= 9) &&
plane_state && plane_state->base.fb &&
- plane_state->base.fb->format->format ==
- DRM_FORMAT_NV12) {
+ is_planar_yuv_format(plane_state->base.fb->format->format))
{
if (INTEL_GEN(dev_priv) == 9 &&
!IS_GEMINILAKE(dev_priv) &&
!IS_SKYLAKE(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c
b/drivers/gpu/drm/i915/intel_atomic_plane.c
index dcba645..58b2fc6 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -182,7 +182,7 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
else
crtc_state->active_planes &= ~BIT(intel_plane->id);
- if (state->visible && state->fb->format->format == DRM_FORMAT_NV12)
+ if (state->visible && is_planar_yuv_format(state->fb->format->format))
crtc_state->nv12_planes |= BIT(intel_plane->id);
else
crtc_state->nv12_planes &= ~BIT(intel_plane->id);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 690e1e8..80ce742 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2667,6 +2667,12 @@ int skl_format_to_fourcc(int format, bool rgb_order,
bool alpha)
return DRM_FORMAT_RGB565;
case PLANE_CTL_FORMAT_NV12:
return DRM_FORMAT_NV12;
+ case PLANE_CTL_FORMAT_P010:
+ return DRM_FORMAT_P010;
+ case PLANE_CTL_FORMAT_P012:
+ return DRM_FORMAT_P012;
+ case PLANE_CTL_FORMAT_P016:
+ return DRM_FORMAT_P016;
default:
case PLANE_CTL_FORMAT_XRGB_:
if (rgb_order) {
@@ -3182,7 +3188,7 @@ int skl_check_plane_surface(const struct intel_crtc_state
*crtc_state,
* Handle the AUX surface first since
* the main surface setup depends on it.
*/
- if (fb->format->format == DRM_FORMAT_NV12) {
+ if (is_planar_yuv_format(fb->format->format)) {
ret = skl_check_nv12_surface(crtc_state, plane_state);
if (ret)
return ret;
@@ -3507,6 +3513,12 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
case DRM_FORMAT_NV12:
return PLANE_CTL_FORMAT_NV12;
+ case DRM_FORMAT_P010:
+ return PLANE_CTL_FORMAT_P010;
+ case DRM_FORMAT_P012:
+ return PLANE_CTL_FORMAT_P012;
+ case DRM_FORMAT_P016:
+ return PLANE_CTL_FORMAT_P016;
default:
MISSING_CASE(pixel_format);
}
@@ -4808,8 +4820,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state,
bool force_detach,
need_scaling = src_w != dst_w || src_h != dst_h;
if (plane_scaler_check)
- if (pixel_format == DRM_FORMAT_NV12)
- need_scaling = true;
+ need_scaling = is_planar_yuv_format(pixel_format);
if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
need_scaling = true;
@@ -4850,7 +4861,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state,
bool force_detach,
return 0;
}
- if (plane_scaler_check && pixel_format == DRM_FORMAT_NV12 &&
+ if (plane_scaler_check && is_planar_yuv_format(pixel_format) &&
(src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
DRM_DEBUG_KMS("NV12: src dimensions not met\n");
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable RGB565 rotation from gen11 onwards
== Series Details == Series: Enable RGB565 rotation from gen11 onwards URL : https://patchwork.freedesktop.org/series/48758/ State : warning == Summary == $ dim checkpatch origin/drm-tip 44ee504222cb drm/i915: Move 90/270 rotation validity check into its own function -:12: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #12: v2: (Ville Syrjälä) move all rotation related checks into new function and total: 0 errors, 1 warnings, 0 checks, 95 lines checked 49a28a97f471 drm/i915: Enable RGB565 90/270 plane rotation for gen11 onwards. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915: Enable RGB565 90/270 plane rotation for gen11 onwards.
From gen11 onwards RGB565 90/270 plane rotation is supported on hardware.
IGT: https://patchwork.freedesktop.org/series/48756/
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/intel_atomic_plane.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c
b/drivers/gpu/drm/i915/intel_atomic_plane.c
index 344a16b..c245906 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -123,14 +123,17 @@ static bool intel_plane_valid_rotation(const struct
drm_plane_state *plane_state
}
/*
-* 90/270 is not allowed with RGB64 16:16:16:16,
-* RGB 16-bit 5:6:5, and Indexed 8-bit.
+* 90/270 is not allowed with RGB64 16:16:16:16 and
+* Indexed 8-bit. RGB 16-bit. 5:6:5 is allowed gen11 onwards.
* TBD: Add RGB64 case once its added in supported format
* list.
*/
switch (plane_state->fb->format->format) {
- case DRM_FORMAT_C8:
case DRM_FORMAT_RGB565:
+ if (INTEL_GEN(dev_priv) >= 11)
+ break;
+ /* fall through */
+ case DRM_FORMAT_C8:
DRM_DEBUG_KMS("Unsupported pixel format %s for
90/270!\n",
drm_get_format_name(plane_state->fb->format->format,
_name));
--
2.7.4
___
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[Intel-gfx] [PATCH 0/2] Enable RGB565 rotation from gen11 onwards
These patches enable RGB565 format to be rotated 90 and 270 degrees on gen11 and later. Related changes to IGT here: https://patchwork.freedesktop.org/series/48756/ /Juha-Pekka Juha-Pekka Heikkila (2): drm/i915: Move 90/270 rotation validity check into its own function drm/i915: Enable RGB565 90/270 plane rotation for gen11 onwards. drivers/gpu/drm/i915/intel_atomic_plane.c | 75 ++- 1 file changed, 45 insertions(+), 30 deletions(-) -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915: Move 90/270 rotation validity check into its own function
This makes intel_plane_atomic_check_with_state() generally shorter.
v2: (Ville Syrjälä) move all rotation related checks into new function and
don't pass dev_priv pointer around.
v3: (Ville Syljälä) rename new function.
v4: rebase
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/intel_atomic_plane.c | 66 ++-
1 file changed, 39 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c
b/drivers/gpu/drm/i915/intel_atomic_plane.c
index dcba645..344a16b 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -107,44 +107,34 @@ intel_plane_destroy_state(struct drm_plane *plane,
drm_atomic_helper_plane_destroy_state(plane, state);
}
-int intel_plane_atomic_check_with_state(const struct intel_crtc_state
*old_crtc_state,
- struct intel_crtc_state *crtc_state,
- const struct intel_plane_state
*old_plane_state,
- struct intel_plane_state *intel_state)
+static bool intel_plane_valid_rotation(const struct drm_plane_state
*plane_state)
{
- struct drm_plane *plane = intel_state->base.plane;
- struct drm_i915_private *dev_priv = to_i915(plane->dev);
- struct drm_plane_state *state = _state->base;
- struct intel_plane *intel_plane = to_intel_plane(plane);
- const struct drm_display_mode *adjusted_mode =
- _state->base.adjusted_mode;
- int ret;
+ struct intel_plane *plane = to_intel_plane(plane_state->plane);
+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
- if (!intel_state->base.crtc && !old_plane_state->base.crtc)
- return 0;
-
- if (state->fb && drm_rotation_90_or_270(state->rotation)) {
+ if (plane_state->fb &&
+ drm_rotation_90_or_270(plane_state->rotation)) {
struct drm_format_name_buf format_name;
- if (state->fb->modifier != I915_FORMAT_MOD_Y_TILED &&
- state->fb->modifier != I915_FORMAT_MOD_Yf_TILED) {
+ if (plane_state->fb->modifier != I915_FORMAT_MOD_Y_TILED &&
+ plane_state->fb->modifier != I915_FORMAT_MOD_Yf_TILED) {
DRM_DEBUG_KMS("Y/Yf tiling required for 90/270!\n");
- return -EINVAL;
+ return false;
}
/*
* 90/270 is not allowed with RGB64 16:16:16:16,
* RGB 16-bit 5:6:5, and Indexed 8-bit.
-* TBD: Add RGB64 case once its added in supported format list.
+* TBD: Add RGB64 case once its added in supported format
+* list.
*/
- switch (state->fb->format->format) {
+ switch (plane_state->fb->format->format) {
case DRM_FORMAT_C8:
case DRM_FORMAT_RGB565:
DRM_DEBUG_KMS("Unsupported pixel format %s for
90/270!\n",
-
drm_get_format_name(state->fb->format->format,
- _name));
- return -EINVAL;
-
+
drm_get_format_name(plane_state->fb->format->format,
+ _name));
+ return false;
default:
break;
}
@@ -152,12 +142,34 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
/* CHV ignores the mirror bit when the rotate bit is set :( */
if (IS_CHERRYVIEW(dev_priv) &&
- state->rotation & DRM_MODE_ROTATE_180 &&
- state->rotation & DRM_MODE_REFLECT_X) {
+ plane_state->rotation & DRM_MODE_ROTATE_180 &&
+ plane_state->rotation & DRM_MODE_REFLECT_X) {
DRM_DEBUG_KMS("Cannot rotate and reflect at the same time\n");
- return -EINVAL;
+ return false;
}
+ return true;
+}
+
+int intel_plane_atomic_check_with_state(const struct intel_crtc_state
*old_crtc_state,
+ struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state
*old_plane_state,
+ struct intel_plane_state *intel_state)
+{
+ struct drm_plane *plane = intel_state->base.plane;
+ struct drm_i915_private *dev_priv = to_i915(plane->dev);
+ struct drm_plane_state *state = _state->base;
+ struct intel_plane *intel_plane = to_intel_plane(plane);
+ const struct drm_display_mode *adjusted_mode =
+ _state->base.adjusted_mode;
+ int ret;
+
+ if (!intel_state->base.crtc && !old_plane_state->base.crtc)
+ return 0;
+
+ if
Re: [Intel-gfx] [PATCH v4] drm/i915: Re-apply "Perform link quality check, unconditionally during long pulse"
On Sat, Aug 25, 2018 at 03:10:35PM -0400, Lyude Paul wrote:
> From: Jan-Marek Glogowski
>
> This re-applies the workaround for "some DP sinks, [which] are a
> little nuts" from commit 1a36147bb939 ("drm/i915: Perform link
> quality check unconditionally during long pulse").
> It makes the secondary AOC E2460P monitor connected via DP to an
> acer Veriton N4640G usable again.
>
> This hunk was dropped in commit c85d200e8321 ("drm/i915: Move SST
> DP link retraining into the ->post_hotplug() hook")
>
> Fixes: c85d200e8321 ("drm/i915: Move SST DP link retraining into the
> ->post_hotplug() hook")
> [Cleaned up commit message, added stable cc]
> Signed-off-by: Lyude Paul
> Signed-off-by: Jan-Marek Glogowski
> Cc: sta...@vger.kernel.org
> ---
> Resending this to update patchwork; will push in a little bit
>
> drivers/gpu/drm/i915/intel_dp.c | 33 +++--
> 1 file changed, 19 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index b3f6f04c3c7d..db8515171270 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4333,18 +4333,6 @@ intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
> return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
> }
>
> -/*
> - * If display is now connected check links status,
> - * there has been known issues of link loss triggering
> - * long pulse.
> - *
> - * Some sinks (eg. ASUS PB287Q) seem to perform some
> - * weird HPD ping pong during modesets. So we can apparently
> - * end up with HPD going low during a modeset, and then
> - * going back up soon after. And once that happens we must
> - * retrain the link to get a picture. That's in case no
> - * userspace component reacted to intermittent HPD dip.
> - */
> int intel_dp_retrain_link(struct intel_encoder *encoder,
> struct drm_modeset_acquire_ctx *ctx)
> {
> @@ -5031,7 +5019,8 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
> }
>
> static int
> -intel_dp_long_pulse(struct intel_connector *connector)
> +intel_dp_long_pulse(struct intel_connector *connector,
> + struct drm_modeset_acquire_ctx *ctx)
> {
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct intel_dp *intel_dp = intel_attached_dp(>base);
> @@ -5090,6 +5079,22 @@ intel_dp_long_pulse(struct intel_connector *connector)
>*/
> status = connector_status_disconnected;
> goto out;
> + } else {
> + /*
> + * If display is now connected check links status,
> + * there has been known issues of link loss triggering
> + * long pulse.
> + *
> + * Some sinks (eg. ASUS PB287Q) seem to perform some
> + * weird HPD ping pong during modesets. So we can apparently
> + * end up with HPD going low during a modeset, and then
> + * going back up soon after. And once that happens we must
> + * retrain the link to get a picture. That's in case no
> + * userspace component reacted to intermittent HPD dip.
> + */
> + struct intel_encoder *encoder = _to_dig_port(intel_dp)->base;
> +
> + intel_dp_retrain_link(encoder, ctx);
We should really have a comment here that this is purely duct tape for
sinks that fail to signal a hpd when the link goes bad (either that or
we fail to process the hpd correctly).
I suppose a better way to do this hack would be to do the link quality
check at the end of modeset, or from a delayed work. As is this depends
on userspace/fbdev doing an explicit probe after the modeset which seems
pretty fragile.
> }
>
> /*
> @@ -5151,7 +5156,7 @@ intel_dp_detect(struct drm_connector *connector,
> return ret;
> }
>
> - status = intel_dp_long_pulse(intel_dp->attached_connector);
> + status = intel_dp_long_pulse(intel_dp->attached_connector, ctx);
> }
>
> intel_dp->detect_done = false;
> --
> 2.17.1
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH 2/2] drm/i915: Do not advertize support for NV12 on ICL yet.
On Fri, Aug 24, 2018 at 01:38:56PM -0700, Dhinakaran Pandiyan wrote:
> ICL requires two planes for scanning out a NV12 framebuffer. Do
> not advertize support for creating NV12 framebuffers until required
> plane programming is implemented.
>
> v2: Do not allow adding buffers.
> Check inside skl_plane_has_planar (Ville)
>
> Bspec: Plane Planar YUV programming (18566)
> Cc: Ville Syrjälä
> Cc: Rodrigo Vivi
> Signed-off-by: Dhinakaran Pandiyan
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_display.c | 9 -
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 7e18bd8b21b8..8e4e88eb10e4 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -13622,6 +13622,13 @@ static bool skl_plane_has_fbc(struct
> drm_i915_private *dev_priv,
> bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
> enum pipe pipe, enum plane_id plane_id)
> {
> + /*
> + * FIXME: ICL requires two hardware planes for scanning out NV12
> + * framebuffers. Do not advertize support until this is implemented.
> + */
> + if (INTEL_GEN(dev_priv) >= 11)
> + return false;
> +
> if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
> return false;
>
> @@ -14543,7 +14550,7 @@ static int intel_framebuffer_init(struct
> intel_framebuffer *intel_fb,
> break;
> case DRM_FORMAT_NV12:
> if (INTEL_GEN(dev_priv) < 9 || IS_SKYLAKE(dev_priv) ||
> - IS_BROXTON(dev_priv)) {
> + IS_BROXTON(dev_priv) || INTEL_GEN(dev_priv) >= 11) {
> DRM_DEBUG_KMS("unsupported pixel format: %s\n",
>
> drm_get_format_name(mode_cmd->pixel_format,
> _name));
> --
> 2.17.1
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Clean up skl_plane_has_planar()
On Fri, Aug 24, 2018 at 01:38:55PM -0700, Dhinakaran Pandiyan wrote:
> skl_plane_has_planar is hard to read, simplify the logic by checking for
> support in the order of platform, pipe and plane.
I had a slightly different version of this somewhere. But this one might
be even better.
>
> No change in functionality intended.
>
> Cc: Ville Syrjälä
> Signed-off-by: Dhinakaran Pandiyan
> ---
> drivers/gpu/drm/i915/intel_display.c | 27 +--
> 1 file changed, 9 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 30fdfd1a3037..7e18bd8b21b8 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -13622,24 +13622,15 @@ static bool skl_plane_has_fbc(struct
> drm_i915_private *dev_priv,
> bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
> enum pipe pipe, enum plane_id plane_id)
> {
> - if (plane_id == PLANE_PRIMARY) {
> - if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
> - return false;
> - else if ((INTEL_GEN(dev_priv) == 9 && pipe == PIPE_C) &&
> - !IS_GEMINILAKE(dev_priv))
> - return false;
> - } else if (plane_id >= PLANE_SPRITE0) {
> - if (plane_id == PLANE_CURSOR)
> - return false;
> - if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) == 10) {
> - if (plane_id != PLANE_SPRITE0)
> - return false;
> - } else {
> - if (plane_id != PLANE_SPRITE0 || pipe == PIPE_C ||
> - IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
> - return false;
> - }
> - }
> + if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
> + return false;
> +
> + if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv) && pipe ==
> PIPE_C)
> + return false;
> +
> + if (plane_id == PLANE_CURSOR || plane_id != PLANE_SPRITE0)
> + return false;
The cursor check is rather redundant here. IIRC I put it at the very
start of the function to make it obvious that cursor never supports
this. But we could just as well drop the check entirely.
This also disables NV12 for the primary plane which isn't correct.
> +
> return true;
> }
>
> --
> 2.17.1
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH 11/18] drm/i915: Move skl plane fb related checks into a better place
On Fri, Aug 24, 2018 at 07:56:34PM +, Souza, Jose wrote:
> On Thu, 2018-07-19 at 21:22 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Move the skl+ specific framebuffer related checks from
> > intel_plane_atomic_check_with_state() into a new function
> > (skl_plane_check_fb()) which we'll simply call from the skl
> > plane->check() hook.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/intel_atomic_plane.c | 42
> > drivers/gpu/drm/i915/intel_display.c | 12 --
> > drivers/gpu/drm/i915/intel_sprite.c | 66
> > +++
> > 3 files changed, 66 insertions(+), 54 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c
> > b/drivers/gpu/drm/i915/intel_atomic_plane.c
> > index eddcdd6e4b3b..7c0873060934 100644
> > --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
> > +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
> > @@ -116,40 +116,11 @@ int intel_plane_atomic_check_with_state(const
> > struct intel_crtc_state *old_crtc_
> > struct drm_i915_private *dev_priv = to_i915(plane->dev);
> > struct drm_plane_state *state = _state->base;
> > struct intel_plane *intel_plane = to_intel_plane(plane);
> > - const struct drm_display_mode *adjusted_mode =
> > - _state->base.adjusted_mode;
> > int ret;
> >
> > if (!intel_state->base.crtc && !old_plane_state->base.crtc)
> > return 0;
> >
> > - if (state->fb && drm_rotation_90_or_270(state->rotation)) {
> > - struct drm_format_name_buf format_name;
> > -
> > - if (state->fb->modifier != I915_FORMAT_MOD_Y_TILED &&
> > - state->fb->modifier != I915_FORMAT_MOD_Yf_TILED) {
> > - DRM_DEBUG_KMS("Y/Yf tiling required for
> > 90/270!\n");
> > - return -EINVAL;
> > - }
> > -
> > - /*
> > -* 90/270 is not allowed with RGB64 16:16:16:16,
> > -* RGB 16-bit 5:6:5, and Indexed 8-bit.
> > -* TBD: Add RGB64 case once its added in supported
> > format list.
> > -*/
> > - switch (state->fb->format->format) {
> > - case DRM_FORMAT_C8:
> > - case DRM_FORMAT_RGB565:
> > - DRM_DEBUG_KMS("Unsupported pixel format %s for
> > 90/270!\n",
> > - drm_get_format_name(state->fb-
> > >format->format,
> > - _name)
> > );
> > - return -EINVAL;
> > -
> > - default:
> > - break;
> > - }
> > - }
> > -
> > /* CHV ignores the mirror bit when the rotate bit is set :( */
> > if (IS_CHERRYVIEW(dev_priv) &&
> > state->rotation & DRM_MODE_ROTATE_180 &&
> > @@ -163,19 +134,6 @@ int intel_plane_atomic_check_with_state(const
> > struct intel_crtc_state *old_crtc_
> > if (ret)
> > return ret;
> >
> > - /*
> > -* Y-tiling is not supported in IF-ID Interlace mode in
> > -* GEN9 and above.
> > -*/
> > - if (state->fb && INTEL_GEN(dev_priv) >= 9 && crtc_state-
> > >base.enable &&
> > - adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
> > - if (state->fb->modifier == I915_FORMAT_MOD_Y_TILED ||
> > - state->fb->modifier == I915_FORMAT_MOD_Yf_TILED) {
> > - DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-
> > ID mode\n");
> > - return -EINVAL;
> > - }
> > - }
> > -
> > /* FIXME pre-g4x don't work like this */
> > if (state->visible)
> > crtc_state->active_planes |= BIT(intel_plane->id);
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 9b9eaeda15dd..2381b762d109 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -3151,12 +3151,6 @@ static int skl_check_ccs_aux_surface(struct
> > intel_plane_state *plane_state)
> > int y = src_y / vsub;
> > u32 offset;
> >
> > - if (plane_state->base.rotation & ~(DRM_MODE_ROTATE_0 |
> > DRM_MODE_ROTATE_180)) {
> > - DRM_DEBUG_KMS("RC support only with 0/180 degree
> > rotation %x\n",
> > - plane_state->base.rotation);
> > - return -EINVAL;
> > - }
> > -
> > intel_add_fb_offsets(, , plane_state, 1);
> > offset = intel_plane_compute_aligned_offset(, ,
> > plane_state, 1);
> >
> > @@ -3178,12 +3172,6 @@ int skl_check_plane_surface(const struct
> > intel_crtc_state *crtc_state,
> > plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0,
> > rotation);
> > plane_state->color_plane[1].stride = intel_fb_pitch(fb, 1,
> > rotation);
> >
> > - if (rotation & DRM_MODE_REFLECT_X &&
> > - fb->modifier == DRM_FORMAT_MOD_LINEAR) {
> > - DRM_DEBUG_KMS("horizontal flip is not supported with
> > linear surface formats\n");
> > - return -EINVAL;
> > - }
> > -
Re: [Intel-gfx] [PATCH 3/4] drm/i915: preparations for enabling P010, P012, P016 formats
Op 16-08-18 om 14:55 schreef Juha-Pekka Heikkila:
> Preparations for enabling P010, P012 and P016 formats. These
> formats will extend NV12 for larger bit depths.
>
> Signed-off-by: Juha-Pekka Heikkila
> Reviewed-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/intel_atomic.c | 3 +-
> drivers/gpu/drm/i915/intel_atomic_plane.c | 2 +-
> drivers/gpu/drm/i915/intel_display.c | 46
> +++
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 19 ++---
> drivers/gpu/drm/i915/intel_sprite.c | 18 +++-
> 6 files changed, 69 insertions(+), 20 deletions(-)
For patches 2, 3, 4:
Acked-by: Jani Nikula #irc, for merging through
drm-misc-next.
Are you ok with Swati Sharma's comment on patch 4? I can fix it up when
committing.
> diff --git a/drivers/gpu/drm/i915/intel_atomic.c
> b/drivers/gpu/drm/i915/intel_atomic.c
> index b04952b..ab76b72 100644
> --- a/drivers/gpu/drm/i915/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/intel_atomic.c
> @@ -334,8 +334,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private
> *dev_priv,
> /* set scaler mode */
> if ((INTEL_GEN(dev_priv) >= 9) &&
> plane_state && plane_state->base.fb &&
> - plane_state->base.fb->format->format ==
> - DRM_FORMAT_NV12) {
> + is_planar_yuv_format(plane_state->base.fb->format->format))
> {
> if (INTEL_GEN(dev_priv) == 9 &&
> !IS_GEMINILAKE(dev_priv) &&
> !IS_SKYLAKE(dev_priv))
> diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c
> b/drivers/gpu/drm/i915/intel_atomic_plane.c
> index dcba645..58b2fc6 100644
> --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
> @@ -182,7 +182,7 @@ int intel_plane_atomic_check_with_state(const struct
> intel_crtc_state *old_crtc_
> else
> crtc_state->active_planes &= ~BIT(intel_plane->id);
>
> - if (state->visible && state->fb->format->format == DRM_FORMAT_NV12)
> + if (state->visible && is_planar_yuv_format(state->fb->format->format))
> crtc_state->nv12_planes |= BIT(intel_plane->id);
> else
> crtc_state->nv12_planes &= ~BIT(intel_plane->id);
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 690e1e8..80ce742 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2667,6 +2667,12 @@ int skl_format_to_fourcc(int format, bool rgb_order,
> bool alpha)
> return DRM_FORMAT_RGB565;
> case PLANE_CTL_FORMAT_NV12:
> return DRM_FORMAT_NV12;
> + case PLANE_CTL_FORMAT_P010:
> + return DRM_FORMAT_P010;
> + case PLANE_CTL_FORMAT_P012:
> + return DRM_FORMAT_P012;
> + case PLANE_CTL_FORMAT_P016:
> + return DRM_FORMAT_P016;
> default:
> case PLANE_CTL_FORMAT_XRGB_:
> if (rgb_order) {
> @@ -3182,7 +3188,7 @@ int skl_check_plane_surface(const struct
> intel_crtc_state *crtc_state,
>* Handle the AUX surface first since
>* the main surface setup depends on it.
>*/
> - if (fb->format->format == DRM_FORMAT_NV12) {
> + if (is_planar_yuv_format(fb->format->format)) {
> ret = skl_check_nv12_surface(crtc_state, plane_state);
> if (ret)
> return ret;
> @@ -3507,6 +3513,12 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
> return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
> case DRM_FORMAT_NV12:
> return PLANE_CTL_FORMAT_NV12;
> + case DRM_FORMAT_P010:
> + return PLANE_CTL_FORMAT_P010;
> + case DRM_FORMAT_P012:
> + return PLANE_CTL_FORMAT_P012;
> + case DRM_FORMAT_P016:
> + return PLANE_CTL_FORMAT_P016;
> default:
> MISSING_CASE(pixel_format);
> }
> @@ -4808,8 +4820,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state,
> bool force_detach,
> need_scaling = src_w != dst_w || src_h != dst_h;
>
> if (plane_scaler_check)
> - if (pixel_format == DRM_FORMAT_NV12)
> - need_scaling = true;
> + need_scaling = is_planar_yuv_format(pixel_format);
>
> if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
> need_scaling = true;
> @@ -4850,7 +4861,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state,
> bool force_detach,
> return 0;
> }
>
> - if (plane_scaler_check && pixel_format == DRM_FORMAT_NV12 &&
> + if (plane_scaler_check && is_planar_yuv_format(pixel_format) &&
> (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
> DRM_DEBUG_KMS("NV12: src dimensions not met\n");
> return
Re: [Intel-gfx] [PATCH 3/4] drm/i915: preparations for enabling P010, P012, P016 formats
On 21.08.2018 17:26, Sharma, Swati2 wrote:
On 16-Aug-18 6:25 PM, Juha-Pekka Heikkila wrote:
Preparations for enabling P010, P012 and P016 formats. These
formats will extend NV12 for larger bit depths.
Signed-off-by: Juha-Pekka Heikkila
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_atomic.c | 3 +-
drivers/gpu/drm/i915/intel_atomic_plane.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 46
+++
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 19 ++---
drivers/gpu/drm/i915/intel_sprite.c | 18 +++-
6 files changed, 69 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_atomic.c
b/drivers/gpu/drm/i915/intel_atomic.c
index b04952b..ab76b72 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -334,8 +334,7 @@ int intel_atomic_setup_scalers(struct
drm_i915_private *dev_priv,
/* set scaler mode */
if ((INTEL_GEN(dev_priv) >= 9) &&
plane_state && plane_state->base.fb &&
- plane_state->base.fb->format->format ==
- DRM_FORMAT_NV12) {
+
is_planar_yuv_format(plane_state->base.fb->format->format)) {
if (INTEL_GEN(dev_priv) == 9 &&
!IS_GEMINILAKE(dev_priv) &&
!IS_SKYLAKE(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c
b/drivers/gpu/drm/i915/intel_atomic_plane.c
index dcba645..58b2fc6 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -182,7 +182,7 @@ int intel_plane_atomic_check_with_state(const
struct intel_crtc_state *old_crtc_
else
crtc_state->active_planes &= ~BIT(intel_plane->id);
- if (state->visible && state->fb->format->format == DRM_FORMAT_NV12)
+ if (state->visible &&
is_planar_yuv_format(state->fb->format->format))
crtc_state->nv12_planes |= BIT(intel_plane->id);
else
crtc_state->nv12_planes &= ~BIT(intel_plane->id);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 690e1e8..80ce742 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2667,6 +2667,12 @@ int skl_format_to_fourcc(int format, bool
rgb_order, bool alpha)
return DRM_FORMAT_RGB565;
case PLANE_CTL_FORMAT_NV12:
return DRM_FORMAT_NV12;
+ case PLANE_CTL_FORMAT_P010:
+ return DRM_FORMAT_P010;
+ case PLANE_CTL_FORMAT_P012:
+ return DRM_FORMAT_P012;
+ case PLANE_CTL_FORMAT_P016:
+ return DRM_FORMAT_P016;
default:
case PLANE_CTL_FORMAT_XRGB_:
if (rgb_order) {
@@ -3182,7 +3188,7 @@ int skl_check_plane_surface(const struct
intel_crtc_state *crtc_state,
* Handle the AUX surface first since
* the main surface setup depends on it.
*/
- if (fb->format->format == DRM_FORMAT_NV12) {
+ if (is_planar_yuv_format(fb->format->format)) {
ret = skl_check_nv12_surface(crtc_state, plane_state);
if (ret)
return ret;
@@ -3507,6 +3513,12 @@ static u32 skl_plane_ctl_format(uint32_t
pixel_format)
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
case DRM_FORMAT_NV12:
return PLANE_CTL_FORMAT_NV12;
+ case DRM_FORMAT_P010:
+ return PLANE_CTL_FORMAT_P010;
+ case DRM_FORMAT_P012:
+ return PLANE_CTL_FORMAT_P012;
+ case DRM_FORMAT_P016:
+ return PLANE_CTL_FORMAT_P016;
default:
MISSING_CASE(pixel_format);
}
@@ -4808,8 +4820,7 @@ skl_update_scaler(struct intel_crtc_state
*crtc_state, bool force_detach,
need_scaling = src_w != dst_w || src_h != dst_h;
if (plane_scaler_check)
- if (pixel_format == DRM_FORMAT_NV12)
- need_scaling = true;
+ need_scaling = is_planar_yuv_format(pixel_format);
if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
need_scaling = true;
@@ -4850,7 +4861,7 @@ skl_update_scaler(struct intel_crtc_state
*crtc_state, bool force_detach,
return 0;
}
- if (plane_scaler_check && pixel_format == DRM_FORMAT_NV12 &&
+ if (plane_scaler_check && is_planar_yuv_format(pixel_format) &&
(src_h < SKL_MIN_YUV_420_SRC_H || src_w <
SKL_MIN_YUV_420_SRC_W)) {
DRM_DEBUG_KMS("NV12: src dimensions not met\n");
return -EINVAL;
@@ -4955,6 +4966,9 @@ static int skl_update_scaler_plane(struct
intel_crtc_state *crtc_state,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_P010:
+ case DRM_FORMAT_P012:
+ case DRM_FORMAT_P016:
break;
default:
DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling
format 0x%x\n",
@@ -13179,7 +13193,7 @@ skl_max_scale(struct intel_crtc *intel_crtc,
* or
* cdclk/crtc_clock
Re: [Intel-gfx] [PATCH v4] drm/i915: Re-apply "Perform link quality check, unconditionally during long pulse"
On Sat, 25 Aug 2018, Lyude Paul wrote:
> From: Jan-Marek Glogowski
>
> This re-applies the workaround for "some DP sinks, [which] are a
> little nuts" from commit 1a36147bb939 ("drm/i915: Perform link
> quality check unconditionally during long pulse").
> It makes the secondary AOC E2460P monitor connected via DP to an
> acer Veriton N4640G usable again.
>
> This hunk was dropped in commit c85d200e8321 ("drm/i915: Move SST
> DP link retraining into the ->post_hotplug() hook")
>
> Fixes: c85d200e8321 ("drm/i915: Move SST DP link retraining into the
> ->post_hotplug() hook")
> [Cleaned up commit message, added stable cc]
> Signed-off-by: Lyude Paul
> Signed-off-by: Jan-Marek Glogowski
> Cc: sta...@vger.kernel.org
> ---
> Resending this to update patchwork; will push in a little bit
Is there a bugzilla? Reference to a list discussion? Something with a
dmesg where someone can actually verify this is the right fix?
IMO needs an ack from Ville too. He should be in Cc: in the first place
as the author of the regressing commit.
'dim fixes c85d200e8321' gives you the output:
Fixes: c85d200e8321 ("drm/i915: Move SST DP link retraining into the
->post_hotplug() hook")
Cc: Manasi Navare
Cc: Maarten Lankhorst
Cc: Ville Syrjälä
Cc: Lyude Paul
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: intel-gfx@lists.freedesktop.org
Cc: # v4.17+
BR,
Jani.
>
> drivers/gpu/drm/i915/intel_dp.c | 33 +++--
> 1 file changed, 19 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index b3f6f04c3c7d..db8515171270 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4333,18 +4333,6 @@ intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
> return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
> }
>
> -/*
> - * If display is now connected check links status,
> - * there has been known issues of link loss triggering
> - * long pulse.
> - *
> - * Some sinks (eg. ASUS PB287Q) seem to perform some
> - * weird HPD ping pong during modesets. So we can apparently
> - * end up with HPD going low during a modeset, and then
> - * going back up soon after. And once that happens we must
> - * retrain the link to get a picture. That's in case no
> - * userspace component reacted to intermittent HPD dip.
> - */
> int intel_dp_retrain_link(struct intel_encoder *encoder,
> struct drm_modeset_acquire_ctx *ctx)
> {
> @@ -5031,7 +5019,8 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
> }
>
> static int
> -intel_dp_long_pulse(struct intel_connector *connector)
> +intel_dp_long_pulse(struct intel_connector *connector,
> + struct drm_modeset_acquire_ctx *ctx)
> {
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct intel_dp *intel_dp = intel_attached_dp(>base);
> @@ -5090,6 +5079,22 @@ intel_dp_long_pulse(struct intel_connector *connector)
>*/
> status = connector_status_disconnected;
> goto out;
> + } else {
> + /*
> + * If display is now connected check links status,
> + * there has been known issues of link loss triggering
> + * long pulse.
> + *
> + * Some sinks (eg. ASUS PB287Q) seem to perform some
> + * weird HPD ping pong during modesets. So we can apparently
> + * end up with HPD going low during a modeset, and then
> + * going back up soon after. And once that happens we must
> + * retrain the link to get a picture. That's in case no
> + * userspace component reacted to intermittent HPD dip.
> + */
> + struct intel_encoder *encoder = _to_dig_port(intel_dp)->base;
> +
> + intel_dp_retrain_link(encoder, ctx);
> }
>
> /*
> @@ -5151,7 +5156,7 @@ intel_dp_detect(struct drm_connector *connector,
> return ret;
> }
>
> - status = intel_dp_long_pulse(intel_dp->attached_connector);
> + status = intel_dp_long_pulse(intel_dp->attached_connector, ctx);
> }
>
> intel_dp->detect_done = false;
--
Jani Nikula, Intel Open Source Graphics Center
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for Enable Y210, Y212, Y216 formats for ICL
== Series Details == Series: Enable Y210, Y212, Y216 formats for ICL URL : https://patchwork.freedesktop.org/series/48729/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4706_full -> Patchwork_10019_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_10019_full that come from known issues: === IGT changes === Issues hit igt@drv_suspend@shrink: shard-glk: PASS -> INCOMPLETE (fdo#106886, k.org#198133, fdo#103359) igt@gem_exec_big: shard-hsw: PASS -> INCOMPLETE (fdo#103540) igt@kms_setmode@basic: shard-kbl: PASS -> FAIL (fdo#99912) Possible fixes igt@gem_ctx_isolation@bcs0-s3: shard-kbl: INCOMPLETE (fdo#103665) -> PASS igt@kms_flip@flip-vs-expired-vblank-interruptible: shard-glk: FAIL (fdo#105363, fdo#102887) -> PASS fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4706 -> Patchwork_10019 CI_DRM_4706: 6d5687919f3a3426243041b99111b576dd0576d0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4609: 0bc9763af77bbb37f2ed65cc39c398e88db7d8e3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10019: ff10f4e6686cf96d938487319a831907cc81227c @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10019/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/4] drm/i915: Enable Y210, Y212, Y216 format for primary and sprite planes
On 8/27/2018 12:17 PM, Swati Sharma wrote:
From: Vidya Srinivas
In this patch, a list for icl specific pixel formats is created
in which Y210, Y212 and Y216 pixel formats are added along with
legacy pixel formats for primary and sprite plane.
Signed-off-by: Swati Sharma
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/intel_display.c | 25 +++--
drivers/gpu/drm/i915/intel_sprite.c | 22 --
2 files changed, 43 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 91aa8cc..30065e3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -104,6 +104,24 @@
DRM_FORMAT_NV12,
};
+static const uint32_t icl_primary_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_Y210,
+ DRM_FORMAT_Y212,
+ DRM_FORMAT_Y216,
+};
+
static const uint64_t skl_format_modifiers_noccs[] = {
I915_FORMAT_MOD_Yf_TILED,
I915_FORMAT_MOD_Y_TILED,
@@ -13718,8 +13736,11 @@ bool skl_plane_has_planar(struct drm_i915_private
*dev_priv,
if (INTEL_GEN(dev_priv) >= 9) {
primary->has_ccs = skl_plane_has_ccs(dev_priv, pipe,
PLANE_PRIMARY);
-
- if (skl_plane_has_planar(dev_priv, pipe, PLANE_PRIMARY)) {
+ if (INTEL_GEN(dev_priv) >= 11) {
+ intel_primary_formats = icl_primary_formats;
+ num_formats = ARRAY_SIZE(icl_primary_formats);
+ } else if (skl_plane_has_planar(dev_priv, pipe,
+ PLANE_PRIMARY)) {
intel_primary_formats = skl_pri_planar_formats;
num_formats = ARRAY_SIZE(skl_pri_planar_formats);
} else {
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 417501f..2abdd85 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1281,6 +1281,21 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device
*dev, void *data,
DRM_FORMAT_NV12,
};
+static uint32_t icl_plane_formats[] = {
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_Y210,
+ DRM_FORMAT_Y212,
+ DRM_FORMAT_Y216,
+};
+
static const uint64_t skl_plane_format_modifiers_noccs[] = {
I915_FORMAT_MOD_Yf_TILED,
I915_FORMAT_MOD_Y_TILED,
@@ -1536,8 +1551,11 @@ struct intel_plane *
intel_plane->disable_plane = skl_disable_plane;
intel_plane->get_hw_state = skl_plane_get_hw_state;
- if (skl_plane_has_planar(dev_priv, pipe,
-PLANE_SPRITE0 + plane)) {
+ if (INTEL_GEN(dev_priv) >= 11) {
+ plane_formats = icl_plane_formats;
+ num_plane_formats = ARRAY_SIZE(icl_plane_formats);
64 bits pixel formats are supported only with HDR planes.
-Mahesh
+ } else if (skl_plane_has_planar(dev_priv, pipe,
+ PLANE_SPRITE0 + plane)) {
plane_formats = skl_planar_formats;
num_plane_formats = ARRAY_SIZE(skl_planar_formats);
} else {
___
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Re: [Intel-gfx] [PATCH 3/4] drm/i915: Preparations for enabling Y210, Y212, Y216 formats
Hi,
On 8/27/2018 12:17 PM, Swati Sharma wrote:
From: Vidya Srinivas
Signed-off-by: Swati Sharma
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/intel_display.c | 15 +++
drivers/gpu/drm/i915/intel_sprite.c | 3 +++
2 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 30fdfd1..91aa8cc 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3511,6 +3511,12 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
case DRM_FORMAT_NV12:
return PLANE_CTL_FORMAT_NV12;
+ case DRM_FORMAT_Y210:
+ return PLANE_CTL_FORMAT_Y210;
+ case DRM_FORMAT_Y212:
+ return PLANE_CTL_FORMAT_Y212;
+ case DRM_FORMAT_Y216:
+ return PLANE_CTL_FORMAT_Y216;
While programming YUV pixel format, you also need to program order of
samples in bits [17:16]
BTW 64 bits pixel format are not supported in all the planes, these are
supported only in HDR planes.
You should handle that as well.
-Mahesh
default:
MISSING_CASE(pixel_format);
}
@@ -4959,6 +4965,9 @@ static int skl_update_scaler_plane(struct
intel_crtc_state *crtc_state,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_Y210:
+ case DRM_FORMAT_Y212:
+ case DRM_FORMAT_Y216:
break;
default:
DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format
0x%x\n",
@@ -13413,6 +13422,9 @@ static bool skl_plane_format_mod_supported(struct
drm_plane *_plane,
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
+ case DRM_FORMAT_Y210:
+ case DRM_FORMAT_Y212:
+ case DRM_FORMAT_Y216:
case DRM_FORMAT_NV12:
if (modifier == I915_FORMAT_MOD_Yf_TILED)
return true;
@@ -14544,6 +14556,9 @@ static int intel_framebuffer_init(struct
intel_framebuffer *intel_fb,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_YVYU:
case DRM_FORMAT_VYUY:
+ case DRM_FORMAT_Y210:
+ case DRM_FORMAT_Y212:
+ case DRM_FORMAT_Y216:
if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
DRM_DEBUG_KMS("unsupported pixel format: %s\n",
drm_get_format_name(mode_cmd->pixel_format,
_name));
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index c286dda..417501f 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1419,6 +1419,9 @@ static bool skl_plane_format_mod_supported(struct
drm_plane *_plane,
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
+ case DRM_FORMAT_Y210:
+ case DRM_FORMAT_Y212:
+ case DRM_FORMAT_Y216:
case DRM_FORMAT_NV12:
if (modifier == I915_FORMAT_MOD_Yf_TILED)
return true;
___
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Re: [Intel-gfx] [PATCH 1/4] drm: Add Y210, Y212, Y216 format definitions and fourcc
On 8/27/2018 12:47 PM, Kumar, Mahesh wrote:
Hi,
On 8/27/2018 12:17 PM, Swati Sharma wrote:
From: Vidya Srinivas
The following pixel formats are packed format that follows 4:2:2
chroma sampling. For memory represenation each component is
allocated 16 bits each. Thus each pixel occupies a DWORD.
Y210: Valid data occupies MSB 10 bits.
LSB 6 bits are filled with zeroes.
Y212: Valid data occupies MSB 12 bits.
LSB 4 bits are filled with zeroes.
Y216: Valid data occupies 16 bits,
doesn't require any padding bits.
First 16 bits stores the Y value and the next 16 bits stores one
of the chroma samples alternatively. The first luma sample will
be accompanied by first U sample and second luma sample is
accompanied by the first V sample.
Signed-off-by: Swati Sharma
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/drm_fourcc.c | 3 +++
include/uapi/drm/drm_fourcc.h | 4
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 35c1e27..4bf04a5 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -173,6 +173,9 @@ const struct drm_format_info
*__drm_format_info(u32 format)
{ .format = DRM_FORMAT_UYVY, .depth = 0, .num_planes
= 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_VYUY, .depth = 0, .num_planes
= 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_AYUV, .depth = 0, .num_planes
= 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true,
.is_yuv = true },
+ { .format = DRM_FORMAT_Y210, .depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1 },
+ { .format = DRM_FORMAT_Y212, .depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1 },
+ { .format = DRM_FORMAT_Y216, .depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1 },
};
you should also set is_yuv to true.
Apart from this there can be different order for YUV samples, Are you
going to add those as well?
-Mahesh
unsigned int i;
diff --git a/include/uapi/drm/drm_fourcc.h
b/include/uapi/drm/drm_fourcc.h
index 2ed46e9..6a03e6d 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -149,6 +149,10 @@
#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /*
[31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
+#define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /*
[63:0] Y0:Cb0:Y1:Cr1 10:10:10:10 little endian */
+#define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /*
[63:0] Y0:Cb0:Y1:Cr1 12:12:12:12 little endian */
+#define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /*
[63:0] Y0:Cb0:Y1:Cr1 16:16:16:16 little endian */
+
/*
* 2 plane RGB + A
* index 0 = RGB plane, same format as the corresponding non _A8
format has
___
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Re: [Intel-gfx] [PATCH] mm, oom: distinguish blockable mode for mmu notifiers
Am 26.08.2018 um 10:40 schrieb Tetsuo Handa:
On 2018/08/24 22:52, Michal Hocko wrote:
@@ -180,11 +180,15 @@ void amdgpu_mn_unlock(struct amdgpu_mn *mn)
*/
static int amdgpu_mn_read_lock(struct amdgpu_mn *amn, bool blockable)
{
- if (blockable)
- mutex_lock(>read_lock);
- else if (!mutex_trylock(>read_lock))
- return -EAGAIN;
-
+ /*
+* We can take sleepable lock even on !blockable mode because
+* read_lock is only ever take from this path and the notifier
+* lock never really sleeps. In fact the only reason why the
+* later is sleepable is because the notifier itself might sleep
+* in amdgpu_mn_invalidate_node but blockable mode is handled
+* before calling into that path.
+*/
+ mutex_lock(>read_lock);
if (atomic_inc_return(>recursion) == 1)
down_read_non_owner(>lock);
mutex_unlock(>read_lock);
I'm not following. Why don't we need to do like below (given that
nobody except amdgpu_mn_read_lock() holds ->read_lock) because e.g.
drm_sched_fence_create() from drm_sched_job_init() from amdgpu_cs_submit()
is doing GFP_KERNEL memory allocation with ->lock held for write?
That's a bug which needs to be fixed separately.
Allocating memory with GFP_KERNEL while holding a lock which is also
taken in the reclaim code path is illegal not matter what you do.
Patches to fix this are already on the appropriate mailing list and will
be pushed upstream today.
Regards,
Christian.
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
index e55508b..e1cb344 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
@@ -64,8 +64,6 @@
* @node: hash table node to find structure by adev and mn
* @lock: rw semaphore protecting the notifier nodes
* @objects: interval tree containing amdgpu_mn_nodes
- * @read_lock: mutex for recursive locking of @lock
- * @recursion: depth of recursion
*
* Data for each amdgpu device and process address space.
*/
@@ -85,8 +83,6 @@ struct amdgpu_mn {
/* objects protected by lock */
struct rw_semaphore lock;
struct rb_root_cached objects;
- struct mutexread_lock;
- atomic_trecursion;
};
/**
@@ -181,14 +177,9 @@ void amdgpu_mn_unlock(struct amdgpu_mn *mn)
static int amdgpu_mn_read_lock(struct amdgpu_mn *amn, bool blockable)
{
if (blockable)
- mutex_lock(>read_lock);
- else if (!mutex_trylock(>read_lock))
+ down_read(>lock);
+ else if (!down_read_trylock(>lock))
return -EAGAIN;
-
- if (atomic_inc_return(>recursion) == 1)
- down_read_non_owner(>lock);
- mutex_unlock(>read_lock);
-
return 0;
}
@@ -199,8 +190,7 @@ static int amdgpu_mn_read_lock(struct amdgpu_mn *amn, bool blockable)
*/
static void amdgpu_mn_read_unlock(struct amdgpu_mn *amn)
{
- if (atomic_dec_return(>recursion) == 0)
- up_read_non_owner(>lock);
+ up_read(>lock);
}
/**
@@ -410,8 +400,6 @@ struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev,
amn->type = type;
amn->mn.ops = _mn_ops[type];
amn->objects = RB_ROOT_CACHED;
- mutex_init(>read_lock);
- atomic_set(>recursion, 0);
r = __mmu_notifier_register(>mn, mm);
if (r)
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Re: [Intel-gfx] [PATCH 2/4] drm/i915: Add Y210, Y212, Y216 plane control definitions
Hi,
Please include platform name in subject line:
On 8/27/2018 12:17 PM, Swati Sharma wrote:
From: Vidya Srinivas
Added needed plane control flag definitions for Y210, Y212 and
Y216 formats.
may be, add more info in commit message
-Mahesh
Signed-off-by: Swati Sharma
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8534f88..926e42d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6504,6 +6504,9 @@ enum {
#define PLANE_CTL_FORMAT_RGB_565(14 << 24)
#define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23)
#define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) /* Pre-GLK */
+#define PLANE_CTL_FORMAT_Y210(1 << 23)
+#define PLANE_CTL_FORMAT_Y212(3 << 23)
+#define PLANE_CTL_FORMAT_Y216(5 << 23)
#define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21)
#define PLANE_CTL_KEY_ENABLE_SOURCE (1 << 21)
#define PLANE_CTL_KEY_ENABLE_DESTINATION(2 << 21)
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[Intel-gfx] ✓ Fi.CI.BAT: success for Enable Y210, Y212, Y216 formats for ICL
== Series Details ==
Series: Enable Y210, Y212, Y216 formats for ICL
URL : https://patchwork.freedesktop.org/series/48729/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4706 -> Patchwork_10019 =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_10019 need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10019, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/48729/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_10019:
=== IGT changes ===
Warnings
igt@drv_selftest@live_execlists:
fi-whl-u: SKIP -> PASS +1
{igt@kms_psr@primary_page_flip}:
fi-cnl-psr: DMESG-WARN -> DMESG-FAIL
== Known issues ==
Here are the changes found in Patchwork_10019 that come from known issues:
=== IGT changes ===
Issues hit
igt@drv_selftest@live_guc:
fi-skl-guc: NOTRUN -> DMESG-WARN (fdo#107175, fdo#107258)
Possible fixes
igt@drv_selftest@live_hangcheck:
fi-whl-u: DMESG-FAIL (fdo#106560) -> PASS
igt@gem_exec_suspend@basic-s3:
fi-blb-e6850: INCOMPLETE -> PASS
{igt@pm_rpm@module-reload}:
fi-cnl-psr: WARN (fdo#107602) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
fdo#107175 https://bugs.freedesktop.org/show_bug.cgi?id=107175
fdo#107258 https://bugs.freedesktop.org/show_bug.cgi?id=107258
fdo#107602 https://bugs.freedesktop.org/show_bug.cgi?id=107602
== Participating hosts (53 -> 49) ==
Additional (1): fi-skl-guc
Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4706 -> Patchwork_10019
CI_DRM_4706: 6d5687919f3a3426243041b99111b576dd0576d0 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4609: 0bc9763af77bbb37f2ed65cc39c398e88db7d8e3 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10019: ff10f4e6686cf96d938487319a831907cc81227c @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
ff10f4e6686c drm/i915: Enable Y210, Y212, Y216 format for primary and sprite
planes
b21269a9abdb drm/i915: Preparations for enabling Y210, Y212, Y216 formats
c5c4436ab3aa drm/i915: Add Y210, Y212, Y216 plane control definitions
c9d04d7941bb drm: Add Y210, Y212, Y216 format definitions and fourcc
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10019/issues.html
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Re: [Intel-gfx] [PATCH 1/4] drm: Add Y210, Y212, Y216 format definitions and fourcc
Hi,
On 8/27/2018 12:17 PM, Swati Sharma wrote:
From: Vidya Srinivas
The following pixel formats are packed format that follows 4:2:2
chroma sampling. For memory represenation each component is
allocated 16 bits each. Thus each pixel occupies a DWORD.
Y210: Valid data occupies MSB 10 bits.
LSB 6 bits are filled with zeroes.
Y212: Valid data occupies MSB 12 bits.
LSB 4 bits are filled with zeroes.
Y216: Valid data occupies 16 bits,
doesn't require any padding bits.
First 16 bits stores the Y value and the next 16 bits stores one
of the chroma samples alternatively. The first luma sample will
be accompanied by first U sample and second luma sample is
accompanied by the first V sample.
Signed-off-by: Swati Sharma
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/drm_fourcc.c | 3 +++
include/uapi/drm/drm_fourcc.h | 4
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 35c1e27..4bf04a5 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -173,6 +173,9 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_UYVY,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_VYUY,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_AYUV,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true,
.is_yuv = true },
+ { .format = DRM_FORMAT_Y210,.depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1 },
+ { .format = DRM_FORMAT_Y212,.depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1 },
+ { .format = DRM_FORMAT_Y216,.depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1 },
};
you should also set is_yuv to true.
-Mahesh
unsigned int i;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 2ed46e9..6a03e6d 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -149,6 +149,10 @@
#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
+#define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Y0:Cb0:Y1:Cr1 10:10:10:10 little endian */
+#define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0]
Y0:Cb0:Y1:Cr1 12:12:12:12 little endian */
+#define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0]
Y0:Cb0:Y1:Cr1 16:16:16:16 little endian */
+
/*
* 2 plane RGB + A
* index 0 = RGB plane, same format as the corresponding non _A8 format has
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable Y210, Y212, Y216 formats for ICL
== Series Details ==
Series: Enable Y210, Y212, Y216 formats for ICL
URL : https://patchwork.freedesktop.org/series/48729/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c9d04d7941bb drm: Add Y210, Y212, Y216 format definitions and fourcc
-:33: WARNING:LONG_LINE: line over 100 characters
#33: FILE: drivers/gpu/drm/drm_fourcc.c:176:
+ { .format = DRM_FORMAT_Y210,.depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1 },
-:34: WARNING:LONG_LINE: line over 100 characters
#34: FILE: drivers/gpu/drm/drm_fourcc.c:177:
+ { .format = DRM_FORMAT_Y212,.depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1 },
-:35: WARNING:LONG_LINE: line over 100 characters
#35: FILE: drivers/gpu/drm/drm_fourcc.c:178:
+ { .format = DRM_FORMAT_Y216,.depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1 },
-:47: WARNING:LONG_LINE_COMMENT: line over 100 characters
#47: FILE: include/uapi/drm/drm_fourcc.h:152:
+#define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0]
Y0:Cb0:Y1:Cr1 10:10:10:10 little endian */
-:48: WARNING:LONG_LINE_COMMENT: line over 100 characters
#48: FILE: include/uapi/drm/drm_fourcc.h:153:
+#define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0]
Y0:Cb0:Y1:Cr1 12:12:12:12 little endian */
-:49: WARNING:LONG_LINE_COMMENT: line over 100 characters
#49: FILE: include/uapi/drm/drm_fourcc.h:154:
+#define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0]
Y0:Cb0:Y1:Cr1 16:16:16:16 little endian */
total: 0 errors, 6 warnings, 0 checks, 19 lines checked
c5c4436ab3aa drm/i915: Add Y210, Y212, Y216 plane control definitions
b21269a9abdb drm/i915: Preparations for enabling Y210, Y212, Y216 formats
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
total: 0 errors, 1 warnings, 0 checks, 48 lines checked
ff10f4e6686c drm/i915: Enable Y210, Y212, Y216 format for primary and sprite
planes
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[Intel-gfx] [PATCH 3/4] drm/i915: Preparations for enabling Y210, Y212, Y216 formats
From: Vidya Srinivas
Signed-off-by: Swati Sharma
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/intel_display.c | 15 +++
drivers/gpu/drm/i915/intel_sprite.c | 3 +++
2 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 30fdfd1..91aa8cc 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3511,6 +3511,12 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
case DRM_FORMAT_NV12:
return PLANE_CTL_FORMAT_NV12;
+ case DRM_FORMAT_Y210:
+ return PLANE_CTL_FORMAT_Y210;
+ case DRM_FORMAT_Y212:
+ return PLANE_CTL_FORMAT_Y212;
+ case DRM_FORMAT_Y216:
+ return PLANE_CTL_FORMAT_Y216;
default:
MISSING_CASE(pixel_format);
}
@@ -4959,6 +4965,9 @@ static int skl_update_scaler_plane(struct
intel_crtc_state *crtc_state,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_Y210:
+ case DRM_FORMAT_Y212:
+ case DRM_FORMAT_Y216:
break;
default:
DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format
0x%x\n",
@@ -13413,6 +13422,9 @@ static bool skl_plane_format_mod_supported(struct
drm_plane *_plane,
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
+ case DRM_FORMAT_Y210:
+ case DRM_FORMAT_Y212:
+ case DRM_FORMAT_Y216:
case DRM_FORMAT_NV12:
if (modifier == I915_FORMAT_MOD_Yf_TILED)
return true;
@@ -14544,6 +14556,9 @@ static int intel_framebuffer_init(struct
intel_framebuffer *intel_fb,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_YVYU:
case DRM_FORMAT_VYUY:
+ case DRM_FORMAT_Y210:
+ case DRM_FORMAT_Y212:
+ case DRM_FORMAT_Y216:
if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
DRM_DEBUG_KMS("unsupported pixel format: %s\n",
drm_get_format_name(mode_cmd->pixel_format, _name));
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index c286dda..417501f 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1419,6 +1419,9 @@ static bool skl_plane_format_mod_supported(struct
drm_plane *_plane,
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
+ case DRM_FORMAT_Y210:
+ case DRM_FORMAT_Y212:
+ case DRM_FORMAT_Y216:
case DRM_FORMAT_NV12:
if (modifier == I915_FORMAT_MOD_Yf_TILED)
return true;
--
1.9.1
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[Intel-gfx] [PATCH 4/4] drm/i915: Enable Y210, Y212, Y216 format for primary and sprite planes
From: Vidya Srinivas
In this patch, a list for icl specific pixel formats is created
in which Y210, Y212 and Y216 pixel formats are added along with
legacy pixel formats for primary and sprite plane.
Signed-off-by: Swati Sharma
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/intel_display.c | 25 +++--
drivers/gpu/drm/i915/intel_sprite.c | 22 --
2 files changed, 43 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 91aa8cc..30065e3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -104,6 +104,24 @@
DRM_FORMAT_NV12,
};
+static const uint32_t icl_primary_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_Y210,
+ DRM_FORMAT_Y212,
+ DRM_FORMAT_Y216,
+};
+
static const uint64_t skl_format_modifiers_noccs[] = {
I915_FORMAT_MOD_Yf_TILED,
I915_FORMAT_MOD_Y_TILED,
@@ -13718,8 +13736,11 @@ bool skl_plane_has_planar(struct drm_i915_private
*dev_priv,
if (INTEL_GEN(dev_priv) >= 9) {
primary->has_ccs = skl_plane_has_ccs(dev_priv, pipe,
PLANE_PRIMARY);
-
- if (skl_plane_has_planar(dev_priv, pipe, PLANE_PRIMARY)) {
+ if (INTEL_GEN(dev_priv) >= 11) {
+ intel_primary_formats = icl_primary_formats;
+ num_formats = ARRAY_SIZE(icl_primary_formats);
+ } else if (skl_plane_has_planar(dev_priv, pipe,
+ PLANE_PRIMARY)) {
intel_primary_formats = skl_pri_planar_formats;
num_formats = ARRAY_SIZE(skl_pri_planar_formats);
} else {
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 417501f..2abdd85 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1281,6 +1281,21 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device
*dev, void *data,
DRM_FORMAT_NV12,
};
+static uint32_t icl_plane_formats[] = {
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_Y210,
+ DRM_FORMAT_Y212,
+ DRM_FORMAT_Y216,
+};
+
static const uint64_t skl_plane_format_modifiers_noccs[] = {
I915_FORMAT_MOD_Yf_TILED,
I915_FORMAT_MOD_Y_TILED,
@@ -1536,8 +1551,11 @@ struct intel_plane *
intel_plane->disable_plane = skl_disable_plane;
intel_plane->get_hw_state = skl_plane_get_hw_state;
- if (skl_plane_has_planar(dev_priv, pipe,
-PLANE_SPRITE0 + plane)) {
+ if (INTEL_GEN(dev_priv) >= 11) {
+ plane_formats = icl_plane_formats;
+ num_plane_formats = ARRAY_SIZE(icl_plane_formats);
+ } else if (skl_plane_has_planar(dev_priv, pipe,
+ PLANE_SPRITE0 + plane)) {
plane_formats = skl_planar_formats;
num_plane_formats = ARRAY_SIZE(skl_planar_formats);
} else {
--
1.9.1
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[Intel-gfx] [PATCH 1/4] drm: Add Y210, Y212, Y216 format definitions and fourcc
From: Vidya Srinivas
The following pixel formats are packed format that follows 4:2:2
chroma sampling. For memory represenation each component is
allocated 16 bits each. Thus each pixel occupies a DWORD.
Y210: Valid data occupies MSB 10 bits.
LSB 6 bits are filled with zeroes.
Y212: Valid data occupies MSB 12 bits.
LSB 4 bits are filled with zeroes.
Y216: Valid data occupies 16 bits,
doesn't require any padding bits.
First 16 bits stores the Y value and the next 16 bits stores one
of the chroma samples alternatively. The first luma sample will
be accompanied by first U sample and second luma sample is
accompanied by the first V sample.
Signed-off-by: Swati Sharma
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/drm_fourcc.c | 3 +++
include/uapi/drm/drm_fourcc.h | 4
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 35c1e27..4bf04a5 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -173,6 +173,9 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_UYVY,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_VYUY,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_AYUV,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true,
.is_yuv = true },
+ { .format = DRM_FORMAT_Y210,.depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1 },
+ { .format = DRM_FORMAT_Y212,.depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1 },
+ { .format = DRM_FORMAT_Y216,.depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1 },
};
unsigned int i;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 2ed46e9..6a03e6d 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -149,6 +149,10 @@
#define DRM_FORMAT_AYUVfourcc_code('A', 'Y', 'U', 'V') /*
[31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
+#define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0]
Y0:Cb0:Y1:Cr1 10:10:10:10 little endian */
+#define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0]
Y0:Cb0:Y1:Cr1 12:12:12:12 little endian */
+#define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0]
Y0:Cb0:Y1:Cr1 16:16:16:16 little endian */
+
/*
* 2 plane RGB + A
* index 0 = RGB plane, same format as the corresponding non _A8 format has
--
1.9.1
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[Intel-gfx] [PATCH 2/4] drm/i915: Add Y210, Y212, Y216 plane control definitions
From: Vidya Srinivas
Added needed plane control flag definitions for Y210, Y212 and
Y216 formats.
Signed-off-by: Swati Sharma
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8534f88..926e42d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6504,6 +6504,9 @@ enum {
#define PLANE_CTL_FORMAT_RGB_565 (14 << 24)
#define ICL_PLANE_CTL_FORMAT_MASK(0x1f << 23)
#define PLANE_CTL_PIPE_CSC_ENABLE(1 << 23) /* Pre-GLK */
+#define PLANE_CTL_FORMAT_Y210(1 << 23)
+#define PLANE_CTL_FORMAT_Y212(3 << 23)
+#define PLANE_CTL_FORMAT_Y216(5 << 23)
#define PLANE_CTL_KEY_ENABLE_MASK(0x3 << 21)
#define PLANE_CTL_KEY_ENABLE_SOURCE (1 << 21)
#define PLANE_CTL_KEY_ENABLE_DESTINATION (2 << 21)
--
1.9.1
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[Intel-gfx] [PATCH 0/4] Enable Y210, Y212, Y216 formats for ICL
These patches enable packed format YUV422-Y210, Y212 and Y216 for 10, 12 and 16 bit respectively for ICL. For user space component IGT:WIP Vidya Srinivas (4): drm: Add Y210, Y212, Y216 format definitions and fourcc drm/i915: Add Y210, Y212, Y216 plane control definitions drm/i915: Preparations for enabling Y210, Y212, Y216 formats drm/i915: Enable Y210, Y212, Y216 format for primary and sprite planes drivers/gpu/drm/drm_fourcc.c | 3 +++ drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_display.c | 40 ++-- drivers/gpu/drm/i915/intel_sprite.c | 25 -- include/uapi/drm/drm_fourcc.h| 4 5 files changed, 71 insertions(+), 4 deletions(-) -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
