[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/icl: Add POWER_DOMAIN_GT_IRQ to ICL DC_OFF_POWER_DOMAINS
== Series Details == Series: drm/i915/icl: Add POWER_DOMAIN_GT_IRQ to ICL DC_OFF_POWER_DOMAINS URL : https://patchwork.freedesktop.org/series/49514/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4806_full -> Patchwork_10146_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_10146_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10146_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10146_full: === IGT changes === Warnings igt@kms_atomic_interruptible@universal-setplane-primary: shard-snb: PASS -> SKIP +4 == Known issues == Here are the changes found in Patchwork_10146_full that come from known issues: === IGT changes === Issues hit igt@drv_suspend@shrink: shard-glk: PASS -> FAIL (fdo#106886) igt@gem_exec_await@wide-contexts: shard-kbl: PASS -> FAIL (fdo#106680) Possible fixes igt@gem_exec_await@wide-contexts: shard-glk: FAIL (fdo#106680) -> PASS igt@kms_cursor_legacy@cursor-vs-flip-toggle: shard-hsw: FAIL (fdo#103355) -> PASS igt@kms_flip@flip-vs-expired-vblank: shard-glk: FAIL (fdo#105363) -> PASS fdo#103355 https://bugs.freedesktop.org/show_bug.cgi?id=103355 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#106680 https://bugs.freedesktop.org/show_bug.cgi?id=106680 fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4806 -> Patchwork_10146 CI_DRM_4806: feeccde66999c5e87be3550f2159e5d7eeb61c67 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4638: 20a7ead8bdf09774c7d58fcbe6a0980d08ed5365 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10146: 5e67647ffd56c598988f0c70a71dd9607a51e96a @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10146/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 0/3] add LG panel to dpcd quirk database
Only specific N value (0x8000) would be acceptable for LG LP140WF6-SPM1 eDP panel which is running at asynchronous clock mode. With the other N value, it will enter BITS mode and display black screen. This patch series set constant N value for specific sink/branch device that would cover similar issue. Cc: Jani Nikula Cc: Cooper Chiou Cc: Matt Atwood Cc: Maarten Lankhorst Cc: Dhinakaran Pandiyan Cc: Clint Taylor Lee, Shawn C (3): drm: Add support for device_id based detection. drm: Change limited M/N quirk to constant N quirk. drm: add LG eDP panel to quirk database drivers/gpu/drm/drm_dp_helper.c | 17 - drivers/gpu/drm/i915/intel_display.c | 28 +--- drivers/gpu/drm/i915/intel_display.h | 2 +- drivers/gpu/drm/i915/intel_dp.c | 8 drivers/gpu/drm/i915/intel_dp_mst.c | 6 +++--- include/drm/drm_dp_helper.h | 6 +++--- 6 files changed, 40 insertions(+), 27 deletions(-) -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 2/3] drm: Change limited M/N quirk to constant N quirk.
Some DP dongles in particular seem to be fussy about too large
link M/N values. Set specific value for N divider can resolve
this issue per dongle vendor's comment. So configure N as
constant value (0x8000) to instead of reduce M/N formula when
specific DP dongle connected.
v2: add more comments for issue description and fix typo.
v3: add lost commit messages back for version 2
v4: send patch to both intel-gfx and dri-devel
Cc: Jani Nikula
Cc: Cooper Chiou
Cc: Matt Atwood
Cc: Maarten Lankhorst
Cc: Dhinakaran Pandiyan
Cc: Clint Taylor
Signed-off-by: Lee, Shawn C
---
drivers/gpu/drm/drm_dp_helper.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 28 +---
drivers/gpu/drm/i915/intel_display.h | 2 +-
drivers/gpu/drm/i915/intel_dp.c | 8
drivers/gpu/drm/i915/intel_dp_mst.c | 6 +++---
include/drm/drm_dp_helper.h | 6 +++---
6 files changed, 25 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 0362c645d96e..f3a7563eb8a1 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1269,7 +1269,7 @@ struct dpcd_quirk {
static const struct dpcd_quirk dpcd_quirk_list[] = {
/* Analogix 7737 needs reduced M and N at HBR2 link rates */
- { OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true,
BIT(DP_DPCD_QUIRK_LIMITED_M_N) },
+ { OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true,
BIT(DP_DPCD_QUIRK_CONSTANT_N) },
};
#undef OUI
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index ec3e24f07486..da0c7fbef3ef 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6680,22 +6680,20 @@ intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
static void compute_m_n(unsigned int m, unsigned int n,
uint32_t *ret_m, uint32_t *ret_n,
- bool reduce_m_n)
+ bool constant_n)
{
/*
-* Reduce M/N as much as possible without loss in precision. Several DP
-* dongles in particular seem to be fussy about too large *link* M/N
-* values. The passed in values are more likely to have the least
-* significant bits zero than M after rounding below, so do this first.
+* Several DP dongles in particular seem to be fussy about
+* too large link M/N values. Give N value as 0x8000 that
+* should be acceptable by specific devices. 0x8000 is the
+* specified fixed N value for asynchronous clock mode,
+* which the devices expect also in synchronous clock mode.
*/
- if (reduce_m_n) {
- while ((m & 1) == 0 && (n & 1) == 0) {
- m >>= 1;
- n >>= 1;
- }
- }
+ if (constant_n)
+ *ret_n = 0x8000;
+ else
+ *ret_n = min_t(unsigned int, roundup_pow_of_two(n),
DATA_LINK_N_MAX);
- *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
*ret_m = div_u64((uint64_t) m * *ret_n, n);
intel_reduce_m_n_ratio(ret_m, ret_n);
}
@@ -6704,18 +6702,18 @@ void
intel_link_compute_m_n(int bits_per_pixel, int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
- bool reduce_m_n)
+ bool constant_n)
{
m_n->tu = 64;
compute_m_n(bits_per_pixel * pixel_clock,
link_clock * nlanes * 8,
_n->gmch_m, _n->gmch_n,
- reduce_m_n);
+ constant_n);
compute_m_n(pixel_clock, link_clock,
_n->link_m, _n->link_n,
- reduce_m_n);
+ constant_n);
}
static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_display.h
b/drivers/gpu/drm/i915/intel_display.h
index 43f080c6538d..8e8bd5eed2c2 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -379,7 +379,7 @@ struct intel_link_m_n {
void intel_link_compute_m_n(int bpp, int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
- bool reduce_m_n);
+ bool constant_n);
bool is_ccs_modifier(u64 modifier);
#endif
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 436c22de33b6..6b4c19123f2a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1998,8 +1998,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_connector *intel_connector = intel_dp->attached_connector;
struct intel_digital_connector_state *intel_conn_state =
to_intel_digital_connector_state(conn_state);
- bool reduce_m_n =
[Intel-gfx] [PATCH v4 1/3] drm: Add support for device_id based detection.
DP quirk list just compare sink or branch device's OUI so far.
That means particular vendor's products will be applied specific
change. This change would confirm device_id the same or not.
Then driver can implement some changes for branch/sink device
that really need additional WA.
v2: use sizeof instead of hard coded '6'
v3: add lost commit messages back for version 2
v4: send patch to both intel-gfx and dri-devel
Cc: Jani Nikula
Cc: Cooper Chiou
Cc: Matt Atwood
Cc: Maarten Lankhorst
Cc: Dhinakaran Pandiyan
Cc: Clint Taylor
Signed-off-by: Lee, Shawn C
---
drivers/gpu/drm/drm_dp_helper.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 0cccbcb2d03e..0362c645d96e 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1256,15 +1256,20 @@ EXPORT_SYMBOL(drm_dp_stop_crc);
struct dpcd_quirk {
u8 oui[3];
+ u8 device_id[6];
bool is_branch;
u32 quirks;
};
#define OUI(first, second, third) { (first), (second), (third) }
+#define DEVICE_ID(first, second, third, fourth, fifth, sixth) \
+ { (first), (second), (third), (fourth), (fifth), (sixth) }
+
+#define DEVICE_ID_ANY DEVICE_ID(0, 0, 0, 0, 0, 0)
static const struct dpcd_quirk dpcd_quirk_list[] = {
/* Analogix 7737 needs reduced M and N at HBR2 link rates */
- { OUI(0x00, 0x22, 0xb9), true, BIT(DP_DPCD_QUIRK_LIMITED_M_N) },
+ { OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true,
BIT(DP_DPCD_QUIRK_LIMITED_M_N) },
};
#undef OUI
@@ -1283,6 +1288,7 @@ drm_dp_get_quirks(const struct drm_dp_dpcd_ident *ident,
bool is_branch)
const struct dpcd_quirk *quirk;
u32 quirks = 0;
int i;
+ u8 any_device[] = DEVICE_ID_ANY;
for (i = 0; i < ARRAY_SIZE(dpcd_quirk_list); i++) {
quirk = _quirk_list[i];
@@ -1293,12 +1299,19 @@ drm_dp_get_quirks(const struct drm_dp_dpcd_ident
*ident, bool is_branch)
if (memcmp(quirk->oui, ident->oui, sizeof(ident->oui)) != 0)
continue;
+ if (memcmp(quirk->device_id, any_device, sizeof(any_device)) !=
0 &&
+ memcmp(quirk->device_id, ident->device_id,
sizeof(ident->device_id)) != 0)
+ continue;
+
quirks |= quirk->quirks;
}
return quirks;
}
+#undef DEVICE_ID_ANY
+#undef DEVICE_ID
+
/**
* drm_dp_read_desc - read sink/branch descriptor from DPCD
* @aux: DisplayPort AUX channel
--
2.7.4
___
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[Intel-gfx] [PATCH v4 3/3] drm: add LG eDP panel to quirk database
The N value was computed by kernel driver that based on synchronous clock
mode. But only specific N value (0x8000) would be acceptable for
LG LP140WF6-SPM1 eDP panel which is running at asynchronous clock mode.
With the other N value, Tcon will enter BITS mode and display black screen.
Add this panel into quirk database and give particular N value when
calculate M/N divider.
v2: no update
v3: add lost commit messages back for version 2
v4: send patch to both intel-gfx and dri-devel
Cc: Jani Nikula
Cc: Cooper Chiou
Cc: Matt Atwood
Cc: Maarten Lankhorst
Cc: Dhinakaran Pandiyan
Cc: Clint Taylor
Signed-off-by: Lee, Shawn C
---
drivers/gpu/drm/drm_dp_helper.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index f3a7563eb8a1..67d683453f1c 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1270,6 +1270,8 @@ struct dpcd_quirk {
static const struct dpcd_quirk dpcd_quirk_list[] = {
/* Analogix 7737 needs reduced M and N at HBR2 link rates */
{ OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true,
BIT(DP_DPCD_QUIRK_CONSTANT_N) },
+ /* LG LP140WF6-SPM1 eDP panel */
+ { OUI(0x00, 0x22, 0xb9), DEVICE_ID('s', 'i', 'v', 'a', 'r', 'T'),
false, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
};
#undef OUI
--
2.7.4
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Re: [Intel-gfx] [PATCH v2 1/3] drm: Add support for device_id based detection.
On Wed 9/12/2018 8:12 AM , Dhinakaran Pandiyan wrote:
>> DP quirk list just compare sink or branch device's OUI so far.
>> That means particular vendor's products will be applied specific
>> change. This change would confirm device_id the same or not.
>> Then driver can implement some changes for branch/sink device that
>> really need additional WA.
>>
>> Cc: Jani Nikula
>> Cc: Cooper Chiou
>> Cc: Matt Atwood
>> Cc: Maarten Lankhorst
>> Cc: Dhinakaran Pandiyan
>> Cc: Clint Taylor
>> Signed-off-by: Lee, Shawn C
>> ---
>> drivers/gpu/drm/drm_dp_helper.c | 15 ++-
>> 1 file changed, 14 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/drm_dp_helper.c
>> b/drivers/gpu/drm/drm_dp_helper.c index 0cccbcb2d03e..0362c645d96e
>> 100644
>> --- a/drivers/gpu/drm/drm_dp_helper.c
>> +++ b/drivers/gpu/drm/drm_dp_helper.c
>> @@ -1256,15 +1256,20 @@ EXPORT_SYMBOL(drm_dp_stop_crc);
>>
>> struct dpcd_quirk {
>> u8 oui[3];
>> +u8 device_id[6];
>> bool is_branch;
>
>With device id included, do we still need is_branch?
>
I think we should keep is_branch here. So far, this WA will be applied for all
analogix
branch devices to fix multiple dongles can't display issue.
>> u32 quirks;
>> };
>>
>> #define OUI(first, second, third) { (first), (second), (third) }
>> +#define DEVICE_ID(first, second, third, fourth, fifth, sixth) \
>> +{ (first), (second), (third), (fourth), (fifth), (sixth) }
>> +
>> +#define DEVICE_ID_ANY DEVICE_ID(0, 0, 0, 0, 0, 0)
>>
>> static const struct dpcd_quirk dpcd_quirk_list[] = {
>> /* Analogix 7737 needs reduced M and N at HBR2 link rates */
>> -{ OUI(0x00, 0x22, 0xb9), true,
>> BIT(DP_DPCD_QUIRK_LIMITED_M_N) },
>> +{ OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true,
>> BIT(DP_DPCD_QUIRK_LIMITED_M_N) },
>> };
>>
>> #undef OUI
>> @@ -1283,6 +1288,7 @@ drm_dp_get_quirks(const struct drm_dp_dpcd_ident
>> *ident, bool is_branch)
>> const struct dpcd_quirk *quirk;
>> u32 quirks = 0;
>> int i;
>> +u8 any_device[] = DEVICE_ID_ANY;
>>
>> for (i = 0; i < ARRAY_SIZE(dpcd_quirk_list); i++) {
>> quirk = _quirk_list[i];
>> @@ -1293,12 +1299,19 @@ drm_dp_get_quirks(const struct
>> drm_dp_dpcd_ident *ident, bool is_branch)
>
>Update documentation that currently says -
> "* For now, only the OUI (first three bytes) is used, but this may be extended
> * to device identification string ..."
>
>> if (memcmp(quirk->oui, ident->oui, sizeof(ident-
>> >oui)) != 0)
>> continue;
>>
>> +if (memcmp(quirk->device_id, any_device,
>> sizeof(any_device)) != 0 &&
>> +memcmp(quirk->device_id, ident->device_id,
>> sizeof(ident->device_id)) != 0)
>> +continue;
>> +
>> quirks |= quirk->quirks;
>> }
>>
>> return quirks;
>> }
>>
>> +#undef DEVICE_ID_ANY
>> +#undef DEVICE_ID
>> +
>> /**
>> * drm_dp_read_desc - read sink/branch descriptor from DPCD
>> * @aux: DisplayPort AUX channel
>
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/icl: Add POWER_DOMAIN_GT_IRQ to ICL DC_OFF_POWER_DOMAINS
== Series Details == Series: drm/i915/icl: Add POWER_DOMAIN_GT_IRQ to ICL DC_OFF_POWER_DOMAINS URL : https://patchwork.freedesktop.org/series/49514/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4806 -> Patchwork_10146 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/49514/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10146 that come from known issues: === IGT changes === Issues hit igt@amdgpu/amd_prime@amd-to-i915: fi-kbl-8809g: NOTRUN -> FAIL (fdo#107341) igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: PASS -> FAIL (fdo#103167) Possible fixes igt@amdgpu/amd_basic@userptr: fi-kbl-8809g: INCOMPLETE (fdo#107402) -> PASS igt@gem_exec_suspend@basic-s3: fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS fi-icl-u: INCOMPLETE (fdo#107901) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-byt-clapper: FAIL (fdo#103191, fdo#107362) -> PASS igt@prime_vgem@basic-fence-flip: fi-ilk-650: FAIL (fdo#104008) -> PASS fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008 fdo#107341 https://bugs.freedesktop.org/show_bug.cgi?id=107341 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107402 https://bugs.freedesktop.org/show_bug.cgi?id=107402 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#107901 https://bugs.freedesktop.org/show_bug.cgi?id=107901 == Participating hosts (49 -> 43) == Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-glk-j4005 == Build changes == * Linux: CI_DRM_4806 -> Patchwork_10146 CI_DRM_4806: feeccde66999c5e87be3550f2159e5d7eeb61c67 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4638: 20a7ead8bdf09774c7d58fcbe6a0980d08ed5365 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10146: 5e67647ffd56c598988f0c70a71dd9607a51e96a @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 5e67647ffd56 drm/i915/icl: Add POWER_DOMAIN_GT_IRQ to ICL DC_OFF_POWER_DOMAINS == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10146/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for Display Stream Compression enabling on eDP/DP (rev4)
== Series Details == Series: Display Stream Compression enabling on eDP/DP (rev4) URL : https://patchwork.freedesktop.org/series/47514/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4806 -> Patchwork_10145 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10145 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10145, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/47514/revisions/4/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10145: === IGT changes === Possible regressions igt@drv_module_reload@basic-reload: fi-icl-u: NOTRUN -> DMESG-WARN +21 Warnings igt@gem_exec_suspend@basic-s3: fi-icl-u: INCOMPLETE (fdo#107901) -> DMESG-WARN == Known issues == Here are the changes found in Patchwork_10145 that come from known issues: === IGT changes === Issues hit igt@amdgpu/amd_prime@amd-to-i915: fi-kbl-8809g: NOTRUN -> FAIL (fdo#107341) igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: PASS -> FAIL (fdo#103167) igt@kms_psr@primary_page_flip: fi-kbl-7560u: PASS -> FAIL (fdo#107336) Possible fixes igt@amdgpu/amd_basic@userptr: fi-kbl-8809g: INCOMPLETE (fdo#107402) -> PASS igt@gem_exec_suspend@basic-s3: fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-byt-clapper: FAIL (fdo#103191, fdo#107362) -> PASS igt@prime_vgem@basic-fence-flip: fi-ilk-650: FAIL (fdo#104008) -> PASS fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008 fdo#107336 https://bugs.freedesktop.org/show_bug.cgi?id=107336 fdo#107341 https://bugs.freedesktop.org/show_bug.cgi?id=107341 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107402 https://bugs.freedesktop.org/show_bug.cgi?id=107402 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#107901 https://bugs.freedesktop.org/show_bug.cgi?id=107901 == Participating hosts (49 -> 44) == Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u == Build changes == * Linux: CI_DRM_4806 -> Patchwork_10145 CI_DRM_4806: feeccde66999c5e87be3550f2159e5d7eeb61c67 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4638: 20a7ead8bdf09774c7d58fcbe6a0980d08ed5365 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10145: d52012c3f51f135735abe1050b133bd2dc88daef @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == d52012c3f51f drm/i915/dp: Disable DSC in source by disabling DSS CTL bits 7adbcfab9358 drm/i915/dp: Configure Display stream splitter registers during DSC enable 667d667fcc32 drm/i915/icl: Add Display Stream Splitter control registers ebfeb6c84440 drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes d81afaa3f3af drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs f31be5cedd0e drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling 36a228201d7c drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI 2e8d374ecf60 drm/i915/dp: Enable/Disable DSC in DP Sink 364395179414 drm/i915/dsc: Compute Rate Control parameters for DSC 2dc4510a94cf drm/i915/dsc: Define & Compute VESA DSC params 6071851e78f6 drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants 6505ec03ee07 drm/i915/dp: Do not enable PSR2 if DSC is enabled a269e9cbb0cb drm/i915/dp: Compute DSC pipe config in atomic check c373898f4090 drm/i915/dp: Add DSC params and DSC config to intel_crtc_state b37f405578b5 drm/dsc: Add helpers for DSC picture parameter set infoframes 2fa50580e540 drm/dsc: Define Rate Control values that do not change over configurations 3f646b2cd07d drm/dsc: Define VESA Display Stream Compression Capabilities 80275c56167e drm/dsc: Define Display Stream Compression PPS infoframe 91e0ef49ef5f drm/dp: Define payload size for DP SDP PPS packet 3229480fcf42 drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported b05fa7e9e1c0 drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC 3d7e87c20a5e drm/dp: DRM DP helper/macros to get DP sink DSC parameters 23db8f3fa417 drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init f1feaec457cc drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT c28404862aa9 drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming == Logs == For more details see:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Display Stream Compression enabling on eDP/DP (rev4)
== Series Details == Series: Display Stream Compression enabling on eDP/DP (rev4) URL : https://patchwork.freedesktop.org/series/47514/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming Okay! Commit: drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT Okay! Commit: drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init Okay! Commit: drm/dp: DRM DP helper/macros to get DP sink DSC parameters Okay! Commit: drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC +drivers/gpu/drm/i915/intel_dp.c:4126:26: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dp.c:4126:26: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dp.c:4169:27: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dp.c:4169:27: warning: expression using sizeof(void) Commit: drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported Okay! Commit: drm/dp: Define payload size for DP SDP PPS packet Okay! Commit: drm/dsc: Define Display Stream Compression PPS infoframe Okay! Commit: drm/dsc: Define VESA Display Stream Compression Capabilities Okay! Commit: drm/dsc: Define Rate Control values that do not change over configurations Okay! Commit: drm/dsc: Add helpers for DSC picture parameter set infoframes - +drivers/gpu/drm/drm_dsc.c:195:61:expected restricted __be16 +drivers/gpu/drm/drm_dsc.c:195:61:got unsigned short [unsigned] [usertype] +drivers/gpu/drm/drm_dsc.c:195:61: warning: incorrect type in assignment (different base types) +drivers/gpu/drm/drm_dsc.c:202:25:expected unsigned short [unsigned] [usertype] val +drivers/gpu/drm/drm_dsc.c:202:25:got restricted __be16 +drivers/gpu/drm/drm_dsc.c:202:25: warning: cast from restricted __be16 +drivers/gpu/drm/drm_dsc.c:202:25: warning: cast from restricted __be16 +drivers/gpu/drm/drm_dsc.c:202:25: warning: cast from restricted __be16 +drivers/gpu/drm/drm_dsc.c:202:25: warning: incorrect type in argument 1 (different base types) Commit: drm/i915/dp: Add DSC params and DSC config to intel_crtc_state -drivers/gpu/drm/i915/selftests/../i915_drv.h:3689:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3690:16: warning: expression using sizeof(void) Commit: drm/i915/dp: Compute DSC pipe config in atomic check +drivers/gpu/drm/i915/intel_dp.c:1902:23: warning: expression using sizeof(void) Commit: drm/i915/dp: Do not enable PSR2 if DSC is enabled Okay! Commit: drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Okay! Commit: drm/i915/dsc: Define & Compute VESA DSC params +drivers/gpu/drm/i915/intel_vdsc.c:351:17: warning: expression using sizeof(void) +./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000 becomes 0) Commit: drm/i915/dsc: Compute Rate Control parameters for DSC Okay! Commit: drm/i915/dp: Enable/Disable DSC in DP Sink Okay! Commit: drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI Okay! Commit: drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling -drivers/gpu/drm/i915/selftests/../i915_drv.h:3690:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3692:16: warning: expression using sizeof(void) Commit: drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Okay! Commit: drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Okay! Commit: drm/i915/icl: Add Display Stream Splitter control registers Okay! Commit: drm/i915/dp: Configure Display stream splitter registers during DSC enable Okay! Commit: drm/i915/dp: Disable DSC in source by disabling DSS CTL bits -drivers/gpu/drm/i915/selftests/../i915_drv.h:3692:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3694:16: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Display Stream Compression enabling on eDP/DP (rev4)
== Series Details ==
Series: Display Stream Compression enabling on eDP/DP (rev4)
URL : https://patchwork.freedesktop.org/series/47514/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c28404862aa9 drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming
f1feaec457cc drm/dp: Add DP DSC DPCD receiver capability size define and
missing SHIFT
23db8f3fa417 drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP
Init
3d7e87c20a5e drm/dp: DRM DP helper/macros to get DP sink DSC parameters
b05fa7e9e1c0 drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC
-:27: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#27:
* rename it as SMALL_JOINER since we are not enabling big joiner yet (Anusha)
total: 0 errors, 1 warnings, 0 checks, 132 lines checked
3229480fcf42 drm/i915/dp: Validate modes using max Output BPP and slice count
when DSC supported
91e0ef49ef5f drm/dp: Define payload size for DP SDP PPS packet
80275c56167e drm/dsc: Define Display Stream Compression PPS infoframe
-:27: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#27:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 347 lines checked
3f646b2cd07d drm/dsc: Define VESA Display Stream Compression Capabilities
-:34: WARNING:BAD_SIGN_OFF: Non-standard signature: Co-developed-by:
#34:
Co-developed-by: Manasi Navare
-:73: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible
alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#73: FILE: include/drm/drm_dsc.h:40:
+ bool convert_rgb;
-:83: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible
alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#83: FILE: include/drm/drm_dsc.h:50:
+ bool enable422;
-:108: CHECK:BOOL_MEMBER: Avoid using bool structure members because of
possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#108: FILE: include/drm/drm_dsc.h:75:
+ bool block_pred_enable;
-:136: CHECK:BOOL_MEMBER: Avoid using bool structure members because of
possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#136: FILE: include/drm/drm_dsc.h:103:
+ bool vbr_enable;
-:151: CHECK:BOOL_MEMBER: Avoid using bool structure members because of
possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#151: FILE: include/drm/drm_dsc.h:118:
+ bool native_422;
-:153: CHECK:BOOL_MEMBER: Avoid using bool structure members because of
possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#153: FILE: include/drm/drm_dsc.h:120:
+ bool native_420;
total: 0 errors, 1 warnings, 6 checks, 121 lines checked
2fa50580e540 drm/dsc: Define Rate Control values that do not change over
configurations
-:42: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch
author 'Srivatsa, Anusha '
total: 0 errors, 1 warnings, 0 checks, 12 lines checked
b37f405578b5 drm/dsc: Add helpers for DSC picture parameter set infoframes
-:23: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#23:
* Add reference to added kernel-docs in Documentation/gpu/drm-kms-helpers.rst
-:74: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#74:
new file mode 100644
total: 0 errors, 2 warnings, 0 checks, 287 lines checked
c373898f4090 drm/i915/dp: Add DSC params and DSC config to intel_crtc_state
-:46: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible
alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#46: FILE: drivers/gpu/drm/i915/intel_drv.h:904:
+ bool compression_enable;
-:47: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible
alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#47: FILE: drivers/gpu/drm/i915/intel_drv.h:905:
+ bool dsc_split;
total: 0 errors, 0 warnings, 2 checks, 22 lines checked
a269e9cbb0cb drm/i915/dp: Compute DSC pipe config in atomic check
6505ec03ee07 drm/i915/dp: Do not enable PSR2 if DSC is enabled
6071851e78f6 drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants
2dc4510a94cf drm/i915/dsc: Define & Compute VESA DSC params
-:65: WARNING:BAD_SIGN_OFF: Non-standard signature: Co-developed-by:
#65:
Co-developed-by: Manasi Navare
-:91: WARNING:MISSING_SPACE: break quoted strings at a space character
#91: FILE: drivers/gpu/drm/i915/intel_dp.c:2045:
+ DRM_ERROR("Cannot compute valid DSC parameters for Input Bpp =
%d"
+ "Compressed BPP = %d\n",
-:115: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#115:
new file mode 100644
-:401: CHECK:LINE_SPACING: Please use a blank line after
function/struct/union/enum declarations
#401: FILE: drivers/gpu/drm/i915/intel_vdsc.c:282:
+}
+};
total: 0 errors, 3
[Intel-gfx] [PATCH] drm/i915/icl: Add POWER_DOMAIN_GT_IRQ to ICL DC_OFF_POWER_DOMAINS
Without this gem will not be able to turn off DC states to redunce interruption latency when no sink is being driven by driver. Cc: Paulo Zanoni Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_runtime_pm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 480dadb1047b..af8a0b6ee79b 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -1978,6 +1978,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, */ #define ICL_DISPLAY_DC_OFF_POWER_DOMAINS ( \ ICL_PW_2_POWER_DOMAINS |\ + BIT_ULL(POWER_DOMAIN_GT_IRQ) | \ BIT_ULL(POWER_DOMAIN_MODESET) | \ BIT_ULL(POWER_DOMAIN_AUX_A) | \ BIT_ULL(POWER_DOMAIN_INIT)) -- 2.18.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 07/25] drm/dp: Define payload size for DP SDP PPS packet
DP 1.4 spec defines DP secondary data packet for DSC
picture parameter set. This patch defines its payload size
according to the DP 1.4 specification.
Signed-off-by: Manasi Navare
Cc: dri-de...@lists.freedesktop.org
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Reviewed-by: Harry Wentland
---
include/drm/drm_dp_helper.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index ce6297908fd6..9f5825dde804 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -999,6 +999,7 @@ struct dp_sdp_header {
#define EDP_SDP_HEADER_REVISION_MASK 0x1F
#define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F
+#define DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 0x7F
struct edp_vsc_psr {
struct dp_sdp_header sdp_header;
--
2.18.0
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 23/25] drm/i915/icl: Add Display Stream Splitter control registers
From: "Srivatsa, Anusha"
Add defines for DSS_CTL registers.
These registers specify the big joiner, splitter,
overlap pixels and info regarding display stream
compression enabled on left or right branch.
v3 (From Manasi):
- Change the hex values to lower case (Madhav)
- Use BIT macro (Manasi)
v2:
- Add define to conditionally check the buffer target depth (James Ausmus)
Suggested-by: Madhav Chauhan
Cc: Madhav Chauhan
Cc: Manasi Navare
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 33 +
1 file changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c0225dfa030a..27baf83bbb34 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7701,6 +7701,39 @@ enum {
#define RC_MAX_QP_SHIFT5
#define RC_MIN_QP_SHIFT0
+/* Display Stream Splitter Control */
+#define DSS_CTL1 _MMIO(0x67400)
+#define SPLITTER_ENABLE (1 << 31)
+#define JOINER_ENABLE (1 << 30)
+#define DUAL_LINK_MODE_INTERLEAVE (1 << 24)
+#define DUAL_LINK_MODE_FRONTBACK (0 << 24)
+#define OVERLAP_PIXELS_MASK (0xf << 16)
+#define OVERLAP_PIXELS(pixels)((pixels) << 16)
+#define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
+#define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
+#define MAX_DL_BUFFER_TARGET_DEPTH0x5a0
+
+#define DSS_CTL2 _MMIO(0x67404)
+#define LEFT_BRANCH_VDSC_ENABLE (1 << 31)
+#define RIGHT_BRANCH_VDSC_ENABLE (1 << 15)
+#define RIGHT_DL_BUF_TARGET_DEPTH_MASK(0xfff << 0)
+#define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
+
+#define _ICL_PIPE_DSS_CTL1_PB 0x78200
+#define _ICL_PIPE_DSS_CTL1_PC 0x78400
+#define ICL_PIPE_DSS_CTL1(pipe)_MMIO_PIPE((pipe) -
PIPE_B, \
+
_ICL_PIPE_DSS_CTL1_PB, \
+
_ICL_PIPE_DSS_CTL1_PC)
+#define BIG_JOINER_ENABLE (1 << 29)
+#define MASTER_BIG_JOINER_ENABLE (1 << 28)
+#define VGA_CENTERING_ENABLE (1 << 27)
+
+#define _ICL_PIPE_DSS_CTL2_PB 0x78204
+#define _ICL_PIPE_DSS_CTL2_PC 0x78404
+#define ICL_PIPE_DSS_CTL2(pipe)_MMIO_PIPE((pipe) -
PIPE_B, \
+
_ICL_PIPE_DSS_CTL2_PB, \
+
_ICL_PIPE_DSS_CTL2_PC)
+
#define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248)
#define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4)
#define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48)
--
2.18.0
___
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[Intel-gfx] [PATCH v4 25/25] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits
1. Disable Left/right VDSC branch in DSS Ctrl reg
depending on the number of VDSC engines being used
2. Disable joiner in DSS Ctrl reg
v3 (From Manasi):
* Add Disable PG2 for VDSC on eDP
v2 (From Manasi):
* Use old_crtc_state to find dsc params
* Add a condition to disable only if
dsc state compression is enabled
* Use correct DSS CTL regs
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Signed-off-by: Gaurav K Singh
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_display.c | 13 ++
drivers/gpu/drm/i915/intel_vdsc.c| 37
3 files changed, 52 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f085df3f8c29..70d80cfaa3ae 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3471,6 +3471,8 @@ extern bool intel_set_memory_cxsr(struct drm_i915_private
*dev_priv,
bool enable);
extern void intel_dsc_enable(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state);
+extern void intel_dsc_disable(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state);
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 8010735d55be..f7760e92eb82 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5838,6 +5838,9 @@ static void haswell_crtc_disable(struct intel_crtc_state
*old_crtc_state,
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
+ struct drm_connector_state *conn_state;
+ struct drm_connector *conn;
+ int i;
intel_encoders_disable(crtc, old_crtc_state, old_state);
@@ -5854,6 +5857,16 @@ static void haswell_crtc_disable(struct intel_crtc_state
*old_crtc_state,
if (!transcoder_is_dsi(cpu_transcoder))
intel_ddi_disable_transcoder_func(old_crtc_state);
+ for_each_new_connector_in_state(old_state, conn, conn_state, i) {
+ struct intel_encoder *encoder =
+ to_intel_encoder(conn_state->best_encoder);
+
+ if (conn_state->crtc != crtc)
+ continue;
+
+ intel_dsc_disable(encoder, old_crtc_state);
+ }
+
if (INTEL_GEN(dev_priv) >= 9)
skylake_scaler_disable(intel_crtc);
else
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index c1874001ca67..422b37e9772f 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -1046,3 +1046,40 @@ void intel_dsc_enable(struct intel_encoder *encoder,
return;
}
+
+void intel_dsc_disable(struct intel_encoder *encoder,
+ struct intel_crtc_state *old_crtc_state)
+{
+ struct intel_dp *intel_dp = enc_to_intel_dp(>base);
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum pipe pipe = crtc->pipe;
+ i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
+ u32 dss_ctl1_val = 0, dss_ctl2_val = 0;
+
+ if (!old_crtc_state->dsc_params.compression_enable)
+ return;
+
+ if (encoder->type == INTEL_OUTPUT_EDP) {
+ dss_ctl1_reg = DSS_CTL1;
+ dss_ctl2_reg = DSS_CTL2;
+ } else {
+ dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
+ dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
+ }
+ dss_ctl1_val = I915_READ(dss_ctl1_reg);
+ if (dss_ctl1_val & JOINER_ENABLE)
+ dss_ctl1_val &= ~JOINER_ENABLE;
+ I915_WRITE(dss_ctl1_reg, dss_ctl1_val);
+
+ dss_ctl2_val = I915_READ(dss_ctl2_reg);
+ if (dss_ctl2_val & LEFT_BRANCH_VDSC_ENABLE ||
+ dss_ctl2_val & RIGHT_BRANCH_VDSC_ENABLE)
+ dss_ctl2_val &= ~(LEFT_BRANCH_VDSC_ENABLE |
+ RIGHT_BRANCH_VDSC_ENABLE);
+ I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
+
+ /* Put the PG2 power well for VDSC on eDP */
+ if (intel_dp_is_edp(intel_dp))
+ intel_display_power_put(dev_priv, POWER_DOMAIN_VDSC_EDP_MIPI);
+}
--
2.18.0
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[Intel-gfx] [PATCH v4 19/25] drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI
On Icelake, a separate power well PG2 is created for
VDSC engine used for eDP/MIPI DSI. This patch adds a new
display power domain for Power well 2.
Cc: Rodrigo Vivi
Cc: Imre Deak
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/intel_display.h| 1 +
drivers/gpu/drm/i915/intel_runtime_pm.c | 12 ++--
2 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.h
b/drivers/gpu/drm/i915/intel_display.h
index 3fe52788b4cf..bef71d27cdfe 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -256,6 +256,7 @@ enum intel_display_power_domain {
POWER_DOMAIN_MODESET,
POWER_DOMAIN_GT_IRQ,
POWER_DOMAIN_INIT,
+ POWER_DOMAIN_VDSC_EDP_MIPI,
POWER_DOMAIN_NUM,
};
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 480dadb1047b..146e2d6cf954 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -146,6 +146,8 @@ intel_display_power_domain_str(enum
intel_display_power_domain domain)
return "MODESET";
case POWER_DOMAIN_GT_IRQ:
return "GT_IRQ";
+ case POWER_DOMAIN_VDSC_EDP_MIPI:
+ return "VDSC_EDP_MIPI";
default:
MISSING_CASE(domain);
return "?";
@@ -1966,18 +1968,16 @@ void intel_display_power_put(struct drm_i915_private
*dev_priv,
BIT_ULL(POWER_DOMAIN_AUDIO) | \
BIT_ULL(POWER_DOMAIN_INIT))
/*
-* - transcoder WD
-* - KVMR (HW control)
+* - eDP/MIPI DSI VDSC
*/
#define ICL_PW_2_POWER_DOMAINS ( \
- ICL_PW_3_POWER_DOMAINS |\
- BIT_ULL(POWER_DOMAIN_INIT))
+ BIT_ULL(POWER_DOMAIN_VDSC_EDP_MIPI))
/*
-* - eDP/DSI VDSC
+* - transcoder WD
* - KVMR (HW control)
*/
#define ICL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- ICL_PW_2_POWER_DOMAINS |\
+ ICL_PW_3_POWER_DOMAINS |\
BIT_ULL(POWER_DOMAIN_MODESET) | \
BIT_ULL(POWER_DOMAIN_AUX_A) | \
BIT_ULL(POWER_DOMAIN_INIT))
--
2.18.0
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[Intel-gfx] [PATCH v4 15/25] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants
DSC specification defines linebuf_depth which contains the
line buffer bit depth used to generate the bitstream.
These values are defined as per Table 4.1 in DSC 1.2 spec
v2 (From Manasi):
* Rename as MAX_LINEBUF_DEPTH for DSC 1.1 and DSC 1.2
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjälä
Signed-off-by: Gaurav K Singh
Signed-off-by: Manasi Navare
---
include/drm/drm_dsc.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index 0e5e3368d645..8562d8ee8161 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -41,6 +41,9 @@
#define DSC_PPS_RC_RANGE_MINQP_SHIFT 11
#define DSC_PPS_RC_RANGE_MAXQP_SHIFT 6
#define DSC_PPS_NATIVE_420_SHIFT 1
+#define DSC_1_2_MAX_LINEBUF_DEPTH_BITS 16
+#define DSC_1_2_MAX_LINEBUF_DEPTH_VAL 0
+#define DSC_1_1_MAX_LINEBUF_DEPTH_BITS 13
/* Configuration for a single Rate Control model range */
struct dsc_rc_range_parameters {
--
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[Intel-gfx] [PATCH v4 24/25] drm/i915/dp: Configure Display stream splitter registers during DSC enable
Display Stream Splitter registers need to be programmed to enable
the joiner if two DSC engines are used and also to enable
the left and the right DSC engines. This happens as part of
the DSC enabling routine in the source in atomic commit.
v2:
* Rebase (Manasi)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_vdsc.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index 2011c3ea852e..c1874001ca67 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -1011,6 +1011,11 @@ void intel_dsc_enable(struct intel_encoder *encoder,
{
struct intel_dp *intel_dp = enc_to_intel_dp(>base);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ enum pipe pipe = crtc->pipe;
+ i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
+ u32 dss_ctl1_val = 0;
+ u32 dss_ctl2_val = 0;
if (!crtc_state->dsc_params.compression_enable)
return;
@@ -1023,5 +1028,21 @@ void intel_dsc_enable(struct intel_encoder *encoder,
intel_dp_send_dsc_pps_sdp(encoder, crtc_state);
+ /* Configure DSS_CTL registers for DSC */
+ if (encoder->type == INTEL_OUTPUT_EDP) {
+ dss_ctl1_reg = DSS_CTL1;
+ dss_ctl2_reg = DSS_CTL2;
+ } else {
+ dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
+ dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
+ }
+ dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE;
+ if (crtc_state->dsc_params.dsc_split) {
+ dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;
+ dss_ctl1_val |= JOINER_ENABLE;
+ }
+ I915_WRITE(dss_ctl1_reg, dss_ctl1_val);
+ I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
+
return;
}
--
2.18.0
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[Intel-gfx] [PATCH v4 22/25] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes
DSC PPS secondary data packet infoframes are filled with
DSC picure parameter set metadata according to the DSC standard.
These infoframes are sent to the sink device and used during DSC
decoding.
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_vdsc.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index 6eecf6abd4a9..2011c3ea852e 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -987,6 +987,25 @@ static void intel_configure_pps_for_dsc_encoder(struct
intel_encoder *encoder,
}
}
+static void intel_dp_send_dsc_pps_sdp(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ struct intel_dp *intel_dp = enc_to_intel_dp(>base);
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct drm_dsc_config *vdsc_cfg = _state->dp_dsc_cfg;
+ struct drm_dsc_pps_infoframe dp_dsc_pps_sdp;
+
+ /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */
+ drm_dsc_dp_pps_header_init(_dsc_pps_sdp);
+
+ /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */
+ drm_dsc_pps_infoframe_pack(_dsc_pps_sdp, vdsc_cfg);
+
+ intel_dig_port->write_infoframe(>base, crtc_state,
+ DP_SDP_PPS, _dsc_pps_sdp,
+ sizeof(dp_dsc_pps_sdp));
+}
+
void intel_dsc_enable(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state)
{
@@ -1002,5 +1021,7 @@ void intel_dsc_enable(struct intel_encoder *encoder,
intel_configure_pps_for_dsc_encoder(encoder, crtc_state);
+ intel_dp_send_dsc_pps_sdp(encoder, crtc_state);
+
return;
}
--
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[Intel-gfx] [PATCH v4 16/25] drm/i915/dsc: Define & Compute VESA DSC params
From: Gaurav K Singh
This patches does the following:
1. This patch defines all the DSC parameters as per the VESA
DSC specification. These are stored in the encoder and used
to compute the PPS parameters to be sent to the Sink.
2. Compute all the DSC parameters which are derived from DSC
state of intel_crtc_state.
3. Compute all parameters that are VESA DSC specific
This computation happens in the atomic check phase during
compute_config() to validate if display stream compression
can be enabled for the requested mode.
v7: (From Manasi)
* Dont use signed int for rc_range_params (Manasi)
* Mask the range_bpg_offset to use only 6 bits
* Add SPDX identifier (Chris Wilson)
v6 (From Manasi):
* Add a check for line_buf_depth return value (Anusha)
* Remove DRM DSC constants to different patch (Manasi)
v5 (From Manasi):
* Add logic to limit the max line buf depth for DSC 1.1 to 13
as per DSC 1.1 spec
* Fix dim checkpatch warnings/checks
v4 (From Gaurav):
* Rebase on latest drm tip
* rename variable name(Manasi)
* Populate linebuf_depth variable(Manasi)
v3 (From Gaurav):
* Rebase my previous patches on top of Manasi's latest patch
series
* Using >>n rather than /2^n (Manasi)
* Change the commit message to explain what the patch is doing(Gaurav)
Fixed review comments from Ville:
* Don't use macro TWOS_COMPLEMENT
* Mention in comment about the source of RC params
* Return directly from case statements
* Using single asssignment for assigning rc_range_params
* Using <
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Gaurav K Singh
Signed-off-by: Gaurav K Singh
Signed-off-by: Manasi Navare
Co-developed-by: Manasi Navare
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/intel_dp.c | 7 +
drivers/gpu/drm/i915/intel_drv.h | 4 +
drivers/gpu/drm/i915/intel_vdsc.c | 455 ++
include/drm/drm_dp_helper.h | 3 +
5 files changed, 471 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/intel_vdsc.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 5794f102f9b8..deaf2d4b5113 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -153,7 +153,8 @@ i915-y += dvo_ch7017.o \
intel_sdvo.o \
intel_tv.o \
vlv_dsi.o \
- vlv_dsi_pll.o
+ vlv_dsi_pll.o \
+ intel_vdsc.o
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index ade25fbfcdd1..97749f763574 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2040,6 +2040,13 @@ static bool intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
return false;
}
}
+ if (intel_dp_compute_dsc_params(intel_dp, pipe_config) < 0) {
+ DRM_ERROR("Cannot compute valid DSC parameters for Input Bpp =
%d"
+ "Compressed BPP = %d\n",
+ pipe_config->pipe_bpp,
+ pipe_config->dsc_params.compressed_bpp);
+ return false;
+ }
pipe_config->dsc_params.compression_enable = true;
DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d "
"Compressed Bpp = %d Slice Count = %d\n",
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 541372ea11f4..5494d5d1452a 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1758,6 +1758,10 @@ uint16_t intel_dp_dsc_get_output_bpp(int link_clock,
uint8_t lane_count,
uint8_t intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock,
int mode_hdisplay);
+/* intel_vdsc.c */
+int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config);
+
static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
{
return ~((1 << lane_count) - 1) & 0xf;
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
new file mode 100644
index ..351ea7d71c21
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -0,0 +1,455 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Author: Gaurav K Singh
+ * Manasi Navare
+ */
+
+#include
+#include
+#include "i915_drv.h"
+#include "intel_drv.h"
+
+enum ROW_INDEX_BPP {
+ ROW_INDEX_6BPP = 0,
+ ROW_INDEX_8BPP,
+ ROW_INDEX_10BPP,
+ ROW_INDEX_12BPP,
+ ROW_INDEX_15BPP,
+ MAX_ROW_INDEX
+};
+
+enum COLUMN_INDEX_BPC {
+ COLUMN_INDEX_8BPC = 0,
+ COLUMN_INDEX_10BPC,
+ COLUMN_INDEX_12BPC,
+ COLUMN_INDEX_14BPC,
+ COLUMN_INDEX_16BPC,
+ MAX_COLUMN_INDEX
+};
+
+#define DSC_SUPPORTED_VERSION_MIN 1
+
+/* From DSC_v1.11 spec, rc_parameter_Set syntax element
[Intel-gfx] [PATCH v4 00/25] Display Stream Compression enabling on eDP/DP
VESA has developed an industry standard Display Stream Compression(DSC) for interoperable, visually lossless compression over display links to address the needs for higher resolution displays. This patch series enables DSC on Gen 10 eDP and Gen 11 eDP/DP panels. This implementation is based on VESA DP 1.4 and DSC specifications. These patches have been validated on 1080p eDP 1.4 panel with DSC support and FPGA based DP 1.4 sink device for following configurations: - DSC with both VDSC engines enabled - DSC with only Left VDSC engine enabled - DSC for Input = 24bpp, Output = 8bpp - DSC for Input = 24bpp, Output = 10bpp - DSC for Input = 24bpp, output = 12bpp Anusha Srivatsa (1): drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming Gaurav K Singh (4): drm/dsc: Define VESA Display Stream Compression Capabilities drm/i915/dsc: Define & Compute VESA DSC params drm/i915/dsc: Compute Rate Control parameters for DSC drm/i915/dp: Enable/Disable DSC in DP Sink Manasi Navare (18): drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init drm/dp: DRM DP helper/macros to get DP sink DSC parameters drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported drm/dp: Define payload size for DP SDP PPS packet drm/dsc: Define Display Stream Compression PPS infoframe drm/dsc: Add helpers for DSC picture parameter set infoframes drm/i915/dp: Add DSC params and DSC config to intel_crtc_state drm/i915/dp: Compute DSC pipe config in atomic check drm/i915/dp: Do not enable PSR2 if DSC is enabled drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes drm/i915/dp: Configure Display stream splitter registers during DSC enable drm/i915/dp: Disable DSC in source by disabling DSS CTL bits Srivatsa, Anusha (2): drm/dsc: Define Rate Control values that do not change over configurations drm/i915/icl: Add Display Stream Splitter control registers Documentation/gpu/drm-kms-helpers.rst | 12 + drivers/gpu/drm/Makefile|2 +- drivers/gpu/drm/drm_dp_helper.c | 90 ++ drivers/gpu/drm/drm_dsc.c | 223 + drivers/gpu/drm/i915/Makefile |3 +- drivers/gpu/drm/i915/i915_drv.h |5 + drivers/gpu/drm/i915/i915_reg.h | 35 + drivers/gpu/drm/i915/intel_ddi.c|5 + drivers/gpu/drm/i915/intel_display.c| 39 +- drivers/gpu/drm/i915/intel_display.h|4 +- drivers/gpu/drm/i915/intel_dp.c | 342 ++- drivers/gpu/drm/i915/intel_dp_mst.c |2 +- drivers/gpu/drm/i915/intel_drv.h| 21 + drivers/gpu/drm/i915/intel_hdmi.c | 23 +- drivers/gpu/drm/i915/intel_psr.c| 14 + drivers/gpu/drm/i915/intel_runtime_pm.c | 12 +- drivers/gpu/drm/i915/intel_vdsc.c | 1085 +++ include/drm/drm_dp_helper.h | 40 + include/drm/drm_dsc.h | 491 ++ 19 files changed, 2407 insertions(+), 41 deletions(-) create mode 100644 drivers/gpu/drm/drm_dsc.c create mode 100644 drivers/gpu/drm/i915/intel_vdsc.c create mode 100644 include/drm/drm_dsc.h -- 2.18.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 08/25] drm/dsc: Define Display Stream Compression PPS infoframe
This patch defines a new header file for all the DSC 1.2 structures
and creates a structure for PPS infoframe which will be used to send
picture parameter set secondary data packet for display stream compression.
All the PPS infoframe syntax elements are taken from DSC 1.2 specification
from VESA.
v3:
* Add the SPDX shorthand (Chris Wilson)
v2:
* Do not use bitfields in the struct (Jani Nikula)
Cc: Gaurav K Singh
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Harry Wentland
Signed-off-by: Manasi Navare
Reviewed-by: Harry Wentland
---
include/drm/drm_dsc.h | 347 ++
1 file changed, 347 insertions(+)
create mode 100644 include/drm/drm_dsc.h
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
new file mode 100644
index ..1d8a03983b90
--- /dev/null
+++ b/include/drm/drm_dsc.h
@@ -0,0 +1,347 @@
+/* SPDX-License-Identifier: MIT
+ * Copyright (C) 2018 Intel Corp.
+ *
+ * Authors:
+ * Manasi Navare
+ */
+
+#ifndef DRM_DSC_H_
+#define DRM_DSC_H_
+
+#include
+
+/* VESA Display Stream Compression DSC 1.2 constants */
+#define DSC_NUM_BUF_RANGES 15
+
+/**
+ * struct picture_parameter_set - Represents 128 bytes of Picture Parameter Set
+ *
+ * The VESA DSC standard defines picture parameter set (PPS) which display
+ * stream compression encoders must communicate to decoders.
+ * The PPS is encapsulated in 128 bytes (PPS 0 through PPS 127). The fields in
+ * this structure are as per Table 4.1 in Vesa DSC specification v1.1/v1.2.
+ * The PPS fields that span over more than a byte should be stored in Big
Endian
+ * format.
+ */
+struct picture_parameter_set {
+ /**
+* @dsc_version:
+* PPS0[3:0] - dsc_version_minor: Contains Minor version of DSC
+* PPS0[7:4] - dsc_version_major: Contains major version of DSC
+*/
+ u8 dsc_version;
+ /**
+* @pps_identifier:
+* PPS1[7:0] - Application specific identifier that can be
+* used to differentiate between different PPS tables.
+*/
+ u8 pps_identifier;
+ /**
+* @pps_reserved:
+* PPS2[7:0]- RESERVED Byte
+*/
+ u8 pps_reserved;
+ /**
+* @pps_3:
+* PPS3[3:0] - linebuf_depth: Contains linebuffer bit depth used to
+* generate the bitstream. (0x0 - 16 bits for DSC 1.2, 0x8 - 8 bits,
+* 0xA - 10 bits, 0xB - 11 bits, 0xC - 12 bits, 0xD - 13 bits,
+* 0xE - 14 bits for DSC1.2, 0xF - 14 bits for DSC 1.2.
+* PPS3[7:4] - bits_per_component: Bits per component for the original
+* pixels of the encoded picture.
+* 0x0 = 16bpc (allowed only when dsc_version_minor = 0x2)
+* 0x8 = 8bpc, 0xA = 10bpc, 0xC = 12bpc, 0xE = 14bpc (also
+* allowed only when dsc_minor_version = 0x2)
+*/
+ u8 pps_3;
+ /**
+* @pps_4:
+* PPS4[1:0] -These are the most significant 2 bits of
+* compressed BPP bits_per_pixel[9:0] syntax element.
+* PPS4[2] - vbr_enable: 0 = VBR disabled, 1 = VBR enabled
+* PPS4[3] - simple_422: Indicates if decoder drops samples to
+* reconstruct the 4:2:2 picture.
+* PPS4[4] - Convert_rgb: Indicates if DSC color space conversion is
+* active.
+* PPS4[5] - blobk_pred_enable: Indicates if BP is used to code any
+* groups in picture
+* PPS4[7:6] - Reseved bits
+*/
+ u8 pps_4;
+ /**
+* @bits_per_pixel_low:
+* PPS5[7:0] - This indicates the lower significant 8 bits of
+* the compressed BPP bits_per_pixel[9:0] element.
+*/
+ u8 bits_per_pixel_low;
+ /**
+* @pic_height:
+* PPS6[7:0], PPS7[7:0] -pic_height: Specifies the number of pixel rows
+* within the raster.
+*/
+ __be16 pic_height;
+ /**
+* @pic_width:
+* PPS8[7:0], PPS9[7:0] - pic_width: Number of pixel columns within
+* the raster.
+*/
+ __be16 pic_width;
+ /**
+* @slice_height:
+* PPS10[7:0], PPS11[7:0] - Slice height in units of pixels.
+*/
+ __be16 slice_height;
+ /**
+* @slice_width:
+* PPS12[7:0], PPS13[7:0] - Slice width in terms of pixels.
+*/
+ __be16 slice_width;
+ /**
+* @chunk_size:
+* PPS14[7:0], PPS15[7:0] - Size in units of bytes of the chunks
+* that are used for slice multiplexing.
+*/
+ __be16 chunk_size;
+ /**
+* @initial_xmit_delay_high:
+* PPS16[1:0] - Most Significant two bits of initial transmission delay.
+* It specifies the number of pixel times that the encoder waits before
+* transmitting data from its rate buffer.
+* PPS16[7:2] - Reserved
+*/
+ u8 initial_xmit_delay_high;
+ /**
+* @initial_xmit_delay_low:
+* PPS17[7:0] - Least significant 8 bits of
[Intel-gfx] [PATCH v4 14/25] drm/i915/dp: Do not enable PSR2 if DSC is enabled
If a eDP panel supports both PSR2 and VDSC, our HW cannot
support both at a time. Give priority to PSR2 if a requested
resolution can be supported without compression else enable
VDSC and keep PSR2 disabled.
v2:
* Add warning for DSC and PSR2 enabled together (DK)
Cc: Rodrigo Vivi
Cc: Jani Nikula
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_psr.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index b6838b525502..13cacf8a25e3 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -71,6 +71,10 @@ static bool psr_global_enabled(u32 debug)
static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
const struct intel_crtc_state *crtc_state)
{
+ /* Cannot enable DSC and PSR2 simultaneously */
+ WARN_ON(crtc_state->dsc_params.compression_enable &&
+ crtc_state->has_psr2);
+
switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
case I915_PSR_DEBUG_FORCE_PSR1:
return false;
@@ -458,6 +462,16 @@ static bool intel_psr2_config_valid(struct intel_dp
*intel_dp,
if (!dev_priv->psr.sink_psr2_support)
return false;
+ /*
+* DSC and PSR2 cannot be enabled simultaneously. If a requested
+* resolution requires DSC to be enabled, priority is given to DSC
+* over PSR2.
+*/
+ if (crtc_state->dsc_params.compression_enable) {
+ DRM_DEBUG_KMS("PSR2 cannot be enabled since DSC is enabled\n");
+ return false;
+ }
+
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
psr_max_h = 4096;
psr_max_v = 2304;
--
2.18.0
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[Intel-gfx] [PATCH v4 01/25] drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming
From: Anusha Srivatsa
Add the newly added slice_row_per_frame parameter
in the Picture Parameter Set registers.
This defines the number of vertically stacked slices
in a frame.
Credits to Manasi for noticing bSpec change.
Suggested-by: Manasi Navare
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
Reviewed-by: Manasi Navare
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c80e56959e21..6de15f781090 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10638,6 +10638,7 @@ enum skl_power_gate {
#define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe)_MMIO_PIPE((pipe) -
PIPE_B, \
_ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
_ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
+#define DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame) ((slice_row_per_frame)
<< 20)
#define DSC_SLICE_PER_LINE(slice_per_line)((slice_per_line) << 16)
#define DSC_SLICE_CHUNK_SIZE(slice_chunk_size)
((slice_chunk_size) << 0)
--
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[Intel-gfx] [PATCH v4 17/25] drm/i915/dsc: Compute Rate Control parameters for DSC
From: Gaurav K Singh
This computation of RC params happens in the atomic commit phase
during compute_config() to validate if display stream compression
can be enabled for the requested mode.
v5 (From Manasi):
* Fix dim checkpatch warnings/checks
v4(From Gaurav):
* No change.Rebase on drm-tip
v3 (From Gaurav):
* Rebase on top of Manasi's latest series
* Return -ve value in case of failure scenarios (Manasi)
Fix review comments from Ville:
* Remove unnecessary comments
* Remove unnecessary paranthesis
* Add comments for few RC params calculations
v2 (From Manasi):
* Rebase Gaurav's patch from intel-gfx to gfx-internal
* Use struct drm_dsc_cfg instead of struct intel_dp
as a parameter
Cc: Manasi Navare
Cc: Jani Nikula
Cc: Ville Syrjala
Signed-off-by: Gaurav K Singh
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/intel_vdsc.c | 127 ++
1 file changed, 127 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index 351ea7d71c21..4e4e1e55f249 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -317,6 +317,130 @@ static int get_column_index_for_rc_params(u8
bits_per_component)
}
}
+static int intel_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
+{
+ unsigned long groups_per_line = 0;
+ unsigned long groups_total = 0;
+ unsigned long num_extra_mux_bits = 0;
+ unsigned long slice_bits = 0;
+ unsigned long hrd_delay = 0;
+ unsigned long final_scale = 0;
+ unsigned long rbs_min = 0;
+
+ /* Number of groups used to code each line of a slice */
+ groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
+ DSC_RC_PIXELS_PER_GROUP);
+
+ /* chunksize in Bytes */
+ vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
+ vdsc_cfg->bits_per_pixel,
+ (8 * 16));
+
+ if (vdsc_cfg->convert_rgb)
+ num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size +
+ (4 * vdsc_cfg->bits_per_component + 4)
+ - 2);
+ else
+ num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size +
+ (4 * vdsc_cfg->bits_per_component + 4) +
+ 2 * (4 * vdsc_cfg->bits_per_component) - 2;
+ /* Number of bits in one Slice */
+ slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height;
+
+ while ((num_extra_mux_bits > 0) &&
+ ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size))
+ num_extra_mux_bits--;
+
+ if (groups_per_line < vdsc_cfg->initial_scale_value - 8)
+ vdsc_cfg->initial_scale_value = groups_per_line + 8;
+
+ /* scale_decrement_interval calculation according to DSC spec 1.11 */
+ if (vdsc_cfg->initial_scale_value > 8)
+ vdsc_cfg->scale_decrement_interval = groups_per_line /
+ (vdsc_cfg->initial_scale_value - 8);
+ else
+ vdsc_cfg->scale_decrement_interval =
DSC_SCALE_DECREMENT_INTERVAL_MAX;
+
+ vdsc_cfg->final_offset = vdsc_cfg->rc_model_size -
+ (vdsc_cfg->initial_xmit_delay *
+vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits;
+
+ if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) {
+ DRM_ERROR("FinalOfs < RcModelSze for this InitialXmitDelay\n");
+ return -1;
+ }
+
+ final_scale = (vdsc_cfg->rc_model_size * 8) /
+ (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset);
+ if (vdsc_cfg->slice_height > 1)
+ /*
+* NflBpgOffset is 16 bit value with 11 fractional bits
+* hence we multiply by 2^11 for preserving the
+* fractional part
+*/
+ vdsc_cfg->nfl_bpg_offset =
DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11),
+ (vdsc_cfg->slice_height
- 1));
+ else
+ vdsc_cfg->nfl_bpg_offset = 0;
+
+ /* 2^16 - 1 */
+ if (vdsc_cfg->nfl_bpg_offset > 65535) {
+ DRM_ERROR("NflBpgOffset is too large for this slice height\n");
+ return -1;
+ }
+
+ /* Number of groups used to code the entire slice */
+ groups_total = groups_per_line * vdsc_cfg->slice_height;
+
+ /* slice_bpg_offset is 16 bit value with 11 fractional bits */
+ vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size -
+ vdsc_cfg->initial_offset +
+ num_extra_mux_bits) << 11),
+ groups_total);
+
+ if (final_scale > 0x9) {
+ /*
+
[Intel-gfx] [PATCH v4 10/25] drm/dsc: Define Rate Control values that do not change over configurations
From: "Srivatsa, Anusha"
DSC has some Rate Control values that remain constant
across all configurations. These are as per the DSC
standard.
v3:
* Define them in drm_dsc.h as they are
DSC constants (Manasi)
v2:
* Add DP_DSC_ prefix (Jani Nikula)
Cc: dri-de...@lists.freedesktop.org
Cc: Manasi Navare
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Gaurav K Singh
Cc: Harry Wentland
Signed-off-by: Anusha Srivatsa
Reviewed-by: Manasi Navare
---
include/drm/drm_dsc.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index e90078faeb56..986f962f38d4 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -18,6 +18,12 @@
#define DSC_SCALE_DECREMENT_INTERVAL_MAX 4095
#define DSC_RANGE_BPG_OFFSET_MASK 0x3f
+/* DSC Rate Control Constants */
+#define DSC_RC_MODEL_SIZE_CONST8192
+#define DSC_RC_EDGE_FACTOR_CONST 6
+#define DSC_RC_TGT_OFFSET_HI_CONST 3
+#define DSC_RC_TGT_OFFSET_LO_CONST 3
+
/* Configuration for a single Rate Control model range */
struct dsc_rc_range_parameters {
/* Min Quantization Parameters allowed for this range */
--
2.18.0
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[Intel-gfx] [PATCH v4 12/25] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state
Basic DSC parameters and DSC configuration data needs to be computed
for each of the requested mode during atomic check. This is
required since for certain modes, valid DSC parameters and config
data might not be computed in which case compression cannot be
enabled for that mode.
For that reason we need to add these params and config structure
to the intel_crtc_state so that if valid this state information
can directly be used while enabling DSC in atomic commit.
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_drv.h | 9 +
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7ea442033a57..7dacc2500c08 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -53,6 +53,7 @@
#include
#include
#include
+#include
#include "i915_params.h"
#include "i915_reg.h"
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c56e3092be25..541372ea11f4 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -898,6 +898,15 @@ struct intel_crtc_state {
/* output format is YCBCR 4:2:0 */
bool ycbcr420;
+
+ /* Display Stream compression state */
+ struct {
+ bool compression_enable;
+ bool dsc_split;
+ u16 compressed_bpp;
+ u8 slice_count;
+ } dsc_params;
+ struct drm_dsc_config dp_dsc_cfg;
};
struct intel_crtc {
--
2.18.0
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[Intel-gfx] [PATCH v4 18/25] drm/i915/dp: Enable/Disable DSC in DP Sink
From: Gaurav K Singh
This patch enables decompression support in sink device
before link training and disables the same during the
DDI disabling.
v2:(From Manasi)
* Change the enable/disable function to take crtc_state
instead of intel_dp as an argument (Manasi)
* Use the compression_enable flag as part of crtc_state (Manasi)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Gaurav K Singh
Signed-off-by: Gaurav K Singh
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_ddi.c | 5 +
drivers/gpu/drm/i915/intel_dp.c | 15 +++
drivers/gpu/drm/i915/intel_drv.h | 3 +++
3 files changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index cd01a09c5e0f..9ecc872081c9 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2906,6 +2906,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder
*encoder,
intel_ddi_init_dp_buf_reg(encoder);
if (!is_mst)
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+ intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
+ DP_DECOMPRESSION_EN);
intel_dp_start_link_train(intel_dp);
if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
intel_dp_stop_link_train(intel_dp);
@@ -3236,6 +3238,9 @@ static void intel_disable_ddi_dp(struct intel_encoder
*encoder,
intel_edp_drrs_disable(intel_dp, old_crtc_state);
intel_psr_disable(intel_dp, old_crtc_state);
intel_edp_backlight_off(old_conn_state);
+ /* Disable the decompression in DP Sink */
+ intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
+ ~DP_DECOMPRESSION_EN);
}
static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 97749f763574..a6703e9f2fbf 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2922,6 +2922,21 @@ static bool downstream_hpd_needs_d0(struct intel_dp
*intel_dp)
intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
}
+void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
+ const struct intel_crtc_state
*crtc_state,
+ int state)
+{
+ int ret;
+
+ if (!crtc_state->dsc_params.compression_enable)
+ return;
+
+ ret = drm_dp_dpcd_writeb(_dp->aux, DP_DSC_ENABLE, state);
+ if (ret < 0)
+ DRM_DEBUG_KMS("Failed to %s sink decompression state\n",
+ state == DP_DECOMPRESSION_EN ? "enable" :
"disable");
+}
+
/* If the sink supports it, try to set the power state appropriately */
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
{
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 5494d5d1452a..6256ff876748 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1700,6 +1700,9 @@ void intel_dp_stop_link_train(struct intel_dp *intel_dp);
int intel_dp_retrain_link(struct intel_encoder *encoder,
struct drm_modeset_acquire_ctx *ctx);
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
+void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
+ const struct intel_crtc_state
*crtc_state,
+ int state);
void intel_dp_encoder_reset(struct drm_encoder *encoder);
void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
void intel_dp_encoder_destroy(struct drm_encoder *encoder);
--
2.18.0
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[Intel-gfx] [PATCH v4 13/25] drm/i915/dp: Compute DSC pipe config in atomic check
DSC params like the enable, compressed bpp, slice ocunt and
dsc_split are added to the intel_crtc_state. These parameters
are set based on the requested mode and available link parameters
during the pipe configuration in atomic check phase.
These values are then later used to populate the remaining DSC
and RC parameters before enbaling DSC in atomic commit.
v8:
* Check for DSC bpc not 0 (manasi)
v7:
* Fix indentation in compute_m_n (Manasi)
v6 (From Gaurav):
* Remove function call of intel_dp_compute_dsc_params() and
invoke intel_dp_compute_dsc_params() in the patch where
it is defined to fix compilation warning (Gaurav)
v5:
Add drm_dsc_cfg in intel_crtc_state (Manasi)
v4:
* Rebase on refactoring of intel_dp_compute_config on tip (Manasi)
* Add a comment why we need to check PSR while enabling DSC (Gaurav)
v3:
* Check PPR > max_cdclock to use 2 VDSC instances (Ville)
v2:
* Add if-else for eDP/DP (Gaurav)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Gaurav K Singh
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/intel_display.c | 20 ++--
drivers/gpu/drm/i915/intel_display.h | 3 +-
drivers/gpu/drm/i915/intel_dp.c | 153 +++
drivers/gpu/drm/i915/intel_dp_mst.c | 2 +-
4 files changed, 148 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 2b77d9350a3a..a7554132bfe0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6471,7 +6471,7 @@ static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc,
pipe_config->fdi_lanes = lane;
- intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
+ intel_link_compute_m_n(pipe_config->pipe_bpp, 0, lane, fdi_dotclock,
link_bw, _config->fdi_m_n, false);
ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
@@ -6708,17 +6708,25 @@ static void compute_m_n(unsigned int m, unsigned int n,
}
void
-intel_link_compute_m_n(int bits_per_pixel, int nlanes,
+intel_link_compute_m_n(int bits_per_pixel, uint16_t compressed_bpp,
+ int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
bool reduce_m_n)
{
m_n->tu = 64;
- compute_m_n(bits_per_pixel * pixel_clock,
- link_clock * nlanes * 8,
- _n->gmch_m, _n->gmch_n,
- reduce_m_n);
+ /* For DSC, Data M/N calculation uses compressed BPP */
+ if (compressed_bpp)
+ compute_m_n(compressed_bpp * pixel_clock,
+ link_clock * nlanes * 8,
+ _n->gmch_m, _n->gmch_n,
+ reduce_m_n);
+ else
+ compute_m_n(bits_per_pixel * pixel_clock,
+ link_clock * nlanes * 8,
+ _n->gmch_m, _n->gmch_n,
+ reduce_m_n);
compute_m_n(pixel_clock, link_clock,
_n->link_m, _n->link_n,
diff --git a/drivers/gpu/drm/i915/intel_display.h
b/drivers/gpu/drm/i915/intel_display.h
index ed474da6c200..3fe52788b4cf 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -402,7 +402,8 @@ struct intel_link_m_n {
(__i)++) \
for_each_if(plane)
-void intel_link_compute_m_n(int bpp, int nlanes,
+void intel_link_compute_m_n(int bpp, uint16_t compressed_bpp,
+ int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
bool reduce_m_n);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 63b7efa10a0f..ade25fbfcdd1 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -47,6 +47,8 @@
/* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
#define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
+#define DP_DSC_MIN_SUPPORTED_BPC 8
+#define DP_DSC_MAX_SUPPORTED_BPC 10
/* DP DSC throughput values used for slice count calculations KPixels/s */
#define DP_DSC_PEAK_PIXEL_RATE 272
@@ -1894,6 +1896,16 @@ static int intel_dp_compute_bpp(struct intel_dp
*intel_dp,
}
}
+ /* If DSC is supported, use the max value reported by panel */
+ if (INTEL_GEN(dev_priv) >= 10 &&
+ drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
+ bpc = min_t(u8,
+ drm_dp_dsc_sink_max_color_depth(intel_dp->dsc_dpcd),
+ DP_DSC_MAX_SUPPORTED_BPC);
+ if (bpc)
+ bpp = 3 * bpc;
+ }
+
return bpp;
}
@@ -1954,14 +1966,11 @@ intel_dp_compute_link_config_wide(struct intel_dp
*intel_dp,
[Intel-gfx] [PATCH v4 11/25] drm/dsc: Add helpers for DSC picture parameter set infoframes
According to Display Stream compression spec 1.2, the picture
parameter set metadata is sent from source to sink device
using the DP Secondary data packet. An infoframe is formed
for the PPS SDP header and PPS SDP payload bytes.
This patch adds helpers to fill the PPS SDP header
and PPS SDP payload according to the DSC 1.2 specification.
v6:
* Use proper sequence points for breaking down the
assignments (Chris Wilson)
* Use SPDX identifier
v5:
Do not use bitfields for DRM structs (Jani N)
v4:
* Use DSC constants for params that dont change across
configurations
v3:
* Add reference to added kernel-docs in Documentation/gpu/drm-kms-helpers.rst
(Daniel Vetter)
v2:
* Add EXPORT_SYMBOL for the drm functions (Manasi)
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Harry Wentland
Signed-off-by: Manasi Navare
Acked-by: Harry Wentland
---
Documentation/gpu/drm-kms-helpers.rst | 12 ++
drivers/gpu/drm/Makefile | 2 +-
drivers/gpu/drm/drm_dsc.c | 223 ++
include/drm/drm_dsc.h | 22 +++
4 files changed, 258 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/drm_dsc.c
diff --git a/Documentation/gpu/drm-kms-helpers.rst
b/Documentation/gpu/drm-kms-helpers.rst
index f9cfcdcdf024..50bb71712f82 100644
--- a/Documentation/gpu/drm-kms-helpers.rst
+++ b/Documentation/gpu/drm-kms-helpers.rst
@@ -223,6 +223,18 @@ MIPI DSI Helper Functions Reference
.. kernel-doc:: drivers/gpu/drm/drm_mipi_dsi.c
:export:
+Display Stream Compression Helper Functions Reference
+=
+
+.. kernel-doc:: drivers/gpu/drm/drm_dsc.c
+ :doc: dsc helpers
+
+.. kernel-doc:: include/drm/drm_dsc.h
+ :internal:
+
+.. kernel-doc:: drivers/gpu/drm/drm_dsc.c
+ :export:
+
Output Probing Helper Functions Reference
=
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index bc6a16a3c36e..8e310fadb95d 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -32,7 +32,7 @@ drm-$(CONFIG_AGP) += drm_agpsupport.o
drm-$(CONFIG_DEBUG_FS) += drm_debugfs.o drm_debugfs_crc.o
drm-$(CONFIG_DRM_LOAD_EDID_FIRMWARE) += drm_edid_load.o
-drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_probe_helper.o \
+drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_dsc.o
drm_probe_helper.o \
drm_plane_helper.o drm_dp_mst_topology.o drm_atomic_helper.o \
drm_kms_helper_common.o drm_dp_dual_mode_helper.o \
drm_simple_kms_helper.o drm_modeset_helper.o \
diff --git a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c
new file mode 100644
index ..21ae8d015afd
--- /dev/null
+++ b/drivers/gpu/drm/drm_dsc.c
@@ -0,0 +1,223 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2018 Intel Corp
+ *
+ * Author:
+ * Manasi Navare
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ * DOC: dsc helpers
+ *
+ * These functions contain some common logic and helpers to deal with VESA
+ * Display Stream Compression standard required for DSC on Display Port/eDP or
+ * MIPI display interfaces.
+ */
+
+/**
+ * drm_dsc_dp_pps_header_init() - Initializes the PPS Header
+ * for DisplayPort as per the DP 1.4 spec.
+ * @pps_sdp: Secondary data packet for DSC Picture Parameter Set
+ */
+void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp)
+{
+ memset(_sdp->pps_header, 0, sizeof(pps_sdp->pps_header));
+
+ pps_sdp->pps_header.HB1 = DP_SDP_PPS;
+ pps_sdp->pps_header.HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1;
+}
+EXPORT_SYMBOL(drm_dsc_dp_pps_header_init);
+
+/**
+ * drm_dsc_pps_infoframe_pack() - Populates the DSC PPS infoframe
+ * using the DSC configuration parameters in the order expected
+ * by the DSC Display Sink device. For the DSC, the sink device
+ * expects the PPS payload in the big endian format for the fields
+ * that span more than 1 byte.
+ *
+ * @pps_sdp:
+ * Secondary data packet for DSC Picture Parameter Set
+ * @dsc_cfg:
+ * DSC Configuration data filled by driver
+ */
+void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
+ struct drm_dsc_config *dsc_cfg)
+{
+ u8 i = 0;
+
+ memset(_sdp->pps_payload, 0, sizeof(pps_sdp->pps_payload));
+
+ /* PPS 0 */
+ pps_sdp->pps_payload.dsc_version =
+ dsc_cfg->dsc_version_minor |
+ dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT;
+
+ /* PPS 1, 2 is 0 */
+
+ /* PPS 3 */
+ pps_sdp->pps_payload.pps_3 =
+ dsc_cfg->line_buf_depth |
+ dsc_cfg->bits_per_component << DSC_PPS_BPC_SHIFT;
+
+ /* PPS 4 */
+ pps_sdp->pps_payload.pps_4 =
+ (u8)((dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >>
+DSC_PPS_MSB_SHIFT) |
+ (u8)dsc_cfg->vbr_enable <<
[Intel-gfx] [PATCH v4 20/25] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling
After encoder->pre_enable() hook, after link training sequence is
completed, PPS registers for DSC encoder are configured using the
DSC state parameters in intel_crtc_state as part of DSC enabling
routine in the source. DSC enabling routine is called after
encoder->pre_enable() before enbaling the pipe and after
compression is enabled on the sink.
v3:
* Configure Pic_width/2 for each VDSC engine when two VDSC engines per pipe
are used (Manasi)
* Add DSC slice_row_per_frame in PPS16 (Manasi)
v2:
* Enable PG2 power well for VDSC on eDP
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/intel_display.c | 6 +
drivers/gpu/drm/i915/intel_vdsc.c| 424 +++
3 files changed, 432 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7dacc2500c08..f085df3f8c29 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3469,6 +3469,8 @@ extern void intel_rps_mark_interactive(struct
drm_i915_private *i915,
bool interactive);
extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
bool enable);
+extern void intel_dsc_enable(struct intel_encoder *encoder,
+struct intel_crtc_state *crtc_state);
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index a7554132bfe0..8010735d55be 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5419,6 +5419,12 @@ static void intel_encoders_pre_enable(struct drm_crtc
*crtc,
if (encoder->pre_enable)
encoder->pre_enable(encoder, crtc_state, conn_state);
+
+ /*
+* Enable and Configure Display Stream Compression in the source
+* if enabled in intel_crtc_state.
+*/
+ intel_dsc_enable(encoder, crtc_state);
}
}
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index 4e4e1e55f249..6eecf6abd4a9 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -580,3 +580,427 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
return 0;
}
+
+static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
+ struct intel_crtc_state
*crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct drm_dsc_config *vdsc_cfg = _state->dp_dsc_cfg;
+ enum pipe pipe = crtc->pipe;
+ u32 pps_val = 0;
+ u32 rc_buf_thresh_dword[4];
+ u32 rc_range_params_dword[8];
+ u8 num_vdsc_instances = (crtc_state->dsc_params.dsc_split) ? 2 : 1;
+ int i = 0;
+
+ /* Populate PICTURE_PARAMETER_SET_0 registers */
+ pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<
+ DSC_VER_MIN_SHIFT |
+ vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
+ vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
+ if (vdsc_cfg->block_pred_enable)
+ pps_val |= DSC_BLOCK_PREDICTION;
+ else
+ pps_val &= ~DSC_BLOCK_PREDICTION;
+ if (vdsc_cfg->convert_rgb)
+ pps_val |= DSC_COLOR_SPACE_CONVERSION;
+ else
+ pps_val &= ~DSC_COLOR_SPACE_CONVERSION;
+ if (vdsc_cfg->enable422)
+ pps_val |= DSC_422_ENABLE;
+ else
+ pps_val &= ~DSC_422_ENABLE;
+ if (vdsc_cfg->vbr_enable)
+ pps_val |= DSC_VBR_ENABLE;
+ else
+ pps_val &= ~DSC_VBR_ENABLE;
+
+ DRM_INFO("PPS0 = 0x%08x\n", pps_val);
+ if (encoder->type == INTEL_OUTPUT_EDP) {
+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_0, pps_val);
+ /*
+* If 2 VDSC instances are needed, configure PPS for second
+* VDSC
+*/
+ if (crtc_state->dsc_params.dsc_split)
+ I915_WRITE(DSCC_PICTURE_PARAMETER_SET_0, pps_val);
+ } else {
+ I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), pps_val);
+ if (crtc_state->dsc_params.dsc_split)
+ I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe),
+ pps_val);
+ }
+
+ /* Populate PICTURE_PARAMETER_SET_1 registers */
+ pps_val = 0;
+ pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel);
+ DRM_INFO("PPS1 = 0x%08x\n", pps_val);
+ if (encoder->type == INTEL_OUTPUT_EDP) {
+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_1, pps_val);
+
[Intel-gfx] [PATCH v4 06/25] drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported
When DSC is supported we need to validate the modes based on the
maximum supported compressed BPP and maximum supported slice count.
This allows us to allow the modes with pixel clock greater than the
available link BW as long as it meets the compressed BPP
and slice count requirements.
v3:
* Use the macro for dsc sink support (Jani N)
v2:
* Properly comment why we are right shifting the bpp value (Anusha)
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_dp.c | 31 ++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 719c2e426c28..63b7efa10a0f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -605,9 +605,12 @@ intel_dp_mode_valid(struct drm_connector *connector,
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct intel_connector *intel_connector = to_intel_connector(connector);
struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
+ struct drm_i915_private *dev_priv = to_i915(connector->dev);
int target_clock = mode->clock;
int max_rate, mode_rate, max_lanes, max_link_clock;
int max_dotclk;
+ u16 dsc_max_output_bpp = 0;
+ u8 dsc_slice_count = 0;
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
return MODE_NO_DBLESCAN;
@@ -630,7 +633,33 @@ intel_dp_mode_valid(struct drm_connector *connector,
max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
mode_rate = intel_dp_link_required(target_clock, 18);
- if (mode_rate > max_rate || target_clock > max_dotclk)
+ /*
+* Output bpp is stored in 6.4 format so right shift by 4 to get the
+* integer value since we support only integer values of bpp.
+*/
+ if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
+ drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
+ if (intel_dp_is_edp(intel_dp)) {
+ dsc_max_output_bpp =
+ drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd)
>> 4;
+ dsc_slice_count =
+
drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
+ true);
+ } else {
+ dsc_max_output_bpp =
+ intel_dp_dsc_get_output_bpp(max_link_clock,
+ max_lanes,
+ target_clock,
+ mode->hdisplay) >>
4;
+ dsc_slice_count =
+ intel_dp_dsc_get_slice_count(intel_dp,
+target_clock,
+mode->hdisplay);
+ }
+ }
+
+ if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count))
||
+ target_clock > max_dotclk)
return MODE_CLOCK_HIGH;
if (mode->clock < 1)
--
2.18.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 21/25] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs
Infoframes are used to send secondary data packets. This patch
adds support for DSC Picture parameter set secondary data packets
in the existing write_infoframe helpers.
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_hdmi.c | 23 +--
2 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6de15f781090..c0225dfa030a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4565,6 +4565,7 @@ enum {
* of the infoframe structure specified by CEA-861. */
#define VIDEO_DIP_DATA_SIZE 32
#define VIDEO_DIP_VSC_DATA_SIZE 36
+#define VIDEO_DIP_PPS_DATA_SIZE 132
#define VIDEO_DIP_CTL _MMIO(0x61170)
/* Pre HSW: */
#define VIDEO_DIP_ENABLE (1 << 31)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index a2dab0b6bde6..5caea48924bd 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -115,6 +115,8 @@ static u32 hsw_infoframe_enable(unsigned int type)
switch (type) {
case DP_SDP_VSC:
return VIDEO_DIP_ENABLE_VSC_HSW;
+ case DP_SDP_PPS:
+ return VDIP_ENABLE_PPS;
case HDMI_INFOFRAME_TYPE_AVI:
return VIDEO_DIP_ENABLE_AVI_HSW;
case HDMI_INFOFRAME_TYPE_SPD:
@@ -136,6 +138,8 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv,
switch (type) {
case DP_SDP_VSC:
return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
+ case DP_SDP_PPS:
+ return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
case HDMI_INFOFRAME_TYPE_AVI:
return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
case HDMI_INFOFRAME_TYPE_SPD:
@@ -148,6 +152,18 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv,
}
}
+static int hsw_dip_data_size(unsigned int type)
+{
+ switch (type) {
+ case DP_SDP_VSC:
+ return VIDEO_DIP_VSC_DATA_SIZE;
+ case DP_SDP_PPS:
+ return VIDEO_DIP_PPS_DATA_SIZE;
+ default:
+ return VIDEO_DIP_DATA_SIZE;
+ }
+}
+
static void g4x_write_infoframe(struct drm_encoder *encoder,
const struct intel_crtc_state *crtc_state,
unsigned int type,
@@ -390,11 +406,14 @@ static void hsw_write_infoframe(struct drm_encoder
*encoder,
struct drm_i915_private *dev_priv = to_i915(dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
- int data_size = type == DP_SDP_VSC ?
- VIDEO_DIP_VSC_DATA_SIZE : VIDEO_DIP_DATA_SIZE;
+ i915_reg_t data_reg;
+ int data_size = 0;
int i;
u32 val = I915_READ(ctl_reg);
+ data_size = hsw_dip_data_size(type);
+ data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0);
+
val &= ~hsw_infoframe_enable(type);
I915_WRITE(ctl_reg, val);
--
2.18.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 03/25] drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init
DSC is supported on eDP starting GEN 10 display (on GLK) and on DP starting
GEN 11.
This patch implements the discovery phase of DSC. On hotplug,
source reads the DSC DPCD register set (0x00060 - 0x0006F) to
read the decompression capabilities of the sink device.
This entire block of registers is cached in intel_dp so that
capability information can be used during DSC configuration
phase during compute_config phase of the modeset.
For eDP, this caching happens during the eDP initialization.
This caching is done only for eDP and DP rev >= 1.4
v5:
* Fix the block comment (Gaurav)
* Fix the commit message DSC DPCD addresses (Gaurav)
* Use DRM_ERROR for dpcd_read fail (Gaurav,Anusha)
v4:
* Cache these only for Gen >= 11
v3:
* Remove the dsc_sink_support field in intel_dp (Jani N)
v2:
* Clear the cached registers on hotplug always (Jani N)
* Combine the eDP and DP caching in same function (Jani N)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Daniel Vetter
Cc: Anusha Srivatsa
Cc: Gaurav K Singh
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
Reviewed-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_dp.c | 32
drivers/gpu/drm/i915/intel_drv.h | 1 +
2 files changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 436c22de33b6..1dfcceb55182 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3870,6 +3870,29 @@ intel_dp_read_dpcd(struct intel_dp *intel_dp)
return intel_dp->dpcd[DP_DPCD_REV] != 0;
}
+static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
+{
+ /*
+*Clear the cached register set to avoid using stale values
+* for the sinks that do not support DSC.
+*/
+ memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
+
+ /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
+ if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
+ intel_dp->edp_dpcd[0] >= DP_EDP_14) {
+ if (drm_dp_dpcd_read(_dp->aux, DP_DSC_SUPPORT,
+intel_dp->dsc_dpcd,
+sizeof(intel_dp->dsc_dpcd)) < 0)
+ DRM_ERROR("Failed to read DPCD register 0x%x\n",
+ DP_DSC_SUPPORT);
+
+ DRM_DEBUG_KMS("DSC DPCD: %*ph\n",
+ (int)sizeof(intel_dp->dsc_dpcd),
+ intel_dp->dsc_dpcd);
+ }
+}
+
static bool
intel_edp_init_dpcd(struct intel_dp *intel_dp)
{
@@ -3946,6 +3969,10 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
intel_dp_set_common_rates(intel_dp);
+ /* Read the eDP DSC DPCD registers */
+ if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ intel_dp_get_dsc_sink_cap(intel_dp);
+
return true;
}
@@ -5034,6 +5061,7 @@ intel_dp_long_pulse(struct intel_connector *connector,
if (status == connector_status_disconnected) {
memset(_dp->compliance, 0, sizeof(intel_dp->compliance));
+ memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
if (intel_dp->is_mst) {
DRM_DEBUG_KMS("MST device may have disappeared %d vs
%d\n",
@@ -5059,6 +5087,10 @@ intel_dp_long_pulse(struct intel_connector *connector,
intel_dp_print_rates(intel_dp);
+ /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
+ if (INTEL_GEN(dev_priv) >= 11)
+ intel_dp_get_dsc_sink_cap(intel_dp);
+
drm_dp_read_desc(_dp->aux, _dp->desc,
drm_dp_is_branch(intel_dp->dpcd));
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f5731215210a..0828fcb7af90 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1073,6 +1073,7 @@ struct intel_dp {
uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
+ u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
/* source rates */
int num_source_rates;
const int *source_rates;
--
2.18.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 09/25] drm/dsc: Define VESA Display Stream Compression Capabilities
From: Gaurav K Singh
This defines all the DSC parameters as per the VESA DSC spec
that will be required for DSC encoder/decoder
v6: (From Manasi)
* Add a bit mask for RANGE_BPG_OFFSET for 6 bits(Manasi)
v5 (From Manasi)
* Add the RC constants as per the spec
v4 (From Manasi)
* Add the DSC_MUX_WORD_SIZE constants (Manasi)
v3 (From Manasi)
* Remove the duplicate define (Suggested By:Harry Wentland)
v2: Define this struct in DRM (From Manasi)
* Changed the data types to u8/u16 instead of unsigned longs (Manasi)
* Remove driver specific fields (Manasi)
* Move this struct definition to DRM (Manasi)
* Define DSC 1.2 parameters (Manasi)
* Use DSC_NUM_BUF_RANGES (Manasi)
* Call it drm_dsc_config (Manasi)
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Harry Wentland
Signed-off-by: Manasi Navare
Signed-off-by: Gaurav K Singh
Co-developed-by: Manasi Navare
Acked-by: Harry Wentland
Reviewed-by: Anusha Srivatsa
---
include/drm/drm_dsc.h | 115 +-
1 file changed, 114 insertions(+), 1 deletion(-)
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index 1d8a03983b90..e90078faeb56 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -11,7 +11,120 @@
#include
/* VESA Display Stream Compression DSC 1.2 constants */
-#define DSC_NUM_BUF_RANGES 15
+#define DSC_NUM_BUF_RANGES 15
+#define DSC_MUX_WORD_SIZE_8_10_BPC 48
+#define DSC_MUX_WORD_SIZE_12_BPC 64
+#define DSC_RC_PIXELS_PER_GROUP3
+#define DSC_SCALE_DECREMENT_INTERVAL_MAX 4095
+#define DSC_RANGE_BPG_OFFSET_MASK 0x3f
+
+/* Configuration for a single Rate Control model range */
+struct dsc_rc_range_parameters {
+ /* Min Quantization Parameters allowed for this range */
+ u8 range_min_qp;
+ /* Max Quantization Parameters allowed for this range */
+ u8 range_max_qp;
+ /* Bits/group offset to apply to target for this group */
+ u8 range_bpg_offset;
+};
+
+struct drm_dsc_config {
+ /* Bits / component for previous reconstructed line buffer */
+ u8 line_buf_depth;
+ /* Bits per component to code (must be 8, 10, or 12) */
+ u8 bits_per_component;
+ /*
+* Flag indicating to do RGB - YCoCg conversion
+* and back (should be 1 for RGB input)
+*/
+ bool convert_rgb;
+ u8 slice_count;
+ /* Slice Width */
+ u16 slice_width;
+ /* Slice Height */
+ u16 slice_height;
+ /*
+* 4:2:2 enable mode (from PPS, 4:2:2 conversion happens
+* outside of DSC encode/decode algorithm)
+*/
+ bool enable422;
+ /* Picture Width */
+ u16 pic_width;
+ /* Picture Height */
+ u16 pic_height;
+ /* Offset to bits/group used by RC to determine QP adjustment */
+ u8 rc_tgt_offset_high;
+ /* Offset to bits/group used by RC to determine QP adjustment */
+ u8 rc_tgt_offset_low;
+ /* Bits/pixel target << 4 (ie., 4 fractional bits) */
+ u16 bits_per_pixel;
+ /*
+* Factor to determine if an edge is present based
+* on the bits produced
+*/
+ u8 rc_edge_factor;
+ /* Slow down incrementing once the range reaches this value */
+ u8 rc_quant_incr_limit1;
+ /* Slow down incrementing once the range reaches this value */
+ u8 rc_quant_incr_limit0;
+ /* Number of pixels to delay the initial transmission */
+ u16 initial_xmit_delay;
+ /* Number of pixels to delay the VLD on the decoder,not including SSM */
+ u16 initial_dec_delay;
+ /* Block prediction enable */
+ bool block_pred_enable;
+ /* Bits/group offset to use for first line of the slice */
+ u8 first_line_bpg_offset;
+ /* Value to use for RC model offset at slice start */
+ u16 initial_offset;
+ /* Thresholds defining each of the buffer ranges */
+ u16 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1];
+ /* Parameters for each of the RC ranges */
+ struct dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
+ /* Total size of RC model */
+ u16 rc_model_size;
+ /* Minimum QP where flatness information is sent */
+ u8 flatness_min_qp;
+ /* Maximum QP where flatness information is sent */
+ u8 flatness_max_qp;
+ /* Initial value for scale factor */
+ u8 initial_scale_value;
+ /* Decrement scale factor every scale_decrement_interval groups */
+ u16 scale_decrement_interval;
+ /* Increment scale factor every scale_increment_interval groups */
+ u16 scale_increment_interval;
+ /* Non-first line BPG offset to use */
+ u16 nfl_bpg_offset;
+ /* BPG offset used to enforce slice bit */
+ u16 slice_bpg_offset;
+ /* Final RC linear transformation offset value */
+ u16 final_offset;
+ /* Enable
[Intel-gfx] [PATCH v4 05/25] drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC
This patch adds helpers for calculating the maximum compressed BPP
supported with small joiner.
This also adds a helper for calculating the slice count in case
of small joiner.
These are inside intel_dp since they take into account hardware
limitations.
v6:
* Take mode_clock and mode_hdisplay as input arguments
so that this can be called in intel_dp_mode_valid (Manasi)
v5:
* Get the max slice width from DPCD
* Check against Min_Slice_width of 2560 (Anusha)
v4:
* #defines for PPR in slice count helper (Gaurav)
v3:
* Simply logic for bpp (DK)
* Limit the valid slice count by max supported by Sink (Manasi)
v2:
* Change the small joiner RAM buffer constant as bspec changed (Manasi)
* rename it as SMALL_JOINER since we are not enabling big joiner yet (Anusha)
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Dhinakaran Pandiyan
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_dp.c | 104 +++
drivers/gpu/drm/i915/intel_drv.h | 4 ++
2 files changed, 108 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 1dfcceb55182..719c2e426c28 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -45,6 +45,17 @@
#define DP_DPRX_ESI_LEN 14
+/* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
+#define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
+
+/* DP DSC throughput values used for slice count calculations KPixels/s */
+#define DP_DSC_PEAK_PIXEL_RATE 272
+#define DP_DSC_MAX_ENC_THROUGHPUT_034
+#define DP_DSC_MAX_ENC_THROUGHPUT_140
+
+/* DP DSC FEC Overhead factor = (100 - 2.4)/100 */
+#define DP_DSC_FEC_OVERHEAD_FACTOR 976
+
/* Compliance test status bits */
#define INTEL_DP_RESOLUTION_SHIFT_MASK 0
#define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
@@ -93,6 +104,14 @@ static const struct dp_link_dpll chv_dpll[] = {
{ .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c0 } },
};
+/* Constants for DP DSC configurations */
+static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
+
+/* With Single pipe configuration, HW is capable of supporting maximum
+ * of 4 slices per line.
+ */
+static const u8 valid_dsc_slicecount[] = {1, 2, 4};
+
/**
* intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or
PCH)
* @intel_dp: DP struct
@@ -4080,6 +4099,91 @@ intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8
*sink_irq_vector)
DP_DPRX_ESI_LEN;
}
+uint16_t intel_dp_dsc_get_output_bpp(int link_clock, uint8_t lane_count,
+int mode_clock, int mode_hdisplay)
+{
+ u16 bits_per_pixel, max_bpp_small_joiner_ram;
+ int i;
+
+ /*
+* Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
+* (LinkSymbolClock)* 8 * ((100-FECOverhead)/100)*(TimeSlotsPerMTP)
+* FECOverhead = 2.4%, for SST -> TimeSlotsPerMTP is 1,
+* for MST -> TimeSlotsPerMTP has to be calculated
+*/
+ bits_per_pixel = (link_clock * lane_count * 8 *
+ DP_DSC_FEC_OVERHEAD_FACTOR) /
+ mode_clock;
+
+ /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
+ max_bpp_small_joiner_ram = DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER /
+ mode_hdisplay;
+
+ /*
+* Greatest allowed DSC BPP = MIN (output BPP from avaialble Link BW
+* check, output bpp from small joiner RAM check)
+*/
+ bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
+
+ /* Error out if the max bpp is less than smallest allowed valid bpp */
+ if (bits_per_pixel < valid_dsc_bpp[0]) {
+ DRM_DEBUG_KMS("Unsupported BPP %d\n", bits_per_pixel);
+ return 0;
+ }
+
+ /* Find the nearest match in the array of known BPPs from VESA */
+ for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
+ if (bits_per_pixel < valid_dsc_bpp[i + 1])
+ break;
+ }
+ bits_per_pixel = valid_dsc_bpp[i];
+
+ /*
+* Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
+* fractional part is 0
+*/
+ return bits_per_pixel << 4;
+}
+
+uint8_t intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
+int mode_clock,
+int mode_hdisplay)
+{
+ u8 min_slice_count, i;
+ int max_slice_width;
+
+ if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
+ min_slice_count = DIV_ROUND_UP(mode_clock,
+ DP_DSC_MAX_ENC_THROUGHPUT_0);
+ else
+ min_slice_count = DIV_ROUND_UP(mode_clock,
+ DP_DSC_MAX_ENC_THROUGHPUT_1);
+
+ max_slice_width =
[Intel-gfx] [PATCH v4 02/25] drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT
This patch defines the DP DSC receiver capability size that gives total number of DP DSC DPCD registers. This also adds a missing #defines for DP DSC support missed in the commit id (ab6a46ea6842ce "Add DPCD definitions for DP 1.4 DSC feature") v3: * MIN_SLICE_WIDTH = 2560 (Anusha) * Define DP_DSC_SLICE_WIDTH_MULTIPLIER = 320 v2: * Add SHIFT define and DECOMPRESSION_EN define missed in prev patch Cc: dri-de...@lists.freedesktop.org Cc: Jani Nikula Cc: Ville Syrjala Cc: Anusha Srivatsa Cc: Gaurav K Singh Signed-off-by: Manasi Navare Reviewed-by: Anusha Srivatsa --- include/drm/drm_dp_helper.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 698082a02b97..7f6237cad10d 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -231,6 +231,8 @@ #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */ #define DP_DSC_MAX_BITS_PER_PIXEL_HI0x068 /* eDP 1.4 */ +# define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0) +# define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8 #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069 # define DP_DSC_RGB (1 << 0) @@ -279,6 +281,8 @@ # define DP_DSC_THROUGHPUT_MODE_1_1000 (14 << 4) #define DP_DSC_MAX_SLICE_WIDTH 0x06C +#define DP_DSC_MIN_SLICE_WIDTH_VALUE2560 +#define DP_DSC_SLICE_WIDTH_MULTIPLIER 320 #define DP_DSC_SLICE_CAP_2 0x06D # define DP_DSC_16_PER_DP_DSC_SINK (1 << 0) @@ -477,6 +481,7 @@ # define DP_AUX_FRAME_SYNC_VALID (1 << 0) #define DP_DSC_ENABLE 0x160 /* DP 1.4 */ +# define DP_DECOMPRESSION_EN(1 << 0) #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ # define DP_PSR_ENABLE (1 << 0) @@ -963,6 +968,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI #define DP_BRANCH_OUI_HEADER_SIZE 0xc #define DP_RECEIVER_CAP_SIZE 0xf +#define DP_DSC_RECEIVER_CAP_SIZE0xf #define EDP_PSR_RECEIVER_CAP_SIZE 2 #define EDP_DISPLAY_CTL_CAP_SIZE 3 -- 2.18.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 04/25] drm/dp: DRM DP helper/macros to get DP sink DSC parameters
This patch adds inline functions and helpers for obtaining
DP sink's supported DSC parameters like DSC sink support,
eDP compressed BPP supported, maximum slice count supported
by the sink devices, DSC line buffer bit depth supported on DP sink,
DSC sink maximum color depth by parsing corresponding DPCD registers.
v4:
* Add helper to give line buf bit depth (Manasi)
* Correct the bit masking in color depth helper (manasi)
v3:
* Use SLICE_CAP_2 for DP (Anusha)
v2:
* Add DSC sink support macro (Jani N)
Cc: Gaurav K Singh
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/drm_dp_helper.c | 90 +
include/drm/drm_dp_helper.h | 30 +++
2 files changed, 120 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 8c6b9fd89f8a..5d5879f115ce 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1337,3 +1337,93 @@ int drm_dp_read_desc(struct drm_dp_aux *aux, struct
drm_dp_desc *desc,
return 0;
}
EXPORT_SYMBOL(drm_dp_read_desc);
+
+/**
+ * DRM DP Helpers for DSC
+ */
+u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
+ bool is_edp)
+{
+ u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT];
+
+ if (is_edp) {
+ /* For eDP, register DSC_SLICE_CAPABILITIES_1 gives slice count
*/
+ if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
+ return 4;
+ if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
+ return 2;
+ if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
+ return 1;
+ } else {
+ /* For DP, use values from DSC_SLICE_CAP_1 and DSC_SLICE_CAP2 */
+ u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT];
+
+ if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK)
+ return 24;
+ if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK)
+ return 20;
+ if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK)
+ return 16;
+ if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK)
+ return 12;
+ if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK)
+ return 10;
+ if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK)
+ return 8;
+ if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK)
+ return 6;
+ if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
+ return 4;
+ if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
+ return 2;
+ if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
+ return 1;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count);
+
+u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
+{
+ u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH -
DP_DSC_SUPPORT];
+
+ switch (line_buf_depth & DP_DSC_LINE_BUF_BIT_DEPTH_MASK) {
+ case DP_DSC_LINE_BUF_BIT_DEPTH_9:
+ return 9;
+ case DP_DSC_LINE_BUF_BIT_DEPTH_10:
+ return 10;
+ case DP_DSC_LINE_BUF_BIT_DEPTH_11:
+ return 11;
+ case DP_DSC_LINE_BUF_BIT_DEPTH_12:
+ return 12;
+ case DP_DSC_LINE_BUF_BIT_DEPTH_13:
+ return 13;
+ case DP_DSC_LINE_BUF_BIT_DEPTH_14:
+ return 14;
+ case DP_DSC_LINE_BUF_BIT_DEPTH_15:
+ return 15;
+ case DP_DSC_LINE_BUF_BIT_DEPTH_16:
+ return 16;
+ case DP_DSC_LINE_BUF_BIT_DEPTH_8:
+ return 8;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth);
+
+u8 drm_dp_dsc_sink_max_color_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
+{
+ u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];
+
+ if (color_depth & DP_DSC_12_BPC)
+ return 12;
+ if (color_depth & DP_DSC_10_BPC)
+ return 10;
+ if (color_depth & DP_DSC_8_BPC)
+ return 8;
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_dsc_sink_max_color_depth);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 7f6237cad10d..ce6297908fd6 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1065,6 +1065,36 @@ drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT;
}
+/* DP/eDP DSC support */
+u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
+ bool is_edp);
+u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
+u8
[Intel-gfx] linux-next: manual merge of the drm-misc tree with the drm tree
Hi all,
Today's linux-next merge of the drm-misc tree got a conflict in:
drivers/gpu/drm/i915/intel_display.h
between commit:
dce888798d3e ("drm/i915: remove confusing GPIO vs PCH_GPIO")
from the drm tree and commit:
d78aa650670d ("drm: Add drm/drm_util.h header file")
from the drm-misc tree.
I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging. You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.
--
Cheers,
Stephen Rothwell
diff --cc drivers/gpu/drm/i915/intel_display.h
index e20e6a36a748,809c06ae4c07..
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@@ -25,22 -25,8 +25,24 @@@
#ifndef _INTEL_DISPLAY_H_
#define _INTEL_DISPLAY_H_
+ #include
+
+enum i915_gpio {
+ GPIOA,
+ GPIOB,
+ GPIOC,
+ GPIOD,
+ GPIOE,
+ GPIOF,
+ GPIOG,
+ GPIOH,
+ __GPIOI_UNUSED,
+ GPIOJ,
+ GPIOK,
+ GPIOL,
+ GPIOM,
+};
+
enum pipe {
INVALID_PIPE = -1,
pgpCKr0_j9MHS.pgp
Description: OpenPGP digital signature
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/3] drm: add LG eDP panel to quirk database
On Mon, 2018-09-10 at 14:43 +0300, Jani Nikula wrote:
> On Mon, 10 Sep 2018, "Lee, Shawn C" wrote:
> > The N value was computed by kernel driver that based on synchronous
> > clock
> > mode. But only specific N value (0x8000) would be acceptable for
> > LG LP140WF6-SPM1 eDP panel which is running at asynchronous clock
> > mode.
> > With the other N value, Tcon will enter BITS mode and display black
> > screen.
> > Add this panel into quirk database and give particular N value when
> > calculate M/N divider.
> >
> > Cc: Jani Nikula
> > Cc: Cooper Chiou
> > Cc: Matt Atwood
> > Cc: Maarten Lankhorst
> > Cc: Dhinakaran Pandiyan
> > Cc: Clint Taylor
> > Signed-off-by: Lee, Shawn C
>
> No access to the panel or its details, so instead of review,
>
> Acked-by: Jani Nikula
>
> > ---
> > drivers/gpu/drm/drm_dp_helper.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/drm_dp_helper.c
> > b/drivers/gpu/drm/drm_dp_helper.c
> > index d0c1250975ab..0ef7c43a9025 100644
> > --- a/drivers/gpu/drm/drm_dp_helper.c
> > +++ b/drivers/gpu/drm/drm_dp_helper.c
> > @@ -1270,6 +1270,8 @@ struct dpcd_quirk {
> > static const struct dpcd_quirk dpcd_quirk_list[] = {
> > /* Analogix 7737 needs reduced M and N at HBR2 link rates
> > */
> > { OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true,
Wonder if DEVICE_ID_ANY still the accurate criteria for these dongles
now that we can check against device IDs. I guess, since the quirk
fixes multiple dongles we probably can't check against a single device
ID.
> > BIT(DP_DPCD_QUIRK_CONSTANT_N) },
> > + /* LG LP140WF6-SPM1 eDP panel */
If you are resending the patches, it might be worth updating the
comment to
/* LG LP140WF6-SPM1 eDP panel needs N value of 0x8000 */
> > + { OUI(0x00, 0x22, 0xb9), DEVICE_ID('s', 'i', 'v', 'a',
> > 'r', 'T'), false, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
> > };
> >
> > #undef OUI
>
>
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Re: [Intel-gfx] [PATCH v2 1/3] drm: Add support for device_id based detection.
On Mon, 2018-09-10 at 08:26 -0700, Lee, Shawn C wrote:
> DP quirk list just compare sink or branch device's OUI so far.
> That means particular vendor's products will be applied specific
> change. This change would confirm device_id the same or not.
> Then driver can implement some changes for branch/sink device
> that really need additional WA.
>
> Cc: Jani Nikula
> Cc: Cooper Chiou
> Cc: Matt Atwood
> Cc: Maarten Lankhorst
> Cc: Dhinakaran Pandiyan
> Cc: Clint Taylor
> Signed-off-by: Lee, Shawn C
> ---
> drivers/gpu/drm/drm_dp_helper.c | 15 ++-
> 1 file changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c
> b/drivers/gpu/drm/drm_dp_helper.c
> index 0cccbcb2d03e..0362c645d96e 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -1256,15 +1256,20 @@ EXPORT_SYMBOL(drm_dp_stop_crc);
>
> struct dpcd_quirk {
> u8 oui[3];
> + u8 device_id[6];
> bool is_branch;
With device id included, do we still need is_branch?
> u32 quirks;
> };
>
> #define OUI(first, second, third) { (first), (second), (third) }
> +#define DEVICE_ID(first, second, third, fourth, fifth, sixth) \
> + { (first), (second), (third), (fourth), (fifth), (sixth) }
> +
> +#define DEVICE_ID_ANYDEVICE_ID(0, 0, 0, 0, 0, 0)
>
> static const struct dpcd_quirk dpcd_quirk_list[] = {
> /* Analogix 7737 needs reduced M and N at HBR2 link rates */
> - { OUI(0x00, 0x22, 0xb9), true,
> BIT(DP_DPCD_QUIRK_LIMITED_M_N) },
> + { OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true,
> BIT(DP_DPCD_QUIRK_LIMITED_M_N) },
> };
>
> #undef OUI
> @@ -1283,6 +1288,7 @@ drm_dp_get_quirks(const struct
> drm_dp_dpcd_ident *ident, bool is_branch)
> const struct dpcd_quirk *quirk;
> u32 quirks = 0;
> int i;
> + u8 any_device[] = DEVICE_ID_ANY;
>
> for (i = 0; i < ARRAY_SIZE(dpcd_quirk_list); i++) {
> quirk = _quirk_list[i];
> @@ -1293,12 +1299,19 @@ drm_dp_get_quirks(const struct
> drm_dp_dpcd_ident *ident, bool is_branch)
Update documentation that currently says -
"* For now, only the OUI (first three bytes) is used, but this may be
extended
* to device identification string ..."
> if (memcmp(quirk->oui, ident->oui, sizeof(ident-
> >oui)) != 0)
> continue;
>
> + if (memcmp(quirk->device_id, any_device,
> sizeof(any_device)) != 0 &&
> + memcmp(quirk->device_id, ident->device_id,
> sizeof(ident->device_id)) != 0)
> + continue;
> +
> quirks |= quirk->quirks;
> }
>
> return quirks;
> }
>
> +#undef DEVICE_ID_ANY
> +#undef DEVICE_ID
> +
> /**
> * drm_dp_read_desc - read sink/branch descriptor from DPCD
> * @aux: DisplayPort AUX channel
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[Intel-gfx] [PULL] drm-intel-fixes
Hi Dave, Here goes drm-intel-fixes-2018-09-11: This contains a regression fix for video playbacks on gen 2 hardware, a IPS timeout error suppression on Broadwell and GVT bucked with "Most critical one is to fix KVM's mm reference when we access guest memory, issue was raised by Linus [1], and another one with virtual opregion fix." [1] - https://lists.freedesktop.org/archives/intel-gvt-dev/2018-August/004130.html Thanks, Rodrigo. The following changes since commit 11da3a7f84f19c26da6f86af878298694ede0804: Linux 4.19-rc3 (2018-09-09 17:26:43 -0700) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2018-09-11 for you to fetch changes up to 17dc7af70e89db773a7213f0b4270c69236a63ab: drm/i915/overlay: Allocate physical registers from stolen (2018-09-11 08:24:03 -0700) This contains a regression fix for video playbacks on gen 2 hardware, a IPS timeout error suppression on Broadwell and GVT bucked with "Most critical one is to fix KVM's mm reference when we access guest memory, issue was raised by Linus [1], and another one with virtual opregion fix." [1] - https://lists.freedesktop.org/archives/intel-gvt-dev/2018-August/004130.html Chris Wilson (1): drm/i915/overlay: Allocate physical registers from stolen Imre Deak (1): drm/i915/bdw: Increase IPS disable timeout to 100ms Rodrigo Vivi (1): Merge tag 'gvt-fixes-2018-09-10' of https://github.com/intel/gvt-linux into drm-intel-fixes Weinan Li (1): drm/i915/gvt: Fix the incorrect length of child_device_config issue Zhenyu Wang (1): drm/i915/gvt: Fix life cycle reference on KVM mm drivers/gpu/drm/i915/gvt/kvmgt.c | 10 +- drivers/gpu/drm/i915/gvt/opregion.c | 20 ++- drivers/gpu/drm/i915/intel_display.c | 8 +- drivers/gpu/drm/i915/intel_overlay.c | 228 --- 4 files changed, 98 insertions(+), 168 deletions(-) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fix a potential integer overflow with framebuffers extending past 4 GiB
== Series Details == Series: drm/i915: Fix a potential integer overflow with framebuffers extending past 4 GiB URL : https://patchwork.freedesktop.org/series/49495/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4801_full -> Patchwork_10144_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_10144_full that come from known issues: === IGT changes === Issues hit igt@gem_exec_schedule@pi-ringfull-bsd: shard-glk: NOTRUN -> FAIL (fdo#103158) igt@kms_available_modes_crc@available_mode_test_crc: shard-glk: NOTRUN -> FAIL (fdo#106641) igt@kms_cursor_crc@cursor-256x85-random: shard-kbl: PASS -> DMESG-WARN (fdo#105345) Possible fixes igt@gem_eio@in-flight-suspend: shard-glk: INCOMPLETE (k.org#198133, fdo#103359) -> PASS igt@kms_setmode@basic: shard-apl: FAIL (fdo#99912) -> PASS fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#105345 https://bugs.freedesktop.org/show_bug.cgi?id=105345 fdo#106641 https://bugs.freedesktop.org/show_bug.cgi?id=106641 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4801 -> Patchwork_10144 CI_DRM_4801: 47eb47da6081c676a6f9e6046db5a72fa7d22ef4 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4638: 20a7ead8bdf09774c7d58fcbe6a0980d08ed5365 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10144: 2eb7a152755603e9a9228c43dce43415e03d4097 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10144/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Protect against wrong reg offset and warn.
Em Ter, 2018-09-11 às 14:26 -0700, Rodrigo Vivi escreveu: > On Tue, Sep 11, 2018 at 01:39:53PM -0700, Paulo Zanoni wrote: > > Em Dom, 2018-09-02 às 22:15 -0700, Rodrigo Vivi escreveu: > > > In case we forget to change intel_port_is_tc > > > we would be trying to access registers with port == -1, > > > i.e. PORT_TC_NONE, what would be wrong offset. > > > > > > > There are some many things that would break if intel_port_is_tc() > > is > > incorrect that we would have to add a few dozen more WARNs. Why add > > this specific check at this specific case and not all other checks > > in > > other possible cases that could break? > > because static analyzer tools just bother to inform us about this > case here... > > but I can mark that as intentional/false-positive/impossible/don't- > bother-anymore > and just move one if you think this is really un impossible > possibility It's not impossible: every future platform that has TC has the potential to hit it until someone fixes it. So there is some value to the WARN. I was just wondering why add the code specifically here, maybe this is not the best place, but it is. Perhaps breaking intel_port_is_tc by purpose on ICL and trying to boot it would tell us the appropriate places to add WARNs and return :). > > > > > > > So let's just add a protection and warn here. > > > > > > Cc: Paulo Zanoni > > > Signed-off-by: Rodrigo Vivi > > > --- > > > drivers/gpu/drm/i915/intel_dp.c | 3 +++ > > > 1 file changed, 3 insertions(+) > > > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c > > > b/drivers/gpu/drm/i915/intel_dp.c > > > index 436c22de33b6..6a93fa9bbbd9 100644 > > > --- a/drivers/gpu/drm/i915/intel_dp.c > > > +++ b/drivers/gpu/drm/i915/intel_dp.c > > > @@ -4886,6 +4886,9 @@ static bool icl_tc_port_connected(struct > > > drm_i915_private *dev_priv, > > > bool is_legacy, is_typec, is_tbt; > > > u32 dpsp; > > > > > > + if (WARN_ON(tc_port == PORT_TC_NONE)) > > > + return false; > > > + > > > is_legacy = I915_READ(SDEISR) & > > > SDE_TC_HOTPLUG_ICP(tc_port); > > > > > > /* > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Put all permanent stolen allocations together
== Series Details == Series: drm/i915: Put all permanent stolen allocations together URL : https://patchwork.freedesktop.org/series/49485/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4801_full -> Patchwork_10143_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_10143_full that come from known issues: === IGT changes === Issues hit igt@gem_exec_schedule@pi-ringfull-bsd: shard-glk: NOTRUN -> FAIL (fdo#103158) igt@kms_available_modes_crc@available_mode_test_crc: shard-glk: NOTRUN -> FAIL (fdo#106641) igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: shard-glk: NOTRUN -> FAIL (fdo#105363) Possible fixes igt@gem_eio@in-flight-suspend: shard-glk: INCOMPLETE (k.org#198133, fdo#103359) -> PASS igt@kms_setmode@basic: shard-apl: FAIL (fdo#99912) -> PASS fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#106641 https://bugs.freedesktop.org/show_bug.cgi?id=106641 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4801 -> Patchwork_10143 CI_DRM_4801: 47eb47da6081c676a6f9e6046db5a72fa7d22ef4 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4638: 20a7ead8bdf09774c7d58fcbe6a0980d08ed5365 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10143: 5aca5b253d2522becd92748b5a05773c3ad18e78 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10143/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Protect against wrong reg offset and warn.
On Tue, Sep 11, 2018 at 01:39:53PM -0700, Paulo Zanoni wrote: > Em Dom, 2018-09-02 às 22:15 -0700, Rodrigo Vivi escreveu: > > In case we forget to change intel_port_is_tc > > we would be trying to access registers with port == -1, > > i.e. PORT_TC_NONE, what would be wrong offset. > > > > There are some many things that would break if intel_port_is_tc() is > incorrect that we would have to add a few dozen more WARNs. Why add > this specific check at this specific case and not all other checks in > other possible cases that could break? because static analyzer tools just bother to inform us about this case here... but I can mark that as intentional/false-positive/impossible/don't-bother-anymore and just move one if you think this is really un impossible possibility > > > > So let's just add a protection and warn here. > > > > Cc: Paulo Zanoni > > Signed-off-by: Rodrigo Vivi > > --- > > drivers/gpu/drm/i915/intel_dp.c | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c > > b/drivers/gpu/drm/i915/intel_dp.c > > index 436c22de33b6..6a93fa9bbbd9 100644 > > --- a/drivers/gpu/drm/i915/intel_dp.c > > +++ b/drivers/gpu/drm/i915/intel_dp.c > > @@ -4886,6 +4886,9 @@ static bool icl_tc_port_connected(struct > > drm_i915_private *dev_priv, > > bool is_legacy, is_typec, is_tbt; > > u32 dpsp; > > > > + if (WARN_ON(tc_port == PORT_TC_NONE)) > > + return false; > > + > > is_legacy = I915_READ(SDEISR) & SDE_TC_HOTPLUG_ICP(tc_port); > > > > /* ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Protect against wrong reg offset and warn.
Em Dom, 2018-09-02 às 22:15 -0700, Rodrigo Vivi escreveu: > In case we forget to change intel_port_is_tc > we would be trying to access registers with port == -1, > i.e. PORT_TC_NONE, what would be wrong offset. > There are some many things that would break if intel_port_is_tc() is incorrect that we would have to add a few dozen more WARNs. Why add this specific check at this specific case and not all other checks in other possible cases that could break? > So let's just add a protection and warn here. > > Cc: Paulo Zanoni > Signed-off-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/intel_dp.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c > b/drivers/gpu/drm/i915/intel_dp.c > index 436c22de33b6..6a93fa9bbbd9 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -4886,6 +4886,9 @@ static bool icl_tc_port_connected(struct > drm_i915_private *dev_priv, > bool is_legacy, is_typec, is_tbt; > u32 dpsp; > > + if (WARN_ON(tc_port == PORT_TC_NONE)) > + return false; > + > is_legacy = I915_READ(SDEISR) & SDE_TC_HOTPLUG_ICP(tc_port); > > /* ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Display gtt remapping prep stuff (rev2)
== Series Details == Series: drm/i915: Display gtt remapping prep stuff (rev2) URL : https://patchwork.freedesktop.org/series/49354/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4801_full -> Patchwork_10142_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_10142_full that come from known issues: === IGT changes === Issues hit igt@gem_exec_schedule@pi-ringfull-bsd: shard-glk: NOTRUN -> FAIL (fdo#103158) igt@gem_wait@basic-wait-write-all: shard-snb: PASS -> INCOMPLETE (fdo#105411) igt@kms_available_modes_crc@available_mode_test_crc: shard-glk: NOTRUN -> FAIL (fdo#106641) Possible fixes igt@gem_eio@in-flight-suspend: shard-glk: INCOMPLETE (fdo#103359, k.org#198133) -> PASS igt@kms_setmode@basic: shard-kbl: FAIL (fdo#99912) -> PASS fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#106641 https://bugs.freedesktop.org/show_bug.cgi?id=106641 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4801 -> Patchwork_10142 CI_DRM_4801: 47eb47da6081c676a6f9e6046db5a72fa7d22ef4 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4638: 20a7ead8bdf09774c7d58fcbe6a0980d08ed5365 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10142: 04db3d9a8eadc8b27b938fd83c386e5fea30153e @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10142/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Put all permanent stolen allocations together
Quoting Ville Syrjälä (2018-09-11 17:13:18)
> On Tue, Sep 11, 2018 at 04:14:39PM +0100, Chris Wilson wrote:
> > @@ -513,7 +515,8 @@ static int intel_fbc_alloc_cfb(struct intel_crtc *crtc)
> > goto err_fb;
> >
> > ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb,
> > - 4096, 4096);
> > + 4096, 4096,
> > + DRM_MM_INSERT_LOW);
>
> We seem to alloc/free the line length buffer alongside the cfb.
> So should this use best instead?
Ok, a quick glance suggested that this might have been alloc once.
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index d99e5fabe93c..5d18301ba079 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -7382,7 +7382,8 @@ static void valleyview_setup_pctx(struct
> > drm_i915_private *dev_priv)
> >* overlap with other ranges, such as the frame buffer, protected
> >* memory, or any other relevant ranges.
> >*/
> > - pctx = i915_gem_object_create_stolen(dev_priv, pctx_size);
> > + pctx = i915_gem_object_create_stolen(dev_priv,
> > + pctx_size, DRM_MM_INSERT_LOW);
>
> I guess there was no special requirement for the placement of this.
> AFAIK the BIOS always allocates it just below the wopcm, but I suppose
> it doesn't matter if we take a different approach.
HIGH or LOW doesn't make much difference. Could be HIGH just for fun ;)
> > if (!pctx) {
> > DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
> > goto out;
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index 472939f5c18f..e6a23a241cf3 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -1104,7 +1104,7 @@ intel_ring_create_vma(struct drm_i915_private
> > *dev_priv, int size)
> > struct drm_i915_gem_object *obj;
> > struct i915_vma *vma;
> >
> > - obj = i915_gem_object_create_stolen(dev_priv, size);
> > + obj = i915_gem_object_create_stolen(dev_priv, size,
> > DRM_MM_INSERT_BEST);
>
> Should these go low? We never reallocate them, right?
There's one per context per engine in execlists, i.e. they are
transient. I didn't feel it was worth differentiating
execlists/legacy as a few allocations once upon startup are more than
likely to be allocated sequentially from the bottom.
Hmm. That does get trickier then as it means that depending on order if
there are any transient allocations amongst the startup, we still end up
with holes and fragmentation layer. Needs a little more thought.
-Chris
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Re: [Intel-gfx] [PATCH 4/7] drm/i915/perf: lock powergating configuration to default when active
On 10/09/2018 14:44, Tvrtko Ursulin wrote: On 07/09/2018 10:55, Lionel Landwerlin wrote: On 07/09/2018 10:39, Tvrtko Ursulin wrote: On 07/09/2018 10:23, Lionel Landwerlin wrote: On 07/09/2018 09:26, Tvrtko Ursulin wrote: On 06/09/2018 11:36, Lionel Landwerlin wrote: On 06/09/2018 11:22, Chris Wilson wrote: Quoting Lionel Landwerlin (2018-09-06 11:18:01) On 06/09/2018 11:10, Chris Wilson wrote: Quoting Lionel Landwerlin (2018-09-06 10:57:47) On 05/09/2018 15:22, Tvrtko Ursulin wrote: From: Lionel Landwerlin If some of the contexts submitting workloads to the GPU have been configured to shutdown slices/subslices, we might loose the NOA configurations written in the NOA muxes. One possible solution to this problem is to reprogram the NOA muxes when we switch to a new context. We initially tried this in the workaround batchbuffer but some concerns where raised about the cost of reprogramming at every context switch. This solution is also not without consequences from the userspace point of view. Reprogramming of the muxes can only happen once the powergating configuration has changed (which happens after context switch). This means for a window of time during the recording, counters recorded by the OA unit might be invalid. This requires userspace dealing with OA reports to discard the invalid values. Minimizing the reprogramming could be implemented by tracking of the last programmed configuration somewhere in GGTT and use MI_PREDICATE to discard some of the programming commands, but the command streamer would still have to parse all the MI_LRI instructions in the workaround batchbuffer. Another solution, which this change implements, is to simply disregard the user requested configuration for the period of time when i915/perf is active. There is no known issue with this apart from a performance penality for some media workloads that benefit from running on a partially powergated GPU. We already prevent RC6 from affecting the programming so it doesn't sound completely unreasonable to hold on powergating for the same reason. v2: Leave RPCS programming in intel_lrc.c (Lionel) v3: Update for s/union intel_sseu/struct intel_sseu/ (Lionel) More to_intel_context() (Tvrtko) s/dev_priv/i915/ (Tvrtko) Tvrtko Ursulin: v4: * Rebase for make_rpcs changes. v5: * Apply OA restriction from make_rpcs directly. v6: * Rebase for context image setup changes. Signed-off-by: Lionel Landwerlin Signed-off-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_perf.c | 5 + drivers/gpu/drm/i915/intel_lrc.c | 30 -- drivers/gpu/drm/i915/intel_lrc.h | 3 +++ 3 files changed, 28 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index ccb20230df2c..dd65b72bddd4 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -1677,6 +1677,11 @@ static void gen8_update_reg_state_unlocked(struct i915_gem_context *ctx, CTX_REG(reg_state, state_offset, flex_regs[i], value); } + + CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, + gen8_make_rpcs(dev_priv, + _intel_context(ctx, + dev_priv->engine[RCS])->sseu)); I think there is one issue I missed on the previous iterations of this patch. This gen8_update_reg_state_unlocked() is called when the GPU is parked on the kernel context. It's supposed to update all contexts, but I think we might not be able to update the kernel context image while the GPU is using it. The kernel context is only ever taken in extremis (you are either parking or stalling userspace) so I don't care. The patch exposing the RPCS configuration to userspace will make use of the kernel context while OA/perf is enabled. Even if it reprograms the locked value that will break the power configuration stability on Gen11 (because the locked configuration will be different from the kernel context configuration). Sure, but as you point out that's only on changing configuration. What's missing in the patch is that we only bail early if the new sseu matches the ce->sseu, but that doesn't necessarily match whats in the context due to OA. (Or maybe I missed the conversion to rpcs value and checking.) -Chris Yep, because the gen8_make_rpcs() post processes the values store at the gem context level, we risk rerunning the kernel context to write the exiting value. Sorry this is all so messy :( Lets see if I managed to follow here. The current code indeed bails out at the set ctx param level if the requested state matches the ce->state. My thinking was that ce->state is the master state and whatever happens in "post processing" via gen8_make_rpcs should be hidden from it since the design is that the i915_perf.c will re-configure all contexts when the OA active status changes (to either direction). So I don't see a problem in those two
Re: [Intel-gfx] [PATCH] drm/i915: Nuke struct_mutex from context_setparam
Quoting Tvrtko Ursulin (2018-09-11 14:34:03)
>
> On 11/09/2018 14:22, Chris Wilson wrote:
> > Userspace should be free to race against itself and shoot itself in
> > the foot if it so desires to adjust a parameter at the same time as
> > submitting a batch to that context. As such, the struct_mutex in context
> > setparam is only being used to serialise userspace against itself and
> > not for any protection of internal structs and so is superfluous.
> >
> > v2: Separate user_flags from internal flags to reduce chance of
> > interference; and use locked bit ops for user updates.
> Okay, email criss-cross!
>
> > Signed-off-by: Chris Wilson
> > Cc: Tvrtko Ursulin
> > ---
> > drivers/gpu/drm/i915/i915_gem_context.c| 20 +
> > drivers/gpu/drm/i915/i915_gem_context.h| 33 +-
> > drivers/gpu/drm/i915/i915_gem_execbuffer.c | 2 +-
> > 3 files changed, 27 insertions(+), 28 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
> > b/drivers/gpu/drm/i915/i915_gem_context.c
> > index 747b8170a15a..f772593b99ab 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_context.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> > @@ -862,7 +862,7 @@ int i915_gem_context_getparam_ioctl(struct drm_device
> > *dev, void *data,
> > ret = -EINVAL;
> > break;
> > case I915_CONTEXT_PARAM_NO_ZEROMAP:
> > - args->value = ctx->flags & CONTEXT_NO_ZEROMAP;
> > + args->value = test_bit(UCONTEXT_NO_ZEROMAP, >user_flags);
> > break;
> > case I915_CONTEXT_PARAM_GTT_SIZE:
> > if (ctx->ppgtt)
> > @@ -896,27 +896,23 @@ int i915_gem_context_setparam_ioctl(struct drm_device
> > *dev, void *data,
> > struct drm_i915_file_private *file_priv = file->driver_priv;
> > struct drm_i915_gem_context_param *args = data;
> > struct i915_gem_context *ctx;
> > - int ret;
> > + int ret = 0;
> >
> > ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
> > if (!ctx)
> > return -ENOENT;
> >
> > - ret = i915_mutex_lock_interruptible(dev);
> > - if (ret)
> > - goto out;
> > -
> > switch (args->param) {
> > case I915_CONTEXT_PARAM_BAN_PERIOD:
> > ret = -EINVAL;
> > break;
> > case I915_CONTEXT_PARAM_NO_ZEROMAP:
> > - if (args->size) {
> > + if (args->size)
> > ret = -EINVAL;
> > - } else {
> > - ctx->flags &= ~CONTEXT_NO_ZEROMAP;
> > - ctx->flags |= args->value ? CONTEXT_NO_ZEROMAP : 0;
> > - }
> > + else if (args->value)
> > + set_bit(UCONTEXT_NO_ZEROMAP, >user_flags);
> > + else
> > + clear_bit(UCONTEXT_NO_ZEROMAP, >user_flags);
> > break;
> > case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
> > if (args->size)
> > @@ -960,9 +956,7 @@ int i915_gem_context_setparam_ioctl(struct drm_device
> > *dev, void *data,
> > ret = -EINVAL;
> > break;
> > }
> > - mutex_unlock(>struct_mutex);
> >
> > -out:
> > i915_gem_context_put(ctx);
> > return ret;
> > }
> > diff --git a/drivers/gpu/drm/i915/i915_gem_context.h
> > b/drivers/gpu/drm/i915/i915_gem_context.h
> > index e09673ca731d..08165f6a0a84 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_context.h
> > +++ b/drivers/gpu/drm/i915/i915_gem_context.h
> > @@ -116,16 +116,21 @@ struct i915_gem_context {
> >*/
> > struct rcu_head rcu;
> >
> > + /**
> > + * @user_flags: small set of booleans controlled by the user
> > + */
> > + unsigned long user_flags;
> > +#define UCONTEXT_NO_ZEROMAP 0
> > +#define UCONTEXT_NO_ERROR_CAPTURE1
> > +#define UCONTEXT_BANNABLE2
> > +
> > /**
> >* @flags: small set of booleans
> >*/
> > unsigned long flags;
> > -#define CONTEXT_NO_ZEROMAP BIT(0)
> > -#define CONTEXT_NO_ERROR_CAPTURE 1
> > -#define CONTEXT_CLOSED 2
> > -#define CONTEXT_BANNABLE 3
> > -#define CONTEXT_BANNED 4
> > -#define CONTEXT_FORCE_SINGLE_SUBMISSION 5
> > +#define CONTEXT_BANNED 0
> > +#define CONTEXT_CLOSED 1
> > +#define CONTEXT_FORCE_SINGLE_SUBMISSION 2
> >
> > /**
> >* @hw_id: - unique identifier for the context
> > @@ -209,37 +214,37 @@ static inline bool i915_gem_context_is_closed(const
> > struct i915_gem_context *ctx
> > static inline void i915_gem_context_set_closed(struct i915_gem_context
> > *ctx)
> > {
> > GEM_BUG_ON(i915_gem_context_is_closed(ctx));
> > - __set_bit(CONTEXT_CLOSED, >flags);
> > + set_bit(CONTEXT_CLOSED, >flags);
> > }
> >
> > static inline bool i915_gem_context_no_error_capture(const struct
> > i915_gem_context
Re: [Intel-gfx] [PATCH v5 00/13] ICELAKE DSI DRIVER
On Tue, 10 Jul 2018, Madhav Chauhan wrote: > From ICELAKE platform onwards, new MIPI DSI IP controller is integrated to > GPU/Display Engine and same could be extended for future Intel platforms as > well. > DSI IP controller supports MIPI DSI 1.3 and DPHY 1.2 specification. > > So, a new DSI driver has been added inside I915. > > Given below patches are the part of new DSI driver which implements BSPEC > sequence till transcoder configuration. Rest of the patches published to > GITHUB > and latest snapshot can be downloaded using: > #git clone https://github.com/madhavchauhan/Intel-DSI-Driver.git > > v2: Addressed review comments from Jani N for Patches 1-6 and rebase for some > other few patches. > v3: Renamed intel_dsi_new.c to gen11_dsi.c as per discussion with Jani, > Daniel, > Ville. Also addressed review comments for couple of patches. > v4: Rename gen11_dsi.c to icl_dsi.c (Ville). No functional changes. > v5: Rebase on drm-tip after initial 7 patches got merged. Hi Madhav, I think there's enough review here to warrant a revised set. I regret I haven't been able to review this earlier, and I'm now throwing the ball back in your court... with the added pressure that I'd really like to get this merged for v4.20. Which means the deadline for merging is about 1½ weeks away. Is there any chance? BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v5 12/13] drm/i915/icl: Define TRANS_DSI_FUNC_CONF register
On Tue, 10 Jul 2018, Madhav Chauhan wrote:
> This patch defines transcoder function configuration
> registers and its bitfields for both DSI ports.
> Used while programming/enabling DSI transcoder.
>
> Signed-off-by: Madhav Chauhan
> ---
> drivers/gpu/drm/i915/i915_reg.h | 47
> +
> 1 file changed, 47 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 62bc76e..71ce6ba 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10134,6 +10134,53 @@ enum skl_power_gate {
> #define TA_SURE_TIME(x) (x << 16)
> #define TA_SURE_TIME_MASK (0x1f << 16)
>
> +/* DSI transcoder configuration */
> +#define _DSI_TRANS_FUNC_CONF_0 0x6b030
> +#define _DSI_TRANS_FUNC_CONF_1 0x6b830
> +#define DSI_TRANS_FUNC_CONF(tc) _MMIO_DSI(tc, \
> + _DSI_TRANS_FUNC_CONF_0,\
> + _DSI_TRANS_FUNC_CONF_1)
> +#define OP_MODE(x) (x << 28)
> +#define OP_MODE_MASK(0x3 << 28)
> +#define CMD_MODE_NO_GATE0x0
> +#define CMD_MODE_TE_GATE0x1
> +#define VIDEO_MODE_SYNC_EVENT 0x2
> +#define VIDEO_MODE_SYNC_PULSE 0x3
The convention is to define macros for field values that you can OR
directly in place instead of requiring a shift. Please stick to the
conventions. Use _SHIFT and _MASK.
We can debate the relative merits of both approaches at some point, but
this is not the time.
BR,
Jani.
> +#define LINK_READY (1 << 20)
> +#define PIX_FMT(x) (x << 16)
> +#define PIX_FMT_MASK(0x3 << 16)
> +#define PIX_FMT_RGB565 0x0
> +#define PIX_FMT_RGB666_PACKED 0x1
> +#define PIX_FMT_RGB666_LOOSE0x2
> +#define PIX_FMT_RGB888 0x3
> +#define PIX_FMT_RGB101010 0x4
> +#define PIX_FMT_RGB121212 0x5
> +#define PIX_FMT_COMPRESSED 0x6
> +#define BGR_TRANSMISSION(1 << 15)
> +#define PIX_VIRT_CHAN(x)(x << 12)
> +#define PIX_VIRT_CHAN_MASK (0x3 << 12)
> +#define PIX_BUF_THRESHOLD(x)((x & 0x3) << 10)
> +#define PIX_BUF_THRESHOLD_MASK (0x3 << 10)
> +#define PIX_BUF_THRESHOLD_1_4 0x0
> +#define PIX_BUF_THRESHOLD_1_2 0x1
> +#define PIX_BUF_THRESHOLD_3_4 0x2
> +#define PIX_BUF_THRESHOLD_FULL 0x3
> +#define CONTINUOUS_CLK(x) (x << 8)
> +#define CONTINUOUS_CLK_MASK (0x3 << 8)
> +#define CLK_ENTER_LP_AFTER_DATA 0x0
> +#define CLK_HS_OR_LP0x2
> +#define CLK_HS_CONTINUOUS 0x3
> +#define LINK_CALIBRATION(x) (x << 4)
> +#define LINK_CALIBRATION_MASK (0x3 << 4)
> +#define CALIBRATION_DISABLED0x0
> +#define CALIBRATION_ENABLED_INITIAL_ONLY0x2
> +#define CALIBRATION_ENABLED_INITIAL_PERIODIC0x3
> +#define S3D_ORIENTATION(x) (x << 1)
> +#define S3D_ORIENTATION_MASK(0x1 << 1)
> +#define S3D_ORIENTATION_PORTRAIT0x0
> +#define S3D_ORIENTATION_LANDSCAPE 0x1
> +#define EOTP_DISABLED (1 << 0)
> +
> /* bits 31:0 */
> #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
> #define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
--
Jani Nikula, Intel Open Source Graphics Center
___
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Re: [Intel-gfx] [PATCH v5 09/13] drm/i915/icl: Program TA_TIMING_PARAM registers
On Fri, 20 Jul 2018, "Chauhan, Madhav" wrote:
>> -Original Message-
>> From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>> Sent: Thursday, July 19, 2018 9:51 PM
>> To: Chauhan, Madhav
>> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani ;
>> Zanoni, Paulo R ; Vivi, Rodrigo
>>
>> Subject: Re: [Intel-gfx] [PATCH v5 09/13] drm/i915/icl: Program
>> TA_TIMING_PARAM registers
>>
>> On Tue, Jul 10, 2018 at 03:10:10PM +0530, Madhav Chauhan wrote:
>> > This patch programs D-PHY timing parameters for the bus turn around
>> > flow(in escape clocks) only if dsi link frequency <=800 MHz using
>> > DPHY_TA_TIMING_PARAM and its identical register
>> DSI_TA_TIMING_PARAM
>> > (inside DSI Controller within the Display Core).
>> >
>> > Signed-off-by: Madhav Chauhan
>> > ---
>> > drivers/gpu/drm/i915/icl_dsi.c | 21 +
>> > drivers/gpu/drm/i915/intel_dsi.h | 1 +
>> > drivers/gpu/drm/i915/intel_dsi_vbt.c | 1 +
>> > 3 files changed, 23 insertions(+)
>> >
>> > diff --git a/drivers/gpu/drm/i915/icl_dsi.c
>> > b/drivers/gpu/drm/i915/icl_dsi.c index 832772d..8fd5284 100644
>> > --- a/drivers/gpu/drm/i915/icl_dsi.c
>> > +++ b/drivers/gpu/drm/i915/icl_dsi.c
>> > @@ -302,6 +302,27 @@ static void gen11_dsi_setup_dphy_timings(struct
>> intel_encoder *encoder)
>> >I915_WRITE(DSI_DATA_TIMING_PARAM(port),
>> > intel_dsi->dphy_data_lane_reg);
>> >}
>> > +
>> > + /*
>> > + * If DSI link operating at or below an 800 MHz,
>> > + * TA_SURE should be override and programmed to
>> > + * a value '0' inside TA_PARAM_REGISTERS otherwise
>> > + * leave all fields at HW default values.
>> > + */
>> > + if (intel_dsi->bitrate_khz <= KHz(800)) {
>>
>> The KHz(800) confuses me. My brain thinks this value is 800 kHz when it's
>> not. So I'd write it without the KHz() macro.
>
> Ok. Initially I wrote without using KHz macro, but got comment to use KHz
> macro :)
Did I? Oh well. Go with 80.
Please don't add additional state with intel_dsi->bitrate_khz when you
can calculate the bitrate at any time. Add a function to do it if you
like, and use it in both places.
BR,
Jani.
>
> Regards,
> Madhav
>
>>
>> > + for_each_dsi_port(port, intel_dsi->ports) {
>> > + tmp = I915_READ(DPHY_TA_TIMING_PARAM(port));
>> > + tmp &= ~TA_SURE_TIME_MASK;
>> > + tmp |= (TA_SURE_OVERRIDE | TA_SURE_TIME(0));
>> > + I915_WRITE(DPHY_TA_TIMING_PARAM(port), tmp);
>> > +
>> > + /* shadow register inside display core */
>> > + tmp = I915_READ(DSI_TA_TIMING_PARAM(port));
>> > + tmp &= ~TA_SURE_TIME_MASK;
>> > + tmp |= (TA_SURE_OVERRIDE | TA_SURE_TIME(0));
>> > + I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp);
>> > + }
>> > + }
>> > }
>> >
>> > static void gen11_dsi_enable_port_and_phy(struct intel_encoder
>> > *encoder) diff --git a/drivers/gpu/drm/i915/intel_dsi.h
>> > b/drivers/gpu/drm/i915/intel_dsi.h
>> > index 9fd8526..25e7396 100644
>> > --- a/drivers/gpu/drm/i915/intel_dsi.h
>> > +++ b/drivers/gpu/drm/i915/intel_dsi.h
>> > @@ -101,6 +101,7 @@ struct intel_dsi {
>> >
>> >u16 init_count;
>> >u32 pclk;
>> > + u32 bitrate_khz;
>> >u16 burst_mode_ratio;
>> >
>> >/* all delays in ms */
>> > diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c
>> > b/drivers/gpu/drm/i915/intel_dsi_vbt.c
>> > index 428290d..a9a98a4 100644
>> > --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
>> > +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
>> > @@ -589,6 +589,7 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi,
>> u16 panel_id)
>> >intel_dsi->pclk = pclk;
>> >
>> >bitrate = (pclk * bpp) / intel_dsi->lane_count;
>> > + intel_dsi->bitrate_khz = bitrate;
>> >
>> >switch (intel_dsi->escape_clk_div) {
>> >case 0:
>> > --
>> > 2.7.4
>> >
>> > ___
>> > Intel-gfx mailing list
>> > Intel-gfx@lists.freedesktop.org
>> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
>> --
>> Ville Syrjälä
>> Intel
--
Jani Nikula, Intel Open Source Graphics Center
___
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Re: [Intel-gfx] [PATCH v5 08/13] drm/i915/icl: Define TA_TIMING_PARAM registers
On Tue, 10 Jul 2018, Madhav Chauhan wrote:
> This patch defines DSI_TA_TIMING_PARAM and
> DPHY_TA_TIMING_PARAM registers used in
> dphy programming.
>
> Signed-off-by: Madhav Chauhan
> ---
> drivers/gpu/drm/i915/i915_reg.h | 14 ++
> 1 file changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0dbdd57..1d13ba9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10115,6 +10115,20 @@ enum skl_power_gate {
> #define HS_EXIT_OVERRIDE(1 << 7)
> #define HS_EXIT_TIME(x) (x << 0)
>
> +#define _DPHY_TA_TIMING_PARAM_0 0x162188
> +#define _DPHY_TA_TIMING_PARAM_1 0x6c188
> +#define DPHY_TA_TIMING_PARAM(port) _MMIO_PORT(port,\
> +_DPHY_TA_TIMING_PARAM_0,\
> +_DPHY_TA_TIMING_PARAM_1)
> +#define _DSI_TA_TIMING_PARAM_0 0x6b098
> +#define _DSI_TA_TIMING_PARAM_1 0x6b898
> +#define DSI_TA_TIMING_PARAM(port)_MMIO_PORT(port,\
> +_DSI_TA_TIMING_PARAM_0,\
> +_DSI_TA_TIMING_PARAM_1)
> +#define TA_SURE_OVERRIDE(1 << 31)
> +#define TA_SURE_TIME(x) (x << 16)
> +#define TA_SURE_TIME_MASK (0x1f << 16)
Please stick to _SHIFT. And in any case macro arguments need parens
around them.
Please add all the fields for the registers in one go.
BR,
Jani.
> +
> /* bits 31:0 */
> #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
> #define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
--
Jani Nikula, Intel Open Source Graphics Center
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Re: [Intel-gfx] [PATCH v5 04/13] drm/i915/icl: Define T_INIT_MASTER registers
On Tue, 10 Jul 2018, Madhav Chauhan wrote:
> This patch defines DSI_T_INIT_MASTER register for DSI ports
> 0/1 which will be used in dphy programming.
>
> Signed-off-by: Madhav Chauhan
Thanks, pushed to dinq.
BR,
Jani.
> ---
> drivers/gpu/drm/i915/i915_reg.h | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0424e45..6129372 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10069,6 +10069,12 @@ enum skl_power_gate {
> #define PREPARE_COUNT_SHIFT 0
> #define PREPARE_COUNT_MASK (0x3f << 0)
>
> +#define _ICL_DSI_T_INIT_MASTER_0 0x6b088
> +#define _ICL_DSI_T_INIT_MASTER_1 0x6b888
> +#define ICL_DSI_T_INIT_MASTER(port) _MMIO_PORT(port,\
> +_ICL_DSI_T_INIT_MASTER_0,\
> +_ICL_DSI_T_INIT_MASTER_1)
> +
> /* bits 31:0 */
> #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
> #define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
--
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Re: [Intel-gfx] [PATCH v5 05/13] drm/i915/icl: Program T_INIT_MASTER registers
On Tue, 10 Jul 2018, Madhav Chauhan wrote:
> This patch programs the time (in escape clocks) to drive
> the link in the initialization (i.e. LP-11) state.
>
> v2: Rebase
>
> Signed-off-by: Madhav Chauhan
> ---
> drivers/gpu/drm/i915/icl_dsi.c | 19 +++
> 1 file changed, 19 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index 41faa19..bc27e34 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -270,6 +270,22 @@ static void gen11_dsi_enable_ddi_buffer(struct
> intel_encoder *encoder)
> }
> }
>
> +static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
> + u32 tmp;
> + enum port port;
> +
> + /* Program T-INIT master registers */
> + for_each_dsi_port(port, intel_dsi->ports) {
> + tmp = I915_READ(ICL_DSI_T_INIT_MASTER(port));
> + tmp &= ~MASTER_INIT_TIMER_MASK;
> + tmp |= intel_dsi->init_count;
> + I915_WRITE(ICL_DSI_T_INIT_MASTER(port), tmp);
> + }
Mmh, the high word is MBZ so the RMW is unnecessary. But *shrug*.
Reviewed-by: Jani Nikula
> +}
> +
> static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
> {
> /* step 4a: power up all lanes of the DDI used by DSI */
> @@ -283,6 +299,9 @@ static void gen11_dsi_enable_port_and_phy(struct
> intel_encoder *encoder)
>
> /* step 4d: enable DDI buffer */
> gen11_dsi_enable_ddi_buffer(encoder);
> +
> + /* step 4e: setup D-PHY timings */
> + gen11_dsi_setup_dphy_timings(encoder);
> }
>
> static void __attribute__((unused))
--
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Re: [Intel-gfx] [PATCH v5 06/13] drm/i915/icl: Define data/clock lanes dphy timing registers
On Tue, 10 Jul 2018, Madhav Chauhan wrote:
> This patch defines DSI_CLK_TIMING_PARAM, DPHY_CLK_TIMING_PARAM,
> DSI_DATA_TIMING_PARAM, DPHY_DATA_TIMING_PARAM register used in
> dphy programming.
>
> Signed-off-by: Madhav Chauhan
> ---
> drivers/gpu/drm/i915/i915_reg.h | 40
> 1 file changed, 40 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6129372..0dbdd57 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10075,6 +10075,46 @@ enum skl_power_gate {
> _ICL_DSI_T_INIT_MASTER_0,\
> _ICL_DSI_T_INIT_MASTER_1)
>
> +#define _DPHY_CLK_TIMING_PARAM_0 0x162180
> +#define _DPHY_CLK_TIMING_PARAM_1 0x6c180
> +#define DPHY_CLK_TIMING_PARAM(port) _MMIO_PORT(port,\
> +_DPHY_CLK_TIMING_PARAM_0,\
> +_DPHY_CLK_TIMING_PARAM_1)
> +#define _DSI_CLK_TIMING_PARAM_0 0x6b080
> +#define _DSI_CLK_TIMING_PARAM_1 0x6b880
> +#define DSI_CLK_TIMING_PARAM(port) _MMIO_PORT(port,\
> +_DSI_CLK_TIMING_PARAM_0,\
> +_DSI_CLK_TIMING_PARAM_1)
> +#define CLK_PREP_OVERRIDE (1 << 31)
> +#define CLK_PREP_TIME(x)(x << 28)
> +#define CLK_ZERO_OVERRIDE (1 << 27)
> +#define CLK_ZERO_TIME(x)(x << 20)
> +#define CLK_PRE_OVERRIDE(1 << 19)
> +#define CLK_PRE_TIME(x) (x << 16)
> +#define CLK_POST_OVERRIDE (1 << 15)
> +#define CLK_POST_TIME(x)(x << 8)
> +#define CLK_TRAIL_OVERRIDE (1 << 7)
> +#define CLK_TRAIL_TIME(x) (x << 0)
I would prefer we stuck to the convention of defining _SHIFT and _MASK
macros for the bitfields. Even if the above style has started to creep
in without proper discussion. (I approve of the function-like macros for
things that aren't straight shifts; stuff with split bitfields or
calculations.)
No matter what, you need to wrap the macro arguments in parens!
Also, please don't do your own abbreviations or renames of the field
names when the bspec name is short/good enough.
> +
> +#define _DPHY_DATA_TIMING_PARAM_00x162184
> +#define _DPHY_DATA_TIMING_PARAM_10x6c184
> +#define DPHY_DATA_TIMING_PARAM(port) _MMIO_PORT(port,\
> +_DPHY_DATA_TIMING_PARAM_0,\
> +_DPHY_DATA_TIMING_PARAM_1)
> +#define _DSI_DATA_TIMING_PARAM_0 0x6B084
> +#define _DSI_DATA_TIMING_PARAM_1 0x6B884
> +#define DSI_DATA_TIMING_PARAM(port) _MMIO_PORT(port,\
> +_DSI_DATA_TIMING_PARAM_0,\
> +_DSI_DATA_TIMING_PARAM_1)
> +#define HS_PREP_OVERRIDE(1 << 31)
> +#define HS_PREP_TIME(x) (x << 24)
> +#define HS_ZERO_OVERRIDE(1 << 23)
> +#define HS_ZERO_TIME(x) (x << 16)
> +#define HS_TRAIL_OVERRIDE (1 << 15)
> +#define HS_TRAIL_TIME(x)(x << 8)
> +#define HS_EXIT_OVERRIDE(1 << 7)
> +#define HS_EXIT_TIME(x) (x << 0)
Same as above.
The register offsets and shifts etc. look ok.
BR,
Jani.
> +
> /* bits 31:0 */
> #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
> #define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
--
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Re: [Intel-gfx] [PATCH xf86-video-intel] SNA: fix PRIME output support since xserver 1.20
In meantime this patch has been picked up by the Arch Linux packages:
https://bugs.archlinux.org/task/58895
Is there any chance that this patch can be reviewed/applied? The diff is
quite small and should be easy to review.
On Wed, Aug 29, 2018 at 12:22:21PM +0200, Peter Wu wrote:
> Ping.
>
> This patch was independently verified working (see the linked bug
> report) and is essential for Xorg 1.20 using this driver.
>
> On Tue, Aug 14, 2018 at 02:16:07AM +0200, Peter Wu wrote:
> > Since xorg-server 1.20, an external monitor would remain blank when used
> > in a PRIME output slave setup. Only a cursor was visible. The cause is
> > "Make PixmapDirtyUpdateRec::src a DrawablePtr" in xserver, the "src"
> > pointer might point to the root window (created by the server) instead
> > of a pixmap (as created by xf86-video-intel). Use get_drawable_pixmap to
> > handle both cases.
> >
> > When built with -fsanitize=address, the following test will trigger a
> > heap-buffer-overflow error due to to_sna_from_pixmap receiving a window
> > instead of a pixmap.
> >
> > Test on a hybrid graphics laptop (Intel + modesetting/nouveau):
> >
> > xrandr --setprovideroutputsource modesetting Intel
> > xrandr --output DP-1-1 --mode 2560x1440 # should not crash
> > glxgears # should display gears on both screens
> >
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100086
> > Signed-off-by: Peter Wu
> > ---
> > Tested with xserver 1.20.1 with ASAN enabled. Survives multiple
> > resolution changes, works with a Plasma desktop session, it seems
> > stable. Something like this patch is required to make multi-monitor
> > setups usable in a hybrid graphics setting with Xorg 1.20.
> > ---
> > src/sna/sna_accel.c | 18 ++
> > 1 file changed, 18 insertions(+)
> >
> > diff --git a/src/sna/sna_accel.c b/src/sna/sna_accel.c
> > index 2f669bcf..80b116a3 100644
> > --- a/src/sna/sna_accel.c
> > +++ b/src/sna/sna_accel.c
> > @@ -17510,7 +17510,11 @@ static bool has_offload_slaves(struct sna *sna)
> > PixmapDirtyUpdatePtr dirty;
> >
> > xorg_list_for_each_entry(dirty, >pixmap_dirty_list, ent) {
> > +#ifdef HAS_DIRTYTRACKING_DRAWABLE_SRC
> > + assert(dirty->src == >front->drawable);
> > +#else
> > assert(dirty->src == sna->front);
> > +#endif
> > if (RegionNotEmpty(DamageRegion(dirty->damage)))
> > return true;
> > }
> > @@ -17671,7 +17675,11 @@ static void sna_accel_post_damage(struct sna *sna)
> > if (RegionNil(damage))
> > continue;
> >
> > +#ifdef HAS_DIRTYTRACKING_DRAWABLE_SRC
> > + src = get_drawable_pixmap(dirty->src);
> > +#else
> > src = dirty->src;
> > +#endif
> > dst = dirty->slave_dst->master_pixmap;
> >
> > region.extents.x1 = dirty->x;
> > @@ -17922,9 +17930,15 @@ migrate_dirty_tracking(PixmapPtr old_front,
> > PixmapPtr new_front)
> > PixmapDirtyUpdatePtr dirty, safe;
> >
> > xorg_list_for_each_entry_safe(dirty, safe, >pixmap_dirty_list,
> > ent) {
> > +#ifdef HAS_DIRTYTRACKING_DRAWABLE_SRC
> > + assert(dirty->src == _front->drawable);
> > + if (dirty->src != _front->drawable)
> > + continue;
> > +#else
> > assert(dirty->src == old_front);
> > if (dirty->src != old_front)
> > continue;
> > +#endif
> >
> > DamageUnregister(>src->drawable, dirty->damage);
> > DamageDestroy(dirty->damage);
> > @@ -17939,7 +17953,11 @@ migrate_dirty_tracking(PixmapPtr old_front,
> > PixmapPtr new_front)
> > }
> >
> > DamageRegister(_front->drawable, dirty->damage);
> > +#ifdef HAS_DIRTYTRACKING_DRAWABLE_SRC
> > + dirty->src = _front->drawable;
> > +#else
> > dirty->src = new_front;
> > +#endif
> > }
> > #endif
> > }
> > --
> > 2.18.0
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Re: [Intel-gfx] [PATCH v5 03/13] drm/i915/icl: Enable DDI Buffer
On Tue, 10 Jul 2018, Madhav Chauhan wrote:
> This patch enables DDI buffer by writing to DDI_BUF_CTL
> register and wait for DDI status to be *not idle* for a
> port.
>
> v2: Rebase
>
> Signed-off-by: Madhav Chauhan
> ---
> drivers/gpu/drm/i915/icl_dsi.c | 22 ++
> 1 file changed, 22 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index dc16c1f..41faa19 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -251,6 +251,25 @@ static void gen11_dsi_voltage_swing_program_seq(struct
> intel_encoder *encoder)
> }
> }
>
> +static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
> + u32 tmp;
> + enum port port;
> +
> + for_each_dsi_port(port, intel_dsi->ports) {
> + tmp = I915_READ(DDI_BUF_CTL(port));
> + tmp |= DDI_BUF_CTL_ENABLE;
> + I915_WRITE(DDI_BUF_CTL(port), tmp);
> +
> + if (wait_for_us(!(I915_READ(DDI_BUF_CTL(port)) &
> + DDI_BUF_IS_IDLE),
> + 500))
IMO a "== 0" check reads better in wait_for_us.
> + DRM_ERROR("DDI port:%c buffer idle\n", port_name(port));
> + }
> +}
> +
> static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
> {
> /* step 4a: power up all lanes of the DDI used by DSI */
> @@ -261,6 +280,9 @@ static void gen11_dsi_enable_port_and_phy(struct
> intel_encoder *encoder)
>
> /* step 4c: configure voltage swing and skew */
> gen11_dsi_voltage_swing_program_seq(encoder);
> +
> + /* step 4d: enable DDI buffer */
Alas, this is step 4e now, and you have a new 4d to take care of for
B0+.
Regardless,
Reviewed-by: Jani Nikula
> + gen11_dsi_enable_ddi_buffer(encoder);
> }
>
> static void __attribute__((unused))
--
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Re: [Intel-gfx] [PATCH v5 02/13] drm/i915/icl: DSI vswing programming sequence
On Tue, 10 Jul 2018, Madhav Chauhan wrote:
> This patch setup voltage swing before enabling
> combo PHY DDI (shared with DSI).
> Note that DSI voltage swing programming is for
> high speed data buffers. HW automatically handles
> the voltage swing for the low power data buffers.
>
> v2: Rebase
>
> Signed-off-by: Madhav Chauhan
> ---
> drivers/gpu/drm/i915/icl_dsi.c | 114
> +
> 1 file changed, 114 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index a571339..dc16c1f 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -27,6 +27,65 @@
>
> #include "intel_dsi.h"
>
> +static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
> + enum port port;
> + u32 tmp;
> + int lane;
> +
> + for_each_dsi_port(port, intel_dsi->ports) {
> +
> + /* Bspec: set scaling mode to 0x6 */
Today bspec says 2. Also, please don't duplicate the value in the
comment.
> + tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
> + tmp |= SCALING_MODE_SEL(6);
> + I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
Like Ville said, adding a blank line between each read-modify-write
group helps readability. Perhaps add /* DW5 */ etc. comments to group
the, eh, groups.
> + tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
> + tmp |= SCALING_MODE_SEL(6);
> + I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
> + tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
> + tmp |= TAP2_DISABLE | TAP3_DISABLE;
> + I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
> + tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
> + tmp |= TAP2_DISABLE | TAP3_DISABLE;
> + I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
Are you missing RTERM_SELECT?
Why do you do two read-modify-writes (RMW) on both GRP and AUX, instead
of doing all the changes at once?
The RMW doesn't actually clear the fields before changing them, just ORs
more stuff on top of them, and cursor program or coeff polarity might
contain garbage (at least in theory). The same below.
> +
> + /*
> + * swing and scaling values are taken from DSI
> + * table under vswing programming sequence for
> + * combo phy ddi in BSPEC.
> + * program swing values
> + */
Please reflow the comment.
> + tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
> + tmp |= SWING_SEL_UPPER(0x2);
> + tmp |= SWING_SEL_LOWER(0x2);
This would benefit from
+#define SWING_SEL_MASK (SWING_SEL_UPPER_MASK |
SWING_SEL_LOWER_MASK)
+#define SWING_SEL(x) (SWING_SEL_UPPER(x) |
SWING_SEL_LOWER(x))
in i915_reg.h. But I can look the other way and fix it myself later...
> + tmp |= RCOMP_SCALAR(0x98);
> + I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
> + tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
> + tmp |= SWING_SEL_UPPER(0x2);
> + tmp |= SWING_SEL_LOWER(0x2);
> + tmp |= RCOMP_SCALAR(0x98);
> + I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
> +
> + /* program scaling values */
> + tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
> + tmp |= POST_CURSOR_1(0x0);
> + tmp |= POST_CURSOR_2(0x0);
> + tmp |= CURSOR_COEFF(0x18);
0x3f?
Again, you need to zero the fields before ORin the new values into them.
> + I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
> +
> + for (lane = 0; lane <= 3; lane++) {
> + /* Bspec: must not use GRP register for write */
I'll take your word for it, although I've missed such a requirement.
> + tmp = I915_READ(ICL_PORT_TX_DW4_LN(port, lane));
> + tmp |= POST_CURSOR_1(0x0);
> + tmp |= POST_CURSOR_2(0x0);
> + tmp |= CURSOR_COEFF(0x18);
0x3f?
> + I915_WRITE(ICL_PORT_TX_DW4_LN(port, lane), tmp);
> + }
> + }
> +}
> +
> static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> @@ -140,6 +199,58 @@ static void gen11_dsi_config_phy_lanes_sequence(struct
> intel_encoder *encoder)
> }
> }
>
> +static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder
> *encoder)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
> + u32 tmp;
> + enum port port;
> +
The step numbering below has changed in bspec. Please update. Maybe drop
the numbering, and use just the headings.
Otherwise, the
Re: [Intel-gfx] [v5, 02/13] drm/i915/icl: DSI vswing programming sequence
On Mon, 10 Sep 2018, Madhav Chauhan wrote:
> On 9/6/2018 7:31 PM, Kulkarni, Vandita wrote:
>>
>>
>>
>> On 7/10/2018 3:10 PM, Madhav Chauhan wrote:
>>> This patch setup voltage swing before enabling
>>> combo PHY DDI (shared with DSI).
>>> Note that DSI voltage swing programming is for
>>> high speed data buffers. HW automatically handles
>>> the voltage swing for the low power data buffers.
>>>
>>> v2: Rebase
>>>
>>> Signed-off-by: Madhav Chauhan
>>> ---
>>> drivers/gpu/drm/i915/icl_dsi.c | 114
>>> +
>>> 1 file changed, 114 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
>>> index a571339..dc16c1f 100644
>>> --- a/drivers/gpu/drm/i915/icl_dsi.c
>>> +++ b/drivers/gpu/drm/i915/icl_dsi.c
>>> @@ -27,6 +27,65 @@
>>>
>>> #include "intel_dsi.h"
>>>
>>> +static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
>>> +{
>>> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>>> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
>>> + enum port port;
>>> + u32 tmp;
>>> + int lane;
>>> +
>>> + for_each_dsi_port(port, intel_dsi->ports) {
>>> +
>>> + /* Bspec: set scaling mode to 0x6 */
>>> + tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
>>> + tmp |= SCALING_MODE_SEL(6);
>>> + I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
>>> + tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
>>> + tmp |= SCALING_MODE_SEL(6);
>>> + I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
>>> + tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
>>> + tmp |= TAP2_DISABLE | TAP3_DISABLE;
>>> + I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
>>> + tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
>>> + tmp |= TAP2_DISABLE | TAP3_DISABLE;
>>> + I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
>>> +
>>> + /*
>>> +* swing and scaling values are taken from DSI
>>> +* table under vswing programming sequence for
>>> +* combo phy ddi in BSPEC.
>>> +* program swing values
>>> +*/
>>> + tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
>>> + tmp |= SWING_SEL_UPPER(0x2);
>>> + tmp |= SWING_SEL_LOWER(0x2);
>>> + tmp |= RCOMP_SCALAR(0x98);
>>> + I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
>>> + tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
>>> + tmp |= SWING_SEL_UPPER(0x2);
>>> + tmp |= SWING_SEL_LOWER(0x2);
>>> + tmp |= RCOMP_SCALAR(0x98);
>>> + I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
>>> +
>>> + /* program scaling values */
>>> + tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
>>> + tmp |= POST_CURSOR_1(0x0);
>>> + tmp |= POST_CURSOR_2(0x0);
>>> + tmp |= CURSOR_COEFF(0x18);
>>> + I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
>>> +
>>> + for (lane = 0; lane <= 3; lane++) {
>>> + /* Bspec: must not use GRP register for write */
>>> + tmp = I915_READ(ICL_PORT_TX_DW4_LN(port, lane));
>>> + tmp |= POST_CURSOR_1(0x0);
>>> + tmp |= POST_CURSOR_2(0x0);
>>> + tmp |= CURSOR_COEFF(0x18);
>>> + I915_WRITE(ICL_PORT_TX_DW4_LN(port, lane), tmp);
>>> + }
>>> + }
>>> +}
>>> +
>>> static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
>>> {
>>> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>>> @@ -140,6 +199,58 @@ static void gen11_dsi_config_phy_lanes_sequence(struct
>>> intel_encoder *encoder)
>>> }
>>> }
>>>
>>
>> I see from the bspec that except for the Loadgen Select and Latency
>> Optimization all other DDI buffer programming can be taken from the
>> DDI Buffer section.
>>
>> Can we use this function "icl_ddi_combo_vswing_program" function which
>> is already there
>> patch for reference:
>> https://patchwork.freedesktop.org/patch/213515/
For code already merged upstream, please use commit id or file
references.
>
> We can't directly use that implementation. Reasons:
> 1. For DSI we use AUX register as well to write which is not the case
> for DDI. We need to add multiple INTEL_OUTPUT_DSI
> checks .
> 2. DSI specific icl_combo_phy_ddi_buf_trans not added in intel_ddi.c
> which will be used while doing vswing programming
> 3. intel_ddi_dp_level doesn't support "level" calculation for DSI.
>
> Also in past we had similar discussion (with Jani N) to keep DSI
> specific entries/code in DSI encoder.
>
> Jani N whats the suggestion here??
Let's go with the slightly duplicated code, at least for now to get this
merged. This is tedious stuff to review, and combining that with merging
to DP/HDMI buf programming makes it unnecessarily hard. We can refactor
afterwards as needed.
BR,
Jani.
>
> Regards,
> Madhav
>
>>
>> Thanks,
Re: [Intel-gfx] [PATCH v5 01/13] drm/i915/icl: Configure lane sequencing of combo phy transmitter
On Fri, 27 Jul 2018, "Chauhan, Madhav" wrote:
>> -Original Message-
>> From: Chauhan, Madhav
>> Sent: Friday, July 20, 2018 12:06 AM
>> To: Ville Syrjälä
>> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani ;
>> Zanoni, Paulo R ; Vivi, Rodrigo
>>
>> Subject: RE: [Intel-gfx] [PATCH v5 01/13] drm/i915/icl: Configure lane
>> sequencing of combo phy transmitter
>>
>> > -Original Message-
>> > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>> > Sent: Thursday, July 19, 2018 9:42 PM
>> > To: Chauhan, Madhav
>> > Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani
>> > ; Zanoni, Paulo R ;
>> > Vivi, Rodrigo
>> > Subject: Re: [Intel-gfx] [PATCH v5 01/13] drm/i915/icl: Configure lane
>> > sequencing of combo phy transmitter
>> >
>> > On Tue, Jul 10, 2018 at 03:10:02PM +0530, Madhav Chauhan wrote:
>> > > This patch set the loadgen select and latency optimization for aux
>> > > and transmit lanes of combo phy transmitters. It will be used for
>> > > MIPI DSI HS operations.
>>
>> Thanks for reviewing DSI patches.
>>
>> > >
>> > > v2: Rebase
>> > >
>> > > Signed-off-by: Madhav Chauhan
>> > > ---
>> > > drivers/gpu/drm/i915/icl_dsi.c | 38
>> > > ++
>> > > 1 file changed, 38 insertions(+)
>> > >
>> > > diff --git a/drivers/gpu/drm/i915/icl_dsi.c
>> > > b/drivers/gpu/drm/i915/icl_dsi.c index 13830e4..a571339 100644
>> > > --- a/drivers/gpu/drm/i915/icl_dsi.c
>> > > +++ b/drivers/gpu/drm/i915/icl_dsi.c
>> > > @@ -105,10 +105,48 @@ static void gen11_dsi_power_up_lanes(struct
>> > intel_encoder *encoder)
>> > > }
>> > > }
>> > >
>> > > +static void gen11_dsi_config_phy_lanes_sequence(struct
>> > > +intel_encoder
>> > > +*encoder) {
>> > > +struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> > > +struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
>> > > +enum port port;
>> > > +u32 tmp;
>> > > +int lane;
>> >
>> > tmp/lane could be moved to into the loops.
>
> Was it due to intel_dsi->ports have no port assigned and
> loop for_each_dsi_port() will not proceed further??
> If that's the case, these encoder enable/disable function should be called
> Only when dsi_init is success and then, intel_dsi->ports have some valid port
> value.
>
> Please clarify.
Ville's comments are purely about style and readability.
>
> Regards,
> Madhav
>
>> >
>> > Same in other patches.
>>
>> Agree, make sense.
>
> Just to understand
>>
>> >
>> > > +
>> > > +/* Step 4b(i) set loadgen select for transmit and aux lanes */
>> > > +for_each_dsi_port(port, intel_dsi->ports) {
>> > > +tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
>> > > +tmp &= ~LOADGEN_SELECT;
>> > > +I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
>> > > +for (lane = 0; lane <= 3; lane++) {
>> > > +tmp = I915_READ(ICL_PORT_TX_DW4_LN(port,
>> > lane));
>> > > +tmp &= ~LOADGEN_SELECT;
>> > > +if (lane != 2)
>> > > +tmp |= LOADGEN_SELECT;
>> > > +I915_WRITE(ICL_PORT_TX_DW4_LN(port, lane),
>> > tmp);
>> > > +}
>> > > +}
>> > > +
>> > > +/* Step 4b(ii) set latency optimization for transmit and aux
>> > > lanes */
>> > > +for_each_dsi_port(port, intel_dsi->ports) {
>> > > +tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
>> > > +tmp &= ~FRC_LATENCY_OPTIM_MASK;
>> > > +tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
>> > > +I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
>> > > +tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
>> > > +tmp &= ~FRC_LATENCY_OPTIM_MASK;
>> > > +tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
>> > > +I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
The "read something, modify, write something else" pattern always gives
me the creeps. But I guess reading _GRP is not an option?
Anyway, for the actual content,
Reviewed-by: Jani Nikula
>> > > +}
>> >
>> > An empty line here and there would make this a bit more legible.
>> >
>> > Same in other patches.
>>
>> Ok. Thought this will be additional line, multiple Places in code use this
>> :)
>>
>> Regards,
>> Madhav
>>
>> >
>> > > +}
>> > > +
>> > > static void gen11_dsi_enable_port_and_phy(struct intel_encoder
>> > > *encoder) {
>> > > /* step 4a: power up all lanes of the DDI used by DSI */
>> > > gen11_dsi_power_up_lanes(encoder);
>> > > +
>> > > +/* step 4b: configure lane sequencing of the Combo-PHY
>> > > +transmitters
>> > */
>> > > +gen11_dsi_config_phy_lanes_sequence(encoder);
>> > > }
>> > >
>> > > static void __attribute__((unused))
>> > > --
>> > > 2.7.4
>> > >
>> > > ___
>> > > Intel-gfx mailing list
>> > > Intel-gfx@lists.freedesktop.org
>> > >
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix a potential integer overflow with framebuffers extending past 4 GiB
== Series Details == Series: drm/i915: Fix a potential integer overflow with framebuffers extending past 4 GiB URL : https://patchwork.freedesktop.org/series/49495/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4801 -> Patchwork_10144 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/49495/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10144 that come from known issues: === IGT changes === Issues hit igt@amdgpu/amd_basic@userptr: fi-kbl-8809g: PASS -> INCOMPLETE (fdo#107402) igt@drv_selftest@live_guc: fi-skl-guc: NOTRUN -> DMESG-WARN (fdo#107258) Possible fixes igt@kms_pipe_crc_basic@read-crc-pipe-a: fi-byt-clapper: FAIL (fdo#107362) -> PASS igt@kms_psr@primary_page_flip: fi-kbl-7560u: FAIL (fdo#107336) -> PASS igt@prime_vgem@basic-fence-flip: fi-ilk-650: FAIL (fdo#104008) -> PASS fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008 fdo#107258 https://bugs.freedesktop.org/show_bug.cgi?id=107258 fdo#107336 https://bugs.freedesktop.org/show_bug.cgi?id=107336 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107402 https://bugs.freedesktop.org/show_bug.cgi?id=107402 == Participating hosts (48 -> 43) == Additional (1): fi-skl-guc Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-gdg-551 == Build changes == * Linux: CI_DRM_4801 -> Patchwork_10144 CI_DRM_4801: 47eb47da6081c676a6f9e6046db5a72fa7d22ef4 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4638: 20a7ead8bdf09774c7d58fcbe6a0980d08ed5365 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10144: 2eb7a152755603e9a9228c43dce43415e03d4097 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 2eb7a1527556 drm/i915: Fix a potential integer overflow with framebuffers extending past 4 GiB == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10144/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Fix a potential integer overflow with framebuffers extending past 4 GiB
== Series Details == Series: drm/i915: Fix a potential integer overflow with framebuffers extending past 4 GiB URL : https://patchwork.freedesktop.org/series/49495/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: Fix a potential integer overflow with framebuffers extending past 4 GiB -O:drivers/gpu/drm/i915/intel_display.c:2636:28: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_display.c:2636:28: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_display.c:2636:28: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_display.c:2636:28: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Fix a potential integer overflow with framebuffers extending past 4 GiB
== Series Details == Series: drm/i915: Fix a potential integer overflow with framebuffers extending past 4 GiB URL : https://patchwork.freedesktop.org/series/49495/ State : warning == Summary == $ dim checkpatch origin/drm-tip 2eb7a1527556 drm/i915: Fix a potential integer overflow with framebuffers extending past 4 GiB -:50: CHECK:SPACING: No space is necessary after a cast #50: FILE: drivers/gpu/drm/i915/intel_display.c:2641: + (unsigned long long) mul_u32_u32(max_size, tile_size), total: 0 errors, 0 warnings, 1 checks, 13 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Put all permanent stolen allocations together
== Series Details == Series: drm/i915: Put all permanent stolen allocations together URL : https://patchwork.freedesktop.org/series/49485/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4801 -> Patchwork_10143 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/49485/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10143 that come from known issues: === IGT changes === Issues hit igt@amdgpu/amd_basic@userptr: fi-kbl-8809g: PASS -> INCOMPLETE (fdo#107402) igt@debugfs_test@read_all_entries: fi-snb-2520m: PASS -> INCOMPLETE (fdo#103713) igt@drv_module_reload@basic-reload: fi-blb-e6850: NOTRUN -> INCOMPLETE (fdo#107718) igt@drv_selftest@live_guc: fi-skl-guc: NOTRUN -> DMESG-WARN (fdo#107258) igt@kms_chamelium@dp-edid-read: fi-kbl-7500u: PASS -> FAIL (fdo#103841) igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: PASS -> FAIL (fdo#103167) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c: fi-bxt-dsi: PASS -> INCOMPLETE (fdo#103927) Possible fixes igt@gem_exec_suspend@basic-s4-devices: fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-a: fi-byt-clapper: FAIL (fdo#107362) -> PASS igt@kms_psr@primary_page_flip: fi-kbl-7560u: FAIL (fdo#107336) -> PASS igt@prime_vgem@basic-fence-flip: fi-ilk-650: FAIL (fdo#104008) -> PASS fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008 fdo#107258 https://bugs.freedesktop.org/show_bug.cgi?id=107258 fdo#107336 https://bugs.freedesktop.org/show_bug.cgi?id=107336 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107402 https://bugs.freedesktop.org/show_bug.cgi?id=107402 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 == Participating hosts (48 -> 44) == Additional (1): fi-skl-guc Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u == Build changes == * Linux: CI_DRM_4801 -> Patchwork_10143 CI_DRM_4801: 47eb47da6081c676a6f9e6046db5a72fa7d22ef4 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4638: 20a7ead8bdf09774c7d58fcbe6a0980d08ed5365 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10143: 5aca5b253d2522becd92748b5a05773c3ad18e78 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 5aca5b253d25 drm/i915: Put all permanent stolen allocations together == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10143/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Nuke struct_mutex from context_setparam (rev2)
== Series Details == Series: drm/i915: Nuke struct_mutex from context_setparam (rev2) URL : https://patchwork.freedesktop.org/series/49479/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4798_full -> Patchwork_10141_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_10141_full that come from known issues: === IGT changes === Issues hit igt@gem_ctx_isolation@bcs0-s3: shard-kbl: PASS -> INCOMPLETE (fdo#103665) igt@gem_exec_flush@basic-uc-pro-default: shard-snb: PASS -> INCOMPLETE (fdo#105411) fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4798 -> Patchwork_10141 CI_DRM_4798: b35a9812b9bbb5b562fd5b4faf7bf06fc80f59ee @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4637: 57e3d826dee154cb8664667db7660d854a707fc6 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10141: 05149d761c10cadf0e919099d15d31ef2f01f2ef @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10141/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Put all permanent stolen allocations together
== Series Details == Series: drm/i915: Put all permanent stolen allocations together URL : https://patchwork.freedesktop.org/series/49485/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: Put all permanent stolen allocations together -drivers/gpu/drm/i915/selftests/../i915_drv.h:3689:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3692:16: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Display gtt remapping prep stuff (rev2)
== Series Details == Series: drm/i915: Display gtt remapping prep stuff (rev2) URL : https://patchwork.freedesktop.org/series/49354/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4801 -> Patchwork_10142 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/49354/revisions/2/mbox/ == Known issues == Here are the changes found in Patchwork_10142 that come from known issues: === IGT changes === Issues hit igt@drv_module_reload@basic-reload: fi-blb-e6850: NOTRUN -> INCOMPLETE (fdo#107718) igt@drv_selftest@live_guc: fi-skl-guc: NOTRUN -> DMESG-WARN (fdo#107258) Possible fixes igt@gem_exec_suspend@basic-s4-devices: fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-a: fi-byt-clapper: FAIL (fdo#107362) -> PASS igt@kms_psr@primary_page_flip: fi-kbl-7560u: FAIL (fdo#107336) -> PASS igt@prime_vgem@basic-fence-flip: fi-ilk-650: FAIL (fdo#104008) -> PASS fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008 fdo#107258 https://bugs.freedesktop.org/show_bug.cgi?id=107258 fdo#107336 https://bugs.freedesktop.org/show_bug.cgi?id=107336 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 == Participating hosts (48 -> 43) == Additional (1): fi-skl-guc Missing(6): fi-ilk-m540 fi-bxt-dsi fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 == Build changes == * Linux: CI_DRM_4801 -> Patchwork_10142 CI_DRM_4801: 47eb47da6081c676a6f9e6046db5a72fa7d22ef4 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4638: 20a7ead8bdf09774c7d58fcbe6a0980d08ed5365 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10142: 04db3d9a8eadc8b27b938fd83c386e5fea30153e @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 04db3d9a8ead drm/i915: Extract intel_cursor_check_surface() 7851964f9e0b drm/i915: Move chv rotation checks to plane->check() 85aaae102c8f drm/i915: Move display w/a #1175 850272e82229 drm/i915: Move skl plane fb related checks into a better place 0e874d00f385 drm/i915: Extract per-platform plane->check() functions 55e8183ad477 drm/i915: Nuke plane->can_scale/min_downscale b00df41c99db drm/i915: s/int plane/int color_plane/ 30e60b5898ea drm/i915: Store ggtt_view in plane_state 13c19137b4ea drm/i915: Store the final plane stride in plane_state c1836eb396c4 drm/i915: Rename the plane_state->main/aux to plane_state->color_plane[] ee8258b9ede2 drm/i915: Use pipe A primary plane .max_stride() as the global stride limit fd0a612c9182 drm/i915: Add .max_stride() plane hook 561ec0959f52 drm/i915: s/tile_offset/aligned_offset/ etc. == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10142/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Fix a potential integer overflow with framebuffers extending past 4 GiB
From: Ville Syrjälä
If we have framebuffers that are >= 4GiB in size we will overflow
the fb size check in intel_fill_fb_info().
Currently that is only possible with NV12 and CCS as offsets[1]
may be anything between 0 and 0x. ofsets[0] is currently
required to be 0 so we can't hit the overflow with any single
plane format (thanks to max fb size of 8kx8k and max stride of
32 KiB).
In the future we may allow almost any framebuffer to exceed 4GiB
in size so we really should fix the overflow. Not that the overflow
is particularly dangerous. It's mostly just a sanity check against
insane userspace. The display engine can't write to memory anyway
so I suppose in the worst case we might anger the hw by attempting
scanout past the end of the ggtt, or we might scan out some data
that we're not supposed to see from other parts of the ggtt.
Note that triggering this overflow depends on the driver
aligning the fb height to the next tile boundary to push the
calculated size above 4GiB. With linear buffers the effective
tile height is one so that never happens, and the core already
has a check for 32bit overflow of offsets[]+pitches[]*height.
Testcase: igt/kms_big_fb/x-tiled-addfb-size-offset-overflow
Testcase: igt/kms_big_fb/y-tiled-addfb-size-offset-overflow
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 2b77d9350a3a..2b474d049074 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2636,9 +2636,10 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
max_size = max(max_size, offset + size);
}
- if (max_size * tile_size > obj->base.size) {
- DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu
bytes)\n",
- max_size * tile_size, obj->base.size);
+ if (mul_u32_u32(max_size, tile_size) > obj->base.size) {
+ DRM_DEBUG_KMS("fb too big for bo (need %llu bytes, have %zu
bytes)\n",
+ (unsigned long long) mul_u32_u32(max_size,
tile_size),
+ obj->base.size);
return -EINVAL;
}
--
2.16.4
___
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Display gtt remapping prep stuff (rev2)
== Series Details == Series: drm/i915: Display gtt remapping prep stuff (rev2) URL : https://patchwork.freedesktop.org/series/49354/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: s/tile_offset/aligned_offset/ etc. Okay! Commit: drm/i915: Add .max_stride() plane hook +drivers/gpu/drm/i915/intel_sprite.c:245:24: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_sprite.c:247:24: warning: expression using sizeof(void) Commit: drm/i915: Use pipe A primary plane .max_stride() as the global stride limit -O:drivers/gpu/drm/i915/intel_display.c:14446:24: warning: expression using sizeof(void) Commit: drm/i915: Rename the plane_state->main/aux to plane_state->color_plane[] Okay! Commit: drm/i915: Store the final plane stride in plane_state Okay! Commit: drm/i915: Store ggtt_view in plane_state Okay! Commit: drm/i915: s/int plane/int color_plane/ Okay! Commit: drm/i915: Nuke plane->can_scale/min_downscale Okay! Commit: drm/i915: Extract per-platform plane->check() functions Okay! Commit: drm/i915: Move skl plane fb related checks into a better place Okay! Commit: drm/i915: Move display w/a #1175 Okay! Commit: drm/i915: Move chv rotation checks to plane->check() Okay! Commit: drm/i915: Extract intel_cursor_check_surface() Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Display gtt remapping prep stuff (rev2)
== Series Details == Series: drm/i915: Display gtt remapping prep stuff (rev2) URL : https://patchwork.freedesktop.org/series/49354/ State : warning == Summary == $ dim checkpatch origin/drm-tip 561ec0959f52 drm/i915: s/tile_offset/aligned_offset/ etc. fd0a612c9182 drm/i915: Add .max_stride() plane hook -:35: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #35: FILE: drivers/gpu/drm/i915/intel_display.c:3225: + return 32*1024; ^ -:38: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #38: FILE: drivers/gpu/drm/i915/intel_display.c:3228: + return 16*1024; ^ -:40: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #40: FILE: drivers/gpu/drm/i915/intel_display.c:3230: + return 32*1024; ^ -:43: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #43: FILE: drivers/gpu/drm/i915/intel_display.c:3233: + return 8*1024; ^ -:45: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #45: FILE: drivers/gpu/drm/i915/intel_display.c:3235: + return 16*1024; ^ -:48: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #48: FILE: drivers/gpu/drm/i915/intel_display.c:3238: + return 4*1024; ^ -:50: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #50: FILE: drivers/gpu/drm/i915/intel_display.c:3240: + return 8*1024; ^ total: 0 errors, 0 warnings, 7 checks, 205 lines checked ee8258b9ede2 drm/i915: Use pipe A primary plane .max_stride() as the global stride limit c1836eb396c4 drm/i915: Rename the plane_state->main/aux to plane_state->color_plane[] 13c19137b4ea drm/i915: Store the final plane stride in plane_state 30e60b5898ea drm/i915: Store ggtt_view in plane_state b00df41c99db drm/i915: s/int plane/int color_plane/ -:12: WARNING:BAD_SIGN_OFF: 'Weak-reviewed-by:' is the preferred signature form #12: Weak-Reviewed-by: José Roberto de Souza total: 0 errors, 1 warnings, 0 checks, 309 lines checked 55e8183ad477 drm/i915: Nuke plane->can_scale/min_downscale 0e874d00f385 drm/i915: Extract per-platform plane->check() functions 850272e82229 drm/i915: Move skl plane fb related checks into a better place 85aaae102c8f drm/i915: Move display w/a #1175 7851964f9e0b drm/i915: Move chv rotation checks to plane->check() 04db3d9a8ead drm/i915: Extract intel_cursor_check_surface() ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Put all permanent stolen allocations together
On Tue, Sep 11, 2018 at 04:14:39PM +0100, Chris Wilson wrote:
> Whilst reviewing another new user of stolen memory, Ville made the
> observation that we should try to ensure that all permanent allocations
> within stolen memory are clustered together at either end of the stolen
> region, in order to reduce fragmentation. In the depths of
> i915_gem_stolen.c it is not always clear what manner of allocation we
> need, so expose the drm_mm search parameter and push the decision to our
> callers.
>
> Suggested-by: Ville Syrjälä
> Signed-off-by: Chris Wilson
> Cc: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_drv.h | 15 +--
> drivers/gpu/drm/i915/i915_gem_stolen.c | 19 ---
> drivers/gpu/drm/i915/intel_engine_cs.c | 3 ++-
> drivers/gpu/drm/i915/intel_fbc.c| 13 -
> drivers/gpu/drm/i915/intel_fbdev.c | 3 ++-
> drivers/gpu/drm/i915/intel_overlay.c| 3 ++-
> drivers/gpu/drm/i915/intel_pm.c | 3 ++-
> drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
> 8 files changed, 38 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 7ea442033a57..e68102141067 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3302,19 +3302,22 @@ static inline void i915_gem_chipset_flush(struct
> drm_i915_private *dev_priv)
>
> /* i915_gem_stolen.c */
> int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
> - struct drm_mm_node *node, u64 size,
> - unsigned alignment);
> + struct drm_mm_node *node,
> + u64 size, unsigned int alignment,
> + unsigned int search);
> int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
> - struct drm_mm_node *node, u64 size,
> - unsigned alignment, u64 start,
> - u64 end);
> + struct drm_mm_node *node,
> + u64 size, unsigned int alignment,
> + u64 start, u64 end,
> + unsigned int search);
> void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
>struct drm_mm_node *node);
> int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
> void i915_gem_cleanup_stolen(struct drm_device *dev);
> struct drm_i915_gem_object *
> i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
> - resource_size_t size);
> + resource_size_t size,
> + unsigned int search);
> struct drm_i915_gem_object *
> i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private
> *dev_priv,
> resource_size_t stolen_offset,
> diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c
> b/drivers/gpu/drm/i915/i915_gem_stolen.c
> index 53440bf87650..ed440e280dd0 100644
> --- a/drivers/gpu/drm/i915/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
> @@ -43,8 +43,10 @@
> */
>
> int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
> - struct drm_mm_node *node, u64 size,
> - unsigned alignment, u64 start, u64 end)
> + struct drm_mm_node *node,
> + u64 size, unsigned int alignment,
> + u64 start, u64 end,
> + unsigned int search)
> {
> int ret;
>
> @@ -58,7 +60,7 @@ int i915_gem_stolen_insert_node_in_range(struct
> drm_i915_private *dev_priv,
> mutex_lock(_priv->mm.stolen_lock);
> ret = drm_mm_insert_node_in_range(_priv->mm.stolen, node,
> size, alignment, 0,
> - start, end, DRM_MM_INSERT_BEST);
> + start, end, search);
> mutex_unlock(_priv->mm.stolen_lock);
>
> return ret;
> @@ -66,10 +68,12 @@ int i915_gem_stolen_insert_node_in_range(struct
> drm_i915_private *dev_priv,
>
> int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
> struct drm_mm_node *node, u64 size,
> - unsigned alignment)
> + unsigned int alignment,
> + unsigned int search)
> {
> return i915_gem_stolen_insert_node_in_range(dev_priv, node, size,
> - alignment, 0, U64_MAX);
> + alignment, 0, U64_MAX,
> +
Re: [Intel-gfx] [PATCH] drm/i915: Put all permanent stolen allocations together
On Tue, Sep 11, 2018 at 04:47:42PM +0100, Chris Wilson wrote: > Quoting Ville Syrjälä (2018-09-11 16:31:56) > > On Tue, Sep 11, 2018 at 04:14:39PM +0100, Chris Wilson wrote: > > > Whilst reviewing another new user of stolen memory, Ville made the > > > observation that we should try to ensure that all permanent allocations > > > within stolen memory are clustered together at either end of the stolen > > > region, in order to reduce fragmentation. In the depths of > > > i915_gem_stolen.c it is not always clear what manner of allocation we > > > need, so expose the drm_mm search parameter and push the decision to our > > > callers. > > > > > > Suggested-by: Ville Syrjälä > > > Signed-off-by: Chris Wilson > > > Cc: Ville Syrjälä > > > --- > > > drivers/gpu/drm/i915/i915_drv.h | 15 +-- > > > drivers/gpu/drm/i915/i915_gem_stolen.c | 19 --- > > > drivers/gpu/drm/i915/intel_engine_cs.c | 3 ++- > > > drivers/gpu/drm/i915/intel_fbc.c| 13 - > > > drivers/gpu/drm/i915/intel_fbdev.c | 3 ++- > > > drivers/gpu/drm/i915/intel_overlay.c| 3 ++- > > > drivers/gpu/drm/i915/intel_pm.c | 3 ++- > > > drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +- > > > 8 files changed, 38 insertions(+), 23 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_overlay.c > > > b/drivers/gpu/drm/i915/intel_overlay.c > > > index 72eb7e48e8bc..b134b9cabf93 100644 > > > --- a/drivers/gpu/drm/i915/intel_overlay.c > > > +++ b/drivers/gpu/drm/i915/intel_overlay.c > > > @@ -1306,7 +1306,8 @@ static int get_registers(struct intel_overlay > > > *overlay, bool use_phys) > > > struct i915_vma *vma; > > > int err; > > > > > > - obj = i915_gem_object_create_stolen(overlay->i915, PAGE_SIZE); > > > + obj = i915_gem_object_create_stolen(overlay->i915, > > > + PAGE_SIZE, DRM_MM_INSERT_LOW); > > > > Won't these early INSERT_LOWs create problems for the BIOS fb takeover? > > The BIOS reservation is the very first thing we do, right? The sequence > is meant to be init the drm_mm, probe all the HW state (BIOS fb, vlv > pctx, anything else?) and make the reservations, then finish > initialising the unreserved portions before allowing ourselves to > allocate from it. Hmm. Yeah, I think you're right. Somehow I got it into my head that at least the overlay setup would be done before the state readout. In theory that would be the correct order if we had to eg. turn off the overlay while sanitizing the display state in case the BIOS left the overlay on for some reason. But that is likely to never happen so I guess we're fine with the current order. -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Put all permanent stolen allocations together
Quoting Ville Syrjälä (2018-09-11 16:31:56) > On Tue, Sep 11, 2018 at 04:14:39PM +0100, Chris Wilson wrote: > > Whilst reviewing another new user of stolen memory, Ville made the > > observation that we should try to ensure that all permanent allocations > > within stolen memory are clustered together at either end of the stolen > > region, in order to reduce fragmentation. In the depths of > > i915_gem_stolen.c it is not always clear what manner of allocation we > > need, so expose the drm_mm search parameter and push the decision to our > > callers. > > > > Suggested-by: Ville Syrjälä > > Signed-off-by: Chris Wilson > > Cc: Ville Syrjälä > > --- > > drivers/gpu/drm/i915/i915_drv.h | 15 +-- > > drivers/gpu/drm/i915/i915_gem_stolen.c | 19 --- > > drivers/gpu/drm/i915/intel_engine_cs.c | 3 ++- > > drivers/gpu/drm/i915/intel_fbc.c| 13 - > > drivers/gpu/drm/i915/intel_fbdev.c | 3 ++- > > drivers/gpu/drm/i915/intel_overlay.c| 3 ++- > > drivers/gpu/drm/i915/intel_pm.c | 3 ++- > > drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +- > > 8 files changed, 38 insertions(+), 23 deletions(-) > > > > > diff --git a/drivers/gpu/drm/i915/intel_overlay.c > > b/drivers/gpu/drm/i915/intel_overlay.c > > index 72eb7e48e8bc..b134b9cabf93 100644 > > --- a/drivers/gpu/drm/i915/intel_overlay.c > > +++ b/drivers/gpu/drm/i915/intel_overlay.c > > @@ -1306,7 +1306,8 @@ static int get_registers(struct intel_overlay > > *overlay, bool use_phys) > > struct i915_vma *vma; > > int err; > > > > - obj = i915_gem_object_create_stolen(overlay->i915, PAGE_SIZE); > > + obj = i915_gem_object_create_stolen(overlay->i915, > > + PAGE_SIZE, DRM_MM_INSERT_LOW); > > Won't these early INSERT_LOWs create problems for the BIOS fb takeover? The BIOS reservation is the very first thing we do, right? The sequence is meant to be init the drm_mm, probe all the HW state (BIOS fb, vlv pctx, anything else?) and make the reservations, then finish initialising the unreserved portions before allowing ourselves to allocate from it. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Put all permanent stolen allocations together
On Tue, Sep 11, 2018 at 04:14:39PM +0100, Chris Wilson wrote:
> Whilst reviewing another new user of stolen memory, Ville made the
> observation that we should try to ensure that all permanent allocations
> within stolen memory are clustered together at either end of the stolen
> region, in order to reduce fragmentation. In the depths of
> i915_gem_stolen.c it is not always clear what manner of allocation we
> need, so expose the drm_mm search parameter and push the decision to our
> callers.
>
> Suggested-by: Ville Syrjälä
> Signed-off-by: Chris Wilson
> Cc: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_drv.h | 15 +--
> drivers/gpu/drm/i915/i915_gem_stolen.c | 19 ---
> drivers/gpu/drm/i915/intel_engine_cs.c | 3 ++-
> drivers/gpu/drm/i915/intel_fbc.c| 13 -
> drivers/gpu/drm/i915/intel_fbdev.c | 3 ++-
> drivers/gpu/drm/i915/intel_overlay.c| 3 ++-
> drivers/gpu/drm/i915/intel_pm.c | 3 ++-
> drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
> 8 files changed, 38 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_overlay.c
> b/drivers/gpu/drm/i915/intel_overlay.c
> index 72eb7e48e8bc..b134b9cabf93 100644
> --- a/drivers/gpu/drm/i915/intel_overlay.c
> +++ b/drivers/gpu/drm/i915/intel_overlay.c
> @@ -1306,7 +1306,8 @@ static int get_registers(struct intel_overlay *overlay,
> bool use_phys)
> struct i915_vma *vma;
> int err;
>
> - obj = i915_gem_object_create_stolen(overlay->i915, PAGE_SIZE);
> + obj = i915_gem_object_create_stolen(overlay->i915,
> + PAGE_SIZE, DRM_MM_INSERT_LOW);
Won't these early INSERT_LOWs create problems for the BIOS fb takeover?
> if (obj == NULL)
> obj = i915_gem_object_create_internal(overlay->i915, PAGE_SIZE);
> if (IS_ERR(obj))
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d99e5fabe93c..5d18301ba079 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7382,7 +7382,8 @@ static void valleyview_setup_pctx(struct
> drm_i915_private *dev_priv)
>* overlap with other ranges, such as the frame buffer, protected
>* memory, or any other relevant ranges.
>*/
> - pctx = i915_gem_object_create_stolen(dev_priv, pctx_size);
> + pctx = i915_gem_object_create_stolen(dev_priv,
> + pctx_size, DRM_MM_INSERT_LOW);
> if (!pctx) {
> DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
> goto out;
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 472939f5c18f..e6a23a241cf3 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1104,7 +1104,7 @@ intel_ring_create_vma(struct drm_i915_private
> *dev_priv, int size)
> struct drm_i915_gem_object *obj;
> struct i915_vma *vma;
>
> - obj = i915_gem_object_create_stolen(dev_priv, size);
> + obj = i915_gem_object_create_stolen(dev_priv, size, DRM_MM_INSERT_BEST);
> if (!obj)
> obj = i915_gem_object_create_internal(dev_priv, size);
> if (IS_ERR(obj))
> --
> 2.19.0.rc2
--
Ville Syrjälä
Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Put all permanent stolen allocations together
Whilst reviewing another new user of stolen memory, Ville made the
observation that we should try to ensure that all permanent allocations
within stolen memory are clustered together at either end of the stolen
region, in order to reduce fragmentation. In the depths of
i915_gem_stolen.c it is not always clear what manner of allocation we
need, so expose the drm_mm search parameter and push the decision to our
callers.
Suggested-by: Ville Syrjälä
Signed-off-by: Chris Wilson
Cc: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.h | 15 +--
drivers/gpu/drm/i915/i915_gem_stolen.c | 19 ---
drivers/gpu/drm/i915/intel_engine_cs.c | 3 ++-
drivers/gpu/drm/i915/intel_fbc.c| 13 -
drivers/gpu/drm/i915/intel_fbdev.c | 3 ++-
drivers/gpu/drm/i915/intel_overlay.c| 3 ++-
drivers/gpu/drm/i915/intel_pm.c | 3 ++-
drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
8 files changed, 38 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7ea442033a57..e68102141067 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3302,19 +3302,22 @@ static inline void i915_gem_chipset_flush(struct
drm_i915_private *dev_priv)
/* i915_gem_stolen.c */
int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
- struct drm_mm_node *node, u64 size,
- unsigned alignment);
+ struct drm_mm_node *node,
+ u64 size, unsigned int alignment,
+ unsigned int search);
int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
-struct drm_mm_node *node, u64 size,
-unsigned alignment, u64 start,
-u64 end);
+struct drm_mm_node *node,
+u64 size, unsigned int alignment,
+u64 start, u64 end,
+unsigned int search);
void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
struct drm_mm_node *node);
int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
void i915_gem_cleanup_stolen(struct drm_device *dev);
struct drm_i915_gem_object *
i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
- resource_size_t size);
+ resource_size_t size,
+ unsigned int search);
struct drm_i915_gem_object *
i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private
*dev_priv,
resource_size_t stolen_offset,
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c
b/drivers/gpu/drm/i915/i915_gem_stolen.c
index 53440bf87650..ed440e280dd0 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -43,8 +43,10 @@
*/
int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
-struct drm_mm_node *node, u64 size,
-unsigned alignment, u64 start, u64 end)
+struct drm_mm_node *node,
+u64 size, unsigned int alignment,
+u64 start, u64 end,
+unsigned int search)
{
int ret;
@@ -58,7 +60,7 @@ int i915_gem_stolen_insert_node_in_range(struct
drm_i915_private *dev_priv,
mutex_lock(_priv->mm.stolen_lock);
ret = drm_mm_insert_node_in_range(_priv->mm.stolen, node,
size, alignment, 0,
- start, end, DRM_MM_INSERT_BEST);
+ start, end, search);
mutex_unlock(_priv->mm.stolen_lock);
return ret;
@@ -66,10 +68,12 @@ int i915_gem_stolen_insert_node_in_range(struct
drm_i915_private *dev_priv,
int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
struct drm_mm_node *node, u64 size,
- unsigned alignment)
+ unsigned int alignment,
+ unsigned int search)
{
return i915_gem_stolen_insert_node_in_range(dev_priv, node, size,
- alignment, 0, U64_MAX);
+ alignment, 0, U64_MAX,
+ search);
}
void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
@@ -591,7 +595,8 @@ _i915_gem_object_create_stolen(struct drm_i915_private
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Nuke struct_mutex from context_setparam (rev2)
== Series Details == Series: drm/i915: Nuke struct_mutex from context_setparam (rev2) URL : https://patchwork.freedesktop.org/series/49479/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4798 -> Patchwork_10141 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/49479/revisions/2/mbox/ == Known issues == Here are the changes found in Patchwork_10141 that come from known issues: === IGT changes === Issues hit igt@debugfs_test@read_all_entries: fi-snb-2520m: PASS -> INCOMPLETE (fdo#103713) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c: fi-bxt-dsi: PASS -> INCOMPLETE (fdo#103927) Possible fixes igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: FAIL (fdo#103167) -> PASS igt@kms_pipe_crc_basic@hang-read-crc-pipe-a: fi-byt-clapper: FAIL (fdo#103191, fdo#107362) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS igt@prime_vgem@basic-fence-flip: fi-ilk-650: FAIL (fdo#104008) -> PASS fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 == Participating hosts (48 -> 44) == Additional (1): fi-hsw-4770r Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u == Build changes == * Linux: CI_DRM_4798 -> Patchwork_10141 CI_DRM_4798: b35a9812b9bbb5b562fd5b4faf7bf06fc80f59ee @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4637: 57e3d826dee154cb8664667db7660d854a707fc6 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10141: 05149d761c10cadf0e919099d15d31ef2f01f2ef @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 05149d761c10 drm/i915: Nuke struct_mutex from context_setparam == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10141/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 05/13] drm/i915: Store the final plane stride in plane_state
From: Ville Syrjälä
Let's store the final plane stride in the plane state. This avoids
having to pick between the normal vs. rotated stride during hardware
programming. And once we get GTT remapping the plane stride will
no longer match the fb stride so we'll need a place to store it
anyway.
v2: Keep checking fb->pitches[0] for cursor as later on we won't
populate plane_state->color_plane[0].stride for invisible planes
and we have been checking the cursor fb stride even for invisible
planes
v3: s/betwen/between in commit msg (José)
v4: Check color_plane[0].stride instead of fb->pitches[0] in
the skl_check_main_surface() X-tiling kludge
Reviewed-by: José Roberto de Souza
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 47
drivers/gpu/drm/i915/intel_drv.h | 10 ++--
drivers/gpu/drm/i915/intel_sprite.c | 12 -
3 files changed, 46 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index c0dd62a617e3..ee6090c4b7f0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2203,7 +2203,7 @@ u32 intel_fb_xy_to_linear(int x, int y,
{
const struct drm_framebuffer *fb = state->base.fb;
unsigned int cpp = fb->format->cpp[plane];
- unsigned int pitch = fb->pitches[plane];
+ unsigned int pitch = state->color_plane[plane].stride;
return y * pitch + x * cpp;
}
@@ -2260,11 +2260,11 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
static u32 intel_adjust_aligned_offset(int *x, int *y,
const struct drm_framebuffer *fb, int
plane,
unsigned int rotation,
+ unsigned int pitch,
u32 old_offset, u32 new_offset)
{
struct drm_i915_private *dev_priv = to_i915(fb->dev);
unsigned int cpp = fb->format->cpp[plane];
- unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
WARN_ON(new_offset > old_offset);
@@ -2306,6 +2306,7 @@ static u32 intel_plane_adjust_aligned_offset(int *x, int
*y,
{
return intel_adjust_aligned_offset(x, y, state->base.fb, plane,
state->base.rotation,
+ state->color_plane[plane].stride,
old_offset, new_offset);
}
@@ -2382,7 +2383,7 @@ static u32 intel_plane_compute_aligned_offset(int *x, int
*y,
struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
const struct drm_framebuffer *fb = state->base.fb;
unsigned int rotation = state->base.rotation;
- int pitch = intel_fb_pitch(fb, plane, rotation);
+ int pitch = state->color_plane[plane].stride;
u32 alignment;
if (intel_plane->id == PLANE_CURSOR)
@@ -2409,6 +2410,7 @@ static int intel_fb_offset_to_xy(int *x, int *y,
intel_adjust_aligned_offset(x, y,
fb, plane, DRM_MODE_ROTATE_0,
+ fb->pitches[0],
fb->offsets[plane], 0);
return 0;
@@ -2855,6 +2857,9 @@ intel_find_initial_plane_obj(struct intel_crtc
*intel_crtc,
return;
valid_fb:
+ intel_state->color_plane[0].stride =
+ intel_fb_pitch(fb, 0, intel_state->base.rotation);
+
mutex_lock(>struct_mutex);
intel_state->vma =
intel_pin_and_fence_fb_obj(fb,
@@ -3048,7 +3053,7 @@ static int skl_check_main_surface(const struct
intel_crtc_state *crtc_state,
if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
int cpp = fb->format->cpp[0];
- while ((x + w) * cpp > fb->pitches[0]) {
+ while ((x + w) * cpp > plane_state->color_plane[0].stride) {
if (offset == 0) {
DRM_DEBUG_KMS("Unable to find suitable display
surface offset due to X-tiling\n");
return -EINVAL;
@@ -3171,6 +3176,9 @@ int skl_check_plane_surface(const struct intel_crtc_state
*crtc_state,
unsigned int rotation = plane_state->base.rotation;
int ret;
+ plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
+ plane_state->color_plane[1].stride = intel_fb_pitch(fb, 1, rotation);
+
if (rotation & DRM_MODE_REFLECT_X &&
fb->modifier == DRM_FORMAT_MOD_LINEAR) {
DRM_DEBUG_KMS("horizontal flip is not supported with linear
surface formats\n");
@@ -3307,10 +3315,14 @@ int i9xx_check_plane_surface(struct intel_plane_state
*plane_state)
{
struct drm_i915_private *dev_priv =
to_i915(plane_state->base.plane->dev);
+ const struct drm_framebuffer *fb = plane_state->base.fb;
+ unsigned int rotation =
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [01/26] drm/i915/ringbuffer: Reload PDs harder on byt/bcs
== Series Details == Series: series starting with [01/26] drm/i915/ringbuffer: Reload PDs harder on byt/bcs URL : https://patchwork.freedesktop.org/series/49476/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4797_full -> Patchwork_10140_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_10140_full that come from known issues: === IGT changes === Issues hit igt@gem_eio@suspend: shard-kbl: PASS -> INCOMPLETE (fdo#103665) +1 shard-apl: PASS -> INCOMPLETE (fdo#103927) +1 shard-glk: PASS -> INCOMPLETE (fdo#103359, k.org#198133) +1 igt@kms_flip@flip-vs-expired-vblank: shard-glk: PASS -> FAIL (fdo#105363, fdo#102887) Possible fixes igt@drv_suspend@shrink: shard-apl: FAIL (fdo#106886) -> PASS igt@gem_exec_big: shard-hsw: INCOMPLETE (fdo#103540) -> PASS fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4797 -> Patchwork_10140 CI_DRM_4797: 3209f38d7ee600583963aa7c049c5dfde658d453 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4637: 57e3d826dee154cb8664667db7660d854a707fc6 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10140: a8d5adacb4565e184ad84a38152cdb8f2470adc5 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10140/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v10 3/8] drm/i915: Add CRTC output format YCBCR 4:4:4
On Tue, Aug 14, 2018 at 03:23:21PM +0530, Shashank Sharma wrote:
> This patch adds support for YCBCR 4:4:4 CRTC output format.
> To do this, this patch extends the existing YCBCR 4:2:0
> framework by:
> - Adding new parameter in for YCBCR 4:4:4 enum crtc_iutput_format.
> - Adding case for YCBCR 4:4:4 in while setting AVI infoframes.
> - Adding necessary checks in modeset sequence.
>
> V3: Added this patch in the series
> V4: Added r-b from Maarten (for v3)
> Addressed review comment from Ville:
> Do not use (config->output_format > CRTC_OUTPUT_RGB)
> V5: Rebase
> V6: Rebase and small change, to accommodate changes in patch 2
> V7: Fixed checkpatch alignment warnings
> V8: Rebase
> V9: Rebase
> V10: Rebase
>
> Cc: Ville Syrjälä
> Cc: Maarten Lankhorst
> Signed-off-by: Shashank Sharma
> ---
> drivers/gpu/drm/i915/intel_color.c | 3 ++-
> drivers/gpu/drm/i915/intel_display.c | 13 +
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> drivers/gpu/drm/i915/intel_hdmi.c| 2 ++
> 4 files changed, 14 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_color.c
> b/drivers/gpu/drm/i915/intel_color.c
> index bf9d8f6..5127da2 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -149,7 +149,8 @@ static void ilk_load_csc_matrix(struct drm_crtc_state
> *crtc_state)
> if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
> limited_color_range = intel_crtc_state->limited_color_range;
>
> - if (intel_crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
> + if (intel_crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
> + intel_crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
> ilk_load_ycbcr_conversion_matrix(intel_crtc);
> return;
> } else if (crtc_state->ctm) {
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index e2a1e4f..3384129 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6621,8 +6621,9 @@ static int intel_crtc_compute_config(struct intel_crtc
> *crtc,
> return -EINVAL;
> }
>
> - if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
> - pipe_config->base.ctm) {
> + if ((pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
> + pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) &&
> + pipe_config->base.ctm) {
> /*
>* There is only one pipe CSC unit per pipe, and we need that
>* for output conversion from RGB->YCBCR. So if CTM is already
> @@ -7842,6 +7843,8 @@ static void intel_get_crtc_ycbcr_config(struct
> intel_crtc *crtc,
> output = INTEL_OUTPUT_FORMAT_INVALID;
> else
> output = INTEL_OUTPUT_FORMAT_YCBCR420;
> + } else {
> + output = INTEL_OUTPUT_FORMAT_YCBCR444;
> }
> }
> }
> @@ -8484,11 +8487,13 @@ static void haswell_set_pipemisc(struct drm_crtc
> *crtc)
> if (intel_crtc->config->dither)
> val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
>
> - if (config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
> + if (config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
> + config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
> val |= PIPEMISC_OUTPUT_COLORSPACE_YUV;
> +
> + if (config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
> val |= PIPEMISC_YUV420_ENABLE |
> PIPEMISC_YUV420_MODE_FULL_BLEND;
> - }
>
> I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
> }
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index cc7a46e..74ea4ac 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -712,6 +712,7 @@ enum intel_output_format {
> INTEL_OUTPUT_FORMAT_INVALID,
> INTEL_OUTPUT_FORMAT_RGB,
> INTEL_OUTPUT_FORMAT_YCBCR420,
> + INTEL_OUTPUT_FORMAT_YCBCR444,
> };
Missing output_format_str[INTEL_OUTPUT_FORMAT_YCBCR444].
With that fixed
Reviewed-by: Ville Syrjälä
>
> struct intel_crtc_state {
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
> b/drivers/gpu/drm/i915/intel_hdmi.c
> index f1259a9..893d53d 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -488,6 +488,8 @@ static void intel_hdmi_set_avi_infoframe(struct
> drm_encoder *encoder,
>
> if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
> frame.avi.colorspace = HDMI_COLORSPACE_YUV420;
> + else if (crtc_state->output_format ==
Re: [Intel-gfx] [PATCH v10 2/8] drm/i915: Add CRTC output format YCBCR 4:2:0
On Tue, Aug 14, 2018 at 03:23:20PM +0530, Shashank Sharma wrote:
> Currently, we are using a bool in CRTC state (state->ycbcr420),
> to indicate modeset, that the output format is YCBCR 4:2:0. Now in
> order to support other YCBCR formats, we will need more such flags.
>
> This patch adds a new enum parameter for YCBCR 4:2:0 outputs, in the
> CRTC output formats and then plugs it during the modeset.
>
> V3: Added this patch in the series, to address review comments from
> second patchset.
> V4: Added r-b from Maarten (on v3)
> Addressed review comments from Ville:
> - Change the enum name to intel_output_format.
> - Start the enum value (INVALID) from 0 instaed of 1.
> - Set the crtc's output_format to RGB in encoder's compute_config.
> V5: Broke previous patch 1 into two parts,
> - first patch to add CRTC output format in general
> - second patch (this one) to add YCBCR 4:2:0 output
> format specifically.
> - Use ARRAY_SIZE(format_str) for output format validity check (Ville)
> V6: Added a separate function to calculate crtc_state->output_format, and
> calling it from various get_config function (Fix CI build warning)
> V7: Fixed checkpatch warnings for alignment
> V8: Rebase
> V9: Rebase
> V10: Rebase
>
> Cc: Ville Syrjala
> Cc: Maarten Lankhorst
> Reviewed-by: Maarten Lankhorst
> Signed-off-by: Shashank Sharma
> ---
> drivers/gpu/drm/i915/intel_color.c | 2 +-
> drivers/gpu/drm/i915/intel_ddi.c | 2 +-
> drivers/gpu/drm/i915/intel_display.c | 72
> +---
> drivers/gpu/drm/i915/intel_drv.h | 4 +-
> drivers/gpu/drm/i915/intel_hdmi.c| 6 +--
> drivers/gpu/drm/i915/intel_panel.c | 2 +-
> 6 files changed, 50 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_color.c
> b/drivers/gpu/drm/i915/intel_color.c
> index c6a7bea..bf9d8f6 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -149,7 +149,7 @@ static void ilk_load_csc_matrix(struct drm_crtc_state
> *crtc_state)
> if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
> limited_color_range = intel_crtc_state->limited_color_range;
>
> - if (intel_crtc_state->ycbcr420) {
> + if (intel_crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
> ilk_load_ycbcr_conversion_matrix(intel_crtc);
> return;
> } else if (crtc_state->ctm) {
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 0adc043..a036fe6 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1442,7 +1442,7 @@ static void ddi_dotclock_get(struct intel_crtc_state
> *pipe_config)
> else
> dotclock = pipe_config->port_clock;
>
> - if (pipe_config->ycbcr420)
> + if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
> dotclock *= 2;
>
> if (pipe_config->pixel_multiplier)
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 5e5bc06..e2a1e4f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4811,7 +4811,8 @@ skl_update_scaler(struct intel_crtc_state *crtc_state,
> bool force_detach,
> if (pixel_format == DRM_FORMAT_NV12)
> need_scaling = true;
>
> - if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
> + if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
> + scaler_user == SKL_CRTC_INDEX)
> need_scaling = true;
>
> /*
> @@ -6620,7 +6621,8 @@ static int intel_crtc_compute_config(struct intel_crtc
> *crtc,
> return -EINVAL;
> }
>
> - if (pipe_config->ycbcr420 && pipe_config->base.ctm) {
> + if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
> + pipe_config->base.ctm) {
> /*
>* There is only one pipe CSC unit per pipe, and we need that
>* for output conversion from RGB->YCBCR. So if CTM is already
> @@ -7818,6 +7820,35 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc,
> pipe_config->port_clock = chv_calc_dpll_params(refclk, );
> }
>
> +static void intel_get_crtc_ycbcr_config(struct intel_crtc *crtc,
> + struct intel_crtc_state *pipe_config)
> +{
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum intel_output_format output = INTEL_OUTPUT_FORMAT_RGB;
> +
> + if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
> + u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
> +
> + if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
> + bool ycbcr420_enabled = tmp & PIPEMISC_YUV420_ENABLE;
> + bool blend = tmp & PIPEMISC_YUV420_MODE_FULL_BLEND;
> +
> + if (ycbcr420_enabled)
[Intel-gfx] [PATH i-g-t v12 2/2] tests: add slice power programming test
From: Lionel Landwerlin
Verifies that the kernel programs slices correctly based by reading
the value of PWR_CLK_STATE register or MI_SET_PREDICATE on platforms
before Cannonlake.
v2: Add subslice tests (Lionel)
Use MI_SET_PREDICATE for further verification when available (Lionel)
v3: Rename to gem_ctx_rpcs (Lionel)
v4: Update kernel API (Lionel)
Add 0 value test (Lionel)
Exercise invalid values (Lionel)
v5: Add perf tests (Lionel)
v6: Add new sysfs entry tests (Lionel)
v7: Test rsvd fields
Update for kernel series changes
v8: Drop test_no_sseu_support() test (Kelvin)
Drop drm_intel_*() apis (Chris)
v9: by Chris:
Drop all do_ioctl/do_ioctl_err()
Use gem_context_[gs]et_param()
Use gem_read() instead of mapping memory
by Lionel:
Test dynamic sseu on/off more
Tvrtko Ursulin:
v10:
* Various style tweaks and refactorings.
* New test coverage.
v11:
* Change platform support to just Gen11.
* Simplify availability test. (Chris Wilson)
* More invalid pointer tests. (Chris Wilson)
v12:
* Fix MAP_FIXED use (doh!).
* Fix get/set copy errors.
* Drop supported platform test. (Chris Wilson)
* Add mmap__gtt test. (Chris Wilson)
Signed-off-by: Lionel Landwerlin
Signed-off-by: Tvrtko Ursulin
---
tests/Makefile.am |1 +
tests/Makefile.sources |1 +
tests/gem_ctx_param.c |4 +-
tests/gem_ctx_sseu.c | 1128
tests/meson.build |7 +
5 files changed, 1140 insertions(+), 1 deletion(-)
create mode 100644 tests/gem_ctx_sseu.c
diff --git a/tests/Makefile.am b/tests/Makefile.am
index ee5a7c5e83b8..6b67bd2cc17a 100644
--- a/tests/Makefile.am
+++ b/tests/Makefile.am
@@ -107,6 +107,7 @@ gem_close_race_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
gem_close_race_LDADD = $(LDADD) -lpthread
gem_ctx_thrash_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
gem_ctx_thrash_LDADD = $(LDADD) -lpthread
+gem_ctx_sseu_LDADD = $(LDADD) $(top_builddir)/lib/libigt_perf.la
gem_exec_parallel_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
gem_exec_parallel_LDADD = $(LDADD) -lpthread
gem_fence_thrash_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index c84933f1d971..f8f2c8d67d72 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -56,6 +56,7 @@ TESTS_progs = \
gem_ctx_exec \
gem_ctx_isolation \
gem_ctx_param \
+ gem_ctx_sseu \
gem_ctx_switch \
gem_ctx_thrash \
gem_double_irq_loop \
diff --git a/tests/gem_ctx_param.c b/tests/gem_ctx_param.c
index c46fd709b0d7..af1afeaa2f2f 100644
--- a/tests/gem_ctx_param.c
+++ b/tests/gem_ctx_param.c
@@ -294,11 +294,13 @@ igt_main
set_priority(fd);
}
+ /* I915_CONTEXT_PARAM_SSEU tests are located in gem_ctx_sseu.c */
+
/* NOTE: This testcase intentionally tests for the next free parameter
* to catch ABI extensions. Don't "fix" this testcase without adding all
* the tests for the new param first.
*/
- arg.param = I915_CONTEXT_PARAM_PRIORITY + 1;
+ arg.param = I915_CONTEXT_PARAM_SSEU + 1;
igt_subtest("invalid-param-get") {
arg.ctx_id = ctx;
diff --git a/tests/gem_ctx_sseu.c b/tests/gem_ctx_sseu.c
new file mode 100644
index ..b38b1e527767
--- /dev/null
+++ b/tests/gem_ctx_sseu.c
@@ -0,0 +1,1128 @@
+/*
+ * Copyright © 2017-2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *Lionel Landwerlin
+ *
+ */
+
+#include "igt.h"
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "igt_dummyload.h"
+#include "igt_perf.h"
+#include "igt_sysfs.h"
+#include "ioctl_wrappers.h"
+
+IGT_TEST_DESCRIPTION("Test context render powergating programming.");
+
+#define MI_STORE_REGISTER_MEM (0x24 << 23)
+
+#define
Re: [Intel-gfx] [PATCH v10 1/8] drm/i915: Introduce CRTC output format
On Tue, Aug 14, 2018 at 03:23:19PM +0530, Shashank Sharma wrote:
> This patch adds an enum "intel_output_format" to represent
> the output format of a particular CRTC. This enum will be
> used to produce a RGB/YCBCR4:4:4/YCBCR4:2:0 output format
> during the atomic modeset calculations.
>
> V5:
> - Created this separate patch to introduce and init output_format.
> - Initialize parameters of output_format_str respectively (Jani N).
> - Call it intel_output_format than crtc_output_format(Ville).
> - Set output format in pipe_config for every encoder (Ville).
> - Get rid of extra DRM_DEBUG_KMS during get_pipe_config (Ville)
>
> V6: Rebase
> V7: Fixed alignment warnings (checkpatch)
> V8: Another check[atch warning for alignment
> V9: Rebase
> V10: Rebase on top of DSI restructure
>
> Signed-off-by: Shashank Sharma
> ---
> drivers/gpu/drm/i915/intel_crt.c | 3 +++
> drivers/gpu/drm/i915/intel_display.c | 17 +
> drivers/gpu/drm/i915/intel_dp.c | 1 +
> drivers/gpu/drm/i915/intel_dp_mst.c | 1 +
> drivers/gpu/drm/i915/intel_drv.h | 8
> drivers/gpu/drm/i915/intel_dvo.c | 1 +
> drivers/gpu/drm/i915/intel_hdmi.c| 1 +
> drivers/gpu/drm/i915/intel_lvds.c| 2 ++
> drivers/gpu/drm/i915/intel_sdvo.c| 1 +
> drivers/gpu/drm/i915/intel_tv.c | 1 +
> drivers/gpu/drm/i915/vlv_dsi.c | 1 +
> 11 files changed, 37 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_crt.c
> b/drivers/gpu/drm/i915/intel_crt.c
> index 0c6bf82..e85963c 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -354,6 +354,7 @@ static bool intel_crt_compute_config(struct intel_encoder
> *encoder,
> if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
> return false;
>
> + pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
> return true;
> }
>
> @@ -368,6 +369,7 @@ static bool pch_crt_compute_config(struct intel_encoder
> *encoder,
> return false;
>
> pipe_config->has_pch_encoder = true;
> + pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
>
> return true;
> }
> @@ -389,6 +391,7 @@ static bool hsw_crt_compute_config(struct intel_encoder
> *encoder,
> return false;
>
> pipe_config->has_pch_encoder = true;
> + pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
>
> /* LPT FDI RX only supports 8bpc. */
> if (HAS_PCH_LPT(dev_priv)) {
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index cd5f1e75..5e5bc06 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -9535,6 +9535,7 @@ static bool haswell_get_pipe_config(struct intel_crtc
> *crtc,
> }
> }
>
> + pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
Looks like we're missing this for pre-hsw.
With that fixed
Reviewed-by: Ville Syrjälä
> power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
> if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
> power_domain_mask |= BIT_ULL(power_domain);
> @@ -10882,6 +10883,18 @@ static void snprintf_output_types(char *buf, size_t
> len,
> WARN_ON_ONCE(output_types != 0);
> }
>
> +static const char * const output_format_str[] = {
> + [INTEL_OUTPUT_FORMAT_INVALID] = "Invalid",
> + [INTEL_OUTPUT_FORMAT_RGB] = "RGB",
> +};
> +
> +static const char *output_formats(enum intel_output_format format)
> +{
> + if (format != INTEL_OUTPUT_FORMAT_RGB)
> + format = INTEL_OUTPUT_FORMAT_INVALID;
> + return output_format_str[format];
> +}
> +
> static void intel_dump_pipe_config(struct intel_crtc *crtc,
> struct intel_crtc_state *pipe_config,
> const char *context)
> @@ -10901,6 +10914,9 @@ static void intel_dump_pipe_config(struct intel_crtc
> *crtc,
> DRM_DEBUG_KMS("output_types: %s (0x%x)\n",
> buf, pipe_config->output_types);
>
> + DRM_DEBUG_KMS("output format: %s\n",
> + output_formats(pipe_config->output_format));
> +
> DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
> transcoder_name(pipe_config->cpu_transcoder),
> pipe_config->pipe_bpp, pipe_config->dither);
> @@ -11490,6 +11506,7 @@ intel_pipe_config_compare(struct drm_i915_private
> *dev_priv,
> PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
>
> PIPE_CONF_CHECK_I(pixel_multiplier);
> + PIPE_CONF_CHECK_I(output_format);
> PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
> if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
> IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 8e0e14b..5d907a2 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/26] drm/i915/ringbuffer: Reload PDs harder on byt/bcs
== Series Details ==
Series: series starting with [01/26] drm/i915/ringbuffer: Reload PDs harder on
byt/bcs
URL : https://patchwork.freedesktop.org/series/49476/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4797 -> Patchwork_10140 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/49476/revisions/1/mbox/
== Known issues ==
Here are the changes found in Patchwork_10140 that come from known issues:
=== IGT changes ===
Issues hit
igt@debugfs_test@read_all_entries:
fi-snb-2520m: PASS -> INCOMPLETE (fdo#103713)
igt@kms_chamelium@hdmi-hpd-fast:
fi-kbl-7500u: SKIP -> FAIL (fdo#103841, fdo#102672)
igt@kms_psr@primary_mmap_gtt:
{fi-cnl-u}: NOTRUN -> FAIL (fdo#107383) +3
Possible fixes
igt@debugfs_test@read_all_entries:
fi-icl-u: DMESG-FAIL (fdo#107411) -> PASS
igt@gem_exec_reloc@basic-gtt-read-noreloc:
fi-icl-u: DMESG-WARN (fdo#107411) -> PASS +77
igt@gem_exec_suspend@basic-s3:
fi-icl-u: DMESG-WARN (fdo#107716) -> PASS
igt@kms_psr@primary_page_flip:
fi-icl-u: FAIL (fdo#107383) -> PASS +3
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#102672 https://bugs.freedesktop.org/show_bug.cgi?id=102672
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
fdo#107383 https://bugs.freedesktop.org/show_bug.cgi?id=107383
fdo#107411 https://bugs.freedesktop.org/show_bug.cgi?id=107411
fdo#107716 https://bugs.freedesktop.org/show_bug.cgi?id=107716
== Participating hosts (51 -> 42) ==
Additional (1): fi-cnl-u
Missing(10): fi-hsw-4770r fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-ctg-p8600 fi-glk-j4005 fi-cnl-psr fi-skl-caroline fi-bdw-samus
== Build changes ==
* Linux: CI_DRM_4797 -> Patchwork_10140
CI_DRM_4797: 3209f38d7ee600583963aa7c049c5dfde658d453 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4637: 57e3d826dee154cb8664667db7660d854a707fc6 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10140: a8d5adacb4565e184ad84a38152cdb8f2470adc5 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
a8d5adacb456 drm/i915: Serialise concurrent calls to i915_gem_set_wedged()
dd26c97c9761 drm/i915: Mark up Ironlake ips with rpm wakerefs
88b1d112dd9d drm/i915: Complain if hsw_get_pipe_config acquires the same power
well twice
aaceeead6988 drm/i915/dp: Markup pps lock power well
dd7335ca2592 drm/i915: Track the wakeref used to initialise display power
domains
0f6bcf238601 drm/i915: Markup paired operations on display power domains
e99e0144c2a0 drm/i915: Syntatic sugar for using intel_runtime_pm
4e54576eb08a drm/i915: Markup paired operations on wakerefs
d49d4fa7f977 drm/i915: Track all held rpm wakerefs
28012de36835 drm/i915: Remove debugfs/i915_ppgtt_info
20da3956671d drm/i915: Report the number of closed vma held by each context in
debugfs
cb23ad1b2375 drm/i915/execlists: Assert the queue is non-empty on unsubmitting
aac3ebe81400 drm/i915/execlists: Onion unwind for logical_ring_init() failure
28400c1b7b09 drm/i915/execlists: Use coherent writes into the context image
7505baf59285 drm/i915/execlists: Delay updating ring register state after resume
c2feee8968a4 drm/i915/selftests: Basic stress test for rapid context switching
290e940a72d3 drm/i915/execlists: Avoid kicking priority on the current context
08f507254f93 drm/i915/execlists: Reset CSB pointers on canceling requests
(wedging)
c32da9127a1f drm/i915/overlay: Use the ioctl parameters directly
0871ba469085 drm/i915/overlay: Allocate physical registers from stolen
23e66541c511 drm/i915: Cache the error string
9a31f12210ea drm/i915: Clear the error PTE just once on finish
15afc0fb5e45 drm/i915: Handle incomplete Z_FINISH for compressed error states
f46fe87029ff drm/i915: Limit number of capture objects
b9e2092df49e drm/i915: Reorder execobject[] to insert non-48b objects into the
low 4G
9de40986b147 drm/i915/ringbuffer: Reload PDs harder on byt/bcs
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10140/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/psr: Enable PSR1 on gen-9+ HW
On Thu, Sep 06, 2018 at 10:06:09PM -0700, Rodrigo Vivi wrote:
> On Thu, Sep 06, 2018 at 04:52:02PM -0700, Dhinakaran Pandiyan wrote:
> > We have new tests and fixes in place since the feature was last
> > disabled.
> >
> > Try again for gen-9+ hardware and enable only PSR1 as a first step.
> >
> > Cc: Jani Nikula
> > Cc: Jose Roberto de Souza
> > Cc: Paulo Zanoni
> > Cc: Rodrigo Vivi
> > Cc: Ville Syrjälä
> > References: commit 2ee7dc497e34 ("drm/i915: disable PSR by default on
> > HSW/BDW")
> > References: commit dcb2e993f3c0 ("Revert "drm/i915: Enable PSR by default
> > on Valleyview and Cherryview."")
> > Signed-off-by: Dhinakaran Pandiyan
> > ---
> > drivers/gpu/drm/i915/intel_psr.c | 17 -
> > 1 file changed, 8 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > b/drivers/gpu/drm/i915/intel_psr.c
> > index b6838b525502..fc823f93a4dc 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -71,6 +71,10 @@ static bool psr_global_enabled(u32 debug)
> > static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
> >const struct intel_crtc_state *crtc_state)
> > {
> > + /* Disable PSR2 by default for all platforms */
> > + if (i915_modparams.enable_psr == -1)
> > + return false;
> > +
> > switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
> > case I915_PSR_DEBUG_FORCE_PSR1:
> > return false;
> > @@ -1051,7 +1055,7 @@ void intel_psr_flush(struct drm_i915_private
> > *dev_priv,
> > * intel_psr_init - Init basic PSR work and mutex.
> > * @dev_priv: i915 device private
> > *
> > - * This function is called only once at driver load to initialize basic
> > + * This function is called only once at driver load to initialize basic
> > * PSR stuff.
> > */
> > void intel_psr_init(struct drm_i915_private *dev_priv)
> > @@ -1065,19 +1069,14 @@ void intel_psr_init(struct drm_i915_private
> > *dev_priv)
> > if (!dev_priv->psr.sink_support)
> > return;
> >
> > - if (i915_modparams.enable_psr == -1) {
> > - i915_modparams.enable_psr = dev_priv->vbt.psr.enable;
> > -
> > - /* Per platform default: all disabled. */
> > - i915_modparams.enable_psr = 0;
> > - }
> > + if (i915_modparams.enable_psr == -1)
> > + if (INTEL_GEN(dev_priv) < 9 || !dev_priv->vbt.psr.enable)
> > + i915_modparams.enable_psr = 0;
> >
> > - /* Set link_standby x link_off defaults */
> > if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> > /* HSW and BDW require workarounds that we don't implement. */
> > dev_priv->psr.link_standby = false;
> > else
> > - /* For new platforms let's respect VBT back again */
>
> bikeshed: Can we please leave the clean-up for a separated patch?
> In case we need to revert we don't loose the clean-up part! :$
>
> Also a bikeshed of bikeshed: I think we need to revisit this block entirely
> anyways. I can't remember why we stopped respecting the bspec here.
> And probably this was only masking some issues that got fixed during
> your great journey! ;)
Another vbt related thing was the aux handshake thing. We tried it here
https://patchwork.freedesktop.org/series/8046/ but IIRC it caused some
problems that no one had time to diagnose so we never merged that stuff.
Not sure if anyone wants to try and figure out what went wrong there.
Actually, after a bit more digging I guess the fails were listed here
https://lists.freedesktop.org/archives/intel-gfx/2016-June/097379.html
Some sink crc issues, but as that was deemed unusable anyway maybe
there was nothing wrong after all?
--
Ville Syrjälä
Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [01/26] drm/i915/ringbuffer: Reload PDs harder on byt/bcs
== Series Details == Series: series starting with [01/26] drm/i915/ringbuffer: Reload PDs harder on byt/bcs URL : https://patchwork.freedesktop.org/series/49476/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915/ringbuffer: Reload PDs harder on byt/bcs Okay! Commit: drm/i915: Reorder execobject[] to insert non-48b objects into the low 4G Okay! Commit: drm/i915: Limit number of capture objects +./include/linux/slab.h:631:13: error: not a function Commit: drm/i915: Handle incomplete Z_FINISH for compressed error states Okay! Commit: drm/i915: Clear the error PTE just once on finish Okay! Commit: drm/i915: Cache the error string +drivers/gpu/drm/i915/i915_gpu_error.c:854:25: warning: Using plain integer as NULL pointer +drivers/gpu/drm/i915/i915_gpu_error.c:918:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gpu_error.c:918:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_sysfs.c:531:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_sysfs.c:531:23: warning: expression using sizeof(void) Commit: drm/i915/overlay: Allocate physical registers from stolen Okay! Commit: drm/i915/overlay: Use the ioctl parameters directly -O:drivers/gpu/drm/i915/intel_overlay.c:832:29: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_overlay.c:832:29: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_overlay.c:820:29: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_overlay.c:820:29: warning: expression using sizeof(void) Commit: drm/i915/execlists: Reset CSB pointers on canceling requests (wedging) Okay! Commit: drm/i915/execlists: Avoid kicking priority on the current context Okay! Commit: drm/i915/selftests: Basic stress test for rapid context switching +./include/linux/slab.h:631:13: error: undefined identifier '__builtin_mul_overflow' +./include/linux/slab.h:631:13: warning: call with no type! Commit: drm/i915/execlists: Delay updating ring register state after resume Okay! Commit: drm/i915/execlists: Use coherent writes into the context image -drivers/gpu/drm/i915/selftests/../i915_drv.h:3689:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3695:16: warning: expression using sizeof(void) Commit: drm/i915/execlists: Onion unwind for logical_ring_init() failure Okay! Commit: drm/i915/execlists: Assert the queue is non-empty on unsubmitting Okay! Commit: drm/i915: Report the number of closed vma held by each context in debugfs Okay! Commit: drm/i915: Remove debugfs/i915_ppgtt_info Okay! Commit: drm/i915: Track all held rpm wakerefs -drivers/gpu/drm/i915/selftests/../i915_drv.h:3695:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3702:16: warning: expression using sizeof(void) Commit: drm/i915: Markup paired operations on wakerefs -drivers/gpu/drm/i915/selftests/../i915_drv.h:3702:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3706:16: warning: expression using sizeof(void) Commit: drm/i915: Syntatic sugar for using intel_runtime_pm Okay! Commit: drm/i915: Markup paired operations on display power domains -drivers/gpu/drm/i915/selftests/../i915_drv.h:3706:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3708:16: warning: expression using sizeof(void) Commit: drm/i915: Track the wakeref used to initialise display power domains -drivers/gpu/drm/i915/selftests/../i915_drv.h:3708:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3710:16: warning: expression using sizeof(void) Commit: drm/i915/dp: Markup pps lock power well Okay! Commit: drm/i915: Complain if hsw_get_pipe_config acquires the same power well twice Okay! Commit: drm/i915: Mark up Ironlake ips with rpm wakerefs Okay! Commit: drm/i915: Serialise concurrent calls to i915_gem_set_wedged() Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v1] drm/i915/chv: Update csc coefficient matrix during modeset
On Mon, Sep 10, 2018 at 07:57:14PM +0530, raviraj.p.sita...@intel.com wrote: > From: P Raviraj Sitaram > > During modeset, previously configured csc coefficient matrix,if any, will > not persist. This can result in blank screen as csc mode will be programmed > while loading LUT but csc coefficient matrix remains unprogrammed. > > Changes since V1: > - Removed platform check > > Signed-off-by: P Raviraj Sitaram Thanks for the patch. Pushed to dinq. > --- > drivers/gpu/drm/i915/intel_display.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index b2bab57cd113..2b77d9350a3a 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -6014,6 +6014,8 @@ static void valleyview_crtc_enable(struct > intel_crtc_state *pipe_config, > > i9xx_set_pipeconf(intel_crtc); > > + intel_color_set_csc(_config->base); > + > intel_crtc->active = true; > > intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); > -- > 2.7.4 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/26] drm/i915/ringbuffer: Reload PDs harder on byt/bcs
== Series Details ==
Series: series starting with [01/26] drm/i915/ringbuffer: Reload PDs harder on
byt/bcs
URL : https://patchwork.freedesktop.org/series/49476/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
9de40986b147 drm/i915/ringbuffer: Reload PDs harder on byt/bcs
b9e2092df49e drm/i915: Reorder execobject[] to insert non-48b objects into the
low 4G
f46fe87029ff drm/i915: Limit number of capture objects
15afc0fb5e45 drm/i915: Handle incomplete Z_FINISH for compressed error states
9a31f12210ea drm/i915: Clear the error PTE just once on finish
23e66541c511 drm/i915: Cache the error string
0871ba469085 drm/i915/overlay: Allocate physical registers from stolen
-:16: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 6a2c4232ece1 ("drm/i915: Make
the physical object coherent with GTT")'
#16:
commit 6a2c4232ece145d8b5a8f95f767bd6d0d2d2f2bb
total: 1 errors, 0 warnings, 0 checks, 358 lines checked
c32da9127a1f drm/i915/overlay: Use the ioctl parameters directly
08f507254f93 drm/i915/execlists: Reset CSB pointers on canceling requests
(wedging)
290e940a72d3 drm/i915/execlists: Avoid kicking priority on the current context
c2feee8968a4 drm/i915/selftests: Basic stress test for rapid context switching
7505baf59285 drm/i915/execlists: Delay updating ring register state after resume
28400c1b7b09 drm/i915/execlists: Use coherent writes into the context image
aac3ebe81400 drm/i915/execlists: Onion unwind for logical_ring_init() failure
cb23ad1b2375 drm/i915/execlists: Assert the queue is non-empty on unsubmitting
-:9: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#9:
<0>[ 531.960431] drv_self-48067 527402570us : intel_gpu_reset:
engine_mask=1, ret=0, retry=0
total: 0 errors, 1 warnings, 0 checks, 7 lines checked
20da3956671d drm/i915: Report the number of closed vma held by each context in
debugfs
-:43: WARNING:LONG_LINE: line over 100 characters
#43: FILE: drivers/gpu/drm/i915/i915_debugfs.c:350:
+ seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu
inactive, %llu global, %llu shared, %llu unbound, %llu closed)\n", \
total: 0 errors, 1 warnings, 0 checks, 169 lines checked
28012de36835 drm/i915: Remove debugfs/i915_ppgtt_info
d49d4fa7f977 drm/i915: Track all held rpm wakerefs
-:105: CHECK:UNCOMMENTED_DEFINITION: spinlock_t definition without comment
#105: FILE: drivers/gpu/drm/i915/i915_drv.h:1294:
+ spinlock_t debug_lock;
total: 0 errors, 0 warnings, 1 checks, 571 lines checked
4e54576eb08a drm/i915: Markup paired operations on wakerefs
-:707: WARNING:NEW_TYPEDEFS: do not add new typedefs
#707: FILE: drivers/gpu/drm/i915/i915_drv.h:131:
+typedef depot_stack_handle_t intel_wakeref_t;
total: 0 errors, 1 warnings, 0 checks, 1970 lines checked
e99e0144c2a0 drm/i915: Syntatic sugar for using intel_runtime_pm
-:491: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible
side-effects?
#491: FILE: drivers/gpu/drm/i915/intel_drv.h:2062:
+#define with_intel_runtime_pm(i915, wf) \
+ for (wf = intel_runtime_pm_get(i915); wf; \
+intel_runtime_pm_put(i915, wf), wf = 0)
-:491: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'wf' - possible side-effects?
#491: FILE: drivers/gpu/drm/i915/intel_drv.h:2062:
+#define with_intel_runtime_pm(i915, wf) \
+ for (wf = intel_runtime_pm_get(i915); wf; \
+intel_runtime_pm_put(i915, wf), wf = 0)
-:495: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible
side-effects?
#495: FILE: drivers/gpu/drm/i915/intel_drv.h:2066:
+#define with_intel_runtime_pm_if_in_use(i915, wf) \
+ for (wf = intel_runtime_pm_get_if_in_use(i915); wf; \
+intel_runtime_pm_put(i915, wf), wf = 0)
-:495: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'wf' - possible side-effects?
#495: FILE: drivers/gpu/drm/i915/intel_drv.h:2066:
+#define with_intel_runtime_pm_if_in_use(i915, wf) \
+ for (wf = intel_runtime_pm_get_if_in_use(i915); wf; \
+intel_runtime_pm_put(i915, wf), wf = 0)
total: 0 errors, 0 warnings, 4 checks, 569 lines checked
0f6bcf238601 drm/i915: Markup paired operations on display power domains
dd7335ca2592 drm/i915: Track the wakeref used to initialise display power
domains
-:207: WARNING:LINE_SPACING: Missing a blank line after declarations
#207: FILE: drivers/gpu/drm/i915/intel_runtime_pm.c:4112:
+ struct i915_power_domains *power_domains = >power_domains;
+ intel_wakeref_t wakeref __maybe_unused =
-:224: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written
"i915->csr.dmc_payload"
#224: FILE: drivers/gpu/drm/i915/intel_runtime_pm.c:4126:
+ i915->csr.dmc_payload != NULL) {
total: 0 errors, 1 warnings, 1 checks, 320 lines checked
aaceeead6988 drm/i915/dp: Markup pps lock power well
-:52: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dp' - possible side-effects?
#52: FILE:
Re: [Intel-gfx] [PATCH] drm/i915: Nuke struct_mutex from context_setparam
On 11/09/2018 14:22, Chris Wilson wrote:
Userspace should be free to race against itself and shoot itself in
the foot if it so desires to adjust a parameter at the same time as
submitting a batch to that context. As such, the struct_mutex in context
setparam is only being used to serialise userspace against itself and
not for any protection of internal structs and so is superfluous.
v2: Separate user_flags from internal flags to reduce chance of
interference; and use locked bit ops for user updates.
Okay, email criss-cross!
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_context.c| 20 +
drivers/gpu/drm/i915/i915_gem_context.h| 33 +-
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 2 +-
3 files changed, 27 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 747b8170a15a..f772593b99ab 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -862,7 +862,7 @@ int i915_gem_context_getparam_ioctl(struct drm_device *dev,
void *data,
ret = -EINVAL;
break;
case I915_CONTEXT_PARAM_NO_ZEROMAP:
- args->value = ctx->flags & CONTEXT_NO_ZEROMAP;
+ args->value = test_bit(UCONTEXT_NO_ZEROMAP, >user_flags);
break;
case I915_CONTEXT_PARAM_GTT_SIZE:
if (ctx->ppgtt)
@@ -896,27 +896,23 @@ int i915_gem_context_setparam_ioctl(struct drm_device
*dev, void *data,
struct drm_i915_file_private *file_priv = file->driver_priv;
struct drm_i915_gem_context_param *args = data;
struct i915_gem_context *ctx;
- int ret;
+ int ret = 0;
ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
if (!ctx)
return -ENOENT;
- ret = i915_mutex_lock_interruptible(dev);
- if (ret)
- goto out;
-
switch (args->param) {
case I915_CONTEXT_PARAM_BAN_PERIOD:
ret = -EINVAL;
break;
case I915_CONTEXT_PARAM_NO_ZEROMAP:
- if (args->size) {
+ if (args->size)
ret = -EINVAL;
- } else {
- ctx->flags &= ~CONTEXT_NO_ZEROMAP;
- ctx->flags |= args->value ? CONTEXT_NO_ZEROMAP : 0;
- }
+ else if (args->value)
+ set_bit(UCONTEXT_NO_ZEROMAP, >user_flags);
+ else
+ clear_bit(UCONTEXT_NO_ZEROMAP, >user_flags);
break;
case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
if (args->size)
@@ -960,9 +956,7 @@ int i915_gem_context_setparam_ioctl(struct drm_device *dev,
void *data,
ret = -EINVAL;
break;
}
- mutex_unlock(>struct_mutex);
-out:
i915_gem_context_put(ctx);
return ret;
}
diff --git a/drivers/gpu/drm/i915/i915_gem_context.h
b/drivers/gpu/drm/i915/i915_gem_context.h
index e09673ca731d..08165f6a0a84 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/i915_gem_context.h
@@ -116,16 +116,21 @@ struct i915_gem_context {
*/
struct rcu_head rcu;
+ /**
+* @user_flags: small set of booleans controlled by the user
+*/
+ unsigned long user_flags;
+#define UCONTEXT_NO_ZEROMAP0
+#define UCONTEXT_NO_ERROR_CAPTURE 1
+#define UCONTEXT_BANNABLE 2
+
/**
* @flags: small set of booleans
*/
unsigned long flags;
-#define CONTEXT_NO_ZEROMAP BIT(0)
-#define CONTEXT_NO_ERROR_CAPTURE 1
-#define CONTEXT_CLOSED 2
-#define CONTEXT_BANNABLE 3
-#define CONTEXT_BANNED 4
-#define CONTEXT_FORCE_SINGLE_SUBMISSION5
+#define CONTEXT_BANNED 0
+#define CONTEXT_CLOSED 1
+#define CONTEXT_FORCE_SINGLE_SUBMISSION2
/**
* @hw_id: - unique identifier for the context
@@ -209,37 +214,37 @@ static inline bool i915_gem_context_is_closed(const
struct i915_gem_context *ctx
static inline void i915_gem_context_set_closed(struct i915_gem_context *ctx)
{
GEM_BUG_ON(i915_gem_context_is_closed(ctx));
- __set_bit(CONTEXT_CLOSED, >flags);
+ set_bit(CONTEXT_CLOSED, >flags);
}
static inline bool i915_gem_context_no_error_capture(const struct i915_gem_context *ctx)
{
- return test_bit(CONTEXT_NO_ERROR_CAPTURE, >flags);
+ return test_bit(UCONTEXT_NO_ERROR_CAPTURE, >user_flags);
}
static inline void i915_gem_context_set_no_error_capture(struct i915_gem_context *ctx)
{
- __set_bit(CONTEXT_NO_ERROR_CAPTURE, >flags);
+ set_bit(UCONTEXT_NO_ERROR_CAPTURE, >user_flags);
}
static inline void i915_gem_context_clear_no_error_capture(struct i915_gem_context *ctx)
Re: [Intel-gfx] [PATCH] drm/i915: Nuke struct_mutex from context_setparam
On 11/09/2018 14:14, Chris Wilson wrote: Quoting Chris Wilson (2018-09-11 13:50:22) Userspace should be free to race against itself and shoot itself in the foot if it so desires to adjust a parameter at the same time as submitting a batch to that context. As such, the struct_mutex in context setparam is only being used to serialise userspace against itself and not for any protection of internal structs and so is superfluous. Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin To reduce the amount of queasiness here, we should split off the ctx->flags and ctx->user_flags. I think all that would be needed for a start is to handle PARAM_NO_ZEROMAP with the same set/clear_bit approach as the rest. With that it would all be atomic for all theoretical scenarios. Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Nuke struct_mutex from context_setparam
Userspace should be free to race against itself and shoot itself in
the foot if it so desires to adjust a parameter at the same time as
submitting a batch to that context. As such, the struct_mutex in context
setparam is only being used to serialise userspace against itself and
not for any protection of internal structs and so is superfluous.
v2: Separate user_flags from internal flags to reduce chance of
interference; and use locked bit ops for user updates.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_context.c| 20 +
drivers/gpu/drm/i915/i915_gem_context.h| 33 +-
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 2 +-
3 files changed, 27 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 747b8170a15a..f772593b99ab 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -862,7 +862,7 @@ int i915_gem_context_getparam_ioctl(struct drm_device *dev,
void *data,
ret = -EINVAL;
break;
case I915_CONTEXT_PARAM_NO_ZEROMAP:
- args->value = ctx->flags & CONTEXT_NO_ZEROMAP;
+ args->value = test_bit(UCONTEXT_NO_ZEROMAP, >user_flags);
break;
case I915_CONTEXT_PARAM_GTT_SIZE:
if (ctx->ppgtt)
@@ -896,27 +896,23 @@ int i915_gem_context_setparam_ioctl(struct drm_device
*dev, void *data,
struct drm_i915_file_private *file_priv = file->driver_priv;
struct drm_i915_gem_context_param *args = data;
struct i915_gem_context *ctx;
- int ret;
+ int ret = 0;
ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
if (!ctx)
return -ENOENT;
- ret = i915_mutex_lock_interruptible(dev);
- if (ret)
- goto out;
-
switch (args->param) {
case I915_CONTEXT_PARAM_BAN_PERIOD:
ret = -EINVAL;
break;
case I915_CONTEXT_PARAM_NO_ZEROMAP:
- if (args->size) {
+ if (args->size)
ret = -EINVAL;
- } else {
- ctx->flags &= ~CONTEXT_NO_ZEROMAP;
- ctx->flags |= args->value ? CONTEXT_NO_ZEROMAP : 0;
- }
+ else if (args->value)
+ set_bit(UCONTEXT_NO_ZEROMAP, >user_flags);
+ else
+ clear_bit(UCONTEXT_NO_ZEROMAP, >user_flags);
break;
case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
if (args->size)
@@ -960,9 +956,7 @@ int i915_gem_context_setparam_ioctl(struct drm_device *dev,
void *data,
ret = -EINVAL;
break;
}
- mutex_unlock(>struct_mutex);
-out:
i915_gem_context_put(ctx);
return ret;
}
diff --git a/drivers/gpu/drm/i915/i915_gem_context.h
b/drivers/gpu/drm/i915/i915_gem_context.h
index e09673ca731d..08165f6a0a84 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/i915_gem_context.h
@@ -116,16 +116,21 @@ struct i915_gem_context {
*/
struct rcu_head rcu;
+ /**
+* @user_flags: small set of booleans controlled by the user
+*/
+ unsigned long user_flags;
+#define UCONTEXT_NO_ZEROMAP0
+#define UCONTEXT_NO_ERROR_CAPTURE 1
+#define UCONTEXT_BANNABLE 2
+
/**
* @flags: small set of booleans
*/
unsigned long flags;
-#define CONTEXT_NO_ZEROMAP BIT(0)
-#define CONTEXT_NO_ERROR_CAPTURE 1
-#define CONTEXT_CLOSED 2
-#define CONTEXT_BANNABLE 3
-#define CONTEXT_BANNED 4
-#define CONTEXT_FORCE_SINGLE_SUBMISSION5
+#define CONTEXT_BANNED 0
+#define CONTEXT_CLOSED 1
+#define CONTEXT_FORCE_SINGLE_SUBMISSION2
/**
* @hw_id: - unique identifier for the context
@@ -209,37 +214,37 @@ static inline bool i915_gem_context_is_closed(const
struct i915_gem_context *ctx
static inline void i915_gem_context_set_closed(struct i915_gem_context *ctx)
{
GEM_BUG_ON(i915_gem_context_is_closed(ctx));
- __set_bit(CONTEXT_CLOSED, >flags);
+ set_bit(CONTEXT_CLOSED, >flags);
}
static inline bool i915_gem_context_no_error_capture(const struct
i915_gem_context *ctx)
{
- return test_bit(CONTEXT_NO_ERROR_CAPTURE, >flags);
+ return test_bit(UCONTEXT_NO_ERROR_CAPTURE, >user_flags);
}
static inline void i915_gem_context_set_no_error_capture(struct
i915_gem_context *ctx)
{
- __set_bit(CONTEXT_NO_ERROR_CAPTURE, >flags);
+ set_bit(UCONTEXT_NO_ERROR_CAPTURE, >user_flags);
}
static inline void i915_gem_context_clear_no_error_capture(struct
i915_gem_context *ctx)
{
- __clear_bit(CONTEXT_NO_ERROR_CAPTURE, >flags);
+
Re: [Intel-gfx] [PATCH] drm/i915: Nuke struct_mutex from context_setparam
Quoting Chris Wilson (2018-09-11 13:50:22) > Userspace should be free to race against itself and shoot itself in > the foot if it so desires to adjust a parameter at the same time as > submitting a batch to that context. As such, the struct_mutex in context > setparam is only being used to serialise userspace against itself and > not for any protection of internal structs and so is superfluous. > > Signed-off-by: Chris Wilson > Cc: Tvrtko Ursulin To reduce the amount of queasiness here, we should split off the ctx->flags and ctx->user_flags. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915/overlay: Allocate physical registers from stolen
Quoting Ville Syrjälä (2018-09-11 14:07:18) > On Thu, Sep 06, 2018 at 08:01:43PM +0100, Chris Wilson wrote: > > Given that we are now reasonably confident in our ability to detect and > > reserve the stolen memory (physical memory reserved for graphics by the > > BIOS) for ourselves on most machines, we can put it to use. In this > > case, we need a page to hold the overlay registers. > > > > On an i915g running MythTv, H Buus noticed that > > > > commit 6a2c4232ece145d8b5a8f95f767bd6d0d2d2f2bb > > Author: Chris Wilson > > Date: Tue Nov 4 04:51:40 2014 -0800 > > drm/i915: Make the physical object coherent with GTT > > > > introduced stuttering into his video playback. After discarding the > > likely suspect of it being the physical cursor updates, we were left > > with the use of the phys object for the overlay. And lo, if we > > completely avoid using the phys object (allocated just once on module > > load!) by switching to stolen memory, the stuttering goes away. > > > > For lack of a better explanation, claim victory and kill two birds with > > one stone. > > A but peculiar. But looks fine to me. And we should have some > stolen pretty much everywhere. I guess my only concern is permanently > fragmenting stolen with this. Or does the allocator grab it from the > very end? Hmm, it using DRM_MM_INSERT_BEST for all atm. We can do better by using DRM_MM_INSERT_LOW for the permanent stuff, but at the beginning BEST should still be one-sided. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/overlay: Use the ioctl parameters directly
On Thu, Sep 06, 2018 at 08:01:44PM +0100, Chris Wilson wrote:
> The user parameters to put_image are not copied back to userspace
> (DRM_IOW), and so we can modify the ioctl parameters (having already been
> copied to a temporary kernel struct) directly and use those in place,
> avoiding another temporary malloc and lots of manual copying.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/intel_overlay.c | 147 ++-
> 1 file changed, 54 insertions(+), 93 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_overlay.c
> b/drivers/gpu/drm/i915/intel_overlay.c
> index 443dfaefd7a6..72eb7e48e8bc 100644
> --- a/drivers/gpu/drm/i915/intel_overlay.c
> +++ b/drivers/gpu/drm/i915/intel_overlay.c
> @@ -487,23 +487,6 @@ void intel_overlay_reset(struct drm_i915_private
> *dev_priv)
> overlay->active = false;
> }
>
> -struct put_image_params {
> - int format;
> - short dst_x;
> - short dst_y;
> - short dst_w;
> - short dst_h;
> - short src_w;
> - short src_scan_h;
> - short src_scan_w;
> - short src_h;
> - short stride_Y;
> - short stride_UV;
> - int offset_Y;
> - int offset_U;
> - int offset_V;
> -};
> -
> static int packed_depth_bytes(u32 format)
> {
> switch (format & I915_OVERLAY_DEPTH_MASK) {
> @@ -618,25 +601,25 @@ static void update_polyphase_filter(struct
> overlay_registers __iomem *regs)
>
> static bool update_scaling_factors(struct intel_overlay *overlay,
> struct overlay_registers __iomem *regs,
> -struct put_image_params *params)
> +struct drm_intel_overlay_put_image *params)
I believe we could constify a bunch of these while at it.
Quick scan didn't find any obvious fails so
Reviewed-by: Ville Syrjälä
> {
> /* fixed point with a 12 bit shift */
> u32 xscale, yscale, xscale_UV, yscale_UV;
> #define FP_SHIFT 12
> #define FRACT_MASK 0xfff
> bool scale_changed = false;
> - int uv_hscale = uv_hsubsampling(params->format);
> - int uv_vscale = uv_vsubsampling(params->format);
> + int uv_hscale = uv_hsubsampling(params->flags);
> + int uv_vscale = uv_vsubsampling(params->flags);
>
> - if (params->dst_w > 1)
> - xscale = ((params->src_scan_w - 1) << FP_SHIFT)
> - /(params->dst_w);
> + if (params->dst_width > 1)
> + xscale = ((params->src_scan_width - 1) << FP_SHIFT) /
> + params->dst_width;
> else
> xscale = 1 << FP_SHIFT;
>
> - if (params->dst_h > 1)
> - yscale = ((params->src_scan_h - 1) << FP_SHIFT)
> - /(params->dst_h);
> + if (params->dst_height > 1)
> + yscale = ((params->src_scan_height - 1) << FP_SHIFT) /
> + params->dst_height;
> else
> yscale = 1 << FP_SHIFT;
>
> @@ -713,12 +696,12 @@ static void update_colorkey(struct intel_overlay
> *overlay,
> iowrite32(flags, >DCLRKM);
> }
>
> -static u32 overlay_cmd_reg(struct put_image_params *params)
> +static u32 overlay_cmd_reg(struct drm_intel_overlay_put_image *params)
> {
> u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
>
> - if (params->format & I915_OVERLAY_YUV_PLANAR) {
> - switch (params->format & I915_OVERLAY_DEPTH_MASK) {
> + if (params->flags & I915_OVERLAY_YUV_PLANAR) {
> + switch (params->flags & I915_OVERLAY_DEPTH_MASK) {
> case I915_OVERLAY_YUV422:
> cmd |= OCMD_YUV_422_PLANAR;
> break;
> @@ -731,7 +714,7 @@ static u32 overlay_cmd_reg(struct put_image_params
> *params)
> break;
> }
> } else { /* YUV packed */
> - switch (params->format & I915_OVERLAY_DEPTH_MASK) {
> + switch (params->flags & I915_OVERLAY_DEPTH_MASK) {
> case I915_OVERLAY_YUV422:
> cmd |= OCMD_YUV_422_PACKED;
> break;
> @@ -740,7 +723,7 @@ static u32 overlay_cmd_reg(struct put_image_params
> *params)
> break;
> }
>
> - switch (params->format & I915_OVERLAY_SWAP_MASK) {
> + switch (params->flags & I915_OVERLAY_SWAP_MASK) {
> case I915_OVERLAY_NO_SWAP:
> break;
> case I915_OVERLAY_UV_SWAP:
> @@ -760,7 +743,7 @@ static u32 overlay_cmd_reg(struct put_image_params
> *params)
>
> static int intel_overlay_do_put_image(struct intel_overlay *overlay,
> struct drm_i915_gem_object *new_bo,
> - struct put_image_params *params)
> + struct drm_intel_overlay_put_image
> *params)
> {
> struct overlay_registers __iomem *regs = overlay->regs;
> struct drm_i915_private *dev_priv =
Re: [Intel-gfx] [PATCH 1/2] drm/i915/overlay: Allocate physical registers from stolen
On Thu, Sep 06, 2018 at 08:01:43PM +0100, Chris Wilson wrote:
> Given that we are now reasonably confident in our ability to detect and
> reserve the stolen memory (physical memory reserved for graphics by the
> BIOS) for ourselves on most machines, we can put it to use. In this
> case, we need a page to hold the overlay registers.
>
> On an i915g running MythTv, H Buus noticed that
>
> commit 6a2c4232ece145d8b5a8f95f767bd6d0d2d2f2bb
> Author: Chris Wilson
> Date: Tue Nov 4 04:51:40 2014 -0800
> drm/i915: Make the physical object coherent with GTT
>
> introduced stuttering into his video playback. After discarding the
> likely suspect of it being the physical cursor updates, we were left
> with the use of the phys object for the overlay. And lo, if we
> completely avoid using the phys object (allocated just once on module
> load!) by switching to stolen memory, the stuttering goes away.
>
> For lack of a better explanation, claim victory and kill two birds with
> one stone.
A but peculiar. But looks fine to me. And we should have some
stolen pretty much everywhere. I guess my only concern is permanently
fragmenting stolen with this. Or does the allocator grab it from the
very end?
Reviewed-by: Ville Syrjälä
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107600
> Fixes: 6a2c4232ece1 ("drm/i915: Make the physical object coherent with GTT")
> Signed-off-by: Chris Wilson
> Cc: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_overlay.c | 228 +--
> 1 file changed, 75 insertions(+), 153 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_overlay.c
> b/drivers/gpu/drm/i915/intel_overlay.c
> index c2f10d899329..443dfaefd7a6 100644
> --- a/drivers/gpu/drm/i915/intel_overlay.c
> +++ b/drivers/gpu/drm/i915/intel_overlay.c
> @@ -181,8 +181,9 @@ struct intel_overlay {
> u32 brightness, contrast, saturation;
> u32 old_xscale, old_yscale;
> /* register access */
> - u32 flip_addr;
> struct drm_i915_gem_object *reg_bo;
> + struct overlay_registers __iomem *regs;
> + u32 flip_addr;
> /* flip handling */
> struct i915_gem_active last_flip;
> };
> @@ -210,29 +211,6 @@ static void i830_overlay_clock_gating(struct
> drm_i915_private *dev_priv,
> PCI_DEVFN(0, 0), I830_CLOCK_GATE, val);
> }
>
> -static struct overlay_registers __iomem *
> -intel_overlay_map_regs(struct intel_overlay *overlay)
> -{
> - struct drm_i915_private *dev_priv = overlay->i915;
> - struct overlay_registers __iomem *regs;
> -
> - if (OVERLAY_NEEDS_PHYSICAL(dev_priv))
> - regs = (struct overlay_registers __iomem
> *)overlay->reg_bo->phys_handle->vaddr;
> - else
> - regs = io_mapping_map_wc(_priv->ggtt.iomap,
> - overlay->flip_addr,
> - PAGE_SIZE);
> -
> - return regs;
> -}
> -
> -static void intel_overlay_unmap_regs(struct intel_overlay *overlay,
> - struct overlay_registers __iomem *regs)
> -{
> - if (!OVERLAY_NEEDS_PHYSICAL(overlay->i915))
> - io_mapping_unmap(regs);
> -}
> -
> static void intel_overlay_submit_request(struct intel_overlay *overlay,
>struct i915_request *rq,
>i915_gem_retire_fn retire)
> @@ -784,13 +762,13 @@ static int intel_overlay_do_put_image(struct
> intel_overlay *overlay,
> struct drm_i915_gem_object *new_bo,
> struct put_image_params *params)
> {
> - int ret, tmp_width;
> - struct overlay_registers __iomem *regs;
> - bool scale_changed = false;
> + struct overlay_registers __iomem *regs = overlay->regs;
> struct drm_i915_private *dev_priv = overlay->i915;
> u32 swidth, swidthsw, sheight, ostride;
> enum pipe pipe = overlay->crtc->pipe;
> + bool scale_changed = false;
> struct i915_vma *vma;
> + int ret, tmp_width;
>
> lockdep_assert_held(_priv->drm.struct_mutex);
>
> WARN_ON(!drm_modeset_is_locked(_priv->drm.mode_config.connection_mutex));
> @@ -815,30 +793,19 @@ static int intel_overlay_do_put_image(struct
> intel_overlay *overlay,
>
> if (!overlay->active) {
> u32 oconfig;
> - regs = intel_overlay_map_regs(overlay);
> - if (!regs) {
> - ret = -ENOMEM;
> - goto out_unpin;
> - }
> +
> oconfig = OCONF_CC_OUT_8BIT;
> if (IS_GEN4(dev_priv))
> oconfig |= OCONF_CSC_MODE_BT709;
> oconfig |= pipe == 0 ?
> OCONF_PIPE_A : OCONF_PIPE_B;
> iowrite32(oconfig, >OCONFIG);
> - intel_overlay_unmap_regs(overlay, regs);
>
> ret = intel_overlay_on(overlay);
> if (ret !=
[Intel-gfx] [PATCH] drm/i915: Nuke struct_mutex from context_setparam
Userspace should be free to race against itself and shoot itself in
the foot if it so desires to adjust a parameter at the same time as
submitting a batch to that context. As such, the struct_mutex in context
setparam is only being used to serialise userspace against itself and
not for any protection of internal structs and so is superfluous.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_context.c | 8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 747b8170a15a..10fd742b591d 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -896,16 +896,12 @@ int i915_gem_context_setparam_ioctl(struct drm_device
*dev, void *data,
struct drm_i915_file_private *file_priv = file->driver_priv;
struct drm_i915_gem_context_param *args = data;
struct i915_gem_context *ctx;
- int ret;
+ int ret = 0;
ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
if (!ctx)
return -ENOENT;
- ret = i915_mutex_lock_interruptible(dev);
- if (ret)
- goto out;
-
switch (args->param) {
case I915_CONTEXT_PARAM_BAN_PERIOD:
ret = -EINVAL;
@@ -960,9 +956,7 @@ int i915_gem_context_setparam_ioctl(struct drm_device *dev,
void *data,
ret = -EINVAL;
break;
}
- mutex_unlock(>struct_mutex);
-out:
i915_gem_context_put(ctx);
return ret;
}
--
2.19.0.rc2
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/4] fbdev: Drop FBINFO_CAN_FORCE_OUTPUT flag
On Tue, Sep 11, 2018 at 10:47:34AM +0200, Bartlomiej Zolnierkiewicz wrote: > On 09/11/2018 09:42 AM, Daniel Vetter wrote: > > On Mon, Sep 10, 2018 at 02:48:43PM +0200, Bartlomiej Zolnierkiewicz wrote: > >> > >> On 08/22/2018 10:54 AM, Daniel Vetter wrote: > >>> This was only added for the drm's fbdev emulation support, so that it > >>> would try harder to show the Oops. > >>> > >>> Unfortunately this never really worked reliably, and in practice ended > >>> up pushing the real Oops off the screen due to plentyfull locking, > >>> sleep-while-atomic and other issues. So we removed all that support > >>> from the fbdev emulation a while back. Aside: We've also removed the > >>> kgdb support, for similar reasons. > >>> > >>> Since it's such a small patch I figured I don't split this up into the > >>> usual 3-phase removal. > >>> > >>> Cc: Ben Skeggs > >>> Cc: Bartlomiej Zolnierkiewicz > >>> Cc: Greg Kroah-Hartman > >>> Cc: Hans de Goede > >>> Cc: Daniel Vetter > >>> Cc: Alexander Kapshuk > >>> Cc: Kees Cook > >>> Cc: Thierry Reding > >>> Cc: David Lechner > >>> Cc: nouv...@lists.freedesktop.org > >>> Cc: linux-fb...@vger.kernel.org > >>> Signed-off-by: Daniel Vetter > >> > >> Acked-by: Bartlomiej Zolnierkiewicz > > > > Ack for merging the entire series through drm-misc-next? > > Yes, thanks for taking care of this. Thanks, all merged into drm-misc-next for 4.20. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/4] vt: Remove vc_panic_force_write
On Wed, Aug 22, 2018 at 10:59:19AM +0200, Greg Kroah-Hartman wrote: > On Wed, Aug 22, 2018 at 10:54:03AM +0200, Daniel Vetter wrote: > > It was only used by the panic support in fbcon, which is now gone. > > Remove this now dead code too. > > > > Cc: Greg Kroah-Hartman > > Cc: Kees Cook > > Cc: Joe Perches > > Cc: Daniel Vetter > > Cc: Meng Xu > > Cc: Nicolas Pitre > > Cc: Thomas Meyer > > Cc: Mike Frysinger > > Cc: Bartlomiej Zolnierkiewicz > > Cc: Hans de Goede > > Cc: Thierry Reding > > Cc: David Lechner > > Cc: Philippe Ombredanne > > Cc: Thomas Gleixner > > Cc: Kate Stewart > > Signed-off-by: Daniel Vetter > > --- > > Acked-by: Greg Kroah-Hartman Queued for 4.20/5.0 in drm-misc-next together with the other patches in this series. -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 20/26] drm/i915: Syntatic sugar for using intel_runtime_pm
Frequently, we use intel_runtime_pm_get/_put around a small block.
Formalise that usage by providing a macro to define such a block with an
automatic closure to scope the intel_runtime_pm wakeref to that block,
i.e. macro abuse smelling of python.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 163 ++-
drivers/gpu/drm/i915/i915_gem.c | 10 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 23 ++--
drivers/gpu/drm/i915/i915_gem_shrinker.c | 44 +++---
drivers/gpu/drm/i915/i915_pmu.c | 7 +-
drivers/gpu/drm/i915/i915_sysfs.c| 7 +-
drivers/gpu/drm/i915/intel_drv.h | 8 ++
drivers/gpu/drm/i915/intel_guc_log.c | 26 ++--
drivers/gpu/drm/i915/intel_huc.c | 7 +-
drivers/gpu/drm/i915/intel_panel.c | 18 +--
drivers/gpu/drm/i915/intel_uncore.c | 30 ++---
11 files changed, 162 insertions(+), 181 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index dbfe4e456d97..98fa216d19bb 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -952,9 +952,9 @@ static int i915_gpu_info_open(struct inode *inode, struct
file *file)
struct i915_gpu_state *gpu;
intel_wakeref_t wakeref;
- wakeref = intel_runtime_pm_get(i915);
- gpu = i915_capture_gpu_state(i915);
- intel_runtime_pm_put(i915, wakeref);
+ gpu = NULL;
+ with_intel_runtime_pm(i915, wakeref)
+ gpu = i915_capture_gpu_state(i915);
if (!gpu)
return -ENOMEM;
@@ -1015,9 +1015,8 @@ i915_next_seqno_set(void *data, u64 val)
if (ret)
return ret;
- wakeref = intel_runtime_pm_get(dev_priv);
- ret = i915_gem_set_global_seqno(dev, val);
- intel_runtime_pm_put(dev_priv, wakeref);
+ with_intel_runtime_pm(dev_priv, wakeref)
+ ret = i915_gem_set_global_seqno(dev, val);
mutex_unlock(>struct_mutex);
@@ -1305,17 +1304,15 @@ static int i915_hangcheck_info(struct seq_file *m, void
*unused)
return 0;
}
- wakeref = intel_runtime_pm_get(dev_priv);
+ with_intel_runtime_pm(dev_priv, wakeref) {
+ for_each_engine(engine, dev_priv, id) {
+ acthd[id] = intel_engine_get_active_head(engine);
+ seqno[id] = intel_engine_get_seqno(engine);
+ }
- for_each_engine(engine, dev_priv, id) {
- acthd[id] = intel_engine_get_active_head(engine);
- seqno[id] = intel_engine_get_seqno(engine);
+ intel_engine_get_instdone(dev_priv->engine[RCS], );
}
- intel_engine_get_instdone(dev_priv->engine[RCS], );
-
- intel_runtime_pm_put(dev_priv, wakeref);
-
if (timer_pending(_priv->gpu_error.hangcheck_work.timer))
seq_printf(m, "Hangcheck active, timer fires in %dms\n",
jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
@@ -1591,18 +1588,16 @@ static int i915_drpc_info(struct seq_file *m, void
*unused)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
intel_wakeref_t wakeref;
- int err;
-
- wakeref = intel_runtime_pm_get(dev_priv);
-
- if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- err = vlv_drpc_info(m);
- else if (INTEL_GEN(dev_priv) >= 6)
- err = gen6_drpc_info(m);
- else
- err = ironlake_drpc_info(m);
+ int err = -ENODEV;
- intel_runtime_pm_put(dev_priv, wakeref);
+ with_intel_runtime_pm(dev_priv, wakeref) {
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+ err = vlv_drpc_info(m);
+ else if (INTEL_GEN(dev_priv) >= 6)
+ err = gen6_drpc_info(m);
+ else
+ err = ironlake_drpc_info(m);
+ }
return err;
}
@@ -2167,9 +2162,8 @@ static int i915_huc_load_status_info(struct seq_file *m,
void *data)
p = drm_seq_file_printer(m);
intel_uc_fw_dump(_priv->huc.fw, );
- wakeref = intel_runtime_pm_get(dev_priv);
- seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));
- intel_runtime_pm_put(dev_priv, wakeref);
+ with_intel_runtime_pm(dev_priv, wakeref)
+ seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));
return 0;
}
@@ -2179,7 +2173,6 @@ static int i915_guc_load_status_info(struct seq_file *m,
void *data)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
intel_wakeref_t wakeref;
struct drm_printer p;
- u32 tmp, i;
if (!HAS_GUC(dev_priv))
return -ENODEV;
@@ -2187,22 +2180,23 @@ static int i915_guc_load_status_info(struct seq_file
*m, void *data)
p = drm_seq_file_printer(m);
