[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftest: test aligned offsets for 64K
== Series Details == Series: drm/i915/selftest: test aligned offsets for 64K URL : https://patchwork.freedesktop.org/series/51707/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5052_full -> Patchwork_10636_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_10636_full that come from known issues: === IGT changes === Issues hit igt@drv_suspend@fence-restore-untiled: shard-skl: NOTRUN -> INCOMPLETE (fdo#104108, fdo#107773) igt@gem_exec_schedule@pi-ringfull-bsd: shard-skl: NOTRUN -> FAIL (fdo#103158) igt@gem_userptr_blits@readonly-unsync: shard-skl: NOTRUN -> INCOMPLETE (fdo#108074) igt@kms_busy@extended-modeset-hang-newfb-render-a: shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) +2 igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a: shard-snb: NOTRUN -> DMESG-WARN (fdo#107956) +1 igt@kms_chv_cursor_fail@pipe-c-128x128-top-edge: shard-skl: NOTRUN -> FAIL (fdo#104671) igt@kms_cursor_crc@cursor-256x256-random: shard-apl: PASS -> FAIL (fdo#103232) igt@kms_cursor_crc@cursor-256x256-sliding: shard-glk: PASS -> FAIL (fdo#103232) +3 igt@kms_flip@2x-flip-vs-modeset-interruptible: shard-hsw: PASS -> DMESG-WARN (fdo#102614) igt@kms_flip@dpms-vs-vblank-race: shard-kbl: PASS -> DMESG-WARN (fdo#103313, fdo#103558, fdo#105345) igt@kms_flip@flip-vs-expired-vblank: shard-skl: NOTRUN -> FAIL (fdo#105363) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt: shard-glk: PASS -> FAIL (fdo#103167) +2 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc: shard-skl: NOTRUN -> FAIL (fdo#103167) +2 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move: shard-apl: PASS -> FAIL (fdo#103167) igt@kms_plane_alpha_blend@pipe-a-alpha-7efc: shard-skl: NOTRUN -> FAIL (fdo#108145, fdo#107815) igt@kms_plane_alpha_blend@pipe-c-alpha-7efc: shard-apl: NOTRUN -> FAIL (fdo#108145) igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: shard-skl: NOTRUN -> FAIL (fdo#108145) +1 igt@kms_plane_multiple@atomic-pipe-a-tiling-y: shard-apl: PASS -> FAIL (fdo#103166) +2 igt@kms_setmode@basic: shard-snb: NOTRUN -> FAIL (fdo#99912) igt@kms_sysfs_edid_timing: shard-skl: NOTRUN -> FAIL (fdo#100047) Possible fixes igt@gem_eio@in-flight-contexts-1us: shard-glk: FAIL (fdo#105957) -> PASS igt@gem_ppgtt@blt-vs-render-ctxn: shard-kbl: INCOMPLETE (fdo#103665, fdo#106887, fdo#106023) -> PASS igt@kms_ccs@pipe-a-crc-sprite-planes-basic: shard-glk: FAIL (fdo#108145) -> PASS igt@kms_cursor_crc@cursor-256x256-random: shard-glk: FAIL (fdo#103232) -> PASS igt@kms_cursor_crc@cursor-64x21-sliding: shard-apl: FAIL (fdo#103232) -> PASS +2 igt@kms_cursor_legacy@cursora-vs-flipa-toggle: shard-glk: DMESG-WARN (fdo#105763, fdo#106538) -> PASS igt@kms_draw_crc@draw-method-rgb565-pwrite-ytiled: shard-glk: FAIL (fdo#103184) -> PASS +2 igt@kms_flip@plain-flip-fb-recreate: shard-skl: FAIL (fdo#100368) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt: shard-apl: FAIL (fdo#103167) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move: shard-glk: FAIL (fdo#103167) -> PASS igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff: shard-glk: DMESG-FAIL (fdo#106538, fdo#103167) -> PASS igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: shard-apl: INCOMPLETE (fdo#103927) -> PASS +1 igt@kms_plane_multiple@atomic-pipe-a-tiling-y: shard-glk: FAIL (fdo#103166) -> PASS +1 igt@kms_plane_multiple@atomic-pipe-a-tiling-yf: shard-apl: FAIL (fdo#103166) -> PASS igt@kms_setmode@basic: shard-apl: FAIL (fdo#99912) -> PASS igt@kms_vblank@pipe-c-wait-busy: shard-kbl: DMESG-WARN (fdo#105602, fdo#103558) -> PASS +3 igt@pm_rpm@system-suspend: shard-skl: INCOMPLETE (fdo#104108, fdo#107773, fdo#107807) -> PASS fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047 fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158 fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103184
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftest: fix 64K alignment in igt_write_huge
== Series Details == Series: drm/i915/selftest: fix 64K alignment in igt_write_huge URL : https://patchwork.freedesktop.org/series/51705/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5051_full -> Patchwork_10635_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_10635_full that come from known issues: === IGT changes === Issues hit igt@drv_suspend@shrink: shard-glk: PASS -> INCOMPLETE (k.org#198133, fdo#106886, fdo#103359) igt@gem_softpin@noreloc-s3: shard-skl: PASS -> INCOMPLETE (fdo#107773, fdo#104108) igt@gem_userptr_blits@unsync-unmap: shard-glk: PASS -> DMESG-WARN (fdo#105763, fdo#106538) +1 igt@kms_busy@extended-modeset-hang-newfb-render-c: shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b: shard-snb: NOTRUN -> DMESG-WARN (fdo#107956) +1 igt@kms_color@pipe-c-degamma: shard-apl: PASS -> FAIL (fdo#104782) igt@kms_cursor_crc@cursor-256x85-random: shard-apl: PASS -> FAIL (fdo#103232) +2 igt@kms_draw_crc@draw-method-rgb565-pwrite-ytiled: shard-glk: PASS -> FAIL (fdo#103184) igt@kms_fbcon_fbt@psr-suspend: shard-skl: NOTRUN -> FAIL (fdo#107882) igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen: shard-glk: PASS -> FAIL (fdo#103167) igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff: shard-glk: PASS -> DMESG-FAIL (fdo#106538) igt@kms_frontbuffer_tracking@fbc-stridechange: shard-skl: NOTRUN -> FAIL (fdo#105683) igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb: shard-skl: NOTRUN -> FAIL (fdo#108145) +1 igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: shard-skl: NOTRUN -> FAIL (fdo#107815) igt@kms_plane_multiple@atomic-pipe-b-tiling-x: shard-glk: PASS -> FAIL (fdo#103166) shard-apl: PASS -> FAIL (fdo#103166) +1 igt@kms_setmode@basic: shard-snb: NOTRUN -> FAIL (fdo#99912) igt@pm_rpm@system-suspend-execbuf: shard-skl: PASS -> INCOMPLETE (fdo#107807, fdo#104108) Possible fixes igt@gem_eio@in-flight-contexts-1us: shard-glk: FAIL (fdo#105957) -> PASS igt@gem_eio@in-flight-suspend: shard-glk: DMESG-WARN -> PASS igt@gem_pwrite@big-cpu-forwards: shard-apl: INCOMPLETE (fdo#103927) -> PASS igt@kms_cursor_crc@cursor-256x85-onscreen: shard-apl: FAIL (fdo#103232) -> PASS igt@kms_cursor_legacy@cursorb-vs-flipb-toggle: shard-glk: DMESG-WARN (fdo#105763, fdo#106538) -> PASS igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled: shard-glk: FAIL (fdo#103184) -> PASS igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: shard-glk: FAIL (fdo#105363) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt: shard-apl: FAIL (fdo#103167) -> PASS +1 shard-glk: FAIL (fdo#103167) -> PASS +1 igt@kms_plane@plane-position-covered-pipe-a-planes: shard-apl: FAIL (fdo#103166) -> PASS +1 fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103184 https://bugs.freedesktop.org/show_bug.cgi?id=103184 fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108 fdo#104782 https://bugs.freedesktop.org/show_bug.cgi?id=104782 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105683 https://bugs.freedesktop.org/show_bug.cgi?id=105683 fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763 fdo#105957 https://bugs.freedesktop.org/show_bug.cgi?id=105957 fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538 fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886 fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773 fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807 fdo#107815 https://bugs.freedesktop.org/show_bug.cgi?id=107815 fdo#107882 https://bugs.freedesktop.org/show_bug.cgi?id=107882 fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956 fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 == Participating hosts (6 -> 6) == No changes in participating hosts == Build changes == * Linux: CI_DRM_5051 -> Patchwork_10635 CI_DRM_5051:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/execlists: Poison the CSB after use
== Series Details == Series: drm/i915/execlists: Poison the CSB after use URL : https://patchwork.freedesktop.org/series/51703/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5051_full -> Patchwork_10634_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_10634_full that come from known issues: === IGT changes === Issues hit igt@gem_exec_schedule@pi-ringfull-vebox: shard-skl: NOTRUN -> FAIL (fdo#103158) igt@gem_tiled_blits@interruptible: shard-apl: PASS -> DMESG-WARN (fdo#103558, fdo#105602) +2 igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b: shard-snb: NOTRUN -> DMESG-WARN (fdo#107956) +1 igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c: shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) +1 igt@kms_chv_cursor_fail@pipe-c-128x128-top-edge: shard-skl: NOTRUN -> FAIL (fdo#104671) igt@kms_cursor_crc@cursor-256x85-random: shard-apl: PASS -> FAIL (fdo#103232) +4 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff: shard-apl: PASS -> FAIL (fdo#103167) igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-wc: shard-skl: NOTRUN -> FAIL (fdo#103167) +1 igt@kms_panel_fitting@legacy: shard-skl: NOTRUN -> FAIL (fdo#105456) igt@kms_plane_alpha_blend@pipe-a-alpha-7efc: shard-skl: NOTRUN -> FAIL (fdo#107815, fdo#108145) igt@kms_plane_alpha_blend@pipe-b-alpha-transparant-fb: shard-skl: NOTRUN -> FAIL (fdo#108145) +2 igt@kms_plane_multiple@atomic-pipe-b-tiling-x: shard-glk: PASS -> FAIL (fdo#103166) +1 igt@kms_plane_multiple@atomic-pipe-b-tiling-y: shard-apl: PASS -> FAIL (fdo#103166) +1 igt@kms_setmode@basic: shard-snb: NOTRUN -> FAIL (fdo#99912) igt@perf@blocking: shard-hsw: PASS -> FAIL (fdo#102252) Possible fixes igt@gem_eio@in-flight-contexts-1us: shard-glk: FAIL (fdo#105957) -> PASS igt@gem_eio@in-flight-suspend: shard-glk: DMESG-WARN -> PASS igt@gem_pwrite@big-cpu-forwards: shard-apl: INCOMPLETE (fdo#103927) -> PASS igt@gem_userptr_blits@readonly-unsync: shard-skl: INCOMPLETE (fdo#108074) -> PASS igt@kms_cursor_crc@cursor-256x256-random: shard-apl: FAIL (fdo#103232) -> PASS +1 igt@kms_cursor_legacy@cursorb-vs-flipb-toggle: shard-glk: DMESG-WARN (fdo#106538, fdo#105763) -> PASS igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled: shard-glk: FAIL (fdo#103184) -> PASS igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: shard-glk: FAIL (fdo#105363) -> PASS igt@kms_flip@2x-wf_vblank-ts-check: shard-snb: INCOMPLETE (fdo#105411) -> SKIP igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt: shard-apl: FAIL (fdo#103167) -> PASS +1 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite: shard-glk: FAIL (fdo#103167) -> PASS +1 igt@kms_plane_multiple@atomic-pipe-a-tiling-y: shard-apl: FAIL (fdo#103166) -> PASS +1 Warnings igt@kms_plane_alpha_blend@pipe-b-alpha-basic: shard-kbl: FAIL (fdo#108145) -> DMESG-FAIL (fdo#108145) fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158 fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103184 https://bugs.freedesktop.org/show_bug.cgi?id=103184 fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232 fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#104671 https://bugs.freedesktop.org/show_bug.cgi?id=104671 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#105456 https://bugs.freedesktop.org/show_bug.cgi?id=105456 fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602 fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763 fdo#105957 https://bugs.freedesktop.org/show_bug.cgi?id=105957 fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538 fdo#107815 https://bugs.freedesktop.org/show_bug.cgi?id=107815 fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956 fdo#108074 https://bugs.freedesktop.org/show_bug.cgi?id=108074 fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (6 -> 6) == No changes in participating hosts == Build changes ==
Re: [Intel-gfx] [v3 4/7] i915/dp/fec: Add can_fec to the crtc state.
On Thu, Oct 25, 2018 at 09:49:40PM -0700, Anusha Srivatsa wrote:
> Add a crtc state for FEC. Currently, the state
> is determined by platform, DP and DSC being
> enabled. Moving forward we can use the state
> to have error correction on other scenarios too
> if needed.
>
> Suggested-by: Ville Syrjala
> Cc: Ville Syrjala
> Cc: Jani Nikula
> Cc: Manasi Navare
> Signed-off-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/intel_dp.c | 22 ++
> drivers/gpu/drm/i915/intel_drv.h | 3 +++
> 2 files changed, 25 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index cfcef9e4b5d9..4776ce6f2174 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2045,6 +2045,23 @@ intel_dp_compute_link_config_fast(struct intel_dp
> *intel_dp,
> return false;
> }
>
> +static bool intel_dp_can_fec(struct intel_dp *intel_dp,
> + struct intel_crtc_state *pipe_config)
I would prefer naming it as intel_dp_supports_fec since as per Ville's feedback
on adding helper function for DSC that will be called intel_dp_supports_dsc
> +{
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
You dont need dig_port, you can obtain dev_priv from intel_dp directly:
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> + if (INTEL_GEN(dev_priv) < 11 || intel_dp_is_edp(intel_dp))
> + return false;
> +
> + /* On Gen 11, FEC is Supported Only for DP SST modes.
> + * Let us start by enabling FEC for Compressed streams.
> + */
Where is the check for sink FEC support?
> + if (pipe_config->dsc_params.compression_enable)
> + return true;
I think this logic also looks reversed. The compression_enable state should
be set based on whether can_fec is true and not the vice versa.
IMHO, can_fec is decided solely on the platform support.
Infact since can_fec or fec_support solely depends on platform and sink FEC
support,
we dont need a can_fec state , that can just be obtained using a helper
intel_dp_supports_fec() which will check platform support and sink support.
Now if we are saying that we want to enable fec based on mode, then we need
fec_enable
state in crtc and that can be set if intel_dp_supports_fec and for now only if
compression_en
is set.
Jani, Ville what are your thoughts on this?
> + else
> + return false;
You can swap these and have false earlier and avoid else
Just return true at the end.
Manasi
> +
> +}
> static bool intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> struct intel_crtc_state *pipe_config,
> struct link_config_limits *limits)
> @@ -2129,6 +2146,11 @@ static bool intel_dp_dsc_compute_config(struct
> intel_dp *intel_dp,
> pipe_config->dsc_params.compressed_bpp,
> pipe_config->dsc_params.slice_count);
>
> + /* For DP 1.4, Enable DSC if FEC can be configured */
> + pipe_config->can_fec = intel_dp_can_fec(intel_dp, pipe_config);
> + if (!pipe_config->can_fec)
> + return false;
> +
> return true;
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 9a94c6544bf5..9dac242ead12 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -940,6 +940,9 @@ struct intel_crtc_state {
> u8 slice_count;
> } dsc_params;
> struct drm_dsc_config dp_dsc_cfg;
> +
> + /* Forward Error correction State */
> + bool can_fec;
> };
>
> struct intel_crtc {
> --
> 2.17.1
>
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Re: [Intel-gfx] [v3 2/7] drm/dp/fec: DRM helper for Forward Error Correction
On Thu, Oct 25, 2018 at 09:49:38PM -0700, Anusha Srivatsa wrote:
> DP 1.4 has Forward Error Correction Support(FEC).
> Add helper function to check if the sink device
> supports FEC.
>
> v2: Separate the helper and the code that uses the helper into
> two separate patches. (Manasi)
>
> v3:
> - Move the code to drm_dp_helper.c (Manasi)
> - change the return type, code style changes (Gaurav)
> - Use drm_dp_dpcd_readb instead of drm_dp_dpcd_read. (Jani)
>
> v4:
> - Avoid aux reads everytime, instead read cached
> values of dpcd register (jani)
> - Move helper to drm_dp_helper.h like other dsc
> helpers.(Anusha)
>
> v5: rebased. Change the helper parameter suitably.
>
> Cc: Ville Syrjala
> Cc: Jani Nikula
> Cc: Manasi Navare
> Signed-off-by: Anusha Srivatsa
Reviewed-by: Manasi Navare
Manasi
> ---
> include/drm/drm_dp_helper.h | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 2649529d0d8f..b08f50b852f5 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -1101,6 +1101,13 @@ drm_dp_dsc_sink_max_slice_width(const u8
> dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
> DP_DSC_SLICE_WIDTH_MULTIPLIER;
> }
>
> +/* Forward Error Correction Support on DP 1.4 */
> +static inline bool
> +drm_dp_sink_supports_fec(const u8 fec_capable)
> +{
> + return fec_capable & DP_FEC_CAPABLE;
> +}
> +
> /*
> * DisplayPort AUX channel
> */
> --
> 2.17.1
>
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Re: [Intel-gfx] [v3 1/7] i915/dp/fec: Cache the FEC_CAPABLE DPCD register
On Thu, Oct 25, 2018 at 09:49:37PM -0700, Anusha Srivatsa wrote:
> Similar to DSC DPCD registers, let us cache
> FEC_CAPABLE register to avoid using stale
> values. With this we can avoid aux reads
> everytime and instead read the cached values.
>
> v2: Avoid using memset and array for a single
> field. (Manasi,Jani)
>
> Suggested-by: Jani Nikula
> Cc: Jani Nikula
> Cc: Ville Syrjala
> Cc: Manasi Navare
> Signed-off-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/intel_dp.c | 10 ++
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> 2 files changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 5a638503e36a..16d1db7c9398 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4198,9 +4198,13 @@ static void intel_dp_get_dsc_sink_cap(struct intel_dp
> *intel_dp)
> /*
>*Clear the cached register set to avoid using stale values
>* for the sinks that do not support DSC.
> + * Similarly, clear the cached FEC register.
You dont need this comment here about clearing cached reg since you have
a separate comment below.
>*/
> memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
>
> + /* Clear fec_capable to avoid using stale values */
> + intel_dp->fec_capable = 0;
> +
> /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
> if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
> intel_dp->edp_dpcd[0] >= DP_EDP_14) {
> @@ -4214,6 +4218,12 @@ static void intel_dp_get_dsc_sink_cap(struct intel_dp
> *intel_dp)
> (int)sizeof(intel_dp->dsc_dpcd),
> intel_dp->dsc_dpcd);
> }
Why cant you embed reading FEC reg in the above condition.
Within that just check !edp and read fec reg.
Manasi
> + /* FEC is supported only on DP 1.4 */
> + if (!intel_dp_is_edp(intel_dp) && intel_dp->dpcd[DP_DPCD_REV] >= 0x14) {
> + if (drm_dp_dpcd_readb(_dp->aux, DP_FEC_CAPABILITY,
> + _dp->fec_capable) < 0)
> + DRM_ERROR("Failed to read FEC DPCD register\n");
> + }
> }
>
> static bool
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 16bbc3768e02..9a94c6544bf5 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1119,6 +1119,7 @@ struct intel_dp {
> uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
> uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
> u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
> + u8 fec_capable;
> /* source rates */
> int num_source_rates;
> const int *source_rates;
> --
> 2.17.1
>
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Re: [Intel-gfx] [PATCH] RFC: Make igts for cross-driver stuff mandatory?
On Fri, 19 Oct 2018 at 18:51, Daniel Vetter wrote: > > Hi all, > > This is just to collect feedback on this idea, and see whether the > overall dri-devel community stands on all this. I think the past few > cross-vendor uapi extensions all came with igts attached, and > personally I think there's lots of value in having them: A > cross-vendor interface isn't useful if every driver implements it > slightly differently. > > I think there's 2 questions here: > > - Do we want to make such testcases mandatory? Yes I think if at all practical it probably makes sense to have some mandatory test cases for all cross-vendor features, or features that might become cross vendor in the future. > > - If yes, are we there yet, or is there something crucially missing > still? I think the does igt build in all the places needed is the main one, I've no idea what a baseline IGT test run looks like on non-intel hw, how useful is it? Acked-by: Dave Airlie ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v4,1/2] drm: Add drm_any_plane_has_format()
== Series Details == Series: series starting with [v4,1/2] drm: Add drm_any_plane_has_format() URL : https://patchwork.freedesktop.org/series/51700/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5050_full -> Patchwork_10633_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_10633_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10633_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10633_full: === IGT changes === Warnings igt@perf_pmu@rc6: shard-kbl: SKIP -> PASS == Known issues == Here are the changes found in Patchwork_10633_full that come from known issues: === IGT changes === Issues hit igt@gem_exec_schedule@pi-ringfull-bsd: shard-skl: NOTRUN -> FAIL (fdo#103158) igt@gem_softpin@noreloc-s3: shard-apl: PASS -> INCOMPLETE (fdo#103927) igt@kms_color@pipe-c-degamma: shard-apl: PASS -> FAIL (fdo#104782) igt@kms_cursor_crc@cursor-128x42-onscreen: shard-skl: NOTRUN -> FAIL (fdo#103232) +1 igt@kms_cursor_crc@cursor-256x85-random: shard-apl: PASS -> FAIL (fdo#103232) +2 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt: shard-glk: PASS -> FAIL (fdo#103167) +2 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc: shard-skl: NOTRUN -> FAIL (fdo#105682) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move: shard-apl: PASS -> FAIL (fdo#103167) igt@kms_plane@pixel-format-pipe-c-planes: shard-skl: NOTRUN -> DMESG-FAIL (fdo#106885, fdo#103166) igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: shard-skl: NOTRUN -> FAIL (fdo#108145) igt@kms_plane_alpha_blend@pipe-b-alpha-basic: shard-skl: NOTRUN -> FAIL (fdo#107815, fdo#108145) +2 igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: shard-skl: NOTRUN -> FAIL (fdo#107815) igt@kms_plane_multiple@atomic-pipe-a-tiling-y: shard-apl: PASS -> FAIL (fdo#103166) igt@kms_plane_multiple@atomic-pipe-b-tiling-yf: shard-skl: NOTRUN -> FAIL (fdo#107815, fdo#103166) Possible fixes igt@gem_eio@in-flight-contexts-1us: shard-glk: FAIL (fdo#105957) -> PASS igt@gem_ppgtt@blt-vs-render-ctxn: shard-kbl: INCOMPLETE (fdo#106023, fdo#106887, fdo#103665) -> PASS igt@gem_userptr_blits@unsync-unmap: shard-glk: DMESG-WARN (fdo#105763, fdo#106538) -> PASS +1 igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c: shard-hsw: DMESG-WARN (fdo#107956) -> PASS igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c: shard-kbl: DMESG-WARN (fdo#107956) -> PASS igt@kms_cursor_crc@cursor-256x85-onscreen: shard-apl: FAIL (fdo#103232) -> PASS +6 igt@kms_draw_crc@draw-method-rgb565-pwrite-ytiled: shard-glk: FAIL (fdo#103184) -> PASS +1 igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: shard-glk: FAIL (fdo#105363) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite: shard-apl: FAIL (fdo#103167) -> PASS +1 igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff: shard-glk: FAIL (fdo#103167) -> PASS +2 igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff: shard-glk: DMESG-FAIL (fdo#106538) -> PASS igt@kms_plane@plane-position-covered-pipe-a-planes: shard-apl: FAIL (fdo#103166) -> PASS +2 igt@kms_plane_multiple@atomic-pipe-a-tiling-yf: shard-glk: FAIL (fdo#103166) -> PASS igt@kms_setmode@basic: shard-hsw: FAIL (fdo#99912) -> PASS igt@perf@polling: shard-hsw: FAIL (fdo#102252) -> PASS igt@pm_rpm@system-suspend-devices: shard-skl: INCOMPLETE (fdo#107807) -> PASS fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158 fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103184 https://bugs.freedesktop.org/show_bug.cgi?id=103184 fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#104782 https://bugs.freedesktop.org/show_bug.cgi?id=104782 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105682
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [RFC,1/4] drm/i915: Add Display Gen info.
== Series Details == Series: series starting with [RFC,1/4] drm/i915: Add Display Gen info. URL : https://patchwork.freedesktop.org/series/51717/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_5052 -> Patchwork_10643 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10643 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10643, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/51717/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10643: === IGT changes === Possible regressions igt@pm_rpm@module-reload: fi-glk-dsi: PASS -> DMESG-WARN +2 == Known issues == Here are the changes found in Patchwork_10643 that come from known issues: === IGT changes === Issues hit igt@drv_selftest@live_contexts: fi-icl-u: NOTRUN -> INCOMPLETE (fdo#108535) igt@gem_exec_suspend@basic-s4-devices: fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718) igt@kms_flip@basic-flip-vs-modeset: fi-skl-6700hq: PASS -> DMESG-WARN (fdo#105998) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-byt-clapper: PASS -> FAIL (fdo#107362, fdo#103191) +1 igt@pm_rpm@module-reload: fi-skl-6600u: PASS -> INCOMPLETE (fdo#107807) Possible fixes igt@gem_exec_suspend@basic-s3: fi-icl-u: INCOMPLETE (fdo#107713) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: fi-byt-clapper: FAIL (fdo#107362, fdo#103191) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-b: fi-byt-clapper: FAIL (fdo#107362) -> PASS fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107713 https://bugs.freedesktop.org/show_bug.cgi?id=107713 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807 fdo#108535 https://bugs.freedesktop.org/show_bug.cgi?id=108535 == Participating hosts (49 -> 43) == Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-gdg-551 == Build changes == * Linux: CI_DRM_5052 -> Patchwork_10643 CI_DRM_5052: 24b6ea5d5f299c5e9e6b4d92068651f7f1555bd0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4699: 1270ec553741ac20c45178d2b26f9a9562ea565f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10643: a52eae0799cd11b499651c9e21bfea8c34115451 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == a52eae0799cd drm/i915: Expand DISPLAY_GEN macro usage to display related files. 610ba30a4557 drm/i915: Use Display gen9 for gen9_bc || bxt cbcd72519654 drm/i915: Finally recognize Geminilake as Gen10 Display 082cfae8228c drm/i915: Add Display Gen info. == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10643/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [RFC,1/4] drm/i915: Add Display Gen info.
== Series Details == Series: series starting with [RFC,1/4] drm/i915: Add Display Gen info. URL : https://patchwork.freedesktop.org/series/51717/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Add Display Gen info. -drivers/gpu/drm/i915/selftests/../i915_drv.h:3699:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3723:16: warning: expression using sizeof(void) Commit: drm/i915: Finally recognize Geminilake as Gen10 Display -O:drivers/gpu/drm/i915/intel_cdclk.c:2178:37: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_cdclk.c:2178:37: warning: expression using sizeof(void) -drivers/gpu/drm/i915/selftests/../i915_drv.h:3723:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3722:16: warning: expression using sizeof(void) Commit: drm/i915: Use Display gen9 for gen9_bc || bxt Okay! Commit: drm/i915: Expand DISPLAY_GEN macro usage to display related files. -O:drivers/gpu/drm/i915/intel_cdclk.c:2178:37: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_cdclk.c:2181:37: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_cdclk.c:2201:29: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_cdclk.c:2178:37: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_cdclk.c:2181:37: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_cdclk.c:2201:29: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_fbc.c:88:25: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_fbc.c:90:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_fbc.c:88:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_fbc.c:90:25: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [RFC,1/4] drm/i915: Add Display Gen info.
== Series Details ==
Series: series starting with [RFC,1/4] drm/i915: Add Display Gen info.
URL : https://patchwork.freedesktop.org/series/51717/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
082cfae8228c drm/i915: Add Display Gen info.
-:83: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'x' - possible side-effects?
#83: FILE: drivers/gpu/drm/i915/i915_pci.c:33:
+#define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1), \
+ .display_gen = (x), .display_gen_mask = BIT((x))
-:86: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'x' - possible side-effects?
#86: FILE: drivers/gpu/drm/i915/i915_pci.c:36:
+#define DISPLAY_GEN(x) .display_gen = (x), .display_gen_mask = BIT((x))
total: 0 errors, 0 warnings, 2 checks, 67 lines checked
cbcd72519654 drm/i915: Finally recognize Geminilake as Gen10 Display
-:24: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible
side-effects?
#24: FILE: drivers/gpu/drm/i915/i915_drv.h:2627:
+#define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_DISPLAY_GEN(dev_priv) >= 10 || \
IS_KABYLAKE(dev_priv))
total: 0 errors, 0 warnings, 1 checks, 252 lines checked
610ba30a4557 drm/i915: Use Display gen9 for gen9_bc || bxt
a52eae0799cd drm/i915: Expand DISPLAY_GEN macro usage to display related files.
-:604: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#604: FILE: drivers/gpu/drm/i915/intel_display.c:6636:
+ if ((INTEL_DISPLAY_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
-:765: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 'port ==
PORT_E'
#765: FILE: drivers/gpu/drm/i915/intel_display.c:9494:
+ if (INTEL_DISPLAY_GEN(dev_priv) < 9 &&
(port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
-:1094: CHECK:CAMELCASE: Avoid CamelCase:
#1094: FILE: drivers/gpu/drm/i915/intel_display.c:14036:
+ if (IS_DISPLAY_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) &
ILK_eDP_A_DISABLE))
-:1271: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned'
#1271: FILE: drivers/gpu/drm/i915/intel_display.c:15836:
+ unsigned reg = INTEL_DISPLAY_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL :
INTEL_GMCH_CTRL;
-:1946: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around
'intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED'
#1946: FILE: drivers/gpu/drm/i915/intel_psr.c:245:
+ if (INTEL_DISPLAY_GEN(dev_priv) >= 9 &&
(intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
-:2052: WARNING:BRACES: braces {} are not necessary for single statement blocks
#2052: FILE: drivers/gpu/drm/i915/intel_sdvo.c:2454:
+ if (INTEL_DISPLAY_GEN(dev_priv) >= 4 && IS_MOBILE(dev_priv)) {
intel_attach_broadcast_rgb_property(>base.base);
}
total: 0 errors, 2 warnings, 4 checks, 1856 lines checked
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915: Remove CNL from WA 827 (rev3)
== Series Details == Series: series starting with [1/5] drm/i915: Remove CNL from WA 827 (rev3) URL : https://patchwork.freedesktop.org/series/51713/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5052 -> Patchwork_10642 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/51713/revisions/3/mbox/ == Known issues == Here are the changes found in Patchwork_10642 that come from known issues: === IGT changes === Issues hit igt@kms_flip@basic-flip-vs-modeset: fi-skl-6700hq: PASS -> DMESG-WARN (fdo#105998) igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: fi-byt-clapper: PASS -> FAIL (fdo#107362, fdo#103191) Possible fixes igt@drv_module_reload@basic-reload: fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS igt@gem_exec_suspend@basic-s3: fi-icl-u: INCOMPLETE (fdo#107713) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: fi-byt-clapper: FAIL (fdo#107362, fdo#103191) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-b: fi-byt-clapper: FAIL (fdo#107362) -> PASS fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107713 https://bugs.freedesktop.org/show_bug.cgi?id=107713 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 == Participating hosts (49 -> 43) == Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-pnv-d510 == Build changes == * Linux: CI_DRM_5052 -> Patchwork_10642 CI_DRM_5052: 24b6ea5d5f299c5e9e6b4d92068651f7f1555bd0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4699: 1270ec553741ac20c45178d2b26f9a9562ea565f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10642: 30a66566513ae9c51558214ec1b8ac084e05dcab @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 30a66566513a drm/i915: Kill WA 0826 15d0006b4783 drm/i915: Kill WA 0528 fe56270f324f drm/i915: Introduce HAS_NV12 and define WA 0870. 74b6c8c7fca3 drm/i915/cnl: Remove useless CNL A-stepping workarounds. 85b839db56a9 drm/i915: Remove CNL from WA 827 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10642/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/2] drm/i915/gtt: Record the scratch pte
== Series Details == Series: series starting with [CI,1/2] drm/i915/gtt: Record the scratch pte URL : https://patchwork.freedesktop.org/series/51698/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5050_full -> Patchwork_10632_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_10632_full that come from known issues: === IGT changes === Issues hit igt@gem_cpu_reloc@full: shard-skl: NOTRUN -> INCOMPLETE (fdo#108073) igt@gem_exec_schedule@pi-ringfull-bsd: shard-skl: NOTRUN -> FAIL (fdo#103158) igt@kms_busy@extended-modeset-hang-newfb-render-a: shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) igt@kms_busy@extended-modeset-hang-newfb-render-c: shard-skl: PASS -> DMESG-WARN (fdo#107956) igt@kms_color@pipe-c-degamma: shard-apl: PASS -> FAIL (fdo#104782) igt@kms_cursor_crc@cursor-128x42-offscreen: shard-skl: PASS -> FAIL (fdo#103232) igt@kms_cursor_crc@cursor-128x42-onscreen: shard-skl: NOTRUN -> FAIL (fdo#103232) igt@kms_cursor_crc@cursor-256x256-sliding: shard-glk: PASS -> FAIL (fdo#103232) +3 igt@kms_cursor_crc@cursor-256x85-random: shard-apl: PASS -> FAIL (fdo#103232) +1 igt@kms_cursor_legacy@cursorb-vs-flipb-toggle: shard-glk: PASS -> DMESG-WARN (fdo#105763, fdo#106538) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu: shard-skl: PASS -> FAIL (fdo#105682) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt: shard-glk: PASS -> FAIL (fdo#103167) +3 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move: shard-apl: PASS -> FAIL (fdo#103167) igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-blt: shard-skl: PASS -> FAIL (fdo#103167) +1 igt@kms_plane@pixel-format-pipe-a-planes: shard-skl: NOTRUN -> DMESG-FAIL (fdo#106885, fdo#103166) +1 igt@kms_plane_alpha_blend@pipe-b-alpha-basic: shard-skl: NOTRUN -> FAIL (fdo#107815, fdo#108145) +3 igt@kms_plane_alpha_blend@pipe-c-alpha-transparant-fb: shard-skl: NOTRUN -> FAIL (fdo#108145) igt@kms_plane_multiple@atomic-pipe-a-tiling-y: shard-apl: PASS -> FAIL (fdo#103166) igt@kms_plane_multiple@atomic-pipe-b-tiling-yf: shard-skl: NOTRUN -> FAIL (fdo#107815, fdo#103166) +1 igt@kms_setmode@basic: shard-kbl: PASS -> FAIL (fdo#99912) Possible fixes igt@gem_ppgtt@blt-vs-render-ctxn: shard-kbl: INCOMPLETE (fdo#106023, fdo#106887, fdo#103665) -> PASS igt@gem_userptr_blits@unsync-unmap: shard-glk: DMESG-WARN (fdo#105763, fdo#106538) -> PASS +1 igt@kms_ccs@pipe-a-crc-sprite-planes-basic: shard-glk: FAIL (fdo#108145) -> PASS igt@kms_cursor_crc@cursor-256x256-random: shard-glk: FAIL (fdo#103232) -> PASS igt@kms_cursor_crc@cursor-256x85-onscreen: shard-apl: FAIL (fdo#103232) -> PASS +4 igt@kms_draw_crc@draw-method-rgb565-pwrite-ytiled: shard-glk: FAIL (fdo#103184) -> PASS +1 igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: shard-glk: FAIL (fdo#105363) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite: shard-apl: FAIL (fdo#103167) -> PASS +2 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move: shard-glk: FAIL (fdo#103167) -> PASS +1 igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff: shard-glk: DMESG-FAIL (fdo#106538) -> PASS igt@kms_plane@plane-position-covered-pipe-a-planes: shard-apl: FAIL (fdo#103166) -> PASS +2 igt@kms_plane_multiple@atomic-pipe-a-tiling-y: shard-glk: FAIL (fdo#103166) -> PASS +1 igt@kms_setmode@basic: shard-apl: FAIL (fdo#99912) -> PASS igt@perf@polling: shard-hsw: FAIL (fdo#102252) -> PASS fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158 fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103184 https://bugs.freedesktop.org/show_bug.cgi?id=103184 fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#104782 https://bugs.freedesktop.org/show_bug.cgi?id=104782 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105682 https://bugs.freedesktop.org/show_bug.cgi?id=105682 fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763 fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023 fdo#106538
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/5] drm/i915: Remove CNL from WA 827 (rev3)
== Series Details == Series: series starting with [1/5] drm/i915: Remove CNL from WA 827 (rev3) URL : https://patchwork.freedesktop.org/series/51713/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Remove CNL from WA 827 Okay! Commit: drm/i915/cnl: Remove useless CNL A-stepping workarounds. Okay! Commit: drm/i915: Introduce HAS_NV12 and define WA 0870. -drivers/gpu/drm/i915/selftests/../i915_drv.h:3699:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3700:16: warning: expression using sizeof(void) Commit: drm/i915: Kill WA 0528 Okay! Commit: drm/i915: Kill WA 0826 Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/7] drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming
== Series Details == Series: series starting with [CI,1/7] drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming URL : https://patchwork.freedesktop.org/series/51711/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5052 -> Patchwork_10641 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/51711/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10641 that come from known issues: === IGT changes === Issues hit igt@drv_selftest@live_contexts: fi-icl-u: NOTRUN -> DMESG-FAIL (fdo#108569) igt@kms_flip@basic-flip-vs-modeset: fi-skl-6700hq: PASS -> DMESG-WARN (fdo#105998) Possible fixes igt@drv_module_reload@basic-reload: fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS igt@gem_exec_suspend@basic-s3: fi-icl-u: INCOMPLETE (fdo#107713) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: fi-byt-clapper: FAIL (fdo#103191, fdo#107362) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-b: fi-byt-clapper: FAIL (fdo#107362) -> PASS fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107713 https://bugs.freedesktop.org/show_bug.cgi?id=107713 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#108569 https://bugs.freedesktop.org/show_bug.cgi?id=108569 == Participating hosts (49 -> 44) == Missing(5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 == Build changes == * Linux: CI_DRM_5052 -> Patchwork_10641 CI_DRM_5052: 24b6ea5d5f299c5e9e6b4d92068651f7f1555bd0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4699: 1270ec553741ac20c45178d2b26f9a9562ea565f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10641: 230934458b9e879092fe002731280f87a41a80ce @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 230934458b9e drm/dp: Define payload size for DP SDP PPS packet d8e85c672d0d drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported 894c07b4e484 drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC 878ecbe54ad8 drm/dp: DRM DP helper/macros to get DP sink DSC parameters 26faef30ee2e drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init 6e748a91bab8 drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT 4a405ecfcade drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10641/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/7] drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming
== Series Details == Series: series starting with [CI,1/7] drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming URL : https://patchwork.freedesktop.org/series/51558/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5050_full -> Patchwork_10631_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_10631_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10631_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10631_full: === IGT changes === Warnings igt@perf_pmu@rc6: shard-kbl: SKIP -> PASS == Known issues == Here are the changes found in Patchwork_10631_full that come from known issues: === IGT changes === Issues hit igt@drv_suspend@shrink: shard-kbl: PASS -> INCOMPLETE (fdo#106886, fdo#103665) igt@kms_busy@extended-modeset-hang-newfb-render-c: shard-skl: PASS -> DMESG-WARN (fdo#107956) igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c: shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) igt@kms_cursor_crc@cursor-256x85-offscreen: shard-skl: NOTRUN -> FAIL (fdo#103232) igt@kms_cursor_crc@cursor-256x85-random: shard-apl: PASS -> FAIL (fdo#103232) +2 igt@kms_cursor_legacy@cursorb-vs-flipb-toggle: shard-glk: PASS -> DMESG-WARN (fdo#106538, fdo#105763) igt@kms_flip@2x-flip-vs-wf_vblank-interruptible: shard-glk: PASS -> INCOMPLETE (k.org#198133, fdo#103359) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt: shard-apl: PASS -> FAIL (fdo#103167) +1 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc: shard-skl: NOTRUN -> FAIL (fdo#103167) igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen: shard-glk: PASS -> FAIL (fdo#103167) igt@kms_panel_fitting@legacy: shard-skl: NOTRUN -> FAIL (fdo#105456) igt@kms_plane@pixel-format-pipe-a-planes: shard-skl: NOTRUN -> DMESG-FAIL (fdo#103166, fdo#106885) +1 igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: shard-skl: NOTRUN -> FAIL (fdo#107815) igt@kms_plane_alpha_blend@pipe-c-alpha-7efc: shard-skl: NOTRUN -> FAIL (fdo#107815, fdo#108145) +1 igt@kms_plane_alpha_blend@pipe-c-alpha-transparant-fb: shard-skl: NOTRUN -> FAIL (fdo#108145) +2 igt@kms_plane_multiple@atomic-pipe-c-tiling-yf: shard-skl: NOTRUN -> FAIL (fdo#103166, fdo#107815) igt@kms_setmode@basic: shard-kbl: PASS -> FAIL (fdo#99912) Possible fixes igt@gem_ppgtt@blt-vs-render-ctxn: shard-kbl: INCOMPLETE (fdo#106887, fdo#106023, fdo#103665) -> PASS igt@gem_userptr_blits@unsync-unmap: shard-glk: DMESG-WARN (fdo#106538, fdo#105763) -> PASS +1 igt@kms_busy@extended-pageflip-hang-newfb-render-b: shard-glk: DMESG-WARN (fdo#107956) -> PASS igt@kms_cursor_crc@cursor-256x85-onscreen: shard-apl: FAIL (fdo#103232) -> PASS +3 igt@kms_draw_crc@draw-method-rgb565-pwrite-ytiled: shard-glk: FAIL (fdo#103184) -> PASS +1 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite: shard-apl: FAIL (fdo#103167) -> PASS igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff: shard-glk: DMESG-FAIL (fdo#106538) -> PASS igt@kms_plane@plane-position-covered-pipe-a-planes: shard-apl: FAIL (fdo#103166) -> PASS +1 igt@perf@polling: shard-hsw: FAIL (fdo#102252) -> PASS igt@pm_rpm@system-suspend-devices: shard-skl: INCOMPLETE (fdo#107807) -> PASS fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103184 https://bugs.freedesktop.org/show_bug.cgi?id=103184 fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#105456 https://bugs.freedesktop.org/show_bug.cgi?id=105456 fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763 fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023 fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538 fdo#106885 https://bugs.freedesktop.org/show_bug.cgi?id=106885 fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886 fdo#106887 https://bugs.freedesktop.org/show_bug.cgi?id=106887
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/fia: FIA registers offset implementation. (rev2)
== Series Details == Series: drm/i915/fia: FIA registers offset implementation. (rev2) URL : https://patchwork.freedesktop.org/series/51566/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_5052 -> Patchwork_10640 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10640 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10640, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/51566/revisions/2/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10640: === IGT changes === Possible regressions igt@drv_selftest@live_requests: fi-icl-u: NOTRUN -> INCOMPLETE == Known issues == Here are the changes found in Patchwork_10640 that come from known issues: === IGT changes === Issues hit igt@kms_flip@basic-flip-vs-modeset: fi-skl-6700hq: PASS -> DMESG-WARN (fdo#105998) igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: PASS -> DMESG-WARN (fdo#102614) Possible fixes igt@gem_exec_suspend@basic-s3: fi-icl-u: INCOMPLETE (fdo#107713) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: fi-byt-clapper: FAIL (fdo#107362, fdo#103191) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-b: fi-byt-clapper: FAIL (fdo#107362) -> PASS fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107713 https://bugs.freedesktop.org/show_bug.cgi?id=107713 == Participating hosts (49 -> 44) == Missing(5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 == Build changes == * Linux: CI_DRM_5052 -> Patchwork_10640 CI_DRM_5052: 24b6ea5d5f299c5e9e6b4d92068651f7f1555bd0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4699: 1270ec553741ac20c45178d2b26f9a9562ea565f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10640: 45d8bcb2c70420a81d0b4bb3d6c20fef33bf9ee2 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 45d8bcb2c704 drm/i915/fia: FIA registers offset implementation. == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10640/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC 4/4] drm/i915: Expand DISPLAY_GEN macro usage to display related files.
Let's prefer DISPLAY_GEN over GEN check on Display related files.
On this first step let's just convert using coccinelle and later
we adjust the gray areas and work to minimize the existent mix
of GEN and platform checks.
spatch -sp_file display_gen.cocci intel_atomic*.c intel_audio.c \
intel_cdclk.c intel_color.c intel_connector.c intel_crt.c \
intel_csr.c intel_ddi.c intel_display.{c,h} intel_dp*{c,h} \
*dsi*{c,h} intel_dvo.c intel_fbc.c intel_fifo_underrun.c \
intel_frontbuffer.{c,h} intel_hdcp.c intel_hdmi.c \
intel_hotplug.c intel_i2c.c intel_lpe_audio.c intel_lspcon.c \
intel_lvds.c intel_overlay.c intel_panel.c intel_psr.c \
intel_sdvo.c intel_sprite.c intel_tv.c --in-place
where display_gen.cocci:
@@ expression e1, e2; @@
-INTEL_GEN(e1) >= e2
+INTEL_DISPLAY_GEN(e1) >= e2
@@ expression e1, e2; @@
-INTEL_GEN(e1) > e2
+INTEL_DISPLAY_GEN(e1) > e2
@@ expression e1, e2; @@
-INTEL_GEN(e1) <= e2
+INTEL_DISPLAY_GEN(e1) <= e2
@@ expression e1, e2; @@
-INTEL_GEN(e1) < e2
+INTEL_DISPLAY_GEN(e1) < e2
@gen3@ expression e; @@
-IS_GEN3(e)
+IS_DISPLAY_GEN3(e)
@gen4@ expression e; @@
-IS_GEN4(e)
+IS_DISPLAY_GEN4(e)
@gen5@ expression e; @@
-IS_GEN5(e)
+IS_DISPLAY_GEN5(e)
@gen6@ expression e; @@
-IS_GEN6(e)
+IS_DISPLAY_GEN6(e)
@gen7@ expression e; @@
-IS_GEN7(e)
+IS_DISPLAY_GEN7(e)
@gen8@ expression e; @@
-IS_GEN8(e)
+IS_DISPLAY_GEN8(e)
@gen9@ expression e; @@
-IS_GEN9(e)
+IS_DISPLAY_GEN9(e)
@gen10@ expression e; @@
-IS_GEN10(e)
+IS_DISPLAY_GEN10(e)
@gen11@ expression e; @@
-IS_GEN11(e)
+IS_DISPLAY_GEN11(e)
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_audio.c | 4 +-
drivers/gpu/drm/i915/intel_cdclk.c | 14 +-
drivers/gpu/drm/i915/intel_color.c | 4 +-
drivers/gpu/drm/i915/intel_crt.c | 8 +-
drivers/gpu/drm/i915/intel_ddi.c | 16 +-
drivers/gpu/drm/i915/intel_display.c | 242 ++---
drivers/gpu/drm/i915/intel_dp.c| 48 ++--
drivers/gpu/drm/i915/intel_dpll_mgr.c | 6 +-
drivers/gpu/drm/i915/intel_fbc.c | 38 ++--
drivers/gpu/drm/i915/intel_fifo_underrun.c | 8 +-
drivers/gpu/drm/i915/intel_hdcp.c | 2 +-
drivers/gpu/drm/i915/intel_hdmi.c | 8 +-
drivers/gpu/drm/i915/intel_i2c.c | 2 +-
drivers/gpu/drm/i915/intel_lvds.c | 14 +-
drivers/gpu/drm/i915/intel_overlay.c | 4 +-
drivers/gpu/drm/i915/intel_panel.c | 14 +-
drivers/gpu/drm/i915/intel_psr.c | 20 +-
drivers/gpu/drm/i915/intel_sdvo.c | 14 +-
drivers/gpu/drm/i915/intel_sprite.c| 28 +--
drivers/gpu/drm/i915/intel_tv.c| 2 +-
20 files changed, 248 insertions(+), 248 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_audio.c
b/drivers/gpu/drm/i915/intel_audio.c
index ccd88da20a14..0407089c4ccd 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -733,7 +733,7 @@ void intel_init_audio_hooks(struct drm_i915_private
*dev_priv)
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
- } else if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8) {
+ } else if (IS_HASWELL(dev_priv) || INTEL_DISPLAY_GEN(dev_priv) >= 8) {
dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
} else if (HAS_PCH_SPLIT(dev_priv)) {
@@ -758,7 +758,7 @@ static void i915_audio_component_codec_wake_override(struct
device *kdev,
struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
u32 tmp;
- if (!IS_GEN9(dev_priv))
+ if (!IS_DISPLAY_GEN9(dev_priv))
return;
i915_audio_component_get_power(kdev);
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
b/drivers/gpu/drm/i915/intel_cdclk.c
index 093f75dc0aee..d32faf7feb23 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -2140,7 +2140,7 @@ static int intel_pixel_rate_to_cdclk(struct
drm_i915_private *dev_priv,
{
if (INTEL_DISPLAY_GEN(dev_priv) >= 10)
return DIV_ROUND_UP(pixel_rate, 2);
- else if (IS_GEN9(dev_priv) ||
+ else if (IS_DISPLAY_GEN9(dev_priv) ||
IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
return pixel_rate;
else if (IS_CHERRYVIEW(dev_priv))
@@ -2176,7 +2176,7 @@ int intel_crtc_compute_min_cdclk(const struct
intel_crtc_state *crtc_state)
if (IS_DISPLAY_GEN10(dev_priv)) {
/* Display WA #1145: glk,cnl */
min_cdclk = max(316800, min_cdclk);
- } else if (IS_GEN9(dev_priv) || IS_BROADWELL(dev_priv)) {
+ } else if (IS_DISPLAY_GEN9(dev_priv) || IS_BROADWELL(dev_priv))
{
/* Display WA
[Intel-gfx] [RFC 3/4] drm/i915: Use Display gen9 for gen9_bc || bxt
Now that GLK is properly defined as gen10 display
we can use gen9 display to identify this case here
Cc: Jani Nikula
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_color.c | 3 +--
drivers/gpu/drm/i915/intel_pm.c| 5 +
2 files changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 7b25bcede388..70aaf915245c 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -655,8 +655,7 @@ void intel_color_init(struct drm_crtc *crtc)
} else if (IS_HASWELL(dev_priv)) {
dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
dev_priv->display.load_luts = haswell_load_luts;
- } else if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv) ||
- IS_BROXTON(dev_priv)) {
+ } else if (IS_BROADWELL(dev_priv) || IS_DISPLAY_GEN9(dev_priv)) {
dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
dev_priv->display.load_luts = broadwell_load_luts;
} else if (IS_DISPLAY_GEN10(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 23d01d781e7f..a6aaf3b75c73 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3602,10 +3602,7 @@ static bool skl_needs_memory_bw_wa(struct
intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv))
- return true;
-
- return false;
+ return IS_DISPLAY_GEN9(dev_priv);
}
static bool
--
2.19.1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC 2/4] drm/i915: Finally recognize Geminilake as Gen10 Display
Now that we have INTEL_DISPLAY_GEN checks in place we
can recognize Geminilake as Gen 10 display instead of
individual platform checks mixed with gen ones.
Cc: Lucas De Marchi
Cc: Jani Nikula
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_drv.h | 3 +--
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/intel_atomic.c | 5 ++---
drivers/gpu/drm/i915/intel_bios.c| 3 +--
drivers/gpu/drm/i915/intel_cdclk.c | 6 +++---
drivers/gpu/drm/i915/intel_color.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 13 ++---
drivers/gpu/drm/i915/intel_fbc.c | 4 ++--
drivers/gpu/drm/i915/intel_hdmi.c| 7 +++
drivers/gpu/drm/i915/intel_pm.c | 8 +++-
drivers/gpu/drm/i915/intel_psr.c | 6 +++---
drivers/gpu/drm/i915/intel_sprite.c | 8
13 files changed, 31 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3242229688e3..6c051388652f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2624,8 +2624,7 @@ intel_info(const struct drm_i915_private *dev_priv)
IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
#define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
-#define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
- IS_GEMINILAKE(dev_priv) || \
+#define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_DISPLAY_GEN(dev_priv) >= 10 || \
IS_KABYLAKE(dev_priv))
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index fb8caf846c02..d298418cccf4 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -538,6 +538,7 @@ static const struct intel_device_info intel_broxton_info = {
static const struct intel_device_info intel_geminilake_info = {
GEN9_LP_FEATURES,
+ DISPLAY_GEN(10),
PLATFORM(INTEL_GEMINILAKE),
.ddb_size = 1024,
GLK_COLORS,
diff --git a/drivers/gpu/drm/i915/intel_atomic.c
b/drivers/gpu/drm/i915/intel_atomic.c
index a5a2c8fe58a7..c631545fc315 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -232,8 +232,7 @@ static void intel_atomic_setup_scaler(struct
intel_crtc_scaler_state *scaler_sta
if (plane_state && plane_state->base.fb &&
plane_state->base.fb->format->is_yuv &&
plane_state->base.fb->format->num_planes > 1) {
- if (IS_GEN9(dev_priv) &&
- !IS_GEMINILAKE(dev_priv)) {
+ if (IS_DISPLAY_GEN9(dev_priv)) {
mode = SKL_PS_SCALER_MODE_NV12;
} else if
(icl_is_hdr_plane(to_intel_plane(plane_state->base.plane))) {
/*
@@ -248,7 +247,7 @@ static void intel_atomic_setup_scaler(struct
intel_crtc_scaler_state *scaler_sta
if (plane_state->linked_plane)
mode |=
PS_PLANE_Y_SEL(plane_state->linked_plane->id);
}
- } else if (INTEL_GEN(dev_priv) > 9 || IS_GEMINILAKE(dev_priv)) {
+ } else if (INTEL_DISPLAY_GEN(dev_priv) >= 10) {
mode = PS_SCALER_MODE_NORMAL;
} else if (num_scalers_need == 1 && intel_crtc->num_scalers > 1) {
/*
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index 1faa494e2bc9..59301aa7dd14 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -711,8 +711,7 @@ parse_psr(struct drm_i915_private *dev_priv, const struct
bdb_header *bdb)
* Old decimal value is wake up time in multiples of 100 us.
*/
if (bdb->version >= 205 &&
- (IS_GEN9_BC(dev_priv) || IS_GEMINILAKE(dev_priv) ||
-INTEL_GEN(dev_priv) >= 10)) {
+ (IS_GEN9_BC(dev_priv) || INTEL_DISPLAY_GEN(dev_priv) >= 10)) {
switch (psr_table->tp1_wakeup_time) {
case 0:
dev_priv->vbt.psr.tp1_wakeup_time_us = 500;
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
b/drivers/gpu/drm/i915/intel_cdclk.c
index 8d74276029e6..093f75dc0aee 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -2138,7 +2138,7 @@ void intel_set_cdclk(struct drm_i915_private *dev_priv,
static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv,
int pixel_rate)
{
- if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (INTEL_DISPLAY_GEN(dev_priv) >= 10)
return DIV_ROUND_UP(pixel_rate, 2);
else if (IS_GEN9(dev_priv) ||
IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
@@ -2173,7 +2173,7 @@ int
[Intel-gfx] [RFC 1/4] drm/i915: Add Display Gen info.
Introduce Display Gen. The goal is to use this to minimize
the amount of platform codename checks we have nowdays on
display code.
The introduction of a new platform should be just
gen >= current.
Just a gen++ without exposing any new feature or ip.
so this would minimize the amount of patches needed
for a bring-up specially holding them on internal branches.
Cc: Jani Nikula
Cc: Lucas De Marchi
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_drv.h | 28 ++--
drivers/gpu/drm/i915/i915_pci.c | 5 -
drivers/gpu/drm/i915/intel_device_info.h | 2 ++
3 files changed, 32 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c9e5bab6861b..3242229688e3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2349,8 +2349,9 @@ intel_info(const struct drm_i915_private *dev_priv)
#define INTEL_INFO(dev_priv) intel_info((dev_priv))
#define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
-#define INTEL_GEN(dev_priv)((dev_priv)->info.gen)
-#define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
+#define INTEL_GEN(dev_priv)((dev_priv)->info.gen)
+#define INTEL_DISPLAY_GEN(dev_priv)((dev_priv)->info.display_gen)
+#define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
#define REVID_FOREVER 0xff
#define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
@@ -2363,6 +2364,8 @@ intel_info(const struct drm_i915_private *dev_priv)
/* Returns true if Gen is in inclusive range [Start, End] */
#define IS_GEN(dev_priv, s, e) \
(!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e
+#define IS_DISPLAY_GEN(dev_priv, s, e) \
+ (!!((dev_priv)->info.display_gen_mask & INTEL_GEN_MASK((s), (e
/*
* Return true if revision is in range [since,until] inclusive.
@@ -2532,6 +2535,27 @@ intel_info(const struct drm_i915_private *dev_priv)
#define IS_GEN10(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(9)))
#define IS_GEN11(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(10)))
+#define IS_DISPLAY_GEN2(dev_priv) (!!((dev_priv)->info.display_gen_mask \
+ & BIT(2)))
+#define IS_DISPLAY_GEN3(dev_priv) (!!((dev_priv)->info.display_gen_mask \
+ & BIT(3)))
+#define IS_DISPLAY_GEN4(dev_priv) (!!((dev_priv)->info.display_gen_mask \
+ & BIT(4)))
+#define IS_DISPLAY_GEN5(dev_priv) (!!((dev_priv)->info.display_gen_mask \
+ & BIT(5)))
+#define IS_DISPLAY_GEN6(dev_priv) (!!((dev_priv)->info.display_gen_mask \
+ & BIT(6)))
+#define IS_DISPLAY_GEN7(dev_priv) (!!((dev_priv)->info.display_gen_mask \
+ & BIT(7)))
+#define IS_DISPLAY_GEN8(dev_priv) (!!((dev_priv)->info.display_gen_mask \
+ & BIT(8)))
+#define IS_DISPLAY_GEN9(dev_priv) (!!((dev_priv)->info.display_gen_mask \
+ & BIT(9)))
+#define IS_DISPLAY_GEN10(dev_priv) (!!((dev_priv)->info.display_gen_mask \
+ & BIT(10)))
+#define IS_DISPLAY_GEN11(dev_priv) (!!((dev_priv)->info.display_gen_mask \
+ & BIT(11)))
+
#define IS_LP(dev_priv)(INTEL_INFO(dev_priv)->is_lp)
#define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv))
#define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 44e745921ac1..fb8caf846c02 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -30,7 +30,10 @@
#include "i915_selftest.h"
#define PLATFORM(x) .platform = (x), .platform_mask = BIT(x)
-#define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
+#define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1), \
+ .display_gen = (x), .display_gen_mask = BIT((x))
+/* Unless explicitly stated otherwise Display gen inherits platform gen */
+#define DISPLAY_GEN(x) .display_gen = (x), .display_gen_mask = BIT((x))
#define GEN_DEFAULT_PIPEOFFSETS \
.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index b4c2c4eae78b..9f31f29186a8 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -151,8 +151,10 @@ typedef u8 intel_ring_mask_t;
struct intel_device_info {
u16 device_id;
u16 gen_mask;
+ u16 display_gen_mask;
u8 gen;
+ u8 display_gen;
u8 gt; /* GT number, 0 if undefined */
u8 num_rings;
intel_ring_mask_t ring_mask; /* Rings supported by the HW */
--
2.19.1
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915: Remove CNL from WA 827
== Series Details == Series: series starting with [1/5] drm/i915: Remove CNL from WA 827 URL : https://patchwork.freedesktop.org/series/51713/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5052 -> Patchwork_10639 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/51713/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10639 that come from known issues: === IGT changes === Issues hit igt@drv_selftest@live_contexts: fi-icl-u: NOTRUN -> DMESG-FAIL (fdo#108569) igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b: fi-byt-clapper: PASS -> FAIL (fdo#107362) Possible fixes igt@drv_module_reload@basic-reload: fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS igt@gem_exec_suspend@basic-s3: fi-icl-u: INCOMPLETE (fdo#107713) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: fi-byt-clapper: FAIL (fdo#107362, fdo#103191) -> PASS fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107713 https://bugs.freedesktop.org/show_bug.cgi?id=107713 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#108569 https://bugs.freedesktop.org/show_bug.cgi?id=108569 == Participating hosts (49 -> 42) == Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-apl-guc fi-ctg-p8600 fi-glk-j4005 == Build changes == * Linux: CI_DRM_5052 -> Patchwork_10639 CI_DRM_5052: 24b6ea5d5f299c5e9e6b4d92068651f7f1555bd0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4699: 1270ec553741ac20c45178d2b26f9a9562ea565f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10639: a6b96e81cb3d3d642a32967d090d6cbc067dca7a @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == a6b96e81cb3d drm/i915: Kill WA 0826 9c1684e0212b drm/i915: Kill WA 0528 cb2ab46ffd52 drm/i915: Introduce HAS_NV12 and define WA 0870. 06e251358bb0 drm/i915/cnl: Remove useless CNL A-stepping workarounds. 06502866f130 drm/i915: Remove CNL from WA 827 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10639/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Kill WA 0826
According to BSpec this is not needed anymore:
"This workaround is no longer needed since NV12
support is dropped for the affected projects.
"
v2: Rebase
Cc: Clinton Taylor
Cc: Maarten Lankhorst
Cc: Ville Syrjälä
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_pm.c | 10 --
1 file changed, 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e1b712a43162..f202b9b3b796 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4823,16 +4823,6 @@ static int skl_compute_plane_wm(const struct
drm_i915_private *dev_priv,
}
}
- /*
-* Display WA #826 (SKL:ALL, BXT:ALL)
-* disable wm level 1-7 on NV12 planes
-*/
- if (wp->is_planar && level >= 1 &&
- (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))) {
- result->plane_en = false;
- return 0;
- }
-
/* The number of lines are ignored for the level 0 watermark. */
result->plane_res_b = res_blocks;
result->plane_res_l = res_lines;
--
2.19.1
___
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/5] drm/i915: Remove CNL from WA 827
== Series Details == Series: series starting with [1/5] drm/i915: Remove CNL from WA 827 URL : https://patchwork.freedesktop.org/series/51713/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Remove CNL from WA 827 Okay! Commit: drm/i915/cnl: Remove useless CNL A-stepping workarounds. -drivers/gpu/drm/i915/i915_drv.h:172:19: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_drv.h:172:19: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_drv.h:172:19: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_drv.h:172:19: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_drv.h:181:19: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_drv.h:181:19: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_drv.h:181:19: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_drv.h:181:19: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_drv.h:181:19: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_drv.h:181:19: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_drv.h:181:19: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_drv.h:181:19: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_drv.h:181:19: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_drv.h:181:19: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_drv.h:181:19: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_drv.h:181:19: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:1145:22: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:1145:22: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:1153:16: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:1179:17: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:1431:25: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:1431:25: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:1438:34: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:1438:34: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:1440:35: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:1440:35: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:1442:32: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:1442:32: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:1445:36: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:1445:36: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:1447:37: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:1447:37: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:1449:34: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:1449:34: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:1636:16: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:1711:31: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:1711:31: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:1914:45: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:1914:45: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:1914:45: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:1914:45: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:1914:45: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:1914:45: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:1914:45: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:1914:45: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:1914:45: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:1914:45: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:1914:45: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:1914:45: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:1914:45: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:1914:45: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:2055:36: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:2055:36: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:2064:33: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:2064:33: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:2068:49: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:2068:49: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:2070:50: warning:
[Intel-gfx] [PATCH] drm/i915/cnl: Remove useless CNL A-stepping workarounds.
These were always useless since CNL A stepping needed many
more workarounds that were never introduced and also
we started Linux work on CNL B stepping anyways.
v2: Clinton noticed this isolated patch outside of series
wasn't compiling due to missing brackets.
Cc: Clinton Taylor
Cc: Paulo Zanoni
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_pm.c| 10 ++
drivers/gpu/drm/i915/intel_wopcm.c | 3 +--
2 files changed, 3 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 82c82e233154..e1b712a43162 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4824,12 +4824,11 @@ static int skl_compute_plane_wm(const struct
drm_i915_private *dev_priv,
}
/*
-* Display WA #826 (SKL:ALL, BXT:ALL) & #1059 (CNL:A)
+* Display WA #826 (SKL:ALL, BXT:ALL)
* disable wm level 1-7 on NV12 planes
*/
if (wp->is_planar && level >= 1 &&
- (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
-IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))) {
+ (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))) {
result->plane_en = false;
return 0;
}
@@ -4953,11 +4952,6 @@ static void skl_compute_transition_wm(const struct
intel_crtc_state *cstate,
trans_offset_b;
} else {
res_blocks = wm0_sel_res_b + trans_offset_b;
-
- /* WA BUG:1938466 add one block for non y-tile planes */
- if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))
- res_blocks += 1;
-
}
res_blocks += 1;
diff --git a/drivers/gpu/drm/i915/intel_wopcm.c
b/drivers/gpu/drm/i915/intel_wopcm.c
index 92cb82dd0c07..b8ee8669c260 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_wopcm.c
@@ -133,8 +133,7 @@ static inline int check_hw_restriction(struct
drm_i915_private *i915,
if (IS_GEN9(i915))
err = gen9_check_dword_gap(guc_wopcm_base, guc_wopcm_size);
- if (!err &&
- (IS_GEN9(i915) || IS_CNL_REVID(i915, CNL_REVID_A0, CNL_REVID_A0)))
+ if (!err && IS_GEN9(i915))
err = gen9_check_huc_fw_fits(guc_wopcm_size, huc_fw_size);
return err;
--
2.19.1
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/icl: Enable DC9 as lowest possible state during screen-off (rev6)
== Series Details == Series: drm/i915/icl: Enable DC9 as lowest possible state during screen-off (rev6) URL : https://patchwork.freedesktop.org/series/49447/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5052 -> Patchwork_10638 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/49447/revisions/6/mbox/ == Known issues == Here are the changes found in Patchwork_10638 that come from known issues: === IGT changes === Issues hit igt@drv_selftest@live_contexts: fi-icl-u: NOTRUN -> DMESG-FAIL (fdo#108569) igt@kms_flip@basic-flip-vs-modeset: fi-skl-6700hq: PASS -> DMESG-WARN (fdo#105998) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-byt-clapper: PASS -> FAIL (fdo#103191, fdo#107362) +1 Possible fixes igt@drv_module_reload@basic-reload: fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS igt@gem_exec_suspend@basic-s3: fi-icl-u: INCOMPLETE (fdo#107713) -> PASS igt@kms_flip@basic-flip-vs-dpms: fi-skl-6700hq: DMESG-WARN (fdo#105998) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: fi-byt-clapper: FAIL (fdo#103191, fdo#107362) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-b: fi-byt-clapper: FAIL (fdo#107362) -> PASS fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107713 https://bugs.freedesktop.org/show_bug.cgi?id=107713 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#108569 https://bugs.freedesktop.org/show_bug.cgi?id=108569 == Participating hosts (49 -> 44) == Missing(5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 == Build changes == * Linux: CI_DRM_5052 -> Patchwork_10638 CI_DRM_5052: 24b6ea5d5f299c5e9e6b4d92068651f7f1555bd0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4699: 1270ec553741ac20c45178d2b26f9a9562ea565f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10638: 400a4e829380666942c2193967b231dd0b9275b1 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 400a4e829380 drm/i915/icl: Enable DC9 as lowest possible state during screen-off == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10638/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/5] drm/i915: Remove CNL from WA 827
On 10/29/2018 04:00 PM, Rodrigo Vivi wrote: CNL A stepping was the only affected there. But also it is time to clean old pre-production CNL Workarounds, so let's just remove and clean this W/A. Cc: Maarten Lankhorst Cc: Ville Syrjälä Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_display.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index c3cadc09f859..dd88ffe9e273 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5242,8 +5242,8 @@ static bool needs_nv12_wa(struct drm_i915_private *dev_priv, if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv)) return false; - if ((IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) || - IS_CANNONLAKE(dev_priv)) + /* WA Display #0827: Gen9:all */ + if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) return true; return false; Looks good. Reviewed-by: Clint Taylor ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/fia: FIA registers offset implementation.
On Mon, Oct 29, 2018 at 04:23:15PM -0700, Anusha Srivatsa wrote:
> The registers DPCSSS,DPSP,DPMLE1 and DPPMS are all at an offset
> from the base - which is the FLexi IO Adaptor. Lets follow the
> offset calculation while accessing these registers.
>
> v2:
> - Follow spec for numbering - s/0/1(Lucas)
> - s/FIA_1/FIA1_BASE (Anusha)
>
> Cc: Lucas De Marchi
> Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
thanks
Lucas De Marchi
> ---
> drivers/gpu/drm/i915/i915_reg.h | 15 +++
> 1 file changed, 11 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index bcee91bcfba6..dd74bc01c64e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2057,8 +2057,15 @@ enum i915_power_well_id {
> #define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy),
> _PORT_CL2CM_DW6_BC)
> #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
>
> +/* FIA Offsets */
> +#define FIA1_BASE0x163000
> +#define PORT_TX_DFLEXDPMLE1_OFFSET 0x008C0
> +#define PORT_TX_DFLEXDPPMS_OFFSET0x00890
> +#define PORT_TX_DFLEXDPCSSS_OFFSET 0x00894
> +#define PORT_TX_DFLEXDPSP_OFFSET 0x008A0
> +
> /* ICL PHY DFLEX registers */
> -#define PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0)
> +#define PORT_TX_DFLEXDPMLE1 _MMIO(FIA1_BASE +
> PORT_TX_DFLEXDPMLE1_OFFSET)
> #define DFLEXDPMLE1_DPMLETC_MASK(n)(0xf << (4 * (n)))
> #define DFLEXDPMLE1_DPMLETC(n, x) ((x) << (4 * (n)))
>
> @@ -10988,17 +10995,17 @@ enum skl_power_gate {
>
> _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
>
> _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
>
> -#define PORT_TX_DFLEXDPSP_MMIO(0x1638A0)
> +#define PORT_TX_DFLEXDPSP_MMIO(FIA1_BASE +
> PORT_TX_DFLEXDPSP_OFFSET)
> #define TC_LIVE_STATE_TBT(tc_port) (1 << ((tc_port) * 8 + 6))
> #define TC_LIVE_STATE_TC(tc_port) (1 << ((tc_port) * 8 + 5))
> #define DP_LANE_ASSIGNMENT_SHIFT(tc_port) ((tc_port) * 8)
> #define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8))
> #define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8))
>
> -#define PORT_TX_DFLEXDPPMS _MMIO(0x163890)
> +#define PORT_TX_DFLEXDPPMS _MMIO(FIA1_BASE +
> PORT_TX_DFLEXDPPMS_OFFSET)
> #define DP_PHY_MODE_STATUS_COMPLETED(tc_port) (1 << (tc_port))
>
> -#define PORT_TX_DFLEXDPCSSS _MMIO(0x163894)
> +#define PORT_TX_DFLEXDPCSSS _MMIO(FIA1_BASE +
> PORT_TX_DFLEXDPCSSS_OFFSET)
> #define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))
>
> #endif /* _I915_REG_H_ */
> --
> 2.17.1
>
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/7] drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming
== Series Details == Series: series starting with [CI,1/7] drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming URL : https://patchwork.freedesktop.org/series/51711/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_5052 -> Patchwork_10637 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10637 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10637, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/51711/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10637: === IGT changes === Possible regressions igt@drv_selftest@live_contexts: fi-bsw-n3050: PASS -> DMESG-FAIL == Known issues == Here are the changes found in Patchwork_10637 that come from known issues: === IGT changes === Issues hit igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-byt-clapper: PASS -> FAIL (fdo#107362, fdo#103191) fi-icl-u: NOTRUN -> INCOMPLETE (fdo#107713) igt@pm_rpm@basic-pci-d3-state: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106097) Possible fixes igt@drv_module_reload@basic-reload: fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS igt@gem_exec_suspend@basic-s3: fi-icl-u: INCOMPLETE (fdo#107713) -> PASS igt@kms_flip@basic-flip-vs-dpms: fi-skl-6700hq: DMESG-WARN (fdo#105998) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: fi-byt-clapper: FAIL (fdo#107362, fdo#103191) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-b: fi-byt-clapper: FAIL (fdo#107362) -> PASS fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998 fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107713 https://bugs.freedesktop.org/show_bug.cgi?id=107713 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 == Participating hosts (49 -> 44) == Missing(5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 == Build changes == * Linux: CI_DRM_5052 -> Patchwork_10637 CI_DRM_5052: 24b6ea5d5f299c5e9e6b4d92068651f7f1555bd0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4699: 1270ec553741ac20c45178d2b26f9a9562ea565f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10637: d7bcf254d5781c291e4db7a7b0269241943c07c8 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == d7bcf254d578 drm/dp: Define payload size for DP SDP PPS packet 4760c751a865 drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported 03afa383a0c4 drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC f33cb1e31640 drm/dp: DRM DP helper/macros to get DP sink DSC parameters 8af94d076e1c drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init a96d367cf933 drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT 40a5992273a1 drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10637/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/fia: FIA registers offset implementation.
The registers DPCSSS,DPSP,DPMLE1 and DPPMS are all at an offset
from the base - which is the FLexi IO Adaptor. Lets follow the
offset calculation while accessing these registers.
v2:
- Follow spec for numbering - s/0/1(Lucas)
- s/FIA_1/FIA1_BASE (Anusha)
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_reg.h | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bcee91bcfba6..dd74bc01c64e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2057,8 +2057,15 @@ enum i915_power_well_id {
#define BXT_PORT_CL2CM_DW6(phy)_BXT_PHY((phy),
_PORT_CL2CM_DW6_BC)
#define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
+/* FIA Offsets */
+#define FIA1_BASE 0x163000
+#define PORT_TX_DFLEXDPMLE1_OFFSET 0x008C0
+#define PORT_TX_DFLEXDPPMS_OFFSET 0x00890
+#define PORT_TX_DFLEXDPCSSS_OFFSET 0x00894
+#define PORT_TX_DFLEXDPSP_OFFSET 0x008A0
+
/* ICL PHY DFLEX registers */
-#define PORT_TX_DFLEXDPMLE1_MMIO(0x1638C0)
+#define PORT_TX_DFLEXDPMLE1_MMIO(FIA1_BASE +
PORT_TX_DFLEXDPMLE1_OFFSET)
#define DFLEXDPMLE1_DPMLETC_MASK(n) (0xf << (4 * (n)))
#define DFLEXDPMLE1_DPMLETC(n, x)((x) << (4 * (n)))
@@ -10988,17 +10995,17 @@ enum skl_power_gate {
_ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
_ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
-#define PORT_TX_DFLEXDPSP _MMIO(0x1638A0)
+#define PORT_TX_DFLEXDPSP _MMIO(FIA1_BASE +
PORT_TX_DFLEXDPSP_OFFSET)
#define TC_LIVE_STATE_TBT(tc_port) (1 << ((tc_port) * 8 + 6))
#define TC_LIVE_STATE_TC(tc_port)(1 << ((tc_port) * 8 + 5))
#define DP_LANE_ASSIGNMENT_SHIFT(tc_port)((tc_port) * 8)
#define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8))
#define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8))
-#define PORT_TX_DFLEXDPPMS _MMIO(0x163890)
+#define PORT_TX_DFLEXDPPMS _MMIO(FIA1_BASE +
PORT_TX_DFLEXDPPMS_OFFSET)
#define DP_PHY_MODE_STATUS_COMPLETED(tc_port)(1 << (tc_port))
-#define PORT_TX_DFLEXDPCSSS_MMIO(0x163894)
+#define PORT_TX_DFLEXDPCSSS_MMIO(FIA1_BASE +
PORT_TX_DFLEXDPCSSS_OFFSET)
#define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))
#endif /* _I915_REG_H_ */
--
2.17.1
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Re: [Intel-gfx] [v5 2/2] drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion
On Fri, Oct 26, 2018 at 03:31:57PM +0530, Uma Shankar wrote:
> Plane input CSC needs to be enabled to convert frambuffers from
> YUV to RGB. This is needed for bottom 3 planes on ICL, rest of
> the planes have hardcoded conversion and taken care by the legacy
> code.
>
> This patch defines the co-efficient values for YUV to RGB conversion
> in BT709 and BT601 formats. It programs the coefficients and enables
> the plane input csc unit in hardware.
>
> Note: This is currently untested and floated to get an early feedback
> on the design and implementation for this feature. In parallel,
> I will test this on actual ICL hardware and confirm with planar
> formats.
>
> v2: Addressed Maarten's and Ville's review comments and added the
> coefficients in a 2D array instead of independent Macros.
>
> v3: Added individual coefficient matrix (9 values) instead of 6
> register values as per Maarten's comment. Also addresed a shift
> issue with B channel coefficient.
>
> v4: Added support for Limited Range Color Handling
>
> v5: Fixed Matt and Maarten's review comments.
>
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/drm/i915/intel_color.c | 79
>
> drivers/gpu/drm/i915/intel_display.c | 23 ---
> drivers/gpu/drm/i915/intel_drv.h | 2 +
> 3 files changed, 98 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_color.c
> b/drivers/gpu/drm/i915/intel_color.c
> index 5127da2..681cd13 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -57,6 +57,15 @@
> #define CSC_RGB_TO_YUV_RV_GV 0xbce89ad8
> #define CSC_RGB_TO_YUV_BV 0x1e08
>
> +#define ROFF(x) (((x) & 0x) << 16)
> +#define GOFF(x) (((x) & 0x) << 0)
> +#define BOFF(x) (((x) & 0x) << 16)
> +
> +/* Preoffset values for YUV to RGB Conversion */
> +#define PREOFF_YUV_TO_RGB_HI 0x1800
> +#define PREOFF_YUV_TO_RGB_ME 0x1F00
> +#define PREOFF_YUV_TO_RGB_LO 0x1800
> +
> /*
> * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
> * format). This macro takes the coefficient we want transformed and the
> @@ -643,6 +652,76 @@ int intel_color_check(struct drm_crtc *crtc,
> return -EINVAL;
> }
>
> +void icl_program_input_csc_coeff(const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> +{
> + struct drm_i915_private *dev_priv =
> + to_i915(plane_state->base.plane->dev);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + enum pipe pipe = crtc->pipe;
> + struct intel_plane *intel_plane =
> + to_intel_plane(plane_state->base.plane);
> + enum plane_id plane = intel_plane->id;
> +
> + static const u16 input_csc_matrix[][9] = {
Can you add comments to these indicating the human-readable values they
translate to?
> + /* BT.601 full range YCbCr -> full range RGB */
> + [DRM_COLOR_YCBCR_BT601] = {
> + 0x7AF8, 0x7800, 0x0,
> + 0x8B28, 0x7800, 0x9AC0,
> + 0x0, 0x7800, 0x7DD8,
> + },
> + /* BT.709 full range YCbCr -> full range RGB */
> + [DRM_COLOR_YCBCR_BT709] = {
> + 0x7C98, 0x7800, 0x0,
> + 0x9EF8, 0x7800, 0xABF8,
> + 0x0, 0x7800, 0x7ED8,
> + },
> + };
> +
> + /* Matrix for Limited Range to Full Range Conversion */
> + static const u16 input_csc_matrix_lr[][9] = {
> + /* BT.601 Limted range YCbCr -> full range RGB */
> + [DRM_COLOR_YCBCR_BT601] = {
> + 0x7CC8, 0x7950, 0x0,
> + 0x8CB8, 0x7918, 0x9C40,
> + 0x0, 0x7918, 0x7FC8,
Are these obtained by scaling the first row (Y-based) by 256/219 and the
other two rows (Cb and Cr) by 256/224? If so, it looks like you've
always rounded down, whereas in some cases rounding up gives you a
closer value (and matches how the bspec seems to have chosen the full
range encodings for their example).
[ 0x7CD0, 0x7958,0x0 ]
[ 0x8CC0, 0x7928, 0x9C48 ]
[0x0, 0x7928, 0x7FD8 ]
Our encodings of the 1.0 value on the second two rows seems to deviate
slightly more for some reason; not sure why that is.
For completeness, here's how I came up with 0x7928:
1 * 256/224 = 1.142857143
Sign bit = 0
Exponent bits = 0b111
Mantissa bits = round(1.142857143 << 8)
= round(292.571428571)
= 293
= 0b100100101
Reserved bits = 0b000
Result = 0111 1001 0010 1000
= 0x7928
If you did floor() instead of round() for the mantissa, you'd get 292,
which would translate to 0x7920 instead.
> + },
> + /* BT.709 Limited range YCbCr -> full range
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Account for scale factor when calculating initial phase (rev2)
== Series Details == Series: drm/i915: Account for scale factor when calculating initial phase (rev2) URL : https://patchwork.freedesktop.org/series/51696/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5049_full -> Patchwork_10630_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_10630_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10630_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10630_full: === IGT changes === Warnings igt@perf_pmu@rc6: shard-kbl: PASS -> SKIP == Known issues == Here are the changes found in Patchwork_10630_full that come from known issues: === IGT changes === Issues hit igt@gem_exec_schedule@pi-ringfull-blt: shard-skl: NOTRUN -> FAIL (fdo#103158) igt@kms_busy@extended-modeset-hang-newfb-render-c: shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) +1 igt@kms_color@pipe-a-ctm-max: shard-apl: PASS -> FAIL (fdo#108147) igt@kms_cursor_crc@cursor-128x42-offscreen: shard-skl: PASS -> FAIL (fdo#103232) igt@kms_cursor_crc@cursor-128x42-sliding: shard-apl: PASS -> FAIL (fdo#103232) +2 igt@kms_cursor_legacy@cursorb-vs-flipb-toggle: shard-glk: PASS -> DMESG-WARN (fdo#106538, fdo#105763) igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled: shard-glk: PASS -> FAIL (fdo#103184) igt@kms_fbcon_fbt@psr-suspend: shard-skl: NOTRUN -> FAIL (fdo#107882) igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: shard-glk: PASS -> FAIL (fdo#105363) igt@kms_flip@flip-vs-expired-vblank: shard-skl: NOTRUN -> FAIL (fdo#105363) igt@kms_flip@plain-flip-ts-check-interruptible: shard-kbl: PASS -> FAIL (fdo#100368) igt@kms_flip_tiling@flip-to-x-tiled: shard-skl: PASS -> FAIL (fdo#108134) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu: shard-skl: PASS -> FAIL (fdo#105682) +1 igt@kms_frontbuffer_tracking@fbc-1p-rte: shard-apl: PASS -> FAIL (fdo#103167, fdo#105682) igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-blt: shard-skl: PASS -> FAIL (fdo#103167) igt@kms_plane@plane-position-covered-pipe-a-planes: shard-apl: PASS -> FAIL (fdo#103166) +2 igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb: shard-skl: NOTRUN -> FAIL (fdo#108145) igt@kms_plane_alpha_blend@pipe-c-alpha-7efc: shard-skl: NOTRUN -> FAIL (fdo#107815, fdo#108145) igt@pm_rpm@drm-resources-equal: shard-skl: PASS -> INCOMPLETE (fdo#107807) Possible fixes igt@drv_suspend@debugfs-reader: shard-skl: INCOMPLETE (fdo#107773, fdo#104108) -> PASS igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a: shard-hsw: DMESG-WARN (fdo#107956) -> PASS igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b: shard-kbl: DMESG-WARN (fdo#107956) -> PASS +1 igt@kms_cursor_crc@cursor-256x85-offscreen: shard-skl: FAIL (fdo#103232) -> PASS igt@kms_cursor_crc@cursor-64x21-sliding: shard-apl: FAIL (fdo#103232) -> PASS +2 igt@kms_cursor_legacy@cursora-vs-flipa-toggle: shard-glk: DMESG-WARN (fdo#106538, fdo#105763) -> PASS igt@kms_draw_crc@draw-method-rgb565-pwrite-ytiled: shard-glk: FAIL (fdo#103184) -> PASS igt@kms_flip@basic-flip-vs-wf_vblank: shard-skl: FAIL (fdo#100368) -> PASS igt@kms_flip@modeset-vs-vblank-race: shard-kbl: FAIL (fdo#103060) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff: shard-apl: FAIL (fdo#103167) -> PASS +1 igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff: shard-glk: DMESG-FAIL (fdo#103167, fdo#106538) -> PASS igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: shard-skl: FAIL (fdo#107815) -> PASS +1 igt@kms_plane_multiple@atomic-pipe-b-tiling-x: shard-glk: FAIL (fdo#103166) -> PASS igt@kms_plane_multiple@atomic-pipe-b-tiling-y: shard-apl: FAIL (fdo#103166) -> PASS igt@kms_setmode@basic: shard-apl: FAIL (fdo#99912) -> PASS shard-kbl: FAIL (fdo#99912) -> PASS igt@perf@rc6-disable: shard-kbl: FAIL (fdo#103179) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060 fdo#103158
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/7] drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming
== Series Details == Series: series starting with [CI,1/7] drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming URL : https://patchwork.freedesktop.org/series/51711/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming Okay! Commit: drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT Okay! Commit: drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init Okay! Commit: drm/dp: DRM DP helper/macros to get DP sink DSC parameters Okay! Commit: drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC +drivers/gpu/drm/i915/intel_dp.c:4208:26: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dp.c:4208:26: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dp.c:4251:27: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dp.c:4251:27: warning: expression using sizeof(void) Commit: drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported Okay! Commit: drm/dp: Define payload size for DP SDP PPS packet Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/7] drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming
== Series Details == Series: series starting with [CI,1/7] drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming URL : https://patchwork.freedesktop.org/series/51711/ State : warning == Summary == $ dim checkpatch origin/drm-tip 40a5992273a1 drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming a96d367cf933 drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT 8af94d076e1c drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init f33cb1e31640 drm/dp: DRM DP helper/macros to get DP sink DSC parameters 03afa383a0c4 drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC -:27: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #27: * rename it as SMALL_JOINER since we are not enabling big joiner yet (Anusha) total: 0 errors, 1 warnings, 0 checks, 132 lines checked 4760c751a865 drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported d7bcf254d578 drm/dp: Define payload size for DP SDP PPS packet ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftest: test aligned offsets for 64K
== Series Details == Series: drm/i915/selftest: test aligned offsets for 64K URL : https://patchwork.freedesktop.org/series/51707/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5052 -> Patchwork_10636 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/51707/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10636 that come from known issues: === IGT changes === Issues hit igt@drv_selftest@live_coherency: fi-gdg-551: PASS -> DMESG-FAIL (fdo#107164) igt@gem_exec_suspend@basic-s4-devices: fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718) igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: PASS -> DMESG-WARN (fdo#102614) igt@pm_rpm@basic-pci-d3-state: fi-skl-6600u: PASS -> FAIL (fdo#107707) Possible fixes igt@kms_flip@basic-flip-vs-dpms: fi-skl-6700hq: DMESG-WARN (fdo#105998) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: fi-byt-clapper: FAIL (fdo#107362, fdo#103191) -> PASS fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998 fdo#107164 https://bugs.freedesktop.org/show_bug.cgi?id=107164 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107707 https://bugs.freedesktop.org/show_bug.cgi?id=107707 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 == Participating hosts (49 -> 43) == Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-icl-u == Build changes == * Linux: CI_DRM_5052 -> Patchwork_10636 CI_DRM_5052: 24b6ea5d5f299c5e9e6b4d92068651f7f1555bd0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4699: 1270ec553741ac20c45178d2b26f9a9562ea565f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10636: 13b72d6d80b4f8018edf3b7dc82eb0a22015b76d @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 13b72d6d80b4 drm/i915/selftest: test aligned offsets for 64K == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10636/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v6 13/28] drm/i915/dp: Compute DSC pipe config in atomic check
On Mon, Oct 29, 2018 at 10:34:58PM +0200, Ville Syrjälä wrote:
> On Mon, Oct 29, 2018 at 10:30:39PM +0200, Ville Syrjälä wrote:
> > On Wed, Oct 24, 2018 at 03:28:25PM -0700, Manasi Navare wrote:
> > > DSC params like the enable, compressed bpp, slice count and
> > > dsc_split are added to the intel_crtc_state. These parameters
> > > are set based on the requested mode and available link parameters
> > > during the pipe configuration in atomic check phase.
> > > These values are then later used to populate the remaining DSC
> > > and RC parameters before enbaling DSC in atomic commit.
> > >
> > > v9:
> > > * Rebase on top of drm-tip that now uses fast_narrow config
> > > for edp (Manasi)
> > > v8:
> > > * Check for DSC bpc not 0 (manasi)
> > >
> > > v7:
> > > * Fix indentation in compute_m_n (Manasi)
> > >
> > > v6 (From Gaurav):
> > > * Remove function call of intel_dp_compute_dsc_params() and
> > > invoke intel_dp_compute_dsc_params() in the patch where
> > > it is defined to fix compilation warning (Gaurav)
> > >
> > > v5:
> > > Add drm_dsc_cfg in intel_crtc_state (Manasi)
> > >
> > > v4:
> > > * Rebase on refactoring of intel_dp_compute_config on tip (Manasi)
> > > * Add a comment why we need to check PSR while enabling DSC (Gaurav)
> > >
> > > v3:
> > > * Check PPR > max_cdclock to use 2 VDSC instances (Ville)
> > >
> > > v2:
> > > * Add if-else for eDP/DP (Gaurav)
> > >
> > > Cc: Jani Nikula
> > > Cc: Ville Syrjala
> > > Cc: Anusha Srivatsa
> > > Cc: Gaurav K Singh
> > > Signed-off-by: Manasi Navare
> > > Reviewed-by: Anusha Srivatsa
> > > Acked-by: Jani Nikula
> > > ---
> > > drivers/gpu/drm/i915/intel_display.c | 20 +++-
> > > drivers/gpu/drm/i915/intel_display.h | 3 +-
> > > drivers/gpu/drm/i915/intel_dp.c | 170 ++-
> > > drivers/gpu/drm/i915/intel_dp_mst.c | 2 +-
> > > 4 files changed, 155 insertions(+), 40 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > > b/drivers/gpu/drm/i915/intel_display.c
> > > index fe045abb6472..18737bd82b68 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -6434,7 +6434,7 @@ static int ironlake_fdi_compute_config(struct
> > > intel_crtc *intel_crtc,
> > >
> > > pipe_config->fdi_lanes = lane;
> > >
> > > - intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
> > > + intel_link_compute_m_n(pipe_config->pipe_bpp, 0, lane, fdi_dotclock,
> > > link_bw, _config->fdi_m_n, false);
> > >
> > > ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
> > > @@ -6671,17 +6671,25 @@ static void compute_m_n(unsigned int m, unsigned
> > > int n,
> > > }
> > >
> > > void
> > > -intel_link_compute_m_n(int bits_per_pixel, int nlanes,
> > > +intel_link_compute_m_n(int bits_per_pixel, uint16_t compressed_bpp,
> > > +int nlanes,
> > > int pixel_clock, int link_clock,
> > > struct intel_link_m_n *m_n,
> > > bool constant_n)
> > > {
> > > m_n->tu = 64;
> > >
> > > - compute_m_n(bits_per_pixel * pixel_clock,
> > > - link_clock * nlanes * 8,
> > > - _n->gmch_m, _n->gmch_n,
> > > - constant_n);
> > > + /* For DSC, Data M/N calculation uses compressed BPP */
> > > + if (compressed_bpp)
> > > + compute_m_n(compressed_bpp * pixel_clock,
> > > + link_clock * nlanes * 8,
> > > + _n->gmch_m, _n->gmch_n,
> > > + constant_n);
> > > + else
> > > + compute_m_n(bits_per_pixel * pixel_clock,
> > > + link_clock * nlanes * 8,
> > > + _n->gmch_m, _n->gmch_n,
> > > + constant_n);
> > >
> > > compute_m_n(pixel_clock, link_clock,
> > > _n->link_m, _n->link_n,
> > > diff --git a/drivers/gpu/drm/i915/intel_display.h
> > > b/drivers/gpu/drm/i915/intel_display.h
> > > index 5d50decbcbb5..b0b23e1e9392 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.h
> > > +++ b/drivers/gpu/drm/i915/intel_display.h
> > > @@ -407,7 +407,8 @@ struct intel_link_m_n {
> > >(__i)++) \
> > > for_each_if(plane)
> > >
> > > -void intel_link_compute_m_n(int bpp, int nlanes,
> > > +void intel_link_compute_m_n(int bpp, uint16_t compressed_bpp,
> > > + int nlanes,
> > > int pixel_clock, int link_clock,
> > > struct intel_link_m_n *m_n,
> > > bool constant_n);
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > > b/drivers/gpu/drm/i915/intel_dp.c
> > > index 6f66a38ba0b2..a88f9371dd32 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -47,6 +47,8 @@
> > >
> > > /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
> > > #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
> > > +#define
[Intel-gfx] [PATCH 5/5] drm/i915: Kill WA 0826
According to BSpec this is not needed anymore: "This workaround is no longer needed since NV12 support is dropped for the affected projects. " Cc: Maarten Lankhorst Cc: Ville Syrjälä Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_pm.c | 10 -- 1 file changed, 10 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 9ee96016cfd5..f202b9b3b796 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4823,16 +4823,6 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, } } - /* -* Display WA #826 (SKL:ALL, BXT:ALL) -* disable wm level 1-7 on NV12 planes -*/ - if (wp->is_planar && level >= 1 && - (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv)) - result->plane_en = false; - return 0; - } - /* The number of lines are ignored for the level 0 watermark. */ result->plane_res_b = res_blocks; result->plane_res_l = res_lines; -- 2.19.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/5] drm/i915: Remove CNL from WA 827
CNL A stepping was the only affected there. But also it is time to clean old pre-production CNL Workarounds, so let's just remove and clean this W/A. Cc: Maarten Lankhorst Cc: Ville Syrjälä Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_display.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index c3cadc09f859..dd88ffe9e273 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5242,8 +5242,8 @@ static bool needs_nv12_wa(struct drm_i915_private *dev_priv, if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv)) return false; - if ((IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) || - IS_CANNONLAKE(dev_priv)) + /* WA Display #0827: Gen9:all */ + if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) return true; return false; -- 2.19.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/5] drm/i915/cnl: Remove useless CNL A-stepping workarounds.
These were always useless since CNL A stepping needed many
more workarounds that were never introduced and also
we started Linux work on CNL B stepping anyways.
Cc: Paulo Zanoni
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_pm.c| 10 ++
drivers/gpu/drm/i915/intel_wopcm.c | 3 +--
2 files changed, 3 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 82c82e233154..9ee96016cfd5 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4824,12 +4824,11 @@ static int skl_compute_plane_wm(const struct
drm_i915_private *dev_priv,
}
/*
-* Display WA #826 (SKL:ALL, BXT:ALL) & #1059 (CNL:A)
+* Display WA #826 (SKL:ALL, BXT:ALL)
* disable wm level 1-7 on NV12 planes
*/
if (wp->is_planar && level >= 1 &&
- (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
-IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))) {
+ (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
result->plane_en = false;
return 0;
}
@@ -4953,11 +4952,6 @@ static void skl_compute_transition_wm(const struct
intel_crtc_state *cstate,
trans_offset_b;
} else {
res_blocks = wm0_sel_res_b + trans_offset_b;
-
- /* WA BUG:1938466 add one block for non y-tile planes */
- if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))
- res_blocks += 1;
-
}
res_blocks += 1;
diff --git a/drivers/gpu/drm/i915/intel_wopcm.c
b/drivers/gpu/drm/i915/intel_wopcm.c
index 92cb82dd0c07..b8ee8669c260 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_wopcm.c
@@ -133,8 +133,7 @@ static inline int check_hw_restriction(struct
drm_i915_private *i915,
if (IS_GEN9(i915))
err = gen9_check_dword_gap(guc_wopcm_base, guc_wopcm_size);
- if (!err &&
- (IS_GEN9(i915) || IS_CNL_REVID(i915, CNL_REVID_A0, CNL_REVID_A0)))
+ if (!err && IS_GEN9(i915))
err = gen9_check_huc_fw_fits(guc_wopcm_size, huc_fw_size);
return err;
--
2.19.1
___
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[Intel-gfx] [PATCH 3/5] drm/i915: Introduce HAS_NV12 and define WA 0870.
Let's introduce HAS_NV12 to check for feature itself
than spread the platform checks everywhere.
Also let's introduce the WA number that is the
cause of having NV12 disabled on both SLK and BXT.
According to Spec:
WA 0870: "Display flickers with NV12 video playback in
Y tiling mode.
WA: Use YUV422 surface format instead of NV12."
Cc: Maarten Lankhorst
Cc: Ville Syrjälä
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_pci.c | 5 +
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 7 +++
drivers/gpu/drm/i915/intel_sprite.c | 2 +-
5 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c9e5bab6861b..57ea094054d5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2630,6 +2630,7 @@ intel_info(const struct drm_i915_private *dev_priv)
#define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
#define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
+#define HAS_NV12(dev_priv) ((dev_priv)->info.has_nv12)
#define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
#define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 44e745921ac1..eb797c1ef842 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -462,6 +462,7 @@ static const struct intel_device_info intel_cherryview_info
= {
GEN(9), \
GEN9_DEFAULT_PAGE_SIZES, \
.has_logical_ring_preemption = 1, \
+ .has_nv12 = 1, \
.has_csr = 1, \
.has_guc = 1, \
.has_ipc = 1, \
@@ -471,6 +472,8 @@ static const struct intel_device_info intel_cherryview_info
= {
GEN9_FEATURES, \
/* Display WA #0477 WaDisableIPC: skl */ \
.has_ipc = 0, \
+ /* Display WA #0870: skl */ \
+ .has_nv12 = 0, \
PLATFORM(INTEL_SKYLAKE)
static const struct intel_device_info intel_skylake_gt1_info = {
@@ -531,6 +534,8 @@ static const struct intel_device_info intel_broxton_info = {
GEN9_LP_FEATURES,
PLATFORM(INTEL_BROXTON),
.ddb_size = 512,
+ /* Display WA #0870: bxt */
+ .has_nv12 = 0,
};
static const struct intel_device_info intel_geminilake_info = {
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index b4c2c4eae78b..ba9e9c59dc6c 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -104,6 +104,7 @@ enum intel_ppgtt {
func(has_logical_ring_contexts); \
func(has_logical_ring_elsq); \
func(has_logical_ring_preemption); \
+ func(has_nv12); \
func(has_overlay); \
func(has_pooled_eu); \
func(has_psr); \
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index dd88ffe9e273..14f6f66b00d2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -470,7 +470,7 @@ skl_wa_528(struct drm_i915_private *dev_priv, int pipe,
bool enable)
static void
skl_wa_clkgate(struct drm_i915_private *dev_priv, int pipe, bool enable)
{
- if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
+ if (!HAS_NV12(dev_priv))
return;
if (enable)
@@ -5239,7 +5239,7 @@ static bool needs_nv12_wa(struct drm_i915_private
*dev_priv,
if (!crtc_state->nv12_planes)
return false;
- if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
+ if (!HAS_NV12(dev_priv))
return false;
/* WA Display #0827: Gen9:all */
@@ -14519,8 +14519,7 @@ static int intel_framebuffer_init(struct
intel_framebuffer *intel_fb,
}
break;
case DRM_FORMAT_NV12:
- if (INTEL_GEN(dev_priv) < 9 || IS_SKYLAKE(dev_priv) ||
- IS_BROXTON(dev_priv)) {
+ if (!HAS_NV12(dev_priv)) {
DRM_DEBUG_KMS("unsupported pixel format: %s\n",
drm_get_format_name(mode_cmd->pixel_format,
_name));
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index e7c95ec879cc..582a2972c90d 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1868,7 +1868,7 @@ static bool skl_plane_has_planar(struct drm_i915_private
*dev_priv,
if (INTEL_GEN(dev_priv) >= 11)
return plane_id <= PLANE_SPRITE3;
- if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
+ if (!HAS_NV12(dev_priv))
return false;
if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C)
--
2.19.1
___
[Intel-gfx] [PATCH 4/5] drm/i915: Kill WA 0528
First of all I believe this WA as written here was wrong.
Because it is listed on BSpec only for SKL and BXT, exactly
the only 2 platforms skipped here.
But also it is written there that we don't need this WA
anymore:
"This workaround is no longer needed since NV12 support is
dropped for the affected projects in #0870."
SO, let's kill it.
Cc: Maarten Lankhorst
Cc: Vidya Srinivas
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_display.c | 14 --
1 file changed, 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 14f6f66b00d2..aacc340d4eec 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -455,18 +455,6 @@ static const struct intel_limit intel_limits_bxt = {
.p2 = { .p2_slow = 1, .p2_fast = 20 },
};
-static void
-skl_wa_528(struct drm_i915_private *dev_priv, int pipe, bool enable)
-{
- if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
- return;
-
- if (enable)
- I915_WRITE(CHICKEN_PIPESL_1(pipe), HSW_FBCQ_DIS);
- else
- I915_WRITE(CHICKEN_PIPESL_1(pipe), 0);
-}
-
static void
skl_wa_clkgate(struct drm_i915_private *dev_priv, int pipe, bool enable)
{
@@ -5286,7 +5274,6 @@ static void intel_post_plane_update(struct
intel_crtc_state *old_crtc_state)
if (needs_nv12_wa(dev_priv, old_crtc_state) &&
!needs_nv12_wa(dev_priv, pipe_config)) {
skl_wa_clkgate(dev_priv, crtc->pipe, false);
- skl_wa_528(dev_priv, crtc->pipe, false);
}
}
@@ -5326,7 +5313,6 @@ static void intel_pre_plane_update(struct
intel_crtc_state *old_crtc_state,
if (!needs_nv12_wa(dev_priv, old_crtc_state) &&
needs_nv12_wa(dev_priv, pipe_config)) {
skl_wa_clkgate(dev_priv, crtc->pipe, true);
- skl_wa_528(dev_priv, crtc->pipe, true);
}
/*
--
2.19.1
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 1/2] drm: Add drm_any_plane_has_format()
Ville Syrjala writes: > From: Ville Syrjälä > > Add a function to check whether there is at least one plane that > supports a specific format and modifier combination. Drivers can > use this to reject unsupported formats/modifiers in .fb_create(). > > v2: Accept anyformat if the driver doesn't do planes (Eric) > s/planes_have_format/any_plane_has_format/ (Eric) > Check the modifier as well since we already have a function > that does both > v3: Don't do the check in the core since we may not know the > modifier yet, instead export the function and let drivers > call it themselves > > Cc: Eric Anholt > Cc: Dhinakaran Pandiyan > Signed-off-by: Ville Syrjälä > Reviewed-by: Dhinakaran Pandiyan I don't particularly see the point in having FB creation duplicate the validation that atomic check will eventually do, and it means that FB creation cost scales with plane count, but if i915's going to do this, it seems reasonable for them. signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/icl: Enable DC9 as lowest possible state during screen-off
From: Animesh Manna
ICL supports DC5, DC6, and DC9. Enable DC9 during screen-off, and enable
DC5/6 when appropriate.
v2: (James Ausmus)
- Also handle ICL as GEN9_LP in i915_drm_suspend_late and
i915_drm_suspend_early
- Add DC9 to gen9_dc_mask for ICL
- Re-order GEN checks for newest platform first
- Use INTEL_GEN instead of INTEL_INFO->gen
- Use INTEL_GEN >= 11 instead of IS_ICELAKE
- Consolidate GEN checks
v3: (James Ausmus)
- Also allow DC6 for ICL (Imre, Art)
- Simplify !(GEN >= 11) to GEN < 11 (Imre)
v4: (James Ausmus)
- Don't call intel_power_sequencer_reset after DC9 for Gen11+, as the
PPS regs are Always On
- Rebase against upstream changes
v5: (Anusha Srivatsa)
- rebased against the latest upstream changes.
v6: (Anusha Srivatsa)
- rebased.Use INTEL_GEN consistently.
- Simplify the code (Rodrigo)
v7: rebased. Change order according to platforms(Jyoti)
v8: rebased. Change the check from platform specific to
HAS_PCH_SPLIT(). Add comment in code to be more clear.(Rodrigo)
Cc: Imre Deak
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
Signed-off-by: James Ausmus
Signed-off-by: Anusha Srivatsa
Tested-by: Jyoti Yadav
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_drv.c | 20 +---
drivers/gpu/drm/i915/intel_drv.h| 3 +++
drivers/gpu/drm/i915/intel_runtime_pm.c | 32 -
3 files changed, 41 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1ad13da61d7a..6bdcd5a3d7b7 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2157,7 +2157,7 @@ static int i915_drm_resume_early(struct drm_device *dev)
intel_uncore_resume_early(dev_priv);
- if (IS_GEN9_LP(dev_priv)) {
+ if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
gen9_sanitize_dc_state(dev_priv);
bxt_disable_dc9(dev_priv);
} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
@@ -2924,7 +2924,10 @@ static int intel_runtime_suspend(struct device *kdev)
intel_uncore_suspend(dev_priv);
ret = 0;
- if (IS_GEN9_LP(dev_priv)) {
+ if (INTEL_GEN(dev_priv) >= 11) {
+ icl_display_core_uninit(dev_priv);
+ bxt_enable_dc9(dev_priv);
+ } else if (IS_GEN9_LP(dev_priv)) {
bxt_display_core_uninit(dev_priv);
bxt_enable_dc9(dev_priv);
} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
@@ -3009,7 +3012,18 @@ static int intel_runtime_resume(struct device *kdev)
if (intel_uncore_unclaimed_mmio(dev_priv))
DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
- if (IS_GEN9_LP(dev_priv)) {
+ if (INTEL_GEN(dev_priv) >= 11) {
+ bxt_disable_dc9(dev_priv);
+ icl_display_core_init(dev_priv, true);
+ if (dev_priv->csr.dmc_payload) {
+ if (dev_priv->csr.allowed_dc_mask &
+ DC_STATE_EN_UPTO_DC6)
+ skl_enable_dc6(dev_priv);
+ else if (dev_priv->csr.allowed_dc_mask &
+DC_STATE_EN_UPTO_DC5)
+ gen9_enable_dc5(dev_priv);
+ }
+ } else if (IS_GEN9_LP(dev_priv)) {
bxt_disable_dc9(dev_priv);
bxt_display_core_init(dev_priv, true);
if (dev_priv->csr.dmc_payload &&
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 268afb6d2746..e4eaa40bd5f1 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1695,6 +1695,7 @@ void bxt_enable_dc9(struct drm_i915_private *dev_priv);
void bxt_disable_dc9(struct drm_i915_private *dev_priv);
void gen9_enable_dc5(struct drm_i915_private *dev_priv);
unsigned int skl_cdclk_get_vco(unsigned int freq);
+void skl_enable_dc6(struct drm_i915_private *dev_priv);
void intel_dp_get_m_n(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config);
void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
@@ -2045,6 +2046,8 @@ int intel_power_domains_init(struct drm_i915_private *);
void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool
resume);
void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv);
+void icl_display_core_init(struct drm_i915_private *dev_priv, bool resume);
+void icl_display_core_uninit(struct drm_i915_private *dev_priv);
void intel_power_domains_enable(struct drm_i915_private *dev_priv);
void intel_power_domains_disable(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 5f5416eb9644..b1901a6c17be 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++
Re: [Intel-gfx] [PATCH v6 13/28] drm/i915/dp: Compute DSC pipe config in atomic check
On Mon, Oct 29, 2018 at 10:30:39PM +0200, Ville Syrjälä wrote:
> On Wed, Oct 24, 2018 at 03:28:25PM -0700, Manasi Navare wrote:
> > DSC params like the enable, compressed bpp, slice count and
> > dsc_split are added to the intel_crtc_state. These parameters
> > are set based on the requested mode and available link parameters
> > during the pipe configuration in atomic check phase.
> > These values are then later used to populate the remaining DSC
> > and RC parameters before enbaling DSC in atomic commit.
> >
> > v9:
> > * Rebase on top of drm-tip that now uses fast_narrow config
> > for edp (Manasi)
> > v8:
> > * Check for DSC bpc not 0 (manasi)
> >
> > v7:
> > * Fix indentation in compute_m_n (Manasi)
> >
> > v6 (From Gaurav):
> > * Remove function call of intel_dp_compute_dsc_params() and
> > invoke intel_dp_compute_dsc_params() in the patch where
> > it is defined to fix compilation warning (Gaurav)
> >
> > v5:
> > Add drm_dsc_cfg in intel_crtc_state (Manasi)
> >
> > v4:
> > * Rebase on refactoring of intel_dp_compute_config on tip (Manasi)
> > * Add a comment why we need to check PSR while enabling DSC (Gaurav)
> >
> > v3:
> > * Check PPR > max_cdclock to use 2 VDSC instances (Ville)
> >
> > v2:
> > * Add if-else for eDP/DP (Gaurav)
> >
> > Cc: Jani Nikula
> > Cc: Ville Syrjala
> > Cc: Anusha Srivatsa
> > Cc: Gaurav K Singh
> > Signed-off-by: Manasi Navare
> > Reviewed-by: Anusha Srivatsa
> > Acked-by: Jani Nikula
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 20 +++-
> > drivers/gpu/drm/i915/intel_display.h | 3 +-
> > drivers/gpu/drm/i915/intel_dp.c | 170 ++-
> > drivers/gpu/drm/i915/intel_dp_mst.c | 2 +-
> > 4 files changed, 155 insertions(+), 40 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index fe045abb6472..18737bd82b68 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -6434,7 +6434,7 @@ static int ironlake_fdi_compute_config(struct
> > intel_crtc *intel_crtc,
> >
> > pipe_config->fdi_lanes = lane;
> >
> > - intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
> > + intel_link_compute_m_n(pipe_config->pipe_bpp, 0, lane, fdi_dotclock,
> >link_bw, _config->fdi_m_n, false);
> >
> > ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
> > @@ -6671,17 +6671,25 @@ static void compute_m_n(unsigned int m, unsigned
> > int n,
> > }
> >
> > void
> > -intel_link_compute_m_n(int bits_per_pixel, int nlanes,
> > +intel_link_compute_m_n(int bits_per_pixel, uint16_t compressed_bpp,
> > + int nlanes,
> >int pixel_clock, int link_clock,
> >struct intel_link_m_n *m_n,
> >bool constant_n)
> > {
> > m_n->tu = 64;
> >
> > - compute_m_n(bits_per_pixel * pixel_clock,
> > - link_clock * nlanes * 8,
> > - _n->gmch_m, _n->gmch_n,
> > - constant_n);
> > + /* For DSC, Data M/N calculation uses compressed BPP */
> > + if (compressed_bpp)
> > + compute_m_n(compressed_bpp * pixel_clock,
> > + link_clock * nlanes * 8,
> > + _n->gmch_m, _n->gmch_n,
> > + constant_n);
> > + else
> > + compute_m_n(bits_per_pixel * pixel_clock,
> > + link_clock * nlanes * 8,
> > + _n->gmch_m, _n->gmch_n,
> > + constant_n);
> >
> > compute_m_n(pixel_clock, link_clock,
> > _n->link_m, _n->link_n,
> > diff --git a/drivers/gpu/drm/i915/intel_display.h
> > b/drivers/gpu/drm/i915/intel_display.h
> > index 5d50decbcbb5..b0b23e1e9392 100644
> > --- a/drivers/gpu/drm/i915/intel_display.h
> > +++ b/drivers/gpu/drm/i915/intel_display.h
> > @@ -407,7 +407,8 @@ struct intel_link_m_n {
> > (__i)++) \
> > for_each_if(plane)
> >
> > -void intel_link_compute_m_n(int bpp, int nlanes,
> > +void intel_link_compute_m_n(int bpp, uint16_t compressed_bpp,
> > + int nlanes,
> > int pixel_clock, int link_clock,
> > struct intel_link_m_n *m_n,
> > bool constant_n);
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 6f66a38ba0b2..a88f9371dd32 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -47,6 +47,8 @@
> >
> > /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
> > #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
> > +#define DP_DSC_MIN_SUPPORTED_BPC 8
> > +#define DP_DSC_MAX_SUPPORTED_BPC 10
> >
> > /* DP DSC throughput values used for slice count calculations KPixels/s */
> > #define DP_DSC_PEAK_PIXEL_RATE 272
> > @@ -1924,6
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftest: fix 64K alignment in igt_write_huge
== Series Details == Series: drm/i915/selftest: fix 64K alignment in igt_write_huge URL : https://patchwork.freedesktop.org/series/51705/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5051 -> Patchwork_10635 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/51705/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10635 that come from known issues: === IGT changes === Issues hit igt@gem_exec_suspend@basic-s3: fi-kbl-soraka: NOTRUN -> INCOMPLETE (fdo#107859, fdo#107774, fdo#107556) igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: fi-byt-clapper: PASS -> FAIL (fdo#103191, fdo#107362) Possible fixes igt@gem_exec_suspend@basic-s3: fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS igt@kms_frontbuffer_tracking@basic: fi-icl-u2: FAIL (fdo#103167) -> PASS fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107556 https://bugs.freedesktop.org/show_bug.cgi?id=107556 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#107774 https://bugs.freedesktop.org/show_bug.cgi?id=107774 fdo#107859 https://bugs.freedesktop.org/show_bug.cgi?id=107859 == Participating hosts (48 -> 43) == Additional (1): fi-kbl-soraka Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-pnv-d510 == Build changes == * Linux: CI_DRM_5051 -> Patchwork_10635 CI_DRM_5051: 2523b4d2158bc0fc25031aad0def0b4ba04432f2 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4699: 1270ec553741ac20c45178d2b26f9a9562ea565f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10635: c5f887b3440ca7d64b51dd4f3f27e368e90510f5 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c5f887b3440c drm/i915/selftest: fix 64K alignment in igt_write_huge == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10635/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] drm/i915: Make 48bit full ppgtt configuration generic (v7)
Quoting Bob Paauwe (2018-10-29 21:39:49) > 48 bit ppgtt device configuration is really just extended address > range full ppgtt and may actually be something other than 48 bits. > > Change HAS_FULL_48BIT_PPGTT() to HAS_4LVL_PPGTT() to better > describe that a 4 level walk table extended range PPGTT is being > used. Add a new device info field that specifies the number of > bits to prepare for cases where the range is not 32 or 48 bits. > Also rename other functions and comments from 48bit to 4-level. > > Making use of the device info address range for gen6 highlights > simularities in the gen6 and gen8 code paths so move the common > code in to a common function. > > v2: Keep HAS_FULL_PPGTT() unchanged (Chris) > v3: Simplify condition in gen8_ppgtt_create() (Chris) > Remove unnecessary line coninuations (Bob) > Rename functions/defines/comments from 48bit to 4lvl (Rodrigo/Bob) > v4: Rename FULL_4LVL_PPGTT to simply 4LVL_PPGTT (Rodrigo) > Be explised in setting vm.total to 1ULL << 32 (Rodrigo) > Gen 7 is 31 bits, not 32 (Chris) > v5: Mock device is 64b(63b) not 48b (Chris) > v6: Rebase to latest drm-tip (Bob) > v7: Combine common code for gen6/gen8 ppgtt create (Chris) > Improve comment on device info field (Chris) > > Signed-off-by: Bob Paauwe > CC: Rodrigo Vivi > CC: Michel Thierry > CC: Chris Wilson > --- > drivers/gpu/drm/i915/gvt/vgpu.c | 2 +- > drivers/gpu/drm/i915/i915_drv.c | 2 +- > drivers/gpu/drm/i915/i915_drv.h | 2 +- > drivers/gpu/drm/i915/i915_gem_context.c | 2 +- > drivers/gpu/drm/i915/i915_gem_gtt.c | 139 -- > drivers/gpu/drm/i915/i915_gem_gtt.h | 4 +- > drivers/gpu/drm/i915/i915_pci.c | 6 + > drivers/gpu/drm/i915/i915_pvinfo.h| 2 +- > drivers/gpu/drm/i915/i915_vgpu.c | 4 +- > drivers/gpu/drm/i915/i915_vgpu.h | 2 +- > drivers/gpu/drm/i915/intel_device_info.c | 1 + > drivers/gpu/drm/i915/intel_device_info.h | 3 + > drivers/gpu/drm/i915/intel_lrc.c | 6 +- > drivers/gpu/drm/i915/selftests/huge_pages.c | 8 +- > .../gpu/drm/i915/selftests/mock_gem_device.c | 2 + > 15 files changed, 90 insertions(+), 95 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c > index c628be05fbfe..6002ded0042b 100644 > --- a/drivers/gpu/drm/i915/gvt/vgpu.c > +++ b/drivers/gpu/drm/i915/gvt/vgpu.c > @@ -44,7 +44,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu) > vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0; > vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id; > > - vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT; > + vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_4LVL_PPGTT; The cap is actually full-ppgtt support. The 48b was accidental and gvt now does both 3-lvl and 4-lvl aiui. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 4/7] drm/dp: DRM DP helper/macros to get DP sink DSC parameters
This patch adds inline functions and helpers for obtaining
DP sink's supported DSC parameters like DSC sink support,
eDP compressed BPP supported, maximum slice count supported
by the sink devices, DSC line buffer bit depth supported on DP sink,
DSC sink maximum color depth by parsing corresponding DPCD registers.
v4:
* Add helper to give line buf bit depth (Manasi)
* Correct the bit masking in color depth helper (manasi)
v3:
* Use SLICE_CAP_2 for DP (Anusha)
v2:
* Add DSC sink support macro (Jani N)
Cc: Gaurav K Singh
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
Reviewed-by: Gaurav K Singh
---
drivers/gpu/drm/drm_dp_helper.c | 90 +
include/drm/drm_dp_helper.h | 30 +++
2 files changed, 120 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 37c01b6076ec..6d483487f2b4 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1352,3 +1352,93 @@ int drm_dp_read_desc(struct drm_dp_aux *aux, struct
drm_dp_desc *desc,
return 0;
}
EXPORT_SYMBOL(drm_dp_read_desc);
+
+/**
+ * DRM DP Helpers for DSC
+ */
+u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
+ bool is_edp)
+{
+ u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT];
+
+ if (is_edp) {
+ /* For eDP, register DSC_SLICE_CAPABILITIES_1 gives slice count
*/
+ if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
+ return 4;
+ if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
+ return 2;
+ if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
+ return 1;
+ } else {
+ /* For DP, use values from DSC_SLICE_CAP_1 and DSC_SLICE_CAP2 */
+ u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT];
+
+ if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK)
+ return 24;
+ if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK)
+ return 20;
+ if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK)
+ return 16;
+ if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK)
+ return 12;
+ if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK)
+ return 10;
+ if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK)
+ return 8;
+ if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK)
+ return 6;
+ if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
+ return 4;
+ if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
+ return 2;
+ if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
+ return 1;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count);
+
+u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
+{
+ u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH -
DP_DSC_SUPPORT];
+
+ switch (line_buf_depth & DP_DSC_LINE_BUF_BIT_DEPTH_MASK) {
+ case DP_DSC_LINE_BUF_BIT_DEPTH_9:
+ return 9;
+ case DP_DSC_LINE_BUF_BIT_DEPTH_10:
+ return 10;
+ case DP_DSC_LINE_BUF_BIT_DEPTH_11:
+ return 11;
+ case DP_DSC_LINE_BUF_BIT_DEPTH_12:
+ return 12;
+ case DP_DSC_LINE_BUF_BIT_DEPTH_13:
+ return 13;
+ case DP_DSC_LINE_BUF_BIT_DEPTH_14:
+ return 14;
+ case DP_DSC_LINE_BUF_BIT_DEPTH_15:
+ return 15;
+ case DP_DSC_LINE_BUF_BIT_DEPTH_16:
+ return 16;
+ case DP_DSC_LINE_BUF_BIT_DEPTH_8:
+ return 8;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth);
+
+u8 drm_dp_dsc_sink_max_color_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
+{
+ u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];
+
+ if (color_depth & DP_DSC_12_BPC)
+ return 12;
+ if (color_depth & DP_DSC_10_BPC)
+ return 10;
+ if (color_depth & DP_DSC_8_BPC)
+ return 8;
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_dsc_sink_max_color_depth);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index dd33d59739f8..7f7f5b965466 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1067,6 +1067,36 @@ drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT;
}
+/* DP/eDP DSC support */
+u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
+ bool is_edp);
+u8 drm_dp_dsc_sink_line_buf_depth(const u8
[Intel-gfx] [CI 3/7] drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init
DSC is supported on eDP starting GEN 10 display (on GLK) and on DP starting
GEN 11.
This patch implements the discovery phase of DSC. On hotplug,
source reads the DSC DPCD register set (0x00060 - 0x0006F) to
read the decompression capabilities of the sink device.
This entire block of registers is cached in intel_dp so that
capability information can be used during DSC configuration
phase during compute_config phase of the modeset.
For eDP, this caching happens during the eDP initialization.
This caching is done only for eDP and DP rev >= 1.4
v5:
* Fix the block comment (Gaurav)
* Fix the commit message DSC DPCD addresses (Gaurav)
* Use DRM_ERROR for dpcd_read fail (Gaurav,Anusha)
v4:
* Cache these only for Gen >= 11
v3:
* Remove the dsc_sink_support field in intel_dp (Jani N)
v2:
* Clear the cached registers on hotplug always (Jani N)
* Combine the eDP and DP caching in same function (Jani N)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Daniel Vetter
Cc: Anusha Srivatsa
Cc: Gaurav K Singh
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
Reviewed-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_dp.c | 32
drivers/gpu/drm/i915/intel_drv.h | 1 +
2 files changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8e64f149ab09..55e070b85c02 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3956,6 +3956,29 @@ intel_dp_read_dpcd(struct intel_dp *intel_dp)
return intel_dp->dpcd[DP_DPCD_REV] != 0;
}
+static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
+{
+ /*
+*Clear the cached register set to avoid using stale values
+* for the sinks that do not support DSC.
+*/
+ memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
+
+ /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
+ if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
+ intel_dp->edp_dpcd[0] >= DP_EDP_14) {
+ if (drm_dp_dpcd_read(_dp->aux, DP_DSC_SUPPORT,
+intel_dp->dsc_dpcd,
+sizeof(intel_dp->dsc_dpcd)) < 0)
+ DRM_ERROR("Failed to read DPCD register 0x%x\n",
+ DP_DSC_SUPPORT);
+
+ DRM_DEBUG_KMS("DSC DPCD: %*ph\n",
+ (int)sizeof(intel_dp->dsc_dpcd),
+ intel_dp->dsc_dpcd);
+ }
+}
+
static bool
intel_edp_init_dpcd(struct intel_dp *intel_dp)
{
@@ -4032,6 +4055,10 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
intel_dp_set_common_rates(intel_dp);
+ /* Read the eDP DSC DPCD registers */
+ if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ intel_dp_get_dsc_sink_cap(intel_dp);
+
return true;
}
@@ -5126,6 +5153,7 @@ intel_dp_detect(struct drm_connector *connector,
if (status == connector_status_disconnected) {
memset(_dp->compliance, 0, sizeof(intel_dp->compliance));
+ memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
if (intel_dp->is_mst) {
DRM_DEBUG_KMS("MST device may have disappeared %d vs
%d\n",
@@ -5151,6 +5179,10 @@ intel_dp_detect(struct drm_connector *connector,
intel_dp_print_rates(intel_dp);
+ /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
+ if (INTEL_GEN(dev_priv) >= 11)
+ intel_dp_get_dsc_sink_cap(intel_dp);
+
drm_dp_read_desc(_dp->aux, _dp->desc,
drm_dp_is_branch(intel_dp->dpcd));
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index db24308729b4..4cacf0e3fa17 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1109,6 +1109,7 @@ struct intel_dp {
uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
+ u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
/* source rates */
int num_source_rates;
const int *source_rates;
--
2.18.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 5/7] drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC
This patch adds helpers for calculating the maximum compressed BPP
supported with small joiner.
This also adds a helper for calculating the slice count in case
of small joiner.
These are inside intel_dp since they take into account hardware
limitations.
v6:
* Take mode_clock and mode_hdisplay as input arguments
so that this can be called in intel_dp_mode_valid (Manasi)
v5:
* Get the max slice width from DPCD
* Check against Min_Slice_width of 2560 (Anusha)
v4:
* #defines for PPR in slice count helper (Gaurav)
v3:
* Simply logic for bpp (DK)
* Limit the valid slice count by max supported by Sink (Manasi)
v2:
* Change the small joiner RAM buffer constant as bspec changed (Manasi)
* rename it as SMALL_JOINER since we are not enabling big joiner yet (Anusha)
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Dhinakaran Pandiyan
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
Reviewed-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_dp.c | 104 +++
drivers/gpu/drm/i915/intel_drv.h | 4 ++
2 files changed, 108 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 55e070b85c02..8380044affed 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -45,6 +45,17 @@
#define DP_DPRX_ESI_LEN 14
+/* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
+#define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
+
+/* DP DSC throughput values used for slice count calculations KPixels/s */
+#define DP_DSC_PEAK_PIXEL_RATE 272
+#define DP_DSC_MAX_ENC_THROUGHPUT_034
+#define DP_DSC_MAX_ENC_THROUGHPUT_140
+
+/* DP DSC FEC Overhead factor = (100 - 2.4)/100 */
+#define DP_DSC_FEC_OVERHEAD_FACTOR 976
+
/* Compliance test status bits */
#define INTEL_DP_RESOLUTION_SHIFT_MASK 0
#define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
@@ -93,6 +104,14 @@ static const struct dp_link_dpll chv_dpll[] = {
{ .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c0 } },
};
+/* Constants for DP DSC configurations */
+static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
+
+/* With Single pipe configuration, HW is capable of supporting maximum
+ * of 4 slices per line.
+ */
+static const u8 valid_dsc_slicecount[] = {1, 2, 4};
+
/**
* intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or
PCH)
* @intel_dp: DP struct
@@ -4162,6 +4181,91 @@ intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8
*sink_irq_vector)
DP_DPRX_ESI_LEN;
}
+u16 intel_dp_dsc_get_output_bpp(int link_clock, uint8_t lane_count,
+ int mode_clock, int mode_hdisplay)
+{
+ u16 bits_per_pixel, max_bpp_small_joiner_ram;
+ int i;
+
+ /*
+* Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
+* (LinkSymbolClock)* 8 * ((100-FECOverhead)/100)*(TimeSlotsPerMTP)
+* FECOverhead = 2.4%, for SST -> TimeSlotsPerMTP is 1,
+* for MST -> TimeSlotsPerMTP has to be calculated
+*/
+ bits_per_pixel = (link_clock * lane_count * 8 *
+ DP_DSC_FEC_OVERHEAD_FACTOR) /
+ mode_clock;
+
+ /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
+ max_bpp_small_joiner_ram = DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER /
+ mode_hdisplay;
+
+ /*
+* Greatest allowed DSC BPP = MIN (output BPP from avaialble Link BW
+* check, output bpp from small joiner RAM check)
+*/
+ bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
+
+ /* Error out if the max bpp is less than smallest allowed valid bpp */
+ if (bits_per_pixel < valid_dsc_bpp[0]) {
+ DRM_DEBUG_KMS("Unsupported BPP %d\n", bits_per_pixel);
+ return 0;
+ }
+
+ /* Find the nearest match in the array of known BPPs from VESA */
+ for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
+ if (bits_per_pixel < valid_dsc_bpp[i + 1])
+ break;
+ }
+ bits_per_pixel = valid_dsc_bpp[i];
+
+ /*
+* Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
+* fractional part is 0
+*/
+ return bits_per_pixel << 4;
+}
+
+u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
+ int mode_clock,
+ int mode_hdisplay)
+{
+ u8 min_slice_count, i;
+ int max_slice_width;
+
+ if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
+ min_slice_count = DIV_ROUND_UP(mode_clock,
+ DP_DSC_MAX_ENC_THROUGHPUT_0);
+ else
+ min_slice_count = DIV_ROUND_UP(mode_clock,
+ DP_DSC_MAX_ENC_THROUGHPUT_1);
+
+ max_slice_width =
[Intel-gfx] [CI 2/7] drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT
This patch defines the DP DSC receiver capability size that gives total number of DP DSC DPCD registers. This also adds a missing #defines for DP DSC support missed in the commit id (ab6a46ea6842ce "Add DPCD definitions for DP 1.4 DSC feature") v3: * MIN_SLICE_WIDTH = 2560 (Anusha) * Define DP_DSC_SLICE_WIDTH_MULTIPLIER = 320 v2: * Add SHIFT define and DECOMPRESSION_EN define missed in prev patch Cc: dri-de...@lists.freedesktop.org Cc: Jani Nikula Cc: Ville Syrjala Cc: Anusha Srivatsa Cc: Gaurav K Singh Signed-off-by: Manasi Navare Reviewed-by: Anusha Srivatsa --- include/drm/drm_dp_helper.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 9ad98e8d9ede..dd33d59739f8 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -231,6 +231,8 @@ #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */ #define DP_DSC_MAX_BITS_PER_PIXEL_HI0x068 /* eDP 1.4 */ +# define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0) +# define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8 #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069 # define DP_DSC_RGB (1 << 0) @@ -279,6 +281,8 @@ # define DP_DSC_THROUGHPUT_MODE_1_1000 (14 << 4) #define DP_DSC_MAX_SLICE_WIDTH 0x06C +#define DP_DSC_MIN_SLICE_WIDTH_VALUE2560 +#define DP_DSC_SLICE_WIDTH_MULTIPLIER 320 #define DP_DSC_SLICE_CAP_2 0x06D # define DP_DSC_16_PER_DP_DSC_SINK (1 << 0) @@ -477,6 +481,7 @@ # define DP_AUX_FRAME_SYNC_VALID (1 << 0) #define DP_DSC_ENABLE 0x160 /* DP 1.4 */ +# define DP_DECOMPRESSION_EN(1 << 0) #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ # define DP_PSR_ENABLE (1 << 0) @@ -965,6 +970,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI #define DP_BRANCH_OUI_HEADER_SIZE 0xc #define DP_RECEIVER_CAP_SIZE 0xf +#define DP_DSC_RECEIVER_CAP_SIZE0xf #define EDP_PSR_RECEIVER_CAP_SIZE 2 #define EDP_DISPLAY_CTL_CAP_SIZE 3 -- 2.18.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/3] drm/i915: Remove HAS_FULL_PPGTT and device_info.ppgtt enum
Quoting Bob Paauwe (2018-10-29 21:39:51) > The distincsion between aliasing, full, and 4 level ppgtt is primarily No, it is not. The distinction is the HW capability of the platform. snb would be doing full-ppgtt but can't handle a mm switch... -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 1/7] drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming
From: Anusha Srivatsa
Add the newly added slice_row_per_frame parameter
in the Picture Parameter Set registers.
This defines the number of vertically stacked slices
in a frame.
Credits to Manasi for noticing bSpec change.
Suggested-by: Manasi Navare
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
Reviewed-by: Manasi Navare
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 69eb573348b3..64cca0a83cf7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10903,6 +10903,7 @@ enum skl_power_gate {
#define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe)_MMIO_PIPE((pipe) -
PIPE_B, \
_ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
_ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
+#define DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame) ((slice_row_per_frame)
<< 20)
#define DSC_SLICE_PER_LINE(slice_per_line)((slice_per_line) << 16)
#define DSC_SLICE_CHUNK_SIZE(slice_chunk_size)
((slice_chunk_size) << 0)
--
2.18.0
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[Intel-gfx] [CI 7/7] drm/dp: Define payload size for DP SDP PPS packet
DP 1.4 spec defines DP secondary data packet for DSC
picture parameter set. This patch defines its payload size
according to the DP 1.4 specification.
Signed-off-by: Manasi Navare
Cc: dri-de...@lists.freedesktop.org
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Reviewed-by: Harry Wentland
---
include/drm/drm_dp_helper.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 7f7f5b965466..730243dd41e2 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1001,6 +1001,7 @@ struct dp_sdp_header {
#define EDP_SDP_HEADER_REVISION_MASK 0x1F
#define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F
+#define DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 0x7F
struct edp_vsc_psr {
struct dp_sdp_header sdp_header;
--
2.18.0
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[Intel-gfx] [CI 6/7] drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported
When DSC is supported we need to validate the modes based on the
maximum supported compressed BPP and maximum supported slice count.
This allows us to allow the modes with pixel clock greater than the
available link BW as long as it meets the compressed BPP
and slice count requirements.
v3:
* Use the macro for dsc sink support (Jani N)
v2:
* Properly comment why we are right shifting the bpp value (Anusha)
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
Reviewed-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_dp.c | 31 ++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8380044affed..6f66a38ba0b2 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -635,9 +635,12 @@ intel_dp_mode_valid(struct drm_connector *connector,
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct intel_connector *intel_connector = to_intel_connector(connector);
struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
+ struct drm_i915_private *dev_priv = to_i915(connector->dev);
int target_clock = mode->clock;
int max_rate, mode_rate, max_lanes, max_link_clock;
int max_dotclk;
+ u16 dsc_max_output_bpp = 0;
+ u8 dsc_slice_count = 0;
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
return MODE_NO_DBLESCAN;
@@ -660,7 +663,33 @@ intel_dp_mode_valid(struct drm_connector *connector,
max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
mode_rate = intel_dp_link_required(target_clock, 18);
- if (mode_rate > max_rate || target_clock > max_dotclk)
+ /*
+* Output bpp is stored in 6.4 format so right shift by 4 to get the
+* integer value since we support only integer values of bpp.
+*/
+ if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
+ drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
+ if (intel_dp_is_edp(intel_dp)) {
+ dsc_max_output_bpp =
+ drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd)
>> 4;
+ dsc_slice_count =
+
drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
+ true);
+ } else {
+ dsc_max_output_bpp =
+ intel_dp_dsc_get_output_bpp(max_link_clock,
+ max_lanes,
+ target_clock,
+ mode->hdisplay) >>
4;
+ dsc_slice_count =
+ intel_dp_dsc_get_slice_count(intel_dp,
+target_clock,
+mode->hdisplay);
+ }
+ }
+
+ if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count))
||
+ target_clock > max_dotclk)
return MODE_CLOCK_HIGH;
if (mode->clock < 1)
--
2.18.0
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/selftest: fix 64K alignment in igt_write_huge
== Series Details == Series: drm/i915/selftest: fix 64K alignment in igt_write_huge URL : https://patchwork.freedesktop.org/series/51705/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/selftest: fix 64K alignment in igt_write_huge +drivers/gpu/drm/i915/selftests/huge_pages.c:1132:29: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/3] drm/i915: Remove HAS_4LVL_PPGTT
We no longer need to differentiate between 4LVL and FULL ppgtt as
the number of bits in the address range provides that information now.
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/i915_drv.h | 2 --
drivers/gpu/drm/i915/i915_pci.c | 4 ++--
drivers/gpu/drm/i915/intel_device_info.h| 1 -
drivers/gpu/drm/i915/selftests/huge_pages.c | 4 ++--
4 files changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b109fc0c29be..5b104dad75d8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2587,8 +2587,6 @@ intel_info(const struct drm_i915_private *dev_priv)
(INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
#define HAS_FULL_PPGTT(dev_priv) \
(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
-#define HAS_4LVL_PPGTT(dev_priv) \
- (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL_4LVL)
#define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
GEM_BUG_ON((sizes) == 0); \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 7fd1150d4baf..fac4c69cb5db 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -400,7 +400,7 @@ static const struct intel_device_info
intel_haswell_gt3_info = {
.page_sizes = I915_GTT_PAGE_SIZE_4K | \
I915_GTT_PAGE_SIZE_2M, \
.has_logical_ring_contexts = 1, \
- .ppgtt = INTEL_PPGTT_FULL_4LVL, \
+ .ppgtt = INTEL_PPGTT_FULL, \
.ppgtt_bits = 48, \
.has_64bit_reloc = 1, \
.has_reset_engine = 1
@@ -522,7 +522,7 @@ static const struct intel_device_info
intel_skylake_gt4_info = {
.has_logical_ring_contexts = 1, \
.has_logical_ring_preemption = 1, \
.has_guc = 1, \
- .ppgtt = INTEL_PPGTT_FULL_4LVL, \
+ .ppgtt = INTEL_PPGTT_FULL, \
.ppgtt_bits = 48, \
.has_reset_engine = 1, \
.has_snoop = true, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 4980da8ccfc3..dc60be4b1435 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -80,7 +80,6 @@ enum intel_ppgtt {
INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
- INTEL_PPGTT_FULL_4LVL,
};
#define DEV_INFO_FOR_EACH_FLAG(func) \
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c
b/drivers/gpu/drm/i915/selftests/huge_pages.c
index 60b012781002..95abf8475464 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -1436,7 +1436,7 @@ static int igt_ppgtt_pin_update(void *arg)
* huge-gtt-pages.
*/
- if (!HAS_4LVL_PPGTT(dev_priv)) {
+ if (INTEL_INFO(dev_priv)->ppgtt_bits <= 32) {
pr_info("Extended range PPGTT not supported, skipping\n");
return 0;
}
@@ -1697,7 +1697,7 @@ int i915_gem_huge_page_mock_selftests(void)
return -ENOMEM;
/* Pretend to be a device which supports the 48b PPGTT */
- mkwrite_device_info(dev_priv)->ppgtt = INTEL_PPGTT_FULL_4LVL;
+ mkwrite_device_info(dev_priv)->ppgtt = INTEL_PPGTT_FULL;
pdev = dev_priv->drm.pdev;
dma_coerce_mask_and_coherent(>dev, DMA_BIT_MASK(39));
--
2.17.1
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[Intel-gfx] [PATCH 3/3] drm/i915: Remove HAS_FULL_PPGTT and device_info.ppgtt enum
The distincsion between aliasing, full, and 4 level ppgtt is primarily
the size of the address range. Now that we have that specified for
each platform, having a separate enum that specifies the ppgtt type is
redundant. A platform either has support for ppgtt or it doesn't.
This means we can now remove the HAS_FULL_PPGTT macro and the devcie
info ppgtt type.
However, there are still a few places where GEN 6's aliasing ppgtt
differences matter. For those cases, it makes just as much sense to
check if we're running on GEN 6 as it does to check a device info flag.
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/i915_drv.c | 7 ++-
drivers/gpu/drm/i915/i915_drv.h | 8 +---
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_pci.c | 6 --
drivers/gpu/drm/i915/intel_device_info.c| 2 +-
drivers/gpu/drm/i915/intel_device_info.h| 9 +
drivers/gpu/drm/i915/selftests/huge_pages.c | 4 ++--
drivers/gpu/drm/i915/selftests/i915_gem_evict.c | 2 +-
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 2 +-
10 files changed, 19 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 393e89e2b309..eafb70407356 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -345,7 +345,12 @@ static int i915_getparam_ioctl(struct drm_device *dev,
void *data,
value = HAS_WT(dev_priv);
break;
case I915_PARAM_HAS_ALIASING_PPGTT:
- value = min_t(int, INTEL_PPGTT(dev_priv), I915_GEM_PPGTT_FULL);
+ if (INTEL_GEN(dev_priv) < 6)
+ value = I915_GEM_PPGTT_NONE;
+ else if (IS_GEN6(dev_priv))
+ value = I915_GEM_PPGTT_ALIASING;
+ else
+ value = I915_GEM_PPGTT_FULL;
break;
case I915_PARAM_HAS_SEMAPHORES:
value = HAS_LEGACY_SEMAPHORES(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5b104dad75d8..3acdda232ea1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2582,11 +2582,13 @@ intel_info(const struct drm_i915_private *dev_priv)
#define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
-#define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt)
+#define INTEL_PPGTT_BITS(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_bits)
#define HAS_PPGTT(dev_priv) \
- (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
+ (INTEL_PPGTT_BITS(dev_priv) != 0)
+/*
#define HAS_FULL_PPGTT(dev_priv) \
- (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
+ (INTEL_PPGTT_BITS(dev_priv) >= 31)
+*/
#define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
GEM_BUG_ON((sizes) == 0); \
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 1853e82cebd5..7bab4754b20c 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -414,7 +414,7 @@ i915_gem_create_context(struct drm_i915_private *dev_priv,
if (IS_ERR(ctx))
return ctx;
- if (HAS_FULL_PPGTT(dev_priv)) {
+ if (INTEL_GEN(dev_priv) > 6) {
struct i915_hw_ppgtt *ppgtt;
ppgtt = i915_ppgtt_create(dev_priv, file_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index e818d3c00bba..1272f7d9e915 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2861,7 +2861,7 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
/* And finally clear the reserved guard page */
ggtt->vm.clear_range(>vm, ggtt->vm.total - PAGE_SIZE, PAGE_SIZE);
- if (INTEL_PPGTT(dev_priv) == INTEL_PPGTT_ALIASING) {
+ if (IS_GEN6(dev_priv)) {
ret = i915_gem_init_aliasing_ppgtt(dev_priv);
if (ret)
goto err;
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index fac4c69cb5db..76d3c96733b0 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -252,7 +252,6 @@ static const struct intel_device_info intel_ironlake_m_info
= {
.has_llc = 1, \
.has_rc6 = 1, \
.has_rc6p = 1, \
- .ppgtt = INTEL_PPGTT_ALIASING, \
.ppgtt_bits = 31, \
GEN_DEFAULT_PIPEOFFSETS, \
GEN_DEFAULT_PAGE_SIZES, \
@@ -298,7 +297,6 @@ static const struct intel_device_info
intel_sandybridge_m_gt2_info = {
.has_llc = 1, \
.has_rc6 = 1, \
.has_rc6p = 1, \
- .ppgtt = INTEL_PPGTT_FULL, \
.ppgtt_bits = 31, \
GEN_DEFAULT_PIPEOFFSETS, \
GEN_DEFAULT_PAGE_SIZES, \
@@ -352,7 +350,6 @@ static const struct intel_device_info intel_valleyview_info
= {
[Intel-gfx] [PATCH 1/3] drm/i915: Make 48bit full ppgtt configuration generic (v7)
48 bit ppgtt device configuration is really just extended address
range full ppgtt and may actually be something other than 48 bits.
Change HAS_FULL_48BIT_PPGTT() to HAS_4LVL_PPGTT() to better
describe that a 4 level walk table extended range PPGTT is being
used. Add a new device info field that specifies the number of
bits to prepare for cases where the range is not 32 or 48 bits.
Also rename other functions and comments from 48bit to 4-level.
Making use of the device info address range for gen6 highlights
simularities in the gen6 and gen8 code paths so move the common
code in to a common function.
v2: Keep HAS_FULL_PPGTT() unchanged (Chris)
v3: Simplify condition in gen8_ppgtt_create() (Chris)
Remove unnecessary line coninuations (Bob)
Rename functions/defines/comments from 48bit to 4lvl (Rodrigo/Bob)
v4: Rename FULL_4LVL_PPGTT to simply 4LVL_PPGTT (Rodrigo)
Be explised in setting vm.total to 1ULL << 32 (Rodrigo)
Gen 7 is 31 bits, not 32 (Chris)
v5: Mock device is 64b(63b) not 48b (Chris)
v6: Rebase to latest drm-tip (Bob)
v7: Combine common code for gen6/gen8 ppgtt create (Chris)
Improve comment on device info field (Chris)
Signed-off-by: Bob Paauwe
CC: Rodrigo Vivi
CC: Michel Thierry
CC: Chris Wilson
---
drivers/gpu/drm/i915/gvt/vgpu.c | 2 +-
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 139 --
drivers/gpu/drm/i915/i915_gem_gtt.h | 4 +-
drivers/gpu/drm/i915/i915_pci.c | 6 +
drivers/gpu/drm/i915/i915_pvinfo.h| 2 +-
drivers/gpu/drm/i915/i915_vgpu.c | 4 +-
drivers/gpu/drm/i915/i915_vgpu.h | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 3 +
drivers/gpu/drm/i915/intel_lrc.c | 6 +-
drivers/gpu/drm/i915/selftests/huge_pages.c | 8 +-
.../gpu/drm/i915/selftests/mock_gem_device.c | 2 +
15 files changed, 90 insertions(+), 95 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index c628be05fbfe..6002ded0042b 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -44,7 +44,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
- vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT;
+ vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_4LVL_PPGTT;
vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 6571044c9286..393e89e2b309 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1367,7 +1367,7 @@ static int i915_driver_init_hw(struct drm_i915_private
*dev_priv)
if (HAS_PPGTT(dev_priv)) {
if (intel_vgpu_active(dev_priv) &&
- !intel_vgpu_has_full_48bit_ppgtt(dev_priv)) {
+ !intel_vgpu_has_4lvl_ppgtt(dev_priv)) {
i915_report_error(dev_priv,
"incompatible vGPU found, support for
isolated ppGTT required\n");
return -ENXIO;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2d7761b8ac07..b109fc0c29be 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2587,7 +2587,7 @@ intel_info(const struct drm_i915_private *dev_priv)
(INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
#define HAS_FULL_PPGTT(dev_priv) \
(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
-#define HAS_FULL_48BIT_PPGTT(dev_priv) \
+#define HAS_4LVL_PPGTT(dev_priv) \
(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL_4LVL)
#define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index b97963db0287..1853e82cebd5 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -307,7 +307,7 @@ static u32 default_desc_template(const struct
drm_i915_private *i915,
desc = GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
address_mode = INTEL_LEGACY_32B_CONTEXT;
- if (ppgtt && i915_vm_is_48bit(>vm))
+ if (ppgtt && i915_vm_is_4lvl(>vm))
address_mode = INTEL_LEGACY_64B_CONTEXT;
desc |= address_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 98d9a1eb1ed2..e818d3c00bba 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -579,14 +579,14 @@
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Poison the CSB after use
== Series Details == Series: drm/i915/execlists: Poison the CSB after use URL : https://patchwork.freedesktop.org/series/51703/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5051 -> Patchwork_10634 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/51703/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10634 that come from known issues: === IGT changes === Issues hit igt@gem_exec_suspend@basic-s3: fi-kbl-soraka: NOTRUN -> INCOMPLETE (fdo#107774, fdo#107556, fdo#107859) igt@kms_flip@basic-flip-vs-modeset: fi-hsw-4770r: PASS -> DMESG-WARN (fdo#105602) igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: PASS -> FAIL (fdo#103167) igt@pm_rpm@module-reload: fi-skl-6600u: PASS -> INCOMPLETE (fdo#107807) fi-glk-j4005: PASS -> DMESG-WARN (fdo#106000) Possible fixes igt@drv_selftest@live_contexts: fi-icl-u: DMESG-FAIL (fdo#108569) -> PASS igt@gem_exec_suspend@basic-s3: fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#107556 https://bugs.freedesktop.org/show_bug.cgi?id=107556 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#107774 https://bugs.freedesktop.org/show_bug.cgi?id=107774 fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807 fdo#107859 https://bugs.freedesktop.org/show_bug.cgi?id=107859 fdo#108569 https://bugs.freedesktop.org/show_bug.cgi?id=108569 == Participating hosts (48 -> 44) == Additional (1): fi-kbl-soraka Missing(5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 == Build changes == * Linux: CI_DRM_5051 -> Patchwork_10634 CI_DRM_5051: 2523b4d2158bc0fc25031aad0def0b4ba04432f2 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4699: 1270ec553741ac20c45178d2b26f9a9562ea565f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10634: 79f7fdf2421a2cfd0f8e6afb694232e961fd1c5b @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 79f7fdf2421a drm/i915/execlists: Poison the CSB after use == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10634/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v6 13/28] drm/i915/dp: Compute DSC pipe config in atomic check
On Mon, Oct 29, 2018 at 10:30:39PM +0200, Ville Syrjälä wrote:
> On Wed, Oct 24, 2018 at 03:28:25PM -0700, Manasi Navare wrote:
> > DSC params like the enable, compressed bpp, slice count and
> > dsc_split are added to the intel_crtc_state. These parameters
> > are set based on the requested mode and available link parameters
> > during the pipe configuration in atomic check phase.
> > These values are then later used to populate the remaining DSC
> > and RC parameters before enbaling DSC in atomic commit.
> >
> > v9:
> > * Rebase on top of drm-tip that now uses fast_narrow config
> > for edp (Manasi)
> > v8:
> > * Check for DSC bpc not 0 (manasi)
> >
> > v7:
> > * Fix indentation in compute_m_n (Manasi)
> >
> > v6 (From Gaurav):
> > * Remove function call of intel_dp_compute_dsc_params() and
> > invoke intel_dp_compute_dsc_params() in the patch where
> > it is defined to fix compilation warning (Gaurav)
> >
> > v5:
> > Add drm_dsc_cfg in intel_crtc_state (Manasi)
> >
> > v4:
> > * Rebase on refactoring of intel_dp_compute_config on tip (Manasi)
> > * Add a comment why we need to check PSR while enabling DSC (Gaurav)
> >
> > v3:
> > * Check PPR > max_cdclock to use 2 VDSC instances (Ville)
> >
> > v2:
> > * Add if-else for eDP/DP (Gaurav)
> >
> > Cc: Jani Nikula
> > Cc: Ville Syrjala
> > Cc: Anusha Srivatsa
> > Cc: Gaurav K Singh
> > Signed-off-by: Manasi Navare
> > Reviewed-by: Anusha Srivatsa
> > Acked-by: Jani Nikula
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 20 +++-
> > drivers/gpu/drm/i915/intel_display.h | 3 +-
> > drivers/gpu/drm/i915/intel_dp.c | 170 ++-
> > drivers/gpu/drm/i915/intel_dp_mst.c | 2 +-
> > 4 files changed, 155 insertions(+), 40 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index fe045abb6472..18737bd82b68 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -6434,7 +6434,7 @@ static int ironlake_fdi_compute_config(struct
> > intel_crtc *intel_crtc,
> >
> > pipe_config->fdi_lanes = lane;
> >
> > - intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
> > + intel_link_compute_m_n(pipe_config->pipe_bpp, 0, lane, fdi_dotclock,
> >link_bw, _config->fdi_m_n, false);
> >
> > ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
> > @@ -6671,17 +6671,25 @@ static void compute_m_n(unsigned int m, unsigned
> > int n,
> > }
> >
> > void
> > -intel_link_compute_m_n(int bits_per_pixel, int nlanes,
> > +intel_link_compute_m_n(int bits_per_pixel, uint16_t compressed_bpp,
> > + int nlanes,
> >int pixel_clock, int link_clock,
> >struct intel_link_m_n *m_n,
> >bool constant_n)
> > {
> > m_n->tu = 64;
> >
> > - compute_m_n(bits_per_pixel * pixel_clock,
> > - link_clock * nlanes * 8,
> > - _n->gmch_m, _n->gmch_n,
> > - constant_n);
> > + /* For DSC, Data M/N calculation uses compressed BPP */
> > + if (compressed_bpp)
> > + compute_m_n(compressed_bpp * pixel_clock,
> > + link_clock * nlanes * 8,
> > + _n->gmch_m, _n->gmch_n,
> > + constant_n);
> > + else
> > + compute_m_n(bits_per_pixel * pixel_clock,
> > + link_clock * nlanes * 8,
> > + _n->gmch_m, _n->gmch_n,
> > + constant_n);
> >
> > compute_m_n(pixel_clock, link_clock,
> > _n->link_m, _n->link_n,
> > diff --git a/drivers/gpu/drm/i915/intel_display.h
> > b/drivers/gpu/drm/i915/intel_display.h
> > index 5d50decbcbb5..b0b23e1e9392 100644
> > --- a/drivers/gpu/drm/i915/intel_display.h
> > +++ b/drivers/gpu/drm/i915/intel_display.h
> > @@ -407,7 +407,8 @@ struct intel_link_m_n {
> > (__i)++) \
> > for_each_if(plane)
> >
> > -void intel_link_compute_m_n(int bpp, int nlanes,
> > +void intel_link_compute_m_n(int bpp, uint16_t compressed_bpp,
> > + int nlanes,
> > int pixel_clock, int link_clock,
> > struct intel_link_m_n *m_n,
> > bool constant_n);
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 6f66a38ba0b2..a88f9371dd32 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -47,6 +47,8 @@
> >
> > /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
> > #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
> > +#define DP_DSC_MIN_SUPPORTED_BPC 8
> > +#define DP_DSC_MAX_SUPPORTED_BPC 10
> >
> > /* DP DSC throughput values used for slice count calculations KPixels/s */
> > #define DP_DSC_PEAK_PIXEL_RATE 272
> > @@ -1924,6
Re: [Intel-gfx] [PATCH v6 27/28] drm/i915/dsc: Add Per connector debugfs node for DSC support/enable
On Mon, Oct 29, 2018 at 10:39:21PM +0200, Ville Syrjälä wrote:
> On Wed, Oct 24, 2018 at 03:28:39PM -0700, Manasi Navare wrote:
> > DSC can be supported per DP connector. This patch adds a per connector
> > debugfs node to expose DSC support capability by the kernel.
> > The same node can be used from userspace to force DSC enable.
>
> Why is the force_dsc thing split between two patches so strangely?
This patch just defines the force_dsc and sets it through the debugfs
node. But how it configures DSC during atomic check is moved to a
separate patch.
Would you prefer having that integrated with this patch itself?
Manasi
>
> >
> > v2:
> > * Use kstrtobool_from_user to avoid explicit error checking (Lyude)
> > * Rebase on drm-tip (Manasi)
> >
> > Cc: Rodrigo Vivi
> > Cc: Ville Syrjala
> > Cc: Anusha Srivatsa
> > Cc: Lyude Paul
> > Signed-off-by: Manasi Navare
> > Reviewed-by: Lyude Paul
> > ---
> > drivers/gpu/drm/i915/i915_debugfs.c | 71 -
> > drivers/gpu/drm/i915/intel_dp.c | 1 +
> > drivers/gpu/drm/i915/intel_drv.h| 3 ++
> > 3 files changed, 74 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 5cadfcd03ea9..6e631f08dd4b 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -4999,6 +4999,72 @@ static int i915_hdcp_sink_capability_show(struct
> > seq_file *m, void *data)
> > }
> > DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability);
> >
> > +static int i915_dsc_support_show(struct seq_file *m, void *data)
> > +{
> > + struct drm_connector *connector = m->private;
> > + struct intel_encoder *encoder = intel_attached_encoder(connector);
> > + struct intel_dp *intel_dp =
> > + enc_to_intel_dp(>base);
> > + struct intel_crtc *crtc;
> > + struct intel_crtc_state *crtc_state;
> > +
> > + crtc = to_intel_crtc(encoder->base.crtc);
> > + crtc_state = to_intel_crtc_state(crtc->base.state);
> > + drm_modeset_lock(>base.mutex, NULL);
> > + seq_printf(m, "Enabled: %s\n",
> > + yesno(crtc_state->dsc_params.compression_enable));
> > + seq_printf(m, "Supported: %s\n",
> > + yesno(drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)));
> > + drm_modeset_unlock(>base.mutex);
> > +
> > + return 0;
> > +}
> > +
> > +static ssize_t i915_dsc_support_write(struct file *file,
> > + const char __user *ubuf,
> > + size_t len, loff_t *offp)
> > +{
> > + bool dsc_enable = false;
> > + int ret;
> > + struct drm_connector *connector =
> > + ((struct seq_file *)file->private_data)->private;
> > + struct intel_encoder *encoder = intel_attached_encoder(connector);
> > + struct intel_dp *intel_dp = enc_to_intel_dp(>base);
> > +
> > + if (len == 0)
> > + return 0;
> > +
> > + DRM_DEBUG_DRIVER("Copied %d bytes from user to force DSC\n",
> > +(unsigned int)len);
> > +
> > + ret = kstrtobool_from_user(ubuf, len, _enable);
> > + if (ret < 0)
> > + return ret;
> > +
> > + DRM_DEBUG_DRIVER("Got %s for DSC Enable\n",
> > +(dsc_enable) ? "true" : "false");
> > + intel_dp->force_dsc_en = dsc_enable;
> > +
> > + *offp += len;
> > + return len;
> > +}
> > +
> > +static int i915_dsc_support_open(struct inode *inode,
> > +struct file *file)
> > +{
> > + return single_open(file, i915_dsc_support_show,
> > + inode->i_private);
> > +}
> > +
> > +static const struct file_operations i915_dsc_support_fops = {
> > + .owner = THIS_MODULE,
> > + .open = i915_dsc_support_open,
> > + .read = seq_read,
> > + .llseek = seq_lseek,
> > + .release = single_release,
> > + .write = i915_dsc_support_write
> > +};
> > +
> > /**
> > * i915_debugfs_connector_add - add i915 specific connector debugfs files
> > * @connector: pointer to a registered drm_connector
> > @@ -5017,9 +5083,12 @@ int i915_debugfs_connector_add(struct drm_connector
> > *connector)
> > return -ENODEV;
> >
> > if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
> > - connector->connector_type == DRM_MODE_CONNECTOR_eDP)
> > + connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
> > debugfs_create_file("i915_dpcd", S_IRUGO, root,
> > connector, _dpcd_fops);
> > + debugfs_create_file("i915_dsc_support", S_IRUGO, root,
> > + connector, _dsc_support_fops);
> > + }
> >
> > if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
> > debugfs_create_file("i915_panel_timings", S_IRUGO, root,
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 72e6605f0ed7..0b5939992c2b 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Test vm isolation (rev3)
== Series Details == Series: drm/i915/selftests: Test vm isolation (rev3) URL : https://patchwork.freedesktop.org/series/51689/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5047_full -> Patchwork_10629_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_10629_full that come from known issues: === IGT changes === Issues hit igt@drv_suspend@shrink: shard-snb: PASS -> INCOMPLETE (fdo#106886, fdo#105411) igt@gem_exec_reloc@basic-cpu-gtt: shard-apl: PASS -> DMESG-WARN (fdo#103558, fdo#105602) +2 igt@gem_userptr_blits@unsync-unmap: shard-glk: PASS -> DMESG-WARN (fdo#105763, fdo#106538) +1 igt@kms_busy@extended-modeset-hang-newfb-render-c: shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) igt@kms_ccs@pipe-a-crc-sprite-planes-basic: shard-glk: PASS -> FAIL (fdo#108145) igt@kms_cursor_crc@cursor-128x42-offscreen: shard-skl: PASS -> FAIL (fdo#103232) igt@kms_cursor_crc@cursor-256x256-random: shard-glk: PASS -> FAIL (fdo#103232) igt@kms_cursor_crc@cursor-256x85-onscreen: shard-apl: PASS -> FAIL (fdo#103232) +4 igt@kms_cursor_crc@cursor-64x64-suspend: shard-skl: PASS -> INCOMPLETE (fdo#107773, fdo#104108) igt@kms_draw_crc@draw-method-rgb565-pwrite-ytiled: shard-glk: PASS -> FAIL (fdo#103184) +1 igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-untiled: shard-skl: PASS -> FAIL (fdo#103184, fdo#103232) igt@kms_fbcon_fbt@psr-suspend: shard-skl: NOTRUN -> FAIL (fdo#107882) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu: shard-skl: PASS -> FAIL (fdo#105682) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move: shard-glk: PASS -> FAIL (fdo#103167) igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff: shard-glk: PASS -> DMESG-FAIL (fdo#106538, fdo#103167) igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-blt: shard-skl: PASS -> FAIL (fdo#103167) +1 igt@kms_plane@pixel-format-pipe-b-planes: shard-skl: NOTRUN -> DMESG-FAIL (fdo#103166, fdo#106885) +1 igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb: shard-skl: NOTRUN -> FAIL (fdo#108145) +1 igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: shard-skl: NOTRUN -> FAIL (fdo#107815) igt@kms_plane_multiple@atomic-pipe-a-tiling-y: shard-glk: PASS -> FAIL (fdo#103166) igt@kms_plane_multiple@atomic-pipe-b-tiling-y: shard-apl: PASS -> FAIL (fdo#103166) igt@kms_setmode@basic: shard-kbl: PASS -> FAIL (fdo#99912) Possible fixes igt@kms_busy@extended-modeset-hang-newfb-render-c: shard-hsw: DMESG-WARN (fdo#107956) -> PASS igt@kms_color@pipe-a-degamma: shard-apl: FAIL (fdo#108145, fdo#104782) -> PASS igt@kms_cursor_crc@cursor-128x128-suspend: shard-apl: FAIL (fdo#103232, fdo#103191) -> PASS igt@kms_cursor_crc@cursor-64x21-sliding: shard-apl: FAIL (fdo#103232) -> PASS +1 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt: shard-apl: FAIL (fdo#103167) -> PASS +1 igt@kms_frontbuffer_tracking@fbc-1p-rte: shard-glk: FAIL (fdo#105682, fdo#103167) -> PASS igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-move: shard-glk: FAIL (fdo#103167) -> PASS +4 igt@kms_frontbuffer_tracking@psr-suspend: shard-skl: INCOMPLETE (fdo#107773, fdo#106978, fdo#104108) -> PASS igt@kms_mmap_write_crc: shard-kbl: DMESG-WARN (fdo#105345, fdo#103313) -> PASS igt@kms_plane@plane-position-covered-pipe-a-planes: shard-glk: FAIL (fdo#103166) -> PASS +1 shard-apl: FAIL (fdo#103166) -> PASS +1 igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max: shard-glk: FAIL (fdo#108145) -> PASS fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103184 https://bugs.freedesktop.org/show_bug.cgi?id=103184 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232 fdo#103313 https://bugs.freedesktop.org/show_bug.cgi?id=103313 fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558 fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108 fdo#104782 https://bugs.freedesktop.org/show_bug.cgi?id=104782 fdo#105345 https://bugs.freedesktop.org/show_bug.cgi?id=105345 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602 fdo#105682
Re: [Intel-gfx] [PATCH] drm/i915/selftest: test aligned offsets for 64K
Quoting Matthew Auld (2018-10-29 20:37:34)
> When using softpin it's not enough to just pad the vma size, we also
> need to ensure the vma offset is at the start of the pt boundary, if we
> plan to utilize 64K pages. Therefore to improve test coverage we should
> use both aligned and unaligned gtt offsets in igt_write_huge.
>
> Suggested-by: Chris Wilson
> Signed-off-by: Matthew Auld
> Cc: Chris Wilson
> ---
> drivers/gpu/drm/i915/selftests/huge_pages.c | 22 +
> 1 file changed, 18 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c
> b/drivers/gpu/drm/i915/selftests/huge_pages.c
> index 256001b00e32..26c065c8d2c0 100644
> --- a/drivers/gpu/drm/i915/selftests/huge_pages.c
> +++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
> @@ -1135,7 +1135,8 @@ static int igt_write_huge(struct i915_gem_context *ctx,
> n = 0;
> for_each_engine(engine, i915, id) {
> if (!intel_engine_can_store_dword(engine)) {
> - pr_info("store-dword-imm not supported on
> engine=%u\n", id);
> + pr_info("store-dword-imm not supported on
> engine=%u\n",
> + id);
> continue;
> }
> engines[n++] = engine;
> @@ -1167,17 +1168,30 @@ static int igt_write_huge(struct i915_gem_context
> *ctx,
> engine = engines[order[i] % n];
> i = (i + 1) % (n * I915_NUM_ENGINES);
>
> - err = __igt_write_huge(ctx, engine, obj, size, offset_low,
> dword, num + 1);
> + /*
> +* In order to utilize 64K pages we need to both pad the vma
> +* size and ensure the vma offset is at the start of the pt
> +* boundary, however to improve coverage we opt for testing
> both
> +* aligned and unaligned offsets.
> +*/
> + if (obj->mm.page_sizes.sg & I915_GTT_PAGE_SIZE_64K)
> + offset_low = round_down(offset_low,
> + I915_GTT_PAGE_SIZE_2M);
> +
> + err = __igt_write_huge(ctx, engine, obj, size, offset_low,
> + dword, num + 1);
> if (err)
> break;
>
> - err = __igt_write_huge(ctx, engine, obj, size, offset_high,
> dword, num + 1);
> + err = __igt_write_huge(ctx, engine, obj, size, offset_high,
> + dword, num + 1);
Gotcha, alternating between an aligned address and unaligned address.
Reviewed-by: Chris Wilson
-Chris
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[Intel-gfx] [PATCH i-g-t] igt/gem_tiled_fence_blits: Remember to mark up fence blits
Older platforms require fence registers to perform blits, and so
userspace is expected to mark up the objects to request fences be
assigned.
Fixes: ff2db94acb53 ("igt/gem_tiled_fence_blits: Remove libdrm_intel
dependence")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108591
Signed-off-by: Chris Wilson
---
tests/i915/gem_tiled_fence_blits.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/tests/i915/gem_tiled_fence_blits.c
b/tests/i915/gem_tiled_fence_blits.c
index 7560fa52..e40a7b43 100644
--- a/tests/i915/gem_tiled_fence_blits.c
+++ b/tests/i915/gem_tiled_fence_blits.c
@@ -141,6 +141,8 @@ static void run_test(int fd, int count)
memset(reloc, 0, sizeof(reloc));
memset(obj, 0, sizeof(obj));
+ obj[0].flags = EXEC_OBJECT_NEEDS_FENCE;
+ obj[1].flags = EXEC_OBJECT_NEEDS_FENCE;
obj[2].handle = create_batch(fd, reloc);
obj[2].relocs_ptr = to_user_pointer(reloc);
obj[2].relocation_count = ARRAY_SIZE(reloc);
--
2.19.1
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v4,1/2] drm: Add drm_any_plane_has_format()
== Series Details == Series: series starting with [v4,1/2] drm: Add drm_any_plane_has_format() URL : https://patchwork.freedesktop.org/series/51700/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5050 -> Patchwork_10633 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/51700/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10633 that come from known issues: === IGT changes === Issues hit igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: PASS -> FAIL (fdo#103167) Possible fixes igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: fi-byt-clapper: FAIL (fdo#107362, fdo#103191) -> PASS Warnings igt@drv_selftest@live_contexts: fi-icl-u: INCOMPLETE (fdo#108535) -> DMESG-FAIL (fdo#108569) fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#108535 https://bugs.freedesktop.org/show_bug.cgi?id=108535 fdo#108569 https://bugs.freedesktop.org/show_bug.cgi?id=108569 == Participating hosts (49 -> 43) == Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-gdg-551 == Build changes == * Linux: CI_DRM_5050 -> Patchwork_10633 CI_DRM_5050: bc6dcb88d08376d667bcb0fa1e5b8d06ac2251f2 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4699: 1270ec553741ac20c45178d2b26f9a9562ea565f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10633: 9053e8add523c4bc75de6a9f83b5becea96bb19c @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 9053e8add523 drm/i915: Eliminate the horrendous format check code cce1ebf50ced drm: Add drm_any_plane_has_format() == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10633/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Move VIDEO_DIP_CTL definitions to their right place.
On Fri, 2018-10-05 at 12:03 -0700, Manasi Navare wrote:
> On Fri, Oct 05, 2018 at 11:56:43AM -0700, Dhinakaran Pandiyan wrote:
> > The bits weren't defined in descending order.
> > v2: Move definitions in a separate patch (Manasi)
> >
> > Cc: Manasi Navare
> > Signed-off-by: Dhinakaran Pandiyan
>
> Reviewed-by: Manasi Navare
Thanks for the reviews, pushed.
-DK
>
> Manasi
>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 19 +--
> > 1 file changed, 9 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 61148b9a4a8e..a98b95922818 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4584,6 +4584,15 @@ enum {
> > #define VIDEO_DIP_FREQ_2VSYNC(2 << 16)
> > #define VIDEO_DIP_FREQ_MASK (3 << 16)
> > /* HSW and later: */
> > +#define DRM_DIP_ENABLE (1 << 28)
> > +#define PSR_VSC_BIT_7_SET(1 << 27)
> > +#define VSC_SELECT_MASK (0x3 << 25)
> > +#define VSC_SELECT_SHIFT 25
> > +#define VSC_DIP_HW_HEA_DATA (0 << 25)
> > +#define VSC_DIP_HW_HEA_SW_DATA (1 << 25)
> > +#define VSC_DIP_HW_DATA_SW_HEA (2 << 25)
> > +#define VSC_DIP_SW_HEA_DATA (3 << 25)
> > +#define VDIP_ENABLE_PPS (1 << 24)
> > #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
> > #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
> > #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
> > @@ -4591,16 +4600,6 @@ enum {
> > #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
> > #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
> >
> > -#define DRM_DIP_ENABLE(1 << 28)
> > -#define PSR_VSC_BIT_7_SET (1 << 27)
> > -#define VSC_SELECT_MASK (0x3 << 25)
> > -#define VSC_SELECT_SHIFT 25
> > -#define VSC_DIP_HW_HEA_DATA (0 << 25)
> > -#define VSC_DIP_HW_HEA_SW_DATA(1 << 25)
> > -#define VSC_DIP_HW_DATA_SW_HEA(2 << 25)
> > -#define VSC_DIP_SW_HEA_DATA (3 << 25)
> > -#define VDIP_ENABLE_PPS (1 << 24)
> > -
> > /* Panel power sequencing */
> > #define PPS_BASE 0x61200
> > #define VLV_PPS_BASE (VLV_DISPLAY_BASE +
> > PPS_BASE)
> > --
> > 2.17.1
> >
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Re: [Intel-gfx] [PATCH v6 27/28] drm/i915/dsc: Add Per connector debugfs node for DSC support/enable
On Wed, Oct 24, 2018 at 03:28:39PM -0700, Manasi Navare wrote:
> DSC can be supported per DP connector. This patch adds a per connector
> debugfs node to expose DSC support capability by the kernel.
> The same node can be used from userspace to force DSC enable.
Why is the force_dsc thing split between two patches so strangely?
>
> v2:
> * Use kstrtobool_from_user to avoid explicit error checking (Lyude)
> * Rebase on drm-tip (Manasi)
>
> Cc: Rodrigo Vivi
> Cc: Ville Syrjala
> Cc: Anusha Srivatsa
> Cc: Lyude Paul
> Signed-off-by: Manasi Navare
> Reviewed-by: Lyude Paul
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 71 -
> drivers/gpu/drm/i915/intel_dp.c | 1 +
> drivers/gpu/drm/i915/intel_drv.h| 3 ++
> 3 files changed, 74 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 5cadfcd03ea9..6e631f08dd4b 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -4999,6 +4999,72 @@ static int i915_hdcp_sink_capability_show(struct
> seq_file *m, void *data)
> }
> DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability);
>
> +static int i915_dsc_support_show(struct seq_file *m, void *data)
> +{
> + struct drm_connector *connector = m->private;
> + struct intel_encoder *encoder = intel_attached_encoder(connector);
> + struct intel_dp *intel_dp =
> + enc_to_intel_dp(>base);
> + struct intel_crtc *crtc;
> + struct intel_crtc_state *crtc_state;
> +
> + crtc = to_intel_crtc(encoder->base.crtc);
> + crtc_state = to_intel_crtc_state(crtc->base.state);
> + drm_modeset_lock(>base.mutex, NULL);
> + seq_printf(m, "Enabled: %s\n",
> +yesno(crtc_state->dsc_params.compression_enable));
> + seq_printf(m, "Supported: %s\n",
> +yesno(drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)));
> + drm_modeset_unlock(>base.mutex);
> +
> + return 0;
> +}
> +
> +static ssize_t i915_dsc_support_write(struct file *file,
> + const char __user *ubuf,
> + size_t len, loff_t *offp)
> +{
> + bool dsc_enable = false;
> + int ret;
> + struct drm_connector *connector =
> + ((struct seq_file *)file->private_data)->private;
> + struct intel_encoder *encoder = intel_attached_encoder(connector);
> + struct intel_dp *intel_dp = enc_to_intel_dp(>base);
> +
> + if (len == 0)
> + return 0;
> +
> + DRM_DEBUG_DRIVER("Copied %d bytes from user to force DSC\n",
> + (unsigned int)len);
> +
> + ret = kstrtobool_from_user(ubuf, len, _enable);
> + if (ret < 0)
> + return ret;
> +
> + DRM_DEBUG_DRIVER("Got %s for DSC Enable\n",
> + (dsc_enable) ? "true" : "false");
> + intel_dp->force_dsc_en = dsc_enable;
> +
> + *offp += len;
> + return len;
> +}
> +
> +static int i915_dsc_support_open(struct inode *inode,
> + struct file *file)
> +{
> + return single_open(file, i915_dsc_support_show,
> +inode->i_private);
> +}
> +
> +static const struct file_operations i915_dsc_support_fops = {
> + .owner = THIS_MODULE,
> + .open = i915_dsc_support_open,
> + .read = seq_read,
> + .llseek = seq_lseek,
> + .release = single_release,
> + .write = i915_dsc_support_write
> +};
> +
> /**
> * i915_debugfs_connector_add - add i915 specific connector debugfs files
> * @connector: pointer to a registered drm_connector
> @@ -5017,9 +5083,12 @@ int i915_debugfs_connector_add(struct drm_connector
> *connector)
> return -ENODEV;
>
> if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
> - connector->connector_type == DRM_MODE_CONNECTOR_eDP)
> + connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
> debugfs_create_file("i915_dpcd", S_IRUGO, root,
> connector, _dpcd_fops);
> + debugfs_create_file("i915_dsc_support", S_IRUGO, root,
> + connector, _dsc_support_fops);
> + }
>
> if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
> debugfs_create_file("i915_panel_timings", S_IRUGO, root,
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 72e6605f0ed7..0b5939992c2b 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2287,6 +2287,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
> return false;
>
> + DRM_DEBUG_KMS("Force DSC en = %d\n", intel_dp->force_dsc_en);
> if (!intel_dp_compute_link_config(encoder, pipe_config))
> return false;
>
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
>
[Intel-gfx] [PATCH] drm/i915/selftest: test aligned offsets for 64K
When using softpin it's not enough to just pad the vma size, we also
need to ensure the vma offset is at the start of the pt boundary, if we
plan to utilize 64K pages. Therefore to improve test coverage we should
use both aligned and unaligned gtt offsets in igt_write_huge.
Suggested-by: Chris Wilson
Signed-off-by: Matthew Auld
Cc: Chris Wilson
---
drivers/gpu/drm/i915/selftests/huge_pages.c | 22 +
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c
b/drivers/gpu/drm/i915/selftests/huge_pages.c
index 256001b00e32..26c065c8d2c0 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -1135,7 +1135,8 @@ static int igt_write_huge(struct i915_gem_context *ctx,
n = 0;
for_each_engine(engine, i915, id) {
if (!intel_engine_can_store_dword(engine)) {
- pr_info("store-dword-imm not supported on engine=%u\n",
id);
+ pr_info("store-dword-imm not supported on engine=%u\n",
+ id);
continue;
}
engines[n++] = engine;
@@ -1167,17 +1168,30 @@ static int igt_write_huge(struct i915_gem_context *ctx,
engine = engines[order[i] % n];
i = (i + 1) % (n * I915_NUM_ENGINES);
- err = __igt_write_huge(ctx, engine, obj, size, offset_low,
dword, num + 1);
+ /*
+* In order to utilize 64K pages we need to both pad the vma
+* size and ensure the vma offset is at the start of the pt
+* boundary, however to improve coverage we opt for testing both
+* aligned and unaligned offsets.
+*/
+ if (obj->mm.page_sizes.sg & I915_GTT_PAGE_SIZE_64K)
+ offset_low = round_down(offset_low,
+ I915_GTT_PAGE_SIZE_2M);
+
+ err = __igt_write_huge(ctx, engine, obj, size, offset_low,
+ dword, num + 1);
if (err)
break;
- err = __igt_write_huge(ctx, engine, obj, size, offset_high,
dword, num + 1);
+ err = __igt_write_huge(ctx, engine, obj, size, offset_high,
+ dword, num + 1);
if (err)
break;
if (igt_timeout(end_time,
"%s timed out on engine=%u, offset_low=%llx
offset_high=%llx, max_page_size=%x\n",
- __func__, engine->id, offset_low, offset_high,
max_page_size))
+ __func__, engine->id, offset_low, offset_high,
+ max_page_size))
break;
}
--
2.17.2
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Re: [Intel-gfx] [PATCH v6 13/28] drm/i915/dp: Compute DSC pipe config in atomic check
On Mon, Oct 29, 2018 at 10:30:39PM +0200, Ville Syrjälä wrote:
> On Wed, Oct 24, 2018 at 03:28:25PM -0700, Manasi Navare wrote:
> > DSC params like the enable, compressed bpp, slice count and
> > dsc_split are added to the intel_crtc_state. These parameters
> > are set based on the requested mode and available link parameters
> > during the pipe configuration in atomic check phase.
> > These values are then later used to populate the remaining DSC
> > and RC parameters before enbaling DSC in atomic commit.
> >
> > v9:
> > * Rebase on top of drm-tip that now uses fast_narrow config
> > for edp (Manasi)
> > v8:
> > * Check for DSC bpc not 0 (manasi)
> >
> > v7:
> > * Fix indentation in compute_m_n (Manasi)
> >
> > v6 (From Gaurav):
> > * Remove function call of intel_dp_compute_dsc_params() and
> > invoke intel_dp_compute_dsc_params() in the patch where
> > it is defined to fix compilation warning (Gaurav)
> >
> > v5:
> > Add drm_dsc_cfg in intel_crtc_state (Manasi)
> >
> > v4:
> > * Rebase on refactoring of intel_dp_compute_config on tip (Manasi)
> > * Add a comment why we need to check PSR while enabling DSC (Gaurav)
> >
> > v3:
> > * Check PPR > max_cdclock to use 2 VDSC instances (Ville)
> >
> > v2:
> > * Add if-else for eDP/DP (Gaurav)
> >
> > Cc: Jani Nikula
> > Cc: Ville Syrjala
> > Cc: Anusha Srivatsa
> > Cc: Gaurav K Singh
> > Signed-off-by: Manasi Navare
> > Reviewed-by: Anusha Srivatsa
> > Acked-by: Jani Nikula
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 20 +++-
> > drivers/gpu/drm/i915/intel_display.h | 3 +-
> > drivers/gpu/drm/i915/intel_dp.c | 170 ++-
> > drivers/gpu/drm/i915/intel_dp_mst.c | 2 +-
> > 4 files changed, 155 insertions(+), 40 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index fe045abb6472..18737bd82b68 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -6434,7 +6434,7 @@ static int ironlake_fdi_compute_config(struct
> > intel_crtc *intel_crtc,
> >
> > pipe_config->fdi_lanes = lane;
> >
> > - intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
> > + intel_link_compute_m_n(pipe_config->pipe_bpp, 0, lane, fdi_dotclock,
> >link_bw, _config->fdi_m_n, false);
> >
> > ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
> > @@ -6671,17 +6671,25 @@ static void compute_m_n(unsigned int m, unsigned
> > int n,
> > }
> >
> > void
> > -intel_link_compute_m_n(int bits_per_pixel, int nlanes,
> > +intel_link_compute_m_n(int bits_per_pixel, uint16_t compressed_bpp,
> > + int nlanes,
> >int pixel_clock, int link_clock,
> >struct intel_link_m_n *m_n,
> >bool constant_n)
> > {
> > m_n->tu = 64;
> >
> > - compute_m_n(bits_per_pixel * pixel_clock,
> > - link_clock * nlanes * 8,
> > - _n->gmch_m, _n->gmch_n,
> > - constant_n);
> > + /* For DSC, Data M/N calculation uses compressed BPP */
> > + if (compressed_bpp)
> > + compute_m_n(compressed_bpp * pixel_clock,
> > + link_clock * nlanes * 8,
> > + _n->gmch_m, _n->gmch_n,
> > + constant_n);
> > + else
> > + compute_m_n(bits_per_pixel * pixel_clock,
> > + link_clock * nlanes * 8,
> > + _n->gmch_m, _n->gmch_n,
> > + constant_n);
> >
> > compute_m_n(pixel_clock, link_clock,
> > _n->link_m, _n->link_n,
> > diff --git a/drivers/gpu/drm/i915/intel_display.h
> > b/drivers/gpu/drm/i915/intel_display.h
> > index 5d50decbcbb5..b0b23e1e9392 100644
> > --- a/drivers/gpu/drm/i915/intel_display.h
> > +++ b/drivers/gpu/drm/i915/intel_display.h
> > @@ -407,7 +407,8 @@ struct intel_link_m_n {
> > (__i)++) \
> > for_each_if(plane)
> >
> > -void intel_link_compute_m_n(int bpp, int nlanes,
> > +void intel_link_compute_m_n(int bpp, uint16_t compressed_bpp,
> > + int nlanes,
> > int pixel_clock, int link_clock,
> > struct intel_link_m_n *m_n,
> > bool constant_n);
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 6f66a38ba0b2..a88f9371dd32 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -47,6 +47,8 @@
> >
> > /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
> > #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
> > +#define DP_DSC_MIN_SUPPORTED_BPC 8
> > +#define DP_DSC_MAX_SUPPORTED_BPC 10
> >
> > /* DP DSC throughput values used for slice count calculations KPixels/s */
> > #define DP_DSC_PEAK_PIXEL_RATE 272
> > @@ -1924,6
Re: [Intel-gfx] [PATCH v6 13/28] drm/i915/dp: Compute DSC pipe config in atomic check
On Wed, Oct 24, 2018 at 03:28:25PM -0700, Manasi Navare wrote:
> DSC params like the enable, compressed bpp, slice count and
> dsc_split are added to the intel_crtc_state. These parameters
> are set based on the requested mode and available link parameters
> during the pipe configuration in atomic check phase.
> These values are then later used to populate the remaining DSC
> and RC parameters before enbaling DSC in atomic commit.
>
> v9:
> * Rebase on top of drm-tip that now uses fast_narrow config
> for edp (Manasi)
> v8:
> * Check for DSC bpc not 0 (manasi)
>
> v7:
> * Fix indentation in compute_m_n (Manasi)
>
> v6 (From Gaurav):
> * Remove function call of intel_dp_compute_dsc_params() and
> invoke intel_dp_compute_dsc_params() in the patch where
> it is defined to fix compilation warning (Gaurav)
>
> v5:
> Add drm_dsc_cfg in intel_crtc_state (Manasi)
>
> v4:
> * Rebase on refactoring of intel_dp_compute_config on tip (Manasi)
> * Add a comment why we need to check PSR while enabling DSC (Gaurav)
>
> v3:
> * Check PPR > max_cdclock to use 2 VDSC instances (Ville)
>
> v2:
> * Add if-else for eDP/DP (Gaurav)
>
> Cc: Jani Nikula
> Cc: Ville Syrjala
> Cc: Anusha Srivatsa
> Cc: Gaurav K Singh
> Signed-off-by: Manasi Navare
> Reviewed-by: Anusha Srivatsa
> Acked-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_display.c | 20 +++-
> drivers/gpu/drm/i915/intel_display.h | 3 +-
> drivers/gpu/drm/i915/intel_dp.c | 170 ++-
> drivers/gpu/drm/i915/intel_dp_mst.c | 2 +-
> 4 files changed, 155 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index fe045abb6472..18737bd82b68 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6434,7 +6434,7 @@ static int ironlake_fdi_compute_config(struct
> intel_crtc *intel_crtc,
>
> pipe_config->fdi_lanes = lane;
>
> - intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
> + intel_link_compute_m_n(pipe_config->pipe_bpp, 0, lane, fdi_dotclock,
> link_bw, _config->fdi_m_n, false);
>
> ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
> @@ -6671,17 +6671,25 @@ static void compute_m_n(unsigned int m, unsigned int
> n,
> }
>
> void
> -intel_link_compute_m_n(int bits_per_pixel, int nlanes,
> +intel_link_compute_m_n(int bits_per_pixel, uint16_t compressed_bpp,
> +int nlanes,
> int pixel_clock, int link_clock,
> struct intel_link_m_n *m_n,
> bool constant_n)
> {
> m_n->tu = 64;
>
> - compute_m_n(bits_per_pixel * pixel_clock,
> - link_clock * nlanes * 8,
> - _n->gmch_m, _n->gmch_n,
> - constant_n);
> + /* For DSC, Data M/N calculation uses compressed BPP */
> + if (compressed_bpp)
> + compute_m_n(compressed_bpp * pixel_clock,
> + link_clock * nlanes * 8,
> + _n->gmch_m, _n->gmch_n,
> + constant_n);
> + else
> + compute_m_n(bits_per_pixel * pixel_clock,
> + link_clock * nlanes * 8,
> + _n->gmch_m, _n->gmch_n,
> + constant_n);
>
> compute_m_n(pixel_clock, link_clock,
> _n->link_m, _n->link_n,
> diff --git a/drivers/gpu/drm/i915/intel_display.h
> b/drivers/gpu/drm/i915/intel_display.h
> index 5d50decbcbb5..b0b23e1e9392 100644
> --- a/drivers/gpu/drm/i915/intel_display.h
> +++ b/drivers/gpu/drm/i915/intel_display.h
> @@ -407,7 +407,8 @@ struct intel_link_m_n {
>(__i)++) \
> for_each_if(plane)
>
> -void intel_link_compute_m_n(int bpp, int nlanes,
> +void intel_link_compute_m_n(int bpp, uint16_t compressed_bpp,
> + int nlanes,
> int pixel_clock, int link_clock,
> struct intel_link_m_n *m_n,
> bool constant_n);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 6f66a38ba0b2..a88f9371dd32 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -47,6 +47,8 @@
>
> /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
> #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
> +#define DP_DSC_MIN_SUPPORTED_BPC 8
> +#define DP_DSC_MAX_SUPPORTED_BPC 10
>
> /* DP DSC throughput values used for slice count calculations KPixels/s */
> #define DP_DSC_PEAK_PIXEL_RATE 272
> @@ -1924,6 +1926,16 @@ static int intel_dp_compute_bpp(struct intel_dp
> *intel_dp,
> }
> }
>
> + /* If DSC is supported, use the max value reported by panel */
> + if (INTEL_GEN(dev_priv) >= 10 &&
> +
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915/gtt: Record the scratch pte
== Series Details == Series: series starting with [CI,1/2] drm/i915/gtt: Record the scratch pte URL : https://patchwork.freedesktop.org/series/51698/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5050 -> Patchwork_10632 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/51698/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10632 that come from known issues: === IGT changes === Issues hit igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: PASS -> DMESG-WARN (fdo#102614) igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence: fi-byt-clapper: PASS -> FAIL (fdo#103191, fdo#107362) Possible fixes igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: fi-byt-clapper: FAIL (fdo#103191, fdo#107362) -> PASS Warnings igt@drv_selftest@live_contexts: fi-icl-u: INCOMPLETE (fdo#108535) -> DMESG-FAIL (fdo#108569) fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#108535 https://bugs.freedesktop.org/show_bug.cgi?id=108535 fdo#108569 https://bugs.freedesktop.org/show_bug.cgi?id=108569 == Participating hosts (49 -> 43) == Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-pnv-d510 == Build changes == * Linux: CI_DRM_5050 -> Patchwork_10632 CI_DRM_5050: bc6dcb88d08376d667bcb0fa1e5b8d06ac2251f2 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4699: 1270ec553741ac20c45178d2b26f9a9562ea565f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10632: cb661e6ab58409f84f93c09e4088aecb8fc59af9 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == cb661e6ab584 drm/i915/gtt: Reuse the read-only 64KiB scratch page and directories 1f674fe72f2e drm/i915/gtt: Record the scratch pte == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10632/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/7] drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming
== Series Details == Series: series starting with [CI,1/7] drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming URL : https://patchwork.freedesktop.org/series/51558/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5050 -> Patchwork_10631 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/51558/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10631 that come from known issues: === IGT changes === Issues hit igt@gem_exec_suspend@basic-s4-devices: fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718) igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size: fi-icl-u: PASS -> DMESG-WARN (fdo#106107) igt@kms_frontbuffer_tracking@basic: fi-icl-u2: PASS -> FAIL (fdo#103167) Possible fixes igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: fi-byt-clapper: FAIL (fdo#103191, fdo#107362) -> PASS fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#106107 https://bugs.freedesktop.org/show_bug.cgi?id=106107 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 == Participating hosts (49 -> 44) == Missing(5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 == Build changes == * Linux: CI_DRM_5050 -> Patchwork_10631 CI_DRM_5050: bc6dcb88d08376d667bcb0fa1e5b8d06ac2251f2 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4699: 1270ec553741ac20c45178d2b26f9a9562ea565f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10631: 75f222a3e79def88e104dd884bfd1a43f3954131 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 75f222a3e79d drm/dp: Define payload size for DP SDP PPS packet 3cd43527a220 drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported 67b6fb92ceb4 drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC 0fe8b78dc63c drm/dp: DRM DP helper/macros to get DP sink DSC parameters 16d27aaae564 drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init be79c858bc71 drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT e4483de97162 drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10631/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [CI v3 1/2] drm/i915: Add function to check for linear surfaces
On Fri, 2018-10-26 at 12:38 -0700, Dhinakaran Pandiyan wrote: > A framebuffer can comprise surfaces with distinct tiling formats, > making checks against modifier alone insufficient. Make use of a > function to identify a linear surface based on both modifier and > color > plane. > > v2: Typo fix > v3: remove 'inline' from function definition (Ville) > > Cc: Ville Syrjälä > Signed-off-by: Dhinakaran Pandiyan > Reviewed-by: Ville Syrjälä Thanks for the review, pushed series to -queued. -DK ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/selftest: fix 64K alignment in igt_write_huge
On Mon, 29 Oct 2018 at 19:40, Chris Wilson wrote: > > Quoting Matthew Auld (2018-10-29 19:36:37) > > When using softpin it's not enough to just pad the vma size, we also > > need to ensure the vma offset is at the start of the pt boundary, if we > > plan to utilize 64K pages. > > For testing purposes, we have to assume the worst as well as best cases. > Looks like we could extend this to cover both aligned and unaligned > offsets. Or have I missed the purpose of the test? Yup, even better. > -Chris > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Switch the order of function parameters
On Mon, 2018-10-29 at 16:18 +0200, Ville Syrjälä wrote: > On Fri, Oct 26, 2018 at 12:53:42PM -0700, Dhinakaran Pandiyan wrote: > > intel_fb_pitch_limit() has the parameters pixel_format and > > fb_modifier > > switched in their positions. The parameters are however used > > correctly, > > but change the order for consistency. > > > > Also use kernel data types for both parameters. > > > > Cc: Ville Syrjälä > > Signed-off-by: Dhinakaran Pandiyan > > Reviewed-by: Ville Syrjälä Thanks, pushed this to -queued. -DK ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/selftest: fix 64K alignment in igt_write_huge
Quoting Matthew Auld (2018-10-29 19:36:37) > When using softpin it's not enough to just pad the vma size, we also > need to ensure the vma offset is at the start of the pt boundary, if we > plan to utilize 64K pages. For testing purposes, we have to assume the worst as well as best cases. Looks like we could extend this to cover both aligned and unaligned offsets. Or have I missed the purpose of the test? -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/selftest: fix 64K alignment in igt_write_huge
When using softpin it's not enough to just pad the vma size, we also
need to ensure the vma offset is at the start of the pt boundary, if we
plan to utilize 64K pages.
Signed-off-by: Matthew Auld
Cc: Chris Wilson
---
drivers/gpu/drm/i915/selftests/huge_pages.c | 28 +
1 file changed, 17 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c
b/drivers/gpu/drm/i915/selftests/huge_pages.c
index 256001b00e32..765e69471958 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -1114,8 +1114,8 @@ static int igt_write_huge(struct i915_gem_context *ctx,
struct intel_engine_cs *engine;
I915_RND_STATE(prng);
IGT_TIMEOUT(end_time);
- unsigned int max_page_size;
unsigned int id;
+ u64 alignment;
u64 max;
u64 num;
u64 size;
@@ -1126,16 +1126,19 @@ static int igt_write_huge(struct i915_gem_context *ctx,
GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
size = obj->base.size;
- if (obj->mm.page_sizes.sg & I915_GTT_PAGE_SIZE_64K)
+ alignment = rounddown_pow_of_two(obj->mm.page_sizes.sg);
+ if (obj->mm.page_sizes.sg & I915_GTT_PAGE_SIZE_64K) {
size = round_up(size, I915_GTT_PAGE_SIZE_2M);
+ alignment = max(alignment, I915_GTT_PAGE_SIZE_2M);
+ }
- max_page_size = rounddown_pow_of_two(obj->mm.page_sizes.sg);
- max = div_u64((vm->total - size), max_page_size);
+ max = div_u64((vm->total - size), alignment);
n = 0;
for_each_engine(engine, i915, id) {
if (!intel_engine_can_store_dword(engine)) {
- pr_info("store-dword-imm not supported on engine=%u\n",
id);
+ pr_info("store-dword-imm not supported on engine=%u\n",
+ id);
continue;
}
engines[n++] = engine;
@@ -1160,24 +1163,27 @@ static int igt_write_huge(struct i915_gem_context *ctx,
*/
i = 0;
for_each_prime_number_from(num, 0, max) {
- u64 offset_low = num * max_page_size;
- u64 offset_high = (max - num) * max_page_size;
+ u64 offset_low = num * alignment;
+ u64 offset_high = (max - num) * alignment;
u32 dword = offset_in_page(num) / 4;
engine = engines[order[i] % n];
i = (i + 1) % (n * I915_NUM_ENGINES);
- err = __igt_write_huge(ctx, engine, obj, size, offset_low,
dword, num + 1);
+ err = __igt_write_huge(ctx, engine, obj, size, offset_low,
+ dword, num + 1);
if (err)
break;
- err = __igt_write_huge(ctx, engine, obj, size, offset_high,
dword, num + 1);
+ err = __igt_write_huge(ctx, engine, obj, size, offset_high,
+ dword, num + 1);
if (err)
break;
if (igt_timeout(end_time,
- "%s timed out on engine=%u, offset_low=%llx
offset_high=%llx, max_page_size=%x\n",
- __func__, engine->id, offset_low, offset_high,
max_page_size))
+ "%s timed out on engine=%u, offset_low=%llx
offset_high=%llx, max_page_size=%lx\n",
+ __func__, engine->id, offset_low, offset_high,
+ rounddown_pow_of_two(obj->mm.page_sizes.sg)))
break;
}
--
2.17.2
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Account for scale factor when calculating initial phase (rev2)
== Series Details == Series: drm/i915: Account for scale factor when calculating initial phase (rev2) URL : https://patchwork.freedesktop.org/series/51696/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5049 -> Patchwork_10630 = == Summary - WARNING == Minor unknown changes coming with Patchwork_10630 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10630, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/51696/revisions/2/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10630: === IGT changes === Warnings igt@drv_selftest@live_execlists: fi-icl-u2: SKIP -> PASS +1 == Known issues == Here are the changes found in Patchwork_10630 that come from known issues: === IGT changes === Issues hit igt@drv_selftest@live_evict: fi-bsw-kefka: PASS -> DMESG-WARN (fdo#107709) igt@gem_exec_suspend@basic-s3: fi-kbl-soraka: NOTRUN -> INCOMPLETE (fdo#107556, fdo#107859, fdo#107774) igt@kms_flip@basic-flip-vs-modeset: fi-skl-6700hq: PASS -> DMESG-WARN (fdo#105998) igt@kms_frontbuffer_tracking@basic: fi-icl-u2: PASS -> FAIL (fdo#103167) Possible fixes igt@drv_selftest@live_hangcheck: fi-icl-u2: INCOMPLETE (fdo#108315) -> PASS igt@kms_flip@basic-flip-vs-modeset: fi-hsw-4770r: DMESG-WARN (fdo#105602) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence: fi-skl-6700k2: FAIL (fdo#103191, fdo#107362) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-byt-clapper: FAIL (fdo#103191, fdo#107362) -> PASS igt@pm_rpm@basic-rte: fi-glk-j4005: DMESG-WARN (fdo#106000) -> PASS fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602 fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107556 https://bugs.freedesktop.org/show_bug.cgi?id=107556 fdo#107709 https://bugs.freedesktop.org/show_bug.cgi?id=107709 fdo#107774 https://bugs.freedesktop.org/show_bug.cgi?id=107774 fdo#107859 https://bugs.freedesktop.org/show_bug.cgi?id=107859 fdo#108315 https://bugs.freedesktop.org/show_bug.cgi?id=108315 == Participating hosts (47 -> 42) == Additional (2): fi-kbl-soraka fi-byt-j1900 Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-gdg-551 fi-skl-iommu == Build changes == * Linux: CI_DRM_5049 -> Patchwork_10630 CI_DRM_5049: b83dd2b523b803feea122cb1489c663a73536b9e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4699: 1270ec553741ac20c45178d2b26f9a9562ea565f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10630: ea55177d3bf0991b692f38b36cd92c32bb5752c2 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ea55177d3bf0 drm/i915: Account for scale factor when calculating initial phase == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10630/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/execlists: Poison the CSB after use
After reading the event status from the CSB, write back 0 (an invalid value) so we can detect if the HW should signal a new event without writing the event in the future. References: https://bugs.freedesktop.org/show_bug.cgi?id=108315 Signed-off-by: Chris Wilson Cc: Mika Kuoppala --- drivers/gpu/drm/i915/intel_lrc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 22b57b8926fc..126efe20d2d6 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -910,6 +910,9 @@ static void process_csb(struct intel_engine_cs *engine) execlists->active); status = buf[2 * head]; + GEM_BUG_ON(!status); + GEM_DEBUG_EXEC(WRITE_ONCE(*(u32 *)(buf + 2 * head), 0)); + if (status & (GEN8_CTX_STATUS_IDLE_ACTIVE | GEN8_CTX_STATUS_PREEMPTED)) execlists_set_active(execlists, -- 2.19.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 2/2] drm/i915: Eliminate the horrendous format check code
On Mon, 2018-10-29 at 20:34 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Replace the messy framebuffer format/modifier validation code
> with a single call to drm_any_plane_has_format(). The code was
> extremely annoying to maintain as you had to have a lot of platform
> checks for different formats. The new code requires zero maintenance.
>
> v2: Nuke the modifier checks as well since the core does that too now
> v3: Call drm_any_plane_has_format() from the driver code
> v4: Rebase
>
> Cc: Dhinakaran Pandiyan
Reviewed-by: Dhinakaran Pandiyan
-DK
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_display.c | 105 ++---
> --
> 1 file changed, 8 insertions(+), 97 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 9b549d3dd055..de38d5545f3b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -14368,7 +14368,6 @@ static int intel_framebuffer_init(struct
> intel_framebuffer *intel_fb,
> {
> struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
> struct drm_framebuffer *fb = _fb->base;
> - struct drm_format_name_buf format_name;
> u32 pitch_limit;
> unsigned int tiling, stride;
> int ret = -EINVAL;
> @@ -14399,39 +14398,14 @@ static int intel_framebuffer_init(struct
> intel_framebuffer *intel_fb,
> }
> }
>
> - /* Passed in modifier sanity checking. */
> - switch (mode_cmd->modifier[0]) {
> - case I915_FORMAT_MOD_Y_TILED_CCS:
> - case I915_FORMAT_MOD_Yf_TILED_CCS:
> - switch (mode_cmd->pixel_format) {
> - case DRM_FORMAT_XBGR:
> - case DRM_FORMAT_ABGR:
> - case DRM_FORMAT_XRGB:
> - case DRM_FORMAT_ARGB:
> - break;
> - default:
> - DRM_DEBUG_KMS("RC supported only with RGB
> formats\n");
> - goto err;
> - }
> - /* fall through */
> - case I915_FORMAT_MOD_Yf_TILED:
> - if (mode_cmd->pixel_format == DRM_FORMAT_C8) {
> - DRM_DEBUG_KMS("Indexed format does not support
> Yf tiling\n");
> - goto err;
> - }
> - /* fall through */
> - case I915_FORMAT_MOD_Y_TILED:
> - if (INTEL_GEN(dev_priv) < 9) {
> - DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
> - mode_cmd->modifier[0]);
> - goto err;
> - }
> - break;
> - case DRM_FORMAT_MOD_LINEAR:
> - case I915_FORMAT_MOD_X_TILED:
> - break;
> - default:
> - DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
> + if (!drm_any_plane_has_format(_priv->drm,
> + mode_cmd->pixel_format,
> + mode_cmd->modifier[0])) {
> + struct drm_format_name_buf format_name;
> +
> + DRM_DEBUG_KMS("unsupported pixel format %s / modifier
> 0x%llx\n",
> + drm_get_format_name(mode_cmd-
> >pixel_format,
> + _name),
> mode_cmd->modifier[0]);
> goto err;
> }
> @@ -14466,69 +14440,6 @@ static int intel_framebuffer_init(struct
> intel_framebuffer *intel_fb,
> goto err;
> }
>
> - /* Reject formats not supported by any plane early. */
> - switch (mode_cmd->pixel_format) {
> - case DRM_FORMAT_C8:
> - case DRM_FORMAT_RGB565:
> - case DRM_FORMAT_XRGB:
> - case DRM_FORMAT_ARGB:
> - break;
> - case DRM_FORMAT_XRGB1555:
> - if (INTEL_GEN(dev_priv) > 3) {
> - DRM_DEBUG_KMS("unsupported pixel format: %s\n",
> - drm_get_format_name(mode_cmd-
> >pixel_format, _name));
> - goto err;
> - }
> - break;
> - case DRM_FORMAT_ABGR:
> - if (!IS_VALLEYVIEW(dev_priv) &&
> !IS_CHERRYVIEW(dev_priv) &&
> - INTEL_GEN(dev_priv) < 9) {
> - DRM_DEBUG_KMS("unsupported pixel format: %s\n",
> - drm_get_format_name(mode_cmd-
> >pixel_format, _name));
> - goto err;
> - }
> - break;
> - case DRM_FORMAT_XBGR:
> - case DRM_FORMAT_XRGB2101010:
> - case DRM_FORMAT_XBGR2101010:
> - if (INTEL_GEN(dev_priv) < 4) {
> - DRM_DEBUG_KMS("unsupported pixel format: %s\n",
> - drm_get_format_name(mode_cmd-
> >pixel_format, _name));
> - goto err;
> - }
> - break;
> - case DRM_FORMAT_ABGR2101010:
> - if (!IS_VALLEYVIEW(dev_priv) &&
> !IS_CHERRYVIEW(dev_priv)) {
>
Re: [Intel-gfx] [PATCH v6 21/28] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs
On Thu, Oct 25, 2018 at 05:08:39PM +0300, Ville Syrjälä wrote:
> On Wed, Oct 24, 2018 at 03:28:33PM -0700, Manasi Navare wrote:
> > Infoframes are used to send secondary data packets. This patch
> > adds support for DSC Picture parameter set secondary data packets
> > in the existing write_infoframe helpers.
> >
> > v2:
> > * Rebase on drm-tip (Manasi)
> >
> > Cc: Jani Nikula
> > Cc: Ville Syrjala
> > Cc: Anusha Srivatsa
> > Signed-off-by: Manasi Navare
> > Reviewed-by: Anusha Srivatsa
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > drivers/gpu/drm/i915/intel_hdmi.c | 23 +--
> > 2 files changed, 22 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 64cca0a83cf7..0ecdc95f56d8 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4545,6 +4545,7 @@ enum {
> > * of the infoframe structure specified by CEA-861. */
> > #define VIDEO_DIP_DATA_SIZE 32
> > #define VIDEO_DIP_VSC_DATA_SIZE 36
> > +#define VIDEO_DIP_PPS_DATA_SIZE 132
> > #define VIDEO_DIP_CTL _MMIO(0x61170)
> > /* Pre HSW: */
> > #define VIDEO_DIP_ENABLE (1 << 31)
> > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
> > b/drivers/gpu/drm/i915/intel_hdmi.c
> > index d3e653640ce7..02fb54737d92 100644
> > --- a/drivers/gpu/drm/i915/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> > @@ -115,6 +115,8 @@ static u32 hsw_infoframe_enable(unsigned int type)
> > switch (type) {
> > case DP_SDP_VSC:
> > return VIDEO_DIP_ENABLE_VSC_HSW;
> > + case DP_SDP_PPS:
> > + return VDIP_ENABLE_PPS;
>
> Hmm. Why is that bit named so differently to the rest?
Will have to address the mess around VDIP_CVTL reg earlier defs in a separate
patch set
>
> > case HDMI_INFOFRAME_TYPE_AVI:
> > return VIDEO_DIP_ENABLE_AVI_HSW;
> > case HDMI_INFOFRAME_TYPE_SPD:
> > @@ -136,6 +138,8 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv,
> > switch (type) {
> > case DP_SDP_VSC:
> > return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
> > + case DP_SDP_PPS:
> > + return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
> > case HDMI_INFOFRAME_TYPE_AVI:
> > return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
> > case HDMI_INFOFRAME_TYPE_SPD:
> > @@ -148,6 +152,18 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv,
> > }
> > }
> >
> > +static int hsw_dip_data_size(unsigned int type)
> > +{
> > + switch (type) {
> > + case DP_SDP_VSC:
> > + return VIDEO_DIP_VSC_DATA_SIZE;
> > + case DP_SDP_PPS:
> > + return VIDEO_DIP_PPS_DATA_SIZE;
> > + default:
> > + return VIDEO_DIP_DATA_SIZE;
> > + }
> > +}
> > +
> > static void g4x_write_infoframe(struct intel_encoder *encoder,
> > const struct intel_crtc_state *crtc_state,
> > unsigned int type,
> > @@ -382,11 +398,14 @@ static void hsw_write_infoframe(struct intel_encoder
> > *encoder,
> > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
> > - int data_size = type == DP_SDP_VSC ?
> > - VIDEO_DIP_VSC_DATA_SIZE : VIDEO_DIP_DATA_SIZE;
> > + i915_reg_t data_reg;
> > + int data_size = 0;
>
> =0 is unnecessary.
This was added to adderss a warning that data_size is uninitialized.
But will double check again if its really needed.
>
> > int i;
> > u32 val = I915_READ(ctl_reg);
> >
> > + data_size = hsw_dip_data_size(type);
> > + data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0);
>
> data_reg is unused.
Yes I think the cleanup patch series that was sent sometime recently now
uses hsw_dip_data_reg directly in I915_WRITE call.
I will remove the data_reg.
Manasi
>
> > +
> > val &= ~hsw_infoframe_enable(type);
> > I915_WRITE(ctl_reg, val);
> >
> > --
> > 2.18.0
>
> --
> Ville Syrjälä
> Intel
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Re: [Intel-gfx] [PATCH] drm/i915: Simplify has_sagv function
On Mon, Oct 29, 2018 at 12:08:38PM +0200, Jani Nikula wrote:
> On Fri, 26 Oct 2018, Rodrigo Vivi wrote:
> > The specially case for SKL for not controlled sagv
> > is already taken care inside intel_enable_sagv, so there's
> > no need to duplicate the check here.
> >
> > v2: Go one step further and remove skl special case. (Jani)
> > v3: Separate runtime status handle from has_sagv flag.
> > v4: Go back and accept simple Jani proposed solution.
>
> Thanks.
>
> Reviewed-by: Jani Nikula
pushed to dinq. Thanks for review and idea!
>
>
>
> >
> > Signed-off-by: Rodrigo Vivi
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 11 ++-
> > 1 file changed, 2 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index bc70f6bb86ae..82c82e233154 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3611,15 +3611,8 @@ static bool skl_needs_memory_bw_wa(struct
> > intel_atomic_state *state)
> > static bool
> > intel_has_sagv(struct drm_i915_private *dev_priv)
> > {
> > - if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) ||
> > - IS_CANNONLAKE(dev_priv) || IS_ICELAKE(dev_priv))
> > - return true;
> > -
> > - if (IS_SKYLAKE(dev_priv) &&
> > - dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED)
> > - return true;
> > -
> > - return false;
> > + return (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) &&
> > + dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
> > }
> >
> > /*
>
> --
> Jani Nikula, Intel Open Source Graphics Center
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[Intel-gfx] [PATCH v4 1/2] drm: Add drm_any_plane_has_format()
From: Ville Syrjälä
Add a function to check whether there is at least one plane that
supports a specific format and modifier combination. Drivers can
use this to reject unsupported formats/modifiers in .fb_create().
v2: Accept anyformat if the driver doesn't do planes (Eric)
s/planes_have_format/any_plane_has_format/ (Eric)
Check the modifier as well since we already have a function
that does both
v3: Don't do the check in the core since we may not know the
modifier yet, instead export the function and let drivers
call it themselves
Cc: Eric Anholt
Cc: Dhinakaran Pandiyan
Signed-off-by: Ville Syrjälä
Reviewed-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/drm_plane.c | 23 +++
include/drm/drm_mode_config.h | 6 ++
include/drm/drm_plane.h | 2 ++
3 files changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c
index 1fa98bd12003..679455e36829 100644
--- a/drivers/gpu/drm/drm_plane.c
+++ b/drivers/gpu/drm/drm_plane.c
@@ -636,6 +636,29 @@ static int __setplane_check(struct drm_plane *plane,
return 0;
}
+/**
+ * drm_any_plane_has_format - Check whether any plane supports this format and
modifier combination
+ * @dev: DRM device
+ * @format: pixel format (DRM_FORMAT_*)
+ * @modifier: data layout modifier
+ *
+ * Returns:
+ * Whether at least one plane supports the specified format and modifier
combination.
+ */
+bool drm_any_plane_has_format(struct drm_device *dev,
+ u32 format, u64 modifier)
+{
+ struct drm_plane *plane;
+
+ drm_for_each_plane(plane, dev) {
+ if (drm_plane_check_pixel_format(plane, format, modifier) == 0)
+ return true;
+ }
+
+ return false;
+}
+EXPORT_SYMBOL(drm_any_plane_has_format);
+
/*
* __setplane_internal - setplane handler for internal callers
*
diff --git a/include/drm/drm_mode_config.h b/include/drm/drm_mode_config.h
index d643d268693e..5dbeabdbaf91 100644
--- a/include/drm/drm_mode_config.h
+++ b/include/drm/drm_mode_config.h
@@ -52,6 +52,12 @@ struct drm_mode_config_funcs {
* requested metadata, but most of that is left to the driver. See
* drm_mode_fb_cmd2 for details.
*
+* To validate the pixel format and modifier drivers can use
+* drm_any_plane_has_format() to make sure at least one plane supports
+* the requested values. Note that the driver must first determine the
+* actual modifier used if the request doesn't have it specified,
+* ie. when (@mode_cmd->flags & DRM_MODE_FB_MODIFIERS) == 0.
+*
* If the parameters are deemed valid and the backing storage objects in
* the underlying memory manager all exist, then the driver allocates
* a new _framebuffer structure, subclassed to contain
diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h
index 0a0834bef8bd..3701f56c3362 100644
--- a/include/drm/drm_plane.h
+++ b/include/drm/drm_plane.h
@@ -798,5 +798,7 @@ static inline struct drm_plane *drm_plane_find(struct
drm_device *dev,
#define drm_for_each_plane(plane, dev) \
list_for_each_entry(plane, &(dev)->mode_config.plane_list, head)
+bool drm_any_plane_has_format(struct drm_device *dev,
+ u32 format, u64 modifier);
#endif
--
2.18.1
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[Intel-gfx] [PATCH v4 2/2] drm/i915: Eliminate the horrendous format check code
From: Ville Syrjälä
Replace the messy framebuffer format/modifier validation code
with a single call to drm_any_plane_has_format(). The code was
extremely annoying to maintain as you had to have a lot of platform
checks for different formats. The new code requires zero maintenance.
v2: Nuke the modifier checks as well since the core does that too now
v3: Call drm_any_plane_has_format() from the driver code
v4: Rebase
Cc: Dhinakaran Pandiyan
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 105 ++-
1 file changed, 8 insertions(+), 97 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 9b549d3dd055..de38d5545f3b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14368,7 +14368,6 @@ static int intel_framebuffer_init(struct
intel_framebuffer *intel_fb,
{
struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
struct drm_framebuffer *fb = _fb->base;
- struct drm_format_name_buf format_name;
u32 pitch_limit;
unsigned int tiling, stride;
int ret = -EINVAL;
@@ -14399,39 +14398,14 @@ static int intel_framebuffer_init(struct
intel_framebuffer *intel_fb,
}
}
- /* Passed in modifier sanity checking. */
- switch (mode_cmd->modifier[0]) {
- case I915_FORMAT_MOD_Y_TILED_CCS:
- case I915_FORMAT_MOD_Yf_TILED_CCS:
- switch (mode_cmd->pixel_format) {
- case DRM_FORMAT_XBGR:
- case DRM_FORMAT_ABGR:
- case DRM_FORMAT_XRGB:
- case DRM_FORMAT_ARGB:
- break;
- default:
- DRM_DEBUG_KMS("RC supported only with RGB
formats\n");
- goto err;
- }
- /* fall through */
- case I915_FORMAT_MOD_Yf_TILED:
- if (mode_cmd->pixel_format == DRM_FORMAT_C8) {
- DRM_DEBUG_KMS("Indexed format does not support Yf
tiling\n");
- goto err;
- }
- /* fall through */
- case I915_FORMAT_MOD_Y_TILED:
- if (INTEL_GEN(dev_priv) < 9) {
- DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
- mode_cmd->modifier[0]);
- goto err;
- }
- break;
- case DRM_FORMAT_MOD_LINEAR:
- case I915_FORMAT_MOD_X_TILED:
- break;
- default:
- DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
+ if (!drm_any_plane_has_format(_priv->drm,
+ mode_cmd->pixel_format,
+ mode_cmd->modifier[0])) {
+ struct drm_format_name_buf format_name;
+
+ DRM_DEBUG_KMS("unsupported pixel format %s / modifier 0x%llx\n",
+ drm_get_format_name(mode_cmd->pixel_format,
+ _name),
mode_cmd->modifier[0]);
goto err;
}
@@ -14466,69 +14440,6 @@ static int intel_framebuffer_init(struct
intel_framebuffer *intel_fb,
goto err;
}
- /* Reject formats not supported by any plane early. */
- switch (mode_cmd->pixel_format) {
- case DRM_FORMAT_C8:
- case DRM_FORMAT_RGB565:
- case DRM_FORMAT_XRGB:
- case DRM_FORMAT_ARGB:
- break;
- case DRM_FORMAT_XRGB1555:
- if (INTEL_GEN(dev_priv) > 3) {
- DRM_DEBUG_KMS("unsupported pixel format: %s\n",
-
drm_get_format_name(mode_cmd->pixel_format, _name));
- goto err;
- }
- break;
- case DRM_FORMAT_ABGR:
- if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
- INTEL_GEN(dev_priv) < 9) {
- DRM_DEBUG_KMS("unsupported pixel format: %s\n",
-
drm_get_format_name(mode_cmd->pixel_format, _name));
- goto err;
- }
- break;
- case DRM_FORMAT_XBGR:
- case DRM_FORMAT_XRGB2101010:
- case DRM_FORMAT_XBGR2101010:
- if (INTEL_GEN(dev_priv) < 4) {
- DRM_DEBUG_KMS("unsupported pixel format: %s\n",
-
drm_get_format_name(mode_cmd->pixel_format, _name));
- goto err;
- }
- break;
- case DRM_FORMAT_ABGR2101010:
- if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
- DRM_DEBUG_KMS("unsupported pixel format: %s\n",
-
drm_get_format_name(mode_cmd->pixel_format, _name));
-
[Intel-gfx] [CI 1/2] drm/i915/gtt: Record the scratch pte
Record the scratch PTE encoding upon creation rather than recomputing
the bits everytime. This is important for the next patch where we forgo
having a valid scratch page with which we may compute the bits and so
require keeping the PTE value instead.
v2: Fix up scrub_64K to use scratch_pte as well.
Signed-off-by: Chris Wilson
Cc: Matthew Auld
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 85 +++--
drivers/gpu/drm/i915/i915_gem_gtt.h | 11 ++--
2 files changed, 50 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 19b2d991b5d8..afe45cbcd762 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -186,9 +186,9 @@ static void clear_pages(struct i915_vma *vma)
memset(>page_sizes, 0, sizeof(vma->page_sizes));
}
-static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
- enum i915_cache_level level,
- u32 flags)
+static u64 gen8_pte_encode(dma_addr_t addr,
+ enum i915_cache_level level,
+ u32 flags)
{
gen8_pte_t pte = addr | _PAGE_PRESENT | _PAGE_RW;
@@ -225,9 +225,9 @@ static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
#define gen8_pdpe_encode gen8_pde_encode
#define gen8_pml4e_encode gen8_pde_encode
-static gen6_pte_t snb_pte_encode(dma_addr_t addr,
-enum i915_cache_level level,
-u32 unused)
+static u64 snb_pte_encode(dma_addr_t addr,
+ enum i915_cache_level level,
+ u32 flags)
{
gen6_pte_t pte = GEN6_PTE_VALID;
pte |= GEN6_PTE_ADDR_ENCODE(addr);
@@ -247,9 +247,9 @@ static gen6_pte_t snb_pte_encode(dma_addr_t addr,
return pte;
}
-static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
-enum i915_cache_level level,
-u32 unused)
+static u64 ivb_pte_encode(dma_addr_t addr,
+ enum i915_cache_level level,
+ u32 flags)
{
gen6_pte_t pte = GEN6_PTE_VALID;
pte |= GEN6_PTE_ADDR_ENCODE(addr);
@@ -271,9 +271,9 @@ static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
return pte;
}
-static gen6_pte_t byt_pte_encode(dma_addr_t addr,
-enum i915_cache_level level,
-u32 flags)
+static u64 byt_pte_encode(dma_addr_t addr,
+ enum i915_cache_level level,
+ u32 flags)
{
gen6_pte_t pte = GEN6_PTE_VALID;
pte |= GEN6_PTE_ADDR_ENCODE(addr);
@@ -287,9 +287,9 @@ static gen6_pte_t byt_pte_encode(dma_addr_t addr,
return pte;
}
-static gen6_pte_t hsw_pte_encode(dma_addr_t addr,
-enum i915_cache_level level,
-u32 unused)
+static u64 hsw_pte_encode(dma_addr_t addr,
+ enum i915_cache_level level,
+ u32 flags)
{
gen6_pte_t pte = GEN6_PTE_VALID;
pte |= HSW_PTE_ADDR_ENCODE(addr);
@@ -300,9 +300,9 @@ static gen6_pte_t hsw_pte_encode(dma_addr_t addr,
return pte;
}
-static gen6_pte_t iris_pte_encode(dma_addr_t addr,
- enum i915_cache_level level,
- u32 unused)
+static u64 iris_pte_encode(dma_addr_t addr,
+ enum i915_cache_level level,
+ u32 flags)
{
gen6_pte_t pte = GEN6_PTE_VALID;
pte |= HSW_PTE_ADDR_ENCODE(addr);
@@ -666,14 +666,13 @@ static void free_pt(struct i915_address_space *vm, struct
i915_page_table *pt)
static void gen8_initialize_pt(struct i915_address_space *vm,
struct i915_page_table *pt)
{
- fill_px(vm, pt,
- gen8_pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC, 0));
+ fill_px(vm, pt, vm->scratch_pte);
}
-static void gen6_initialize_pt(struct gen6_hw_ppgtt *ppgtt,
+static void gen6_initialize_pt(struct i915_address_space *vm,
struct i915_page_table *pt)
{
- fill32_px(>base.vm, pt, ppgtt->scratch_pte);
+ fill32_px(vm, pt, vm->scratch_pte);
}
static struct i915_page_directory *alloc_pd(struct i915_address_space *vm)
@@ -807,15 +806,13 @@ static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
/* Removes entries from a single page table, releasing it if it's empty.
* Caller can use the return value to update higher-level entries.
*/
-static bool gen8_ppgtt_clear_pt(struct i915_address_space *vm,
+static bool gen8_ppgtt_clear_pt(const struct i915_address_space *vm,
struct i915_page_table *pt,
u64 start, u64 length)
{
unsigned int num_entries = gen8_pte_count(start, length);
[Intel-gfx] [CI 2/2] drm/i915/gtt: Reuse the read-only 64KiB scratch page and directories
If we can prevent stray writes from landing in the scratch page, we can
reuse the same page and same scratch PT for all contexts without fear of
information leaks and side-channels.
Signed-off-by: Chris Wilson
Cc: Matthew Auld
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 30 +
1 file changed, 26 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index afe45cbcd762..9ea024395d49 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -580,10 +580,9 @@ setup_scratch_page(struct i915_address_space *vm, gfp_t
gfp)
* region, including any PTEs which happen to point to scratch.
*
* This is only relevant for the 48b PPGTT where we support
-* huge-gtt-pages, see also i915_vma_insert().
-*
-* TODO: we should really consider write-protecting the scratch-page and
-* sharing between ppgtt
+* huge-gtt-pages, see also i915_vma_insert(). However, as we share the
+* scratch (read-only) between all vm, we create one 64k scratch page
+* for all.
*/
size = I915_GTT_PAGE_SIZE_4K;
if (i915_vm_is_48bit(vm) &&
@@ -1209,6 +1208,26 @@ static int gen8_init_scratch(struct i915_address_space
*vm)
{
int ret;
+ /*
+* If everybody agrees to not to write into the scratch page,
+* we can reuse it for all vm, keeping contexts and processes separate.
+*/
+ if (vm->has_read_only &&
+ vm->i915->kernel_context &&
+ vm->i915->kernel_context->ppgtt) {
+ struct i915_address_space *clone =
+ >i915->kernel_context->ppgtt->vm;
+
+ GEM_BUG_ON(!clone->has_read_only);
+
+ vm->scratch_page.order = clone->scratch_page.order;
+ vm->scratch_pte = clone->scratch_pte;
+ vm->scratch_pt = clone->scratch_pt;
+ vm->scratch_pd = clone->scratch_pd;
+ vm->scratch_pdp = clone->scratch_pdp;
+ return 0;
+ }
+
ret = setup_scratch_page(vm, __GFP_HIGHMEM);
if (ret)
return ret;
@@ -1289,6 +1308,9 @@ static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt
*ppgtt, bool create)
static void gen8_free_scratch(struct i915_address_space *vm)
{
+ if (!vm->scratch_page.daddr)
+ return;
+
if (use_4lvl(vm))
free_pdp(vm, vm->scratch_pdp);
free_pd(vm, vm->scratch_pd);
--
2.19.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915: Account for scale factor when calculating initial phase
From: Ville Syrjälä
To get the initial phase correct we need to account for the scale
factor as well. I forgot this initially and was mostly looking at
heavily upscaled content where the minor difference between -0.5
and the proper initial phase was not readily apparent.
And let's toss in a comment that tries to explain the formula
a little bit.
v2: The initial phase upper limit is 1.5, not 24.0!
Cc: Maarten Lankhorst
Fixes: 0a59952b24e2 ("drm/i915: Configure SKL+ scaler initial phase correctly")
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 45 ++--
drivers/gpu/drm/i915/intel_drv.h | 2 +-
drivers/gpu/drm/i915/intel_sprite.c | 20 +
3 files changed, 57 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index fe045abb6472..33dd2e9751e6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4786,8 +4786,31 @@ static void cpt_verify_modeset(struct drm_device *dev,
int pipe)
* chroma samples for both of the luma samples, and thus we don't
* actually get the expected MPEG2 chroma siting convention :(
* The same behaviour is observed on pre-SKL platforms as well.
+ *
+ * Theory behind the formula (note that we ignore sub-pixel
+ * source coordinates):
+ * s = source sample position
+ * d = destination sample position
+ *
+ * Downscaling 4:1:
+ * -0.5
+ * | 0.0
+ * | | 1.5 (initial phase)
+ * | | |
+ * v v v
+ * | s | s | s | s |
+ * | d |
+ *
+ * Upscaling 1:4:
+ * -0.5
+ * | -0.375 (initial phase)
+ * | | 0.0
+ * | | |
+ * v v v
+ * | s |
+ * | d | d | d | d |
*/
-u16 skl_scaler_calc_phase(int sub, bool chroma_cosited)
+u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
{
int phase = -0x8000;
u16 trip = 0;
@@ -4795,6 +4818,15 @@ u16 skl_scaler_calc_phase(int sub, bool chroma_cosited)
if (chroma_cosited)
phase += (sub - 1) * 0x8000 / sub;
+ phase += scale / (2 * sub);
+
+ /*
+* Hardware initial phase limited to [-0.5:1.5].
+* Since the max hardware scale factor is 3.0, we
+* should never actually excdeed 1.0 here.
+*/
+ WARN_ON(phase < -0x8000 || phase > 0x18000);
+
if (phase < 0)
phase = 0x1 + phase;
else
@@ -5003,13 +5035,20 @@ static void skylake_pfit_enable(const struct
intel_crtc_state *crtc_state)
if (crtc_state->pch_pfit.enabled) {
u16 uv_rgb_hphase, uv_rgb_vphase;
+ int pfit_w, pfit_h, hscale, vscale;
int id;
if (WARN_ON(crtc_state->scaler_state.scaler_id < 0))
return;
- uv_rgb_hphase = skl_scaler_calc_phase(1, false);
- uv_rgb_vphase = skl_scaler_calc_phase(1, false);
+ pfit_w = (crtc_state->pch_pfit.size >> 16) & 0x;
+ pfit_h = crtc_state->pch_pfit.size & 0x;
+
+ hscale = (crtc_state->pipe_src_w << 16) / pfit_w;
+ vscale = (crtc_state->pipe_src_h << 16) / pfit_h;
+
+ uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
+ uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
id = scaler_state->scaler_id;
I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index db24308729b4..86d551a331b1 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1709,7 +1709,7 @@ void intel_mode_from_pipe_config(struct drm_display_mode
*mode,
void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state);
-u16 skl_scaler_calc_phase(int sub, bool chroma_center);
+u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center);
int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
int skl_max_scale(const struct intel_crtc_state *crtc_state,
u32 pixel_format);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index cfaddc05fea6..fbb916506c77 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -326,27 +326,35 @@ skl_program_scaler(struct drm_i915_private *dev_priv,
uint32_t crtc_h = drm_rect_height(_state->base.dst);
u16 y_hphase, uv_rgb_hphase;
u16 y_vphase, uv_rgb_vphase;
+ int hscale, vscale;
/* Sizes are 0 based */
crtc_w--;
crtc_h--;
+ hscale = drm_rect_calc_hscale(_state->base.src,
+ _state->base.dst,
+ 0, INT_MAX);
+ vscale = drm_rect_calc_vscale(_state->base.src,
+ _state->base.dst,
+
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Test vm isolation (rev3)
== Series Details == Series: drm/i915/selftests: Test vm isolation (rev3) URL : https://patchwork.freedesktop.org/series/51689/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5047 -> Patchwork_10629 = == Summary - WARNING == Minor unknown changes coming with Patchwork_10629 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10629, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/51689/revisions/3/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10629: === IGT changes === Warnings igt@pm_rpm@module-reload: fi-hsw-4770r: SKIP -> PASS == Known issues == Here are the changes found in Patchwork_10629 that come from known issues: === IGT changes === Issues hit igt@drv_selftest@live_contexts: fi-icl-u: PASS -> DMESG-FAIL (fdo#108569) igt@gem_exec_suspend@basic-s3: fi-kbl-soraka: NOTRUN -> INCOMPLETE (fdo#107556, fdo#107774, fdo#107859) fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718) igt@kms_flip@basic-flip-vs-modeset: fi-skl-6700hq: PASS -> DMESG-WARN (fdo#105998) +1 igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: fi-icl-u2: PASS -> DMESG-WARN (fdo#106107) Possible fixes igt@drv_module_reload@basic-reload-inject: fi-hsw-4770r: DMESG-WARN (fdo#107425, fdo#107924) -> PASS igt@drv_selftest@live_contexts: fi-icl-u2: DMESG-FAIL (fdo#108569) -> PASS igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: FAIL (fdo#103167) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-byt-clapper: FAIL (fdo#107362, fdo#103191) -> PASS fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998 fdo#106107 https://bugs.freedesktop.org/show_bug.cgi?id=106107 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107425 https://bugs.freedesktop.org/show_bug.cgi?id=107425 fdo#107556 https://bugs.freedesktop.org/show_bug.cgi?id=107556 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#107774 https://bugs.freedesktop.org/show_bug.cgi?id=107774 fdo#107859 https://bugs.freedesktop.org/show_bug.cgi?id=107859 fdo#107924 https://bugs.freedesktop.org/show_bug.cgi?id=107924 fdo#108569 https://bugs.freedesktop.org/show_bug.cgi?id=108569 == Participating hosts (46 -> 43) == Additional (1): fi-kbl-soraka Missing(4): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-apl-guc == Build changes == * Linux: CI_DRM_5047 -> Patchwork_10629 CI_DRM_5047: cc8c29937b897a11db4c0e874029ea83f6eaa10a @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4699: 1270ec553741ac20c45178d2b26f9a9562ea565f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10629: e9dcbb986f118dba8d8ea0c78cf6d56242da5363 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == e9dcbb986f11 drm/i915/selftests: Test vm isolation == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10629/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Simplify has_sagv (rev3)
== Series Details == Series: drm/i915: Simplify has_sagv (rev3) URL : https://patchwork.freedesktop.org/series/51266/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5045_full -> Patchwork_10627_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_10627_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10627_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10627_full: === IGT changes === Warnings igt@kms_plane_lowres@pipe-a-tiling-none: shard-snb: PASS -> SKIP +2 == Known issues == Here are the changes found in Patchwork_10627_full that come from known issues: === IGT changes === Issues hit igt@gem_ppgtt@blt-vs-render-ctxn: shard-kbl: PASS -> INCOMPLETE (fdo#106023, fdo#106887, fdo#103665) shard-skl: NOTRUN -> TIMEOUT (fdo#108039) igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a: shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) igt@kms_ccs@pipe-a-crc-sprite-planes-basic: shard-glk: PASS -> FAIL (fdo#108145) igt@kms_chv_cursor_fail@pipe-b-256x256-bottom-edge: shard-skl: NOTRUN -> FAIL (fdo#104671) igt@kms_cursor_crc@cursor-128x42-sliding: shard-apl: PASS -> FAIL (fdo#103232) +2 igt@kms_cursor_crc@cursor-256x256-random: shard-glk: PASS -> FAIL (fdo#103232) igt@kms_cursor_crc@cursor-64x21-random: shard-skl: NOTRUN -> FAIL (fdo#103232) igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-ytiled: shard-apl: PASS -> INCOMPLETE (fdo#103927) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu: shard-skl: NOTRUN -> FAIL (fdo#103167) +3 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite: shard-apl: PASS -> FAIL (fdo#103167) +1 igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff: shard-glk: PASS -> FAIL (fdo#103167) +1 igt@kms_plane@pixel-format-pipe-a-planes: shard-skl: NOTRUN -> DMESG-FAIL (fdo#103166, fdo#106885) igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max: shard-skl: NOTRUN -> FAIL (fdo#108145) +4 igt@kms_plane_alpha_blend@pipe-b-alpha-7efc: shard-skl: NOTRUN -> FAIL (fdo#108145, fdo#107815) +2 igt@kms_plane_multiple@atomic-pipe-a-tiling-y: shard-glk: PASS -> FAIL (fdo#103166) +2 igt@kms_plane_multiple@atomic-pipe-b-tiling-x: shard-apl: PASS -> FAIL (fdo#103166) +1 igt@kms_plane_multiple@atomic-pipe-c-tiling-yf: shard-skl: NOTRUN -> FAIL (fdo#103166, fdo#107815) igt@kms_setmode@basic: shard-kbl: PASS -> FAIL (fdo#99912) igt@pm_backlight@fade_with_suspend: shard-skl: NOTRUN -> FAIL (fdo#107847) Possible fixes igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c: shard-glk: DMESG-WARN (fdo#107956) -> PASS igt@kms_cursor_crc@cursor-128x128-suspend: shard-skl: INCOMPLETE (fdo#104108) -> PASS igt@kms_cursor_crc@cursor-256x85-offscreen: shard-skl: FAIL (fdo#103232) -> PASS igt@kms_cursor_crc@cursor-64x21-sliding: shard-apl: FAIL (fdo#103232) -> PASS +2 igt@kms_cursor_legacy@pipe-a-torture-move: shard-skl: INCOMPLETE -> PASS igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled: shard-glk: FAIL (fdo#103184) -> PASS igt@kms_flip@flip-vs-expired-vblank: shard-skl: FAIL (fdo#105363) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff: shard-apl: FAIL (fdo#103167) -> PASS +1 igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen: shard-glk: FAIL (fdo#103167) -> PASS +1 igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: shard-skl: FAIL (fdo#107815) -> PASS igt@kms_plane_multiple@atomic-pipe-a-tiling-x: shard-apl: FAIL (fdo#103166) -> PASS +1 igt@kms_plane_multiple@atomic-pipe-c-tiling-y: shard-glk: FAIL (fdo#103166) -> PASS +1 igt@kms_setmode@basic: shard-apl: FAIL (fdo#99912) -> PASS fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103184 https://bugs.freedesktop.org/show_bug.cgi?id=103184 fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#104108
Re: [Intel-gfx] [RFC 1/3] drm/i915: Rename IS_GEN to IS_GEN_RANGE.
On Mon, Oct 29, 2018 at 12:19:37PM +0200, Jani Nikula wrote:
> On Tue, 23 Oct 2018, Rodrigo Vivi wrote:
> > RANGE makes it longer, but clear.
>
> IS_GEN_RANGE() was the first proposal, but in review this was changed to
> IS_GEN() following IS_REVID() and IS__REVID().
>
> IMO unnecessary change.
consider this one dropped then.
other 2 patches from this series got pushed.
Thanks,
Rodrigo.
>
> BR,
> Jani.
>
> >
> > Diff generated with:
> >
> > sed 's/IS_GEN(/IS_GEN_RANGE(/g' drivers/gpu/drm/i915/*.{c,h} -i
> >
> > Cc: Tvrtko Ursulin
> > Signed-off-by: Rodrigo Vivi
> > ---
> > drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
> > drivers/gpu/drm/i915/i915_drv.h | 2 +-
> > drivers/gpu/drm/i915/i915_perf.c| 4 ++--
> > drivers/gpu/drm/i915/intel_bios.c | 2 +-
> > drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
> > drivers/gpu/drm/i915/intel_fbc.c| 2 +-
> > drivers/gpu/drm/i915/intel_hangcheck.c | 2 +-
> > drivers/gpu/drm/i915/intel_ringbuffer.c | 8
> > drivers/gpu/drm/i915/intel_uncore.c | 12 ++--
> > 9 files changed, 18 insertions(+), 18 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 5b37d5f8e132..3deab30388f2 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -2919,7 +2919,7 @@ static int i915_dmc_info(struct seq_file *m, void
> > *unused)
> > if (IS_BROXTON(dev_priv)) {
> > seq_printf(m, "DC3 -> DC5 count: %d\n",
> >I915_READ(BXT_CSR_DC3_DC5_COUNT));
> > - } else if (IS_GEN(dev_priv, 9, 11)) {
> > + } else if (IS_GEN_RANGE(dev_priv, 9, 11)) {
> > seq_printf(m, "DC3 -> DC5 count: %d\n",
> >I915_READ(SKL_CSR_DC3_DC5_COUNT));
> > seq_printf(m, "DC5 -> DC6 count: %d\n",
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 3017ef037fed..f766bb1e873b 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -2387,7 +2387,7 @@ intel_info(const struct drm_i915_private *dev_priv)
> > *
> > * Use GEN_FOREVER for unbound start and or end.
> > */
> > -#define IS_GEN(dev_priv, s, e) \
> > +#define IS_GEN_RANGE(dev_priv, s, e) \
> > (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e
> >
> > /*
> > diff --git a/drivers/gpu/drm/i915/i915_perf.c
> > b/drivers/gpu/drm/i915/i915_perf.c
> > index 664b96bb65a3..0888b6e6080f 100644
> > --- a/drivers/gpu/drm/i915/i915_perf.c
> > +++ b/drivers/gpu/drm/i915/i915_perf.c
> > @@ -1795,7 +1795,7 @@ static int gen8_enable_metric_set(struct
> > drm_i915_private *dev_priv,
> > * be read back from automatically triggered reports, as part of the
> > * RPT_ID field.
> > */
> > - if (IS_GEN(dev_priv, 9, 11)) {
> > + if (IS_GEN_RANGE(dev_priv, 9, 11)) {
> > I915_WRITE(GEN8_OA_DEBUG,
> >
> > _MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
> > GEN9_OA_DEBUG_INCLUDE_CLK_RATIO));
> > @@ -3439,7 +3439,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
> >
> > dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16);
> > }
> > - } else if (IS_GEN(dev_priv, 10, 11)) {
> > + } else if (IS_GEN_RANGE(dev_priv, 10, 11)) {
> > dev_priv->perf.oa.ops.is_valid_b_counter_reg =
> > gen7_is_valid_b_counter_addr;
> > dev_priv->perf.oa.ops.is_valid_mux_reg =
> > diff --git a/drivers/gpu/drm/i915/intel_bios.c
> > b/drivers/gpu/drm/i915/intel_bios.c
> > index 1faa494e2bc9..43cf0b026143 100644
> > --- a/drivers/gpu/drm/i915/intel_bios.c
> > +++ b/drivers/gpu/drm/i915/intel_bios.c
> > @@ -446,7 +446,7 @@ parse_sdvo_device_mapping(struct drm_i915_private
> > *dev_priv, u8 bdb_version)
> > * Only parse SDVO mappings on gens that could have SDVO. This isn't
> > * accurate and doesn't have to be, as long as it's not too strict.
> > */
> > - if (!IS_GEN(dev_priv, 3, 7)) {
> > + if (!IS_GEN_RANGE(dev_priv, 3, 7)) {
> > DRM_DEBUG_KMS("Skipping SDVO device mapping\n");
> > return;
> > }
> > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
> > b/drivers/gpu/drm/i915/intel_engine_cs.c
> > index 8bfab22068a3..65f6c9bc10cf 100644
> > --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> > @@ -1286,7 +1286,7 @@ static void intel_engine_print_registers(const struct
> > intel_engine_cs *engine,
> > >execlists;
> > u64 addr;
> >
> > - if (engine->id == RCS && IS_GEN(dev_priv, 4, 7))
> > + if (engine->id == RCS && IS_GEN_RANGE(dev_priv, 4, 7))
> > drm_printf(m, "\tCCID: 0x%08x\n", I915_READ(CCID));
> > drm_printf(m, "\tRING_START: 0x%08x\n",
> >
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Test vm isolation (rev3)
== Series Details == Series: drm/i915/selftests: Test vm isolation (rev3) URL : https://patchwork.freedesktop.org/series/51689/ State : warning == Summary == $ dim checkpatch origin/drm-tip e9dcbb986f11 drm/i915/selftests: Test vm isolation -:242: WARNING:LINE_SPACING: Missing a blank line after declarations #242: FILE: drivers/gpu/drm/i915/selftests/i915_gem_context.c:980: + struct drm_file *file; + I915_RND_STATE(prng); total: 0 errors, 1 warnings, 0 checks, 330 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/glk: Remove 99% limitation.
On Fri, Oct 26, 2018 at 07:53:34PM +0300, Ville Syrjälä wrote:
> On Thu, Oct 25, 2018 at 05:56:36PM -0700, Rodrigo Vivi wrote:
> > While checking the opportunity to add a display_gen
> > check to allow glk and cnl to be on same bucket I noticed
> > these FIXME cases here.
> >
> > So I got the confirmation from HW architect that we actually
> > never needed this workaround.
> >
> > "GLK supports 2 pixel per clock, so pixel clock can be up to 2 * cdclk."
>
> Cool.
>
> Reviewed-by: Ville Syrjälä
Thanks, patch pushed to dinq.
>
> >
> > So, this reverts commit 97f55ca5b662 ("drm/i915/glk: limit pixel
> > clock to 99% of cdclk workaround")
> >
> > Fixes: 97f55ca5b662 ("drm/i915/glk: limit pixel clock to 99% of cdclk
> > workaround")
> >
> > Cc: Ville Syrjälä
> > Cc: Madhav Chauhan
> > Cc: Jani Nikula
> > Cc: Clinton Taylor
> > Cc: Arthur J Runyan
> > Signed-off-by: Rodrigo Vivi
> > ---
> > drivers/gpu/drm/i915/intel_cdclk.c | 18 ++
> > 1 file changed, 2 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> > b/drivers/gpu/drm/i915/intel_cdclk.c
> > index 29075c763428..8d74276029e6 100644
> > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > @@ -2138,16 +2138,8 @@ void intel_set_cdclk(struct drm_i915_private
> > *dev_priv,
> > static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv,
> > int pixel_rate)
> > {
> > - if (INTEL_GEN(dev_priv) >= 10)
> > + if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> > return DIV_ROUND_UP(pixel_rate, 2);
> > - else if (IS_GEMINILAKE(dev_priv))
> > - /*
> > -* FIXME: Avoid using a pixel clock that is more than 99% of
> > the cdclk
> > -* as a temporary workaround. Use a higher cdclk instead. (Note
> > that
> > -* intel_compute_max_dotclk() limits the max pixel clock to 99%
> > of max
> > -* cdclk.)
> > -*/
> > - return DIV_ROUND_UP(pixel_rate * 100, 2 * 99);
> > else if (IS_GEN9(dev_priv) ||
> > IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> > return pixel_rate;
> > @@ -2543,14 +2535,8 @@ static int intel_compute_max_dotclk(struct
> > drm_i915_private *dev_priv)
> > {
> > int max_cdclk_freq = dev_priv->max_cdclk_freq;
> >
> > - if (INTEL_GEN(dev_priv) >= 10)
> > + if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> > return 2 * max_cdclk_freq;
> > - else if (IS_GEMINILAKE(dev_priv))
> > - /*
> > -* FIXME: Limiting to 99% as a temporary workaround. See
> > -* intel_min_cdclk() for details.
> > -*/
> > - return 2 * max_cdclk_freq * 99 / 100;
> > else if (IS_GEN9(dev_priv) ||
> > IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> > return max_cdclk_freq;
> > --
> > 2.19.1
>
> --
> Ville Syrjälä
> Intel
___
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Intel-gfx@lists.freedesktop.org
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Re: [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Prefer IS_GEN check with bitmask.
On Sat, Oct 27, 2018 at 05:24:41AM +, Patchwork wrote: > == Series Details == > > Series: series starting with [1/2] drm/i915: Prefer IS_GEN check with > bitmask. > URL : https://patchwork.freedesktop.org/series/51622/ > State : success > > == Summary == > > = CI Bug Log - changes from CI_DRM_5044_full -> Patchwork_10613_full = > > == Summary - SUCCESS == > > No regressions found. Thanks for reviews. Patches pushed to dinq. > > > > == Known issues == > > Here are the changes found in Patchwork_10613_full that come from known > issues: > > === IGT changes === > > Issues hit > > igt@drv_suspend@shrink: > shard-snb: PASS -> INCOMPLETE (fdo#106886, fdo#105411) > > igt@gem_cpu_reloc@full: > shard-skl: NOTRUN -> INCOMPLETE (fdo#108073) > > igt@gem_ctx_isolation@bcs0-s3: > shard-kbl: PASS -> INCOMPLETE (fdo#103665) > > igt@gem_exec_reloc@basic-gtt: > shard-snb: NOTRUN -> INCOMPLETE (fdo#105411) > > igt@kms_atomic_interruptible@legacy-dpms: > shard-apl: PASS -> DMESG-WARN (fdo#108549) +10 > > igt@kms_busy@extended-modeset-hang-newfb-render-a: > shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) +2 > > igt@kms_ccs@pipe-a-crc-primary-basic: > shard-skl: NOTRUN -> FAIL (fdo#107725) > > igt@kms_color@pipe-b-degamma: > shard-apl: PASS -> FAIL (fdo#104782) > > igt@kms_cursor_crc@cursor-128x128-suspend: > shard-glk: PASS -> FAIL (fdo#103232) +1 > > igt@kms_fbcon_fbt@psr: > shard-skl: NOTRUN -> FAIL (fdo#107882) > > igt@kms_flip@flip-vs-expired-vblank-interruptible: > shard-skl: PASS -> FAIL (fdo#105363) > shard-glk: PASS -> FAIL (fdo#105363) > > igt@kms_flip@plain-flip-ts-check-interruptible: > shard-skl: NOTRUN -> FAIL (fdo#100368) > > igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff: > shard-apl: PASS -> FAIL (fdo#103167) +1 > > igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-pwrite: > shard-glk: PASS -> FAIL (fdo#103167) +1 > > igt@kms_plane@pixel-format-pipe-c-planes: > shard-kbl: NOTRUN -> FAIL (fdo#103166) > > igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: > shard-skl: PASS -> INCOMPLETE (fdo#104108, fdo#107773) +1 > > igt@kms_plane_alpha_blend@pipe-a-alpha-7efc: > shard-skl: NOTRUN -> FAIL (fdo#108145, fdo#107815) +1 > > igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb: > shard-skl: NOTRUN -> FAIL (fdo#108145) +1 > > igt@kms_plane_multiple@atomic-pipe-c-tiling-x: > shard-glk: PASS -> FAIL (fdo#103166) +1 > > igt@kms_universal_plane@universal-plane-pipe-a-functional: > shard-apl: PASS -> FAIL (fdo#103166) > > igt@perf@polling: > shard-hsw: PASS -> FAIL (fdo#102252) > > > Possible fixes > > igt@drv_suspend@debugfs-reader: > shard-skl: INCOMPLETE (fdo#104108) -> PASS > > igt@gem_wait@write-wait-bsd1: > shard-snb: INCOMPLETE (fdo#105411) -> SKIP > > igt@gem_workarounds@suspend-resume-context: > shard-kbl: INCOMPLETE (fdo#103665) -> PASS > > igt@kms_ccs@pipe-b-crc-sprite-planes-basic: > shard-glk: FAIL (fdo#108145) -> PASS > > igt@kms_chv_cursor_fail@pipe-b-128x128-bottom-edge: > shard-skl: FAIL (fdo#104671) -> PASS > > igt@kms_color@pipe-b-ctm-max: > shard-apl: DMESG-WARN (fdo#108549) -> PASS +14 > > igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu: > shard-glk: DMESG-WARN (fdo#106538, fdo#105763) -> PASS +1 > > igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite: > shard-apl: FAIL (fdo#103167) -> PASS > > igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen: > shard-glk: FAIL (fdo#103167) -> PASS +1 > > igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: > shard-apl: FAIL (fdo#103375) -> PASS > > igt@kms_plane@plane-panning-top-left-pipe-b-planes: > shard-apl: INCOMPLETE (fdo#103927) -> PASS > > igt@kms_plane_multiple@atomic-pipe-b-tiling-yf: > shard-apl: FAIL (fdo#103166) -> PASS > > igt@kms_setmode@basic: > shard-apl: FAIL (fdo#99912) -> PASS > > igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend: > shard-snb: DMESG-WARN (fdo#102365) -> PASS > > igt@kms_vblank@pipe-c-ts-continuation-dpms-rpm: > shard-apl: DMESG-FAIL (fdo#108549) -> PASS > > igt@pm_rpm@dpms-lpsp: > shard-skl: INCOMPLETE (fdo#107807) -> PASS > > > Warnings > > igt@kms_cursor_crc@cursor-128x128-suspend: > shard-apl:
[Intel-gfx] [PATCH] drm/i915: Account for scale factor when calculating initial phase
From: Ville Syrjälä
To get the initial phase correct we need to account for the scale
factor as well. I forgot this initially and was mostly looking at
heavily upscaled content where the minor difference between -0.5
and the proper initial phase was not readily apparent.
And let's toss in a comment that tries to explain the formula
a little bit.
Cc: Maarten Lankhorst
Fixes: 0a59952b24e2 ("drm/i915: Configure SKL+ scaler initial phase correctly")
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 45 ++--
drivers/gpu/drm/i915/intel_drv.h | 2 +-
drivers/gpu/drm/i915/intel_sprite.c | 20 +
3 files changed, 57 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index fe045abb6472..c806909698fd 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4786,8 +4786,31 @@ static void cpt_verify_modeset(struct drm_device *dev,
int pipe)
* chroma samples for both of the luma samples, and thus we don't
* actually get the expected MPEG2 chroma siting convention :(
* The same behaviour is observed on pre-SKL platforms as well.
+ *
+ * Theory behind the formula (note that we ignore sub-pixel
+ * source coordinates):
+ * s = source sample position
+ * d = destination sample position
+ *
+ * Downscaling 4:1:
+ * -0.5
+ * | 0.0
+ * | | 1.5 (initial phase)
+ * | | |
+ * v v v
+ * | s | s | s | s |
+ * | d |
+ *
+ * Upscaling 1:4:
+ * -0.5
+ * | -0.375 (initial phase)
+ * | | 0.0
+ * | | |
+ * v v v
+ * | s |
+ * | d | d | d | d |
*/
-u16 skl_scaler_calc_phase(int sub, bool chroma_cosited)
+u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
{
int phase = -0x8000;
u16 trip = 0;
@@ -4795,6 +4818,15 @@ u16 skl_scaler_calc_phase(int sub, bool chroma_cosited)
if (chroma_cosited)
phase += (sub - 1) * 0x8000 / sub;
+ phase += scale / (2 * sub);
+
+ /*
+* Hardware initial phase limited to [-0.5:1.5].
+* Since the max hardware scale factor is 3.0, we
+* should never actually excdeed 1.0 here.
+*/
+ WARN_ON(phase < -0x8000 || phase > 0x18);
+
if (phase < 0)
phase = 0x1 + phase;
else
@@ -5003,13 +5035,20 @@ static void skylake_pfit_enable(const struct
intel_crtc_state *crtc_state)
if (crtc_state->pch_pfit.enabled) {
u16 uv_rgb_hphase, uv_rgb_vphase;
+ int pfit_w, pfit_h, hscale, vscale;
int id;
if (WARN_ON(crtc_state->scaler_state.scaler_id < 0))
return;
- uv_rgb_hphase = skl_scaler_calc_phase(1, false);
- uv_rgb_vphase = skl_scaler_calc_phase(1, false);
+ pfit_w = (crtc_state->pch_pfit.size >> 16) & 0x;
+ pfit_h = crtc_state->pch_pfit.size & 0x;
+
+ hscale = (crtc_state->pipe_src_w << 16) / pfit_w;
+ vscale = (crtc_state->pipe_src_h << 16) / pfit_h;
+
+ uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
+ uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
id = scaler_state->scaler_id;
I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index db24308729b4..86d551a331b1 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1709,7 +1709,7 @@ void intel_mode_from_pipe_config(struct drm_display_mode
*mode,
void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state);
-u16 skl_scaler_calc_phase(int sub, bool chroma_center);
+u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center);
int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
int skl_max_scale(const struct intel_crtc_state *crtc_state,
u32 pixel_format);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index cfaddc05fea6..fbb916506c77 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -326,27 +326,35 @@ skl_program_scaler(struct drm_i915_private *dev_priv,
uint32_t crtc_h = drm_rect_height(_state->base.dst);
u16 y_hphase, uv_rgb_hphase;
u16 y_vphase, uv_rgb_vphase;
+ int hscale, vscale;
/* Sizes are 0 based */
crtc_w--;
crtc_h--;
+ hscale = drm_rect_calc_hscale(_state->base.src,
+ _state->base.dst,
+ 0, INT_MAX);
+ vscale = drm_rect_calc_vscale(_state->base.src,
+ _state->base.dst,
+ 0, INT_MAX);
+
/* TODO: handle
[Intel-gfx] [CI] drm/i915/selftests: Test vm isolation
The vm of two contexts are supposed to be independent, such that a stray
write by one cannot be detected by another. Normally the GTT is filled
explicitly by userspace, but the space in between objects is filled with
a scratch page -- and that scratch page should not be able to form an
inter-context backchannel.
Signed-off-by: Chris Wilson
Cc: Matthew Auld
Cc: Joonas Lahtinen
Reviewed-by: Matthew Auld
---
.../gpu/drm/i915/selftests/i915_gem_context.c | 318 ++
1 file changed, 318 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
index 1be3b67a7c48..067303446a1c 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
@@ -760,6 +760,323 @@ static int igt_ctx_readonly(void *arg)
return err;
}
+static int check_scratch(struct i915_gem_context *ctx, u64 offset)
+{
+ struct drm_mm_node *node =
+ __drm_mm_interval_first(>ppgtt->vm.mm,
+ offset, offset + sizeof(u32) - 1);
+ if (!node || node->start > offset)
+ return 0;
+
+ GEM_BUG_ON(offset >= node->start + node->size);
+
+ pr_err("Target offset 0x%08x_%08x overlaps with a node in the mm!\n",
+ upper_32_bits(offset), lower_32_bits(offset));
+ return -EINVAL;
+}
+
+static int write_to_scratch(struct i915_gem_context *ctx,
+ struct intel_engine_cs *engine,
+ u64 offset, u32 value)
+{
+ struct drm_i915_private *i915 = ctx->i915;
+ struct drm_i915_gem_object *obj;
+ struct i915_request *rq;
+ struct i915_vma *vma;
+ u32 *cmd;
+ int err;
+
+ GEM_BUG_ON(offset < I915_GTT_PAGE_SIZE);
+
+ obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
+ if (IS_ERR(obj))
+ return PTR_ERR(obj);
+
+ cmd = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ if (IS_ERR(cmd)) {
+ err = PTR_ERR(cmd);
+ goto err;
+ }
+
+ *cmd++ = MI_STORE_DWORD_IMM_GEN4;
+ if (INTEL_GEN(i915) >= 8) {
+ *cmd++ = lower_32_bits(offset);
+ *cmd++ = upper_32_bits(offset);
+ } else {
+ *cmd++ = 0;
+ *cmd++ = offset;
+ }
+ *cmd++ = value;
+ *cmd = MI_BATCH_BUFFER_END;
+ i915_gem_object_unpin_map(obj);
+
+ err = i915_gem_object_set_to_gtt_domain(obj, false);
+ if (err)
+ goto err;
+
+ vma = i915_vma_instance(obj, >ppgtt->vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto err;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER | PIN_OFFSET_FIXED);
+ if (err)
+ goto err;
+
+ err = check_scratch(ctx, offset);
+ if (err)
+ goto err_unpin;
+
+ rq = i915_request_alloc(engine, ctx);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto err_unpin;
+ }
+
+ err = engine->emit_bb_start(rq, vma->node.start, vma->node.size, 0);
+ if (err)
+ goto err_request;
+
+ err = i915_vma_move_to_active(vma, rq, 0);
+ if (err)
+ goto skip_request;
+
+ i915_gem_object_set_active_reference(obj);
+ i915_vma_unpin(vma);
+ i915_vma_close(vma);
+
+ i915_request_add(rq);
+
+ return 0;
+
+skip_request:
+ i915_request_skip(rq, err);
+err_request:
+ i915_request_add(rq);
+err_unpin:
+ i915_vma_unpin(vma);
+err:
+ i915_gem_object_put(obj);
+ return err;
+}
+
+static int read_from_scratch(struct i915_gem_context *ctx,
+struct intel_engine_cs *engine,
+u64 offset, u32 *value)
+{
+ struct drm_i915_private *i915 = ctx->i915;
+ struct drm_i915_gem_object *obj;
+ struct i915_request *rq;
+ struct i915_vma *vma;
+ const u32 RCS_GPR0 = 0x2600;
+ const u32 result = 0x100;
+ u32 *cmd;
+ int err;
+
+ GEM_BUG_ON(offset < I915_GTT_PAGE_SIZE);
+
+ obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
+ if (IS_ERR(obj))
+ return PTR_ERR(obj);
+
+ cmd = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ if (IS_ERR(cmd)) {
+ err = PTR_ERR(cmd);
+ goto err;
+ }
+
+ memset(cmd, POISON_INUSE, PAGE_SIZE);
+ if (INTEL_GEN(i915) >= 8) {
+ *cmd++ = MI_LOAD_REGISTER_MEM_GEN8;
+ *cmd++ = RCS_GPR0;
+ *cmd++ = lower_32_bits(offset);
+ *cmd++ = upper_32_bits(offset);
+ *cmd++ = MI_STORE_REGISTER_MEM_GEN8;
+ *cmd++ = RCS_GPR0;
+ *cmd++ = result;
+ *cmd++ = 0;
+ } else {
+ *cmd++ = MI_LOAD_REGISTER_MEM;
+ *cmd++ = RCS_GPR0;
+
Re: [Intel-gfx] [PATCH] drm/i915: Fix the HDMI hot plug disconnection failure (v2)
On Tue, 23 Oct 2018 17:14:34 +0800
Chris Chiu wrote:
> On Thu, Oct 11, 2018 at 2:04 AM Guang Bai wrote:
>
> > On Mon, 8 Oct 2018 08:56:20 -0700
> > Guang Bai wrote:
> >
> > > On Mon, 8 Oct 2018 22:35:34 +0800
> > > Chris Chiu wrote:
> > >
> > > > Thanks! I have no problem with this patch.
> > >
> > > There are Fi.CI.BAT failures with the v2 (only with formatting fix
> > > added) while the previous patch had passing results.
> > > Now trying to identify why the failures happened with trybot
> > > Thanks,
> > > Guang
> > The tribot run my patch twice and passes the tests without any error
> > however I'm recommended to chase down root causes of Patchwork
> > Fi.CI.BAT test errors still - WIP on that.
> > Thanks,
> > Guang
> >
>
> Gentle ping. Any good news on this?
>
> Chris
>
Sorry...was distracted by other dev taks...will get update ASAP.
-Guang
>
> > >
> > > >
> > > > On Thu, Oct 4, 2018 at 2:08 AM Guang Bai
> > > > wrote:
> > > > > On some platforms, slowly unplugging (wiggling) the HDMI cable
> > > > > makes the kernel to believe the HDMI display still connected.
> > > > > This is because the HDMI DDC lines are disconnected sometimes
> > > > > later after the hot-plug interrupt triggered. Use the hot plug
> > > > > live states to honor HDMI hot plug status in addtion to access
> > > > > the DDC channels.
> > > > >
> > > > > v2: Fix the formatting issue
> > > > >
> > > > > Cc: Jani Nikula
> > > > > Cc: Chris Chiu
> > > > > Signed-off-by: Guang Bai
> > > > > ---
> > > > > drivers/gpu/drm/i915/intel_hotplug.c | 32
> > > > > +--- 1 file changed, 29
> > > > > insertions(+), 3 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/intel_hotplug.c
> > > > > b/drivers/gpu/drm/i915/intel_hotplug.c
> > > > > index 648a13c..98ab1ab 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_hotplug.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_hotplug.c
> > > > > @@ -246,17 +246,43 @@ static void
> > > > > intel_hpd_irq_storm_reenable_work(struct work_struct *work)
> > > > > intel_runtime_pm_put(dev_priv);
> > > > > }
> > > > >
> > > > > +#define MAX_SHORT_PULSE_MS 100
> > > > > +#define PORT_CHECK_LOOP_COUNT 3
> > > > > +
> > > > > bool intel_encoder_hotplug(struct intel_encoder *encoder,
> > > > >struct intel_connector *connector)
> > > > > {
> > > > > struct drm_device *dev = connector->base.dev;
> > > > > - enum drm_connector_status old_status;
> > > > > + enum drm_connector_status old_status, new_status;
> > > > > + enum hpd_pin pin = encoder->hpd_pin;
> > > > > + struct drm_i915_private *dev_priv =
> > > > > to_i915(encoder->base.dev);
> > > > > + u32 count = 0;
> > > > >
> > > > > WARN_ON(!mutex_is_locked(>mode_config.mutex));
> > > > > old_status = connector->base.status;
> > > > >
> > > > > - connector->base.status =
> > > > > - drm_helper_probe_detect(>base,
> > > > > NULL, false);
> > > > > + /*
> > > > > +* Set HDMI connection status based on hot-plug live
> > > > > states and
> > > > > +* display probe results.
> > > > > +*/
> > > > > + if ((encoder->type == INTEL_OUTPUT_HDMI ||
> > > > > +encoder->type == INTEL_OUTPUT_DDI) &&
> > > > > + dev_priv->hotplug.stats[pin].state ==
> > > > > HPD_ENABLED) {
> > > > > + do {
> > > > > + new_status =
> > > > > connector_status_disconnected;
> > > > > + msleep(MAX_SHORT_PULSE_MS);
> > > > > +
> > > > > + if
> > > > > (intel_digital_port_connected(encoder))
> > > > > + new_status =
> > > > > drm_helper_probe_detect(>base,
> > > > > +
> > > > > NULL, false);
> > > > > + if (new_status ==
> > > > > connector_status_connected)
> > > > > + break;
> > > > > + } while (++count <= PORT_CHECK_LOOP_COUNT);
> > > > > + connector->base.status = new_status;
> > > > > + } else {
> > > > > + connector->base.status =
> > > > > +
> > > > > drm_helper_probe_detect(>base, NULL, false);
> > > > > + }
> > > > >
> > > > > if (old_status == connector->base.status)
> > > > > return false;
> > > > > --
> > > > > 2.7.4
> > > > >
> > > > >
> > >
> > > ___
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> >
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: Test vm isolation (rev2)
== Series Details == Series: drm/i915/selftests: Test vm isolation (rev2) URL : https://patchwork.freedesktop.org/series/51689/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_5047 -> Patchwork_10628 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10628 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10628, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/51689/revisions/2/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10628: === IGT changes === Possible regressions igt@drv_selftest@live_contexts: fi-byt-j1900: PASS -> DMESG-FAIL Warnings igt@pm_rpm@module-reload: fi-hsw-4770r: SKIP -> PASS == Known issues == Here are the changes found in Patchwork_10628 that come from known issues: === IGT changes === Issues hit igt@gem_exec_suspend@basic-s3: fi-kbl-soraka: NOTRUN -> INCOMPLETE (fdo#107774, fdo#107859, fdo#107556) igt@kms_flip@basic-flip-vs-dpms: fi-hsw-4770r: PASS -> DMESG-WARN (fdo#105602) igt@kms_flip@basic-flip-vs-modeset: fi-skl-6700hq: PASS -> DMESG-WARN (fdo#105998) igt@pm_rpm@module-reload: fi-skl-6600u: PASS -> INCOMPLETE (fdo#107807) Possible fixes igt@drv_module_reload@basic-reload-inject: fi-hsw-4770r: DMESG-WARN (fdo#107924, fdo#107425) -> PASS igt@gem_exec_suspend@basic-s4-devices: fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602 fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998 fdo#107425 https://bugs.freedesktop.org/show_bug.cgi?id=107425 fdo#107556 https://bugs.freedesktop.org/show_bug.cgi?id=107556 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#107774 https://bugs.freedesktop.org/show_bug.cgi?id=107774 fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807 fdo#107859 https://bugs.freedesktop.org/show_bug.cgi?id=107859 fdo#107924 https://bugs.freedesktop.org/show_bug.cgi?id=107924 == Participating hosts (46 -> 44) == Additional (1): fi-kbl-soraka Missing(3): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan == Build changes == * Linux: CI_DRM_5047 -> Patchwork_10628 CI_DRM_5047: cc8c29937b897a11db4c0e874029ea83f6eaa10a @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4699: 1270ec553741ac20c45178d2b26f9a9562ea565f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10628: bb703a5b47b6a1165abd0ee6ad15abd052e6a8f8 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == bb703a5b47b6 drm/i915/selftests: Test vm isolation == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10628/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for HAX: poison the CSB after use (rev3)
== Series Details == Series: HAX: poison the CSB after use (rev3) URL : https://patchwork.freedesktop.org/series/51677/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5045_full -> Patchwork_10626_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_10626_full that come from known issues: === IGT changes === Issues hit igt@gem_exec_whisper@normal: shard-skl: NOTRUN -> TIMEOUT (fdo#108592) igt@gem_ppgtt@blt-vs-render-ctxn: shard-kbl: PASS -> INCOMPLETE (fdo#106023, fdo#103665, fdo#106887) shard-skl: NOTRUN -> TIMEOUT (fdo#108039) igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a: shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) igt@kms_ccs@pipe-a-crc-sprite-planes-basic: shard-glk: PASS -> FAIL (fdo#108145) igt@kms_chv_cursor_fail@pipe-b-256x256-bottom-edge: shard-skl: NOTRUN -> FAIL (fdo#104671) igt@kms_color@pipe-a-legacy-gamma: shard-apl: PASS -> FAIL (fdo#108145, fdo#104782) igt@kms_cursor_crc@cursor-128x42-sliding: shard-apl: PASS -> FAIL (fdo#103232) +5 igt@kms_cursor_crc@cursor-256x256-random: shard-glk: PASS -> FAIL (fdo#103232) igt@kms_cursor_crc@cursor-256x256-suspend: shard-skl: PASS -> INCOMPLETE (fdo#104108, fdo#107773) +1 igt@kms_cursor_crc@cursor-64x21-random: shard-skl: NOTRUN -> FAIL (fdo#103232) igt@kms_flip@flip-vs-expired-vblank-interruptible: shard-skl: PASS -> FAIL (fdo#105363) igt@kms_flip@plain-flip-fb-recreate: shard-apl: PASS -> INCOMPLETE (fdo#103927) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu: shard-skl: NOTRUN -> FAIL (fdo#103167) +3 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite: shard-apl: PASS -> FAIL (fdo#103167) igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff: shard-glk: PASS -> FAIL (fdo#103167) +4 igt@kms_plane@pixel-format-pipe-b-planes: shard-skl: NOTRUN -> DMESG-FAIL (fdo#106885, fdo#103166) igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: shard-skl: PASS -> INCOMPLETE (fdo#104108) igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max: shard-skl: NOTRUN -> FAIL (fdo#108145) +4 igt@kms_plane_alpha_blend@pipe-b-alpha-7efc: shard-skl: NOTRUN -> FAIL (fdo#107815, fdo#108145) +1 igt@kms_plane_multiple@atomic-pipe-a-tiling-y: shard-glk: PASS -> FAIL (fdo#103166) +2 igt@kms_plane_multiple@atomic-pipe-a-tiling-yf: shard-apl: PASS -> FAIL (fdo#103166) igt@kms_setmode@basic: shard-kbl: PASS -> FAIL (fdo#99912) igt@pm_backlight@fade_with_suspend: shard-skl: NOTRUN -> FAIL (fdo#107847) igt@pm_rpm@cursor: shard-skl: NOTRUN -> INCOMPLETE (fdo#107807) Possible fixes igt@kms_cursor_crc@cursor-128x128-suspend: shard-skl: INCOMPLETE (fdo#104108) -> PASS igt@kms_cursor_crc@cursor-64x21-sliding: shard-apl: FAIL (fdo#103232) -> PASS +1 igt@kms_cursor_legacy@pipe-a-torture-move: shard-skl: INCOMPLETE -> PASS igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled: shard-glk: FAIL (fdo#103184) -> PASS igt@kms_flip@flip-vs-expired-vblank: shard-skl: FAIL (fdo#105363) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt: shard-apl: FAIL (fdo#103167) -> PASS +1 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite: shard-glk: FAIL (fdo#103167) -> PASS +2 igt@kms_plane_multiple@atomic-pipe-a-tiling-x: shard-apl: FAIL (fdo#103166) -> PASS igt@kms_plane_multiple@atomic-pipe-c-tiling-y: shard-glk: FAIL (fdo#103166) -> PASS igt@pm_rpm@gem-execbuf: shard-skl: INCOMPLETE (fdo#107803, fdo#107807) -> PASS fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103184 https://bugs.freedesktop.org/show_bug.cgi?id=103184 fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108 fdo#104671 https://bugs.freedesktop.org/show_bug.cgi?id=104671 fdo#104782 https://bugs.freedesktop.org/show_bug.cgi?id=104782 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023 fdo#106885 https://bugs.freedesktop.org/show_bug.cgi?id=106885
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Test vm isolation (rev2)
== Series Details == Series: drm/i915/selftests: Test vm isolation (rev2) URL : https://patchwork.freedesktop.org/series/51689/ State : warning == Summary == $ dim checkpatch origin/drm-tip bb703a5b47b6 drm/i915/selftests: Test vm isolation -:242: WARNING:LINE_SPACING: Missing a blank line after declarations #242: FILE: drivers/gpu/drm/i915/selftests/i915_gem_context.c:980: + struct drm_file *file; + I915_RND_STATE(prng); total: 0 errors, 1 warnings, 0 checks, 330 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 2/4] drm/dp_mst: Start tracking per-port VCPI allocations
On Mon, 2018-10-29 at 15:24 +0100, Daniel Vetter wrote:
> On Fri, Oct 26, 2018 at 04:35:47PM -0400, Lyude Paul wrote:
> > There has been a TODO waiting for quite a long time in
> > drm_dp_mst_topology.c:
> >
> > /* We cannot rely on port->vcpi.num_slots to update
> > * topology_state->avail_slots as the port may not exist if the parent
> > * branch device was unplugged. This should be fixed by tracking
> > * per-port slot allocation in drm_dp_mst_topology_state instead of
> > * depending on the caller to tell us how many slots to release.
> > */
> >
> > That's not the only reason we should fix this: forcing the driver to
> > track the VCPI allocations throughout a state's atomic check is
> > error prone, because it means that extra care has to be taken with the
> > order that drm_dp_atomic_find_vcpi_slots() and
> > drm_dp_atomic_release_vcpi_slots() are called in in order to ensure
> > idempotency. Currently the only driver actually using these helpers,
> > i915, doesn't even do this correctly: multiple ->best_encoder() checks
> > with i915's current implementation would not be idempotent and would
> > over-allocate VCPI slots, something I learned trying to implement
> > fallback retraining in MST.
> >
> > So: simplify this whole mess, and teach drm_dp_atomic_find_vcpi_slots()
> > and drm_dp_atomic_release_vcpi_slots() to track the VCPI allocations for
> > each port. This allows us to ensure idempotency without having to rely
> > on the driver as much. Additionally: the driver doesn't need to do any
> > kind of VCPI slot tracking anymore if it doesn't need it for it's own
> > internal state.
> >
> > Additionally; this adds a new drm_dp_mst_atomic_check() helper which
> > must be used by atomic drivers to perform validity checks for the new
> > VCPI allocations incurred by a state.
> >
> > Also: update the documentation and make it more obvious that these
> > /must/ be called by /all/ atomic drivers supporting MST.
> >
> > Changes since v1:
> > - Don't use the now-removed ->atomic_check() for private objects hook,
> >just give drivers a function to call themselves
> >
> > Signed-off-by: Lyude Paul
> > Cc: Daniel Vetter
> > ---
> > drivers/gpu/drm/drm_dp_mst_topology.c | 190 +-
> > drivers/gpu/drm/i915/intel_display.c | 8 ++
> > drivers/gpu/drm/i915/intel_dp_mst.c | 31 +++--
> > include/drm/drm_dp_mst_helper.h | 11 +-
> > 4 files changed, 192 insertions(+), 48 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
> > b/drivers/gpu/drm/drm_dp_mst_topology.c
> > index 8c3cfac437f4..dcfab7536914 100644
> > --- a/drivers/gpu/drm/drm_dp_mst_topology.c
> > +++ b/drivers/gpu/drm/drm_dp_mst_topology.c
> > @@ -2614,21 +2614,33 @@ static int drm_dp_init_vcpi(struct
> > drm_dp_mst_topology_mgr *mgr,
> > }
> >
> > /**
> > - * drm_dp_atomic_find_vcpi_slots() - Find and add vcpi slots to the state
> > + * drm_dp_atomic_find_vcpi_slots() - Find and add VCPI slots to the state
> > * @state: global atomic state
> > * @mgr: MST topology manager for the port
> > * @port: port to find vcpi slots for
> > * @pbn: bandwidth required for the mode in PBN
> > *
> > + * Allocates VCPI slots to @port, replacing any previous VCPI allocations
> > it
> > + * may have had. Any atomic drivers which support MST must call this
> > function
> > + * in their atomic_check() handlers to change the current VCPI allocation
> > for
>
> Maybe do a nice kerneldoc reference to the right atomic_check here.
>
> > + * the new state. After the ->atomic_check() hooks of the driver and all
> > other
>
> This will upset the kerneldoc parser I think.
>
> > + * mode objects in the state have been called, DRM will check the final
> > VCPI
> > + * allocations to ensure that they will fit into the available bandwidth
> > on
> > + * the topology.
> > + *
> > + * See also: drm_dp_atomic_release_vcpi_slots()
>
> Also need to reference drm_dp_mst_atomic_check() here and that drivers
> must call it or nothing happens.
> > + *
> > * RETURNS:
> > - * Total slots in the atomic state assigned for this port or error
> > + * Total slots in the atomic state assigned for this port, or a negative
> > error
> > + * code if the port no longer exists
> > */
> > int drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state,
> > struct drm_dp_mst_topology_mgr *mgr,
> > struct drm_dp_mst_port *port, int pbn)
> > {
> > struct drm_dp_mst_topology_state *topology_state;
> > - int req_slots;
> > + struct drm_dp_vcpi_allocation *pos, *vcpi = NULL;
> > + int prev_slots, req_slots, ret;
> >
> > topology_state = drm_atomic_get_mst_topology_state(state, mgr);
> > if (IS_ERR(topology_state))
> > @@ -2637,20 +2649,41 @@ int drm_dp_atomic_find_vcpi_slots(struct
> > drm_atomic_state *state,
> > port = drm_dp_get_validated_port_ref(mgr, port);
> > if (port == NULL)
> >
