[Intel-gfx] ✓ Fi.CI.IGT: success for Remaining DSC + FEC patches
== Series Details == Series: Remaining DSC + FEC patches URL : https://patchwork.freedesktop.org/series/52461/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5134_full -> Patchwork_10822_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_10822_full that come from known issues: === IGT changes === Issues hit igt@drv_suspend@shrink: shard-apl: PASS -> INCOMPLETE (fdo#106886, fdo#103927) igt@gem_exec_schedule@pi-ringfull-render: shard-skl: NOTRUN -> FAIL (fdo#103158) igt@gem_ppgtt@blt-vs-render-ctx0: shard-skl: NOTRUN -> TIMEOUT (fdo#108039) shard-kbl: PASS -> INCOMPLETE (fdo#106887, fdo#106023, fdo#103665) igt@gem_userptr_blits@readonly-unsync: shard-skl: NOTRUN -> INCOMPLETE (fdo#108074) igt@kms_available_modes_crc@available_mode_test_crc: shard-skl: NOTRUN -> FAIL (fdo#106641) igt@kms_busy@extended-modeset-hang-newfb-render-a: shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) +2 igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b: shard-kbl: PASS -> DMESG-WARN (fdo#107956) igt@kms_ccs@pipe-b-crc-sprite-planes-basic: shard-glk: PASS -> FAIL (fdo#108145) igt@kms_color@pipe-a-ctm-0-75: shard-skl: NOTRUN -> FAIL (fdo#108682) igt@kms_fbcon_fbt@psr: shard-skl: NOTRUN -> FAIL (fdo#107882) igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw: shard-skl: NOTRUN -> FAIL (fdo#103167) +2 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen: shard-glk: PASS -> FAIL (fdo#103167) +2 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move: shard-apl: PASS -> FAIL (fdo#103167) igt@kms_frontbuffer_tracking@fbc-rgb565-draw-render: shard-skl: NOTRUN -> FAIL (fdo#105682) +1 igt@kms_frontbuffer_tracking@fbcpsr-stridechange: shard-skl: NOTRUN -> FAIL (fdo#105683) igt@kms_plane@pixel-format-pipe-b-planes: shard-skl: NOTRUN -> DMESG-WARN (fdo#106885) +1 igt@kms_plane@plane-position-covered-pipe-b-planes: shard-glk: PASS -> FAIL (fdo#103166) +1 igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb: shard-skl: NOTRUN -> FAIL (fdo#108145) +3 igt@kms_rotation_crc@primary-rotation-90: shard-skl: NOTRUN -> FAIL (fdo#103925, fdo#107815) Possible fixes igt@kms_flip@2x-dpms-vs-vblank-race: shard-hsw: DMESG-WARN (fdo#102614) -> PASS igt@kms_flip@flip-vs-expired-vblank: shard-skl: FAIL (fdo#105363) -> PASS igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff: shard-glk: FAIL (fdo#103167) -> PASS igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max: shard-glk: FAIL (fdo#108145) -> PASS igt@kms_plane_multiple@atomic-pipe-b-tiling-y: shard-glk: FAIL (fdo#103166) -> PASS igt@kms_plane_multiple@atomic-pipe-c-tiling-y: shard-apl: FAIL (fdo#103166) -> PASS +1 igt@perf@polling: shard-hsw: FAIL (fdo#102252) -> PASS igt@perf_pmu@busy-start-vcs0: shard-kbl: DMESG-WARN (fdo#103558, fdo#105602) -> PASS igt@pm_rpm@basic-rte: shard-skl: INCOMPLETE (fdo#107807) -> PASS igt@pm_rpm@dpms-mode-unset-non-lpsp: shard-skl: INCOMPLETE (fdo#107807) -> SKIP fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158 fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602 fdo#105682 https://bugs.freedesktop.org/show_bug.cgi?id=105682 fdo#105683 https://bugs.freedesktop.org/show_bug.cgi?id=105683 fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023 fdo#106641 https://bugs.freedesktop.org/show_bug.cgi?id=106641 fdo#106885 https://bugs.freedesktop.org/show_bug.cgi?id=106885 fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886 fdo#106887 https://bugs.freedesktop.org/show_bug.cgi?id=106887 fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807 fdo#107815 https://bugs.freedesktop.org/show_bug.cgi?id=107815 fdo#107882 https://bugs.freedesktop.org/show_bug.cgi?id=107882 fdo#107956
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: don't apply Display WAs 1125 and 1126 to GLK/CNL+
== Series Details == Series: drm/i915: don't apply Display WAs 1125 and 1126 to GLK/CNL+ URL : https://patchwork.freedesktop.org/series/52460/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5134_full -> Patchwork_10821_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_10821_full that come from known issues: === IGT changes === Issues hit igt@gem_exec_schedule@pi-ringfull-render: shard-skl: NOTRUN -> FAIL (fdo#103158) igt@gem_exec_schedule@preempt-self-blt: shard-snb: NOTRUN -> INCOMPLETE (fdo#105411) igt@gem_ppgtt@blt-vs-render-ctx0: shard-kbl: PASS -> INCOMPLETE (fdo#103665, fdo#106887, fdo#106023) igt@kms_available_modes_crc@available_mode_test_crc: shard-skl: NOTRUN -> FAIL (fdo#106641) igt@kms_busy@extended-modeset-hang-newfb-render-a: shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) +1 igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b: shard-kbl: PASS -> DMESG-WARN (fdo#107956) igt@kms_cursor_crc@cursor-128x128-sliding: shard-apl: PASS -> FAIL (fdo#103232) igt@kms_fbcon_fbt@psr: shard-skl: NOTRUN -> FAIL (fdo#107882) igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw: shard-skl: NOTRUN -> FAIL (fdo#103167) +3 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu: shard-apl: PASS -> FAIL (fdo#103167) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite: shard-glk: PASS -> FAIL (fdo#103167) +1 igt@kms_frontbuffer_tracking@fbc-rgb565-draw-render: shard-skl: NOTRUN -> FAIL (fdo#105682) igt@kms_frontbuffer_tracking@fbcpsr-stridechange: shard-skl: NOTRUN -> FAIL (fdo#105683) igt@kms_plane@pixel-format-pipe-b-planes: shard-skl: NOTRUN -> DMESG-WARN (fdo#106885) +1 igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max: shard-skl: NOTRUN -> FAIL (fdo#108145) +5 igt@kms_plane_multiple@atomic-pipe-a-tiling-yf: shard-glk: PASS -> FAIL (fdo#103166) igt@kms_rotation_crc@primary-rotation-90: shard-skl: NOTRUN -> FAIL (fdo#107815, fdo#103925) igt@kms_setmode@basic: shard-apl: PASS -> FAIL (fdo#99912) shard-kbl: PASS -> FAIL (fdo#99912) igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend: shard-skl: PASS -> INCOMPLETE (fdo#107773, fdo#104108) +1 igt@pm_rpm@dpms-mode-unset-lpsp: shard-skl: PASS -> INCOMPLETE (fdo#107807) Possible fixes igt@gem_cpu_reloc@full: shard-skl: INCOMPLETE (fdo#108073) -> PASS igt@kms_cursor_crc@cursor-256x256-suspend: shard-apl: FAIL (fdo#103191, fdo#103232) -> PASS igt@kms_flip@2x-dpms-vs-vblank-race: shard-hsw: DMESG-WARN (fdo#102614) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite: shard-apl: FAIL (fdo#103167) -> PASS +1 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move: shard-glk: FAIL (fdo#103167) -> PASS igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max: shard-glk: FAIL (fdo#108145) -> PASS igt@kms_plane_multiple@atomic-pipe-b-tiling-y: shard-glk: FAIL (fdo#103166) -> PASS +1 igt@kms_plane_multiple@atomic-pipe-c-tiling-y: shard-apl: FAIL (fdo#103166) -> PASS igt@perf@polling: shard-hsw: FAIL (fdo#102252) -> PASS igt@perf_pmu@busy-start-vcs0: shard-kbl: DMESG-WARN (fdo#103558, fdo#105602) -> PASS igt@pm_rpm@basic-rte: shard-skl: INCOMPLETE (fdo#107807) -> PASS +1 igt@pm_rpm@dpms-mode-unset-non-lpsp: shard-skl: INCOMPLETE (fdo#107807) -> SKIP Warnings igt@kms_vblank@pipe-a-query-busy: shard-snb: INCOMPLETE (fdo#105411) -> DMESG-WARN (fdo#107469) fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158 fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232 fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925 fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602 fdo#105682
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v3,1/3] drm/i915/icl: replace check for combo phy
== Series Details == Series: series starting with [v3,1/3] drm/i915/icl: replace check for combo phy URL : https://patchwork.freedesktop.org/series/52459/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5134_full -> Patchwork_10820_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_10820_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10820_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10820_full: === IGT changes === Warnings igt@perf_pmu@rc6: shard-kbl: PASS -> SKIP == Known issues == Here are the changes found in Patchwork_10820_full that come from known issues: === IGT changes === Issues hit igt@gem_ppgtt@blt-vs-render-ctx0: shard-skl: NOTRUN -> TIMEOUT (fdo#108039) shard-kbl: PASS -> INCOMPLETE (fdo#106887, fdo#103665, fdo#106023) igt@kms_available_modes_crc@available_mode_test_crc: shard-skl: NOTRUN -> FAIL (fdo#106641) igt@kms_busy@extended-modeset-hang-newfb-render-a: shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) +2 igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b: shard-kbl: PASS -> DMESG-WARN (fdo#107956) igt@kms_ccs@pipe-b-crc-sprite-planes-basic: shard-glk: PASS -> FAIL (fdo#108145) igt@kms_cursor_crc@cursor-256x256-sliding: shard-apl: PASS -> FAIL (fdo#103232) igt@kms_flip@flip-vs-expired-vblank: shard-glk: PASS -> FAIL (fdo#105363) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt: shard-glk: PASS -> FAIL (fdo#103167) +1 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render: shard-apl: PASS -> FAIL (fdo#103167) +2 igt@kms_frontbuffer_tracking@fbcpsr-stridechange: shard-skl: NOTRUN -> FAIL (fdo#105683) igt@kms_plane@pixel-format-pipe-b-planes: shard-skl: NOTRUN -> DMESG-WARN (fdo#106885) igt@kms_plane@plane-panning-bottom-right-pipe-b-planes: shard-skl: NOTRUN -> FAIL (fdo#103166) igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb: shard-skl: NOTRUN -> FAIL (fdo#108145) +5 igt@kms_plane_alpha_blend@pipe-b-alpha-7efc: shard-skl: NOTRUN -> FAIL (fdo#108145, fdo#107815) igt@kms_plane_multiple@atomic-pipe-a-tiling-x: shard-apl: PASS -> FAIL (fdo#103166) igt@kms_plane_multiple@atomic-pipe-a-tiling-yf: shard-glk: PASS -> FAIL (fdo#103166) igt@kms_properties@connector-properties-legacy: shard-kbl: PASS -> DMESG-WARN (fdo#105345, fdo#103313) igt@kms_setmode@basic: shard-apl: PASS -> FAIL (fdo#99912) shard-kbl: PASS -> FAIL (fdo#99912) igt@pm_backlight@fade_with_suspend: shard-skl: NOTRUN -> FAIL (fdo#107847) Possible fixes igt@kms_flip@2x-dpms-vs-vblank-race: shard-hsw: DMESG-WARN (fdo#102614) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite: shard-apl: FAIL (fdo#103167) -> PASS +1 igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max: shard-glk: FAIL (fdo#108145) -> PASS igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: shard-skl: FAIL (fdo#107815) -> PASS igt@kms_plane_multiple@atomic-pipe-b-tiling-y: shard-glk: FAIL (fdo#103166) -> PASS +1 shard-apl: FAIL (fdo#103166) -> PASS +2 igt@perf@polling: shard-hsw: FAIL (fdo#102252) -> PASS igt@perf_pmu@busy-start-vcs0: shard-kbl: DMESG-WARN (fdo#103558, fdo#105602) -> PASS igt@pm_rpm@debugfs-forcewake-user: shard-skl: INCOMPLETE (fdo#107807) -> PASS igt@pm_rpm@dpms-mode-unset-non-lpsp: shard-skl: INCOMPLETE (fdo#107807) -> SKIP fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232 fdo#103313 https://bugs.freedesktop.org/show_bug.cgi?id=103313 fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#105345 https://bugs.freedesktop.org/show_bug.cgi?id=105345 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602 fdo#105683
[Intel-gfx] ✓ Fi.CI.BAT: success for Remaining DSC + FEC patches
== Series Details == Series: Remaining DSC + FEC patches URL : https://patchwork.freedesktop.org/series/52461/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5134 -> Patchwork_10822 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/52461/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10822 that come from known issues: === IGT changes === Issues hit igt@drv_module_reload@basic-reload: fi-ilk-650: PASS -> DMESG-WARN (fdo#106387) +1 igt@drv_selftest@live_hangcheck: fi-skl-guc: PASS -> DMESG-FAIL (fdo#108593) igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a: fi-byt-clapper: PASS -> FAIL (fdo#107362) Possible fixes igt@drv_module_reload@basic-no-display: fi-byt-clapper: WARN (fdo#108688) -> PASS igt@drv_selftest@live_evict: fi-bsw-kefka: DMESG-WARN (fdo#107709) -> PASS igt@kms_chamelium@common-hpd-after-suspend: fi-skl-6700k2: WARN (fdo#108680) -> PASS igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: DMESG-WARN (fdo#102614) -> PASS igt@kms_pipe_crc_basic@hang-read-crc-pipe-a: fi-byt-clapper: FAIL (fdo#103191, fdo#107362) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-cfl-8109u: DMESG-WARN (fdo#107345) -> PASS +1 fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#106387 https://bugs.freedesktop.org/show_bug.cgi?id=106387 fdo#107345 https://bugs.freedesktop.org/show_bug.cgi?id=107345 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107709 https://bugs.freedesktop.org/show_bug.cgi?id=107709 fdo#108593 https://bugs.freedesktop.org/show_bug.cgi?id=108593 fdo#108680 https://bugs.freedesktop.org/show_bug.cgi?id=108680 fdo#108688 https://bugs.freedesktop.org/show_bug.cgi?id=108688 == Participating hosts (51 -> 44) == Missing(7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-icl-u == Build changes == * Linux: CI_DRM_5134 -> Patchwork_10822 CI_DRM_5134: 76f4cff023b23764df2956ad64a0840bfebd7ca4 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4714: cab148ca3ec904a94d0cd43476cf7e1f8663f906 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10822: a3127f4f2f7bbc612b2a677cbde1940a84d373f2 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == a3127f4f2f7b drm/i915/fec: Disable FEC state. 054e17f42f24 i915/dp/fec: Configure the Forward Error Correction bits. 0aeb642c2e15 drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION f33cddff8435 i915/dp/fec: Add fec_enable to the crtc state. 35c693dd421d drm/i915/dsc: Add Per connector debugfs node for DSC support/enable 9fe2d8f29a56 drm/i915/dsc: Enable and disable appropriate power wells for VDSC 4b3e4c773bf4 drm/i915/dp: Disable DSC in source by disabling DSS CTL bits bc5d8173bf92 drm/i915/dp: Configure Display stream splitter registers during DSC enable c5a9d7a3edb0 drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes e9add730ac8e drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs a7a9b4502148 drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling bb92419095f2 drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI 7411ddd14780 drm/i915/dp: Enable/Disable DSC in DP Sink 44af64fc1f3c drm/i915/dsc: Compute Rate Control parameters for DSC 63f59e9e7a3b drm/i915/dsc: Define & Compute VESA DSC params 969277b592d1 drm/i915/dp: Do not enable PSR2 if DSC is enabled 2c83276c3c4c drm/i915/dp: Compute DSC pipe config in atomic check 96ce38e6a2ff drm/i915/dp: Add DSC params and DSC config to intel_crtc_state 7b3dae68ebbf drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants 7672bdc04d1d drm/dsc: Add helpers for DSC picture parameter set infoframes 8b49256df332 drm/dsc: Define Rate Control values that do not change over configurations bccacb6d076d drm/dsc: Define VESA Display Stream Compression Capabilities d5bda8fc9dfd drm/dsc: Define Display Stream Compression PPS infoframe b72e39779b9c drm/dsc: Modify DRM helper to return complete DSC color depth capabilities == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10822/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: don't apply Display WAs 1125 and 1126 to GLK/CNL+
== Series Details == Series: drm/i915: don't apply Display WAs 1125 and 1126 to GLK/CNL+ URL : https://patchwork.freedesktop.org/series/52460/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5134 -> Patchwork_10821 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/52460/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10821 that come from known issues: === IGT changes === Issues hit igt@drv_selftest@live_contexts: fi-icl-u: NOTRUN -> DMESG-FAIL (fdo#108569) igt@pm_rpm@basic-rte: fi-icl-u: NOTRUN -> DMESG-WARN (fdo#108654) Possible fixes igt@drv_module_reload@basic-no-display: fi-byt-clapper: WARN (fdo#108688) -> PASS igt@drv_selftest@live_evict: fi-bsw-kefka: DMESG-WARN (fdo#107709) -> PASS igt@kms_chamelium@common-hpd-after-suspend: fi-skl-6700k2: WARN (fdo#108680) -> PASS igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: DMESG-WARN (fdo#102614) -> PASS igt@kms_pipe_crc_basic@hang-read-crc-pipe-a: fi-byt-clapper: FAIL (fdo#103191, fdo#107362) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-icl-u: INCOMPLETE (fdo#107713) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-cfl-8109u: DMESG-WARN (fdo#107345) -> PASS +1 fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#107345 https://bugs.freedesktop.org/show_bug.cgi?id=107345 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107709 https://bugs.freedesktop.org/show_bug.cgi?id=107709 fdo#107713 https://bugs.freedesktop.org/show_bug.cgi?id=107713 fdo#108569 https://bugs.freedesktop.org/show_bug.cgi?id=108569 fdo#108654 https://bugs.freedesktop.org/show_bug.cgi?id=108654 fdo#108680 https://bugs.freedesktop.org/show_bug.cgi?id=108680 fdo#108688 https://bugs.freedesktop.org/show_bug.cgi?id=108688 == Participating hosts (51 -> 43) == Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-apl-guc fi-ctg-p8600 fi-glk-j4005 == Build changes == * Linux: CI_DRM_5134 -> Patchwork_10821 CI_DRM_5134: 76f4cff023b23764df2956ad64a0840bfebd7ca4 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4714: cab148ca3ec904a94d0cd43476cf7e1f8663f906 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10821: 9ce5b67f7387c3ad147a6240171d840225516ffa @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 9ce5b67f7387 drm/i915: don't apply Display WAs 1125 and 1126 to GLK/CNL+ == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10821/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3,1/3] drm/i915/icl: replace check for combo phy
== Series Details == Series: series starting with [v3,1/3] drm/i915/icl: replace check for combo phy URL : https://patchwork.freedesktop.org/series/52459/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5134 -> Patchwork_10820 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/52459/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10820 that come from known issues: === IGT changes === Issues hit igt@drv_selftest@live_contexts: fi-icl-u: NOTRUN -> INCOMPLETE (fdo#108315) igt@kms_chamelium@dp-edid-read: fi-kbl-7500u: PASS -> FAIL (fdo#102672, fdo#103841) igt@kms_flip@basic-flip-vs-modeset: fi-hsw-4770r: PASS -> DMESG-WARN (fdo#105602) igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: PASS -> FAIL (fdo#103167) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-cfl-8109u: PASS -> DMESG-WARN (fdo#107345) Possible fixes igt@drv_module_reload@basic-no-display: fi-byt-clapper: WARN (fdo#108688) -> PASS igt@drv_selftest@live_evict: fi-bsw-kefka: DMESG-WARN (fdo#107709) -> PASS igt@kms_chamelium@common-hpd-after-suspend: fi-skl-6700k2: WARN (fdo#108680) -> PASS igt@kms_pipe_crc_basic@hang-read-crc-pipe-a: fi-byt-clapper: FAIL (fdo#107362, fdo#103191) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-icl-u: INCOMPLETE (fdo#107713) -> PASS Warnings igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-cfl-8109u: DMESG-WARN (fdo#107345) -> INCOMPLETE (fdo#106070, fdo#108126) fdo#102672 https://bugs.freedesktop.org/show_bug.cgi?id=102672 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841 fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602 fdo#106070 https://bugs.freedesktop.org/show_bug.cgi?id=106070 fdo#107345 https://bugs.freedesktop.org/show_bug.cgi?id=107345 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107709 https://bugs.freedesktop.org/show_bug.cgi?id=107709 fdo#107713 https://bugs.freedesktop.org/show_bug.cgi?id=107713 fdo#108126 https://bugs.freedesktop.org/show_bug.cgi?id=108126 fdo#108315 https://bugs.freedesktop.org/show_bug.cgi?id=108315 fdo#108680 https://bugs.freedesktop.org/show_bug.cgi?id=108680 fdo#108688 https://bugs.freedesktop.org/show_bug.cgi?id=108688 == Participating hosts (51 -> 44) == Missing(7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 == Build changes == * Linux: CI_DRM_5134 -> Patchwork_10820 CI_DRM_5134: 76f4cff023b23764df2956ad64a0840bfebd7ca4 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4714: cab148ca3ec904a94d0cd43476cf7e1f8663f906 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10820: 49663aa28220474a070f8e4ac2d4d1e549513d73 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 49663aa28220 drm/i195: spell out reverse on for_each macros a96e90922991 drm/i915/icl: reverse uninit order f5816a94faad drm/i915/icl: replace check for combo phy == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10820/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 2/8] drm/i915: get ready of memory for pvmmio
On 2018.11.13 16:35:14 +0800, Xiaolin Zhang wrote:
> To enable pvmmio feature, we need to prepare one 4K shared page
> which will be accessed by both guest and backend i915 driver used for
> data exchagne.
>
> the layout of shared_page also defined as well in this patch.
>
> guest i915 will allocate one page memory and then pass this page's physical
> address to backend i915 driver through PVINFO register so that backend i915
> driver can access this shared page without hypeviser trap cost
> for shared data exchagne via hyperviser read_gpa functionality.
>
> v0: RFC
> v1: addressed RFC comment to move both shared_page_lock and shared_page
> to i915_virtual_gpu structure
> v2: packed i915_virtual_gpu structure
> v3: added SHARED_PAGE_SETUP g2v notification for pv shared_page setup
>
> Cc: Zhenyu Wang
> Cc: Zhi Wang
> Cc: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: He Min
> Cc: Jiang Fei
> Cc: Gong Zhipeng
> Cc: Yuan Hang
> Cc: Zhiyuan Lv
> Signed-off-by: Xiaolin Zhang
> ---
> drivers/gpu/drm/i915/i915_drv.c| 2 ++
> drivers/gpu/drm/i915/i915_drv.h| 4 +++-
> drivers/gpu/drm/i915/i915_pvinfo.h | 29 -
> drivers/gpu/drm/i915/i915_vgpu.c | 23 +++
> 4 files changed, 56 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index baac35f..557ab67 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -987,6 +987,8 @@ static void i915_mmio_cleanup(struct drm_i915_private
> *dev_priv)
>
> intel_teardown_mchbar(dev_priv);
> pci_iounmap(pdev, dev_priv->regs);
> + if (intel_vgpu_active(dev_priv) && dev_priv->vgpu.shared_page)
> + free_page((unsigned long)dev_priv->vgpu.shared_page);
> }
>
> /**
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 7b2d7cb..d7a972f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1345,7 +1345,9 @@ struct i915_virtual_gpu {
> bool active;
> u32 caps;
> u32 pv_caps;
> -};
> + spinlock_t shared_page_lock;
> + struct gvt_shared_page *shared_page;
> +} __packed;
>
> /* used in computing the new watermarks state */
> struct intel_wm_config {
> diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h
> b/drivers/gpu/drm/i915/i915_pvinfo.h
> index 78a4b9c..aa5eebc 100644
> --- a/drivers/gpu/drm/i915/i915_pvinfo.h
> +++ b/drivers/gpu/drm/i915/i915_pvinfo.h
> @@ -24,6 +24,8 @@
> #ifndef _I915_PVINFO_H_
> #define _I915_PVINFO_H_
>
> +#include "i915_gem.h"
> +
> /* The MMIO offset of the shared info between guest and host emulator */
> #define VGT_PVINFO_PAGE 0x78000
> #define VGT_PVINFO_SIZE 0x1000
> @@ -46,9 +48,29 @@ enum vgt_g2v_type {
> VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY,
> VGT_G2V_EXECLIST_CONTEXT_CREATE,
> VGT_G2V_EXECLIST_CONTEXT_DESTROY,
> + VGT_G2V_SHARED_PAGE_SETUP,
> VGT_G2V_MAX,
> };
>
> +struct pv_ppgtt_update {
> + u64 pdp;
> + u64 start;
> + u64 length;
> + u32 cache_level;
> +};
> +
> +/*
> + * shared page(4KB) between gvt and VM, could be allocated by guest driver
> + * or a fixed location in PCI bar 0 region
> + */
> +struct gvt_shared_page {
> + u32 reg_addr;
> + u32 elsp_data[I915_NUM_ENGINES * 4];
You can't rely on I915_NUM_ENGINES, which may be changed so that would
cause incompatibility in shared page definition.
> + u32 ring_id;
> + u32 disable_irq;
> + struct pv_ppgtt_update pv_ppgtt;
> +};
> +
> /*
> * VGT capabilities type
> */
> @@ -121,7 +143,12 @@ struct vgt_if {
>
> u32 pvmmio_caps;
>
> - u32 rsv7[0x200 - 25];/* pad to one page */
> + struct {
> + u32 lo;
> + u32 hi;
> + } shared_page_gpa;
> +
> + u32 rsv7[0x200 - 27];/* pad to one page */
> } __packed;
>
> #define vgtif_reg(x) \
> diff --git a/drivers/gpu/drm/i915/i915_vgpu.c
> b/drivers/gpu/drm/i915/i915_vgpu.c
> index 219c7c0..63f70bf 100644
> --- a/drivers/gpu/drm/i915/i915_vgpu.c
> +++ b/drivers/gpu/drm/i915/i915_vgpu.c
> @@ -63,6 +63,7 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
> u64 magic;
> u16 version_major;
> u32 gvt_caps;
> + u64 gpa;
>
> BUILD_BUG_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
>
> @@ -95,6 +96,28 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
> if (!dev_priv->vgpu.pv_caps)
> return;
>
> + dev_priv->vgpu.shared_page = (struct gvt_shared_page *)
> + get_zeroed_page(GFP_KERNEL);
> + if (!dev_priv->vgpu.shared_page) {
> + DRM_ERROR("out of memory for shared page memory\n");
> + return;
> + }
> + gpa = __pa(dev_priv->vgpu.shared_page);
> + __raw_i915_write32(dev_priv, vgtif_reg(shared_page_gpa.lo),
> + lower_32_bits(gpa));
> + __raw_i915_write32(dev_priv,
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Remaining DSC + FEC patches
== Series Details == Series: Remaining DSC + FEC patches URL : https://patchwork.freedesktop.org/series/52461/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/dsc: Modify DRM helper to return complete DSC color depth capabilities Okay! Commit: drm/dsc: Define Display Stream Compression PPS infoframe Okay! Commit: drm/dsc: Define VESA Display Stream Compression Capabilities Okay! Commit: drm/dsc: Define Rate Control values that do not change over configurations Okay! Commit: drm/dsc: Add helpers for DSC picture parameter set infoframes - +drivers/gpu/drm/drm_dsc.c:200:61:expected restricted __be16 +drivers/gpu/drm/drm_dsc.c:200:61:got int +drivers/gpu/drm/drm_dsc.c:200:61: warning: incorrect type in assignment (different base types) +drivers/gpu/drm/drm_dsc.c:207:25:expected unsigned short [unsigned] [usertype] val +drivers/gpu/drm/drm_dsc.c:207:25:got restricted __be16 +drivers/gpu/drm/drm_dsc.c:207:25: warning: cast from restricted __be16 +drivers/gpu/drm/drm_dsc.c:207:25: warning: cast from restricted __be16 +drivers/gpu/drm/drm_dsc.c:207:25: warning: cast from restricted __be16 +drivers/gpu/drm/drm_dsc.c:207:25: warning: incorrect type in argument 1 (different base types) Commit: drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Okay! Commit: drm/i915/dp: Add DSC params and DSC config to intel_crtc_state -drivers/gpu/drm/i915/selftests/../i915_drv.h:3716:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3717:16: warning: expression using sizeof(void) Commit: drm/i915/dp: Compute DSC pipe config in atomic check +drivers/gpu/drm/i915/intel_dp.c:1901:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dp.c:1925:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dp.c:1925:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dp.c:1944:58: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dp.c:1944:58: warning: expression using sizeof(void) Commit: drm/i915/dp: Do not enable PSR2 if DSC is enabled Okay! Commit: drm/i915/dsc: Define & Compute VESA DSC params +drivers/gpu/drm/i915/intel_vdsc.c:351:17: warning: expression using sizeof(void) +./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000 becomes 0) Commit: drm/i915/dsc: Compute Rate Control parameters for DSC Okay! Commit: drm/i915/dp: Enable/Disable DSC in DP Sink Okay! Commit: drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI Okay! Commit: drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling -drivers/gpu/drm/i915/selftests/../i915_drv.h:3717:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3719:16: warning: expression using sizeof(void) Commit: drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Okay! Commit: drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Okay! Commit: drm/i915/dp: Configure Display stream splitter registers during DSC enable Okay! Commit: drm/i915/dp: Disable DSC in source by disabling DSS CTL bits -drivers/gpu/drm/i915/selftests/../i915_drv.h:3719:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3720:16: warning: expression using sizeof(void) Commit: drm/i915/dsc: Enable and disable appropriate power wells for VDSC Okay! Commit: drm/i915/dsc: Add Per connector debugfs node for DSC support/enable Okay! Commit: i915/dp/fec: Add fec_enable to the crtc state. Okay! Commit: drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION Okay! Commit: i915/dp/fec: Configure the Forward Error Correction bits. Okay! Commit: drm/i915/fec: Disable FEC state. Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Remaining DSC + FEC patches
== Series Details ==
Series: Remaining DSC + FEC patches
URL : https://patchwork.freedesktop.org/series/52461/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b72e39779b9c drm/dsc: Modify DRM helper to return complete DSC color depth
capabilities
d5bda8fc9dfd drm/dsc: Define Display Stream Compression PPS infoframe
-:31: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#31:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 342 lines checked
bccacb6d076d drm/dsc: Define VESA Display Stream Compression Capabilities
-:34: WARNING:BAD_SIGN_OFF: Non-standard signature: Co-developed-by:
#34:
Co-developed-by: Gaurav K Singh
-:73: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible
alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#73: FILE: include/drm/drm_dsc.h:40:
+ bool convert_rgb;
-:83: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible
alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#83: FILE: include/drm/drm_dsc.h:50:
+ bool enable422;
-:108: CHECK:BOOL_MEMBER: Avoid using bool structure members because of
possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#108: FILE: include/drm/drm_dsc.h:75:
+ bool block_pred_enable;
-:136: CHECK:BOOL_MEMBER: Avoid using bool structure members because of
possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#136: FILE: include/drm/drm_dsc.h:103:
+ bool vbr_enable;
-:151: CHECK:BOOL_MEMBER: Avoid using bool structure members because of
possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#151: FILE: include/drm/drm_dsc.h:118:
+ bool native_422;
-:153: CHECK:BOOL_MEMBER: Avoid using bool structure members because of
possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#153: FILE: include/drm/drm_dsc.h:120:
+ bool native_420;
total: 0 errors, 1 warnings, 6 checks, 121 lines checked
8b49256df332 drm/dsc: Define Rate Control values that do not change over
configurations
-:42: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch
author 'Srivatsa, Anusha '
total: 0 errors, 1 warnings, 0 checks, 12 lines checked
7672bdc04d1d drm/dsc: Add helpers for DSC picture parameter set infoframes
-:79: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#79:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 285 lines checked
7b3dae68ebbf drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants
96ce38e6a2ff drm/i915/dp: Add DSC params and DSC config to intel_crtc_state
-:49: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible
alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#49: FILE: drivers/gpu/drm/i915/intel_drv.h:942:
+ bool compression_enable;
-:50: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible
alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#50: FILE: drivers/gpu/drm/i915/intel_drv.h:943:
+ bool dsc_split;
total: 0 errors, 0 warnings, 2 checks, 22 lines checked
2c83276c3c4c drm/i915/dp: Compute DSC pipe config in atomic check
-:309: WARNING:TABSTOP: Statements should start on a tabstop
#309: FILE: drivers/gpu/drm/i915/intel_dp.c:2032:
+else
total: 0 errors, 1 warnings, 0 checks, 310 lines checked
969277b592d1 drm/i915/dp: Do not enable PSR2 if DSC is enabled
63f59e9e7a3b drm/i915/dsc: Define & Compute VESA DSC params
-:68: WARNING:BAD_SIGN_OFF: Non-standard signature: Co-developed-by:
#68:
Co-developed-by: Manasi Navare
-:95: WARNING:MISSING_SPACE: break quoted strings at a space character
#95: FILE: drivers/gpu/drm/i915/intel_dp.c:1964:
+ DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input
Bpp = %d"
+ "Compressed BPP = %d\n",
-:119: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#119:
new file mode 100644
-:405: CHECK:LINE_SPACING: Please use a blank line after
function/struct/union/enum declarations
#405: FILE: drivers/gpu/drm/i915/intel_vdsc.c:282:
+}
+};
total: 0 errors, 3 warnings, 1 checks, 496 lines checked
44af64fc1f3c drm/i915/dsc: Compute Rate Control parameters for DSC
-:141: CHECK:SPACING: space preferred before that '*' (ctx:VxE)
#141: FILE: drivers/gpu/drm/i915/intel_vdsc.c:411:
+ vdsc_cfg->slice_bpg_offset)*
^
-:173: CHECK:LINE_SPACING: Please don't use multiple blank lines
#173: FILE: drivers/gpu/drm/i915/intel_vdsc.c:443:
+
+
total: 0 errors, 0 warnings, 2 checks, 136 lines checked
7411ddd14780 drm/i915/dp: Enable/Disable DSC in DP Sink
bb92419095f2 drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI
a7a9b4502148 drm/i915/dp: Configure i915 Picture parameter Set registers during
DSC enabling
-:45:
[Intel-gfx] [PATCH v9 22/24] drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION
From: Anusha Srivatsa
If the panel supports FEC, the driver has to
set the FEC_READY bit in the dpcd register:
FEC_CONFIGURATION.
This has to happen before link training.
v2: s/intel_dp_set_fec_ready/intel_dp_sink_set_fec_ready
- change commit message. (Gaurav)
v3: rebased. (r-b Manasi)
v4: Use fec crtc state, before setting FEC_READY
bit. (Anusha)
v5: Move to intel_ddi.c
- Make the function static (Anusha)
v6: Dont pass state as a separate argument (Ville)
Cc: dri-de...@lists.freedesktop.org
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
Reviewed-by: Manasi Navare
---
drivers/gpu/drm/i915/intel_ddi.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 0638fd2febfb..2d15520f13c5 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3102,6 +3102,16 @@ static void icl_program_mg_dp_mode(struct
intel_digital_port *intel_dig_port)
I915_WRITE(MG_DP_MODE(port, 1), ln1);
}
+static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
+ const struct intel_crtc_state
*crtc_state)
+{
+ if (!crtc_state->fec_enable)
+ return;
+
+ if (drm_dp_dpcd_writeb(_dp->aux, DP_FEC_CONFIGURATION,
DP_FEC_READY) <= 0)
+ DRM_DEBUG_KMS("Failed to get FEC enabled in sink\n");
+}
+
static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state
*conn_state)
@@ -3142,6 +3152,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder
*encoder,
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
true);
+ intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
intel_dp_start_link_train(intel_dp);
if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
intel_dp_stop_link_train(intel_dp);
--
2.19.1
___
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[Intel-gfx] [PATCH v9 13/24] drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI
On Icelake, a separate power well PG2 is created for
VDSC engine used for eDP/MIPI DSI. This patch adds a new
display power domain for Power well 2.
v3:
* Call it POWER_DOMAIN_TRANSCODER_EDP_VDSC (Ville)
* Move it around TRANSCODER power domain defs (Ville)
v2:
* Fix the power well mismatch CI error (Ville)
* Rename as VDSC_PIPE_A (Imre)
* Fix a whitespace (Anusha)
* Fix Comments (Imre)
Cc: Ville Syrjala
Cc: Rodrigo Vivi
Cc: Imre Deak
Signed-off-by: Manasi Navare
Reviewed-by: Ville Syrjala
---
drivers/gpu/drm/i915/intel_display.h| 1 +
drivers/gpu/drm/i915/intel_runtime_pm.c | 4 +++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.h
b/drivers/gpu/drm/i915/intel_display.h
index b0b23e1e9392..4e6b824ccc8c 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -226,6 +226,7 @@ enum intel_display_power_domain {
POWER_DOMAIN_TRANSCODER_B,
POWER_DOMAIN_TRANSCODER_C,
POWER_DOMAIN_TRANSCODER_EDP,
+ POWER_DOMAIN_TRANSCODER_EDP_VDSC,
POWER_DOMAIN_TRANSCODER_DSI_A,
POWER_DOMAIN_TRANSCODER_DSI_C,
POWER_DOMAIN_PORT_DDI_A_LANES,
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index f945db6ea420..0d8b57382961 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -76,6 +76,8 @@ intel_display_power_domain_str(enum
intel_display_power_domain domain)
return "TRANSCODER_C";
case POWER_DOMAIN_TRANSCODER_EDP:
return "TRANSCODER_EDP";
+ case POWER_DOMAIN_TRANSCODER_EDP_VDSC:
+ return "TRANSCODER_EDP_VDSC";
case POWER_DOMAIN_TRANSCODER_DSI_A:
return "TRANSCODER_DSI_A";
case POWER_DOMAIN_TRANSCODER_DSI_C:
@@ -2014,9 +2016,9 @@ void intel_display_power_put(struct drm_i915_private
*dev_priv,
*/
#define ICL_PW_2_POWER_DOMAINS ( \
ICL_PW_3_POWER_DOMAINS |\
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) | \
BIT_ULL(POWER_DOMAIN_INIT))
/*
-* - eDP/DSI VDSC
* - KVMR (HW control)
*/
#define ICL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
--
2.19.1
___
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[Intel-gfx] [PATCH v9 21/24] i915/dp/fec: Add fec_enable to the crtc state.
From: Anusha Srivatsa
For DP 1.4 and above, Display Stream compression can be
enabled only if Forward Error Correctin can be performed.
Add a crtc state for FEC. Currently, the state
is determined by platform, DP and DSC being
enabled. Moving forward we can use the state
to have error correction on other scenarios too
if needed.
v2:
- Control compression_enable with the fec_enable
parameter in crtc state and with intel_dp_supports_fec()
(Ville)
- intel_dp_can_fec()/intel_dp_supports_fec()(manasi)
v3: Check for FEC support along with setting crtc state.
v4: add checks to intel_dp_source_supports_dsc.(manasi)
- Move intel_dp_supports_fec() closer to
intel_dp_supports_dsc() (Anusha)
v5: Move fec check to intel_dp_supports_dsc(Ville)
v6: Remove warning. rebase.
v7: change crtc state to include DP sink and fec capability
of source.(Manasi)
v8: Set fec_enable in crtc in intel_dp_compute_config().
v9 (From Manasi):
* Combine the !edp and !fec_support check
* Derive dev_priv from intel_dp directly
Suggested-by: Ville Syrjala
Cc: dri-de...@lists.freedesktop.org
Cc: Ville Syrjala
Cc: Jani Nikula
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_dp.c | 27 ++-
drivers/gpu/drm/i915/intel_drv.h | 3 +++
2 files changed, 25 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 99e0dd0e32d6..45e666d7ce6c 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -545,7 +545,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
dsc_slice_count =
drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
true);
- } else {
+ } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
dsc_max_output_bpp =
intel_dp_dsc_get_output_bpp(max_link_clock,
max_lanes,
@@ -1710,14 +1710,25 @@ struct link_config_limits {
int min_bpp, max_bpp;
};
-static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
+static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
const struct intel_crtc_state
*pipe_config)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- /* FIXME: FEC needed for external DP until then reject DSC on DP */
- if (!intel_dp_is_edp(intel_dp))
- return false;
+ return INTEL_GEN(dev_priv) >= 11 && pipe_config->cpu_transcoder !=
TRANSCODER_A;
+}
+
+static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *pipe_config)
+{
+ return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
+ drm_dp_sink_supports_fec(intel_dp->fec_capable);
+}
+
+static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
+const struct intel_crtc_state
*pipe_config)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
return INTEL_GEN(dev_priv) >= 10 &&
pipe_config->cpu_transcoder != TRANSCODER_A;
@@ -1726,6 +1737,9 @@ static bool intel_dp_source_supports_dsc(struct intel_dp
*intel_dp,
static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
const struct intel_crtc_state *pipe_config)
{
+ if (!intel_dp_is_edp(intel_dp) && !pipe_config->fec_enable)
+ return false;
+
if (!intel_dp_source_supports_dsc(intel_dp, pipe_config) ||
!drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd))
return false;
@@ -2135,6 +2149,9 @@ intel_dp_compute_config(struct intel_encoder *encoder,
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
return false;
+ pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
+ intel_dp_supports_fec(intel_dp, pipe_config);
+
DRM_DEBUG_KMS("Force DSC en = %d\n", intel_dp->force_dsc_en);
if (!intel_dp_compute_link_config(encoder, pipe_config, conn_state))
return false;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 9eeb08142327..b9be60f04abf 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -945,6 +945,9 @@ struct intel_crtc_state {
u8 slice_count;
} dsc_params;
struct drm_dsc_config dp_dsc_cfg;
+
+ /* Forward Error correction State */
+ bool fec_enable;
};
struct intel_crtc {
--
2.19.1
___
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[Intel-gfx] [PATCH v9 05/24] drm/dsc: Add helpers for DSC picture parameter set infoframes
According to Display Stream compression spec 1.2, the picture
parameter set metadata is sent from source to sink device
using the DP Secondary data packet. An infoframe is formed
for the PPS SDP header and PPS SDP payload bytes.
This patch adds helpers to fill the PPS SDP header
and PPS SDP payload according to the DSC 1.2 specification.
v7:
* Use BUILD_BUG_ON() to protect changing struct size (Ville)
* Remove typecaseting (Ville)
* Include byteorder.h in drm_dsc.c (Ville)
* Correct kernel doc spacing (Anusha)
v6:
* Use proper sequence points for breaking down the
assignments (Chris Wilson)
* Use SPDX identifier
v5:
Do not use bitfields for DRM structs (Jani N)
v4:
* Use DSC constants for params that dont change across
configurations
v3:
* Add reference to added kernel-docs in
Documentation/gpu/drm-kms-helpers.rst (Daniel Vetter)
v2:
* Add EXPORT_SYMBOL for the drm functions (Manasi)
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Harry Wentland
Signed-off-by: Manasi Navare
Acked-by: Harry Wentland
---
Documentation/gpu/drm-kms-helpers.rst | 12 ++
drivers/gpu/drm/Makefile | 2 +-
drivers/gpu/drm/drm_dsc.c | 228 ++
include/drm/drm_dsc.h | 21 +++
4 files changed, 262 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/drm_dsc.c
diff --git a/Documentation/gpu/drm-kms-helpers.rst
b/Documentation/gpu/drm-kms-helpers.rst
index 4b4dc236ef6f..b422eb8edf16 100644
--- a/Documentation/gpu/drm-kms-helpers.rst
+++ b/Documentation/gpu/drm-kms-helpers.rst
@@ -232,6 +232,18 @@ MIPI DSI Helper Functions Reference
.. kernel-doc:: drivers/gpu/drm/drm_mipi_dsi.c
:export:
+Display Stream Compression Helper Functions Reference
+=
+
+.. kernel-doc:: drivers/gpu/drm/drm_dsc.c
+ :doc: dsc helpers
+
+.. kernel-doc:: include/drm/drm_dsc.h
+ :internal:
+
+.. kernel-doc:: drivers/gpu/drm/drm_dsc.c
+ :export:
+
Output Probing Helper Functions Reference
=
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 576ba985e138..3a3e6fb6d476 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -32,7 +32,7 @@ drm-$(CONFIG_AGP) += drm_agpsupport.o
drm-$(CONFIG_DEBUG_FS) += drm_debugfs.o drm_debugfs_crc.o
drm-$(CONFIG_DRM_LOAD_EDID_FIRMWARE) += drm_edid_load.o
-drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_probe_helper.o \
+drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_dsc.o
drm_probe_helper.o \
drm_plane_helper.o drm_dp_mst_topology.o drm_atomic_helper.o \
drm_kms_helper_common.o drm_dp_dual_mode_helper.o \
drm_simple_kms_helper.o drm_modeset_helper.o \
diff --git a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c
new file mode 100644
index ..bc2b23adb072
--- /dev/null
+++ b/drivers/gpu/drm/drm_dsc.c
@@ -0,0 +1,228 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2018 Intel Corp
+ *
+ * Author:
+ * Manasi Navare
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ * DOC: dsc helpers
+ *
+ * These functions contain some common logic and helpers to deal with VESA
+ * Display Stream Compression standard required for DSC on Display Port/eDP or
+ * MIPI display interfaces.
+ */
+
+/**
+ * drm_dsc_dp_pps_header_init() - Initializes the PPS Header
+ * for DisplayPort as per the DP 1.4 spec.
+ * @pps_sdp: Secondary data packet for DSC Picture Parameter Set
+ */
+void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp)
+{
+ memset(_sdp->pps_header, 0, sizeof(pps_sdp->pps_header));
+
+ pps_sdp->pps_header.HB1 = DP_SDP_PPS;
+ pps_sdp->pps_header.HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1;
+}
+EXPORT_SYMBOL(drm_dsc_dp_pps_header_init);
+
+/**
+ * drm_dsc_pps_infoframe_pack() - Populates the DSC PPS infoframe
+ * using the DSC configuration parameters in the order expected
+ * by the DSC Display Sink device. For the DSC, the sink device
+ * expects the PPS payload in the big endian format for the fields
+ * that span more than 1 byte.
+ *
+ * @pps_sdp:
+ * Secondary data packet for DSC Picture Parameter Set
+ * @dsc_cfg:
+ * DSC Configuration data filled by driver
+ */
+void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
+ const struct drm_dsc_config *dsc_cfg)
+{
+ int i;
+
+ /* Protect against someone accidently changing struct size */
+ BUILD_BUG_ON(sizeof(pps_sdp->pps_payload) !=
+DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 + 1);
+
+ memset(_sdp->pps_payload, 0, sizeof(pps_sdp->pps_payload));
+
+ /* PPS 0 */
+ pps_sdp->pps_payload.dsc_version =
+ dsc_cfg->dsc_version_minor |
+ dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT;
+
+ /* PPS 1, 2 is 0 */
+
+
[Intel-gfx] [PATCH v9 23/24] i915/dp/fec: Configure the Forward Error Correction bits.
From: Anusha Srivatsa
If FEC is supported, the corresponding
DP_TP_CTL register bits have to be configured.
The driver has to program the FEC_ENABLE in DP_TP_CTL[30] register
and wait till FEC_STATUS in DP_TP_CTL[28] is 1.
Also add the warn message to make sure that the control
register is already active while enabling FEC.
v2:
- Change commit message. Configure fec state after
link training (Manasi, Gaurav)
- Remove redundent checks (Manasi)
- Remove the registers that get added automagically (Anusha)
v3: s/intel_dp_set_fec_state()/intel_dp_enable_fec_state() (Gaurav)
v4: rebased.
v5:
- Move the code to the proper spot, according to spec.(Ville)
- Use fec state as a check too.
v6: Pass intel_encoder, instead of intel_dp. (Ville)
v7: Remove unwanted comments (Manasi)
Cc: dri-de...@lists.freedesktop.org
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_ddi.c | 23 +++
2 files changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 21e82c03cf80..5713754ace99 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9198,6 +9198,7 @@ enum skl_power_gate {
#define _DP_TP_CTL_B 0x64140
#define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
#define DP_TP_CTL_ENABLE (1 << 31)
+#define DP_TP_CTL_FEC_ENABLE (1 << 30)
#define DP_TP_CTL_MODE_SST(0 << 27)
#define DP_TP_CTL_MODE_MST(1 << 27)
#define DP_TP_CTL_FORCE_ACT (1 << 25)
@@ -9216,6 +9217,7 @@ enum skl_power_gate {
#define _DP_TP_STATUS_A0x64044
#define _DP_TP_STATUS_B0x64144
#define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
+#define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28)
#define DP_TP_STATUS_IDLE_DONE(1 << 25)
#define DP_TP_STATUS_ACT_SENT (1 << 24)
#define DP_TP_STATUS_MODE_STATUS_MST (1 << 23)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 2d15520f13c5..fb9f8c22cefb 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3112,6 +3112,27 @@ static void intel_dp_sink_set_fec_ready(struct intel_dp
*intel_dp,
DRM_DEBUG_KMS("Failed to get FEC enabled in sink\n");
}
+static void intel_ddi_enable_fec(struct intel_encoder *encoder,
+const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum port port = encoder->port;
+ u32 val;
+
+ if (!crtc_state->fec_enable)
+ return;
+
+ val = I915_READ(DP_TP_CTL(port));
+ val |= DP_TP_CTL_FEC_ENABLE;
+ I915_WRITE(DP_TP_CTL(port), val);
+
+ if (intel_wait_for_register(dev_priv, DP_TP_STATUS(port),
+ DP_TP_STATUS_FEC_ENABLE_LIVE,
+ DP_TP_STATUS_FEC_ENABLE_LIVE,
+ 1))
+ DRM_ERROR("Timed out waiting for FEC Enable Status\n");
+}
+
static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state
*conn_state)
@@ -3157,6 +3178,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder
*encoder,
if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
intel_dp_stop_link_train(intel_dp);
+ intel_ddi_enable_fec(encoder, crtc_state);
+
icl_enable_phy_clock_gating(dig_port);
if (!is_mst)
--
2.19.1
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[Intel-gfx] [PATCH v9 20/24] drm/i915/dsc: Add Per connector debugfs node for DSC support/enable
DSC can be supported per DP connector. This patch adds a per connector
debugfs node to expose DSC support capability by the kernel.
The same node can be used from userspace to force DSC enable.
force_dsc_en written through this debugfs node is used to force
DSC even for lower resolutions.
v4:
* Add missed connector_status check (Manasi)
* Create i915_dsc_support node only for Gen >=10 (manasi)
* Access intel_dp->dsc_dpcd only if its not NULL (Manasi)
v3:
* Combine Force_dsc_en with this patch (Ville)
v2:
* Use kstrtobool_from_user to avoid explicit error checking (Lyude)
* Rebase on drm-tip (Manasi)
Cc: Rodrigo Vivi
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Lyude Paul
Signed-off-by: Manasi Navare
Reviewed-by: Lyude Paul
---
drivers/gpu/drm/i915/i915_debugfs.c | 77 +
drivers/gpu/drm/i915/intel_dp.c | 3 +-
drivers/gpu/drm/i915/intel_drv.h| 3 ++
3 files changed, 82 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 670db5073d70..3c112bb225d6 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -5074,6 +5074,76 @@ static int i915_hdcp_sink_capability_show(struct
seq_file *m, void *data)
}
DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability);
+static int i915_dsc_support_show(struct seq_file *m, void *data)
+{
+ struct drm_connector *connector = m->private;
+ struct intel_encoder *encoder = intel_attached_encoder(connector);
+ struct intel_dp *intel_dp =
+ enc_to_intel_dp(>base);
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *crtc_state;
+
+ if (connector->status != connector_status_connected)
+ return -ENODEV;
+
+ crtc = to_intel_crtc(encoder->base.crtc);
+ crtc_state = to_intel_crtc_state(crtc->base.state);
+ drm_modeset_lock(>base.mutex, NULL);
+ seq_printf(m, "Enabled: %s\n",
+ yesno(crtc_state->dsc_params.compression_enable));
+ if (intel_dp->dsc_dpcd)
+ seq_printf(m, "Supported: %s\n",
+ yesno(drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)));
+ drm_modeset_unlock(>base.mutex);
+
+ return 0;
+}
+
+static ssize_t i915_dsc_support_write(struct file *file,
+ const char __user *ubuf,
+ size_t len, loff_t *offp)
+{
+ bool dsc_enable = false;
+ int ret;
+ struct drm_connector *connector =
+ ((struct seq_file *)file->private_data)->private;
+ struct intel_encoder *encoder = intel_attached_encoder(connector);
+ struct intel_dp *intel_dp = enc_to_intel_dp(>base);
+
+ if (len == 0)
+ return 0;
+
+ DRM_DEBUG_DRIVER("Copied %d bytes from user to force DSC\n",
+(unsigned int)len);
+
+ ret = kstrtobool_from_user(ubuf, len, _enable);
+ if (ret < 0)
+ return ret;
+
+ DRM_DEBUG_DRIVER("Got %s for DSC Enable\n",
+(dsc_enable) ? "true" : "false");
+ intel_dp->force_dsc_en = dsc_enable;
+
+ *offp += len;
+ return len;
+}
+
+static int i915_dsc_support_open(struct inode *inode,
+struct file *file)
+{
+ return single_open(file, i915_dsc_support_show,
+ inode->i_private);
+}
+
+static const struct file_operations i915_dsc_support_fops = {
+ .owner = THIS_MODULE,
+ .open = i915_dsc_support_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+ .write = i915_dsc_support_write
+};
+
/**
* i915_debugfs_connector_add - add i915 specific connector debugfs files
* @connector: pointer to a registered drm_connector
@@ -5086,6 +5156,7 @@ DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability);
int i915_debugfs_connector_add(struct drm_connector *connector)
{
struct dentry *root = connector->debugfs_entry;
+ struct drm_i915_private *dev_priv = to_i915(connector->dev);
/* The connector must have been registered beforehands. */
if (!root)
@@ -5110,5 +5181,11 @@ int i915_debugfs_connector_add(struct drm_connector
*connector)
connector, _hdcp_sink_capability_fops);
}
+ if (INTEL_GEN(dev_priv) >= 10 &&
+ (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
+connector->connector_type == DRM_MODE_CONNECTOR_eDP))
+ debugfs_create_file("i915_dsc_support", S_IRUGO, root,
+ connector, _dsc_support_fops);
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b43a77bf42df..99e0dd0e32d6 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2042,7 +2042,7 @@ intel_dp_compute_link_config(struct intel_encoder
*encoder,
[Intel-gfx] [PATCH v9 24/24] drm/i915/fec: Disable FEC state.
From: Anusha Srivatsa
Set the suitable bits in DP_TP_CTL to stop
bit correction when DSC is disabled.
v2:
- rebased.
- Add additional check for compression state. (Gaurav)
v3: rebased.
v4:
- Move the code to the proper spot according to spec (Ville)
- Use proper checks (manasi)
v5: Remove unnecessary checks (Ville)
v6: Resolve warnings. Add crtc_state as an argument to
intel_disable_ddi_buf(). (Manasi)
Cc: dri-de...@lists.freedesktop.org
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
Reviewed-by: Manasi Navare
---
drivers/gpu/drm/i915/intel_ddi.c | 28
1 file changed, 24 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index fb9f8c22cefb..8ded2ebc5efd 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3133,6 +3133,22 @@ static void intel_ddi_enable_fec(struct intel_encoder
*encoder,
DRM_ERROR("Timed out waiting for FEC Enable Status\n");
}
+static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
+ const struct intel_crtc_state
*crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum port port = encoder->port;
+ u32 val;
+
+ if (!crtc_state->fec_enable)
+ return;
+
+ val = I915_READ(DP_TP_CTL(port));
+ val &= ~DP_TP_CTL_FEC_ENABLE;
+ I915_WRITE(DP_TP_CTL(port), val);
+ POSTING_READ(DP_TP_CTL(port));
+}
+
static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state
*conn_state)
@@ -3276,7 +3292,8 @@ static void intel_ddi_pre_enable(struct intel_encoder
*encoder,
}
}
-static void intel_disable_ddi_buf(struct intel_encoder *encoder)
+static void intel_disable_ddi_buf(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum port port = encoder->port;
@@ -3295,6 +3312,9 @@ static void intel_disable_ddi_buf(struct intel_encoder
*encoder)
val |= DP_TP_CTL_LINK_TRAIN_PAT1;
I915_WRITE(DP_TP_CTL(port), val);
+ /* Disable FEC in DP Sink */
+ intel_ddi_disable_fec_state(encoder, crtc_state);
+
if (wait)
intel_wait_ddi_buf_idle(dev_priv, port);
}
@@ -3318,7 +3338,7 @@ static void intel_ddi_post_disable_dp(struct
intel_encoder *encoder,
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
}
- intel_disable_ddi_buf(encoder);
+ intel_disable_ddi_buf(encoder, old_crtc_state);
intel_edp_panel_vdd_on(intel_dp);
intel_edp_panel_off(intel_dp);
@@ -3341,7 +3361,7 @@ static void intel_ddi_post_disable_hdmi(struct
intel_encoder *encoder,
intel_ddi_disable_pipe_clock(old_crtc_state);
- intel_disable_ddi_buf(encoder);
+ intel_disable_ddi_buf(encoder, old_crtc_state);
intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
@@ -3392,7 +3412,7 @@ void intel_ddi_fdi_post_disable(struct intel_encoder
*encoder,
val &= ~FDI_RX_ENABLE;
I915_WRITE(FDI_RX_CTL(PIPE_A), val);
- intel_disable_ddi_buf(encoder);
+ intel_disable_ddi_buf(encoder, old_crtc_state);
intel_ddi_clk_disable(encoder);
val = I915_READ(FDI_RX_MISC(PIPE_A));
--
2.19.1
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[Intel-gfx] [PATCH v9 14/24] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling
After encoder->pre_enable() hook, after link training sequence is
completed, PPS registers for DSC encoder are configured using the
DSC state parameters in intel_crtc_state as part of DSC enabling
routine in the source. DSC enabling routine is called after
encoder->pre_enable() before enbaling the pipe and after
compression is enabled on the sink.
v6:
intel_dsc_enable to be part of pre_enable hook (Ville)
v5:
* make crtc_state const (Ville)
v4:
* Use cpu_transcoder instead of encoder->type for using EDP transcoder
DSC registers(Ville)
* Keep all PSS regs together (Anusha)
v3:
* Configure Pic_width/2 for each VDSC engine when two VDSC engines per pipe
are used (Manasi)
* Add DSC slice_row_per_frame in PPS16 (Manasi)
v2:
* Enable PG2 power well for VDSC on eDP
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/intel_ddi.c | 6 +
drivers/gpu/drm/i915/intel_display.c | 1 +
drivers/gpu/drm/i915/intel_vdsc.c| 419 +++
4 files changed, 428 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8fbf45cd3eb8..dbabe54b0ae2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3490,6 +3490,8 @@ extern void intel_rps_mark_interactive(struct
drm_i915_private *i915,
bool interactive);
extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
bool enable);
+extern void intel_dsc_enable(struct intel_encoder *encoder,
+const struct intel_crtc_state *crtc_state);
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index c7d417e6262f..f6279e54f15b 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3144,6 +3144,12 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder
*encoder,
if (!is_mst)
intel_ddi_enable_pipe_clock(crtc_state);
+
+ /*
+* Enable and Configure Display Stream Compression in the source
+* if enabled in intel_crtc_state.
+*/
+ intel_dsc_enable(encoder, crtc_state);
}
static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 390c4b3970db..210da9e9d31e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5458,6 +5458,7 @@ static void intel_encoders_pre_enable(struct drm_crtc
*crtc,
if (encoder->pre_enable)
encoder->pre_enable(encoder, crtc_state, conn_state);
+
}
}
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index b644f69f1c93..94f346b97c10 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -577,3 +577,422 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
return intel_compute_rc_parameters(vdsc_cfg);
}
+
+static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
+ const struct intel_crtc_state
*crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ const struct drm_dsc_config *vdsc_cfg = _state->dp_dsc_cfg;
+ enum pipe pipe = crtc->pipe;
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ u32 pps_val = 0;
+ u32 rc_buf_thresh_dword[4];
+ u32 rc_range_params_dword[8];
+ u8 num_vdsc_instances = (crtc_state->dsc_params.dsc_split) ? 2 : 1;
+ int i = 0;
+
+ /* Populate PICTURE_PARAMETER_SET_0 registers */
+ pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<
+ DSC_VER_MIN_SHIFT |
+ vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
+ vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
+ if (vdsc_cfg->block_pred_enable)
+ pps_val |= DSC_BLOCK_PREDICTION;
+ else
+ pps_val &= ~DSC_BLOCK_PREDICTION;
+ if (vdsc_cfg->convert_rgb)
+ pps_val |= DSC_COLOR_SPACE_CONVERSION;
+ else
+ pps_val &= ~DSC_COLOR_SPACE_CONVERSION;
+ if (vdsc_cfg->enable422)
+ pps_val |= DSC_422_ENABLE;
+ else
+ pps_val &= ~DSC_422_ENABLE;
+ if (vdsc_cfg->vbr_enable)
+ pps_val |= DSC_VBR_ENABLE;
+ else
+ pps_val &= ~DSC_VBR_ENABLE;
+
+ DRM_INFO("PPS0 = 0x%08x\n", pps_val);
+ if (cpu_transcoder == TRANSCODER_EDP) {
+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_0, pps_val);
+
[Intel-gfx] [PATCH v9 06/24] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants
DSC specification defines linebuf_depth which contains the
line buffer bit depth used to generate the bitstream.
These values are defined as per Table 4.1 in DSC 1.2 spec
v2 (From Manasi):
* Rename as MAX_LINEBUF_DEPTH for DSC 1.1 and DSC 1.2
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjälä
Signed-off-by: Gaurav K Singh
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
include/drm/drm_dsc.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index 52e57ceaff80..d03f1b83421a 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -40,6 +40,9 @@
#define DSC_PPS_RC_RANGE_MINQP_SHIFT 11
#define DSC_PPS_RC_RANGE_MAXQP_SHIFT 6
#define DSC_PPS_NATIVE_420_SHIFT 1
+#define DSC_1_2_MAX_LINEBUF_DEPTH_BITS 16
+#define DSC_1_2_MAX_LINEBUF_DEPTH_VAL 0
+#define DSC_1_1_MAX_LINEBUF_DEPTH_BITS 13
/* Configuration for a single Rate Control model range */
struct drm_dsc_rc_range_parameters {
--
2.19.1
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[Intel-gfx] [PATCH v9 00/24] Remaining DSC + FEC patches
This patch series addresses review comments from DSC patch set: https://patchwork.freedesktop.org/series/51986/ and FEc patch set: https://patchwork.freedesktop.org/series/47848/ Anusha Srivatsa (4): i915/dp/fec: Add fec_enable to the crtc state. drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION i915/dp/fec: Configure the Forward Error Correction bits. drm/i915/fec: Disable FEC state. Gaurav K Singh (3): drm/i915/dsc: Define & Compute VESA DSC params drm/i915/dsc: Compute Rate Control parameters for DSC drm/i915/dp: Enable/Disable DSC in DP Sink Manasi Navare (16): drm/dsc: Modify DRM helper to return complete DSC color depth capabilities drm/dsc: Define Display Stream Compression PPS infoframe drm/dsc: Define VESA Display Stream Compression Capabilities drm/dsc: Add helpers for DSC picture parameter set infoframes drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants drm/i915/dp: Add DSC params and DSC config to intel_crtc_state drm/i915/dp: Compute DSC pipe config in atomic check drm/i915/dp: Do not enable PSR2 if DSC is enabled drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes drm/i915/dp: Configure Display stream splitter registers during DSC enable drm/i915/dp: Disable DSC in source by disabling DSS CTL bits drm/i915/dsc: Enable and disable appropriate power wells for VDSC drm/i915/dsc: Add Per connector debugfs node for DSC support/enable Srivatsa, Anusha (1): drm/dsc: Define Rate Control values that do not change over configurations Documentation/gpu/drm-kms-helpers.rst | 12 + drivers/gpu/drm/Makefile|2 +- drivers/gpu/drm/drm_dp_helper.c | 29 +- drivers/gpu/drm/drm_dsc.c | 228 + drivers/gpu/drm/i915/Makefile |3 +- drivers/gpu/drm/i915/i915_debugfs.c | 77 ++ drivers/gpu/drm/i915/i915_drv.h |4 + drivers/gpu/drm/i915/i915_reg.h |3 + drivers/gpu/drm/i915/intel_ddi.c| 79 +- drivers/gpu/drm/i915/intel_display.c| 23 +- drivers/gpu/drm/i915/intel_display.h|4 +- drivers/gpu/drm/i915/intel_dp.c | 230 - drivers/gpu/drm/i915/intel_dp_mst.c |2 +- drivers/gpu/drm/i915/intel_drv.h| 24 + drivers/gpu/drm/i915/intel_hdmi.c | 21 +- drivers/gpu/drm/i915/intel_psr.c| 14 + drivers/gpu/drm/i915/intel_runtime_pm.c |4 +- drivers/gpu/drm/i915/intel_vdsc.c | 1097 +++ include/drm/drm_dp_helper.h | 12 +- include/drm/drm_dsc.h | 485 ++ 20 files changed, 2301 insertions(+), 52 deletions(-) create mode 100644 drivers/gpu/drm/drm_dsc.c create mode 100644 drivers/gpu/drm/i915/intel_vdsc.c create mode 100644 include/drm/drm_dsc.h -- 2.19.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v9 19/24] drm/i915/dsc: Enable and disable appropriate power wells for VDSC
A separate power well 2 (PG2) is required for VDSC on eDP transcoder
whereas all other transcoders use the power wells associated with the
transcoders for VDSC.
This patch adds a helper to obtain correct power domain depending on
transcoder being used and enables/disables the power wells during
VDSC enabling/disabling.
v4:
* Get VDSC power domain only if compression en is set
in crtc_state (Ville, Imre)
v3:
* Call it intel_dsc_power_domain, add to
intel_ddi_get_power_domains (Ville)
v2:
* Fix tabs, const crtc_state, fix comments (Ville)
Suggested-by: Ville Syrjala
Cc: Ville Syrjala
Cc: Imre Deak
Cc: Rodrigo Vivi
Signed-off-by: Manasi Navare
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_ddi.c | 6 ++
drivers/gpu/drm/i915/intel_drv.h | 2 ++
drivers/gpu/drm/i915/intel_vdsc.c | 25 +
3 files changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index f6279e54f15b..0638fd2febfb 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2154,6 +2154,12 @@ static u64 intel_ddi_get_power_domains(struct
intel_encoder *encoder,
intel_port_is_tc(dev_priv, encoder->port))
domains |= BIT_ULL(intel_ddi_main_link_aux_domain(dig_port));
+ /*
+* VDSC power is needed when DSC is enabled
+*/
+ if (crtc_state->dsc_params.compression_enable)
+ domains |= BIT_ULL(intel_dsc_power_domain(crtc_state));
+
return domains;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 5b53fc262b91..92e987fc3d9f 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1857,6 +1857,8 @@ uint8_t intel_dp_dsc_get_slice_count(struct intel_dp
*intel_dp, int mode_clock,
/* intel_vdsc.c */
int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config);
+enum intel_display_power_domain
+intel_dsc_power_domain(const struct intel_crtc_state *crtc_state);
static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
{
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index c0b0c8211481..58366cbc6045 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -578,6 +578,24 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
return intel_compute_rc_parameters(vdsc_cfg);
}
+enum intel_display_power_domain
+intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
+{
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+ /*
+* On ICL VDSC/joining for eDP transcoder uses a separate power well PW2
+* This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
+* For any other transcoder, VDSC/joining uses the power well associated
+* with the pipe/transcoder in use. Hence another reference on the
+* transcoder power domain will suffice.
+*/
+ if (cpu_transcoder == TRANSCODER_EDP)
+ return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
+ else
+ return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
+}
+
static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
const struct intel_crtc_state
*crtc_state)
{
@@ -1017,6 +1035,10 @@ void intel_dsc_enable(struct intel_encoder *encoder,
if (!crtc_state->dsc_params.compression_enable)
return;
+ /* Enable Power wells for VDSC/joining */
+ intel_display_power_get(dev_priv,
+ intel_dsc_power_domain(crtc_state));
+
intel_configure_pps_for_dsc_encoder(encoder, crtc_state);
intel_dp_write_dsc_pps_sdp(encoder, crtc_state);
@@ -1069,4 +1091,7 @@ void intel_dsc_disable(const struct intel_crtc_state
*old_crtc_state)
RIGHT_BRANCH_VDSC_ENABLE);
I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
+ /* Disable Power wells for VDSC/joining */
+ intel_display_power_put(dev_priv,
+ intel_dsc_power_domain(old_crtc_state));
}
--
2.19.1
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[Intel-gfx] [PATCH v9 15/24] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs
Infoframes are used to send secondary data packets. This patch
adds support for DSC Picture parameter set secondary data packets
in the existing write_infoframe helpers.
v3:
* Unused variables cleanup (Ville)
v2:
* Rebase on drm-tip (Manasi)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_hdmi.c | 21 +++--
2 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fe4b913e46ac..21e82c03cf80 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4567,6 +4567,7 @@ enum {
* of the infoframe structure specified by CEA-861. */
#define VIDEO_DIP_DATA_SIZE 32
#define VIDEO_DIP_VSC_DATA_SIZE 36
+#define VIDEO_DIP_PPS_DATA_SIZE 132
#define VIDEO_DIP_CTL _MMIO(0x61170)
/* Pre HSW: */
#define VIDEO_DIP_ENABLE (1 << 31)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index bc5b945f9a71..ae751679047c 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -115,6 +115,8 @@ static u32 hsw_infoframe_enable(unsigned int type)
switch (type) {
case DP_SDP_VSC:
return VIDEO_DIP_ENABLE_VSC_HSW;
+ case DP_SDP_PPS:
+ return VDIP_ENABLE_PPS;
case HDMI_INFOFRAME_TYPE_AVI:
return VIDEO_DIP_ENABLE_AVI_HSW;
case HDMI_INFOFRAME_TYPE_SPD:
@@ -136,6 +138,8 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv,
switch (type) {
case DP_SDP_VSC:
return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
+ case DP_SDP_PPS:
+ return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
case HDMI_INFOFRAME_TYPE_AVI:
return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
case HDMI_INFOFRAME_TYPE_SPD:
@@ -148,6 +152,18 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv,
}
}
+static int hsw_dip_data_size(unsigned int type)
+{
+ switch (type) {
+ case DP_SDP_VSC:
+ return VIDEO_DIP_VSC_DATA_SIZE;
+ case DP_SDP_PPS:
+ return VIDEO_DIP_PPS_DATA_SIZE;
+ default:
+ return VIDEO_DIP_DATA_SIZE;
+ }
+}
+
static void g4x_write_infoframe(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
unsigned int type,
@@ -382,11 +398,12 @@ static void hsw_write_infoframe(struct intel_encoder
*encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
- int data_size = type == DP_SDP_VSC ?
- VIDEO_DIP_VSC_DATA_SIZE : VIDEO_DIP_DATA_SIZE;
+ int data_size;
int i;
u32 val = I915_READ(ctl_reg);
+ data_size = hsw_dip_data_size(type);
+
val &= ~hsw_infoframe_enable(type);
I915_WRITE(ctl_reg, val);
--
2.19.1
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[Intel-gfx] [PATCH v9 08/24] drm/i915/dp: Compute DSC pipe config in atomic check
DSC params like the enable, compressed bpp, slice count and
dsc_split are added to the intel_crtc_state. These parameters
are set based on the requested mode and available link parameters
during the pipe configuration in atomic check phase.
These values are then later used to populate the remaining DSC
and RC parameters before enbaling DSC in atomic commit.
v13:
* Compute DSC bpc only when DSC is req to be enabled (Ville)
v12:
* Override bpp with dsc dpcd color depth (Manasi)
v11:
* Const crtc_state, reject DSC on DP without FEC (Ville)
* Dont set dsc_split to false (Ville)
v10:
* Add a helper for dp_dsc support (Ville)
* Set pipe_config to max bpp, link params for DSC for now (Ville)
* Compute bpp - use dp dsc support helper (Ville)
v9:
* Rebase on top of drm-tip that now uses fast_narrow config
for edp (Manasi)
v8:
* Check for DSC bpc not 0 (manasi)
v7:
* Fix indentation in compute_m_n (Manasi)
v6 (From Gaurav):
* Remove function call of intel_dp_compute_dsc_params() and
invoke intel_dp_compute_dsc_params() in the patch where
it is defined to fix compilation warning (Gaurav)
v5:
Add drm_dsc_cfg in intel_crtc_state (Manasi)
v4:
* Rebase on refactoring of intel_dp_compute_config on tip (Manasi)
* Add a comment why we need to check PSR while enabling DSC (Gaurav)
v3:
* Check PPR > max_cdclock to use 2 VDSC instances (Ville)
v2:
* Add if-else for eDP/DP (Gaurav)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Gaurav K Singh
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
Acked-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_display.c | 20 ++-
drivers/gpu/drm/i915/intel_display.h | 3 +-
drivers/gpu/drm/i915/intel_dp.c | 187 ---
drivers/gpu/drm/i915/intel_dp_mst.c | 2 +-
4 files changed, 184 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 132e978227fb..390c4b3970db 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6483,7 +6483,7 @@ static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc,
pipe_config->fdi_lanes = lane;
- intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
+ intel_link_compute_m_n(pipe_config->pipe_bpp, 0, lane, fdi_dotclock,
link_bw, _config->fdi_m_n, false);
ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
@@ -6723,17 +6723,25 @@ static void compute_m_n(unsigned int m, unsigned int n,
}
void
-intel_link_compute_m_n(int bits_per_pixel, int nlanes,
+intel_link_compute_m_n(int bits_per_pixel, uint16_t compressed_bpp,
+ int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
bool constant_n)
{
m_n->tu = 64;
- compute_m_n(bits_per_pixel * pixel_clock,
- link_clock * nlanes * 8,
- _n->gmch_m, _n->gmch_n,
- constant_n);
+ /* For DSC, Data M/N calculation uses compressed BPP */
+ if (compressed_bpp)
+ compute_m_n(compressed_bpp * pixel_clock,
+ link_clock * nlanes * 8,
+ _n->gmch_m, _n->gmch_n,
+ constant_n);
+ else
+ compute_m_n(bits_per_pixel * pixel_clock,
+ link_clock * nlanes * 8,
+ _n->gmch_m, _n->gmch_n,
+ constant_n);
compute_m_n(pixel_clock, link_clock,
_n->link_m, _n->link_n,
diff --git a/drivers/gpu/drm/i915/intel_display.h
b/drivers/gpu/drm/i915/intel_display.h
index 5d50decbcbb5..b0b23e1e9392 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -407,7 +407,8 @@ struct intel_link_m_n {
(__i)++) \
for_each_if(plane)
-void intel_link_compute_m_n(int bpp, int nlanes,
+void intel_link_compute_m_n(int bpp, uint16_t compressed_bpp,
+ int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
bool constant_n);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 2b090609bee2..931c3c7e55c1 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -47,6 +47,8 @@
/* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
#define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
+#define DP_DSC_MIN_SUPPORTED_BPC 8
+#define DP_DSC_MAX_SUPPORTED_BPC 10
/* DP DSC throughput values used for slice count calculations KPixels/s */
#define DP_DSC_PEAK_PIXEL_RATE 272
@@ -1708,6 +1710,29 @@ struct link_config_limits {
int min_bpp, max_bpp;
};
+static bool
[Intel-gfx] [PATCH v9 02/24] drm/dsc: Define Display Stream Compression PPS infoframe
This patch defines a new header file for all the DSC 1.2 structures
and creates a structure for PPS infoframe which will be used to send
picture parameter set secondary data packet for display stream compression.
All the PPS infoframe syntax elements are taken from DSC 1.2 specification
from VESA.
v4:
* Remove redundant blankline in doc (Ville)
* use drm_dsc namespace for all structs (Ville)
* Use packed struct (Ville)
v3:
* Add the SPDX shorthand (Chris Wilson)
v2:
* Do not use bitfields in the struct (Jani Nikula)
Cc: Gaurav K Singh
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Harry Wentland
Signed-off-by: Manasi Navare
Reviewed-by: Harry Wentland
---
include/drm/drm_dsc.h | 342 ++
1 file changed, 342 insertions(+)
create mode 100644 include/drm/drm_dsc.h
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
new file mode 100644
index ..78db4f61d01c
--- /dev/null
+++ b/include/drm/drm_dsc.h
@@ -0,0 +1,342 @@
+/* SPDX-License-Identifier: MIT
+ * Copyright (C) 2018 Intel Corp.
+ *
+ * Authors:
+ * Manasi Navare
+ */
+
+#ifndef DRM_DSC_H_
+#define DRM_DSC_H_
+
+#include
+
+/* VESA Display Stream Compression DSC 1.2 constants */
+#define DSC_NUM_BUF_RANGES 15
+
+/**
+ * struct picture_parameter_set - Represents 128 bytes of Picture Parameter Set
+ *
+ * The VESA DSC standard defines picture parameter set (PPS) which display
+ * stream compression encoders must communicate to decoders.
+ * The PPS is encapsulated in 128 bytes (PPS 0 through PPS 127). The fields in
+ * this structure are as per Table 4.1 in Vesa DSC specification v1.1/v1.2.
+ * The PPS fields that span over more than a byte should be stored in Big
Endian
+ * format.
+ */
+struct drm_dsc_picture_parameter_set {
+ /**
+* @dsc_version:
+* PPS0[3:0] - dsc_version_minor: Contains Minor version of DSC
+* PPS0[7:4] - dsc_version_major: Contains major version of DSC
+*/
+ u8 dsc_version;
+ /**
+* @pps_identifier:
+* PPS1[7:0] - Application specific identifier that can be
+* used to differentiate between different PPS tables.
+*/
+ u8 pps_identifier;
+ /**
+* @pps_reserved:
+* PPS2[7:0]- RESERVED Byte
+*/
+ u8 pps_reserved;
+ /**
+* @pps_3:
+* PPS3[3:0] - linebuf_depth: Contains linebuffer bit depth used to
+* generate the bitstream. (0x0 - 16 bits for DSC 1.2, 0x8 - 8 bits,
+* 0xA - 10 bits, 0xB - 11 bits, 0xC - 12 bits, 0xD - 13 bits,
+* 0xE - 14 bits for DSC1.2, 0xF - 14 bits for DSC 1.2.
+* PPS3[7:4] - bits_per_component: Bits per component for the original
+* pixels of the encoded picture.
+* 0x0 = 16bpc (allowed only when dsc_version_minor = 0x2)
+* 0x8 = 8bpc, 0xA = 10bpc, 0xC = 12bpc, 0xE = 14bpc (also
+* allowed only when dsc_minor_version = 0x2)
+*/
+ u8 pps_3;
+ /**
+* @pps_4:
+* PPS4[1:0] -These are the most significant 2 bits of
+* compressed BPP bits_per_pixel[9:0] syntax element.
+* PPS4[2] - vbr_enable: 0 = VBR disabled, 1 = VBR enabled
+* PPS4[3] - simple_422: Indicates if decoder drops samples to
+* reconstruct the 4:2:2 picture.
+* PPS4[4] - Convert_rgb: Indicates if DSC color space conversion is
+* active.
+* PPS4[5] - blobk_pred_enable: Indicates if BP is used to code any
+* groups in picture
+* PPS4[7:6] - Reseved bits
+*/
+ u8 pps_4;
+ /**
+* @bits_per_pixel_low:
+* PPS5[7:0] - This indicates the lower significant 8 bits of
+* the compressed BPP bits_per_pixel[9:0] element.
+*/
+ u8 bits_per_pixel_low;
+ /**
+* @pic_height:
+* PPS6[7:0], PPS7[7:0] -pic_height: Specifies the number of pixel rows
+* within the raster.
+*/
+ __be16 pic_height;
+ /**
+* @pic_width:
+* PPS8[7:0], PPS9[7:0] - pic_width: Number of pixel columns within
+* the raster.
+*/
+ __be16 pic_width;
+ /**
+* @slice_height:
+* PPS10[7:0], PPS11[7:0] - Slice height in units of pixels.
+*/
+ __be16 slice_height;
+ /**
+* @slice_width:
+* PPS12[7:0], PPS13[7:0] - Slice width in terms of pixels.
+*/
+ __be16 slice_width;
+ /**
+* @chunk_size:
+* PPS14[7:0], PPS15[7:0] - Size in units of bytes of the chunks
+* that are used for slice multiplexing.
+*/
+ __be16 chunk_size;
+ /**
+* @initial_xmit_delay_high:
+* PPS16[1:0] - Most Significant two bits of initial transmission delay.
+* It specifies the number of pixel times that the encoder waits before
+* transmitting data from its rate buffer.
+* PPS16[7:2] - Reserved
+*/
+
[Intel-gfx] [PATCH v9 04/24] drm/dsc: Define Rate Control values that do not change over configurations
From: "Srivatsa, Anusha"
DSC has some Rate Control values that remain constant
across all configurations. These are as per the DSC
standard.
v3:
* Define them in drm_dsc.h as they are
DSC constants (Manasi)
v2:
* Add DP_DSC_ prefix (Jani Nikula)
Cc: dri-de...@lists.freedesktop.org
Cc: Manasi Navare
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Gaurav K Singh
Cc: Harry Wentland
Signed-off-by: Anusha Srivatsa
Reviewed-by: Manasi Navare
---
include/drm/drm_dsc.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index 3292dfed9d0a..b88e31bd9da7 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -18,6 +18,12 @@
#define DSC_SCALE_DECREMENT_INTERVAL_MAX 4095
#define DSC_RANGE_BPG_OFFSET_MASK 0x3f
+/* DSC Rate Control Constants */
+#define DSC_RC_MODEL_SIZE_CONST8192
+#define DSC_RC_EDGE_FACTOR_CONST 6
+#define DSC_RC_TGT_OFFSET_HI_CONST 3
+#define DSC_RC_TGT_OFFSET_LO_CONST 3
+
/* Configuration for a single Rate Control model range */
struct drm_dsc_rc_range_parameters {
/* Min Quantization Parameters allowed for this range */
--
2.19.1
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[Intel-gfx] [PATCH v9 18/24] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits
1. Disable Left/right VDSC branch in DSS Ctrl reg
depending on the number of VDSC engines being used
2. Disable joiner in DSS Ctrl reg
v4:
* Remove encoder, make crtc_state const (Ville)
v3 (From Manasi):
* Add Disable PG2 for VDSC on eDP
v2 (From Manasi):
* Use old_crtc_state to find dsc params
* Add a condition to disable only if
dsc state compression is enabled
* Use correct DSS CTL regs
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Signed-off-by: Gaurav K Singh
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 2 ++
drivers/gpu/drm/i915/intel_vdsc.c| 32
3 files changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index dbabe54b0ae2..a2f1b27abbd6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3492,6 +3492,7 @@ extern bool intel_set_memory_cxsr(struct drm_i915_private
*dev_priv,
bool enable);
extern void intel_dsc_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
+extern void intel_dsc_disable(const struct intel_crtc_state *crtc_state);
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 210da9e9d31e..419f7a3ee1f9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5889,6 +5889,8 @@ static void haswell_crtc_disable(struct intel_crtc_state
*old_crtc_state,
if (!transcoder_is_dsi(cpu_transcoder))
intel_ddi_disable_transcoder_func(old_crtc_state);
+ intel_dsc_disable(old_crtc_state);
+
if (INTEL_GEN(dev_priv) >= 9)
skylake_scaler_disable(intel_crtc);
else
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index f0a74a83478f..c0b0c8211481 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -1038,3 +1038,35 @@ void intel_dsc_enable(struct intel_encoder *encoder,
return;
}
+
+void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
+ u32 dss_ctl1_val = 0, dss_ctl2_val = 0;
+
+ if (!old_crtc_state->dsc_params.compression_enable)
+ return;
+
+ if (old_crtc_state->cpu_transcoder == TRANSCODER_EDP) {
+ dss_ctl1_reg = DSS_CTL1;
+ dss_ctl2_reg = DSS_CTL2;
+ } else {
+ dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
+ dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
+ }
+ dss_ctl1_val = I915_READ(dss_ctl1_reg);
+ if (dss_ctl1_val & JOINER_ENABLE)
+ dss_ctl1_val &= ~JOINER_ENABLE;
+ I915_WRITE(dss_ctl1_reg, dss_ctl1_val);
+
+ dss_ctl2_val = I915_READ(dss_ctl2_reg);
+ if (dss_ctl2_val & LEFT_BRANCH_VDSC_ENABLE ||
+ dss_ctl2_val & RIGHT_BRANCH_VDSC_ENABLE)
+ dss_ctl2_val &= ~(LEFT_BRANCH_VDSC_ENABLE |
+ RIGHT_BRANCH_VDSC_ENABLE);
+ I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
+
+}
--
2.19.1
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[Intel-gfx] [PATCH v9 01/24] drm/dsc: Modify DRM helper to return complete DSC color depth capabilities
DSC DPCD color depth register advertises its color depth capabilities
by setting each of the bits that corresponding to a specific color
depth. This patch defines those specific color depths and adds
a helper to return an array of color depth capabilities.
Signed-off-by: Manasi Navare
Cc: Ville Syrjala
---
drivers/gpu/drm/drm_dp_helper.c | 29 +++--
include/drm/drm_dp_helper.h | 9 +
2 files changed, 24 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 6d483487f2b4..286567063960 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1428,17 +1428,26 @@ u8 drm_dp_dsc_sink_line_buf_depth(const u8
dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
}
EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth);
-u8 drm_dp_dsc_sink_max_color_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
+void drm_dp_dsc_sink_color_depth_cap(const u8
dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
+u8 *dsc_sink_color_depth_cap)
{
+ int i, cnt = 0;
u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];
- if (color_depth & DP_DSC_12_BPC)
- return 12;
- if (color_depth & DP_DSC_10_BPC)
- return 10;
- if (color_depth & DP_DSC_8_BPC)
- return 8;
-
- return 0;
+ for (i = 1; i <= 3; i++) {
+ if (!(color_depth & BIT(i)))
+ continue;
+ switch (i) {
+ case 1:
+ dsc_sink_color_depth_cap[cnt++] = DP_DSC_8_BPC;
+ break;
+ case 2:
+ dsc_sink_color_depth_cap[cnt++] = DP_DSC_10_BPC;
+ break;
+ case 3:
+ dsc_sink_color_depth_cap[cnt++] = DP_DSC_12_BPC;
+ break;
+ }
+ }
}
-EXPORT_SYMBOL(drm_dp_dsc_sink_max_color_depth);
+EXPORT_SYMBOL(drm_dp_dsc_sink_color_depth_cap);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 3314e91f6eb3..ea3233b0a790 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -242,9 +242,9 @@
# define DP_DSC_YCbCr420_Native (1 << 4)
#define DP_DSC_DEC_COLOR_DEPTH_CAP 0x06A
-# define DP_DSC_8_BPC (1 << 1)
-# define DP_DSC_10_BPC (1 << 2)
-# define DP_DSC_12_BPC (1 << 3)
+# define DP_DSC_8_BPC 8
+# define DP_DSC_10_BPC 10
+# define DP_DSC_12_BPC 12
#define DP_DSC_PEAK_THROUGHPUT 0x06B
# define DP_DSC_THROUGHPUT_MODE_0_MASK (0xf << 0)
@@ -1123,7 +1123,8 @@ drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
bool is_edp);
u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
-u8 drm_dp_dsc_sink_max_color_depth(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE]);
+void drm_dp_dsc_sink_color_depth_cap(const u8
dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE],
+u8 *dsc_sink_color_depth_cap);
static inline bool
drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
--
2.19.1
___
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[Intel-gfx] [PATCH v9 03/24] drm/dsc: Define VESA Display Stream Compression Capabilities
This defines all the DSC parameters as per the VESA DSC spec
that will be required for DSC encoder/decoder
v6: (From Manasi)
* Add a bit mask for RANGE_BPG_OFFSET for 6 bits(Manasi)
v5 (From Manasi)
* Add the RC constants as per the spec
v4 (From Manasi)
* Add the DSC_MUX_WORD_SIZE constants (Manasi)
v3 (From Manasi)
* Remove the duplicate define (Suggested By:Harry Wentland)
v2: Define this struct in DRM (From Manasi)
* Changed the data types to u8/u16 instead of unsigned longs (Manasi)
* Remove driver specific fields (Manasi)
* Move this struct definition to DRM (Manasi)
* Define DSC 1.2 parameters (Manasi)
* Use DSC_NUM_BUF_RANGES (Manasi)
* Call it drm_dsc_config (Manasi)
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Harry Wentland
Signed-off-by: Manasi Navare
Signed-off-by: Gaurav K Singh
Co-developed-by: Gaurav K Singh
Acked-by: Harry Wentland
Reviewed-by: Anusha Srivatsa
---
include/drm/drm_dsc.h | 115 +-
1 file changed, 114 insertions(+), 1 deletion(-)
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index 78db4f61d01c..3292dfed9d0a 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -11,7 +11,120 @@
#include
/* VESA Display Stream Compression DSC 1.2 constants */
-#define DSC_NUM_BUF_RANGES 15
+#define DSC_NUM_BUF_RANGES 15
+#define DSC_MUX_WORD_SIZE_8_10_BPC 48
+#define DSC_MUX_WORD_SIZE_12_BPC 64
+#define DSC_RC_PIXELS_PER_GROUP3
+#define DSC_SCALE_DECREMENT_INTERVAL_MAX 4095
+#define DSC_RANGE_BPG_OFFSET_MASK 0x3f
+
+/* Configuration for a single Rate Control model range */
+struct drm_dsc_rc_range_parameters {
+ /* Min Quantization Parameters allowed for this range */
+ u8 range_min_qp;
+ /* Max Quantization Parameters allowed for this range */
+ u8 range_max_qp;
+ /* Bits/group offset to apply to target for this group */
+ u8 range_bpg_offset;
+};
+
+struct drm_dsc_config {
+ /* Bits / component for previous reconstructed line buffer */
+ u8 line_buf_depth;
+ /* Bits per component to code (must be 8, 10, or 12) */
+ u8 bits_per_component;
+ /*
+* Flag indicating to do RGB - YCoCg conversion
+* and back (should be 1 for RGB input)
+*/
+ bool convert_rgb;
+ u8 slice_count;
+ /* Slice Width */
+ u16 slice_width;
+ /* Slice Height */
+ u16 slice_height;
+ /*
+* 4:2:2 enable mode (from PPS, 4:2:2 conversion happens
+* outside of DSC encode/decode algorithm)
+*/
+ bool enable422;
+ /* Picture Width */
+ u16 pic_width;
+ /* Picture Height */
+ u16 pic_height;
+ /* Offset to bits/group used by RC to determine QP adjustment */
+ u8 rc_tgt_offset_high;
+ /* Offset to bits/group used by RC to determine QP adjustment */
+ u8 rc_tgt_offset_low;
+ /* Bits/pixel target << 4 (ie., 4 fractional bits) */
+ u16 bits_per_pixel;
+ /*
+* Factor to determine if an edge is present based
+* on the bits produced
+*/
+ u8 rc_edge_factor;
+ /* Slow down incrementing once the range reaches this value */
+ u8 rc_quant_incr_limit1;
+ /* Slow down incrementing once the range reaches this value */
+ u8 rc_quant_incr_limit0;
+ /* Number of pixels to delay the initial transmission */
+ u16 initial_xmit_delay;
+ /* Number of pixels to delay the VLD on the decoder,not including SSM */
+ u16 initial_dec_delay;
+ /* Block prediction enable */
+ bool block_pred_enable;
+ /* Bits/group offset to use for first line of the slice */
+ u8 first_line_bpg_offset;
+ /* Value to use for RC model offset at slice start */
+ u16 initial_offset;
+ /* Thresholds defining each of the buffer ranges */
+ u16 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1];
+ /* Parameters for each of the RC ranges */
+ struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
+ /* Total size of RC model */
+ u16 rc_model_size;
+ /* Minimum QP where flatness information is sent */
+ u8 flatness_min_qp;
+ /* Maximum QP where flatness information is sent */
+ u8 flatness_max_qp;
+ /* Initial value for scale factor */
+ u8 initial_scale_value;
+ /* Decrement scale factor every scale_decrement_interval groups */
+ u16 scale_decrement_interval;
+ /* Increment scale factor every scale_increment_interval groups */
+ u16 scale_increment_interval;
+ /* Non-first line BPG offset to use */
+ u16 nfl_bpg_offset;
+ /* BPG offset used to enforce slice bit */
+ u16 slice_bpg_offset;
+ /* Final RC linear transformation offset value */
+ u16 final_offset;
+ /* Enable on-off VBR (ie.,
[Intel-gfx] [PATCH v9 09/24] drm/i915/dp: Do not enable PSR2 if DSC is enabled
If a eDP panel supports both PSR2 and VDSC, our HW cannot
support both at a time. Give priority to PSR2 if a requested
resolution can be supported without compression else enable
VDSC and keep PSR2 disabled.
v4:
Fix the unrealted stuff removed during rebase (Ville)
v3:
* Rebase
v2:
* Add warning for DSC and PSR2 enabled together (DK)
Cc: Rodrigo Vivi
Cc: Jani Nikula
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_psr.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 48df16a02fac..c42670b20326 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -75,6 +75,10 @@ static bool intel_psr2_enabled(struct drm_i915_private
*dev_priv,
if (i915_modparams.enable_psr == -1)
return false;
+ /* Cannot enable DSC and PSR2 simultaneously */
+ WARN_ON(crtc_state->dsc_params.compression_enable &&
+ crtc_state->has_psr2);
+
switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
case I915_PSR_DEBUG_FORCE_PSR1:
return false;
@@ -463,6 +467,16 @@ static bool intel_psr2_config_valid(struct intel_dp
*intel_dp,
if (!dev_priv->psr.sink_psr2_support)
return false;
+ /*
+* DSC and PSR2 cannot be enabled simultaneously. If a requested
+* resolution requires DSC to be enabled, priority is given to DSC
+* over PSR2.
+*/
+ if (crtc_state->dsc_params.compression_enable) {
+ DRM_DEBUG_KMS("PSR2 cannot be enabled since DSC is enabled\n");
+ return false;
+ }
+
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
psr_max_h = 4096;
psr_max_v = 2304;
--
2.19.1
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[Intel-gfx] [PATCH v9 10/24] drm/i915/dsc: Define & Compute VESA DSC params
From: Gaurav K Singh
This patches does the following:
1. This patch defines all the DSC parameters as per the VESA
DSC specification. These are stored in the encoder and used
to compute the PPS parameters to be sent to the Sink.
2. Compute all the DSC parameters which are derived from DSC
state of intel_crtc_state.
3. Compute all parameters that are VESA DSC specific
This computation happens in the atomic check phase during
compute_config() to validate if display stream compression
can be enabled for the requested mode.
v8 (From Manasi):
* DEBUG_KMS instead of DRM_ERROR for user triggerable
errors (Ville)
v7: (From Manasi)
* Dont use signed int for rc_range_params (Manasi)
* Mask the range_bpg_offset to use only 6 bits
* Add SPDX identifier (Chris Wilson)
v6 (From Manasi):
* Add a check for line_buf_depth return value (Anusha)
* Remove DRM DSC constants to different patch (Manasi)
v5 (From Manasi):
* Add logic to limit the max line buf depth for DSC 1.1 to 13
as per DSC 1.1 spec
* Fix dim checkpatch warnings/checks
v4 (From Gaurav):
* Rebase on latest drm tip
* rename variable name(Manasi)
* Populate linebuf_depth variable(Manasi)
v3 (From Gaurav):
* Rebase my previous patches on top of Manasi's latest patch
series
* Using >>n rather than /2^n (Manasi)
* Change the commit message to explain what the patch is doing(Gaurav)
Fixed review comments from Ville:
* Don't use macro TWOS_COMPLEMENT
* Mention in comment about the source of RC params
* Return directly from case statements
* Using single asssignment for assigning rc_range_params
* Using <
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Gaurav K Singh
Signed-off-by: Gaurav K Singh
Signed-off-by: Manasi Navare
Co-developed-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/intel_dp.c | 7 +
drivers/gpu/drm/i915/intel_drv.h | 4 +
drivers/gpu/drm/i915/intel_vdsc.c | 455 ++
include/drm/drm_dp_helper.h | 3 +
5 files changed, 471 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/intel_vdsc.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 0ff878c994e2..8370b9de6e4f 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -157,7 +157,8 @@ i915-y += dvo_ch7017.o \
intel_sdvo.o \
intel_tv.o \
vlv_dsi.o \
- vlv_dsi_pll.o
+ vlv_dsi_pll.o \
+ intel_vdsc.o
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 931c3c7e55c1..0bdaa6e848a9 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1959,6 +1959,13 @@ static bool intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
return false;
}
}
+ if (intel_dp_compute_dsc_params(intel_dp, pipe_config) < 0) {
+ DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input
Bpp = %d"
+ "Compressed BPP = %d\n",
+ pipe_config->pipe_bpp,
+ pipe_config->dsc_params.compressed_bpp);
+ return false;
+ }
pipe_config->dsc_params.compression_enable = true;
DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d "
"Compressed Bpp = %d Slice Count = %d\n",
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 10476fec9485..d6466c401358 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1851,6 +1851,10 @@ uint16_t intel_dp_dsc_get_output_bpp(int link_clock,
uint8_t lane_count,
uint8_t intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock,
int mode_hdisplay);
+/* intel_vdsc.c */
+int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config);
+
static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
{
return ~((1 << lane_count) - 1) & 0xf;
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
new file mode 100644
index ..0a1918f2f643
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -0,0 +1,455 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Author: Gaurav K Singh
+ * Manasi Navare
+ */
+
+#include
+#include
+#include "i915_drv.h"
+#include "intel_drv.h"
+
+enum ROW_INDEX_BPP {
+ ROW_INDEX_6BPP = 0,
+ ROW_INDEX_8BPP,
+ ROW_INDEX_10BPP,
+ ROW_INDEX_12BPP,
+ ROW_INDEX_15BPP,
+ MAX_ROW_INDEX
+};
+
+enum COLUMN_INDEX_BPC {
+ COLUMN_INDEX_8BPC = 0,
+ COLUMN_INDEX_10BPC,
+ COLUMN_INDEX_12BPC,
+ COLUMN_INDEX_14BPC,
+ COLUMN_INDEX_16BPC,
+
[Intel-gfx] [PATCH v9 16/24] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes
DSC PPS secondary data packet infoframes are filled with
DSC picure parameter set metadata according to the DSC standard.
These infoframes are sent to the sink device and used during DSC
decoding.
v3:
* Rename to intel_dp_write_pps_sdp (Ville)
* Use const intel_crtc_state (Ville)
v2:
* Rebase ond drm-tip
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_vdsc.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index 94f346b97c10..e18053043067 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -985,6 +985,25 @@ static void intel_configure_pps_for_dsc_encoder(struct
intel_encoder *encoder,
}
}
+static void intel_dp_write_dsc_pps_sdp(struct intel_encoder *encoder,
+ const struct intel_crtc_state
*crtc_state)
+{
+ struct intel_dp *intel_dp = enc_to_intel_dp(>base);
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ const struct drm_dsc_config *vdsc_cfg = _state->dp_dsc_cfg;
+ struct drm_dsc_pps_infoframe dp_dsc_pps_sdp;
+
+ /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */
+ drm_dsc_dp_pps_header_init(_dsc_pps_sdp);
+
+ /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */
+ drm_dsc_pps_infoframe_pack(_dsc_pps_sdp, vdsc_cfg);
+
+ intel_dig_port->write_infoframe(encoder, crtc_state,
+ DP_SDP_PPS, _dsc_pps_sdp,
+ sizeof(dp_dsc_pps_sdp));
+}
+
void intel_dsc_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
@@ -994,5 +1013,7 @@ void intel_dsc_enable(struct intel_encoder *encoder,
intel_configure_pps_for_dsc_encoder(encoder, crtc_state);
+ intel_dp_write_dsc_pps_sdp(encoder, crtc_state);
+
return;
}
--
2.19.1
___
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[Intel-gfx] [PATCH v9 17/24] drm/i915/dp: Configure Display stream splitter registers during DSC enable
Display Stream Splitter registers need to be programmed to enable
the joiner if two DSC engines are used and also to enable
the left and the right DSC engines. This happens as part of
the DSC enabling routine in the source in atomic commit.
v4:
* Remove redundant comment (Ville)
v3:
* Use cpu_transcoder instead of encoder->type (Ville)
v2:
* Rebase (Manasi)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_vdsc.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index e18053043067..f0a74a83478f 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -1007,6 +1007,12 @@ static void intel_dp_write_dsc_pps_sdp(struct
intel_encoder *encoder,
void intel_dsc_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum pipe pipe = crtc->pipe;
+ i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
+ u32 dss_ctl1_val = 0;
+ u32 dss_ctl2_val = 0;
if (!crtc_state->dsc_params.compression_enable)
return;
@@ -1015,5 +1021,20 @@ void intel_dsc_enable(struct intel_encoder *encoder,
intel_dp_write_dsc_pps_sdp(encoder, crtc_state);
+ if (crtc_state->cpu_transcoder == TRANSCODER_EDP) {
+ dss_ctl1_reg = DSS_CTL1;
+ dss_ctl2_reg = DSS_CTL2;
+ } else {
+ dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
+ dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
+ }
+ dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE;
+ if (crtc_state->dsc_params.dsc_split) {
+ dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;
+ dss_ctl1_val |= JOINER_ENABLE;
+ }
+ I915_WRITE(dss_ctl1_reg, dss_ctl1_val);
+ I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
+
return;
}
--
2.19.1
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[Intel-gfx] [PATCH v9 11/24] drm/i915/dsc: Compute Rate Control parameters for DSC
From: Gaurav K Singh
This computation of RC params happens in the atomic commit phase
during compute_config() to validate if display stream compression
can be enabled for the requested mode.
v7 (From Manasi):
* Use DRM_DEBUG instead of DRM_ERROR (Ville)
* Use Error numberinstead of -1 (Ville)
v6 (From Manasi):
* Use 9 instead of 0x9 for consistency (Anusha)
v5 (From Manasi):
* Fix dim checkpatch warnings/checks
v4(From Gaurav):
* No change.Rebase on drm-tip
v3 (From Gaurav):
* Rebase on top of Manasi's latest series
* Return -ve value in case of failure scenarios (Manasi)
Fix review comments from Ville:
* Remove unnecessary comments
* Remove unnecessary paranthesis
* Add comments for few RC params calculations
v2 (From Manasi):
* Rebase Gaurav's patch from intel-gfx to gfx-internal
* Use struct drm_dsc_cfg instead of struct intel_dp
as a parameter
Cc: Manasi Navare
Cc: Jani Nikula
Cc: Ville Syrjala
Signed-off-by: Gaurav K Singh
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_vdsc.c | 126 +-
1 file changed, 125 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index 0a1918f2f643..b644f69f1c93 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -317,6 +317,130 @@ static int get_column_index_for_rc_params(u8
bits_per_component)
}
}
+static int intel_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
+{
+ unsigned long groups_per_line = 0;
+ unsigned long groups_total = 0;
+ unsigned long num_extra_mux_bits = 0;
+ unsigned long slice_bits = 0;
+ unsigned long hrd_delay = 0;
+ unsigned long final_scale = 0;
+ unsigned long rbs_min = 0;
+
+ /* Number of groups used to code each line of a slice */
+ groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
+ DSC_RC_PIXELS_PER_GROUP);
+
+ /* chunksize in Bytes */
+ vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
+ vdsc_cfg->bits_per_pixel,
+ (8 * 16));
+
+ if (vdsc_cfg->convert_rgb)
+ num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size +
+ (4 * vdsc_cfg->bits_per_component + 4)
+ - 2);
+ else
+ num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size +
+ (4 * vdsc_cfg->bits_per_component + 4) +
+ 2 * (4 * vdsc_cfg->bits_per_component) - 2;
+ /* Number of bits in one Slice */
+ slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height;
+
+ while ((num_extra_mux_bits > 0) &&
+ ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size))
+ num_extra_mux_bits--;
+
+ if (groups_per_line < vdsc_cfg->initial_scale_value - 8)
+ vdsc_cfg->initial_scale_value = groups_per_line + 8;
+
+ /* scale_decrement_interval calculation according to DSC spec 1.11 */
+ if (vdsc_cfg->initial_scale_value > 8)
+ vdsc_cfg->scale_decrement_interval = groups_per_line /
+ (vdsc_cfg->initial_scale_value - 8);
+ else
+ vdsc_cfg->scale_decrement_interval =
DSC_SCALE_DECREMENT_INTERVAL_MAX;
+
+ vdsc_cfg->final_offset = vdsc_cfg->rc_model_size -
+ (vdsc_cfg->initial_xmit_delay *
+vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits;
+
+ if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) {
+ DRM_DEBUG_KMS("FinalOfs < RcModelSze for this
InitialXmitDelay\n");
+ return -ERANGE;
+ }
+
+ final_scale = (vdsc_cfg->rc_model_size * 8) /
+ (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset);
+ if (vdsc_cfg->slice_height > 1)
+ /*
+* NflBpgOffset is 16 bit value with 11 fractional bits
+* hence we multiply by 2^11 for preserving the
+* fractional part
+*/
+ vdsc_cfg->nfl_bpg_offset =
DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11),
+ (vdsc_cfg->slice_height
- 1));
+ else
+ vdsc_cfg->nfl_bpg_offset = 0;
+
+ /* 2^16 - 1 */
+ if (vdsc_cfg->nfl_bpg_offset > 65535) {
+ DRM_DEBUG_KMS("NflBpgOffset is too large for this slice
height\n");
+ return -ERANGE;
+ }
+
+ /* Number of groups used to code the entire slice */
+ groups_total = groups_per_line * vdsc_cfg->slice_height;
+
+ /* slice_bpg_offset is 16 bit value with 11 fractional bits */
+ vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size -
+
[Intel-gfx] [PATCH v9 12/24] drm/i915/dp: Enable/Disable DSC in DP Sink
From: Gaurav K Singh
This patch enables decompression support in sink device
before link training and disables the same during the
DDI disabling.
v3 (From manasi):
* Pass bool state to enable/disable (Ville)
v2:(From Manasi)
* Change the enable/disable function to take crtc_state
instead of intel_dp as an argument (Manasi)
* Use the compression_enable flag as part of crtc_state (Manasi)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Gaurav K Singh
Signed-off-by: Gaurav K Singh
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_ddi.c | 5 +
drivers/gpu/drm/i915/intel_dp.c | 16
drivers/gpu/drm/i915/intel_drv.h | 3 +++
3 files changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 4913bbdac843..c7d417e6262f 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3134,6 +3134,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder
*encoder,
intel_ddi_init_dp_buf_reg(encoder);
if (!is_mst)
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+ intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
+ true);
intel_dp_start_link_train(intel_dp);
if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
intel_dp_stop_link_train(intel_dp);
@@ -3478,6 +3480,9 @@ static void intel_disable_ddi_dp(struct intel_encoder
*encoder,
intel_edp_drrs_disable(intel_dp, old_crtc_state);
intel_psr_disable(intel_dp, old_crtc_state);
intel_edp_backlight_off(old_conn_state);
+ /* Disable the decompression in DP Sink */
+ intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
+ false);
}
static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 0bdaa6e848a9..b43a77bf42df 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2856,6 +2856,22 @@ static bool downstream_hpd_needs_d0(struct intel_dp
*intel_dp)
intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
}
+void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
+ const struct intel_crtc_state
*crtc_state,
+ bool enable)
+{
+ int ret;
+
+ if (!crtc_state->dsc_params.compression_enable)
+ return;
+
+ ret = drm_dp_dpcd_writeb(_dp->aux, DP_DSC_ENABLE,
+enable ? DP_DECOMPRESSION_EN : 0);
+ if (ret < 0)
+ DRM_DEBUG_KMS("Failed to %s sink decompression state\n",
+ enable ? "enable" : "disable");
+}
+
/* If the sink supports it, try to set the power state appropriately */
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
{
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d6466c401358..5b53fc262b91 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1796,6 +1796,9 @@ void intel_dp_stop_link_train(struct intel_dp *intel_dp);
int intel_dp_retrain_link(struct intel_encoder *encoder,
struct drm_modeset_acquire_ctx *ctx);
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
+void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
+ const struct intel_crtc_state
*crtc_state,
+ bool enable);
void intel_dp_encoder_reset(struct drm_encoder *encoder);
void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
void intel_dp_encoder_destroy(struct drm_encoder *encoder);
--
2.19.1
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[Intel-gfx] [PATCH v9 07/24] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state
Basic DSC parameters and DSC configuration data needs to be computed
for each of the requested mode during atomic check. This is
required since for certain modes, valid DSC parameters and config
data might not be computed in which case compression cannot be
enabled for that mode.
For that reason we need to add these params and config structure
to the intel_crtc_state so that if valid this state information
can directly be used while enabling DSC in atomic commit.
v2:
* Rebase on drm-tip (Manasi)
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_drv.h | 9 +
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5d686b585a95..8fbf45cd3eb8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -53,6 +53,7 @@
#include
#include
#include
+#include
#include "i915_params.h"
#include "i915_reg.h"
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 18b419f7f7fe..10476fec9485 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -936,6 +936,15 @@ struct intel_crtc_state {
/* Output down scaling is done in LSPCON device */
bool lspcon_downsampling;
+
+ /* Display Stream compression state */
+ struct {
+ bool compression_enable;
+ bool dsc_split;
+ u16 compressed_bpp;
+ u8 slice_count;
+ } dsc_params;
+ struct drm_dsc_config dp_dsc_cfg;
};
struct intel_crtc {
--
2.19.1
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[Intel-gfx] [CI] drm/i915: don't apply Display WAs 1125 and 1126 to GLK/CNL+
BSpec does not show these WAs as applicable to GLK, and for CNL it
only shows them applicable for a super early pre-production stepping
we shouldn't be caring about anymore. Remove these so we can avoid
them on ICL too.
v2: Change how we check for gen9 display platforms (Ville).
Cc: Matt Roper
Reviewed-by: Ville Syrjälä
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_pm.c | 43 ++---
1 file changed, 23 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 27498ded4949..18914c4ca070 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4755,28 +4755,31 @@ static int skl_compute_plane_wm(const struct
drm_i915_private *dev_priv,
res_lines = div_round_up_fixed16(selected_result,
wp->plane_blocks_per_line);
- /* Display WA #1125: skl,bxt,kbl,glk */
- if (level == 0 && wp->rc_surface)
- res_blocks += fixed16_to_u32_round_up(wp->y_tile_minimum);
+ if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) {
+ /* Display WA #1125: skl,bxt,kbl */
+ if (level == 0 && wp->rc_surface)
+ res_blocks +=
+ fixed16_to_u32_round_up(wp->y_tile_minimum);
+
+ /* Display WA #1126: skl,bxt,kbl */
+ if (level >= 1 && level <= 7) {
+ if (wp->y_tiled) {
+ res_blocks +=
+ fixed16_to_u32_round_up(wp->y_tile_minimum);
+ res_lines += wp->y_min_scanlines;
+ } else {
+ res_blocks++;
+ }
- /* Display WA #1126: skl,bxt,kbl,glk */
- if (level >= 1 && level <= 7) {
- if (wp->y_tiled) {
- res_blocks += fixed16_to_u32_round_up(
- wp->y_tile_minimum);
- res_lines += wp->y_min_scanlines;
- } else {
- res_blocks++;
+ /*
+* Make sure result blocks for higher latency levels are
+* atleast as high as level below the current level.
+* Assumption in DDB algorithm optimization for special
+* cases. Also covers Display WA #1125 for RC.
+*/
+ if (result_prev->plane_res_b > res_blocks)
+ res_blocks = result_prev->plane_res_b;
}
-
- /*
-* Make sure result blocks for higher latency levels are atleast
-* as high as level below the current level.
-* Assumption in DDB algorithm optimization for special cases.
-* Also covers Display WA #1125 for RC.
-*/
- if (result_prev->plane_res_b > res_blocks)
- res_blocks = result_prev->plane_res_b;
}
if (INTEL_GEN(dev_priv) >= 11) {
--
2.17.2
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/3] drm/i915/icl: replace check for combo phy
== Series Details == Series: series starting with [v3,1/3] drm/i915/icl: replace check for combo phy URL : https://patchwork.freedesktop.org/series/52459/ State : warning == Summary == $ dim checkpatch origin/drm-tip f5816a94faad drm/i915/icl: replace check for combo phy -:23: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__port' - possible side-effects? #23: FILE: drivers/gpu/drm/i915/intel_combo_phy.c:8: +#define for_each_combo_port(__dev_priv, __port) \ + for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \ + for_each_if(intel_port_is_combophy(__dev_priv, __port)) total: 0 errors, 0 warnings, 1 checks, 26 lines checked a96e90922991 drm/i915/icl: reverse uninit order -:26: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__port' - possible side-effects? #26: FILE: drivers/gpu/drm/i915/intel_combo_phy.c:12: +#define for_each_combo_port_reverse(__dev_priv, __port) \ + for ((__port) = I915_MAX_PORTS; (__port)-- > PORT_A;) \ + for_each_if(intel_port_is_combophy(__dev_priv, __port)) total: 0 errors, 0 warnings, 1 checks, 18 lines checked 49663aa28220 drm/i195: spell out reverse on for_each macros -:20: ERROR:MULTISTATEMENT_MACRO_USE_DO_WHILE: Macros with multiple statements should be enclosed in a do - while loop #20: FILE: drivers/gpu/drm/i915/intel_display.h:371: +#define for_each_power_well_reverse(__dev_priv, __power_well) \ for ((__power_well) = (__dev_priv)->power_domains.power_wells + \ (__dev_priv)->power_domains.power_well_count - 1; \ (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \ -:20: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__dev_priv' - possible side-effects? #20: FILE: drivers/gpu/drm/i915/intel_display.h:371: +#define for_each_power_well_reverse(__dev_priv, __power_well) \ for ((__power_well) = (__dev_priv)->power_domains.power_wells + \ (__dev_priv)->power_domains.power_well_count - 1; \ (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \ -:20: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__power_well' - possible side-effects? #20: FILE: drivers/gpu/drm/i915/intel_display.h:371: +#define for_each_power_well_reverse(__dev_priv, __power_well) \ for ((__power_well) = (__dev_priv)->power_domains.power_wells + \ (__dev_priv)->power_domains.power_well_count - 1; \ (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \ -:30: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #30: FILE: drivers/gpu/drm/i915/intel_display.h:381: +#define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \ + for_each_power_well_reverse(__dev_priv, __power_well) \ for_each_if((__power_well)->desc->domains & (__domain_mask)) -:30: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__power_well' - possible side-effects? #30: FILE: drivers/gpu/drm/i915/intel_display.h:381: +#define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \ + for_each_power_well_reverse(__dev_priv, __power_well) \ for_each_if((__power_well)->desc->domains & (__domain_mask)) total: 2 errors, 0 warnings, 3 checks, 34 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 1/3] drm/i915/icl: replace check for combo phy
These are the only places that assume ports A and B are the ones with
combo phy. Let's use intel_port_is_combophy() there to make sure
it checks for combo phy ports the same way everywhere.
v2: define for_each_combo_port() helper to check the ports
Signed-off-by: Lucas De Marchi
Reviewed-by: Imre Deak
---
drivers/gpu/drm/i915/intel_combo_phy.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_combo_phy.c
b/drivers/gpu/drm/i915/intel_combo_phy.c
index f7c16f6724f0..49f3a533860d 100644
--- a/drivers/gpu/drm/i915/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/intel_combo_phy.c
@@ -5,6 +5,10 @@
#include "intel_drv.h"
+#define for_each_combo_port(__dev_priv, __port) \
+ for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
+ for_each_if(intel_port_is_combophy(__dev_priv, __port))
+
enum {
PROCMON_0_85V_DOT_0,
PROCMON_0_95V_DOT_0,
@@ -199,7 +203,7 @@ void icl_combo_phys_init(struct drm_i915_private *dev_priv)
{
enum port port;
- for (port = PORT_A; port <= PORT_B; port++) {
+ for_each_combo_port(dev_priv, port) {
u32 val;
if (icl_combo_phy_verify_state(dev_priv, port)) {
@@ -228,7 +232,7 @@ void icl_combo_phys_uninit(struct drm_i915_private
*dev_priv)
{
enum port port;
- for (port = PORT_A; port <= PORT_B; port++) {
+ for_each_combo_port(dev_priv, port) {
u32 val;
if (!icl_combo_phy_verify_state(dev_priv, port))
--
2.19.1.1.g56c4683e68
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[Intel-gfx] [PATCH v3 2/3] drm/i915/icl: reverse uninit order
Bspec 21257 says "DDIA PHY is the comp master, so it must
not be un-initialized if other combo PHYs are in use". Here
we are shutting down all phys, so it's not strictly required.
However let's be consistent on deinitializing things in the
reversed order we initialized them.
v2: simplify protection for enum port being unsigned in future
v3: spell out reverse rather than rev
Signed-off-by: Lucas De Marchi
Reviewed-by: Imre Deak
---
drivers/gpu/drm/i915/intel_combo_phy.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_combo_phy.c
b/drivers/gpu/drm/i915/intel_combo_phy.c
index 49f3a533860d..3d0271cebf99 100644
--- a/drivers/gpu/drm/i915/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/intel_combo_phy.c
@@ -9,6 +9,10 @@
for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
for_each_if(intel_port_is_combophy(__dev_priv, __port))
+#define for_each_combo_port_reverse(__dev_priv, __port) \
+ for ((__port) = I915_MAX_PORTS; (__port)-- > PORT_A;) \
+ for_each_if(intel_port_is_combophy(__dev_priv, __port))
+
enum {
PROCMON_0_85V_DOT_0,
PROCMON_0_95V_DOT_0,
@@ -232,7 +236,7 @@ void icl_combo_phys_uninit(struct drm_i915_private
*dev_priv)
{
enum port port;
- for_each_combo_port(dev_priv, port) {
+ for_each_combo_port_reverse(dev_priv, port) {
u32 val;
if (!icl_combo_phy_verify_state(dev_priv, port))
--
2.19.1.1.g56c4683e68
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[Intel-gfx] [PATCH v3 3/3] drm/i195: spell out reverse on for_each macros
Do like it's done for list.h macros, and use "reverse" suffix rather
than "rev".
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_display.h| 6 +++---
drivers/gpu/drm/i915/intel_runtime_pm.c | 4 ++--
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.h
b/drivers/gpu/drm/i915/intel_display.h
index 5d50decbcbb5..43eb4ebbcc35 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -368,7 +368,7 @@ struct intel_link_m_n {
(__dev_priv)->power_domains.power_well_count; \
(__power_well)++)
-#define for_each_power_well_rev(__dev_priv, __power_well)
\
+#define for_each_power_well_reverse(__dev_priv, __power_well)
\
for ((__power_well) = (__dev_priv)->power_domains.power_wells +
\
(__dev_priv)->power_domains.power_well_count - 1;
\
(__power_well) - (__dev_priv)->power_domains.power_wells >= 0;
\
@@ -378,8 +378,8 @@ struct intel_link_m_n {
for_each_power_well(__dev_priv, __power_well)
\
for_each_if((__power_well)->desc->domains & (__domain_mask))
-#define for_each_power_domain_well_rev(__dev_priv, __power_well,
__domain_mask) \
- for_each_power_well_rev(__dev_priv, __power_well)
\
+#define for_each_power_domain_well_reverse(__dev_priv, __power_well,
__domain_mask) \
+ for_each_power_well_reverse(__dev_priv, __power_well)
\
for_each_if((__power_well)->desc->domains & (__domain_mask))
#define for_each_new_intel_plane_in_state(__state, plane, new_plane_state,
__i) \
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index f945db6ea420..7aa5f07f1356 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -208,7 +208,7 @@ bool __intel_display_power_is_enabled(struct
drm_i915_private *dev_priv,
is_enabled = true;
- for_each_power_domain_well_rev(dev_priv, power_well, BIT_ULL(domain)) {
+ for_each_power_domain_well_reverse(dev_priv, power_well,
BIT_ULL(domain)) {
if (power_well->desc->always_on)
continue;
@@ -1651,7 +1651,7 @@ void intel_display_power_put(struct drm_i915_private
*dev_priv,
intel_display_power_domain_str(domain));
power_domains->domain_use_count[domain]--;
- for_each_power_domain_well_rev(dev_priv, power_well, BIT_ULL(domain))
+ for_each_power_domain_well_reverse(dev_priv, power_well,
BIT_ULL(domain))
intel_power_well_put(dev_priv, power_well);
mutex_unlock(_domains->lock);
--
2.19.1.1.g56c4683e68
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Re: [Intel-gfx] [RFC v5 2/8] drm: Add Plane Degamma properties
On Sun, Sep 16, 2018 at 01:45:25PM +0530, Uma Shankar wrote:
> Add Plane Degamma as a blob property and plane degamma size as
> a range property.
>
> v2: Rebase
>
> v3: Fixed Sean, Paul's review comments. Moved the property from
> mode_config to drm_plane. Created a helper function to instantiate
> these properties and removed from drm_mode_create_standard_properties
> Added property documentation as suggested by Daniel, Vetter.
>
> v4: Rebase
>
> v5: Added "Display Color Hardware Pipeline" flow to kernel
> documentation as suggested by "Ville Syrjala" and "Brian Starkey".
> Moved the property creation to drm_color_mgmt.c file to consolidate
> all color operations at one place.
>
> Signed-off-by: Uma Shankar
> Reviewed-by: Alexandru Gheorghe
> ---
> Documentation/gpu/drm-kms.rst | 90
> +
> drivers/gpu/drm/drm_atomic.c| 13 ++
> drivers/gpu/drm/drm_atomic_helper.c | 6 +++
> drivers/gpu/drm/drm_color_mgmt.c| 44 --
> include/drm/drm_plane.h | 24 ++
> 5 files changed, 174 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/gpu/drm-kms.rst b/Documentation/gpu/drm-kms.rst
> index f8f5bf1..253d546 100644
> --- a/Documentation/gpu/drm-kms.rst
> +++ b/Documentation/gpu/drm-kms.rst
> @@ -551,12 +551,102 @@ Plane Composition Properties
> Color Management Properties
> ---
>
> +Below is how a typical hardware pipeline for color
> +will look like:
> +
> +.. kernel-render:: DOT
> + :alt: Display Color Pipeline
> + :caption: Display Color Pipeline Overview
> +
> + digraph "KMS" {
> + node [shape=box]
> +
> + subgraph cluster_static {
> + style=dashed
> + label="Display Color Hardware Blocks"
> +
> + node [bgcolor=grey style=filled]
> + "Plane Degamma A" -> "Plane CSC/CTM A"
> + "Plane CSC/CTM A" -> "Plane Gamma A"
> + "Pipe Blender" [color=lightblue,style=filled, width=5.25,
> height=0.75];
> + "Plane Gamma A" -> "Pipe Blender"
> + "Pipe Blender" -> "Pipe DeGamma"
> + "Pipe DeGamma" -> "Pipe CSC/CTM"
> + "Pipe CSC/CTM" -> "Pipe Gamma"
> + "Pipe Gamma" -> "Pipe Output"
> + }
> +
> + subgraph cluster_static {
> + style=dashed
> +
> + node [shape=box]
> + "Plane Degamma B" -> "Plane CSC/CTM B"
> + "Plane CSC/CTM B" -> "Plane Gamma B"
> + "Plane Gamma B" -> "Pipe Blender"
> + }
> +
> + subgraph cluster_static {
> + style=dashed
> +
> + node [shape=box]
> + "Plane Degamma C" -> "Plane CSC/CTM C"
> + "Plane CSC/CTM C" -> "Plane Gamma C"
> + "Plane Gamma C" -> "Pipe Blender"
> + }
> +
> + subgraph cluster_fb {
> + style=dashed
> + label="RAM"
> +
> + node [shape=box width=1.7 height=0.2]
> +
> + "FB 1" -> "Plane Degamma A"
> + "FB 2" -> "Plane Degamma B"
> + "FB 3" -> "Plane Degamma C"
> + }
> + }
> +
> +In real world usecases,
> +
> +1. Plane Degamma can be used to linearize a non linear gamma
> +encoded framebuffer. This is needed to do any linear math like
> +color space conversion. For ex, linearize frames encoded in SRGB
> +or by HDR curve.
> +
> +2. Later Plane CTM block can convert the content to some different
> +colorspace. For ex, SRGB to BT2020 etc.
> +
> +3. Plane Gamma block can be used later to re-apply the non-linear
> +curve. This can also be used to apply Tone Mapping for HDR usecases.
> +
> +All the layers or framebuffers need to be converted to same color
> +space and format before blending. The plane color hardware blocks
> +can help with this. Once the Data is blended, similar color processing
> +can be done on blended output using pipe color hardware blocks.
> +
> +DRM Properties have been created to define and expose all these
> +hardware blocks to userspace. A userspace application (compositor
> +or any color app) can use these interfaces and define policies to
> +efficiently use the display hardware for such color operations.
> +
> +Pipe Color Management Properties
> +-
> +
> .. kernel-doc:: drivers/gpu/drm/drm_color_mgmt.c
> :doc: overview
>
> .. kernel-doc:: drivers/gpu/drm/drm_color_mgmt.c
> :export:
>
> +Plane Color Management Properties
> +-
> +
> +.. kernel-doc:: drivers/gpu/drm/drm_color_mgmt.c
> + :doc: Plane Color Properties
> +
> +.. kernel-doc:: drivers/gpu/drm/drm_color_mgmt.c
> + :doc: export
> +
> Tile Group Property
> ---
>
> diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
> index d0478ab..e716614 100644
> --- a/drivers/gpu/drm/drm_atomic.c
> +++ b/drivers/gpu/drm/drm_atomic.c
> @@ -857,6 +857,8 @@ static int drm_atomic_plane_set_property(struct drm_plane
> *plane,
> {
> struct drm_device *dev = plane->dev;
> struct
[Intel-gfx] ✓ Fi.CI.BAT: success for CRTC background color (rev2)
== Series Details == Series: CRTC background color (rev2) URL : https://patchwork.freedesktop.org/series/50834/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5133 -> Patchwork_10819 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/50834/revisions/2/mbox/ == Known issues == Here are the changes found in Patchwork_10819 that come from known issues: === IGT changes === Issues hit igt@gem_ctx_create@basic-files: fi-bsw-n3050: PASS -> FAIL (fdo#108656) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-byt-clapper: PASS -> FAIL (fdo#107362, fdo#103191) Possible fixes igt@drv_selftest@live_hangcheck: fi-bwr-2160:DMESG-FAIL (fdo#108735) -> PASS igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: DMESG-WARN (fdo#102614) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-byt-clapper: FAIL (fdo#107362, fdo#103191) -> PASS fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#108656 https://bugs.freedesktop.org/show_bug.cgi?id=108656 fdo#108735 https://bugs.freedesktop.org/show_bug.cgi?id=108735 == Participating hosts (53 -> 44) == Missing(9): fi-kbl-soraka fi-ilk-m540 fi-icl-u fi-hsw-4200u fi-byt-squawks fi-icl-u2 fi-bsw-cyan fi-ctg-p8600 fi-blb-e6850 == Build changes == * Linux: CI_DRM_5133 -> Patchwork_10819 CI_DRM_5133: 5c71926a1834348a68951622a950de0355b73450 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4714: cab148ca3ec904a94d0cd43476cf7e1f8663f906 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10819: 470dfe72d6c81515372d60ce69beb8107a6724c6 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 470dfe72d6c8 drm/i915/gen9+: Add support for pipe background color (v2) a25e43dadb92 drm: Add CRTC background color property (v2) 99a0ae2cbae8 drm/i915: Force background color to black for gen9+ == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10819/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t v2] tests/kms_crtc_background_color: overhaul for latest ABI proposal (v2)
On Tue, Nov 13, 2018 at 11:43:12PM +, Lionel Landwerlin wrote: > On 13/11/2018 23:22, Matt Roper wrote: > > It's worth noting that we don't seem to be able to test this feature > > with CRC's. Originally we wanted to draw a color into a plane's FB > > (with Cairo) and then compare the CRC to turning off all planes and just > > setting the CRTC background to the same color. However the precision > > and rounding of the color components causes the CRC's to come out > > differently, even though the end result is visually identical. So at > > the moment this test is mainly useful for visual inspection in > > interactive mode. > Hey Matt, > Out of curiosity, are the CRCs different only when with 16bpc? Or with 8bpc > too? Both 8 and 16 give different CRC's. I suspect it's because cairo handles the color values (which get passed as double) slightly differently internally, although I haven't ruled out a slight inaccuracy on the hardware side. Given the alpha problems on gen9/gen10, it wouldn't surprise me if it turns out that our hardware is also treating a 10bpc component of 0x3ff as 0.999 rather than 1.0. Matt > > Thanks, > > - > Lionel > > > -- Matt Roper Graphics Software Engineer IoTG Platform Enabling & Development Intel Corporation (916) 356-2795 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t v2] tests/kms_crtc_background_color: overhaul for latest ABI proposal (v2)
On 13/11/2018 23:22, Matt Roper wrote: It's worth noting that we don't seem to be able to test this feature with CRC's. Originally we wanted to draw a color into a plane's FB (with Cairo) and then compare the CRC to turning off all planes and just setting the CRTC background to the same color. However the precision and rounding of the color components causes the CRC's to come out differently, even though the end result is visually identical. So at the moment this test is mainly useful for visual inspection in interactive mode. Hey Matt, Out of curiosity, are the CRCs different only when with 16bpc? Or with 8bpc too? Thanks, - Lionel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for CRTC background color (rev2)
== Series Details == Series: CRTC background color (rev2) URL : https://patchwork.freedesktop.org/series/50834/ State : warning == Summary == $ dim checkpatch origin/drm-tip 99a0ae2cbae8 drm/i915: Force background color to black for gen9+ a25e43dadb92 drm: Add CRTC background color property (v2) -:146: WARNING:BOOL_BITFIELD: Avoid using bool as bitfield. Prefer bool bitfields as unsigned int or u<8|16|32> #146: FILE: include/drm/drm_crtc.h:175: + bool bgcolor_changed : 1; -:214: CHECK:SPACING: spaces preferred around that '-' (ctx:VxV) #214: FILE: include/uapi/drm/drm_mode.h:912: +#define DRM_RGBA_BLUE(c, numbits) (__u16)((c & 0xull) >> (16-numbits)) ^ -:214: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'c' may be better as '(c)' to avoid precedence issues #214: FILE: include/uapi/drm/drm_mode.h:912: +#define DRM_RGBA_BLUE(c, numbits) (__u16)((c & 0xull) >> (16-numbits)) -:214: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'numbits' may be better as '(numbits)' to avoid precedence issues #214: FILE: include/uapi/drm/drm_mode.h:912: +#define DRM_RGBA_BLUE(c, numbits) (__u16)((c & 0xull) >> (16-numbits)) -:215: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #215: FILE: include/uapi/drm/drm_mode.h:913: +#define DRM_RGBA_GREEN(c, numbits) (__u16)((c & 0xull<<16) >> (32-numbits)) ^ -:215: CHECK:SPACING: spaces preferred around that '-' (ctx:VxV) #215: FILE: include/uapi/drm/drm_mode.h:913: +#define DRM_RGBA_GREEN(c, numbits) (__u16)((c & 0xull<<16) >> (32-numbits)) ^ -:215: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'c' may be better as '(c)' to avoid precedence issues #215: FILE: include/uapi/drm/drm_mode.h:913: +#define DRM_RGBA_GREEN(c, numbits) (__u16)((c & 0xull<<16) >> (32-numbits)) -:215: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'numbits' may be better as '(numbits)' to avoid precedence issues #215: FILE: include/uapi/drm/drm_mode.h:913: +#define DRM_RGBA_GREEN(c, numbits) (__u16)((c & 0xull<<16) >> (32-numbits)) -:216: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #216: FILE: include/uapi/drm/drm_mode.h:914: +#define DRM_RGBA_RED(c, numbits) (__u16)((c & 0xull<<32) >> (48-numbits)) ^ -:216: CHECK:SPACING: spaces preferred around that '-' (ctx:VxV) #216: FILE: include/uapi/drm/drm_mode.h:914: +#define DRM_RGBA_RED(c, numbits) (__u16)((c & 0xull<<32) >> (48-numbits)) ^ -:216: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'c' may be better as '(c)' to avoid precedence issues #216: FILE: include/uapi/drm/drm_mode.h:914: +#define DRM_RGBA_RED(c, numbits) (__u16)((c & 0xull<<32) >> (48-numbits)) -:216: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'numbits' may be better as '(numbits)' to avoid precedence issues #216: FILE: include/uapi/drm/drm_mode.h:914: +#define DRM_RGBA_RED(c, numbits) (__u16)((c & 0xull<<32) >> (48-numbits)) -:217: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #217: FILE: include/uapi/drm/drm_mode.h:915: +#define DRM_RGBA_ALPHA(c, numbits) (__u16)((c & 0xull<<48) >> (64-numbits)) ^ -:217: CHECK:SPACING: spaces preferred around that '-' (ctx:VxV) #217: FILE: include/uapi/drm/drm_mode.h:915: +#define DRM_RGBA_ALPHA(c, numbits) (__u16)((c & 0xull<<48) >> (64-numbits)) ^ -:217: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'c' may be better as '(c)' to avoid precedence issues #217: FILE: include/uapi/drm/drm_mode.h:915: +#define DRM_RGBA_ALPHA(c, numbits) (__u16)((c & 0xull<<48) >> (64-numbits)) -:217: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'numbits' may be better as '(numbits)' to avoid precedence issues #217: FILE: include/uapi/drm/drm_mode.h:915: +#define DRM_RGBA_ALPHA(c, numbits) (__u16)((c & 0xull<<48) >> (64-numbits)) total: 0 errors, 1 warnings, 15 checks, 143 lines checked 470dfe72d6c8 drm/i915/gen9+: Add support for pipe background color (v2) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t v2] tests/kms_crtc_background_color: overhaul for latest ABI proposal (v2)
CRTC background color kernel patches were written about 2.5 years ago
and floated on the upstream mailing list, but since no opensource
userspace materialized, we never actually merged them. However the
corresponding IGT test did get merged and has basically been dead code
ever since.
A couple years later we may finally be getting closer to landing the
kernel patches (there's some interest in this functionality now from
both the ChromeOS and Weston camps), so lets update the IGT test to
match the latest proposed ABI, and to remove some of the cruft from the
original test that wouldn't actually work.
It's worth noting that we don't seem to be able to test this feature
with CRC's. Originally we wanted to draw a color into a plane's FB
(with Cairo) and then compare the CRC to turning off all planes and just
setting the CRTC background to the same color. However the precision
and rounding of the color components causes the CRC's to come out
differently, even though the end result is visually identical. So at
the moment this test is mainly useful for visual inspection in
interactive mode.
v2:
- Swap red and blue ordering in property value to reflect change
in v2 of kernel series.
Cc: igt-...@lists.freedesktop.org
Signed-off-by: Matt Roper
---
lib/igt_kms.c | 2 +-
tests/kms_crtc_background_color.c | 221 --
2 files changed, 120 insertions(+), 103 deletions(-)
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index d806ccc1..33d6a6fb 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -180,7 +180,7 @@ const char * const
igt_plane_prop_names[IGT_NUM_PLANE_PROPS] = {
};
const char * const igt_crtc_prop_names[IGT_NUM_CRTC_PROPS] = {
- [IGT_CRTC_BACKGROUND] = "background_color",
+ [IGT_CRTC_BACKGROUND] = "BACKGROUND_COLOR",
[IGT_CRTC_CTM] = "CTM",
[IGT_CRTC_GAMMA_LUT] = "GAMMA_LUT",
[IGT_CRTC_GAMMA_LUT_SIZE] = "GAMMA_LUT_SIZE",
diff --git a/tests/kms_crtc_background_color.c
b/tests/kms_crtc_background_color.c
index 3df3401f..e990ecfa 100644
--- a/tests/kms_crtc_background_color.c
+++ b/tests/kms_crtc_background_color.c
@@ -25,164 +25,181 @@
#include "igt.h"
#include
-
IGT_TEST_DESCRIPTION("Test crtc background color feature");
+/*
+ * The original idea was to paint a desired color into a full-screen primary
+ * plane and then compare that CRC with turning off all planes and setting the
+ * CRTC background to the same color. Unforunately, the rounding and precision
+ * of color values as rendered by cairo vs created by the display controller
+ * are slightly different and give different CRC's, even though they're
+ * visually identical.
+ *
+ * Since we can't really use CRC's for testing, this test is mainly useful for
+ * visual inspection in interactive mode at the moment.
+ */
+
typedef struct {
int gfx_fd;
- igt_display_t display;
- struct igt_fb fb;
- igt_crc_t ref_crc;
- igt_pipe_crc_t *pipe_crc;
+ igt_output_t *output;
+ drmModeModeInfo *mode;
} data_t;
-#define BLACK 0x00 /* BGR 8bpc */
-#define CYAN 0x00 /* BGR 8bpc */
-#define PURPLE 0xFF00FF /* BGR 8bpc */
-#define WHITE 0xFF /* BGR 8bpc */
-
-#define BLACK640x /* BGR 16bpc */
-#define CYAN64 0x /* BGR 16bpc */
-#define PURPLE64 0x /* BGR 16bpc */
-#define YELLOW64 0x /* BGR 16bpc */
-#define WHITE640x /* BGR 16bpc */
-#define RED64 0x /* BGR 16bpc */
-#define GREEN640x /* BGR 16bpc */
-#define BLUE64 0x /* BGR 16bpc */
+/*
+ * Local copy of proposed kernel uapi
+ */
+static inline __u64
+local_rgba(__u8 bpc, __u16 red, __u16 green, __u16 blue, __u16 alpha)
+{
+ int msb_shift = 16 - bpc;
+ return (__u64)alpha << msb_shift << 48 |
+ (__u64)red << msb_shift << 32 |
+ (__u64)green << msb_shift << 16 |
+ (__u64)blue << msb_shift;
+}
+#define LOCAL_RGBA_BLUE(c, numbits) (__u16)((c & 0xull) >>
(16-numbits))
+#define LOCAL_RGBA_GREEN(c, numbits) (__u16)((c & 0xull<<16) >>
(32-numbits))
+#define LOCAL_RGBA_RED(c, numbits) (__u16)((c & 0xull<<32) >>
(48-numbits))
+#define LOCAL_RGBA_ALPHA(c, numbits) (__u16)((c & 0xull<<48) >>
(64-numbits))
+
+
+/* 8bpc values */
+#define BLACK local_rgba(8,0,0,0, 0xff)
+#define REDlocal_rgba(8, 0xff,0,0, 0xff)
+#define GREEN local_rgba(8,0, 0xff,0, 0xff)
+#define BLUE local_rgba(8,0,0, 0xff, 0xff)
+#define YELLOW local_rgba(8, 0xff, 0xff,0, 0xff)
+#define WHITE local_rgba(8, 0xff, 0xff, 0xff, 0xff)
+
+/* 16bpc values */
+#define BLACK64local_rgba(16, 0, 0, 0, 0x)
+#define RED64 local_rgba(16, 0x, 0, 0, 0x)
+#define GREEN64local_rgba(16,
[Intel-gfx] [PATCH v2 3/3] drm/i915/gen9+: Add support for pipe background color (v2)
Gen9+ platforms allow CRTC's to be programmed with a background/canvas
color below the programmable planes. Let's expose this for use by
compositors.
v2:
- Split out bgcolor sanitization and programming of csc/gamma bits to a
separate patch that we can land before the ABI changes are ready to
go in. (Ville)
- Change a temporary variable name to be more consistent with
other similar functions. (Ville)
- Change register name to SKL_CANVAS for consistency with the
CHV_CANVAS register.
Cc: dri-de...@lists.freedesktop.org
Cc: wei.c...@intel.com
Cc: harish.krupo@intel.com
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_debugfs.c | 9 +
drivers/gpu/drm/i915/intel_display.c | 35 ---
2 files changed, 37 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 670db5073d70..1f2a19e6ec79 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3254,6 +3254,15 @@ static int i915_display_info(struct seq_file *m, void
*unused)
intel_plane_info(m, crtc);
}
+ if (INTEL_GEN(dev_priv) >= 9 && pipe_config->base.active) {
+ uint64_t background = pipe_config->base.bgcolor;
+
+ seq_printf(m, "\tbackground color (10bpc): r=%x g=%x
b=%x\n",
+ DRM_RGBA_RED(background, 10),
+ DRM_RGBA_GREEN(background, 10),
+ DRM_RGBA_BLUE(background, 10));
+ }
+
seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
yesno(!crtc->cpu_fifo_underrun_disabled),
yesno(!crtc->pch_fifo_underrun_disabled));
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 1d089d93d88b..e7a759e0c021 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3834,6 +3834,27 @@ void intel_finish_reset(struct drm_i915_private
*dev_priv)
clear_bit(I915_RESET_MODESET, _priv->gpu_error.flags);
}
+static void skl_update_background_color(const struct intel_crtc_state *cstate)
+{
+ struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ uint64_t propval = cstate->base.bgcolor;
+ uint32_t tmp;
+
+ /* Hardware is programmed with 10 bits of precision */
+ tmp = DRM_RGBA_RED(propval, 10) << 20
+ | DRM_RGBA_GREEN(propval, 10) << 10
+ | DRM_RGBA_BLUE(propval, 10);
+
+ /*
+* Set CSC and gamma for bottom color to ensure background pixels
+* receive the same color transformations as plane content.
+*/
+ tmp |= SKL_CANVAS_CSC_ENABLE | SKL_CANVAS_GAMMA_ENABLE;
+
+ I915_WRITE_FW(SKL_CANVAS(crtc->pipe), tmp);
+}
+
static void intel_update_pipe_config(const struct intel_crtc_state
*old_crtc_state,
const struct intel_crtc_state
*new_crtc_state)
{
@@ -3869,14 +3890,8 @@ static void intel_update_pipe_config(const struct
intel_crtc_state *old_crtc_sta
ironlake_pfit_disable(old_crtc_state);
}
- /*
-* We don't (yet) allow userspace to control the pipe background color,
-* so force it to black, but apply pipe gamma and CSC so that its
-* handling will match how we program our planes.
-*/
if (INTEL_GEN(dev_priv) >= 9)
- I915_WRITE(SKL_CANVAS(crtc->pipe),
- SKL_CANVAS_GAMMA_ENABLE | SKL_CANVAS_CSC_ENABLE);
+ skl_update_background_color(new_crtc_state);
}
static void intel_fdi_normal_train(struct intel_crtc *crtc)
@@ -10896,6 +10911,9 @@ static int intel_crtc_atomic_check(struct drm_crtc
*crtc,
crtc_state->planes_changed = true;
}
+ if (crtc_state->bgcolor_changed)
+ pipe_config->update_pipe = true;
+
ret = 0;
if (dev_priv->display.compute_pipe_wm) {
ret = dev_priv->display.compute_pipe_wm(pipe_config);
@@ -14035,6 +14053,9 @@ static int intel_crtc_init(struct drm_i915_private
*dev_priv, enum pipe pipe)
WARN_ON(drm_crtc_index(_crtc->base) != intel_crtc->pipe);
+ if (INTEL_GEN(dev_priv) >= 9)
+ drm_crtc_add_bgcolor_property(_crtc->base);
+
return 0;
fail:
--
2.14.4
___
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Intel-gfx@lists.freedesktop.org
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[Intel-gfx] [PATCH v2 0/3] CRTC background color
This is a second revision of the series previously posted here: https://lists.freedesktop.org/archives/intel-gfx/2018-October/178202.html As noted before, this functionality adds new ABI so we need a userspace consumer ready before we merge the kernel work. My understanding is that some of the folks involved with ChromeOS are looking at this and that there's a ChromeOS userspace review happening at https://chromium-review.googlesource.com/c/chromium/src/+/1278858 Since there are a few Intel-specific background color changes that we want to make independently of the new ABI, I've separated those out into a new patch #1; we may want to consider landing that patch before the rest of the series since it fixes an inconsistency in how we currently program our hardware. On the i915-side of things, this series only deals with gen9+ at the moment. It looks like CHV may also have support for background color functionality, but I couldn't find the register layout details for that platform, so I haven't added support for it yet. Cc: dri-de...@lists.freedesktop.org Cc: Wei C Li Cc: Sean Paul Cc: Ville Syrjälä Matt Roper (3): drm/i915: Force background color to black for gen9+ drm: Add CRTC background color property (v2) drm/i915/gen9+: Add support for pipe background color (v2) drivers/gpu/drm/drm_atomic_state_helper.c | 1 + drivers/gpu/drm/drm_atomic_uapi.c | 5 drivers/gpu/drm/drm_blend.c | 21 ++--- drivers/gpu/drm/drm_mode_config.c | 6 + drivers/gpu/drm/i915/i915_debugfs.c | 9 +++ drivers/gpu/drm/i915/i915_reg.h | 6 + drivers/gpu/drm/i915/intel_display.c | 39 +++ include/drm/drm_blend.h | 1 + include/drm/drm_crtc.h| 17 ++ include/drm/drm_mode_config.h | 5 include/uapi/drm/drm_mode.h | 26 + 11 files changed, 133 insertions(+), 3 deletions(-) -- 2.14.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 2/3] drm: Add CRTC background color property (v2)
Some display controllers can be programmed to present non-black colors
for pixels not covered by any plane (or pixels covered by the
transparent regions of higher planes). Compositors that want a UI with
a solid color background can potentially save memory bandwidth by
setting the CRTC background property and using smaller planes to display
the rest of the content.
To avoid confusion between different ways of encoding RGB data, we
define a standard 64-bit format that should be used for this property's
value. Helper functions and macros are provided to generate and dissect
values in this standard format with varying component precision values.
v2:
- Swap internal representation's blue and red bits to make it easier
to read if printed out. (Ville)
- Document bgcolor property in drm_blend.c. (Sean Paul)
- s/background_color/bgcolor/ for consistency between property name and
value storage field. (Sean Paul)
- Add a convenience function to attach property to a given crtc.
Cc: dri-de...@lists.freedesktop.org
Cc: wei.c...@intel.com
Cc: harish.krupo@intel.com
Cc: Ville Syrjälä
Cc: Sean Paul
Signed-off-by: Matt Roper
---
drivers/gpu/drm/drm_atomic_state_helper.c | 1 +
drivers/gpu/drm/drm_atomic_uapi.c | 5 +
drivers/gpu/drm/drm_blend.c | 21 ++---
drivers/gpu/drm/drm_mode_config.c | 6 ++
include/drm/drm_blend.h | 1 +
include/drm/drm_crtc.h| 17 +
include/drm/drm_mode_config.h | 5 +
include/uapi/drm/drm_mode.h | 26 ++
8 files changed, 79 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c
b/drivers/gpu/drm/drm_atomic_state_helper.c
index 3ba996069d69..2f8c55668089 100644
--- a/drivers/gpu/drm/drm_atomic_state_helper.c
+++ b/drivers/gpu/drm/drm_atomic_state_helper.c
@@ -101,6 +101,7 @@ void __drm_atomic_helper_crtc_duplicate_state(struct
drm_crtc *crtc,
state->planes_changed = false;
state->connectors_changed = false;
state->color_mgmt_changed = false;
+ state->bgcolor_changed = false;
state->zpos_changed = false;
state->commit = NULL;
state->event = NULL;
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index 86ac33922b09..b95a55a778e2 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -467,6 +467,9 @@ static int drm_atomic_crtc_set_property(struct drm_crtc
*crtc,
return -EFAULT;
set_out_fence_for_crtc(state->state, crtc, fence_ptr);
+ } else if (property == config->bgcolor_property) {
+ state->bgcolor = val;
+ state->bgcolor_changed = true;
} else if (crtc->funcs->atomic_set_property) {
return crtc->funcs->atomic_set_property(crtc, state, property,
val);
} else {
@@ -499,6 +502,8 @@ drm_atomic_crtc_get_property(struct drm_crtc *crtc,
*val = (state->gamma_lut) ? state->gamma_lut->base.id : 0;
else if (property == config->prop_out_fence_ptr)
*val = 0;
+ else if (property == config->bgcolor_property)
+ *val = state->bgcolor;
else if (crtc->funcs->atomic_get_property)
return crtc->funcs->atomic_get_property(crtc, state, property,
val);
else
diff --git a/drivers/gpu/drm/drm_blend.c b/drivers/gpu/drm/drm_blend.c
index 0c78ca386cbe..7c73cb83874a 100644
--- a/drivers/gpu/drm/drm_blend.c
+++ b/drivers/gpu/drm/drm_blend.c
@@ -175,9 +175,16 @@
* plane does not expose the "alpha" property, then this is
* assumed to be 1.0
*
- * Note that all the property extensions described here apply either to the
- * plane or the CRTC (e.g. for the background color, which currently is not
- * exposed and assumed to be black).
+ * The property extensions described above all apply to the plane. Drivers
+ * may also expose the following crtc property extension:
+ *
+ * bgcolor:
+ * Background color is setup with drm_crtc_add_bgcolor_property(). It
+ * controls the RGB color of a full-screen, fully-opaque layer that exists
+ * below all planes. This color will be used for pixels not covered by
+ * any plane and may also be blended with plane contents as allowed by a
+ * plane's alpha values. The background color defaults to black, and is
+ * assumed to be black for drivers that do not expose this property.
*/
/**
@@ -593,3 +600,11 @@ int drm_plane_create_blend_mode_property(struct drm_plane
*plane,
return 0;
}
EXPORT_SYMBOL(drm_plane_create_blend_mode_property);
+
+void drm_crtc_add_bgcolor_property(struct drm_crtc *crtc)
+{
+ drm_object_attach_property(>base,
+ crtc->dev->mode_config.bgcolor_property,
+ drm_rgba(16, 0, 0, 0, 0x));
+}
[Intel-gfx] [PATCH v2 1/3] drm/i915: Force background color to black for gen9+
We don't yet allow userspace to control the CRTC background color, but
we should manually program the color to black to ensure the BIOS didn't
leave us with some other color. We should also set the pipe gamma and
pipe CSC bits so that the background color goes through the same color
management transformations that a plane with black pixels would.
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
---
We may want to land this patch before the rest of the series since it's
still valuable even without the new ABI the rest of the series adds.
drivers/gpu/drm/i915/i915_reg.h | 6 ++
drivers/gpu/drm/i915/intel_display.c | 18 ++
2 files changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fe4b913e46ac..b92a721c9bcb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5662,6 +5662,12 @@ enum {
#define PIPEMISC_DITHER_TYPE_SP (0 << 2)
#define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A)
+/* Skylake+ pipe bottom (background) color */
+#define _SKL_CANVAS_A 0x70034
+#define SKL_CANVAS_GAMMA_ENABLE (1 << 31)
+#define SKL_CANVAS_CSC_ENABLE(1 << 30)
+#define SKL_CANVAS(pipe) _MMIO_PIPE2(pipe, _SKL_CANVAS_A)
+
#define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE +
0x70028)
#define PIPEB_LINE_COMPARE_INT_EN(1 << 29)
#define PIPEB_HLINE_INT_EN (1 << 28)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 132e978227fb..1d089d93d88b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3868,6 +3868,15 @@ static void intel_update_pipe_config(const struct
intel_crtc_state *old_crtc_sta
else if (old_crtc_state->pch_pfit.enabled)
ironlake_pfit_disable(old_crtc_state);
}
+
+ /*
+* We don't (yet) allow userspace to control the pipe background color,
+* so force it to black, but apply pipe gamma and CSC so that its
+* handling will match how we program our planes.
+*/
+ if (INTEL_GEN(dev_priv) >= 9)
+ I915_WRITE(SKL_CANVAS(crtc->pipe),
+ SKL_CANVAS_GAMMA_ENABLE | SKL_CANVAS_CSC_ENABLE);
}
static void intel_fdi_normal_train(struct intel_crtc *crtc)
@@ -15356,6 +15365,15 @@ static void intel_sanitize_crtc(struct intel_crtc
*crtc,
plane->base.type != DRM_PLANE_TYPE_PRIMARY)
intel_plane_disable_noatomic(crtc, plane);
}
+
+ /*
+* Disable any background color set by the BIOS, but enable the
+* gamma and CSC to match how we program our planes.
+*/
+ if (INTEL_GEN(dev_priv) >= 9)
+ I915_WRITE(SKL_CANVAS(crtc->pipe),
+ SKL_CANVAS_GAMMA_ENABLE |
+ SKL_CANVAS_CSC_ENABLE);
}
/* Adjust the state of the output pipe according to whether we
--
2.14.4
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Re: [Intel-gfx] [RFC 6/7] drm/i915: Introduce subplatform concept
On Tue, 13 Nov 2018, Tvrtko Ursulin wrote:
> On 13/11/2018 11:40, Jani Nikula wrote:
>> On Mon, 12 Nov 2018, Tvrtko Ursulin wrote:
>>> From: Tvrtko Ursulin
>>>
>>> Introduce subplatform mask to eliminate throughout the code devid checking
>>> sprinkle, mostly courtesy of IS_*_UL[TX] macros.
>>>
>>> Subplatform mask initialization is done at runtime device info init.
>>
>> I kind of like the concept, and I like the centralization of devid
>> checks in one function, but I've always wanted to take this to one step
>> further: only specify device ids in i915_pciids.h, and *nowhere* else.
>>
>> It's perhaps too much duplication to create a device info for all these
>> variants, but I think it would be possible to make the subplatform info
>> table driven using macros defined in i915_pciids.h.
>
> It would be much nicer, but how would you do it? Perhaps my imagination
> is just strong enough today.
So here's an idea.
>
> Simply by splitting the id's into subplatform parts, for instance where
> we have today:
>
> #define INTEL_BDW_GT1_IDS(info) \
> INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
> INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
> INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \
> INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \
> INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
> INTEL_VGA_DEVICE(0x160D, info) /* GT1 Workstation */
>
> We'd split to:
>
> #define INTEL_BDW_GT1_ULT_IDS(info) \
> INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
> INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
>
> #define INTEL_BDW_GT1_ULX_IDS(info) \
> INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \
So far so good.
>
> #define INTEL_BDW_GT1_IDS(info) \
> INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \
> INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
> INTEL_VGA_DEVICE(0x160D, info) /* GT1 Workstation */
Now include INTEL_BDW_GT1_ULT_IDS(info) and INTEL_BDW_GT1_ULX_IDS(info)
to the above...
>
> Then in i915_pci.c, instead of:
>
> ...
> INTEL_BDW_GT1_IDS(_broadwell_gt1_info),
> ...
>
> We'd have:
>
> ...
> INTEL_BDW_GT1_ULT_IDS(_broadwell_gt1_info),
> INTEL_BDW_GT1_ULX_IDS(_broadwell_gt1_info),
> INTEL_BDW_GT1_IDS(_broadwell_gt1_info),
> ...
...so you don't need to make this change at all. But that's a minor
detail.
> And a separate table to map the id's to subplatform values.
>
> Hmm, but we would probably need to extrac the id's from the
> INTEL_BDW1_GT_IDS like macros so they can be used in this second site
> without the info parameter. Something like the trick for device info
> flags, but can it be made to generate a macro? I think not..
Are we shy of macro magic? Pfft.
#undef INTEL_VGA_DEVICE
#define INTEL_VGA_DEVICE(id, info) (id)
static const u32 bdw_ult_ids[] = {
INTEL_BDW_GT1_ULT_IDS(0),
};
static const u32 bdw_ulx_ids[] = {
INTEL_BDW_GT1_ULX_IDS(0),
};
#undef INTEL_VGA_DEVICE
Now you can add another mapping on top with pointers to similar arrays
as above and corresponding subplatform bits. Just need to order the code
to not clobber the real INTEL_VGA_DEVICE needs.
We don't need to split the ult/ulx tables by platform either if we only
care about the subplatform ult/ulx here, just need to remember add all
ult/ulx in corresponding arrays.
BR,
Jani.
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Re: [Intel-gfx] [PATCH v2] drm/i915/icl: reverse uninit order
On Tue, 13 Nov 2018, Lucas De Marchi wrote:
> On Tue, Nov 13, 2018 at 10:31:25PM +0200, Jani Nikula wrote:
>> On Tue, 13 Nov 2018, Lucas De Marchi wrote:
>> > Bspec 21257 says "DDIA PHY is the comp master, so it must
>> > not be un-initialized if other combo PHYs are in use". Here
>> > we are shutting down all phys, so it's not strictly required.
>> > However let's be consistent on deinitializing things in the
>> > reversed order we initialized them.
>> >
>> > v2: simplify protection for enum port being unsigned in future
>> >
>> > Signed-off-by: Lucas De Marchi
>> > ---
>> > drivers/gpu/drm/i915/intel_combo_phy.c | 6 +-
>> > 1 file changed, 5 insertions(+), 1 deletion(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/intel_combo_phy.c
>> > b/drivers/gpu/drm/i915/intel_combo_phy.c
>> > index 49f3a533860d..62939df048d7 100644
>> > --- a/drivers/gpu/drm/i915/intel_combo_phy.c
>> > +++ b/drivers/gpu/drm/i915/intel_combo_phy.c
>> > @@ -9,6 +9,10 @@
>> >for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
>> >for_each_if(intel_port_is_combophy(__dev_priv, __port))
>> >
>> > +#define for_each_combo_port_rev(__dev_priv, __port) \
>>
>> The list.h list macros use _reverse suffix for reverse traversal. I
>> think we can afford to spend the extra letters here too.
>
> I followed what we do on other for_each macro:
> for_each_power_well_rev
> for_each_power_domain_well_rev
>
> Should those be reverse as well?
I think so yes.
BR,
Jani.
>
> Lucas De Marchi
>
>>
>> BR,
>> Jani.
>>
>> > + for ((__port) = I915_MAX_PORTS; (__port)-- > PORT_A;) \
>> > + for_each_if(intel_port_is_combophy(__dev_priv, __port))
>> > +
>> > enum {
>> >PROCMON_0_85V_DOT_0,
>> >PROCMON_0_95V_DOT_0,
>> > @@ -232,7 +236,7 @@ void icl_combo_phys_uninit(struct drm_i915_private
>> > *dev_priv)
>> > {
>> >enum port port;
>> >
>> > - for_each_combo_port(dev_priv, port) {
>> > + for_each_combo_port_rev(dev_priv, port) {
>> >u32 val;
>> >
>> >if (!icl_combo_phy_verify_state(dev_priv, port))
>>
>> --
>> Jani Nikula, Intel Open Source Graphics Center
--
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Re: [Intel-gfx] [PATCH v2] drm/i915/icl: reverse uninit order
On Tue, Nov 13, 2018 at 10:31:25PM +0200, Jani Nikula wrote:
> On Tue, 13 Nov 2018, Lucas De Marchi wrote:
> > Bspec 21257 says "DDIA PHY is the comp master, so it must
> > not be un-initialized if other combo PHYs are in use". Here
> > we are shutting down all phys, so it's not strictly required.
> > However let's be consistent on deinitializing things in the
> > reversed order we initialized them.
> >
> > v2: simplify protection for enum port being unsigned in future
> >
> > Signed-off-by: Lucas De Marchi
> > ---
> > drivers/gpu/drm/i915/intel_combo_phy.c | 6 +-
> > 1 file changed, 5 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_combo_phy.c
> > b/drivers/gpu/drm/i915/intel_combo_phy.c
> > index 49f3a533860d..62939df048d7 100644
> > --- a/drivers/gpu/drm/i915/intel_combo_phy.c
> > +++ b/drivers/gpu/drm/i915/intel_combo_phy.c
> > @@ -9,6 +9,10 @@
> > for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
> > for_each_if(intel_port_is_combophy(__dev_priv, __port))
> >
> > +#define for_each_combo_port_rev(__dev_priv, __port) \
>
> The list.h list macros use _reverse suffix for reverse traversal. I
> think we can afford to spend the extra letters here too.
I followed what we do on other for_each macro:
for_each_power_well_rev
for_each_power_domain_well_rev
Should those be reverse as well?
Lucas De Marchi
>
> BR,
> Jani.
>
> > + for ((__port) = I915_MAX_PORTS; (__port)-- > PORT_A;) \
> > + for_each_if(intel_port_is_combophy(__dev_priv, __port))
> > +
> > enum {
> > PROCMON_0_85V_DOT_0,
> > PROCMON_0_95V_DOT_0,
> > @@ -232,7 +236,7 @@ void icl_combo_phys_uninit(struct drm_i915_private
> > *dev_priv)
> > {
> > enum port port;
> >
> > - for_each_combo_port(dev_priv, port) {
> > + for_each_combo_port_rev(dev_priv, port) {
> > u32 val;
> >
> > if (!icl_combo_phy_verify_state(dev_priv, port))
>
> --
> Jani Nikula, Intel Open Source Graphics Center
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Re: [Intel-gfx] [PATCH xf86-video-intel v8 2/2] sna: Added AYUV format support for textured and sprite video adapters.
Quoting Ville Syrjälä (2018-11-13 19:13:40)
> On Tue, Nov 13, 2018 at 06:49:38PM +, Chris Wilson wrote:
> > Quoting Stanislav Lisovskiy (2018-11-13 07:45:02)
> > > @@ -408,6 +424,9 @@ void sna_video_textured_setup(struct sna *sna,
> > > ScreenPtr screen)
> > > } else if (sna->kgem.gen < 040) {
> > > adaptor->nImages = ARRAY_SIZE(gen3_Images);
> > > adaptor->pImages = (XvImageRec *)gen3_Images;
> > > + } else if (sna->kgem.gen >= 0110) {
> > > + adaptor->nImages = ARRAY_SIZE(gen9_Images);
> > > + adaptor->pImages = (XvImageRec *)gen9_Images;
> > > } else {
> > > adaptor->nImages = ARRAY_SIZE(gen4_Images);
> > > adaptor->pImages = (XvImageRec *)gen4_Images;
> >
> > Grr. Aside from the minor nits, ok. Ville?
>
> Yeah. Seems good enough. For both
> Reviewed-by: Ville Syrjälä
Ta, thanks for the patches.
To gitlab.freedesktop.org:xorg/driver/xf86-video-intel.git
0932a6b3..746ab3bb master -> master
-Chris
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Re: [Intel-gfx] [PATCH v2] drm/i915/icl: reverse uninit order
On Tue, 13 Nov 2018, Lucas De Marchi wrote:
> Bspec 21257 says "DDIA PHY is the comp master, so it must
> not be un-initialized if other combo PHYs are in use". Here
> we are shutting down all phys, so it's not strictly required.
> However let's be consistent on deinitializing things in the
> reversed order we initialized them.
>
> v2: simplify protection for enum port being unsigned in future
>
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/intel_combo_phy.c | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_combo_phy.c
> b/drivers/gpu/drm/i915/intel_combo_phy.c
> index 49f3a533860d..62939df048d7 100644
> --- a/drivers/gpu/drm/i915/intel_combo_phy.c
> +++ b/drivers/gpu/drm/i915/intel_combo_phy.c
> @@ -9,6 +9,10 @@
> for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
> for_each_if(intel_port_is_combophy(__dev_priv, __port))
>
> +#define for_each_combo_port_rev(__dev_priv, __port) \
The list.h list macros use _reverse suffix for reverse traversal. I
think we can afford to spend the extra letters here too.
BR,
Jani.
> + for ((__port) = I915_MAX_PORTS; (__port)-- > PORT_A;) \
> + for_each_if(intel_port_is_combophy(__dev_priv, __port))
> +
> enum {
> PROCMON_0_85V_DOT_0,
> PROCMON_0_95V_DOT_0,
> @@ -232,7 +236,7 @@ void icl_combo_phys_uninit(struct drm_i915_private
> *dev_priv)
> {
> enum port port;
>
> - for_each_combo_port(dev_priv, port) {
> + for_each_combo_port_rev(dev_priv, port) {
> u32 val;
>
> if (!icl_combo_phy_verify_state(dev_priv, port))
--
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Re: [Intel-gfx] [PATCH 1/2] drm/edid: Add and export function to parse manufacturer id
On Thu, 08 Nov 2018, Daniel Vetter wrote:
> On Thu, Nov 08, 2018 at 08:42:52PM +, Souza, Jose wrote:
>> On Thu, 2018-11-08 at 09:31 +0100, Daniel Vetter wrote:
>> > On Wed, Nov 07, 2018 at 04:23:52PM -0800, José Roberto de Souza
>> > wrote:
>> > > This function will be helpful to drivers that wants to add its own
>> > > quirks to sinks.
>> >
>> > Why would you want to do that? The point of a shared edid parsing
>> > code is
>> > that we can share all these quirks ...
>> >
>> > For these kind of patches, always include the driver code that makes
>> > use
>> > of your new code too. That makes it much easier to answer these
>> > questions.
>>
>> This will be used to disable or enable with quirks PSR in some panels
>> that do not behave like eDP spec states.
>> As this would be specifc to i915, I guess is better keep the list only
>> in i915.
>>
>> What is your opinion about that?
>
> For anything dp, shouldn't we use the OUI instead? Or is that more garbage
> than the EDID serial?
The OUI isn't always present, but we can use it when it is. And we
already have DPCD quirk support for that in drm_dp_helper.c.
> And yes, psr quirking for i915 seems like a reasonable thing to do, using
> either approach. But definitely include the full picture, including i915
> patches, in your next round.
I think all of the quirk matching should be in drm core or helpers. For
most quirks, it's up to the drivers to actually do something with that
information anyway, so it'll still remain i915 specific.
BR,
Jani.
> -Daniel
>
>>
>> >
>> > Thanks, Daniel
>> >
>> >
>> > > Signed-off-by: José Roberto de Souza
>> > > ---
>> > > drivers/gpu/drm/drm_edid.c | 20
>> > > include/drm/drm_edid.h | 1 +
>> > > 2 files changed, 17 insertions(+), 4 deletions(-)
>> > >
>> > > diff --git a/drivers/gpu/drm/drm_edid.c
>> > > b/drivers/gpu/drm/drm_edid.c
>> > > index b506e3622b08..1a0ddf3d326b 100644
>> > > --- a/drivers/gpu/drm/drm_edid.c
>> > > +++ b/drivers/gpu/drm/drm_edid.c
>> > > @@ -1755,6 +1755,21 @@ EXPORT_SYMBOL(drm_edid_duplicate);
>> > >
>> > > /*** EDID parsing ***/
>> > >
>> > > +/**
>> > > + * drm_edid_manufacturer_parse - parse the EDID manufacturer id to
>> > > readable
>> > > + * characters and set into manufacturer parameter.
>> > > + * @edid: EDID to get the manufacturer
>> > > + * @manufacturer: the char buffer to store the id
>> > > + */
>> > > +void drm_edid_manufacturer_parse(const struct edid *edid, char
>> > > manufacturer[3])
>> > > +{
>> > > +manufacturer[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
>> > > +manufacturer[1] = (((edid->mfg_id[0] & 0x3) << 3) |
>> > > + ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
>> > > +manufacturer[2] = (edid->mfg_id[1] & 0x1f) + '@';
>> > > +}
>> > > +EXPORT_SYMBOL(drm_edid_manufacturer_parse);
>> > > +
>> > > /**
>> > > * edid_vendor - match a string against EDID's obfuscated vendor
>> > > field
>> > > * @edid: EDID to match
>> > > @@ -1766,10 +1781,7 @@ static bool edid_vendor(const struct edid
>> > > *edid, const char *vendor)
>> > > {
>> > > char edid_vendor[3];
>> > >
>> > > -edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
>> > > -edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
>> > > - ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
>> > > -edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
>> > > +drm_edid_manufacturer_parse(edid, edid_vendor);
>> > >
>> > > return !strncmp(edid_vendor, vendor, 3);
>> > > }
>> > > diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
>> > > index e3c404833115..e4f3f7f34d6a 100644
>> > > --- a/include/drm/drm_edid.h
>> > > +++ b/include/drm/drm_edid.h
>> > > @@ -466,6 +466,7 @@ struct edid *drm_get_edid_switcheroo(struct
>> > > drm_connector *connector,
>> > > struct i2c_adapter *adapter);
>> > > struct edid *drm_edid_duplicate(const struct edid *edid);
>> > > int drm_add_edid_modes(struct drm_connector *connector, struct
>> > > edid *edid);
>> > > +void drm_edid_manufacturer_parse(const struct edid *edid, char
>> > > manufacturer[3]);
>> > >
>> > > u8 drm_match_cea_mode(const struct drm_display_mode *to_match);
>> > > enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8
>> > > video_code);
>> > > --
>> > > 2.19.1
>> > >
>> > > ___
>> > > Intel-gfx mailing list
>> > > Intel-gfx@lists.freedesktop.org
>> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Graphics Center
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[Intel-gfx] ✓ Fi.CI.IGT: success for Fix the possible watermark miswriting for skl+
== Series Details == Series: Fix the possible watermark miswriting for skl+ URL : https://patchwork.freedesktop.org/series/52425/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5132_full -> Patchwork_10814_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_10814_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10814_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10814_full: === IGT changes === Warnings igt@kms_atomic_interruptible@universal-setplane-cursor: shard-snb: PASS -> SKIP +2 igt@perf_pmu@rc6: shard-kbl: PASS -> SKIP == Known issues == Here are the changes found in Patchwork_10814_full that come from known issues: === IGT changes === Issues hit igt@gem_softpin@noreloc-s3: shard-skl: PASS -> INCOMPLETE (fdo#104108, fdo#107773) igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c: shard-kbl: NOTRUN -> DMESG-WARN (fdo#107956) igt@kms_ccs@pipe-b-crc-sprite-planes-basic: shard-kbl: NOTRUN -> DMESG-WARN (fdo#103313) igt@kms_color@pipe-c-legacy-gamma: shard-apl: PASS -> FAIL (fdo#104782) igt@kms_cursor_crc@cursor-128x128-random: shard-apl: PASS -> FAIL (fdo#103232) igt@kms_flip@plain-flip-ts-check: shard-skl: PASS -> FAIL (fdo#100368) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff: shard-apl: PASS -> FAIL (fdo#103167) +1 igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-gtt: shard-glk: PASS -> FAIL (fdo#103167) igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max: shard-glk: NOTRUN -> FAIL (fdo#108145) igt@kms_plane_lowres@pipe-b-tiling-none: shard-kbl: NOTRUN -> DMESG-WARN (fdo#105345) igt@kms_properties@connector-properties-legacy: shard-kbl: PASS -> DMESG-WARN (fdo#105345, fdo#103313) igt@pm_rpm@gem-pread: shard-skl: PASS -> INCOMPLETE (fdo#107807) igt@pm_rpm@modeset-pc8-residency-stress: shard-skl: SKIP -> INCOMPLETE (fdo#107807) Possible fixes igt@drm_import_export@import-close-race-flink: shard-skl: TIMEOUT (fdo#108667) -> PASS igt@gem_exec_suspend@basic-s3: shard-glk: INCOMPLETE (k.org#198133, fdo#103359) -> PASS igt@gem_exec_whisper@normal: shard-skl: TIMEOUT (fdo#108592) -> PASS igt@gem_ppgtt@blt-vs-render-ctx0: shard-kbl: INCOMPLETE (fdo#106023, fdo#103665, fdo#106887) -> PASS igt@gem_tiled_blits@normal: shard-apl: INCOMPLETE (fdo#103927) -> PASS igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b: shard-skl: DMESG-WARN (fdo#107956) -> PASS igt@kms_cursor_crc@cursor-256x256-onscreen: shard-skl: FAIL (fdo#103232) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu: shard-apl: FAIL (fdo#103167) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt: shard-glk: FAIL (fdo#103167) -> PASS +1 igt@kms_plane@plane-position-covered-pipe-b-planes: shard-glk: FAIL (fdo#103166) -> PASS igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: shard-skl: FAIL (fdo#107815) -> PASS igt@kms_plane_multiple@atomic-pipe-b-tiling-y: shard-apl: FAIL (fdo#103166) -> PASS igt@kms_properties@plane-properties-atomic: shard-kbl: DMESG-WARN (fdo#105345, fdo#103313) -> PASS igt@kms_setmode@basic: shard-kbl: FAIL (fdo#99912) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232 fdo#103313 https://bugs.freedesktop.org/show_bug.cgi?id=103313 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108 fdo#104782 https://bugs.freedesktop.org/show_bug.cgi?id=104782 fdo#105345 https://bugs.freedesktop.org/show_bug.cgi?id=105345 fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023 fdo#106887 https://bugs.freedesktop.org/show_bug.cgi?id=106887 fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773 fdo#107807
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/icl: replace check for combo phy (rev2)
== Series Details == Series: series starting with [v2,1/2] drm/i915/icl: replace check for combo phy (rev2) URL : https://patchwork.freedesktop.org/series/52400/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5133 -> Patchwork_10818 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/52400/revisions/2/mbox/ == Known issues == Here are the changes found in Patchwork_10818 that come from known issues: === IGT changes === Issues hit igt@gem_ctx_create@basic-files: fi-bsw-kefka: PASS -> FAIL (fdo#108656) igt@kms_chamelium@common-hpd-after-suspend: fi-skl-6700k2: PASS -> WARN (fdo#108680) igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: PASS -> FAIL (fdo#103167) igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence: fi-ilk-650: PASS -> DMESG-WARN (fdo#106387) Possible fixes igt@drv_selftest@live_hangcheck: fi-bwr-2160:DMESG-FAIL (fdo#108735) -> PASS igt@gem_ctx_switch@basic-default: fi-icl-u2: DMESG-WARN (fdo#107724) -> PASS igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: DMESG-WARN (fdo#102614) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-byt-clapper: FAIL (fdo#107362, fdo#103191) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#106387 https://bugs.freedesktop.org/show_bug.cgi?id=106387 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#107724 https://bugs.freedesktop.org/show_bug.cgi?id=107724 fdo#108656 https://bugs.freedesktop.org/show_bug.cgi?id=108656 fdo#108680 https://bugs.freedesktop.org/show_bug.cgi?id=108680 fdo#108735 https://bugs.freedesktop.org/show_bug.cgi?id=108735 == Participating hosts (53 -> 46) == Missing(7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-icl-u == Build changes == * Linux: CI_DRM_5133 -> Patchwork_10818 CI_DRM_5133: 5c71926a1834348a68951622a950de0355b73450 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4714: cab148ca3ec904a94d0cd43476cf7e1f8663f906 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10818: bf6d9fe159515700d2b86b87fa10304924af75aa @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == bf6d9fe15951 drm/i915/icl: reverse uninit order cf571a614561 drm/i915/icl: replace check for combo phy == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10818/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH xf86-video-intel v8 2/2] sna: Added AYUV format support for textured and sprite video adapters.
On Tue, Nov 13, 2018 at 06:49:38PM +, Chris Wilson wrote:
> Quoting Stanislav Lisovskiy (2018-11-13 07:45:02)
> > @@ -408,6 +424,9 @@ void sna_video_textured_setup(struct sna *sna,
> > ScreenPtr screen)
> > } else if (sna->kgem.gen < 040) {
> > adaptor->nImages = ARRAY_SIZE(gen3_Images);
> > adaptor->pImages = (XvImageRec *)gen3_Images;
> > + } else if (sna->kgem.gen >= 0110) {
> > + adaptor->nImages = ARRAY_SIZE(gen9_Images);
> > + adaptor->pImages = (XvImageRec *)gen9_Images;
> > } else {
> > adaptor->nImages = ARRAY_SIZE(gen4_Images);
> > adaptor->pImages = (XvImageRec *)gen4_Images;
>
> Grr. Aside from the minor nits, ok. Ville?
Yeah. Seems good enough. For both
Reviewed-by: Ville Syrjälä
--
Ville Syrjälä
Intel
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/2] drm/i915/icl: replace check for combo phy (rev2)
== Series Details == Series: series starting with [v2,1/2] drm/i915/icl: replace check for combo phy (rev2) URL : https://patchwork.freedesktop.org/series/52400/ State : warning == Summary == $ dim checkpatch origin/drm-tip cf571a614561 drm/i915/icl: replace check for combo phy -:23: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__port' - possible side-effects? #23: FILE: drivers/gpu/drm/i915/intel_combo_phy.c:8: +#define for_each_combo_port(__dev_priv, __port) \ + for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \ + for_each_if(intel_port_is_combophy(__dev_priv, __port)) total: 0 errors, 0 warnings, 1 checks, 26 lines checked bf6d9fe15951 drm/i915/icl: reverse uninit order -:24: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__port' - possible side-effects? #24: FILE: drivers/gpu/drm/i915/intel_combo_phy.c:12: +#define for_each_combo_port_rev(__dev_priv, __port) \ + for ((__port) = I915_MAX_PORTS; (__port)-- > PORT_A;) \ + for_each_if(intel_port_is_combophy(__dev_priv, __port)) total: 0 errors, 0 warnings, 1 checks, 18 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915/icl: reverse uninit order
Bspec 21257 says "DDIA PHY is the comp master, so it must
not be un-initialized if other combo PHYs are in use". Here
we are shutting down all phys, so it's not strictly required.
However let's be consistent on deinitializing things in the
reversed order we initialized them.
v2: simplify protection for enum port being unsigned in future
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_combo_phy.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_combo_phy.c
b/drivers/gpu/drm/i915/intel_combo_phy.c
index 49f3a533860d..62939df048d7 100644
--- a/drivers/gpu/drm/i915/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/intel_combo_phy.c
@@ -9,6 +9,10 @@
for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
for_each_if(intel_port_is_combophy(__dev_priv, __port))
+#define for_each_combo_port_rev(__dev_priv, __port) \
+ for ((__port) = I915_MAX_PORTS; (__port)-- > PORT_A;) \
+ for_each_if(intel_port_is_combophy(__dev_priv, __port))
+
enum {
PROCMON_0_85V_DOT_0,
PROCMON_0_95V_DOT_0,
@@ -232,7 +236,7 @@ void icl_combo_phys_uninit(struct drm_i915_private
*dev_priv)
{
enum port port;
- for_each_combo_port(dev_priv, port) {
+ for_each_combo_port_rev(dev_priv, port) {
u32 val;
if (!icl_combo_phy_verify_state(dev_priv, port))
--
2.19.1.1.g56c4683e68
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[Intel-gfx] ✓ Fi.CI.IGT: success for Fix the possible watermark miswriting
== Series Details == Series: Fix the possible watermark miswriting URL : https://patchwork.freedesktop.org/series/52423/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5132_full -> Patchwork_10813_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_10813_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10813_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10813_full: === IGT changes === Warnings igt@perf_pmu@rc6: shard-kbl: PASS -> SKIP igt@tools_test@tools_test: shard-apl: PASS -> SKIP == Known issues == Here are the changes found in Patchwork_10813_full that come from known issues: === IGT changes === Issues hit igt@kms_ccs@pipe-b-crc-sprite-planes-basic: shard-glk: PASS -> FAIL (fdo#108145) igt@kms_color@pipe-c-legacy-gamma: shard-apl: PASS -> FAIL (fdo#104782) igt@kms_cursor_crc@cursor-128x128-random: shard-apl: PASS -> FAIL (fdo#103232) +1 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen: shard-glk: PASS -> FAIL (fdo#103167) +1 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff: shard-apl: PASS -> FAIL (fdo#103167) +2 igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: shard-skl: PASS -> FAIL (fdo#107815) igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max: shard-glk: NOTRUN -> FAIL (fdo#108145) igt@kms_plane_multiple@atomic-pipe-c-tiling-y: shard-glk: PASS -> FAIL (fdo#103166) igt@kms_vblank@pipe-b-ts-continuation-suspend: shard-skl: PASS -> INCOMPLETE (fdo#104108, fdo#107773) igt@perf@polling: shard-hsw: PASS -> FAIL (fdo#102252) igt@perf_pmu@busy-start-vcs0: shard-apl: PASS -> DMESG-WARN (fdo#105602, fdo#103558) +1 igt@pm_rpm@pc8-residency: shard-skl: SKIP -> INCOMPLETE (fdo#107807) +1 igt@pm_rpm@universal-planes-dpms: shard-skl: PASS -> INCOMPLETE (fdo#107807) Possible fixes igt@drv_suspend@shrink: shard-skl: INCOMPLETE (fdo#106886) -> PASS igt@gem_exec_suspend@basic-s3: shard-glk: INCOMPLETE (fdo#103359, k.org#198133) -> PASS igt@gem_exec_whisper@normal: shard-skl: TIMEOUT (fdo#108592) -> PASS igt@gem_tiled_blits@normal: shard-apl: INCOMPLETE (fdo#103927) -> PASS igt@kms_color@pipe-a-ctm-0-75: shard-skl: FAIL (fdo#108682) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite: shard-apl: FAIL (fdo#103167) -> PASS +1 igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff: shard-glk: FAIL (fdo#103167) -> PASS +2 igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: shard-skl: INCOMPLETE (fdo#104108, fdo#107773) -> PASS igt@kms_plane_multiple@atomic-pipe-b-tiling-y: shard-apl: FAIL (fdo#103166) -> PASS igt@kms_properties@plane-properties-atomic: shard-kbl: DMESG-WARN (fdo#103313, fdo#105345) -> PASS igt@kms_setmode@basic: shard-hsw: FAIL (fdo#99912) -> PASS shard-kbl: FAIL (fdo#99912) -> PASS fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232 fdo#103313 https://bugs.freedesktop.org/show_bug.cgi?id=103313 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108 fdo#104782 https://bugs.freedesktop.org/show_bug.cgi?id=104782 fdo#105345 https://bugs.freedesktop.org/show_bug.cgi?id=105345 fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602 fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886 fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773 fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807 fdo#107815 https://bugs.freedesktop.org/show_bug.cgi?id=107815 fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145 fdo#108592 https://bugs.freedesktop.org/show_bug.cgi?id=108592 fdo#108682 https://bugs.freedesktop.org/show_bug.cgi?id=108682 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 k.org#198133
Re: [Intel-gfx] [PATCH xf86-video-intel v8 2/2] sna: Added AYUV format support for textured and sprite video adapters.
Quoting Stanislav Lisovskiy (2018-11-13 07:45:02)
> @@ -408,6 +424,9 @@ void sna_video_textured_setup(struct sna *sna, ScreenPtr
> screen)
> } else if (sna->kgem.gen < 040) {
> adaptor->nImages = ARRAY_SIZE(gen3_Images);
> adaptor->pImages = (XvImageRec *)gen3_Images;
> + } else if (sna->kgem.gen >= 0110) {
> + adaptor->nImages = ARRAY_SIZE(gen9_Images);
> + adaptor->pImages = (XvImageRec *)gen9_Images;
> } else {
> adaptor->nImages = ARRAY_SIZE(gen4_Images);
> adaptor->pImages = (XvImageRec *)gen4_Images;
Grr. Aside from the minor nits, ok. Ville?
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Disable LP3 watermarks on all SNB machines
== Series Details == Series: drm/i915: Disable LP3 watermarks on all SNB machines URL : https://patchwork.freedesktop.org/series/52440/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5133 -> Patchwork_10817 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/52440/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10817 that come from known issues: === IGT changes === Issues hit igt@gem_exec_suspend@basic-s3: fi-icl-u2: PASS -> DMESG-WARN (fdo#107724) igt@gem_exec_suspend@basic-s4-devices: fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718) igt@kms_frontbuffer_tracking@basic: fi-icl-u2: PASS -> FAIL (fdo#103167) Possible fixes igt@drv_selftest@live_hangcheck: fi-bwr-2160:DMESG-FAIL (fdo#108735) -> PASS igt@gem_ctx_switch@basic-default: fi-icl-u2: DMESG-WARN (fdo#107724) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-byt-clapper: FAIL (fdo#103191, fdo#107362) -> PASS fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#107724 https://bugs.freedesktop.org/show_bug.cgi?id=107724 fdo#108735 https://bugs.freedesktop.org/show_bug.cgi?id=108735 == Participating hosts (53 -> 47) == Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 == Build changes == * Linux: CI_DRM_5133 -> Patchwork_10817 CI_DRM_5133: 5c71926a1834348a68951622a950de0355b73450 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4714: cab148ca3ec904a94d0cd43476cf7e1f8663f906 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10817: 1192a5586c45b581271fffcf310ba2904b108f31 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 1192a5586c45 drm/i915: Disable LP3 watermarks on all SNB machines == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10817/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Disable LP3 watermarks on all SNB machines
On Tue, Nov 13, 2018 at 06:25:47PM +, Chris Wilson wrote:
> Quoting Ville Syrjala (2018-11-13 18:10:23)
> > From: Ville Syrjälä
> >
> > I have a Thinkpad X220 Tablet in my hands that is losing vblank
> > interrupts whenever LP3 watermarks are used.
> >
> > If I nudge the latency value written to the WM3 register just
> > by one in either direction the problem disappears. That to me
> > suggests that the punit will not enter the corrsponding
> > powersave mode (MPLL shutdown IIRC) unless the latency value
> > in the register matches exactly what we read from SSKPD. Ie.
> > it's not really a latency value but rather just a cookie
> > by which the punit can identify the desired power saving state.
> > On HSW/BDW this was changed such that we actually just write
> > the WM level number into those bits, which makes much more
> > sense given the observed behaviour.
> >
> > We could try to handle this by disallowing LP3 watermarks
> > only when vblank interrupts are enabled but we'd first have
> > to prove that only vblank interrupts are affected, which
> > seems unlikely. Also we can't grab the wm mutex from the
> > vblank enable/disable hooks because those are called with
> > various spinlocks held. Thus we'd have to redesigne the
> > watermark locking. So to play it safe and keep the code
> > simple we simply disable LP3 watermarks on all SNB machines.
> >
> > To do that we simply zero out the latency values for
> > watermark level 3, and we adjust the watermark computation
> > to check for that. The behaviour now matches that of the
> > g4x/vlv/skl wm code in the presence of a zeroed latency
> > value.
> >
> > Cc: sta...@vger.kernel.org
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101269
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103713
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 41 -
> > 1 file changed, 40 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index 27498ded4949..ef1ae2ede379 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -2493,6 +2493,9 @@ static uint32_t ilk_compute_pri_wm(const struct
> > intel_crtc_state *cstate,
> > uint32_t method1, method2;
> > int cpp;
> >
> > + if (mem_value == 0)
> > + return USHRT_MAX;
> > +
> > if (!intel_wm_plane_visible(cstate, pstate))
> > return 0;
> >
> > @@ -2522,6 +2525,9 @@ static uint32_t ilk_compute_spr_wm(const struct
> > intel_crtc_state *cstate,
> > uint32_t method1, method2;
> > int cpp;
> >
> > + if (mem_value == 0)
> > + return USHRT_MAX;
> > +
> > if (!intel_wm_plane_visible(cstate, pstate))
> > return 0;
> >
> > @@ -2545,6 +2551,9 @@ static uint32_t ilk_compute_cur_wm(const struct
> > intel_crtc_state *cstate,
> > {
> > int cpp;
> >
> > + if (mem_value == 0)
> > + return USHRT_MAX;
> > +
> > if (!intel_wm_plane_visible(cstate, pstate))
> > return 0;
> >
> > @@ -3008,6 +3017,34 @@ static void snb_wm_latency_quirk(struct
> > drm_i915_private *dev_priv)
> > intel_print_wm_latency(dev_priv, "Cursor",
> > dev_priv->wm.cur_latency);
> > }
> >
> > +static void snb_wm_lp3_irq_quirk(struct drm_i915_private *dev_priv)
> > +{
> > + /*
> > +* On some SNB machines (Thinkpad X220 Tablet at least)
> > +* LP3 usage can cause vblank interrupts to be lost.
> > +* The DEIIR bit will go high but it looks like the CPU
> > +* never gets interrupted.
> > +*
> > +* It's not clear whether other interrupt source could
> > +* be affected or if this is somehow limited to vblank
> > +* interrupts only. To play it safe we disable LP3
> > +* watermarks entirely.
> > +*/
> > + if (dev_priv->wm.pri_latency[3] == 0 &&
> > + dev_priv->wm.spr_latency[3] == 0 &&
> > + dev_priv->wm.cur_latency[3] == 0)
> > + return;
> > +
> > + dev_priv->wm.pri_latency[3] = 0;
> > + dev_priv->wm.spr_latency[3] = 0;
> > + dev_priv->wm.cur_latency[3] = 0;
>
> -> return USHRT_MAX for pri/spr/cur planes.
> -> result->enable = false;
>
> Only question then why USHRT_MAX for a u32 parameter? Seems to be copied
> from gm45 where it is a u16 parameter instead.
A good question. My excuse is that I was expecting it to be a u16.
The max value the registers can hold is 11 bits, so u16 would be
more than enough for our needs.
Looks like we store these as u32 in the struct as well so we end
up wasting a bit of memory. I'll go write a patch to shrink it
a bit.
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH] drm/i915: Disable LP3 watermarks on all SNB machines
Quoting Ville Syrjala (2018-11-13 18:10:23)
> From: Ville Syrjälä
>
> I have a Thinkpad X220 Tablet in my hands that is losing vblank
> interrupts whenever LP3 watermarks are used.
>
> If I nudge the latency value written to the WM3 register just
> by one in either direction the problem disappears. That to me
> suggests that the punit will not enter the corrsponding
> powersave mode (MPLL shutdown IIRC) unless the latency value
> in the register matches exactly what we read from SSKPD. Ie.
> it's not really a latency value but rather just a cookie
> by which the punit can identify the desired power saving state.
> On HSW/BDW this was changed such that we actually just write
> the WM level number into those bits, which makes much more
> sense given the observed behaviour.
>
> We could try to handle this by disallowing LP3 watermarks
> only when vblank interrupts are enabled but we'd first have
> to prove that only vblank interrupts are affected, which
> seems unlikely. Also we can't grab the wm mutex from the
> vblank enable/disable hooks because those are called with
> various spinlocks held. Thus we'd have to redesigne the
> watermark locking. So to play it safe and keep the code
> simple we simply disable LP3 watermarks on all SNB machines.
>
> To do that we simply zero out the latency values for
> watermark level 3, and we adjust the watermark computation
> to check for that. The behaviour now matches that of the
> g4x/vlv/skl wm code in the presence of a zeroed latency
> value.
>
> Cc: sta...@vger.kernel.org
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101269
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103713
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_pm.c | 41 -
> 1 file changed, 40 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 27498ded4949..ef1ae2ede379 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2493,6 +2493,9 @@ static uint32_t ilk_compute_pri_wm(const struct
> intel_crtc_state *cstate,
> uint32_t method1, method2;
> int cpp;
>
> + if (mem_value == 0)
> + return USHRT_MAX;
> +
> if (!intel_wm_plane_visible(cstate, pstate))
> return 0;
>
> @@ -2522,6 +2525,9 @@ static uint32_t ilk_compute_spr_wm(const struct
> intel_crtc_state *cstate,
> uint32_t method1, method2;
> int cpp;
>
> + if (mem_value == 0)
> + return USHRT_MAX;
> +
> if (!intel_wm_plane_visible(cstate, pstate))
> return 0;
>
> @@ -2545,6 +2551,9 @@ static uint32_t ilk_compute_cur_wm(const struct
> intel_crtc_state *cstate,
> {
> int cpp;
>
> + if (mem_value == 0)
> + return USHRT_MAX;
> +
> if (!intel_wm_plane_visible(cstate, pstate))
> return 0;
>
> @@ -3008,6 +3017,34 @@ static void snb_wm_latency_quirk(struct
> drm_i915_private *dev_priv)
> intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
> }
>
> +static void snb_wm_lp3_irq_quirk(struct drm_i915_private *dev_priv)
> +{
> + /*
> +* On some SNB machines (Thinkpad X220 Tablet at least)
> +* LP3 usage can cause vblank interrupts to be lost.
> +* The DEIIR bit will go high but it looks like the CPU
> +* never gets interrupted.
> +*
> +* It's not clear whether other interrupt source could
> +* be affected or if this is somehow limited to vblank
> +* interrupts only. To play it safe we disable LP3
> +* watermarks entirely.
> +*/
> + if (dev_priv->wm.pri_latency[3] == 0 &&
> + dev_priv->wm.spr_latency[3] == 0 &&
> + dev_priv->wm.cur_latency[3] == 0)
> + return;
> +
> + dev_priv->wm.pri_latency[3] = 0;
> + dev_priv->wm.spr_latency[3] = 0;
> + dev_priv->wm.cur_latency[3] = 0;
-> return USHRT_MAX for pri/spr/cur planes.
-> result->enable = false;
Only question then why USHRT_MAX for a u32 parameter? Seems to be copied
from gm45 where it is a u16 parameter instead.
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Use explicit old crtc state in skl_compute_wm()
== Series Details == Series: series starting with [1/3] drm/i915: Use explicit old crtc state in skl_compute_wm() URL : https://patchwork.freedesktop.org/series/52436/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5133 -> Patchwork_10816 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/52436/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10816 that come from known issues: === IGT changes === Issues hit igt@gem_exec_suspend@basic-s4-devices: fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718) igt@kms_busy@basic-flip-b: fi-hsw-peppy: PASS -> FAIL (fdo#103182) igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: fi-byt-clapper: PASS -> FAIL (fdo#107362, fdo#103191) Possible fixes igt@drv_selftest@live_hangcheck: fi-bwr-2160:DMESG-FAIL (fdo#108735) -> PASS igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: DMESG-WARN (fdo#102614) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-byt-clapper: FAIL (fdo#107362, fdo#103191) -> PASS fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103182 https://bugs.freedesktop.org/show_bug.cgi?id=103182 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#108735 https://bugs.freedesktop.org/show_bug.cgi?id=108735 == Participating hosts (53 -> 45) == Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-icl-u2 fi-bsw-cyan fi-ctg-p8600 fi-icl-u == Build changes == * Linux: CI_DRM_5133 -> Patchwork_10816 CI_DRM_5133: 5c71926a1834348a68951622a950de0355b73450 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4714: cab148ca3ec904a94d0cd43476cf7e1f8663f906 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10816: 5aa5c7a34c312bb224f5f22c140ff5d113fb089e @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 5aa5c7a34c31 drm/i915: Remove dead update_wm_pre assignment from SKL wm code 57ff2d377da8 drm/i915: Remove bogus FIXME from SKL wm computation 5c01f5293e5b drm/i915: Use explicit old crtc state in skl_compute_wm() == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10816/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Disable LP3 watermarks on all SNB machines
From: Ville Syrjälä
I have a Thinkpad X220 Tablet in my hands that is losing vblank
interrupts whenever LP3 watermarks are used.
If I nudge the latency value written to the WM3 register just
by one in either direction the problem disappears. That to me
suggests that the punit will not enter the corrsponding
powersave mode (MPLL shutdown IIRC) unless the latency value
in the register matches exactly what we read from SSKPD. Ie.
it's not really a latency value but rather just a cookie
by which the punit can identify the desired power saving state.
On HSW/BDW this was changed such that we actually just write
the WM level number into those bits, which makes much more
sense given the observed behaviour.
We could try to handle this by disallowing LP3 watermarks
only when vblank interrupts are enabled but we'd first have
to prove that only vblank interrupts are affected, which
seems unlikely. Also we can't grab the wm mutex from the
vblank enable/disable hooks because those are called with
various spinlocks held. Thus we'd have to redesigne the
watermark locking. So to play it safe and keep the code
simple we simply disable LP3 watermarks on all SNB machines.
To do that we simply zero out the latency values for
watermark level 3, and we adjust the watermark computation
to check for that. The behaviour now matches that of the
g4x/vlv/skl wm code in the presence of a zeroed latency
value.
Cc: sta...@vger.kernel.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101269
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103713
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 41 -
1 file changed, 40 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 27498ded4949..ef1ae2ede379 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2493,6 +2493,9 @@ static uint32_t ilk_compute_pri_wm(const struct
intel_crtc_state *cstate,
uint32_t method1, method2;
int cpp;
+ if (mem_value == 0)
+ return USHRT_MAX;
+
if (!intel_wm_plane_visible(cstate, pstate))
return 0;
@@ -2522,6 +2525,9 @@ static uint32_t ilk_compute_spr_wm(const struct
intel_crtc_state *cstate,
uint32_t method1, method2;
int cpp;
+ if (mem_value == 0)
+ return USHRT_MAX;
+
if (!intel_wm_plane_visible(cstate, pstate))
return 0;
@@ -2545,6 +2551,9 @@ static uint32_t ilk_compute_cur_wm(const struct
intel_crtc_state *cstate,
{
int cpp;
+ if (mem_value == 0)
+ return USHRT_MAX;
+
if (!intel_wm_plane_visible(cstate, pstate))
return 0;
@@ -3008,6 +3017,34 @@ static void snb_wm_latency_quirk(struct drm_i915_private
*dev_priv)
intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
}
+static void snb_wm_lp3_irq_quirk(struct drm_i915_private *dev_priv)
+{
+ /*
+* On some SNB machines (Thinkpad X220 Tablet at least)
+* LP3 usage can cause vblank interrupts to be lost.
+* The DEIIR bit will go high but it looks like the CPU
+* never gets interrupted.
+*
+* It's not clear whether other interrupt source could
+* be affected or if this is somehow limited to vblank
+* interrupts only. To play it safe we disable LP3
+* watermarks entirely.
+*/
+ if (dev_priv->wm.pri_latency[3] == 0 &&
+ dev_priv->wm.spr_latency[3] == 0 &&
+ dev_priv->wm.cur_latency[3] == 0)
+ return;
+
+ dev_priv->wm.pri_latency[3] = 0;
+ dev_priv->wm.spr_latency[3] = 0;
+ dev_priv->wm.cur_latency[3] = 0;
+
+ DRM_DEBUG_KMS("LP3 watermarks disabled due to potential for lost
interrupts\n");
+ intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
+ intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
+ intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
+}
+
static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
{
intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
@@ -3024,8 +3061,10 @@ static void ilk_setup_wm_latency(struct drm_i915_private
*dev_priv)
intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
- if (IS_GEN6(dev_priv))
+ if (IS_GEN6(dev_priv)) {
snb_wm_latency_quirk(dev_priv);
+ snb_wm_lp3_irq_quirk(dev_priv);
+ }
}
static void skl_setup_wm_latency(struct drm_i915_private *dev_priv)
--
2.18.1
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Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/icl: reverse uninit order
On Tue, Nov 13, 2018 at 03:23:07PM +0200, Imre Deak wrote:
> On Tue, Nov 13, 2018 at 03:19:06PM +0200, Imre Deak wrote:
> > On Mon, Nov 12, 2018 at 06:45:03PM -0800, Lucas De Marchi wrote:
> > > Bspec 21257 says "DDIA PHY is the comp master, so it must
> > > not be un-initialized if other combo PHYs are in use". Here
> > > we are shutting down all phys, so it's not strictly required.
> > > However let's be consistent on deinitializing things in the
> > > reversed order we initialized them.
> > >
> > > Signed-off-by: Lucas De Marchi
> > > ---
> > > drivers/gpu/drm/i915/intel_combo_phy.c | 8 +++-
> > > 1 file changed, 7 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_combo_phy.c
> > > b/drivers/gpu/drm/i915/intel_combo_phy.c
> > > index 49f3a533860d..9c06be45b84e 100644
> > > --- a/drivers/gpu/drm/i915/intel_combo_phy.c
> > > +++ b/drivers/gpu/drm/i915/intel_combo_phy.c
> > > @@ -9,6 +9,12 @@
> > > for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
> > > for_each_if(intel_port_is_combophy(__dev_priv, __port))
> > >
> > > +#define for_each_combo_port_rev(__dev_priv, __port) \
> > > + for ((__port) = I915_MAX_PORTS - 1; \
> > > + (__port) >= PORT_A && (__port) < I915_MAX_PORTS; \
> > > + (__port)--) \
> >
> > Heh, so 'enum port' is unsigned. Surely I would have get this right
> > only after seeing it fail with only the >= condition :) An
> > alternative:
> >
> > for ((__port) = I915_MAX_PORTS; (__port)-- > 0;)
> >
> > or add a negative value, like INVALID_PORT=-1 to 'enum port', but we'd
>
> Hm, actually we do have PORT_NONE=-1, in which case 'enum port' is a
> signed int. So why do we need (__port) < I915_MAX_PORTS ?
We don't actually *need*. I only thought the fact that the type is not explicit
but rather depends on the enum value, it would be to fragile and it would start
to fail silently if we ever change that. I like the alternative you gave since
it's
shorter and works on both cases.
thanks
Lucas De Marchi
>
> > need some user for that too. Either way:
> >
> > Reviewed-by: Imre Deak
> >
> > > + for_each_if(intel_port_is_combophy(__dev_priv, __port))
> > > +
> > > enum {
> > > PROCMON_0_85V_DOT_0,
> > > PROCMON_0_95V_DOT_0,
> > > @@ -232,7 +238,7 @@ void icl_combo_phys_uninit(struct drm_i915_private
> > > *dev_priv)
> > > {
> > > enum port port;
> > >
> > > - for_each_combo_port(dev_priv, port) {
> > > + for_each_combo_port_rev(dev_priv, port) {
> > > u32 val;
> > >
> > > if (!icl_combo_phy_verify_state(dev_priv, port))
> > > --
> > > 2.19.1.1.g56c4683e68
> > >
> > ___
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> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [RFC 4/7] drm/i915: Remove mkwrite_device_info
Quoting Tvrtko Ursulin (2018-11-13 17:33:38) > > On 13/11/2018 11:51, Chris Wilson wrote: > > Quoting Jani Nikula (2018-11-13 11:45:02) > >> On Mon, 12 Nov 2018, Tvrtko Ursulin wrote: > >>> From: Tvrtko Ursulin > >>> > >>> Now that we are down to one caller, which does not even modify copied > >>> device info, we can remove the mkwrite_device_info helper and convert the > >>> device info pointer itself to be a pointer to static table instead of a > >>> copy. > >>> > >>> Only unfortnate thing is that we need to convert all callsites which were > >>> referencing the device info directly to using the INTEL_INFO helper. > >> > >> I'm not sure if that's all that bad. When I was toying around with > >> mkwrite_device_info removal, I actually started off with changing all > >> device info references to INTEL_INFO. It's a big patch, but it nicely > >> centralizes many of the other changes instead of splattering all over > >> the place. > > > > Fwiw, replacing all the static i915->info accesses with INTEL_INFO (or > > DEVICE_INFO since STATIC_INFO I think is too confusing with C, and > > INTEL_INFO is not distinct enough from RUNTIME_INFO) is perhaps a > > You propose DEVICE_INFO for the static part and RUNTIME_INFO for > dynamic, all with INTEL_ prefix? INTEL_DEVICE_INFO() INTEL_RUNTIME_INFO() is getting unwieldy? I just used DEVICE_INFO() and RUNTIME_INFO(). Although, there aren't that many direct users of INTEL_*_INFO() so I guess it's not that bad, and any that are, merit a shorter helper. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC 4/7] drm/i915: Remove mkwrite_device_info
On 13/11/2018 11:51, Chris Wilson wrote: Quoting Jani Nikula (2018-11-13 11:45:02) On Mon, 12 Nov 2018, Tvrtko Ursulin wrote: From: Tvrtko Ursulin Now that we are down to one caller, which does not even modify copied device info, we can remove the mkwrite_device_info helper and convert the device info pointer itself to be a pointer to static table instead of a copy. Only unfortnate thing is that we need to convert all callsites which were referencing the device info directly to using the INTEL_INFO helper. I'm not sure if that's all that bad. When I was toying around with mkwrite_device_info removal, I actually started off with changing all device info references to INTEL_INFO. It's a big patch, but it nicely centralizes many of the other changes instead of splattering all over the place. Fwiw, replacing all the static i915->info accesses with INTEL_INFO (or DEVICE_INFO since STATIC_INFO I think is too confusing with C, and INTEL_INFO is not distinct enough from RUNTIME_INFO) is perhaps a You propose DEVICE_INFO for the static part and RUNTIME_INFO for dynamic, all with INTEL_ prefix? pre-requisite for single platform DCE. Along the lines of #define INTEL_INFO(i915) (_gt3_info) Definitely, and I think this patch changed them all. There weren't that many. We also need to minimize the runtime portion for best DCE results. But AFAIR it was quite good already with just IS_GEN and IS_PLATFORM changes and not even LTO. Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/3] drm/i915: Remove bogus FIXME from SKL wm computation
From: Ville Syrjälä
We do return an error when the watermark calculation fails, so
the FIXME claiming otherwise is outdated. Remove it.
Cc: Stanislav Lisovskiy
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6426af873cef..5d823bdc63a9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5458,10 +5458,6 @@ skl_compute_wm(struct drm_atomic_state *state)
* Note that the DDB allocation above may have added more CRTC's that
* weren't otherwise being modified (and set bits in dirty_pipes) if
* pipe allocations had to change.
-*
-* FIXME: Now that we're doing this in the atomic check phase, we
-* should allow skl_update_pipe_wm() to return failure in cases where
-* no suitable watermark values can be found.
*/
for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, cstate, i) {
struct intel_crtc_state *intel_cstate =
--
2.18.1
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[Intel-gfx] [PATCH 1/3] drm/i915: Use explicit old crtc state in skl_compute_wm()
From: Ville Syrjälä
skl_compute_wm() wants to compare the old and new watermarks. Currently
it gets at the old watermarks via crtc->state, which is confusing since
it can point at either the old or the new state depending on where
in the sequence we are. In this case it is correct since we have not yet
swapped the states, but let's make it super clear what this is doing
by using the explicit old state.
Cc: Stanislav Lisovskiy
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 27498ded4949..6426af873cef 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5435,6 +5435,7 @@ skl_compute_wm(struct drm_atomic_state *state)
{
struct drm_crtc *crtc;
struct drm_crtc_state *cstate;
+ struct drm_crtc_state *old_crtc_state;
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
struct skl_ddb_values *results = _state->wm_results;
struct skl_pipe_wm *pipe_wm;
@@ -5462,11 +5463,11 @@ skl_compute_wm(struct drm_atomic_state *state)
* should allow skl_update_pipe_wm() to return failure in cases where
* no suitable watermark values can be found.
*/
- for_each_new_crtc_in_state(state, crtc, cstate, i) {
+ for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, cstate, i) {
struct intel_crtc_state *intel_cstate =
to_intel_crtc_state(cstate);
const struct skl_pipe_wm *old_pipe_wm =
- _intel_crtc_state(crtc->state)->wm.skl.optimal;
+ _intel_crtc_state(old_crtc_state)->wm.skl.optimal;
pipe_wm = _cstate->wm.skl.optimal;
ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm,
--
2.18.1
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[Intel-gfx] [PATCH 3/3] drm/i915: Remove dead update_wm_pre assignment from SKL wm code
From: Ville Syrjälä SKL+ do not use crtc_state->update_wm_pre, so there is absolutely no point it setting it. crtc_state->update_wm_pre only exists as a temporary hack for pre-g4x platforms until we redo their watermarks to be be atomic. Cc: Stanislav Lisovskiy Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_pm.c | 6 -- 1 file changed, 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 5d823bdc63a9..9801412062cc 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5473,12 +5473,6 @@ skl_compute_wm(struct drm_atomic_state *state) if (changed) results->dirty_pipes |= drm_crtc_mask(crtc); - - if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0) - /* This pipe's WM's did not change */ - continue; - - intel_cstate->update_wm_pre = true; } skl_print_wm_changes(state); -- 2.18.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC 4/7] drm/i915: Remove mkwrite_device_info
On 13/11/2018 11:45, Jani Nikula wrote: On Mon, 12 Nov 2018, Tvrtko Ursulin wrote: From: Tvrtko Ursulin Now that we are down to one caller, which does not even modify copied device info, we can remove the mkwrite_device_info helper and convert the device info pointer itself to be a pointer to static table instead of a copy. Only unfortnate thing is that we need to convert all callsites which were referencing the device info directly to using the INTEL_INFO helper. I'm not sure if that's all that bad. When I was toying around with mkwrite_device_info removal, I actually started off with changing all device info references to INTEL_INFO. It's a big patch, but it nicely centralizes many of the other changes instead of splattering all over the place. Yes, but then you still need to splat all over the place to change the same use sites to RUNTIME_INFO or equivalent. I'd actually like to see RUNTIME_INFO or similar macro as well, just to be able to change the way it's handled later on. I actually started of with introducing INTEL_RUNTIME_INFO but ended up backing off with that idea since it looked to "uppercasey". Not saying that the sprinkle of dev_priv->runtime_info.something is that much better, but at least it did not hurt my eyes so much. Don't know.. I am happy to go with popular vote here. Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC 6/7] drm/i915: Introduce subplatform concept
On 13/11/2018 11:40, Jani Nikula wrote: On Mon, 12 Nov 2018, Tvrtko Ursulin wrote: From: Tvrtko Ursulin Introduce subplatform mask to eliminate throughout the code devid checking sprinkle, mostly courtesy of IS_*_UL[TX] macros. Subplatform mask initialization is done at runtime device info init. I kind of like the concept, and I like the centralization of devid checks in one function, but I've always wanted to take this to one step further: only specify device ids in i915_pciids.h, and *nowhere* else. It's perhaps too much duplication to create a device info for all these variants, but I think it would be possible to make the subplatform info table driven using macros defined in i915_pciids.h. It would be much nicer, but how would you do it? Perhaps my imagination is just strong enough today. Simply by splitting the id's into subplatform parts, for instance where we have today: #define INTEL_BDW_GT1_IDS(info) \ INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \ INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \ INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \ INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \ INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \ INTEL_VGA_DEVICE(0x160D, info) /* GT1 Workstation */ We'd split to: #define INTEL_BDW_GT1_ULT_IDS(info) \ INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \ INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \ #define INTEL_BDW_GT1_ULX_IDS(info) \ INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \ #define INTEL_BDW_GT1_IDS(info) \ INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \ INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \ INTEL_VGA_DEVICE(0x160D, info) /* GT1 Workstation */ Then in i915_pci.c, instead of: ... INTEL_BDW_GT1_IDS(_broadwell_gt1_info), ... We'd have: ... INTEL_BDW_GT1_ULT_IDS(_broadwell_gt1_info), INTEL_BDW_GT1_ULX_IDS(_broadwell_gt1_info), INTEL_BDW_GT1_IDS(_broadwell_gt1_info), ... And a separate table to map the id's to subplatform values. Hmm, but we would probably need to extrac the id's from the INTEL_BDW1_GT_IDS like macros so they can be used in this second site without the info parameter. Something like the trick for device info flags, but can it be made to generate a macro? I think not.. Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/3] drm/i915: Return immediately if trylock fails for direct-reclaim
Quoting Tvrtko Ursulin (2018-11-13 10:24:43)
>
> On 09/11/2018 11:44, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-11-09 07:30:34)
> >>
> >> On 08/11/2018 16:48, Chris Wilson wrote:
> >>> Quoting Tvrtko Ursulin (2018-11-08 16:23:08)
>
> On 08/11/2018 08:17, Chris Wilson wrote:
> > Ignore trying to shrink from i915 if we fail to acquire the struct_mutex
> > in the shrinker while performing direct-reclaim. The trade-off being
> > (much) lower latency for non-i915 clients at an increased risk of being
> > unable to obtain a page from direct-reclaim without hitting the
> > oom-notifier. The proviso being that we still keep trying to hard
> > obtain the lock for oom so that we can reap under heavy memory pressure.
> >
> > Signed-off-by: Chris Wilson
> > Cc: Tvrtko Ursulin
> > ---
> > drivers/gpu/drm/i915/i915_gem_shrinker.c | 24
> > +++-
> > 1 file changed, 11 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_gem_shrinker.c
> > b/drivers/gpu/drm/i915/i915_gem_shrinker.c
> > index ea90d3a0d511..d461f458f4af 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_shrinker.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_shrinker.c
> > @@ -36,7 +36,9 @@
> > #include "i915_drv.h"
> > #include "i915_trace.h"
> >
> > -static bool shrinker_lock(struct drm_i915_private *i915, bool *unlock)
> > +static bool shrinker_lock(struct drm_i915_private *i915,
> > + unsigned int flags,
> > + bool *unlock)
> > {
> > switch (mutex_trylock_recursive(>drm.struct_mutex)) {
> > case MUTEX_TRYLOCK_RECURSIVE:
> > @@ -45,15 +47,11 @@ static bool shrinker_lock(struct drm_i915_private
> > *i915, bool *unlock)
> >
> > case MUTEX_TRYLOCK_FAILED:
> > *unlock = false;
> > - preempt_disable();
> > - do {
> > - cpu_relax();
> > - if (mutex_trylock(>drm.struct_mutex)) {
> > - *unlock = true;
> > - break;
> > - }
> > - } while (!need_resched());
> > - preempt_enable();
> > + if (flags & I915_SHRINK_ACTIVE) {
>
> So until I915_SHRINK_ACTIVE, which is the last ditch attempt to shrink
> in the normal case (direct reclaim?) or oom, we bail out on the first
> sign of struct mutex contention. Doesn't this make our shrinker much
> less effective at runtime and why is that OK?
> >>>
> >>> As I said, it's a tradeoff between blocking others for _several_
> >>> _seconds_ and making no progress and returning immediately and making no
> >>> progress. My argument is along the lines of if direct-reclaim is running
> >>> in another process and something else is engaged in the driver hopefully
> >>> the driver will be cleaning up as it goes along or else what remains is
> >>> active and won't be reaped anyway. If direct reclaim is failing, the
> >>> delay before trying the oom path is insignificant.
> >>
> >> What was the rationale behind busy looping there btw?
> >
> > Emulating the optimistic spin for mutex (my patches to expose it from
> > kernel/locking were kept hidden for public decency). My thinking was the
> > exact opposite to this patch, that direct reclaim was of paramount
> > importance and spending the time to try and ensure we grabbed the
> > struct_mutex to search for some pages to free was preferable.
> >
> > It's just on the basis of looking at the actual syslatency and realising
> > the cause is this spinner, I want to swing the axe in other direction.
> >
> > (There's probably a compromise, but honestly I'd prefer to sell the
> > struct_mutex free version of the shrinker first :)
> >
> >> Compared to
> >> perhaps an alternative of micro-sleeps and trying a few times? I know it
> >> would be opposite from what this patch is trying to achieve, I Just
> >> don't had a good judgment on what makes most sense for the shrinker. Is
> >> it better to perhaps try a little bit harder instead of giving up
> >> immediately, but try a little bit harder in a softer way? Or that ends
> >> up blocking the callers and has the same effect of making no progress?
> >
> > Exactly. We can definitely measure the impact of the spinner on
> > unrelated processes, but detecting the premature allocation failure is
> > harder (we wait for more dmesg-warns). The compromise that I've tried to
> > reach here is that if direct-reclaim isn't enough, then we should still
> > try hard to grab the struct_mutex. (That leaves __GFP_RETRY_MAYFAIL
> > vulnerable to not shrinking i915, but a worthwhile compromise as it's
> > allowed to fail?)
> >
> Or in other words, for what use cases, tests or benchmark was the
> existing
Re: [Intel-gfx] [PATCH v2] Fix the possible watermark miswriting for skl+
Quoting Stanislav Lisovskiy (2018-11-13 14:31:38) > Currently whenever we attempt to recalculate > watermarks, we assign dirty_pipes to zero, > then compare current wm results to the recalculated > one and if they changed we set correspondent dirty_pipes > bit again. > This can lead to situation, when we are clearing dirty_pipes, > same wm results twice in a row and not setting dirty_pipes > => so that watermarks are not actually updated, which then might > lead to fifo underruns, crc mismatch and other issues. > > Instead, whenever we detect that wm results are changed, > need to set correspondent dirty_pipes bit and clear it > only once the change is written, but not clear it everytime > we attempt to recalculate those in skl_compute_wm. Ok, but are not dirty_pipes being recomputed for each commit wrt to the current HW state. Should dirty_pipes not be 0 at the start of compute_wm naturally due to it not being used before in the atomic commit sequence? -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Move skip_intermediate_wm handling into ilk_compute_intermediate_wm()
On Thu, Nov 08, 2018 at 05:10:13PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> No point in cluttering the common codepaths with the
> skip_intermediate_wm handling. Just move it into
> ilk_compute_intermediate_wm() as those are the only
> platforms using this.
>
> Signed-off-by: Ville Syrjälä
Pushed with Maarten's irc r-b.
> ---
> drivers/gpu/drm/i915/intel_display.c | 7 +--
> drivers/gpu/drm/i915/intel_pm.c | 3 ++-
> 2 files changed, 3 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 71b7bff85e52..00e775f22a45 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -10817,7 +10817,6 @@ static int intel_crtc_atomic_check(struct drm_crtc
> *crtc,
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> struct intel_crtc_state *pipe_config =
> to_intel_crtc_state(crtc_state);
> - struct drm_atomic_state *state = crtc_state->state;
> int ret;
> bool mode_changed = needs_modeset(crtc_state);
>
> @@ -10854,8 +10853,7 @@ static int intel_crtc_atomic_check(struct drm_crtc
> *crtc,
> }
> }
>
> - if (dev_priv->display.compute_intermediate_wm &&
> - !to_intel_atomic_state(state)->skip_intermediate_wm) {
> + if (dev_priv->display.compute_intermediate_wm) {
> if (WARN_ON(!dev_priv->display.compute_pipe_wm))
> return 0;
>
> @@ -10871,9 +10869,6 @@ static int intel_crtc_atomic_check(struct drm_crtc
> *crtc,
> DRM_DEBUG_KMS("No valid intermediate pipe watermarks
> are possible\n");
> return ret;
> }
> - } else if (dev_priv->display.compute_intermediate_wm) {
> - if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
> - pipe_config->wm.ilk.intermediate =
> pipe_config->wm.ilk.optimal;
> }
>
> if (INTEL_GEN(dev_priv) >= 9) {
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 9da8ff263d36..2b57e360c043 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3159,7 +3159,8 @@ static int ilk_compute_intermediate_wm(struct
> drm_device *dev,
>* and after the vblank.
>*/
> *a = newstate->wm.ilk.optimal;
> - if (!newstate->base.active ||
> drm_atomic_crtc_needs_modeset(>base))
> + if (!newstate->base.active ||
> drm_atomic_crtc_needs_modeset(>base) ||
> + intel_state->skip_intermediate_wm)
> return 0;
>
> a->pipe_enabled |= b->pipe_enabled;
> --
> 2.18.1
--
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Re: [Intel-gfx] [PATCH v2 1/3] drm/i915: Fix the VLV/CHV DSI panel orientation hw readout
On Mon, Oct 22, 2018 at 09:41:36PM +0200, Hans de Goede wrote:
> Hi,
>
> On 22-10-18 16:19, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Let's make sure the DSI port is actually on before we go
> > poking at the plane register to determine which way
> > it's rotated. Otherwise we could be looking at a plane
> > that is feeding a HDMI port for instance.
> >
> > And in order to read the plane register we need the power
> > well to be on. Make sure that is indeed the case. We'll
> > also make sure the plane is actually enabled before we
> > trust the rotation bit to tell us the truth.
> >
> > v2: s/intel_dsi/vlv_dsi/
> >
> > Cc: Hans de Goede
> > Signed-off-by: Ville Syrjälä
>
> Ok, this series correctly detects the panel being upside-down
> on the BYT tablet with an upside down panel which I have, so
> this series is:
>
> Tested-by: Hans de Goede
>
> I assume that most tablets like this one will have the general->rotate_180
> bit set so that the firmware setup / EFI console will show up the right way
> up. So I think going ahead with this is fine.
Thanks. Pushed patch 1 and 2, with Maarten's irc r-b for patch 1.
I might leave patch 3 to sit for a while longer.
>
> Regards,
>
> Hans
>
>
>
>
> > ---
> > drivers/gpu/drm/i915/vlv_dsi.c | 56 ++
> > 1 file changed, 43 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c
> > index ee0cd5d0bf91..dcc59f653e5b 100644
> > --- a/drivers/gpu/drm/i915/vlv_dsi.c
> > +++ b/drivers/gpu/drm/i915/vlv_dsi.c
> > @@ -1647,27 +1647,57 @@ static const struct drm_connector_funcs
> > intel_dsi_connector_funcs = {
> > .atomic_duplicate_state = intel_digital_connector_duplicate_state,
> > };
> >
> > -static int intel_dsi_get_panel_orientation(struct intel_connector
> > *connector)
> > +static enum drm_panel_orientation
> > +vlv_dsi_get_hw_panel_orientation(struct intel_connector *connector)
> > {
> > struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> > - int orientation = DRM_MODE_PANEL_ORIENTATION_NORMAL;
> > - enum i9xx_plane_id i9xx_plane;
> > + struct intel_encoder *encoder = connector->encoder;
> > + enum intel_display_power_domain power_domain;
> > + enum drm_panel_orientation orientation;
> > + struct intel_plane *plane;
> > + struct intel_crtc *crtc;
> > + enum pipe pipe;
> > u32 val;
> >
> > - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> > - if (connector->encoder->crtc_mask == BIT(PIPE_B))
> > - i9xx_plane = PLANE_B;
> > - else
> > - i9xx_plane = PLANE_A;
> > + if (!encoder->get_hw_state(encoder, ))
> > + return DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
> >
> > - val = I915_READ(DSPCNTR(i9xx_plane));
> > - if (val & DISPPLANE_ROTATE_180)
> > - orientation = DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP;
> > - }
> > + crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> > + plane = to_intel_plane(crtc->base.primary);
> > +
> > + power_domain = POWER_DOMAIN_PIPE(pipe);
> > + if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
> > + return DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
> > +
> > + val = I915_READ(DSPCNTR(plane->i9xx_plane));
> > +
> > + if (!(val & DISPLAY_PLANE_ENABLE))
> > + orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
> > + else if (val & DISPPLANE_ROTATE_180)
> > + orientation = DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP;
> > + else
> > + orientation = DRM_MODE_PANEL_ORIENTATION_NORMAL;
> > +
> > + intel_display_power_put(dev_priv, power_domain);
> >
> > return orientation;
> > }
> >
> > +static enum drm_panel_orientation
> > +vlv_dsi_get_panel_orientation(struct intel_connector *connector)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> > + enum drm_panel_orientation orientation;
> > +
> > + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> > + orientation = vlv_dsi_get_hw_panel_orientation(connector);
> > + if (orientation != DRM_MODE_PANEL_ORIENTATION_UNKNOWN)
> > + return orientation;
> > + }
> > +
> > + return DRM_MODE_PANEL_ORIENTATION_NORMAL;
> > +}
> > +
> > static void intel_dsi_add_properties(struct intel_connector *connector)
> > {
> > struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> > @@ -1685,7 +1715,7 @@ static void intel_dsi_add_properties(struct
> > intel_connector *connector)
> > connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT;
> >
> > connector->base.display_info.panel_orientation =
> > - intel_dsi_get_panel_orientation(connector);
> > + vlv_dsi_get_panel_orientation(connector);
> > drm_connector_init_panel_orientation_property(
> > >base,
> >
Re: [Intel-gfx] [PATCH v2] drm/i915: Account for scale factor when calculating initial phase
On Fri, Nov 02, 2018 at 11:47:13AM +0200, Juha-Pekka Heikkila wrote:
> This seems to fix some DRM_FORMAT_RGB565 (up-)scaling IGT tests on on my
> KBL.
>
> Tested-by: Juha-Pekka Heikkila
Pushed with Maarten's irc r-b and t-b. Thanks for the review and
testing.
>
> On 29.10.2018 20:18, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > To get the initial phase correct we need to account for the scale
> > factor as well. I forgot this initially and was mostly looking at
> > heavily upscaled content where the minor difference between -0.5
> > and the proper initial phase was not readily apparent.
> >
> > And let's toss in a comment that tries to explain the formula
> > a little bit.
> >
> > v2: The initial phase upper limit is 1.5, not 24.0!
> >
> > Cc: Maarten Lankhorst
> > Fixes: 0a59952b24e2 ("drm/i915: Configure SKL+ scaler initial phase
> > correctly")
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 45 ++--
> > drivers/gpu/drm/i915/intel_drv.h | 2 +-
> > drivers/gpu/drm/i915/intel_sprite.c | 20 +
> > 3 files changed, 57 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index fe045abb6472..33dd2e9751e6 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -4786,8 +4786,31 @@ static void cpt_verify_modeset(struct drm_device
> > *dev, int pipe)
> >* chroma samples for both of the luma samples, and thus we don't
> >* actually get the expected MPEG2 chroma siting convention :(
> >* The same behaviour is observed on pre-SKL platforms as well.
> > + *
> > + * Theory behind the formula (note that we ignore sub-pixel
> > + * source coordinates):
> > + * s = source sample position
> > + * d = destination sample position
> > + *
> > + * Downscaling 4:1:
> > + * -0.5
> > + * | 0.0
> > + * | | 1.5 (initial phase)
> > + * | | |
> > + * v v v
> > + * | s | s | s | s |
> > + * | d |
> > + *
> > + * Upscaling 1:4:
> > + * -0.5
> > + * | -0.375 (initial phase)
> > + * | | 0.0
> > + * | | |
> > + * v v v
> > + * | s |
> > + * | d | d | d | d |
> >*/
> > -u16 skl_scaler_calc_phase(int sub, bool chroma_cosited)
> > +u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
> > {
> > int phase = -0x8000;
> > u16 trip = 0;
> > @@ -4795,6 +4818,15 @@ u16 skl_scaler_calc_phase(int sub, bool
> > chroma_cosited)
> > if (chroma_cosited)
> > phase += (sub - 1) * 0x8000 / sub;
> >
> > + phase += scale / (2 * sub);
> > +
> > + /*
> > +* Hardware initial phase limited to [-0.5:1.5].
> > +* Since the max hardware scale factor is 3.0, we
> > +* should never actually excdeed 1.0 here.
> > +*/
> > + WARN_ON(phase < -0x8000 || phase > 0x18000);
> > +
> > if (phase < 0)
> > phase = 0x1 + phase;
> > else
> > @@ -5003,13 +5035,20 @@ static void skylake_pfit_enable(const struct
> > intel_crtc_state *crtc_state)
> >
> > if (crtc_state->pch_pfit.enabled) {
> > u16 uv_rgb_hphase, uv_rgb_vphase;
> > + int pfit_w, pfit_h, hscale, vscale;
> > int id;
> >
> > if (WARN_ON(crtc_state->scaler_state.scaler_id < 0))
> > return;
> >
> > - uv_rgb_hphase = skl_scaler_calc_phase(1, false);
> > - uv_rgb_vphase = skl_scaler_calc_phase(1, false);
> > + pfit_w = (crtc_state->pch_pfit.size >> 16) & 0x;
> > + pfit_h = crtc_state->pch_pfit.size & 0x;
> > +
> > + hscale = (crtc_state->pipe_src_w << 16) / pfit_w;
> > + vscale = (crtc_state->pipe_src_h << 16) / pfit_h;
> > +
> > + uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
> > + uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
> >
> > id = scaler_state->scaler_id;
> > I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index db24308729b4..86d551a331b1 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -1709,7 +1709,7 @@ void intel_mode_from_pipe_config(struct
> > drm_display_mode *mode,
> > void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
> > struct intel_crtc_state *crtc_state);
> >
> > -u16 skl_scaler_calc_phase(int sub, bool chroma_center);
> > +u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center);
> > int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
> > int skl_max_scale(const struct intel_crtc_state *crtc_state,
> > u32 pixel_format);
> > diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> > b/drivers/gpu/drm/i915/intel_sprite.c
> > index cfaddc05fea6..fbb916506c77 100644
> > ---
Re: [Intel-gfx] [PATCH] drm/i915: Always write both TILEOFF and LINOFF plane registers
On Thu, Nov 08, 2018 at 05:09:55PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Reduce the clutter in the sprite update functions by writing
> both TILEOFF and LINOFF registers unconditionally. We already
> did this for primary planes so might as well do it for the
> sprites too.
>
> There is no harm in writing both registers. Which one gets
> used depends on the tilimg mode selected in the plane control
> registers.
>
> It might even make sense to clear the register that won't
> get used. That could make register dumps a little easier to
> parse. But I'm not sure it's worth the extra hassle.
>
> Cc: Rodrigo Vivi
> Signed-off-by: Ville Syrjälä
Pushed with Maarten's irc r-b.
> ---
> drivers/gpu/drm/i915/intel_sprite.c | 21 +++--
> 1 file changed, 7 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> b/drivers/gpu/drm/i915/intel_sprite.c
> index 1293182dbcb0..06e8845b071d 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -792,7 +792,6 @@ vlv_update_plane(struct intel_plane *plane,
>const struct intel_plane_state *plane_state)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> - const struct drm_framebuffer *fb = plane_state->base.fb;
> enum pipe pipe = plane->pipe;
> enum plane_id plane_id = plane->id;
> u32 sprctl = plane_state->ctl;
> @@ -829,10 +828,8 @@ vlv_update_plane(struct intel_plane *plane,
> plane_state->color_plane[0].stride);
> I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
>
> - if (fb->modifier == I915_FORMAT_MOD_X_TILED)
> - I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x);
> - else
> - I915_WRITE_FW(SPLINOFF(pipe, plane_id), linear_offset);
> + I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x);
> + I915_WRITE_FW(SPLINOFF(pipe, plane_id), linear_offset);
>
> I915_WRITE_FW(SPCONSTALPHA(pipe, plane_id), 0);
>
> @@ -950,7 +947,6 @@ ivb_update_plane(struct intel_plane *plane,
>const struct intel_plane_state *plane_state)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> - const struct drm_framebuffer *fb = plane_state->base.fb;
> enum pipe pipe = plane->pipe;
> u32 sprctl = plane_state->ctl, sprscale = 0;
> u32 sprsurf_offset = plane_state->color_plane[0].offset;
> @@ -990,12 +986,12 @@ ivb_update_plane(struct intel_plane *plane,
>
> /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
>* register */
> - if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> I915_WRITE_FW(SPROFFSET(pipe), (y << 16) | x);
> - else if (fb->modifier == I915_FORMAT_MOD_X_TILED)
> + } else {
> I915_WRITE_FW(SPRTILEOFF(pipe), (y << 16) | x);
> - else
> I915_WRITE_FW(SPRLINOFF(pipe), linear_offset);
> + }
>
> I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
> if (IS_IVYBRIDGE(dev_priv))
> @@ -1119,7 +1115,6 @@ g4x_update_plane(struct intel_plane *plane,
>const struct intel_plane_state *plane_state)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> - const struct drm_framebuffer *fb = plane_state->base.fb;
> enum pipe pipe = plane->pipe;
> u32 dvscntr = plane_state->ctl, dvsscale = 0;
> u32 dvssurf_offset = plane_state->color_plane[0].offset;
> @@ -1157,10 +1152,8 @@ g4x_update_plane(struct intel_plane *plane,
> I915_WRITE_FW(DVSSTRIDE(pipe), plane_state->color_plane[0].stride);
> I915_WRITE_FW(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
>
> - if (fb->modifier == I915_FORMAT_MOD_X_TILED)
> - I915_WRITE_FW(DVSTILEOFF(pipe), (y << 16) | x);
> - else
> - I915_WRITE_FW(DVSLINOFF(pipe), linear_offset);
> + I915_WRITE_FW(DVSTILEOFF(pipe), (y << 16) | x);
> + I915_WRITE_FW(DVSLINOFF(pipe), linear_offset);
>
> I915_WRITE_FW(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
> I915_WRITE_FW(DVSSCALE(pipe), dvsscale);
> --
> 2.18.1
--
Ville Syrjälä
Intel
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[Intel-gfx] ✗ Fi.CI.BAT: failure for Per context dynamic (sub)slice power-gating (rev7)
== Series Details == Series: Per context dynamic (sub)slice power-gating (rev7) URL : https://patchwork.freedesktop.org/series/48194/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_5132 -> Patchwork_10815 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10815 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10815, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/48194/revisions/7/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10815: === IGT changes === Possible regressions igt@drv_selftest@live_contexts: fi-kbl-7560u: PASS -> INCOMPLETE Warnings igt@prime_vgem@basic-fence-flip: fi-hsw-4770:PASS -> SKIP +2 == Known issues == Here are the changes found in Patchwork_10815 that come from known issues: === IGT changes === Issues hit igt@gem_exec_suspend@basic-s3: fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-cfl-8109u: PASS -> DMESG-WARN (fdo#107345) +2 Possible fixes igt@kms_chamelium@dp-crc-fast: fi-kbl-7500u: FAIL (fdo#108725) -> PASS +1 igt@kms_chamelium@dp-hpd-fast: fi-kbl-7500u: FAIL (fdo#108724) -> PASS igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b: fi-byt-clapper: FAIL (fdo#107362) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence: fi-byt-clapper: FAIL (fdo#103191, fdo#107362) -> PASS Warnings igt@kms_chamelium@common-hpd-after-suspend: fi-kbl-7500u: FAIL (fdo#108724) -> DMESG-WARN (fdo#105079, fdo#105602, fdo#102505) fdo#102505 https://bugs.freedesktop.org/show_bug.cgi?id=102505 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#105079 https://bugs.freedesktop.org/show_bug.cgi?id=105079 fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602 fdo#107345 https://bugs.freedesktop.org/show_bug.cgi?id=107345 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#108724 https://bugs.freedesktop.org/show_bug.cgi?id=108724 fdo#108725 https://bugs.freedesktop.org/show_bug.cgi?id=108725 == Participating hosts (49 -> 44) == Additional (3): fi-byt-j1900 fi-glk-j4005 fi-kbl-7567u Missing(8): fi-kbl-soraka fi-ilk-m540 fi-bdw-5557u fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-icl-u == Build changes == * Linux: CI_DRM_5132 -> Patchwork_10815 CI_DRM_5132: 7fa49786320fddb8a4f89318e7eeb65ce6134f8b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4714: cab148ca3ec904a94d0cd43476cf7e1f8663f906 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10815: d06e39a5d493e7d819ae89771bc4f47a8cc10023 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == d06e39a5d493 drm/i915/icl: Support co-existence between per-context SSEU and OA 6f3ff0f5558a drm/i915: Expose RPCS (SSEU) configuration to userspace (Gen11 only) 519b5713792c drm/i915: Add timeline barrier support 111ba44372b7 drm/i915/perf: lock powergating configuration to default when active 5c2565cbc409 drm/i915: Record the sseu configuration per-context & engine e5e9458e7692 drm/i915/execlists: Move RPCS setup to context pin == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10815/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for Fix the possible watermark miswriting for skl+
== Series Details == Series: Fix the possible watermark miswriting for skl+ URL : https://patchwork.freedesktop.org/series/52425/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5132 -> Patchwork_10814 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/52425/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10814 that come from known issues: === IGT changes === Issues hit igt@gem_ctx_create@basic-files: fi-bsw-kefka: PASS -> INCOMPLETE (fdo#108714) igt@gem_exec_suspend@basic-s3: fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718) Possible fixes igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: DMESG-WARN (fdo#102614) -> PASS igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b: fi-byt-clapper: FAIL (fdo#107362) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence: fi-byt-clapper: FAIL (fdo#107362, fdo#103191) -> PASS fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#108714 https://bugs.freedesktop.org/show_bug.cgi?id=108714 == Participating hosts (49 -> 45) == Additional (3): fi-byt-j1900 fi-glk-j4005 fi-kbl-7567u Missing(7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-icl-u == Build changes == * Linux: CI_DRM_5132 -> Patchwork_10814 CI_DRM_5132: 7fa49786320fddb8a4f89318e7eeb65ce6134f8b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4714: cab148ca3ec904a94d0cd43476cf7e1f8663f906 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10814: 4b84e468f305112108e6b42d8fad677db4d7e5ca @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 4b84e468f305 Fix the possible watermark miswriting for skl+ == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10814/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Per context dynamic (sub)slice power-gating (rev7)
== Series Details == Series: Per context dynamic (sub)slice power-gating (rev7) URL : https://patchwork.freedesktop.org/series/48194/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/execlists: Move RPCS setup to context pin Okay! Commit: drm/i915: Record the sseu configuration per-context & engine -drivers/gpu/drm/i915/selftests/../i915_drv.h:3714:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3728:16: warning: expression using sizeof(void) Commit: drm/i915/perf: lock powergating configuration to default when active Okay! Commit: drm/i915: Add timeline barrier support Okay! Commit: drm/i915: Expose RPCS (SSEU) configuration to userspace (Gen11 only) +drivers/gpu/drm/i915/intel_lrc.c:2413:25: warning: expression using sizeof(void) Commit: drm/i915/icl: Support co-existence between per-context SSEU and OA Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Per context dynamic (sub)slice power-gating (rev7)
== Series Details == Series: Per context dynamic (sub)slice power-gating (rev7) URL : https://patchwork.freedesktop.org/series/48194/ State : warning == Summary == $ dim checkpatch origin/drm-tip e5e9458e7692 drm/i915/execlists: Move RPCS setup to context pin 5c2565cbc409 drm/i915: Record the sseu configuration per-context & engine 111ba44372b7 drm/i915/perf: lock powergating configuration to default when active 519b5713792c drm/i915: Add timeline barrier support 6f3ff0f5558a drm/i915: Expose RPCS (SSEU) configuration to userspace (Gen11 only) -:47: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #47: v2: Fix offset of CTX_R_PWR_CLK_STATE in intel_lr_context_set_sseu() (Lionel) -:496: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 'user->min_eus_per_subslice != device->max_eus_per_subslice' #496: FILE: drivers/gpu/drm/i915/i915_gem_context.c:1175: + if ((user->min_eus_per_subslice != +device->max_eus_per_subslice) || + (user->max_eus_per_subslice != +device->max_eus_per_subslice)) -:496: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 'user->max_eus_per_subslice != device->max_eus_per_subslice' #496: FILE: drivers/gpu/drm/i915/i915_gem_context.c:1175: + if ((user->min_eus_per_subslice != +device->max_eus_per_subslice) || + (user->max_eus_per_subslice != +device->max_eus_per_subslice)) total: 0 errors, 1 warnings, 2 checks, 479 lines checked d06e39a5d493 drm/i915/icl: Support co-existence between per-context SSEU and OA ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 0/6] Per context dynamic (sub)slice power-gating
Quoting Tvrtko Ursulin (2018-11-13 14:35:29) > From: Tvrtko Ursulin > > Just a resend since almost two months have passed since the last one and there > were some rebases needed due underlying code changes. > > Nothing major to warrant re-requesting the reviews, or in other words, the > series is still fully reviewed. And looks good. Nothing looked silly or out of place in re-reading the mechanics. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for Fix the possible watermark miswriting
== Series Details == Series: Fix the possible watermark miswriting URL : https://patchwork.freedesktop.org/series/52423/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5132 -> Patchwork_10813 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/52423/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10813 that come from known issues: === IGT changes === Issues hit igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: PASS -> FAIL (fdo#103167) igt@kms_pipe_crc_basic@hang-read-crc-pipe-b: fi-byt-clapper: PASS -> FAIL (fdo#103191, fdo#107362) Possible fixes igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: DMESG-WARN (fdo#102614) -> PASS igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b: fi-byt-clapper: FAIL (fdo#107362) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence: fi-byt-clapper: FAIL (fdo#103191, fdo#107362) -> PASS fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 == Participating hosts (49 -> 44) == Additional (3): fi-byt-j1900 fi-glk-j4005 fi-kbl-7567u Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-elk-e7500 fi-icl-u == Build changes == * Linux: CI_DRM_5132 -> Patchwork_10813 CI_DRM_5132: 7fa49786320fddb8a4f89318e7eeb65ce6134f8b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4714: cab148ca3ec904a94d0cd43476cf7e1f8663f906 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10813: 4bd7c3cebd073fd0205cfa012293c97b2e9c5a51 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 4bd7c3cebd07 Fix the possible watermark miswriting == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10813/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v1] Fix the possible watermark miswriting
On Tue, Nov 13, 2018 at 04:27:28PM +0200, Stanislav Lisovskiy wrote: > Currently whenever we attempt to recalculate > watermarks, we assign dirty_pipes to zero, > then compare current wm results to the recalculated > one and if they changed we set correspondent dirty_pipes > bit again. > This can lead to situation, when we same clearing dirty_pipes, > same wm results twice and not setting dirty_pipes => so that > watermarks are not actually updated, which then might > lead to fifo underruns, crc mismatch and other issues. > > Instead, whenever we detect that wm results are changed, > need to set correspondent dirty_pipes bit and clear it > only once the change is written, but not clear it everytime > we attempt to recalculate those in skl_compute_wm. > > Signed-off-by: Stanislav Lisovskiy > --- > drivers/gpu/drm/i915/intel_pm.c | 8 +--- > 1 file changed, 5 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index dc034617febb..f7fbc4bc0d43 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -5441,9 +5441,6 @@ skl_compute_wm(struct drm_atomic_state *state) > bool changed = false; > int ret, i; > > - /* Clear all dirty flags */ > - results->dirty_pipes = 0; > - > ret = skl_ddb_add_affected_pipes(state, ); > if (ret || !changed) > return ret; > @@ -5496,6 +5493,7 @@ static void skl_atomic_update_crtc_wm(struct > intel_atomic_state *state, > struct drm_i915_private *dev_priv = to_i915(state->base.dev); > struct skl_pipe_wm *pipe_wm = >wm.skl.optimal; > const struct skl_ddb_allocation *ddb = >wm_results.ddb; > + struct skl_ddb_values *results = >wm_results; > enum pipe pipe = crtc->pipe; > enum plane_id plane_id; > > @@ -5512,6 +5510,10 @@ static void skl_atomic_update_crtc_wm(struct > intel_atomic_state *state, > skl_write_cursor_wm(crtc, _wm->planes[plane_id], > ddb); > } > + > + /* Clear correspondent dirty bit */ > + results->dirty_pipes &= ~drm_crtc_mask(>base); > + > } Hmm. I can't figure out what the problem really is here. Yes, it does look like we'd end up writing the watermarks twice for pipes that are getting enabled. But that should be safeish (apart from the whole "need PLANE_SURF write to atually arm the update" mess). Note that this whole code is getting nuked soon (I hope): https://patchwork.freedesktop.org/series/51878/ but in the meantime if there is a clear bug we probably want the fix in first so that it can be backported. So I think we need a clear analysis of the actual problem. -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 2/4] tests/gem_ctx_sseu: Dynamic (sub)slice programming tests
From: Lionel Landwerlin
Verify that the per-context dynamic SSEU uAPI works as expected.
To achieve that, in the absence of a better mechamism, we read the value
of PWR_CLK_STATE register, or use MI_SET_PREDICATE on platforms before
Cannonlake.
This register is written to by the GPU on context restore so this way
we verify i915 is correctly updating the context image in all
circumstances.
v2: Add subslice tests (Lionel)
Use MI_SET_PREDICATE for further verification when available (Lionel)
v3: Rename to gem_ctx_rpcs (Lionel)
v4: Update kernel API (Lionel)
Add 0 value test (Lionel)
Exercise invalid values (Lionel)
v5: Add perf tests (Lionel)
v6: Add new sysfs entry tests (Lionel)
v7: Test rsvd fields
Update for kernel series changes
v8: Drop test_no_sseu_support() test (Kelvin)
Drop drm_intel_*() apis (Chris)
v9: by Chris:
Drop all do_ioctl/do_ioctl_err()
Use gem_context_[gs]et_param()
Use gem_read() instead of mapping memory
by Lionel:
Test dynamic sseu on/off more
Tvrtko Ursulin:
v10:
* Various style tweaks and refactorings.
* New test coverage.
v11:
* Change platform support to just Gen11.
* Simplify availability test. (Chris Wilson)
* More invalid pointer tests. (Chris Wilson)
v12:
* Fix MAP_FIXED use (doh!).
* Fix get/set copy errors.
* Drop supported platform test. (Chris Wilson)
* Add mmap__gtt test. (Chris Wilson)
v13:
* Commit message tweaks.
* Added reset/hang/suspend tests. (Chris Wilson)
* Assert spinner is busy. (Chris Wilson)
* Remove some more ABI assumptions. (Chris Wilson)
v14:
* Use default resume time. (Chris Wilson)
* Trigger hang after rpcs read batch has been submitted. (Chris Wilson)
v15:
* Adjust for uAPI restrictions.
v16:
* Build system changes.
Signed-off-by: Lionel Landwerlin
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson # v14
---
tests/Makefile.am |1 +
tests/Makefile.sources |3 +
tests/i915/gem_ctx_param.c |4 +-
tests/i915/gem_ctx_sseu.c | 1190
tests/meson.build |8 +
5 files changed, 1205 insertions(+), 1 deletion(-)
create mode 100644 tests/i915/gem_ctx_sseu.c
diff --git a/tests/Makefile.am b/tests/Makefile.am
index 3d1ce0bc1af8..79333ac7db26 100644
--- a/tests/Makefile.am
+++ b/tests/Makefile.am
@@ -109,6 +109,7 @@ gem_close_race_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
gem_close_race_LDADD = $(LDADD) -lpthread
gem_ctx_thrash_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
gem_ctx_thrash_LDADD = $(LDADD) -lpthread
+gem_ctx_sseu_LDADD = $(LDADD) $(top_builddir)/lib/libigt_perf.la
gem_exec_parallel_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
gem_exec_parallel_LDADD = $(LDADD) -lpthread
gem_fence_thrash_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index c910210b992f..fd99bc15da67 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -159,6 +159,9 @@ gem_ctx_isolation_SOURCES = i915/gem_ctx_isolation.c
TESTS_progs += gem_ctx_param
gem_ctx_param_SOURCES = i915/gem_ctx_param.c
+TESTS_progs += gem_ctx_sseu
+gem_ctx_sseu_SOURCES = i915/gem_ctx_sseu.c
+
TESTS_progs += gem_ctx_switch
gem_ctx_switch_SOURCES = i915/gem_ctx_switch.c
diff --git a/tests/i915/gem_ctx_param.c b/tests/i915/gem_ctx_param.c
index c46fd709b0d7..af1afeaa2f2f 100644
--- a/tests/i915/gem_ctx_param.c
+++ b/tests/i915/gem_ctx_param.c
@@ -294,11 +294,13 @@ igt_main
set_priority(fd);
}
+ /* I915_CONTEXT_PARAM_SSEU tests are located in gem_ctx_sseu.c */
+
/* NOTE: This testcase intentionally tests for the next free parameter
* to catch ABI extensions. Don't "fix" this testcase without adding all
* the tests for the new param first.
*/
- arg.param = I915_CONTEXT_PARAM_PRIORITY + 1;
+ arg.param = I915_CONTEXT_PARAM_SSEU + 1;
igt_subtest("invalid-param-get") {
arg.ctx_id = ctx;
diff --git a/tests/i915/gem_ctx_sseu.c b/tests/i915/gem_ctx_sseu.c
new file mode 100644
index ..889f70643392
--- /dev/null
+++ b/tests/i915/gem_ctx_sseu.c
@@ -0,0 +1,1190 @@
+/*
+ * Copyright © 2017-2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
[Intel-gfx] [PATCH i-g-t 3/4] tests/gem_media_vme: Simple test to exercise the VME block
From: Tony Ye
Simple test which exercises the VME fixed function block.
v2: (Tvrtko Ursulin)
* Small cleanups like copyright date, tabs, remove unused bits.
v3: (Tony Ye)
* Added curbe data entry for dst surface.
* Read the dst surface after the VME kernel being executed.
Signed-off-by: Tony Ye
Signed-off-by: Tvrtko Ursulin
---
lib/gpu_cmds.c | 136 +
lib/gpu_cmds.h | 20 +-
lib/intel_batchbuffer.c| 9 +++
lib/intel_batchbuffer.h| 7 ++
lib/media_fill.c | 117 +++
lib/media_fill.h | 6 ++
lib/surfaceformat.h| 2 +
tests/Makefile.sources | 3 +
tests/i915/gem_media_vme.c | 114 +++
tests/meson.build | 1 +
10 files changed, 413 insertions(+), 2 deletions(-)
create mode 100644 tests/i915/gem_media_vme.c
diff --git a/lib/gpu_cmds.c b/lib/gpu_cmds.c
index 556a94c6f0b6..b490a63bdfef 100644
--- a/lib/gpu_cmds.c
+++ b/lib/gpu_cmds.c
@@ -52,6 +52,22 @@ gen7_fill_curbe_buffer_data(struct intel_batchbuffer *batch,
return offset;
}
+uint32_t
+gen11_fill_curbe_buffer_data(struct intel_batchbuffer *batch)
+{
+ uint32_t *curbe_buffer;
+ uint32_t offset;
+
+ curbe_buffer = intel_batchbuffer_subdata_alloc(batch,
+ sizeof(uint32_t) * 8,
+ 64);
+ offset = intel_batchbuffer_subdata_offset(batch, curbe_buffer);
+ *curbe_buffer++ = 0;
+ *curbe_buffer = 1;
+
+ return offset;
+}
+
uint32_t
gen7_fill_surface_state(struct intel_batchbuffer *batch,
const struct igt_buf *buf,
@@ -119,6 +135,26 @@ gen7_fill_binding_table(struct intel_batchbuffer *batch,
return offset;
}
+uint32_t
+gen11_fill_binding_table(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,const struct igt_buf *dst)
+{
+ uint32_t *binding_table, offset;
+
+ binding_table = intel_batchbuffer_subdata_alloc(batch, 64, 64);
+ offset = intel_batchbuffer_subdata_offset(batch, binding_table);
+ binding_table[0] = gen11_fill_surface_state(batch, src,
+
SURFACE_1D,SURFACEFORMAT_R32G32B32A32_FLOAT,
+ 0,0,
+ 0);
+ binding_table[1] = gen11_fill_surface_state(batch, dst,
+ SURFACE_BUFFER,
SURFACEFORMAT_RAW,
+ 1,1,
+ 1);
+
+ return offset;
+}
+
uint32_t
gen7_fill_kernel(struct intel_batchbuffer *batch,
const uint32_t kernel[][4],
@@ -384,6 +420,71 @@ gen8_fill_surface_state(struct intel_batchbuffer *batch,
return offset;
}
+uint32_t
+gen11_fill_surface_state(struct intel_batchbuffer *batch,
+ const struct igt_buf *buf,
+ uint32_t surface_type,
+ uint32_t format,
+ uint32_t vertical_alignment,
+ uint32_t horizontal_alignment,
+ int is_dst)
+{
+ struct gen8_surface_state *ss;
+ uint32_t write_domain, read_domain, offset;
+ int ret;
+
+ if (is_dst) {
+ write_domain = read_domain = I915_GEM_DOMAIN_RENDER;
+ } else {
+ write_domain = 0;
+ read_domain = I915_GEM_DOMAIN_SAMPLER;
+ }
+
+ ss = intel_batchbuffer_subdata_alloc(batch, sizeof(*ss), 64);
+ offset = intel_batchbuffer_subdata_offset(batch, ss);
+
+ ss->ss0.surface_type = surface_type;
+ ss->ss0.surface_format = format;
+ ss->ss0.render_cache_read_write = 1;
+ ss->ss0.vertical_alignment = vertical_alignment; /* align 4 */
+ ss->ss0.horizontal_alignment = horizontal_alignment; /* align 4 */
+
+ if (buf->tiling == I915_TILING_X)
+ ss->ss0.tiled_mode = 2;
+ else if (buf->tiling == I915_TILING_Y)
+ ss->ss0.tiled_mode = 3;
+ else
+ ss->ss0.tiled_mode = 0;
+
+ ss->ss8.base_addr = buf->bo->offset;
+
+ ret = drm_intel_bo_emit_reloc(batch->bo,
+ intel_batchbuffer_subdata_offset(batch, ss) + 8
* 4,
+ buf->bo, 0, read_domain, write_domain);
+ igt_assert(ret == 0);
+
+ if (is_dst) {
+ ss->ss1.memory_object_control = 2;
+ ss->ss2.height = 1;
+ ss->ss2.width = 95;
+ ss->ss3.pitch = 0;
+ ss->ss7.shader_chanel_select_r = 4;
+ ss->ss7.shader_chanel_select_g = 5;
+ ss->ss7.shader_chanel_select_b = 6;
+ ss->ss7.shader_chanel_select_a = 7;
+ }
+ else {
+ ss->ss1.qpitch =
[Intel-gfx] [PATCH i-g-t 0/4] Per context dynamic (sub)slice power-gating
From: Tvrtko Ursulin Tests to accompany the respective i915 series. Contributed by Tony Ye is gem_media_vme, anew test which exercises the media VME block to demonstrate the effectiveness of the uAPI for this particular issue. Lionel Landwerlin (2): headers: bump tests/gem_ctx_sseu: Dynamic (sub)slice programming tests Tony Ye (2): tests/gem_media_vme: Simple test to exercise the VME block tests/gem_media_vme: Shut down half of subslices to avoid gpu hang on ICL include/drm-uapi/amdgpu_drm.h | 52 +- include/drm-uapi/drm.h | 17 + include/drm-uapi/drm_fourcc.h | 224 ++ include/drm-uapi/drm_mode.h| 26 +- include/drm-uapi/etnaviv_drm.h |6 + include/drm-uapi/exynos_drm.h | 240 +++ include/drm-uapi/i915_drm.h| 80 +++ include/drm-uapi/msm_drm.h |2 + include/drm-uapi/tegra_drm.h | 492 - include/drm-uapi/v3d_drm.h | 204 ++ include/drm-uapi/vc4_drm.h | 13 +- include/drm-uapi/virtgpu_drm.h |1 + include/drm-uapi/vmwgfx_drm.h | 166 - lib/gpu_cmds.c | 148 lib/gpu_cmds.h | 23 +- lib/intel_batchbuffer.c|9 + lib/intel_batchbuffer.h|7 + lib/media_fill.c | 117 lib/media_fill.h |6 + lib/surfaceformat.h|2 + tests/Makefile.am |1 + tests/Makefile.sources |6 + tests/i915/gem_ctx_param.c |4 +- tests/i915/gem_ctx_sseu.c | 1190 tests/i915/gem_media_vme.c | 179 + tests/meson.build |9 + 26 files changed, 3165 insertions(+), 59 deletions(-) create mode 100644 include/drm-uapi/v3d_drm.h create mode 100644 tests/i915/gem_ctx_sseu.c create mode 100644 tests/i915/gem_media_vme.c -- 2.19.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 1/4] headers: bump
From: Lionel Landwerlin
---
include/drm-uapi/amdgpu_drm.h | 52 +++-
include/drm-uapi/drm.h | 17 ++
include/drm-uapi/drm_fourcc.h | 224 +++
include/drm-uapi/drm_mode.h| 26 +-
include/drm-uapi/etnaviv_drm.h | 6 +
include/drm-uapi/exynos_drm.h | 240
include/drm-uapi/i915_drm.h| 80 ++
include/drm-uapi/msm_drm.h | 2 +
include/drm-uapi/tegra_drm.h | 492 -
include/drm-uapi/v3d_drm.h | 204 ++
include/drm-uapi/vc4_drm.h | 13 +-
include/drm-uapi/virtgpu_drm.h | 1 +
include/drm-uapi/vmwgfx_drm.h | 166 ---
13 files changed, 1467 insertions(+), 56 deletions(-)
create mode 100644 include/drm-uapi/v3d_drm.h
diff --git a/include/drm-uapi/amdgpu_drm.h b/include/drm-uapi/amdgpu_drm.h
index 1816bd8200d1..370e9a5536ef 100644
--- a/include/drm-uapi/amdgpu_drm.h
+++ b/include/drm-uapi/amdgpu_drm.h
@@ -72,12 +72,41 @@ extern "C" {
#define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE +
DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
#define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE +
DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
+/**
+ * DOC: memory domains
+ *
+ * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible.
+ * Memory in this pool could be swapped out to disk if there is pressure.
+ *
+ * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the
+ * GPU's virtual address space via gart. Gart memory linearizes non-contiguous
+ * pages of system memory, allows GPU access system memory in a linezrized
+ * fashion.
+ *
+ * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory
+ * carved out by the BIOS.
+ *
+ * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data
+ * across shader threads.
+ *
+ * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the
+ * execution of all the waves on a device.
+ *
+ * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines
+ * for appending data.
+ */
#define AMDGPU_GEM_DOMAIN_CPU 0x1
#define AMDGPU_GEM_DOMAIN_GTT 0x2
#define AMDGPU_GEM_DOMAIN_VRAM 0x4
#define AMDGPU_GEM_DOMAIN_GDS 0x8
#define AMDGPU_GEM_DOMAIN_GWS 0x10
#define AMDGPU_GEM_DOMAIN_OA 0x20
+#define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \
+AMDGPU_GEM_DOMAIN_GTT | \
+AMDGPU_GEM_DOMAIN_VRAM | \
+AMDGPU_GEM_DOMAIN_GDS | \
+AMDGPU_GEM_DOMAIN_GWS | \
+AMDGPU_GEM_DOMAIN_OA)
/* Flag that CPU access will be required for the case of VRAM domain */
#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
@@ -95,6 +124,10 @@ extern "C" {
#define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)
/* Flag that BO sharing will be explicitly synchronized */
#define AMDGPU_GEM_CREATE_EXPLICIT_SYNC(1 << 7)
+/* Flag that indicates allocating MQD gart on GFX9, where the mtype
+ * for the second page onward should be set to NC.
+ */
+#define AMDGPU_GEM_CREATE_MQD_GFX9 (1 << 8)
struct drm_amdgpu_gem_create_in {
/** the requested memory size */
@@ -473,7 +506,8 @@ struct drm_amdgpu_gem_va {
#define AMDGPU_HW_IP_UVD_ENC 5
#define AMDGPU_HW_IP_VCN_DEC 6
#define AMDGPU_HW_IP_VCN_ENC 7
-#define AMDGPU_HW_IP_NUM 8
+#define AMDGPU_HW_IP_VCN_JPEG 8
+#define AMDGPU_HW_IP_NUM 9
#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
@@ -482,6 +516,7 @@ struct drm_amdgpu_gem_va {
#define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03
#define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04
#define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05
+#define AMDGPU_CHUNK_ID_BO_HANDLES 0x06
struct drm_amdgpu_cs_chunk {
__u32 chunk_id;
@@ -520,6 +555,10 @@ union drm_amdgpu_cs {
/* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */
#define AMDGPU_IB_FLAG_PREEMPT (1<<2)
+/* The IB fence should do the L2 writeback but not invalidate any shader
+ * caches (L2/vL1/sL1/I$). */
+#define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3)
+
struct drm_amdgpu_cs_chunk_ib {
__u32 _pad;
/** AMDGPU_IB_FLAG_* */
@@ -618,6 +657,16 @@ struct drm_amdgpu_cs_chunk_data {
#define AMDGPU_INFO_FW_SOS 0x0c
/* Subquery id: Query PSP ASD firmware version */
#define AMDGPU_INFO_FW_ASD 0x0d
+ /* Subquery id: Query VCN firmware version */
+ #define AMDGPU_INFO_FW_VCN 0x0e
+ /* Subquery id: Query GFX RLC SRLC firmware version */
+ #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f
+ /* Subquery id: Query GFX RLC SRLG firmware version */
+ #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10
+ /* Subquery id: Query GFX
[Intel-gfx] [PATCH i-g-t 4/4] tests/gem_media_vme: Shut down half of subslices to avoid gpu hang on ICL
From: Tony Ye
On Icelake we need to turn off subslices not containing the VME block or
the VME kernel will hang.
v2: (Tvrtko Ursulin)
* Remove libdrm usage for setting context param.
* Cleanup bitmask operation.
* Only apply the workaround for ICL.
v3:
* Added hang detector. (Chris Wilson)
Signed-off-by: Tony Ye
Signed-off-by: Tvrtko Ursulin
---
lib/gpu_cmds.c | 12 +++
lib/gpu_cmds.h | 3 ++
lib/media_fill.c | 2 +-
tests/i915/gem_media_vme.c | 67 +-
4 files changed, 82 insertions(+), 2 deletions(-)
diff --git a/lib/gpu_cmds.c b/lib/gpu_cmds.c
index b490a63bdfef..8d270ee86229 100644
--- a/lib/gpu_cmds.c
+++ b/lib/gpu_cmds.c
@@ -36,6 +36,18 @@ gen7_render_flush(struct intel_batchbuffer *batch, uint32_t
batch_end)
igt_assert(ret == 0);
}
+void
+gen7_render_context_flush(struct intel_batchbuffer *batch, uint32_t batch_end)
+{
+ int ret;
+
+ ret = drm_intel_bo_subdata(batch->bo, 0, 4096, batch->buffer);
+ if (ret == 0)
+ ret = drm_intel_gem_bo_context_exec(batch->bo, batch->ctx,
+ batch_end, 0);
+ igt_assert(ret == 0);
+}
+
uint32_t
gen7_fill_curbe_buffer_data(struct intel_batchbuffer *batch,
uint8_t color)
diff --git a/lib/gpu_cmds.h b/lib/gpu_cmds.h
index ca671fb52daf..1321af446161 100644
--- a/lib/gpu_cmds.h
+++ b/lib/gpu_cmds.h
@@ -40,6 +40,9 @@
void
gen7_render_flush(struct intel_batchbuffer *batch, uint32_t batch_end);
+void
+gen7_render_context_flush(struct intel_batchbuffer *batch, uint32_t batch_end);
+
uint32_t
gen7_fill_curbe_buffer_data(struct intel_batchbuffer *batch,
uint8_t color);
diff --git a/lib/media_fill.c b/lib/media_fill.c
index ab613b308742..d630f2785ae4 100644
--- a/lib/media_fill.c
+++ b/lib/media_fill.c
@@ -345,7 +345,7 @@ __gen11_media_vme_func(struct intel_batchbuffer *batch,
batch_end = intel_batchbuffer_align(batch, 8);
assert(batch_end < BATCH_STATE_SPLIT);
- gen7_render_flush(batch, batch_end);
+ gen7_render_context_flush(batch, batch_end);
intel_batchbuffer_reset(batch);
}
diff --git a/tests/i915/gem_media_vme.c b/tests/i915/gem_media_vme.c
index 1c2f33a45eb5..a8f7864621f7 100644
--- a/tests/i915/gem_media_vme.c
+++ b/tests/i915/gem_media_vme.c
@@ -81,6 +81,53 @@ static void scratch_buf_init_dst(drm_intel_bufmgr *bufmgr,
struct igt_buf *buf)
buf->stride = 1;
}
+static uint64_t switch_off_n_bits(uint64_t mask, unsigned int n)
+{
+ unsigned int i;
+
+ igt_assert(n > 0 && n <= (sizeof(mask) * 8));
+ igt_assert(n <= __builtin_popcount(mask));
+
+ for (i = 0; n && i < (sizeof(mask) * 8); i++) {
+ uint64_t bit = 1ULL << i;
+
+ if (bit & mask) {
+ mask &= ~bit;
+ n--;
+ }
+ }
+
+ return mask;
+}
+
+static void shut_non_vme_subslices(int drm_fd, uint32_t ctx)
+{
+ struct drm_i915_gem_context_param_sseu sseu = { };
+ struct drm_i915_gem_context_param arg =
+ {
+ .param = I915_CONTEXT_PARAM_SSEU,
+ .ctx_id = ctx,
+ .size = sizeof(sseu),
+ .value = to_user_pointer(),
+ };
+ int ret;
+
+ if (__gem_context_get_param(drm_fd, ))
+ return; /* no sseu support */
+
+ ret = __gem_context_set_param(drm_fd, );
+ igt_assert(ret == 0 || ret == -ENODEV || ret == -EINVAL);
+ if (ret)
+ return; /* no sseu support */
+
+ /* shutdown half subslices*/
+ sseu.subslice_mask =
+ switch_off_n_bits(sseu.subslice_mask,
+ __builtin_popcount(sseu.subslice_mask) / 2);
+
+ gem_context_set_param(drm_fd, );
+}
+
igt_simple_main
{
int drm_fd;
@@ -91,7 +138,7 @@ igt_simple_main
struct igt_buf src, dst;
uint8_t dst_linear[OUTPUT_SIZE];
- drm_fd = drm_open_driver_render(DRIVER_INTEL);
+ drm_fd = drm_open_driver(DRIVER_INTEL);
igt_require_gem(drm_fd);
devid = intel_get_drm_devid(drm_fd);
@@ -108,7 +155,25 @@ igt_simple_main
scratch_buf_init_src(bufmgr, );
scratch_buf_init_dst(bufmgr, );
+ batch->ctx = drm_intel_gem_context_create(bufmgr);
+ igt_assert(batch->ctx);
+
+ /* ICL hangs if non-VME enabled slices are enabled with a VME kernel. */
+ if (intel_gen(devid) == 11) {
+ uint32_t ctx_id;
+ int ret;
+
+ ret = drm_intel_gem_context_get_id(batch->ctx, _id);
+ igt_assert_eq(ret, 0);
+
+ shut_non_vme_subslices(drm_fd, ctx_id);
+ }
+
+ igt_fork_hang_detector(drm_fd);
+
media_vme(batch, , WIDTH, HEIGHT, );
gem_read(drm_fd, dst.bo->handle, 0,
dst_linear, sizeof(dst_linear));
+
+
[Intel-gfx] [PATCH 6/6] drm/i915/icl: Support co-existence between per-context SSEU and OA
From: Tvrtko Ursulin
When OA is active we want to lock the powergating configuration, but on
Icelake, users like the media stack will have issues if we lock to the
full device configuration.
Instead lock to a subset of (sub)slices which are currently a known
working configuration for all users.
v2:
* Fix commit message spelling.
v3:
Lionel:
* Add bspec reference.
* Fix spelling in comment.
Signed-off-by: Tvrtko Ursulin
Bspec: 21140
Cc: Lionel Landwerlin
Reviewed-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/intel_lrc.c | 25 -
1 file changed, 20 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index bf3bb0460824..3b867f81f5b4 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2372,13 +2372,28 @@ u32 gen8_make_rpcs(struct drm_i915_private *i915,
struct intel_sseu *req_sseu)
/*
* If i915/perf is active, we want a stable powergating configuration
-* on the system. The most natural configuration to take in that case
-* is the default (i.e maximum the hardware can do).
+* on the system.
+*
+* We could choose full enablement, but on ICL we know there are use
+* cases which disable slices for functional, apart for performance
+* reasons. So in this case we select a known stable subset.
*/
- if (unlikely(i915->perf.oa.exclusive_stream))
- ctx_sseu = intel_device_default_sseu(i915);
- else
+ if (!i915->perf.oa.exclusive_stream) {
ctx_sseu = *req_sseu;
+ } else {
+ ctx_sseu = intel_device_default_sseu(i915);
+
+ if (IS_GEN11(i915)) {
+ /*
+* We only need subslice count so it doesn't matter
+* which ones we select - just turn off low bits in the
+* amount of half of all available subslices per slice.
+*/
+ ctx_sseu.subslice_mask =
+ ~(~0 << (hweight8(ctx_sseu.subslice_mask) / 2));
+ ctx_sseu.slice_mask = 0x1;
+ }
+ }
slices = hweight8(ctx_sseu.slice_mask);
subslices = hweight8(ctx_sseu.subslice_mask);
--
2.19.1
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[Intel-gfx] [PATCH 1/6] drm/i915/execlists: Move RPCS setup to context pin
From: Tvrtko Ursulin
Configuring RPCS in context image just before pin is sufficient and will
come extra handy in one of the following patches.
v2:
* Split image setup a bit differently. (Chris Wilson)
v3:
* Update context image after reset as well - otherwise the application
of pinned default state clears the RPCS.
v4:
* Use local variable throughout the function. (Chris Wilson)
Signed-off-by: Tvrtko Ursulin
Suggested-by: Chris Wilson
Cc: Chris Wilson
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_lrc.c | 45
1 file changed, 28 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 08fd9b12e4d7..ab75088697a3 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1152,6 +1152,24 @@ static int __context_pin(struct i915_gem_context *ctx,
struct i915_vma *vma)
return i915_vma_pin(vma, 0, 0, flags);
}
+static u32 make_rpcs(struct drm_i915_private *dev_priv);
+
+static void
+__execlists_update_reg_state(struct intel_engine_cs *engine,
+struct intel_context *ce)
+{
+ u32 *regs = ce->lrc_reg_state;
+ struct intel_ring *ring = ce->ring;
+
+ regs[CTX_RING_BUFFER_START + 1] = i915_ggtt_offset(ring->vma);
+ regs[CTX_RING_HEAD + 1] = ring->head;
+ regs[CTX_RING_TAIL + 1] = ring->tail;
+
+ /* RPCS */
+ if (engine->class == RENDER_CLASS)
+ regs[CTX_R_PWR_CLK_STATE + 1] = make_rpcs(engine->i915);
+}
+
static struct intel_context *
__execlists_context_pin(struct intel_engine_cs *engine,
struct i915_gem_context *ctx,
@@ -1190,10 +1208,8 @@ __execlists_context_pin(struct intel_engine_cs *engine,
GEM_BUG_ON(!intel_ring_offset_valid(ce->ring, ce->ring->head));
ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
- ce->lrc_reg_state[CTX_RING_BUFFER_START+1] =
- i915_ggtt_offset(ce->ring->vma);
- ce->lrc_reg_state[CTX_RING_HEAD + 1] = ce->ring->head;
- ce->lrc_reg_state[CTX_RING_TAIL + 1] = ce->ring->tail;
+
+ __execlists_update_reg_state(engine, ce);
ce->state->obj->pin_global++;
i915_gem_context_get(ctx);
@@ -1803,14 +1819,14 @@ static void execlists_reset(struct intel_engine_cs
*engine,
engine->pinned_default_state + LRC_STATE_PN * PAGE_SIZE,
engine->context_size - PAGE_SIZE);
}
- execlists_init_reg_state(regs,
-request->gem_context, engine, request->ring);
/* Move the RING_HEAD onto the breadcrumb, past the hanging batch */
- regs[CTX_RING_BUFFER_START + 1] = i915_ggtt_offset(request->ring->vma);
-
request->ring->head = intel_ring_wrap(request->ring, request->postfix);
- regs[CTX_RING_HEAD + 1] = request->ring->head;
+
+ execlists_init_reg_state(regs, request->gem_context, engine,
+request->ring);
+
+ __execlists_update_reg_state(engine, request->hw_context);
intel_ring_update_space(request->ring);
@@ -2560,8 +2576,7 @@ static void execlists_init_reg_state(u32 *regs,
if (rcs) {
regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
- CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
- make_rpcs(dev_priv));
+ CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, 0);
i915_oa_init_reg_state(engine, ctx, regs);
}
@@ -2722,12 +2737,8 @@ void intel_lr_context_resume(struct drm_i915_private
*i915)
intel_ring_reset(ce->ring, 0);
- if (ce->pin_count) { /* otherwise done in context_pin */
- u32 *regs = ce->lrc_reg_state;
-
- regs[CTX_RING_HEAD + 1] = ce->ring->head;
- regs[CTX_RING_TAIL + 1] = ce->ring->tail;
- }
+ if (ce->pin_count) /* otherwise done in context_pin */
+ __execlists_update_reg_state(engine, ce);
}
}
}
--
2.19.1
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[Intel-gfx] [PATCH 4/6] drm/i915: Add timeline barrier support
From: Tvrtko Ursulin
Timeline barrier allows serialization between different timelines.
After calling i915_timeline_set_barrier with a request, all following
submissions on this timeline will be set up as depending on this request,
or barrier. Once the barrier has been completed it automatically gets
cleared and things continue as normal.
This facility will be used by the upcoming context SSEU code.
v2:
* Assert barrier has been retired on timeline_fini. (Chris Wilson)
* Fix mock_timeline.
Signed-off-by: Tvrtko Ursulin
Suggested-by: Chris Wilson
Cc: Chris Wilson
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_request.c | 13 +
drivers/gpu/drm/i915/i915_timeline.c | 3 +++
drivers/gpu/drm/i915/i915_timeline.h | 27 +++
.../gpu/drm/i915/selftests/mock_timeline.c| 2 ++
4 files changed, 45 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 71107540581d..d1b2ebfc0ff3 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -563,6 +563,15 @@ submit_notify(struct i915_sw_fence *fence, enum
i915_sw_fence_notify state)
return NOTIFY_DONE;
}
+static int add_timeline_barrier(struct i915_request *rq)
+{
+ struct i915_request *barrier =
+ i915_gem_active_raw(>timeline->barrier,
+ >i915->drm.struct_mutex);
+
+ return barrier ? i915_request_await_dma_fence(rq, >fence) : 0;
+}
+
/**
* i915_request_alloc - allocate a request structure
*
@@ -716,6 +725,10 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
*/
rq->head = rq->ring->emit;
+ ret = add_timeline_barrier(rq);
+ if (ret)
+ goto err_unwind;
+
/* Unconditionally invalidate GPU caches and TLBs. */
ret = engine->emit_flush(rq, EMIT_INVALIDATE);
if (ret)
diff --git a/drivers/gpu/drm/i915/i915_timeline.c
b/drivers/gpu/drm/i915/i915_timeline.c
index 4667cc08c416..5a87c5bd5154 100644
--- a/drivers/gpu/drm/i915/i915_timeline.c
+++ b/drivers/gpu/drm/i915/i915_timeline.c
@@ -37,6 +37,8 @@ void i915_timeline_init(struct drm_i915_private *i915,
INIT_LIST_HEAD(>requests);
i915_syncmap_init(>sync);
+
+ init_request_active(>barrier, NULL);
}
/**
@@ -69,6 +71,7 @@ void i915_timelines_park(struct drm_i915_private *i915)
void i915_timeline_fini(struct i915_timeline *timeline)
{
GEM_BUG_ON(!list_empty(>requests));
+ GEM_BUG_ON(i915_gem_active_isset(>barrier));
i915_syncmap_free(>sync);
diff --git a/drivers/gpu/drm/i915/i915_timeline.h
b/drivers/gpu/drm/i915/i915_timeline.h
index a2c2c3ab5fb0..c8526ab44dbc 100644
--- a/drivers/gpu/drm/i915/i915_timeline.h
+++ b/drivers/gpu/drm/i915/i915_timeline.h
@@ -72,6 +72,16 @@ struct i915_timeline {
*/
u32 global_sync[I915_NUM_ENGINES];
+ /**
+* Barrier provides the ability to serialize ordering between different
+* timelines.
+*
+* Users can call i915_timeline_set_barrier which will make all
+* subsequent submissions be executed only after this barrier has been
+* completed.
+*/
+ struct i915_gem_active barrier;
+
struct list_head link;
const char *name;
@@ -125,4 +135,21 @@ static inline bool i915_timeline_sync_is_later(struct
i915_timeline *tl,
void i915_timelines_park(struct drm_i915_private *i915);
+/**
+ * i915_timeline_set_barrier - orders submission between different timelines
+ * @timeline: timeline to set the barrier on
+ * @rq: request after which new submissions can proceed
+ *
+ * Sets the passed in request as the serialization point for all subsequent
+ * submissions on @timeline. Subsequent requests will not be submitted to GPU
+ * until the barrier has been completed.
+ */
+static inline void
+i915_timeline_set_barrier(struct i915_timeline *timeline,
+ struct i915_request *rq)
+{
+ GEM_BUG_ON(timeline->fence_context == rq->timeline->fence_context);
+ i915_gem_active_set(>barrier, rq);
+}
+
#endif
diff --git a/drivers/gpu/drm/i915/selftests/mock_timeline.c
b/drivers/gpu/drm/i915/selftests/mock_timeline.c
index dcf3b16f5a07..a718b64c988e 100644
--- a/drivers/gpu/drm/i915/selftests/mock_timeline.c
+++ b/drivers/gpu/drm/i915/selftests/mock_timeline.c
@@ -19,6 +19,8 @@ void mock_timeline_init(struct i915_timeline *timeline, u64
context)
i915_syncmap_init(>sync);
+ init_request_active(>barrier, NULL);
+
INIT_LIST_HEAD(>link);
}
--
2.19.1
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[Intel-gfx] [PATCH 3/6] drm/i915/perf: lock powergating configuration to default when active
From: Lionel Landwerlin
If some of the contexts submitting workloads to the GPU have been
configured to shutdown slices/subslices, we might loose the NOA
configurations written in the NOA muxes.
One possible solution to this problem is to reprogram the NOA muxes
when we switch to a new context. We initially tried this in the
workaround batchbuffer but some concerns where raised about the cost
of reprogramming at every context switch. This solution is also not
without consequences from the userspace point of view. Reprogramming
of the muxes can only happen once the powergating configuration has
changed (which happens after context switch). This means for a window
of time during the recording, counters recorded by the OA unit might
be invalid. This requires userspace dealing with OA reports to discard
the invalid values.
Minimizing the reprogramming could be implemented by tracking of the
last programmed configuration somewhere in GGTT and use MI_PREDICATE
to discard some of the programming commands, but the command streamer
would still have to parse all the MI_LRI instructions in the
workaround batchbuffer.
Another solution, which this change implements, is to simply disregard
the user requested configuration for the period of time when i915/perf
is active. There is no known issue with this apart from a performance
penality for some media workloads that benefit from running on a
partially powergated GPU. We already prevent RC6 from affecting the
programming so it doesn't sound completely unreasonable to hold on
powergating for the same reason.
v2: Leave RPCS programming in intel_lrc.c (Lionel)
v3: Update for s/union intel_sseu/struct intel_sseu/ (Lionel)
More to_intel_context() (Tvrtko)
s/dev_priv/i915/ (Tvrtko)
Tvrtko Ursulin:
v4:
* Rebase for make_rpcs changes.
v5:
* Apply OA restriction from make_rpcs directly.
v6:
* Rebase for context image setup changes.
v7:
* Move stream assignment before metric enable.
v8-9:
* Rebase.
Signed-off-by: Lionel Landwerlin
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_perf.c | 13 +
drivers/gpu/drm/i915/intel_lrc.c | 31 ---
drivers/gpu/drm/i915/intel_lrc.h | 2 ++
3 files changed, 31 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 2c2b63be7a6c..627a83af2288 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1677,6 +1677,11 @@ static void gen8_update_reg_state_unlocked(struct
i915_gem_context *ctx,
CTX_REG(reg_state, state_offset, flex_regs[i], value);
}
+
+ CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
+ gen8_make_rpcs(dev_priv,
+ _intel_context(ctx,
+dev_priv->engine[RCS])->sseu));
}
/*
@@ -2098,21 +2103,21 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
if (ret)
goto err_lock;
+ stream->ops = _oa_stream_ops;
+ dev_priv->perf.oa.exclusive_stream = stream;
+
ret = dev_priv->perf.oa.ops.enable_metric_set(stream);
if (ret) {
DRM_DEBUG("Unable to enable metric set\n");
goto err_enable;
}
- stream->ops = _oa_stream_ops;
-
- dev_priv->perf.oa.exclusive_stream = stream;
-
mutex_unlock(_priv->drm.struct_mutex);
return 0;
err_enable:
+ dev_priv->perf.oa.exclusive_stream = NULL;
dev_priv->perf.oa.ops.disable_metric_set(dev_priv);
mutex_unlock(_priv->drm.struct_mutex);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index dc1e08b72446..ee02c593a72c 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1152,9 +1152,6 @@ static int __context_pin(struct i915_gem_context *ctx,
struct i915_vma *vma)
return i915_vma_pin(vma, 0, 0, flags);
}
-static u32
-make_rpcs(struct drm_i915_private *i915, struct intel_sseu *ctx_sseu);
-
static void
__execlists_update_reg_state(struct intel_engine_cs *engine,
struct intel_context *ce)
@@ -1168,8 +1165,8 @@ __execlists_update_reg_state(struct intel_engine_cs
*engine,
/* RPCS */
if (engine->class == RENDER_CLASS)
- regs[CTX_R_PWR_CLK_STATE + 1] = make_rpcs(engine->i915,
- >sseu);
+ regs[CTX_R_PWR_CLK_STATE + 1] = gen8_make_rpcs(engine->i915,
+ >sseu);
}
static struct intel_context *
@@ -2358,13 +2355,12 @@ int logical_xcs_ring_init(struct intel_engine_cs
*engine)
return logical_ring_init(engine);
}
-static u32
-make_rpcs(struct drm_i915_private *i915, struct intel_sseu *ctx_sseu)
+u32 gen8_make_rpcs(struct drm_i915_private *i915, struct
[Intel-gfx] [PATCH 5/6] drm/i915: Expose RPCS (SSEU) configuration to userspace (Gen11 only)
From: Tvrtko Ursulin
We want to allow userspace to reconfigure the subslice configuration on a
per context basis.
This is required for the functional requirement of shutting down non-VME
enabled sub-slices on Gen11 parts.
To do so, we expose a context parameter to allow adjustment of the RPCS
register stored within the context image (and currently not accessible via
LRI).
If the context is adjusted before first use or whilst idle, the adjustment
is for "free"; otherwise if the context is active we queue a request to do
so (using the kernel context), following all other activity by that
context, which is also marked as barrier for all following submission
against the same context.
Since the overhead of device re-configuration during context switching can
be significant, especially in multi-context workloads, we limit this new
uAPI to only support the Gen11 VME use case. In this use case either the
device is fully enabled, and exactly one slice and half of the subslices
are enabled.
Example usage:
struct drm_i915_gem_context_param_sseu sseu = { };
struct drm_i915_gem_context_param arg =
{ .param = I915_CONTEXT_PARAM_SSEU,
.ctx_id = gem_context_create(fd),
.size = sizeof(sseu),
.value = to_user_pointer()
};
/* Query device defaults. */
gem_context_get_param(fd, );
/* Set VME configuration on a 1x6x8 part. */
sseu.slice_mask = 0x1;
sseu.subslice_mask = 0xe0;
gem_context_set_param(fd, );
v2: Fix offset of CTX_R_PWR_CLK_STATE in intel_lr_context_set_sseu() (Lionel)
v3: Add ability to program this per engine (Chris)
v4: Move most get_sseu() into i915_gem_context.c (Lionel)
v5: Validate sseu configuration against the device's capabilities (Lionel)
v6: Change context powergating settings through MI_SDM on kernel context (Chris)
v7: Synchronize the requests following a powergating setting change using a
global
dependency (Chris)
Iterate timelines through dev_priv.gt.active_rings (Tvrtko)
Disable RPCS configuration setting for non capable users (Lionel/Tvrtko)
v8: s/union intel_sseu/struct intel_sseu/ (Lionel)
s/dev_priv/i915/ (Tvrtko)
Change uapi class/instance fields to u16 (Tvrtko)
Bump mask fields to 64bits (Lionel)
Don't return EPERM when dynamic sseu is disabled (Tvrtko)
v9: Import context image into kernel context's ppgtt only when
reconfiguring powergated slice/subslices (Chris)
Use aliasing ppgtt when needed (Michel)
Tvrtko Ursulin:
v10:
* Update for upstream changes.
* Request submit needs a RPM reference.
* Reject on !FULL_PPGTT for simplicity.
* Pull out get/set param to helpers for readability and less indent.
* Use i915_request_await_dma_fence in add_global_barrier to skip waits
on the same timeline and avoid GEM_BUG_ON.
* No need to explicitly assign a NULL pointer to engine in legacy mode.
* No need to move gen8_make_rpcs up.
* Factored out global barrier as prep patch.
* Allow to only CAP_SYS_ADMIN if !Gen11.
v11:
* Remove engine vfunc in favour of local helper. (Chris Wilson)
* Stop retiring requests before updates since it is not needed
(Chris Wilson)
* Implement direct CPU update path for idle contexts. (Chris Wilson)
* Left side dependency needs only be on the same context timeline.
(Chris Wilson)
* It is sufficient to order the timeline. (Chris Wilson)
* Reject !RCS configuration attempts with -ENODEV for now.
v12:
* Rebase for make_rpcs.
v13:
* Centralize SSEU normalization to make_rpcs.
* Type width checking (uAPI <-> implementation).
* Gen11 restrictions uAPI checks.
* Gen11 subslice count differences handling.
Chris Wilson:
* args->size handling fixes.
* Update context image from GGTT.
* Postpone context image update to pinning.
* Use i915_gem_active_raw instead of last_request_on_engine.
v14:
* Add activity tracker on intel_context to fix the lifetime issues
and simplify the code. (Chris Wilson)
v15:
* Fix context pin leak if no space in ring by simplifying the
context pinning sequence.
v16:
* Rebase for context get/set param locking changes.
* Just -ENODEV on !Gen11. (Joonas)
v17:
* Fix one Gen11 subslice enablement rule.
* Handle error from i915_sw_fence_await_sw_fence_gfp. (Chris Wilson)
v18:
* Update commit message. (Joonas)
* Restrict uAPI to VME use case. (Joonas)
v19:
* Rebase.
v20:
* Rebase for ce->active_tracker.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100899
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107634
Issue: https://github.com/intel/media-driver/issues/267
Signed-off-by: Chris Wilson
Signed-off-by: Lionel Landwerlin
Cc: Dmitry Rogozhkin
Cc: Tvrtko Ursulin
Cc: Zhipeng Gong
Cc: Joonas Lahtinen
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_context.c | 341 +++-
drivers/gpu/drm/i915/i915_gem_context.h | 6 +
[Intel-gfx] [PATCH 2/6] drm/i915: Record the sseu configuration per-context & engine
From: Lionel Landwerlin
We want to expose the ability to reconfigure the slices, subslice and
eu per context and per engine. To facilitate that, store the current
configuration on the context for each engine, which is initially set
to the device default upon creation.
v2: record sseu configuration per context & engine (Chris)
v3: introduce the i915_gem_context_sseu to store powergating
programming, sseu_dev_info has grown quite a bit (Lionel)
v4: rename i915_gem_sseu into intel_sseu (Chris)
use to_intel_context() (Chris)
v5: More to_intel_context() (Tvrtko)
Switch intel_sseu from union to struct (Tvrtko)
Move context default sseu in existing loop (Chris)
v6: s/intel_sseu_from_device_sseu/intel_device_default_sseu/ (Tvrtko)
Tvrtko Ursulin:
v7:
* Pass intel_sseu by pointer instead of value to make_rpcs.
* Rebase for make_rpcs changes.
v8:
* Rebase for RPCS edit on pin.
v9:
* Rebase for context image setup changes.
v10:
* Rename dev_priv to i915. (Chris Wilson)
v11:
* Rebase.
Signed-off-by: Chris Wilson
Signed-off-by: Lionel Landwerlin
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 14 +++
drivers/gpu/drm/i915/i915_gem_context.c | 2 ++
drivers/gpu/drm/i915/i915_gem_context.h | 4
drivers/gpu/drm/i915/i915_request.h | 10
drivers/gpu/drm/i915/intel_lrc.c| 31 +
5 files changed, 46 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 08d25aa480f7..6d5bf6173cd3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3471,6 +3471,20 @@ mkwrite_device_info(struct drm_i915_private *dev_priv)
return (struct intel_device_info *)_priv->info;
}
+static inline struct intel_sseu
+intel_device_default_sseu(struct drm_i915_private *i915)
+{
+ const struct sseu_dev_info *sseu = _INFO(i915)->sseu;
+ struct intel_sseu value = {
+ .slice_mask = sseu->slice_mask,
+ .subslice_mask = sseu->subslice_mask[0],
+ .min_eus_per_subslice = sseu->max_eus_per_subslice,
+ .max_eus_per_subslice = sseu->max_eus_per_subslice,
+ };
+
+ return value;
+}
+
/* modesetting */
extern void intel_modeset_init_hw(struct drm_device *dev);
extern int intel_modeset_init(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index b97963db0287..c8d09fdea49f 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -343,6 +343,8 @@ __create_hw_context(struct drm_i915_private *dev_priv,
struct intel_context *ce = >__engine[n];
ce->gem_context = ctx;
+ /* Use the whole device by default */
+ ce->sseu = intel_device_default_sseu(dev_priv);
}
INIT_RADIX_TREE(>handles_vma, GFP_KERNEL);
diff --git a/drivers/gpu/drm/i915/i915_gem_context.h
b/drivers/gpu/drm/i915/i915_gem_context.h
index f6d870b1f73e..ef04e422cf9a 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/i915_gem_context.h
@@ -31,6 +31,7 @@
#include "i915_gem.h"
#include "i915_scheduler.h"
+#include "intel_device_info.h"
struct pid;
@@ -171,6 +172,9 @@ struct i915_gem_context {
int pin_count;
const struct intel_context_ops *ops;
+
+ /** sseu: Control eu/slice partitioning */
+ struct intel_sseu sseu;
} __engine[I915_NUM_ENGINES];
/** ring_size: size for allocating the per-engine ring buffer */
diff --git a/drivers/gpu/drm/i915/i915_request.h
b/drivers/gpu/drm/i915/i915_request.h
index 90e9d170a0cd..07aaf9b43716 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -39,6 +39,16 @@ struct drm_i915_gem_object;
struct i915_request;
struct i915_timeline;
+/*
+ * Powergating configuration for a particular (context,engine).
+ */
+struct intel_sseu {
+ u8 slice_mask;
+ u8 subslice_mask;
+ u8 min_eus_per_subslice;
+ u8 max_eus_per_subslice;
+};
+
struct intel_wait {
struct rb_node node;
struct task_struct *tsk;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index ab75088697a3..dc1e08b72446 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1152,7 +1152,8 @@ static int __context_pin(struct i915_gem_context *ctx,
struct i915_vma *vma)
return i915_vma_pin(vma, 0, 0, flags);
}
-static u32 make_rpcs(struct drm_i915_private *dev_priv);
+static u32
+make_rpcs(struct drm_i915_private *i915, struct intel_sseu *ctx_sseu);
static void
__execlists_update_reg_state(struct intel_engine_cs *engine,
@@ -1167,7 +1168,8 @@ __execlists_update_reg_state(struct intel_engine_cs
*engine,
/* RPCS */
if
[Intel-gfx] [PATCH 0/6] Per context dynamic (sub)slice power-gating
From: Tvrtko Ursulin Just a resend since almost two months have passed since the last one and there were some rebases needed due underlying code changes. Nothing major to warrant re-requesting the reviews, or in other words, the series is still fully reviewed. Lionel Landwerlin (2): drm/i915: Record the sseu configuration per-context & engine drm/i915/perf: lock powergating configuration to default when active Tvrtko Ursulin (4): drm/i915/execlists: Move RPCS setup to context pin drm/i915: Add timeline barrier support drm/i915: Expose RPCS (SSEU) configuration to userspace (Gen11 only) drm/i915/icl: Support co-existence between per-context SSEU and OA drivers/gpu/drm/i915/i915_drv.h | 14 + drivers/gpu/drm/i915/i915_gem_context.c | 343 +- drivers/gpu/drm/i915/i915_gem_context.h | 10 + drivers/gpu/drm/i915/i915_perf.c | 13 +- drivers/gpu/drm/i915/i915_request.c | 13 + drivers/gpu/drm/i915/i915_request.h | 10 + drivers/gpu/drm/i915/i915_timeline.c | 3 + drivers/gpu/drm/i915/i915_timeline.h | 27 ++ drivers/gpu/drm/i915/intel_lrc.c | 100 +++-- drivers/gpu/drm/i915/intel_lrc.h | 2 + .../gpu/drm/i915/selftests/mock_timeline.c| 2 + include/uapi/drm/i915_drm.h | 43 +++ 12 files changed, 543 insertions(+), 37 deletions(-) -- 2.19.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
