Re: [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/2] drm/i915: Don't use DDB allocation when choosing gen9 watermark method (rev2)
Hi,
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> Matt Roper
> Sent: keskiviikko 12. joulukuuta 2018 2.05
> To: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with
> [CI,1/2]
> drm/i915: Don't use DDB allocation when choosing gen9 watermark method
> (rev2)
>
> The rc6 pass->skip mentioned below doesn't appear to be related to this
> series,
> so pushing to dinq. Thanks to Ville for reviewing.
>
> I also notice that CI indicates a bunch of pre-existing ICL watermark
> failures are
> no longer happening with my series (or the earlier revisions of my series),
> so it's
> possible that we've also fixed
> https://bugs.freedesktop.org/show_bug.cgi?id=107724 "by accident" with this
> series.
Thanks Matt! Let's hope so.
>
>
> Matt
>
> On Tue, Dec 11, 2018 at 11:48:05PM +, Patchwork wrote:
> > == Series Details ==
> >
> > Series: series starting with [CI,1/2] drm/i915: Don't use DDB allocation
> > when
> choosing gen9 watermark method (rev2)
> > URL : https://patchwork.freedesktop.org/series/53901/
> > State : success
> >
> > == Summary ==
> >
> > CI Bug Log - changes from CI_DRM_5296_full -> Patchwork_11069_full
> >
> >
> > Summary
> > ---
> >
> > **WARNING**
> >
> > Minor unknown changes coming with Patchwork_11069_full need to be
> verified
> > manually.
> >
> > If you think the reported changes have nothing to do with the changes
> > introduced in Patchwork_11069_full, please notify your bug team to allow
> them
> > to document this new failure mode, which will reduce false positives in
> > CI.
> >
> >
> >
> > Possible new issues
> > ---
> >
> > Here are the unknown changes that may have been introduced in
> Patchwork_11069_full:
> >
> > ### IGT changes ###
> >
> > Warnings
> >
> > * igt@pm_rc6_residency@rc6-accuracy:
> > - shard-snb: PASS -> SKIP
> >
> > * igt@tools_test@tools_test:
> > - shard-skl: SKIP -> PASS
> >
> >
> > Known issues
> >
> >
> > Here are the changes found in Patchwork_11069_full that come from known
> issues:
> >
> > ### IGT changes ###
> >
> > Issues hit
> >
> > * igt@gem_userptr_blits@readonly-unsync:
> > - {shard-iclb}: PASS -> INCOMPLETE [fdo#108342]
> >
> > * igt@i915_selftest@live_contexts:
> > - {shard-iclb}: NOTRUN -> DMESG-FAIL [fdo#108569]
> >
> > * igt@kms_busy@extended-modeset-hang-newfb-render-b:
> > - shard-skl: NOTRUN -> DMESG-WARN [fdo#107956]
> > - {shard-iclb}: NOTRUN -> DMESG-WARN [fdo#107956]
> >
> > * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
> > - {shard-iclb}: PASS -> DMESG-WARN [fdo#107956]
> >
> > * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
> > - shard-glk: NOTRUN -> DMESG-WARN [fdo#107956]
> >
> > * igt@kms_chv_cursor_fail@pipe-b-256x256-right-edge:
> > - {shard-iclb}: PASS -> DMESG-WARN [fdo#107724] / [fdo#108336] +10
> >
> > * igt@kms_color@pipe-a-degamma:
> > - shard-apl: PASS -> FAIL [fdo#104782] / [fdo#108145]
> >
> > * igt@kms_color@pipe-b-degamma:
> > - shard-apl: PASS -> FAIL [fdo#104782]
> >
> > * igt@kms_color@pipe-b-gamma:
> > - shard-skl: PASS -> FAIL [fdo#104782]
> >
> > * igt@kms_color@pipe-c-ctm-green-to-red:
> > - shard-skl: PASS -> FAIL [fdo#107201]
> >
> > * igt@kms_cursor_crc@cursor-64x21-random:
> > - shard-apl: PASS -> FAIL [fdo#103232] +11
> >
> > * igt@kms_cursor_crc@cursor-64x64-suspend:
> > - shard-apl: PASS -> FAIL [fdo#103191] / [fdo#103232]
> >
> > * igt@kms_draw_crc@draw-method-rgb565-pwrite-ytiled:
> > - {shard-iclb}: PASS -> FAIL [fdo#103184]
> >
> > * igt@kms_draw_crc@draw-method-xrgb2101010-render-ytiled:
> > - {shard-iclb}: PASS -> WARN [fdo#108336] +2
> >
> > * igt@kms_fbcon_fbt@psr-suspend:
> > - shard-skl: NOTRUN -> FAIL [fdo#107882]
> >
> > * igt@kms_flip@flip-vs-expired-vblank-interruptible:
> > - shard-skl: PASS -> FAIL [fdo#105363]
> >
> > * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-gtt:
> > - {shard-iclb}: PASS -> DMESG-FAIL [fdo#107724] +16
> >
> > * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
> > - shard-apl: PASS -> FAIL [fdo#103167] +5
> >
> > * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc:
> > - shard-glk: PASS -> FAIL [fdo#103167] +2
> >
> > * igt@kms_frontbuffer_tracking@fbc-stridechange:
> > - {shard-iclb}: PASS -> FAIL [fdo#105683] / [fdo#108040]
> >
> > * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-render:
> > - {shard-iclb}: PASS -> FAIL [fdo#103167] +3
> >
> > *
Re: [Intel-gfx] [PATCH v3 0/4] Dynamic EU configuration of Slice/Subslice/EU.
Hi Tvrtko, On Tue, Dec 11, 2018 at 5:18 PM Tvrtko Ursulin wrote: > > > On 11/12/2018 10:14, Ankit Navik wrote: > > drm/i915: Context aware user agnostic EU/Slice/Sub-slice control > > within kernel > > > > Current GPU configuration code for i915 does not allow us to change > > EU/Slice/Sub-slice configuration dynamically. Its done only once while > > context is created. > > > > While particular graphics application is running, if we examine the > > command requests from user space, we observe that command density is not > consistent. > > It means there is scope to change the graphics configuration > > dynamically even while context is running actively. This patch series > > proposes the solution to find the active pending load for all active > > context at given time and based on that, dynamically perform graphics > configuration for each context. > > > > We use a hr (high resolution) timer with i915 driver in kernel to get > > a callback every few milliseconds (this timer value can be configured > > through debugfs, default is '0' indicating timer is in disabled state > > i.e. original system without any intervention).In the timer callback, > > we examine pending commands for a context in the queue, essentially, > > we intercept them before they are executed by GPU and we update context > with required number of EUs. > > > > Two questions, how did we arrive at right timer value? and what's the > > right number of EUs? For the prior one, empirical data to achieve best > > performance in least power was considered. For the later one, we > > roughly categorized number of EUs logically based on platform. Now we > > compare number of pending commands with a particular threshold and > > then set number of EUs accordingly with update context. That threshold > > is also based on experiments & findings. If GPU is able to catch up > > with CPU, typically there are no pending commands, the EU config would > > remain unchanged there. In case there are more pending commands we > > reprogram context with higher number of EUs. Please note, here we are > changing EUs even while context is running by examining pending commands > every 'x' > > milliseconds. > > > > With this solution in place, on KBL-GT3 + Android we saw following pnp > > benefits, power numbers mentioned here are system power. > > > > App /KPI | % Power | > > | Benefit | > > | (mW) | > > -| > > 3D Mark (Ice storm)| 2.30% | > > TRex On screen | 2.49% | > > TRex Off screen| 1.32% | > > ManhattanOn screen | 3.11% | > > Manhattan Off screen | 0.89% | > > AnTuTu 6.1.4 | 3.42% | > > SynMark2 | 1.70% | > > Is this the aggregated SynMark2 result, like all sub-tests averaged or > something? Yes, It is averaged result covering all the test cases. > > I suggest you do want to list much more detail here, all individual sub-tests, > different platforms, etc. The change you are proposing is quite big and the > amount of research that you must demonstrate for people to take this seriously > has to be equally exhaustive. I will verify and add more details covering various platform and sub-tests. Regards, Ankit > > Regards, > > Tvrtko > > > > > Note - For KBL (GEN9) we cannot control at sub-slice level, it was > > always a constraint. > > We always controlled number of EUs rather than sub-slices/slices. > > We have also observed GPU core residencies improves by 1.03%. > > > > Praveen Diwakar (4): > >drm/i915: Get active pending request for given context > >drm/i915: Update render power clock state configuration for given > > context > >drm/i915: set optimum eu/slice/sub-slice configuration based on load > > type > >drm/i915: Predictive governor to control eu/slice/subslice > > > > drivers/gpu/drm/i915/i915_debugfs.c | 90 > +++- > > drivers/gpu/drm/i915/i915_drv.c | 4 ++ > > drivers/gpu/drm/i915/i915_drv.h | 9 > > drivers/gpu/drm/i915/i915_gem_context.c | 23 > > drivers/gpu/drm/i915/i915_gem_context.h | 39 ++ > > drivers/gpu/drm/i915/i915_request.c | 2 + > > drivers/gpu/drm/i915/intel_device_info.c | 47 - > > drivers/gpu/drm/i915/intel_lrc.c | 16 +- > > 8 files changed, 226 insertions(+), 4 deletions(-) > > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 3/4] drm/i915: set optimum eu/slice/sub-slice configuration based on load type
Hi Tvrtko,
> On Tue, Dec 11, 2018 at 6:17 PM Tvrtko Ursulin
> wrote:
>
>
> On 11/12/2018 10:14, Ankit Navik wrote:
> > From: Praveen Diwakar
> >
> > This patch will select optimum eu/slice/sub-slice configuration based
> > on type of load (low, medium, high) as input.
> > Based on our readings and experiments we have predefined set of
> > optimum configuration for each platform(CHT, KBL).
> > i915_gem_context_set_load_type will select optimum configuration from
> > pre-defined optimum configuration table(opt_config).
> >
> > It also introduce flag update_render_config which can set by any governor.
> >
> > v2:
> > * Move static optimum_config to device init time.
> > * Rename function to appropriate name, fix data types and patch ordering.
> > * Rename prev_load_type to pending_load_type. (Tvrtko Ursulin)
> >
> > v3:
> > * Add safe guard check in i915_gem_context_set_load_type.
> > * Rename struct from optimum_config to i915_sseu_optimum_config to
> > avoid namespace clashes.
> > * Reduces memcpy for space efficient.
> > * Rebase.
> > * Improved commit message. (Tvrtko Ursulin)
> >
> > Cc: Kedar J Karanje
> > Cc: Yogesh Marathe
> > Reviewed-by: Tvrtko Ursulin
>
> Again for the record no, I did not r-b this.
Sorry, I wasn't aware that r-b has to be added by reviewer. Will take care in
next patch sets.
>
> > Signed-off-by: Praveen Diwakar
> > Signed-off-by: Aravindan Muthukumar
> > Signed-off-by: Ankit Navik
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 3 ++
> > drivers/gpu/drm/i915/i915_gem_context.c | 18
> > drivers/gpu/drm/i915/i915_gem_context.h | 25 +
> > drivers/gpu/drm/i915/intel_device_info.c | 47
> ++--
> > drivers/gpu/drm/i915/intel_lrc.c | 4 ++-
> > 5 files changed, 94 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h index 4aca534..4b9a8c5 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1681,6 +1681,9 @@ struct drm_i915_private {
> > struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /*
> assume 965 */
> > int num_fence_regs; /* 8 on pre-965, 16 otherwise */
> >
> > + /* optimal slice/subslice/EU configration state */
> > + struct i915_sseu_optimum_config opt_config[LOAD_TYPE_LAST];
>
> Make it a pointer to struct i915_sseu_optimum_config.
Will incorporate this and other reviews in next patch.
>
> > +
> > unsigned int fsb_freq, mem_freq, is_ddr3;
> > unsigned int skl_preferred_vco_freq;
> > unsigned int max_cdclk_freq;
> > diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
> > b/drivers/gpu/drm/i915/i915_gem_context.c
> > index d040858..c0ced72 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_context.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> > @@ -392,10 +392,28 @@ i915_gem_create_context(struct drm_i915_private
> *dev_priv,
> > ctx->subslice_cnt = hweight8(
> > INTEL_INFO(dev_priv)->sseu.subslice_mask[0]);
> > ctx->eu_cnt = INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
> > + ctx->load_type = 0;
> > + ctx->pending_load_type = 0;
>
> Not needed because we zero the allocation and probably depend on untouched
> fields being zero elsewhere.
>
> >
> > return ctx;
> > }
> >
> > +
> > +void i915_gem_context_set_load_type(struct i915_gem_context *ctx,
> > + enum gem_load_type type)
> > +{
> > + struct drm_i915_private *dev_priv = ctx->i915;
> > +
> > + if (GEM_WARN_ON(type > LOAD_TYPE_LAST))
> > + return;
> > +
> > + /* Call opt_config to get correct configuration for eu,slice,subslice */
> > + ctx->slice_cnt = dev_priv->opt_config[type].slice;
> > + ctx->subslice_cnt = dev_priv->opt_config[type].subslice;
> > + ctx->eu_cnt = dev_priv->opt_config[type].eu;
> > + ctx->pending_load_type = type;
> > +}
> > +
> > /**
> >* i915_gem_context_create_gvt - create a GVT GEM context
> >* @dev: drm device *
> > diff --git a/drivers/gpu/drm/i915/i915_gem_context.h
> > b/drivers/gpu/drm/i915/i915_gem_context.h
> > index e000530..a0db13c 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_context.h
> > +++ b/drivers/gpu/drm/i915/i915_gem_context.h
> > @@ -53,6 +53,19 @@ struct intel_context_ops {
> > void (*destroy)(struct intel_context *ce);
> > };
> >
> > +enum gem_load_type {
> > + LOAD_TYPE_LOW,
> > + LOAD_TYPE_MEDIUM,
> > + LOAD_TYPE_HIGH,
> > + LOAD_TYPE_LAST
> > +};
> > +
> > +struct i915_sseu_optimum_config {
> > + u8 slice;
> > + u8 subslice;
> > + u8 eu;
> > +};
> > +
> > /**
> >* struct i915_gem_context - client state
> >*
> > @@ -208,6 +221,16 @@ struct i915_gem_context {
> >
> > /** eu_cnt: used to set the # of eu to be enabled. */
> > u8 eu_cnt;
> > +
> > + /** load_type: The designated load_type (high/medium/low) for a given
> > +* number of pending commands in the command queue.
> > +*/
>
Re: [Intel-gfx] [PATCH 01/10] dma-buf: add new dma_fence_chain container v4
Hi Daniel and Chris,
Could you take a look on all the patches? Can we get your RB or AB on all
patches including igt patch before we submit to drm-misc?
We already fix all existing issues, and also add test case in IGT as your
required.
Btw, the patch set is tested by below tests:
a. vulkan cts " ./deqp-vk -n dEQP-VK. *semaphore*"
b. internal vulkan timeline test
c. libdrm test "sudo ./amdgpu_test -s 9"
d. IGT test, "sudo ./syncobj_basic"
e. IGT test, "sudo ./syncobj_wait"
f. IGT test, "sudo ./syncobj_timeline"
Any other suggestion or requirement is welcome.
-David
> -Original Message-
> From: dri-devel On Behalf Of
> Chunming Zhou
> Sent: Tuesday, December 11, 2018 6:35 PM
> To: Koenig, Christian ; dri-
> de...@lists.freedesktop.org; amd-...@lists.freedesktop.org; intel-
> g...@lists.freedesktop.org
> Cc: Christian König ; Koenig, Christian
>
> Subject: [PATCH 01/10] dma-buf: add new dma_fence_chain container v4
>
> From: Christian König
>
> Lockless container implementation similar to a dma_fence_array, but with
> only two elements per node and automatic garbage collection.
>
> v2: properly document dma_fence_chain_for_each, add
> dma_fence_chain_find_seqno,
> drop prev reference during garbage collection if it's not a chain fence.
> v3: use head and iterator for dma_fence_chain_for_each
> v4: fix reference count in dma_fence_chain_enable_signaling
>
> Signed-off-by: Christian König
> ---
> drivers/dma-buf/Makefile | 3 +-
> drivers/dma-buf/dma-fence-chain.c | 241
> ++
> include/linux/dma-fence-chain.h | 81 ++
> 3 files changed, 324 insertions(+), 1 deletion(-) create mode 100644
> drivers/dma-buf/dma-fence-chain.c create mode 100644 include/linux/dma-
> fence-chain.h
>
> diff --git a/drivers/dma-buf/Makefile b/drivers/dma-buf/Makefile index
> 0913a6ccab5a..1f006e083eb9 100644
> --- a/drivers/dma-buf/Makefile
> +++ b/drivers/dma-buf/Makefile
> @@ -1,4 +1,5 @@
> -obj-y := dma-buf.o dma-fence.o dma-fence-array.o reservation.o seqno-
> fence.o
> +obj-y := dma-buf.o dma-fence.o dma-fence-array.o dma-fence-chain.o \
> + reservation.o seqno-fence.o
> obj-$(CONFIG_SYNC_FILE) += sync_file.o
> obj-$(CONFIG_SW_SYNC)+= sw_sync.o sync_debug.o
> obj-$(CONFIG_UDMABUF)+= udmabuf.o
> diff --git a/drivers/dma-buf/dma-fence-chain.c b/drivers/dma-buf/dma-
> fence-chain.c
> new file mode 100644
> index ..0c5e3c902fa0
> --- /dev/null
> +++ b/drivers/dma-buf/dma-fence-chain.c
> @@ -0,0 +1,241 @@
> +/*
> + * fence-chain: chain fences together in a timeline
> + *
> + * Copyright (C) 2018 Advanced Micro Devices, Inc.
> + * Authors:
> + * Christian König
> + *
> + * This program is free software; you can redistribute it and/or modify
> +it
> + * under the terms of the GNU General Public License version 2 as
> +published by
> + * the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful, but
> +WITHOUT
> + * ANY WARRANTY; without even the implied warranty of
> MERCHANTABILITY
> +or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
> +License for
> + * more details.
> + */
> +
> +#include
> +
> +static bool dma_fence_chain_enable_signaling(struct dma_fence *fence);
> +
> +/**
> + * dma_fence_chain_get_prev - use RCU to get a reference to the
> +previous fence
> + * @chain: chain node to get the previous node from
> + *
> + * Use dma_fence_get_rcu_safe to get a reference to the previous fence
> +of the
> + * chain node.
> + */
> +static struct dma_fence *dma_fence_chain_get_prev(struct
> +dma_fence_chain *chain) {
> + struct dma_fence *prev;
> +
> + rcu_read_lock();
> + prev = dma_fence_get_rcu_safe(>prev);
> + rcu_read_unlock();
> + return prev;
> +}
> +
> +/**
> + * dma_fence_chain_walk - chain walking function
> + * @fence: current chain node
> + *
> + * Walk the chain to the next node. Returns the next fence or NULL if
> +we are at
> + * the end of the chain. Garbage collects chain nodes which are already
> + * signaled.
> + */
> +struct dma_fence *dma_fence_chain_walk(struct dma_fence *fence) {
> + struct dma_fence_chain *chain, *prev_chain;
> + struct dma_fence *prev, *replacement, *tmp;
> +
> + chain = to_dma_fence_chain(fence);
> + if (!chain) {
> + dma_fence_put(fence);
> + return NULL;
> + }
> +
> + while ((prev = dma_fence_chain_get_prev(chain))) {
> +
> + prev_chain = to_dma_fence_chain(prev);
> + if (prev_chain) {
> + if (!dma_fence_is_signaled(prev_chain->fence))
> + break;
> +
> + replacement =
> dma_fence_chain_get_prev(prev_chain);
> + } else {
> + if (!dma_fence_is_signaled(prev))
> + break;
> +
> + replacement = NULL;
> + }
> +
> + tmp
[Intel-gfx] ✓ Fi.CI.IGT: success for Add gamma/degamma LUT validation helpers
== Series Details == Series: Add gamma/degamma LUT validation helpers URL : https://patchwork.freedesktop.org/series/53929/ State : success == Summary == CI Bug Log - changes from CI_DRM_5296_full -> Patchwork_11075_full Summary --- **WARNING** Minor unknown changes coming with Patchwork_11075_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_11075_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_11075_full: ### IGT changes ### Warnings * igt@pm_rc6_residency@rc6-accuracy: - shard-snb: PASS -> SKIP * igt@tools_test@tools_test: - shard-skl: SKIP -> PASS Known issues Here are the changes found in Patchwork_11075_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_create@forked: - shard-apl: PASS -> INCOMPLETE [fdo#103927] * igt@kms_busy@extended-modeset-hang-newfb-render-b: - shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c: - shard-glk: NOTRUN -> DMESG-WARN [fdo#107956] * igt@kms_ccs@pipe-b-crc-primary-basic: - shard-skl: PASS -> FAIL [fdo#107725] * igt@kms_chv_cursor_fail@pipe-b-64x64-right-edge: - shard-skl: PASS -> FAIL [fdo#104671] * igt@kms_color@pipe-a-legacy-gamma: - shard-apl: PASS -> FAIL [fdo#104782] / [fdo#108145] +1 * igt@kms_color@pipe-b-degamma: - shard-apl: PASS -> FAIL [fdo#104782] * igt@kms_color@pipe-c-ctm-green-to-red: - shard-skl: PASS -> FAIL [fdo#107201] * igt@kms_cursor_crc@cursor-256x256-suspend: - shard-skl: PASS -> INCOMPLETE [fdo#104108] * igt@kms_cursor_crc@cursor-64x21-random: - shard-apl: PASS -> FAIL [fdo#103232] +10 * igt@kms_cursor_crc@cursor-64x64-suspend: - shard-apl: PASS -> FAIL [fdo#103191] / [fdo#103232] * igt@kms_fbcon_fbt@psr-suspend: - shard-skl: NOTRUN -> FAIL [fdo#107882] * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-skl: PASS -> FAIL [fdo#105363] * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff: - shard-apl: PASS -> FAIL [fdo#103167] +4 * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-pwrite: - shard-glk: PASS -> FAIL [fdo#103167] +2 * igt@kms_frontbuffer_tracking@fbcpsr-suspend: - shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#106978] * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max: - shard-skl: NOTRUN -> FAIL [fdo#108145] +1 * igt@kms_plane_multiple@atomic-pipe-a-tiling-yf: - shard-glk: PASS -> FAIL [fdo#103166] * igt@kms_sysfs_edid_timing: - shard-skl: NOTRUN -> FAIL [fdo#100047] * igt@pm_rpm@universal-planes: - shard-skl: PASS -> INCOMPLETE [fdo#107807] Possible fixes * igt@gem_userptr_blits@readonly-unsync: - shard-skl: TIMEOUT [fdo#108887] -> PASS * igt@kms_color@pipe-c-degamma: - shard-apl: FAIL [fdo#104782] -> PASS * igt@kms_cursor_crc@cursor-64x21-sliding: - shard-apl: FAIL [fdo#103232] -> PASS +1 * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - shard-skl: INCOMPLETE [fdo#104108] / [fdo#107773] -> PASS * igt@kms_plane@pixel-format-pipe-c-planes: - shard-apl: FAIL [fdo#103166] -> PASS +1 * igt@kms_rotation_crc@sprite-rotation-90: - shard-glk: INCOMPLETE [fdo#103359] / [k.org#198133] -> PASS * igt@kms_setmode@basic: - shard-apl: FAIL [fdo#99912] -> PASS - shard-kbl: FAIL [fdo#99912] -> PASS * igt@perf@blocking: - shard-hsw: FAIL [fdo#102252] -> PASS Warnings * igt@gem_cpu_reloc@full: - shard-skl: INCOMPLETE [fdo#108073] -> TIMEOUT [fdo#108248] [fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047 [fdo#102252]: https://bugs.freedesktop.org/show_bug.cgi?id=102252 [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166 [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232 [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359 [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108 [fdo#104671]: https://bugs.freedesktop.org/show_bug.cgi?id=104671 [fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782 [fdo#105363]:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: correct the pitch check for NV12 framebuffer
== Series Details ==
Series: drm/i915: correct the pitch check for NV12 framebuffer
URL : https://patchwork.freedesktop.org/series/53928/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5296_full -> Patchwork_11074_full
Summary
---
**WARNING**
Minor unknown changes coming with Patchwork_11074_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_11074_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_11074_full:
### IGT changes ###
Warnings
* igt@pm_rc6_residency@rc6-accuracy:
- shard-snb: PASS -> SKIP
Known issues
Here are the changes found in Patchwork_11074_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_contexts:
- {shard-iclb}: NOTRUN -> DMESG-FAIL [fdo#108569]
* igt@kms_busy@extended-modeset-hang-newfb-render-b:
- {shard-iclb}: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
- shard-glk: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_ccs@pipe-b-crc-primary-basic:
- shard-skl: PASS -> FAIL [fdo#107725]
* igt@kms_chv_cursor_fail@pipe-b-64x64-right-edge:
- shard-skl: PASS -> FAIL [fdo#104671]
* igt@kms_color@pipe-a-degamma:
- shard-apl: PASS -> FAIL [fdo#104782] / [fdo#108145]
* igt@kms_color@pipe-b-degamma:
- shard-apl: PASS -> FAIL [fdo#104782]
* igt@kms_color@pipe-b-gamma:
- shard-skl: PASS -> FAIL [fdo#104782]
* igt@kms_color@pipe-c-ctm-green-to-red:
- shard-skl: PASS -> FAIL [fdo#107201]
* igt@kms_cursor_crc@cursor-64x21-random:
- shard-apl: PASS -> FAIL [fdo#103232] +11
* igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-apl: PASS -> FAIL [fdo#103191] / [fdo#103232]
* igt@kms_draw_crc@draw-method-rgb565-render-ytiled:
- shard-skl: PASS -> FAIL [fdo#103184] +1
* igt@kms_draw_crc@draw-method-xrgb-render-ytiled:
- {shard-iclb}: PASS -> WARN [fdo#108336]
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: NOTRUN -> FAIL [fdo#105363]
- shard-glk: PASS -> FAIL [fdo#102887] / [fdo#105363]
* igt@kms_flip@plain-flip-ts-check-interruptible:
- shard-skl: PASS -> FAIL [fdo#100368]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
- shard-apl: PASS -> FAIL [fdo#103167] +5
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-pwrite:
- shard-glk: PASS -> FAIL [fdo#103167] +2
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu:
- {shard-iclb}: PASS -> DMESG-FAIL [fdo#107724]
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt:
- {shard-iclb}: NOTRUN -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-gtt:
- {shard-iclb}: PASS -> FAIL [fdo#103167] +3
* igt@kms_plane@plane-panning-bottom-right-pipe-a-planes:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107724] / [fdo#108336] +1
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- {shard-iclb}: PASS -> DMESG-FAIL [fdo#103166] / [fdo#107724]
* igt@kms_plane@plane-position-covered-pipe-a-planes:
- shard-apl: PASS -> FAIL [fdo#103166] +1
- {shard-iclb}: NOTRUN -> FAIL [fdo#103166]
* igt@kms_plane@plane-position-covered-pipe-b-planes:
- {shard-iclb}: PASS -> FAIL [fdo#103166] +1
* igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
- shard-apl: PASS -> FAIL [fdo#108145]
* igt@kms_psr@no_drrs:
- {shard-iclb}: PASS -> FAIL [fdo#108341]
* igt@kms_sysfs_edid_timing:
- shard-skl: NOTRUN -> FAIL [fdo#100047]
* igt@pm_rpm@gem-evict-pwrite:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107724] +6
* igt@pm_rpm@modeset-lpsp:
- {shard-iclb}: PASS -> INCOMPLETE [fdo#108840]
* igt@pm_rpm@modeset-lpsp-stress:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#108654]
Possible fixes
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
- shard-kbl: DMESG-WARN [fdo#107956] -> PASS
* igt@kms_color@pipe-c-degamma:
- shard-apl: FAIL [fdo#104782] -> PASS
* igt@kms_cursor_crc@cursor-64x21-sliding:
- shard-apl: FAIL [fdo#103232] -> PASS +1
* igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled:
- shard-skl: FAIL [fdo#103184] ->
[Intel-gfx] ✓ Fi.CI.IGT: success for Add HDR Metadata Parsing and handling in DRM layer (rev3)
== Series Details ==
Series: Add HDR Metadata Parsing and handling in DRM layer (rev3)
URL : https://patchwork.freedesktop.org/series/25091/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5296_full -> Patchwork_11073_full
Summary
---
**WARNING**
Minor unknown changes coming with Patchwork_11073_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_11073_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_11073_full:
### IGT changes ###
Warnings
* igt@pm_rc6_residency@rc6-accuracy:
- shard-snb: PASS -> SKIP
* igt@tools_test@tools_test:
- shard-skl: SKIP -> PASS
Known issues
Here are the changes found in Patchwork_11073_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@drm_import_export@import-close-race-flink:
- shard-glk: PASS -> TIMEOUT [fdo#108667]
* igt@gem_eio@in-flight-10ms:
- {shard-iclb}: PASS -> INCOMPLETE [fdo#108343]
* igt@kms_busy@extended-modeset-hang-newfb-render-b:
- {shard-iclb}: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
- shard-glk: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_color@pipe-a-degamma:
- shard-apl: PASS -> FAIL [fdo#104782] / [fdo#108145]
* igt@kms_color@pipe-b-degamma:
- shard-apl: PASS -> FAIL [fdo#104782]
* igt@kms_color@pipe-c-ctm-green-to-red:
- shard-skl: PASS -> FAIL [fdo#107201]
* igt@kms_cursor_crc@cursor-64x21-random:
- shard-apl: PASS -> FAIL [fdo#103232] +11
* igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-apl: PASS -> FAIL [fdo#103191] / [fdo#103232]
* igt@kms_cursor_legacy@pipe-a-torture-move:
- shard-skl: NOTRUN -> INCOMPLETE [fdo#104108]
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-xtiled:
- {shard-iclb}: PASS -> WARN [fdo#108336]
* igt@kms_fbcon_fbt@psr-suspend:
- shard-skl: NOTRUN -> FAIL [fdo#107882]
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: PASS -> FAIL [fdo#105363]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
- shard-apl: PASS -> FAIL [fdo#103167] +5
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render:
- {shard-iclb}: PASS -> DMESG-FAIL [fdo#107724]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
- shard-glk: PASS -> FAIL [fdo#103167] +5
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move:
- {shard-iclb}: PASS -> FAIL [fdo#103167]
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- {shard-iclb}: PASS -> INCOMPLETE [fdo#107713]
* igt@kms_plane@plane-position-covered-pipe-a-planes:
- shard-apl: PASS -> FAIL [fdo#103166] +1
* igt@kms_plane@plane-position-hole-dpms-pipe-a-planes:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107724] / [fdo#108336] +2
* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-glk: PASS -> FAIL [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
- shard-apl: PASS -> FAIL [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
- shard-skl: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_multiple@atomic-pipe-b-tiling-yf:
- {shard-iclb}: PASS -> FAIL [fdo#103166] +2
* igt@kms_plane_multiple@atomic-pipe-c-tiling-x:
- shard-glk: PASS -> FAIL [fdo#103166]
* igt@kms_psr@sprite_plane_move:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107724] +5
* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- shard-skl: NOTRUN -> INCOMPLETE [fdo#104108] / [fdo#107773]
* igt@pm_backlight@basic-brightness:
- {shard-iclb}: PASS -> INCOMPLETE [fdo#107820]
* igt@pm_rpm@legacy-planes:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#108654] +1
* igt@pm_rpm@legacy-planes-dpms:
- shard-skl: PASS -> INCOMPLETE [fdo#105959] / [fdo#107807]
* {igt@runner@aborted}:
- {shard-iclb}: NOTRUN -> ( 2 FAIL ) [fdo#108654] / [fdo#108756]
Possible fixes
* igt@kms_color@pipe-b-ctm-negative:
- shard-skl: FAIL [fdo#107361] -> PASS
* igt@kms_color@pipe-c-degamma:
- shard-apl: FAIL [fdo#104782] -> PASS
* igt@kms_cursor_crc@cursor-64x21-sliding:
- shard-apl: FAIL [fdo#103232] -> PASS +1
*
[Intel-gfx] [drm-tip:drm-tip 5/10] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1666:30: warning: passing argument 1 of 'drm_atomic_private_obj_init' from incompatible pointer type
tree: git://anongit.freedesktop.org/drm/drm-tip drm-tip
head: f7fe8bac92bfd7ceef37f46fbeb9a6c1bac66125
commit: 2c6557b1fc4d6cc24938a27742ac396be7b55e70 [5/10] Merge remote-tracking
branch 'drm-misc/drm-misc-next' into drm-tip
config: i386-randconfig-sb0-12120454 (attached as .config)
compiler: gcc-4.9 (Debian 4.9.4-2) 4.9.4
reproduce:
git checkout 2c6557b1fc4d6cc24938a27742ac396be7b55e70
# save the attached .config to linux build tree
make ARCH=i386
All warnings (new ones prefixed by >>):
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c: In function
'amdgpu_dm_mode_config_init':
>> drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1666:30:
>> warning: passing argument 1 of 'drm_atomic_private_obj_init' from
>> incompatible pointer type
drm_atomic_private_obj_init(>dm.atomic_obj,
^
In file included from include/drm/drm_dp_mst_helper.h:27:0,
from drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h:46,
from drivers/gpu/drm/amd/amdgpu/amdgpu.h:57,
from
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:31:
include/drm/drm_atomic.h:437:6: note: expected 'struct drm_device *' but
argument is of type 'struct drm_private_obj *'
void drm_atomic_private_obj_init(struct drm_device *dev,
^
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1667:9: warning:
passing argument 2 of 'drm_atomic_private_obj_init' from incompatible pointer
type
>base,
^
In file included from include/drm/drm_dp_mst_helper.h:27:0,
from drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h:46,
from drivers/gpu/drm/amd/amdgpu/amdgpu.h:57,
from
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:31:
include/drm/drm_atomic.h:437:6: note: expected 'struct drm_private_obj *'
but argument is of type 'struct drm_private_state *'
void drm_atomic_private_obj_init(struct drm_device *dev,
^
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1668:9: warning:
passing argument 3 of 'drm_atomic_private_obj_init' from incompatible pointer
type
_atomic_state_funcs);
^
In file included from include/drm/drm_dp_mst_helper.h:27:0,
from drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h:46,
from drivers/gpu/drm/amd/amdgpu/amdgpu.h:57,
from
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:31:
include/drm/drm_atomic.h:437:6: note: expected 'struct drm_private_state *'
but argument is of type 'struct drm_private_state_funcs *'
void drm_atomic_private_obj_init(struct drm_device *dev,
^
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1666:2: error:
too few arguments to function 'drm_atomic_private_obj_init'
drm_atomic_private_obj_init(>dm.atomic_obj,
^
In file included from include/drm/drm_dp_mst_helper.h:27:0,
from drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h:46,
from drivers/gpu/drm/amd/amdgpu/amdgpu.h:57,
from
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:31:
include/drm/drm_atomic.h:437:6: note: declared here
void drm_atomic_private_obj_init(struct drm_device *dev,
^
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c: In function
'amdgpu_dm_do_flip':
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:4482:9: warning:
missing braces around initializer [-Wmissing-braces]
struct dc_stream_update stream_update = {0};
^
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:4482:9: warning:
(near initialization for 'stream_update.src') [-Wmissing-braces]
vim +/drm_atomic_private_obj_init +1666
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c
eb3dc897 Nicholas Kazlauskas 2018-11-22 1631
4562236b Harry Wentland 2017-09-12 1632 static int
amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
4562236b Harry Wentland 2017-09-12 1633 {
eb3dc897 Nicholas Kazlauskas 2018-11-22 1634 struct dm_atomic_state *state;
4562236b Harry Wentland 2017-09-12 1635 int r;
4562236b Harry Wentland 2017-09-12 1636
4562236b Harry Wentland 2017-09-12 1637
adev->mode_info.mode_config_initialized = true;
4562236b Harry Wentland 2017-09-12 1638
4562236b Harry Wentland 2017-09-12 1639 adev->ddev->mode_config.funcs =
(void *)_dm_mode_funcs;
54f5499a Andrey Grodzovsky 2017-04-20 1640
adev->ddev->mode_config.helper_private = _dm_mode_config_helperfuncs;
4562236b Harry Wentland 2017-09-12 1641
4562236b Harry Wentland 2017-09-12 1642
adev->ddev->mode_config.max_width = 16384;
4562236b Harry Wentland 2017-09-12 1643
adev->ddev->mode_config.max_height = 16384;
4562236b Harry Wentland 2017-09-12 1644
4562236b Harry Wentland
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/icl: combo port vswing programming changes per BSPEC (rev4)
== Series Details ==
Series: drm/i915/icl: combo port vswing programming changes per BSPEC (rev4)
URL : https://patchwork.freedesktop.org/series/53340/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5296_full -> Patchwork_11072_full
Summary
---
**WARNING**
Minor unknown changes coming with Patchwork_11072_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_11072_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_11072_full:
### IGT changes ###
Warnings
* igt@pm_rc6_residency@rc6-accuracy:
- shard-snb: PASS -> SKIP
* igt@tools_test@tools_test:
- shard-skl: SKIP -> PASS
Known issues
Here are the changes found in Patchwork_11072_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@debugfs_test@read_all_entries_display_off:
- shard-skl: PASS -> INCOMPLETE [fdo#104108]
* igt@i915_selftest@live_contexts:
- {shard-iclb}: NOTRUN -> DMESG-FAIL [fdo#108569]
* igt@kms_atomic_transition@plane-toggle-modeset-transition:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107724] +12
* igt@kms_busy@extended-modeset-hang-newfb-render-b:
- {shard-iclb}: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
- shard-glk: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_chv_cursor_fail@pipe-b-256x256-right-edge:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107724] / [fdo#108336] +5
* igt@kms_color@pipe-a-ctm-max:
- shard-apl: PASS -> FAIL [fdo#108147]
* igt@kms_color@pipe-a-degamma:
- shard-apl: PASS -> FAIL [fdo#104782] / [fdo#108145]
* igt@kms_color@pipe-b-degamma:
- shard-apl: PASS -> FAIL [fdo#104782]
* igt@kms_cursor_crc@cursor-128x128-onscreen:
- shard-apl: PASS -> DMESG-FAIL [fdo#103232] / [fdo#103558] /
[fdo#105602]
* igt@kms_cursor_crc@cursor-64x21-random:
- shard-apl: PASS -> FAIL [fdo#103232] +8
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite:
- shard-apl: PASS -> FAIL [fdo#103167] +2
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff:
- shard-apl: PASS -> DMESG-FAIL [fdo#103167] / [fdo#103558] /
[fdo#105602]
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc:
- shard-glk: PASS -> FAIL [fdo#103167] +4
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-apl: PASS -> FAIL [fdo#103167] / [fdo#105682]
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-cpu:
- {shard-iclb}: PASS -> DMESG-FAIL [fdo#107724] +4
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-gtt:
- {shard-iclb}: PASS -> FAIL [fdo#103167] +3
* igt@kms_plane@plane-position-covered-pipe-a-planes:
- shard-apl: PASS -> FAIL [fdo#103166] +3
* igt@kms_plane@plane-position-covered-pipe-b-planes:
- shard-glk: PASS -> FAIL [fdo#103166] +1
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
- shard-skl: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_multiple@atomic-pipe-c-tiling-y:
- {shard-iclb}: PASS -> FAIL [fdo#103166]
* igt@kms_psr@no_drrs:
- {shard-iclb}: PASS -> FAIL [fdo#108341]
* igt@kms_sysfs_edid_timing:
- shard-skl: NOTRUN -> FAIL [fdo#100047]
* igt@kms_vblank@pipe-c-query-busy:
- shard-apl: PASS -> DMESG-WARN [fdo#103558] / [fdo#105602] +15
* igt@pm_rpm@gem-execbuf-stress:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#108654]
Possible fixes
* igt@gem_ppgtt@blt-vs-render-ctx0:
- shard-skl: TIMEOUT [fdo#108039] -> PASS
* igt@kms_color@pipe-b-ctm-negative:
- shard-skl: FAIL [fdo#107361] -> PASS
* igt@kms_color@pipe-c-degamma:
- shard-apl: FAIL [fdo#104782] -> PASS
* igt@kms_cursor_crc@cursor-64x21-sliding:
- shard-apl: FAIL [fdo#103232] -> PASS +1
* igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled:
- shard-skl: FAIL [fdo#103184] -> PASS
* igt@kms_draw_crc@draw-method-rgb565-render-ytiled:
- {shard-iclb}: WARN [fdo#108336] -> PASS +1
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: FAIL [fdo#103833] / [fdo#105681] -> PASS
* igt@kms_flip@dpms-off-confusion:
- {shard-iclb}: DMESG-WARN [fdo#107724] -> PASS +17
* igt@kms_flip_tiling@flip-changes-tiling:
- {shard-iclb}:
[Intel-gfx] ✓ Fi.CI.BAT: success for Add gamma/degamma LUT validation helpers
== Series Details ==
Series: Add gamma/degamma LUT validation helpers
URL : https://patchwork.freedesktop.org/series/53929/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5296 -> Patchwork_11075
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/53929/revisions/1/mbox/
Known issues
Here are the changes found in Patchwork_11075 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_chamelium@hdmi-hpd-fast:
- {fi-kbl-7500u}: PASS -> FAIL [fdo#108767]
* igt@kms_flip@basic-flip-vs-modeset:
- fi-skl-6700hq: PASS -> DMESG-WARN [fdo#105998] +1
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#105998]: https://bugs.freedesktop.org/show_bug.cgi?id=105998
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#108767]: https://bugs.freedesktop.org/show_bug.cgi?id=108767
Participating hosts (48 -> 43)
--
Additional (1): fi-byt-j1900
Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-ctg-p8600 fi-icl-y
Build changes
-
* Linux: CI_DRM_5296 -> Patchwork_11075
CI_DRM_5296: 70751bd8a3f27b035d203ecafcad452f4d7c2c15 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4745: 3b52e8a5809a4e860350c59476a456745cd9fee0 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11075: a98821b8fc98c4698c74f04a0a3d80444534626f @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
a98821b8fc98 drm/i915: Validate userspace-provided color management LUT's
520a78550419 drm: Add color management LUT validation helpers
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11075/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add gamma/degamma LUT validation helpers
== Series Details == Series: Add gamma/degamma LUT validation helpers URL : https://patchwork.freedesktop.org/series/53929/ State : warning == Summary == $ dim checkpatch origin/drm-tip 520a78550419 drm: Add color management LUT validation helpers -:69: CHECK:SPACING: spaces preferred around that '-' (ctx:VxV) #69: FILE: drivers/gpu/drm/drm_color_mgmt.c:510: + if (entry[i].red < entry[i-1].red || ^ -:70: CHECK:SPACING: spaces preferred around that '-' (ctx:VxV) #70: FILE: drivers/gpu/drm/drm_color_mgmt.c:511: + entry[i].green < entry[i-1].green || ^ -:71: CHECK:SPACING: spaces preferred around that '-' (ctx:VxV) #71: FILE: drivers/gpu/drm/drm_color_mgmt.c:512: + entry[i].blue < entry[i-1].blue) ^ total: 0 errors, 0 warnings, 3 checks, 63 lines checked a98821b8fc98 drm/i915: Validate userspace-provided color management LUT's ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915: Validate userspace-provided color management LUT's
We currently program userspace-provided gamma and degamma LUT's into our
hardware without really checking to see whether they satisfy our
hardware's rules. We should try to catch tables that are invalid for
our hardware early and reject the atomic transaction.
All of our platforms that accept a degamma LUT expect that the entries
in the LUT are always flat or increasing, never decreasing. Also, our
GLK and ICL platforms only accept degamma tables with r=g=b entries; so
we should also add the relevant checks for that in anticipation of
degamma support landing for those platforms.
Cc: Uma Shankar
Cc: Swati Sharma
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/intel_color.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 1d572e83db7f..041bb5d6a6cd 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -610,6 +610,24 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+ /*
+* GLK and gen11 only accept a single value for red, green, and
+* blue in the degamma table. Make sure userspace didn't try to
+* pass us something we can't handle.
+*/
+ if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 11) {
+ if
(!drm_color_lut_has_equal_channels(crtc_state->base.degamma_lut)) {
+ DRM_DEBUG_KMS("All degamma entries must have equal
r/g/b\n");
+ return -EINVAL;
+ }
+ }
+
+ /* All platforms require that the degamma curve be non-decreasing */
+ if (!drm_color_lut_is_increasing(crtc_state->base.degamma_lut)) {
+ DRM_DEBUG_KMS("Degamma curve must never decrease.\n");
+ return -EINVAL;
+ }
+
/*
* We allow both degamma & gamma luts at the right size or
* NULL.
--
2.14.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: correct the pitch check for NV12 framebuffer
== Series Details ==
Series: drm/i915: correct the pitch check for NV12 framebuffer
URL : https://patchwork.freedesktop.org/series/53928/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5296 -> Patchwork_11074
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/53928/revisions/1/mbox/
Known issues
Here are the changes found in Patchwork_11074 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_chamelium@hdmi-hpd-fast:
- {fi-kbl-7500u}: PASS -> FAIL [fdo#108767]
* igt@kms_flip@basic-flip-vs-dpms:
- fi-skl-6700hq: PASS -> DMESG-WARN [fdo#105998]
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362] +1
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-cfl-8109u: PASS -> INCOMPLETE [fdo#106070] / [fdo#108126]
* igt@kms_psr@sprite_plane_onoff:
- fi-skl-6700hq: PASS -> FAIL [fdo#107383] +3
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#105998]: https://bugs.freedesktop.org/show_bug.cgi?id=105998
[fdo#106070]: https://bugs.freedesktop.org/show_bug.cgi?id=106070
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107383]: https://bugs.freedesktop.org/show_bug.cgi?id=107383
[fdo#108126]: https://bugs.freedesktop.org/show_bug.cgi?id=108126
[fdo#108767]: https://bugs.freedesktop.org/show_bug.cgi?id=108767
Participating hosts (48 -> 44)
--
Additional (1): fi-byt-j1900
Missing(5): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-ctg-p8600
Build changes
-
* Linux: CI_DRM_5296 -> Patchwork_11074
CI_DRM_5296: 70751bd8a3f27b035d203ecafcad452f4d7c2c15 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4745: 3b52e8a5809a4e860350c59476a456745cd9fee0 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11074: 0012e602944e9cb0772ac3b8b8222562324e120c @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
0012e602944e drm/i915: correct the pitch check for NV12 framebuffer
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11074/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm: Add color management LUT validation helpers
Some hardware may place additional restrictions on the gamma/degamma
curves described by our LUT properties. E.g., that a gamma curve never
decreases or that the red/green/blue channels of a LUT's entries must be
equal. Let's add a couple helpers that drivers can use to test that a
userspace-provided LUT doesn't violate hardware requirements.
Cc: Uma Shankar
Cc: Swati Sharma
Signed-off-by: Matt Roper
---
drivers/gpu/drm/drm_color_mgmt.c | 53
include/drm/drm_color_mgmt.h | 3 +++
2 files changed, 56 insertions(+)
diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
index 07dcf47daafe..41e617e34c10 100644
--- a/drivers/gpu/drm/drm_color_mgmt.c
+++ b/drivers/gpu/drm/drm_color_mgmt.c
@@ -462,3 +462,56 @@ int drm_plane_create_color_properties(struct drm_plane
*plane,
return 0;
}
EXPORT_SYMBOL(drm_plane_create_color_properties);
+
+/**
+ * drm_color_lut_has_equal_channels - check LUT for equal r/g/b values
+ * @lut: property blob containing LUT to check
+ *
+ * Helper to check whether the entries of a LUT all have equal values for the
+ * red, green, and blue channels. Some hardware can only be programmed
+ * with a single value per LUT entry, which is assumed to apply to all
+ * three color components.
+ */
+bool drm_color_lut_has_equal_channels(struct drm_property_blob *lut)
+{
+ struct drm_color_lut *entry;
+ int i;
+
+ if (!lut)
+ return true;
+
+ entry = lut->data;
+ for (i = 0; i < drm_color_lut_size(lut); i++)
+ if (entry[i].red != entry[i].blue ||
+ entry[i].red != entry[i].green)
+ return false;
+
+ return true;
+}
+EXPORT_SYMBOL(drm_color_lut_has_equal_channels);
+
+/**
+ * drm_color_lut_is_increasing - check that LUT is always flat/increasing
+ * @lut: LUT to check
+ *
+ * Helper to check whether the entries of a LUT are always flat or increasing
+ * (never decreasing).
+ */
+bool drm_color_lut_is_increasing(struct drm_property_blob *lut)
+{
+ struct drm_color_lut *entry;
+ int i;
+
+ if (!lut)
+ return true;
+
+ entry = lut->data;
+ for (i = 1; i < drm_color_lut_size(lut); i++)
+ if (entry[i].red < entry[i-1].red ||
+ entry[i].green < entry[i-1].green ||
+ entry[i].blue < entry[i-1].blue)
+ return false;
+
+ return true;
+}
+EXPORT_SYMBOL(drm_color_lut_is_increasing);
diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h
index 90ef9996d9a4..6c38f5477e29 100644
--- a/include/drm/drm_color_mgmt.h
+++ b/include/drm/drm_color_mgmt.h
@@ -69,4 +69,7 @@ int drm_plane_create_color_properties(struct drm_plane *plane,
u32 supported_ranges,
enum drm_color_encoding default_encoding,
enum drm_color_range default_range);
+
+bool drm_color_lut_has_equal_channels(struct drm_property_blob *lut);
+bool drm_color_lut_is_increasing(struct drm_property_blob *lut);
#endif
--
2.14.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/2] Add gamma/degamma LUT validation helpers
Some platforms require that gamma or degamma LUT's have certain characteristics in order to be programmed into the hardware. If a userspace-provided LUT violates a platform's hardware requirements, we want to be able to catch this during the atomic check and reject the transaction rather than just silently trying to program an invalid table into the hardware. Let's add a couple helpers that can be called by drivers' check functions: - drm_color_lut_is_increasing() checks a table to see whether subsequent entries are always equal to or greater than prior entries (i.e., the gamma ramp never decreases). - drm_color_lut_has_equal_channels() checks a table to see whether the r, g, and b channels are equal for each table entry. On Intel, we need the first helper for the degamma table on all platforms, and we need the second one for the degamma table on GLK and ICL (actual degamma support for those two platforms hasn't landed yet, but there's work in flight by Uma and Swati to add it, so we might as well get the checks ready early). Matt Roper (2): drm: Add color management LUT validation helpers drm/i915: Validate userspace-provided color management LUT's drivers/gpu/drm/drm_color_mgmt.c | 53 ++ drivers/gpu/drm/i915/intel_color.c | 18 + include/drm/drm_color_mgmt.h | 3 +++ 3 files changed, 74 insertions(+) -- 2.14.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [drm-tip:drm-tip 5/10] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1666:30: error: passing argument 1 of 'drm_atomic_private_obj_init' from incompatible pointer type
tree: git://anongit.freedesktop.org/drm/drm-tip drm-tip
head: f7fe8bac92bfd7ceef37f46fbeb9a6c1bac66125
commit: 2c6557b1fc4d6cc24938a27742ac396be7b55e70 [5/10] Merge remote-tracking
branch 'drm-misc/drm-misc-next' into drm-tip
config: x86_64-randconfig-s4-12120354 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
git checkout 2c6557b1fc4d6cc24938a27742ac396be7b55e70
# save the attached .config to linux build tree
make ARCH=x86_64
All errors (new ones prefixed by >>):
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c: In function
'amdgpu_dm_mode_config_init':
>> drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1666:30: error:
>> passing argument 1 of 'drm_atomic_private_obj_init' from incompatible
>> pointer type [-Werror=incompatible-pointer-types]
drm_atomic_private_obj_init(>dm.atomic_obj,
^
In file included from include/drm/drm_dp_mst_helper.h:27:0,
from drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h:46,
from drivers/gpu/drm/amd/amdgpu/amdgpu.h:57,
from
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:31:
include/drm/drm_atomic.h:437:6: note: expected 'struct drm_device *' but
argument is of type 'struct drm_private_obj *'
void drm_atomic_private_obj_init(struct drm_device *dev,
^~~
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1667:9: error:
passing argument 2 of 'drm_atomic_private_obj_init' from incompatible pointer
type [-Werror=incompatible-pointer-types]
>base,
^
In file included from include/drm/drm_dp_mst_helper.h:27:0,
from drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h:46,
from drivers/gpu/drm/amd/amdgpu/amdgpu.h:57,
from
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:31:
include/drm/drm_atomic.h:437:6: note: expected 'struct drm_private_obj *'
but argument is of type 'struct drm_private_state *'
void drm_atomic_private_obj_init(struct drm_device *dev,
^~~
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1668:9: error:
passing argument 3 of 'drm_atomic_private_obj_init' from incompatible pointer
type [-Werror=incompatible-pointer-types]
_atomic_state_funcs);
^
In file included from include/drm/drm_dp_mst_helper.h:27:0,
from drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h:46,
from drivers/gpu/drm/amd/amdgpu/amdgpu.h:57,
from
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:31:
include/drm/drm_atomic.h:437:6: note: expected 'struct drm_private_state *'
but argument is of type 'struct drm_private_state_funcs *'
void drm_atomic_private_obj_init(struct drm_device *dev,
^~~
>> drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1666:2: error:
>> too few arguments to function 'drm_atomic_private_obj_init'
drm_atomic_private_obj_init(>dm.atomic_obj,
^~~
In file included from include/drm/drm_dp_mst_helper.h:27:0,
from drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h:46,
from drivers/gpu/drm/amd/amdgpu/amdgpu.h:57,
from
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:31:
include/drm/drm_atomic.h:437:6: note: declared here
void drm_atomic_private_obj_init(struct drm_device *dev,
^~~
cc1: some warnings being treated as errors
vim +/drm_atomic_private_obj_init +1666
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c
eb3dc897 Nicholas Kazlauskas 2018-11-22 1631
4562236b Harry Wentland 2017-09-12 1632 static int
amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
4562236b Harry Wentland 2017-09-12 1633 {
eb3dc897 Nicholas Kazlauskas 2018-11-22 1634 struct dm_atomic_state *state;
4562236b Harry Wentland 2017-09-12 1635 int r;
4562236b Harry Wentland 2017-09-12 1636
4562236b Harry Wentland 2017-09-12 1637
adev->mode_info.mode_config_initialized = true;
4562236b Harry Wentland 2017-09-12 1638
4562236b Harry Wentland 2017-09-12 1639 adev->ddev->mode_config.funcs =
(void *)_dm_mode_funcs;
54f5499a Andrey Grodzovsky 2017-04-20 1640
adev->ddev->mode_config.helper_private = _dm_mode_config_helperfuncs;
4562236b Harry Wentland 2017-09-12 1641
4562236b Harry Wentland 2017-09-12 1642
adev->ddev->mode_config.max_width = 16384;
4562236b Harry Wentland 2017-09-12 1643
adev->ddev->mode_config.max_height = 16384;
4562236b Harry Wentland 2017-09-12 1644
4562236b Harry Wentland 2017-09-12 1645
adev->ddev->mode_config.preferred_depth = 24;
4562236b Harry Wentland 2017-09-12 1646
adev->ddev->mode_config.prefer_shadow =
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: DFSM pipe disable is valid from gen9 onwards (rev2)
== Series Details ==
Series: drm/i915: DFSM pipe disable is valid from gen9 onwards (rev2)
URL : https://patchwork.freedesktop.org/series/53900/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5296_full -> Patchwork_11070_full
Summary
---
**WARNING**
Minor unknown changes coming with Patchwork_11070_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_11070_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_11070_full:
### IGT changes ###
Warnings
* igt@kms_cursor_legacy@flip-vs-cursor-toggle:
- shard-snb: PASS -> SKIP
* igt@tools_test@tools_test:
- shard-glk: PASS -> SKIP
- shard-skl: SKIP -> PASS
Known issues
Here are the changes found in Patchwork_11070_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773]
* igt@i915_selftest@live_contexts:
- {shard-iclb}: NOTRUN -> DMESG-FAIL [fdo#108569]
* igt@kms_busy@extended-modeset-hang-newfb-render-b:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#107956]
- {shard-iclb}: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_chv_cursor_fail@pipe-b-256x256-right-edge:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107724] / [fdo#108336] +7
* igt@kms_color@pipe-a-ctm-max:
- shard-apl: PASS -> FAIL [fdo#108147]
* igt@kms_color@pipe-b-degamma:
- shard-apl: PASS -> FAIL [fdo#104782]
* igt@kms_cursor_crc@cursor-256x85-sliding:
- shard-apl: PASS -> DMESG-FAIL [fdo#103232] / [fdo#103558] /
[fdo#105602] +1
* igt@kms_cursor_crc@cursor-64x21-random:
- shard-apl: PASS -> FAIL [fdo#103232] +6
* igt@kms_draw_crc@draw-method-xrgb-render-ytiled:
- {shard-iclb}: PASS -> WARN [fdo#108336]
* igt@kms_fbcon_fbt@psr-suspend:
- shard-skl: NOTRUN -> FAIL [fdo#107882]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite:
- shard-apl: PASS -> FAIL [fdo#103167] +2
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff:
- shard-apl: PASS -> DMESG-FAIL [fdo#103167] / [fdo#103558] /
[fdo#105602] +1
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-pwrite:
- shard-glk: PASS -> FAIL [fdo#103167] +2
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-cpu:
- {shard-iclb}: PASS -> DMESG-FAIL [fdo#107724] +5
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-render:
- {shard-iclb}: PASS -> FAIL [fdo#103167] +1
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- {shard-iclb}: PASS -> INCOMPLETE [fdo#107713]
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- {shard-iclb}: PASS -> DMESG-FAIL [fdo#103166] / [fdo#107724]
* igt@kms_plane@plane-position-covered-pipe-a-planes:
- shard-apl: PASS -> FAIL [fdo#103166] +3
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-skl: NOTRUN -> FAIL [fdo#108145] +1
* igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
- shard-apl: PASS -> FAIL [fdo#108145]
* igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
- {shard-iclb}: PASS -> FAIL [fdo#103166]
* igt@kms_plane_multiple@atomic-pipe-a-tiling-yf:
- shard-glk: PASS -> FAIL [fdo#103166]
- shard-apl: PASS -> DMESG-FAIL [fdo#103166] / [fdo#103558] /
[fdo#105602]
* igt@kms_sysfs_edid_timing:
- shard-skl: NOTRUN -> FAIL [fdo#100047]
* igt@kms_vblank@pipe-a-ts-continuation-idle:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107724] +18
* igt@kms_vblank@pipe-c-query-busy:
- shard-apl: PASS -> DMESG-WARN [fdo#103558] / [fdo#105602] +21
* igt@pm_rpm@pm-caching:
- {shard-iclb}: PASS -> INCOMPLETE [fdo#108840] +1
Possible fixes
* igt@gem_ppgtt@blt-vs-render-ctx0:
- shard-skl: TIMEOUT [fdo#108039] -> PASS
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a:
- shard-apl: DMESG-WARN [fdo#107956] -> PASS
* igt@kms_color@pipe-b-ctm-negative:
- shard-skl: FAIL [fdo#107361] -> PASS
* igt@kms_color@pipe-c-degamma:
- shard-apl: FAIL [fdo#104782] -> PASS
* igt@kms_cursor_crc@cursor-64x21-sliding:
- shard-apl: FAIL [fdo#103232] -> PASS
*
[Intel-gfx] [PATCH v2] drm/i915: correct the pitch check for NV12 framebuffer
framebuffer for NV12 requires the pitch to the multiplier of 4, instead
of the width. This patch corrects it.
For instance, a 480p video, whose width and pitch are 854 and 896
respectively, is excluded for NV12 plane so far.
Signed-off-by: Dongseong Hwang
Cc: Chandra Konduru
Cc: Vidya Srinivas
Cc: Ville Syrjälä
Cc: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 13e5650..8a3de12 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14600,7 +14600,7 @@ static int intel_framebuffer_init(struct
intel_framebuffer *intel_fb,
if (fb->format->format == DRM_FORMAT_NV12 &&
(fb->width < SKL_MIN_YUV_420_SRC_W ||
fb->height < SKL_MIN_YUV_420_SRC_H ||
-(fb->width % 4) != 0 || (fb->height % 4) != 0)) {
+(fb->pitches[0] % 4) != 0 || (fb->height % 4) != 0)) {
DRM_DEBUG_KMS("src dimensions not correct for NV12\n");
goto err;
}
--
2.7.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: DFSM pipe disable is valid from gen9 onwards (v2)
On Tue, Dec 11, 2018 at 11:25:45AM -0800, Bob Paauwe wrote:
> It's not just GEN9 platforms that allow for pipes to be disabled via
> the DFSM register, but all later platforms as well.
>
> v2: drop pointless parentheses (Ville)
>
> Signed-off-by: Bob Paauwe
Reviewed-by: Matt Roper
Pushed to dinq. Thanks for the patch.
Matt
> ---
> drivers/gpu/drm/i915/intel_device_info.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> b/drivers/gpu/drm/i915/intel_device_info.c
> index 1e56319334f3..bd5c4d62c635 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -811,7 +811,7 @@ void intel_device_info_runtime_init(struct
> intel_device_info *info)
> DRM_INFO("PipeC fused off\n");
> info->num_pipes -= 1;
> }
> - } else if (HAS_DISPLAY(dev_priv) && IS_GEN9(dev_priv)) {
> + } else if (HAS_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 9) {
> u32 dfsm = I915_READ(SKL_DFSM);
> u8 disabled_mask = 0;
> bool invalid;
> --
> 2.17.1
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/2] drm/i915: Don't use DDB allocation when choosing gen9 watermark method (rev2)
The rc6 pass->skip mentioned below doesn't appear to be related to this
series, so pushing to dinq. Thanks to Ville for reviewing.
I also notice that CI indicates a bunch of pre-existing ICL watermark
failures are no longer happening with my series (or the earlier
revisions of my series), so it's possible that we've also fixed
https://bugs.freedesktop.org/show_bug.cgi?id=107724 "by accident" with
this series.
Matt
On Tue, Dec 11, 2018 at 11:48:05PM +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [CI,1/2] drm/i915: Don't use DDB allocation when
> choosing gen9 watermark method (rev2)
> URL : https://patchwork.freedesktop.org/series/53901/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_5296_full -> Patchwork_11069_full
>
>
> Summary
> ---
>
> **WARNING**
>
> Minor unknown changes coming with Patchwork_11069_full need to be verified
> manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_11069_full, please notify your bug team to allow
> them
> to document this new failure mode, which will reduce false positives in CI.
>
>
>
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> Patchwork_11069_full:
>
> ### IGT changes ###
>
> Warnings
>
> * igt@pm_rc6_residency@rc6-accuracy:
> - shard-snb: PASS -> SKIP
>
> * igt@tools_test@tools_test:
> - shard-skl: SKIP -> PASS
>
>
> Known issues
>
>
> Here are the changes found in Patchwork_11069_full that come from known
> issues:
>
> ### IGT changes ###
>
> Issues hit
>
> * igt@gem_userptr_blits@readonly-unsync:
> - {shard-iclb}: PASS -> INCOMPLETE [fdo#108342]
>
> * igt@i915_selftest@live_contexts:
> - {shard-iclb}: NOTRUN -> DMESG-FAIL [fdo#108569]
>
> * igt@kms_busy@extended-modeset-hang-newfb-render-b:
> - shard-skl: NOTRUN -> DMESG-WARN [fdo#107956]
> - {shard-iclb}: NOTRUN -> DMESG-WARN [fdo#107956]
>
> * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
> - {shard-iclb}: PASS -> DMESG-WARN [fdo#107956]
>
> * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
> - shard-glk: NOTRUN -> DMESG-WARN [fdo#107956]
>
> * igt@kms_chv_cursor_fail@pipe-b-256x256-right-edge:
> - {shard-iclb}: PASS -> DMESG-WARN [fdo#107724] / [fdo#108336] +10
>
> * igt@kms_color@pipe-a-degamma:
> - shard-apl: PASS -> FAIL [fdo#104782] / [fdo#108145]
>
> * igt@kms_color@pipe-b-degamma:
> - shard-apl: PASS -> FAIL [fdo#104782]
>
> * igt@kms_color@pipe-b-gamma:
> - shard-skl: PASS -> FAIL [fdo#104782]
>
> * igt@kms_color@pipe-c-ctm-green-to-red:
> - shard-skl: PASS -> FAIL [fdo#107201]
>
> * igt@kms_cursor_crc@cursor-64x21-random:
> - shard-apl: PASS -> FAIL [fdo#103232] +11
>
> * igt@kms_cursor_crc@cursor-64x64-suspend:
> - shard-apl: PASS -> FAIL [fdo#103191] / [fdo#103232]
>
> * igt@kms_draw_crc@draw-method-rgb565-pwrite-ytiled:
> - {shard-iclb}: PASS -> FAIL [fdo#103184]
>
> * igt@kms_draw_crc@draw-method-xrgb2101010-render-ytiled:
> - {shard-iclb}: PASS -> WARN [fdo#108336] +2
>
> * igt@kms_fbcon_fbt@psr-suspend:
> - shard-skl: NOTRUN -> FAIL [fdo#107882]
>
> * igt@kms_flip@flip-vs-expired-vblank-interruptible:
> - shard-skl: PASS -> FAIL [fdo#105363]
>
> * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-gtt:
> - {shard-iclb}: PASS -> DMESG-FAIL [fdo#107724] +16
>
> * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
> - shard-apl: PASS -> FAIL [fdo#103167] +5
>
> * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc:
> - shard-glk: PASS -> FAIL [fdo#103167] +2
>
> * igt@kms_frontbuffer_tracking@fbc-stridechange:
> - {shard-iclb}: PASS -> FAIL [fdo#105683] / [fdo#108040]
>
> * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-render:
> - {shard-iclb}: PASS -> FAIL [fdo#103167] +3
>
> * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt:
> - {shard-iclb}: NOTRUN -> FAIL [fdo#103167]
>
> * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
> - shard-skl: PASS -> INCOMPLETE [fdo#104108]
>
> * igt@kms_plane@plane-position-covered-pipe-a-planes:
> - shard-glk: PASS -> FAIL [fdo#103166]
> - {shard-iclb}: NOTRUN -> FAIL [fdo#103166]
>
> * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
> - shard-skl: NOTRUN -> FAIL [fdo#108145] +1
>
> * igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
> - shard-glk: PASS -> FAIL [fdo#108145]
>
> *
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/2] drm/i915: Don't use DDB allocation when choosing gen9 watermark method (rev2)
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Don't use DDB allocation when
choosing gen9 watermark method (rev2)
URL : https://patchwork.freedesktop.org/series/53901/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5296_full -> Patchwork_11069_full
Summary
---
**WARNING**
Minor unknown changes coming with Patchwork_11069_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_11069_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_11069_full:
### IGT changes ###
Warnings
* igt@pm_rc6_residency@rc6-accuracy:
- shard-snb: PASS -> SKIP
* igt@tools_test@tools_test:
- shard-skl: SKIP -> PASS
Known issues
Here are the changes found in Patchwork_11069_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_userptr_blits@readonly-unsync:
- {shard-iclb}: PASS -> INCOMPLETE [fdo#108342]
* igt@i915_selftest@live_contexts:
- {shard-iclb}: NOTRUN -> DMESG-FAIL [fdo#108569]
* igt@kms_busy@extended-modeset-hang-newfb-render-b:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#107956]
- {shard-iclb}: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
- shard-glk: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_chv_cursor_fail@pipe-b-256x256-right-edge:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107724] / [fdo#108336] +10
* igt@kms_color@pipe-a-degamma:
- shard-apl: PASS -> FAIL [fdo#104782] / [fdo#108145]
* igt@kms_color@pipe-b-degamma:
- shard-apl: PASS -> FAIL [fdo#104782]
* igt@kms_color@pipe-b-gamma:
- shard-skl: PASS -> FAIL [fdo#104782]
* igt@kms_color@pipe-c-ctm-green-to-red:
- shard-skl: PASS -> FAIL [fdo#107201]
* igt@kms_cursor_crc@cursor-64x21-random:
- shard-apl: PASS -> FAIL [fdo#103232] +11
* igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-apl: PASS -> FAIL [fdo#103191] / [fdo#103232]
* igt@kms_draw_crc@draw-method-rgb565-pwrite-ytiled:
- {shard-iclb}: PASS -> FAIL [fdo#103184]
* igt@kms_draw_crc@draw-method-xrgb2101010-render-ytiled:
- {shard-iclb}: PASS -> WARN [fdo#108336] +2
* igt@kms_fbcon_fbt@psr-suspend:
- shard-skl: NOTRUN -> FAIL [fdo#107882]
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: PASS -> FAIL [fdo#105363]
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-gtt:
- {shard-iclb}: PASS -> DMESG-FAIL [fdo#107724] +16
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
- shard-apl: PASS -> FAIL [fdo#103167] +5
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc:
- shard-glk: PASS -> FAIL [fdo#103167] +2
* igt@kms_frontbuffer_tracking@fbc-stridechange:
- {shard-iclb}: PASS -> FAIL [fdo#105683] / [fdo#108040]
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-render:
- {shard-iclb}: PASS -> FAIL [fdo#103167] +3
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt:
- {shard-iclb}: NOTRUN -> FAIL [fdo#103167]
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
- shard-skl: PASS -> INCOMPLETE [fdo#104108]
* igt@kms_plane@plane-position-covered-pipe-a-planes:
- shard-glk: PASS -> FAIL [fdo#103166]
- {shard-iclb}: NOTRUN -> FAIL [fdo#103166]
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-skl: NOTRUN -> FAIL [fdo#108145] +1
* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-glk: PASS -> FAIL [fdo#108145]
* igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
- {shard-iclb}: PASS -> FAIL [fdo#103166] +3
* igt@kms_psr@cursor_mmap_gtt:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107724] +19
* igt@kms_sysfs_edid_timing:
- shard-skl: NOTRUN -> FAIL [fdo#100047]
* igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend:
- {shard-iclb}: PASS -> INCOMPLETE [fdo#107713]
* igt@perf@short-reads:
- shard-skl: PASS -> FAIL [fdo#103183]
* igt@pm_rpm@modeset-stress-extra-wait:
- {shard-iclb}: PASS -> INCOMPLETE [fdo#108840]
Possible fixes
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
- shard-apl: FAIL [fdo#105458] / [fdo#106510] -> PASS
* igt@kms_color@pipe-c-degamma:
[Intel-gfx] ✓ Fi.CI.BAT: success for Add HDR Metadata Parsing and handling in DRM layer (rev3)
== Series Details == Series: Add HDR Metadata Parsing and handling in DRM layer (rev3) URL : https://patchwork.freedesktop.org/series/25091/ State : success == Summary == CI Bug Log - changes from CI_DRM_5296 -> Patchwork_11073 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/25091/revisions/3/mbox/ Known issues Here are the changes found in Patchwork_11073 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_hangcheck: - fi-skl-guc: PASS -> DMESG-FAIL [fdo#108593] * igt@kms_frontbuffer_tracking@basic: - fi-hsw-peppy: PASS -> DMESG-WARN [fdo#102614] * igt@pm_rpm@module-reload: - fi-skl-6700k2: PASS -> INCOMPLETE [fdo#107807] [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614 [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807 [fdo#108593]: https://bugs.freedesktop.org/show_bug.cgi?id=108593 Participating hosts (48 -> 43) -- Additional (1): fi-byt-j1900 Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-ctg-p8600 fi-icl-y Build changes - * Linux: CI_DRM_5296 -> Patchwork_11073 CI_DRM_5296: 70751bd8a3f27b035d203ecafcad452f4d7c2c15 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4745: 3b52e8a5809a4e860350c59476a456745cd9fee0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_11073: def7680b600da56d5ca8d170cc80bc267a325402 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == def7680b600d drivers/video: Constantify function argument for HDMI infoframe log 885017e75a4b drm/i915:Enabled Modeset when HDR Infoframe changes 95b30187cd3b drm/i915: Enable infoframes on GLK+ for HDR 2ca030434539 drm/i915: Add HLG EOTF 4b5a7e4be9bf drm/i915: [DO NOT MERGE] hack for glk board outputs 09c5cf8f9dc8 drm/i915: Write HDR infoframe and send to panel 69240a4dd2ec drm: Enable HDR infoframe support 8595788ee7d3 drm: Implement HDR source metadata set and get property handling 26b04ef7c84c drm: Add HDR capability field to plane structure 8ba29ca0b12a drm/i915: Attach HDR metadata property to connector c32feedce988 drm: Parse Colorimetry data block from EDID c0f32ec43843 drm: Parse HDR metadata info from EDID 9274c63b5377 drm: Add CEA extended tag blocks and HDR bitfield macros 9feff89ee8cd drm: Add HDR source metadata property == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11073/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add HDR Metadata Parsing and handling in DRM layer (rev3)
== Series Details ==
Series: Add HDR Metadata Parsing and handling in DRM layer (rev3)
URL : https://patchwork.freedesktop.org/series/25091/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
9feff89ee8cd drm: Add HDR source metadata property
9274c63b5377 drm: Add CEA extended tag blocks and HDR bitfield macros
c0f32ec43843 drm: Parse HDR metadata info from EDID
-:34: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#34: FILE: drivers/gpu/drm/drm_edid.c:3834:
+{
+
-:40: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#40: FILE: drivers/gpu/drm/drm_edid.c:3840:
+
+}
-:44: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#44: FILE: drivers/gpu/drm/drm_edid.c:3844:
+{
+
total: 0 errors, 0 warnings, 3 checks, 57 lines checked
c32feedce988 drm: Parse Colorimetry data block from EDID
-:43: CHECK:LINE_SPACING: Please don't use multiple blank lines
#43: FILE: drivers/gpu/drm/drm_edid.c:3842:
+
+
total: 0 errors, 0 warnings, 1 checks, 44 lines checked
8ba29ca0b12a drm/i915: Attach HDR metadata property to connector
-:21: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#21: FILE: drivers/gpu/drm/i915/intel_hdmi.c:2158:
+ drm_object_attach_property(>base,
+ connector->dev->mode_config.hdr_source_metadata_property, 0);
total: 0 errors, 0 warnings, 1 checks, 8 lines checked
26b04ef7c84c drm: Add HDR capability field to plane structure
-:26: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible
alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#26: FILE: include/drm/drm_plane.h:642:
+ bool hdr_supported;
total: 0 errors, 0 warnings, 1 checks, 9 lines checked
8595788ee7d3 drm: Implement HDR source metadata set and get property handling
-:25: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#25: FILE: drivers/gpu/drm/drm_atomic.c:874:
+ drm_printf(p, "\thdr_metadata_changed=%d\n",
+ state->hdr_metadata_changed);
-:48: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#48: FILE: drivers/gpu/drm/drm_atomic_uapi.c:741:
+ ret = drm_atomic_replace_property_blob_from_id(dev,
+ >hdr_source_metadata_blob_ptr,
total: 0 errors, 0 warnings, 2 checks, 39 lines checked
69240a4dd2ec drm: Enable HDR infoframe support
-:54: CHECK:LINE_SPACING: Please don't use multiple blank lines
#54: FILE: drivers/gpu/drm/drm_edid.c:4946:
+
+
-:83: CHECK:LINE_SPACING: Please don't use multiple blank lines
#83: FILE: drivers/gpu/drm/drm_edid.c:4975:
+
+
-:215: ERROR:CODE_INDENT: code indent should use tabs where possible
#215: FILE: drivers/video/hdmi.c:1386:
+ struct device *dev,$
-:215: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#215: FILE: drivers/video/hdmi.c:1386:
+static void hdmi_drm_infoframe_log(const char *level,
+ struct device *dev,
-:215: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#215: FILE: drivers/video/hdmi.c:1386:
+ struct device *dev,$
-:216: ERROR:CODE_INDENT: code indent should use tabs where possible
#216: FILE: drivers/video/hdmi.c:1387:
+ struct hdmi_drm_infoframe *frame)$
-:216: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#216: FILE: drivers/video/hdmi.c:1387:
+ struct hdmi_drm_infoframe *frame)$
-:221: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#221: FILE: drivers/video/hdmi.c:1392:
+ hdmi_infoframe_log_header(level, dev,
+ (struct hdmi_any_infoframe *)frame);
-:234: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#234: FILE: drivers/video/hdmi.c:1405:
+ hdmi_log("max_mastering_display_luminance: %d\n",
+ frame->max_mastering_display_luminance);
-:236: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#236: FILE: drivers/video/hdmi.c:1407:
+ hdmi_log("min_mastering_display_luminance: %d\n",
+ frame->min_mastering_display_luminance);
total: 2 errors, 2 warnings, 6 checks, 279 lines checked
09c5cf8f9dc8 drm/i915: Write HDR infoframe and send to panel
4b5a7e4be9bf drm/i915: [DO NOT MERGE] hack for glk board outputs
2ca030434539 drm/i915: Add HLG EOTF
95b30187cd3b drm/i915: Enable infoframes on GLK+ for HDR
-:47: WARNING:LONG_LINE: line over 100 characters
#47: FILE: drivers/gpu/drm/i915/i915_reg.h:8058:
+#define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(trans,
_GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4)
total: 0 errors, 1 warnings, 0 checks, 70 lines checked
885017e75a4b drm/i915:Enabled Modeset when HDR Infoframe changes
-:57: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#57: FILE: drivers/gpu/drm/i915/intel_hdmi.c:495:
+ if
Re: [Intel-gfx] [PATCH 5/5] drm/i915/debugfs: Print PSR selective update status register values
On Tue, 2018-12-04 at 15:00 -0800, José Roberto de Souza wrote:
> The value of this registers will be used to test if PSR2 is doing
> selective update and if the number of blocks match with the expected.
>
> Cc: Rodrigo Vivi
> Cc: Dhinakaran Pandiyan
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 42 ++-
> --
> 1 file changed, 38 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 505d93b31eb6..754b33194e09 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2760,10 +2760,44 @@ static int i915_edp_psr_status(struct
> seq_file *m, void *data)
> seq_printf(m, "Performance counter: %u\n", val);
> }
>
> - if ((psr->debug & I915_PSR_DEBUG_IRQ) && !psr->psr2_enabled) {
> - seq_printf(m, "Last attempted entry at: %lld\n",
> -psr->last_entry_attempt);
> - seq_printf(m, "Last exit at: %lld\n", psr->last_exit);
> + if (!psr->psr2_enabled) {
> + if (psr->debug & I915_PSR_DEBUG_IRQ) {
> + seq_printf(m, "Last attempted entry at:
> %lld\n",
> +psr->last_entry_attempt);
> + seq_printf(m, "Last exit at: %lld\n", psr-
> >last_exit);
> + }
> + } else {
> + u8 i;
> +
> + val = I915_READ(EDP_PSR2_SU_STATUS);
> + seq_printf(m, "PSR2 SU status: 0x%08x\n", val);
> + for (i = 0; val && i < 3; i++) {
> + u32 num;
> +
> + num = val &
> EDP_PSR2_SU_STATUS_NUM_SU_BLOCKS_IN_FRAME_MASK(i);
> + num = num >>
> EDP_PSR2_SU_STATUS_NUM_SU_BLOCKS_IN_FRAME_SHIFT(i);
> + seq_printf(m, "\tSU num blocks in frame N-%u:
> %u\n", i, num);
> + }
> +
> + val = I915_READ(EDP_PSR2_SU_STATUS2);
> + seq_printf(m, "PSR2 SU status2: 0x%08x\n", val);
> + for (i = 0; val && i < 3; i++) {
> + u32 num;
> +
> + num = val &
> EDP_PSR2_SU_STATUS_NUM_SU_BLOCKS_IN_FRAME_MASK(i);
> + num = num >>
> EDP_PSR2_SU_STATUS_NUM_SU_BLOCKS_IN_FRAME_SHIFT(i);
> + seq_printf(m, "\tSU num blocks in frame N-%u:
> %u\n", i + 3, num);
> + }
> +
> + val = I915_READ(EDP_PSR2_SU_STATUS3);
> + seq_printf(m, "PSR2 SU status3: 0x%08x\n", val);
> + for (i = 0; val && i < 2; i++) {
> + u32 num;
> +
> + num = val &
> EDP_PSR2_SU_STATUS_NUM_SU_BLOCKS_IN_FRAME_MASK(i);
> + num = num >>
> EDP_PSR2_SU_STATUS_NUM_SU_BLOCKS_IN_FRAME_SHIFT(i);
> + seq_printf(m, "\tSU num blocks in frame N-%u:
> %u\n", i + 6, num);
nitpick: Have you considered reducing the text that's getting printed
here? I guess we might not need to increase the read buffer size in IGT
if we do some thing like this.
Frame SU blocks
0 f
1 o
2 o
I'll leave it to you if you want to change, but I do prefer making this
less verbose.
> + }
> }
>
> unlock:
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[Intel-gfx] [v3 08/14] drm: Enable HDR infoframe support
Enable Dynamic Range and Mastering Infoframe for HDR
content, which is defined in CEA 861.3 spec.
The metadata will be computed based on blending
policy in userspace compositors and passed as a connector
property blob to driver. The same will be sent as infoframe
to panel which support HDR.
v2: Rebase and added Ville's POC changes.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_edid.c | 58
drivers/video/hdmi.c | 129 +
include/drm/drm_edid.h | 4 ++
include/linux/hdmi.h | 22
4 files changed, 213 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 344d8c1..5a7fc9b 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -4916,6 +4916,64 @@ void drm_set_preferred_mode(struct drm_connector
*connector,
EXPORT_SYMBOL(drm_set_preferred_mode);
/**
+ * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI AVI infoframe with
+ * HDR metadata from userspace
+ * @frame: HDMI AVI infoframe
+ * @hdr_source_metadata: hdr_source_metadata info from userspace
+ *
+ * Return: 0 on success or a negative error code on failure.
+ */
+int
+drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame,
+ void *hdr_metadata)
+{
+ struct hdr_static_metadata *hdr_source_metadata;
+ int err, i;
+
+ if (!frame || !hdr_metadata)
+ return -EINVAL;
+
+ err = hdmi_drm_infoframe_init(frame);
+ if (err < 0)
+ return err;
+
+ DRM_DEBUG_KMS("type = %x\n", frame->type);
+
+ hdr_source_metadata = (struct hdr_static_metadata *)hdr_metadata;
+
+ frame->length = sizeof(struct hdr_static_metadata);
+
+
+ frame->eotf = hdr_source_metadata->eotf;
+ frame->metadata_type = hdr_source_metadata->metadata_type;
+
+ for (i = 0; i < 3; i++) {
+ frame->display_primaries[i].x =
+ hdr_source_metadata->display_primaries[i].x;
+ frame->display_primaries[i].y =
+ hdr_source_metadata->display_primaries[i].y;
+ }
+
+ frame->white_point.x = hdr_source_metadata->white_point.x;
+ frame->white_point.y = hdr_source_metadata->white_point.y;
+
+ frame->max_mastering_display_luminance =
+ hdr_source_metadata->max_mastering_display_luminance;
+ frame->min_mastering_display_luminance =
+ hdr_source_metadata->min_mastering_display_luminance;
+
+ frame->max_cll = hdr_source_metadata->max_cll;
+ frame->max_fall = hdr_source_metadata->max_fall;
+
+ hdmi_infoframe_log(KERN_CRIT, NULL,
+ (union hdmi_infoframe *)frame);
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata);
+
+
+/**
* drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
* data from a DRM display mode
* @frame: HDMI AVI infoframe
diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c
index 799ae49..0937c8c 100644
--- a/drivers/video/hdmi.c
+++ b/drivers/video/hdmi.c
@@ -650,6 +650,93 @@ ssize_t hdmi_vendor_infoframe_pack(struct
hdmi_vendor_infoframe *frame,
return 0;
}
+/**
+ * hdmi_drm_infoframe_init() - initialize an HDMI Dynaminc Range and
+ * mastering infoframe
+ * @frame: HDMI DRM infoframe
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+int hdmi_drm_infoframe_init(struct hdmi_drm_infoframe *frame)
+{
+ memset(frame, 0, sizeof(*frame));
+
+ frame->type = HDMI_INFOFRAME_TYPE_DRM;
+ frame->version = 1;
+
+ return 0;
+}
+EXPORT_SYMBOL(hdmi_drm_infoframe_init);
+
+/**
+ * hdmi_drm_infoframe_pack() - write HDMI DRM infoframe to binary buffer
+ * @frame: HDMI DRM infoframe
+ * @buffer: destination buffer
+ * @size: size of buffer
+ *
+ * Packs the information contained in the @frame structure into a binary
+ * representation that can be written into the corresponding controller
+ * registers. Also computes the checksum as required by section 5.3.5 of
+ * the HDMI 1.4 specification.
+ *
+ * Returns the number of bytes packed into the binary buffer or a negative
+ * error code on failure.
+ */
+ssize_t hdmi_drm_infoframe_pack(struct hdmi_drm_infoframe *frame, void *buffer,
+ size_t size)
+{
+ u8 *ptr = buffer;
+ size_t length;
+ int i;
+
+ length = HDMI_INFOFRAME_HEADER_SIZE + frame->length;
+
+ if (size < length)
+ return -ENOSPC;
+
+ memset(buffer, 0, size);
+
+ ptr[0] = frame->type;
+ ptr[1] = frame->version;
+ ptr[2] = frame->length;
+ ptr[3] = 0; /* checksum */
+
+ /* start infoframe payload */
+ ptr += HDMI_INFOFRAME_HEADER_SIZE;
+
+ *ptr++ = frame->eotf;
+ *ptr++ = frame->metadata_type;
+
+ for (i = 0; i < 3; i++) {
+
[Intel-gfx] [v3 12/14] drm/i915: Enable infoframes on GLK+ for HDR
From: Ville Syrjälä
This patch enables infoframes on GLK+ to be
used to send HDR metadata to HDMI sink.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 4
drivers/gpu/drm/i915/intel_hdmi.c | 12 +---
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0a7d605..6f44d02 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4591,6 +4591,7 @@ enum {
#define VIDEO_DIP_FREQ_MASK (3 << 16)
/* HSW and later: */
#define DRM_DIP_ENABLE (1 << 28)
+#define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28)
#define PSR_VSC_BIT_7_SET(1 << 27)
#define VSC_SELECT_MASK (0x3 << 25)
#define VSC_SELECT_SHIFT 25
@@ -8015,6 +8016,7 @@ enum {
#define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
#define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
#define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320
+#define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440
#define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240
#define _HSW_VIDEO_DIP_VS_ECC_A0x60280
#define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
@@ -8028,6 +8030,7 @@ enum {
#define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
#define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
#define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320
+#define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440
#define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240
#define _HSW_VIDEO_DIP_VS_ECC_B0x61280
#define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
@@ -8052,6 +8055,7 @@ enum {
#define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans,
_HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
#define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans,
_HSW_VIDEO_DIP_GCP_A)
#define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans,
_HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
+#define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(trans,
_GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4)
#define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans,
_ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
#define ICL_VIDEO_DIP_PPS_ECC(trans, i)_MMIO_TRANS2(trans,
_ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 3e7c074..8d145d4 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -123,6 +123,8 @@ static u32 hsw_infoframe_enable(unsigned int type)
return VIDEO_DIP_ENABLE_SPD_HSW;
case HDMI_INFOFRAME_TYPE_VENDOR:
return VIDEO_DIP_ENABLE_VS_HSW;
+ case HDMI_INFOFRAME_TYPE_DRM:
+ return VIDEO_DIP_ENABLE_DRM_GLK;
default:
MISSING_CASE(type);
return 0;
@@ -146,6 +148,8 @@ static u32 hsw_infoframe_enable(unsigned int type)
return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
case HDMI_INFOFRAME_TYPE_VENDOR:
return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
+ case HDMI_INFOFRAME_TYPE_DRM:
+ return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i);
default:
MISSING_CASE(type);
return INVALID_MMIO_REG;
@@ -432,7 +436,8 @@ static bool hsw_infoframe_enabled(struct intel_encoder
*encoder,
return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
- VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
+ VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
+ VIDEO_DIP_ENABLE_DRM_GLK);
}
/*
@@ -889,7 +894,8 @@ static void hsw_set_infoframes(struct intel_encoder
*encoder,
val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
-VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
+VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
+VIDEO_DIP_ENABLE_DRM_GLK);
if (!enable) {
I915_WRITE(reg, val);
@@ -908,7 +914,7 @@ static void hsw_set_infoframes(struct intel_encoder
*encoder,
intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
/* Set Dynamic Range and Mastering Infoframe if supported and changed */
- if (conn_state->hdr_metadata_changed)
+ if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
intel_hdmi_set_drm_infoframe(encoder, crtc_state, conn_state);
}
--
1.9.1
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[Intel-gfx] [v3 11/14] drm/i915: Add HLG EOTF
From: Ville Syrjälä
ADD HLG EOTF to the list of EOTF transfer functions
supported.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_edid.c | 4 ++--
include/linux/hdmi.h | 1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 5a7fc9b..fa86494 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -3857,8 +3857,8 @@ static uint16_t eotf_supported(const u8 *edid_ext)
return edid_ext[2] &
(BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
-BIT(HDMI_EOTF_SMPTE_ST2084));
-
+BIT(HDMI_EOTF_SMPTE_ST2084) |
+BIT(HDMI_EOTF_BT_2100_HLG));
}
static uint16_t hdr_metadata_type(const u8 *edid_ext)
diff --git a/include/linux/hdmi.h b/include/linux/hdmi.h
index ce00e1e..b5346c3 100644
--- a/include/linux/hdmi.h
+++ b/include/linux/hdmi.h
@@ -146,6 +146,7 @@ enum hdmi_eotf {
HDMI_EOTF_TRADITIONAL_GAMMA_SDR,
HDMI_EOTF_TRADITIONAL_GAMMA_HDR,
HDMI_EOTF_SMPTE_ST2084,
+ HDMI_EOTF_BT_2100_HLG,
};
struct hdmi_avi_infoframe {
--
1.9.1
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[Intel-gfx] [v3 10/14] drm/i915: [DO NOT MERGE] hack for glk board outputs
From: Ville Syrjälä
This is to limit PORT C on GLK to drive only
HDMI. Not sure if this is mandatory, this is just
to test HDR on GLK HDMI.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_bios.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index 6d3e026..e1c48ad 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -1381,6 +1381,13 @@ static void parse_ddi_port(struct drm_i915_private
*dev_priv, enum port port,
is_hdmi = false;
}
+ if (IS_GEMINILAKE(dev_priv) && port == PORT_C) {
+ is_hdmi = true;
+ is_dvi = true;
+ is_dp = false;
+ is_edp = false;
+ }
+
info->supports_dvi = is_dvi;
info->supports_hdmi = is_hdmi;
info->supports_dp = is_dp;
--
1.9.1
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[Intel-gfx] [v3 07/14] drm: Implement HDR source metadata set and get property handling
HDR source metadata set and get property implemented in this
patch. The blob data is received from userspace and saved in
connector state, the same is returned as blob in get property
call to userspace.
v2: Rebase and added Ville's POC changes
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_atomic.c | 2 ++
drivers/gpu/drm/drm_atomic_uapi.c | 13 +
2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 5eb4013..4e71c6b 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -881,6 +881,8 @@ static void drm_atomic_connector_print_state(struct
drm_printer *p,
drm_printf(p, "connector[%u]: %s\n", connector->base.id,
connector->name);
drm_printf(p, "\tcrtc=%s\n", state->crtc ? state->crtc->name :
"(null)");
+ drm_printf(p, "\thdr_metadata_changed=%d\n",
+ state->hdr_metadata_changed);
if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
if (state->writeback_job && state->writeback_job->fb)
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index c408898..b721b12 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -686,6 +686,8 @@ static int drm_atomic_connector_set_property(struct
drm_connector *connector,
{
struct drm_device *dev = connector->dev;
struct drm_mode_config *config = >mode_config;
+ bool replaced = false;
+ int ret;
if (property == config->prop_crtc_id) {
struct drm_crtc *crtc = drm_crtc_find(dev, NULL, val);
@@ -734,6 +736,14 @@ static int drm_atomic_connector_set_property(struct
drm_connector *connector,
*/
if (state->link_status != DRM_LINK_STATUS_GOOD)
state->link_status = val;
+ } else if (property == config->hdr_source_metadata_property) {
+ ret = drm_atomic_replace_property_blob_from_id(dev,
+ >hdr_source_metadata_blob_ptr,
+ val,
+ -1, sizeof(struct hdr_static_metadata),
+ );
+ state->hdr_metadata_changed |= replaced;
+ return ret;
} else if (property == config->aspect_ratio_property) {
state->picture_aspect_ratio = val;
} else if (property == config->content_type_property) {
@@ -816,6 +826,9 @@ static int drm_atomic_connector_set_property(struct
drm_connector *connector,
*val = state->content_type;
} else if (property == connector->scaling_mode_property) {
*val = state->scaling_mode;
+ } else if (property == config->hdr_source_metadata_property) {
+ *val = (state->hdr_source_metadata_blob_ptr) ?
+ state->hdr_source_metadata_blob_ptr->base.id : 0;
} else if (property == connector->content_protection_property) {
*val = state->content_protection;
} else if (property == config->writeback_fb_id_property) {
--
1.9.1
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[Intel-gfx] [v3 13/14] drm/i915:Enabled Modeset when HDR Infoframe changes
This patch enables modeset whenever HDR metadata
needs to be updated to sink.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_atomic.c | 15 ++-
drivers/gpu/drm/i915/intel_hdmi.c | 4
2 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_atomic.c
b/drivers/gpu/drm/i915/intel_atomic.c
index 8cb02f2..72c3fcb 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -101,6 +101,16 @@ int intel_digital_connector_atomic_set_property(struct
drm_connector *connector,
return -EINVAL;
}
+static bool blob_equal(const struct drm_property_blob *a,
+ const struct drm_property_blob *b)
+{
+ if (a && b)
+ return a->length == b->length &&
+ !memcmp(a->data, b->data, a->length);
+
+ return !a == !b;
+}
+
int intel_digital_connector_atomic_check(struct drm_connector *conn,
struct drm_connector_state *new_state)
{
@@ -127,7 +137,10 @@ int intel_digital_connector_atomic_check(struct
drm_connector *conn,
new_conn_state->broadcast_rgb != old_conn_state->broadcast_rgb ||
new_conn_state->base.picture_aspect_ratio !=
old_conn_state->base.picture_aspect_ratio ||
new_conn_state->base.content_type !=
old_conn_state->base.content_type ||
- new_conn_state->base.scaling_mode !=
old_conn_state->base.scaling_mode)
+ new_conn_state->base.scaling_mode !=
+ old_conn_state->base.scaling_mode ||
+ !blob_equal(new_conn_state->base.hdr_source_metadata_blob_ptr,
+ old_conn_state->base.hdr_source_metadata_blob_ptr))
crtc_state->mode_changed = true;
return 0;
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 8d145d4..414768a 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -491,6 +491,10 @@ static void intel_hdmi_set_drm_infoframe(struct
intel_encoder *encoder,
struct hdr_static_metadata *hdr_metadata;
int ret;
+ if (!conn_state->hdr_source_metadata_blob_ptr ||
+ conn_state->hdr_source_metadata_blob_ptr->length == 0)
+ return;
+
hdr_metadata = (struct hdr_static_metadata *)
conn_state->hdr_source_metadata_blob_ptr->data;
--
1.9.1
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[Intel-gfx] [v3 14/14] drivers/video: Constantify function argument for HDMI infoframe log
From: Ville Syrjälä
Function argument for hdmi_drm_infoframe_log is made constant.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/video/hdmi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c
index 0937c8c..7ab8086 100644
--- a/drivers/video/hdmi.c
+++ b/drivers/video/hdmi.c
@@ -1383,8 +1383,8 @@ static void hdmi_audio_infoframe_log(const char *level,
* @frame: HDMI DRM infoframe
*/
static void hdmi_drm_infoframe_log(const char *level,
- struct device *dev,
- struct hdmi_drm_infoframe *frame)
+ struct device *dev,
+ const struct hdmi_drm_infoframe *frame)
{
int i;
--
1.9.1
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[Intel-gfx] [v3 09/14] drm/i915: Write HDR infoframe and send to panel
Enable writing of HDR metadata infoframe to panel.
The data will be provid by usersapace compositors, based
on blending policies and passsed to driver through a blob
property.
v2: Rebase
v3: Fixed a warning message
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_hdmi.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 8a1e5cb..3e7c074 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -475,6 +475,29 @@ static void intel_write_infoframe(struct intel_encoder
*encoder,
frame->any.type, buffer, len);
}
+/* Set Dynamic Range and Mastering Infoframe */
+static void intel_hdmi_set_drm_infoframe(struct intel_encoder *encoder,
+const struct intel_crtc_state
+*crtc_state,
+const struct drm_connector_state
+*conn_state)
+{
+ union hdmi_infoframe frame;
+ struct hdr_static_metadata *hdr_metadata;
+ int ret;
+
+ hdr_metadata = (struct hdr_static_metadata *)
+ conn_state->hdr_source_metadata_blob_ptr->data;
+
+ ret = drm_hdmi_infoframe_set_hdr_metadata(, hdr_metadata);
+ if (ret < 0) {
+ DRM_ERROR("couldn't set HDR metadata in infoframe\n");
+ return;
+ }
+
+ intel_write_infoframe(encoder, crtc_state, );
+}
+
static void intel_hdmi_set_avi_infoframe(struct intel_encoder *encoder,
const struct intel_crtc_state
*crtc_state,
const struct drm_connector_state
*conn_state)
@@ -883,6 +906,10 @@ static void hsw_set_infoframes(struct intel_encoder
*encoder,
intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
intel_hdmi_set_spd_infoframe(encoder, crtc_state);
intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
+
+ /* Set Dynamic Range and Mastering Infoframe if supported and changed */
+ if (conn_state->hdr_metadata_changed)
+ intel_hdmi_set_drm_infoframe(encoder, crtc_state, conn_state);
}
void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
--
1.9.1
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[Intel-gfx] [v3 04/14] drm: Parse Colorimetry data block from EDID
CEA 861.3 spec adds colorimetry data block for HDMI.
Parsing the block to get the colorimetry data from
panel.
v2: Rebase
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_edid.c | 24
include/drm/drm_connector.h | 2 ++
2 files changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index d12b74e..344d8c1 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -3818,6 +3818,28 @@ static void fixup_detailed_cea_mode_clock(struct
drm_display_mode *mode)
mode->clock = clock;
}
+static bool cea_db_is_hdmi_colorimetry_data_block(const u8 *db)
+{
+ if (cea_db_tag(db) != DATA_BLOCK_EXTENDED_TAG)
+ return false;
+
+ if (db[1] != COLORIMETRY_DATA_BLOCK)
+ return false;
+
+ return true;
+}
+
+static void
+drm_parse_colorimetry_data_block(struct drm_connector *connector, const u8 *db)
+{
+ struct drm_hdmi_info *info = >display_info.hdmi;
+ uint16_t len;
+
+ len = cea_db_payload_len(db);
+ info->colorimetry = db[2];
+}
+
+
static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db)
{
if (cea_db_tag(db) != DATA_BLOCK_EXTENDED_TAG)
@@ -4513,6 +4535,8 @@ static void drm_parse_cea_ext(struct drm_connector
*connector,
drm_parse_y420cmdb_bitmap(connector, db);
if (cea_db_is_hdmi_hdr_metadata_block(db))
drm_parse_hdr_metadata_block(connector, db);
+ if (cea_db_is_hdmi_colorimetry_data_block(db))
+ drm_parse_colorimetry_data_block(connector, db);
}
}
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 2ee45dc..90ce364 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -206,6 +206,8 @@ struct drm_hdmi_info {
/** @y420_dc_modes: bitmap of deep color support index */
u8 y420_dc_modes;
+
+ u8 colorimetry;
};
/**
--
1.9.1
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[Intel-gfx] [v3 03/14] drm: Parse HDR metadata info from EDID
HDR metadata block is introduced in CEA-861.3 spec.
Parsing the same to get the panel's HDR metadata.
v2: Rebase and added Ville's POC changes to the patch.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_edid.c | 45 +
1 file changed, 45 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 106fd38..d12b74e 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -3818,6 +3818,49 @@ static void fixup_detailed_cea_mode_clock(struct
drm_display_mode *mode)
mode->clock = clock;
}
+static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db)
+{
+ if (cea_db_tag(db) != DATA_BLOCK_EXTENDED_TAG)
+ return false;
+
+ if (db[1] != HDR_STATIC_METADATA_BLOCK)
+ return false;
+
+ return true;
+}
+
+static uint16_t eotf_supported(const u8 *edid_ext)
+{
+
+ return edid_ext[2] &
+ (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
+BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
+BIT(HDMI_EOTF_SMPTE_ST2084));
+
+}
+
+static uint16_t hdr_metadata_type(const u8 *edid_ext)
+{
+
+ return edid_ext[3] &
+ BIT(HDMI_STATIC_METADATA_TYPE1);
+}
+
+static void
+drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
+{
+ uint16_t len;
+
+ len = cea_db_payload_len(db);
+ connector->hdr_metadata.eotf = eotf_supported(db);
+ connector->hdr_metadata.metadata_type = hdr_metadata_type(db);
+
+ if (len >= 5)
+ connector->hdr_metadata.max_fall = db[5];
+ if (len >= 4)
+ connector->hdr_metadata.max_cll = db[4];
+}
+
static void
drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
{
@@ -4468,6 +4511,8 @@ static void drm_parse_cea_ext(struct drm_connector
*connector,
drm_parse_hdmi_forum_vsdb(connector, db);
if (cea_db_is_y420cmdb(db))
drm_parse_y420cmdb_bitmap(connector, db);
+ if (cea_db_is_hdmi_hdr_metadata_block(db))
+ drm_parse_hdr_metadata_block(connector, db);
}
}
--
1.9.1
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[Intel-gfx] [v3 06/14] drm: Add HDR capability field to plane structure
Hardware may have HDR capability on certain plane
engines. Enabling the same in drm plane structure
so that this can be communicated to user space.
Each drm driver should set this flag to true for planes
which support HDR.
v2: Rebase
Signed-off-by: Uma Shankar
---
include/drm/drm_plane.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h
index 6078c70..206eefc 100644
--- a/include/drm/drm_plane.h
+++ b/include/drm/drm_plane.h
@@ -638,6 +638,9 @@ struct drm_plane {
/** @type: Type of plane, see drm_plane_type for details. */
enum drm_plane_type type;
+ /* Value of true:1 means HDR is supported */
+ bool hdr_supported;
+
/**
* @index: Position inside the mode_config.list, can be used as an array
* index. It is invariant over the lifetime of the plane.
--
1.9.1
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[Intel-gfx] [v3 02/14] drm: Add CEA extended tag blocks and HDR bitfield macros
Add bit field and macro for extended tag in CEA block. Also, declare macros for HDR metadata block. v2: Rebase Signed-off-by: Uma Shankar --- drivers/gpu/drm/drm_edid.c | 16 1 file changed, 16 insertions(+) diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index b506e36..106fd38 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -2843,6 +2843,22 @@ static int drm_cvt_modes(struct drm_connector *connector, #define EDID_CEA_YCRCB422 (1 << 4) #define EDID_CEA_VCDB_QS (1 << 6) +#define DATA_BLOCK_EXTENDED_TAG0x07 +#define VIDEO_CAPABILITY_DATA_BLOCK0x0 +#define VSVD_DATA_BLOCK0x1 +#define COLORIMETRY_DATA_BLOCK 0x5 +#define HDR_STATIC_METADATA_BLOCK 0x6 + +/* HDR Metadata Block: Bit fields */ +#define SUPPORTED_EOTF_MASK0x3f +#define TRADITIONAL_GAMMA_SDR (0x1 << 0) +#define TRADITIONAL_GAMMA_HDR (0x1 << 1) +#define SMPTE_ST2084 (0x1 << 2) +#define FUTURE_EOTF(0x1 << 3) +#define RESERVED_EOTF (0x3 << 4) + +#define STATIC_METADATA_TYPE1 (0x1 << 0) + /* * Search EDID for CEA extension block. */ -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v3 01/14] drm: Add HDR source metadata property
This patch adds a blob property to get HDR metadata
information from userspace. This will be send as part
of AVI Infoframe to panel.
v2: Rebase and modified the metadata structure elements
as per Ville's POC changes.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_connector.c | 6 ++
include/drm/drm_connector.h | 10 ++
include/drm/drm_mode_config.h | 6 ++
include/linux/hdmi.h| 10 ++
include/uapi/drm/drm_mode.h | 16
5 files changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index da8ae80..361fcda 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -1027,6 +1027,12 @@ int drm_connector_create_standard_properties(struct
drm_device *dev)
return -ENOMEM;
dev->mode_config.non_desktop_property = prop;
+ prop = drm_property_create(dev, DRM_MODE_PROP_BLOB,
+ "HDR_SOURCE_METADATA", 0);
+ if (!prop)
+ return -ENOMEM;
+ dev->mode_config.hdr_source_metadata_property = prop;
+
return 0;
}
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 9be2181..2ee45dc 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -520,6 +520,13 @@ struct drm_connector_state {
* and the connector bpc limitations obtained from edid.
*/
u8 max_bpc;
+
+ /**
+* @metadata_blob_ptr:
+* DRM blob property for HDR metadata
+*/
+ struct drm_property_blob *hdr_source_metadata_blob_ptr;
+ u8 hdr_metadata_changed : 1;
};
/**
@@ -1154,6 +1161,9 @@ struct drm_connector {
* _mode_config.connector_free_work.
*/
struct llist_node free_node;
+
+ /* HDR metdata */
+ struct hdr_static_metadata hdr_metadata;
};
#define obj_to_connector(x) container_of(x, struct drm_connector, base)
diff --git a/include/drm/drm_mode_config.h b/include/drm/drm_mode_config.h
index 69ccd27..4b3211b 100644
--- a/include/drm/drm_mode_config.h
+++ b/include/drm/drm_mode_config.h
@@ -836,6 +836,12 @@ struct drm_mode_config {
*/
struct drm_property *writeback_out_fence_ptr_property;
+ /*
+* hdr_metadata_property: Connector property containing hdr metatda
+* This will be provided by userspace compositors based on HDR content
+*/
+ struct drm_property *hdr_source_metadata_property;
+
/* dumb ioctl parameters */
uint32_t preferred_depth, prefer_shadow;
diff --git a/include/linux/hdmi.h b/include/linux/hdmi.h
index d2bacf5..bed3e08 100644
--- a/include/linux/hdmi.h
+++ b/include/linux/hdmi.h
@@ -137,6 +137,16 @@ enum hdmi_content_type {
HDMI_CONTENT_TYPE_GAME,
};
+enum hdmi_metadata_type {
+ HDMI_STATIC_METADATA_TYPE1 = 1,
+};
+
+enum hdmi_eotf {
+ HDMI_EOTF_TRADITIONAL_GAMMA_SDR,
+ HDMI_EOTF_TRADITIONAL_GAMMA_HDR,
+ HDMI_EOTF_SMPTE_ST2084,
+};
+
struct hdmi_avi_infoframe {
enum hdmi_infoframe_type type;
unsigned char version;
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index a439c2e..5012af2 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -630,6 +630,22 @@ struct drm_color_lut {
__u16 reserved;
};
+/* HDR Metadata */
+struct hdr_static_metadata {
+ uint8_t eotf;
+ uint8_t metadata_type;
+ struct {
+ uint16_t x, y;
+ } display_primaries[3];
+ struct {
+ uint16_t x, y;
+ } white_point;
+ uint16_t max_mastering_display_luminance;
+ uint16_t min_mastering_display_luminance;
+ uint16_t max_fall;
+ uint16_t max_cll;
+};
+
#define DRM_MODE_PAGE_FLIP_EVENT 0x01
#define DRM_MODE_PAGE_FLIP_ASYNC 0x02
#define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4
--
1.9.1
___
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[Intel-gfx] [v3 05/14] drm/i915: Attach HDR metadata property to connector
Attach HDR metadata property to connector object. v2: Rebase Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/intel_hdmi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 07e803a..8a1e5cb 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -2154,6 +2154,8 @@ static void intel_hdmi_destroy(struct drm_connector *connector) intel_attach_aspect_ratio_property(connector); drm_connector_attach_content_type_property(connector); connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE; + drm_object_attach_property(>base, + connector->dev->mode_config.hdr_source_metadata_property, 0); if (!HAS_GMCH_DISPLAY(dev_priv)) drm_connector_attach_max_bpc_property(connector, 8, 12); -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v3 00/14] Add HDR Metadata Parsing and handling in DRM layer
This patch series enables HDR support in drm. It basically defines HDR metadata structures, property to pass content (after blending) metadata from user space compositors to driver. Dynamic Range and Mastering infoframe creation and sending. ToDo: 1. We need to get the color framework in place for all planes which support HDR content in hardware. This is already in progres and patches are out for review in mailing list. 2. UserSpace/Compositors: Blending policies and metadata blob creation and passing to driver. Work is already in progress by Intel's middleware teams on wayland and we should be getting the initial version pretty soon for review. Please review and share your feedbacks/suggestions. Note: The intention for these patches is to get a design feedback on the uapi changes, generic property design and infoframe handling. This cannot get merged as of now without the userspace support in place. A POC has already been developed by Ville based on wayland. Please refer below link to see the component interactions and usage: https://lists.freedesktop.org/archives/wayland-devel/2017-December/036403.html v2: Updated Ville's POC changes to the patch series.Incorporated cleanups and fixes from Ville. Rebase on latest drm-tip. v3: Fixed a warning causing builds to break on CI. No major change. Note: It took a while to float this version as there was no userspace consumer for it and dependency on full userspace stack. However, things are falling in place now. Media driver and VAAPI changes for HDR are already out, with compositors changes also expected to land soon. Uma Shankar (10): drm: Add HDR source metadata property drm: Add CEA extended tag blocks and HDR bitfield macros drm: Parse HDR metadata info from EDID drm: Parse Colorimetry data block from EDID drm/i915: Attach HDR metadata property to connector drm: Add HDR capability field to plane structure drm: Implement HDR source metadata set and get property handling drm: Enable HDR infoframe support drm/i915: Write HDR infoframe and send to panel drm/i915:Enabled Modeset when HDR Infoframe changes Ville Syrjälä (4): drm/i915: [DO NOT MERGE] hack for glk board outputs drm/i915: Add HLG EOTF drm/i915: Enable infoframes on GLK+ for HDR drivers/video: Constantify function argument for HDMI infoframe log drivers/gpu/drm/drm_atomic.c| 2 + drivers/gpu/drm/drm_atomic_uapi.c | 13 drivers/gpu/drm/drm_connector.c | 6 ++ drivers/gpu/drm/drm_edid.c | 143 drivers/gpu/drm/i915/i915_reg.h | 4 + drivers/gpu/drm/i915/intel_atomic.c | 15 +++- drivers/gpu/drm/i915/intel_bios.c | 7 ++ drivers/gpu/drm/i915/intel_hdmi.c | 43 ++- drivers/video/hdmi.c| 129 include/drm/drm_connector.h | 12 +++ include/drm/drm_edid.h | 4 + include/drm/drm_mode_config.h | 6 ++ include/drm/drm_plane.h | 3 + include/linux/hdmi.h| 33 + include/uapi/drm/drm_mode.h | 16 15 files changed, 433 insertions(+), 3 deletions(-) -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 7/7] drm/i915/psr: Disable DRRS if enabled when enabling PSR from debugfs
On Mon, 2018-11-12 at 11:17 +0100, Maarten Lankhorst wrote:
> Op 09-11-18 om 21:20 schreef José Roberto de Souza:
> > If panel supports DRRS and PSR and if driver is loaded without PSR
> > enabled, driver will enable DRRS as expected but if PSR is enabled
> > by
> > debugfs latter it will keep PSR and DRRS enabled causing possible
> > problems as DRRS will lower the refresh rate while PSR enabled.
> >
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108341
> > Cc: Maarten Lankhorst
> > Cc: Dhinakaran Pandiyan
> > Signed-off-by: José Roberto de Souza
> > ---
> > drivers/gpu/drm/i915/intel_psr.c | 5 -
> > 1 file changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > b/drivers/gpu/drm/i915/intel_psr.c
> > index 853e3f1370a0..bfc6a08b5cf4 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -904,8 +904,11 @@ int intel_psr_set_debugfs_mode(struct
> > drm_i915_private *dev_priv,
> >
> > intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
> >
> > - if (dev_priv->psr.prepared && enable)
> > + if (dev_priv->psr.prepared && enable) {
> > + if (crtc_state)
> > + intel_edp_drrs_disable(dp, crtc_state);
> > intel_psr_enable_locked(dev_priv, crtc_state);
> > + }
> >
> > mutex_unlock(_priv->psr.lock);
> > return ret;
>
> I've considered this, but I thought it was a feature, not a bug. It's
> a pain to track
> how we handle this as intended.
>
> kms_frontbuffer_tracking is also controlling DRRS during the test, so
> perhaps simply
> fix the test?
>
> It seems the no_drrs test simply checks that if PSR is enabled, we
> don't have drrs
> enabled. We probably care about the default configuration, so I would
> simply disable
> the pipe, update the PSR flag, and then start running the tests. Else
> the only thing
> we test is that debugfs disables DRRS. Not that the default modeset
> path prevents
> PSR and DRRS simultaneously.
>
> ~Maarten
>
> Maybe something like below?
>
> Perhaps move the drrs manipulation functions from
> kms_frontbuffer_tracking to lib/kms_psr.c
>
> 8<---
> diff --git a/tests/kms_psr.c b/tests/kms_psr.c
> index 9767f475bf23..ffc356df06ce 100644
> --- a/tests/kms_psr.c
> +++ b/tests/kms_psr.c
> @@ -414,9 +414,6 @@ int main(int argc, char *argv[])
> kmstest_set_vt_graphics_mode();
> data.devid = intel_get_drm_devid(data.drm_fd);
>
> - if (!data.with_psr_disabled)
> - psr_enable(data.debugfs_fd);
> -
> igt_require_f(sink_support(),
> "Sink does not support PSR\n");
>
> @@ -428,18 +425,25 @@ int main(int argc, char *argv[])
> }
>
> igt_subtest("basic") {
> - setup_test_plane(, DRM_PLANE_TYPE_PRIMARY);
> - igt_assert(psr_wait_entry_if_enabled());
> - test_cleanup();
> - }
> + /* Disable display to get a default setup. */
> + igt_display_commit2(,
> data.display.is_atomic ? COMMIT_ATOMIC : COMMIT_LEGACY);
> +
> + if (!data.with_psr_disabled)
> + psr_enable(data.debugfs_fd);
>
> - igt_subtest("no_drrs") {
> setup_test_plane(, DRM_PLANE_TYPE_PRIMARY);
> igt_assert(psr_wait_entry_if_enabled());
> igt_assert(drrs_disabled());
> test_cleanup();
This makes a lot more sense to me, ensuring that DRRS does not get
enabled in the default code path was the goal of the no-drrs test.
-DK
> }
>
> + igt_fixture {
> + drrs_disable();
> +
> + if (!data.with_psr_disabled)
> + psr_enable(data.debugfs_fd);
> + }
> +
> for (op = PAGE_FLIP; op <= RENDER; op++) {
> igt_subtest_f("primary_%s", op_str(op)) {
> data.op = op;
>
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/icl: combo port vswing programming changes per BSPEC (rev4)
== Series Details == Series: drm/i915/icl: combo port vswing programming changes per BSPEC (rev4) URL : https://patchwork.freedesktop.org/series/53340/ State : success == Summary == CI Bug Log - changes from CI_DRM_5296 -> Patchwork_11072 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/53340/revisions/4/mbox/ Known issues Here are the changes found in Patchwork_11072 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_hangcheck: - fi-bwr-2160:PASS -> DMESG-FAIL [fdo#108735] [fdo#108735]: https://bugs.freedesktop.org/show_bug.cgi?id=108735 Participating hosts (48 -> 44) -- Additional (1): fi-byt-j1900 Missing(5): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-ctg-p8600 Build changes - * Linux: CI_DRM_5296 -> Patchwork_11072 CI_DRM_5296: 70751bd8a3f27b035d203ecafcad452f4d7c2c15 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4745: 3b52e8a5809a4e860350c59476a456745cd9fee0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_11072: cc1e8bb822a1ecae4953f8f6a45517f59815f851 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == cc1e8bb822a1 drm/i915/icl: combo port vswing programming changes per BSPEC == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11072/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for Add Colorspace connector property interface (rev5)
== Series Details ==
Series: Add Colorspace connector property interface (rev5)
URL : https://patchwork.freedesktop.org/series/47132/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5296_full -> Patchwork_11068_full
Summary
---
**WARNING**
Minor unknown changes coming with Patchwork_11068_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_11068_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_11068_full:
### IGT changes ###
Warnings
* igt@pm_rc6_residency@rc6-accuracy:
- shard-snb: PASS -> SKIP
* igt@tools_test@tools_test:
- shard-skl: SKIP -> PASS
Known issues
Here are the changes found in Patchwork_11068_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@debugfs_test@read_all_entries_display_off:
- shard-skl: PASS -> INCOMPLETE [fdo#104108]
* igt@i915_suspend@fence-restore-untiled:
- {shard-iclb}: PASS -> INCOMPLETE [fdo#107713]
* igt@kms_busy@extended-modeset-hang-newfb-render-b:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#107956]
- {shard-iclb}: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
- shard-glk: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_ccs@pipe-c-bad-pixel-format:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107724] +21
* igt@kms_chv_cursor_fail@pipe-b-256x256-right-edge:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107724] / [fdo#108336] +13
* igt@kms_color@pipe-a-degamma:
- shard-apl: PASS -> FAIL [fdo#104782] / [fdo#108145]
* igt@kms_color@pipe-b-degamma:
- shard-apl: PASS -> FAIL [fdo#104782]
* igt@kms_color@pipe-c-ctm-green-to-red:
- shard-skl: PASS -> FAIL [fdo#107201]
* igt@kms_cursor_crc@cursor-128x42-sliding:
- shard-glk: PASS -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-64x21-random:
- shard-apl: PASS -> FAIL [fdo#103232] +11
* igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-apl: PASS -> FAIL [fdo#103191] / [fdo#103232]
* igt@kms_cursor_legacy@all-pipes-torture-move:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107122]
* igt@kms_draw_crc@draw-method-rgb565-render-ytiled:
- shard-skl: PASS -> FAIL [fdo#103184]
* igt@kms_draw_crc@fill-fb:
- {shard-iclb}: PASS -> WARN [fdo#108336]
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-glk: PASS -> FAIL [fdo#103833] / [fdo#105681]
- {shard-iclb}: PASS -> FAIL [fdo#103833] / [fdo#105681]
* igt@kms_fbcon_fbt@psr-suspend:
- shard-skl: NOTRUN -> FAIL [fdo#107882]
* igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible:
- shard-hsw: PASS -> DMESG-WARN [fdo#102614]
* igt@kms_flip@dpms-vs-vblank-race:
- shard-kbl: PASS -> FAIL [fdo#103060] +1
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
- shard-apl: PASS -> FAIL [fdo#103167] +6
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
- {shard-iclb}: PASS -> DMESG-FAIL [fdo#107724] +7
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-pwrite:
- shard-glk: PASS -> FAIL [fdo#103167] +3
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#105959] /
[fdo#107773]
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt:
- {shard-iclb}: NOTRUN -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move:
- {shard-iclb}: PASS -> FAIL [fdo#103167] +1
* igt@kms_plane@pixel-format-pipe-a-planes:
- shard-apl: PASS -> FAIL [fdo#103166]
* igt@kms_plane@plane-position-covered-pipe-a-planes:
- {shard-iclb}: NOTRUN -> FAIL [fdo#103166]
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-skl: NOTRUN -> FAIL [fdo#108145] +1
* igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
- shard-apl: PASS -> FAIL [fdo#108145]
* igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
- shard-glk: PASS -> FAIL [fdo#103166] +1
- {shard-iclb}: PASS -> FAIL [fdo#103166] +2
* igt@kms_psr@no_drrs:
- {shard-iclb}: PASS -> FAIL [fdo#108341]
* {igt@kms_rotation_crc@multiplane-rotation-cropping-top}:
- shard-glk: PASS -> DMESG-FAIL [fdo#105763] / [fdo#106538]
* igt@kms_sysfs_edid_timing:
-
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/icl: combo port vswing programming changes per BSPEC (rev4)
== Series Details == Series: drm/i915/icl: combo port vswing programming changes per BSPEC (rev4) URL : https://patchwork.freedesktop.org/series/53340/ State : warning == Summary == $ dim checkpatch origin/drm-tip cc1e8bb822a1 drm/i915/icl: combo port vswing programming changes per BSPEC -:256: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #256: FILE: drivers/gpu/drm/i915/intel_ddi.c:857: + icl_get_combo_buf_trans(dev_priv, port, INTEL_OUTPUT_HDMI, + 54, _entries); total: 0 errors, 0 warnings, 1 checks, 341 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4] drm/i915/icl: combo port vswing programming changes per BSPEC
From: Clint Taylor
In August 2018 the BSPEC changed the ICL port programming sequence to
closely resemble earlier gen programming sequence. Restrict combo phy to
HBR max rate unless eDP panel is connected to port.
v2: remove debug code that Imre found
v3: simplify translation table if-else
v4: edp translation table now based on link rate and low_swing
BSpec: 21257
Cc: Ville Syrjälä
Cc: Imre Deak
Cc: Rodrigo Vivi
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/i915_reg.h | 4 +
drivers/gpu/drm/i915/intel_ddi.c | 240 ++-
drivers/gpu/drm/i915/intel_dp.c | 4 +-
3 files changed, 95 insertions(+), 153 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0a7d605..29acdb9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1866,6 +1866,10 @@ enum i915_power_well_id {
#define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 7))
#define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 7))
+#define ICL_PORT_TX_DW7_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(7, port))
+#define ICL_PORT_TX_DW7_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(7, port))
+#define ICL_PORT_TX_DW7_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port))
+#define ICL_PORT_TX_DW7_LN(port, ln) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port))
#define N_SCALAR(x) ((x) << 24)
#define N_SCALAR_MASK(0x7F << 24)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index f3e1d6a..33bf77b 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -494,103 +494,58 @@ struct cnl_ddi_buf_trans {
{ 0x2, 0x7F, 0x3F, 0x00, 0x00 },/* 400 400 0.0 */
};
-struct icl_combo_phy_ddi_buf_trans {
- u32 dw2_swing_select;
- u32 dw2_swing_scalar;
- u32 dw4_scaling;
-};
-
-/* Voltage Swing Programming for VccIO 0.85V for DP */
-static const struct icl_combo_phy_ddi_buf_trans
icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = {
- /* Voltage mV db*/
- { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
- { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
- { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
- { 0x2, 0x98, 0x900F }, /* 400 9.5 */
- { 0xB, 0x70, 0x0018 }, /* 600 0.0 */
- { 0xB, 0x70, 0x3015 }, /* 600 3.5 */
- { 0xB, 0x70, 0x6012 }, /* 600 6.0 */
- { 0x5, 0x00, 0x0018 }, /* 800 0.0 */
- { 0x5, 0x00, 0x3015 }, /* 800 3.5 */
- { 0x6, 0x98, 0x0018 }, /* 12000.0 */
-};
-
-/* FIXME - After table is updated in Bspec */
-/* Voltage Swing Programming for VccIO 0.85V for eDP */
-static const struct icl_combo_phy_ddi_buf_trans
icl_combo_phy_ddi_translations_edp_0_85V[] = {
- /* Voltage mV db*/
- { 0x0, 0x00, 0x00 },/* 200 0.0 */
- { 0x0, 0x00, 0x00 },/* 200 1.5 */
- { 0x0, 0x00, 0x00 },/* 200 4.0 */
- { 0x0, 0x00, 0x00 },/* 200 6.0 */
- { 0x0, 0x00, 0x00 },/* 250 0.0 */
- { 0x0, 0x00, 0x00 },/* 250 1.5 */
- { 0x0, 0x00, 0x00 },/* 250 4.0 */
- { 0x0, 0x00, 0x00 },/* 300 0.0 */
- { 0x0, 0x00, 0x00 },/* 300 1.5 */
- { 0x0, 0x00, 0x00 },/* 350 0.0 */
-};
-
-/* Voltage Swing Programming for VccIO 0.95V for DP */
-static const struct icl_combo_phy_ddi_buf_trans
icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {
- /* Voltage mV db*/
- { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
- { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
- { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
- { 0x2, 0x98, 0x900F }, /* 400 9.5 */
- { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
- { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
- { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
- { 0x5, 0x76, 0x0018 }, /* 800 0.0 */
- { 0x5, 0x76, 0x3015 }, /* 800 3.5 */
- { 0x6, 0x98, 0x0018 }, /* 12000.0 */
+/* icl_combo_phy_ddi_translations */
+static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[]
= {
+ /* NT mV Trans mV db*/
+ { 0xA, 0x35, 0x3F, 0x00, 0x00 },/* 350 350 0.0 */
+ { 0xA, 0x4F, 0x37, 0x00, 0x08 },/* 350 500 3.1 */
+ { 0xC, 0x71, 0x2F, 0x00, 0x10 },/* 350 700 6.0 */
+ { 0x6, 0x7F, 0x2B, 0x00, 0x14 },/* 350 900 8.2 */
+ { 0xA, 0x4C, 0x3F, 0x00, 0x00 },/* 500 500 0.0 */
+ { 0xC, 0x73, 0x34, 0x00, 0x0B },/* 500 700 2.9 */
+ { 0x6, 0x7F, 0x2F, 0x00,
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/2] drm/i915: Don't use DDB allocation when choosing gen9 watermark method
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Don't use DDB allocation when
choosing gen9 watermark method
URL : https://patchwork.freedesktop.org/series/53901/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5296_full -> Patchwork_11067_full
Summary
---
**WARNING**
Minor unknown changes coming with Patchwork_11067_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_11067_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_11067_full:
### IGT changes ###
Possible regressions
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- {shard-iclb}: NOTRUN -> FAIL
* igt@kms_rmfb@rmfb-ioctl:
- {shard-iclb}: PASS -> FAIL +5
Warnings
* igt@kms_plane_lowres@pipe-b-tiling-none:
- {shard-iclb}: PASS -> SKIP
* igt@pm_rc6_residency@rc6-accuracy:
- shard-snb: PASS -> SKIP
* igt@tools_test@tools_test:
- shard-skl: SKIP -> PASS
Known issues
Here are the changes found in Patchwork_11067_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_contexts:
- {shard-iclb}: NOTRUN -> DMESG-FAIL [fdo#108569]
* igt@kms_busy@extended-modeset-hang-newfb-render-b:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#107956]
- {shard-iclb}: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
- shard-glk: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_chv_cursor_fail@pipe-b-64x64-right-edge:
- shard-skl: PASS -> FAIL [fdo#104671]
* igt@kms_color@pipe-a-degamma:
- shard-apl: PASS -> FAIL [fdo#104782] / [fdo#108145]
* igt@kms_color@pipe-b-degamma:
- shard-apl: PASS -> FAIL [fdo#104782]
* igt@kms_color@pipe-c-ctm-green-to-red:
- shard-skl: PASS -> FAIL [fdo#107201]
* igt@kms_cursor_crc@cursor-256x256-onscreen:
- shard-glk: NOTRUN -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-64x21-random:
- shard-apl: PASS -> FAIL [fdo#103232] +5
* igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773] +1
- shard-glk: PASS -> FAIL [fdo#103232]
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-glk: PASS -> FAIL [fdo#103833] / [fdo#105681]
- {shard-iclb}: PASS -> FAIL [fdo#103833] / [fdo#105681]
* igt@kms_fbcon_fbt@psr-suspend:
- shard-skl: NOTRUN -> FAIL [fdo#107882]
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: PASS -> FAIL [fdo#105363]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff:
- shard-apl: PASS -> FAIL [fdo#103167] +1
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc:
- shard-glk: PASS -> FAIL [fdo#103167] +5
* igt@kms_frontbuffer_tracking@fbc-stridechange:
- {shard-iclb}: PASS -> FAIL [fdo#105683] / [fdo#108040]
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-gtt:
- {shard-iclb}: PASS -> FAIL [fdo#103167] +2
* igt@kms_plane@plane-position-covered-pipe-a-planes:
- shard-apl: PASS -> FAIL [fdo#103166] +3
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-skl: NOTRUN -> FAIL [fdo#108145] +1
* igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
- shard-apl: PASS -> FAIL [fdo#108145]
* igt@kms_plane_multiple@atomic-pipe-c-tiling-x:
- shard-glk: PASS -> FAIL [fdo#103166]
* igt@kms_plane_multiple@atomic-pipe-c-tiling-y:
- {shard-iclb}: PASS -> FAIL [fdo#103166]
* {igt@kms_rotation_crc@multiplane-rotation-cropping-top}:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107724] +1
- shard-glk: PASS -> DMESG-FAIL [fdo#105763] / [fdo#106538]
* igt@perf@polling:
- shard-hsw: PASS -> FAIL [fdo#102252]
* igt@pm_rpm@debugfs-read:
- {shard-iclb}: PASS -> INCOMPLETE [fdo#108840]
* igt@pm_rpm@dpms-lpsp:
- shard-skl: NOTRUN -> INCOMPLETE [fdo#107807]
Possible fixes
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
- shard-apl: FAIL [fdo#105458] / [fdo#106510] -> PASS
* igt@kms_color@pipe-b-ctm-negative:
- shard-skl: FAIL [fdo#107361] -> PASS
* igt@kms_color@pipe-c-degamma:
- shard-apl: FAIL [fdo#104782] -> PASS
* igt@kms_cursor_crc@cursor-256x85-onscreen:
-
[Intel-gfx] ✗ Fi.CI.BAT: failure for Add HDR Metadata Parsing and handling in DRM layer (rev2)
== Series Details == Series: Add HDR Metadata Parsing and handling in DRM layer (rev2) URL : https://patchwork.freedesktop.org/series/25091/ State : failure == Summary == CALLscripts/checksyscalls.sh DESCEND objtool CHK include/generated/compile.h CC [M] drivers/gpu/drm/i915/intel_hdmi.o drivers/gpu/drm/i915/intel_hdmi.c: In function ‘intel_hdmi_set_drm_infoframe’: drivers/gpu/drm/i915/intel_hdmi.c:507:24: error: passing argument 1 of ‘intel_write_infoframe’ from incompatible pointer type [-Werror=incompatible-pointer-types] intel_write_infoframe(encoder, crtc_state, ); ^~~ drivers/gpu/drm/i915/intel_hdmi.c:460:13: note: expected ‘struct intel_encoder *’ but argument is of type ‘struct drm_encoder *’ static void intel_write_infoframe(struct intel_encoder *encoder, ^ drivers/gpu/drm/i915/intel_hdmi.c: In function ‘hsw_set_infoframes’: drivers/gpu/drm/i915/intel_hdmi.c:922:32: error: passing argument 1 of ‘intel_hdmi_set_drm_infoframe’ from incompatible pointer type [-Werror=incompatible-pointer-types] intel_hdmi_set_drm_infoframe(encoder, crtc_state, conn_state); ^~~ drivers/gpu/drm/i915/intel_hdmi.c:484:13: note: expected ‘struct drm_encoder *’ but argument is of type ‘struct intel_encoder *’ static void intel_hdmi_set_drm_infoframe(struct drm_encoder *encoder, ^~~~ cc1: all warnings being treated as errors scripts/Makefile.build:291: recipe for target 'drivers/gpu/drm/i915/intel_hdmi.o' failed make[4]: *** [drivers/gpu/drm/i915/intel_hdmi.o] Error 1 scripts/Makefile.build:516: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:516: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:516: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1060: recipe for target 'drivers' failed make: *** [drivers] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v2 12/14] drm/i915: Enable infoframes on GLK+ for HDR
From: Ville Syrjälä
This patch enables infoframes on GLK+ to be
used to send HDR metadata to HDMI sink.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 4
drivers/gpu/drm/i915/intel_hdmi.c | 12 +---
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0a7d605..6f44d02 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4591,6 +4591,7 @@ enum {
#define VIDEO_DIP_FREQ_MASK (3 << 16)
/* HSW and later: */
#define DRM_DIP_ENABLE (1 << 28)
+#define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28)
#define PSR_VSC_BIT_7_SET(1 << 27)
#define VSC_SELECT_MASK (0x3 << 25)
#define VSC_SELECT_SHIFT 25
@@ -8015,6 +8016,7 @@ enum {
#define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
#define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
#define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320
+#define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440
#define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240
#define _HSW_VIDEO_DIP_VS_ECC_A0x60280
#define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
@@ -8028,6 +8030,7 @@ enum {
#define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
#define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
#define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320
+#define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440
#define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240
#define _HSW_VIDEO_DIP_VS_ECC_B0x61280
#define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
@@ -8052,6 +8055,7 @@ enum {
#define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans,
_HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
#define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans,
_HSW_VIDEO_DIP_GCP_A)
#define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans,
_HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
+#define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(trans,
_GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4)
#define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans,
_ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
#define ICL_VIDEO_DIP_PPS_ECC(trans, i)_MMIO_TRANS2(trans,
_ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 6286c4a..5c2e3c9 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -123,6 +123,8 @@ static u32 hsw_infoframe_enable(unsigned int type)
return VIDEO_DIP_ENABLE_SPD_HSW;
case HDMI_INFOFRAME_TYPE_VENDOR:
return VIDEO_DIP_ENABLE_VS_HSW;
+ case HDMI_INFOFRAME_TYPE_DRM:
+ return VIDEO_DIP_ENABLE_DRM_GLK;
default:
MISSING_CASE(type);
return 0;
@@ -146,6 +148,8 @@ static u32 hsw_infoframe_enable(unsigned int type)
return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
case HDMI_INFOFRAME_TYPE_VENDOR:
return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
+ case HDMI_INFOFRAME_TYPE_DRM:
+ return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i);
default:
MISSING_CASE(type);
return INVALID_MMIO_REG;
@@ -432,7 +436,8 @@ static bool hsw_infoframe_enabled(struct intel_encoder
*encoder,
return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
- VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
+ VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
+ VIDEO_DIP_ENABLE_DRM_GLK);
}
/*
@@ -889,7 +894,8 @@ static void hsw_set_infoframes(struct intel_encoder
*encoder,
val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
-VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
+VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
+VIDEO_DIP_ENABLE_DRM_GLK);
if (!enable) {
I915_WRITE(reg, val);
@@ -908,7 +914,7 @@ static void hsw_set_infoframes(struct intel_encoder
*encoder,
intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
/* Set Dynamic Range and Mastering Infoframe if supported and changed */
- if (conn_state->hdr_metadata_changed)
+ if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
intel_hdmi_set_drm_infoframe(encoder, crtc_state, conn_state);
}
--
1.9.1
___
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[Intel-gfx] [v2 11/14] drm/i915: Add HLG EOTF
From: Ville Syrjälä
ADD HLG EOTF to the list of EOTF transfer functions
supported.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_edid.c | 4 ++--
include/linux/hdmi.h | 1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 5a7fc9b..fa86494 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -3857,8 +3857,8 @@ static uint16_t eotf_supported(const u8 *edid_ext)
return edid_ext[2] &
(BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
-BIT(HDMI_EOTF_SMPTE_ST2084));
-
+BIT(HDMI_EOTF_SMPTE_ST2084) |
+BIT(HDMI_EOTF_BT_2100_HLG));
}
static uint16_t hdr_metadata_type(const u8 *edid_ext)
diff --git a/include/linux/hdmi.h b/include/linux/hdmi.h
index ce00e1e..b5346c3 100644
--- a/include/linux/hdmi.h
+++ b/include/linux/hdmi.h
@@ -146,6 +146,7 @@ enum hdmi_eotf {
HDMI_EOTF_TRADITIONAL_GAMMA_SDR,
HDMI_EOTF_TRADITIONAL_GAMMA_HDR,
HDMI_EOTF_SMPTE_ST2084,
+ HDMI_EOTF_BT_2100_HLG,
};
struct hdmi_avi_infoframe {
--
1.9.1
___
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[Intel-gfx] [v2 13/14] drm/i915:Enabled Modeset when HDR Infoframe changes
This patch enables modeset whenever HDR metadata
needs to be updated to sink.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_atomic.c | 15 ++-
drivers/gpu/drm/i915/intel_hdmi.c | 4
2 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_atomic.c
b/drivers/gpu/drm/i915/intel_atomic.c
index 8cb02f2..72c3fcb 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -101,6 +101,16 @@ int intel_digital_connector_atomic_set_property(struct
drm_connector *connector,
return -EINVAL;
}
+static bool blob_equal(const struct drm_property_blob *a,
+ const struct drm_property_blob *b)
+{
+ if (a && b)
+ return a->length == b->length &&
+ !memcmp(a->data, b->data, a->length);
+
+ return !a == !b;
+}
+
int intel_digital_connector_atomic_check(struct drm_connector *conn,
struct drm_connector_state *new_state)
{
@@ -127,7 +137,10 @@ int intel_digital_connector_atomic_check(struct
drm_connector *conn,
new_conn_state->broadcast_rgb != old_conn_state->broadcast_rgb ||
new_conn_state->base.picture_aspect_ratio !=
old_conn_state->base.picture_aspect_ratio ||
new_conn_state->base.content_type !=
old_conn_state->base.content_type ||
- new_conn_state->base.scaling_mode !=
old_conn_state->base.scaling_mode)
+ new_conn_state->base.scaling_mode !=
+ old_conn_state->base.scaling_mode ||
+ !blob_equal(new_conn_state->base.hdr_source_metadata_blob_ptr,
+ old_conn_state->base.hdr_source_metadata_blob_ptr))
crtc_state->mode_changed = true;
return 0;
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 5c2e3c9..29b4218 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -491,6 +491,10 @@ static void intel_hdmi_set_drm_infoframe(struct
drm_encoder *encoder,
struct hdr_static_metadata *hdr_metadata;
int ret;
+ if (!conn_state->hdr_source_metadata_blob_ptr ||
+ conn_state->hdr_source_metadata_blob_ptr->length == 0)
+ return;
+
hdr_metadata = (struct hdr_static_metadata *)
conn_state->hdr_source_metadata_blob_ptr->data;
--
1.9.1
___
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[Intel-gfx] [v2 08/14] drm: Enable HDR infoframe support
Enable Dynamic Range and Mastering Infoframe for HDR
content, which is defined in CEA 861.3 spec.
The metadata will be computed based on blending
policy in userspace compositors and passed as a connector
property blob to driver. The same will be sent as infoframe
to panel which support HDR.
v2: Rebase and added Ville's POC changes.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_edid.c | 58
drivers/video/hdmi.c | 129 +
include/drm/drm_edid.h | 4 ++
include/linux/hdmi.h | 22
4 files changed, 213 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 344d8c1..5a7fc9b 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -4916,6 +4916,64 @@ void drm_set_preferred_mode(struct drm_connector
*connector,
EXPORT_SYMBOL(drm_set_preferred_mode);
/**
+ * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI AVI infoframe with
+ * HDR metadata from userspace
+ * @frame: HDMI AVI infoframe
+ * @hdr_source_metadata: hdr_source_metadata info from userspace
+ *
+ * Return: 0 on success or a negative error code on failure.
+ */
+int
+drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame,
+ void *hdr_metadata)
+{
+ struct hdr_static_metadata *hdr_source_metadata;
+ int err, i;
+
+ if (!frame || !hdr_metadata)
+ return -EINVAL;
+
+ err = hdmi_drm_infoframe_init(frame);
+ if (err < 0)
+ return err;
+
+ DRM_DEBUG_KMS("type = %x\n", frame->type);
+
+ hdr_source_metadata = (struct hdr_static_metadata *)hdr_metadata;
+
+ frame->length = sizeof(struct hdr_static_metadata);
+
+
+ frame->eotf = hdr_source_metadata->eotf;
+ frame->metadata_type = hdr_source_metadata->metadata_type;
+
+ for (i = 0; i < 3; i++) {
+ frame->display_primaries[i].x =
+ hdr_source_metadata->display_primaries[i].x;
+ frame->display_primaries[i].y =
+ hdr_source_metadata->display_primaries[i].y;
+ }
+
+ frame->white_point.x = hdr_source_metadata->white_point.x;
+ frame->white_point.y = hdr_source_metadata->white_point.y;
+
+ frame->max_mastering_display_luminance =
+ hdr_source_metadata->max_mastering_display_luminance;
+ frame->min_mastering_display_luminance =
+ hdr_source_metadata->min_mastering_display_luminance;
+
+ frame->max_cll = hdr_source_metadata->max_cll;
+ frame->max_fall = hdr_source_metadata->max_fall;
+
+ hdmi_infoframe_log(KERN_CRIT, NULL,
+ (union hdmi_infoframe *)frame);
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata);
+
+
+/**
* drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
* data from a DRM display mode
* @frame: HDMI AVI infoframe
diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c
index 799ae49..0937c8c 100644
--- a/drivers/video/hdmi.c
+++ b/drivers/video/hdmi.c
@@ -650,6 +650,93 @@ ssize_t hdmi_vendor_infoframe_pack(struct
hdmi_vendor_infoframe *frame,
return 0;
}
+/**
+ * hdmi_drm_infoframe_init() - initialize an HDMI Dynaminc Range and
+ * mastering infoframe
+ * @frame: HDMI DRM infoframe
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+int hdmi_drm_infoframe_init(struct hdmi_drm_infoframe *frame)
+{
+ memset(frame, 0, sizeof(*frame));
+
+ frame->type = HDMI_INFOFRAME_TYPE_DRM;
+ frame->version = 1;
+
+ return 0;
+}
+EXPORT_SYMBOL(hdmi_drm_infoframe_init);
+
+/**
+ * hdmi_drm_infoframe_pack() - write HDMI DRM infoframe to binary buffer
+ * @frame: HDMI DRM infoframe
+ * @buffer: destination buffer
+ * @size: size of buffer
+ *
+ * Packs the information contained in the @frame structure into a binary
+ * representation that can be written into the corresponding controller
+ * registers. Also computes the checksum as required by section 5.3.5 of
+ * the HDMI 1.4 specification.
+ *
+ * Returns the number of bytes packed into the binary buffer or a negative
+ * error code on failure.
+ */
+ssize_t hdmi_drm_infoframe_pack(struct hdmi_drm_infoframe *frame, void *buffer,
+ size_t size)
+{
+ u8 *ptr = buffer;
+ size_t length;
+ int i;
+
+ length = HDMI_INFOFRAME_HEADER_SIZE + frame->length;
+
+ if (size < length)
+ return -ENOSPC;
+
+ memset(buffer, 0, size);
+
+ ptr[0] = frame->type;
+ ptr[1] = frame->version;
+ ptr[2] = frame->length;
+ ptr[3] = 0; /* checksum */
+
+ /* start infoframe payload */
+ ptr += HDMI_INFOFRAME_HEADER_SIZE;
+
+ *ptr++ = frame->eotf;
+ *ptr++ = frame->metadata_type;
+
+ for (i = 0; i < 3; i++) {
+
[Intel-gfx] [v2 10/14] drm/i915: [DO NOT MERGE] hack for glk board outputs
From: Ville Syrjälä
This is to limit PORT C on GLK to drive only
HDMI. Not sure if this is mandatory, this is just
to test HDR on GLK HDMI.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_bios.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index 6d3e026..e1c48ad 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -1381,6 +1381,13 @@ static void parse_ddi_port(struct drm_i915_private
*dev_priv, enum port port,
is_hdmi = false;
}
+ if (IS_GEMINILAKE(dev_priv) && port == PORT_C) {
+ is_hdmi = true;
+ is_dvi = true;
+ is_dp = false;
+ is_edp = false;
+ }
+
info->supports_dvi = is_dvi;
info->supports_hdmi = is_hdmi;
info->supports_dp = is_dp;
--
1.9.1
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[Intel-gfx] [v2 14/14] drivers/video: Constantify function argument for HDMI infoframe log
From: Ville Syrjälä
Function argument for hdmi_drm_infoframe_log is made constant.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/video/hdmi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c
index 0937c8c..7ab8086 100644
--- a/drivers/video/hdmi.c
+++ b/drivers/video/hdmi.c
@@ -1383,8 +1383,8 @@ static void hdmi_audio_infoframe_log(const char *level,
* @frame: HDMI DRM infoframe
*/
static void hdmi_drm_infoframe_log(const char *level,
- struct device *dev,
- struct hdmi_drm_infoframe *frame)
+ struct device *dev,
+ const struct hdmi_drm_infoframe *frame)
{
int i;
--
1.9.1
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[Intel-gfx] [v2 07/14] drm: Implement HDR source metadata set and get property handling
HDR source metadata set and get property implemented in this
patch. The blob data is received from userspace and saved in
connector state, the same is returned as blob in get property
call to userspace.
v2: Rebase and added Ville's POC changes
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_atomic.c | 2 ++
drivers/gpu/drm/drm_atomic_uapi.c | 13 +
2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 5eb4013..4e71c6b 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -881,6 +881,8 @@ static void drm_atomic_connector_print_state(struct
drm_printer *p,
drm_printf(p, "connector[%u]: %s\n", connector->base.id,
connector->name);
drm_printf(p, "\tcrtc=%s\n", state->crtc ? state->crtc->name :
"(null)");
+ drm_printf(p, "\thdr_metadata_changed=%d\n",
+ state->hdr_metadata_changed);
if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
if (state->writeback_job && state->writeback_job->fb)
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index c408898..b721b12 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -686,6 +686,8 @@ static int drm_atomic_connector_set_property(struct
drm_connector *connector,
{
struct drm_device *dev = connector->dev;
struct drm_mode_config *config = >mode_config;
+ bool replaced = false;
+ int ret;
if (property == config->prop_crtc_id) {
struct drm_crtc *crtc = drm_crtc_find(dev, NULL, val);
@@ -734,6 +736,14 @@ static int drm_atomic_connector_set_property(struct
drm_connector *connector,
*/
if (state->link_status != DRM_LINK_STATUS_GOOD)
state->link_status = val;
+ } else if (property == config->hdr_source_metadata_property) {
+ ret = drm_atomic_replace_property_blob_from_id(dev,
+ >hdr_source_metadata_blob_ptr,
+ val,
+ -1, sizeof(struct hdr_static_metadata),
+ );
+ state->hdr_metadata_changed |= replaced;
+ return ret;
} else if (property == config->aspect_ratio_property) {
state->picture_aspect_ratio = val;
} else if (property == config->content_type_property) {
@@ -816,6 +826,9 @@ static int drm_atomic_connector_set_property(struct
drm_connector *connector,
*val = state->content_type;
} else if (property == connector->scaling_mode_property) {
*val = state->scaling_mode;
+ } else if (property == config->hdr_source_metadata_property) {
+ *val = (state->hdr_source_metadata_blob_ptr) ?
+ state->hdr_source_metadata_blob_ptr->base.id : 0;
} else if (property == connector->content_protection_property) {
*val = state->content_protection;
} else if (property == config->writeback_fb_id_property) {
--
1.9.1
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[Intel-gfx] [v2 09/14] drm/i915: Write HDR infoframe and send to panel
Enable writing of HDR metadata infoframe to panel.
The data will be provid by usersapace compositors, based
on blending policies and passsed to driver through a blob
property.
v2: Rebase
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_hdmi.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 8a1e5cb..6286c4a 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -475,6 +475,29 @@ static void intel_write_infoframe(struct intel_encoder
*encoder,
frame->any.type, buffer, len);
}
+/* Set Dynamic Range and Mastering Infoframe */
+static void intel_hdmi_set_drm_infoframe(struct drm_encoder *encoder,
+const struct intel_crtc_state
+*crtc_state,
+const struct drm_connector_state
+*conn_state)
+{
+ union hdmi_infoframe frame;
+ struct hdr_static_metadata *hdr_metadata;
+ int ret;
+
+ hdr_metadata = (struct hdr_static_metadata *)
+ conn_state->hdr_source_metadata_blob_ptr->data;
+
+ ret = drm_hdmi_infoframe_set_hdr_metadata(, hdr_metadata);
+ if (ret < 0) {
+ DRM_ERROR("couldn't set HDR metadata in infoframe\n");
+ return;
+ }
+
+ intel_write_infoframe(encoder, crtc_state, );
+}
+
static void intel_hdmi_set_avi_infoframe(struct intel_encoder *encoder,
const struct intel_crtc_state
*crtc_state,
const struct drm_connector_state
*conn_state)
@@ -883,6 +906,10 @@ static void hsw_set_infoframes(struct intel_encoder
*encoder,
intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
intel_hdmi_set_spd_infoframe(encoder, crtc_state);
intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
+
+ /* Set Dynamic Range and Mastering Infoframe if supported and changed */
+ if (conn_state->hdr_metadata_changed)
+ intel_hdmi_set_drm_infoframe(encoder, crtc_state, conn_state);
}
void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
--
1.9.1
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[Intel-gfx] [v2 06/14] drm: Add HDR capability field to plane structure
Hardware may have HDR capability on certain plane
engines. Enabling the same in drm plane structure
so that this can be communicated to user space.
Each drm driver should set this flag to true for planes
which support HDR.
v2: Rebase
Signed-off-by: Uma Shankar
---
include/drm/drm_plane.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h
index 6078c70..206eefc 100644
--- a/include/drm/drm_plane.h
+++ b/include/drm/drm_plane.h
@@ -638,6 +638,9 @@ struct drm_plane {
/** @type: Type of plane, see drm_plane_type for details. */
enum drm_plane_type type;
+ /* Value of true:1 means HDR is supported */
+ bool hdr_supported;
+
/**
* @index: Position inside the mode_config.list, can be used as an array
* index. It is invariant over the lifetime of the plane.
--
1.9.1
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[Intel-gfx] [v2 04/14] drm: Parse Colorimetry data block from EDID
CEA 861.3 spec adds colorimetry data block for HDMI.
Parsing the block to get the colorimetry data from
panel.
v2: Rebase
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_edid.c | 24
include/drm/drm_connector.h | 2 ++
2 files changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index d12b74e..344d8c1 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -3818,6 +3818,28 @@ static void fixup_detailed_cea_mode_clock(struct
drm_display_mode *mode)
mode->clock = clock;
}
+static bool cea_db_is_hdmi_colorimetry_data_block(const u8 *db)
+{
+ if (cea_db_tag(db) != DATA_BLOCK_EXTENDED_TAG)
+ return false;
+
+ if (db[1] != COLORIMETRY_DATA_BLOCK)
+ return false;
+
+ return true;
+}
+
+static void
+drm_parse_colorimetry_data_block(struct drm_connector *connector, const u8 *db)
+{
+ struct drm_hdmi_info *info = >display_info.hdmi;
+ uint16_t len;
+
+ len = cea_db_payload_len(db);
+ info->colorimetry = db[2];
+}
+
+
static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db)
{
if (cea_db_tag(db) != DATA_BLOCK_EXTENDED_TAG)
@@ -4513,6 +4535,8 @@ static void drm_parse_cea_ext(struct drm_connector
*connector,
drm_parse_y420cmdb_bitmap(connector, db);
if (cea_db_is_hdmi_hdr_metadata_block(db))
drm_parse_hdr_metadata_block(connector, db);
+ if (cea_db_is_hdmi_colorimetry_data_block(db))
+ drm_parse_colorimetry_data_block(connector, db);
}
}
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 2ee45dc..90ce364 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -206,6 +206,8 @@ struct drm_hdmi_info {
/** @y420_dc_modes: bitmap of deep color support index */
u8 y420_dc_modes;
+
+ u8 colorimetry;
};
/**
--
1.9.1
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[Intel-gfx] [v2 05/14] drm/i915: Attach HDR metadata property to connector
Attach HDR metadata property to connector object. v2: Rebase Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/intel_hdmi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 07e803a..8a1e5cb 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -2154,6 +2154,8 @@ static void intel_hdmi_destroy(struct drm_connector *connector) intel_attach_aspect_ratio_property(connector); drm_connector_attach_content_type_property(connector); connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE; + drm_object_attach_property(>base, + connector->dev->mode_config.hdr_source_metadata_property, 0); if (!HAS_GMCH_DISPLAY(dev_priv)) drm_connector_attach_max_bpc_property(connector, 8, 12); -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v2 00/14] Add HDR Metadata Parsing and handling in DRM layer
This patch series enables HDR support in drm. It basically defines HDR metadata structures, property to pass content (after blending) metadata from user space compositors to driver. Dynamic Range and Mastering infoframe creation and sending. ToDo: 1. We need to get the color framework in place for all planes which support HDR content in hardware. This is already in progres and patches are out for review in mailing list. 2. UserSpace/Compositors: Blending policies and metadata blob creation and passing to driver. Work is already in progress by Intel's middleware teams on wayland and we should be getting the initial version pretty soon for review. Please review and share your feedbacks/suggestions. Note: The intention for these patches is to get a design feedback on the uapi changes, generic property design and infoframe handling. This cannot get merged as of now without the userspace support in place. A POC has already been developed by Ville based on wayland. Please refer below link to see the component interactions and usage: https://lists.freedesktop.org/archives/wayland-devel/2017-December/036403.html v2: Updated Ville's POC changes to the patch series.Incorporated cleanups and fixes from Ville. Rebase on latest drm-tip. Note: It took a while to float this version as there was no userspace consumer for it and dependency on full userspace stack. However, things are falling in place now. Media driver and VAAPI changes for HDR are already out, with compositors changes also expected to land soon. Uma Shankar (10): drm: Add HDR source metadata property drm: Add CEA extended tag blocks and HDR bitfield macros drm: Parse HDR metadata info from EDID drm: Parse Colorimetry data block from EDID drm/i915: Attach HDR metadata property to connector drm: Add HDR capability field to plane structure drm: Implement HDR source metadata set and get property handling drm: Enable HDR infoframe support drm/i915: Write HDR infoframe and send to panel drm/i915:Enabled Modeset when HDR Infoframe changes Ville Syrjälä (4): drm/i915: [DO NOT MERGE] hack for glk board outputs drm/i915: Add HLG EOTF drm/i915: Enable infoframes on GLK+ for HDR drivers/video: Constantify function argument for HDMI infoframe log drivers/gpu/drm/drm_atomic.c| 2 + drivers/gpu/drm/drm_atomic_uapi.c | 13 drivers/gpu/drm/drm_connector.c | 6 ++ drivers/gpu/drm/drm_edid.c | 143 drivers/gpu/drm/i915/i915_reg.h | 4 + drivers/gpu/drm/i915/intel_atomic.c | 15 +++- drivers/gpu/drm/i915/intel_bios.c | 7 ++ drivers/gpu/drm/i915/intel_hdmi.c | 43 ++- drivers/video/hdmi.c| 129 include/drm/drm_connector.h | 12 +++ include/drm/drm_edid.h | 4 + include/drm/drm_mode_config.h | 6 ++ include/drm/drm_plane.h | 3 + include/linux/hdmi.h| 33 + include/uapi/drm/drm_mode.h | 16 15 files changed, 433 insertions(+), 3 deletions(-) -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v2 02/14] drm: Add CEA extended tag blocks and HDR bitfield macros
Add bit field and macro for extended tag in CEA block. Also, declare macros for HDR metadata block. v2: Rebase Signed-off-by: Uma Shankar --- drivers/gpu/drm/drm_edid.c | 16 1 file changed, 16 insertions(+) diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index b506e36..106fd38 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -2843,6 +2843,22 @@ static int drm_cvt_modes(struct drm_connector *connector, #define EDID_CEA_YCRCB422 (1 << 4) #define EDID_CEA_VCDB_QS (1 << 6) +#define DATA_BLOCK_EXTENDED_TAG0x07 +#define VIDEO_CAPABILITY_DATA_BLOCK0x0 +#define VSVD_DATA_BLOCK0x1 +#define COLORIMETRY_DATA_BLOCK 0x5 +#define HDR_STATIC_METADATA_BLOCK 0x6 + +/* HDR Metadata Block: Bit fields */ +#define SUPPORTED_EOTF_MASK0x3f +#define TRADITIONAL_GAMMA_SDR (0x1 << 0) +#define TRADITIONAL_GAMMA_HDR (0x1 << 1) +#define SMPTE_ST2084 (0x1 << 2) +#define FUTURE_EOTF(0x1 << 3) +#define RESERVED_EOTF (0x3 << 4) + +#define STATIC_METADATA_TYPE1 (0x1 << 0) + /* * Search EDID for CEA extension block. */ -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v2 03/14] drm: Parse HDR metadata info from EDID
HDR metadata block is introduced in CEA-861.3 spec.
Parsing the same to get the panel's HDR metadata.
v2: Rebase and added Ville's POC changes to the patch.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_edid.c | 45 +
1 file changed, 45 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 106fd38..d12b74e 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -3818,6 +3818,49 @@ static void fixup_detailed_cea_mode_clock(struct
drm_display_mode *mode)
mode->clock = clock;
}
+static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db)
+{
+ if (cea_db_tag(db) != DATA_BLOCK_EXTENDED_TAG)
+ return false;
+
+ if (db[1] != HDR_STATIC_METADATA_BLOCK)
+ return false;
+
+ return true;
+}
+
+static uint16_t eotf_supported(const u8 *edid_ext)
+{
+
+ return edid_ext[2] &
+ (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
+BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
+BIT(HDMI_EOTF_SMPTE_ST2084));
+
+}
+
+static uint16_t hdr_metadata_type(const u8 *edid_ext)
+{
+
+ return edid_ext[3] &
+ BIT(HDMI_STATIC_METADATA_TYPE1);
+}
+
+static void
+drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
+{
+ uint16_t len;
+
+ len = cea_db_payload_len(db);
+ connector->hdr_metadata.eotf = eotf_supported(db);
+ connector->hdr_metadata.metadata_type = hdr_metadata_type(db);
+
+ if (len >= 5)
+ connector->hdr_metadata.max_fall = db[5];
+ if (len >= 4)
+ connector->hdr_metadata.max_cll = db[4];
+}
+
static void
drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
{
@@ -4468,6 +4511,8 @@ static void drm_parse_cea_ext(struct drm_connector
*connector,
drm_parse_hdmi_forum_vsdb(connector, db);
if (cea_db_is_y420cmdb(db))
drm_parse_y420cmdb_bitmap(connector, db);
+ if (cea_db_is_hdmi_hdr_metadata_block(db))
+ drm_parse_hdr_metadata_block(connector, db);
}
}
--
1.9.1
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[Intel-gfx] [v2 01/14] drm: Add HDR source metadata property
This patch adds a blob property to get HDR metadata
information from userspace. This will be send as part
of AVI Infoframe to panel.
v2: Rebase and modified the metadata structure elements
as per Ville's POC changes.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_connector.c | 6 ++
include/drm/drm_connector.h | 10 ++
include/drm/drm_mode_config.h | 6 ++
include/linux/hdmi.h| 10 ++
include/uapi/drm/drm_mode.h | 16
5 files changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index da8ae80..361fcda 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -1027,6 +1027,12 @@ int drm_connector_create_standard_properties(struct
drm_device *dev)
return -ENOMEM;
dev->mode_config.non_desktop_property = prop;
+ prop = drm_property_create(dev, DRM_MODE_PROP_BLOB,
+ "HDR_SOURCE_METADATA", 0);
+ if (!prop)
+ return -ENOMEM;
+ dev->mode_config.hdr_source_metadata_property = prop;
+
return 0;
}
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 9be2181..2ee45dc 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -520,6 +520,13 @@ struct drm_connector_state {
* and the connector bpc limitations obtained from edid.
*/
u8 max_bpc;
+
+ /**
+* @metadata_blob_ptr:
+* DRM blob property for HDR metadata
+*/
+ struct drm_property_blob *hdr_source_metadata_blob_ptr;
+ u8 hdr_metadata_changed : 1;
};
/**
@@ -1154,6 +1161,9 @@ struct drm_connector {
* _mode_config.connector_free_work.
*/
struct llist_node free_node;
+
+ /* HDR metdata */
+ struct hdr_static_metadata hdr_metadata;
};
#define obj_to_connector(x) container_of(x, struct drm_connector, base)
diff --git a/include/drm/drm_mode_config.h b/include/drm/drm_mode_config.h
index 69ccd27..4b3211b 100644
--- a/include/drm/drm_mode_config.h
+++ b/include/drm/drm_mode_config.h
@@ -836,6 +836,12 @@ struct drm_mode_config {
*/
struct drm_property *writeback_out_fence_ptr_property;
+ /*
+* hdr_metadata_property: Connector property containing hdr metatda
+* This will be provided by userspace compositors based on HDR content
+*/
+ struct drm_property *hdr_source_metadata_property;
+
/* dumb ioctl parameters */
uint32_t preferred_depth, prefer_shadow;
diff --git a/include/linux/hdmi.h b/include/linux/hdmi.h
index d2bacf5..bed3e08 100644
--- a/include/linux/hdmi.h
+++ b/include/linux/hdmi.h
@@ -137,6 +137,16 @@ enum hdmi_content_type {
HDMI_CONTENT_TYPE_GAME,
};
+enum hdmi_metadata_type {
+ HDMI_STATIC_METADATA_TYPE1 = 1,
+};
+
+enum hdmi_eotf {
+ HDMI_EOTF_TRADITIONAL_GAMMA_SDR,
+ HDMI_EOTF_TRADITIONAL_GAMMA_HDR,
+ HDMI_EOTF_SMPTE_ST2084,
+};
+
struct hdmi_avi_infoframe {
enum hdmi_infoframe_type type;
unsigned char version;
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index a439c2e..5012af2 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -630,6 +630,22 @@ struct drm_color_lut {
__u16 reserved;
};
+/* HDR Metadata */
+struct hdr_static_metadata {
+ uint8_t eotf;
+ uint8_t metadata_type;
+ struct {
+ uint16_t x, y;
+ } display_primaries[3];
+ struct {
+ uint16_t x, y;
+ } white_point;
+ uint16_t max_mastering_display_luminance;
+ uint16_t min_mastering_display_luminance;
+ uint16_t max_fall;
+ uint16_t max_cll;
+};
+
#define DRM_MODE_PAGE_FLIP_EVENT 0x01
#define DRM_MODE_PAGE_FLIP_ASYNC 0x02
#define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4
--
1.9.1
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: DFSM pipe disable is valid from gen9 onwards (rev2)
== Series Details == Series: drm/i915: DFSM pipe disable is valid from gen9 onwards (rev2) URL : https://patchwork.freedesktop.org/series/53900/ State : success == Summary == CI Bug Log - changes from CI_DRM_5296 -> Patchwork_11070 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/53900/revisions/2/mbox/ Known issues Here are the changes found in Patchwork_11070 that come from known issues: ### IGT changes ### Issues hit * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718] [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 Participating hosts (48 -> 44) -- Additional (1): fi-byt-j1900 Missing(5): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-ctg-p8600 Build changes - * Linux: CI_DRM_5296 -> Patchwork_11070 CI_DRM_5296: 70751bd8a3f27b035d203ecafcad452f4d7c2c15 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4745: 3b52e8a5809a4e860350c59476a456745cd9fee0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_11070: 76de41eefc296a6766b1de710a8452614eb102d2 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 76de41eefc29 drm/i915: DFSM pipe disable is valid from gen9 onwards (v2) == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11070/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: DFSM pipe disable is valid from gen9 onwards
== Series Details ==
Series: drm/i915: DFSM pipe disable is valid from gen9 onwards
URL : https://patchwork.freedesktop.org/series/53900/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5296_full -> Patchwork_11066_full
Summary
---
**WARNING**
Minor unknown changes coming with Patchwork_11066_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_11066_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_11066_full:
### IGT changes ###
Warnings
* igt@tools_test@tools_test:
- shard-snb: PASS -> SKIP +1
- shard-skl: SKIP -> PASS
Known issues
Here are the changes found in Patchwork_11066_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_contexts:
- {shard-iclb}: NOTRUN -> DMESG-FAIL [fdo#108569]
* igt@kms_busy@extended-modeset-hang-newfb-render-b:
- {shard-iclb}: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
- shard-glk: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_color@pipe-a-degamma:
- shard-apl: PASS -> FAIL [fdo#104782] / [fdo#108145]
* igt@kms_color@pipe-b-degamma:
- shard-apl: PASS -> FAIL [fdo#104782]
* igt@kms_color@pipe-c-ctm-green-to-red:
- shard-skl: PASS -> FAIL [fdo#107201]
* igt@kms_cursor_crc@cursor-128x42-sliding:
- shard-glk: PASS -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-256x85-random:
- shard-apl: PASS -> FAIL [fdo#103232] +8
* igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-apl: PASS -> FAIL [fdo#103191] / [fdo#103232]
* igt@kms_draw_crc@draw-method-rgb565-pwrite-ytiled:
- {shard-iclb}: PASS -> FAIL [fdo#103184]
* igt@kms_draw_crc@draw-method-xrgb2101010-pwrite-untiled:
- {shard-iclb}: PASS -> WARN [fdo#108336]
* igt@kms_fbcon_fbt@fbc-suspend:
- {shard-iclb}: PASS -> FAIL [fdo#103833] / [fdo#105681]
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: NOTRUN -> FAIL [fdo#105363]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
- shard-apl: PASS -> FAIL [fdo#103167] +5
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
- {shard-iclb}: PASS -> FAIL [fdo#103167] +1
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-gtt:
- shard-glk: PASS -> FAIL [fdo#103167] +2
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt:
- {shard-iclb}: NOTRUN -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@psr-suspend:
- {shard-iclb}: PASS -> INCOMPLETE [fdo#107713]
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-skl: NOTRUN -> INCOMPLETE [fdo#104108]
* igt@kms_plane@plane-position-covered-pipe-a-planes:
- shard-apl: PASS -> FAIL [fdo#103166]
- {shard-iclb}: NOTRUN -> FAIL [fdo#103166]
* igt@kms_plane@plane-position-covered-pipe-b-planes:
- {shard-iclb}: PASS -> FAIL [fdo#103166]
* igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
- shard-apl: PASS -> FAIL [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
- shard-skl: NOTRUN -> FAIL [fdo#108145]
* {igt@kms_rotation_crc@multiplane-rotation-cropping-top}:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107724] +2
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107724] / [fdo#108336]
* igt@kms_sysfs_edid_timing:
- shard-skl: NOTRUN -> FAIL [fdo#100047]
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773] +1
* igt@pm_rpm@gem-mmap-gtt:
- shard-skl: PASS -> INCOMPLETE [fdo#107807]
* igt@pm_rpm@modeset-lpsp-stress-no-wait:
- {shard-iclb}: PASS -> INCOMPLETE [fdo#108840] +1
* {igt@runner@aborted}:
- {shard-iclb}: NOTRUN -> FAIL [fdo#108654]
Possible fixes
* igt@kms_busy@extended-modeset-hang-newfb-render-b:
- shard-kbl: DMESG-WARN [fdo#107956] -> PASS
* igt@kms_busy@extended-modeset-hang-newfb-render-c:
- {shard-iclb}: DMESG-WARN [fdo#107956] -> PASS
* igt@kms_busy@extended-pageflip-hang-newfb-render-b:
- shard-glk: DMESG-WARN [fdo#107956] -> PASS +1
* igt@kms_color@pipe-b-ctm-negative:
- shard-skl:
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915: Don't use DDB allocation when choosing gen9 watermark method (rev2)
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Don't use DDB allocation when
choosing gen9 watermark method (rev2)
URL : https://patchwork.freedesktop.org/series/53901/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5296 -> Patchwork_11069
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/53901/revisions/2/mbox/
Known issues
Here are the changes found in Patchwork_11069 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_coherency:
- fi-gdg-551: PASS -> DMESG-FAIL [fdo#107164]
* igt@kms_chamelium@hdmi-hpd-fast:
- {fi-kbl-7500u}: PASS -> FAIL [fdo#108767]
* igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-skl-guc: PASS -> FAIL [fdo#103191] / [fdo#107362]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#107164]: https://bugs.freedesktop.org/show_bug.cgi?id=107164
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#108767]: https://bugs.freedesktop.org/show_bug.cgi?id=108767
Participating hosts (48 -> 44)
--
Additional (1): fi-byt-j1900
Missing(5): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-ctg-p8600
Build changes
-
* Linux: CI_DRM_5296 -> Patchwork_11069
CI_DRM_5296: 70751bd8a3f27b035d203ecafcad452f4d7c2c15 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4745: 3b52e8a5809a4e860350c59476a456745cd9fee0 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11069: 2e1fe301f9eaecd0f3525f75f16c525dac9f0354 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
2e1fe301f9ea drm/i915: Switch to level-based DDB allocation algorithm (v6)
f2e2112ac70a drm/i915: Don't use DDB allocation when choosing gen9 watermark
method
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11069/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: DFSM pipe disable is valid from gen9 onwards (v2)
It's not just GEN9 platforms that allow for pipes to be disabled via
the DFSM register, but all later platforms as well.
v2: drop pointless parentheses (Ville)
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/intel_device_info.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index 1e56319334f3..bd5c4d62c635 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -811,7 +811,7 @@ void intel_device_info_runtime_init(struct
intel_device_info *info)
DRM_INFO("PipeC fused off\n");
info->num_pipes -= 1;
}
- } else if (HAS_DISPLAY(dev_priv) && IS_GEN9(dev_priv)) {
+ } else if (HAS_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 9) {
u32 dfsm = I915_READ(SKL_DFSM);
u8 disabled_mask = 0;
bool invalid;
--
2.17.1
___
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/2] drm/i915: Don't use DDB allocation when choosing gen9 watermark method (rev2)
== Series Details == Series: series starting with [CI,1/2] drm/i915: Don't use DDB allocation when choosing gen9 watermark method (rev2) URL : https://patchwork.freedesktop.org/series/53901/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Don't use DDB allocation when choosing gen9 watermark method -drivers/gpu/drm/i915/i915_fixed.h:42:43: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_fixed.h:42:43: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_pm.c:6724:35: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_pm.c:6724:35: warning: expression using sizeof(void) Commit: drm/i915: Switch to level-based DDB allocation algorithm (v6) +drivers/gpu/drm/i915/intel_pm.c:4413:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_pm.c:4413:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_pm.c:4424:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_pm.c:4424:25: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:6618:24: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:6618:24: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:6622:35: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:6622:35: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:6622:35: warning: too many warnings +drivers/gpu/drm/i915/intel_pm.c:6618:24: warning: too many warnings ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 2/2] drm/i915: Switch to level-based DDB allocation algorithm (v6)
The DDB allocation algorithm currently used by the driver grants each
plane a very small minimum allocation of DDB blocks and then divies up
all of the remaining blocks based on the percentage of the total data
rate that the plane makes up. It turns out that this proportional
allocation approach is overly-generous with the larger planes and can
leave very small planes wthout a big enough allocation to even hit their
level 0 watermark requirements (especially on APL, which has a smaller
DDB in general than other gen9 platforms). Or there can be situations
where the smallest planes hit a lower watermark level than they should
have been able to hit with a more equitable division of DDB blocks, thus
limiting the overall system sleep state that can be achieved.
The bspec now describes an alternate algorithm that can be used to
overcome these types of issues. With the new algorithm, we calculate
all plane watermark values for all wm levels first, then go back and
partition a pipe's DDB space second. The DDB allocation will calculate
what the highest watermark level that can be achieved on *all* active
planes, and then grant the blocks necessary to hit that level to each
plane. Any remaining blocks are then divided up proportionally
according to data rate, similar to the old algorithm.
There was a previous attempt to implement this algorithm a couple years
ago in bb9d85f6e9d ("drm/i915/skl: New ddb allocation algorithm"), but
some regressions were reported, the patch was reverted, and nobody
ever got around to figuring out exactly where the bug was in that
version. Our watermark code has evolved significantly in the meantime,
but we're still getting bug reports caused by the unfair proportional
algorithm, so let's give this another shot.
v2:
- Make sure cursor allocation stays constant and fixed at the end of
the pipe allocation.
- Fix some watermark level iterators that weren't handling the max
level.
v3:
- Ensure we don't leave any DDB blocks unused by using DIV_ROUND_UP+min
to calculate the extra blocks for each plane. (Ville)
- Replace a while() loop with a for() loop to be more consistent with
surrounding code. (Ville)
- Clean unattainable watermark levels with memset rather than directly
clearing the member fields. Also do the same for the transition
watermark values if they can't be achieved. (Ville)
- Drop min_disp_buf_needed calculations in skl_compute_plane_wm() since
the results are no longer needed or used. (Ville)
- Drop skl_latency[0] != 0 sanity check; both watermark methods already
account for an invalid 0 latency by returning FP_16_16_MAX. (Ville)
v4:
- Break DDB allocation loop when total_data_rate=0 rather than
alloc_size=0. If total_data_rate has dropped to 0, all remaining
planes are disabled, which isn't true for alloc_size (we might just
have not had any remaining blocks to hand out). Plus
total_data_rate=0 is the case we need to avoid to a prevent a
div-by-0. (Ville)
- s/DIV_ROUND_UP/DIV64_U64_ROUND_UP/ to prevent 32-bit breakage (Ville)
v5:
- Don't forget to move 'start' pointer forward for UV surface when
setting plane DDB boundaries. (Ville)
v6:
- If a watermark level isn't achievable, don't forget to reset blocks=0
when testing the next lower level (otherwise that one will surely
fail as well). (CI)
Cc: Ville Syrjälä
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105458
Signed-off-by: Matt Roper
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 384 +++-
1 file changed, 141 insertions(+), 243 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bf970cf7b8a5..a6c7c11d2c0e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4301,102 +4301,6 @@ icl_get_total_relative_data_rate(struct
intel_crtc_state *intel_cstate,
return total_data_rate;
}
-static uint16_t
-skl_ddb_min_alloc(const struct intel_plane_state *plane_state, const int plane)
-{
- struct drm_framebuffer *fb = plane_state->base.fb;
- uint32_t src_w, src_h;
- uint32_t min_scanlines = 8;
- uint8_t plane_bpp;
-
- if (WARN_ON(!fb))
- return 0;
-
- /* For packed formats, and uv-plane, return 0 */
- if (plane == 1 && fb->format->format != DRM_FORMAT_NV12)
- return 0;
-
- /* For Non Y-tile return 8-blocks */
- if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
- fb->modifier != I915_FORMAT_MOD_Yf_TILED &&
- fb->modifier != I915_FORMAT_MOD_Y_TILED_CCS &&
- fb->modifier != I915_FORMAT_MOD_Yf_TILED_CCS)
- return 8;
-
- /*
-* Src coordinates are already rotated by 270 degrees for
-* the 90/270 degree plane rotation cases (to match the
-* GTT mapping), hence no need to account for rotation here.
-*/
- src_w = drm_rect_width(_state->base.src)
Re: [Intel-gfx] [PATCH 2/5] drm/i915: Refactor PSR status debugfs
On Tue, 2018-12-11 at 10:32 -0800, Dhinakaran Pandiyan wrote:
> On Tue, 2018-12-11 at 04:44 -0800, Souza, Jose wrote:
> > On Mon, 2018-12-10 at 22:51 -0800, Dhinakaran Pandiyan wrote:
> > > On Tue, 2018-12-04 at 15:00 -0800, José Roberto de Souza wrote:
> > > > The old debugfs fields was not following a naming partern and
> > > > it
> > > > was
> > > > a bit confusing.
> > > >
> > > > So it went from:
> > > > ~$ sudo more /sys/kernel/debug/dri/0/i915_edp_psr_status
> > > > Sink_Support: yes
> > > > PSR mode: PSR1
> > > > Enabled: yes
> > > > Busy frontbuffer bits: 0x000
> > > > Main link in standby mode: no
> > > > HW Enabled & Active bit: yes
> > > > Source PSR status: 0x24050006 [SRDONACK]
> > > >
> > > > To:
> > > > ~$ sudo more /sys/kernel/debug/dri/0/i915_edp_psr_status
> > > > Sink support: yes [0x0003]
> > > > Status: PSR1 enabled
> > > > Source PSR ctl: enabled [0x81f00e26]
> > > > Source PSR status: SRDENT [0x40040006]
> > > > Busy frontbuffer bits: 0x
> > > >
> > > > The 'Main link in standby mode' was removed as it is not useful
> > > > but
> > > > if needed by someone the information is still in the register
> > > > value
> > > > of 'Source PSR ctl' inside of the brackets, PSR mode and
> > > > Enabled
> > > > was
> > > > squashed into Status, some renames and reorders and we have
> > > > this
> > > > cleaner version. This will also make easy to parse debugfs for
> > > > IGT
> > > > tests.
> > > >
> > > > Cc: Rodrigo Vivi
> > > > Cc: Dhinakaran Pandiyan
> > > > Suggested-by: Dhinakaran Pandiyan <
> > > > dhinakaran.pandi...@intel.com>
> > > > Signed-off-by: José Roberto de Souza
> > > > ---
> > > > drivers/gpu/drm/i915/i915_debugfs.c | 96 +++--
> > > >
> > > >
> > > > 1 file changed, 49 insertions(+), 47 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > > > b/drivers/gpu/drm/i915/i915_debugfs.c
> > > > index 38dcee1ca062..86303ba02666 100644
> > > > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > > > @@ -2665,7 +2665,8 @@
> > > > DEFINE_SHOW_ATTRIBUTE(i915_psr_sink_status);
> > > > static void
> > > > psr_source_status(struct drm_i915_private *dev_priv, struct
> > > > seq_file
> > > > *m)
> > > > {
> > > > - u32 val, psr_status;
> > > > + u32 val, status_val;
> > > > + const char *status = "unknown";
> > > >
> > > > if (dev_priv->psr.psr2_enabled) {
> > > > static const char * const live_status[] = {
> > > > @@ -2681,14 +2682,11 @@ psr_source_status(struct
> > > > drm_i915_private
> > > > *dev_priv, struct seq_file *m)
> > > > "BUF_ON",
> > > > "TG_ON"
> > > > };
> > > > - psr_status = I915_READ(EDP_PSR2_STATUS);
> > > > - val = (psr_status & EDP_PSR2_STATUS_STATE_MASK)
> > > > >>
> > > > - EDP_PSR2_STATUS_STATE_SHIFT;
> > > > - if (val < ARRAY_SIZE(live_status)) {
> > > > - seq_printf(m, "Source PSR status: 0x%x
> > > > [%s]\n",
> > > > - psr_status,
> > > > live_status[val]);
> > > > - return;
> > > > - }
> > > > + val = I915_READ(EDP_PSR2_STATUS);
> > > > + status_val = (val & EDP_PSR2_STATUS_STATE_MASK)
> > > > >>
> > > > + EDP_PSR2_STATUS_STATE_SHIFT;
> > > > + if (status_val < ARRAY_SIZE(live_status))
> > > > + status = live_status[status_val];
> > > > } else {
> > > > static const char * const live_status[] = {
> > > > "IDLE",
> > > > @@ -2700,74 +2698,78 @@ psr_source_status(struct
> > > > drm_i915_private
> > > > *dev_priv, struct seq_file *m)
> > > > "SRDOFFACK",
> > > > "SRDENT_ON",
> > > > };
> > > > - psr_status = I915_READ(EDP_PSR_STATUS);
> > > > - val = (psr_status & EDP_PSR_STATUS_STATE_MASK)
> > > > >>
> > > > - EDP_PSR_STATUS_STATE_SHIFT;
> > > > - if (val < ARRAY_SIZE(live_status)) {
> > > > - seq_printf(m, "Source PSR status: 0x%x
> > > > [%s]\n",
> > > > - psr_status,
> > > > live_status[val]);
> > > > - return;
> > > > - }
> > > > + val = I915_READ(EDP_PSR_STATUS);
> > > > + status_val = (val & EDP_PSR_STATUS_STATE_MASK)
> > > > >>
> > > > + EDP_PSR_STATUS_STATE_SHIFT;
> > > > + if (status_val < ARRAY_SIZE(live_status))
> > > > + status = live_status[status_val];
> > > > }
> > > >
> > > > - seq_printf(m, "Source PSR status: 0x%x [%s]\n",
> > > > psr_status,
> > > > "unknown");
> > > > + seq_printf(m, "Source PSR status:
[Intel-gfx] ✓ Fi.CI.BAT: success for Add Colorspace connector property interface (rev5)
== Series Details == Series: Add Colorspace connector property interface (rev5) URL : https://patchwork.freedesktop.org/series/47132/ State : success == Summary == CI Bug Log - changes from CI_DRM_5296 -> Patchwork_11068 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/47132/revisions/5/mbox/ Known issues Here are the changes found in Patchwork_11068 that come from known issues: ### IGT changes ### Issues hit * igt@i915_module_load@reload: - fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718] * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: - fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362] * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-apl-guc: PASS -> DMESG-WARN [fdo#108529] / [fdo#108566] [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#108529]: https://bugs.freedesktop.org/show_bug.cgi?id=108529 [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566 Participating hosts (48 -> 44) -- Additional (1): fi-byt-j1900 Missing(5): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-ctg-p8600 Build changes - * Linux: CI_DRM_5296 -> Patchwork_11068 CI_DRM_5296: 70751bd8a3f27b035d203ecafcad452f4d7c2c15 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4745: 3b52e8a5809a4e860350c59476a456745cd9fee0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_11068: 48917be04d317cc7522cb7c9ff55f13ce57087e1 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 48917be04d31 drm/i915: Attach colorspace property and enable modeset 63b9d3d2f8f9 drm: Add colorspace connector property == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11068/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v3,1/2] drm/i915: Don't use DDB allocation when choosing gen9 watermark method
== Series Details ==
Series: series starting with [v3,1/2] drm/i915: Don't use DDB allocation when
choosing gen9 watermark method
URL : https://patchwork.freedesktop.org/series/53898/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5296_full -> Patchwork_11065_full
Summary
---
**WARNING**
Minor unknown changes coming with Patchwork_11065_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_11065_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_11065_full:
### IGT changes ###
Possible regressions
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparant-fb:
- {shard-iclb}: PASS -> FAIL +7
Warnings
* igt@kms_plane_lowres@pipe-a-tiling-x:
- {shard-iclb}: PASS -> SKIP
* igt@kms_vblank@pipe-a-wait-busy-hang:
- shard-snb: PASS -> SKIP +7
* igt@tools_test@tools_test:
- shard-skl: SKIP -> PASS
Known issues
Here are the changes found in Patchwork_11065_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_workarounds@suspend-resume-fd:
- shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773]
* igt@kms_busy@extended-modeset-hang-newfb-render-b:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#107956]
- {shard-iclb}: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
- shard-glk: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_color@pipe-c-ctm-green-to-red:
- shard-skl: PASS -> FAIL [fdo#107201]
* igt@kms_cursor_crc@cursor-128x128-suspend:
- shard-skl: PASS -> INCOMPLETE [fdo#104108]
* igt@kms_cursor_crc@cursor-256x256-random:
- shard-apl: PASS -> FAIL [fdo#103232] +4
* igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-apl: PASS -> FAIL [fdo#103191] / [fdo#103232]
* igt@kms_draw_crc@draw-method-xrgb2101010-render-untiled:
- shard-skl: PASS -> FAIL [fdo#103184]
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-glk: PASS -> FAIL [fdo#103833] / [fdo#105681]
* igt@kms_fbcon_fbt@psr-suspend:
- shard-skl: NOTRUN -> FAIL [fdo#107882]
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-glk: PASS -> FAIL [fdo#102887] / [fdo#105363]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
- shard-apl: PASS -> FAIL [fdo#103167] +1
- {shard-iclb}: PASS -> FAIL [fdo#103167] +1
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-pwrite:
- shard-glk: PASS -> FAIL [fdo#103167] +4
* igt@kms_frontbuffer_tracking@fbcpsr-1p-rte:
- {shard-iclb}: PASS -> FAIL [fdo#103167] / [fdo#105682]
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-skl: NOTRUN -> INCOMPLETE [fdo#104108]
* igt@kms_plane@plane-position-covered-pipe-a-planes:
- shard-apl: PASS -> FAIL [fdo#103166] +3
* igt@kms_plane@plane-position-covered-pipe-b-planes:
- {shard-iclb}: PASS -> FAIL [fdo#103166] +2
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-skl: NOTRUN -> FAIL [fdo#108145] +1
* igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
- shard-apl: PASS -> FAIL [fdo#108145]
* igt@kms_plane_multiple@atomic-pipe-c-tiling-x:
- shard-glk: PASS -> FAIL [fdo#103166]
* igt@kms_psr@no_drrs:
- {shard-iclb}: PASS -> FAIL [fdo#108341]
* {igt@kms_rotation_crc@multiplane-rotation-cropping-top}:
- shard-glk: PASS -> DMESG-FAIL [fdo#105763] / [fdo#106538]
* igt@pm_rpm@debugfs-forcewake-user:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107724]
* igt@pm_rpm@debugfs-read:
- shard-kbl: PASS -> DMESG-WARN [fdo#103313]
* igt@pm_rpm@legacy-planes-dpms:
- shard-skl: PASS -> INCOMPLETE [fdo#105959] / [fdo#107807]
* igt@pm_rpm@system-suspend-execbuf:
- shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773] /
[fdo#107807]
Possible fixes
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
- shard-apl: FAIL [fdo#105458] / [fdo#106510] -> PASS +1
* igt@kms_color@pipe-b-ctm-negative:
- shard-skl: FAIL [fdo#107361] -> PASS
* igt@kms_cursor_crc@cursor-64x21-sliding:
- shard-apl: FAIL [fdo#103232] -> PASS +1
* igt@kms_draw_crc@draw-method-rgb565-pwrite-ytiled:
- shard-glk: FAIL [fdo#103184] -> PASS
*
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add Colorspace connector property interface (rev5)
== Series Details == Series: Add Colorspace connector property interface (rev5) URL : https://patchwork.freedesktop.org/series/47132/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm: Add colorspace connector property Okay! Commit: drm/i915: Attach colorspace property and enable modeset +drivers/gpu/drm/i915/intel_hdmi.c:510:51: int enum absolute_colorimetry_list versus +drivers/gpu/drm/i915/intel_hdmi.c:510:51: int enum hdmi_colorimetry +drivers/gpu/drm/i915/intel_hdmi.c:510:51: warning: mixing different enum types ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/5] drm/i915: Refactor PSR status debugfs
On Tue, 2018-12-11 at 04:44 -0800, Souza, Jose wrote:
> On Mon, 2018-12-10 at 22:51 -0800, Dhinakaran Pandiyan wrote:
> > On Tue, 2018-12-04 at 15:00 -0800, José Roberto de Souza wrote:
> > > The old debugfs fields was not following a naming partern and it
> > > was
> > > a bit confusing.
> > >
> > > So it went from:
> > > ~$ sudo more /sys/kernel/debug/dri/0/i915_edp_psr_status
> > > Sink_Support: yes
> > > PSR mode: PSR1
> > > Enabled: yes
> > > Busy frontbuffer bits: 0x000
> > > Main link in standby mode: no
> > > HW Enabled & Active bit: yes
> > > Source PSR status: 0x24050006 [SRDONACK]
> > >
> > > To:
> > > ~$ sudo more /sys/kernel/debug/dri/0/i915_edp_psr_status
> > > Sink support: yes [0x0003]
> > > Status: PSR1 enabled
> > > Source PSR ctl: enabled [0x81f00e26]
> > > Source PSR status: SRDENT [0x40040006]
> > > Busy frontbuffer bits: 0x
> > >
> > > The 'Main link in standby mode' was removed as it is not useful
> > > but
> > > if needed by someone the information is still in the register
> > > value
> > > of 'Source PSR ctl' inside of the brackets, PSR mode and Enabled
> > > was
> > > squashed into Status, some renames and reorders and we have this
> > > cleaner version. This will also make easy to parse debugfs for
> > > IGT
> > > tests.
> > >
> > > Cc: Rodrigo Vivi
> > > Cc: Dhinakaran Pandiyan
> > > Suggested-by: Dhinakaran Pandiyan
> > > Signed-off-by: José Roberto de Souza
> > > ---
> > > drivers/gpu/drm/i915/i915_debugfs.c | 96 +++--
> > >
> > >
> > > 1 file changed, 49 insertions(+), 47 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > > b/drivers/gpu/drm/i915/i915_debugfs.c
> > > index 38dcee1ca062..86303ba02666 100644
> > > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > > @@ -2665,7 +2665,8 @@
> > > DEFINE_SHOW_ATTRIBUTE(i915_psr_sink_status);
> > > static void
> > > psr_source_status(struct drm_i915_private *dev_priv, struct
> > > seq_file
> > > *m)
> > > {
> > > - u32 val, psr_status;
> > > + u32 val, status_val;
> > > + const char *status = "unknown";
> > >
> > > if (dev_priv->psr.psr2_enabled) {
> > > static const char * const live_status[] = {
> > > @@ -2681,14 +2682,11 @@ psr_source_status(struct drm_i915_private
> > > *dev_priv, struct seq_file *m)
> > > "BUF_ON",
> > > "TG_ON"
> > > };
> > > - psr_status = I915_READ(EDP_PSR2_STATUS);
> > > - val = (psr_status & EDP_PSR2_STATUS_STATE_MASK) >>
> > > - EDP_PSR2_STATUS_STATE_SHIFT;
> > > - if (val < ARRAY_SIZE(live_status)) {
> > > - seq_printf(m, "Source PSR status: 0x%x [%s]\n",
> > > -psr_status, live_status[val]);
> > > - return;
> > > - }
> > > + val = I915_READ(EDP_PSR2_STATUS);
> > > + status_val = (val & EDP_PSR2_STATUS_STATE_MASK) >>
> > > + EDP_PSR2_STATUS_STATE_SHIFT;
> > > + if (status_val < ARRAY_SIZE(live_status))
> > > + status = live_status[status_val];
> > > } else {
> > > static const char * const live_status[] = {
> > > "IDLE",
> > > @@ -2700,74 +2698,78 @@ psr_source_status(struct drm_i915_private
> > > *dev_priv, struct seq_file *m)
> > > "SRDOFFACK",
> > > "SRDENT_ON",
> > > };
> > > - psr_status = I915_READ(EDP_PSR_STATUS);
> > > - val = (psr_status & EDP_PSR_STATUS_STATE_MASK) >>
> > > - EDP_PSR_STATUS_STATE_SHIFT;
> > > - if (val < ARRAY_SIZE(live_status)) {
> > > - seq_printf(m, "Source PSR status: 0x%x [%s]\n",
> > > -psr_status, live_status[val]);
> > > - return;
> > > - }
> > > + val = I915_READ(EDP_PSR_STATUS);
> > > + status_val = (val & EDP_PSR_STATUS_STATE_MASK) >>
> > > + EDP_PSR_STATUS_STATE_SHIFT;
> > > + if (status_val < ARRAY_SIZE(live_status))
> > > + status = live_status[status_val];
> > > }
> > >
> > > - seq_printf(m, "Source PSR status: 0x%x [%s]\n", psr_status,
> > > "unknown");
> > > + seq_printf(m, "Source PSR status: %s [0x%08x]\n", status, val);
> > > }
> > >
> > > static int i915_edp_psr_status(struct seq_file *m, void *data)
> > > {
> > > struct drm_i915_private *dev_priv = node_to_i915(m->private);
> > > - u32 psrperf = 0;
> > > - bool enabled = false;
> > > - bool sink_support;
> > > + struct i915_psr *psr = _priv->psr;
> > > + const char *status;
> > > + bool enabled;
> > > + u32 val;
> > >
> > > if (!HAS_PSR(dev_priv))
> > > return -ENODEV;
> > >
> > > - sink_support = dev_priv->psr.sink_support;
> > > - seq_printf(m, "Sink_Support: %s\n", yesno(sink_support));
> > > - if (!sink_support)
> > > + seq_printf(m, "Sink support: %s", yesno(psr->sink_support));
> > > +
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add Colorspace connector property interface (rev5)
== Series Details == Series: Add Colorspace connector property interface (rev5) URL : https://patchwork.freedesktop.org/series/47132/ State : warning == Summary == $ dim checkpatch origin/drm-tip 63b9d3d2f8f9 drm: Add colorspace connector property 48917be04d31 drm/i915: Attach colorspace property and enable modeset -:112: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #112: FILE: drivers/gpu/drm/i915/intel_connector.c:316: + if (!drm_mode_create_colorspace_property(connector, + gen10_hdmi_colorspace, -:115: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #115: FILE: drivers/gpu/drm/i915/intel_connector.c:319: + drm_object_attach_property(>base, + connector->colorspace_property, 0); -:118: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #118: FILE: drivers/gpu/drm/i915/intel_connector.c:322: + if (!drm_mode_create_colorspace_property(connector, + legacy_hdmi_colorspace, -:121: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #121: FILE: drivers/gpu/drm/i915/intel_connector.c:325: + drm_object_attach_property(>base, + connector->colorspace_property, 0); total: 0 errors, 0 warnings, 4 checks, 116 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/psr: Execute the default PSR code path when setting i915_edp_psr_debug
On Tue, 2018-12-04 at 13:23 -0800, Dhinakaran Pandiyan wrote:
> On Tue, 2018-12-04 at 10:52 -0800, Souza, Jose wrote:
> > On Mon, 2018-12-03 at 18:58 -0800, Dhinakaran Pandiyan wrote:
> > > On Mon, 2018-12-03 at 17:54 -0800, Souza, Jose wrote:
> > > > On Mon, 2018-12-03 at 17:33 -0800, Dhinakaran Pandiyan wrote:
> > > > > On Thu, 2018-11-29 at 18:31 -0800, José Roberto de Souza
> > > > > wrote:
> > > > > > Changing the i915_edp_psr_debug was enabling, disabling or
> > > > > > switching
> > > > > > PSR version by directly calling intel_psr_disable_locked()
> > > > > > and
> > > > > > intel_psr_enable_locked(), what is not the default PSR path
> > > > > > that
> > > > > > is
> > > > > > executed in a regular modesets.
> > > > > >
> > > > > > So lets force a modeset in the PSR CRTC to trigger the
> > > > > > requested
> > > > > > PSR
> > > > > > state change and really stress the code path that matters
> > > > > > for
> > > > > > the
> > > > > > regular user.
> > > > > >
> > > > > > Also by doing this way it fixes the issue below, were DRRS
> > > > > > was
> > > > > > left
> > > > > > enabled together with PSR when enabling PSR from debugfs.
> > > > >
> > > > > While this patch does fix the issue, psr_compute_config() not
> > > > > checking
> > > > > crtc_state->has_drrs seems odd. We should change it to not
> > > > > set
> > > > > crtc_state->has_psr if crtc_state->has_drrs happens to be
> > > > > set.
> > > > > Or
> > > > > do
> > > > > it
> > > > > the other way around.
> > > >
> > > > psr_compute_config() is not called when enabling PSR from
> > > > debugfs,
> > > > this
> > >
> > > Right. My suggestion is to allow either ->has_drrs or ->has_psr
> > > being
> > > set (not both) in the kernel and disable DRRS in the IGT before
> > > starting the test.
> >
> > So in case were PSR is disabled by parameter and DRRS is supported
> > we
> > would not enable DRRS? Because has_psr is set even if PSR is
> > disabled.
> Set ->has_psr = true in psr_compute_config() only if the module
> parameter and debugfs mode allow it. That is how the code worked
> earlier. Given that this patch duplicates the atomic state and runs
> through all state checks, we can move back to the earlier way of
> completing all checks in psr_compute_config().
>
> > Disabling DRRS from IGT is duplicating the code that already do
> > that
> > and also not validating the default code path.
> Call drrs_compute_config() after psr_compute_config(), don't set
> has_drrs if has_psr is set.
What about add a flag to skip modeset so when running IGT tests we set
that flag and PSR mode will be changed in the next modeset, what is
already done after every write to i915_edp_psr_debug in IGT tests? This
way we remove the code duplication and only stress the default code
path.
Also plus the changes in has_drrs that you mentioned but in other
patch.
>
> > >
> > > > issue was reported when PSR1 was not enabled by default so DRRS
> > > > was
> > > > being enabled by default but not PSR and when PSR was enabled
> > > > from
> > > > debugfs both were kept enabled.
> > > >
> > > > In the first version of this patch I was just disabling DRRS
> > > > when
> > > > enabling PSR but Maarten suggested to not do so and instead
> > > > stress
> > > > the
> > > > default code path.
> > >
> > > This patch changes crtc_state->mode_changed to force a modeset,
> > > which
> > > means it is not exactly the same as the 'default' code path.
> >
> > Some drm and i915 code paths also set mode_changed and the result
> > of
> > this is exactly the same as do a full modeset.
> >
> > >
> > >
> > > > > > Bugzilla:
> > > > > > https://bugs.freedesktop.org/show_bug.cgi?id=108341
> > > > > > Cc: Maarten Lankhorst
> > > > > > Cc: Dhinakaran Pandiyan
> > > > > > Cc: Rodrigo Vivi
> > > > > > Signed-off-by: José Roberto de Souza
> > > > > > ---
> > > > > > drivers/gpu/drm/i915/i915_debugfs.c | 14 +---
> > > > > > drivers/gpu/drm/i915/i915_drv.h | 2 +-
> > > > > > drivers/gpu/drm/i915/intel_drv.h| 4 +-
> > > > > > drivers/gpu/drm/i915/intel_psr.c| 119
> > > > > >
> > > > > >
> > > > > >
> > > > > > 4 files changed, 55 insertions(+), 84 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > > > > > b/drivers/gpu/drm/i915/i915_debugfs.c
> > > > > > index 129b9a6f8309..bc32f683dc46 100644
> > > > > > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > > > > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > > > > > @@ -2775,7 +2775,6 @@ static int
> > > > > > i915_edp_psr_debug_set(void *data, u64 val)
> > > > > > {
> > > > > > struct drm_i915_private *dev_priv = data;
> > > > > > - struct drm_modeset_acquire_ctx ctx;
> > > > > > int ret;
> > > > > >
> > > > > > if (!CAN_PSR(dev_priv))
> > > > > > @@ -2785,18 +2784,7 @@ i915_edp_psr_debug_set(void *data,
> > > > > > u64
> > > > > > val)
> > > > > >
> > > > > > intel_runtime_pm_get(dev_priv);
> > > > > >
> > > > > > -
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915: Don't use DDB allocation when choosing gen9 watermark method
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Don't use DDB allocation when
choosing gen9 watermark method
URL : https://patchwork.freedesktop.org/series/53901/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5296 -> Patchwork_11067
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/53901/revisions/1/mbox/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_11067:
### IGT changes ###
Warnings
* igt@kms_busy@basic-flip-a:
- {fi-kbl-7567u}: PASS -> SKIP +2
Known issues
Here are the changes found in Patchwork_11067 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
Participating hosts (48 -> 43)
--
Additional (1): fi-byt-j1900
Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-ctg-p8600 fi-pnv-d510
Build changes
-
* Linux: CI_DRM_5296 -> Patchwork_11067
CI_DRM_5296: 70751bd8a3f27b035d203ecafcad452f4d7c2c15 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4745: 3b52e8a5809a4e860350c59476a456745cd9fee0 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11067: 134ff01059a8bc017c061f3784f0bde602b8bd99 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
134ff01059a8 drm/i915: Switch to level-based DDB allocation algorithm (v5)
76df04365984 drm/i915: Don't use DDB allocation when choosing gen9 watermark
method
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11067/
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/2] drm/i915: Don't use DDB allocation when choosing gen9 watermark method
== Series Details == Series: series starting with [CI,1/2] drm/i915: Don't use DDB allocation when choosing gen9 watermark method URL : https://patchwork.freedesktop.org/series/53901/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Don't use DDB allocation when choosing gen9 watermark method -drivers/gpu/drm/i915/i915_fixed.h:42:43: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_fixed.h:42:43: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_pm.c:6724:35: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_pm.c:6724:35: warning: expression using sizeof(void) Commit: drm/i915: Switch to level-based DDB allocation algorithm (v5) +drivers/gpu/drm/i915/intel_pm.c:4412:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_pm.c:4412:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_pm.c:4423:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_pm.c:4423:25: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:6617:24: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:6617:24: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:6621:35: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:6621:35: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:6621:35: warning: too many warnings +drivers/gpu/drm/i915/intel_pm.c:6617:24: warning: too many warnings ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: DFSM pipe disable is valid from gen9 onwards
== Series Details ==
Series: drm/i915: DFSM pipe disable is valid from gen9 onwards
URL : https://patchwork.freedesktop.org/series/53900/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5296 -> Patchwork_11066
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/53900/revisions/1/mbox/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_11066:
### IGT changes ###
Warnings
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c:
- {fi-kbl-7567u}: PASS -> SKIP +33
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
Participating hosts (48 -> 43)
--
Additional (1): fi-byt-j1900
Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-ctg-p8600 fi-icl-y
Build changes
-
* Linux: CI_DRM_5296 -> Patchwork_11066
CI_DRM_5296: 70751bd8a3f27b035d203ecafcad452f4d7c2c15 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4745: 3b52e8a5809a4e860350c59476a456745cd9fee0 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11066: 88c7b8d76516e045cbad3afbf46328f1f335b218 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
88c7b8d76516 drm/i915: DFSM pipe disable is valid from gen9 onwards
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11066/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v5 2/2] drm/i915: Attach colorspace property and enable modeset
This patch attaches the colorspace connector property to the
hdmi connector. Based on colorspace change, modeset will be
triggered to switch to new colorspace.
Based on colorspace property value create an infoframe
with appropriate colorspace. This can be used to send an
infoframe packet with proper colorspace value set which
will help to enable wider color gamut like BT2020 on sink.
This patch attaches and enables HDMI colorspace, DP will be
taken care separately.
v2: Merged the changes of creating infoframe as well to this
patch as per Maarten's suggestion.
v3: Addressed review comments from Shashank. Separated HDMI
and DP colorspaces as suggested by Ville and Maarten.
v4: Addressed Chris and Ville's review comments, and created a
common colorspace property for DP and HDMI, filtered the list
based on the colorspaces supported by the respective protocol
standard. Handle the default case properly.
v5: Added Platform specific colorspace enums and called the
property creation helper using the same.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_atomic.c| 1 +
drivers/gpu/drm/i915/intel_connector.c | 63 ++
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_hdmi.c | 18 ++
4 files changed, 83 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_atomic.c
b/drivers/gpu/drm/i915/intel_atomic.c
index a5a2c8f..35ef70a 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -125,6 +125,7 @@ int intel_digital_connector_atomic_check(struct
drm_connector *conn,
*/
if (new_conn_state->force_audio != old_conn_state->force_audio ||
new_conn_state->broadcast_rgb != old_conn_state->broadcast_rgb ||
+ new_state->colorspace != old_state->colorspace ||
new_conn_state->base.picture_aspect_ratio !=
old_conn_state->base.picture_aspect_ratio ||
new_conn_state->base.content_type !=
old_conn_state->base.content_type ||
new_conn_state->base.scaling_mode !=
old_conn_state->base.scaling_mode)
diff --git a/drivers/gpu/drm/i915/intel_connector.c
b/drivers/gpu/drm/i915/intel_connector.c
index 18e370f..59fa420 100644
--- a/drivers/gpu/drm/i915/intel_connector.c
+++ b/drivers/gpu/drm/i915/intel_connector.c
@@ -31,6 +31,48 @@
#include "intel_drv.h"
#include "i915_drv.h"
+static const struct drm_prop_enum_list gen10_hdmi_colorspace[] = {
+ /* For Default case, driver will set the colorspace */
+ { COLORIMETRY_DEFAULT, "Default" },
+ /* Standard Definition Colorimetry based on CEA 861 */
+ { COLORIMETRY_ITU_601, "ITU_601" },
+ { COLORIMETRY_ITU_709, "ITU_709" },
+ /* Standard Definition Colorimetry based on IEC 61966-2-4 */
+ { COLORIMETRY_XV_YCC_601, "XV_YCC_601" },
+ /* High Definition Colorimetry based on IEC 61966-2-4 */
+ { COLORIMETRY_XV_YCC_709, "XV_YCC_709" },
+ /* Colorimetry based on IEC 61966-2-1/Amendment 1 */
+ { COLORIMETRY_S_YCC_601, "S_YCC_601" },
+ /* Colorimetry based on IEC 61966-2-5 [33] */
+ { COLORIMETRY_OPYCC_601, "opYCC_601" },
+ /* Colorimetry based on IEC 61966-2-5 */
+ { COLORIMETRY_OPRGB, "opRGB" },
+ /* Colorimetry based on ITU-R BT.2020 */
+ { COLORIMETRY_BT2020_RGB, "BT2020_RGB" },
+ /* Colorimetry based on ITU-R BT.2020 */
+ { COLORIMETRY_BT2020_YCC, "BT2020_YCC" },
+ /* Colorimetry based on ITU-R BT.2020 */
+ { COLORIMETRY_BT2020_CYCC, "BT2020_CYCC" },
+};
+
+static const struct drm_prop_enum_list legacy_hdmi_colorspace[] = {
+ /* For Default case, driver will set the colorspace */
+ { COLORIMETRY_DEFAULT, "Default" },
+ /* Standard Definition Colorimetry based on CEA 861 */
+ { COLORIMETRY_ITU_601, "ITU_601" },
+ { COLORIMETRY_ITU_709, "ITU_709" },
+ /* Standard Definition Colorimetry based on IEC 61966-2-4 */
+ { COLORIMETRY_XV_YCC_601, "XV_YCC_601" },
+ /* High Definition Colorimetry based on IEC 61966-2-4 */
+ { COLORIMETRY_XV_YCC_709, "XV_YCC_709" },
+ /* Colorimetry based on IEC 61966-2-1/Amendment 1 */
+ { COLORIMETRY_S_YCC_601, "S_YCC_601" },
+ /* Colorimetry based on IEC 61966-2-5 [33] */
+ { COLORIMETRY_OPYCC_601, "opYCC_601" },
+ /* Colorimetry based on IEC 61966-2-5 */
+ { COLORIMETRY_OPRGB, "opRGB" },
+};
+
int intel_connector_init(struct intel_connector *connector)
{
struct intel_digital_connector_state *conn_state;
@@ -262,3 +304,24 @@ int intel_ddc_get_modes(struct drm_connector *connector,
connector->dev->mode_config.aspect_ratio_property,
DRM_MODE_PICTURE_ASPECT_NONE);
}
+
+void
+intel_attach_colorspace_property(struct drm_connector *connector)
+{
+ struct drm_device *dev = connector->dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+
+ if (INTEL_GEN(dev_priv) >= 10) {
+
[Intel-gfx] [v5 0/2] Add Colorspace connector property interface
This patch series creates a new connector property to program colorspace to sink devices. Modern sink devices support more than 1 type of colorspace like 601, 709, BT2020 etc. This helps to switch based on content type which is to be displayed. The decision lies with compositors as to in which scenarios, a particular colorspace will be picked. This will be helpful mostly to switch to higher gamut colorspaces like BT2020 when the media content is encoded as BT2020. Thereby giving a good visual experience to users. The expectation from userspace is that it should parse the EDID and get supported colorspaces. Use this property and switch to the one supported. Kernel will not give the supported colorspaces since this is panel dependent and our current property infrastructure is not supporting it. Basically the expectation from userspace is: - Set up CRTC DEGAMMA/CTM/GAMMA to convert to some sink colorspace - Set this new property to let the sink know what it converted the CRTC output to. - This property is just to inform sink what colorspace source is trying to drive. Have tested this using xrandr by using below command: xrandr --output HDMI2 --set "Colorspace" "BT2020_rgb" v2: Addressed Ville and Maarten's review comments. Merged the 2nd and 3rd patch into one common logical patch. v3: Removed Adobe references from enum definitions as per Ville, Hans Verkuil and Jonas Karlman suggestions. Changed default to an unset state where driver will assign the colorspace when not chosen by user, suggested by Ville and Maarten. Addressed other misc review comments from Maarten. Split the changes to have separate colorspace property for DP and HDMI. v4: Addressed Chris and Ville's review comments, and created a common colorspace property for DP and HDMI, filtered the list based on the colorspaces supported by the respective protocol standard. Handled the default case more efficiently. v5: Modified the colorspace property creation helper to take platform specific enum list based on the capabilities of the platform as suggested by Shashank. With this there is no need for segregation between DP and HDMI. Uma Shankar (2): drm: Add colorspace connector property drm/i915: Attach colorspace property and enable modeset drivers/gpu/drm/drm_atomic_uapi.c | 4 ++ drivers/gpu/drm/drm_connector.c| 82 ++ drivers/gpu/drm/i915/intel_atomic.c| 1 + drivers/gpu/drm/i915/intel_connector.c | 63 ++ drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_hdmi.c | 18 include/drm/drm_connector.h| 17 +++ include/uapi/drm/drm_mode.h| 33 ++ 8 files changed, 219 insertions(+) -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v5 1/2] drm: Add colorspace connector property
This patch adds a colorspace connector property, enabling
userspace to switch to various supported colorspaces.
This will help enable BT2020 along with other colorspaces.
v2: Addressed Maarten and Ville's review comments. Enhanced
the colorspace enum to incorporate both HDMI and DP supported
colorspaces. Also, added a default option for colorspace.
v3: Removed Adobe references from enum definitions as per
Ville, Hans Verkuil and Jonas Karlman suggestions. Changed
Default to an unset state where driver will assign the colorspace
is not chosen by user, suggested by Ville and Maarten. Addressed
other misc review comments from Maarten. Split the changes to
have separate colorspace property for DP and HDMI.
v4: Addressed Chris and Ville's review comments, and created a
common colorspace property for DP and HDMI, filtered the list
based on the colorspaces supported by the respective protocol
standard.
v5: Made the property creation helper accept enum list based on
platform capabilties as suggested by Shashank. Consolidated HDMI
and DP property creation in the common helper.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_atomic_uapi.c | 4 ++
drivers/gpu/drm/drm_connector.c | 82 +++
include/drm/drm_connector.h | 17
include/uapi/drm/drm_mode.h | 33
4 files changed, 136 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index 86ac339..9df7520 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -729,6 +729,8 @@ static int drm_atomic_connector_set_property(struct
drm_connector *connector,
return -EINVAL;
}
state->content_protection = val;
+ } else if (property == connector->colorspace_property) {
+ state->colorspace = val;
} else if (property == config->writeback_fb_id_property) {
struct drm_framebuffer *fb = drm_framebuffer_lookup(dev, NULL,
val);
int ret = drm_atomic_set_writeback_fb_for_connector(state, fb);
@@ -797,6 +799,8 @@ static int drm_atomic_connector_set_property(struct
drm_connector *connector,
*val = state->picture_aspect_ratio;
} else if (property == config->content_type_property) {
*val = state->content_type;
+ } else if (property == connector->colorspace_property) {
+ *val = state->colorspace;
} else if (property == connector->scaling_mode_property) {
*val = state->scaling_mode;
} else if (property == connector->content_protection_property) {
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index fa9baac..46928f7 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -826,6 +826,54 @@ int drm_display_info_set_bus_formats(struct
drm_display_info *info,
};
DRM_ENUM_NAME_FN(drm_get_content_protection_name, drm_cp_enum_list)
+/* List of HDMI Colorspaces supported */
+static const struct drm_prop_enum_list hdmi_colorspace[] = {
+ /* For Default case, driver will set the colorspace */
+ { COLORIMETRY_DEFAULT, "Default" },
+ /* Standard Definition Colorimetry based on CEA 861 */
+ { COLORIMETRY_ITU_601, "ITU_601" },
+ { COLORIMETRY_ITU_709, "ITU_709" },
+ /* Standard Definition Colorimetry based on IEC 61966-2-4 */
+ { COLORIMETRY_XV_YCC_601, "XV_YCC_601" },
+ /* High Definition Colorimetry based on IEC 61966-2-4 */
+ { COLORIMETRY_XV_YCC_709, "XV_YCC_709" },
+ /* Colorimetry based on IEC 61966-2-1/Amendment 1 */
+ { COLORIMETRY_S_YCC_601, "S_YCC_601" },
+ /* Colorimetry based on IEC 61966-2-5 [33] */
+ { COLORIMETRY_OPYCC_601, "opYCC_601" },
+ /* Colorimetry based on IEC 61966-2-5 */
+ { COLORIMETRY_OPRGB, "opRGB" },
+ /* Colorimetry based on ITU-R BT.2020 */
+ { COLORIMETRY_BT2020_RGB, "BT2020_RGB" },
+ /* Colorimetry based on ITU-R BT.2020 */
+ { COLORIMETRY_BT2020_YCC, "BT2020_YCC" },
+ /* Colorimetry based on ITU-R BT.2020 */
+ { COLORIMETRY_BT2020_CYCC, "BT2020_CYCC" },
+};
+
+/* List of DP Colorspaces supported */
+static const struct drm_prop_enum_list dp_colorspace[] = {
+ /* For Default case, driver will set the colorspace */
+ { COLORIMETRY_DEFAULT, "Default" },
+ /* Standard Definition Colorimetry based on CEA 861 */
+ { COLORIMETRY_ITU_601, "ITU_601" },
+ { COLORIMETRY_ITU_709, "ITU_709" },
+ /* Standard Definition Colorimetry based on IEC 61966-2-4 */
+ { COLORIMETRY_XV_YCC_601, "XV_YCC_601" },
+ /* High Definition Colorimetry based on IEC 61966-2-4 */
+ { COLORIMETRY_XV_YCC_709, "XV_YCC_709" },
+ /* Colorimetry based on IEC 61966-2-5 */
+ { COLORIMETRY_OPRGB, "opRGB" },
+ /* DP MSA Colorimetry */
+ { DP_COLORIMETRY_Y_CBCR_ITU_601, "YCBCR_ITU_601"
Re: [Intel-gfx] [PATCH] drm/i915: DFSM pipe disable is valid from gen9 onwards
On Tue, Dec 11, 2018 at 09:30:43AM -0800, Bob Paauwe wrote:
> It's not just GEN9 platforms that allow for pipes to be disabled via
> the DFSM register, but all later platforms as well.
>
> Signed-off-by: Bob Paauwe
> ---
> drivers/gpu/drm/i915/intel_device_info.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> b/drivers/gpu/drm/i915/intel_device_info.c
> index 1e56319334f3..7ac641e8c0bd 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -811,7 +811,7 @@ void intel_device_info_runtime_init(struct
> intel_device_info *info)
> DRM_INFO("PipeC fused off\n");
> info->num_pipes -= 1;
> }
> - } else if (HAS_DISPLAY(dev_priv) && IS_GEN9(dev_priv)) {
> + } else if (HAS_DISPLAY(dev_priv) && (INTEL_GEN(dev_priv) >= 9)) {
^^
Drop the pointless parens please. Otherwise seems good.
> u32 dfsm = I915_READ(SKL_DFSM);
> u8 disabled_mask = 0;
> bool invalid;
> --
> 2.17.1
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3,1/2] drm/i915: Don't use DDB allocation when choosing gen9 watermark method
== Series Details ==
Series: series starting with [v3,1/2] drm/i915: Don't use DDB allocation when
choosing gen9 watermark method
URL : https://patchwork.freedesktop.org/series/53898/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5296 -> Patchwork_11065
Summary
---
**WARNING**
Minor unknown changes coming with Patchwork_11065 need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_11065, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/53898/revisions/1/mbox/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_11065:
### IGT changes ###
Warnings
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- fi-hsw-4770:PASS -> SKIP +3
Known issues
Here are the changes found in Patchwork_11065 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_module_load@reload:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
* igt@i915_selftest@live_hangcheck:
- fi-bwr-2160:PASS -> DMESG-FAIL [fdo#108735]
* igt@kms_chamelium@hdmi-hpd-fast:
- {fi-kbl-7500u}: PASS -> FAIL [fdo#108767]
* igt@kms_frontbuffer_tracking@basic:
- fi-byt-clapper: PASS -> FAIL [fdo#103167]
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
- fi-byt-clapper: PASS -> FAIL [fdo#107362]
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-cfl-8109u: PASS -> INCOMPLETE [fdo#106070] / [fdo#108126]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#106070]: https://bugs.freedesktop.org/show_bug.cgi?id=106070
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108126]: https://bugs.freedesktop.org/show_bug.cgi?id=108126
[fdo#108735]: https://bugs.freedesktop.org/show_bug.cgi?id=108735
[fdo#108767]: https://bugs.freedesktop.org/show_bug.cgi?id=108767
Participating hosts (48 -> 43)
--
Additional (1): fi-byt-j1900
Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-ctg-p8600 fi-glk-j4005
Build changes
-
* Linux: CI_DRM_5296 -> Patchwork_11065
CI_DRM_5296: 70751bd8a3f27b035d203ecafcad452f4d7c2c15 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4745: 3b52e8a5809a4e860350c59476a456745cd9fee0 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11065: 90bd51755c2d48489f006ed396fa47512df770e7 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
90bd51755c2d drm/i915: Switch to level-based DDB allocation algorithm (v4)
1c4026616532 drm/i915: Don't use DDB allocation when choosing gen9 watermark
method
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11065/
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 1/2] drm/i915: Don't use DDB allocation when choosing gen9 watermark method
The bspec gives an if/else chain for choosing whether to use "method 1"
or "method 2" for calculating the watermark "Selected Result Blocks"
value for a plane. One of the branches of the if chain is:
"Else If ('plane buffer allocation' is known and (plane buffer
allocation / plane blocks per line) >=1)"
Since our driver currently calculates DDB allocations first and the
actual watermark values second, the plane buffer allocation is known at
this point in our code and we include this test in our driver's logic.
However we plan to soon move to a "watermarks first, ddb allocation
second" sequence where we won't know the DDB allocation at this point.
Let's drop this arm of the if/else statement (effectively considering
the DDB allocation unknown) as an independent patch so that any
regressions can be more accurately bisected to either the different
watermark value (in this patch) or the new DDB allocation (in the next
patch).
Signed-off-by: Matt Roper
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2bba5315b764..bf970cf7b8a5 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4761,13 +4761,6 @@ static int skl_compute_plane_wm(const struct
intel_crtc_state *cstate,
wp->dbuf_block_size < 1) &&
(wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) {
selected_result = method2;
- } else if (ddb_allocation >=
-fixed16_to_u32_round_up(wp->plane_blocks_per_line)) {
- if (IS_GEN9(dev_priv) &&
- !IS_GEMINILAKE(dev_priv))
- selected_result = min_fixed16(method1, method2);
- else
- selected_result = method2;
} else if (latency >= wp->linetime_us) {
if (IS_GEN9(dev_priv) &&
!IS_GEMINILAKE(dev_priv))
--
2.14.4
___
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[Intel-gfx] [CI 2/2] drm/i915: Switch to level-based DDB allocation algorithm (v5)
The DDB allocation algorithm currently used by the driver grants each
plane a very small minimum allocation of DDB blocks and then divies up
all of the remaining blocks based on the percentage of the total data
rate that the plane makes up. It turns out that this proportional
allocation approach is overly-generous with the larger planes and can
leave very small planes wthout a big enough allocation to even hit their
level 0 watermark requirements (especially on APL, which has a smaller
DDB in general than other gen9 platforms). Or there can be situations
where the smallest planes hit a lower watermark level than they should
have been able to hit with a more equitable division of DDB blocks, thus
limiting the overall system sleep state that can be achieved.
The bspec now describes an alternate algorithm that can be used to
overcome these types of issues. With the new algorithm, we calculate
all plane watermark values for all wm levels first, then go back and
partition a pipe's DDB space second. The DDB allocation will calculate
what the highest watermark level that can be achieved on *all* active
planes, and then grant the blocks necessary to hit that level to each
plane. Any remaining blocks are then divided up proportionally
according to data rate, similar to the old algorithm.
There was a previous attempt to implement this algorithm a couple years
ago in bb9d85f6e9d ("drm/i915/skl: New ddb allocation algorithm"), but
some regressions were reported, the patch was reverted, and nobody
ever got around to figuring out exactly where the bug was in that
version. Our watermark code has evolved significantly in the meantime,
but we're still getting bug reports caused by the unfair proportional
algorithm, so let's give this another shot.
v2:
- Make sure cursor allocation stays constant and fixed at the end of
the pipe allocation.
- Fix some watermark level iterators that weren't handling the max
level.
v3:
- Ensure we don't leave any DDB blocks unused by using DIV_ROUND_UP+min
to calculate the extra blocks for each plane. (Ville)
- Replace a while() loop with a for() loop to be more consistent with
surrounding code. (Ville)
- Clean unattainable watermark levels with memset rather than directly
clearing the member fields. Also do the same for the transition
watermark values if they can't be achieved. (Ville)
- Drop min_disp_buf_needed calculations in skl_compute_plane_wm() since
the results are no longer needed or used. (Ville)
- Drop skl_latency[0] != 0 sanity check; both watermark methods already
account for an invalid 0 latency by returning FP_16_16_MAX. (Ville)
v4:
- Break DDB allocation loop when total_data_rate=0 rather than
alloc_size=0. If total_data_rate has dropped to 0, all remaining
planes are disabled, which isn't true for alloc_size (we might just
have not had any remaining blocks to hand out). Plus
total_data_rate=0 is the case we need to avoid to a prevent a
div-by-0. (Ville)
- s/DIV_ROUND_UP/DIV64_U64_ROUND_UP/ to prevent 32-bit breakage (Ville)
v5:
- Don't forget to move 'start' pointer forward for UV surface when
setting plane DDB boundaries. (Ville)
Cc: Ville Syrjälä
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105458
Signed-off-by: Matt Roper
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 383 +++-
1 file changed, 140 insertions(+), 243 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bf970cf7b8a5..6d074f2e69d3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4301,102 +4301,6 @@ icl_get_total_relative_data_rate(struct
intel_crtc_state *intel_cstate,
return total_data_rate;
}
-static uint16_t
-skl_ddb_min_alloc(const struct intel_plane_state *plane_state, const int plane)
-{
- struct drm_framebuffer *fb = plane_state->base.fb;
- uint32_t src_w, src_h;
- uint32_t min_scanlines = 8;
- uint8_t plane_bpp;
-
- if (WARN_ON(!fb))
- return 0;
-
- /* For packed formats, and uv-plane, return 0 */
- if (plane == 1 && fb->format->format != DRM_FORMAT_NV12)
- return 0;
-
- /* For Non Y-tile return 8-blocks */
- if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
- fb->modifier != I915_FORMAT_MOD_Yf_TILED &&
- fb->modifier != I915_FORMAT_MOD_Y_TILED_CCS &&
- fb->modifier != I915_FORMAT_MOD_Yf_TILED_CCS)
- return 8;
-
- /*
-* Src coordinates are already rotated by 270 degrees for
-* the 90/270 degree plane rotation cases (to match the
-* GTT mapping), hence no need to account for rotation here.
-*/
- src_w = drm_rect_width(_state->base.src) >> 16;
- src_h = drm_rect_height(_state->base.src) >> 16;
-
- /* Halve UV plane width and height for NV12 */
- if (plane == 1) {
- src_w
[Intel-gfx] [PATCH] drm/i915: DFSM pipe disable is valid from gen9 onwards
It's not just GEN9 platforms that allow for pipes to be disabled via
the DFSM register, but all later platforms as well.
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/intel_device_info.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index 1e56319334f3..7ac641e8c0bd 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -811,7 +811,7 @@ void intel_device_info_runtime_init(struct
intel_device_info *info)
DRM_INFO("PipeC fused off\n");
info->num_pipes -= 1;
}
- } else if (HAS_DISPLAY(dev_priv) && IS_GEN9(dev_priv)) {
+ } else if (HAS_DISPLAY(dev_priv) && (INTEL_GEN(dev_priv) >= 9)) {
u32 dfsm = I915_READ(SKL_DFSM);
u8 disabled_mask = 0;
bool invalid;
--
2.17.1
___
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Re: [Intel-gfx] [PATCH v3 2/2] drm/i915: Switch to level-based DDB allocation algorithm (v4)
On Tue, Dec 11, 2018 at 09:03:46AM -0800, Matt Roper wrote:
> The DDB allocation algorithm currently used by the driver grants each
> plane a very small minimum allocation of DDB blocks and then divies up
> all of the remaining blocks based on the percentage of the total data
> rate that the plane makes up. It turns out that this proportional
> allocation approach is overly-generous with the larger planes and can
> leave very small planes wthout a big enough allocation to even hit their
> level 0 watermark requirements (especially on APL, which has a smaller
> DDB in general than other gen9 platforms). Or there can be situations
> where the smallest planes hit a lower watermark level than they should
> have been able to hit with a more equitable division of DDB blocks, thus
> limiting the overall system sleep state that can be achieved.
>
> The bspec now describes an alternate algorithm that can be used to
> overcome these types of issues. With the new algorithm, we calculate
> all plane watermark values for all wm levels first, then go back and
> partition a pipe's DDB space second. The DDB allocation will calculate
> what the highest watermark level that can be achieved on *all* active
> planes, and then grant the blocks necessary to hit that level to each
> plane. Any remaining blocks are then divided up proportionally
> according to data rate, similar to the old algorithm.
>
> There was a previous attempt to implement this algorithm a couple years
> ago in bb9d85f6e9d ("drm/i915/skl: New ddb allocation algorithm"), but
> some regressions were reported, the patch was reverted, and nobody
> ever got around to figuring out exactly where the bug was in that
> version. Our watermark code has evolved significantly in the meantime,
> but we're still getting bug reports caused by the unfair proportional
> algorithm, so let's give this another shot.
>
> v2:
> - Make sure cursor allocation stays constant and fixed at the end of
>the pipe allocation.
> - Fix some watermark level iterators that weren't handling the max
>level.
>
> v3:
> - Ensure we don't leave any DDB blocks unused by using DIV_ROUND_UP+min
>to calculate the extra blocks for each plane. (Ville)
> - Replace a while() loop with a for() loop to be more consistent with
>surrounding code. (Ville)
> - Clean unattainable watermark levels with memset rather than directly
>clearing the member fields. Also do the same for the transition
>watermark values if they can't be achieved. (Ville)
> - Drop min_disp_buf_needed calculations in skl_compute_plane_wm() since
>the results are no longer needed or used. (Ville)
> - Drop skl_latency[0] != 0 sanity check; both watermark methods already
>account for an invalid 0 latency by returning FP_16_16_MAX. (Ville)
>
> v4:
> - Break DDB allocation loop when total_data_rate=0 rather than
>alloc_size=0. If total_data_rate has dropped to 0, all remaining
>planes are disabled, which isn't true for alloc_size (we might just
>have not had any remaining blocks to hand out). Plus
>total_data_rate=0 is the case we need to avoid to a prevent a
>div-by-0. (Ville)
> - s/DIV_ROUND_UP/DIV64_U64_ROUND_UP/ to prevent 32-bit breakage (Ville)
>
> Cc: Ville Syrjälä
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105458
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/intel_pm.c | 381
> +++-
> 1 file changed, 138 insertions(+), 243 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index bf970cf7b8a5..3bdd8fa40eac 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4301,102 +4301,6 @@ icl_get_total_relative_data_rate(struct
> intel_crtc_state *intel_cstate,
> return total_data_rate;
> }
>
> -static uint16_t
> -skl_ddb_min_alloc(const struct intel_plane_state *plane_state, const int
> plane)
> -{
> - struct drm_framebuffer *fb = plane_state->base.fb;
> - uint32_t src_w, src_h;
> - uint32_t min_scanlines = 8;
> - uint8_t plane_bpp;
> -
> - if (WARN_ON(!fb))
> - return 0;
> -
> - /* For packed formats, and uv-plane, return 0 */
> - if (plane == 1 && fb->format->format != DRM_FORMAT_NV12)
> - return 0;
> -
> - /* For Non Y-tile return 8-blocks */
> - if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
> - fb->modifier != I915_FORMAT_MOD_Yf_TILED &&
> - fb->modifier != I915_FORMAT_MOD_Y_TILED_CCS &&
> - fb->modifier != I915_FORMAT_MOD_Yf_TILED_CCS)
> - return 8;
> -
> - /*
> - * Src coordinates are already rotated by 270 degrees for
> - * the 90/270 degree plane rotation cases (to match the
> - * GTT mapping), hence no need to account for rotation here.
> - */
> - src_w = drm_rect_width(_state->base.src) >> 16;
> - src_h = drm_rect_height(_state->base.src) >> 16;
> -
> - /* Halve UV
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v3,1/2] drm/i915: Don't use DDB allocation when choosing gen9 watermark method
== Series Details == Series: series starting with [v3,1/2] drm/i915: Don't use DDB allocation when choosing gen9 watermark method URL : https://patchwork.freedesktop.org/series/53898/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Don't use DDB allocation when choosing gen9 watermark method -drivers/gpu/drm/i915/i915_fixed.h:42:43: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_fixed.h:42:43: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_pm.c:6724:35: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_pm.c:6724:35: warning: expression using sizeof(void) Commit: drm/i915: Switch to level-based DDB allocation algorithm (v4) +drivers/gpu/drm/i915/intel_pm.c:4412:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_pm.c:4412:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_pm.c:4423:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_pm.c:4423:25: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:6615:24: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:6615:24: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:6619:35: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:6619:35: warning: expression using sizeof(void) -drivers/gpu/drm/i915/intel_pm.c:6619:35: warning: too many warnings +drivers/gpu/drm/i915/intel_pm.c:6615:24: warning: too many warnings ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 1/2] drm/i915: Don't use DDB allocation when choosing gen9 watermark method
The bspec gives an if/else chain for choosing whether to use "method 1"
or "method 2" for calculating the watermark "Selected Result Blocks"
value for a plane. One of the branches of the if chain is:
"Else If ('plane buffer allocation' is known and (plane buffer
allocation / plane blocks per line) >=1)"
Since our driver currently calculates DDB allocations first and the
actual watermark values second, the plane buffer allocation is known at
this point in our code and we include this test in our driver's logic.
However we plan to soon move to a "watermarks first, ddb allocation
second" sequence where we won't know the DDB allocation at this point.
Let's drop this arm of the if/else statement (effectively considering
the DDB allocation unknown) as an independent patch so that any
regressions can be more accurately bisected to either the different
watermark value (in this patch) or the new DDB allocation (in the next
patch).
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/intel_pm.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2bba5315b764..bf970cf7b8a5 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4761,13 +4761,6 @@ static int skl_compute_plane_wm(const struct
intel_crtc_state *cstate,
wp->dbuf_block_size < 1) &&
(wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) {
selected_result = method2;
- } else if (ddb_allocation >=
-fixed16_to_u32_round_up(wp->plane_blocks_per_line)) {
- if (IS_GEN9(dev_priv) &&
- !IS_GEMINILAKE(dev_priv))
- selected_result = min_fixed16(method1, method2);
- else
- selected_result = method2;
} else if (latency >= wp->linetime_us) {
if (IS_GEN9(dev_priv) &&
!IS_GEMINILAKE(dev_priv))
--
2.14.4
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[Intel-gfx] [PATCH v3 2/2] drm/i915: Switch to level-based DDB allocation algorithm (v4)
The DDB allocation algorithm currently used by the driver grants each
plane a very small minimum allocation of DDB blocks and then divies up
all of the remaining blocks based on the percentage of the total data
rate that the plane makes up. It turns out that this proportional
allocation approach is overly-generous with the larger planes and can
leave very small planes wthout a big enough allocation to even hit their
level 0 watermark requirements (especially on APL, which has a smaller
DDB in general than other gen9 platforms). Or there can be situations
where the smallest planes hit a lower watermark level than they should
have been able to hit with a more equitable division of DDB blocks, thus
limiting the overall system sleep state that can be achieved.
The bspec now describes an alternate algorithm that can be used to
overcome these types of issues. With the new algorithm, we calculate
all plane watermark values for all wm levels first, then go back and
partition a pipe's DDB space second. The DDB allocation will calculate
what the highest watermark level that can be achieved on *all* active
planes, and then grant the blocks necessary to hit that level to each
plane. Any remaining blocks are then divided up proportionally
according to data rate, similar to the old algorithm.
There was a previous attempt to implement this algorithm a couple years
ago in bb9d85f6e9d ("drm/i915/skl: New ddb allocation algorithm"), but
some regressions were reported, the patch was reverted, and nobody
ever got around to figuring out exactly where the bug was in that
version. Our watermark code has evolved significantly in the meantime,
but we're still getting bug reports caused by the unfair proportional
algorithm, so let's give this another shot.
v2:
- Make sure cursor allocation stays constant and fixed at the end of
the pipe allocation.
- Fix some watermark level iterators that weren't handling the max
level.
v3:
- Ensure we don't leave any DDB blocks unused by using DIV_ROUND_UP+min
to calculate the extra blocks for each plane. (Ville)
- Replace a while() loop with a for() loop to be more consistent with
surrounding code. (Ville)
- Clean unattainable watermark levels with memset rather than directly
clearing the member fields. Also do the same for the transition
watermark values if they can't be achieved. (Ville)
- Drop min_disp_buf_needed calculations in skl_compute_plane_wm() since
the results are no longer needed or used. (Ville)
- Drop skl_latency[0] != 0 sanity check; both watermark methods already
account for an invalid 0 latency by returning FP_16_16_MAX. (Ville)
v4:
- Break DDB allocation loop when total_data_rate=0 rather than
alloc_size=0. If total_data_rate has dropped to 0, all remaining
planes are disabled, which isn't true for alloc_size (we might just
have not had any remaining blocks to hand out). Plus
total_data_rate=0 is the case we need to avoid to a prevent a
div-by-0. (Ville)
- s/DIV_ROUND_UP/DIV64_U64_ROUND_UP/ to prevent 32-bit breakage (Ville)
Cc: Ville Syrjälä
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105458
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/intel_pm.c | 381 +++-
1 file changed, 138 insertions(+), 243 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bf970cf7b8a5..3bdd8fa40eac 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4301,102 +4301,6 @@ icl_get_total_relative_data_rate(struct
intel_crtc_state *intel_cstate,
return total_data_rate;
}
-static uint16_t
-skl_ddb_min_alloc(const struct intel_plane_state *plane_state, const int plane)
-{
- struct drm_framebuffer *fb = plane_state->base.fb;
- uint32_t src_w, src_h;
- uint32_t min_scanlines = 8;
- uint8_t plane_bpp;
-
- if (WARN_ON(!fb))
- return 0;
-
- /* For packed formats, and uv-plane, return 0 */
- if (plane == 1 && fb->format->format != DRM_FORMAT_NV12)
- return 0;
-
- /* For Non Y-tile return 8-blocks */
- if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
- fb->modifier != I915_FORMAT_MOD_Yf_TILED &&
- fb->modifier != I915_FORMAT_MOD_Y_TILED_CCS &&
- fb->modifier != I915_FORMAT_MOD_Yf_TILED_CCS)
- return 8;
-
- /*
-* Src coordinates are already rotated by 270 degrees for
-* the 90/270 degree plane rotation cases (to match the
-* GTT mapping), hence no need to account for rotation here.
-*/
- src_w = drm_rect_width(_state->base.src) >> 16;
- src_h = drm_rect_height(_state->base.src) >> 16;
-
- /* Halve UV plane width and height for NV12 */
- if (plane == 1) {
- src_w /= 2;
- src_h /= 2;
- }
-
- plane_bpp = fb->format->cpp[plane];
-
- if
Re: [Intel-gfx] [PATCH v2 2/2] drm/i915: Switch to level-based DDB allocation algorithm (v3)
On Tue, Dec 11, 2018 at 06:21:29PM +0200, Ville Syrjälä wrote:
> On Tue, Dec 11, 2018 at 08:11:16AM -0800, Matt Roper wrote:
> > On Tue, Dec 11, 2018 at 05:59:56PM +0200, Ville Syrjälä wrote:
> > > On Mon, Dec 10, 2018 at 05:05:43PM -0800, Matt Roper wrote:
> > ...snip...
> > > >
> > > > - alloc_size -= total_min_blocks;
> > > > - cstate->wm.skl.plane_ddb_y[PLANE_CURSOR].start = alloc->end -
> > > > minimum[PLANE_CURSOR];
> > > > - cstate->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end;
> > > > -
> > > > /*
> > > > -* 2. Distribute the remaining space in proportion to the
> > > > amount of
> > > > -* data each plane needs to fetch from memory.
> > > > -*
> > > > -* FIXME: we may not allocate every single block here.
> > > > +* Grant each plane the blocks it requires at the highest
> > > > achievable
> > > > +* watermark level, plus an extra share of the leftover blocks
> > > > +* proportional to its relative data rate.
> > > > */
> > > > - if (total_data_rate == 0)
> > > > - return 0;
> > > > -
> > > > - start = alloc->start;
> > > > for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> > > > - u64 data_rate, uv_data_rate;
> > > > - uint16_t plane_blocks, uv_plane_blocks;
> > > > + u64 rate;
> > > > + u16 extra;
> > > >
> > > > if (plane_id == PLANE_CURSOR)
> > > > continue;
> > > > + if (alloc_size == 0)
> > > > + continue;
> > >
> > > This seems wrong. We wouldn't assign anything to total/uv_total for the
> > > plane in this case. I guess you could move those assignments to the
> > > earlier loop and then s/continue/break/ here? Or we just remove the
> > > continue entirely and let the calculations go through even if
> > > alloc_size==0.
> >
> > It should probably be a break, since we'll only hit this on a loop
> > iteration where we've handed the whole pipe allocation and all remaining
> > planes are disabled. The total and uv_total were initialized to 0 at
> > initialization time, so that should be correct for all remaining planes.
>
> Not sure we can trust all the remaining planes to be really off due to
> the round_up.
>
> >
> > Also, we can't let the calculation proceed here, otherwise we'll divide
> > by 0 (total_data_rate) farther down since that value also decreases with
> > each loop iteration.
Oh and there's actually no guarantee that we have any extra blocks left
after accounting for the watermarks anyway.
>
> Just keep the 'if (total_data_rate==0) return 0;' before the loop?
>
> >
> >
> > Matt
> >
> > >
> > > >
> > > > - data_rate = plane_data_rate[plane_id];
> > > > + wm = >wm.skl.optimal.planes[plane_id];
> > > >
> > > > - /*
> > > > -* allocation for (packed formats) or (uv-plane part of
> > > > planar format):
> > > > -* promote the expression to 64 bits to avoid
> > > > overflowing, the
> > > > -* result is < available as data_rate / total_data_rate
> > > > < 1
> > > > -*/
> > > > - plane_blocks = minimum[plane_id];
> > > > - plane_blocks += div64_u64(alloc_size * data_rate,
> > > > total_data_rate);
> > > > + rate = plane_data_rate[plane_id];
> > > > + extra = min_t(u16, alloc_size,
> > > > + DIV_ROUND_UP(alloc_size * rate,
> > > > total_data_rate));
>
> Needs DIV64_U64_ROUND_UP() on 32bit.
>
> > > > + total[plane_id] = wm->wm[level].plane_res_b + extra;
> > > > + alloc_size -= extra;
> > > > + total_data_rate -= rate;
> > > >
> > > > - /* Leave disabled planes at (0,0) */
> > > > - if (data_rate) {
> > > > - cstate->wm.skl.plane_ddb_y[plane_id].start =
> > > > start;
> > > > - cstate->wm.skl.plane_ddb_y[plane_id].end =
> > > > start + plane_blocks;
> > > > - }
> > > > + if (alloc_size == 0)
> > > > + continue;
> > > >
> > > > - start += plane_blocks;
> > > > + rate = uv_plane_data_rate[plane_id];
> > > > + extra = min_t(u16, alloc_size,
> > > > + DIV_ROUND_UP(alloc_size * rate,
> > > > total_data_rate));
> > > > + uv_total[plane_id] = wm->uv_wm[level].plane_res_b +
> > > > extra;
> > > > + alloc_size -= extra;
> > > > + total_data_rate -= rate;
> > > > + }
> > > > + WARN_ON(alloc_size != 0 || total_data_rate != 0);
> > > >
> > > > - /* Allocate DDB for UV plane for planar format/NV12 */
> > > > - uv_data_rate = uv_plane_data_rate[plane_id];
> > > > + /* Set the actual DDB start/end points
Re: [Intel-gfx] [PATCH v2 2/2] drm/i915: Switch to level-based DDB allocation algorithm (v3)
On Tue, Dec 11, 2018 at 08:11:16AM -0800, Matt Roper wrote:
> On Tue, Dec 11, 2018 at 05:59:56PM +0200, Ville Syrjälä wrote:
> > On Mon, Dec 10, 2018 at 05:05:43PM -0800, Matt Roper wrote:
> ...snip...
> > >
> > > - alloc_size -= total_min_blocks;
> > > - cstate->wm.skl.plane_ddb_y[PLANE_CURSOR].start = alloc->end -
> > > minimum[PLANE_CURSOR];
> > > - cstate->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end;
> > > -
> > > /*
> > > - * 2. Distribute the remaining space in proportion to the amount of
> > > - * data each plane needs to fetch from memory.
> > > - *
> > > - * FIXME: we may not allocate every single block here.
> > > + * Grant each plane the blocks it requires at the highest achievable
> > > + * watermark level, plus an extra share of the leftover blocks
> > > + * proportional to its relative data rate.
> > >*/
> > > - if (total_data_rate == 0)
> > > - return 0;
> > > -
> > > - start = alloc->start;
> > > for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> > > - u64 data_rate, uv_data_rate;
> > > - uint16_t plane_blocks, uv_plane_blocks;
> > > + u64 rate;
> > > + u16 extra;
> > >
> > > if (plane_id == PLANE_CURSOR)
> > > continue;
> > > + if (alloc_size == 0)
> > > + continue;
> >
> > This seems wrong. We wouldn't assign anything to total/uv_total for the
> > plane in this case. I guess you could move those assignments to the
> > earlier loop and then s/continue/break/ here? Or we just remove the
> > continue entirely and let the calculations go through even if
> > alloc_size==0.
>
> It should probably be a break, since we'll only hit this on a loop
> iteration where we've handed the whole pipe allocation and all remaining
> planes are disabled. The total and uv_total were initialized to 0 at
> initialization time, so that should be correct for all remaining planes.
Not sure we can trust all the remaining planes to be really off due to
the round_up.
>
> Also, we can't let the calculation proceed here, otherwise we'll divide
> by 0 (total_data_rate) farther down since that value also decreases with
> each loop iteration.
Just keep the 'if (total_data_rate==0) return 0;' before the loop?
>
>
> Matt
>
> >
> > >
> > > - data_rate = plane_data_rate[plane_id];
> > > + wm = >wm.skl.optimal.planes[plane_id];
> > >
> > > - /*
> > > - * allocation for (packed formats) or (uv-plane part of planar
> > > format):
> > > - * promote the expression to 64 bits to avoid overflowing, the
> > > - * result is < available as data_rate / total_data_rate < 1
> > > - */
> > > - plane_blocks = minimum[plane_id];
> > > - plane_blocks += div64_u64(alloc_size * data_rate,
> > > total_data_rate);
> > > + rate = plane_data_rate[plane_id];
> > > + extra = min_t(u16, alloc_size,
> > > + DIV_ROUND_UP(alloc_size * rate, total_data_rate));
Needs DIV64_U64_ROUND_UP() on 32bit.
> > > + total[plane_id] = wm->wm[level].plane_res_b + extra;
> > > + alloc_size -= extra;
> > > + total_data_rate -= rate;
> > >
> > > - /* Leave disabled planes at (0,0) */
> > > - if (data_rate) {
> > > - cstate->wm.skl.plane_ddb_y[plane_id].start = start;
> > > - cstate->wm.skl.plane_ddb_y[plane_id].end = start +
> > > plane_blocks;
> > > - }
> > > + if (alloc_size == 0)
> > > + continue;
> > >
> > > - start += plane_blocks;
> > > + rate = uv_plane_data_rate[plane_id];
> > > + extra = min_t(u16, alloc_size,
> > > + DIV_ROUND_UP(alloc_size * rate, total_data_rate));
> > > + uv_total[plane_id] = wm->uv_wm[level].plane_res_b + extra;
> > > + alloc_size -= extra;
> > > + total_data_rate -= rate;
> > > + }
> > > + WARN_ON(alloc_size != 0 || total_data_rate != 0);
> > >
> > > - /* Allocate DDB for UV plane for planar format/NV12 */
> > > - uv_data_rate = uv_plane_data_rate[plane_id];
> > > + /* Set the actual DDB start/end points for each plane */
> > > + start = alloc->start;
> > > + for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> > > + struct skl_ddb_entry *plane_alloc, *uv_plane_alloc;
> > >
> > > - uv_plane_blocks = uv_minimum[plane_id];
> > > - uv_plane_blocks += div64_u64(alloc_size * uv_data_rate,
> > > total_data_rate);
> > > + if (plane_id == PLANE_CURSOR)
> > > + continue;
> > > +
> > > + plane_alloc = >wm.skl.plane_ddb_y[plane_id];
> > > + uv_plane_alloc = >wm.skl.plane_ddb_uv[plane_id];
> > >
> > > /* Gen11+ uses a separate plane for UV watermarks */
> > > - WARN_ON(INTEL_GEN(dev_priv) >= 11 && uv_plane_blocks);
> > > + WARN_ON(INTEL_GEN(dev_priv) >= 11 && uv_total[plane_id]);
> > > +
> > > + /* Leave
Re: [Intel-gfx] [PATCH v2 2/2] drm/i915: Switch to level-based DDB allocation algorithm (v3)
On Tue, Dec 11, 2018 at 05:59:56PM +0200, Ville Syrjälä wrote:
> On Mon, Dec 10, 2018 at 05:05:43PM -0800, Matt Roper wrote:
...snip...
> >
> > - alloc_size -= total_min_blocks;
> > - cstate->wm.skl.plane_ddb_y[PLANE_CURSOR].start = alloc->end -
> > minimum[PLANE_CURSOR];
> > - cstate->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end;
> > -
> > /*
> > -* 2. Distribute the remaining space in proportion to the amount of
> > -* data each plane needs to fetch from memory.
> > -*
> > -* FIXME: we may not allocate every single block here.
> > +* Grant each plane the blocks it requires at the highest achievable
> > +* watermark level, plus an extra share of the leftover blocks
> > +* proportional to its relative data rate.
> > */
> > - if (total_data_rate == 0)
> > - return 0;
> > -
> > - start = alloc->start;
> > for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> > - u64 data_rate, uv_data_rate;
> > - uint16_t plane_blocks, uv_plane_blocks;
> > + u64 rate;
> > + u16 extra;
> >
> > if (plane_id == PLANE_CURSOR)
> > continue;
> > + if (alloc_size == 0)
> > + continue;
>
> This seems wrong. We wouldn't assign anything to total/uv_total for the
> plane in this case. I guess you could move those assignments to the
> earlier loop and then s/continue/break/ here? Or we just remove the
> continue entirely and let the calculations go through even if
> alloc_size==0.
It should probably be a break, since we'll only hit this on a loop
iteration where we've handed the whole pipe allocation and all remaining
planes are disabled. The total and uv_total were initialized to 0 at
initialization time, so that should be correct for all remaining planes.
Also, we can't let the calculation proceed here, otherwise we'll divide
by 0 (total_data_rate) farther down since that value also decreases with
each loop iteration.
Matt
>
> >
> > - data_rate = plane_data_rate[plane_id];
> > + wm = >wm.skl.optimal.planes[plane_id];
> >
> > - /*
> > -* allocation for (packed formats) or (uv-plane part of planar
> > format):
> > -* promote the expression to 64 bits to avoid overflowing, the
> > -* result is < available as data_rate / total_data_rate < 1
> > -*/
> > - plane_blocks = minimum[plane_id];
> > - plane_blocks += div64_u64(alloc_size * data_rate,
> > total_data_rate);
> > + rate = plane_data_rate[plane_id];
> > + extra = min_t(u16, alloc_size,
> > + DIV_ROUND_UP(alloc_size * rate, total_data_rate));
> > + total[plane_id] = wm->wm[level].plane_res_b + extra;
> > + alloc_size -= extra;
> > + total_data_rate -= rate;
> >
> > - /* Leave disabled planes at (0,0) */
> > - if (data_rate) {
> > - cstate->wm.skl.plane_ddb_y[plane_id].start = start;
> > - cstate->wm.skl.plane_ddb_y[plane_id].end = start +
> > plane_blocks;
> > - }
> > + if (alloc_size == 0)
> > + continue;
> >
> > - start += plane_blocks;
> > + rate = uv_plane_data_rate[plane_id];
> > + extra = min_t(u16, alloc_size,
> > + DIV_ROUND_UP(alloc_size * rate, total_data_rate));
> > + uv_total[plane_id] = wm->uv_wm[level].plane_res_b + extra;
> > + alloc_size -= extra;
> > + total_data_rate -= rate;
> > + }
> > + WARN_ON(alloc_size != 0 || total_data_rate != 0);
> >
> > - /* Allocate DDB for UV plane for planar format/NV12 */
> > - uv_data_rate = uv_plane_data_rate[plane_id];
> > + /* Set the actual DDB start/end points for each plane */
> > + start = alloc->start;
> > + for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> > + struct skl_ddb_entry *plane_alloc, *uv_plane_alloc;
> >
> > - uv_plane_blocks = uv_minimum[plane_id];
> > - uv_plane_blocks += div64_u64(alloc_size * uv_data_rate,
> > total_data_rate);
> > + if (plane_id == PLANE_CURSOR)
> > + continue;
> > +
> > + plane_alloc = >wm.skl.plane_ddb_y[plane_id];
> > + uv_plane_alloc = >wm.skl.plane_ddb_uv[plane_id];
> >
> > /* Gen11+ uses a separate plane for UV watermarks */
> > - WARN_ON(INTEL_GEN(dev_priv) >= 11 && uv_plane_blocks);
> > + WARN_ON(INTEL_GEN(dev_priv) >= 11 && uv_total[plane_id]);
> > +
> > + /* Leave disabled planes at (0,0) */
> > + if (total[plane_id]) {
> > + plane_alloc->start = start;
> > + plane_alloc->end = start += total[plane_id];
> > + }
> >
> > - if (uv_data_rate) {
> > - cstate->wm.skl.plane_ddb_uv[plane_id].start = start;
> > -
Re: [Intel-gfx] [PATCH v2 2/2] drm/i915: Switch to level-based DDB allocation algorithm (v3)
On Mon, Dec 10, 2018 at 05:05:43PM -0800, Matt Roper wrote:
> The DDB allocation algorithm currently used by the driver grants each
> plane a very small minimum allocation of DDB blocks and then divies up
> all of the remaining blocks based on the percentage of the total data
> rate that the plane makes up. It turns out that this proportional
> allocation approach is overly-generous with the larger planes and can
> leave very small planes wthout a big enough allocation to even hit their
> level 0 watermark requirements (especially on APL, which has a smaller
> DDB in general than other gen9 platforms). Or there can be situations
> where the smallest planes hit a lower watermark level than they should
> have been able to hit with a more equitable division of DDB blocks, thus
> limiting the overall system sleep state that can be achieved.
>
> The bspec now describes an alternate algorithm that can be used to
> overcome these types of issues. With the new algorithm, we calculate
> all plane watermark values for all wm levels first, then go back and
> partition a pipe's DDB space second. The DDB allocation will calculate
> what the highest watermark level that can be achieved on *all* active
> planes, and then grant the blocks necessary to hit that level to each
> plane. Any remaining blocks are then divided up proportionally
> according to data rate, similar to the old algorithm.
>
> There was a previous attempt to implement this algorithm a couple years
> ago in bb9d85f6e9d ("drm/i915/skl: New ddb allocation algorithm"), but
> some regressions were reported, the patch was reverted, and nobody
> ever got around to figuring out exactly where the bug was in that
> version. Our watermark code has evolved significantly in the meantime,
> but we're still getting bug reports caused by the unfair proportional
> algorithm, so let's give this another shot.
>
> v2:
> - Make sure cursor allocation stays constant and fixed at the end of
>the pipe allocation.
> - Fix some watermark level iterators that weren't handling the max
>level.
>
> v3:
> - Ensure we don't leave any DDB blocks unused by using DIV_ROUND_UP+min
>to calculate the extra blocks for each plane. (Ville)
> - Replace a while() loop with a for() loop to be more consistent with
>surrounding code. (Ville)
> - Clean unattainable watermark levels with memset rather than directly
>clearing the member fields. Also do the same for the transition
>watermark values if they can't be achieved. (Ville)
> - Drop min_disp_buf_needed calculations in skl_compute_plane_wm() since
>the results are no longer needed or used. (Ville)
> - Drop skl_latency[0] != 0 sanity check; both watermark methods already
>account for an invalid 0 latency by returning FP_16_16_MAX. (Ville)
>
> Cc: Ville Syrjälä
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105458
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/intel_pm.c | 376
> ++--
> 1 file changed, 132 insertions(+), 244 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index bf970cf7b8a5..f5f86757457d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4301,102 +4301,6 @@ icl_get_total_relative_data_rate(struct
> intel_crtc_state *intel_cstate,
> return total_data_rate;
> }
>
> -static uint16_t
> -skl_ddb_min_alloc(const struct intel_plane_state *plane_state, const int
> plane)
> -{
> - struct drm_framebuffer *fb = plane_state->base.fb;
> - uint32_t src_w, src_h;
> - uint32_t min_scanlines = 8;
> - uint8_t plane_bpp;
> -
> - if (WARN_ON(!fb))
> - return 0;
> -
> - /* For packed formats, and uv-plane, return 0 */
> - if (plane == 1 && fb->format->format != DRM_FORMAT_NV12)
> - return 0;
> -
> - /* For Non Y-tile return 8-blocks */
> - if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
> - fb->modifier != I915_FORMAT_MOD_Yf_TILED &&
> - fb->modifier != I915_FORMAT_MOD_Y_TILED_CCS &&
> - fb->modifier != I915_FORMAT_MOD_Yf_TILED_CCS)
> - return 8;
> -
> - /*
> - * Src coordinates are already rotated by 270 degrees for
> - * the 90/270 degree plane rotation cases (to match the
> - * GTT mapping), hence no need to account for rotation here.
> - */
> - src_w = drm_rect_width(_state->base.src) >> 16;
> - src_h = drm_rect_height(_state->base.src) >> 16;
> -
> - /* Halve UV plane width and height for NV12 */
> - if (plane == 1) {
> - src_w /= 2;
> - src_h /= 2;
> - }
> -
> - plane_bpp = fb->format->cpp[plane];
> -
> - if (drm_rotation_90_or_270(plane_state->base.rotation)) {
> - switch (plane_bpp) {
> - case 1:
> - min_scanlines = 32;
> - break;
> - case 2:
> - min_scanlines =
Re: [Intel-gfx] [PATCH 4/7] drm: Move the legacy kms disable_all helper to crtc helpers
On Tue, Dec 11, 2018 at 10:53 AM Sean Paul wrote:
>
> On Mon, Dec 10, 2018 at 10:58:20AM -0500, Alex Deucher wrote:
> > On Mon, Dec 10, 2018 at 5:04 AM Daniel Vetter
> > wrote:
> > >
> > > It's not a core function, and the matching atomic functions are also
> > > not in the core. Plus the suspend/resume helper is also already there.
> > >
> > > Needs a tiny bit of open-coding, but less midlayer beats that I think.
> > >
> > > Cc: Sam Bobroff
> > > Signed-off-by: Daniel Vetter
> > > Cc: Maarten Lankhorst
> > > Cc: Maxime Ripard
> > > Cc: Sean Paul
> > > Cc: David Airlie
> > > Cc: Ben Skeggs
> > > Cc: Alex Deucher
> > > Cc: "Christian König"
> > > Cc: "David (ChunMing) Zhou"
> > > Cc: Rex Zhu
> > > Cc: Andrey Grodzovsky
> > > Cc: Huang Rui
> > > Cc: Shaoyun Liu
> > > Cc: Monk Liu
> > > Cc: nouv...@lists.freedesktop.org
> > > Cc: amd-...@lists.freedesktop.org
> > > ---
> > > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
> > > drivers/gpu/drm/drm_crtc.c | 31 ---
> > > drivers/gpu/drm/drm_crtc_helper.c | 35 ++
> > > drivers/gpu/drm/nouveau/nouveau_display.c | 2 +-
> > > drivers/gpu/drm/radeon/radeon_display.c| 2 +-
> > > include/drm/drm_crtc.h | 2 --
> > > include/drm/drm_crtc_helper.h | 1 +
> > > 7 files changed, 39 insertions(+), 36 deletions(-)
> > >
>
> /snip
>
> > > diff --git a/drivers/gpu/drm/drm_crtc_helper.c
> > > b/drivers/gpu/drm/drm_crtc_helper.c
> > > index a3c81850e755..23159eb494f1 100644
> > > --- a/drivers/gpu/drm/drm_crtc_helper.c
> > > +++ b/drivers/gpu/drm/drm_crtc_helper.c
> > > @@ -984,3 +984,38 @@ void drm_helper_resume_force_mode(struct drm_device
> > > *dev)
> > > drm_modeset_unlock_all(dev);
> > > }
> > > EXPORT_SYMBOL(drm_helper_resume_force_mode);
> > > +
> > > +/**
> > > + * drm_helper_force_disable_all - Forcibly turn off all enabled CRTCs
> > > + * @dev: DRM device whose CRTCs to turn off
> > > + *
> > > + * Drivers may want to call this on unload to ensure that all displays
> > > are
> > > + * unlit and the GPU is in a consistent, low power state. Takes modeset
> > > locks.
> > > + *
> > > + * Note: This should only be used by non-atomic legacy drivers. For an
> > > atomic
> > > + * version look at drm_atomic_helper_shutdown().
> > > + *
> > > + * Returns:
> > > + * Zero on success, error code on failure.
> > > + */
> > > +int drm_helper_force_disable_all(struct drm_device *dev)
> >
> > Maybe put crtc somewhere in the function name so it's clear what we
> > are disabling.
>
> FWIW, I think it's more clear this way. set_config_internal will turn off
> everything attached to the crtc, so _everything_ will be disabled in this
> case.
I'm not pressed. RB either way for me as well.
Alex
>
> Either way,
>
> Reviewed-by: Sean Paul
>
> Sean
>
> > With that fixed:
> > Reviewed-by: Alex Deucher
> >
> > > +{
> > > + struct drm_crtc *crtc;
> > > + int ret = 0;
> > > +
> > > + drm_modeset_lock_all(dev);
> > > + drm_for_each_crtc(crtc, dev)
> > > + if (crtc->enabled) {
> > > + struct drm_mode_set set = {
> > > + .crtc = crtc,
> > > + };
> > > +
> > > + ret = drm_mode_set_config_internal();
> > > + if (ret)
> > > + goto out;
> > > + }
> > > +out:
> > > + drm_modeset_unlock_all(dev);
> > > + return ret;
> > > +}
> > > +EXPORT_SYMBOL(drm_helper_force_disable_all);
> > > diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c
> > > b/drivers/gpu/drm/nouveau/nouveau_display.c
> > > index f326ffd86766..5d273a655479 100644
> > > --- a/drivers/gpu/drm/nouveau/nouveau_display.c
> > > +++ b/drivers/gpu/drm/nouveau/nouveau_display.c
> > > @@ -453,7 +453,7 @@ nouveau_display_fini(struct drm_device *dev, bool
> > > suspend, bool runtime)
> > > if (drm_drv_uses_atomic_modeset(dev))
> > > drm_atomic_helper_shutdown(dev);
> > > else
> > > - drm_crtc_force_disable_all(dev);
> > > + drm_helper_force_disable_all(dev);
> > > }
> > >
> > > /* disable flip completion events */
> > > diff --git a/drivers/gpu/drm/radeon/radeon_display.c
> > > b/drivers/gpu/drm/radeon/radeon_display.c
> > > index e6912eb99b42..92332226e5cf 100644
> > > --- a/drivers/gpu/drm/radeon/radeon_display.c
> > > +++ b/drivers/gpu/drm/radeon/radeon_display.c
> > > @@ -1643,7 +1643,7 @@ void radeon_modeset_fini(struct radeon_device *rdev)
> > > if (rdev->mode_info.mode_config_initialized) {
> > > drm_kms_helper_poll_fini(rdev->ddev);
> > > radeon_hpd_fini(rdev);
> > > - drm_crtc_force_disable_all(rdev->ddev);
> > > + drm_helper_force_disable_all(rdev->ddev);
> > >
Re: [Intel-gfx] [PATCH 4/7] drm: Move the legacy kms disable_all helper to crtc helpers
On Mon, Dec 10, 2018 at 10:58:20AM -0500, Alex Deucher wrote:
> On Mon, Dec 10, 2018 at 5:04 AM Daniel Vetter wrote:
> >
> > It's not a core function, and the matching atomic functions are also
> > not in the core. Plus the suspend/resume helper is also already there.
> >
> > Needs a tiny bit of open-coding, but less midlayer beats that I think.
> >
> > Cc: Sam Bobroff
> > Signed-off-by: Daniel Vetter
> > Cc: Maarten Lankhorst
> > Cc: Maxime Ripard
> > Cc: Sean Paul
> > Cc: David Airlie
> > Cc: Ben Skeggs
> > Cc: Alex Deucher
> > Cc: "Christian König"
> > Cc: "David (ChunMing) Zhou"
> > Cc: Rex Zhu
> > Cc: Andrey Grodzovsky
> > Cc: Huang Rui
> > Cc: Shaoyun Liu
> > Cc: Monk Liu
> > Cc: nouv...@lists.freedesktop.org
> > Cc: amd-...@lists.freedesktop.org
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
> > drivers/gpu/drm/drm_crtc.c | 31 ---
> > drivers/gpu/drm/drm_crtc_helper.c | 35 ++
> > drivers/gpu/drm/nouveau/nouveau_display.c | 2 +-
> > drivers/gpu/drm/radeon/radeon_display.c| 2 +-
> > include/drm/drm_crtc.h | 2 --
> > include/drm/drm_crtc_helper.h | 1 +
> > 7 files changed, 39 insertions(+), 36 deletions(-)
> >
/snip
> > diff --git a/drivers/gpu/drm/drm_crtc_helper.c
> > b/drivers/gpu/drm/drm_crtc_helper.c
> > index a3c81850e755..23159eb494f1 100644
> > --- a/drivers/gpu/drm/drm_crtc_helper.c
> > +++ b/drivers/gpu/drm/drm_crtc_helper.c
> > @@ -984,3 +984,38 @@ void drm_helper_resume_force_mode(struct drm_device
> > *dev)
> > drm_modeset_unlock_all(dev);
> > }
> > EXPORT_SYMBOL(drm_helper_resume_force_mode);
> > +
> > +/**
> > + * drm_helper_force_disable_all - Forcibly turn off all enabled CRTCs
> > + * @dev: DRM device whose CRTCs to turn off
> > + *
> > + * Drivers may want to call this on unload to ensure that all displays are
> > + * unlit and the GPU is in a consistent, low power state. Takes modeset
> > locks.
> > + *
> > + * Note: This should only be used by non-atomic legacy drivers. For an
> > atomic
> > + * version look at drm_atomic_helper_shutdown().
> > + *
> > + * Returns:
> > + * Zero on success, error code on failure.
> > + */
> > +int drm_helper_force_disable_all(struct drm_device *dev)
>
> Maybe put crtc somewhere in the function name so it's clear what we
> are disabling.
FWIW, I think it's more clear this way. set_config_internal will turn off
everything attached to the crtc, so _everything_ will be disabled in this case.
Either way,
Reviewed-by: Sean Paul
Sean
> With that fixed:
> Reviewed-by: Alex Deucher
>
> > +{
> > + struct drm_crtc *crtc;
> > + int ret = 0;
> > +
> > + drm_modeset_lock_all(dev);
> > + drm_for_each_crtc(crtc, dev)
> > + if (crtc->enabled) {
> > + struct drm_mode_set set = {
> > + .crtc = crtc,
> > + };
> > +
> > + ret = drm_mode_set_config_internal();
> > + if (ret)
> > + goto out;
> > + }
> > +out:
> > + drm_modeset_unlock_all(dev);
> > + return ret;
> > +}
> > +EXPORT_SYMBOL(drm_helper_force_disable_all);
> > diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c
> > b/drivers/gpu/drm/nouveau/nouveau_display.c
> > index f326ffd86766..5d273a655479 100644
> > --- a/drivers/gpu/drm/nouveau/nouveau_display.c
> > +++ b/drivers/gpu/drm/nouveau/nouveau_display.c
> > @@ -453,7 +453,7 @@ nouveau_display_fini(struct drm_device *dev, bool
> > suspend, bool runtime)
> > if (drm_drv_uses_atomic_modeset(dev))
> > drm_atomic_helper_shutdown(dev);
> > else
> > - drm_crtc_force_disable_all(dev);
> > + drm_helper_force_disable_all(dev);
> > }
> >
> > /* disable flip completion events */
> > diff --git a/drivers/gpu/drm/radeon/radeon_display.c
> > b/drivers/gpu/drm/radeon/radeon_display.c
> > index e6912eb99b42..92332226e5cf 100644
> > --- a/drivers/gpu/drm/radeon/radeon_display.c
> > +++ b/drivers/gpu/drm/radeon/radeon_display.c
> > @@ -1643,7 +1643,7 @@ void radeon_modeset_fini(struct radeon_device *rdev)
> > if (rdev->mode_info.mode_config_initialized) {
> > drm_kms_helper_poll_fini(rdev->ddev);
> > radeon_hpd_fini(rdev);
> > - drm_crtc_force_disable_all(rdev->ddev);
> > + drm_helper_force_disable_all(rdev->ddev);
> > radeon_fbdev_fini(rdev);
> > radeon_afmt_fini(rdev);
> > drm_mode_config_cleanup(rdev->ddev);
> > diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
> > index b45bec0b7a9c..85abd3fe9e83 100644
> > --- a/include/drm/drm_crtc.h
> > +++ b/include/drm/drm_crtc.h
> > @@ -1149,8 +1149,6 @@ static inline uint32_t drm_crtc_mask(const struct
> > drm_crtc
Re: [Intel-gfx] linux-firmware PR for BXT HUC
Hi, Can these changes be merged from branch BXT_HUC to linux_fir,ware.git? Anusha From: Srivatsa, Anusha Sent: Friday, December 7, 2018 2:14 PM To: jwbo...@kernel.org; k...@kernel.org; b...@decadent.org.uk Cc: intel-gfx@lists.freedesktop.org; Vivi, Rodrigo Subject: linux-firmware PR for BXT HUC Hi Josh, Kyle, Ben, Kindly add the below i915 changes to linux-firmware.git- The following changes since commit 1baa34868b2c0a004dc595b20678145e3fff83e7: Merge branch 'nxp_mc' of https://github.com/NXP/linux-firmware (2018-10-26 08:13:19 -0400) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-firmware BXT_HUC for you to fetch changes up to 69f153bbc2c44eb581c1f8c7cecd4d878e4e727a: firmware/huc/bxt: Add huC Update for BXT (2018-11-28 10:33:57 -0800) Anusha Srivatsa (1): firmware/huc/bxt: Add huC Update for BXT WHENCE| 3 +++ i915/bxt_huc_ver01_8_2893.bin | Bin 0 -> 146880 bytes 2 files changed, 3 insertions(+) create mode 100644 i915/bxt_huc_ver01_8_2893.bin Thanks, Anusha ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 3/3] drm/i915: merge gen checks to use range
On Wed, 05 Dec 2018, Lucas De Marchi wrote:
> Instead of using IS_GEN() for consecutive gen checks, let's pass the
> range to IS_GEN_RANGE(). By code inspection these were the ranges deemed
> necessary for spatch:
>
> @@
> expression e;
> @@
> (
> - IS_GEN(e, 3) || IS_GEN(e, 2)
> + IS_GEN_RANGE(e, 2, 3)
> |
> - IS_GEN(e, 3) || IS_GEN(e, 4)
> + IS_GEN_RANGE(e, 3, 4)
> |
> - IS_GEN(e, 5) || IS_GEN(e, 6)
> + IS_GEN_RANGE(e, 5, 6)
> |
> - IS_GEN(e, 6) || IS_GEN(e, 7)
> + IS_GEN_RANGE(e, 6, 7)
> |
> - IS_GEN(e, 7) || IS_GEN(e, 8)
> + IS_GEN_RANGE(e, 7, 8)
> |
> - IS_GEN(e, 8) || IS_GEN(e, 9)
> + IS_GEN_RANGE(e, 8, 9)
> |
> - IS_GEN(e, 10) || IS_GEN(e, 9)
> + IS_GEN_RANGE(e, 9, 10)
> |
> - IS_GEN(e, 9) || IS_GEN(e, 10)
> + IS_GEN_RANGE(e, 9, 10)
> )
>
> After conversion, checking we don't have any missing IS_GEN_RANGE() ||
> IS_GEN() was also done.
>
> Signed-off-by: Lucas De Marchi
Should've just looked at the whole series before commenting on the
others. It's all
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_debugfs.c| 6 +++---
> drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
> drivers/gpu/drm/i915/i915_perf.c | 2 +-
> drivers/gpu/drm/i915/intel_crt.c | 2 +-
> drivers/gpu/drm/i915/intel_device_info.c | 2 +-
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
> drivers/gpu/drm/i915/intel_fifo_underrun.c | 2 +-
> drivers/gpu/drm/i915/intel_pipe_crc.c | 4 ++--
> drivers/gpu/drm/i915/intel_uncore.c| 6 +++---
> 10 files changed, 15 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 53e3f57a13f3..33ff75c6a4a3 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2034,7 +2034,7 @@ static int i915_swizzle_info(struct seq_file *m, void
> *data)
> seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
> swizzle_string(dev_priv->mm.bit_6_swizzle_y));
>
> - if (IS_GEN(dev_priv, 3) || IS_GEN(dev_priv, 4)) {
> + if (IS_GEN_RANGE(dev_priv, 3, 4)) {
> seq_printf(m, "DDC = 0x%08x\n",
> I915_READ(DCC));
> seq_printf(m, "DDC2 = 0x%08x\n",
> @@ -4268,7 +4268,7 @@ i915_cache_sharing_get(void *data, u64 *val)
> struct drm_i915_private *dev_priv = data;
> u32 snpcr;
>
> - if (!(IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)))
> + if (!(IS_GEN_RANGE(dev_priv, 6, 7)))
> return -ENODEV;
>
> intel_runtime_pm_get(dev_priv);
> @@ -4288,7 +4288,7 @@ i915_cache_sharing_set(void *data, u64 val)
> struct drm_i915_private *dev_priv = data;
> u32 snpcr;
>
> - if (!(IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)))
> + if (!(IS_GEN_RANGE(dev_priv, 6, 7)))
> return -ENODEV;
>
> if (val > 3)
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
> b/drivers/gpu/drm/i915/i915_gpu_error.c
> index ccfd91c72477..581a40ac3591 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -1753,7 +1753,7 @@ static void capture_reg_state(struct i915_gpu_state
> *error)
> error->ccid = I915_READ(CCID);
>
> /* 3: Feature specific registers */
> - if (IS_GEN(dev_priv, 6) || IS_GEN(dev_priv, 7)) {
> + if (IS_GEN_RANGE(dev_priv, 6, 7)) {
> error->gam_ecochk = I915_READ(GAM_ECOCHK);
> error->gac_eco = I915_READ(GAC_ECO_BITS);
> }
> diff --git a/drivers/gpu/drm/i915/i915_perf.c
> b/drivers/gpu/drm/i915/i915_perf.c
> index 6c7992320443..4288c0e02f0c 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -3415,7 +3415,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
> dev_priv->perf.oa.ops.read = gen8_oa_read;
> dev_priv->perf.oa.ops.oa_hw_tail_read = gen8_oa_hw_tail_read;
>
> - if (IS_GEN(dev_priv, 8) || IS_GEN(dev_priv, 9)) {
> + if (IS_GEN_RANGE(dev_priv, 8, 9)) {
> dev_priv->perf.oa.ops.is_valid_b_counter_reg =
> gen7_is_valid_b_counter_addr;
> dev_priv->perf.oa.ops.is_valid_mux_reg =
> diff --git a/drivers/gpu/drm/i915/intel_crt.c
> b/drivers/gpu/drm/i915/intel_crt.c
> index bf4fd739b68c..0a41e58d61de 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -322,7 +322,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
>* DAC limit supposedly 355 MHz.
>*/
> max_clock = 27;
> - else if (IS_GEN(dev_priv, 3) || IS_GEN(dev_priv, 4))
> + else if (IS_GEN_RANGE(dev_priv, 3, 4))
> max_clock = 40;
> else
> max_clock = 35;
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> b/drivers/gpu/drm/i915/intel_device_info.c
> index
Re: [Intel-gfx] [PATCH v3 2/3] drm/i915: replace IS_GEN with IS_GEN(..., N)
On Wed, 05 Dec 2018, Lucas De Marchi wrote: > Define IS_GEN() similarly to our IS_GEN_RANGE(). but use gen instead of > gen_mask to do the comparison. Now callers can pass then gen as a parameter, > so we don't require one macro for each gen. > > The following spatch was used to convert the users of these macros: > > @@ > expression e; > @@ > ( > - IS_GEN2(e) > + IS_GEN(e, 2) > | > - IS_GEN3(e) > + IS_GEN(e, 3) > | > - IS_GEN4(e) > + IS_GEN(e, 4) > | > - IS_GEN5(e) > + IS_GEN(e, 5) > | > - IS_GEN6(e) > + IS_GEN(e, 6) > | > - IS_GEN7(e) > + IS_GEN(e, 7) > | > - IS_GEN8(e) > + IS_GEN(e, 8) > | > - IS_GEN9(e) > + IS_GEN(e, 9) > | > - IS_GEN10(e) > + IS_GEN(e, 10) > | > - IS_GEN11(e) > + IS_GEN(e, 11) > ) > > v2: use IS_GEN rather than GT_GEN and compare to info.gen rather than > using the bitmask > > Signed-off-by: Lucas De Marchi I think the discussion on the IS_GEN() definition is slightly irrelevant here, as this lets use trivially change it. There's some potential follow-up work to change some of the IS_GEN(n) || IS_GEN(n + 1) uses to IS_GEN_RANGE(n, n + 1). Anyway, I think this is the direction to go to, as the IS_GEN macros are getting a bit tedious. Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/gvt/vgpu.c| 4 +- > drivers/gpu/drm/i915/i915_cmd_parser.c | 2 +- > drivers/gpu/drm/i915/i915_debugfs.c| 16 ++--- > drivers/gpu/drm/i915/i915_drv.c| 18 +++--- > drivers/gpu/drm/i915/i915_drv.h| 29 +++-- > drivers/gpu/drm/i915/i915_gem.c| 14 ++-- > drivers/gpu/drm/i915/i915_gem_context.c| 2 +- > drivers/gpu/drm/i915/i915_gem_execbuffer.c | 4 +- > drivers/gpu/drm/i915/i915_gem_fence_reg.c | 10 +-- > drivers/gpu/drm/i915/i915_gem_gtt.c| 6 +- > drivers/gpu/drm/i915/i915_gem_stolen.c | 7 +- > drivers/gpu/drm/i915/i915_gem_tiling.c | 4 +- > drivers/gpu/drm/i915/i915_gpu_error.c | 18 +++--- > drivers/gpu/drm/i915/i915_irq.c| 24 +++ > drivers/gpu/drm/i915/i915_perf.c | 4 +- > drivers/gpu/drm/i915/i915_suspend.c| 12 ++-- > drivers/gpu/drm/i915/intel_atomic.c| 2 +- > drivers/gpu/drm/i915/intel_audio.c | 2 +- > drivers/gpu/drm/i915/intel_cdclk.c | 10 +-- > drivers/gpu/drm/i915/intel_crt.c | 6 +- > drivers/gpu/drm/i915/intel_device_info.c | 16 ++--- > drivers/gpu/drm/i915/intel_display.c | 74 +++--- > drivers/gpu/drm/i915/intel_dp.c| 24 +++ > drivers/gpu/drm/i915/intel_engine_cs.c | 4 +- > drivers/gpu/drm/i915/intel_fbc.c | 22 +++ > drivers/gpu/drm/i915/intel_fifo_underrun.c | 6 +- > drivers/gpu/drm/i915/intel_guc_fw.c| 2 +- > drivers/gpu/drm/i915/intel_hangcheck.c | 2 +- > drivers/gpu/drm/i915/intel_lrc.c | 4 +- > drivers/gpu/drm/i915/intel_lvds.c | 4 +- > drivers/gpu/drm/i915/intel_mocs.c | 2 +- > drivers/gpu/drm/i915/intel_overlay.c | 10 +-- > drivers/gpu/drm/i915/intel_panel.c | 8 +-- > drivers/gpu/drm/i915/intel_pipe_crc.c | 8 +-- > drivers/gpu/drm/i915/intel_pm.c| 60 +- > drivers/gpu/drm/i915/intel_psr.c | 4 +- > drivers/gpu/drm/i915/intel_ringbuffer.c| 28 > drivers/gpu/drm/i915/intel_ringbuffer.h| 4 +- > drivers/gpu/drm/i915/intel_runtime_pm.c| 4 +- > drivers/gpu/drm/i915/intel_sprite.c| 6 +- > drivers/gpu/drm/i915/intel_uc.c| 2 +- > drivers/gpu/drm/i915/intel_uncore.c| 18 +++--- > drivers/gpu/drm/i915/intel_wopcm.c | 4 +- > drivers/gpu/drm/i915/intel_workarounds.c | 4 +- > 44 files changed, 251 insertions(+), 263 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c > index c628be05fbfe..e1c860f80eb0 100644 > --- a/drivers/gpu/drm/i915/gvt/vgpu.c > +++ b/drivers/gpu/drm/i915/gvt/vgpu.c > @@ -148,10 +148,10 @@ int intel_gvt_init_vgpu_types(struct intel_gvt *gvt) > gvt->types[i].avail_instance = min(low_avail / > vgpu_types[i].low_mm, > high_avail / > vgpu_types[i].high_mm); > > - if (IS_GEN8(gvt->dev_priv)) > + if (IS_GEN(gvt->dev_priv, 8)) > sprintf(gvt->types[i].name, "GVTg_V4_%s", > vgpu_types[i].name); > - else if (IS_GEN9(gvt->dev_priv)) > + else if (IS_GEN(gvt->dev_priv, 9)) > sprintf(gvt->types[i].name, "GVTg_V5_%s", > vgpu_types[i].name); > > diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c > b/drivers/gpu/drm/i915/i915_cmd_parser.c > index 95478db9998b..33e8eed64423 100644 > --- a/drivers/gpu/drm/i915/i915_cmd_parser.c > +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c > @@ -865,7 +865,7 @@ void intel_engine_init_cmd_parser(struct intel_engine_cs > *engine) >
Re: [Intel-gfx] [PATCH v3] /drm/i915/hdmi: SCDC Scrambling enable without CTS mode
On Mon, Dec 10, 2018 at 02:52:54PM -0800, clinton.a.tay...@intel.com wrote:
> From: Clint Taylor
>
> Setting the SCDC scrambling CTS mode causes HDMI Link Layer protocol tests
> HF1-12 and HF1-13 to fail.
>
> V2: Removed "Source Shall" entries to a new patch
> V3: Rebase to drm-tip
> Cc: Ville Syrjälä
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107895
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107896
> Signed-off-by: Clint Taylor
Thanks for the patch. Pushed to dinq.
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index f3e1d6a..92c0bf7 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1880,7 +1880,7 @@ void intel_ddi_enable_transcoder_func(const struct
> intel_crtc_state *crtc_state)
> temp |= TRANS_DDI_MODE_SELECT_DVI;
>
> if (crtc_state->hdmi_scrambling)
> - temp |= TRANS_DDI_HDMI_SCRAMBLING_MASK;
> + temp |= TRANS_DDI_HDMI_SCRAMBLING;
> if (crtc_state->hdmi_high_tmds_clock_ratio)
> temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
> } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
> @@ -3793,8 +3793,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> if (intel_dig_port->infoframe_enabled(encoder, pipe_config))
> pipe_config->has_infoframe = true;
>
> - if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) ==
> - TRANS_DDI_HDMI_SCRAMBLING_MASK)
> + if (temp & TRANS_DDI_HDMI_SCRAMBLING)
> pipe_config->hdmi_scrambling = true;
> if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
> pipe_config->hdmi_high_tmds_clock_ratio = true;
> --
> 1.9.1
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v3] drm/i915/icl: combo port vswing programming changes per BSPEC
On Tue, Dec 11, 2018 at 04:18:47PM +0200, Ville Syrjälä wrote:
> On Tue, Dec 11, 2018 at 11:40:43AM +0200, Imre Deak wrote:
> > On Wed, Dec 05, 2018 at 06:32:22PM +0200, Imre Deak wrote:
> > > On Tue, Dec 04, 2018 at 03:41:09PM -0800, clinton.a.tay...@intel.com
> > > wrote:
> > > > From: Clint Taylor
> > > >
> > > > In August 2018 the BSPEC changed the ICL port programming sequence to
> > > > closely resemble earlier gen programming sequence.
> > > >
> > > > v2: remove debug code that Imre found
> > > > v3: simplify translation table if-else
> > > >
> > > > BSpec: 21257
> > > > Cc: Ville Syrjälä
> > > > Cc: Imre Deak
> > > > Cc: Rodrigo Vivi
> > > > Signed-off-by: Clint Taylor
> > > > ---
> > > > drivers/gpu/drm/i915/i915_reg.h | 4 +
> > > > drivers/gpu/drm/i915/intel_ddi.c | 224
> > > > ++-
> > > > 2 files changed, 85 insertions(+), 143 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > > b/drivers/gpu/drm/i915/i915_reg.h
> > > > index 0a7d605..29acdb9 100644
> > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > @@ -1866,6 +1866,10 @@ enum i915_power_well_id {
> > > >
> > > > #define CNL_PORT_TX_DW7_GRP(port)
> > > > _MMIO(_CNL_PORT_TX_DW_GRP((port), 7))
> > > > #define CNL_PORT_TX_DW7_LN0(port)
> > > > _MMIO(_CNL_PORT_TX_DW_LN0((port), 7))
> > > > +#define ICL_PORT_TX_DW7_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(7,
> > > > port))
> > > > +#define ICL_PORT_TX_DW7_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(7,
> > > > port))
> > > > +#define ICL_PORT_TX_DW7_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(7, 0,
> > > > port))
> > > > +#define ICL_PORT_TX_DW7_LN(port, ln) _MMIO(_ICL_PORT_TX_DW_LN(7, ln,
> > > > port))
> > >
> > > Looks like _CNL_PORT_TX_DW_GRP() is inconsistent with the ICL
> > > counterpart and CNL_PORT_TX_DW2_* / CNL_PORT_TX_DW5_* are broken atm,
> > > they need to be fixed as a follow-up.
> > >
> > > > #define N_SCALAR(x) ((x) << 24)
> > > > #define N_SCALAR_MASK(0x7F << 24)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > > > b/drivers/gpu/drm/i915/intel_ddi.c
> > > > index f3e1d6a..d78ec17 100644
> > > > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > > > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > > > @@ -494,103 +494,63 @@ struct cnl_ddi_buf_trans {
> > > > { 0x2, 0x7F, 0x3F, 0x00, 0x00 },/* 400 400 0.0
> > > > */
> > > > };
> > > >
> > > > -struct icl_combo_phy_ddi_buf_trans {
> > > > - u32 dw2_swing_select;
> > > > - u32 dw2_swing_scalar;
> > > > - u32 dw4_scaling;
> > > > -};
> > > > -
> > > > -/* Voltage Swing Programming for VccIO 0.85V for DP */
> > > > -static const struct icl_combo_phy_ddi_buf_trans
> > > > icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = {
> > > > - /* Voltage mV db*/
> > > > - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
> > > > - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
> > > > - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
> > > > - { 0x2, 0x98, 0x900F }, /* 400 9.5 */
> > > > - { 0xB, 0x70, 0x0018 }, /* 600 0.0 */
> > > > - { 0xB, 0x70, 0x3015 }, /* 600 3.5 */
> > > > - { 0xB, 0x70, 0x6012 }, /* 600 6.0 */
> > > > - { 0x5, 0x00, 0x0018 }, /* 800 0.0 */
> > > > - { 0x5, 0x00, 0x3015 }, /* 800 3.5 */
> > > > - { 0x6, 0x98, 0x0018 }, /* 12000.0 */
> > > > -};
> > > > -
> > > > -/* FIXME - After table is updated in Bspec */
> > > > -/* Voltage Swing Programming for VccIO 0.85V for eDP */
> > > > -static const struct icl_combo_phy_ddi_buf_trans
> > > > icl_combo_phy_ddi_translations_edp_0_85V[] = {
> > > > - /* Voltage mV db*/
> > > > - { 0x0, 0x00, 0x00 },/* 200 0.0 */
> > > > - { 0x0, 0x00, 0x00 },/* 200 1.5 */
> > > > - { 0x0, 0x00, 0x00 },/* 200 4.0 */
> > > > - { 0x0, 0x00, 0x00 },/* 200 6.0 */
> > > > - { 0x0, 0x00, 0x00 },/* 250 0.0 */
> > > > - { 0x0, 0x00, 0x00 },/* 250 1.5 */
> > > > - { 0x0, 0x00, 0x00 },/* 250 4.0 */
> > > > - { 0x0, 0x00, 0x00 },/* 300 0.0 */
> > > > - { 0x0, 0x00, 0x00 },/* 300 1.5 */
> > > > - { 0x0, 0x00, 0x00 },/* 350 0.0 */
> > > > +/* icl_combo_phy_ddi_translations */
> > > > +static const struct cnl_ddi_buf_trans
> > > > icl_combo_phy_ddi_translations_dp[] = {
> > > > + /* NT mV Trans mV db
> > > > */
> > > > + { 0xA, 0x35, 0x3F, 0x00, 0x00 },/* 350 350 0.0
> > > > */
> > > > + { 0xA, 0x4F, 0x37, 0x00, 0x08 },/* 350 500 3.1
> > > > */
> > > > + { 0xC, 0x71,
