[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Call i915_sw_fence_fini on request cleanup
== Series Details == Series: drm/i915: Call i915_sw_fence_fini on request cleanup URL : https://patchwork.freedesktop.org/series/59340/ State : success == Summary == CI Bug Log - changes from CI_DRM_5913_full -> Patchwork_12763_full Summary --- **WARNING** Minor unknown changes coming with Patchwork_12763_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12763_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12763_full: ### IGT changes ### Warnings * igt@gem_tiled_swapping@non-threaded: - shard-iclb: FAIL [fdo#108686] -> INCOMPLETE Known issues Here are the changes found in Patchwork_12763_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_params@rsvd2-dirt: - shard-iclb: NOTRUN -> SKIP [fdo#109283] * igt@gem_pwrite@huge-gtt-random: - shard-iclb: NOTRUN -> SKIP [fdo#109290] * igt@gem_pwrite@stolen-uncached: - shard-iclb: NOTRUN -> SKIP [fdo#109277] * igt@i915_pm_rc6_residency@rc6-accuracy: - shard-kbl: PASS -> SKIP [fdo#109271] * igt@i915_pm_rpm@modeset-non-lpsp-stress: - shard-iclb: NOTRUN -> SKIP [fdo#109308] * igt@i915_selftest@live_workarounds: - shard-iclb: PASS -> DMESG-FAIL [fdo#108954] * igt@i915_suspend@debugfs-reader: - shard-apl: PASS -> DMESG-WARN [fdo#108566] +2 * igt@kms_busy@extended-modeset-hang-oldfb-render-f: - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +12 * igt@kms_chamelium@hdmi-cmp-nv21: - shard-iclb: NOTRUN -> SKIP [fdo#109284] +1 * igt@kms_content_protection@legacy: - shard-iclb: NOTRUN -> SKIP [fdo#109300] * igt@kms_cursor_crc@cursor-512x170-offscreen: - shard-iclb: NOTRUN -> SKIP [fdo#109279] * igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic: - shard-glk: PASS -> FAIL [fdo#106509] / [fdo#107409] * igt@kms_fbcon_fbt@fbc-suspend: - shard-skl: PASS -> INCOMPLETE [fdo#104108] * igt@kms_flip@2x-plain-flip-ts-check-interruptible: - shard-iclb: NOTRUN -> SKIP [fdo#109274] +3 * igt@kms_flip@flip-vs-suspend-interruptible: - shard-skl: PASS -> INCOMPLETE [fdo#109507] - shard-kbl: PASS -> DMESG-WARN [fdo#108566] +1 * igt@kms_frontbuffer_tracking@fbc-2p-indfb-fliptrack: - shard-iclb: NOTRUN -> SKIP [fdo#109280] +9 * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt: - shard-skl: NOTRUN -> SKIP [fdo#109271] +133 * igt@kms_frontbuffer_tracking@fbcpsr-tilingchange: - shard-iclb: PASS -> FAIL [fdo#103167] +7 * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-blt: - shard-iclb: PASS -> FAIL [fdo#109247] +14 * igt@kms_lease@atomic_implicit_crtc: - shard-skl: NOTRUN -> FAIL [fdo#110279] * igt@kms_lease@cursor_implicit_plane: - shard-skl: NOTRUN -> FAIL [fdo#110278] * igt@kms_lease@setcrtc_implicit_plane: - shard-skl: NOTRUN -> FAIL [fdo#110281] - shard-iclb: NOTRUN -> FAIL [fdo#110281] * igt@kms_plane@pixel-format-pipe-a-planes: - shard-glk: PASS -> SKIP [fdo#109271] * igt@kms_plane_alpha_blend@pipe-a-alpha-basic: - shard-skl: NOTRUN -> FAIL [fdo#108145] +1 * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: NOTRUN -> FAIL [fdo#110403] * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: PASS -> FAIL [fdo#108145] * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: PASS -> FAIL [fdo#110403] * igt@kms_plane_lowres@pipe-a-tiling-x: - shard-iclb: PASS -> FAIL [fdo#103166] +1 * igt@kms_plane_scaling@pipe-c-scaler-with-rotation: - shard-glk: PASS -> SKIP [fdo#109271] / [fdo#109278] - shard-iclb: NOTRUN -> FAIL [fdo#109052] * igt@kms_psr2_su@page_flip: - shard-iclb: PASS -> SKIP [fdo#109642] * igt@kms_psr@psr2_cursor_plane_onoff: - shard-iclb: PASS -> SKIP [fdo#109441] +1 * igt@kms_psr@psr2_dpms: - shard-iclb: NOTRUN -> SKIP [fdo#109441] +2 * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0: - shard-iclb: PASS -> INCOMPLETE [fdo#110026] / [fdo#110040 ] * igt@kms_setmode@basic: - shard-skl: NOTRUN -> FAIL [fdo#99912] * igt@kms_sysfs_edid_timing: - shard-iclb: PASS -> FAIL [fdo#100047] - shard-skl: NOTRUN -> FAIL [fdo#100047] * igt@kms_universal_plane@cursor-fb-leak-pipe-e: - shard-iclb: NOTRUN -> SKIP
[Intel-gfx] ✓ Fi.CI.IGT: success for GuC 32.0.3 (rev2)
== Series Details == Series: GuC 32.0.3 (rev2) URL : https://patchwork.freedesktop.org/series/58760/ State : success == Summary == CI Bug Log - changes from CI_DRM_5913_full -> Patchwork_12762_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_12762_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_params@rsvd2-dirt: - shard-iclb: NOTRUN -> SKIP [fdo#109283] * igt@gem_pwrite@stolen-uncached: - shard-iclb: NOTRUN -> SKIP [fdo#109277] * igt@i915_pm_rc6_residency@rc6-accuracy: - shard-kbl: PASS -> SKIP [fdo#109271] * igt@i915_pm_rpm@modeset-non-lpsp-stress: - shard-iclb: NOTRUN -> SKIP [fdo#109308] * igt@i915_suspend@debugfs-reader: - shard-apl: PASS -> DMESG-WARN [fdo#108566] +3 * igt@kms_addfb_basic@size-max: - shard-apl: PASS -> INCOMPLETE [fdo#103927] * igt@kms_atomic_transition@1x-modeset-transitions-nonblocking: - shard-apl: PASS -> FAIL [fdo#109660] * igt@kms_busy@extended-modeset-hang-oldfb-render-f: - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +15 * igt@kms_chamelium@hdmi-cmp-nv21: - shard-iclb: NOTRUN -> SKIP [fdo#109284] +1 * igt@kms_content_protection@legacy: - shard-iclb: NOTRUN -> SKIP [fdo#109300] * igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled: - shard-skl: NOTRUN -> FAIL [fdo#103184] * igt@kms_flip@2x-plain-flip-ts-check-interruptible: - shard-iclb: NOTRUN -> SKIP [fdo#109274] +2 * igt@kms_flip@flip-vs-suspend-interruptible: - shard-kbl: PASS -> DMESG-WARN [fdo#108566] +2 * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt: - shard-iclb: NOTRUN -> FAIL [fdo#103167] * igt@kms_frontbuffer_tracking@fbc-2p-indfb-fliptrack: - shard-iclb: NOTRUN -> SKIP [fdo#109280] +7 * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt: - shard-skl: NOTRUN -> SKIP [fdo#109271] +151 * igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc: - shard-snb: PASS -> SKIP [fdo#109271] * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite: - shard-iclb: PASS -> FAIL [fdo#109247] +9 - shard-skl: NOTRUN -> FAIL [fdo#103167] * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite: - shard-iclb: PASS -> FAIL [fdo#103167] +5 * igt@kms_lease@atomic_implicit_crtc: - shard-skl: NOTRUN -> FAIL [fdo#110279] * igt@kms_lease@cursor_implicit_plane: - shard-skl: NOTRUN -> FAIL [fdo#110278] * igt@kms_lease@setcrtc_implicit_plane: - shard-skl: NOTRUN -> FAIL [fdo#110281] - shard-iclb: NOTRUN -> FAIL [fdo#110281] * igt@kms_plane@pixel-format-pipe-a-planes: - shard-glk: PASS -> SKIP [fdo#109271] * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc: - shard-skl: NOTRUN -> FAIL [fdo#108145] +2 * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: NOTRUN -> FAIL [fdo#110403] * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: PASS -> FAIL [fdo#108145] * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: PASS -> FAIL [fdo#110403] * igt@kms_plane_lowres@pipe-a-tiling-x: - shard-iclb: PASS -> FAIL [fdo#103166] * igt@kms_plane_scaling@pipe-c-scaler-with-rotation: - shard-glk: PASS -> SKIP [fdo#109271] / [fdo#109278] - shard-iclb: NOTRUN -> FAIL [fdo#109052] * igt@kms_psr2_su@page_flip: - shard-iclb: PASS -> SKIP [fdo#109642] * igt@kms_psr@no_drrs: - shard-iclb: PASS -> FAIL [fdo#108341] * igt@kms_psr@psr2_cursor_plane_onoff: - shard-iclb: PASS -> SKIP [fdo#109441] +2 * igt@kms_psr@psr2_primary_mmap_gtt: - shard-iclb: NOTRUN -> SKIP [fdo#109441] +1 * igt@kms_setmode@basic: - shard-skl: NOTRUN -> FAIL [fdo#99912] * igt@kms_universal_plane@cursor-fb-leak-pipe-e: - shard-iclb: NOTRUN -> SKIP [fdo#109278] +3 * igt@prime_busy@wait-after-bsd2: - shard-iclb: NOTRUN -> SKIP [fdo#109276] +2 * igt@prime_nv_api@nv_self_import_to_different_fd: - shard-iclb: NOTRUN -> SKIP [fdo#109291] * igt@prime_vgem@fence-flip-hang: - shard-iclb: NOTRUN -> SKIP [fdo#109295] * igt@v3d_mmap@mmap-bad-handle: - shard-iclb: NOTRUN -> SKIP [fdo#109315] Possible fixes * igt@gem_eio@reset-stress: - shard-snb: FAIL [fdo#109661] -> PASS * igt@gem_softpin@noreloc-s3: - shard-kbl: DMESG-WARN [fdo#108566] -> PASS +3 * igt@gem_workarounds@suspend-resume-context: - shard-apl: DMESG-WARN [fdo#108566] -> PASS +4
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/ehl: Add support for DPLL4 (v3) (rev2)
== Series Details == Series: drm/i915/ehl: Add support for DPLL4 (v3) (rev2) URL : https://patchwork.freedesktop.org/series/59078/ State : success == Summary == CI Bug Log - changes from CI_DRM_5917 -> Patchwork_12771 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/59078/revisions/2/mbox/ Known issues Here are the changes found in Patchwork_12771 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_basic@gtt-bsd2: - fi-byt-clapper: NOTRUN -> SKIP [fdo#109271] +52 * igt@gem_exec_basic@readonly-bsd1: - fi-snb-2520m: NOTRUN -> SKIP [fdo#109271] +52 * igt@gem_exec_store@basic-bsd2: - fi-hsw-4770:NOTRUN -> SKIP [fdo#109271] +41 * igt@kms_busy@basic-flip-c: - fi-byt-clapper: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-snb-2520m: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_frontbuffer_tracking@basic: - fi-byt-clapper: NOTRUN -> FAIL [fdo#103167] Possible fixes * igt@i915_selftest@live_contexts: - fi-bdw-gvtdvm: DMESG-FAIL [fdo#110235 ] -> PASS * igt@i915_selftest@live_hangcheck: - fi-icl-y: INCOMPLETE [fdo#108569] -> PASS [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#110235 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110235 Participating hosts (47 -> 42) -- Additional (3): fi-hsw-4770 fi-byt-clapper fi-snb-2520m Missing(8): fi-kbl-soraka fi-hsw-4200u fi-byt-j1900 fi-bsw-n3050 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus Build changes - * Linux: CI_DRM_5917 -> Patchwork_12771 CI_DRM_5917: b01c0e68e8d1092c436dbba4d03b260c828f37c9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4944: 9b74b8226e8c108db091bd3b1d105a71dc0fb861 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12771: aad97f450c0946316db4497022256b0b37633c6f @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == aad97f450c09 drm/i915/ehl: Add support for DPLL4 (v4) == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12771/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/ehl: Inherit Ice Lake conditional code
== Series Details == Series: drm/i915/ehl: Inherit Ice Lake conditional code URL : https://patchwork.freedesktop.org/series/59364/ State : success == Summary == CI Bug Log - changes from CI_DRM_5917 -> Patchwork_12770 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/59364/revisions/1/mbox/ Known issues Here are the changes found in Patchwork_12770 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_basic@gtt-bsd2: - fi-byt-clapper: NOTRUN -> SKIP [fdo#109271] +52 * igt@gem_exec_basic@readonly-bsd1: - fi-snb-2520m: NOTRUN -> SKIP [fdo#109271] +52 * igt@gem_exec_store@basic-bsd2: - fi-hsw-4770:NOTRUN -> SKIP [fdo#109271] +41 * igt@i915_selftest@live_evict: - fi-bsw-kefka: PASS -> DMESG-WARN [fdo#107709] * igt@kms_busy@basic-flip-c: - fi-byt-clapper: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-snb-2520m: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_pipe_crc_basic@hang-read-crc-pipe-a: - fi-byt-clapper: NOTRUN -> FAIL [fdo#103191] * igt@runner@aborted: - fi-bsw-kefka: NOTRUN -> FAIL [fdo#107709] Possible fixes * igt@i915_selftest@live_contexts: - fi-bdw-gvtdvm: DMESG-FAIL [fdo#110235 ] -> PASS * igt@i915_selftest@live_hangcheck: - fi-icl-y: INCOMPLETE [fdo#108569] -> PASS [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#107709]: https://bugs.freedesktop.org/show_bug.cgi?id=107709 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#110235 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110235 Participating hosts (47 -> 42) -- Additional (3): fi-hsw-4770 fi-byt-clapper fi-snb-2520m Missing(8): fi-kbl-soraka fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-guc fi-ctg-p8600 fi-whl-u fi-bdw-samus Build changes - * Linux: CI_DRM_5917 -> Patchwork_12770 CI_DRM_5917: b01c0e68e8d1092c436dbba4d03b260c828f37c9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4944: 9b74b8226e8c108db091bd3b1d105a71dc0fb861 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12770: c187b9fb7d35b64361cd432dddb89a5a295c6b66 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c187b9fb7d35 drm/i915/ehl: Inherit Ice Lake conditional code == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12770/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Nuke drm_crtc_state and use intel_atomic_state instead
== Series Details == Series: drm/i915: Nuke drm_crtc_state and use intel_atomic_state instead URL : https://patchwork.freedesktop.org/series/59363/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5917 -> Patchwork_12769 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12769 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12769, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/59363/revisions/1/mbox/ Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12769: ### IGT changes ### Possible regressions * igt@gem_busy@basic-busy-default: - fi-icl-y: PASS -> INCOMPLETE Known issues Here are the changes found in Patchwork_12769 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_basic@gtt-bsd2: - fi-byt-clapper: NOTRUN -> SKIP [fdo#109271] +52 * igt@gem_exec_basic@readonly-bsd1: - fi-snb-2520m: NOTRUN -> SKIP [fdo#109271] +52 * igt@gem_exec_store@basic-bsd2: - fi-hsw-4770:NOTRUN -> SKIP [fdo#109271] +41 * igt@i915_module_load@reload: - fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718] * igt@kms_busy@basic-flip-c: - fi-byt-clapper: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-snb-2520m: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_frontbuffer_tracking@basic: - fi-byt-clapper: NOTRUN -> FAIL [fdo#103167] Possible fixes * igt@i915_selftest@live_execlists: - fi-apl-guc: INCOMPLETE [fdo#103927] / [fdo#109720] -> PASS [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720 Participating hosts (47 -> 43) -- Additional (3): fi-hsw-4770 fi-byt-clapper fi-snb-2520m Missing(7): fi-kbl-soraka fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-gdg-551 fi-bdw-samus Build changes - * Linux: CI_DRM_5917 -> Patchwork_12769 CI_DRM_5917: b01c0e68e8d1092c436dbba4d03b260c828f37c9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4944: 9b74b8226e8c108db091bd3b1d105a71dc0fb861 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12769: ca70ec970e00607d2b759e098067b1a6b1b567ee @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ca70ec970e00 drm/i915: Nuke drm_crtc_state and use intel_atomic_state instead == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12769/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Don't call bxt_ddi_phy_calc_lane_lat_optim_mask() after failing intel_dp_compute_config() (rev2)
== Series Details == Series: drm/i915: Don't call bxt_ddi_phy_calc_lane_lat_optim_mask() after failing intel_dp_compute_config() (rev2) URL : https://patchwork.freedesktop.org/series/59351/ State : success == Summary == CI Bug Log - changes from CI_DRM_5917 -> Patchwork_12768 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/59351/revisions/2/mbox/ Known issues Here are the changes found in Patchwork_12768 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_basic@gtt-bsd2: - fi-byt-clapper: NOTRUN -> SKIP [fdo#109271] +52 * igt@gem_exec_basic@readonly-bsd1: - fi-snb-2520m: NOTRUN -> SKIP [fdo#109271] +52 * igt@gem_exec_store@basic-bsd2: - fi-hsw-4770:NOTRUN -> SKIP [fdo#109271] +41 * igt@i915_module_load@reload: - fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718] * igt@kms_busy@basic-flip-c: - fi-byt-clapper: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-snb-2520m: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_frontbuffer_tracking@basic: - fi-byt-clapper: NOTRUN -> FAIL [fdo#103167] * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-byt-clapper: NOTRUN -> FAIL [fdo#103191] +1 Possible fixes * igt@i915_selftest@live_contexts: - fi-bdw-gvtdvm: DMESG-FAIL [fdo#110235 ] -> PASS * igt@i915_selftest@live_execlists: - fi-apl-guc: INCOMPLETE [fdo#103927] / [fdo#109720] -> PASS * igt@i915_selftest@live_hangcheck: - fi-icl-y: INCOMPLETE [fdo#108569] -> PASS [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720 [fdo#110235 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110235 Participating hosts (47 -> 44) -- Additional (3): fi-hsw-4770 fi-byt-clapper fi-snb-2520m Missing(6): fi-kbl-soraka fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus Build changes - * Linux: CI_DRM_5917 -> Patchwork_12768 CI_DRM_5917: b01c0e68e8d1092c436dbba4d03b260c828f37c9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4944: 9b74b8226e8c108db091bd3b1d105a71dc0fb861 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12768: 0330b8c0daa984c2131ab495358d6cad7126d8f0 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 0330b8c0daa9 drm/i915: Restore correct bxt_ddi_phy_calc_lane_lat_optim_mask() calculation == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12768/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 19/22] drm/i915/guc: Enable GuC CTB communication on Gen11
On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
Gen11 GuC firmware expects H2G command messages to be sent over CTB
(command transport buffers).
Even gen9 blobs can now use CTB, so we can just make the whole CTB
handling unconditional. I'm ok with doing that as a follow up as this
series already changes enough things as is.
Reviewed-by: Daniele Ceraolo Spurio
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: John Spotswood
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f893c2cbce15..8af8820b3df8 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -743,6 +743,7 @@ static const struct intel_device_info intel_cannonlake_info
= {
}, \
GEN(11), \
.ddb_size = 2048, \
+ .has_guc_ct = 1, \
.has_logical_ring_elsq = 1, \
.color = { .degamma_lut_size = 33, .gamma_lut_size = 1024 }
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PULL] drm-intel-fixes
Hi Dave and Daniel, Here goes drm-intel-fixes-2019-04-11: - Revert back to max link rate and lane count on eDP. - DSI related fixes for all platforms including Ice Lake. - GVT Fixes including one vGPU display plane size regression fix, one for preventing use-after-free in ppgtt shadow free function, and another warning fix for iomem access annotation. Thanks, Rodrigo. The following changes since commit 57cbec02f9b10992319ca578797c8059ac47d71e: Merge tag 'gvt-fixes-2019-04-04' of https://github.com/intel/gvt-linux into drm-intel-fixes (2019-04-03 18:00:42 -0700) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2019-04-11 for you to fetch changes up to 3f5f5d534bd40b666cf37bbeeb48bfe6c2efc1e0: Merge tag 'gvt-fixes-2019-04-11' of https://github.com/intel/gvt-linux into drm-intel-fixes (2019-04-11 09:18:14 -0700) - Revert back to max link rate and lane count on eDP. - DSI related fixes for all platforms including Ice Lake. - GVT Fixes including one vGPU display plane size regression fix, one for preventing use-after-free in ppgtt shadow free function, and another warning fix for iomem access annotation. Chris Wilson (2): drm/i915/gvt: Annotate iomem usage drm/i915/gvt: Prevent use-after-free in ppgtt_free_all_spt() Imre Deak (1): drm/i915: Get power refs in encoder->get_power_domains() Jani Nikula (1): drm/i915/dp: revert back to max link rate and lane count on eDP Rodrigo Vivi (1): Merge tag 'gvt-fixes-2019-04-11' of https://github.com/intel/gvt-linux into drm-intel-fixes Vandita Kulkarni (2): drm/i915/icl: Ungate ddi clocks before IO enable drm/i915/icl: Fix port disable sequence for mipi-dsi Ville Syrjälä (1): drm/i915: Fix pipe_bpp readout for BXT/GLK DSI Xiong Zhang (1): drm/i915/gvt: Roundup fb->height into tile's height at calucation fb->size drivers/gpu/drm/i915/gvt/dmabuf.c| 9 +++-- drivers/gpu/drm/i915/gvt/gtt.c | 12 +-- drivers/gpu/drm/i915/gvt/kvmgt.c | 6 ++-- drivers/gpu/drm/i915/icl_dsi.c | 48 ++--- drivers/gpu/drm/i915/intel_ddi.c | 23 ++-- drivers/gpu/drm/i915/intel_display.c | 6 +--- drivers/gpu/drm/i915/intel_dp.c | 69 ++-- drivers/gpu/drm/i915/intel_drv.h | 10 +++--- drivers/gpu/drm/i915/vlv_dsi.c | 24 + 9 files changed, 97 insertions(+), 110 deletions(-) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/ehl: Add support for DPLL4 (v4)
This patch adds support for DPLL4 on EHL that include the
following restrictions:
- DPLL4 cannot be used with DDIA (combo port A internal eDP usage).
DPLL4 can be used with other DDIs, including DDID
(combo port A external usage).
- DPLL4 cannot be enabled when DC5 or DC6 are enabled.
- The DPLL4 enable, lock, power enabled, and power state are connected
to the MGPLL1_ENABLE register.
v2: (suggestions from Bob Paauwe)
- Rework ehl_get_dpll() function to call intel_find_shared_dpll() and
iterate twice: once for Combo plls and once for MG plls.
- Use MG pll funcs for DPLL4 instead of creating new ones and modify
mg_pll_enable to include the restrictions for EHL.
v3: Fix compilation error
v4: (suggestions from Lucas and Ville)
- Treat DPLL4 as a combo phy PLL and not as MG PLL
- Disable DC states when this DPLL is being enabled
- Reuse icl_get_dpll instead of creating a separate one for EHL
Cc: Lucas De Marchi
Cc: José Roberto de Souza
Cc: Bob Paauwe
Signed-off-by: Vivek Kasireddy
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 35 ---
drivers/gpu/drm/i915/intel_dpll_mgr.h | 4
2 files changed, 36 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index e01c057ce50b..207af4af4978 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2825,6 +2825,12 @@ icl_get_dpll(struct intel_crtc_state *crtc_state,
if (intel_port_is_combophy(dev_priv, port)) {
min = DPLL_ID_ICL_DPLL0;
max = DPLL_ID_ICL_DPLL1;
+
+ if (IS_ELKHARTLAKE(dev_priv)) {
+ if (encoder->type != INTEL_OUTPUT_EDP)
+ max = DPLL_ID_EHL_DPLL4;
+ }
+
ret = icl_calc_dpll_state(crtc_state, encoder);
} else if (intel_port_is_tc(dev_priv, port)) {
if (encoder->type == INTEL_OUTPUT_DP_MST) {
@@ -2964,8 +2970,14 @@ static bool combo_pll_get_hw_state(struct
drm_i915_private *dev_priv,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *hw_state)
{
- return icl_pll_get_hw_state(dev_priv, pll, hw_state,
- CNL_DPLL_ENABLE(pll->info->id));
+ i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
+
+ if (IS_ELKHARTLAKE(dev_priv) &&
+ pll->info->id == DPLL_ID_EHL_DPLL4) {
+ enable_reg = MG_PLL_ENABLE(0);
+ }
+
+ return icl_pll_get_hw_state(dev_priv, pll, hw_state, enable_reg);
}
static bool tbt_pll_get_hw_state(struct drm_i915_private *dev_priv,
@@ -3076,6 +3088,14 @@ static void combo_pll_enable(struct drm_i915_private
*dev_priv,
{
i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
+ if (IS_ELKHARTLAKE(dev_priv) &&
+ pll->info->id == DPLL_ID_EHL_DPLL4) {
+ enable_reg = MG_PLL_ENABLE(0);
+
+ /* Need to disable DC states when this DPLL is enabled. */
+ bxt_disable_dc9(dev_priv);
+ }
+
icl_pll_power_enable(dev_priv, pll, enable_reg);
icl_dpll_write(dev_priv, pll);
@@ -3171,7 +3191,15 @@ static void icl_pll_disable(struct drm_i915_private
*dev_priv,
static void combo_pll_disable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
- icl_pll_disable(dev_priv, pll, CNL_DPLL_ENABLE(pll->info->id));
+ i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
+
+ if (IS_ELKHARTLAKE(dev_priv) &&
+ pll->info->id == DPLL_ID_EHL_DPLL4) {
+ enable_reg = MG_PLL_ENABLE(0);
+ bxt_enable_dc9(dev_priv);
+ }
+
+ icl_pll_disable(dev_priv, pll, enable_reg);
}
static void tbt_pll_disable(struct drm_i915_private *dev_priv,
@@ -3249,6 +3277,7 @@ static const struct intel_dpll_mgr icl_pll_mgr = {
static const struct dpll_info ehl_plls[] = {
{ "DPLL 0", _pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
{ "DPLL 1", _pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
+ { "DPLL 4", _pll_funcs, DPLL_ID_EHL_DPLL4, 0 },
{ },
};
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h
b/drivers/gpu/drm/i915/intel_dpll_mgr.h
index bd8124cc81ed..f3f99929cee8 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
@@ -113,6 +113,10 @@ enum intel_dpll_id {
* @DPLL_ID_ICL_DPLL1: ICL combo PHY DPLL1
*/
DPLL_ID_ICL_DPLL1 = 1,
+ /**
+* @DPLL_ID_EHL_DPLL4: EHL combo PHY DPLL4
+*/
+ DPLL_ID_EHL_DPLL4 = 2,
/**
* @DPLL_ID_ICL_TBTPLL: ICL TBT PLL
*/
--
2.14.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/ehl: Inherit Ice Lake conditional code
On Thu, Apr 11, 2019 at 04:16:41PM -0700, Souza, Jose wrote:
> On Thu, 2019-04-11 at 16:08 -0700, Rodrigo Vivi wrote:
> > From: Bob Paauwe
> >
> > Most of the conditional code for ICELAKE also applies to ELKHARTLAKE
> > so use IS_GEN(dev_priv, 11) even for PM and Workarounds for now.
> >
> > v2: - Rename commit (Jose)
> > - Include a wm workaround (Jose and Lucas)
> > - Include display core init (Jose and Lucas)
> >
> > Cc: José Roberto de Souza
> > Cc: Lucas De Marchi
> > Signed-off-by: Bob Paauwe
> > Signed-off-by: Rodrigo Vivi
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 6 +++---
> > drivers/gpu/drm/i915/intel_runtime_pm.c | 6 +++---
> > drivers/gpu/drm/i915/intel_workarounds.c | 8
> > 3 files changed, 10 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index 8e826a6ab62e..7357bddf9ad9 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4530,10 +4530,10 @@ skl_allocate_pipe_ddb(struct intel_crtc_state
> > *cstate,
> > memset(>wm[level], 0, sizeof(wm-
> > >wm[level]));
> >
> > /*
> > -* Wa_1408961008:icl
> > +* Wa_1408961008:icl, ehl
> > * Underruns with WM1+ disabled
> > */
> > - if (IS_ICELAKE(dev_priv) &&
> > + if (IS_GEN(dev_priv, 11) &&
> > level == 1 && wm->wm[0].plane_en) {
> > wm->wm[level].plane_res_b = wm-
> > >wm[0].plane_res_b;
> > wm->wm[level].plane_res_l = wm-
> > >wm[0].plane_res_l;
> > @@ -9573,7 +9573,7 @@ static void nop_init_clock_gating(struct
> > drm_i915_private *dev_priv)
> > */
> > void intel_init_clock_gating_hooks(struct drm_i915_private
> > *dev_priv)
> > {
> > - if (IS_ICELAKE(dev_priv))
> > + if (IS_GEN(dev_priv, 11))
> > dev_priv->display.init_clock_gating =
> > icl_init_clock_gating;
> > else if (IS_CANNONLAKE(dev_priv))
> > dev_priv->display.init_clock_gating =
> > cnl_init_clock_gating;
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index 3107a742d8ad..fcd388e8978b 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -3448,7 +3448,7 @@ int intel_power_domains_init(struct
> > drm_i915_private *dev_priv)
> > * The enabling order will be from lower to higher indexed
> > wells,
> > * the disabling order is reversed.
> > */
> > - if (IS_ICELAKE(dev_priv)) {
> > + if (IS_GEN(dev_priv, 11)) {
> > err = set_power_wells(power_domains, icl_power_wells);
> > } else if (IS_CANNONLAKE(dev_priv)) {
> > err = set_power_wells(power_domains, cnl_power_wells);
> > @@ -4061,7 +4061,7 @@ void intel_power_domains_init_hw(struct
> > drm_i915_private *i915, bool resume)
> >
> > power_domains->initializing = true;
> >
> > - if (IS_ICELAKE(i915)) {
> > + if (INTEL_GEN(i915) >= 11) {
> > icl_display_core_init(i915, resume);
> > } else if (IS_CANNONLAKE(i915)) {
> > cnl_display_core_init(i915, resume);
> > @@ -4209,7 +4209,7 @@ void intel_power_domains_suspend(struct
> > drm_i915_private *i915,
> > intel_power_domains_verify_state(i915);
> > }
> >
> > - if (IS_ICELAKE(i915))
> > + if (IS_GEN(i915, 11))
>
> To be consistent with init: if (INTEL_GEN(i915) >= 11)
hmmm... I tried to keep power well stuff not using this
greater-than behaviour on purpose... Because so far all
platforms had different wells, besides gen9_bc group of course...
But even display_10 glk and cnl are different on display wells :/
>
> Other than that:
>
> Reviewed-by: José Roberto de Souza
>
> > icl_display_core_uninit(i915);
> > else if (IS_CANNONLAKE(i915))
> > cnl_display_core_uninit(i915);
> > diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
> > b/drivers/gpu/drm/i915/intel_workarounds.c
> > index a04dbc58ec1c..c0977036db79 100644
> > --- a/drivers/gpu/drm/i915/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> > @@ -569,7 +569,7 @@ void intel_engine_init_ctx_wa(struct
> > intel_engine_cs *engine)
> >
> > wa_init_start(wal, "context");
> >
> > - if (IS_ICELAKE(i915))
> > + if (IS_GEN(i915, 11))
> > icl_ctx_workarounds_init(engine);
> > else if (IS_CANNONLAKE(i915))
> > cnl_ctx_workarounds_init(engine);
> > @@ -867,7 +867,7 @@ icl_gt_workarounds_init(struct drm_i915_private
> > *i915, struct i915_wa_list *wal)
> > static void
> > gt_init_workarounds(struct drm_i915_private *i915, struct
> > i915_wa_list *wal)
> > {
> > - if (IS_ICELAKE(i915))
> > + if (IS_GEN(i915, 11))
> > icl_gt_workarounds_init(i915, wal);
> > else if
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm: Add detection of changing of edid on between suspend and resume
== Series Details == Series: drm: Add detection of changing of edid on between suspend and resume URL : https://patchwork.freedesktop.org/series/59352/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5917 -> Patchwork_12767 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12767 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12767, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/59352/revisions/1/mbox/ Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12767: ### IGT changes ### Possible regressions * igt@runner@aborted: - fi-icl-y: NOTRUN -> FAIL Known issues Here are the changes found in Patchwork_12767 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@semaphore: - fi-kbl-7500u: NOTRUN -> SKIP [fdo#109271] +28 * igt@gem_exec_basic@gtt-bsd2: - fi-byt-clapper: NOTRUN -> SKIP [fdo#109271] +52 * igt@gem_exec_basic@readonly-bsd1: - fi-snb-2520m: NOTRUN -> SKIP [fdo#109271] +52 * igt@gem_exec_store@basic-bsd2: - fi-hsw-4770:NOTRUN -> SKIP [fdo#109271] +41 * igt@kms_busy@basic-flip-c: - fi-byt-clapper: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-snb-2520m: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-7500u: NOTRUN -> DMESG-WARN [fdo#102505] / [fdo#103558] / [fdo#105079] / [fdo#105602] * igt@kms_flip@basic-flip-vs-dpms: - fi-byt-j1900: PASS -> INCOMPLETE [fdo#102657] * igt@kms_flip@basic-flip-vs-modeset: - fi-byt-n2820: PASS -> INCOMPLETE [fdo#102657] * igt@kms_frontbuffer_tracking@basic: - fi-byt-clapper: NOTRUN -> FAIL [fdo#103167] * igt@kms_pipe_crc_basic@read-crc-pipe-b: - fi-glk-dsi: PASS -> FAIL [fdo#103191] * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-byt-clapper: NOTRUN -> FAIL [fdo#103191] Possible fixes * igt@i915_selftest@live_contexts: - fi-bdw-gvtdvm: DMESG-FAIL [fdo#110235 ] -> PASS * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: DMESG-WARN [fdo#103841] -> PASS [fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505 [fdo#102657]: https://bugs.freedesktop.org/show_bug.cgi?id=102657 [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558 [fdo#103841]: https://bugs.freedesktop.org/show_bug.cgi?id=103841 [fdo#105079]: https://bugs.freedesktop.org/show_bug.cgi?id=105079 [fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#110235 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110235 Participating hosts (47 -> 44) -- Additional (3): fi-hsw-4770 fi-byt-clapper fi-snb-2520m Missing(6): fi-kbl-soraka fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus Build changes - * Linux: CI_DRM_5917 -> Patchwork_12767 CI_DRM_5917: b01c0e68e8d1092c436dbba4d03b260c828f37c9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4944: 9b74b8226e8c108db091bd3b1d105a71dc0fb861 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12767: ccdf8a88a55c02a77ad81b97714fdf561a8dbbee @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ccdf8a88a55c drm/i915: Add a missed update of edid property of drm connector f8af584568d1 drm: Add detection of changing of edid on between suspend and resume == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12767/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v6] drm/i915/icl: Fix clockgating issue when using scalers
On Thu, 2019-04-11 at 14:41 -0700, Souza, Jose wrote:
> On Fri, 2019-04-05 at 14:14 -0700, Radhakrishna Sripada wrote:
> > Fixes the clock-gating issue when pipe scaling is enabled.
> > (Lineage #2006604312)
> >
> > V2: Fix typo in headline(Chris)
> > Handle the non double buffered nature of the register(Ville)
> > V3: Fix checkpatch warning. BAT failure for V2 on gen3 looks
> > unrelated.
> > V4: Split the icl and skl wa's(Ville)
> > V5: Split the checks for icl and skl(Ville)
> > V6: Correct the flipped checks in intel_pre_plane_update(Ville)
> >
> > Cc: Chris Wilson
> > Cc: Ville Syrjala
> > Cc: Rodrigo Vivi
> > Cc: Aditya Swarup
> > Signed-off-by: Radhakrishna Sripada > >
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 39
> >
> > 1 file changed, 34 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index cf6046390eeb..ab820cad990d 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -466,6 +466,7 @@ static const struct intel_limit
> > intel_limits_bxt
> > = {
> > .p2 = { .p2_slow = 1, .p2_fast = 20 },
> > };
> >
> > +/* WA Display #0827: Gen9:all */
> > static void
> > skl_wa_827(struct drm_i915_private *dev_priv, int pipe, bool
> > enable)
> > {
> > @@ -479,6 +480,18 @@ skl_wa_827(struct drm_i915_private *dev_priv,
> > int pipe, bool enable)
> >~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
> > }
> >
> > +/* Wa_2006604312:icl */
> > +static void
> > +icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, int
> > pipe,
> > bool enable)
> > +{
> > + if (enable)
> > + I915_WRITE(CLKGATE_DIS_PSL(pipe),
> > + I915_READ(CLKGATE_DIS_PSL(pipe)) |
> > DPFR_GATING_DIS);
> > + else
> > + I915_WRITE(CLKGATE_DIS_PSL(pipe),
> > + I915_READ(CLKGATE_DIS_PSL(pipe)) &
> > ~DPFR_GATING_DIS);
> > +}
> > +
> > static bool
> > needs_modeset(const struct drm_crtc_state *state)
> > {
> > @@ -5495,6 +5508,16 @@ static bool needs_nv12_wa(struct
> > drm_i915_private *dev_priv,
> > return false;
> > }
> >
> > +static bool needs_scalerclk_wa(struct drm_i915_private *dev_priv,
> > + const struct intel_crtc_state
> > *crtc_state)
> > +{
> > + /* Wa_2006604312:icl */
> > + if (crtc_state->pch_pfit.enabled && IS_ICELAKE(dev_priv))
> > + return true;
>
> Looking to BSpec this WA is needed for other platforms too like
> elkhartlake, so I would change to:
>
> if (INTEL_GEN(dev_priv) >= 11)
> return crtc_state->pch_pfit.enabled;
That is an interesting feedback. When multiple platforms are involved I
would rather track it as seperate patches for downstream
maintainability and restrict the usage to (IS_ICELAKE(dev_priv) |
IS_ELKHARTLAKE(dev_priv)) comapred to using (INTEL_GEN(dev_priv) >= 11)
IMO that needs to be carried out in a seperate patch. Thoughts?
- Radhakrishna(RK) Sripada
>
> > +
> > + return false;
> > +}
> > +
> > static void intel_post_plane_update(struct intel_crtc_state
> > *old_crtc_state)
> > {
> > struct intel_crtc *crtc = to_intel_crtc(old_crtc_state-
> > > base.crtc);
> >
> > @@ -5528,11 +5551,13 @@ static void intel_post_plane_update(struct
> > intel_crtc_state *old_crtc_state)
> > intel_post_enable_primary(>base,
> > pipe_config);
> > }
> >
> > - /* Display WA 827 */
> > if (needs_nv12_wa(dev_priv, old_crtc_state) &&
> > - !needs_nv12_wa(dev_priv, pipe_config)) {
> > + !needs_nv12_wa(dev_priv, pipe_config))
> > skl_wa_827(dev_priv, crtc->pipe, false);
> > - }
> > +
> > + if (needs_scalerclk_wa(dev_priv, old_crtc_state) &&
> > + !needs_scalerclk_wa(dev_priv, pipe_config))
> > + icl_wa_scalerclkgating(dev_priv, crtc->pipe, false);
> > }
> >
> > static void intel_pre_plane_update(struct intel_crtc_state
> > *old_crtc_state,
> > @@ -5569,9 +5594,13 @@ static void intel_pre_plane_update(struct
> > intel_crtc_state *old_crtc_state,
> >
> > /* Display WA 827 */
> > if (!needs_nv12_wa(dev_priv, old_crtc_state) &&
> > - needs_nv12_wa(dev_priv, pipe_config)) {
> > + needs_nv12_wa(dev_priv, pipe_config))
> > skl_wa_827(dev_priv, crtc->pipe, true);
> > - }
> > +
> > + /* Wa_2006604312:icl */
> > + if (!needs_scalerclk_wa(dev_priv, old_crtc_state) &&
> > + needs_scalerclk_wa(dev_priv, pipe_config))
> > + icl_wa_scalerclkgating(dev_priv, crtc->pipe, true);
> >
> > /*
> > * Vblank time updates from the shadow to live plane control
> > register
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/5] drm/i915: don't specify the IRQ register in the gen2 macros
On 4/10/19 4:53 PM, Paulo Zanoni wrote:
Like the gen3+ macros, the gen2 versions of the IRQ initialization
macros take the register name in the 'type' argument. But gen2 only
has one set of registers, so there's really no need to specify the
type. This commit removes the type argument and uses the registers
directly instead of passing them through variables.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_irq.c | 57 +++--
1 file changed, 25 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 60a3f4203ac3..b1f1db2bd879 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -151,19 +151,18 @@ static void gen3_irq_reset(struct drm_i915_private
*dev_priv, i915_reg_t imr,
POSTING_READ(iir);
}
-static void gen2_irq_reset(struct drm_i915_private *dev_priv, i915_reg_t imr,
- i915_reg_t iir, i915_reg_t ier)
+static void gen2_irq_reset(struct drm_i915_private *dev_priv)
{
- I915_WRITE16(imr, 0x);
- POSTING_READ16(imr);
+ I915_WRITE16(IMR, 0x);
+ POSTING_READ16(IMR);
- I915_WRITE16(ier, 0);
+ I915_WRITE16(IER, 0);
/* IIR can theoretically queue up two events. Be paranoid. */
- I915_WRITE16(iir, 0x);
- POSTING_READ16(iir);
- I915_WRITE16(iir, 0x);
- POSTING_READ16(iir);
+ I915_WRITE16(IIR, 0x);
+ POSTING_READ16(IIR);
+ I915_WRITE16(IIR, 0x);
+ POSTING_READ16(IIR);
}
#define GEN8_IRQ_RESET_NDX(type, which) \
@@ -176,8 +175,8 @@ static void gen2_irq_reset(struct drm_i915_private
*dev_priv, i915_reg_t imr,
#define GEN3_IRQ_RESET(type) \
gen3_irq_reset(dev_priv, type##IMR, type##IIR, type##IER)
-#define GEN2_IRQ_RESET(type) \
- gen2_irq_reset(dev_priv, type##IMR, type##IIR, type##IER)
+#define GEN2_IRQ_RESET() \
+ gen2_irq_reset(dev_priv)
We could potentially drop the macro entirely now since it doesn't really
add any functional value. The same applies for GEN2_IRQ_INIT.
However, I see the argument for keeping things consistent and use the
same "look" across gens, so with or without the change:
Reviewed-by: Daniele Ceraolo Spurio
Daniele
/*
* We should clear IMR at preinstall/uninstall, and just check at postinstall.
@@ -198,20 +197,19 @@ static void gen3_assert_iir_is_zero(struct
drm_i915_private *dev_priv,
POSTING_READ(reg);
}
-static void gen2_assert_iir_is_zero(struct drm_i915_private *dev_priv,
- i915_reg_t reg)
+static void gen2_assert_iir_is_zero(struct drm_i915_private *dev_priv)
{
- u16 val = I915_READ16(reg);
+ u16 val = I915_READ16(IIR);
if (val == 0)
return;
WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
-i915_mmio_reg_offset(reg), val);
- I915_WRITE16(reg, 0x);
- POSTING_READ16(reg);
- I915_WRITE16(reg, 0x);
- POSTING_READ16(reg);
+i915_mmio_reg_offset(IIR), val);
+ I915_WRITE16(IIR, 0x);
+ POSTING_READ16(IIR);
+ I915_WRITE16(IIR, 0x);
+ POSTING_READ16(IIR);
}
static void gen3_irq_init(struct drm_i915_private *dev_priv,
@@ -227,15 +225,13 @@ static void gen3_irq_init(struct drm_i915_private
*dev_priv,
}
static void gen2_irq_init(struct drm_i915_private *dev_priv,
- i915_reg_t imr, u32 imr_val,
- i915_reg_t ier, u32 ier_val,
- i915_reg_t iir)
+ u32 imr_val, u32 ier_val)
{
- gen2_assert_iir_is_zero(dev_priv, iir);
+ gen2_assert_iir_is_zero(dev_priv);
- I915_WRITE16(ier, ier_val);
- I915_WRITE16(imr, imr_val);
- POSTING_READ16(imr);
+ I915_WRITE16(IER, ier_val);
+ I915_WRITE16(IMR, imr_val);
+ POSTING_READ16(IMR);
}
#define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) \
@@ -253,11 +249,8 @@ static void gen2_irq_init(struct drm_i915_private
*dev_priv,
type##IER, ier_val, \
type##IIR)
-#define GEN2_IRQ_INIT(type, imr_val, ier_val) \
- gen2_irq_init(dev_priv, \
- type##IMR, imr_val, \
- type##IER, ier_val, \
- type##IIR)
+#define GEN2_IRQ_INIT(imr_val, ier_val) \
+ gen2_irq_init(dev_priv, imr_val, ier_val)
static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32
pm_iir);
@@ -4247,7 +4240,7 @@ static int i8xx_irq_postinstall(struct drm_device *dev)
I915_MASTER_ERROR_INTERRUPT |
I915_USER_INTERRUPT;
- GEN2_IRQ_INIT(, dev_priv->irq_mask, enable_mask);
+ GEN2_IRQ_INIT(dev_priv->irq_mask, enable_mask);
/* Interrupt setup is already guaranteed to
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm: Add detection of changing of edid on between suspend and resume
== Series Details == Series: drm: Add detection of changing of edid on between suspend and resume URL : https://patchwork.freedesktop.org/series/59352/ State : warning == Summary == $ dim checkpatch origin/drm-tip f8af584568d1 drm: Add detection of changing of edid on between suspend and resume -:90: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #90: FILE: drivers/gpu/drm/drm_probe_helper.c:808: + if (memcmp(old_edid_blob_ptr->data, + connector->edid_blob_ptr->data, total: 0 errors, 0 warnings, 1 checks, 58 lines checked ccdf8a88a55c drm/i915: Add a missed update of edid property of drm connector ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/ehl: Inherit Ice Lake conditional code
On Thu, 2019-04-11 at 16:08 -0700, Rodrigo Vivi wrote:
> From: Bob Paauwe
>
> Most of the conditional code for ICELAKE also applies to ELKHARTLAKE
> so use IS_GEN(dev_priv, 11) even for PM and Workarounds for now.
>
> v2: - Rename commit (Jose)
> - Include a wm workaround (Jose and Lucas)
> - Include display core init (Jose and Lucas)
>
> Cc: José Roberto de Souza
> Cc: Lucas De Marchi
> Signed-off-by: Bob Paauwe
> Signed-off-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/intel_pm.c | 6 +++---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 6 +++---
> drivers/gpu/drm/i915/intel_workarounds.c | 8
> 3 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index 8e826a6ab62e..7357bddf9ad9 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4530,10 +4530,10 @@ skl_allocate_pipe_ddb(struct intel_crtc_state
> *cstate,
> memset(>wm[level], 0, sizeof(wm-
> >wm[level]));
>
> /*
> - * Wa_1408961008:icl
> + * Wa_1408961008:icl, ehl
>* Underruns with WM1+ disabled
>*/
> - if (IS_ICELAKE(dev_priv) &&
> + if (IS_GEN(dev_priv, 11) &&
> level == 1 && wm->wm[0].plane_en) {
> wm->wm[level].plane_res_b = wm-
> >wm[0].plane_res_b;
> wm->wm[level].plane_res_l = wm-
> >wm[0].plane_res_l;
> @@ -9573,7 +9573,7 @@ static void nop_init_clock_gating(struct
> drm_i915_private *dev_priv)
> */
> void intel_init_clock_gating_hooks(struct drm_i915_private
> *dev_priv)
> {
> - if (IS_ICELAKE(dev_priv))
> + if (IS_GEN(dev_priv, 11))
> dev_priv->display.init_clock_gating =
> icl_init_clock_gating;
> else if (IS_CANNONLAKE(dev_priv))
> dev_priv->display.init_clock_gating =
> cnl_init_clock_gating;
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 3107a742d8ad..fcd388e8978b 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -3448,7 +3448,7 @@ int intel_power_domains_init(struct
> drm_i915_private *dev_priv)
>* The enabling order will be from lower to higher indexed
> wells,
>* the disabling order is reversed.
>*/
> - if (IS_ICELAKE(dev_priv)) {
> + if (IS_GEN(dev_priv, 11)) {
> err = set_power_wells(power_domains, icl_power_wells);
> } else if (IS_CANNONLAKE(dev_priv)) {
> err = set_power_wells(power_domains, cnl_power_wells);
> @@ -4061,7 +4061,7 @@ void intel_power_domains_init_hw(struct
> drm_i915_private *i915, bool resume)
>
> power_domains->initializing = true;
>
> - if (IS_ICELAKE(i915)) {
> + if (INTEL_GEN(i915) >= 11) {
> icl_display_core_init(i915, resume);
> } else if (IS_CANNONLAKE(i915)) {
> cnl_display_core_init(i915, resume);
> @@ -4209,7 +4209,7 @@ void intel_power_domains_suspend(struct
> drm_i915_private *i915,
> intel_power_domains_verify_state(i915);
> }
>
> - if (IS_ICELAKE(i915))
> + if (IS_GEN(i915, 11))
To be consistent with init: if (INTEL_GEN(i915) >= 11)
Other than that:
Reviewed-by: José Roberto de Souza
> icl_display_core_uninit(i915);
> else if (IS_CANNONLAKE(i915))
> cnl_display_core_uninit(i915);
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
> b/drivers/gpu/drm/i915/intel_workarounds.c
> index a04dbc58ec1c..c0977036db79 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -569,7 +569,7 @@ void intel_engine_init_ctx_wa(struct
> intel_engine_cs *engine)
>
> wa_init_start(wal, "context");
>
> - if (IS_ICELAKE(i915))
> + if (IS_GEN(i915, 11))
> icl_ctx_workarounds_init(engine);
> else if (IS_CANNONLAKE(i915))
> cnl_ctx_workarounds_init(engine);
> @@ -867,7 +867,7 @@ icl_gt_workarounds_init(struct drm_i915_private
> *i915, struct i915_wa_list *wal)
> static void
> gt_init_workarounds(struct drm_i915_private *i915, struct
> i915_wa_list *wal)
> {
> - if (IS_ICELAKE(i915))
> + if (IS_GEN(i915, 11))
> icl_gt_workarounds_init(i915, wal);
> else if (IS_CANNONLAKE(i915))
> cnl_gt_workarounds_init(i915, wal);
> @@ -1064,7 +1064,7 @@ void intel_engine_init_whitelist(struct
> intel_engine_cs *engine)
>
> wa_init_start(w, "whitelist");
>
> - if (IS_ICELAKE(i915))
> + if (IS_GEN(i915, 11))
> icl_whitelist_build(w);
> else if (IS_CANNONLAKE(i915))
> cnl_whitelist_build(w);
> @@ -1112,7 +1112,7 @@ rcs_engine_wa_init(struct intel_engine_cs
> *engine, struct
[Intel-gfx] [PATCH] drm/i915/ehl: Inherit Ice Lake conditional code
From: Bob Paauwe
Most of the conditional code for ICELAKE also applies to ELKHARTLAKE
so use IS_GEN(dev_priv, 11) even for PM and Workarounds for now.
v2: - Rename commit (Jose)
- Include a wm workaround (Jose and Lucas)
- Include display core init (Jose and Lucas)
Cc: José Roberto de Souza
Cc: Lucas De Marchi
Signed-off-by: Bob Paauwe
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_pm.c | 6 +++---
drivers/gpu/drm/i915/intel_runtime_pm.c | 6 +++---
drivers/gpu/drm/i915/intel_workarounds.c | 8
3 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8e826a6ab62e..7357bddf9ad9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4530,10 +4530,10 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
memset(>wm[level], 0,
sizeof(wm->wm[level]));
/*
-* Wa_1408961008:icl
+* Wa_1408961008:icl, ehl
* Underruns with WM1+ disabled
*/
- if (IS_ICELAKE(dev_priv) &&
+ if (IS_GEN(dev_priv, 11) &&
level == 1 && wm->wm[0].plane_en) {
wm->wm[level].plane_res_b =
wm->wm[0].plane_res_b;
wm->wm[level].plane_res_l =
wm->wm[0].plane_res_l;
@@ -9573,7 +9573,7 @@ static void nop_init_clock_gating(struct drm_i915_private
*dev_priv)
*/
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_ICELAKE(dev_priv))
+ if (IS_GEN(dev_priv, 11))
dev_priv->display.init_clock_gating = icl_init_clock_gating;
else if (IS_CANNONLAKE(dev_priv))
dev_priv->display.init_clock_gating = cnl_init_clock_gating;
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 3107a742d8ad..fcd388e8978b 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -3448,7 +3448,7 @@ int intel_power_domains_init(struct drm_i915_private
*dev_priv)
* The enabling order will be from lower to higher indexed wells,
* the disabling order is reversed.
*/
- if (IS_ICELAKE(dev_priv)) {
+ if (IS_GEN(dev_priv, 11)) {
err = set_power_wells(power_domains, icl_power_wells);
} else if (IS_CANNONLAKE(dev_priv)) {
err = set_power_wells(power_domains, cnl_power_wells);
@@ -4061,7 +4061,7 @@ void intel_power_domains_init_hw(struct drm_i915_private
*i915, bool resume)
power_domains->initializing = true;
- if (IS_ICELAKE(i915)) {
+ if (INTEL_GEN(i915) >= 11) {
icl_display_core_init(i915, resume);
} else if (IS_CANNONLAKE(i915)) {
cnl_display_core_init(i915, resume);
@@ -4209,7 +4209,7 @@ void intel_power_domains_suspend(struct drm_i915_private
*i915,
intel_power_domains_verify_state(i915);
}
- if (IS_ICELAKE(i915))
+ if (IS_GEN(i915, 11))
icl_display_core_uninit(i915);
else if (IS_CANNONLAKE(i915))
cnl_display_core_uninit(i915);
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index a04dbc58ec1c..c0977036db79 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -569,7 +569,7 @@ void intel_engine_init_ctx_wa(struct intel_engine_cs
*engine)
wa_init_start(wal, "context");
- if (IS_ICELAKE(i915))
+ if (IS_GEN(i915, 11))
icl_ctx_workarounds_init(engine);
else if (IS_CANNONLAKE(i915))
cnl_ctx_workarounds_init(engine);
@@ -867,7 +867,7 @@ icl_gt_workarounds_init(struct drm_i915_private *i915,
struct i915_wa_list *wal)
static void
gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
- if (IS_ICELAKE(i915))
+ if (IS_GEN(i915, 11))
icl_gt_workarounds_init(i915, wal);
else if (IS_CANNONLAKE(i915))
cnl_gt_workarounds_init(i915, wal);
@@ -1064,7 +1064,7 @@ void intel_engine_init_whitelist(struct intel_engine_cs
*engine)
wa_init_start(w, "whitelist");
- if (IS_ICELAKE(i915))
+ if (IS_GEN(i915, 11))
icl_whitelist_build(w);
else if (IS_CANNONLAKE(i915))
cnl_whitelist_build(w);
@@ -1112,7 +1112,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct
i915_wa_list *wal)
{
struct drm_i915_private *i915 = engine->i915;
- if (IS_ICELAKE(i915)) {
+ if (IS_GEN(i915, 11)) {
/* This is not an Wa. Enable for better image quality */
wa_masked_en(wal,
_3D_CHICKEN3,
--
2.20.1
[Intel-gfx] [PATCH] drm/i915: Nuke drm_crtc_state and use intel_atomic_state instead
This is one of the patches to start replacing drm pointers
and use the intel_atomic_state and intel_crtc to derive
the necessary intel state variables required for the intel
modeset functions.
Suggested-by: Ville Syrjala
Cc: Ville Syrjala
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/intel_display.c | 38 +---
1 file changed, 18 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index f29a348e8d71..062b9e86a987 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -125,8 +125,8 @@ static void vlv_prepare_pll(struct intel_crtc *crtc,
const struct intel_crtc_state *pipe_config);
static void chv_prepare_pll(struct intel_crtc *crtc,
const struct intel_crtc_state *pipe_config);
-static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state
*);
-static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state
*);
+static void intel_begin_crtc_commit(struct intel_crtc *, struct
intel_atomic_state *);
+static void intel_finish_crtc_commit(struct intel_crtc *, struct
intel_atomic_state *);
static void intel_crtc_init_scalers(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state);
static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state);
@@ -13273,14 +13273,14 @@ static void intel_update_crtc(struct drm_crtc *crtc,
else if (new_plane_state)
intel_fbc_enable(intel_crtc, pipe_config, new_plane_state);
- intel_begin_crtc_commit(crtc, old_crtc_state);
+ intel_begin_crtc_commit(intel_crtc, to_intel_atomic_state(state));
if (INTEL_GEN(dev_priv) >= 9)
skl_update_planes_on_crtc(to_intel_atomic_state(state),
intel_crtc);
else
i9xx_update_planes_on_crtc(to_intel_atomic_state(state),
intel_crtc);
- intel_finish_crtc_commit(crtc, old_crtc_state);
+ intel_finish_crtc_commit(intel_crtc, to_intel_atomic_state(state));
}
static void intel_update_crtcs(struct drm_atomic_state *state)
@@ -14070,18 +14070,16 @@ skl_max_scale(const struct intel_crtc_state
*crtc_state,
return max_scale;
}
-static void intel_begin_crtc_commit(struct drm_crtc *crtc,
- struct drm_crtc_state *old_crtc_state)
+static void intel_begin_crtc_commit(struct intel_crtc *crtc,
+ struct intel_atomic_state *state)
{
- struct drm_device *dev = crtc->dev;
+ struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_crtc_state *old_intel_cstate =
- to_intel_crtc_state(old_crtc_state);
- struct intel_atomic_state *old_intel_state =
- to_intel_atomic_state(old_crtc_state->state);
+ intel_atomic_get_old_crtc_state(state,
+ crtc);
struct intel_crtc_state *intel_cstate =
- intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
+ intel_atomic_get_new_crtc_state(state, crtc);
bool modeset = needs_modeset(_cstate->base);
/* Perform vblank evasion around commit operation */
@@ -14101,7 +14099,7 @@ static void intel_begin_crtc_commit(struct drm_crtc
*crtc,
out:
if (dev_priv->display.atomic_update_watermarks)
- dev_priv->display.atomic_update_watermarks(old_intel_state,
+ dev_priv->display.atomic_update_watermarks(state,
intel_cstate);
}
@@ -14121,21 +14119,21 @@ void intel_crtc_arm_fifo_underrun(struct intel_crtc
*crtc,
}
}
-static void intel_finish_crtc_commit(struct drm_crtc *crtc,
-struct drm_crtc_state *old_crtc_state)
+static void intel_finish_crtc_commit(struct intel_crtc *crtc,
+struct intel_atomic_state *state)
{
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- struct intel_atomic_state *old_intel_state =
- to_intel_atomic_state(old_crtc_state->state);
+ struct drm_crtc_state *old_crtc_state =
+ _atomic_get_old_crtc_state(state,
+ crtc)->base;
struct intel_crtc_state *new_crtc_state =
- intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
+ intel_atomic_get_new_crtc_state(state, crtc);
intel_pipe_update_end(new_crtc_state);
if (new_crtc_state->update_pipe &&
!needs_modeset(_crtc_state->base) &&
old_crtc_state->mode.private_flags & I915_MODE_FLAG_INHERITED)
- intel_crtc_arm_fifo_underrun(intel_crtc, new_crtc_state);
+
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Suppress spurious combo PHY B warning
== Series Details == Series: drm/i915: Suppress spurious combo PHY B warning URL : https://patchwork.freedesktop.org/series/59350/ State : success == Summary == CI Bug Log - changes from CI_DRM_5916 -> Patchwork_12766 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/59350/revisions/1/mbox/ Known issues Here are the changes found in Patchwork_12766 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_cs_nop@fork-compute0: - fi-icl-y: NOTRUN -> SKIP [fdo#109315] +17 * igt@gem_exec_basic@basic-bsd2: - fi-icl-y: NOTRUN -> SKIP [fdo#109276] +7 * igt@gem_exec_parse@basic-rejected: - fi-icl-y: NOTRUN -> SKIP [fdo#109289] +1 * igt@i915_selftest@live_contexts: - fi-icl-y: NOTRUN -> INCOMPLETE [fdo#108569] * igt@kms_busy@basic-flip-a: - fi-bsw-n3050: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1 * igt@kms_busy@basic-flip-c: - fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_chamelium@dp-crc-fast: - fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] +43 - fi-icl-y: NOTRUN -> SKIP [fdo#109284] +8 * igt@kms_chamelium@hdmi-crc-fast: - fi-bsw-n3050: NOTRUN -> SKIP [fdo#109271] +57 * igt@kms_flip@basic-flip-vs-wf_vblank: - fi-bwr-2160:PASS -> FAIL [fdo#100368] * igt@kms_force_connector_basic@force-edid: - fi-glk-dsi: NOTRUN -> SKIP [fdo#109271] +26 * igt@kms_force_connector_basic@force-load-detect: - fi-icl-y: NOTRUN -> SKIP [fdo#109285] +3 * igt@kms_frontbuffer_tracking@basic: - fi-glk-dsi: NOTRUN -> FAIL [fdo#103167] * igt@kms_pipe_crc_basic@read-crc-pipe-a: - fi-byt-clapper: PASS -> FAIL [fdo#103191] * igt@kms_psr@primary_mmap_gtt: - fi-icl-y: NOTRUN -> SKIP [fdo#110189] +3 * igt@prime_vgem@basic-fence-flip: - fi-icl-y: NOTRUN -> SKIP [fdo#109294] Possible fixes * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS * igt@i915_selftest@live_contexts: - fi-bdw-gvtdvm: DMESG-FAIL [fdo#110235 ] -> PASS * igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size: - fi-glk-dsi: INCOMPLETE [fdo#103359] / [k.org#198133] -> PASS * igt@kms_frontbuffer_tracking@basic: - fi-byt-clapper: FAIL [fdo#103167] -> PASS * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-byt-clapper: FAIL [fdo#103191] -> PASS [fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368 [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109294]: https://bugs.freedesktop.org/show_bug.cgi?id=109294 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189 [fdo#110235 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110235 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (47 -> 44) -- Additional (2): fi-icl-y fi-bsw-n3050 Missing(5): fi-kbl-soraka fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus Build changes - * Linux: CI_DRM_5916 -> Patchwork_12766 CI_DRM_5916: e087494198a0b5d13ff742587b9d926b0c6417be @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4944: 9b74b8226e8c108db091bd3b1d105a71dc0fb861 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12766: 96e003f6b5c61231daa83f43d6fe9e7081ae43b9 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 96e003f6b5c6 drm/i915: Suppress spurious combo PHY B warning == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12766/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [01/29] drm/i915: Mark up ips for RCU protection (rev2)
== Series Details == Series: series starting with [01/29] drm/i915: Mark up ips for RCU protection (rev2) URL : https://patchwork.freedesktop.org/series/59155/ State : failure == Summary == Applying: drm/i915: Mark up ips for RCU protection Applying: drm/i915/guc: Replace WARN with a DRM_ERROR Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/intel_guc_submission.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/intel_guc_submission.c No changes -- Patch already applied. Applying: drm/i915: Use static allocation for i915_globals_park() Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/i915_globals.c Falling back to patching base and 3-way merge... No changes -- Patch already applied. Applying: drm/i915: Consolidate the timeline->barrier Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/i915_gem_context.c M drivers/gpu/drm/i915/i915_request.c M drivers/gpu/drm/i915/i915_timeline.c M drivers/gpu/drm/i915/i915_timeline.h M drivers/gpu/drm/i915/i915_timeline_types.h M drivers/gpu/drm/i915/selftests/mock_timeline.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/i915_request.c No changes -- Patch already applied. Applying: drm/i915: Store the default sseu setup on the engine Applying: drm/i915: Move GraphicsTechnology files under gt/ Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/i915_debugfs.c M drivers/gpu/drm/i915/i915_drv.h M drivers/gpu/drm/i915/i915_gem.c M drivers/gpu/drm/i915/i915_gem_gtt.c M drivers/gpu/drm/i915/i915_request.c M drivers/gpu/drm/i915/intel_display.c M drivers/gpu/drm/i915/intel_engine_cs.c M drivers/gpu/drm/i915/intel_engine_types.h M drivers/gpu/drm/i915/intel_guc_submission.c M drivers/gpu/drm/i915/intel_lrc.c M drivers/gpu/drm/i915/intel_lrc.h M drivers/gpu/drm/i915/intel_ringbuffer.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/intel_guc_submission.c Auto-merging drivers/gpu/drm/i915/intel_display.c Auto-merging drivers/gpu/drm/i915/i915_request.c Auto-merging drivers/gpu/drm/i915/i915_gem_gtt.c Auto-merging drivers/gpu/drm/i915/i915_gem.c Auto-merging drivers/gpu/drm/i915/i915_drv.h Auto-merging drivers/gpu/drm/i915/i915_debugfs.c Auto-merging drivers/gpu/drm/i915/gt/intel_ringbuffer.c Auto-merging drivers/gpu/drm/i915/gt/intel_lrc.h Auto-merging drivers/gpu/drm/i915/gt/intel_lrc.c Auto-merging drivers/gpu/drm/i915/gt/intel_engine_types.h Auto-merging drivers/gpu/drm/i915/gt/intel_engine_cs.c Applying: drm/i915: Only reset the pinned kernel contexts on resume Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/gt/intel_context_types.h M drivers/gpu/drm/i915/gt/intel_engine.h M drivers/gpu/drm/i915/gt/intel_engine_cs.c M drivers/gpu/drm/i915/gt/intel_lrc.c M drivers/gpu/drm/i915/gt/intel_lrc.h M drivers/gpu/drm/i915/gt/intel_ringbuffer.c M drivers/gpu/drm/i915/i915_drv.h M drivers/gpu/drm/i915/i915_gem.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/gt/intel_lrc.h Auto-merging drivers/gpu/drm/i915/gt/intel_lrc.c Auto-merging drivers/gpu/drm/i915/gt/intel_engine_cs.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/gt/intel_engine_cs.c Auto-merging drivers/gpu/drm/i915/gt/intel_engine.h error: Failed to merge in the changes. hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0007 drm/i915: Only reset the pinned kernel contexts on resume When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/2] drm/i915/guc: Implement reset locally
== Series Details == Series: series starting with [CI,1/2] drm/i915/guc: Implement reset locally URL : https://patchwork.freedesktop.org/series/59343/ State : failure == Summary == Applying: drm/i915/guc: Implement reset locally Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/intel_guc_submission.c M drivers/gpu/drm/i915/intel_lrc.c M drivers/gpu/drm/i915/intel_lrc.h M drivers/gpu/drm/i915/intel_ringbuffer.h Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/intel_lrc.c No changes -- Patch already applied. Applying: drm/i915/execlists: Always reset the context's RING registers Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/intel_lrc.c Falling back to patching base and 3-way merge... No changes -- Patch already applied. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v6] drm/i915/icl: Fix clockgating issue when using scalers
On Fri, 2019-04-05 at 14:14 -0700, Radhakrishna Sripada wrote:
> Fixes the clock-gating issue when pipe scaling is enabled.
> (Lineage #2006604312)
>
> V2: Fix typo in headline(Chris)
> Handle the non double buffered nature of the register(Ville)
> V3: Fix checkpatch warning. BAT failure for V2 on gen3 looks
> unrelated.
> V4: Split the icl and skl wa's(Ville)
> V5: Split the checks for icl and skl(Ville)
> V6: Correct the flipped checks in intel_pre_plane_update(Ville)
>
> Cc: Chris Wilson
> Cc: Ville Syrjala
> Cc: Rodrigo Vivi
> Cc: Aditya Swarup
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/intel_display.c | 39
>
> 1 file changed, 34 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index cf6046390eeb..ab820cad990d 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -466,6 +466,7 @@ static const struct intel_limit intel_limits_bxt
> = {
> .p2 = { .p2_slow = 1, .p2_fast = 20 },
> };
>
> +/* WA Display #0827: Gen9:all */
> static void
> skl_wa_827(struct drm_i915_private *dev_priv, int pipe, bool enable)
> {
> @@ -479,6 +480,18 @@ skl_wa_827(struct drm_i915_private *dev_priv,
> int pipe, bool enable)
> ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
> }
>
> +/* Wa_2006604312:icl */
> +static void
> +icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, int pipe,
> bool enable)
> +{
> + if (enable)
> + I915_WRITE(CLKGATE_DIS_PSL(pipe),
> +I915_READ(CLKGATE_DIS_PSL(pipe)) |
> DPFR_GATING_DIS);
> + else
> + I915_WRITE(CLKGATE_DIS_PSL(pipe),
> +I915_READ(CLKGATE_DIS_PSL(pipe)) &
> ~DPFR_GATING_DIS);
> +}
> +
> static bool
> needs_modeset(const struct drm_crtc_state *state)
> {
> @@ -5495,6 +5508,16 @@ static bool needs_nv12_wa(struct
> drm_i915_private *dev_priv,
> return false;
> }
>
> +static bool needs_scalerclk_wa(struct drm_i915_private *dev_priv,
> +const struct intel_crtc_state
> *crtc_state)
> +{
> + /* Wa_2006604312:icl */
> + if (crtc_state->pch_pfit.enabled && IS_ICELAKE(dev_priv))
> + return true;
Looking to BSpec this WA is needed for other platforms too like
elkhartlake, so I would change to:
if (INTEL_GEN(dev_priv) >= 11)
return crtc_state->pch_pfit.enabled;
> +
> + return false;
> +}
> +
> static void intel_post_plane_update(struct intel_crtc_state
> *old_crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(old_crtc_state-
> >base.crtc);
> @@ -5528,11 +5551,13 @@ static void intel_post_plane_update(struct
> intel_crtc_state *old_crtc_state)
> intel_post_enable_primary(>base,
> pipe_config);
> }
>
> - /* Display WA 827 */
> if (needs_nv12_wa(dev_priv, old_crtc_state) &&
> - !needs_nv12_wa(dev_priv, pipe_config)) {
> + !needs_nv12_wa(dev_priv, pipe_config))
> skl_wa_827(dev_priv, crtc->pipe, false);
> - }
> +
> + if (needs_scalerclk_wa(dev_priv, old_crtc_state) &&
> + !needs_scalerclk_wa(dev_priv, pipe_config))
> + icl_wa_scalerclkgating(dev_priv, crtc->pipe, false);
> }
>
> static void intel_pre_plane_update(struct intel_crtc_state
> *old_crtc_state,
> @@ -5569,9 +5594,13 @@ static void intel_pre_plane_update(struct
> intel_crtc_state *old_crtc_state,
>
> /* Display WA 827 */
> if (!needs_nv12_wa(dev_priv, old_crtc_state) &&
> - needs_nv12_wa(dev_priv, pipe_config)) {
> + needs_nv12_wa(dev_priv, pipe_config))
> skl_wa_827(dev_priv, crtc->pipe, true);
> - }
> +
> + /* Wa_2006604312:icl */
> + if (!needs_scalerclk_wa(dev_priv, old_crtc_state) &&
> + needs_scalerclk_wa(dev_priv, pipe_config))
> + icl_wa_scalerclkgating(dev_priv, crtc->pipe, true);
>
> /*
>* Vblank time updates from the shadow to live plane control
> register
signature.asc
Description: This is a digitally signed message part
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Do not enable FEC without DSC
On Thu, Apr 11, 2019 at 12:11:42PM -0700, Manasi Navare wrote:
> On Tue, Mar 26, 2019 at 04:49:02PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Currently we enable FEC even when DSC is no used. While that is
> > theoretically valid supposedly there isn't much of a benefit from
> > this. But more importantly we do not account for the FEC link
> > bandwidth overhead (2.4%) in the non-DSC link bandwidth computations.
> > So the code may think we have enough bandwidth when we in fact
> > do not.
> >
> > Cc: Anusha Srivatsa
> > Cc: Manasi Navare
>
> There is a typo in the email address:
> manasi.d.nav...@intel.com
Thanks for the reminder. I already forgot about this and was about to
push without fixing it. Sadly it seems I had copy pasted it from the
same place to both of these patches, so one got pushed with the bad
address.
Hmm. Looks like this escaped into 5.0 already. Added cc:stable
and pushed to dinq. Thanks for the review.
>
> > Fixes: 240999cf339f ("i915/dp/fec: Add fec_enable to the crtc state.")
> > Signed-off-by: Ville Syrjälä
>
> Makes sense to me
>
> Reviewed-by: Manasi Navare
>
> Manasi
>
> > ---
> > drivers/gpu/drm/i915/intel_dp.c | 6 +++---
> > 1 file changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 326de12c3f44..bbf678561509 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -1925,6 +1925,9 @@ static int intel_dp_dsc_compute_config(struct
> > intel_dp *intel_dp,
> > int pipe_bpp;
> > int ret;
> >
> > + pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
> > + intel_dp_supports_fec(intel_dp, pipe_config);
> > +
> > if (!intel_dp_supports_dsc(intel_dp, pipe_config))
> > return -EINVAL;
> >
> > @@ -2168,9 +2171,6 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> > if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
> > return -EINVAL;
> >
> > - pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
> > - intel_dp_supports_fec(intel_dp, pipe_config);
> > -
> > ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
> > if (ret < 0)
> > return ret;
> > --
> > 2.19.2
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 6/6] drm/i915: Set DP min_bpp to 8*3 for non-RGB output formats
On Thu, 2019-04-11 at 21:27 +0300, Ville Syrjälä wrote:
> On Tue, Apr 09, 2019 at 02:04:01PM -0700, Dhinakaran Pandiyan wrote:
> > On Tue, 2019-04-09 at 23:38 +0300, Ville Syrjälä wrote:
> > > On Tue, Apr 09, 2019 at 01:28:18PM -0700, Dhinakaran Pandiyan
> > > wrote:
> > > > On Tue, 2019-03-26 at 16:25 +0200, Ville Syrjala wrote:
> > > > > From: Ville Syrjälä
> > > > >
> > > > > 6bpc is only legal for RGB and RAW pixel encodings. For the
> > > > > rest
> > > > > the minimum is 8bpc. Set our lower limit accordingly.
> > > >
> > > > Patch doesn't apply anymore, got a conflict in intel_drv.h.
> > > >
> > > >
> > > > > Signed-off-by: Ville Syrjälä
> > > > > ---
> > > > > drivers/gpu/drm/i915/intel_dp.c | 10 +-
> > > > > drivers/gpu/drm/i915/intel_dp_mst.c | 2 +-
> > > > > drivers/gpu/drm/i915/intel_drv.h| 1 +
> > > > > 3 files changed, 11 insertions(+), 2 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > > > > b/drivers/gpu/drm/i915/intel_dp.c
> > > > > index 2aee526ed632..149fdfbcb343 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > > > @@ -2002,6 +2002,14 @@ static int
> > > > > intel_dp_dsc_compute_config(struct
> > > > > intel_dp
> > > > > *intel_dp,
> > > > > return 0;
> > > > > }
> > > > >
> > > > > +int intel_dp_min_bpp(const struct intel_crtc_state
> > > > > *crtc_state)
> > > > > +{
> > > > > + if (crtc_state->output_format ==
> > > > > INTEL_OUTPUT_FORMAT_RGB)
> > > > > + return 6 * 3;
> > > > > + else
> > > > > + return 8 * 3;
> > > >
> > > > Code matches spec, however I think there is a possibility of
> > > > min_bpp
> > > > becoming
> > > > greater than max_bpp. The max_bpc property allows user space to
> > > > set a value
> > > > of 6
> > > > and limits.min_bpp can become 24 because of the code above. Add
> > > > a check for
> > > > that
> > > > in compute_link_config()? Probably would mess up the
> > > > compute_config() loop
> > > > too.
> > >
> > > The code looks correct. Ie. should just end up with -EINVAL.
> >
> > Yup, it does now as I read it carefully again :)
> > Reviewed-by: Dhinakaran Pandiyan
>
> Ta. Pushed.
Late on jumping the train but dont we have to limit the range exposed
while attaching the "max bpc" as well in this case?
- Radhakrishna(RK) Sripada
>
> >
> > However, I don't like the fact we are hiding the detail that
> > min_bpp can be >
> > max_bpp. If someone decides add a link config optimization starting
> > from
> > min_bpp, it's easy to miss this detail.
>
> I guess I wouldn't object to an explicit check for this. As a bonus
> we could add a more descriptive debug message for this case.
>
> >
> > -DK
> >
> > >
> > > >
> > > >
> > > > > +}
> > > > > +
> > > > > static int
> > > > > intel_dp_compute_link_config(struct intel_encoder *encoder,
> > > > >struct intel_crtc_state
> > > > > *pipe_config,
> > > > > @@ -2025,7 +2033,7 @@ intel_dp_compute_link_config(struct
> > > > > intel_encoder
> > > > > *encoder,
> > > > > limits.min_lane_count = 1;
> > > > > limits.max_lane_count =
> > > > > intel_dp_max_lane_count(intel_dp);
> > > > >
> > > > > - limits.min_bpp = 6 * 3;
> > > > > + limits.min_bpp = intel_dp_min_bpp(pipe_config);
> > > > > limits.max_bpp = intel_dp_compute_bpp(intel_dp,
> > > > > pipe_config);
> > > > >
> > > > > if (intel_dp_is_edp(intel_dp) && intel_dp->edp_dpcd[0]
> > > > > < DP_EDP_14) {
> > > > > diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
> > > > > b/drivers/gpu/drm/i915/intel_dp_mst.c
> > > > > index 6d2af7cf48e6..79c229184873 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> > > > > @@ -119,7 +119,7 @@ static int
> > > > > intel_dp_mst_compute_config(struct
> > > > > intel_encoder *encoder,
> > > > > limits.min_lane_count =
> > > > > limits.max_lane_count =
> > > > > intel_dp_max_lane_count(intel_dp);
> > > > >
> > > > > - limits.min_bpp = 6 * 3;
> > > > > + limits.min_bpp = intel_dp_min_bpp(pipe_config);
> > > > > limits.max_bpp = pipe_config->pipe_bpp;
> > > > >
> > > > > intel_dp_adjust_compliance_config(intel_dp,
> > > > > pipe_config, );
> > > > > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > > > > b/drivers/gpu/drm/i915/intel_drv.h
> > > > > index e79954c6271c..13f1b0367287 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_drv.h
> > > > > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > > > > @@ -1919,6 +1919,7 @@ void
> > > > > intel_dp_adjust_compliance_config(struct
> > > > > intel_dp
> > > > > *intel_dp,
> > > > > struct
> > > > > link_config_limits *limits);
> > > > > bool intel_dp_limited_color_range(const struct
> > > > > intel_crtc_state
> > > > > *crtc_state,
> > > > > const struct
> > > > > drm_connector_state *conn_state);
> > >
Re: [Intel-gfx] [PATCH v2 00/22] GuC 32.0.3
Quoting Michal Wajdeczko (2019-04-11 09:44:14) > New GuC firmwares (for SKL, BXT, KBL, ICL) with updated ABI interface. It is worth mentioning the trybot run with i915.enable_guc=-1 turned up no problems. Looks like this series is ready, as is the fw release. https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_4129/ -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Call i915_sw_fence_fini on request cleanup
== Series Details == Series: drm/i915: Call i915_sw_fence_fini on request cleanup URL : https://patchwork.freedesktop.org/series/59340/ State : success == Summary == CI Bug Log - changes from CI_DRM_5913 -> Patchwork_12763 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/59340/revisions/1/mbox/ Known issues Here are the changes found in Patchwork_12763 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718] * igt@i915_selftest@live_execlists: - fi-apl-guc: NOTRUN -> INCOMPLETE [fdo#103927] / [fdo#109720] * igt@kms_force_connector_basic@force-edid: - fi-glk-dsi: NOTRUN -> SKIP [fdo#109271] +26 * igt@kms_force_connector_basic@force-load-detect: - fi-bxt-j4205: NOTRUN -> SKIP [fdo#109271] +47 * igt@kms_frontbuffer_tracking@basic: - fi-glk-dsi: NOTRUN -> FAIL [fdo#103167] * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence: - fi-byt-clapper: PASS -> FAIL [fdo#103191] * igt@kms_psr@primary_page_flip: - fi-apl-guc: NOTRUN -> SKIP [fdo#109271] +50 * igt@runner@aborted: - fi-apl-guc: NOTRUN -> FAIL [fdo#108622] / [fdo#109720] Possible fixes * igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size: - fi-glk-dsi: INCOMPLETE [fdo#103359] / [k.org#198133] -> PASS [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359 [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (47 -> 43) -- Additional (2): fi-bxt-j4205 fi-apl-guc Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bdw-samus fi-snb-2600 Build changes - * Linux: CI_DRM_5913 -> Patchwork_12763 CI_DRM_5913: 67eef5880fe95727f01e0ae2233218951bbf251a @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4943: 5941f371b0fe25084d4b1c49882faa8d41d44c9f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12763: 066023b50fe0f716eb23db1b152b80c1cc0ad142 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 066023b50fe0 drm/i915: Call i915_sw_fence_fini on request cleanup == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12763/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Disable read only ppgtt support for gen11
Quoting Rodrigo Vivi (2019-04-11 20:47:48) > On Thu, Apr 11, 2019 at 11:30:34AM +0300, Mika Kuoppala wrote: > > On gen11 writing to read only ppgtt page causes a gpu hang. > > This behaviour is different than with previous gen where > > read only ppgtt access is supported. On those, the write > > is just dropped without visible side effects. > > > > Disable ro ppgtt support on gen11 until a solution can > > be found to bring it into line with its predecessors. > > > > References: HSDES#1807136187 > > References: https://bugzilla.freedesktop.org/show_bug.cgi?id=108569 > > Cc: Chris Wilson > > Signed-off-by: Mika Kuoppala > > --- > > drivers/gpu/drm/i915/i915_gem_gtt.c | 9 +++-- > > 1 file changed, 7 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c > > b/drivers/gpu/drm/i915/i915_gem_gtt.c > > index 736c845eb77f..caae8cdafc1a 100644 > > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > > @@ -1548,8 +1548,13 @@ static struct i915_hw_ppgtt > > *gen8_ppgtt_create(struct drm_i915_private *i915) > > > > ppgtt_init(i915, ppgtt); > > > > - /* From bdw, there is support for read-only pages in the PPGTT. */ > > - ppgtt->vm.has_read_only = true; > > + /* > > + * From bdw, there is hw support for read-only pages in the PPGTT. > > + * > > + * Gen11 has HSDES#:1807136187 unresolved. Disable ro support > > + * for now. > > + */ > > + ppgtt->vm.has_read_only = INTEL_GEN(i915) != 11; > > I believe it is safest to use < 11, no?! No. It's an issue in Icelake. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Disable read only ppgtt support for gen11
On Thu, Apr 11, 2019 at 11:30:34AM +0300, Mika Kuoppala wrote: > On gen11 writing to read only ppgtt page causes a gpu hang. > This behaviour is different than with previous gen where > read only ppgtt access is supported. On those, the write > is just dropped without visible side effects. > > Disable ro ppgtt support on gen11 until a solution can > be found to bring it into line with its predecessors. > > References: HSDES#1807136187 > References: https://bugzilla.freedesktop.org/show_bug.cgi?id=108569 > Cc: Chris Wilson > Signed-off-by: Mika Kuoppala > --- > drivers/gpu/drm/i915/i915_gem_gtt.c | 9 +++-- > 1 file changed, 7 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c > b/drivers/gpu/drm/i915/i915_gem_gtt.c > index 736c845eb77f..caae8cdafc1a 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > @@ -1548,8 +1548,13 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct > drm_i915_private *i915) > > ppgtt_init(i915, ppgtt); > > - /* From bdw, there is support for read-only pages in the PPGTT. */ > - ppgtt->vm.has_read_only = true; > + /* > + * From bdw, there is hw support for read-only pages in the PPGTT. > + * > + * Gen11 has HSDES#:1807136187 unresolved. Disable ro support > + * for now. > + */ > + ppgtt->vm.has_read_only = INTEL_GEN(i915) != 11; I believe it is safest to use < 11, no?! > > /* There are only few exceptions for gen >=6. chv and bxt. >* And we are not sure about the latter so play safe for now. > -- > 2.17.1 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for GuC 32.0.3 (rev2)
== Series Details == Series: GuC 32.0.3 (rev2) URL : https://patchwork.freedesktop.org/series/58760/ State : success == Summary == CI Bug Log - changes from CI_DRM_5913 -> Patchwork_12762 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/58760/revisions/2/mbox/ Known issues Here are the changes found in Patchwork_12762 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_cs_nop@fork-compute0: - fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] +18 * igt@i915_selftest@live_contexts: - fi-bdw-gvtdvm: PASS -> DMESG-FAIL [fdo#110235 ] * igt@i915_selftest@live_evict: - fi-bsw-kefka: PASS -> DMESG-WARN [fdo#107709] * igt@kms_force_connector_basic@force-edid: - fi-glk-dsi: NOTRUN -> SKIP [fdo#109271] +26 * igt@kms_force_connector_basic@force-load-detect: - fi-bxt-j4205: NOTRUN -> SKIP [fdo#109271] +47 * igt@kms_frontbuffer_tracking@basic: - fi-glk-dsi: NOTRUN -> FAIL [fdo#103167] * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c-frame-sequence: - fi-glk-dsi: NOTRUN -> FAIL [fdo#103191] * igt@kms_psr@primary_page_flip: - fi-apl-guc: NOTRUN -> SKIP [fdo#109271] +50 * igt@runner@aborted: - fi-bsw-kefka: NOTRUN -> FAIL [fdo#107709] Possible fixes * igt@i915_module_load@reload: - fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS * igt@i915_selftest@live_hangcheck: - fi-bxt-dsi: INCOMPLETE [fdo#103927] -> PASS * igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size: - fi-glk-dsi: INCOMPLETE [fdo#103359] / [k.org#198133] -> PASS * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-byt-clapper: FAIL [fdo#103191] -> PASS Warnings * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: DMESG-WARN [fdo#103841] -> DMESG-FAIL [fdo#109627] [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359 [fdo#103841]: https://bugs.freedesktop.org/show_bug.cgi?id=103841 [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#107709]: https://bugs.freedesktop.org/show_bug.cgi?id=107709 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109627]: https://bugs.freedesktop.org/show_bug.cgi?id=109627 [fdo#110235 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110235 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (47 -> 43) -- Additional (2): fi-bxt-j4205 fi-apl-guc Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-hsw-peppy fi-byt-squawks fi-bdw-samus Build changes - * Linux: CI_DRM_5913 -> Patchwork_12762 CI_DRM_5913: 67eef5880fe95727f01e0ae2233218951bbf251a @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4943: 5941f371b0fe25084d4b1c49882faa8d41d44c9f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12762: 8bd9521867836937549a4d4b72f735d385bb0087 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 8bd952186783 HAX: prevent CI failures on configs with forced GuC submission edd687854841 drm/i915/huc: Define HuC firmware version for Icelake bf1a92842ba2 drm/i915/guc: Define GuC firmware version for Icelake c61df035872b drm/i915/guc: Enable GuC CTB communication on Gen11 75a2791cf5bb drm/i915/guc: Update GuC CTB response definition 57a4e4be8218 drm/i915/guc: Correctly handle GuC interrupts on Gen11 0ea3f7c5f1b5 drm/i915/guc: Create vfuncs for the GuC interrupts control functions 2e43a34be819 drm/i915/huc: New HuC status register for Gen11 32c33ce38ca9 drm/i915/guc: New GuC scratch registers for Gen11 ef7df7d843dd drm/i915/guc: New GuC interrupt register for Gen11 c46cc04b9b27 drm/i915/guc: Treat GuC initialization failure as -EIO cf9605715387 drm/i915/guc: Reset GuC ADS during sanitize f91d28b80f67 drm/i915/guc: Always ask GuC to update power domain states df04e5f15c1f drm/i915/guc: Update GuC ADS object definition 63112cd315b7 drm/i915/guc: Update GuC sample-forcewake command 0f4ccf8cdc79 drm/i915/guc: Update GuC sleep status values 6250e65c0ecd drm/i915/guc: Update GuC boot parameters 69f77dbb1de2 drm/i915/guc: Update GuC firmware CSS header 67b80c97ecfd drm/i915/guc: Update GuC firmware versions and names 87fb28b4c504 drm/i915/guc: Simplify preparation of GuC parameter block 5c9246394466 drm/i915/guc: Don't allow GuC submission c9aa87194114 drm/i915/guc: Change platform default GuC mode == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12762/ ___ Intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for GuC 32.0.3 (rev2)
== Series Details == Series: GuC 32.0.3 (rev2) URL : https://patchwork.freedesktop.org/series/58760/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/guc: Change platform default GuC mode Okay! Commit: drm/i915/guc: Don't allow GuC submission Okay! Commit: drm/i915/guc: Simplify preparation of GuC parameter block Okay! Commit: drm/i915/guc: Update GuC firmware versions and names Okay! Commit: drm/i915/guc: Update GuC firmware CSS header Okay! Commit: drm/i915/guc: Update GuC boot parameters Okay! Commit: drm/i915/guc: Update GuC sleep status values Okay! Commit: drm/i915/guc: Update GuC sample-forcewake command Okay! Commit: drm/i915/guc: Update GuC ADS object definition Okay! Commit: drm/i915/guc: Always ask GuC to update power domain states Okay! Commit: drm/i915/guc: Reset GuC ADS during sanitize Okay! Commit: drm/i915/guc: Treat GuC initialization failure as -EIO Okay! Commit: drm/i915/guc: New GuC interrupt register for Gen11 Okay! Commit: drm/i915/guc: New GuC scratch registers for Gen11 Okay! Commit: drm/i915/huc: New HuC status register for Gen11 Okay! Commit: drm/i915/guc: Create vfuncs for the GuC interrupts control functions -drivers/gpu/drm/i915/selftests/../i915_drv.h:3616:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3638:16: warning: expression using sizeof(void) Commit: drm/i915/guc: Correctly handle GuC interrupts on Gen11 +drivers/gpu/drm/i915/i915_irq.c:1003:20: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_irq.c:1003:20: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_irq.c:1003:20: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_irq.c:1003:20: warning: expression using sizeof(void) -drivers/gpu/drm/i915/selftests/../i915_drv.h:3638:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3642:16: warning: expression using sizeof(void) Commit: drm/i915/guc: Update GuC CTB response definition Okay! Commit: drm/i915/guc: Enable GuC CTB communication on Gen11 Okay! Commit: drm/i915/guc: Define GuC firmware version for Icelake Okay! Commit: drm/i915/huc: Define HuC firmware version for Icelake Okay! Commit: HAX: prevent CI failures on configs with forced GuC submission Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Do not enable FEC without DSC
On Tue, Mar 26, 2019 at 04:49:02PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Currently we enable FEC even when DSC is no used. While that is
> theoretically valid supposedly there isn't much of a benefit from
> this. But more importantly we do not account for the FEC link
> bandwidth overhead (2.4%) in the non-DSC link bandwidth computations.
> So the code may think we have enough bandwidth when we in fact
> do not.
>
> Cc: Anusha Srivatsa
> Cc: Manasi Navare
There is a typo in the email address:
manasi.d.nav...@intel.com
> Fixes: 240999cf339f ("i915/dp/fec: Add fec_enable to the crtc state.")
> Signed-off-by: Ville Syrjälä
Makes sense to me
Reviewed-by: Manasi Navare
Manasi
> ---
> drivers/gpu/drm/i915/intel_dp.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 326de12c3f44..bbf678561509 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1925,6 +1925,9 @@ static int intel_dp_dsc_compute_config(struct intel_dp
> *intel_dp,
> int pipe_bpp;
> int ret;
>
> + pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
> + intel_dp_supports_fec(intel_dp, pipe_config);
> +
> if (!intel_dp_supports_dsc(intel_dp, pipe_config))
> return -EINVAL;
>
> @@ -2168,9 +2171,6 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
> return -EINVAL;
>
> - pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
> - intel_dp_supports_fec(intel_dp, pipe_config);
> -
> ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
> if (ret < 0)
> return ret;
> --
> 2.19.2
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Disable read only ppgtt support for gen11
== Series Details == Series: drm/i915: Disable read only ppgtt support for gen11 URL : https://patchwork.freedesktop.org/series/59323/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5912 -> Patchwork_12761 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12761 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12761, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/59323/revisions/1/mbox/ Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12761: ### IGT changes ### Possible regressions * igt@gem_render_tiled_blits@basic: - fi-icl-y: NOTRUN -> INCOMPLETE Known issues Here are the changes found in Patchwork_12761 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_basic@basic-bsd2: - fi-icl-y: NOTRUN -> SKIP [fdo#109276] +7 * igt@gem_exec_parse@basic-rejected: - fi-icl-y: NOTRUN -> SKIP [fdo#109289] +1 * igt@i915_selftest@live_hangcheck: - fi-bxt-dsi: PASS -> INCOMPLETE [fdo#103927] * igt@kms_busy@basic-flip-c: - fi-byt-j1900: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_chamelium@hdmi-crc-fast: - fi-byt-j1900: NOTRUN -> SKIP [fdo#109271] +52 * igt@kms_chamelium@hdmi-edid-read: - fi-hsw-peppy: NOTRUN -> SKIP [fdo#109271] +46 * igt@kms_force_connector_basic@force-edid: - fi-glk-dsi: NOTRUN -> SKIP [fdo#109271] +26 * igt@kms_frontbuffer_tracking@basic: - fi-hsw-peppy: NOTRUN -> DMESG-FAIL [fdo#102614] / [fdo#107814] - fi-glk-dsi: NOTRUN -> FAIL [fdo#103167] * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-byt-clapper: PASS -> FAIL [fdo#103191] Possible fixes * igt@gem_ctx_switch@basic-default: - fi-icl-y: INCOMPLETE [fdo#108569] -> PASS * igt@i915_selftest@live_hangcheck: - fi-skl-iommu: INCOMPLETE [fdo#108602] / [fdo#108744] -> PASS * igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size: - fi-glk-dsi: INCOMPLETE [fdo#103359] / [k.org#198133] -> PASS [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614 [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359 [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#107814]: https://bugs.freedesktop.org/show_bug.cgi?id=107814 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602 [fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (50 -> 43) -- Additional (2): fi-byt-j1900 fi-hsw-peppy Missing(9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-icl-u2 fi-bsw-cyan fi-snb-2520m fi-ctg-p8600 fi-bdw-samus Build changes - * Linux: CI_DRM_5912 -> Patchwork_12761 CI_DRM_5912: d7c1889b2e971f44d10c69ec204991f3264d2412 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4943: 5941f371b0fe25084d4b1c49882faa8d41d44c9f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12761: 4df3122417ae11d385696ad010b40e2f16a38b14 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 4df3122417ae drm/i915: Disable read only ppgtt support for gen11 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12761/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Clean up DSC vs. not bpp handling
On Tue, Mar 26, 2019 at 09:02:36AM -0700, Manasi Navare wrote:
> On Tue, Mar 26, 2019 at 04:49:03PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > No point in duplicating all this code when we can just
> > use a variable top hold the output bpp (the only thing
> > that differs between the two branches).
> >
> > Cc: Anusha Srivatsa
> > Cc: Manasi Navare
> > Signed-off-by: Ville Syrjälä
>
> This clean up looks good, thank you for catching this and cleaning it up.
>
> Reviewed-by: Manasi Navare
Patch 2 pushed. Thanks for the review. Patch 1 could still use a rubber
stamp...
>
> Manasi
>
> > ---
> > drivers/gpu/drm/i915/intel_dp.c | 27 ---
> > 1 file changed, 12 insertions(+), 15 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index bbf678561509..b26007a32318 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -2126,7 +2126,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> > to_intel_digital_connector_state(conn_state);
> > bool constant_n = drm_dp_has_quirk(_dp->desc,
> >DP_DPCD_QUIRK_CONSTANT_N);
> > - int ret;
> > + int ret, output_bpp;
> >
> > if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
> > pipe_config->has_pch_encoder = true;
> > @@ -2190,25 +2190,22 @@ intel_dp_compute_config(struct intel_encoder
> > *encoder,
> > intel_conn_state->broadcast_rgb ==
> > INTEL_BROADCAST_RGB_LIMITED;
> > }
> >
> > - if (!pipe_config->dsc_params.compression_enable)
> > - intel_link_compute_m_n(pipe_config->pipe_bpp,
> > - pipe_config->lane_count,
> > - adjusted_mode->crtc_clock,
> > - pipe_config->port_clock,
> > - _config->dp_m_n,
> > - constant_n);
> > + if (pipe_config->dsc_params.compression_enable)
> > + output_bpp = pipe_config->dsc_params.compressed_bpp;
> > else
> > - intel_link_compute_m_n(pipe_config->dsc_params.compressed_bpp,
> > - pipe_config->lane_count,
> > - adjusted_mode->crtc_clock,
> > - pipe_config->port_clock,
> > - _config->dp_m_n,
> > - constant_n);
> > + output_bpp = pipe_config->pipe_bpp;
> > +
> > + intel_link_compute_m_n(output_bpp,
> > + pipe_config->lane_count,
> > + adjusted_mode->crtc_clock,
> > + pipe_config->port_clock,
> > + _config->dp_m_n,
> > + constant_n);
> >
> > if (intel_connector->panel.downclock_mode != NULL &&
> > dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
> > pipe_config->has_drrs = true;
> > - intel_link_compute_m_n(pipe_config->pipe_bpp,
> > + intel_link_compute_m_n(output_bpp,
> >pipe_config->lane_count,
> >
> > intel_connector->panel.downclock_mode->clock,
> >pipe_config->port_clock,
> > --
> > 2.19.2
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 6/6] drm/i915: Set DP min_bpp to 8*3 for non-RGB output formats
On Tue, Apr 09, 2019 at 02:04:01PM -0700, Dhinakaran Pandiyan wrote:
> On Tue, 2019-04-09 at 23:38 +0300, Ville Syrjälä wrote:
> > On Tue, Apr 09, 2019 at 01:28:18PM -0700, Dhinakaran Pandiyan wrote:
> > > On Tue, 2019-03-26 at 16:25 +0200, Ville Syrjala wrote:
> > > > From: Ville Syrjälä
> > > >
> > > > 6bpc is only legal for RGB and RAW pixel encodings. For the rest
> > > > the minimum is 8bpc. Set our lower limit accordingly.
> > >
> > > Patch doesn't apply anymore, got a conflict in intel_drv.h.
> > >
> > >
> > > > Signed-off-by: Ville Syrjälä
> > > > ---
> > > > drivers/gpu/drm/i915/intel_dp.c | 10 +-
> > > > drivers/gpu/drm/i915/intel_dp_mst.c | 2 +-
> > > > drivers/gpu/drm/i915/intel_drv.h| 1 +
> > > > 3 files changed, 11 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > > > b/drivers/gpu/drm/i915/intel_dp.c
> > > > index 2aee526ed632..149fdfbcb343 100644
> > > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > > @@ -2002,6 +2002,14 @@ static int intel_dp_dsc_compute_config(struct
> > > > intel_dp
> > > > *intel_dp,
> > > > return 0;
> > > > }
> > > >
> > > > +int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state)
> > > > +{
> > > > + if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
> > > > + return 6 * 3;
> > > > + else
> > > > + return 8 * 3;
> > >
> > > Code matches spec, however I think there is a possibility of min_bpp
> > > becoming
> > > greater than max_bpp. The max_bpc property allows user space to set a
> > > value
> > > of 6
> > > and limits.min_bpp can become 24 because of the code above. Add a check
> > > for
> > > that
> > > in compute_link_config()? Probably would mess up the compute_config() loop
> > > too.
> >
> > The code looks correct. Ie. should just end up with -EINVAL.
> Yup, it does now as I read it carefully again :)
> Reviewed-by: Dhinakaran Pandiyan
Ta. Pushed.
>
> However, I don't like the fact we are hiding the detail that min_bpp can be >
> max_bpp. If someone decides add a link config optimization starting from
> min_bpp, it's easy to miss this detail.
I guess I wouldn't object to an explicit check for this. As a bonus
we could add a more descriptive debug message for this case.
>
> -DK
>
> >
> > >
> > >
> > > > +}
> > > > +
> > > > static int
> > > > intel_dp_compute_link_config(struct intel_encoder *encoder,
> > > > struct intel_crtc_state *pipe_config,
> > > > @@ -2025,7 +2033,7 @@ intel_dp_compute_link_config(struct intel_encoder
> > > > *encoder,
> > > > limits.min_lane_count = 1;
> > > > limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
> > > >
> > > > - limits.min_bpp = 6 * 3;
> > > > + limits.min_bpp = intel_dp_min_bpp(pipe_config);
> > > > limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
> > > >
> > > > if (intel_dp_is_edp(intel_dp) && intel_dp->edp_dpcd[0] <
> > > > DP_EDP_14) {
> > > > diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
> > > > b/drivers/gpu/drm/i915/intel_dp_mst.c
> > > > index 6d2af7cf48e6..79c229184873 100644
> > > > --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> > > > +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> > > > @@ -119,7 +119,7 @@ static int intel_dp_mst_compute_config(struct
> > > > intel_encoder *encoder,
> > > > limits.min_lane_count =
> > > > limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
> > > >
> > > > - limits.min_bpp = 6 * 3;
> > > > + limits.min_bpp = intel_dp_min_bpp(pipe_config);
> > > > limits.max_bpp = pipe_config->pipe_bpp;
> > > >
> > > > intel_dp_adjust_compliance_config(intel_dp, pipe_config,
> > > > );
> > > > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > > > b/drivers/gpu/drm/i915/intel_drv.h
> > > > index e79954c6271c..13f1b0367287 100644
> > > > --- a/drivers/gpu/drm/i915/intel_drv.h
> > > > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > > > @@ -1919,6 +1919,7 @@ void intel_dp_adjust_compliance_config(struct
> > > > intel_dp
> > > > *intel_dp,
> > > >struct link_config_limits
> > > > *limits);
> > > > bool intel_dp_limited_color_range(const struct intel_crtc_state
> > > > *crtc_state,
> > > > const struct drm_connector_state
> > > > *conn_state);
> > > > +int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state);
> > > > bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
> > > >i915_reg_t dp_reg, enum port port,
> > > >enum pipe *pipe);
> >
> >
--
Ville Syrjälä
Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PULL] gvt-fixes
On Thu, Apr 11, 2019 at 02:49:10PM +0800, Zhenyu Wang wrote: > > Hi, > > This includes one vGPU display plane size regression fix, > one for preventing use-after-free in ppgtt shadow free function > and another warning fix for iomem access annotation. pulled, thanks! > > Thanks. > -- > The following changes since commit cf9ed66671ec5f6cacc7b6efbad9d7c9e5e31776: > > drm/i915/gvt: Fix kerneldoc typo for intel_vgpu_emulate_hotplug (2019-04-04 > 08:45:45 +0800) > > are available in the Git repository at: > > https://github.com/intel/gvt-linux.git tags/gvt-fixes-2019-04-11 > > for you to fetch changes up to cd7879f79f83aec4bb13f0f823f323911dc5397b: > > drm/i915/gvt: Roundup fb->height into tile's height at calucation fb->size > (2019-04-11 11:09:53 +0800) > > > gvt-fixes-2019-04-11 > > - Fix sparse warning on iomem usage (Chris) > - Prevent use-after-free for ppgtt shadow table free (Chris) > - Fix display plane size regression for tiled surface (Xiong) > > > Chris Wilson (2): > drm/i915/gvt: Annotate iomem usage > drm/i915/gvt: Prevent use-after-free in ppgtt_free_all_spt() > > Xiong Zhang (1): > drm/i915/gvt: Roundup fb->height into tile's height at calucation > fb->size > > drivers/gpu/drm/i915/gvt/dmabuf.c | 9 ++--- > drivers/gpu/drm/i915/gvt/gtt.c| 12 +--- > drivers/gpu/drm/i915/gvt/kvmgt.c | 6 +++--- > 3 files changed, 18 insertions(+), 9 deletions(-) > > > -- > Open Source Technology Center, Intel ltd. > > $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915: Restore correct bxt_ddi_phy_calc_lane_lat_optim_mask() calculation
From: Ville Syrjälä
We are no longer calling bxt_ddi_phy_calc_lane_lat_optim_mask() when
intel{hdmi,dp}_compute_config() succeeds, and instead only call it
when those fail. This is fallout from the bool->int
.compute_config() conversion which failed to invert the return
value check before calling bxt_ddi_phy_calc_lane_lat_optim_mask().
Let's just replace it with an early bailout so that it's harder
to miss.
This restores the correct latency optim setting calculation
(which could fix some real failures), and avoids the
MISSING_CASE() from bxt_ddi_phy_calc_lane_lat_optim_mask()
after intel{hdmi,dp}_compute_config() has failed.
Cc: Lyude Paul
Fixes: 204474a6b859 ("drm/i915: Pass down rc in
intel_encoder->compute_config()")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109373
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_ddi.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 3ae55274056c..24f9106efcc6 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3857,14 +3857,16 @@ static int intel_ddi_compute_config(struct
intel_encoder *encoder,
ret = intel_hdmi_compute_config(encoder, pipe_config,
conn_state);
else
ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
+ if (ret)
+ return ret;
- if (IS_GEN9_LP(dev_priv) && ret)
+ if (IS_GEN9_LP(dev_priv))
pipe_config->lane_lat_optim_mask =
bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
- return ret;
+ return 0;
}
--
2.21.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v5 1/2] drm: Add detection of changing of edid on between suspend and resume
On Thu, 2019-04-11 at 17:36 +0300, Gwan-gyeong Mun wrote:
> The hotplug detection routine of drm_helper_hpd_irq_event() can
> detect
> changing of status of connector, but it can not detect changing of
> edid.
>
> Following scenario requires detection of changing of edid.
>
> 1) plug display device to a connector
> 2) system suspend
> 3) unplug 1)'s display device and plug the other display device to a
> connector
> 4) system resume
>
> It adds edid check routine when a connector status still remains as
> "connector_status_connected".
>
> v2: Add NULL check before comparing of EDIDs.
> v3: Make it as part of existing drm_helper_hpd_irq_event() (Stan,
> Mika)
> v4: Rebased
> v5: Use a cached edid property blob data of connector instead of
> adding
> a new detected_edid variable. (Maarten)
> Add an using of reference count for getting a cached edid
> property
> blob data. (Maarten)
>
> Testcase: igt/kms_chamelium/hdmi-edid-change-during-hibernate
> Testcase: igt/kms_chamelium/hdmi-edid-change-during-suspend
> Testcase: igt/kms_chamelium/dp-edid-change-during-hibernate
> Testcase: igt/kms_chamelium/dp-edid-change-during-suspend
>
> Signed-off-by: Gwan-gyeong Mun
> ---
> drivers/gpu/drm/drm_probe_helper.c | 34
> +-
> 1 file changed, 33 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/drm_probe_helper.c
> b/drivers/gpu/drm/drm_probe_helper.c
> index 6fd08e04b323..27ad7f3dabb7 100644
> --- a/drivers/gpu/drm/drm_probe_helper.c
> +++ b/drivers/gpu/drm/drm_probe_helper.c
> @@ -742,7 +742,16 @@ EXPORT_SYMBOL(drm_kms_helper_poll_fini);
> * panels.
> *
> * This helper function is useful for drivers which can't or don't
> track hotplug
> - * interrupts for each connector.
> + * interrupts for each connector. And it also supports a detection
> of changing
> + * of edid on between suspend and resume when a connector status
> still remains
> + * as "connector_status_connected".
> + *
> + * Following scenario requires detection of changing of edid.
> + * 1) plug display device to a connector
> + * 2) system suspend
> + * 3) unplug 1)'s display device and plug the other display device
> to a
> + * connector
> + * 4) system resume
> *
> * Drivers which support hotplug interrupts for each connector
> individually and
> * which have a more fine-grained detect logic should bypass this
> code and
> @@ -760,6 +769,7 @@ bool drm_helper_hpd_irq_event(struct drm_device
> *dev)
> struct drm_connector *connector;
> struct drm_connector_list_iter conn_iter;
> enum drm_connector_status old_status;
> + struct drm_property_blob *old_edid_blob_ptr;
> bool changed = false;
>
> if (!dev->mode_config.poll_enabled)
> @@ -774,6 +784,11 @@ bool drm_helper_hpd_irq_event(struct drm_device
> *dev)
>
> old_status = connector->status;
>
> + if (connector->edid_blob_ptr)
> + old_edid_blob_ptr =
> drm_property_blob_get(connector->edid_blob_ptr);
> + else
> + old_edid_blob_ptr = NULL;
> +
> connector->status = drm_helper_probe_detect(connector,
> NULL, false);
> DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s
> to %s\n",
> connector->base.id,
> @@ -782,6 +797,23 @@ bool drm_helper_hpd_irq_event(struct drm_device
> *dev)
> drm_get_connector_status_name(connector-
> >status));
> if (old_status != connector->status)
> changed = true;
> +
> + /* Check changing of edid when a connector status still
> remains
> + * as "connector_status_connected".
> + */
> + if (old_edid_blob_ptr && connector->edid_blob_ptr &&
I guess you don't need to check both old_edid_blob_ptr && connector-
>edid_blob_ptr here. Because if old_edid_blob_ptr is not NULL - it
means that connector->edid_blob_ptr was not NULL for sure. See the
condition you have added above.
I mean this one:
> + if (connector->edid_blob_ptr)
> + old_edid_blob_ptr =
> drm_property_blob_get(connector->edid_blob_ptr);
> + else
> + old_edid_blob_ptr = NULL;
So I would check only old_edid_blob_ptr for not being NULL here.
> + old_status == connector->status &&
> + old_status == connector_status_connected) {
> + if (memcmp(old_edid_blob_ptr->data,
> + connector->edid_blob_ptr->data,
> + old_edid_blob_ptr->length)) {
> + changed = true;
> + DRM_DEBUG_KMS("[CONNECTOR:%d:%s] edid
> updated\n",
> + connector->base.id,
> + connector->name);
> + }
> + }
> +
[Intel-gfx] [PULL] drm-misc-fixes
Hi Dave, Daniel, Here is a new drm-misc-fixes PR. thanks! maxime drm-misc-fixes-2019-04-11: - core: Make atomic_enable and disable optional for CRTC - dw-hdmi: Lower max frequency for the Allwinner H6, SCDC configuration improvements for older controller versions - omap: a fix for the CEC clock management policy The following changes since commit 9b39b013037fbfa8d4b999345d9e904d8a336fc2: drm/udl: add a release method and delay modeset teardown (2019-04-08 16:20:02 +1000) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-fixes-2019-04-11 for you to fetch changes up to 1a07a94b47b1f528f39c3e6187b5eaf02efe44ea: drm/sun4i: tcon top: Fix NULL/invalid pointer dereference in sun8i_tcon_top_un/bind (2019-04-08 10:30:23 +0200) - core: Make atomic_enable and disable optional for CRTC - dw-hdmi: Lower max frequency for the Allwinner H6, SCDC configuration improvements for older controller versions - omap: a fix for the CEC clock management policy Jernej Skrabec (1): drm/sun4i: DW HDMI: Lower max. supported rate for H6 Matteo Croce (1): drm/omap: fix typo Maxime Ripard (1): Merge drm/drm-fixes into drm-misc-fixes Neil Armstrong (2): drm/bridge: dw-hdmi: disable SCDC configuration for invalid setups Revert "Documentation/gpu/meson: Remove link to meson_canvas.c" Ondrej Jirman (1): drm/sun4i: tcon top: Fix NULL/invalid pointer dereference in sun8i_tcon_top_un/bind Rodrigo Siqueira (1): drm/atomic-helper: Make atomic_enable/disable crtc callbacks optional Sean Paul (1): Documentation/gpu/meson: Remove link to meson_canvas.c Tony Lindgren (1): drm/omap: hdmi4_cec: Fix CEC clock handling for PM drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 34 +++ drivers/gpu/drm/drm_atomic_helper.c | 5 ++--- drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c | 26 --- drivers/gpu/drm/omapdrm/dss/hdmi4_core.c | 2 +- drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 9 ++-- drivers/gpu/drm/sun4i/sun8i_tcon_top.c| 5 +++-- include/drm/drm_modeset_helper_vtables.h | 4 7 files changed, 66 insertions(+), 19 deletions(-) -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [igt-dev] [RFT i-g-t 6/6] test: perf_pmu: use the gem_engine_topology library
On Thu, Apr 11, 2019 at 02:40:45PM +0100, Chris Wilson wrote:
> Quoting Andi Shyti (2019-04-11 14:01:01)
> > On Thu, Apr 11, 2019 at 01:32:03PM +0100, Chris Wilson wrote:
> > > Quoting Tvrtko Ursulin (2019-04-11 13:26:54)
> > > > From: Andi Shyti
> > > >
> > > > Replace the legacy for_each_engine* defines with the ones
> > > > implemented in the gem_engine_topology library.
> > > >
> > > > Use whenever possible gem_engine_can_store_dword() that checks
> > > > class instead of flags.
> > > >
> > > > Now the __for_each_engine_class_instance and
> > > > for_each_engine_class_instance are unused, remove them.
> > > >
> > > > Suggested-by: Tvrtko Ursulin
> > > > Signed-off-by: Andi Shyti
> > > > Cc: Tvrtko Ursulin
> > > > Reviewed-by: Tvrtko Ursulin
> > >
> > > I see a lot of new gem_context_create(), but not gem_require_contexts().
> >
> > gem_require_contexts() should go on top of engine_topology.
>
> engine_topology shouldn't require contexts per se, as we should be able
> to quite happily modify the engine map for Pineview. To what purpose,
> we do not ask!
>
> Just be careful you don't legacy tests.
I created a helper to avoid initializing the whole "think".
Tvrtko, indeed at some point calls "init_engine_list".
The helper looks like this:
+int64_t gem_map_all_engines(int fd)
+{
+ DEFINE_CONTEXT_PARAM(engines, param, 0, GEM_MAX_ENGINES);
+ struct intel_engine_data engine_data = { };
/* here is where I would add gem_require_contexts() */
+ param.ctx_id = gem_context_create(fd);
+
+ if (gem_topology_get_param(fd, ) > 0 && !param.size) {
+ query_engine_list(fd, _data);
+ ctx_map_engines(fd, _data, );
+ }
+
+ return param.ctx_id;
+}
and of course there is an unmap_engines that just deletes the
context.
Maybe such a helper is not required in the new world, but it can
be useful for legacy tests.
Andi
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [igt-dev] [RFT i-g-t 6/6] test: perf_pmu: use the gem_engine_topology library
On 11/04/2019 14:50, Chris Wilson wrote: Quoting Tvrtko Ursulin (2019-04-11 13:53:24) On 11/04/2019 13:32, Chris Wilson wrote: Quoting Tvrtko Ursulin (2019-04-11 13:26:54) From: Andi Shyti Replace the legacy for_each_engine* defines with the ones implemented in the gem_engine_topology library. Use whenever possible gem_engine_can_store_dword() that checks class instead of flags. Now the __for_each_engine_class_instance and for_each_engine_class_instance are unused, remove them. Suggested-by: Tvrtko Ursulin Signed-off-by: Andi Shyti Cc: Tvrtko Ursulin Reviewed-by: Tvrtko Ursulin I see a lot of new gem_context_create(), but not gem_require_contexts(). Problem is __for_each_physical_engine modifies the default context so tests under that iterator can't keep using I915_EXEC_RENDER. It was perhaps a knee-jerk reaction to make them create their own context as a workaround. From the looks of the tests affected, they all should support contexts. I would be more concerned if the basic busyness checking tests grew a new dependency. Basic busyness ones have not, but the ones I fixed up by making them create a context have. Which is fixable with below. Failures are only with gem_wait/basic-*-all, so I suspect something's off in igt_dummyload.c. Will see what happens with the debugs added. Operating on the default context, should be fine though. May require an operation to reset in case a previous subtest failed, which is a downside. Should we have a helper after all to get eb flags for given class:instance? I think resist/delay as much as possible. In 3 months time we can sweep away any evidence of the old ways, and only the explicit legacy ABI tests need concern themselves with BSD | BSD2 ;) perf_pmu tests which I added context_create to open PMU for rcs:0 and submit batches to I915_EXEC_RENDER. Well alternative to the helper could be to change them to submit to I915_EXEC_DEFAULT and rely on context map to always have rcs:0 at index 0. Which could even be passable. If the promise is broken the tests will fail to let us know. Okay with this alternative hack? Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5 2/2] drm/i915: Add a missed update of edid property of drm connector
After suspend/resume process, hotplug detection is handled by i915_hpd_poll_init_work() workqueue. While intel_hdmi_detect() or intel_dp_detect() are called, intel_hdmi_set_edid() or intel_dp_set_edid() only update an internal detect_edid variable of intel_connector. A missed update of edid property of drm_connector leads incorrect behavior of drm_helper_hpd_irq_event() on below testcases. It adds a missed update of edid property of drm connector and updates drm edid modes, while i915_hpd_poll_init_work() workqueue works. Testcase: igt/kms_chamelium/hdmi-edid-change-during-hibernate Testcase: igt/kms_chamelium/hdmi-edid-change-during-suspend Testcase: igt/kms_chamelium/dp-edid-change-during-hibernate Testcase: igt/kms_chamelium/dp-edid-change-during-suspend Signed-off-by: Gwan-gyeong Mun --- drivers/gpu/drm/i915/intel_dp.c | 1 + drivers/gpu/drm/i915/intel_hdmi.c | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index c4e36759a756..0301e58495b4 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -5379,6 +5379,7 @@ intel_dp_set_edid(struct intel_dp *intel_dp) intel_dp->has_audio = drm_detect_monitor_audio(edid); drm_dp_cec_set_edid(_dp->aux, edid); + intel_connector_update_modes(_connector->base, edid); } static void diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index e1005d7b75fd..b53360c4d0ef 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -2493,6 +2493,7 @@ intel_hdmi_set_edid(struct drm_connector *connector) } cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid); + intel_connector_update_modes(connector, edid); return connected; } -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5 1/2] drm: Add detection of changing of edid on between suspend and resume
The hotplug detection routine of drm_helper_hpd_irq_event() can detect
changing of status of connector, but it can not detect changing of edid.
Following scenario requires detection of changing of edid.
1) plug display device to a connector
2) system suspend
3) unplug 1)'s display device and plug the other display device to a
connector
4) system resume
It adds edid check routine when a connector status still remains as
"connector_status_connected".
v2: Add NULL check before comparing of EDIDs.
v3: Make it as part of existing drm_helper_hpd_irq_event() (Stan, Mika)
v4: Rebased
v5: Use a cached edid property blob data of connector instead of adding
a new detected_edid variable. (Maarten)
Add an using of reference count for getting a cached edid property
blob data. (Maarten)
Testcase: igt/kms_chamelium/hdmi-edid-change-during-hibernate
Testcase: igt/kms_chamelium/hdmi-edid-change-during-suspend
Testcase: igt/kms_chamelium/dp-edid-change-during-hibernate
Testcase: igt/kms_chamelium/dp-edid-change-during-suspend
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/drm_probe_helper.c | 34 +-
1 file changed, 33 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_probe_helper.c
b/drivers/gpu/drm/drm_probe_helper.c
index 6fd08e04b323..27ad7f3dabb7 100644
--- a/drivers/gpu/drm/drm_probe_helper.c
+++ b/drivers/gpu/drm/drm_probe_helper.c
@@ -742,7 +742,16 @@ EXPORT_SYMBOL(drm_kms_helper_poll_fini);
* panels.
*
* This helper function is useful for drivers which can't or don't track
hotplug
- * interrupts for each connector.
+ * interrupts for each connector. And it also supports a detection of changing
+ * of edid on between suspend and resume when a connector status still remains
+ * as "connector_status_connected".
+ *
+ * Following scenario requires detection of changing of edid.
+ * 1) plug display device to a connector
+ * 2) system suspend
+ * 3) unplug 1)'s display device and plug the other display device to a
+ * connector
+ * 4) system resume
*
* Drivers which support hotplug interrupts for each connector individually and
* which have a more fine-grained detect logic should bypass this code and
@@ -760,6 +769,7 @@ bool drm_helper_hpd_irq_event(struct drm_device *dev)
struct drm_connector *connector;
struct drm_connector_list_iter conn_iter;
enum drm_connector_status old_status;
+ struct drm_property_blob *old_edid_blob_ptr;
bool changed = false;
if (!dev->mode_config.poll_enabled)
@@ -774,6 +784,11 @@ bool drm_helper_hpd_irq_event(struct drm_device *dev)
old_status = connector->status;
+ if (connector->edid_blob_ptr)
+ old_edid_blob_ptr =
drm_property_blob_get(connector->edid_blob_ptr);
+ else
+ old_edid_blob_ptr = NULL;
+
connector->status = drm_helper_probe_detect(connector, NULL,
false);
DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to
%s\n",
connector->base.id,
@@ -782,6 +797,23 @@ bool drm_helper_hpd_irq_event(struct drm_device *dev)
drm_get_connector_status_name(connector->status));
if (old_status != connector->status)
changed = true;
+
+ /* Check changing of edid when a connector status still remains
+* as "connector_status_connected".
+*/
+ if (old_edid_blob_ptr && connector->edid_blob_ptr &&
+ old_status == connector->status &&
+ old_status == connector_status_connected) {
+ if (memcmp(old_edid_blob_ptr->data,
+ connector->edid_blob_ptr->data,
+ old_edid_blob_ptr->length)) {
+ changed = true;
+ DRM_DEBUG_KMS("[CONNECTOR:%d:%s] edid
updated\n",
+ connector->base.id,
+ connector->name);
+ }
+ }
+ drm_property_blob_put(old_edid_blob_ptr);
}
drm_connector_list_iter_end(_iter);
mutex_unlock(>mode_config.mutex);
--
2.21.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5 0/2] drm: Add detection of changing of edid on between suspend and resume
This patch series fix missed detection of changing of edid on between suspend and resume. First patch fixes drm_helper_hdp_irq_event() in order to fix a below use case. Following scenario requires detection of changing of edid. 1) plug display device to a connector 2) system suspend 3) unplug 1)'s display device and plug the other display device to a connector 4) system resume It adds edid check routine when a connector status still remains as "connector_status_connected". Second patch adds a missed update of edid property of drm connector on i915. v2: Add NULL check before comparing of EDIDs. v3: Make it as part of existing drm_helper_hpd_irq_event() (Stan, Mika) v4: Rebased v5: Use a cached edid property blob data of connector instead of adding a new detected_edid variable. (Maarten) Add an using of reference count for getting a cached edid property blob data. (Maarten) Testcase: igt/kms_chamelium/hdmi-edid-change-during-hibernate Testcase: igt/kms_chamelium/hdmi-edid-change-during-suspend Testcase: igt/kms_chamelium/dp-edid-change-during-hibernate Testcase: igt/kms_chamelium/dp-edid-change-during-suspend v1, v2: https://patchwork.freedesktop.org/series/47680/ v3: https://patchwork.freedesktop.org/series/49298/ v4: https://patchwork.freedesktop.org/series/57397/ Gwan-gyeong Mun (2): drm: Add detection of changing of edid on between suspend and resume drm/i915: Add a missed update of edid property of drm connector drivers/gpu/drm/drm_probe_helper.c | 34 +- drivers/gpu/drm/i915/intel_dp.c| 1 + drivers/gpu/drm/i915/intel_hdmi.c | 1 + 3 files changed, 35 insertions(+), 1 deletion(-) -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Don't call bxt_ddi_phy_calc_lane_lat_optim_mask() after failing intel_dp_compute_config()
From: Ville Syrjälä If intel_dp_compute_config() fails it may not have populated crtc_state->lane_count, which means bxt_ddi_phy_calc_lane_lat_optim_mask() may end up with a MISSING_CASE(). Bail out immediately if intel_dp_compute_config() (or the HDMI counterpart) fails so that we avoid triggeringing this MISSING_CASE warning. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109373 Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_ddi.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 3ae55274056c..3733e5858e08 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -3857,6 +3857,8 @@ static int intel_ddi_compute_config(struct intel_encoder *encoder, ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); else ret = intel_dp_compute_config(encoder, pipe_config, conn_state); + if (ret) + return ret; if (IS_GEN9_LP(dev_priv) && ret) pipe_config->lane_lat_optim_mask = @@ -3864,7 +3866,7 @@ static int intel_ddi_compute_config(struct intel_encoder *encoder, intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); - return ret; + return 0; } -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Suppress spurious combo PHY B warning
From: Ville Syrjälä
On ICL the DMC doesn't reinit combo PHY B so we should not warn
about its state being bogus during the display core uninit.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_combo_phy.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_combo_phy.c
b/drivers/gpu/drm/i915/intel_combo_phy.c
index 3d0271cebf99..2bf4359d7e41 100644
--- a/drivers/gpu/drm/i915/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/intel_combo_phy.c
@@ -239,7 +239,8 @@ void icl_combo_phys_uninit(struct drm_i915_private
*dev_priv)
for_each_combo_port_reverse(dev_priv, port) {
u32 val;
- if (!icl_combo_phy_verify_state(dev_priv, port))
+ if (port == PORT_A &&
+ !icl_combo_phy_verify_state(dev_priv, port))
DRM_WARN("Port %c combo PHY HW state changed
unexpectedly\n",
port_name(port));
--
2.21.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 03/12] drm/i915/fbdev: Move intel_fb_initial_config() to fbdev helper
Den 07.04.2019 18.52, skrev Noralf Trønnes: > It is generic code and having it in the helper will let other drivers > benefit from it. > > One change was necessary assuming this to be true: > INTEL_INFO(dev_priv)->num_pipes == dev->mode_config.num_crtc > > Suggested-by: Daniel Vetter > Cc: Jani Nikula > Cc: Joonas Lahtinen > Cc: Rodrigo Vivi > Cc: intel-gfx@lists.freedesktop.org > Signed-off-by: Noralf Trønnes > Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/drm_fb_helper.c| 194 - > drivers/gpu/drm/i915/intel_fbdev.c | 218 - > include/drm/drm_fb_helper.h| 23 --- > 3 files changed, 190 insertions(+), 245 deletions(-) > Applied to drm-misc-next. Noralf. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm: Add detection of changing of edid on between suspend and resume
On Mon, 2019-03-04 at 12:45 +0100, Maarten Lankhorst wrote: > Op 01-03-2019 om 11:01 schreef Gwan-gyeong Mun: > > The hotplug detection routine of drm_helper_hpd_irq_event() can > > detect > > changing of status of connector, but it can not detect changing of > > edid. > > > > Following scenario requires detection of changing of edid. > > > > 1) plug display device to a connector > > 2) system suspend > > 3) unplug 1)'s display device and plug the other display device to > > a > > connector > > 4) system resume > > > > It adds edid check routine when a connector status still remains as > > "connector_status_connected". > > > > v2: Add NULL check before comparing of EDIDs. > > v3: Make it as part of existing drm_helper_hpd_irq_event() (Stan, > > Mika) > > > > Testcase: igt/kms_chamelium/hdmi-edid-change-during-hibernate > > Testcase: igt/kms_chamelium/hdmi-edid-change-during-suspend > > Testcase: igt/kms_chamelium/dp-edid-change-during-hibernate > > Testcase: igt/kms_chamelium/dp-edid-change-during-suspend > > > > Signed-off-by: Gwan-gyeong Mun > > --- > > drivers/gpu/drm/drm_probe_helper.c | 29 > > - > > 1 file changed, 28 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/drm_probe_helper.c > > b/drivers/gpu/drm/drm_probe_helper.c > > index 6fd08e04b323..036a57d2b29e 100644 > > --- a/drivers/gpu/drm/drm_probe_helper.c > > +++ b/drivers/gpu/drm/drm_probe_helper.c > > @@ -742,7 +742,16 @@ EXPORT_SYMBOL(drm_kms_helper_poll_fini); > > * panels. > > * > > * This helper function is useful for drivers which can't or don't > > track hotplug > > - * interrupts for each connector. > > + * interrupts for each connector. And it also supports a detection > > of changing > > + * of edid on between suspend and resume when a connector status > > still remains > > + * as "connector_status_connected". > > + * > > + * Following scenario requires detection of changing of edid. > > + * 1) plug display device to a connector > > + * 2) system suspend > > + * 3) unplug 1)'s display device and plug the other display > > device to a > > + connector > > + * 4) system resume > > * > > * Drivers which support hotplug interrupts for each connector > > individually and > > * which have a more fine-grained detect logic should bypass this > > code and > > We already have a drm_connector_update_edid_property(), so we cache > edid already? > > Could we use that, perhaps reworking slightly how edids are updated > in i915? > Like drm_connector_update_property_test > Ok, I'll check a cached edid propery and will revise in order to use a cached edid property. > The current code feels like a hack. The fact we don't clear old_edid > or free it, makes me worry that your current patch will either use > old_edid after it'd freed, or have the old_edid leaked. > You are right, I missed the case which you mentioned. In the next patch, I'll handle an edid propery with drm_property_blob_get() and drm_property_blob_put(). Thank you for checking. Br, G.G. > ~Maarten > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Call i915_sw_fence_fini on request cleanup
Hi Chris,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v5.1-rc4 next-20190410]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Chris-Wilson/drm-i915-Call-i915_sw_fence_fini-on-request-cleanup/20190411-205947
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-allyesconfig (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64
All errors (new ones prefixed by >>):
drivers/gpu//drm/i915/i915_request.c: In function 'i915_fence_release':
>> drivers/gpu//drm/i915/i915_request.c:104:24: error: 'struct i915_request'
>> has no member named 'semaphore'
i915_sw_fence_fini(>semaphore);
^~
vim +104 drivers/gpu//drm/i915/i915_request.c
91
92 static void i915_fence_release(struct dma_fence *fence)
93 {
94 struct i915_request *rq = to_request(fence);
95
96 /*
97 * The request is put onto a RCU freelist (i.e. the address
98 * is immediately reused), mark the fences as being freed now.
99 * Otherwise the debugobjects for the fences are only marked as
100 * freed when the slab cache itself is freed, and so we would
get
101 * caught trying to reuse dead objects.
102 */
103 i915_sw_fence_fini(>submit);
> 104 i915_sw_fence_fini(>semaphore);
105
106 kmem_cache_free(global.slab_requests, rq);
107 }
108
---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
.config.gz
Description: application/gzip
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [igt-dev] [RFT i-g-t 6/6] test: perf_pmu: use the gem_engine_topology library
Quoting Tvrtko Ursulin (2019-04-11 13:53:24) > > On 11/04/2019 13:32, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2019-04-11 13:26:54) > >> From: Andi Shyti > >> > >> Replace the legacy for_each_engine* defines with the ones > >> implemented in the gem_engine_topology library. > >> > >> Use whenever possible gem_engine_can_store_dword() that checks > >> class instead of flags. > >> > >> Now the __for_each_engine_class_instance and > >> for_each_engine_class_instance are unused, remove them. > >> > >> Suggested-by: Tvrtko Ursulin > >> Signed-off-by: Andi Shyti > >> Cc: Tvrtko Ursulin > >> Reviewed-by: Tvrtko Ursulin > > > > I see a lot of new gem_context_create(), but not gem_require_contexts(). > > Problem is __for_each_physical_engine modifies the default context so > tests under that iterator can't keep using I915_EXEC_RENDER. > > It was perhaps a knee-jerk reaction to make them create their own > context as a workaround. From the looks of the tests affected, they all should support contexts. I would be more concerned if the basic busyness checking tests grew a new dependency. Operating on the default context, should be fine though. May require an operation to reset in case a previous subtest failed, which is a downside. > Should we have a helper after all to get eb flags for given class:instance? I think resist/delay as much as possible. In 3 months time we can sweep away any evidence of the old ways, and only the explicit legacy ABI tests need concern themselves with BSD | BSD2 ;) -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [igt-dev] [RFT i-g-t 6/6] test: perf_pmu: use the gem_engine_topology library
Quoting Andi Shyti (2019-04-11 14:01:01) > On Thu, Apr 11, 2019 at 01:32:03PM +0100, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2019-04-11 13:26:54) > > > From: Andi Shyti > > > > > > Replace the legacy for_each_engine* defines with the ones > > > implemented in the gem_engine_topology library. > > > > > > Use whenever possible gem_engine_can_store_dword() that checks > > > class instead of flags. > > > > > > Now the __for_each_engine_class_instance and > > > for_each_engine_class_instance are unused, remove them. > > > > > > Suggested-by: Tvrtko Ursulin > > > Signed-off-by: Andi Shyti > > > Cc: Tvrtko Ursulin > > > Reviewed-by: Tvrtko Ursulin > > > > I see a lot of new gem_context_create(), but not gem_require_contexts(). > > gem_require_contexts() should go on top of engine_topology. engine_topology shouldn't require contexts per se, as we should be able to quite happily modify the engine map for Pineview. To what purpose, we do not ask! Just be careful you don't legacy tests. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Switch back to an array of logical per-engine HW contexts
We switched to a tree of per-engine HW context to accommodate the
introduction of virtual engines. However, we plan to also support
multiple instances of the same engine within the GEM context, defeating
our use of the engine as a key to looking up the HW context. Just
allocate a logical per-engine instance and always use an index into the
ctx->engines[]. Later on, this ctx->engines[] may be replaced by a user
specified map.
v2: Add for_each_gem_engine() helper to iterator within the engines lock
v3: intel_context_create_request() helper
v4: s/unsigned long/unsigned int/ 4 billion engines is quite enough.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_context.c | 112 +++-
drivers/gpu/drm/i915/gt/intel_context.h | 27 +---
drivers/gpu/drm/i915/gt/intel_context_types.h | 2 -
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/mock_engine.c | 3 +-
drivers/gpu/drm/i915/gvt/scheduler.c | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 24 ++--
drivers/gpu/drm/i915/i915_gem_context.c | 124 --
drivers/gpu/drm/i915/i915_gem_context.h | 51 +++
drivers/gpu/drm/i915/i915_gem_context_types.h | 33 -
drivers/gpu/drm/i915/i915_gem_execbuffer.c| 70 +-
drivers/gpu/drm/i915/i915_perf.c | 76 ++-
drivers/gpu/drm/i915/i915_request.c | 15 +--
drivers/gpu/drm/i915/intel_guc_submission.c | 23 ++--
.../gpu/drm/i915/selftests/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/selftests/mock_context.c | 14 +-
16 files changed, 338 insertions(+), 242 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index 15ac99c5dd4a..5e506e648454 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -17,7 +17,7 @@ static struct i915_global_context {
struct kmem_cache *slab_ce;
} global;
-struct intel_context *intel_context_alloc(void)
+static struct intel_context *intel_context_alloc(void)
{
return kmem_cache_zalloc(global.slab_ce, GFP_KERNEL);
}
@@ -28,104 +28,17 @@ void intel_context_free(struct intel_context *ce)
}
struct intel_context *
-intel_context_lookup(struct i915_gem_context *ctx,
+intel_context_create(struct i915_gem_context *ctx,
struct intel_engine_cs *engine)
{
- struct intel_context *ce = NULL;
- struct rb_node *p;
-
- spin_lock(>hw_contexts_lock);
- p = ctx->hw_contexts.rb_node;
- while (p) {
- struct intel_context *this =
- rb_entry(p, struct intel_context, node);
-
- if (this->engine == engine) {
- GEM_BUG_ON(this->gem_context != ctx);
- ce = this;
- break;
- }
-
- if (this->engine < engine)
- p = p->rb_right;
- else
- p = p->rb_left;
- }
- spin_unlock(>hw_contexts_lock);
-
- return ce;
-}
-
-struct intel_context *
-__intel_context_insert(struct i915_gem_context *ctx,
- struct intel_engine_cs *engine,
- struct intel_context *ce)
-{
- struct rb_node **p, *parent;
- int err = 0;
-
- spin_lock(>hw_contexts_lock);
-
- parent = NULL;
- p = >hw_contexts.rb_node;
- while (*p) {
- struct intel_context *this;
-
- parent = *p;
- this = rb_entry(parent, struct intel_context, node);
-
- if (this->engine == engine) {
- err = -EEXIST;
- ce = this;
- break;
- }
-
- if (this->engine < engine)
- p = >rb_right;
- else
- p = >rb_left;
- }
- if (!err) {
- rb_link_node(>node, parent, p);
- rb_insert_color(>node, >hw_contexts);
- }
-
- spin_unlock(>hw_contexts_lock);
-
- return ce;
-}
-
-void __intel_context_remove(struct intel_context *ce)
-{
- struct i915_gem_context *ctx = ce->gem_context;
-
- spin_lock(>hw_contexts_lock);
- rb_erase(>node, >hw_contexts);
- spin_unlock(>hw_contexts_lock);
-}
-
-struct intel_context *
-intel_context_instance(struct i915_gem_context *ctx,
- struct intel_engine_cs *engine)
-{
- struct intel_context *ce, *pos;
-
- ce = intel_context_lookup(ctx, engine);
- if (likely(ce))
- return intel_context_get(ce);
+ struct intel_context *ce;
ce = intel_context_alloc();
if (!ce)
return ERR_PTR(-ENOMEM);
intel_context_init(ce, ctx, engine);
-
- pos = __intel_context_insert(ctx, engine, ce);
- if (unlikely(pos != ce)) /* Beaten! Use their HW context instead */
-
Re: [Intel-gfx] [PATCH 21/29] drm/i915: Switch back to an array of logical per-engine HW contexts
Quoting Tvrtko Ursulin (2019-04-11 14:05:19)
>
> On 10/04/2019 17:18, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-04-10 16:32:18)
> >> Yep as mentioned somewhere above. I definitely think another helper
> >> would help code base redability. Even if called unimaginatively as
> >> __i915_request_add.
> >
> > It is just these two (based on a quick grep).
> >
> > Maybe intel_context_create_request() ?
> >
> > Hmm, but isn't that what i915_request_create() is. Quiet!
>
> Why not __i915_request_add? i915_request_add would then be just wedged
> check calling __i915_request_add, no? (Going from memory.. might not be
> reliable.)
At the moment, we have:
__i915_request_create(): no timeline locking, no runtime-pm
i915_request_create(): no pinning, does timeline + runtime-pm
intel_context_create_request(): pin + call i915_request_create
igt_request_alloc(): lookup intel_context + call intel_context_create_request
I suppose there is some room in bringing i915_request_alloc() back from
the dead, but it's not the simple allocator one would expect from the
name. (igt_request_alloc is just for ease of recognition.)
Outside of igt_request_alloc(), there are two users for
intel_context_create_request() in my tree. One in
__intel_engine_record_defaults() and the other in
context_barrier_task().
For the in-kernel blitter tasks, we'll either be using a pinned kernel
context, or be shoehorning it into a pinned user context. Both should be
using i915_request_create() (as currently planned). And things like the
heartbeat and idle barriers, use the pinned kernel context.
Just to say intel_context_create_request() is the odd one out, and
deserves the longest name :)
> >>> +struct i915_gem_engines {
> >>> + struct rcu_work rcu;
> >>> + struct drm_i915_private *i915;
> >>> + unsigned long num_engines;
> >>
> >> unsigned int?
> >
> > Pointer before, array of pointers after, left an unsigned long hole.
> >
> > I was just filling the space.
>
> Well long makes me think there's a reason int is not enough. Which in
> this case there isn't.
And I thought you were planning for a busy future, full of little
engines :)
> So I would still go for an int regardless of the
> hole or not. There is nothing to be gained by filling space. Could even
> be worse if some instructions expand to longer opcodes. :)
Hmm, in the near future this becomes
struct i915_gem_engines {
struct rcu_head rcu;
unsigned long num_engines;
struct intel_context *engines[];
};
struct rcu_head is a pair of pointers, so that's still a pointer sized
hole. I give in. We'll only support 4 billion engines.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Avoiding reclaim tainting from runtime-pm debug
Chris Wilson writes:
> As intel_runtime_pm_get/_put may be called from any blockable context,
> we need to avoid allowing reclaim from our mallocs, as we need to
> avoid tainting any mutexes held by the callers (as they may themselves
> not allow for allocations as they are taken in the shrinker).
>
> <4> [435.339331] WARNING: possible circular locking dependency detected
> <4> [435.339364] 5.1.0-rc4-CI-Trybot_4116+ #1 Tainted: G U
> <4> [435.339395] --
> <4> [435.339426] gem_caching/1334 is trying to acquire lock:
> <4> [435.339456] 4505c39b (wakeref#3){+.+.}, at:
> intel_engine_pm_put+0x1b/0x40 [i915]
> <4> [435.339788]
> but task is already holding lock:
> <4> [435.339819] ee77b4ed (fs_reclaim){+.+.}, at:
> fs_reclaim_acquire.part.24+0x0/0x30
> <4> [435.339879]
> which lock already depends on the new lock.
>
> <4> [435.339918]
> the existing dependency chain (in reverse order) is:
> <4> [435.339952]
> -> #1 (fs_reclaim){+.+.}:
> <4> [435.339998]fs_reclaim_acquire.part.24+0x24/0x30
> <4> [435.340035]kmem_cache_alloc_trace+0x2a/0x290
> <4> [435.340311]__print_intel_runtime_pm_wakeref+0x24/0x160 [i915]
> <4> [435.340590]untrack_intel_runtime_pm_wakeref+0x16e/0x1d0 [i915]
> <4> [435.340869]intel_runtime_pm_put_unchecked+0xd/0x30 [i915]
> <4> [435.341147]__intel_wakeref_put_once+0x22/0x40 [i915]
> <4> [435.341508]i915_request_retire+0x477/0xaf0 [i915]
> <4> [435.341871]ring_retire_requests+0x86/0x160 [i915]
> <4> [435.342226]i915_retire_requests+0x58/0xc0 [i915]
> <4> [435.342576]retire_work_handler+0x5b/0x70 [i915]
> <4> [435.342615]process_one_work+0x245/0x610
> <4> [435.342646]worker_thread+0x37/0x380
> <4> [435.342679]kthread+0x119/0x130
> <4> [435.342714]ret_from_fork+0x3a/0x50
> <4> [435.342739]
> -> #0 (wakeref#3){+.+.}:
> <4> [435.342788]lock_acquire+0xa6/0x1c0
> <4> [435.342822]__mutex_lock+0x8c/0x960
> <4> [435.342853]atomic_dec_and_mutex_lock+0x33/0x50
> <4> [435.343151]intel_engine_pm_put+0x1b/0x40 [i915]
> <4> [435.343501]i915_request_retire+0x477/0xaf0 [i915]
> <4> [435.343851]ring_retire_requests+0x86/0x160 [i915]
> <4> [435.344202]i915_retire_requests+0x58/0xc0 [i915]
> <4> [435.344543]i915_gem_shrink+0xd8/0x5b0 [i915]
> <4> [435.344835]i915_drop_caches_set+0x17b/0x250 [i915]
> <4> [435.344877]simple_attr_write+0xb0/0xd0
> <4> [435.344911]full_proxy_write+0x51/0x80
> <4> [435.344943]vfs_write+0xbd/0x1b0
> <4> [435.344972]ksys_write+0x55/0xe0
> <4> [435.345002]do_syscall_64+0x55/0x190
> <4> [435.345040]entry_SYSCALL_64_after_hwframe+0x49/0xbe
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 8 +---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index e6d1e592225b..3107a742d8ad 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -162,7 +162,7 @@ static void cancel_intel_runtime_pm_wakeref(struct
> drm_i915_private *i915,
>rpm->debug.count, atomic_read(>wakeref_count))) {
> char *buf;
>
> - buf = kmalloc(PAGE_SIZE, GFP_KERNEL);
> + buf = kmalloc(PAGE_SIZE, GFP_NOWAIT | __GFP_NOWARN);
> if (!buf)
> return;
Ok we then just give up on printing the stack so no harm done
even if we increase our chances to fail the alloc. And there will
be a log entry apriori to indicate the unmatch regardless.
Reviewed-by: Mika Kuoppala
>
> @@ -198,7 +198,7 @@ __print_intel_runtime_pm_wakeref(struct drm_printer *p,
> unsigned long i;
> char *buf;
>
> - buf = kmalloc(PAGE_SIZE, GFP_KERNEL);
> + buf = kmalloc(PAGE_SIZE, GFP_NOWAIT | __GFP_NOWARN);
> if (!buf)
> return;
>
> @@ -282,7 +282,9 @@ void print_intel_runtime_pm_wakeref(struct
> drm_i915_private *i915,
> if (dbg.count <= alloc)
> break;
>
> - s = krealloc(dbg.owners, dbg.count * sizeof(*s), GFP_KERNEL);
> + s = krealloc(dbg.owners,
> + dbg.count * sizeof(*s),
> + GFP_NOWAIT | __GFP_NOWARN);
> if (!s)
> goto out;
>
> --
> 2.20.1
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 2/2] drm/i915/execlists: Always reset the context's RING registers
During reset, we try and stop the active ring. This has the consequence that we often clobber the RING registers within the context image. When we find an active request, we update the context image to rerun that request (if it was guilty, we replace the hanging user payload with NOPs). However, we were ignoring an active context if the request had completed, with the consequence that the next submission on that request would start with RING_HEAD==0 and not the tail of the previous request, causing all requests still in the ring to be rerun. Rare, but occasionally seen within CI where we would spot that the context seqno would reverse and complain that we were retiring an incomplete request. <0> [412.390350] -0 3d.s2 408373352us : __i915_request_submit: rcs0 fence 1e95b:3640 -> current 3638 <0> [412.390350] -0 3d.s2 408373353us : __i915_request_submit: rcs0 fence 1e95b:3642 -> current 3638 <0> [412.390350] -0 3d.s2 408373354us : __i915_request_submit: rcs0 fence 1e95b:3644 -> current 3638 <0> [412.390350] -0 3d.s2 408373354us : __i915_request_submit: rcs0 fence 1e95b:3646 -> current 3638 <0> [412.390350] -0 3d.s2 408373356us : __execlists_submission_tasklet: rcs0 in[0]: ctx=2.1, fence 1e95b:3646 (current 3638), prio=4 <0> [412.390350] i915_sel-46130 408373374us : __i915_request_commit: rcs0 fence 1e95b:3648 <0> [412.390350] i915_sel-46130d..1 408373377us : process_csb: rcs0 cs-irq head=2, tail=3 <0> [412.390350] i915_sel-46130d..1 408373377us : process_csb: rcs0 csb[3]: status=0x0001:0x, active=0x1 <0> [412.390350] i915_sel-46130d..1 408373378us : __i915_request_submit: rcs0 fence 1e95b:3648 -> current 3638 <0> [412.390350] -0 3..s1 408373378us : execlists_submission_tasklet: rcs0 awake?=1, active=5 <0> [412.390350] i915_sel-46130d..1 408373379us : __execlists_submission_tasklet: rcs0 in[0]: ctx=2.2, fence 1e95b:3648 (current 3638), prio=4 <0> [412.390350] i915_sel-46130 408373381us : i915_reset_engine: rcs0 flags=4 <0> [412.390350] i915_sel-46130 408373382us : execlists_reset_prepare: rcs0: depth<-0 <0> [412.390350] -0 3d.s2 408373390us : process_csb: rcs0 cs-irq head=3, tail=4 <0> [412.390350] -0 3d.s2 408373390us : process_csb: rcs0 csb[4]: status=0x8002:0x0002, active=0x1 <0> [412.390350] -0 3d.s2 408373390us : process_csb: rcs0 out[0]: ctx=2.2, fence 1e95b:3648 (current 3640), prio=4 <0> [412.390350] i915_sel-46130 408373401us : intel_engine_stop_cs: rcs0 <0> [412.390350] i915_sel-46130d..1 408373402us : process_csb: rcs0 cs-irq head=4, tail=4 <0> [412.390350] i915_sel-46130 408373403us : intel_gpu_reset: engine_mask=1 <0> [412.390350] i915_sel-46130d..1 408373408us : execlists_cancel_port_requests: rcs0:port0 fence 1e95b:3648, (current 3648) <0> [412.390350] i915_sel-46130 408373442us : intel_engine_cancel_stop_cs: rcs0 <0> [412.390350] i915_sel-46130 408373442us : execlists_reset_finish: rcs0: depth->0 <0> [412.390350] ksoftirq-26 3..s. 408373442us : execlists_submission_tasklet: rcs0 awake?=1, active=0 <0> [412.390350] ksoftirq-26 3d.s1 408373443us : process_csb: rcs0 cs-irq head=5, tail=5 <0> [412.390350] i915_sel-46130 408373475us : i915_request_retire: rcs0 fence 1e95b:3640, current 3648 <0> [412.390350] i915_sel-46130 408373476us : i915_request_retire: __retire_engine_request(rcs0) fence 1e95b:3640, current 3648 <0> [412.390350] i915_sel-46130 408373494us : __i915_request_commit: rcs0 fence 1e95b:3650 <0> [412.390350] i915_sel-46130d..1 408373496us : process_csb: rcs0 cs-irq head=5, tail=5 <0> [412.390350] i915_sel-46130d..1 408373496us : __i915_request_submit: rcs0 fence 1e95b:3650 -> current 3648 <0> [412.390350] i915_sel-46130d..1 408373498us : __execlists_submission_tasklet: rcs0 in[0]: ctx=2.1, fence 1e95b:3650 (current 3648), prio=6 <0> [412.390350] i915_sel-46130 408373500us : i915_request_retire_upto: rcs0 fence 1e95b:3648, current 3648 <0> [412.390350] i915_sel-46130 408373500us : i915_request_retire: rcs0 fence 1e95b:3642, current 3648 <0> [412.390350] i915_sel-46130 408373501us : i915_request_retire: __retire_engine_request(rcs0) fence 1e95b:3642, current 3648 <0> [412.390350] i915_sel-46130 408373514us : i915_request_retire: rcs0 fence 1e95b:3644, current 3648 <0> [412.390350] i915_sel-46130 408373515us : i915_request_retire: __retire_engine_request(rcs0) fence 1e95b:3644, current 3648 <0> [412.390350] i915_sel-46130 408373527us : i915_request_retire: rcs0 fence 1e95b:3646, current 3640 <0> [412.390350] -0 3..s1 408373569us : execlists_submission_tasklet: rcs0 awake?=1, active=1 <0> [412.390350] -0 3d.s2
Re: [Intel-gfx] [PATCH 21/29] drm/i915: Switch back to an array of logical per-engine HW contexts
On 10/04/2019 17:18, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-04-10 16:32:18)
On 08/04/2019 10:17, Chris Wilson wrote:
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 3f794bc71958..0df3c5238c04 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -716,7 +716,7 @@ static int pin_context(struct i915_gem_context *ctx,
struct intel_context *ce;
int err;
- ce = intel_context_instance(ctx, engine);
+ ce = i915_gem_context_get_engine(ctx, engine->id);
Staying with intel_context_instance wouldn't help to reduce the churn?
But it takes the GEM context :|
intel_context_lookup() ? But it won't be part of gt/intel_context.h
And I'd like to have 'get' in there for consistency (although other
object lookup functions return a new reference, so that may not be a
solid argument).
It has annoyed me that this does require the GEM context, but that's the
nature of the beast.
Leave it as is then.
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 50266e87c225..21b4a04c424b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4312,8 +4312,9 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
static int __intel_engines_record_defaults(struct drm_i915_private *i915)
{
- struct i915_gem_context *ctx;
struct intel_engine_cs *engine;
+ struct i915_gem_context *ctx;
+ struct i915_gem_engines *e;
enum intel_engine_id id;
int err = 0;
@@ -4330,18 +4331,26 @@ static int __intel_engines_record_defaults(struct drm_i915_private *i915)
if (IS_ERR(ctx))
return PTR_ERR(ctx);
+ e = i915_gem_context_engine_list_lock(ctx);
+
for_each_engine(engine, i915, id) {
Do we need i915 version of for_each_context_engine? If all call sites
will doing this "lock ctx" -> "walk physical engines" -> "lookup in
context" then it seems a bit disconnected.
It's rare, a couple of odd cases imo.
Ok, can re-evaluate at the end.
+ struct intel_context *ce = e->engines[id];
How will index by engine->id work for engine map?
It doesn't, that's the point of these being the odd cases. :)
struct i915_request *rq;
- rq = i915_request_alloc(engine, ctx);
+ err = intel_context_pin(ce);
+ if (err)
+ goto err_active;
+
+ rq = i915_request_create(ce);
+ intel_context_unpin(ce);
Kind of verbose, no? Do you want to add some
middle-ground-between-request-alloc-and-create helper?
There's 2 callers of i915_request_create() in this style.
(Execbuf has a style all of its own.)
At the moment I don't have a good name for the happy middle ground, so
I'm willing to pay the price for forcing control over the pin to the
user.
...
Does it really make any difference for the perma-pinned kernel contexts?
Actually no...
Hmm. The fundamental objective was being able to pass ce and avoid
struct_mutex -- but we already avoid struct_mutex for pinning today as
the context is already pinned.
The downside is that it adds redundant steps to execbuf, and
__i915_request_create() is already taken... And I hope you would say no
if I suggest i915_request_create :)
+static struct i915_gem_engines *default_engines(struct i915_gem_context *ctx)
+{
+ struct intel_engine_cs *engine;
+ struct i915_gem_engines *e;
+ enum intel_engine_id id;
+
+ e = kzalloc(struct_size(e, engines, I915_NUM_ENGINES), GFP_KERNEL);
+ if (!e)
+ return ERR_PTR(-ENOMEM);
+
+ e->i915 = ctx->i915;
+ for_each_engine(engine, ctx->i915, id) {
+ struct intel_context *ce;
+ ce = intel_context_create(ctx, engine);
+ if (IS_ERR(ce)) {
+ free_engines_n(e, id);
I dislike piggy-back of n into e. How about:
__free_engines(e, n)
{
...
}
free_engines(e)
{
__fre_engines(e, e->num_engines):
}
?
Ok.
Or even you could e->num_engines++ in the above loop and just have one
free_engines.
I thought it was cleaner to avoid having multiple counters for the same
loop. free_engines_n() ended up with 5 users.
+ return ERR_CAST(ce);
+ }
+
+ e->engines[id] = ce;
Each context would have a sparse array of engines, on most platforms.
Would it be workable to instead create a compact array per context, and
just have a per device translation table of idx to engine->id? Or
vice-versa, I can't figure out straight from the bat which one would you
need.
As sparse as we do today. I working under the assumption that going
forwards, the default map would be the oddity. But that is better than
the sparse fixed array[] we previously embedded into the GEM context, so
overall I think still an improvement for old platforms.
True.
We can trim the
[Intel-gfx] [CI 1/2] drm/i915/guc: Implement reset locally
Before causing guc and execlists to diverge further (breaking guc in the
process), take a copy of the current reset procedure and make it local to
the guc submission backend
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_guc_submission.c | 102
drivers/gpu/drm/i915/intel_lrc.c| 37 ++-
drivers/gpu/drm/i915/intel_lrc.h| 5 +
drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +-
4 files changed, 143 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c
b/drivers/gpu/drm/i915/intel_guc_submission.c
index dea87253d141..37f60cb8e9e1 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -872,6 +872,104 @@ static void guc_reset_prepare(struct intel_engine_cs
*engine)
flush_workqueue(engine->i915->guc.preempt_wq);
}
+static void guc_reset(struct intel_engine_cs *engine, bool stalled)
+{
+ struct intel_engine_execlists * const execlists = >execlists;
+ struct i915_request *rq;
+ unsigned long flags;
+
+ spin_lock_irqsave(>timeline.lock, flags);
+
+ execlists_cancel_port_requests(execlists);
+
+ /* Push back any incomplete requests for replay after the reset. */
+ rq = execlists_unwind_incomplete_requests(execlists);
+ if (!rq)
+ goto out_unlock;
+
+ if (!i915_request_started(rq))
+ stalled = false;
+
+ i915_reset_request(rq, stalled);
+ intel_lr_context_reset(engine, rq->hw_context, rq->head, stalled);
+
+out_unlock:
+ spin_unlock_irqrestore(>timeline.lock, flags);
+}
+
+static void guc_cancel_requests(struct intel_engine_cs *engine)
+{
+ struct intel_engine_execlists * const execlists = >execlists;
+ struct i915_request *rq, *rn;
+ struct rb_node *rb;
+ unsigned long flags;
+
+ GEM_TRACE("%s\n", engine->name);
+
+ /*
+* Before we call engine->cancel_requests(), we should have exclusive
+* access to the submission state. This is arranged for us by the
+* caller disabling the interrupt generation, the tasklet and other
+* threads that may then access the same state, giving us a free hand
+* to reset state. However, we still need to let lockdep be aware that
+* we know this state may be accessed in hardirq context, so we
+* disable the irq around this manipulation and we want to keep
+* the spinlock focused on its duties and not accidentally conflate
+* coverage to the submission's irq state. (Similarly, although we
+* shouldn't need to disable irq around the manipulation of the
+* submission's irq state, we also wish to remind ourselves that
+* it is irq state.)
+*/
+ spin_lock_irqsave(>timeline.lock, flags);
+
+ /* Cancel the requests on the HW and clear the ELSP tracker. */
+ execlists_cancel_port_requests(execlists);
+
+ /* Mark all executing requests as skipped. */
+ list_for_each_entry(rq, >timeline.requests, link) {
+ if (!i915_request_signaled(rq))
+ dma_fence_set_error(>fence, -EIO);
+
+ i915_request_mark_complete(rq);
+ }
+
+ /* Flush the queued requests to the timeline list (for retiring). */
+ while ((rb = rb_first_cached(>queue))) {
+ struct i915_priolist *p = to_priolist(rb);
+ int i;
+
+ priolist_for_each_request_consume(rq, rn, p, i) {
+ list_del_init(>sched.link);
+ __i915_request_submit(rq);
+ dma_fence_set_error(>fence, -EIO);
+ i915_request_mark_complete(rq);
+ }
+
+ rb_erase_cached(>node, >queue);
+ i915_priolist_free(p);
+ }
+
+ /* Remaining _unready_ requests will be nop'ed when submitted */
+
+ execlists->queue_priority_hint = INT_MIN;
+ execlists->queue = RB_ROOT_CACHED;
+ GEM_BUG_ON(port_isset(execlists->port));
+
+ spin_unlock_irqrestore(>timeline.lock, flags);
+}
+
+static void guc_reset_finish(struct intel_engine_cs *engine)
+{
+ struct intel_engine_execlists * const execlists = >execlists;
+
+ if (__tasklet_enable(>tasklet))
+ /* And kick in case we missed a new request submission. */
+ tasklet_hi_schedule(>tasklet);
+
+ GEM_TRACE("%s: depth->%d\n", engine->name,
+ atomic_read(>tasklet.count));
+}
+
/*
* Everything below here is concerned with setup & teardown, and is
* therefore not part of the somewhat time-critical batch-submission
@@ -1293,6 +1391,10 @@ static void guc_set_default_submission(struct
intel_engine_cs *engine)
engine->unpark = guc_submission_unpark;
engine->reset.prepare = guc_reset_prepare;
+ engine->reset.reset = guc_reset;
+
Re: [Intel-gfx] [igt-dev] [RFT i-g-t 6/6] test: perf_pmu: use the gem_engine_topology library
On Thu, Apr 11, 2019 at 01:32:03PM +0100, Chris Wilson wrote: > Quoting Tvrtko Ursulin (2019-04-11 13:26:54) > > From: Andi Shyti > > > > Replace the legacy for_each_engine* defines with the ones > > implemented in the gem_engine_topology library. > > > > Use whenever possible gem_engine_can_store_dword() that checks > > class instead of flags. > > > > Now the __for_each_engine_class_instance and > > for_each_engine_class_instance are unused, remove them. > > > > Suggested-by: Tvrtko Ursulin > > Signed-off-by: Andi Shyti > > Cc: Tvrtko Ursulin > > Reviewed-by: Tvrtko Ursulin > > I see a lot of new gem_context_create(), but not gem_require_contexts(). gem_require_contexts() should go on top of engine_topology. I will add it there. Thanks, Andi > -Chris > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 16/29] drm/i915: Export intel_context_instance()
On 10/04/2019 20:32, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-04-10 13:06:04)
On 08/04/2019 10:17, Chris Wilson wrote:
We want to pass in a intel_context into intel_context_pin() and that
requires us to first be able to lookup the intel_context!
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_context.c| 37 +++---
drivers/gpu/drm/i915/gt/intel_context.h| 19 +++
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 8 -
drivers/gpu/drm/i915/gt/mock_engine.c | 8 -
drivers/gpu/drm/i915/gvt/scheduler.c | 7 +++-
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 11 +--
drivers/gpu/drm/i915/i915_perf.c | 21
drivers/gpu/drm/i915/i915_request.c| 11 ++-
8 files changed, 83 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index 6ae6a3f58364..a1267739e369 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -104,7 +104,7 @@ void __intel_context_remove(struct intel_context *ce)
spin_unlock(>hw_contexts_lock);
}
-static struct intel_context *
+struct intel_context *
intel_context_instance(struct i915_gem_context *ctx,
struct intel_engine_cs *engine)
{
@@ -112,7 +112,7 @@ intel_context_instance(struct i915_gem_context *ctx,
ce = intel_context_lookup(ctx, engine);
if (likely(ce))
- return ce;
+ return intel_context_get(ce);
ce = intel_context_alloc();
if (!ce)
@@ -125,7 +125,7 @@ intel_context_instance(struct i915_gem_context *ctx,
intel_context_free(ce);
GEM_BUG_ON(intel_context_lookup(ctx, engine) != pos);
- return pos;
+ return intel_context_get(pos);
}
struct intel_context *
@@ -139,30 +139,30 @@ intel_context_pin_lock(struct i915_gem_context *ctx,
if (IS_ERR(ce))
return ce;
- if (mutex_lock_interruptible(>pin_mutex))
+ if (mutex_lock_interruptible(>pin_mutex)) {
+ intel_context_put(ce);
return ERR_PTR(-EINTR);
+ }
return ce;
}
-struct intel_context *
-intel_context_pin(struct i915_gem_context *ctx,
- struct intel_engine_cs *engine)
+void intel_context_pin_unlock(struct intel_context *ce)
+ __releases(ce->pin_mutex)
{
- struct intel_context *ce;
- int err;
-
- ce = intel_context_instance(ctx, engine);
- if (IS_ERR(ce))
- return ce;
+ mutex_unlock(>pin_mutex);
+ intel_context_put(ce);
+}
- if (likely(atomic_inc_not_zero(>pin_count)))
- return ce;
+int __intel_context_do_pin(struct intel_context *ce)
+{
+ int err;
if (mutex_lock_interruptible(>pin_mutex))
- return ERR_PTR(-EINTR);
+ return -EINTR;
if (likely(!atomic_read(>pin_count))) {
+ struct i915_gem_context *ctx = ce->gem_context;
intel_wakeref_t wakeref;
err = 0;
@@ -172,7 +172,6 @@ intel_context_pin(struct i915_gem_context *ctx,
goto err;
i915_gem_context_get(ctx);
- GEM_BUG_ON(ce->gem_context != ctx);
mutex_lock(>mutex);
list_add(>active_link, >active_engines);
@@ -186,11 +185,11 @@ intel_context_pin(struct i915_gem_context *ctx,
GEM_BUG_ON(!intel_context_is_pinned(ce)); /* no overflow! */
mutex_unlock(>pin_mutex);
- return ce;
+ return 0;
err:
mutex_unlock(>pin_mutex);
- return ERR_PTR(err);
+ return err;
}
void intel_context_unpin(struct intel_context *ce)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.h
b/drivers/gpu/drm/i915/gt/intel_context.h
index 9aeef88176b9..da342e9a8c2e 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.h
+++ b/drivers/gpu/drm/i915/gt/intel_context.h
@@ -49,11 +49,7 @@ intel_context_is_pinned(struct intel_context *ce)
return atomic_read(>pin_count);
}
-static inline void intel_context_pin_unlock(struct intel_context *ce)
-__releases(ce->pin_mutex)
-{
- mutex_unlock(>pin_mutex);
-}
Could leave this as static inline since the only addition is kref_put so
compiler could decide what to do? Don't mind either way.
In the next (or two) patch.
+void intel_context_pin_unlock(struct intel_context *ce);
struct intel_context *
__intel_context_insert(struct i915_gem_context *ctx,
@@ -63,7 +59,18 @@ void
__intel_context_remove(struct intel_context *ce);
struct intel_context *
-intel_context_pin(struct i915_gem_context *ctx, struct intel_engine_cs
*engine);
+intel_context_instance(struct i915_gem_context *ctx,
+struct intel_engine_cs *engine);
+
+int __intel_context_do_pin(struct intel_context *ce);
+
+static inline int intel_context_pin(struct intel_context *ce)
+{
Re: [Intel-gfx] [PATCH 1/2] drm/i915/guc: Implement reset locally
Chris Wilson writes:
> Before causing guc and execlists to diverge further (breaking guc in the
> process), take a copy of the current reset procedure and make it local to
> the guc submission backend
>
I agree strongly on the sentiment. This is not the time and
area to try to hold on to the consolidation.
The reset dance has proven to be hard enough and
during trying to atone to the hw's peculiarities,
last thing we want is to step on eachothers toes.
Reviewed-by: Mika Kuoppala
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/intel_guc_submission.c | 102
> drivers/gpu/drm/i915/intel_lrc.c| 37 ++-
> drivers/gpu/drm/i915/intel_lrc.h| 5 +
> drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +-
> 4 files changed, 143 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c
> b/drivers/gpu/drm/i915/intel_guc_submission.c
> index 42fcd622d7a3..6ebc125710ce 100644
> --- a/drivers/gpu/drm/i915/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/intel_guc_submission.c
> @@ -872,6 +872,104 @@ static void guc_reset_prepare(struct intel_engine_cs
> *engine)
> flush_workqueue(engine->i915->guc.preempt_wq);
> }
>
> +static void guc_reset(struct intel_engine_cs *engine, bool stalled)
> +{
> + struct intel_engine_execlists * const execlists = >execlists;
> + struct i915_request *rq;
> + unsigned long flags;
> +
> + spin_lock_irqsave(>timeline.lock, flags);
> +
> + execlists_cancel_port_requests(execlists);
> +
> + /* Push back any incomplete requests for replay after the reset. */
> + rq = execlists_unwind_incomplete_requests(execlists);
> + if (!rq)
> + goto out_unlock;
> +
> + if (!i915_request_started(rq))
> + stalled = false;
> +
> + i915_reset_request(rq, stalled);
> + intel_lr_context_reset(engine, rq->hw_context, rq->head, stalled);
> +
> +out_unlock:
> + spin_unlock_irqrestore(>timeline.lock, flags);
> +}
> +
> +static void guc_cancel_requests(struct intel_engine_cs *engine)
> +{
> + struct intel_engine_execlists * const execlists = >execlists;
> + struct i915_request *rq, *rn;
> + struct rb_node *rb;
> + unsigned long flags;
> +
> + GEM_TRACE("%s\n", engine->name);
> +
> + /*
> + * Before we call engine->cancel_requests(), we should have exclusive
> + * access to the submission state. This is arranged for us by the
> + * caller disabling the interrupt generation, the tasklet and other
> + * threads that may then access the same state, giving us a free hand
> + * to reset state. However, we still need to let lockdep be aware that
> + * we know this state may be accessed in hardirq context, so we
> + * disable the irq around this manipulation and we want to keep
> + * the spinlock focused on its duties and not accidentally conflate
> + * coverage to the submission's irq state. (Similarly, although we
> + * shouldn't need to disable irq around the manipulation of the
> + * submission's irq state, we also wish to remind ourselves that
> + * it is irq state.)
> + */
> + spin_lock_irqsave(>timeline.lock, flags);
> +
> + /* Cancel the requests on the HW and clear the ELSP tracker. */
> + execlists_cancel_port_requests(execlists);
> +
> + /* Mark all executing requests as skipped. */
> + list_for_each_entry(rq, >timeline.requests, link) {
> + if (!i915_request_signaled(rq))
> + dma_fence_set_error(>fence, -EIO);
> +
> + i915_request_mark_complete(rq);
> + }
> +
> + /* Flush the queued requests to the timeline list (for retiring). */
> + while ((rb = rb_first_cached(>queue))) {
> + struct i915_priolist *p = to_priolist(rb);
> + int i;
> +
> + priolist_for_each_request_consume(rq, rn, p, i) {
> + list_del_init(>sched.link);
> + __i915_request_submit(rq);
> + dma_fence_set_error(>fence, -EIO);
> + i915_request_mark_complete(rq);
> + }
> +
> + rb_erase_cached(>node, >queue);
> + i915_priolist_free(p);
> + }
> +
> + /* Remaining _unready_ requests will be nop'ed when submitted */
> +
> + execlists->queue_priority_hint = INT_MIN;
> + execlists->queue = RB_ROOT_CACHED;
> + GEM_BUG_ON(port_isset(execlists->port));
> +
> + spin_unlock_irqrestore(>timeline.lock, flags);
> +}
> +
> +static void guc_reset_finish(struct intel_engine_cs *engine)
> +{
> + struct intel_engine_execlists * const execlists = >execlists;
> +
> + if (__tasklet_enable(>tasklet))
> + /* And kick in case we missed a new request submission. */
> + tasklet_hi_schedule(>tasklet);
> +
> + GEM_TRACE("%s: depth->%d\n", engine->name,
> + atomic_read(>tasklet.count));
> +}
> +
> /*
> *
Re: [Intel-gfx] [igt-dev] [RFT i-g-t 6/6] test: perf_pmu: use the gem_engine_topology library
On 11/04/2019 13:32, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-04-11 13:26:54)
From: Andi Shyti
Replace the legacy for_each_engine* defines with the ones
implemented in the gem_engine_topology library.
Use whenever possible gem_engine_can_store_dword() that checks
class instead of flags.
Now the __for_each_engine_class_instance and
for_each_engine_class_instance are unused, remove them.
Suggested-by: Tvrtko Ursulin
Signed-off-by: Andi Shyti
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
I see a lot of new gem_context_create(), but not gem_require_contexts().
Problem is __for_each_physical_engine modifies the default context so
tests under that iterator can't keep using I915_EXEC_RENDER.
It was perhaps a knee-jerk reaction to make them create their own
context as a workaround.
Should we have a helper after all to get eb flags for given class:instance?
unsigned int
gem_get_ctx_eb_flags(uint32_t ctx, uint16_t class, uint16_t instance)
{
if (ctx.has_map)
return find_class_instance_in_map->flags;
else
return gem_class_instance_to_eb_flags(class, instance);
}
?
Regards,
Tvrtko
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Call i915_sw_fence_fini on request cleanup
Chris Wilson writes:
> As i915_requests are put into an RCU-freelist, they may get reused
> before debugobjects notice them as being freed. On cleanup, explicitly
> call i915_sw_fence_fini() so that the debugobject is properly tracked.
>
> Reported-by: Mika Kuoppala
> Fixes: b7404c7ecb38 ("drm/i915: Bump ready tasks ahead of busywaits")
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> Cc: Tvrtko Ursulin
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_request.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_request.c
> b/drivers/gpu/drm/i915/i915_request.c
> index a7d87cfaabcb..b836721d3b13 100644
> --- a/drivers/gpu/drm/i915/i915_request.c
> +++ b/drivers/gpu/drm/i915/i915_request.c
> @@ -101,6 +101,7 @@ static void i915_fence_release(struct dma_fence *fence)
>* caught trying to reuse dead objects.
>*/
> i915_sw_fence_fini(>submit);
> + i915_sw_fence_fini(>semaphore);
>
> kmem_cache_free(global.slab_requests, rq);
> }
> --
> 2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [igt-dev] [RFT i-g-t 6/6] test: perf_pmu: use the gem_engine_topology library
Quoting Tvrtko Ursulin (2019-04-11 13:26:54) > From: Andi Shyti > > Replace the legacy for_each_engine* defines with the ones > implemented in the gem_engine_topology library. > > Use whenever possible gem_engine_can_store_dword() that checks > class instead of flags. > > Now the __for_each_engine_class_instance and > for_each_engine_class_instance are unused, remove them. > > Suggested-by: Tvrtko Ursulin > Signed-off-by: Andi Shyti > Cc: Tvrtko Ursulin > Reviewed-by: Tvrtko Ursulin I see a lot of new gem_context_create(), but not gem_require_contexts(). -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Call i915_sw_fence_fini on request cleanup
On 11/04/2019 13:24, Chris Wilson wrote:
As i915_requests are put into an RCU-freelist, they may get reused
before debugobjects notice them as being freed. On cleanup, explicitly
call i915_sw_fence_fini() so that the debugobject is properly tracked.
Reported-by: Mika Kuoppala
Fixes: b7404c7ecb38 ("drm/i915: Bump ready tasks ahead of busywaits")
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_request.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index a7d87cfaabcb..b836721d3b13 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -101,6 +101,7 @@ static void i915_fence_release(struct dma_fence *fence)
* caught trying to reuse dead objects.
*/
i915_sw_fence_fini(>submit);
+ i915_sw_fence_fini(>semaphore);
kmem_cache_free(global.slab_requests, rq);
}
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFT i-g-t 5/6] lib: igt_dummyload: use for_each_context_engine()
From: Andi Shyti
With the new getparam/setparam api, engines are mapped to
context. Use for_each_context_engine() to loop through existing
engines.
Suggested-by: Tvrtko Ursulin
Signed-off-by: Andi Shyti
Reviewed-by: Tvrtko Ursulin
---
Just some debug to get more data from CI.
---
lib/igt_dummyload.c | 38 +-
1 file changed, 25 insertions(+), 13 deletions(-)
diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
index 47f6b92b424b..e7f3f480dc26 100644
--- a/lib/igt_dummyload.c
+++ b/lib/igt_dummyload.c
@@ -39,6 +39,7 @@
#include "ioctl_wrappers.h"
#include "sw_sync.h"
#include "igt_vgem.h"
+#include "i915/gem_engine_topology.h"
#include "i915/gem_mman.h"
/**
@@ -86,7 +87,7 @@ emit_recursive_batch(igt_spin_t *spin,
struct drm_i915_gem_relocation_entry relocs[2], *r;
struct drm_i915_gem_execbuffer2 *execbuf;
struct drm_i915_gem_exec_object2 *obj;
- unsigned int engines[16];
+ unsigned int flags[GEM_MAX_ENGINES];
unsigned int nengine;
int fence_fd = -1;
uint32_t *batch, *batch_start;
@@ -94,17 +95,33 @@ emit_recursive_batch(igt_spin_t *spin,
nengine = 0;
if (opts->engine == ALL_ENGINES) {
- unsigned int engine;
+ struct intel_execution_engine2 *engine;
- for_each_physical_engine(fd, engine) {
+ for_each_context_engine(fd, opts->ctx, engine) {
if (opts->flags & IGT_SPIN_POLL_RUN &&
- !gem_can_store_dword(fd, engine))
+ !gem_class_can_store_dword(fd, engine->class))
continue;
- engines[nengine++] = engine;
+ igt_debug("%u=%llx (%u:%u)\n",
+ nengine,
+ engine->flags, engine->class,
engine->instance);
+ flags[nengine++] = engine->flags;
}
} else {
- engines[nengine++] = opts->engine;
+ struct intel_execution_engine2 *e;
+ int class;
+
+ if (!gem_ctx_get_engine(fd, opts->engine, opts->ctx, e)) {
+ class = e->class;
+ } else {
+ gem_require_ring(fd, opts->engine);
+ class = gem_eb_to_class(opts->engine);
+ }
+
+ if (opts->flags & IGT_SPIN_POLL_RUN)
+ igt_require(gem_class_can_store_dword(fd, class));
+
+ flags[nengine++] = opts->engine;
}
igt_require(nengine);
@@ -234,8 +251,9 @@ emit_recursive_batch(igt_spin_t *spin,
for (i = 0; i < nengine; i++) {
execbuf->flags &= ~ENGINE_MASK;
- execbuf->flags |= engines[i];
+ execbuf->flags |= flags[i];
+ igt_debug("eb %u = %llx\n", i, flags[i]);
gem_execbuf_wr(fd, execbuf);
if (opts->flags & IGT_SPIN_FENCE_OUT) {
@@ -308,12 +326,6 @@ igt_spin_batch_factory(int fd, const struct
igt_spin_factory *opts)
igt_require_gem(fd);
- if (opts->engine != ALL_ENGINES) {
- gem_require_ring(fd, opts->engine);
- if (opts->flags & IGT_SPIN_POLL_RUN)
- igt_require(gem_can_store_dword(fd, opts->engine));
- }
-
spin = spin_batch_create(fd, opts);
igt_assert(gem_bo_busy(fd, spin->handle));
--
2.19.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFT i-g-t 6/6] test: perf_pmu: use the gem_engine_topology library
From: Andi Shyti
Replace the legacy for_each_engine* defines with the ones
implemented in the gem_engine_topology library.
Use whenever possible gem_engine_can_store_dword() that checks
class instead of flags.
Now the __for_each_engine_class_instance and
for_each_engine_class_instance are unused, remove them.
Suggested-by: Tvrtko Ursulin
Signed-off-by: Andi Shyti
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
---
lib/igt_gt.h | 7 ---
tests/perf_pmu.c | 143 +--
2 files changed, 88 insertions(+), 62 deletions(-)
diff --git a/lib/igt_gt.h b/lib/igt_gt.h
index af4cc38a1ef7..c2ca07e03738 100644
--- a/lib/igt_gt.h
+++ b/lib/igt_gt.h
@@ -119,11 +119,4 @@ void gem_require_engine(int gem_fd,
igt_require(gem_has_engine(gem_fd, class, instance));
}
-#define __for_each_engine_class_instance(e__) \
- for ((e__) = intel_execution_engines2; (e__)->name; (e__)++)
-
-#define for_each_engine_class_instance(fd__, e__) \
- for ((e__) = intel_execution_engines2; (e__)->name; (e__)++) \
- for_if (gem_has_engine((fd__), (e__)->class, (e__)->instance))
-
#endif /* IGT_GT_H */
diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index 4f552bc2ae28..a889b552236d 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -72,7 +72,7 @@ static int open_group(uint64_t config, int group)
}
static void
-init(int gem_fd, const struct intel_execution_engine2 *e, uint8_t sample)
+init(int gem_fd, struct intel_execution_engine2 *e, uint8_t sample)
{
int fd, err = 0;
bool exists;
@@ -158,11 +158,6 @@ static unsigned int measured_usleep(unsigned int usec)
return igt_nsec_elapsed();
}
-static unsigned int e2ring(int gem_fd, const struct intel_execution_engine2 *e)
-{
- return gem_class_instance_to_eb_flags(gem_fd, e->class, e->instance);
-}
-
#define TEST_BUSY (1)
#define FLAG_SYNC (2)
#define TEST_TRAILING_IDLE (4)
@@ -170,14 +165,15 @@ static unsigned int e2ring(int gem_fd, const struct
intel_execution_engine2 *e)
#define FLAG_LONG (16)
#define FLAG_HANG (32)
-static igt_spin_t * __spin_poll(int fd, uint32_t ctx, unsigned long flags)
+static igt_spin_t * __spin_poll(int fd, uint32_t ctx,
+ struct intel_execution_engine2 *e)
{
struct igt_spin_factory opts = {
.ctx = ctx,
- .engine = flags,
+ .engine = e->flags,
};
- if (gem_can_store_dword(fd, flags))
+ if (gem_class_can_store_dword(fd, e->class))
opts.flags |= IGT_SPIN_POLL_RUN;
return __igt_spin_batch_factory(fd, );
@@ -209,20 +205,34 @@ static unsigned long __spin_wait(int fd, igt_spin_t *spin)
return igt_nsec_elapsed();
}
-static igt_spin_t * __spin_sync(int fd, uint32_t ctx, unsigned long flags)
+static igt_spin_t * __spin_sync(int fd, uint32_t ctx,
+ struct intel_execution_engine2 *e)
{
- igt_spin_t *spin = __spin_poll(fd, ctx, flags);
+ igt_spin_t *spin = __spin_poll(fd, ctx, e);
__spin_wait(fd, spin);
return spin;
}
-static igt_spin_t * spin_sync(int fd, uint32_t ctx, unsigned long flags)
+static igt_spin_t * spin_sync(int fd, uint32_t ctx,
+ struct intel_execution_engine2 *e)
{
igt_require_gem(fd);
- return __spin_sync(fd, ctx, flags);
+ return __spin_sync(fd, ctx, e);
+}
+
+static igt_spin_t * spin_sync_flags(int fd, uint32_t ctx, unsigned int flags)
+{
+ struct intel_execution_engine2 e = { };
+
+ e.class = gem_eb_to_class(flags);
+ e.instance = (flags & (I915_EXEC_BSD_MASK | I915_EXEC_RING_MASK)) ==
+(I915_EXEC_BSD | I915_EXEC_BSD_RING2) ? 1 : 0;
+ e.flags = flags;
+
+ return spin_sync(fd, ctx, );
}
static void end_spin(int fd, igt_spin_t *spin, unsigned int flags)
@@ -257,7 +267,7 @@ static void end_spin(int fd, igt_spin_t *spin, unsigned int
flags)
}
static void
-single(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
+single(int gem_fd, struct intel_execution_engine2 *e, unsigned int flags)
{
unsigned long slept;
igt_spin_t *spin;
@@ -267,7 +277,7 @@ single(int gem_fd, const struct intel_execution_engine2 *e,
unsigned int flags)
fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
if (flags & TEST_BUSY)
- spin = spin_sync(gem_fd, 0, e2ring(gem_fd, e));
+ spin = spin_sync(gem_fd, 0, e);
else
spin = NULL;
@@ -303,7 +313,7 @@ single(int gem_fd, const struct intel_execution_engine2 *e,
unsigned int flags)
}
static void
-busy_start(int gem_fd, const struct intel_execution_engine2 *e)
+busy_start(int gem_fd, struct intel_execution_engine2 *e)
{
unsigned long slept;
uint64_t val, ts[2];
@@ -316,7 +326,7 @@ busy_start(int gem_fd, const struct intel_execution_engine2
*e)
*/
[Intel-gfx] [PATCH] drm/i915: Call i915_sw_fence_fini on request cleanup
As i915_requests are put into an RCU-freelist, they may get reused
before debugobjects notice them as being freed. On cleanup, explicitly
call i915_sw_fence_fini() so that the debugobject is properly tracked.
Reported-by: Mika Kuoppala
Fixes: b7404c7ecb38 ("drm/i915: Bump ready tasks ahead of busywaits")
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_request.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index a7d87cfaabcb..b836721d3b13 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -101,6 +101,7 @@ static void i915_fence_release(struct dma_fence *fence)
* caught trying to reuse dead objects.
*/
i915_sw_fence_fini(>submit);
+ i915_sw_fence_fini(>semaphore);
kmem_cache_free(global.slab_requests, rq);
}
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for IRQ initialization debloat and conversion to uncore
On Wed, Apr 10, 2019 at 03:53:05PM -0700, Paulo Zanoni wrote: > Em ter, 2019-04-09 às 21:20 +0300, Ville Syrjälä escreveu: > > On Tue, Apr 09, 2019 at 10:34:22AM -0700, Paulo Zanoni wrote: > > > Em ter, 2019-04-09 às 00:44 +, Patchwork escreveu: > > > > == Series Details == > > > > > > > > Series: IRQ initialization debloat and conversion to uncore > > > > URL : https://patchwork.freedesktop.org/series/59202/ > > > > State : warning > > > > > > > > == Summary == > > > > > > > > $ dim checkpatch origin/drm-tip > > > > 7f73d1fe31bb drm/i915: refactor the IRQ init/reset macros > > > > -:114: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'which' - possible > > > > side-effects? > > > > #114: FILE: drivers/gpu/drm/i915/i915_irq.c:169: > > > > +#define GEN8_IRQ_RESET_NDX(type, which) \ > > > > + gen3_irq_reset(dev_priv, GEN8_##type##_IMR(which), \ > > > > + GEN8_##type##_IIR(which), > > > > GEN8_##type##_IER(which)) > > > > > > > > -:172: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'which' - possible > > > > side-effects? > > > > #172: FILE: drivers/gpu/drm/i915/i915_irq.c:236: > > > > +#define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) \ > > > > + gen3_irq_init(dev_priv, GEN8_##type##_IMR(which), \ > > > > + GEN8_##type##_IIR(which), > > > > GEN8_##type##_IER(which), \ > > > > + imr_val, ier_val) > > > > > > > > total: 0 errors, 0 warnings, 2 checks, 135 lines checked > > > > 82160241d80f drm/i915: convert the IRQ initialization functions to > > > > intel_uncore > > > > 8c1c76059a41 drm/i915: fully convert the IRQ initialization macros to > > > > intel_uncore > > > > -:24: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'which' - possible > > > > side-effects? > > > > #24: FILE: drivers/gpu/drm/i915/i915_irq.c:169: > > > > +#define GEN8_IRQ_RESET_NDX(uncore, type, which) \ > > > > + gen3_irq_reset((uncore), GEN8_##type##_IMR(which), \ > > > >GEN8_##type##_IIR(which), > > > > GEN8_##type##_IER(which)) > > > > > > > > -:46: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'which' - possible > > > > side-effects? > > > > #46: FILE: drivers/gpu/drm/i915/i915_irq.c:236: > > > > +#define GEN8_IRQ_INIT_NDX(uncore, type, which, imr_val, ier_val) \ > > > > + gen3_irq_init((uncore), GEN8_##type##_IMR(which), \ > > > > GEN8_##type##_IIR(which), > > > > GEN8_##type##_IER(which), \ > > > > imr_val, ier_val) > > > > > > The whiches are not really a regression, but OK we can deal with them > > > to make the robots happy. > > > > > > > -:401: ERROR:SPACING: space prohibited before that close parenthesis ')' > > > > #401: FILE: drivers/gpu/drm/i915/i915_irq.c:4228: > > > > + GEN2_IRQ_RESET(uncore, ); > > > > > > > > -:416: ERROR:SPACING: space prohibited before that ',' (ctx:WxW) > > > > #416: FILE: drivers/gpu/drm/i915/i915_irq.c:4252: > > > > + GEN2_IRQ_INIT(uncore, , dev_priv->irq_mask, enable_mask); > > > > ^ > > > > > > > > -:433: ERROR:SPACING: space prohibited before that close parenthesis ')' > > > > #433: FILE: drivers/gpu/drm/i915/i915_irq.c:4397: > > > > + GEN3_IRQ_RESET(uncore, ); > > > > > > > > -:448: ERROR:SPACING: space prohibited before that ',' (ctx:WxW) > > > > #448: FILE: drivers/gpu/drm/i915/i915_irq.c:4430: > > > > + GEN3_IRQ_INIT(uncore, , dev_priv->irq_mask, enable_mask); > > > > ^ > > > > > > > > -:464: ERROR:SPACING: space prohibited before that close parenthesis ')' > > > > #464: FILE: drivers/gpu/drm/i915/i915_irq.c:4508: > > > > + GEN3_IRQ_RESET(uncore, ); > > > > > > > > -:479: ERROR:SPACING: space prohibited before that ',' (ctx:WxW) > > > > #479: FILE: drivers/gpu/drm/i915/i915_irq.c:4552: > > > > + GEN3_IRQ_INIT(uncore, , dev_priv->irq_mask, enable_mask); > > > > > > For these ones I really think the spaces help. I would love to read > > > some opinions. Perhaps some comment like /* paste token here */ would > > > help make the code more readable and could help silence checkpatch. > > > Opinions? > > > > Or maybe rename the registers to eg. I9XX_IIR? > > That makes more sense. We use these regs on gen2 too, so I suppose > I8XX_IIR (or GEN2_IIR) would make more sense. OTOH it would break our > current naming rule. I tend to use i9xx to indicate anything gmch, and sometimes it even means pre-skl :/ Not the best naming scheme perhaps but I've not been able to come up with anything better. -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 02/22] drm/i915/guc: Don't allow GuC submission
Due to the upcoming changes to the GuC ABI interface, we must
disable GuC submission mode until final ABI will be available
on all GuC firmwares.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: Daniele Ceraolo Spurio
Cc: John Spotswood
Cc: Vinay Belgaumkar
Cc: Tony Ye
Cc: Anusha Srivatsa
Cc: Jeff Mcgee
Cc: Antonio Argenziano
Cc: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/intel_uc.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 2a56e2363888..21310b917ccc 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -130,6 +130,13 @@ static void sanitize_options_early(struct drm_i915_private
*i915)
"no HuC firmware");
}
+ /* XXX: Verify GuC submission support */
+ if (intel_uc_is_using_guc_submission(i915)) {
+ DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
+"enable_guc", i915_modparams.enable_guc,
+"submission not supported");
+ }
+
/* A negative value means "use platform/config default" */
if (i915_modparams.guc_log_level < 0)
i915_modparams.guc_log_level =
@@ -286,6 +293,10 @@ int intel_uc_init(struct drm_i915_private *i915)
if (!HAS_GUC(i915))
return -ENODEV;
+ /* XXX: GuC submission is unavailable for now */
+ if (USES_GUC_SUBMISSION(i915))
+ return -EIO;
+
ret = intel_guc_init(guc);
if (ret)
return ret;
--
2.19.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 01/22] drm/i915/guc: Change platform default GuC mode
Today our most desired GuC configuration is to only enable HuC if it is available and we really don't care about GuC submission. Change platform default GuC mode to match our desire. Signed-off-by: Michal Wajdeczko Cc: Joonas Lahtinen Cc: Rodrigo Vivi Cc: Daniele Ceraolo Spurio Cc: John Spotswood Cc: Vinay Belgaumkar Cc: Tony Ye Cc: Anusha Srivatsa Cc: Jeff Mcgee Cc: Antonio Argenziano Cc: Sujaritha Sundaresan --- drivers/gpu/drm/i915/intel_uc.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c index 25b80ffe71ad..2a56e2363888 100644 --- a/drivers/gpu/drm/i915/intel_uc.c +++ b/drivers/gpu/drm/i915/intel_uc.c @@ -57,10 +57,8 @@ static int __get_platform_enable_guc(struct drm_i915_private *i915) struct intel_uc_fw *huc_fw = >huc.fw; int enable_guc = 0; - /* Default is to enable GuC/HuC if we know their firmwares */ - if (intel_uc_fw_is_selected(guc_fw)) - enable_guc |= ENABLE_GUC_SUBMISSION; - if (intel_uc_fw_is_selected(huc_fw)) + /* Default is to use HuC if we know GuC and HuC firmwares */ + if (intel_uc_fw_is_selected(guc_fw) && intel_uc_fw_is_selected(huc_fw)) enable_guc |= ENABLE_GUC_LOAD_HUC; /* Any platform specific fine-tuning can be done here */ -- 2.19.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 04/22] drm/i915/guc: Update GuC firmware versions and names
GuC firmware changed its release version numbering schema and now it
also includes patch version. Update our GuC firmware path definitions
to match new pattern:
_guc_...bin
While here, reorder platform checks and start from the latest.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Daniele Ceraolo Spurio
Cc: Rodrigo Vivi
Cc: Anusha Srivatsa
Cc: Jeff Mcgee
---
drivers/gpu/drm/i915/intel_guc_fw.c | 76 -
1 file changed, 42 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c
b/drivers/gpu/drm/i915/intel_guc_fw.c
index 792a551450c7..c937a648c2a1 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -30,53 +30,61 @@
#include "intel_guc_fw.h"
#include "i915_drv.h"
-#define SKL_FW_MAJOR 9
-#define SKL_FW_MINOR 33
-
-#define BXT_FW_MAJOR 9
-#define BXT_FW_MINOR 29
-
-#define KBL_FW_MAJOR 9
-#define KBL_FW_MINOR 39
-
-#define GUC_FW_PATH(platform, major, minor) \
- "i915/" __stringify(platform) "_guc_ver" __stringify(major) "_"
__stringify(minor) ".bin"
-
-#define I915_SKL_GUC_UCODE GUC_FW_PATH(skl, SKL_FW_MAJOR, SKL_FW_MINOR)
-MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
-
-#define I915_BXT_GUC_UCODE GUC_FW_PATH(bxt, BXT_FW_MAJOR, BXT_FW_MINOR)
-MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
-
-#define I915_KBL_GUC_UCODE GUC_FW_PATH(kbl, KBL_FW_MAJOR, KBL_FW_MINOR)
-MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
+#define __MAKE_GUC_FW_PATH(KEY) \
+ "i915/" \
+ __stringify(KEY##_GUC_FW_PREFIX) "_guc_" \
+ __stringify(KEY##_GUC_FW_MAJOR) "." \
+ __stringify(KEY##_GUC_FW_MINOR) "." \
+ __stringify(KEY##_GUC_FW_PATCH) ".bin"
+
+#define SKL_GUC_FW_PREFIX skl
+#define SKL_GUC_FW_MAJOR 32
+#define SKL_GUC_FW_MINOR 0
+#define SKL_GUC_FW_PATCH 3
+#define SKL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(SKL)
+
+#define BXT_GUC_FW_PREFIX bxt
+#define BXT_GUC_FW_MAJOR 32
+#define BXT_GUC_FW_MINOR 0
+#define BXT_GUC_FW_PATCH 3
+#define BXT_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(BXT)
+
+#define KBL_GUC_FW_PREFIX kbl
+#define KBL_GUC_FW_MAJOR 32
+#define KBL_GUC_FW_MINOR 0
+#define KBL_GUC_FW_PATCH 3
+#define KBL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(KBL)
+
+MODULE_FIRMWARE(SKL_GUC_FIRMWARE_PATH);
+MODULE_FIRMWARE(BXT_GUC_FIRMWARE_PATH);
+MODULE_FIRMWARE(KBL_GUC_FIRMWARE_PATH);
static void guc_fw_select(struct intel_uc_fw *guc_fw)
{
struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct drm_i915_private *i915 = guc_to_i915(guc);
GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);
- if (!HAS_GUC(dev_priv))
+ if (!HAS_GUC(i915))
return;
if (i915_modparams.guc_firmware_path) {
guc_fw->path = i915_modparams.guc_firmware_path;
guc_fw->major_ver_wanted = 0;
guc_fw->minor_ver_wanted = 0;
- } else if (IS_SKYLAKE(dev_priv)) {
- guc_fw->path = I915_SKL_GUC_UCODE;
- guc_fw->major_ver_wanted = SKL_FW_MAJOR;
- guc_fw->minor_ver_wanted = SKL_FW_MINOR;
- } else if (IS_BROXTON(dev_priv)) {
- guc_fw->path = I915_BXT_GUC_UCODE;
- guc_fw->major_ver_wanted = BXT_FW_MAJOR;
- guc_fw->minor_ver_wanted = BXT_FW_MINOR;
- } else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
- guc_fw->path = I915_KBL_GUC_UCODE;
- guc_fw->major_ver_wanted = KBL_FW_MAJOR;
- guc_fw->minor_ver_wanted = KBL_FW_MINOR;
+ } else if (IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) {
+ guc_fw->path = KBL_GUC_FIRMWARE_PATH;
+ guc_fw->major_ver_wanted = KBL_GUC_FW_MAJOR;
+ guc_fw->minor_ver_wanted = KBL_GUC_FW_MINOR;
+ } else if (IS_BROXTON(i915)) {
+ guc_fw->path = BXT_GUC_FIRMWARE_PATH;
+ guc_fw->major_ver_wanted = BXT_GUC_FW_MAJOR;
+ guc_fw->minor_ver_wanted = BXT_GUC_FW_MINOR;
+ } else if (IS_SKYLAKE(i915)) {
+ guc_fw->path = SKL_GUC_FIRMWARE_PATH;
+ guc_fw->major_ver_wanted = SKL_GUC_FW_MAJOR;
+ guc_fw->minor_ver_wanted = SKL_GUC_FW_MINOR;
}
}
--
2.19.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 06/22] drm/i915/guc: Update GuC boot parameters
New GuC firmwares require updated boot parameters.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
Cc: John Spotswood
---
drivers/gpu/drm/i915/intel_guc.c | 36 +
drivers/gpu/drm/i915/intel_guc_fwif.h | 39 +++
2 files changed, 22 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index c0e8b359b23a..483c7019f817 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -243,14 +243,7 @@ void intel_guc_fini(struct intel_guc *guc)
static u32 guc_ctl_debug_flags(struct intel_guc *guc)
{
u32 level = intel_guc_log_get_level(>log);
- u32 flags;
- u32 ads;
-
- ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >> PAGE_SHIFT;
- flags = ads << GUC_ADS_ADDR_SHIFT | GUC_ADS_ENABLED;
-
- if (!GUC_LOG_LEVEL_IS_ENABLED(level))
- flags |= GUC_LOG_DEFAULT_DISABLED;
+ u32 flags = 0;
if (!GUC_LOG_LEVEL_IS_VERBOSE(level))
flags |= GUC_LOG_DISABLED;
@@ -265,11 +258,7 @@ static u32 guc_ctl_feature_flags(struct intel_guc *guc)
{
u32 flags = 0;
- flags |= GUC_CTL_VCS2_ENABLED;
-
- if (USES_GUC_SUBMISSION(guc_to_i915(guc)))
- flags |= GUC_CTL_KERNEL_SUBMISSIONS;
- else
+ if (!USES_GUC_SUBMISSION(guc_to_i915(guc)))
flags |= GUC_CTL_DISABLE_SCHEDULER;
return flags;
@@ -333,22 +322,21 @@ static u32 guc_ctl_log_params_flags(struct intel_guc *guc)
return flags;
}
-static void guc_prepare_params(struct intel_guc *guc, u32 *params)
+static u32 guc_ctl_ads_flags(struct intel_guc *guc)
{
- /*
-* GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
-* second. This ARAR is calculated by:
-* Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 10 / 10
-*/
- params[GUC_CTL_ARAT_HIGH] = 0;
- params[GUC_CTL_ARAT_LOW] = 1;
+ u32 ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >> PAGE_SHIFT;
+ u32 flags = ads << GUC_ADS_ADDR_SHIFT;
- params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER;
+ return flags;
+}
+static void guc_prepare_params(struct intel_guc *guc, u32 *params)
+{
+ params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc);
+ params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc);
params[GUC_CTL_FEATURE] = guc_ctl_feature_flags(guc);
- params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc);
params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc);
- params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc);
+ params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc);
}
static void guc_write_params(struct intel_guc *guc, const u32 *params)
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 1cb4fad2d539..64b56da9775c 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -73,44 +73,28 @@
#define GUC_STAGE_DESC_ATTR_PCHBIT(6)
#define GUC_STAGE_DESC_ATTR_TERMINATED BIT(7)
-/* The guc control data is 10 DWORDs */
+/* New GuC control data */
#define GUC_CTL_CTXINFO0
#define GUC_CTL_CTXNUM_IN16_SHIFT0
#define GUC_CTL_BASE_ADDR_SHIFT 12
-#define GUC_CTL_ARAT_HIGH 1
-#define GUC_CTL_ARAT_LOW 2
-
-#define GUC_CTL_DEVICE_INFO3
-
-#define GUC_CTL_LOG_PARAMS 4
+#define GUC_CTL_LOG_PARAMS 1
#define GUC_LOG_VALID(1 << 0)
#define GUC_LOG_NOTIFY_ON_HALF_FULL (1 << 1)
#define GUC_LOG_ALLOC_IN_MEGABYTE(1 << 3)
#define GUC_LOG_CRASH_SHIFT 4
-#define GUC_LOG_CRASH_MASK (0x1 << GUC_LOG_CRASH_SHIFT)
+#define GUC_LOG_CRASH_MASK (0x3 << GUC_LOG_CRASH_SHIFT)
#define GUC_LOG_DPC_SHIFT6
#define GUC_LOG_DPC_MASK (0x7 << GUC_LOG_DPC_SHIFT)
#define GUC_LOG_ISR_SHIFT9
#define GUC_LOG_ISR_MASK (0x7 << GUC_LOG_ISR_SHIFT)
#define GUC_LOG_BUF_ADDR_SHIFT 12
-#define GUC_CTL_PAGE_FAULT_CONTROL 5
-
-#define GUC_CTL_WA 6
-#define GUC_CTL_WA_UK_BY_DRIVER (1 << 3)
-
-#define GUC_CTL_FEATURE7
-#define GUC_CTL_VCS2_ENABLED (1 << 0)
-#define GUC_CTL_KERNEL_SUBMISSIONS (1 << 1)
-#define GUC_CTL_FEATURE2 (1 << 2)
-#define GUC_CTL_POWER_GATING (1 << 3)
-#define GUC_CTL_DISABLE_SCHEDULER(1 << 4)
-#define GUC_CTL_PREEMPTION_LOG (1 << 5)
-#define GUC_CTL_ENABLE_SLPC (1 << 7)
-#define GUC_CTL_RESET_ON_PREMPT_FAILURE (1 << 8)
+#define GUC_CTL_WA 2
+#define GUC_CTL_FEATURE3
+#define GUC_CTL_DISABLE_SCHEDULER(1 << 14)
-#define GUC_CTL_DEBUG 8
+#define
[Intel-gfx] [PATCH v2 05/22] drm/i915/guc: Update GuC firmware CSS header
There are few minor changes in the CSS header related to the version
numbering in new GuC firmwares. Update our definition and start using
common tools for extracting bitfields.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: John Spotswood
Cc: Jeff Mcgee
---
drivers/gpu/drm/i915/intel_guc_fwif.h | 23 ---
drivers/gpu/drm/i915/intel_uc_fw.c| 20 ++--
2 files changed, 18 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index b2f5148f4f17..1cb4fad2d539 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -168,11 +168,7 @@
*in fw. So driver will load a truncated firmware in this case.
*
* HuC firmware layout is same as GuC firmware.
- *
- * HuC firmware css header is different. However, the only difference is where
- * the version information is saved. The uc_css_header is unified to support
- * both. Driver should get HuC version from uc_css_header.huc_sw_version, while
- * uc_css_header.guc_sw_version for GuC.
+ * Only HuC version information is saved in a different way.
*/
struct uc_css_header {
@@ -206,16 +202,13 @@ struct uc_css_header {
char username[8];
char buildnumber[12];
- union {
- struct {
- u32 branch_client_version;
- u32 sw_version;
- } guc;
- struct {
- u32 sw_version;
- u32 reserved;
- } huc;
- };
+ u32 sw_version;
+#define CSS_SW_VERSION_GUC_MAJOR (0xFF << 16)
+#define CSS_SW_VERSION_GUC_MINOR (0xFF << 8)
+#define CSS_SW_VERSION_GUC_PATCH (0xFF << 0)
+#define CSS_SW_VERSION_HUC_MAJOR (0x << 16)
+#define CSS_SW_VERSION_HUC_MINOR (0x << 0)
+ u32 sw_reserved;
u32 prod_preprod_fw;
u32 reserved[12];
u32 header_info;
diff --git a/drivers/gpu/drm/i915/intel_uc_fw.c
b/drivers/gpu/drm/i915/intel_uc_fw.c
index becf05ebae4d..957c1feb30d3 100644
--- a/drivers/gpu/drm/i915/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/intel_uc_fw.c
@@ -22,6 +22,7 @@
*
*/
+#include
#include
#include
@@ -119,21 +120,20 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
goto fail;
}
- /*
-* The GuC firmware image has the version number embedded at a
-* well-known offset within the firmware blob; note that major / minor
-* version are TWO bytes each (i.e. u16), although all pointers and
-* offsets are defined in terms of bytes (u8).
-*/
+ /* Get version numbers from the CSS header */
switch (uc_fw->type) {
case INTEL_UC_FW_TYPE_GUC:
- uc_fw->major_ver_found = css->guc.sw_version >> 16;
- uc_fw->minor_ver_found = css->guc.sw_version & 0x;
+ uc_fw->major_ver_found = FIELD_GET(CSS_SW_VERSION_GUC_MAJOR,
+ css->sw_version);
+ uc_fw->minor_ver_found = FIELD_GET(CSS_SW_VERSION_GUC_MINOR,
+ css->sw_version);
break;
case INTEL_UC_FW_TYPE_HUC:
- uc_fw->major_ver_found = css->huc.sw_version >> 16;
- uc_fw->minor_ver_found = css->huc.sw_version & 0x;
+ uc_fw->major_ver_found = FIELD_GET(CSS_SW_VERSION_HUC_MAJOR,
+ css->sw_version);
+ uc_fw->minor_ver_found = FIELD_GET(CSS_SW_VERSION_HUC_MINOR,
+ css->sw_version);
break;
default:
--
2.19.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 15/22] drm/i915/huc: New HuC status register for Gen11
Gen11 defines new register for checking HuC authentication status.
Look into the right register and bit.
BSpec: 19686
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: Tony Ye
Cc: Vinay Belgaumkar
Cc: John Spotswood
Cc: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_guc_reg.h | 3 ++
drivers/gpu/drm/i915/intel_huc.c | 56
2 files changed, 51 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h
b/drivers/gpu/drm/i915/intel_guc_reg.h
index d26de5193568..7eba65795b58 100644
--- a/drivers/gpu/drm/i915/intel_guc_reg.h
+++ b/drivers/gpu/drm/i915/intel_guc_reg.h
@@ -79,6 +79,9 @@
#define HUC_STATUS2 _MMIO(0xD3B0)
#define HUC_FW_VERIFIED (1<<7)
+#define GEN11_HUC_KERNEL_LOAD_INFO _MMIO(0xC1DC)
+#define HUC_LOAD_SUCCESSFUL(1 << 0)
+
#define GUC_WOPCM_SIZE _MMIO(0xc050)
#define GUC_WOPCM_SIZE_LOCKED (1<<0)
#define GUC_WOPCM_SIZE_SHIFT 12
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index 94c04f16a2ad..708a4b387259 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -40,6 +40,47 @@ int intel_huc_init_misc(struct intel_huc *huc)
return 0;
}
+static int gen8_huc_wait_verified(struct intel_huc *huc)
+{
+ struct drm_i915_private *i915 = huc_to_i915(huc);
+ u32 status;
+ int ret;
+
+ ret = __intel_wait_for_register(>uncore,
+ HUC_STATUS2,
+ HUC_FW_VERIFIED,
+ HUC_FW_VERIFIED,
+ 2, 50, );
+ if (ret)
+ DRM_ERROR("HuC: status %#x\n", status);
+ return ret;
+}
+
+static int gen11_huc_wait_verified(struct intel_huc *huc)
+{
+ struct drm_i915_private *i915 = huc_to_i915(huc);
+ int ret;
+
+ ret = __intel_wait_for_register(>uncore,
+ GEN11_HUC_KERNEL_LOAD_INFO,
+ HUC_LOAD_SUCCESSFUL,
+ HUC_LOAD_SUCCESSFUL,
+ 2, 50, NULL);
+ return ret;
+}
+
+static int huc_wait_verified(struct intel_huc *huc)
+{
+ struct drm_i915_private *i915 = huc_to_i915(huc);
+ int ret;
+
+ if (INTEL_GEN(i915) >= 11)
+ ret = gen11_huc_wait_verified(huc);
+ else
+ ret = gen8_huc_wait_verified(huc);
+ return ret;
+}
+
/**
* intel_huc_auth() - Authenticate HuC uCode
* @huc: intel_huc structure
@@ -56,7 +97,6 @@ int intel_huc_auth(struct intel_huc *huc)
struct drm_i915_private *i915 = huc_to_i915(huc);
struct intel_guc *guc = >guc;
struct i915_vma *vma;
- u32 status;
int ret;
if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
@@ -79,13 +119,9 @@ int intel_huc_auth(struct intel_huc *huc)
}
/* Check authentication status, it should be done by now */
- ret = __intel_wait_for_register(>uncore,
- HUC_STATUS2,
- HUC_FW_VERIFIED,
- HUC_FW_VERIFIED,
- 2, 50, );
+ ret = huc_wait_verified(huc);
if (ret) {
- DRM_ERROR("HuC: Firmware not verified %#x\n", status);
+ DRM_ERROR("HuC: Firmware not verified %d\n", ret);
goto fail_unpin;
}
@@ -122,7 +158,11 @@ int intel_huc_check_status(struct intel_huc *huc)
return -ENODEV;
with_intel_runtime_pm(dev_priv, wakeref)
- status = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
+ if (INTEL_GEN(dev_priv) >= 11)
+ status = I915_READ(GEN11_HUC_KERNEL_LOAD_INFO) &
+ HUC_LOAD_SUCCESSFUL;
+ else
+ status = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
return status;
}
--
2.19.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 16/22] drm/i915/guc: Create vfuncs for the GuC interrupts control functions
From: Oscar Mateo
Controlling and handling of the GuC interrupts is Gen specific.
Create virtual functions to avoid redundant runtime Gen checks.
Gen-specific versions of these functions will follow.
Signed-off-by: Oscar Mateo
Signed-off-by: Michal Wajdeczko
Cc: Rodrigo Vivi
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_drv.h | 22 ++
drivers/gpu/drm/i915/i915_irq.c | 18 --
drivers/gpu/drm/i915/intel_drv.h | 3 ---
drivers/gpu/drm/i915/intel_guc.h | 1 -
drivers/gpu/drm/i915/intel_uc.c | 6 +++---
5 files changed, 37 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 35d0782c077e..6c5260d91bc1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1574,6 +1574,13 @@ struct drm_i915_private {
u32 pm_guc_events;
u32 pipestat_irq_mask[I915_MAX_PIPES];
+ struct {
+ bool enabled;
+ void (*reset)(struct drm_i915_private *i915);
+ void (*enable)(struct drm_i915_private *i915);
+ void (*disable)(struct drm_i915_private *i915);
+ } guc_interrupts;
+
struct i915_hotplug hotplug;
struct intel_fbc fbc;
struct i915_drrs drrs;
@@ -2753,6 +2760,21 @@ extern void intel_irq_fini(struct drm_i915_private
*dev_priv);
int intel_irq_install(struct drm_i915_private *dev_priv);
void intel_irq_uninstall(struct drm_i915_private *dev_priv);
+static inline void intel_reset_guc_interrupts(struct drm_i915_private *i915)
+{
+ i915->guc_interrupts.reset(i915);
+}
+
+static inline void intel_enable_guc_interrupts(struct drm_i915_private *i915)
+{
+ i915->guc_interrupts.enable(i915);
+}
+
+static inline void intel_disable_guc_interrupts(struct drm_i915_private *i915)
+{
+ i915->guc_interrupts.disable(i915);
+}
+
static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
{
return dev_priv->gvt;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d934545445e1..e2f0cbee9345 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -554,7 +554,7 @@ void gen6_disable_rps_interrupts(struct drm_i915_private
*dev_priv)
gen6_reset_rps_interrupts(dev_priv);
}
-void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
+static void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
{
assert_rpm_wakelock_held(dev_priv);
@@ -563,26 +563,26 @@ void gen9_reset_guc_interrupts(struct drm_i915_private
*dev_priv)
spin_unlock_irq(_priv->irq_lock);
}
-void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
+static void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
{
assert_rpm_wakelock_held(dev_priv);
spin_lock_irq(_priv->irq_lock);
- if (!dev_priv->guc.interrupts_enabled) {
+ if (!dev_priv->guc_interrupts.enabled) {
WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
dev_priv->pm_guc_events);
- dev_priv->guc.interrupts_enabled = true;
+ dev_priv->guc_interrupts.enabled = true;
gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
}
spin_unlock_irq(_priv->irq_lock);
}
-void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
+static void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
{
assert_rpm_wakelock_held(dev_priv);
spin_lock_irq(_priv->irq_lock);
- dev_priv->guc.interrupts_enabled = false;
+ dev_priv->guc_interrupts.enabled = false;
gen6_disable_pm_irq(dev_priv, dev_priv->pm_guc_events);
@@ -4673,6 +4673,12 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
if (INTEL_GEN(dev_priv) >= 8)
rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
+ if (INTEL_GEN(dev_priv) >= 9) {
+ dev_priv->guc_interrupts.reset = gen9_reset_guc_interrupts;
+ dev_priv->guc_interrupts.enable = gen9_enable_guc_interrupts;
+ dev_priv->guc_interrupts.disable = gen9_disable_guc_interrupts;
+ }
+
if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
dev->driver->get_vblank_counter = g4x_get_vblank_counter;
else if (INTEL_GEN(dev_priv) >= 3)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a38b9cff5cd0..9b6cac90e891 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1627,9 +1627,6 @@ void gen8_irq_power_well_post_enable(struct
drm_i915_private *dev_priv,
u8 pipe_mask);
void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
u8 pipe_mask);
-void gen9_reset_guc_interrupts(struct drm_i915_private
[Intel-gfx] [PATCH v2 03/22] drm/i915/guc: Simplify preparation of GuC parameter block
Definition of the parameters block passed to GuC is about to change.
Slightly refactor code now to make upcoming patch smaller.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: John Spotswood
Reviewed-by: John Spotswood
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/intel_guc.c | 38 +++-
1 file changed, 23 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 3aabfa2d9198..c0e8b359b23a 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -333,19 +333,8 @@ static u32 guc_ctl_log_params_flags(struct intel_guc *guc)
return flags;
}
-/*
- * Initialise the GuC parameter block before starting the firmware
- * transfer. These parameters are read by the firmware on startup
- * and cannot be changed thereafter.
- */
-void intel_guc_init_params(struct intel_guc *guc)
+static void guc_prepare_params(struct intel_guc *guc, u32 *params)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
- u32 params[GUC_CTL_MAX_DWORDS];
- int i;
-
- memset(params, 0, sizeof(params));
-
/*
* GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
* second. This ARAR is calculated by:
@@ -360,9 +349,12 @@ void intel_guc_init_params(struct intel_guc *guc)
params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc);
params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc);
params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc);
+}
- for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
- DRM_DEBUG_DRIVER("param[%2d] = %#x\n", i, params[i]);
+static void guc_write_params(struct intel_guc *guc, const u32 *params)
+{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ int i;
/*
* All SOFT_SCRATCH registers are in FORCEWAKE_BLITTER domain and
@@ -373,12 +365,28 @@ void intel_guc_init_params(struct intel_guc *guc)
I915_WRITE(SOFT_SCRATCH(0), 0);
- for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
+ for (i = 0; i < GUC_CTL_MAX_DWORDS; i++) {
+ DRM_DEBUG_DRIVER("param[%2d] = %#x\n", i, params[i]);
I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
+ }
intel_uncore_forcewake_put(_priv->uncore, FORCEWAKE_BLITTER);
}
+/*
+ * Initialise the GuC parameter block before starting the firmware
+ * transfer. These parameters are read by the firmware on startup
+ * and cannot be changed thereafter.
+ */
+void intel_guc_init_params(struct intel_guc *guc)
+{
+ u32 params[GUC_CTL_MAX_DWORDS];
+
+ memset(params, 0, sizeof(params));
+ guc_prepare_params(guc, params);
+ guc_write_params(guc, params);
+}
+
int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len,
u32 *response_buf, u32 response_buf_size)
{
--
2.19.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 21/22] drm/i915/huc: Define HuC firmware version for Icelake
This patch adds the support to load HuC on ICL.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Anusha Srivatsa
Cc: Tony Ye
---
drivers/gpu/drm/i915/intel_huc_fw.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_huc_fw.c
b/drivers/gpu/drm/i915/intel_huc_fw.c
index 68d47c105939..b8e160dc4621 100644
--- a/drivers/gpu/drm/i915/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/intel_huc_fw.c
@@ -34,6 +34,10 @@
#define KBL_HUC_FW_MINOR 00
#define KBL_BLD_NUM 1810
+#define ICL_HUC_FW_MAJOR 8
+#define ICL_HUC_FW_MINOR 4
+#define ICL_BLD_NUM 3132
+
#define HUC_FW_PATH(platform, major, minor, bld_num) \
"i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
__stringify(minor) "_" __stringify(bld_num) ".bin"
@@ -50,6 +54,10 @@ MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
KBL_HUC_FW_MINOR, KBL_BLD_NUM)
MODULE_FIRMWARE(I915_KBL_HUC_UCODE);
+#define I915_ICL_HUC_UCODE HUC_FW_PATH(icl, ICL_HUC_FW_MAJOR, \
+ ICL_HUC_FW_MINOR, ICL_BLD_NUM)
+MODULE_FIRMWARE(I915_ICL_HUC_UCODE);
+
static void huc_fw_select(struct intel_uc_fw *huc_fw)
{
struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
@@ -76,6 +84,10 @@ static void huc_fw_select(struct intel_uc_fw *huc_fw)
huc_fw->path = I915_KBL_HUC_UCODE;
huc_fw->major_ver_wanted = KBL_HUC_FW_MAJOR;
huc_fw->minor_ver_wanted = KBL_HUC_FW_MINOR;
+ } else if (IS_ICELAKE(dev_priv)) {
+ huc_fw->path = I915_ICL_HUC_UCODE;
+ huc_fw->major_ver_wanted = ICL_HUC_FW_MAJOR;
+ huc_fw->minor_ver_wanted = ICL_HUC_FW_MINOR;
}
}
--
2.19.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 09/22] drm/i915/guc: Update GuC ADS object definition
New GuC firmwares use updated definitions for the Additional Data
Structures (ADS).
Signed-off-by: Michal Wajdeczko
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Fernando Pacheco
Cc: Joonas Lahtinen
Cc: John Spotswood
Cc: Tomasz Lis
---
drivers/gpu/drm/i915/intel_engine_cs.c | 5 ++
drivers/gpu/drm/i915/intel_guc_ads.c| 94 +++--
drivers/gpu/drm/i915/intel_guc_fwif.h | 89 +--
drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +
4 files changed, 117 insertions(+), 73 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index eea9bec04f1b..2a4d1527e171 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -231,6 +231,11 @@ __intel_engine_context_size(struct drm_i915_private
*dev_priv, u8 class)
}
}
+u32 intel_class_context_size(struct drm_i915_private *dev_priv, u8 class)
+{
+ return __intel_engine_context_size(dev_priv, class);
+}
+
static u32 __engine_mmio_base(struct drm_i915_private *i915,
const struct engine_mmio_base *bases)
{
diff --git a/drivers/gpu/drm/i915/intel_guc_ads.c
b/drivers/gpu/drm/i915/intel_guc_ads.c
index bec62f34b15a..abab5cb6909a 100644
--- a/drivers/gpu/drm/i915/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/intel_guc_ads.c
@@ -51,7 +51,7 @@ static void guc_policies_init(struct guc_policies *policies)
policies->max_num_work_items = POLICY_MAX_NUM_WI;
for (p = 0; p < GUC_CLIENT_PRIORITY_NUM; p++) {
- for (i = GUC_RENDER_ENGINE; i < GUC_MAX_ENGINES_NUM; i++) {
+ for (i = 0; i < GUC_MAX_ENGINE_CLASSES; i++) {
policy = >policy[p][i];
guc_policy_init(policy);
@@ -61,6 +61,11 @@ static void guc_policies_init(struct guc_policies *policies)
policies->is_valid = 1;
}
+static void guc_ct_pool_entries_init(struct guc_ct_pool_entry *pool, u32 num)
+{
+ memset(pool, 0, num * sizeof(*pool));
+}
+
/*
* The first 80 dwords of the register state context, containing the
* execlists and ppgtt registers.
@@ -75,20 +80,21 @@ static void guc_policies_init(struct guc_policies *policies)
int intel_guc_ads_create(struct intel_guc *guc)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
- struct i915_vma *vma, *kernel_ctx_vma;
- struct page *page;
+ struct i915_vma *vma;
/* The ads obj includes the struct itself and buffers passed to GuC */
struct {
struct guc_ads ads;
struct guc_policies policies;
struct guc_mmio_reg_state reg_state;
+ struct guc_gt_system_info system_info;
+ struct guc_clients_info clients_info;
+ struct guc_ct_pool_entry ct_pool[GUC_CT_POOL_SIZE];
u8 reg_state_buffer[GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE];
} __packed *blob;
- struct intel_engine_cs *engine;
- enum intel_engine_id id;
- const u32 skipped_offset = LRC_HEADER_PAGES * PAGE_SIZE;
const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE;
u32 base;
+ u8 engine_class;
+ int ret;
GEM_BUG_ON(guc->ads_vma);
@@ -98,51 +104,67 @@ int intel_guc_ads_create(struct intel_guc *guc)
guc->ads_vma = vma;
- page = i915_vma_first_page(vma);
- blob = kmap(page);
+ blob = i915_gem_object_pin_map(guc->ads_vma->obj, I915_MAP_WB);
+ if (IS_ERR(blob)) {
+ ret = PTR_ERR(blob);
+ goto err_vma;
+ }
/* GuC scheduling policies */
guc_policies_init(>policies);
- /* MMIO reg state */
- for_each_engine(engine, dev_priv, id) {
- blob->reg_state.white_list[engine->guc_id].mmio_start =
- engine->mmio_base + GUC_MMIO_WHITE_LIST_START;
-
- /* Nothing to be saved or restored for now. */
- blob->reg_state.white_list[engine->guc_id].count = 0;
- }
-
/*
-* The GuC requires a "Golden Context" when it reinitialises
-* engines after a reset. Here we use the Render ring default
-* context, which must already exist and be pinned in the GGTT,
-* so its address won't change after we've told the GuC where
-* to find it. Note that we have to skip our header (1 page),
-* because our GuC shared data is there.
+* GuC expects a per-engine-class context image and size
+* (minus hwsp and ring context). The context image will be
+* used to reinitialize engines after a reset. It must exist
+* and be pinned in the GGTT, so that the address won't change after
+* we have told GuC where to find it. The context size will be used
+* to validate that the LRC base + size fall within allowed GGTT.
*/
- kernel_ctx_vma =
[Intel-gfx] [PATCH v2 07/22] drm/i915/guc: Update GuC sleep status values
New GuC firmwares use updated sleep status definitions.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Daniele Ceraolo Spurio
Cc: John Spotswood
---
drivers/gpu/drm/i915/intel_guc_fwif.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 64b56da9775c..25d57c819e3f 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -648,9 +648,9 @@ enum intel_guc_report_status {
};
enum intel_guc_sleep_state_status {
- INTEL_GUC_SLEEP_STATE_SUCCESS = 0x0,
- INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x1,
- INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x2
+ INTEL_GUC_SLEEP_STATE_SUCCESS = 0x1,
+ INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x2,
+ INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x3
#define INTEL_GUC_SLEEP_STATE_INVALID_MASK 0x8000
};
--
2.19.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 20/22] drm/i915/guc: Define GuC firmware version for Icelake
Define GuC firmware version for Icelake.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_guc_fw.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c
b/drivers/gpu/drm/i915/intel_guc_fw.c
index c937a648c2a1..c88a089885a0 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -55,9 +55,16 @@
#define KBL_GUC_FW_PATCH 3
#define KBL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(KBL)
+#define ICL_GUC_FW_PREFIX icl
+#define ICL_GUC_FW_MAJOR 32
+#define ICL_GUC_FW_MINOR 0
+#define ICL_GUC_FW_PATCH 3
+#define ICL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(ICL)
+
MODULE_FIRMWARE(SKL_GUC_FIRMWARE_PATH);
MODULE_FIRMWARE(BXT_GUC_FIRMWARE_PATH);
MODULE_FIRMWARE(KBL_GUC_FIRMWARE_PATH);
+MODULE_FIRMWARE(ICL_GUC_FIRMWARE_PATH);
static void guc_fw_select(struct intel_uc_fw *guc_fw)
{
@@ -73,6 +80,10 @@ static void guc_fw_select(struct intel_uc_fw *guc_fw)
guc_fw->path = i915_modparams.guc_firmware_path;
guc_fw->major_ver_wanted = 0;
guc_fw->minor_ver_wanted = 0;
+ } else if (IS_ICELAKE(i915)) {
+ guc_fw->path = ICL_GUC_FIRMWARE_PATH;
+ guc_fw->major_ver_wanted = ICL_GUC_FW_MAJOR;
+ guc_fw->minor_ver_wanted = ICL_GUC_FW_MINOR;
} else if (IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) {
guc_fw->path = KBL_GUC_FIRMWARE_PATH;
guc_fw->major_ver_wanted = KBL_GUC_FW_MAJOR;
--
2.19.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 17/22] drm/i915/guc: Correctly handle GuC interrupts on Gen11
From: Oscar Mateo
The GuC interrupts now get their own interrupt vector (instead of
sharing a register with the PM interrupts) so handle appropriately.
v2: (Chris)
v3: rebased (Michal)
Bspec: 19820
Signed-off-by: Oscar Mateo
Signed-off-by: Michal Wajdeczko
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_drv.h | 6 ++-
drivers/gpu/drm/i915/i915_irq.c | 64 ++--
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_guc_reg.h | 18
4 files changed, 85 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6c5260d91bc1..973f6c724c36 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1571,7 +1571,11 @@ struct drm_i915_private {
u32 pm_imr;
u32 pm_ier;
u32 pm_rps_events;
- u32 pm_guc_events;
+ union {
+ /* RPS and GuC share a register pre-Gen11 */
+ u32 pm_guc_events;
+ u32 guc_events;
+ };
u32 pipestat_irq_mask[I915_MAX_PIPES];
struct {
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index e2f0cbee9345..5580f00a3d28 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -592,6 +592,41 @@ static void gen9_disable_guc_interrupts(struct
drm_i915_private *dev_priv)
gen9_reset_guc_interrupts(dev_priv);
}
+static void gen11_reset_guc_interrupts(struct drm_i915_private *i915)
+{
+ spin_lock_irq(>irq_lock);
+ gen11_reset_one_iir(i915, 0, GEN11_GUC);
+ spin_unlock_irq(>irq_lock);
+}
+
+static void gen11_enable_guc_interrupts(struct drm_i915_private *dev_priv)
+{
+ spin_lock_irq(_priv->irq_lock);
+ if (!dev_priv->guc_interrupts.enabled) {
+ u32 guc_events = dev_priv->guc_events << 16;
+
+ WARN_ON_ONCE(gen11_reset_one_iir(dev_priv, 0, GEN11_GUC));
+ I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, guc_events);
+ I915_WRITE(GEN11_GUC_SG_INTR_MASK, ~guc_events);
+ dev_priv->guc_interrupts.enabled = true;
+ }
+ spin_unlock_irq(_priv->irq_lock);
+}
+
+static void gen11_disable_guc_interrupts(struct drm_i915_private *dev_priv)
+{
+ spin_lock_irq(_priv->irq_lock);
+ dev_priv->guc_interrupts.enabled = false;
+
+ I915_WRITE(GEN11_GUC_SG_INTR_MASK, ~0);
+ I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, 0);
+
+ spin_unlock_irq(_priv->irq_lock);
+ synchronize_irq(dev_priv->drm.irq);
+
+ gen11_reset_guc_interrupts(dev_priv);
+}
+
/**
* bdw_update_port_irq - update DE port interrupt
* @dev_priv: driver private
@@ -1861,6 +1896,12 @@ static void gen9_guc_irq_handler(struct drm_i915_private
*dev_priv, u32 gt_iir)
intel_guc_to_host_event_handler(_priv->guc);
}
+static void gen11_guc_irq_handler(struct drm_i915_private *i915, u16 iir)
+{
+ if (iir & GEN11_GUC_INTR_GUC2HOST)
+ intel_guc_to_host_event_handler(>guc);
+}
+
static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
{
enum pipe pipe;
@@ -2983,6 +3024,9 @@ static void
gen11_other_irq_handler(struct drm_i915_private * const i915,
const u8 instance, const u16 iir)
{
+ if (instance == OTHER_GUC_INSTANCE)
+ return gen11_guc_irq_handler(i915, iir);
+
if (instance == OTHER_GTPM_INSTANCE)
return gen11_rps_irq_handler(i915, iir);
@@ -3501,6 +3545,8 @@ static void gen11_gt_irq_reset(struct drm_i915_private
*dev_priv)
I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
+ I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, 0);
+ I915_WRITE(GEN11_GUC_SG_INTR_MASK, ~0);
}
static void gen11_irq_reset(struct drm_device *dev)
@@ -4143,6 +4189,10 @@ static void gen11_gt_irq_postinstall(struct
drm_i915_private *dev_priv)
dev_priv->pm_imr = ~dev_priv->pm_ier;
I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
+
+ /* Same thing for GuC interrupts */
+ I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, 0);
+ I915_WRITE(GEN11_GUC_SG_INTR_MASK, ~0);
}
static void icp_irq_postinstall(struct drm_device *dev)
@@ -4643,8 +4693,12 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
for (i = 0; i < MAX_L3_SLICES; ++i)
dev_priv->l3_parity.remap_info[i] = NULL;
- if (HAS_GUC_SCHED(dev_priv))
- dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT;
+ if (HAS_GUC_SCHED(dev_priv)) {
+ if (INTEL_GEN(dev_priv) < 11)
+ dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT;
+ else
+ dev_priv->guc_events = GEN11_GUC_INTR_GUC2HOST;
+ }
/* Let's track the enabled rps events */
[Intel-gfx] [PATCH v2 12/22] drm/i915/guc: Treat GuC initialization failure as -EIO
There is no fallback to execlists, but instead of aborting whole
driver load, just mark it as wedged.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 3 ++-
drivers/gpu/drm/i915/intel_uc.c | 6 ++
2 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 0a818a60ad31..ac64a6fd9b91 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4963,7 +4963,8 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
mutex_lock(_priv->drm.struct_mutex);
intel_uc_fini_hw(dev_priv);
err_uc_init:
- intel_uc_fini(dev_priv);
+ if (ret != -EIO)
+ intel_uc_fini(dev_priv);
err_pm:
if (ret != -EIO) {
intel_cleanup_gt_powersave(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 8e5e4226df53..03bc2a0ee34b 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -435,12 +435,10 @@ int intel_uc_init_hw(struct drm_i915_private *i915)
/*
* Note that there is no fallback as either user explicitly asked for
* the GuC or driver default option was to run with the GuC enabled.
+* Return -EIO to just disable GPU submission but keep KMS alive.
*/
- if (GEM_WARN_ON(ret == -EIO))
- ret = -EINVAL;
-
dev_err(i915->drm.dev, "GuC initialization failed %d\n", ret);
- return ret;
+ return -EIO;
}
void intel_uc_fini_hw(struct drm_i915_private *i915)
--
2.19.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 14/22] drm/i915/guc: New GuC scratch registers for Gen11
Gen11 adds new set of scratch registers that can be used for MMIO
based Host-to-Guc communication. Due to limited number of these
registers it is expected that host will use them only for command
transport buffers (CTB) communication setup if one is available.
Bspec: 21044
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_guc.c | 12 +---
drivers/gpu/drm/i915/intel_guc_reg.h | 3 +++
2 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 5bc9bc7c956a..e54de551b567 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -56,9 +56,15 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
enum forcewake_domains fw_domains = 0;
unsigned int i;
- guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
- guc->send_regs.count = GUC_MAX_MMIO_MSG_LEN;
- BUILD_BUG_ON(GUC_MAX_MMIO_MSG_LEN > SOFT_SCRATCH_COUNT);
+ if (HAS_GUC_CT(dev_priv) && INTEL_GEN(dev_priv) >= 11) {
+ guc->send_regs.base =
+ i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0));
+ guc->send_regs.count = GEN11_SOFT_SCRATCH_COUNT;
+ } else {
+ guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
+ guc->send_regs.count = GUC_MAX_MMIO_MSG_LEN;
+ BUILD_BUG_ON(GUC_MAX_MMIO_MSG_LEN > SOFT_SCRATCH_COUNT);
+ }
for (i = 0; i < guc->send_regs.count; i++) {
fw_domains |= intel_uncore_forcewake_for_reg(_priv->uncore,
diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h
b/drivers/gpu/drm/i915/intel_guc_reg.h
index aec02eddbaed..d26de5193568 100644
--- a/drivers/gpu/drm/i915/intel_guc_reg.h
+++ b/drivers/gpu/drm/i915/intel_guc_reg.h
@@ -51,6 +51,9 @@
#define SOFT_SCRATCH(n)_MMIO(0xc180 + (n) * 4)
#define SOFT_SCRATCH_COUNT 16
+#define GEN11_SOFT_SCRATCH(n) _MMIO(0x190240 + (n) * 4)
+#define GEN11_SOFT_SCRATCH_COUNT 4
+
#define UOS_RSA_SCRATCH(i) _MMIO(0xc200 + (i) * 4)
#define UOS_RSA_SCRATCH_COUNT 64
--
2.19.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 11/22] drm/i915/guc: Reset GuC ADS during sanitize
GuC stores some data in there, which might be stale after a reset.
Reinitialize whole ADS in case any part of it was corrupted during
previous GuC run.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: MichaĹ Winiarski
Cc: Tomasz Lis
---
drivers/gpu/drm/i915/intel_guc.h | 2 +
drivers/gpu/drm/i915/intel_guc_ads.c | 85 ++--
drivers/gpu/drm/i915/intel_guc_ads.h | 1 +
3 files changed, 57 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 2c59ff8d9f39..4f3cf8eddfe6 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -26,6 +26,7 @@
#define _INTEL_GUC_H_
#include "intel_uncore.h"
+#include "intel_guc_ads.h"
#include "intel_guc_fw.h"
#include "intel_guc_fwif.h"
#include "intel_guc_ct.h"
@@ -177,6 +178,7 @@ u32 intel_guc_reserved_gtt_size(struct intel_guc *guc);
static inline int intel_guc_sanitize(struct intel_guc *guc)
{
intel_uc_fw_sanitize(>fw);
+ intel_guc_ads_reset(guc);
return 0;
}
diff --git a/drivers/gpu/drm/i915/intel_guc_ads.c
b/drivers/gpu/drm/i915/intel_guc_ads.c
index abab5cb6909a..97926effb944 100644
--- a/drivers/gpu/drm/i915/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/intel_guc_ads.c
@@ -72,43 +72,28 @@ static void guc_ct_pool_entries_init(struct
guc_ct_pool_entry *pool, u32 num)
*/
#define LR_HW_CONTEXT_SIZE (80 * sizeof(u32))
-/**
- * intel_guc_ads_create() - creates GuC ADS
- * @guc: intel_guc struct
- *
- */
-int intel_guc_ads_create(struct intel_guc *guc)
+/* The ads obj includes the struct itself and buffers passed to GuC */
+struct __guc_ads_blob {
+ struct guc_ads ads;
+ struct guc_policies policies;
+ struct guc_mmio_reg_state reg_state;
+ struct guc_gt_system_info system_info;
+ struct guc_clients_info clients_info;
+ struct guc_ct_pool_entry ct_pool[GUC_CT_POOL_SIZE];
+ u8 reg_state_buffer[GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE];
+} __packed;
+
+static int __guc_ads_reinit(struct intel_guc *guc)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
- struct i915_vma *vma;
- /* The ads obj includes the struct itself and buffers passed to GuC */
- struct {
- struct guc_ads ads;
- struct guc_policies policies;
- struct guc_mmio_reg_state reg_state;
- struct guc_gt_system_info system_info;
- struct guc_clients_info clients_info;
- struct guc_ct_pool_entry ct_pool[GUC_CT_POOL_SIZE];
- u8 reg_state_buffer[GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE];
- } __packed *blob;
+ struct __guc_ads_blob *blob;
const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE;
u32 base;
u8 engine_class;
- int ret;
-
- GEM_BUG_ON(guc->ads_vma);
-
- vma = intel_guc_allocate_vma(guc, PAGE_ALIGN(sizeof(*blob)));
- if (IS_ERR(vma))
- return PTR_ERR(vma);
-
- guc->ads_vma = vma;
blob = i915_gem_object_pin_map(guc->ads_vma->obj, I915_MAP_WB);
- if (IS_ERR(blob)) {
- ret = PTR_ERR(blob);
- goto err_vma;
- }
+ if (IS_ERR(blob))
+ return PTR_ERR(blob);
/* GuC scheduling policies */
guc_policies_init(>policies);
@@ -142,7 +127,7 @@ int intel_guc_ads_create(struct intel_guc *guc)
blob->system_info.vebox_enable_mask = VEBOX_MASK(dev_priv);
blob->system_info.vdbox_sfc_support_mask =
RUNTIME_INFO(dev_priv)->vdbox_sfc_access;
- base = intel_guc_ggtt_offset(guc, vma);
+ base = intel_guc_ggtt_offset(guc, guc->ads_vma);
/* Clients info */
guc_ct_pool_entries_init(blob->ct_pool, ARRAY_SIZE(blob->ct_pool));
@@ -161,6 +146,32 @@ int intel_guc_ads_create(struct intel_guc *guc)
i915_gem_object_unpin_map(guc->ads_vma->obj);
return 0;
+}
+
+/**
+ * intel_guc_ads_create() - creates GuC ADS
+ * @guc: intel_guc struct
+ *
+ */
+int intel_guc_ads_create(struct intel_guc *guc)
+{
+ const u32 size = PAGE_ALIGN(sizeof(struct __guc_ads_blob));
+ struct i915_vma *vma;
+ int ret;
+
+ GEM_BUG_ON(guc->ads_vma);
+
+ vma = intel_guc_allocate_vma(guc, size);
+ if (IS_ERR(vma))
+ return PTR_ERR(vma);
+
+ guc->ads_vma = vma;
+
+ ret = __guc_ads_reinit(guc);
+ if (ret)
+ goto err_vma;
+
+ return 0;
err_vma:
i915_vma_unpin_and_release(>ads_vma, 0);
@@ -171,3 +182,15 @@ void intel_guc_ads_destroy(struct intel_guc *guc)
{
i915_vma_unpin_and_release(>ads_vma, 0);
}
+
+/**
+ * intel_guc_ads_reset() - resets GuC ADS
+ * @guc: intel_guc struct
+ *
+ */
+void intel_guc_ads_reset(struct intel_guc *guc)
+{
+ if (!guc->ads_vma)
+ return;
+ __guc_ads_reinit(guc);
+}
diff --git a/drivers/gpu/drm/i915/intel_guc_ads.h
[Intel-gfx] [PATCH v2 18/22] drm/i915/guc: Update GuC CTB response definition
Current GuC firmwares identify response message in a different way.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Kelvin Gardiner
Cc: John Spotswood
---
drivers/gpu/drm/i915/intel_guc_ct.c | 2 +-
drivers/gpu/drm/i915/intel_guc_fwif.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_ct.c
b/drivers/gpu/drm/i915/intel_guc_ct.c
index dde1dc0d6e69..2d5dc2aa22a7 100644
--- a/drivers/gpu/drm/i915/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/intel_guc_ct.c
@@ -565,7 +565,7 @@ static inline unsigned int ct_header_get_action(u32 header)
static inline bool ct_header_is_response(u32 header)
{
- return ct_header_get_action(header) == INTEL_GUC_ACTION_DEFAULT;
+ return !!(header & GUC_CT_MSG_IS_RESPONSE);
}
static int ctb_read(struct intel_guc_ct_buffer *ctb, u32 *data)
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 68dfeecf7b26..115c693daf8e 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -361,6 +361,7 @@ struct guc_ct_buffer_desc {
*
* bit[4..0] message len (in dwords)
* bit[7..5] reserved
+ * bit[8] response (G2H only)
* bit[8] write fence to desc
* bit[9] write status to H2G buff
* bit[10] send status (via G2H)
@@ -369,6 +370,7 @@ struct guc_ct_buffer_desc {
*/
#define GUC_CT_MSG_LEN_SHIFT 0
#define GUC_CT_MSG_LEN_MASK0x1F
+#define GUC_CT_MSG_IS_RESPONSE (1 << 8)
#define GUC_CT_MSG_WRITE_FENCE_TO_DESC (1 << 8)
#define GUC_CT_MSG_WRITE_STATUS_TO_BUFF(1 << 9)
#define GUC_CT_MSG_SEND_STATUS (1 << 10)
--
2.19.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 13/22] drm/i915/guc: New GuC interrupt register for Gen11
Gen11 defines new more flexible Host-to-GuC interrupt register.
Now the host can write any 32-bit payload to trigger an interrupt
and GuC can additionally read this payload from the register.
Current GuC firmware ignores the payload so we just write 0.
Bspec: 21043
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_guc.c | 14 +-
drivers/gpu/drm/i915/intel_guc_reg.h | 1 +
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 483c7019f817..5bc9bc7c956a 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -34,6 +34,13 @@ static void gen8_guc_raise_irq(struct intel_guc *guc)
I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
}
+static void gen11_guc_raise_irq(struct intel_guc *guc)
+{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
+ I915_WRITE(GEN11_GUC_HOST_INTERRUPT, 0);
+}
+
static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
{
GEM_BUG_ON(!guc->send_regs.base);
@@ -63,6 +70,8 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
void intel_guc_init_early(struct intel_guc *guc)
{
+ struct drm_i915_private *i915 = guc_to_i915(guc);
+
intel_guc_fw_init_early(guc);
intel_guc_ct_init_early(>ct);
intel_guc_log_init_early(>log);
@@ -71,7 +80,10 @@ void intel_guc_init_early(struct intel_guc *guc)
spin_lock_init(>irq_lock);
guc->send = intel_guc_send_nop;
guc->handler = intel_guc_to_host_event_handler_nop;
- guc->notify = gen8_guc_raise_irq;
+ if (INTEL_GEN(i915) >= 11)
+ guc->notify = gen11_guc_raise_irq;
+ else
+ guc->notify = gen8_guc_raise_irq;
}
static int guc_init_wq(struct intel_guc *guc)
diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h
b/drivers/gpu/drm/i915/intel_guc_reg.h
index 57e7ad522c2f..aec02eddbaed 100644
--- a/drivers/gpu/drm/i915/intel_guc_reg.h
+++ b/drivers/gpu/drm/i915/intel_guc_reg.h
@@ -103,6 +103,7 @@
#define GUC_SEND_INTERRUPT _MMIO(0xc4c8)
#define GUC_SEND_TRIGGER (1<<0)
+#define GEN11_GUC_HOST_INTERRUPT _MMIO(0x1901f0)
#define GUC_NUM_DOORBELLS 256
--
2.19.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 19/22] drm/i915/guc: Enable GuC CTB communication on Gen11
Gen11 GuC firmware expects H2G command messages to be sent over CTB
(command transport buffers).
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: John Spotswood
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f893c2cbce15..8af8820b3df8 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -743,6 +743,7 @@ static const struct intel_device_info intel_cannonlake_info
= {
}, \
GEN(11), \
.ddb_size = 2048, \
+ .has_guc_ct = 1, \
.has_logical_ring_elsq = 1, \
.color = { .degamma_lut_size = 33, .gamma_lut_size = 1024 }
--
2.19.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 00/22] GuC 32.0.3
New GuC firmwares (for SKL, BXT, KBL, ICL) with updated ABI interface. v2: only HuC authentication is supported Michal Wajdeczko (20): drm/i915/guc: Change platform default GuC mode drm/i915/guc: Don't allow GuC submission drm/i915/guc: Simplify preparation of GuC parameter block drm/i915/guc: Update GuC firmware versions and names drm/i915/guc: Update GuC firmware CSS header drm/i915/guc: Update GuC boot parameters drm/i915/guc: Update GuC sleep status values drm/i915/guc: Update GuC sample-forcewake command drm/i915/guc: Update GuC ADS object definition drm/i915/guc: Always ask GuC to update power domain states drm/i915/guc: Reset GuC ADS during sanitize drm/i915/guc: Treat GuC initialization failure as -EIO drm/i915/guc: New GuC interrupt register for Gen11 drm/i915/guc: New GuC scratch registers for Gen11 drm/i915/huc: New HuC status register for Gen11 drm/i915/guc: Update GuC CTB response definition drm/i915/guc: Enable GuC CTB communication on Gen11 drm/i915/guc: Define GuC firmware version for Icelake drm/i915/huc: Define HuC firmware version for Icelake HAX: prevent CI failures on configs with forced GuC submission Oscar Mateo (2): drm/i915/guc: Create vfuncs for the GuC interrupts control functions drm/i915/guc: Correctly handle GuC interrupts on Gen11 drivers/gpu/drm/i915/i915_drv.h | 28 +++- drivers/gpu/drm/i915/i915_gem.c | 3 +- drivers/gpu/drm/i915/i915_irq.c | 80 +- drivers/gpu/drm/i915/i915_pci.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_drv.h| 3 - drivers/gpu/drm/i915/intel_engine_cs.c | 5 + drivers/gpu/drm/i915/intel_guc.c| 98 +++- drivers/gpu/drm/i915/intel_guc.h| 3 +- drivers/gpu/drm/i915/intel_guc_ads.c| 161 +--- drivers/gpu/drm/i915/intel_guc_ads.h| 1 + drivers/gpu/drm/i915/intel_guc_ct.c | 2 +- drivers/gpu/drm/i915/intel_guc_fw.c | 87 ++- drivers/gpu/drm/i915/intel_guc_fwif.h | 161 +--- drivers/gpu/drm/i915/intel_guc_reg.h| 25 +++ drivers/gpu/drm/i915/intel_guc_submission.c | 4 - drivers/gpu/drm/i915/intel_huc.c| 56 ++- drivers/gpu/drm/i915/intel_huc_fw.c | 12 ++ drivers/gpu/drm/i915/intel_ringbuffer.h | 2 + drivers/gpu/drm/i915/intel_uc.c | 43 -- drivers/gpu/drm/i915/intel_uc_fw.c | 20 +-- 21 files changed, 525 insertions(+), 271 deletions(-) -- 2.19.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 08/22] drm/i915/guc: Update GuC sample-forcewake command
New GuC firmwares use different action code value for this command.
Signed-off-by: Michal Wajdeczko
Cc: John Spotswood
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_guc_fwif.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 25d57c819e3f..dd9d99dc2aca 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -620,7 +620,6 @@ enum intel_guc_action {
INTEL_GUC_ACTION_DEFAULT = 0x0,
INTEL_GUC_ACTION_REQUEST_PREEMPTION = 0x2,
INTEL_GUC_ACTION_REQUEST_ENGINE_RESET = 0x3,
- INTEL_GUC_ACTION_SAMPLE_FORCEWAKE = 0x6,
INTEL_GUC_ACTION_ALLOCATE_DOORBELL = 0x10,
INTEL_GUC_ACTION_DEALLOCATE_DOORBELL = 0x20,
INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE = 0x30,
@@ -628,6 +627,7 @@ enum intel_guc_action {
INTEL_GUC_ACTION_ENTER_S_STATE = 0x501,
INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
+ INTEL_GUC_ACTION_SAMPLE_FORCEWAKE = 0x3005,
INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505,
INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 0x4506,
--
2.19.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 10/22] drm/i915/guc: Always ask GuC to update power domain states
With newer GuC firmware it is always ok to ask GuC to update power
domain states. Make it an unconditional initialization step.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: John Spotswood
---
drivers/gpu/drm/i915/intel_guc_submission.c | 4
drivers/gpu/drm/i915/intel_uc.c | 8
2 files changed, 4 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c
b/drivers/gpu/drm/i915/intel_guc_submission.c
index dea87253d141..856505dbbe91 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -1319,10 +1319,6 @@ int intel_guc_submission_enable(struct intel_guc *guc)
GEM_BUG_ON(!guc->execbuf_client);
- err = intel_guc_sample_forcewake(guc);
- if (err)
- return err;
-
err = guc_clients_enable(guc);
if (err)
return err;
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 21310b917ccc..8e5e4226df53 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -405,14 +405,14 @@ int intel_uc_init_hw(struct drm_i915_private *i915)
goto err_communication;
}
+ ret = intel_guc_sample_forcewake(guc);
+ if (ret)
+ goto err_communication;
+
if (USES_GUC_SUBMISSION(i915)) {
ret = intel_guc_submission_enable(guc);
if (ret)
goto err_communication;
- } else if (INTEL_GEN(i915) < 11) {
- ret = intel_guc_sample_forcewake(guc);
- if (ret)
- goto err_communication;
}
dev_info(i915->drm.dev, "GuC firmware version %u.%u\n",
--
2.19.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 22/22] HAX: prevent CI failures on configs with forced GuC submission
Some CI systems might be configured to run with no longer supported
configuration "enable_guc=3" or "enable_guc=1". Hack that ;)
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/intel_uc.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index a1a068511fd9..c40c8e6e6cd9 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -105,6 +105,12 @@ static void sanitize_options_early(struct drm_i915_private
*i915)
struct intel_uc_fw *guc_fw = >guc.fw;
struct intel_uc_fw *huc_fw = >huc.fw;
+ /* HAX: prevent CI failures on configs with forced GuC */
+ if (i915_modparams.enable_guc & ENABLE_GUC_SUBMISSION) {
+ DRM_DEBUG_DRIVER("turning off ENABLE_GUC_SUBMISSION\n");
+ i915_modparams.enable_guc &= ~ENABLE_GUC_SUBMISSION;
+ }
+
/* A negative value means "use platform default" */
if (i915_modparams.enable_guc < 0)
i915_modparams.enable_guc = __get_platform_enable_guc(i915);
--
2.19.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Disable read only ppgtt support for gen11
Quoting Mika Kuoppala (2019-04-11 09:30:34) > On gen11 writing to read only ppgtt page causes a gpu hang. > This behaviour is different than with previous gen where > read only ppgtt access is supported. On those, the write > is just dropped without visible side effects. > > Disable ro ppgtt support on gen11 until a solution can > be found to bring it into line with its predecessors. > > References: HSDES#1807136187 > References: https://bugzilla.freedesktop.org/show_bug.cgi?id=108569 > Cc: Chris Wilson > Signed-off-by: Mika Kuoppala Acked-by: Chris Wilson Lets see if I remembered to stick those vm->has_read_only checks everywhere we needed them (and remembered to exercise them -- a bit of a catch 22, if I forgot the check, I probably forgot the test as well). Thanks, -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Disable read only ppgtt support for gen11
On gen11 writing to read only ppgtt page causes a gpu hang. This behaviour is different than with previous gen where read only ppgtt access is supported. On those, the write is just dropped without visible side effects. Disable ro ppgtt support on gen11 until a solution can be found to bring it into line with its predecessors. References: HSDES#1807136187 References: https://bugzilla.freedesktop.org/show_bug.cgi?id=108569 Cc: Chris Wilson Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_gem_gtt.c | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 736c845eb77f..caae8cdafc1a 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -1548,8 +1548,13 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915) ppgtt_init(i915, ppgtt); - /* From bdw, there is support for read-only pages in the PPGTT. */ - ppgtt->vm.has_read_only = true; + /* +* From bdw, there is hw support for read-only pages in the PPGTT. +* +* Gen11 has HSDES#:1807136187 unresolved. Disable ro support +* for now. +*/ + ppgtt->vm.has_read_only = INTEL_GEN(i915) != 11; /* There are only few exceptions for gen >=6. chv and bxt. * And we are not sure about the latter so play safe for now. -- 2.17.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [v2 0/7] Add Multi Segment Gamma Support
>> >> >-Original Message- >> >From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On >> >Behalf Of Ville Syrjälä >> >Sent: Monday, April 8, 2019 9:38 PM >> >To: Shankar, Uma >> >Cc: dcasta...@chromium.org; intel-gfx@lists.freedesktop.org; dri- >> >de...@lists.freedesktop.org; seanp...@chromium.org; Syrjala, Ville >> >; Lankhorst, Maarten >> > >> >Subject: Re: [Intel-gfx] [v2 0/7] Add Multi Segment Gamma Support >> > >> >On Mon, Apr 08, 2019 at 03:59:51PM +, Shankar, Uma wrote: >> >> >> >> >> >> >-Original Message- >> >> >From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] >> >> >On Behalf Of Ville Syrjälä >> >> >Sent: Monday, April 8, 2019 9:15 PM >> >> >To: Shankar, Uma >> >> >Cc: dcasta...@chromium.org; intel-gfx@lists.freedesktop.org; dri- >> >> >de...@lists.freedesktop.org; seanp...@chromium.org; Syrjala, Ville >> >> >; Lankhorst, Maarten >> >> > >> >> >Subject: Re: [Intel-gfx] [v2 0/7] Add Multi Segment Gamma Support >> >> > >> >> >On Mon, Apr 08, 2019 at 03:40:39PM +, Shankar, Uma wrote: >> >> >> >> >> >> >> >> >> >-Original Message- >> >> >> >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] >> >> >> >Sent: Monday, April 8, 2019 8:27 PM >> >> >> >To: Shankar, Uma >> >> >> >Cc: dcasta...@chromium.org; intel-gfx@lists.freedesktop.org; >> >> >> >dri- de...@lists.freedesktop.org; seanp...@chromium.org; >> >> >> >Syrjala, Ville ; Lankhorst, Maarten >> >> >> > >> >> >> >Subject: Re: [Intel-gfx] [v2 0/7] Add Multi Segment Gamma >> >> >> >Support >> >> >> > >> >> >> >On Mon, Apr 08, 2019 at 02:40:51PM +, Shankar, Uma wrote: >> >> >> >> >> >> >> >> >> >> >> >> >-Original Message- >> >> >> >> >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] >> >> >> >> >Sent: Monday, April 8, 2019 6:01 PM >> >> >> >> >To: Shankar, Uma >> >> >> >> >Cc: dcasta...@chromium.org; intel-gfx@lists.freedesktop.org; >> >> >> >> >dri- de...@lists.freedesktop.org; seanp...@chromium.org; >> >> >> >> >Syrjala, Ville ; Lankhorst, Maarten >> >> >> >> > >> >> >> >> >Subject: Re: [Intel-gfx] [v2 0/7] Add Multi Segment Gamma >> >> >> >> >Support >> >> >> >> > >> >> >> >> >On Mon, Apr 08, 2019 at 12:26:23PM +, Shankar, Uma wrote: >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >-Original Message- >> >> >> >> >> >From: dri-devel >> >> >> >> >> >[mailto:dri-devel-boun...@lists.freedesktop.org] >> >> >> >> >> >On Behalf Of Ville Syrjälä >> >> >> >> >> >Sent: Friday, April 5, 2019 9:42 PM >> >> >> >> >> >To: Shankar, Uma >> >> >> >> >> >Cc: dcasta...@chromium.org; >> >> >> >> >> >intel-gfx@lists.freedesktop.org; >> >> >> >> >> >dri- de...@lists.freedesktop.org; seanp...@chromium.org; >> >> >> >> >> >Syrjala, Ville ; Lankhorst, >> >> >> >> >> >Maarten >> >> >> >> >> >Subject: Re: [Intel-gfx] [v2 0/7] Add Multi Segment Gamma >> >> >> >> >> >Support >> >> >> >> >> > >> >> >> >> >> >On Mon, Apr 01, 2019 at 11:00:04PM +0530, Uma Shankar wrote: >> >> >> >> >> >> This series adds support for programmable gamma modes >> >> >> >> >> >> and exposes a property interface for the same. Also >> >> >> >> >> >> added, support for multi segment gamma mode introduced >> >> >> >> >> >> in ICL+ >> >> >> >> >> >> >> >> >> >> >> >> It creates 2 property interfaces : >> >> >> >> >> >> 1. GAMMA_MODE_CAPS: This is immutable property and >> >> >> >> >> >> exposes the various gamma modes supported and the lut >> >> >> >> >> >> ranges. This is an enum property with element as blob >> >> >> >> >> >> id. Getting the blob id in userspace, user can get the >> >> >> >> >> >> mode supported and also the range of gamma mode >> >> >> >> >> >> supported with number of lut >> >coefficients. >> >> >> >> >> >> >> >> >> >> >> >> 2. GAMMA_MODE: This is for user to set the gamma mode >> >> >> >> >> >> and send the lut values for that particular mode. >> >> >> >> >> > >> >> >> >> >> >I think we should just go for the BLOB_ENUM prop type instead. >> >> >> >> >> >Then the possible values and the current value are all >> >> >> >> >> >part of the same >> >prop. >> >> >> >> >> >> >> >> >> >> Hi Ville, >> >> >> >> >> With the current approach, we have enum property with >> >> >> >> >> values as blob_ids (representing platform capabilities). >> >> >> >> >> This should not get modified and needs to be immutable. >> >> >> >> > >> >> >> >> >That's not quite what we want. We want to let the user >> >> >> >> >modify the current value so that they can actually select the gamma >mode. >> >> >> >> >Otherwise we need yet another prop for it, or we have to >> >> >> >> >deduce it from the LUT size (that apporach would actually >> >> >> >> >work for >> >> >> >> >i915 but may not work for other drivers/hardware). >> >> >> >> > >> >> >> >> >> >> >> >> >> >> Userspace can query the property and get the blob using the >> >> >> >> >> blob_ids. >> >> >> >> >> Thereby getting all the platform capabilities. >> >> >> >> >> >> >> >> >> >> Now to set the LUT values, he can use another blob >> >> >> >> >> property
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/7] drm/i915: Use dedicated rc6 enabling sequence for gen11 (rev2)
Quoting Patchwork (2019-04-10 23:24:41) > * igt@i915_pm_rps@reset: > - shard-iclb: FAIL [fdo#108059] -> PASS +2 And pushed as it clearly improves upon the current woes for icl. Thanks! -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PULL] gvt-fixes
Hi, This includes one vGPU display plane size regression fix, one for preventing use-after-free in ppgtt shadow free function and another warning fix for iomem access annotation. Thanks. -- The following changes since commit cf9ed66671ec5f6cacc7b6efbad9d7c9e5e31776: drm/i915/gvt: Fix kerneldoc typo for intel_vgpu_emulate_hotplug (2019-04-04 08:45:45 +0800) are available in the Git repository at: https://github.com/intel/gvt-linux.git tags/gvt-fixes-2019-04-11 for you to fetch changes up to cd7879f79f83aec4bb13f0f823f323911dc5397b: drm/i915/gvt: Roundup fb->height into tile's height at calucation fb->size (2019-04-11 11:09:53 +0800) gvt-fixes-2019-04-11 - Fix sparse warning on iomem usage (Chris) - Prevent use-after-free for ppgtt shadow table free (Chris) - Fix display plane size regression for tiled surface (Xiong) Chris Wilson (2): drm/i915/gvt: Annotate iomem usage drm/i915/gvt: Prevent use-after-free in ppgtt_free_all_spt() Xiong Zhang (1): drm/i915/gvt: Roundup fb->height into tile's height at calucation fb->size drivers/gpu/drm/i915/gvt/dmabuf.c | 9 ++--- drivers/gpu/drm/i915/gvt/gtt.c| 12 +--- drivers/gpu/drm/i915/gvt/kvmgt.c | 6 +++--- 3 files changed, 18 insertions(+), 9 deletions(-) -- Open Source Technology Center, Intel ltd. $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827 signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915: Bump ready tasks ahead of busywaits
Quoting Chris Wilson (2019-04-09 16:42:17) > Quoting Tvrtko Ursulin (2019-04-09 16:38:37) > > > > On 09/04/2019 16:29, Chris Wilson wrote: > > > Consider two tasks that are running in parallel on a pair of engines > > > (vcs0, vcs1), but then must complete on a shared engine (rcs0). To > > > maximise throughput, we want to run the first ready task on rcs0 (i.e. > > > the first task that completes on either of vcs0 or vcs1). When using > > > semaphores, however, we will instead queue onto rcs in submission order. > > > > > > To resolve this incorrect ordering, we want to re-evaluate the priority > > > queue when each of the request is ready. Normally this happens because > > > we only insert into the priority queue requests that are ready, but with > > > semaphores we are inserting ahead of their readiness and to compensate > > > we penalize those tasks with reduced priority (so that tasks that do not > > > need to busywait should naturally be run first). However, given a series > > > of tasks that each use semaphores, the queue degrades into submission > > > fifo rather than readiness fifo, and so to counter this we give a small > > > boost to semaphore users as their dependent tasks are completed (and so > > > we no longer require any busywait prior to running the user task as they > > > are then ready themselves). > > > > > > v2: Fixup irqsave for schedule_lock (Tvrtko) > > > > > > Testcase: igt/gem_exec_schedule/semaphore-codependency > > > Signed-off-by: Chris Wilson > > > Cc: Tvrtko Ursulin > > > Cc: Dmitry Rogozhkin > > > Cc: Dmitry Ermilov > > > --- > [snip] > > Looks fine to me. Provisional r-b: > > > > Reviewed-by: Tvrtko Ursulin > > > > But let's wait for a media benchmarking run to see if you have nailed > > the regression. > > Aye, but we need something like this regardless as introducing a trivial > dos is not good behaviour either. Hopefully, this will evolve into > something a lot more elegant. For now, it is just another lesson learnt. Waited a day for any acknowledgement, then pushed to clear CI (as the CI testcase demonstrates the potential dos). Using a fence to perform queue adjustment after emitting semaphores is interesting -- the impact it has on the code (larger irqoff surface) is annoying. While I think the "correct" solution is a timeslicing scheduler that can retire blocking semaphores, using the common fence paraphernalia to check all semaphore status rather than evaluating the ringbuffer commands is compelling. Userspace semaphores though will still be trial-and-error :| -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Only reset the pinned kernel contexts on resume (rev2)
== Series Details == Series: drm/i915: Only reset the pinned kernel contexts on resume (rev2) URL : https://patchwork.freedesktop.org/series/58589/ State : success == Summary == CI Bug Log - changes from CI_DRM_5901_full -> Patchwork_12759_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_12759_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_params@no-blt: - shard-iclb: NOTRUN -> SKIP [fdo#109283] * igt@gem_mocs_settings@mocs-reset-ctx-dirty-render: - shard-iclb: NOTRUN -> SKIP [fdo#110206] * igt@gem_softpin@evict-snoop-interruptible: - shard-iclb: NOTRUN -> SKIP [fdo#109312] * igt@gem_stolen@stolen-pwrite: - shard-iclb: NOTRUN -> SKIP [fdo#109277] * igt@gen3_render_tiledx_blits: - shard-iclb: NOTRUN -> SKIP [fdo#109289] * igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait: - shard-iclb: NOTRUN -> SKIP [fdo#109308] * igt@i915_pm_rpm@system-suspend: - shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773] / [fdo#107807] * igt@i915_selftest@live_workarounds: - shard-iclb: PASS -> DMESG-FAIL [fdo#108954] * igt@i915_suspend@fence-restore-untiled: - shard-apl: PASS -> DMESG-WARN [fdo#108566] +7 * igt@i915_suspend@forcewake: - shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773] * igt@kms_atomic_transition@6x-modeset-transitions-nonblocking-fencing: - shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1 * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-e: - shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_busy@extended-modeset-hang-oldfb-render-d: - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +14 * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-d: - shard-iclb: NOTRUN -> SKIP [fdo#109278] +2 * igt@kms_chamelium@dp-frame-dump: - shard-iclb: NOTRUN -> SKIP [fdo#109284] +3 * igt@kms_color@pipe-a-gamma: - shard-iclb: NOTRUN -> FAIL [fdo#104782] * igt@kms_cursor_crc@cursor-512x170-onscreen: - shard-iclb: NOTRUN -> SKIP [fdo#109279] * igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic: - shard-iclb: NOTRUN -> SKIP [fdo#109274] +5 * igt@kms_fbcon_fbt@psr-suspend: - shard-skl: NOTRUN -> FAIL [fdo#103833] * igt@kms_flip@2x-flip-vs-panning-vs-hang-interruptible: - shard-kbl: NOTRUN -> SKIP [fdo#109271] +19 * igt@kms_flip@nonexisting-fb-interruptible: - shard-apl: PASS -> INCOMPLETE [fdo#103927] * igt@kms_force_connector_basic@force-edid: - shard-iclb: NOTRUN -> SKIP [fdo#109285] * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move: - shard-iclb: PASS -> FAIL [fdo#103167] +2 * igt@kms_frontbuffer_tracking@fbc-2p-indfb-fliptrack: - shard-iclb: NOTRUN -> SKIP [fdo#109280] +21 * igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw: - shard-iclb: NOTRUN -> FAIL [fdo#103167] +1 * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-pwrite: - shard-iclb: PASS -> FAIL [fdo#105682] / [fdo#109247] +2 * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt: - shard-iclb: PASS -> FAIL [fdo#109247] +13 * igt@kms_lease@atomic_implicit_crtc: - shard-iclb: NOTRUN -> FAIL [fdo#110279] * igt@kms_lease@setcrtc_implicit_plane: - shard-iclb: NOTRUN -> FAIL [fdo#110281] * igt@kms_plane@pixel-format-pipe-c-planes-source-clamping: - shard-glk: PASS -> SKIP [fdo#109271] * igt@kms_plane_alpha_blend@pipe-c-alpha-7efc: - shard-apl: NOTRUN -> FAIL [fdo#108145] +1 * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: NOTRUN -> FAIL [fdo#108145] * igt@kms_plane_scaling@pipe-b-scaler-with-rotation: - shard-iclb: NOTRUN -> FAIL [fdo#109052] +1 * igt@kms_psr@psr2_cursor_plane_move: - shard-iclb: PASS -> SKIP [fdo#109441] * igt@kms_psr@psr2_primary_mmap_gtt: - shard-iclb: NOTRUN -> SKIP [fdo#109441] * igt@kms_psr@sprite_render: - shard-iclb: PASS -> FAIL [fdo#107383] / [fdo#110215] +1 * igt@kms_setmode@basic: - shard-skl: NOTRUN -> FAIL [fdo#99912] * igt@kms_sysfs_edid_timing: - shard-iclb: PASS -> FAIL [fdo#100047] * igt@kms_tv_load_detect@load-detect: - shard-iclb: NOTRUN -> SKIP [fdo#109309] * igt@perf_pmu@most-busy-check-all-vcs1: - shard-iclb: NOTRUN -> SKIP [fdo#109276] +12 * igt@perf_pmu@semaphore-wait-vcs1: - shard-skl: NOTRUN -> SKIP [fdo#109271] +96 * igt@prime_nv_api@i915_nv_import_vs_close: - shard-apl: NOTRUN -> SKIP [fdo#109271] +5 *
Re: [Intel-gfx] [PATCH libdrm] headers: Sync with drm-next
On Wednesday, 2019-04-10 21:49:33 -0400, Rob Clark wrote:
> On Tue, Apr 9, 2019 at 8:27 AM Eric Engestrom
> wrote:
> > > > diff --git a/include/drm/msm_drm.h b/include/drm/msm_drm.h
> > > > index c06d0a5..91a16b3 100644
> > > > --- a/include/drm/msm_drm.h
> > > > +++ b/include/drm/msm_drm.h
> > > > @@ -105,14 +105,24 @@ struct drm_msm_gem_new {
> > > > __u32 handle; /* out */
> > > > };
> > > >
> > > > -#define MSM_INFO_IOVA 0x01
> > > > -
> > > > -#define MSM_INFO_FLAGS (MSM_INFO_IOVA)
> > > > +/* Get or set GEM buffer info. The requested value can be passed
> > > > + * directly in 'value', or for data larger than 64b 'value' is a
> > > > + * pointer to userspace buffer, with 'len' specifying the number of
> > > > + * bytes copied into that buffer. For info returned by pointer,
> > > > + * calling the GEM_INFO ioctl with null 'value' will return the
> > > > + * required buffer size in 'len'
> > > > + */
> > > > +#define MSM_INFO_GET_OFFSET0x00 /* get mmap() offset,
> > > > returned by value */
> > > > +#define MSM_INFO_GET_IOVA 0x01 /* get iova, returned by value */
> > > > +#define MSM_INFO_SET_NAME 0x02 /* set the debug name (by pointer) */
> > > > +#define MSM_INFO_GET_NAME 0x03 /* get debug name, returned by
> > > > pointer */
> > > >
> > > > struct drm_msm_gem_info {
> > > > __u32 handle; /* in */
> > > > - __u32 flags; /* in - combination of MSM_INFO_* flags */
> > > > - __u64 offset; /* out, mmap() offset or iova */
> > > > + __u32 info; /* in - one of MSM_INFO_* */
> > > > + __u64 value; /* in or out */
> > > > + __u32 len;/* in or out */
> > > > + __u32 pad;
> >
> > freedreno/msm/msm_bo.c needs to be updated to reflect those changes.
>
>
> I think you can just rename flags->info and offset->value, the rest of
> the struct should be zero-initialized.. if in doubt you can check
> $mesa/src/freedreno/drm/msm_bo.c
>
> side-note: the libdrm_freedreno code was folded into mesa in 19.0, so
> at *some* point we can probably disable libdrm_freedreno build by
> default.
Right now, freedreno's `auto` enables it by default on arm and disables it on
everything else.
I always enable everything to at least build-test it, but Ayan was using
the defaults which is why he didn't see this issue at first.
Btw, the GitLab CI builds everything, so it hopefully won't bitrot unnoticed.
> (I'd kinda still like to keep the code around for some misc
> standalone tools I have, but that is the sort of thing where I can fix
> libdrm if it gets broken). When to switch to disabled by default I
> guess comes down to how long we want to support mesa 18.x with latest
> libdrm?? Maybe after 19.1, since (selfishly motivated) that gives me
> a long enough window back in case I find myself needing to bisect for
> some regression..
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
