[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Lock the engine while dumping the active request (rev2)
== Series Details == Series: drm/i915: Lock the engine while dumping the active request (rev2) URL : https://patchwork.freedesktop.org/series/63442/ State : success == Summary == CI Bug Log - changes from CI_DRM_6441_full -> Patchwork_13583_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13583_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@vecs0-s3: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6441/shard-apl2/igt@gem_ctx_isolat...@vecs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13583/shard-apl4/igt@gem_ctx_isolat...@vecs0-s3.html * igt@kms_color@pipe-c-ctm-green-to-red: - shard-skl: [PASS][3] -> [FAIL][4] ([fdo#107201]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6441/shard-skl2/igt@kms_co...@pipe-c-ctm-green-to-red.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13583/shard-skl5/igt@kms_co...@pipe-c-ctm-green-to-red.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render: - shard-iclb: [PASS][5] -> [FAIL][6] ([fdo#103167]) +8 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6441/shard-iclb1/igt@kms_frontbuffer_track...@fbc-1p-primscrn-cur-indfb-draw-render.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13583/shard-iclb2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-cur-indfb-draw-render.html * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][7] -> [FAIL][8] ([fdo#108145]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6441/shard-skl2/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13583/shard-skl5/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html * igt@kms_psr@psr2_cursor_blt: - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109441]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6441/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13583/shard-iclb8/igt@kms_psr@psr2_cursor_blt.html * igt@kms_vblank@pipe-a-wait-busy-hang: - shard-iclb: [PASS][11] -> [INCOMPLETE][12] ([fdo#107713]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6441/shard-iclb5/igt@kms_vbl...@pipe-a-wait-busy-hang.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13583/shard-iclb7/igt@kms_vbl...@pipe-a-wait-busy-hang.html Possible fixes * igt@gem_exec_balancer@smoke: - shard-iclb: [SKIP][13] ([fdo#110854]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6441/shard-iclb7/igt@gem_exec_balan...@smoke.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13583/shard-iclb4/igt@gem_exec_balan...@smoke.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-apl: [DMESG-WARN][15] ([fdo#108566]) -> [PASS][16] +4 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6441/shard-apl2/igt@i915_susp...@fence-restore-tiled2untiled.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13583/shard-apl1/igt@i915_susp...@fence-restore-tiled2untiled.html * igt@kms_cursor_crc@pipe-c-cursor-128x42-onscreen: - shard-iclb: [INCOMPLETE][17] ([fdo#107713]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6441/shard-iclb1/igt@kms_cursor_...@pipe-c-cursor-128x42-onscreen.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13583/shard-iclb7/igt@kms_cursor_...@pipe-c-cursor-128x42-onscreen.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-apl: [INCOMPLETE][19] ([fdo#103927]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6441/shard-apl7/igt@kms_frontbuffer_track...@fbc-suspend.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13583/shard-apl7/igt@kms_frontbuffer_track...@fbc-suspend.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt: - shard-iclb: [FAIL][21] ([fdo#103167]) -> [PASS][22] +4 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6441/shard-iclb4/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-shrfb-plflip-blt.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13583/shard-iclb1/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-shrfb-plflip-blt.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [FAIL][23] ([fdo#108145] / [fdo#110403]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6441/shard-skl10/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html [24]:
[Intel-gfx] ✗ Fi.CI.BAT: failure for Panel rotation patches (rev7)
== Series Details == Series: Panel rotation patches (rev7) URL : https://patchwork.freedesktop.org/series/61870/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h AR drivers/gpu/drm/i915/built-in.a CC [M] drivers/gpu/drm/i915/header_test_i915_active_types.o CC [M] drivers/gpu/drm/i915/header_test_i915_debugfs.o CC [M] drivers/gpu/drm/i915/header_test_i915_drv.o CC [M] drivers/gpu/drm/i915/header_test_i915_fixed.o CC [M] drivers/gpu/drm/i915/header_test_i915_gem_gtt.o CC [M] drivers/gpu/drm/i915/header_test_i915_globals.o CC [M] drivers/gpu/drm/i915/header_test_i915_irq.o CC [M] drivers/gpu/drm/i915/header_test_i915_params.o CC [M] drivers/gpu/drm/i915/header_test_i915_priolist_types.o CC [M] drivers/gpu/drm/i915/header_test_i915_pvinfo.o CC [M] drivers/gpu/drm/i915/header_test_i915_reg.o CC [M] drivers/gpu/drm/i915/header_test_i915_scheduler_types.o CC [M] drivers/gpu/drm/i915/header_test_i915_utils.o CC [M] drivers/gpu/drm/i915/header_test_i915_vgpu.o CC [M] drivers/gpu/drm/i915/header_test_intel_csr.o CC [M] drivers/gpu/drm/i915/header_test_intel_drv.o CC [M] drivers/gpu/drm/i915/header_test_intel_guc_ct.o CC [M] drivers/gpu/drm/i915/header_test_intel_guc_fwif.o CC [M] drivers/gpu/drm/i915/header_test_intel_guc_reg.o CC [M] drivers/gpu/drm/i915/header_test_intel_gvt.o CC [M] drivers/gpu/drm/i915/header_test_intel_pm.o CC [M] drivers/gpu/drm/i915/header_test_intel_runtime_pm.o CC [M] drivers/gpu/drm/i915/header_test_intel_sideband.o CC [M] drivers/gpu/drm/i915/header_test_intel_uc_fw.o CC [M] drivers/gpu/drm/i915/header_test_intel_uncore.o CC [M] drivers/gpu/drm/i915/header_test_intel_wakeref.o CC [M] drivers/gpu/drm/i915/display/icl_dsi.o drivers/gpu/drm/i915/display/icl_dsi.c: In function ‘icl_dsi_add_properties’: drivers/gpu/drm/i915/display/icl_dsi.c:1526:2: error: too many arguments to function ‘drm_connector_init_panel_orientation_property’ drm_connector_init_panel_orientation_property(>base, ^ In file included from ./include/drm/drm_modes.h:33:0, from ./include/drm/drm_crtc.h:40, from ./include/drm/drm_atomic_helper.h:31, from drivers/gpu/drm/i915/display/icl_dsi.c:28: ./include/drm/drm_connector.h:1517:5: note: declared here int drm_connector_init_panel_orientation_property( ^ scripts/Makefile.build:278: recipe for target 'drivers/gpu/drm/i915/display/icl_dsi.o' failed make[4]: *** [drivers/gpu/drm/i915/display/icl_dsi.o] Error 1 scripts/Makefile.build:489: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:489: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:489: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1071: recipe for target 'drivers' failed make: *** [drivers] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 4/4] drm/mtk: add panel orientation property
This inits the panel orientation property for the mediatek dsi driver
if the panel orientation (connector.display_info.panel_orientation) is
not DRM_MODE_PANEL_ORIENTATION_UNKNOWN.
Signed-off-by: Derek Basehore
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index b91c4616644a..2920458ae2fb 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -790,10 +790,18 @@ static int mtk_dsi_create_connector(struct drm_device
*drm, struct mtk_dsi *dsi)
DRM_ERROR("Failed to attach panel to drm\n");
goto err_connector_cleanup;
}
+
+ ret = drm_connector_init_panel_orientation_property(>conn);
+ if (ret) {
+ DRM_ERROR("Failed to init panel orientation\n");
+ goto err_panel_detach;
+ }
}
return 0;
+err_panel_detach:
+ drm_panel_detach(dsi->panel);
err_connector_cleanup:
drm_connector_cleanup(>conn);
return ret;
--
2.22.0.410.gd8fdbe21b5-goog
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[Intel-gfx] [PATCH v7 1/4] drm/panel: Add helper for reading DT rotation
This adds a helper function for reading the rotation (panel
orientation) from the device tree.
Signed-off-by: Derek Basehore
---
drivers/gpu/drm/drm_panel.c | 43 +
include/drm/drm_panel.h | 9
2 files changed, 52 insertions(+)
diff --git a/drivers/gpu/drm/drm_panel.c b/drivers/gpu/drm/drm_panel.c
index dbd5b873e8f2..169bab54d52d 100644
--- a/drivers/gpu/drm/drm_panel.c
+++ b/drivers/gpu/drm/drm_panel.c
@@ -172,6 +172,49 @@ struct drm_panel *of_drm_find_panel(const struct
device_node *np)
return ERR_PTR(-EPROBE_DEFER);
}
EXPORT_SYMBOL(of_drm_find_panel);
+
+/**
+ * of_drm_get_panel_orientation - look up the orientation of the panel through
+ * the "rotation" binding from a device tree node
+ * @np: device tree node of the panel
+ * @orientation: orientation enum to be filled in
+ *
+ * Looks up the rotation of a panel in the device tree. The orientation of the
+ * panel is expressed as a property name "rotation" in the device tree. The
+ * rotation in the device tree is counter clockwise.
+ *
+ * Return: 0 when a valid rotation value (0, 90, 180, or 270) is read or the
+ * rotation property doesn't exist. -EERROR otherwise.
+ */
+int of_drm_get_panel_orientation(const struct device_node *np,
+enum drm_panel_orientation *orientation)
+{
+ int rotation, ret;
+
+ ret = of_property_read_u32(np, "rotation", );
+ if (ret == -EINVAL) {
+ /* Don't return an error if there's no rotation property. */
+ *orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
+ return 0;
+ }
+
+ if (ret < 0)
+ return ret;
+
+ if (rotation == 0)
+ *orientation = DRM_MODE_PANEL_ORIENTATION_NORMAL;
+ else if (rotation == 90)
+ *orientation = DRM_MODE_PANEL_ORIENTATION_RIGHT_UP;
+ else if (rotation == 180)
+ *orientation = DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP;
+ else if (rotation == 270)
+ *orientation = DRM_MODE_PANEL_ORIENTATION_LEFT_UP;
+ else
+ return -EINVAL;
+
+ return 0;
+}
+EXPORT_SYMBOL(of_drm_get_panel_orientation);
#endif
MODULE_AUTHOR("Thierry Reding ");
diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h
index 8c738c0e6e9f..fc7da55f41d9 100644
--- a/include/drm/drm_panel.h
+++ b/include/drm/drm_panel.h
@@ -33,6 +33,8 @@ struct drm_device;
struct drm_panel;
struct display_timing;
+enum drm_panel_orientation;
+
/**
* struct drm_panel_funcs - perform operations on a given panel
* @disable: disable panel (turn off back light, etc.)
@@ -197,11 +199,18 @@ int drm_panel_detach(struct drm_panel *panel);
#if defined(CONFIG_OF) && defined(CONFIG_DRM_PANEL)
struct drm_panel *of_drm_find_panel(const struct device_node *np);
+int of_drm_get_panel_orientation(const struct device_node *np,
+enum drm_panel_orientation *orientation);
#else
static inline struct drm_panel *of_drm_find_panel(const struct device_node *np)
{
return ERR_PTR(-ENODEV);
}
+static inline int of_drm_get_panel_orientation(const struct device_node *np,
+ enum drm_panel_orientation *orientation)
+{
+ return -ENODEV;
+}
#endif
#endif
--
2.22.0.410.gd8fdbe21b5-goog
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[Intel-gfx] [PATCH v7 3/4] drm/connector: Split out orientation quirk detection
Not every platform needs quirk detection for panel orientation, so
split the drm_connector_init_panel_orientation_property into two
functions. One for platforms without the need for quirks, and the
other for platforms that need quirks.
Signed-off-by: Derek Basehore
---
drivers/gpu/drm/drm_connector.c | 45 ++---
drivers/gpu/drm/i915/display/intel_dp.c | 4 +--
drivers/gpu/drm/i915/display/vlv_dsi.c | 2 +-
include/drm/drm_connector.h | 2 ++
4 files changed, 38 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index b3f2cf7eae9c..52777d647494 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -1892,31 +1892,23 @@ EXPORT_SYMBOL(drm_connector_set_vrr_capable_property);
* drm_connector_init_panel_orientation_property -
* initialize the connecters panel_orientation property
* @connector: connector for which to init the panel-orientation property.
- * @width: width in pixels of the panel, used for panel quirk detection
- * @height: height in pixels of the panel, used for panel quirk detection
*
* This function should only be called for built-in panels, after setting
* connector->display_info.panel_orientation first (if known).
*
- * This function will check for platform specific (e.g. DMI based) quirks
- * overriding display_info.panel_orientation first, then if panel_orientation
- * is not DRM_MODE_PANEL_ORIENTATION_UNKNOWN it will attach the
- * "panel orientation" property to the connector.
+ * This function will check if the panel_orientation is not
+ * DRM_MODE_PANEL_ORIENTATION_UNKNOWN. If not, it will attach the "panel
+ * orientation" property to the connector.
*
* Returns:
* Zero on success, negative errno on failure.
*/
int drm_connector_init_panel_orientation_property(
- struct drm_connector *connector, int width, int height)
+ struct drm_connector *connector)
{
struct drm_device *dev = connector->dev;
struct drm_display_info *info = >display_info;
struct drm_property *prop;
- int orientation_quirk;
-
- orientation_quirk = drm_get_panel_orientation_quirk(width, height);
- if (orientation_quirk != DRM_MODE_PANEL_ORIENTATION_UNKNOWN)
- info->panel_orientation = orientation_quirk;
if (info->panel_orientation == DRM_MODE_PANEL_ORIENTATION_UNKNOWN)
return 0;
@@ -1939,6 +1931,35 @@ int drm_connector_init_panel_orientation_property(
}
EXPORT_SYMBOL(drm_connector_init_panel_orientation_property);
+/**
+ * drm_connector_init_panel_orientation_property_quirk -
+ * initialize the connecters panel_orientation property with a quirk
+ * override
+ * @connector: connector for which to init the panel-orientation property.
+ * @width: width in pixels of the panel, used for panel quirk detection
+ * @height: height in pixels of the panel, used for panel quirk detection
+ *
+ * This function will check for platform specific (e.g. DMI based) quirks
+ * overriding display_info.panel_orientation first, then if panel_orientation
+ * is not DRM_MODE_PANEL_ORIENTATION_UNKNOWN it will attach the
+ * "panel orientation" property to the connector.
+ *
+ * Returns:
+ * Zero on success, negative errno on failure.
+ */
+int drm_connector_init_panel_orientation_property_quirk(
+ struct drm_connector *connector, int width, int height)
+{
+ int orientation_quirk;
+
+ orientation_quirk = drm_get_panel_orientation_quirk(width, height);
+ if (orientation_quirk != DRM_MODE_PANEL_ORIENTATION_UNKNOWN)
+ connector->display_info.panel_orientation = orientation_quirk;
+
+ return drm_connector_init_panel_orientation_property(connector);
+}
+EXPORT_SYMBOL(drm_connector_init_panel_orientation_property_quirk);
+
int drm_connector_set_obj_prop(struct drm_mode_object *obj,
struct drm_property *property,
uint64_t value)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 0bdb7ecc5a81..975196c86e50 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -7063,8 +7063,8 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
intel_panel_setup_backlight(connector, pipe);
if (fixed_mode)
- drm_connector_init_panel_orientation_property(
- connector, fixed_mode->hdisplay, fixed_mode->vdisplay);
+ drm_connector_init_panel_orientation_property_quirk(connector,
+ fixed_mode->hdisplay, fixed_mode->vdisplay);
return true;
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c
b/drivers/gpu/drm/i915/display/vlv_dsi.c
index e272d826210a..dd7fa806f95c 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -1662,7
[Intel-gfx] [PATCH v7 0/4] Panel rotation patches
This adds the plumbing for reading panel rotation from the devicetree and sets up adding a panel property for the panel orientation on Mediatek SoCs when a rotation is present. v7 changes: -forgot to add static inline v6 changes: -added enum declaration to drm_panel.h header v5 changes: -rebased v4 changes: -fixed some changes made to the i915 driver -clarified comments on of orientation helper v3 changes: -changed from attach/detach callbacks to directly setting fixed panel values in drm_panel_attach -removed update to Documentation -added separate function for quirked panel orientation property init v2 changes: fixed build errors in i915 Derek Basehore (4): drm/panel: Add helper for reading DT rotation drm/panel: set display info in panel attach drm/connector: Split out orientation quirk detection drm/mtk: add panel orientation property drivers/gpu/drm/drm_connector.c| 45 ++- drivers/gpu/drm/drm_panel.c| 70 ++ drivers/gpu/drm/i915/intel_dp.c| 4 +- drivers/gpu/drm/i915/vlv_dsi.c | 5 +-- drivers/gpu/drm/mediatek/mtk_dsi.c | 8 include/drm/drm_connector.h| 2 + include/drm/drm_panel.h| 21 + 7 files changed, 138 insertions(+), 17 deletions(-) -- 2.22.0.410.gd8fdbe21b5-goog ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 2/4] drm/panel: set display info in panel attach
Devicetree systems can set panel orientation via a panel binding, but
there's no way, as is, to propagate this setting to the connector,
where the property need to be added.
To address this, this patch sets orientation, as well as other fixed
values for the panel, in the drm_panel_attach function. These values
are stored from probe in the drm_panel struct.
Signed-off-by: Derek Basehore
---
drivers/gpu/drm/drm_panel.c | 28
include/drm/drm_panel.h | 14 ++
2 files changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/drm_panel.c b/drivers/gpu/drm/drm_panel.c
index 169bab54d52d..ca01095470a9 100644
--- a/drivers/gpu/drm/drm_panel.c
+++ b/drivers/gpu/drm/drm_panel.c
@@ -104,11 +104,23 @@ EXPORT_SYMBOL(drm_panel_remove);
*/
int drm_panel_attach(struct drm_panel *panel, struct drm_connector *connector)
{
+ struct drm_display_info *info;
+
if (panel->connector)
return -EBUSY;
panel->connector = connector;
panel->drm = connector->dev;
+ info = >display_info;
+ info->width_mm = panel->width_mm;
+ info->height_mm = panel->height_mm;
+ info->bpc = panel->bpc;
+ info->panel_orientation = panel->orientation;
+ info->bus_flags = panel->bus_flags;
+ if (panel->bus_formats)
+ drm_display_info_set_bus_formats(>display_info,
+panel->bus_formats,
+panel->num_bus_formats);
return 0;
}
@@ -128,6 +140,22 @@ EXPORT_SYMBOL(drm_panel_attach);
*/
int drm_panel_detach(struct drm_panel *panel)
{
+ struct drm_display_info *info;
+
+ if (!panel->connector)
+ goto out;
+
+ info = >connector->display_info;
+ info->width_mm = 0;
+ info->height_mm = 0;
+ info->bpc = 0;
+ info->panel_orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
+ info->bus_flags = 0;
+ kfree(info->bus_formats);
+ info->bus_formats = NULL;
+ info->num_bus_formats = 0;
+
+out:
panel->connector = NULL;
panel->drm = NULL;
diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h
index fc7da55f41d9..a6a881b987dd 100644
--- a/include/drm/drm_panel.h
+++ b/include/drm/drm_panel.h
@@ -39,6 +39,8 @@ enum drm_panel_orientation;
* struct drm_panel_funcs - perform operations on a given panel
* @disable: disable panel (turn off back light, etc.)
* @unprepare: turn off panel
+ * @detach: detach panel->connector (clear internal state, etc.)
+ * @attach: attach panel->connector (update internal state, etc.)
* @prepare: turn on panel and perform set up
* @enable: enable panel (turn on back light, etc.)
* @get_modes: add modes to the connector that the panel is attached to and
@@ -95,6 +97,18 @@ struct drm_panel {
const struct drm_panel_funcs *funcs;
+ /*
+* panel information to be set in the connector when the panel is
+* attached.
+*/
+ unsigned int width_mm;
+ unsigned int height_mm;
+ unsigned int bpc;
+ int orientation;
+ const u32 *bus_formats;
+ unsigned int num_bus_formats;
+ u32 bus_flags;
+
struct list_head list;
};
--
2.22.0.410.gd8fdbe21b5-goog
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[Intel-gfx] ✗ Fi.CI.BAT: failure for GT-fy the uc code
== Series Details ==
Series: GT-fy the uc code
URL : https://patchwork.freedesktop.org/series/63460/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6446 -> Patchwork_13594
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_13594 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_13594, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13594/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_13594:
### IGT changes ###
Possible regressions
* igt@debugfs_test@read_all_entries:
- fi-kbl-guc: [PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/fi-kbl-guc/igt@debugfs_test@read_all_entries.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13594/fi-kbl-guc/igt@debugfs_test@read_all_entries.html
- fi-skl-guc: [PASS][3] -> [DMESG-WARN][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/fi-skl-guc/igt@debugfs_test@read_all_entries.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13594/fi-skl-guc/igt@debugfs_test@read_all_entries.html
- fi-apl-guc: [PASS][5] -> [DMESG-WARN][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/fi-apl-guc/igt@debugfs_test@read_all_entries.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13594/fi-apl-guc/igt@debugfs_test@read_all_entries.html
- fi-cfl-guc: [PASS][7] -> [DMESG-WARN][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/fi-cfl-guc/igt@debugfs_test@read_all_entries.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13594/fi-cfl-guc/igt@debugfs_test@read_all_entries.html
- fi-icl-guc: [PASS][9] -> [DMESG-WARN][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/fi-icl-guc/igt@debugfs_test@read_all_entries.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13594/fi-icl-guc/igt@debugfs_test@read_all_entries.html
* igt@i915_selftest@live_mman:
- fi-bsw-n3050: [PASS][11] -> [INCOMPLETE][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/fi-bsw-n3050/igt@i915_selftest@live_mman.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13594/fi-bsw-n3050/igt@i915_selftest@live_mman.html
Known issues
Here are the changes found in Patchwork_13594 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_mmap_gtt@basic-write:
- fi-icl-u3: [PASS][13] -> [DMESG-WARN][14] ([fdo#107724]) +1
similar issue
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/fi-icl-u3/igt@gem_mmap_...@basic-write.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13594/fi-icl-u3/igt@gem_mmap_...@basic-write.html
* igt@i915_selftest@live_contexts:
- fi-skl-iommu: [PASS][15] -> [INCOMPLETE][16] ([fdo#111050])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/fi-skl-iommu/igt@i915_selftest@live_contexts.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13594/fi-skl-iommu/igt@i915_selftest@live_contexts.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u2: [PASS][17] -> [INCOMPLETE][18] ([fdo#107713] /
[fdo#108569])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13594/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
Possible fixes
* {igt@gem_ctx_switch@legacy-render}:
- fi-cml-u: [INCOMPLETE][19] ([fdo#110566]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/fi-cml-u/igt@gem_ctx_swi...@legacy-render.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13594/fi-cml-u/igt@gem_ctx_swi...@legacy-render.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][21] ([fdo#109485]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13594/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#110566]:
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Vulkan performance query support (rev8)
== Series Details == Series: drm/i915: Vulkan performance query support (rev8) URL : https://patchwork.freedesktop.org/series/60916/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6440_full -> Patchwork_13580_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_13580_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_13580_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_13580_full: ### IGT changes ### Possible regressions * igt@perf@blocking: - shard-hsw: [PASS][1] -> [DMESG-WARN][2] +11 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6440/shard-hsw6/igt@p...@blocking.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13580/shard-hsw5/igt@p...@blocking.html * igt@perf@create-destroy-userspace-config: - shard-glk: [PASS][3] -> [DMESG-WARN][4] +11 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6440/shard-glk5/igt@p...@create-destroy-userspace-config.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13580/shard-glk3/igt@p...@create-destroy-userspace-config.html * igt@perf@disabled-read-error: - shard-skl: [PASS][5] -> [INCOMPLETE][6] +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6440/shard-skl9/igt@p...@disabled-read-error.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13580/shard-skl1/igt@p...@disabled-read-error.html * igt@perf@gen8-unprivileged-single-ctx-counters: - shard-skl: [PASS][7] -> [DMESG-WARN][8] +10 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6440/shard-skl3/igt@p...@gen8-unprivileged-single-ctx-counters.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13580/shard-skl6/igt@p...@gen8-unprivileged-single-ctx-counters.html * igt@perf@invalid-oa-exponent: - shard-iclb: [PASS][9] -> [DMESG-WARN][10] +11 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6440/shard-iclb6/igt@p...@invalid-oa-exponent.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13580/shard-iclb7/igt@p...@invalid-oa-exponent.html * igt@perf@invalid-oa-format-id: - shard-kbl: [PASS][11] -> [DMESG-WARN][12] +11 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6440/shard-kbl3/igt@p...@invalid-oa-format-id.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13580/shard-kbl1/igt@p...@invalid-oa-format-id.html * igt@perf@low-oa-exponent-permissions: - shard-apl: [PASS][13] -> [DMESG-WARN][14] +10 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6440/shard-apl2/igt@p...@low-oa-exponent-permissions.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13580/shard-apl3/igt@p...@low-oa-exponent-permissions.html Known issues Here are the changes found in Patchwork_13580_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_softpin@noreloc-s3: - shard-apl: [PASS][15] -> [DMESG-WARN][16] ([fdo#108566]) +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6440/shard-apl1/igt@gem_soft...@noreloc-s3.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13580/shard-apl4/igt@gem_soft...@noreloc-s3.html * igt@gem_tiled_swapping@non-threaded: - shard-apl: [PASS][17] -> [DMESG-WARN][18] ([fdo#108686]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6440/shard-apl2/igt@gem_tiled_swapp...@non-threaded.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13580/shard-apl8/igt@gem_tiled_swapp...@non-threaded.html * igt@kms_cursor_edge_walk@pipe-b-256x256-left-edge: - shard-snb: [PASS][19] -> [SKIP][20] ([fdo#109271] / [fdo#109278]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6440/shard-snb5/igt@kms_cursor_edge_w...@pipe-b-256x256-left-edge.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13580/shard-snb2/igt@kms_cursor_edge_w...@pipe-b-256x256-left-edge.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic: - shard-hsw: [PASS][21] -> [FAIL][22] ([fdo#105767]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6440/shard-hsw7/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-atomic.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13580/shard-hsw5/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-atomic.html * igt@kms_flip_tiling@flip-changes-tiling-yf: - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108228] / [fdo#108303]) [23]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for GT-fy the uc code
== Series Details == Series: GT-fy the uc code URL : https://patchwork.freedesktop.org/series/63460/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/guc: Remove preemption support for current fw -./drivers/gpu/drm/i915/i915_scheduler.h:70:23: warning: expression using sizeof(void) Commit: drm/i915/guc: simplify guc client Okay! Commit: drm/i915/uc: replace uc init/fini misc Okay! Commit: drm/i915/uc: introduce intel_uc_fw_supported Okay! Commit: drm/i915/guc: move guc irq functions to intel_guc parameter Okay! Commit: drm/i915/guc: unify guc irq handling Okay! Commit: drm/i915/uc: move GuC and HuC files under gt/uc/ +drivers/gpu/drm/i915/gt/uc/intel_guc.c:380:29: warning: expression using sizeof(void) +drivers/gpu/drm/i915/gt/uc/intel_guc.c:380:29: warning: expression using sizeof(void) -drivers/gpu/drm/i915/gt/uc/intel_guc.c:380:29: warning: expression using sizeof(void) -drivers/gpu/drm/i915/gt/uc/intel_guc.c:380:29: warning: expression using sizeof(void) +./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000 becomes 0) +./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000 becomes 0) +./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000 becomes 0) Commit: drm/i915/uc: move GuC/HuC inside intel_gt under a new intel_uc Okay! Commit: drm/i915/uc: Move intel functions to intel_uc Okay! Commit: drm/i915/uc: prefer intel_gt over i915 in GuC/HuC paths -O:drivers/gpu/drm/i915/gt/uc/intel_guc.c:380:29: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/gt/uc/intel_guc.c:380:29: warning: expression using sizeof(void) +drivers/gpu/drm/i915/gt/uc/intel_guc.c:380:29: warning: expression using sizeof(void) +drivers/gpu/drm/i915/gt/uc/intel_guc.c:380:29: warning: expression using sizeof(void) Commit: drm/i915/guc: prefer intel_gt in guc interrupt functions Okay! Commit: drm/i915/uc: kill uc_to_i915 Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for GT-fy the uc code
== Series Details == Series: GT-fy the uc code URL : https://patchwork.freedesktop.org/series/63460/ State : warning == Summary == $ dim checkpatch origin/drm-tip 418baf3690fe drm/i915/guc: Remove preemption support for current fw caf053260254 drm/i915/guc: simplify guc client 363bd5df02b4 drm/i915/uc: replace uc init/fini misc 07dbb4f939f7 drm/i915/uc: introduce intel_uc_fw_supported b38761341584 drm/i915/guc: move guc irq functions to intel_guc parameter 7202c0751a1b drm/i915/guc: unify guc irq handling 9a92b2f4550e drm/i915/uc: move GuC and HuC files under gt/uc/ -:79: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #79: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 140 lines checked 8b866904cad6 drm/i915/uc: move GuC/HuC inside intel_gt under a new intel_uc ee62b0fb9e59 drm/i915/uc: Move intel functions to intel_uc 26611015f973 drm/i915/uc: prefer intel_gt over i915 in GuC/HuC paths a43499aad172 drm/i915/guc: prefer intel_gt in guc interrupt functions 3b20a1de17fc drm/i915/uc: kill uc_to_i915 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/guc: Define GuC firmware version for Comet Lake
On 7/8/19 2:08 PM, Anusha Srivatsa wrote:
Load GuC for Comet Lake. Depending on the REVID,
we load either the KBL firmware or the CML firmware.
v2: Use CFL for CML platform check.(Michal)
Cc: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_guc_fw.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c
b/drivers/gpu/drm/i915/intel_guc_fw.c
index db1e0daca7db..df0dfa49fbc8 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -58,6 +58,13 @@ MODULE_FIRMWARE(BXT_GUC_FIRMWARE_PATH);
#define KBL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(KBL)
MODULE_FIRMWARE(KBL_GUC_FIRMWARE_PATH);
+#define CML_GUC_FW_PREFIX cml
+#define CML_GUC_FW_MAJOR 33
+#define CML_GUC_FW_MINOR 0
+#define CML_GUC_FW_PATCH 0
+#define CML_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(KBL)
s/KBL/CML
+MODULE_FIRMWARE(CML_GUC_FIRMWARE_PATH);
+
#define GLK_GUC_FW_PREFIX glk
#define GLK_GUC_FW_MAJOR 33
#define GLK_GUC_FW_MINOR 0
@@ -94,7 +101,17 @@ static void guc_fw_select(struct intel_uc_fw *guc_fw)
guc_fw->path = GLK_GUC_FIRMWARE_PATH;
guc_fw->major_ver_wanted = GLK_GUC_FW_MAJOR;
guc_fw->minor_ver_wanted = GLK_GUC_FW_MINOR;
- } else if (IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) {
+ } else if (IS_COFFEELAKE(i915)) {
+ if (INTEL_REVID(i915) == 5) {
As Michal already commented on the previous rev, this should be >= 5 for
future-proofing.
Daniele
+ guc_fw->path = CML_GUC_FIRMWARE_PATH;
+ guc_fw->major_ver_wanted = CML_GUC_FW_MAJOR;
+ guc_fw->minor_ver_wanted = CML_GUC_FW_MINOR;
+ } else {
+ guc_fw->path = KBL_GUC_FIRMWARE_PATH;
+ guc_fw->major_ver_wanted = KBL_GUC_FW_MAJOR;
+ guc_fw->minor_ver_wanted = KBL_GUC_FW_MINOR;
+ }
+ } else if (IS_KABYLAKE(i915)) {
guc_fw->path = KBL_GUC_FIRMWARE_PATH;
guc_fw->major_ver_wanted = KBL_GUC_FW_MAJOR;
guc_fw->minor_ver_wanted = KBL_GUC_FW_MINOR;
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 12/12] drm/i915/uc: kill uc_to_i915
Get rid of them to avoid more users being added while the guc code
transitions to use gt more than i915.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 8
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 3 ++-
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 13 +++--
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 ++--
drivers/gpu/drm/i915/i915_drv.h| 10 --
8 files changed, 18 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 6b56f39072b1..83f2c197375f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -77,7 +77,7 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
void intel_guc_init_early(struct intel_guc *guc)
{
- struct drm_i915_private *i915 = guc_to_i915(guc);
+ struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
intel_guc_fw_init_early(guc);
intel_guc_ct_init_early(>ct);
@@ -204,7 +204,7 @@ static u32 guc_ctl_feature_flags(struct intel_guc *guc)
{
u32 flags = 0;
- if (!USES_GUC_SUBMISSION(guc_to_i915(guc)))
+ if (!intel_uc_is_using_guc_submission(_to_gt(guc)->uc))
flags |= GUC_CTL_DISABLE_SCHEDULER;
return flags;
@@ -214,7 +214,7 @@ static u32 guc_ctl_ctxinfo_flags(struct intel_guc *guc)
{
u32 flags = 0;
- if (USES_GUC_SUBMISSION(guc_to_i915(guc))) {
+ if (intel_uc_is_using_guc_submission(_to_gt(guc)->uc)) {
u32 ctxnum, base;
base = intel_guc_ggtt_offset(guc, guc->stage_desc_pool);
@@ -414,7 +414,7 @@ int intel_guc_to_host_process_recv_msg(struct intel_guc
*guc,
int intel_guc_sample_forcewake(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915;
u32 action[2];
action[0] = INTEL_GUC_ACTION_SAMPLE_FORCEWAKE;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 69859d1e047f..a0da80241f22 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -22,6 +22,7 @@
*
*/
+#include "gt/intel_gt.h"
#include "intel_guc_ads.h"
#include "intel_uc.h"
#include "i915_drv.h"
@@ -85,7 +86,7 @@ struct __guc_ads_blob {
static void __guc_ads_init(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915;
struct __guc_ads_blob *blob = guc->ads_blob;
const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE;
u32 base;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
index 98305e3fd42c..3dfa40fdbe99 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
@@ -76,7 +76,7 @@ MODULE_FIRMWARE(ICL_GUC_FIRMWARE_PATH);
static void guc_fw_select(struct intel_uc_fw *guc_fw)
{
struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
- struct drm_i915_private *i915 = guc_to_i915(guc);
+ struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
index 0355724ee997..52f814704d8e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
@@ -24,6 +24,7 @@
#include
+#include "gt/intel_gt.h"
#include "intel_guc_log.h"
#include "i915_drv.h"
@@ -215,7 +216,7 @@ static bool guc_check_log_buf_overflow(struct intel_guc_log
*log,
log->stats[type].sampled_overflow += 16;
}
- dev_notice_ratelimited(guc_to_i915(log_to_guc(log))->drm.dev,
+
dev_notice_ratelimited(guc_to_gt(log_to_guc(log))->i915->drm.dev,
"GuC log buffer overflow\n");
}
@@ -389,7 +390,7 @@ void intel_guc_log_init_early(struct intel_guc_log *log)
static int guc_log_relay_create(struct intel_guc_log *log)
{
struct intel_guc *guc = log_to_guc(log);
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915;
struct rchan *guc_log_relay_chan;
size_t n_subbufs, subbuf_size;
int ret;
@@ -435,7 +436,7 @@ static void guc_log_relay_destroy(struct intel_guc_log *log)
static void guc_log_capture_logs(struct intel_guc_log *log)
{
struct intel_guc *guc = log_to_guc(log);
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
[Intel-gfx] [PATCH 11/12] drm/i915/guc: prefer intel_gt in guc interrupt functions
We can get rid of a few more guc_to_i915 and start compartmentalizing
interrupt management a bit more. We should be able to move more code in
the future once the gt_pm code is also moved across to gt.
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/intel_gt_types.h | 2 +
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/i915_irq.c | 73 +---
3 files changed, 42 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index b711252ff427..735dcf7a445c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -62,6 +62,8 @@ struct intel_gt {
u32 pm_imr;
u32 pm_ier;
+
+ u32 pm_guc_events;
};
enum intel_gt_scratch_field {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 99004c8b833f..2ace1ad173ad 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1399,7 +1399,6 @@ struct drm_i915_private {
};
u32 gt_irq_mask;
u32 pm_rps_events;
- u32 pm_guc_events;
u32 pipestat_irq_mask[I915_MAX_PIPES];
struct i915_hotplug hotplug;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 78c748cb9df8..91f8c81028c3 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -42,6 +42,8 @@
#include "display/intel_lpe_audio.h"
#include "display/intel_psr.h"
+#include "gt/intel_gt.h"
+
#include "i915_drv.h"
#include "i915_irq.h"
#include "i915_trace.h"
@@ -601,85 +603,90 @@ void gen6_disable_rps_interrupts(struct drm_i915_private
*dev_priv)
void gen9_reset_guc_interrupts(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct intel_gt *gt = guc_to_gt(guc);
+ struct drm_i915_private *i915 = gt->i915;
- assert_rpm_wakelock_held(_priv->runtime_pm);
+ assert_rpm_wakelock_held(>runtime_pm);
- spin_lock_irq(_priv->irq_lock);
- gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events);
- spin_unlock_irq(_priv->irq_lock);
+ spin_lock_irq(>irq_lock);
+ gen6_reset_pm_iir(i915, gt->pm_guc_events);
+ spin_unlock_irq(>irq_lock);
}
void gen9_enable_guc_interrupts(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct intel_gt *gt = guc_to_gt(guc);
+ struct drm_i915_private *i915 = gt->i915;
- assert_rpm_wakelock_held(_priv->runtime_pm);
+ assert_rpm_wakelock_held(>runtime_pm);
- spin_lock_irq(_priv->irq_lock);
+ spin_lock_irq(>irq_lock);
if (!guc->interrupts.enabled) {
- WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
- dev_priv->pm_guc_events);
+ WARN_ON_ONCE(intel_uncore_read(gt->uncore, gen6_pm_iir(i915)) &
+gt->pm_guc_events);
guc->interrupts.enabled = true;
- gen6_enable_pm_irq(_priv->gt, dev_priv->pm_guc_events);
+ gen6_enable_pm_irq(gt, gt->pm_guc_events);
}
- spin_unlock_irq(_priv->irq_lock);
+ spin_unlock_irq(>irq_lock);
}
void gen9_disable_guc_interrupts(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct intel_gt *gt = guc_to_gt(guc);
+ struct drm_i915_private *i915 = gt->i915;
- assert_rpm_wakelock_held(_priv->runtime_pm);
+ assert_rpm_wakelock_held(>runtime_pm);
- spin_lock_irq(_priv->irq_lock);
+ spin_lock_irq(>irq_lock);
guc->interrupts.enabled = false;
- gen6_disable_pm_irq(_priv->gt, dev_priv->pm_guc_events);
+ gen6_disable_pm_irq(gt, gt->pm_guc_events);
- spin_unlock_irq(_priv->irq_lock);
- intel_synchronize_irq(dev_priv);
+ spin_unlock_irq(>irq_lock);
+ intel_synchronize_irq(i915);
gen9_reset_guc_interrupts(guc);
}
void gen11_reset_guc_interrupts(struct intel_guc *guc)
{
- struct drm_i915_private *i915 = guc_to_i915(guc);
+ struct intel_gt *gt = guc_to_gt(guc);
+ struct drm_i915_private *i915 = gt->i915;
spin_lock_irq(>irq_lock);
- gen11_reset_one_iir(>gt, 0, GEN11_GUC);
+ gen11_reset_one_iir(gt, 0, GEN11_GUC);
spin_unlock_irq(>irq_lock);
}
void gen11_enable_guc_interrupts(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct intel_gt *gt = guc_to_gt(guc);
- spin_lock_irq(_priv->irq_lock);
+ spin_lock_irq(>i915->irq_lock);
if (!guc->interrupts.enabled) {
u32 events = REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST);
- WARN_ON_ONCE(gen11_reset_one_iir(_priv->gt, 0, GEN11_GUC));
- I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, events);
-
[Intel-gfx] [PATCH 01/12] drm/i915/guc: Remove preemption support for current fw
From: Chris Wilson
Preemption via GuC submission is not being supported with its current
legacy incarnation. The current FW does support a similar pre-emption
flow via H2G, but it is class-based instead of being instance-based,
which doesn't fit well with the i915 tracking. To fix this, the
firmware is being updated to better support our needs with a new flow,
so we can safely remove the old code.
v2 (Daniele): resurrect & rebase, reword commit message, remove
preempt_context as well
Signed-off-by: Chris Wilson
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Michal Wajdeczko
Cc: Matthew Brost
Cc: John Harrison
Acked-by: Matthew Brost
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 17 --
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 13 --
drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 -
drivers/gpu/drm/i915/gt/intel_gt_pm.c| 4 -
drivers/gpu/drm/i915/i915_debugfs.c | 5 -
drivers/gpu/drm/i915/i915_drv.h | 2 -
drivers/gpu/drm/i915/intel_guc.c | 31 ---
drivers/gpu/drm/i915/intel_guc.h | 9 -
drivers/gpu/drm/i915/intel_guc_submission.c | 231 +--
drivers/gpu/drm/i915/selftests/intel_guc.c | 31 +--
10 files changed, 14 insertions(+), 330 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index e367dce2a696..078592912d97 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -644,18 +644,12 @@ static void init_contexts(struct drm_i915_private *i915)
init_llist_head(>contexts.free_list);
}
-static bool needs_preempt_context(struct drm_i915_private *i915)
-{
- return USES_GUC_SUBMISSION(i915);
-}
-
int i915_gem_contexts_init(struct drm_i915_private *dev_priv)
{
struct i915_gem_context *ctx;
/* Reassure ourselves we are only called once */
GEM_BUG_ON(dev_priv->kernel_context);
- GEM_BUG_ON(dev_priv->preempt_context);
init_contexts(dev_priv);
@@ -676,15 +670,6 @@ int i915_gem_contexts_init(struct drm_i915_private
*dev_priv)
GEM_BUG_ON(!atomic_read(>hw_id_pin_count));
dev_priv->kernel_context = ctx;
- /* highest priority; preempting task */
- if (needs_preempt_context(dev_priv)) {
- ctx = i915_gem_context_create_kernel(dev_priv, INT_MAX);
- if (!IS_ERR(ctx))
- dev_priv->preempt_context = ctx;
- else
- DRM_ERROR("Failed to create preempt context; disabling
preemption\n");
- }
-
DRM_DEBUG_DRIVER("%s context support initialized\n",
DRIVER_CAPS(dev_priv)->has_logical_contexts ?
"logical" : "fake");
@@ -695,8 +680,6 @@ void i915_gem_contexts_fini(struct drm_i915_private *i915)
{
lockdep_assert_held(>drm.struct_mutex);
- if (i915->preempt_context)
- destroy_kernel_context(>preempt_context);
destroy_kernel_context(>kernel_context);
/* Must free all deferred contexts (via flush_workqueue) first */
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index bdf279fa3b2e..76b5c068a26d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -841,15 +841,6 @@ int intel_engine_init_common(struct intel_engine_cs
*engine)
if (ret)
return ret;
- /*
-* Similarly the preempt context must always be available so that
-* we can interrupt the engine at any time. However, as preemption
-* is optional, we allow it to fail.
-*/
- if (i915->preempt_context)
- pin_context(i915->preempt_context, engine,
- >preempt_context);
-
ret = measure_breadcrumb_dw(engine);
if (ret < 0)
goto err_unpin;
@@ -861,8 +852,6 @@ int intel_engine_init_common(struct intel_engine_cs *engine)
return 0;
err_unpin:
- if (engine->preempt_context)
- intel_context_unpin(engine->preempt_context);
intel_context_unpin(engine->kernel_context);
return ret;
}
@@ -887,8 +876,6 @@ void intel_engine_cleanup_common(struct intel_engine_cs
*engine)
if (engine->default_state)
i915_gem_object_put(engine->default_state);
- if (engine->preempt_context)
- intel_context_unpin(engine->preempt_context);
intel_context_unpin(engine->kernel_context);
GEM_BUG_ON(!llist_empty(>barrier_tasks));
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 7e056114344e..8be63019d707 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -288,7 +288,6 @@ struct intel_engine_cs {
struct llist_head barrier_tasks;
[Intel-gfx] [PATCH 00/12] GT-fy the uc code
GuC and HuC are a subunits of the GT HW, so it makes sense for the
relevant structures to be inside intel_gt. This series introduces a new
intel_uc structure under intel_gt and moves the GuC/HuC structures in
there. All the general uc code is then encapsulated, working on intel_uc
instead of i915.
Note that a bit of ugliness is inroduced with the move because we have a
lot of layers (i915->gt.uc.guc.fw). Most of these "deep" accesses are
removed by the later patches in the series, but some of them remain,
mainly in debugfs functions. Follow up updates to make the code more
encapsulated should help cleaning up.
Cc: Michal Wajdeczko
Cc: Chris Wilson
Cc: Tvrtko Ursulin
Chris Wilson (1):
drm/i915/guc: Remove preemption support for current fw
Daniele Ceraolo Spurio (11):
drm/i915/guc: simplify guc client
drm/i915/uc: replace uc init/fini misc
drm/i915/uc: introduce intel_uc_fw_supported
drm/i915/guc: move guc irq functions to intel_guc parameter
drm/i915/guc: unify guc irq handling
drm/i915/uc: move GuC and HuC files under gt/uc/
drm/i915/uc: move GuC/HuC inside intel_gt under a new intel_uc
drm/i915/uc: Move intel functions to intel_uc
drm/i915/uc: prefer intel_gt over i915 in GuC/HuC paths
drm/i915/guc: prefer intel_gt in guc interrupt functions
drm/i915/uc: kill uc_to_i915
drivers/gpu/drm/i915/Makefile | 21 +-
drivers/gpu/drm/i915/Makefile.header-test | 4 -
drivers/gpu/drm/i915/gem/i915_gem_context.c | 17 -
drivers/gpu/drm/i915/gem/i915_gem_pm.c| 6 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 13 -
drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 -
drivers/gpu/drm/i915/gt/intel_gt.h| 15 +
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 -
drivers/gpu/drm/i915/gt/intel_gt_types.h | 6 +
drivers/gpu/drm/i915/gt/intel_reset.c | 10 +-
drivers/gpu/drm/i915/gt/uc/Makefile | 5 +
.../gpu/drm/i915/gt/uc/Makefile.header-test | 16 +
drivers/gpu/drm/i915/{ => gt/uc}/intel_guc.c | 144 ++-
drivers/gpu/drm/i915/{ => gt/uc}/intel_guc.h | 17 +-
.../gpu/drm/i915/{ => gt/uc}/intel_guc_ads.c | 3 +-
.../gpu/drm/i915/{ => gt/uc}/intel_guc_ads.h | 0
.../gpu/drm/i915/{ => gt/uc}/intel_guc_ct.c | 0
.../gpu/drm/i915/{ => gt/uc}/intel_guc_ct.h | 0
.../gpu/drm/i915/{ => gt/uc}/intel_guc_fw.c | 89 +++--
.../gpu/drm/i915/{ => gt/uc}/intel_guc_fw.h | 0
.../gpu/drm/i915/{ => gt/uc}/intel_guc_fwif.h | 0
.../gpu/drm/i915/{ => gt/uc}/intel_guc_log.c | 44 ++-
.../gpu/drm/i915/{ => gt/uc}/intel_guc_log.h | 0
.../gpu/drm/i915/{ => gt/uc}/intel_guc_reg.h | 32 +-
.../i915/{ => gt/uc}/intel_guc_submission.c | 358 ++
.../i915/{ => gt/uc}/intel_guc_submission.h | 2 -
drivers/gpu/drm/i915/{ => gt/uc}/intel_huc.c | 32 +-
drivers/gpu/drm/i915/{ => gt/uc}/intel_huc.h | 6 -
.../gpu/drm/i915/{ => gt/uc}/intel_huc_fw.c | 12 +-
.../gpu/drm/i915/{ => gt/uc}/intel_huc_fw.h | 0
drivers/gpu/drm/i915/{ => gt/uc}/intel_uc.c | 237 ++--
drivers/gpu/drm/i915/{ => gt/uc}/intel_uc.h | 39 +-
.../gpu/drm/i915/{ => gt/uc}/intel_uc_fw.c| 4 +-
.../gpu/drm/i915/{ => gt/uc}/intel_uc_fw.h| 30 +-
.../intel_guc.c => gt/uc/selftest_guc.c} | 45 +--
drivers/gpu/drm/i915/i915_debugfs.c | 36 +-
drivers/gpu/drm/i915/i915_drv.c | 18 +-
drivers/gpu/drm/i915/i915_drv.h | 24 +-
drivers/gpu/drm/i915/i915_gem.c | 24 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 8 +-
drivers/gpu/drm/i915/i915_gem_gtt.h | 4 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 11 +-
drivers/gpu/drm/i915/i915_gpu_error.h | 2 +-
drivers/gpu/drm/i915/i915_irq.c | 127 ---
drivers/gpu/drm/i915/i915_irq.h | 13 +-
drivers/gpu/drm/i915/i915_reg.h | 10 -
drivers/gpu/drm/i915/intel_wopcm.c| 4 +-
47 files changed, 556 insertions(+), 937 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/uc/Makefile
create mode 100644 drivers/gpu/drm/i915/gt/uc/Makefile.header-test
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc.c (78%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc.h (92%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_ads.c (98%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_ads.h (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_ct.c (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_ct.h (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_fw.c (78%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_fw.h (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_fwif.h (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_log.c (92%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_log.h (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_reg.h (88%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_submission.c (74%)
rename drivers/gpu/drm/i915/{ =>
[Intel-gfx] [PATCH 03/12] drm/i915/uc: replace uc init/fini misc
The "misc" terminology doesn't clearly explain what we intend to cover
in this phase. The only thing we do in there apart from FW fetch is
initializing the log workqueue, with the latter being required only in
the very rare case where we enable the log relay. To clean this up, we
can move the wq init to when the relay is enabled and rename the
function to clarify that they only fetch/release the blobs.
v2: only create log wq when needed (Michal), reword commit msg
accordingly
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
---
drivers/gpu/drm/i915/i915_gem.c | 12 +++
drivers/gpu/drm/i915/intel_guc.c | 53
drivers/gpu/drm/i915/intel_guc.h | 2 --
drivers/gpu/drm/i915/intel_guc_log.c | 31 +++-
drivers/gpu/drm/i915/intel_huc.c | 8 -
drivers/gpu/drm/i915/intel_huc.h | 6
drivers/gpu/drm/i915/intel_uc.c | 34 +-
drivers/gpu/drm/i915/intel_uc.h | 4 +--
8 files changed, 45 insertions(+), 105 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 7ade42b8ec99..e6e8e4d5ebb1 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1433,13 +1433,11 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
if (ret)
return ret;
- ret = intel_uc_init_misc(dev_priv);
- if (ret)
- return ret;
+ intel_uc_fetch_firmwares(dev_priv);
ret = intel_wopcm_init(_priv->wopcm);
if (ret)
- goto err_uc_misc;
+ goto err_uc_fw;
/* This is just a security blanket to placate dragons.
* On some systems, we very sporadically observe that the first TLBs
@@ -1565,8 +1563,8 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
intel_uncore_forcewake_put(_priv->uncore, FORCEWAKE_ALL);
mutex_unlock(_priv->drm.struct_mutex);
-err_uc_misc:
- intel_uc_fini_misc(dev_priv);
+err_uc_fw:
+ intel_uc_cleanup_firmwares(dev_priv);
if (ret != -EIO) {
i915_gem_cleanup_userptr(dev_priv);
@@ -1632,7 +1630,7 @@ void i915_gem_fini(struct drm_i915_private *dev_priv)
intel_cleanup_gt_powersave(dev_priv);
- intel_uc_fini_misc(dev_priv);
+ intel_uc_cleanup_firmwares(dev_priv);
i915_gem_cleanup_userptr(dev_priv);
intel_timelines_fini(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 501b74f44374..4173b35bf104 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -99,59 +99,6 @@ void intel_guc_init_early(struct intel_guc *guc)
}
}
-static int guc_init_wq(struct intel_guc *guc)
-{
- /*
-* GuC log buffer flush work item has to do register access to
-* send the ack to GuC and this work item, if not synced before
-* suspend, can potentially get executed after the GFX device is
-* suspended.
-* By marking the WQ as freezable, we don't have to bother about
-* flushing of this work item from the suspend hooks, the pending
-* work item if any will be either executed before the suspend
-* or scheduled later on resume. This way the handling of work
-* item can be kept same between system suspend & rpm suspend.
-*/
- guc->log.relay.flush_wq =
- alloc_ordered_workqueue("i915-guc_log",
- WQ_HIGHPRI | WQ_FREEZABLE);
- if (!guc->log.relay.flush_wq) {
- DRM_ERROR("Couldn't allocate workqueue for GuC log\n");
- return -ENOMEM;
- }
-
- return 0;
-}
-
-static void guc_fini_wq(struct intel_guc *guc)
-{
- struct workqueue_struct *wq;
-
- wq = fetch_and_zero(>log.relay.flush_wq);
- if (wq)
- destroy_workqueue(wq);
-}
-
-int intel_guc_init_misc(struct intel_guc *guc)
-{
- struct drm_i915_private *i915 = guc_to_i915(guc);
- int ret;
-
- ret = guc_init_wq(guc);
- if (ret)
- return ret;
-
- intel_uc_fw_fetch(i915, >fw);
-
- return 0;
-}
-
-void intel_guc_fini_misc(struct intel_guc *guc)
-{
- intel_uc_fw_cleanup_fetch(>fw);
- guc_fini_wq(guc);
-}
-
static int guc_shared_data_create(struct intel_guc *guc)
{
struct i915_vma *vma;
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index ec1038c1f50e..91d538fd5f65 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -153,10 +153,8 @@ static inline u32 intel_guc_ggtt_offset(struct intel_guc
*guc,
void intel_guc_init_early(struct intel_guc *guc);
void intel_guc_init_send_regs(struct intel_guc *guc);
void intel_guc_init_params(struct intel_guc *guc);
-int intel_guc_init_misc(struct intel_guc *guc);
int intel_guc_init(struct intel_guc *guc);
void intel_guc_fini(struct intel_guc *guc);
-void
[Intel-gfx] [PATCH 10/12] drm/i915/uc: prefer intel_gt over i915 in GuC/HuC paths
With our HW interface logic moving from i915 to gt and with GuC and HuC
being part of the gt HW, it makes sense to use the intel_gt structure
instead of i915 as our reference object in GuC/HuC paths.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
---
drivers/gpu/drm/i915/gt/intel_gt.h| 10 +++
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 52 ++--
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 81 ++-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 43 +-
drivers/gpu/drm/i915/gt/uc/intel_huc.c| 22 ++---
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 4 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 8 +-
drivers/gpu/drm/i915/i915_gem_gtt.h | 4 +-
9 files changed, 120 insertions(+), 108 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
b/drivers/gpu/drm/i915/gt/intel_gt.h
index 880be05a3f4a..e182509d44ba 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -16,6 +16,16 @@ static inline struct intel_gt *uc_to_gt(struct intel_uc *uc)
return container_of(uc, struct intel_gt, uc);
}
+static inline struct intel_gt *guc_to_gt(struct intel_guc *guc)
+{
+ return container_of(guc, struct intel_gt, uc.guc);
+}
+
+static inline struct intel_gt *huc_to_gt(struct intel_huc *huc)
+{
+ return container_of(huc, struct intel_gt, uc.huc);
+}
+
void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915);
void intel_gt_init_hw(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 4173b35bf104..6b56f39072b1 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -22,6 +22,7 @@
*
*/
+#include "gt/intel_gt.h"
#include "intel_guc.h"
#include "intel_guc_ads.h"
#include "intel_guc_submission.h"
@@ -29,16 +30,16 @@
static void gen8_guc_raise_irq(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct intel_gt *gt = guc_to_gt(guc);
- I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
+ intel_uncore_write(gt->uncore, GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
}
static void gen11_guc_raise_irq(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct intel_gt *gt = guc_to_gt(guc);
- I915_WRITE(GEN11_GUC_HOST_INTERRUPT, 0);
+ intel_uncore_write(gt->uncore, GEN11_GUC_HOST_INTERRUPT, 0);
}
static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
@@ -52,11 +53,11 @@ static inline i915_reg_t guc_send_reg(struct intel_guc
*guc, u32 i)
void intel_guc_init_send_regs(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct intel_gt *gt = guc_to_gt(guc);
enum forcewake_domains fw_domains = 0;
unsigned int i;
- if (INTEL_GEN(dev_priv) >= 11) {
+ if (INTEL_GEN(gt->i915) >= 11) {
guc->send_regs.base =
i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0));
guc->send_regs.count = GEN11_SOFT_SCRATCH_COUNT;
@@ -67,7 +68,7 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
}
for (i = 0; i < guc->send_regs.count; i++) {
- fw_domains |= intel_uncore_forcewake_for_reg(_priv->uncore,
+ fw_domains |= intel_uncore_forcewake_for_reg(gt->uncore,
guc_send_reg(guc, i),
FW_REG_READ | FW_REG_WRITE);
}
@@ -127,7 +128,7 @@ static void guc_shared_data_destroy(struct intel_guc *guc)
int intel_guc_init(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct intel_gt *gt = guc_to_gt(guc);
int ret;
ret = intel_uc_fw_init(>fw);
@@ -153,7 +154,7 @@ int intel_guc_init(struct intel_guc *guc)
goto err_ads;
/* We need to notify the guc whenever we change the GGTT */
- i915_ggtt_enable_guc(dev_priv);
+ i915_ggtt_enable_guc(gt->ggtt);
return 0;
@@ -172,9 +173,9 @@ int intel_guc_init(struct intel_guc *guc)
void intel_guc_fini(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct intel_gt *gt = guc_to_gt(guc);
- i915_ggtt_disable_guc(dev_priv);
+ i915_ggtt_disable_guc(gt->ggtt);
intel_guc_ct_fini(>ct);
@@ -282,7 +283,7 @@ static u32 guc_ctl_ads_flags(struct intel_guc *guc)
*/
void intel_guc_init_params(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
u32 params[GUC_CTL_MAX_DWORDS];
int i;
@@ -302,14 +303,14 @@ void intel_guc_init_params(struct intel_guc *guc)
* they are power context saved so
[Intel-gfx] [PATCH 05/12] drm/i915/guc: move guc irq functions to intel_guc parameter
No functional change, just moving the guc_to_i915 from the caller into
the irq function. This will help with the upcoming move of guc under
intel_gt.
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/i915_irq.c | 40 +---
drivers/gpu/drm/i915/i915_irq.h | 13 ++-
drivers/gpu/drm/i915/intel_guc.h | 6 ++---
drivers/gpu/drm/i915/intel_uc.c | 6 ++---
4 files changed, 39 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 7c5ba5cbea34..831d185c07d2 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -599,8 +599,10 @@ void gen6_disable_rps_interrupts(struct drm_i915_private
*dev_priv)
gen6_reset_rps_interrupts(dev_priv);
}
-void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
+void gen9_reset_guc_interrupts(struct intel_guc *guc)
{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
assert_rpm_wakelock_held(_priv->runtime_pm);
spin_lock_irq(_priv->irq_lock);
@@ -608,61 +610,71 @@ void gen9_reset_guc_interrupts(struct drm_i915_private
*dev_priv)
spin_unlock_irq(_priv->irq_lock);
}
-void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
+void gen9_enable_guc_interrupts(struct intel_guc *guc)
{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
assert_rpm_wakelock_held(_priv->runtime_pm);
spin_lock_irq(_priv->irq_lock);
- if (!dev_priv->guc.interrupts.enabled) {
+ if (!guc->interrupts.enabled) {
WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
dev_priv->pm_guc_events);
- dev_priv->guc.interrupts.enabled = true;
+ guc->interrupts.enabled = true;
gen6_enable_pm_irq(_priv->gt, dev_priv->pm_guc_events);
}
spin_unlock_irq(_priv->irq_lock);
}
-void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
+void gen9_disable_guc_interrupts(struct intel_guc *guc)
{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
assert_rpm_wakelock_held(_priv->runtime_pm);
spin_lock_irq(_priv->irq_lock);
- dev_priv->guc.interrupts.enabled = false;
+ guc->interrupts.enabled = false;
gen6_disable_pm_irq(_priv->gt, dev_priv->pm_guc_events);
spin_unlock_irq(_priv->irq_lock);
intel_synchronize_irq(dev_priv);
- gen9_reset_guc_interrupts(dev_priv);
+ gen9_reset_guc_interrupts(guc);
}
-void gen11_reset_guc_interrupts(struct drm_i915_private *i915)
+void gen11_reset_guc_interrupts(struct intel_guc *guc)
{
+ struct drm_i915_private *i915 = guc_to_i915(guc);
+
spin_lock_irq(>irq_lock);
gen11_reset_one_iir(>gt, 0, GEN11_GUC);
spin_unlock_irq(>irq_lock);
}
-void gen11_enable_guc_interrupts(struct drm_i915_private *dev_priv)
+void gen11_enable_guc_interrupts(struct intel_guc *guc)
{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
spin_lock_irq(_priv->irq_lock);
- if (!dev_priv->guc.interrupts.enabled) {
+ if (!guc->interrupts.enabled) {
u32 events = REG_FIELD_PREP(ENGINE1_MASK,
GEN11_GUC_INTR_GUC2HOST);
WARN_ON_ONCE(gen11_reset_one_iir(_priv->gt, 0, GEN11_GUC));
I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, events);
I915_WRITE(GEN11_GUC_SG_INTR_MASK, ~events);
- dev_priv->guc.interrupts.enabled = true;
+ guc->interrupts.enabled = true;
}
spin_unlock_irq(_priv->irq_lock);
}
-void gen11_disable_guc_interrupts(struct drm_i915_private *dev_priv)
+void gen11_disable_guc_interrupts(struct intel_guc *guc)
{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
spin_lock_irq(_priv->irq_lock);
- dev_priv->guc.interrupts.enabled = false;
+ guc->interrupts.enabled = false;
I915_WRITE(GEN11_GUC_SG_INTR_MASK, ~0);
I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, 0);
@@ -670,7 +682,7 @@ void gen11_disable_guc_interrupts(struct drm_i915_private
*dev_priv)
spin_unlock_irq(_priv->irq_lock);
intel_synchronize_irq(dev_priv);
- gen11_reset_guc_interrupts(dev_priv);
+ gen11_reset_guc_interrupts(guc);
}
/**
diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h
index d93fa4e75442..c3716d674bb9 100644
--- a/drivers/gpu/drm/i915/i915_irq.h
+++ b/drivers/gpu/drm/i915/i915_irq.h
@@ -12,6 +12,7 @@
struct drm_i915_private;
struct intel_crtc;
+struct intel_guc;
extern void intel_irq_init(struct drm_i915_private *dev_priv);
extern void intel_irq_fini(struct drm_i915_private *dev_priv);
@@ -112,12 +113,12 @@ void gen8_irq_power_well_post_enable(struct
drm_i915_private *dev_priv,
u8 pipe_mask);
void
[Intel-gfx] [PATCH 06/12] drm/i915/guc: unify guc irq handling
The 16-bit guc irq vector is unchanged across gens, the only thing that
moved is its position (from the upper 16 bits of the PM regs to its own
register). Instead of duplicating all defines and functions to handle
the 2 different positions, we can work on the vector and shift it as
appropriate. While at it, update the handler to work on intel_guc.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
---
drivers/gpu/drm/i915/i915_irq.c | 24 -
drivers/gpu/drm/i915/i915_reg.h | 10 -
drivers/gpu/drm/i915/intel_guc_reg.h | 32 ++--
3 files changed, 25 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 831d185c07d2..42d6d8bfac70 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -264,7 +264,7 @@ static void gen2_irq_init(struct intel_uncore *uncore,
gen2_irq_init((uncore), imr_val, ier_val)
static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32
pm_iir);
-static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32
pm_iir);
+static void guc_irq_handler(struct intel_guc *guc, u16 guc_iir);
/* For display hotplug interrupt */
static inline void
@@ -658,8 +658,7 @@ void gen11_enable_guc_interrupts(struct intel_guc *guc)
spin_lock_irq(_priv->irq_lock);
if (!guc->interrupts.enabled) {
- u32 events = REG_FIELD_PREP(ENGINE1_MASK,
- GEN11_GUC_INTR_GUC2HOST);
+ u32 events = REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST);
WARN_ON_ONCE(gen11_reset_one_iir(_priv->gt, 0, GEN11_GUC));
I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, events);
@@ -1656,7 +1655,7 @@ static void gen8_gt_irq_handler(struct drm_i915_private
*i915,
if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
gen6_rps_irq_handler(i915, gt_iir[2]);
- gen9_guc_irq_handler(i915, gt_iir[2]);
+ guc_irq_handler(>guc, gt_iir[2] >> 16);
}
}
@@ -1955,16 +1954,10 @@ static void gen6_rps_irq_handler(struct
drm_i915_private *dev_priv, u32 pm_iir)
DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
}
-static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir)
+static void guc_irq_handler(struct intel_guc *guc, u16 iir)
{
- if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT)
- intel_guc_to_host_event_handler(_priv->guc);
-}
-
-static void gen11_guc_irq_handler(struct drm_i915_private *i915, u16 iir)
-{
- if (iir & GEN11_GUC_INTR_GUC2HOST)
- intel_guc_to_host_event_handler(>guc);
+ if (iir & GUC_INTR_GUC2HOST)
+ intel_guc_to_host_event_handler(guc);
}
static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
@@ -3092,7 +3085,7 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8
instance,
struct drm_i915_private *i915 = gt->i915;
if (instance == OTHER_GUC_INSTANCE)
- return gen11_guc_irq_handler(i915, iir);
+ return guc_irq_handler(>guc, iir);
if (instance == OTHER_GTPM_INSTANCE)
return gen11_rps_irq_handler(gt, iir);
@@ -4764,8 +4757,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
for (i = 0; i < MAX_L3_SLICES; ++i)
dev_priv->l3_parity.remap_info[i] = NULL;
+ /* pre-gen11 the guc irqs bits are in the upper 16 bits of the pm reg */
if (HAS_GUC_SCHED(dev_priv) && INTEL_GEN(dev_priv) < 11)
- dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT;
+ dev_priv->pm_guc_events = GUC_INTR_GUC2HOST << 16;
/* Let's track the enabled rps events */
if (IS_VALLEYVIEW(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5898f59e3dd7..4dc31e488b80 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7342,16 +7342,6 @@ enum {
#define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
#define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
-#define GEN9_GUC_TO_HOST_INT_EVENT (1 << 31)
-#define GEN9_GUC_EXEC_ERROR_EVENT (1 << 30)
-#define GEN9_GUC_DISPLAY_EVENT (1 << 29)
-#define GEN9_GUC_SEMA_SIGNAL_EVENT (1 << 28)
-#define GEN9_GUC_IOMMU_MSG_EVENT (1 << 27)
-#define GEN9_GUC_DB_RING_EVENT (1 << 26)
-#define GEN9_GUC_DMA_DONE_EVENT(1 << 25)
-#define GEN9_GUC_FATAL_ERROR_EVENT (1 << 24)
-#define GEN9_GUC_NOTIFICATION_EVENT(1 << 23)
-
#define GEN8_RCS_IRQ_SHIFT 0
#define GEN8_BCS_IRQ_SHIFT 16
#define GEN8_VCS0_IRQ_SHIFT 0 /* NB: VCS1 in bspec! */
diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h
b/drivers/gpu/drm/i915/intel_guc_reg.h
index a5ab7bc5504c..e3cbb23299ce 100644
--- a/drivers/gpu/drm/i915/intel_guc_reg.h
+++ b/drivers/gpu/drm/i915/intel_guc_reg.h
@@ -141,21
[Intel-gfx] [PATCH 07/12] drm/i915/uc: move GuC and HuC files under gt/uc/
Both microcontrollers are part of the GT HW and are closely related to
GT operations. To keep all the files cleanly together, they've been
placed in their own subdir inside the gt/ folder
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Cc: Chris Wilson
---
drivers/gpu/drm/i915/Makefile | 21 ++-
drivers/gpu/drm/i915/Makefile.header-test | 4
drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
drivers/gpu/drm/i915/gt/uc/Makefile | 5 +
.../gpu/drm/i915/gt/uc/Makefile.header-test | 16 ++
drivers/gpu/drm/i915/{ => gt/uc}/intel_guc.c | 0
drivers/gpu/drm/i915/{ => gt/uc}/intel_guc.h | 0
.../gpu/drm/i915/{ => gt/uc}/intel_guc_ads.c | 0
.../gpu/drm/i915/{ => gt/uc}/intel_guc_ads.h | 0
.../gpu/drm/i915/{ => gt/uc}/intel_guc_ct.c | 0
.../gpu/drm/i915/{ => gt/uc}/intel_guc_ct.h | 0
.../gpu/drm/i915/{ => gt/uc}/intel_guc_fw.c | 0
.../gpu/drm/i915/{ => gt/uc}/intel_guc_fw.h | 0
.../gpu/drm/i915/{ => gt/uc}/intel_guc_fwif.h | 0
.../gpu/drm/i915/{ => gt/uc}/intel_guc_log.c | 0
.../gpu/drm/i915/{ => gt/uc}/intel_guc_log.h | 0
.../gpu/drm/i915/{ => gt/uc}/intel_guc_reg.h | 0
.../i915/{ => gt/uc}/intel_guc_submission.c | 9
.../i915/{ => gt/uc}/intel_guc_submission.h | 0
drivers/gpu/drm/i915/{ => gt/uc}/intel_huc.c | 0
drivers/gpu/drm/i915/{ => gt/uc}/intel_huc.h | 0
.../gpu/drm/i915/{ => gt/uc}/intel_huc_fw.c | 0
.../gpu/drm/i915/{ => gt/uc}/intel_huc_fw.h | 0
drivers/gpu/drm/i915/{ => gt/uc}/intel_uc.c | 0
drivers/gpu/drm/i915/{ => gt/uc}/intel_uc.h | 0
.../gpu/drm/i915/{ => gt/uc}/intel_uc_fw.c| 0
.../gpu/drm/i915/{ => gt/uc}/intel_uc_fw.h| 0
.../intel_guc.c => gt/uc/selftest_guc.c} | 0
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gpu_error.h | 2 +-
32 files changed, 42 insertions(+), 23 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/uc/Makefile
create mode 100644 drivers/gpu/drm/i915/gt/uc/Makefile.header-test
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc.c (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc.h (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_ads.c (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_ads.h (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_ct.c (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_ct.h (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_fw.c (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_fw.h (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_fwif.h (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_log.c (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_log.h (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_reg.h (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_submission.c (99%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_submission.h (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_huc.c (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_huc.h (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_huc_fw.c (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_huc_fw.h (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_uc.c (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_uc.h (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_uc_fw.c (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_uc_fw.h (100%)
rename drivers/gpu/drm/i915/{selftests/intel_guc.c => gt/uc/selftest_guc.c}
(100%)
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 5266dbeab01f..524516251a40 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -139,16 +139,17 @@ i915-y += \
intel_wopcm.o
# general-purpose microcontroller (GuC) support
-i915-y += intel_uc.o \
- intel_uc_fw.o \
- intel_guc.o \
- intel_guc_ads.o \
- intel_guc_ct.o \
- intel_guc_fw.o \
- intel_guc_log.o \
- intel_guc_submission.o \
- intel_huc.o \
- intel_huc_fw.o
+obj-y += gt/uc/
+i915-y += gt/uc/intel_uc.o \
+ gt/uc/intel_uc_fw.o \
+ gt/uc/intel_guc.o \
+ gt/uc/intel_guc_ads.o \
+ gt/uc/intel_guc_ct.o \
+ gt/uc/intel_guc_fw.o \
+ gt/uc/intel_guc_log.o \
+ gt/uc/intel_guc_submission.o \
+ gt/uc/intel_huc.o \
+ gt/uc/intel_huc_fw.o
# modesetting core code
obj-y += display/
diff --git a/drivers/gpu/drm/i915/Makefile.header-test
b/drivers/gpu/drm/i915/Makefile.header-test
index 2fd61869bdaa..88ad1ad31c9b 100644
--- a/drivers/gpu/drm/i915/Makefile.header-test
+++ b/drivers/gpu/drm/i915/Makefile.header-test
@@ -19,14 +19,10 @@ header_test := \
i915_vgpu.h \
intel_csr.h \
intel_drv.h \
- intel_guc_ct.h \
- intel_guc_fwif.h
[Intel-gfx] [PATCH 02/12] drm/i915/guc: simplify guc client
We originally added support, in some cases partial, for different modes
of operations via guc clients:
- proxy vs direct submission;
- variable engine mask per-client.
We only ever used one flow (all submissions via a single proxy), so the
other code paths haven't been exercised and are most likely
non-functional. The guc firmware interface is also in the process of
being updated to better fit the i915 flow and our client abstraction
will need to change accordingly (or possibly go away entirely), so these
old unused paths can be considered dead and removed.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Michal Wajdeczko
Cc: Matthew Brost
Cc: John Harrison
Acked-by: Matthew Brost
---
drivers/gpu/drm/i915/i915_debugfs.c | 3 +-
drivers/gpu/drm/i915/intel_guc_submission.c | 73 ++---
drivers/gpu/drm/i915/intel_guc_submission.h | 2 -
drivers/gpu/drm/i915/selftests/intel_guc.c | 12 +---
4 files changed, 8 insertions(+), 82 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index b4d195677877..dc65a6131a5b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2021,7 +2021,6 @@ static int i915_guc_stage_pool(struct seq_file *m, void
*data)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
const struct intel_guc *guc = _priv->guc;
struct guc_stage_desc *desc = guc->stage_desc_pool_vaddr;
- struct intel_guc_client *client = guc->execbuf_client;
intel_engine_mask_t tmp;
int index;
@@ -2051,7 +2050,7 @@ static int i915_guc_stage_pool(struct seq_file *m, void
*data)
desc->wq_addr, desc->wq_size);
seq_putc(m, '\n');
- for_each_engine_masked(engine, dev_priv, client->engines, tmp) {
+ for_each_engine(engine, dev_priv, tmp) {
u32 guc_engine_id = engine->guc_id;
struct guc_execlist_context *lrc =
>lrc[guc_engine_id];
diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c
b/drivers/gpu/drm/i915/intel_guc_submission.c
index 8520bb224175..30692f8289bd 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -363,10 +363,7 @@ static void guc_stage_desc_pool_destroy(struct intel_guc
*guc)
static void guc_stage_desc_init(struct intel_guc_client *client)
{
struct intel_guc *guc = client->guc;
- struct i915_gem_context *ctx = client->owner;
- struct i915_gem_engines_iter it;
struct guc_stage_desc *desc;
- struct intel_context *ce;
u32 gfx_addr;
desc = __get_stage_desc(client);
@@ -380,55 +377,6 @@ static void guc_stage_desc_init(struct intel_guc_client
*client)
desc->priority = client->priority;
desc->db_id = client->doorbell_id;
- for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
- struct guc_execlist_context *lrc;
-
- if (!(ce->engine->mask & client->engines))
- continue;
-
- /* TODO: We have a design issue to be solved here. Only when we
-* receive the first batch, we know which engine is used by the
-* user. But here GuC expects the lrc and ring to be pinned. It
-* is not an issue for default context, which is the only one
-* for now who owns a GuC client. But for future owner of GuC
-* client, need to make sure lrc is pinned prior to enter here.
-*/
- if (!ce->state)
- break; /* XXX: continue? */
-
- /*
-* XXX: When this is a GUC_STAGE_DESC_ATTR_KERNEL client (proxy
-* submission or, in other words, not using a direct submission
-* model) the KMD's LRCA is not used for any work submission.
-* Instead, the GuC uses the LRCA of the user mode context (see
-* guc_add_request below).
-*/
- lrc = >lrc[ce->engine->guc_id];
- lrc->context_desc = lower_32_bits(ce->lrc_desc);
-
- /* The state page is after PPHWSP */
- lrc->ring_lrca = intel_guc_ggtt_offset(guc, ce->state) +
-LRC_STATE_PN * PAGE_SIZE;
-
- /* XXX: In direct submission, the GuC wants the HW context id
-* here. In proxy submission, it wants the stage id
-*/
- lrc->context_id = (client->stage_id << GUC_ELC_CTXID_OFFSET) |
- (ce->engine->guc_id << GUC_ELC_ENGINE_OFFSET);
-
- lrc->ring_begin = intel_guc_ggtt_offset(guc, ce->ring->vma);
- lrc->ring_end = lrc->ring_begin + ce->ring->size - 1;
- lrc->ring_next_free_location = lrc->ring_begin;
-
[Intel-gfx] [PATCH 04/12] drm/i915/uc: introduce intel_uc_fw_supported
Instead of always checking in the device config is GuC and HuC are
supported or not, we can save the state in the uc_fw structure and
avoid going through i915 every time from the low-level uc management
code. while at it FIRMWARE_NONE has been renamed to better indicate that
we haven't started the fetch/load yet, but we might have already selected
a blob.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
---
drivers/gpu/drm/i915/intel_guc_fw.c | 6 +-
drivers/gpu/drm/i915/intel_huc_fw.c | 6 +-
drivers/gpu/drm/i915/intel_uc.c | 25
drivers/gpu/drm/i915/intel_uc_fw.c | 4 +++-
drivers/gpu/drm/i915/intel_uc_fw.h | 30 -
5 files changed, 51 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c
b/drivers/gpu/drm/i915/intel_guc_fw.c
index db1e0daca7db..ee95d4960c5c 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -79,8 +79,12 @@ static void guc_fw_select(struct intel_uc_fw *guc_fw)
GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);
- if (!HAS_GUC(i915))
+ if (!HAS_GUC(i915)) {
+ guc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_SUPPORTED;
return;
+ }
+
+ guc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_STARTED;
if (i915_modparams.guc_firmware_path) {
guc_fw->path = i915_modparams.guc_firmware_path;
diff --git a/drivers/gpu/drm/i915/intel_huc_fw.c
b/drivers/gpu/drm/i915/intel_huc_fw.c
index 05cbf8338f53..06e726ba9863 100644
--- a/drivers/gpu/drm/i915/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/intel_huc_fw.c
@@ -73,8 +73,12 @@ static void huc_fw_select(struct intel_uc_fw *huc_fw)
GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
- if (!HAS_HUC(dev_priv))
+ if (!HAS_HUC(dev_priv)) {
+ huc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_SUPPORTED;
return;
+ }
+
+ huc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_STARTED;
if (i915_modparams.huc_firmware_path) {
huc_fw->path = i915_modparams.huc_firmware_path;
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 789b0bccfb41..ef2a864b8990 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -71,7 +71,8 @@ static int __get_default_guc_log_level(struct
drm_i915_private *i915)
{
int guc_log_level;
- if (!HAS_GUC(i915) || !intel_uc_is_using_guc(i915))
+ if (!intel_uc_fw_supported(>guc.fw) ||
+ !intel_uc_is_using_guc(i915))
guc_log_level = GUC_LOG_LEVEL_DISABLED;
else if (IS_ENABLED(CONFIG_DRM_I915_DEBUG) ||
IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
@@ -119,16 +120,16 @@ static void sanitize_options_early(struct
drm_i915_private *i915)
if (intel_uc_is_using_guc(i915) && !intel_uc_fw_is_selected(guc_fw)) {
DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
"enable_guc", i915_modparams.enable_guc,
-!HAS_GUC(i915) ? "no GuC hardware" :
- "no GuC firmware");
+!intel_uc_fw_supported(guc_fw) ?
+ "no GuC hardware" : "no GuC firmware");
}
/* Verify HuC firmware availability */
if (intel_uc_is_using_huc(i915) && !intel_uc_fw_is_selected(huc_fw)) {
DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
"enable_guc", i915_modparams.enable_guc,
-!HAS_HUC(i915) ? "no HuC hardware" :
- "no HuC firmware");
+!intel_uc_fw_supported(huc_fw) ?
+ "no HuC hardware" : "no HuC firmware");
}
/* XXX: GuC submission is unavailable for now */
@@ -148,8 +149,8 @@ static void sanitize_options_early(struct drm_i915_private
*i915)
if (i915_modparams.guc_log_level > 0 && !intel_uc_is_using_guc(i915)) {
DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
"guc_log_level", i915_modparams.guc_log_level,
-!HAS_GUC(i915) ? "no GuC hardware" :
- "GuC not enabled");
+!intel_uc_fw_supported(guc_fw) ?
+ "no GuC hardware" : "GuC not enabled");
i915_modparams.guc_log_level = 0;
}
@@ -376,7 +377,7 @@ int intel_uc_init(struct drm_i915_private *i915)
if (!USES_GUC(i915))
return 0;
- if (!HAS_GUC(i915))
+ if (!intel_uc_fw_supported(>fw))
return -ENODEV;
/* XXX: GuC submission is unavailable for now */
@@ -419,7 +420,7 @@ void intel_uc_fini(struct drm_i915_private *i915)
if (!USES_GUC(i915))
return;
-
[Intel-gfx] [PATCH 08/12] drm/i915/uc: move GuC/HuC inside intel_gt under a new intel_uc
Being part of the GT HW, it make sense to keep the guc/huc structures
inside the GT structure. To help with the encapsulation work done by the
following patches, both structures are placed inside a new intel_uc
container. Although this results in code with ugly nested dereferences
(i915->gt.uc.guc...), it saves us the extra work required in moving
the structures twice (i915 -> gt -> uc). The following patches will
reduce the number of places where we try to access the guc/huc
structures directly from i915 and reduce the ugliness.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_gt_types.h | 4 ++
drivers/gpu/drm/i915/gt/intel_reset.c | 6 +--
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_huc.c| 4 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 52 +--
drivers/gpu/drm/i915/gt/uc/intel_uc.h | 5 ++
drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 4 +-
drivers/gpu/drm/i915/i915_debugfs.c | 26 +-
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 7 +--
drivers/gpu/drm/i915/i915_gpu_error.c | 11 ++--
drivers/gpu/drm/i915/i915_irq.c | 6 +--
drivers/gpu/drm/i915/intel_wopcm.c| 4 +-
13 files changed, 69 insertions(+), 64 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 3563ce970102..b711252ff427 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -13,6 +13,8 @@
#include
#include
+#include "uc/intel_uc.h"
+
#include "i915_vma.h"
#include "intel_wakeref.h"
@@ -25,6 +27,8 @@ struct intel_gt {
struct intel_uncore *uncore;
struct i915_ggtt *ggtt;
+ struct intel_uc uc;
+
struct intel_gt_timelines {
struct mutex mutex; /* protects list */
struct list_head active_list;
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
b/drivers/gpu/drm/i915/gt/intel_reset.c
index 9abfa28c3020..ccedea636ba3 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -1109,14 +1109,14 @@ int i915_reset_engine(struct intel_engine_cs *engine,
const char *msg)
"Resetting %s for %s\n", engine->name, msg);
error->reset_engine_count[engine->id]++;
- if (!engine->i915->guc.execbuf_client)
+ if (!engine->gt->uc.guc.execbuf_client)
ret = intel_gt_reset_engine(engine->i915, engine);
else
- ret = intel_guc_reset_engine(>i915->guc, engine);
+ ret = intel_guc_reset_engine(>gt->uc.guc, engine);
if (ret) {
/* If we fail here, we expect to fallback to a global reset */
DRM_DEBUG_DRIVER("%sFailed to reset %s, ret=%d\n",
-engine->i915->guc.execbuf_client ? "GuC " : "",
+engine->gt->uc.guc.execbuf_client ? "GuC " :
"",
engine->name, ret);
goto out;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index f015f7dee453..23906228b9b4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -509,7 +509,7 @@ static void guc_submit(struct intel_engine_cs *engine,
struct i915_request **out,
struct i915_request **end)
{
- struct intel_guc *guc = >i915->guc;
+ struct intel_guc *guc = >gt->uc.guc;
struct intel_guc_client *client = guc->execbuf_client;
spin_lock(>wq_lock);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 2a41ee89a16d..581c9c3d4fc0 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -47,7 +47,7 @@ void intel_huc_init_early(struct intel_huc *huc)
static int intel_huc_rsa_data_create(struct intel_huc *huc)
{
struct drm_i915_private *i915 = huc_to_i915(huc);
- struct intel_guc *guc = >guc;
+ struct intel_guc *guc = >gt.uc.guc;
struct i915_vma *vma;
void *vaddr;
@@ -113,7 +113,7 @@ void intel_huc_fini(struct intel_huc *huc)
int intel_huc_auth(struct intel_huc *huc)
{
struct drm_i915_private *i915 = huc_to_i915(huc);
- struct intel_guc *guc = >guc;
+ struct intel_guc *guc = >gt.uc.guc;
int ret;
if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 6193b87855e0..e2080da2e1e4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -54,8 +54,8 @@ static int __intel_uc_reset_hw(struct
[Intel-gfx] [PATCH 09/12] drm/i915/uc: Move intel functions to intel_uc
All the intel_uc_* can now be moved to work on the intel_uc structure
for better encapsulation of uc-related actions.
Note: I've introduced uc_to_gt instead of uc_to_i915 because the aim is
to move everything to be gt-focused in the medium term, so we would've
had to replace it soon anyway.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 6 +-
drivers/gpu/drm/i915/gt/intel_gt.h | 5 +
drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 184 -
drivers/gpu/drm/i915/gt/uc/intel_uc.h | 34 ++---
drivers/gpu/drm/i915/i915_drv.c| 14 +-
drivers/gpu/drm/i915/i915_drv.h| 6 +-
drivers/gpu/drm/i915/i915_gem.c| 18 +--
8 files changed, 137 insertions(+), 132 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
index 4d774376f5b8..3c674c952a78 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
@@ -173,7 +173,7 @@ void i915_gem_suspend(struct drm_i915_private *i915)
i915_gem_drain_freed_objects(i915);
- intel_uc_suspend(i915);
+ intel_uc_suspend(>gt.uc);
}
static struct drm_i915_gem_object *first_mm_object(struct list_head *list)
@@ -238,7 +238,7 @@ void i915_gem_suspend_late(struct drm_i915_private *i915)
}
spin_unlock_irqrestore(>mm.obj_lock, flags);
- intel_uc_sanitize(i915);
+ intel_uc_sanitize(>gt.uc);
i915_gem_sanitize(i915);
}
@@ -265,7 +265,7 @@ void i915_gem_resume(struct drm_i915_private *i915)
if (intel_gt_resume(>gt))
goto err_wedged;
- intel_uc_resume(i915);
+ intel_uc_resume(>gt.uc);
/* Always reload a context for powersaving. */
if (!i915_gem_load_power_context(i915))
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
b/drivers/gpu/drm/i915/gt/intel_gt.h
index 1093dcf36f63..880be05a3f4a 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -11,6 +11,11 @@
struct drm_i915_private;
+static inline struct intel_gt *uc_to_gt(struct intel_uc *uc)
+{
+ return container_of(uc, struct intel_gt, uc);
+}
+
void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915);
void intel_gt_init_hw(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
b/drivers/gpu/drm/i915/gt/intel_reset.c
index ccedea636ba3..be23f4557111 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -720,7 +720,7 @@ static intel_engine_mask_t reset_prepare(struct
drm_i915_private *i915)
reset_prepare_engine(engine);
}
- intel_uc_reset_prepare(i915);
+ intel_uc_reset_prepare(>gt.uc);
return awake;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index e2080da2e1e4..2062e7ff05e8 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -22,19 +22,22 @@
*
*/
+#include "gt/intel_gt.h"
#include "gt/intel_reset.h"
-#include "intel_uc.h"
#include "intel_guc.h"
#include "intel_guc_ads.h"
#include "intel_guc_submission.h"
+#include "intel_uc.h"
+
#include "i915_drv.h"
static void guc_free_load_err_log(struct intel_guc *guc);
/* Reset GuC providing us with fresh state for both GuC and HuC.
*/
-static int __intel_uc_reset_hw(struct drm_i915_private *dev_priv)
+static int __intel_uc_reset_hw(struct intel_uc *uc)
{
+ struct drm_i915_private *dev_priv = uc_to_gt(uc)->i915;
int ret;
u32 guc_status;
@@ -52,10 +55,10 @@ static int __intel_uc_reset_hw(struct drm_i915_private
*dev_priv)
return ret;
}
-static int __get_platform_enable_guc(struct drm_i915_private *i915)
+static int __get_platform_enable_guc(struct intel_uc *uc)
{
- struct intel_uc_fw *guc_fw = >gt.uc.guc.fw;
- struct intel_uc_fw *huc_fw = >gt.uc.huc.fw;
+ struct intel_uc_fw *guc_fw = >guc.fw;
+ struct intel_uc_fw *huc_fw = >huc.fw;
int enable_guc = 0;
/* Default is to use HuC if we know GuC and HuC firmwares */
@@ -67,12 +70,11 @@ static int __get_platform_enable_guc(struct
drm_i915_private *i915)
return enable_guc;
}
-static int __get_default_guc_log_level(struct drm_i915_private *i915)
+static int __get_default_guc_log_level(struct intel_uc *uc)
{
int guc_log_level;
- if (!intel_uc_fw_supported(>gt.uc.guc.fw) ||
- !intel_uc_is_using_guc(i915))
+ if (!intel_uc_fw_supported(>guc.fw) || !intel_uc_is_using_guc(uc))
guc_log_level = GUC_LOG_LEVEL_DISABLED;
else if (IS_ENABLED(CONFIG_DRM_I915_DEBUG) ||
IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
@@ -87,7 +89,7 @@ static int __get_default_guc_log_level(struct
drm_i915_private *i915)
/**
* sanitize_options_early - sanitize
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2] drm/i915/display/tgl: Bump up the mode vertical limits to support 8K (rev2)
== Series Details ==
Series: series starting with [v2] drm/i915/display/tgl: Bump up the mode
vertical limits to support 8K (rev2)
URL : https://patchwork.freedesktop.org/series/63458/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6446 -> Patchwork_13593
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13593/
Known issues
Here are the changes found in Patchwork_13593 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_flink_basic@bad-open:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/fi-icl-u3/igt@gem_flink_ba...@bad-open.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13593/fi-icl-u3/igt@gem_flink_ba...@bad-open.html
* igt@prime_self_import@basic-with_one_bo:
- fi-icl-dsi: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/fi-icl-dsi/igt@prime_self_import@basic-with_one_bo.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13593/fi-icl-dsi/igt@prime_self_import@basic-with_one_bo.html
Possible fixes
* {igt@gem_ctx_switch@legacy-render}:
- fi-cml-u: [INCOMPLETE][5] ([fdo#110566]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/fi-cml-u/igt@gem_ctx_swi...@legacy-render.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13593/fi-cml-u/igt@gem_ctx_swi...@legacy-render.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][7] ([fdo#109485]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13593/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
[fdo#111046 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111046
Participating hosts (51 -> 46)
--
Additional (2): fi-byt-j1900 fi-snb-2600
Missing(7): fi-kbl-soraka fi-byt-squawks fi-bsw-cyan fi-icl-y fi-icl-guc
fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6446 -> Patchwork_13593
CI_DRM_6446: 835fbe24abe47946fc514871f5cbe334d0be9854 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5092: 2a66ae6626d5583240509f84117d1345a799b75a @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13593: a537b92522385cda1cfb1400f1c9d29f11cb3b6b @
git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13593/build_32bit.log
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1287: recipe for target 'modules' failed
make: *** [modules] Error 2
== Linux commits ==
a537b9252238 drm/i915/display/tgl: Bump up the plane/fb height to support 8K
ed957eb65698 drm/i915/display/tgl: Bump up the mode vertical limits to support
8K
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13593/
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Remove unused i915_gem_context_lookup_engine
== Series Details == Series: drm/i915: Remove unused i915_gem_context_lookup_engine URL : https://patchwork.freedesktop.org/series/63437/ State : success == Summary == CI Bug Log - changes from CI_DRM_6440_full -> Patchwork_13579_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13579_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@reset-stress: - shard-snb: [PASS][1] -> [FAIL][2] ([fdo#109661]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6440/shard-snb4/igt@gem_...@reset-stress.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13579/shard-snb5/igt@gem_...@reset-stress.html * igt@i915_pm_rpm@drm-resources-equal: - shard-iclb: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713] / [fdo#108840]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6440/shard-iclb1/igt@i915_pm_...@drm-resources-equal.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13579/shard-iclb2/igt@i915_pm_...@drm-resources-equal.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([fdo#108566]) +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6440/shard-apl8/igt@i915_susp...@fence-restore-tiled2untiled.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13579/shard-apl1/igt@i915_susp...@fence-restore-tiled2untiled.html * igt@i915_suspend@sysfs-reader: - shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([fdo#108566]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6440/shard-kbl2/igt@i915_susp...@sysfs-reader.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13579/shard-kbl4/igt@i915_susp...@sysfs-reader.html * igt@kms_fbcon_fbt@fbc-suspend: - shard-skl: [PASS][9] -> [INCOMPLETE][10] ([fdo#104108]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6440/shard-skl7/igt@kms_fbcon_...@fbc-suspend.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13579/shard-skl9/igt@kms_fbcon_...@fbc-suspend.html * igt@kms_flip@flip-vs-expired-vblank: - shard-glk: [PASS][11] -> [FAIL][12] ([fdo#105363]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6440/shard-glk8/igt@kms_f...@flip-vs-expired-vblank.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13579/shard-glk3/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#105363]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6440/shard-skl4/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13579/shard-skl4/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-skl: [PASS][15] -> [INCOMPLETE][16] ([fdo#109507]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6440/shard-skl8/igt@kms_f...@flip-vs-suspend-interruptible.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13579/shard-skl5/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite: - shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103167]) +4 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6440/shard-iclb3/igt@kms_frontbuffer_track...@fbc-rgb565-draw-pwrite.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13579/shard-iclb8/igt@kms_frontbuffer_track...@fbc-rgb565-draw-pwrite.html * igt@kms_psr@psr2_sprite_plane_move: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6440/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13579/shard-iclb3/igt@kms_psr@psr2_sprite_plane_move.html Possible fixes * igt@gem_exec_nop@basic-series: - shard-iclb: [INCOMPLETE][21] ([fdo#107713] / [fdo#109100]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6440/shard-iclb1/igt@gem_exec_...@basic-series.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13579/shard-iclb7/igt@gem_exec_...@basic-series.html * igt@gem_workarounds@suspend-resume-fd: - shard-skl: [INCOMPLETE][23] ([fdo#104108]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6440/shard-skl1/igt@gem_workarou...@suspend-resume-fd.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13579/shard-skl2/igt@gem_workarou...@suspend-resume-fd.html * igt@i915_suspend@fence-restore-untiled: - shard-kbl: [DMESG-WARN][25] ([fdo#108566]) -> [PASS][26] [25]:
[Intel-gfx] [PATCH v2] drm/i915/display/tgl: Bump up the mode vertical limits to support 8K
On TGL+ we support 8K display resolution, hence bump up the vertical
active limits to 4320 in intel_mode_valid()
v2:
* Checkpatch warning (Manasi)
Cc: Maarten Lankhorst
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_display.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index f07081815b80..cfceb27e4b9e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15764,8 +15764,13 @@ intel_mode_valid(struct drm_device *dev,
DRM_MODE_FLAG_CLKDIV2))
return MODE_BAD;
- if (INTEL_GEN(dev_priv) >= 9 ||
- IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
+ if (INTEL_GEN(dev_priv) >= 12) {
+ hdisplay_max = 8192;
+ vdisplay_max = 4320;
+ htotal_max = 8192;
+ vtotal_max = 8192;
+ } else if (INTEL_GEN(dev_priv) >= 9 ||
+ IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
vdisplay_max = 4096;
htotal_max = 8192;
--
2.19.1
___
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Re: [Intel-gfx] [PATCH 2/2] drm/i915/display/tgl: Bump up the plane/fb height to support 8K
On Tue, 2019-07-09 at 14:47 -0700, Manasi Navare wrote:
> On TGL+, the plane height for 8K planes can be 4320, so bump it up
> To support 4320, we need to increase the number of bits used to
> read plane_height to 13 as opposed to older 12 bits.
>
> Cc: Maarten Lankhorst
> Cc: Ville Syrjälä
> Signed-off-by: Manasi Navare
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 21
> ++--
> 1 file changed, 19 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 0d5c8af01f54..be9a54cb5ecc 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3343,6 +3343,16 @@ static int icl_max_plane_width(const struct
> drm_framebuffer *fb,
> return 5120;
> }
>
> +static int skl_max_plane_height(void)
> +{
> + return 4096;
> +}
> +
> +static int tgl_max_plane_height(void)
> +{
> + return 4320;
> +}
> +
> static bool skl_check_main_ccs_coordinates(struct intel_plane_state
> *plane_state,
> int main_x, int main_y, u32
> main_offset)
> {
> @@ -3391,9 +3401,13 @@ static int skl_check_main_surface(struct
> intel_plane_state *plane_state)
> int w = drm_rect_width(_state->base.src) >> 16;
> int h = drm_rect_height(_state->base.src) >> 16;
> int max_width;
> - int max_height = 4096;
> + int max_height;
> u32 alignment, offset, aux_offset = plane_state-
> >color_plane[1].offset;
>
> + if (INTEL_GEN(dev_priv) >= 12)
> + max_height = tgl_max_plane_height();
> + else
> + max_height = skl_max_plane_height();
Give a line between max_width block, also I would move the height after
the width.
> if (INTEL_GEN(dev_priv) >= 11)
> max_width = icl_max_plane_width(fb, 0, rotation);
> else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> @@ -9865,7 +9879,10 @@ skylake_get_initial_plane_config(struct
> intel_crtc *crtc,
> offset = I915_READ(PLANE_OFFSET(pipe, plane_id));
>
> val = I915_READ(PLANE_SIZE(pipe, plane_id));
> - fb->height = ((val >> 16) & 0xfff) + 1;
> + if (INTEL_GEN(dev_priv) >= 12)
> + fb->height = ((val >> 16) & 0x1fff) + 1;
> + else
> + fb->height = ((val >> 16) & 0xfff) + 1;
> fb->width = ((val >> 0) & 0x1fff) + 1;
>
> val = I915_READ(PLANE_STRIDE(pipe, plane_id));
___
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Re: [Intel-gfx] [PATCH 1/2] drm/i915/display/tgl: Bump up the mode vertical limits to support 8K
On Tue, 2019-07-09 at 14:47 -0700, Manasi Navare wrote:
> On TGL+ we support 8K display resolution, hence bump up the vertical
> active limits to 4320 in intel_mode_valid()
>
> Cc: Maarten Lankhorst
> Cc: Ville Syrjälä
> Signed-off-by: Manasi Navare
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 9 +++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index f07081815b80..0d5c8af01f54 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -15764,8 +15764,13 @@ intel_mode_valid(struct drm_device *dev,
> DRM_MODE_FLAG_CLKDIV2))
> return MODE_BAD;
>
> - if (INTEL_GEN(dev_priv) >= 9 ||
> - IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
> + if (INTEL_GEN(dev_priv) >=12) {
if (INTEL_GEN(dev_priv) >= 12) {
> + hdisplay_max = 8192;
> + vdisplay_max = 4320;
> + htotal_max = 8192;
> + vtotal_max = 8192;
> + } else if (INTEL_GEN(dev_priv) >= 9 ||
> +IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
> hdisplay_max = 8192; /* FDI max 4096 handled elsewhere
> */
> vdisplay_max = 4096;
> htotal_max = 8192;
___
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[Intel-gfx] ✗ Fi.CI.BAT: failure for Panel rotation patches (rev6)
== Series Details == Series: Panel rotation patches (rev6) URL : https://patchwork.freedesktop.org/series/61870/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h AR drivers/gpu/drm/i915/built-in.a CC [M] drivers/gpu/drm/i915/header_test_i915_active_types.o CC [M] drivers/gpu/drm/i915/header_test_i915_debugfs.o CC [M] drivers/gpu/drm/i915/header_test_i915_drv.o CC [M] drivers/gpu/drm/i915/header_test_i915_fixed.o CC [M] drivers/gpu/drm/i915/header_test_i915_gem_gtt.o CC [M] drivers/gpu/drm/i915/header_test_i915_globals.o CC [M] drivers/gpu/drm/i915/header_test_i915_irq.o CC [M] drivers/gpu/drm/i915/header_test_i915_params.o CC [M] drivers/gpu/drm/i915/header_test_i915_priolist_types.o CC [M] drivers/gpu/drm/i915/header_test_i915_pvinfo.o CC [M] drivers/gpu/drm/i915/header_test_i915_reg.o CC [M] drivers/gpu/drm/i915/header_test_i915_scheduler_types.o CC [M] drivers/gpu/drm/i915/header_test_i915_utils.o CC [M] drivers/gpu/drm/i915/header_test_i915_vgpu.o CC [M] drivers/gpu/drm/i915/header_test_intel_csr.o CC [M] drivers/gpu/drm/i915/header_test_intel_drv.o CC [M] drivers/gpu/drm/i915/header_test_intel_guc_ct.o CC [M] drivers/gpu/drm/i915/header_test_intel_guc_fwif.o CC [M] drivers/gpu/drm/i915/header_test_intel_guc_reg.o CC [M] drivers/gpu/drm/i915/header_test_intel_gvt.o CC [M] drivers/gpu/drm/i915/header_test_intel_pm.o CC [M] drivers/gpu/drm/i915/header_test_intel_runtime_pm.o CC [M] drivers/gpu/drm/i915/header_test_intel_sideband.o CC [M] drivers/gpu/drm/i915/header_test_intel_uc_fw.o CC [M] drivers/gpu/drm/i915/header_test_intel_uncore.o CC [M] drivers/gpu/drm/i915/header_test_intel_wakeref.o CC [M] drivers/gpu/drm/i915/display/icl_dsi.o drivers/gpu/drm/i915/display/icl_dsi.c: In function ‘icl_dsi_add_properties’: drivers/gpu/drm/i915/display/icl_dsi.c:1526:2: error: too many arguments to function ‘drm_connector_init_panel_orientation_property’ drm_connector_init_panel_orientation_property(>base, ^ In file included from ./include/drm/drm_modes.h:33:0, from ./include/drm/drm_crtc.h:40, from ./include/drm/drm_atomic_helper.h:31, from drivers/gpu/drm/i915/display/icl_dsi.c:28: ./include/drm/drm_connector.h:1517:5: note: declared here int drm_connector_init_panel_orientation_property( ^ scripts/Makefile.build:278: recipe for target 'drivers/gpu/drm/i915/display/icl_dsi.o' failed make[4]: *** [drivers/gpu/drm/i915/display/icl_dsi.o] Error 1 scripts/Makefile.build:489: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:489: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:489: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1071: recipe for target 'drivers' failed make: *** [drivers] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 2/4] drm/panel: set display info in panel attach
Devicetree systems can set panel orientation via a panel binding, but
there's no way, as is, to propagate this setting to the connector,
where the property need to be added.
To address this, this patch sets orientation, as well as other fixed
values for the panel, in the drm_panel_attach function. These values
are stored from probe in the drm_panel struct.
Signed-off-by: Derek Basehore
---
drivers/gpu/drm/drm_panel.c | 28
include/drm/drm_panel.h | 14 ++
2 files changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/drm_panel.c b/drivers/gpu/drm/drm_panel.c
index 169bab54d52d..ca01095470a9 100644
--- a/drivers/gpu/drm/drm_panel.c
+++ b/drivers/gpu/drm/drm_panel.c
@@ -104,11 +104,23 @@ EXPORT_SYMBOL(drm_panel_remove);
*/
int drm_panel_attach(struct drm_panel *panel, struct drm_connector *connector)
{
+ struct drm_display_info *info;
+
if (panel->connector)
return -EBUSY;
panel->connector = connector;
panel->drm = connector->dev;
+ info = >display_info;
+ info->width_mm = panel->width_mm;
+ info->height_mm = panel->height_mm;
+ info->bpc = panel->bpc;
+ info->panel_orientation = panel->orientation;
+ info->bus_flags = panel->bus_flags;
+ if (panel->bus_formats)
+ drm_display_info_set_bus_formats(>display_info,
+panel->bus_formats,
+panel->num_bus_formats);
return 0;
}
@@ -128,6 +140,22 @@ EXPORT_SYMBOL(drm_panel_attach);
*/
int drm_panel_detach(struct drm_panel *panel)
{
+ struct drm_display_info *info;
+
+ if (!panel->connector)
+ goto out;
+
+ info = >connector->display_info;
+ info->width_mm = 0;
+ info->height_mm = 0;
+ info->bpc = 0;
+ info->panel_orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
+ info->bus_flags = 0;
+ kfree(info->bus_formats);
+ info->bus_formats = NULL;
+ info->num_bus_formats = 0;
+
+out:
panel->connector = NULL;
panel->drm = NULL;
diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h
index a18c59f136ab..1760c11e0298 100644
--- a/include/drm/drm_panel.h
+++ b/include/drm/drm_panel.h
@@ -39,6 +39,8 @@ enum drm_panel_orientation;
* struct drm_panel_funcs - perform operations on a given panel
* @disable: disable panel (turn off back light, etc.)
* @unprepare: turn off panel
+ * @detach: detach panel->connector (clear internal state, etc.)
+ * @attach: attach panel->connector (update internal state, etc.)
* @prepare: turn on panel and perform set up
* @enable: enable panel (turn on back light, etc.)
* @get_modes: add modes to the connector that the panel is attached to and
@@ -95,6 +97,18 @@ struct drm_panel {
const struct drm_panel_funcs *funcs;
+ /*
+* panel information to be set in the connector when the panel is
+* attached.
+*/
+ unsigned int width_mm;
+ unsigned int height_mm;
+ unsigned int bpc;
+ int orientation;
+ const u32 *bus_formats;
+ unsigned int num_bus_formats;
+ u32 bus_flags;
+
struct list_head list;
};
--
2.22.0.410.gd8fdbe21b5-goog
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 0/4] Panel rotation patches
This adds the plumbing for reading panel rotation from the devicetree and sets up adding a panel property for the panel orientation on Mediatek SoCs when a rotation is present. v6 changes: -added enum declaration to drm_panel.h header v5 changes: -rebased v4 changes: -fixed some changes made to the i915 driver -clarified comments on of orientation helper v3 changes: -changed from attach/detach callbacks to directly setting fixed panel values in drm_panel_attach -removed update to Documentation -added separate function for quirked panel orientation property init v2 changes: fixed build errors in i915 Derek Basehore (4): drm/panel: Add helper for reading DT rotation drm/panel: set display info in panel attach drm/connector: Split out orientation quirk detection drm/mtk: add panel orientation property drivers/gpu/drm/drm_connector.c| 45 ++- drivers/gpu/drm/drm_panel.c| 70 ++ drivers/gpu/drm/i915/intel_dp.c| 4 +- drivers/gpu/drm/i915/vlv_dsi.c | 5 +-- drivers/gpu/drm/mediatek/mtk_dsi.c | 8 include/drm/drm_connector.h| 2 + include/drm/drm_panel.h| 21 + 7 files changed, 138 insertions(+), 17 deletions(-) -- 2.22.0.410.gd8fdbe21b5-goog ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 4/4] drm/mtk: add panel orientation property
This inits the panel orientation property for the mediatek dsi driver
if the panel orientation (connector.display_info.panel_orientation) is
not DRM_MODE_PANEL_ORIENTATION_UNKNOWN.
Signed-off-by: Derek Basehore
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index b91c4616644a..2920458ae2fb 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -790,10 +790,18 @@ static int mtk_dsi_create_connector(struct drm_device
*drm, struct mtk_dsi *dsi)
DRM_ERROR("Failed to attach panel to drm\n");
goto err_connector_cleanup;
}
+
+ ret = drm_connector_init_panel_orientation_property(>conn);
+ if (ret) {
+ DRM_ERROR("Failed to init panel orientation\n");
+ goto err_panel_detach;
+ }
}
return 0;
+err_panel_detach:
+ drm_panel_detach(dsi->panel);
err_connector_cleanup:
drm_connector_cleanup(>conn);
return ret;
--
2.22.0.410.gd8fdbe21b5-goog
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[Intel-gfx] [PATCH v6 1/4] drm/panel: Add helper for reading DT rotation
This adds a helper function for reading the rotation (panel
orientation) from the device tree.
Signed-off-by: Derek Basehore
---
drivers/gpu/drm/drm_panel.c | 43 +
include/drm/drm_panel.h | 9
2 files changed, 52 insertions(+)
diff --git a/drivers/gpu/drm/drm_panel.c b/drivers/gpu/drm/drm_panel.c
index dbd5b873e8f2..169bab54d52d 100644
--- a/drivers/gpu/drm/drm_panel.c
+++ b/drivers/gpu/drm/drm_panel.c
@@ -172,6 +172,49 @@ struct drm_panel *of_drm_find_panel(const struct
device_node *np)
return ERR_PTR(-EPROBE_DEFER);
}
EXPORT_SYMBOL(of_drm_find_panel);
+
+/**
+ * of_drm_get_panel_orientation - look up the orientation of the panel through
+ * the "rotation" binding from a device tree node
+ * @np: device tree node of the panel
+ * @orientation: orientation enum to be filled in
+ *
+ * Looks up the rotation of a panel in the device tree. The orientation of the
+ * panel is expressed as a property name "rotation" in the device tree. The
+ * rotation in the device tree is counter clockwise.
+ *
+ * Return: 0 when a valid rotation value (0, 90, 180, or 270) is read or the
+ * rotation property doesn't exist. -EERROR otherwise.
+ */
+int of_drm_get_panel_orientation(const struct device_node *np,
+enum drm_panel_orientation *orientation)
+{
+ int rotation, ret;
+
+ ret = of_property_read_u32(np, "rotation", );
+ if (ret == -EINVAL) {
+ /* Don't return an error if there's no rotation property. */
+ *orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
+ return 0;
+ }
+
+ if (ret < 0)
+ return ret;
+
+ if (rotation == 0)
+ *orientation = DRM_MODE_PANEL_ORIENTATION_NORMAL;
+ else if (rotation == 90)
+ *orientation = DRM_MODE_PANEL_ORIENTATION_RIGHT_UP;
+ else if (rotation == 180)
+ *orientation = DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP;
+ else if (rotation == 270)
+ *orientation = DRM_MODE_PANEL_ORIENTATION_LEFT_UP;
+ else
+ return -EINVAL;
+
+ return 0;
+}
+EXPORT_SYMBOL(of_drm_get_panel_orientation);
#endif
MODULE_AUTHOR("Thierry Reding ");
diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h
index 8c738c0e6e9f..a18c59f136ab 100644
--- a/include/drm/drm_panel.h
+++ b/include/drm/drm_panel.h
@@ -33,6 +33,8 @@ struct drm_device;
struct drm_panel;
struct display_timing;
+enum drm_panel_orientation;
+
/**
* struct drm_panel_funcs - perform operations on a given panel
* @disable: disable panel (turn off back light, etc.)
@@ -197,11 +199,18 @@ int drm_panel_detach(struct drm_panel *panel);
#if defined(CONFIG_OF) && defined(CONFIG_DRM_PANEL)
struct drm_panel *of_drm_find_panel(const struct device_node *np);
+int of_drm_get_panel_orientation(const struct device_node *np,
+enum drm_panel_orientation *orientation);
#else
static inline struct drm_panel *of_drm_find_panel(const struct device_node *np)
{
return ERR_PTR(-ENODEV);
}
+int of_drm_get_panel_orientation(const struct device_node *np,
+enum drm_panel_orientation *orientation)
+{
+ return -ENODEV;
+}
#endif
#endif
--
2.22.0.410.gd8fdbe21b5-goog
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[Intel-gfx] [PATCH v6 3/4] drm/connector: Split out orientation quirk detection
Not every platform needs quirk detection for panel orientation, so
split the drm_connector_init_panel_orientation_property into two
functions. One for platforms without the need for quirks, and the
other for platforms that need quirks.
Signed-off-by: Derek Basehore
---
drivers/gpu/drm/drm_connector.c | 45 ++---
drivers/gpu/drm/i915/display/intel_dp.c | 4 +--
drivers/gpu/drm/i915/display/vlv_dsi.c | 2 +-
include/drm/drm_connector.h | 2 ++
4 files changed, 38 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index b3f2cf7eae9c..52777d647494 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -1892,31 +1892,23 @@ EXPORT_SYMBOL(drm_connector_set_vrr_capable_property);
* drm_connector_init_panel_orientation_property -
* initialize the connecters panel_orientation property
* @connector: connector for which to init the panel-orientation property.
- * @width: width in pixels of the panel, used for panel quirk detection
- * @height: height in pixels of the panel, used for panel quirk detection
*
* This function should only be called for built-in panels, after setting
* connector->display_info.panel_orientation first (if known).
*
- * This function will check for platform specific (e.g. DMI based) quirks
- * overriding display_info.panel_orientation first, then if panel_orientation
- * is not DRM_MODE_PANEL_ORIENTATION_UNKNOWN it will attach the
- * "panel orientation" property to the connector.
+ * This function will check if the panel_orientation is not
+ * DRM_MODE_PANEL_ORIENTATION_UNKNOWN. If not, it will attach the "panel
+ * orientation" property to the connector.
*
* Returns:
* Zero on success, negative errno on failure.
*/
int drm_connector_init_panel_orientation_property(
- struct drm_connector *connector, int width, int height)
+ struct drm_connector *connector)
{
struct drm_device *dev = connector->dev;
struct drm_display_info *info = >display_info;
struct drm_property *prop;
- int orientation_quirk;
-
- orientation_quirk = drm_get_panel_orientation_quirk(width, height);
- if (orientation_quirk != DRM_MODE_PANEL_ORIENTATION_UNKNOWN)
- info->panel_orientation = orientation_quirk;
if (info->panel_orientation == DRM_MODE_PANEL_ORIENTATION_UNKNOWN)
return 0;
@@ -1939,6 +1931,35 @@ int drm_connector_init_panel_orientation_property(
}
EXPORT_SYMBOL(drm_connector_init_panel_orientation_property);
+/**
+ * drm_connector_init_panel_orientation_property_quirk -
+ * initialize the connecters panel_orientation property with a quirk
+ * override
+ * @connector: connector for which to init the panel-orientation property.
+ * @width: width in pixels of the panel, used for panel quirk detection
+ * @height: height in pixels of the panel, used for panel quirk detection
+ *
+ * This function will check for platform specific (e.g. DMI based) quirks
+ * overriding display_info.panel_orientation first, then if panel_orientation
+ * is not DRM_MODE_PANEL_ORIENTATION_UNKNOWN it will attach the
+ * "panel orientation" property to the connector.
+ *
+ * Returns:
+ * Zero on success, negative errno on failure.
+ */
+int drm_connector_init_panel_orientation_property_quirk(
+ struct drm_connector *connector, int width, int height)
+{
+ int orientation_quirk;
+
+ orientation_quirk = drm_get_panel_orientation_quirk(width, height);
+ if (orientation_quirk != DRM_MODE_PANEL_ORIENTATION_UNKNOWN)
+ connector->display_info.panel_orientation = orientation_quirk;
+
+ return drm_connector_init_panel_orientation_property(connector);
+}
+EXPORT_SYMBOL(drm_connector_init_panel_orientation_property_quirk);
+
int drm_connector_set_obj_prop(struct drm_mode_object *obj,
struct drm_property *property,
uint64_t value)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 8f7188d71d08..45b637419085 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -7068,8 +7068,8 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
intel_panel_setup_backlight(connector, pipe);
if (fixed_mode)
- drm_connector_init_panel_orientation_property(
- connector, fixed_mode->hdisplay, fixed_mode->vdisplay);
+ drm_connector_init_panel_orientation_property_quirk(connector,
+ fixed_mode->hdisplay, fixed_mode->vdisplay);
return true;
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c
b/drivers/gpu/drm/i915/display/vlv_dsi.c
index e272d826210a..dd7fa806f95c 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -1662,7
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/display/tgl: Bump up the mode vertical limits to support 8K
== Series Details ==
Series: series starting with [1/2] drm/i915/display/tgl: Bump up the mode
vertical limits to support 8K
URL : https://patchwork.freedesktop.org/series/63458/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6446 -> Patchwork_13591
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13591/
Known issues
Here are the changes found in Patchwork_13591 that come from known issues:
### IGT changes ###
Possible fixes
* {igt@gem_ctx_switch@legacy-render}:
- fi-cml-u: [INCOMPLETE][1] ([fdo#110566]) -> [PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/fi-cml-u/igt@gem_ctx_swi...@legacy-render.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13591/fi-cml-u/igt@gem_ctx_swi...@legacy-render.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111046 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111046
Participating hosts (51 -> 46)
--
Additional (2): fi-byt-j1900 fi-snb-2600
Missing(7): fi-kbl-soraka fi-hsw-4770r fi-byt-squawks fi-bsw-cyan
fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6446 -> Patchwork_13591
CI_DRM_6446: 835fbe24abe47946fc514871f5cbe334d0be9854 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5092: 2a66ae6626d5583240509f84117d1345a799b75a @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13591: dc819529058c1e30cee0b2f6928c72ae2df15cde @
git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13591/build_32bit.log
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1287: recipe for target 'modules' failed
make: *** [modules] Error 2
== Linux commits ==
dc819529058c drm/i915/display/tgl: Bump up the plane/fb height to support 8K
90e13413f8fd drm/i915/display/tgl: Bump up the mode vertical limits to support
8K
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13591/
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[Intel-gfx] ✓ Fi.CI.BAT: success for MCR fixes
== Series Details ==
Series: MCR fixes
URL : https://patchwork.freedesktop.org/series/63457/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6446 -> Patchwork_13590
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13590/
Known issues
Here are the changes found in Patchwork_13590 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: [PASS][1] -> [FAIL][2] ([fdo#108511])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/fi-skl-6770hq/igt@i915_pm_...@module-reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13590/fi-skl-6770hq/igt@i915_pm_...@module-reload.html
* igt@prime_vgem@basic-fence-flip:
- fi-ilk-650: [PASS][3] -> [DMESG-WARN][4] ([fdo#106387])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/fi-ilk-650/igt@prime_v...@basic-fence-flip.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13590/fi-ilk-650/igt@prime_v...@basic-fence-flip.html
Possible fixes
* {igt@gem_ctx_switch@legacy-render}:
- fi-cml-u: [INCOMPLETE][5] ([fdo#110566]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/fi-cml-u/igt@gem_ctx_swi...@legacy-render.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13590/fi-cml-u/igt@gem_ctx_swi...@legacy-render.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][7] ([fdo#109485]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13590/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=106387
[fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
Participating hosts (51 -> 45)
--
Additional (2): fi-byt-j1900 fi-snb-2600
Missing(8): fi-kbl-soraka fi-byt-squawks fi-bsw-cyan fi-pnv-d510
fi-elk-e7500 fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6446 -> Patchwork_13590
CI_DRM_6446: 835fbe24abe47946fc514871f5cbe334d0be9854 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5092: 2a66ae6626d5583240509f84117d1345a799b75a @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13590: 1cbd435fa30d7cf590c0e6260359be85dcd3f139 @
git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13590/build_32bit.log
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1287: recipe for target 'modules' failed
make: *** [modules] Error 2
== Linux commits ==
1cbd435fa30d drm/i915/icl: Verify engine workarounds in GEN8_L3SQCREG4
700a2f938ef9 drm/i915: Move intel_calculate_mcr_s_ss_select to intel_sseu.c
4e1ae32681f0 drm/i915: Fix WaProgramMgsrForL3BankSpecificMmioReads
e757434337b0 drm/i915: Fix GEN8_MCR_SELECTOR programming
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13590/
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/display/tgl: Bump up the mode vertical limits to support 8K
== Series Details ==
Series: series starting with [1/2] drm/i915/display/tgl: Bump up the mode
vertical limits to support 8K
URL : https://patchwork.freedesktop.org/series/63458/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
90e13413f8fd drm/i915/display/tgl: Bump up the mode vertical limits to support
8K
-:27: ERROR:SPACING: spaces required around that '>=' (ctx:WxV)
#27: FILE: drivers/gpu/drm/i915/display/intel_display.c:15767:
+ if (INTEL_GEN(dev_priv) >=12) {
^
total: 1 errors, 0 warnings, 0 checks, 15 lines checked
dc819529058c drm/i915/display/tgl: Bump up the plane/fb height to support 8K
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[Intel-gfx] [PATCH 1/2] drm/i915/display/tgl: Bump up the mode vertical limits to support 8K
On TGL+ we support 8K display resolution, hence bump up the vertical
active limits to 4320 in intel_mode_valid()
Cc: Maarten Lankhorst
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_display.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index f07081815b80..0d5c8af01f54 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15764,8 +15764,13 @@ intel_mode_valid(struct drm_device *dev,
DRM_MODE_FLAG_CLKDIV2))
return MODE_BAD;
- if (INTEL_GEN(dev_priv) >= 9 ||
- IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
+ if (INTEL_GEN(dev_priv) >=12) {
+ hdisplay_max = 8192;
+ vdisplay_max = 4320;
+ htotal_max = 8192;
+ vtotal_max = 8192;
+ } else if (INTEL_GEN(dev_priv) >= 9 ||
+ IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
vdisplay_max = 4096;
htotal_max = 8192;
--
2.19.1
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[Intel-gfx] [PATCH 2/2] drm/i915/display/tgl: Bump up the plane/fb height to support 8K
On TGL+, the plane height for 8K planes can be 4320, so bump it up
To support 4320, we need to increase the number of bits used to
read plane_height to 13 as opposed to older 12 bits.
Cc: Maarten Lankhorst
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_display.c | 21 ++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 0d5c8af01f54..be9a54cb5ecc 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3343,6 +3343,16 @@ static int icl_max_plane_width(const struct
drm_framebuffer *fb,
return 5120;
}
+static int skl_max_plane_height(void)
+{
+ return 4096;
+}
+
+static int tgl_max_plane_height(void)
+{
+ return 4320;
+}
+
static bool skl_check_main_ccs_coordinates(struct intel_plane_state
*plane_state,
int main_x, int main_y, u32
main_offset)
{
@@ -3391,9 +3401,13 @@ static int skl_check_main_surface(struct
intel_plane_state *plane_state)
int w = drm_rect_width(_state->base.src) >> 16;
int h = drm_rect_height(_state->base.src) >> 16;
int max_width;
- int max_height = 4096;
+ int max_height;
u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset;
+ if (INTEL_GEN(dev_priv) >= 12)
+ max_height = tgl_max_plane_height();
+ else
+ max_height = skl_max_plane_height();
if (INTEL_GEN(dev_priv) >= 11)
max_width = icl_max_plane_width(fb, 0, rotation);
else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
@@ -9865,7 +9879,10 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
offset = I915_READ(PLANE_OFFSET(pipe, plane_id));
val = I915_READ(PLANE_SIZE(pipe, plane_id));
- fb->height = ((val >> 16) & 0xfff) + 1;
+ if (INTEL_GEN(dev_priv) >= 12)
+ fb->height = ((val >> 16) & 0x1fff) + 1;
+ else
+ fb->height = ((val >> 16) & 0xfff) + 1;
fb->width = ((val >> 0) & 0x1fff) + 1;
val = I915_READ(PLANE_STRIDE(pipe, plane_id));
--
2.19.1
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Re: [Intel-gfx] [PATCH 4/4] drm/i915/icl: Verify engine workarounds in GEN8_L3SQCREG4
Quoting Tvrtko Ursulin (2019-07-09 22:06:20) > From: Tvrtko Ursulin > > Having fixed the incorect MCR programming in an earlier patch, we can now > stop ignoring read back of GEN8_L3SQCREG4 during engine workaround > verification. > > Signed-off-by: Tvrtko Ursulin Our testing is useful for something, too bad I didn't believe it. Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/4] drm/i915: Move intel_calculate_mcr_s_ss_select to intel_sseu.c
Quoting Tvrtko Ursulin (2019-07-09 22:06:19) > From: Tvrtko Ursulin > > It is a more appropriate home for it. > > Signed-off-by: Tvrtko Ursulin > Suggested-by: Chris Wilson Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/4] drm/i915: Fix WaProgramMgsrForL3BankSpecificMmioReads
Quoting Tvrtko Ursulin (2019-07-09 22:06:18)
> From: Tvrtko Ursulin
>
> Two issues in this code:
>
> 1.
> fls() usage is incorrect causing off by one in subslice mask lookup,
> which in other words means subslice mask of all zeroes is always used
> (subslice mask of a slice which is not present, or even out of bounds
> array access), rendering the checks in wa_init_mcr either futile or
> random.
>
> 2.
> Condition in WARN_ON is not correct. It is doing a bitwise and operation
> between a positive (present subslices) and negative mask (disabled L3
> banks).
>
> This means that with corrected fls() usage the assert would always
> incorrectly fail.
>
> We can fix this by invereting the fuse bits in the check.
s/invereting/inverting/
> Signed-off-by: Tvrtko Ursulin
> Fixes: fe864b76c2ab ("drm/i915: Implement
> WaProgramMgsrForL3BankSpecificMmioReads")
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 26 ++---
> 1 file changed, 13 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 9e069286d3ce..b5f19ad48d22 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -776,26 +776,26 @@ wa_init_mcr(struct drm_i915_private *i915, struct
> i915_wa_list *wal)
> * something more complex that requires checking the range of every
> * MMIO read).
> */
> - if (INTEL_GEN(i915) >= 10 &&
> - is_power_of_2(sseu->slice_mask)) {
> + if (INTEL_GEN(i915) >= 10 && is_power_of_2(sseu->slice_mask)) {
> /*
> -* read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
> -* enabled subslice, no need to redirect MCR packet
> +* Read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
> +* enabled subslice, no need to redirect MCR packet.
> */
> - u32 slice = fls(sseu->slice_mask);
> - u32 fuse3 =
> - intel_uncore_read(>uncore, GEN10_MIRROR_FUSE3);
> - u8 ss_mask = sseu->subslice_mask[slice];
> + unsigned int slice = fls(sseu->slice_mask) - 1;
> + u8 ss, en, dis;
>
> - u8 enabled_mask = (ss_mask | ss_mask >>
> - GEN10_L3BANK_PAIR_COUNT) &
> GEN10_L3BANK_MASK;
> - u8 disabled_mask = fuse3 & GEN10_L3BANK_MASK;
> + GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
> + ss = sseu->subslice_mask[slice];
> +
> + en = (ss | ss >> GEN10_L3BANK_PAIR_COUNT) & GEN10_L3BANK_MASK;
> + dis = intel_uncore_read(>uncore, GEN10_MIRROR_FUSE3) &
> + GEN10_L3BANK_MASK;
Ok.
> /*
> * Production silicon should have matched L3Bank and
> -* subslice enabled
> +* subslice enabled.
> */
> - WARN_ON((enabled_mask & disabled_mask) != enabled_mask);
> + WARN_ON((en & ~dis) != en);
That certainly makes more sense. I always feared that was some deep
magic to reflect the underlying HW.
Reviewed-by: Chris Wilson
-Chris
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Re: [Intel-gfx] [PATCH 1/4] drm/i915: Fix GEN8_MCR_SELECTOR programming
Quoting Tvrtko Ursulin (2019-07-09 22:06:17)
> From: Tvrtko Ursulin
>
> fls returns bit positions starting from one for the lsb and the MCR
> register expects zero based (sub)slice addressing.
>
> Incorrent MCR programming can have the effect of directing MMIO reads of
> registers in the 0xb100-0xb3ff range to invalid subslice returning zeroes
> instead of actual content.
>
> Signed-off-by: Tvrtko Ursulin
> Fixes: 1e40d4aea57b ("drm/i915/cnl: Implement
> WaProgramMgsrForCorrectSliceSpecificMmioReads")
Makes sense to me, just from my meagre understanding of arrays
Reviewed-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 9 +++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index bdf279fa3b2e..ee15d1934486 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -975,9 +975,14 @@ const char *i915_cache_level_str(struct drm_i915_private
> *i915, int type)
> u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv)
> {
> const struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
> + unsigned int slice = fls(sseu->slice_mask) - 1;
I'd vote for __fls() here instead of fls() - 1.
> + unsigned int subslice;
> u32 mcr_s_ss_select;
> - u32 slice = fls(sseu->slice_mask);
> - u32 subslice = fls(sseu->subslice_mask[slice]);
> +
> + GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
> + subslice = fls(sseu->subslice_mask[slice]);
> + GEM_BUG_ON(!subslice);
> + subslice--;
And I think we're a bit late on the BUG_ON here (it's shouldn't change
after probing) so could be happily reduced to __fls().
-Chris
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[Intel-gfx] [PATCH 4/4] drm/i915/icl: Verify engine workarounds in GEN8_L3SQCREG4
From: Tvrtko Ursulin
Having fixed the incorect MCR programming in an earlier patch, we can now
stop ignoring read back of GEN8_L3SQCREG4 during engine workaround
verification.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 27 +
1 file changed, 6 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index b5f19ad48d22..0fa43ff7366c 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -176,19 +176,6 @@ wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32
val)
wa_write_masked_or(wal, reg, val, val);
}
-static void
-ignore_wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask, u32 val)
-{
- struct i915_wa wa = {
- .reg = reg,
- .mask = mask,
- .val = val,
- /* Bonkers HW, skip verifying */
- };
-
- _wa_add(wal, );
-}
-
#define WA_SET_BIT_MASKED(addr, mask) \
wa_write_masked_or(wal, (addr), (mask), _MASKED_BIT_ENABLE(mask))
@@ -1234,10 +1221,9 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE);
/* WaPipelineFlushCoherentLines:icl */
- ignore_wa_write_or(wal,
- GEN8_L3SQCREG4,
- GEN8_LQSC_FLUSH_COHERENT_LINES,
- GEN8_LQSC_FLUSH_COHERENT_LINES);
+ wa_write_or(wal,
+ GEN8_L3SQCREG4,
+ GEN8_LQSC_FLUSH_COHERENT_LINES);
/*
* Wa_1405543622:icl
@@ -1264,10 +1250,9 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
* Wa_1405733216:icl
* Formerly known as WaDisableCleanEvicts
*/
- ignore_wa_write_or(wal,
- GEN8_L3SQCREG4,
- GEN11_LQSC_CLEAN_EVICT_DISABLE,
- GEN11_LQSC_CLEAN_EVICT_DISABLE);
+ wa_write_or(wal,
+ GEN8_L3SQCREG4,
+ GEN11_LQSC_CLEAN_EVICT_DISABLE);
/* WaForwardProgressSoftReset:icl */
wa_write_or(wal,
--
2.20.1
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[Intel-gfx] [PATCH 3/4] drm/i915: Move intel_calculate_mcr_s_ss_select to intel_sseu.c
From: Tvrtko Ursulin
It is a more appropriate home for it.
Signed-off-by: Tvrtko Ursulin
Suggested-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 24 ---
drivers/gpu/drm/i915/gt/intel_sseu.c | 24 +++
drivers/gpu/drm/i915/gt/intel_sseu.h | 2 ++
drivers/gpu/drm/i915/i915_drv.h | 2 --
4 files changed, 26 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index ee15d1934486..ee2db060e349 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -972,30 +972,6 @@ const char *i915_cache_level_str(struct drm_i915_private
*i915, int type)
}
}
-u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv)
-{
- const struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
- unsigned int slice = fls(sseu->slice_mask) - 1;
- unsigned int subslice;
- u32 mcr_s_ss_select;
-
- GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
- subslice = fls(sseu->subslice_mask[slice]);
- GEM_BUG_ON(!subslice);
- subslice--;
-
- if (IS_GEN(dev_priv, 10))
- mcr_s_ss_select = GEN8_MCR_SLICE(slice) |
- GEN8_MCR_SUBSLICE(subslice);
- else if (INTEL_GEN(dev_priv) >= 11)
- mcr_s_ss_select = GEN11_MCR_SLICE(slice) |
- GEN11_MCR_SUBSLICE(subslice);
- else
- mcr_s_ss_select = 0;
-
- return mcr_s_ss_select;
-}
-
static u32
read_subslice_reg(struct intel_engine_cs *engine, int slice, int subslice,
i915_reg_t reg)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c
b/drivers/gpu/drm/i915/gt/intel_sseu.c
index a0756f006f5f..c12cc476391f 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -157,3 +157,27 @@ u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
return rpcs;
}
+
+u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *i915)
+{
+ const struct sseu_dev_info *sseu = _INFO(i915)->sseu;
+ unsigned int slice = fls(sseu->slice_mask) - 1;
+ unsigned int subslice;
+ u32 mcr_s_ss_select;
+
+ GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
+ subslice = fls(sseu->subslice_mask[slice]);
+ GEM_BUG_ON(!subslice);
+ subslice--;
+
+ if (IS_GEN(i915, 10))
+ mcr_s_ss_select = GEN8_MCR_SLICE(slice) |
+ GEN8_MCR_SUBSLICE(subslice);
+ else if (INTEL_GEN(i915) >= 11)
+ mcr_s_ss_select = GEN11_MCR_SLICE(slice) |
+ GEN11_MCR_SUBSLICE(subslice);
+ else
+ mcr_s_ss_select = 0;
+
+ return mcr_s_ss_select;
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h
b/drivers/gpu/drm/i915/gt/intel_sseu.h
index b50d0401a4e2..fbd86ed45612 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -72,4 +72,6 @@ intel_sseu_subslices_per_slice(const struct sseu_dev_info
*sseu, u8 slice);
u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
const struct intel_sseu *req_sseu);
+u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *i915);
+
#endif /* __INTEL_SSEU_H__ */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f9878cbef4d9..983a182d280e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2403,8 +2403,6 @@ extern void intel_engine_init_hangcheck(struct
intel_engine_cs *engine);
extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
-u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv);
-
static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
{
unsigned long delay;
--
2.20.1
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[Intel-gfx] [PATCH 1/4] drm/i915: Fix GEN8_MCR_SELECTOR programming
From: Tvrtko Ursulin
fls returns bit positions starting from one for the lsb and the MCR
register expects zero based (sub)slice addressing.
Incorrent MCR programming can have the effect of directing MMIO reads of
registers in the 0xb100-0xb3ff range to invalid subslice returning zeroes
instead of actual content.
Signed-off-by: Tvrtko Ursulin
Fixes: 1e40d4aea57b ("drm/i915/cnl: Implement
WaProgramMgsrForCorrectSliceSpecificMmioReads")
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index bdf279fa3b2e..ee15d1934486 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -975,9 +975,14 @@ const char *i915_cache_level_str(struct drm_i915_private
*i915, int type)
u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv)
{
const struct sseu_dev_info *sseu = _INFO(dev_priv)->sseu;
+ unsigned int slice = fls(sseu->slice_mask) - 1;
+ unsigned int subslice;
u32 mcr_s_ss_select;
- u32 slice = fls(sseu->slice_mask);
- u32 subslice = fls(sseu->subslice_mask[slice]);
+
+ GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
+ subslice = fls(sseu->subslice_mask[slice]);
+ GEM_BUG_ON(!subslice);
+ subslice--;
if (IS_GEN(dev_priv, 10))
mcr_s_ss_select = GEN8_MCR_SLICE(slice) |
--
2.20.1
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[Intel-gfx] [PATCH 2/4] drm/i915: Fix WaProgramMgsrForL3BankSpecificMmioReads
From: Tvrtko Ursulin
Two issues in this code:
1.
fls() usage is incorrect causing off by one in subslice mask lookup,
which in other words means subslice mask of all zeroes is always used
(subslice mask of a slice which is not present, or even out of bounds
array access), rendering the checks in wa_init_mcr either futile or
random.
2.
Condition in WARN_ON is not correct. It is doing a bitwise and operation
between a positive (present subslices) and negative mask (disabled L3
banks).
This means that with corrected fls() usage the assert would always
incorrectly fail.
We can fix this by invereting the fuse bits in the check.
Signed-off-by: Tvrtko Ursulin
Fixes: fe864b76c2ab ("drm/i915: Implement
WaProgramMgsrForL3BankSpecificMmioReads")
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 26 ++---
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 9e069286d3ce..b5f19ad48d22 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -776,26 +776,26 @@ wa_init_mcr(struct drm_i915_private *i915, struct
i915_wa_list *wal)
* something more complex that requires checking the range of every
* MMIO read).
*/
- if (INTEL_GEN(i915) >= 10 &&
- is_power_of_2(sseu->slice_mask)) {
+ if (INTEL_GEN(i915) >= 10 && is_power_of_2(sseu->slice_mask)) {
/*
-* read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
-* enabled subslice, no need to redirect MCR packet
+* Read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
+* enabled subslice, no need to redirect MCR packet.
*/
- u32 slice = fls(sseu->slice_mask);
- u32 fuse3 =
- intel_uncore_read(>uncore, GEN10_MIRROR_FUSE3);
- u8 ss_mask = sseu->subslice_mask[slice];
+ unsigned int slice = fls(sseu->slice_mask) - 1;
+ u8 ss, en, dis;
- u8 enabled_mask = (ss_mask | ss_mask >>
- GEN10_L3BANK_PAIR_COUNT) & GEN10_L3BANK_MASK;
- u8 disabled_mask = fuse3 & GEN10_L3BANK_MASK;
+ GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
+ ss = sseu->subslice_mask[slice];
+
+ en = (ss | ss >> GEN10_L3BANK_PAIR_COUNT) & GEN10_L3BANK_MASK;
+ dis = intel_uncore_read(>uncore, GEN10_MIRROR_FUSE3) &
+ GEN10_L3BANK_MASK;
/*
* Production silicon should have matched L3Bank and
-* subslice enabled
+* subslice enabled.
*/
- WARN_ON((enabled_mask & disabled_mask) != enabled_mask);
+ WARN_ON((en & ~dis) != en);
}
if (INTEL_GEN(i915) >= 11)
--
2.20.1
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[Intel-gfx] [PATCH 0/4] MCR fixes
From: Tvrtko Ursulin A few bugs in programming the MCR register sneaked in past review. First of all fls() usage is wrong and suffers from off-by-one problem. Secondly the assert in WaProgramMgsrForL3BankSpecificMmioReads is also wrong due inverted logic. With MCR programming fixed we can stop ignoring the engine workarounds verification of GEN8_L3SQCREG4. Tvrtko Ursulin (4): drm/i915: Fix GEN8_MCR_SELECTOR programming drm/i915: Fix WaProgramMgsrForL3BankSpecificMmioReads drm/i915: Move intel_calculate_mcr_s_ss_select to intel_sseu.c drm/i915/icl: Verify engine workarounds in GEN8_L3SQCREG4 drivers/gpu/drm/i915/gt/intel_engine_cs.c | 19 drivers/gpu/drm/i915/gt/intel_sseu.c| 24 ++ drivers/gpu/drm/i915/gt/intel_sseu.h| 2 + drivers/gpu/drm/i915/gt/intel_workarounds.c | 53 - drivers/gpu/drm/i915/i915_drv.h | 2 - 5 files changed, 45 insertions(+), 55 deletions(-) -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/execlists: Disable preemption under GVT (rev6)
== Series Details == Series: drm/i915/execlists: Disable preemption under GVT (rev6) URL : https://patchwork.freedesktop.org/series/62533/ State : success == Summary == CI Bug Log - changes from CI_DRM_6438_full -> Patchwork_13578_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13578_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@bcs0-s3: - shard-skl: [PASS][1] -> [INCOMPLETE][2] ([fdo#104108]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6438/shard-skl2/igt@gem_ctx_isolat...@bcs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13578/shard-skl8/igt@gem_ctx_isolat...@bcs0-s3.html * igt@gem_eio@unwedge-stress: - shard-snb: [PASS][3] -> [FAIL][4] ([fdo#109661]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6438/shard-snb5/igt@gem_...@unwedge-stress.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13578/shard-snb7/igt@gem_...@unwedge-stress.html * igt@gem_tiled_swapping@non-threaded: - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([fdo#108686]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6438/shard-kbl4/igt@gem_tiled_swapp...@non-threaded.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13578/shard-kbl3/igt@gem_tiled_swapp...@non-threaded.html * igt@i915_suspend@sysfs-reader: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([fdo#108566]) +5 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6438/shard-apl4/igt@i915_susp...@sysfs-reader.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13578/shard-apl7/igt@i915_susp...@sysfs-reader.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([fdo#108566]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6438/shard-kbl3/igt@kms_cursor_...@pipe-c-cursor-suspend.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13578/shard-kbl4/igt@kms_cursor_...@pipe-c-cursor-suspend.html * igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled: - shard-skl: [PASS][11] -> [FAIL][12] ([fdo#103184] / [fdo#103232]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6438/shard-skl9/igt@kms_draw_...@draw-method-rgb565-mmap-wc-ytiled.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13578/shard-skl1/igt@kms_draw_...@draw-method-rgb565-mmap-wc-ytiled.html * igt@kms_flip_tiling@flip-changes-tiling-yf: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#108228] / [fdo#108303]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6438/shard-skl9/igt@kms_flip_til...@flip-changes-tiling-yf.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13578/shard-skl1/igt@kms_flip_til...@flip-changes-tiling-yf.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt: - shard-iclb: [PASS][15] -> [INCOMPLETE][16] ([fdo#106978] / [fdo#107713]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6438/shard-iclb6/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-indfb-pgflip-blt.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13578/shard-iclb7/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-indfb-pgflip-blt.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack: - shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103167]) +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6438/shard-iclb7/igt@kms_frontbuffer_track...@fbcpsr-1p-shrfb-fliptrack.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13578/shard-iclb5/igt@kms_frontbuffer_track...@fbcpsr-1p-shrfb-fliptrack.html * igt@kms_psr@psr2_primary_page_flip: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6438/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13578/shard-iclb1/igt@kms_psr@psr2_primary_page_flip.html * igt@kms_setmode@basic: - shard-apl: [PASS][21] -> [FAIL][22] ([fdo#99912]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6438/shard-apl5/igt@kms_setm...@basic.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13578/shard-apl2/igt@kms_setm...@basic.html * igt@kms_vblank@pipe-b-query-forked-busy-hang: - shard-hsw: [PASS][23] -> [INCOMPLETE][24] ([fdo#103540]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6438/shard-hsw2/igt@kms_vbl...@pipe-b-query-forked-busy-hang.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13578/shard-hsw7/igt@kms_vbl...@pipe-b-query-forked-busy-hang.html * igt@perf@blocking: - shard-skl: [PASS][25] -> [FAIL][26] ([fdo#110728])
Re: [Intel-gfx] [PATCH] drm/i915: Remove unused i915_gem_context_lookup_engine
Quoting Chris Wilson (2019-07-09 10:32:57) > Quoting Tvrtko Ursulin (2019-07-09 10:31:05) > > From: Tvrtko Ursulin > > > > There are no known plans to start using it either. > > > > Signed-off-by: Tvrtko Ursulin > > I think I used it in the patch/series and you talked me out of it. > Reviewed-by: Chris Wilson Pushed before someone finds a use. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v8 00/13] drm/i915: Vulkan performance query support
Quoting Lionel Landwerlin (2019-07-09 13:33:38) > drm/i915/perf: ensure we keep a reference on the driver > drm/i915: enumerate scratch fields > drm/i915: add infrastructure to hold off preemption on a request These 3 looked to be standalone, so pushed. Thanks, -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 23/25] drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization
On Mon, 2019-07-08 at 16:16 -0700, Lucas De Marchi wrote:
> According to the spec when initializing the display in TGL we should
> not
> set PORT_CL_DW12 for the Aux channel of the combo PHYs. We will re-
> use the
> power well hooks from ICL so just check for IS_TIGERLAKE() inside it.
BSpec: 4301
It took me a while to find it :P
>
> Cc: Imre Deak
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_display_power.c | 12
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index be3d4d1eece2..f040a74349df 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -458,8 +458,10 @@ icl_combo_phy_aux_power_well_enable(struct
> drm_i915_private *dev_priv,
> val = I915_READ(regs->driver);
> I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
>
> - val = I915_READ(ICL_PORT_CL_DW12(port));
> - I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX);
> + if (!IS_TIGERLAKE(dev_priv)) {
You probably want to change this to if (INTEL_GEN(dev_priv) < 12) or
something like to carry this change to future platforms.
With that:
Reviewed-by: José Roberto de Souza
> + val = I915_READ(ICL_PORT_CL_DW12(port));
> + I915_WRITE(ICL_PORT_CL_DW12(port), val |
> ICL_LANE_ENABLE_AUX);
> + }
>
> hsw_wait_for_power_well_enable(dev_priv, power_well);
>
> @@ -486,8 +488,10 @@ icl_combo_phy_aux_power_well_disable(struct
> drm_i915_private *dev_priv,
> enum port port = ICL_AUX_PW_TO_PORT(pw_idx);
> u32 val;
>
> - val = I915_READ(ICL_PORT_CL_DW12(port));
> - I915_WRITE(ICL_PORT_CL_DW12(port), val & ~ICL_LANE_ENABLE_AUX);
> + if (!IS_TIGERLAKE(dev_priv)) {
> + val = I915_READ(ICL_PORT_CL_DW12(port));
> + I915_WRITE(ICL_PORT_CL_DW12(port), val &
> ~ICL_LANE_ENABLE_AUX);
> + }
>
> val = I915_READ(regs->driver);
> I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+ (rev2)
== Series Details == Series: drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+ (rev2) URL : https://patchwork.freedesktop.org/series/63432/ State : success == Summary == CI Bug Log - changes from CI_DRM_6438_full -> Patchwork_13577_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13577_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_nop@basic-series: - shard-apl: [PASS][1] -> [INCOMPLETE][2] ([fdo#103927]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6438/shard-apl8/igt@gem_exec_...@basic-series.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13577/shard-apl2/igt@gem_exec_...@basic-series.html * igt@gem_exec_suspend@basic-s3: - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6438/shard-kbl1/igt@gem_exec_susp...@basic-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13577/shard-kbl4/igt@gem_exec_susp...@basic-s3.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][5] -> [FAIL][6] ([fdo#105363]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6438/shard-skl1/igt@kms_f...@flip-vs-expired-vblank.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13577/shard-skl7/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_flip@flip-vs-suspend: - shard-kbl: [PASS][7] -> [INCOMPLETE][8] ([fdo#103665]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6438/shard-kbl1/igt@kms_f...@flip-vs-suspend.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13577/shard-kbl3/igt@kms_f...@flip-vs-suspend.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-hsw: [PASS][9] -> [INCOMPLETE][10] ([fdo#103540]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6438/shard-hsw2/igt@kms_f...@flip-vs-suspend-interruptible.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13577/shard-hsw7/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_flip_tiling@flip-changes-tiling-yf: - shard-skl: [PASS][11] -> [FAIL][12] ([fdo#108228] / [fdo#108303]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6438/shard-skl9/igt@kms_flip_til...@flip-changes-tiling-yf.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13577/shard-skl10/igt@kms_flip_til...@flip-changes-tiling-yf.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt: - shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103167]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6438/shard-iclb4/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-msflip-blt.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13577/shard-iclb3/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-msflip-blt.html * igt@kms_plane_lowres@pipe-a-tiling-y: - shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#103166]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6438/shard-iclb3/igt@kms_plane_low...@pipe-a-tiling-y.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13577/shard-iclb6/igt@kms_plane_low...@pipe-a-tiling-y.html * igt@kms_psr@psr2_primary_page_flip: - shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109441]) +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6438/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13577/shard-iclb8/igt@kms_psr@psr2_primary_page_flip.html * igt@kms_vblank@pipe-a-ts-continuation-suspend: - shard-apl: [PASS][19] -> [DMESG-WARN][20] ([fdo#108566]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6438/shard-apl2/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13577/shard-apl6/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html * igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend: - shard-skl: [PASS][21] -> [INCOMPLETE][22] ([fdo#104108]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6438/shard-skl10/igt@kms_vbl...@pipe-c-ts-continuation-dpms-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13577/shard-skl2/igt@kms_vbl...@pipe-c-ts-continuation-dpms-suspend.html * igt@kms_vblank@pipe-c-wait-idle: - shard-iclb: [PASS][23] -> [INCOMPLETE][24] ([fdo#107713]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6438/shard-iclb5/igt@kms_vbl...@pipe-c-wait-idle.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13577/shard-iclb4/igt@kms_vbl...@pipe-c-wait-idle.html * igt@perf_pmu@rc6: - shard-kbl: [PASS][25] -> [SKIP][26] ([fdo#109271]) [25]:
Re: [Intel-gfx] [PATCH v2 08/25] drm/i915/tgl: use TRANSCODER_EDP_VDSC on transcoder A
On Tue, Jul 09, 2019 at 01:07:17AM +, Souza, Jose wrote:
> On Mon, 2019-07-08 at 16:16 -0700, Lucas De Marchi wrote:
> > From: José Roberto de Souza
> >
> > On TGL the special EDP transcoder is gone and it should be handled by
> > transcoder A.
> >
> > v2 (Lucas):
> > - Reuse POWER_DOMAIN_TRANSCODER_EDP_VDSC (suggested by Ville)
> > - Use crtc->dev since new_crtc_state->state may be NULL on atomic
> > commit (suggested by Maarten)
>
> As we are reusing would be nice also rename it to something like:
> POWER_DOMAIN_TRANSCODER_VDSC_PW2
> POWER_DOMAIN_LOW_POWER_TRANSCODER_VDSC /
> POWER_DOMAIN_LP_TRANSCODER_VDSC
We did struggle initially as well to find an appropriate name and settled for
POWER_DOMAIN_TRANSCODER_EDP_VDSC but I agree that now since it is not just for
EDP
but for Transcoder A which could be any connector, its better to rename the
power well
POWER_DOMAIN_TRANSCODER_VDSC_PW2 or
POWER_DOMAIN_TRANSCODER_EDP_A_VDSC and then in the comment clearly mention that
for Gen 11 it is for Transcoder EDP VDSC and then Gen 12 + it is for Transcoder
A VDSC
Manasi
>
> >
> > Cc: Imre Deak
> > Signed-off-by: José Roberto de Souza
> > Signed-off-by: Lucas De Marchi
> > ---
> > drivers/gpu/drm/i915/display/intel_vdsc.c | 9 ++---
> > 1 file changed, 6 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > index ffec807b8960..c27912f552f0 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > @@ -459,16 +459,19 @@ int intel_dp_compute_dsc_params(struct intel_dp
> > *intel_dp,
> > enum intel_display_power_domain
> > intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
> > {
> > + struct drm_i915_private *i915 = to_i915(crtc_state->base.crtc-
> > >dev);
> > enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> >
> > /*
> > -* On ICL VDSC/joining for eDP transcoder uses a separate power
> > well PW2
> > -* This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
> > +* On ICL+ VDSC/joining for eDP/A transcoder uses a separate
> > power well
> > +* PW2. This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power
> > domain.
> > * For any other transcoder, VDSC/joining uses the power well
> > associated
> > * with the pipe/transcoder in use. Hence another reference on
> > the
> > * transcoder power domain will suffice.
> > */
> > - if (cpu_transcoder == TRANSCODER_EDP)
> > + if (INTEL_GEN(i915) >= 12 && cpu_transcoder == TRANSCODER_A)
> > + return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
> > + else if (cpu_transcoder == TRANSCODER_EDP)
> > return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
> > else
> > return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH v2 14/25] drm/i915/tgl: update ddi/tc clock_off bits
On Tue, Jul 09, 2019 at 12:49:21PM -0700, Jose Souza wrote:
FYI
https://patchwork.freedesktop.org/patch/316805/?series=62492=7
Is just waiting CI feedback to get merged and it is doing the same job
as this patch.
But that depends on the enum phy infra. Is that entering now?? This
would means reworking the patches on this series as they are going to
conflict badly.
Lucas De Marchi
On Mon, 2019-07-08 at 16:16 -0700, Lucas De Marchi wrote:
From: Mahesh Kumar
In GEN 12 PORT_C DDI clk_off bit is not equally distanced to A/B,
it's at offset 24. Similarly TC port (5/6) clk off bits are at
offset 22/23. Extend the macros to cover the additional ports.
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_reg.h | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h
b/drivers/gpu/drm/i915/i915_reg.h
index 5ca74eca05a4..4588df9e11de 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9723,9 +9723,11 @@ enum skl_power_gate {
#define DPCLKA_CFGCR0_ICL _MMIO(0x164280)
#define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port)
== PORT_F ? 23 : \
(port) + 10))
-#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) + 10))
-#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) ==
PORT_TC4 ? \
- 21 : (tc_port) +
12))
+#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_C
? 24 : \
+ (port) + 10))
+#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 <<
((tc_port) < PORT_TC4 ? \
+ (tc_port) + 12 :
\
+ (tc_port) -
PORT_TC4 + 21))
#define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) ==
PORT_F ? 21 : \
(port) * 2)
#define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 <<
DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
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Re: [Intel-gfx] [PATCH v8 1/6] drm: Add Content protection type property
On 2019-07-09 at 16:26:31 +0300, Pekka Paalanen wrote:
> On Mon, 8 Jul 2019 14:42:29 +0530
> Ramalingam C wrote:
>
> > On 2019-07-08 at 12:59:59 +0300, Pekka Paalanen wrote:
> > > On Mon, 8 Jul 2019 12:52:17 +0300
> > > Pekka Paalanen wrote:
> > >
> > > > On Fri, 5 Jul 2019 06:16:37 +0530
> > > > Ramalingam C wrote:
> > > >
> > > > > This patch adds a DRM ENUM property to the selected connectors.
> > > > > This property is used for mentioning the protected content's type
> > > > > from userspace to kernel HDCP authentication.
> > > > >
> > > > > Type of the stream is decided by the protected content providers.
> > > > > Type 0 content can be rendered on any HDCP protected display wires.
> > > > > But Type 1 content can be rendered only on HDCP2.2 protected paths.
> > > > >
> > > > > So when a userspace sets this property to Type 1 and starts the HDCP
> > > > > enable, kernel will honour it only if HDCP2.2 authentication is
> > > > > through
> > > > > for type 1. Else HDCP enable will be failed.
> > > > >
> > > > > Need ACK for this new conenctor property from userspace consumer.
> > > > >
> > > > > v2:
> > > > > cp_content_type is replaced with content_protection_type [daniel]
> > > > > check at atomic_set_property is removed [Maarten]
> > > > > v3:
> > > > > %s/content_protection_type/hdcp_content_type [Pekka]
> > > > > v4:
> > > > > property is created for the first requested connector and then
> > > > > reused.
> > > > > [Danvet]
> > > > > v5:
> > > > > kernel doc nits addressed [Daniel]
> > > > > Rebased as part of patch reordering.
> > > > > v6:
> > > > > Kernel docs are modified [pekka]
> > > > >
> > > > > Signed-off-by: Ramalingam C
> > > > > Reviewed-by: Daniel Vetter
> > > > > ---
> > > > > drivers/gpu/drm/drm_atomic_uapi.c | 4 +++
> > > > > drivers/gpu/drm/drm_connector.c | 22 ++
> > > > > drivers/gpu/drm/drm_hdcp.c| 36
> > > > > ++-
> > > > > drivers/gpu/drm/i915/display/intel_hdcp.c | 4 ++-
> > > > > include/drm/drm_connector.h | 7 +
> > > > > include/drm/drm_hdcp.h| 2 +-
> > > > > include/drm/drm_mode_config.h | 6
> > > > > include/uapi/drm/drm_mode.h | 4 +++
> > > > > 8 files changed, 82 insertions(+), 3 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
> > > > > b/drivers/gpu/drm/drm_atomic_uapi.c
> > > > > index abe38bdf85ae..19ae119f1a5d 100644
> > > > > --- a/drivers/gpu/drm/drm_atomic_uapi.c
> > > > > +++ b/drivers/gpu/drm/drm_atomic_uapi.c
> > > > > @@ -747,6 +747,8 @@ static int
> > > > > drm_atomic_connector_set_property(struct drm_connector *connector,
> > > > > return -EINVAL;
> > > > > }
> > > > > state->content_protection = val;
> > > > > + } else if (property == config->hdcp_content_type_property) {
> > > > > + state->hdcp_content_type = val;
> > > > > } else if (property == connector->colorspace_property) {
> > > > > state->colorspace = val;
> > > > > } else if (property == config->writeback_fb_id_property) {
> > > > > @@ -831,6 +833,8 @@ drm_atomic_connector_get_property(struct
> > > > > drm_connector *connector,
> > > > > state->hdr_output_metadata->base.id : 0;
> > > > > } else if (property == config->content_protection_property) {
> > > > > *val = state->content_protection;
> > > > > + } else if (property == config->hdcp_content_type_property) {
> > > > > + *val = state->hdcp_content_type;
> > > > > } else if (property == config->writeback_fb_id_property) {
> > > > > /* Writeback framebuffer is one-shot, write and forget
> > > > > */
> > > > > *val = 0;
> > > > > diff --git a/drivers/gpu/drm/drm_connector.c
> > > > > b/drivers/gpu/drm/drm_connector.c
> > > > > index 068d4b05f1be..17aef88c03a6 100644
> > > > > --- a/drivers/gpu/drm/drm_connector.c
> > > > > +++ b/drivers/gpu/drm/drm_connector.c
> > > > > @@ -951,6 +951,28 @@ static const struct drm_prop_enum_list
> > > > > hdmi_colorspaces[] = {
> > > > > * the value transitions from ENABLED to DESIRED. This signifies
> > > > > the link
> > > > > * is no longer protected and userspace should take appropriate
> > > > > action
> > > > > * (whatever that might be).
> > > > > + * HDCP Content Type:
> > > > > + * This property is used by the userspace to configure the kernel
> > > > > with
> > > > > + * to be displayed stream's content type. Content Type of a stream
> > > > > is
> > > > > + * decided by the owner of the stream, as "HDCP Type0" or "HDCP
> > > > > Type1".
> > > > > + *
> > > > > + * The value of the property can be one the below:
> > > > > + * - "HDCP Type0": DRM_MODE_HDCP_CONTENT_TYPE0 = 0
> > > > > + * HDCP Type0 streams can be transmitted on a link which is
> > >
Re: [Intel-gfx] [PATCH v2 18/25] drm/i915/tgl: extend intel_port_is_combophy/tc
On Mon, 2019-07-08 at 16:16 -0700, Lucas De Marchi wrote:
> From: Mahesh Kumar
>
> TGL has 3 combophy ports, so extend check for tigerlake in
> intel_port_is_combophy/tc function.
Reviewed-by: José Roberto de Souza
>
> Cc: Mika Kahola
> Signed-off-by: Mahesh Kumar
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 12 +---
> 1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index d1148786920e..e224dcf60e31 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6676,10 +6676,10 @@ bool intel_port_is_combophy(struct
> drm_i915_private *dev_priv, enum port port)
> if (port == PORT_NONE)
> return false;
>
> - if (IS_ELKHARTLAKE(dev_priv))
> + if (IS_ELKHARTLAKE(dev_priv) || INTEL_GEN(dev_priv) >= 12)
> return port <= PORT_C;
>
> - if (INTEL_GEN(dev_priv) >= 11)
> + if (IS_GEN(dev_priv, 11))
> return port <= PORT_B;
>
> return false;
> @@ -6687,7 +6687,10 @@ bool intel_port_is_combophy(struct
> drm_i915_private *dev_priv, enum port port)
>
> bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port
> port)
> {
> - if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
> + if (INTEL_GEN(dev_priv) >= 12)
> + return port >= PORT_D && port <= PORT_I;
> +
> + if (IS_GEN(dev_priv, 11) && !IS_ELKHARTLAKE(dev_priv))
> return port >= PORT_C && port <= PORT_F;
>
> return false;
> @@ -6698,6 +6701,9 @@ enum tc_port intel_port_to_tc(struct
> drm_i915_private *dev_priv, enum port port)
> if (!intel_port_is_tc(dev_priv, port))
> return PORT_TC_NONE;
>
> + if (INTEL_GEN(dev_priv) >= 12)
> + return port - PORT_D;
> +
> return port - PORT_C;
> }
>
___
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Re: [Intel-gfx] [PATCH v2 19/25] drm/i915/tgl: init ddi port A-C for Tiger Lake
On Mon, 2019-07-08 at 16:16 -0700, Lucas De Marchi wrote:
> From: Mahesh Kumar
>
> This patch initializes DDI PORT A, B & C for Tiger lake. Other
> TC ports need to be initialized later once corresponding code is
> there.
Reviewed-by: José Roberto de Souza
>
> Cc: Madhav Chauhan
> Signed-off-by: Mahesh Kumar
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 9 +++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index e224dcf60e31..9ccf58ff4dba 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -15302,12 +15302,17 @@ static void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
> if (!HAS_DISPLAY(dev_priv))
> return;
>
> - if (IS_ELKHARTLAKE(dev_priv)) {
> + if (INTEL_GEN(dev_priv) >= 12) {
> + /* TODO: initialize TC ports as well */
> + intel_ddi_init(dev_priv, PORT_A);
> + intel_ddi_init(dev_priv, PORT_B);
> + intel_ddi_init(dev_priv, PORT_C);
> + } else if (IS_ELKHARTLAKE(dev_priv)) {
> intel_ddi_init(dev_priv, PORT_A);
> intel_ddi_init(dev_priv, PORT_B);
> intel_ddi_init(dev_priv, PORT_C);
> icl_dsi_init(dev_priv);
> - } else if (INTEL_GEN(dev_priv) >= 11) {
> + } else if (IS_GEN(dev_priv, 11)) {
> intel_ddi_init(dev_priv, PORT_A);
> intel_ddi_init(dev_priv, PORT_B);
> intel_ddi_init(dev_priv, PORT_C);
___
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Re: [Intel-gfx] [PATCH v2 14/25] drm/i915/tgl: update ddi/tc clock_off bits
FYI
https://patchwork.freedesktop.org/patch/316805/?series=62492=7
Is just waiting CI feedback to get merged and it is doing the same job
as this patch.
On Mon, 2019-07-08 at 16:16 -0700, Lucas De Marchi wrote:
> From: Mahesh Kumar
>
> In GEN 12 PORT_C DDI clk_off bit is not equally distanced to A/B,
> it's at offset 24. Similarly TC port (5/6) clk off bits are at
> offset 22/23. Extend the macros to cover the additional ports.
>
> Signed-off-by: Mahesh Kumar
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/i915_reg.h | 8 +---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 5ca74eca05a4..4588df9e11de 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9723,9 +9723,11 @@ enum skl_power_gate {
> #define DPCLKA_CFGCR0_ICL_MMIO(0x164280)
> #define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port)
> == PORT_F ? 23 : \
> (port) + 10))
> -#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) + 10))
> -#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) ==
> PORT_TC4 ? \
> - 21 : (tc_port) +
> 12))
> +#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_C
> ? 24 : \
> +(port) + 10))
> +#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 <<
> ((tc_port) < PORT_TC4 ? \
> +(tc_port) + 12 :
> \
> +(tc_port) -
> PORT_TC4 + 21))
> #define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) ==
> PORT_F ? 21 : \
> (port) * 2)
> #define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port)(3 <<
> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
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Re: [Intel-gfx] [PATCH v9 1/6] drm: Add Content protection type property
On 2019-07-09 at 17:31:10 +0300, Pekka Paalanen wrote:
> On Mon, 8 Jul 2019 16:51:11 +0530
> Ramalingam C wrote:
>
> > This patch adds a DRM ENUM property to the selected connectors.
> > This property is used for mentioning the protected content's type
> > from userspace to kernel HDCP authentication.
> >
> > Type of the stream is decided by the protected content providers.
> > Type 0 content can be rendered on any HDCP protected display wires.
> > But Type 1 content can be rendered only on HDCP2.2 protected paths.
> >
> > So when a userspace sets this property to Type 1 and starts the HDCP
> > enable, kernel will honour it only if HDCP2.2 authentication is through
> > for type 1. Else HDCP enable will be failed.
> >
> > Need ACK for this new conenctor property from userspace consumer.
> >
> > v2:
> > cp_content_type is replaced with content_protection_type [daniel]
> > check at atomic_set_property is removed [Maarten]
> > v3:
> > %s/content_protection_type/hdcp_content_type [Pekka]
> > v4:
> > property is created for the first requested connector and then reused.
> > [Danvet]
> > v5:
> > kernel doc nits addressed [Daniel]
> > Rebased as part of patch reordering.
> > v6:
> > Kernel docs are modified [pekka]
> > v7:
> > More details in Kernel docs. [pekka]
> >
> > Signed-off-by: Ramalingam C
> > Reviewed-by: Daniel Vetter
> > ---
> > drivers/gpu/drm/drm_atomic_uapi.c | 4 +++
> > drivers/gpu/drm/drm_connector.c | 39 +++
> > drivers/gpu/drm/drm_hdcp.c| 36 -
> > drivers/gpu/drm/i915/display/intel_hdcp.c | 4 ++-
> > include/drm/drm_connector.h | 7
> > include/drm/drm_hdcp.h| 2 +-
> > include/drm/drm_mode_config.h | 6
> > include/uapi/drm/drm_mode.h | 4 +++
> > 8 files changed, 99 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
> > b/drivers/gpu/drm/drm_atomic_uapi.c
> > index abe38bdf85ae..19ae119f1a5d 100644
> > --- a/drivers/gpu/drm/drm_atomic_uapi.c
> > +++ b/drivers/gpu/drm/drm_atomic_uapi.c
> > @@ -747,6 +747,8 @@ static int drm_atomic_connector_set_property(struct
> > drm_connector *connector,
> > return -EINVAL;
> > }
> > state->content_protection = val;
> > + } else if (property == config->hdcp_content_type_property) {
> > + state->hdcp_content_type = val;
> > } else if (property == connector->colorspace_property) {
> > state->colorspace = val;
> > } else if (property == config->writeback_fb_id_property) {
> > @@ -831,6 +833,8 @@ drm_atomic_connector_get_property(struct drm_connector
> > *connector,
> > state->hdr_output_metadata->base.id : 0;
> > } else if (property == config->content_protection_property) {
> > *val = state->content_protection;
> > + } else if (property == config->hdcp_content_type_property) {
> > + *val = state->hdcp_content_type;
> > } else if (property == config->writeback_fb_id_property) {
> > /* Writeback framebuffer is one-shot, write and forget */
> > *val = 0;
> > diff --git a/drivers/gpu/drm/drm_connector.c
> > b/drivers/gpu/drm/drm_connector.c
> > index 068d4b05f1be..732f6645643d 100644
> > --- a/drivers/gpu/drm/drm_connector.c
> > +++ b/drivers/gpu/drm/drm_connector.c
> > @@ -952,6 +952,45 @@ static const struct drm_prop_enum_list
> > hdmi_colorspaces[] = {
> > * is no longer protected and userspace should take appropriate action
> > * (whatever that might be).
> > *
> > + * HDCP Content Type:
> > + * This Enum property is used by the userspace to declare the content type
> > + * of the display stream, to kernel. Here display stream stands for any
> > + * display content that userspace intended to render with HDCP encryption.
>
> Hi,
>
> I'd suggest s/render with/display through/.
>
> As a gfx dev, rendering is something quite different to me.
Ok.
>
> > + *
> > + * Content Type of a stream is decided by the owner of the stream, as
> > + * "HDCP Type0" or "HDCP Type1".
> > + *
> > + * The value of the property can be one the below:
>
> *one of the below
Sure.
>
> > + * - "HDCP Type0": DRM_MODE_HDCP_CONTENT_TYPE0 = 0
> > + * - "HDCP Type1": DRM_MODE_HDCP_CONTENT_TYPE1 = 1
> > + *
> > + * When kernel starts the HDCP authentication upon the "DESIRED" state of
> > + * the "Content Protection", it refers the "HDCP Content Type" property
> > + * state. And perform the HDCP authentication with the display sink for
> > + * the content type mentioned by "HDCP Content Type".
>
> How about:
>
> When kernel starts the HDCP authentication (see "Content Protection"
> for details), it uses the content type in "HDCP Content Type"
> for performing the HDCP authentication with the display sink.
less confusing :) Thanks.
>
> > + *
> > + * Stream classified as HDCP Type0 can be
[Intel-gfx] ✓ Fi.CI.BAT: success for EHL port programming (rev7)
== Series Details ==
Series: EHL port programming (rev7)
URL : https://patchwork.freedesktop.org/series/62492/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6444 -> Patchwork_13589
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/
Known issues
Here are the changes found in Patchwork_13589 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_create@basic:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/fi-icl-u3/igt@gem_exec_cre...@basic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/fi-icl-u3/igt@gem_exec_cre...@basic.html
Possible fixes
* {igt@gem_ctx_switch@legacy-render}:
- fi-icl-guc: [INCOMPLETE][3] ([fdo#107713]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/fi-icl-guc/igt@gem_ctx_swi...@legacy-render.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/fi-icl-guc/igt@gem_ctx_swi...@legacy-render.html
* igt@gem_mmap_gtt@basic-read-no-prefault:
- fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/fi-icl-u3/igt@gem_mmap_...@basic-read-no-prefault.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/fi-icl-u3/igt@gem_mmap_...@basic-read-no-prefault.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111046 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111046
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
Participating hosts (53 -> 45)
--
Missing(8): fi-kbl-soraka fi-byt-j1900 fi-byt-squawks fi-bsw-cyan
fi-pnv-d510 fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6444 -> Patchwork_13589
CI_DRM_6444: 6e842ef98f5278c942ddd9bbe83b19697deef7b0 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5092: 2a66ae6626d5583240509f84117d1345a799b75a @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13589: a188f8f668e0e487c1371e5fdcf143811554a74a @
git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/build_32bit.log
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1287: recipe for target 'modules' failed
make: *** [modules] Error 2
== Linux commits ==
a188f8f668e0 drm/i915/ehl: Enable DDI-D
2d193fd97d83 drm/i915: Transition port type checks to phy checks
2550905e56cc drm/i915/gen11: Convert combo PHY logic to use new 'enum phy'
namespace
97ceed65bf2b drm/i915/gen11: Program ICL_DPCLKA_CFGCR0 according to PHY
0cd776d3f169 drm/i915/gen11: Start distinguishing 'phy' from 'port'
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/
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Re: [Intel-gfx] [PATCH v2 13/25] drm/i915/tgl: Add additional ports for Tiger Lake
On Mon, 2019-07-08 at 16:16 -0700, Lucas De Marchi wrote:
> From: Vandita Kulkarni
>
> There are 2 new additional typeC ports in Tiger Lake and PORT-C is
> now a
> combophy port. This results in 6 typeC ports and 3 combophy ports.
> These 6 TC ports can be DP alternate mode, DP over thunderbolt,
> native
> DP on legacy DP connector or native HDMI on legacy connector.
>
> v2: Rebase on new modular FIA code (Lucas)
>
> Cc: Anusha Srivatsa
> Signed-off-by: Vandita Kulkarni
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 12
> drivers/gpu/drm/i915/display/intel_display.h | 2 ++
> include/drm/i915_component.h | 2 +-
> include/drm/i915_drm.h | 3 +++
> 4 files changed, 18 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 30e48609db1d..e72cf0bb48a7 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4297,6 +4297,18 @@ void intel_ddi_init(struct drm_i915_private
> *dev_priv, enum port port)
> intel_dig_port->ddi_io_power_domain =
> POWER_DOMAIN_PORT_DDI_F_IO;
> break;
> + case PORT_G:
> + intel_dig_port->ddi_io_power_domain =
> + POWER_DOMAIN_PORT_DDI_G_IO;
> + break;
> + case PORT_H:
> + intel_dig_port->ddi_io_power_domain =
> + POWER_DOMAIN_PORT_DDI_H_IO;
> + break;
> + case PORT_I:
> + intel_dig_port->ddi_io_power_domain =
> + POWER_DOMAIN_PORT_DDI_I_IO;
> + break;
> default:
> MISSING_CASE(port);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> b/drivers/gpu/drm/i915/display/intel_display.h
> index e781df463ffa..270b1f18dedd 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
Nit: Missing add new ports to port_identifier() on this file but they
can't be HDMI so it should not cause any bugs, even better would be
make use of port_name()
Other than that:
Reviewed-by: José Roberto de Souza
> @@ -189,6 +189,8 @@ enum tc_port {
> PORT_TC2,
> PORT_TC3,
> PORT_TC4,
> + PORT_TC5,
> + PORT_TC6,
>
> I915_MAX_TC_PORTS
> };
> diff --git a/include/drm/i915_component.h
> b/include/drm/i915_component.h
> index dcb95bd9dee6..55c3b123581b 100644
> --- a/include/drm/i915_component.h
> +++ b/include/drm/i915_component.h
> @@ -34,7 +34,7 @@ enum i915_component_type {
> /* MAX_PORT is the number of port
> * It must be sync with I915_MAX_PORTS defined i915_drv.h
> */
> -#define MAX_PORTS 6
> +#define MAX_PORTS 9
>
> /**
> * struct i915_audio_component - Used for direct communication
> between i915 and hda drivers
> diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
> index 7523e9a7b6e2..eb30062359d1 100644
> --- a/include/drm/i915_drm.h
> +++ b/include/drm/i915_drm.h
> @@ -109,6 +109,9 @@ enum port {
> PORT_D,
> PORT_E,
> PORT_F,
> + PORT_G,
> + PORT_H,
> + PORT_I,
>
> I915_MAX_PORTS
> };
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for EHL port programming (rev7)
== Series Details == Series: EHL port programming (rev7) URL : https://patchwork.freedesktop.org/series/62492/ State : warning == Summary == $ dim checkpatch origin/drm-tip 0cd776d3f169 drm/i915/gen11: Start distinguishing 'phy' from 'port' 97ceed65bf2b drm/i915/gen11: Program ICL_DPCLKA_CFGCR0 according to PHY -:265: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'tc_port' - possible side-effects? #265: FILE: drivers/gpu/drm/i915/i915_reg.h:9709: +#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \ + 21 : (tc_port) + 12)) -:268: WARNING:LONG_LINE: line over 100 characters #268: FILE: drivers/gpu/drm/i915/i915_reg.h:9712: +#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) -:269: WARNING:LONG_LINE: line over 100 characters #269: FILE: drivers/gpu/drm/i915/i915_reg.h:9713: +#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) total: 0 errors, 2 warnings, 1 checks, 212 lines checked 2550905e56cc drm/i915/gen11: Convert combo PHY logic to use new 'enum phy' namespace -:352: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__phy' - possible side-effects? #352: FILE: drivers/gpu/drm/i915/display/intel_combo_phy.c:9: +#define for_each_combo_phy(__dev_priv, __phy) \ + for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \ + for_each_if(intel_phy_is_combo(__dev_priv, __phy)) -:359: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__phy' - possible side-effects? #359: FILE: drivers/gpu/drm/i915/display/intel_combo_phy.c:13: +#define for_each_combo_phy_reverse(__dev_priv, __phy) \ + for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \ + for_each_if(intel_phy_is_combo(__dev_priv, __phy)) -:835: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__phy' - possible side-effects? #835: FILE: drivers/gpu/drm/i915/display/intel_display.h:271: +#define for_each_phy_masked(__phy, __phys_mask) \ + for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \ + for_each_if((__phys_mask) & BIT(__phy)) -:1015: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #1015: FILE: drivers/gpu/drm/i915/i915_reg.h:1880: +#define CNL_PORT_PCS_DW1_LN0(phy) _MMIO(_PICK(phy, \ _CNL_PORT_PCS_DW1_LN0_AE, \ _CNL_PORT_PCS_DW1_LN0_B, \ _CNL_PORT_PCS_DW1_LN0_C, \ total: 1 errors, 0 warnings, 3 checks, 1001 lines checked 2d193fd97d83 drm/i915: Transition port type checks to phy checks a188f8f668e0 drm/i915/ehl: Enable DDI-D ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for Initial support for Tiger Lake (rev3)
== Series Details ==
Series: Initial support for Tiger Lake (rev3)
URL : https://patchwork.freedesktop.org/series/62726/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6444 -> Patchwork_13588
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13588/
Known issues
Here are the changes found in Patchwork_13588 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_sanitycheck:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/fi-icl-u3/igt@i915_selftest@live_sanitycheck.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13588/fi-icl-u3/igt@i915_selftest@live_sanitycheck.html
Possible fixes
* {igt@gem_ctx_switch@legacy-render}:
- fi-icl-guc: [INCOMPLETE][3] ([fdo#107713]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/fi-icl-guc/igt@gem_ctx_swi...@legacy-render.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13588/fi-icl-guc/igt@gem_ctx_swi...@legacy-render.html
* igt@gem_mmap_gtt@basic-read-no-prefault:
- fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/fi-icl-u3/igt@gem_mmap_...@basic-read-no-prefault.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13588/fi-icl-u3/igt@gem_mmap_...@basic-read-no-prefault.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: [FAIL][7] ([fdo#103167]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13588/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
Participating hosts (53 -> 46)
--
Missing(7): fi-kbl-soraka fi-byt-squawks fi-bsw-cyan fi-byt-clapper
fi-icl-y fi-icl-dsi fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6444 -> Patchwork_13588
CI_DRM_6444: 6e842ef98f5278c942ddd9bbe83b19697deef7b0 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5092: 2a66ae6626d5583240509f84117d1345a799b75a @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13588: 281d1bcfc2261eb88918b65d844d7bb9f638ab9a @
git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13588/build_32bit.log
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1287: recipe for target 'modules' failed
make: *** [modules] Error 2
== Linux commits ==
281d1bcfc226 drm/i915/tgl: Update DPLL clock reference register
cf688295aed2 drm/i915/tgl: Add DPLL registers
a840d06f8c92 drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization
cd3414367161 drm/i915/gen12: MBUS B credit change
9bb0ad3b4017 drm/i915/tgl: apply Display WA #1178 to fix type C dongles
414c3ae9ddfd drm/i915/tgl: Add vbt value mapping for DDC Bus pin
33cbf7793050 drm/i915/tgl: init ddi port A-C for Tiger Lake
17b3e3c96fb6 drm/i915/tgl: extend intel_port_is_combophy/tc
e7d46091155c drm/i915/tgl: select correct bit for port select
93b16ee61a60 drm/i915/tgl: port to ddc pin mapping
5ff6a19fe86f drm/i915/tgl: Add gmbus gpio pin to port mapping
7787733b30b1 drm/i915/tgl: update ddi/tc clock_off bits
5e768170eebe drm/i915/tgl: Add additional ports for Tiger Lake
91b16ba0eb18 drm/i915/tgl: Add pll manager
45b62a9eac96 drm/i915/tgl: Add new pll ids
f5175d7ae1c3 drm/i915/tgl: Add power well to support 4th pipe
228a055462e0 drm/i915/tgl: Add power well support
52cd60dca858 drm/i915/tgl: use TRANSCODER_EDP_VDSC on transcoder A
7ad31e8ccdb5 drm/i915/tgl: Check if pipe D is fused
8e56a0e4bf92 x86/gpu: add TGL stolen memory support
9b52a5d4d480 drm/i915/tgl: Add TGL PCI IDs
cb543d474e7a drm/i915/tgl: Add TGL PCH detection in virtualized environment
777a2d8d8266 drm/i915/tgl: Introduce Tiger Lake PCH
0cd4b6f0f2d1 drm/i915/tgl: add initial Tiger Lake definitions
5c5e5e6008d1 drm/i915: Add 4th pipe and transcoder
== Logs
[Intel-gfx] [PATCH v6 4/5] drm/i915: Transition port type checks to phy checks
Transition the remaining uses of intel_port_is_* over to the equivalent
intel_phy_is_* functions and drop the port functions.
v5: Fix a call in a debug function that's only called when
CONFIG_DRM_I915_DEBUG_RUNTIME_PM is on. (CI)
Cc: José Roberto de Souza
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
Reviewed-by: Ville Syrjälä
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_bios.c | 4 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 38 ---
drivers/gpu/drm/i915/display/intel_display.c | 38 +--
.../drm/i915/display/intel_display_power.c| 4 +-
drivers/gpu/drm/i915/display/intel_dp.c | 15 +---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 11 +++---
drivers/gpu/drm/i915/intel_drv.h | 2 -
7 files changed, 55 insertions(+), 57 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 0c9808132d67..4fdbb5c35d87 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -28,6 +28,7 @@
#include
#include
+#include "display/intel_display.h"
#include "display/intel_gmbus.h"
#include "i915_drv.h"
@@ -1733,12 +1734,13 @@ init_vbt_missing_defaults(struct drm_i915_private
*dev_priv)
for (port = PORT_A; port < I915_MAX_PORTS; port++) {
struct ddi_vbt_port_info *info =
_priv->vbt.ddi_port_info[port];
+ enum phy phy = intel_port_to_phy(dev_priv, port);
/*
* VBT has the TypeC mode (native,TBT/USB) and we don't want
* to detect it.
*/
- if (intel_port_is_tc(dev_priv, port))
+ if (intel_phy_is_tc(dev_priv, phy))
continue;
info->supports_dvi = (port != PORT_A && port != PORT_E);
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index d9ea58038642..8f760a3e30fa 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -868,11 +868,12 @@ icl_get_combo_buf_trans(struct drm_i915_private
*dev_priv, int type, int rate,
static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port
port)
{
int n_entries, level, default_entry;
+ enum phy phy = intel_port_to_phy(dev_priv, port);
level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
if (INTEL_GEN(dev_priv) >= 11) {
- if (intel_port_is_combophy(dev_priv, port))
+ if (intel_phy_is_combo(dev_priv, phy))
icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
0, _entries);
else
@@ -1487,9 +1488,10 @@ static void icl_ddi_clock_get(struct intel_encoder
*encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dpll_hw_state *pll_state = _config->dpll_hw_state;
enum port port = encoder->port;
+ enum phy phy = intel_port_to_phy(dev_priv, port);
int link_clock;
- if (intel_port_is_combophy(dev_priv, port)) {
+ if (intel_phy_is_combo(dev_priv, phy)) {
link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
} else {
enum intel_dpll_id pll_id = intel_get_shared_dpll_id(dev_priv,
@@ -2086,6 +2088,7 @@ static void intel_ddi_get_power_domains(struct
intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_digital_port *dig_port;
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
/*
* TODO: Add support for MST encoders. Atm, the following should never
@@ -2103,7 +2106,7 @@ static void intel_ddi_get_power_domains(struct
intel_encoder *encoder,
* ports.
*/
if (intel_crtc_has_dp_encoder(crtc_state) ||
- intel_port_is_tc(dev_priv, encoder->port))
+ intel_phy_is_tc(dev_priv, phy))
intel_display_power_get(dev_priv,
intel_ddi_main_link_aux_domain(dig_port));
@@ -2228,10 +2231,11 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder
*encoder)
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dp *intel_dp = enc_to_intel_dp(>base);
enum port port = encoder->port;
+ enum phy phy = intel_port_to_phy(dev_priv, port);
int n_entries;
if (INTEL_GEN(dev_priv) >= 11) {
- if (intel_port_is_combophy(dev_priv, port))
+ if (intel_phy_is_combo(dev_priv, phy))
icl_get_combo_buf_trans(dev_priv, encoder->type,
intel_dp->link_rate,
_entries);
else
@@ -2664,9 +2668,9 @@ static void icl_ddi_vswing_sequence(struct intel_encoder
*encoder,
[Intel-gfx] [PATCH v6 1/5] drm/i915/gen11: Start distinguishing 'phy' from 'port'
Our past DDI-based Intel platforms have had a fixed DDI<->PHY mapping.
Because of this, both the bspec documentation and our i915 code has used
the term "port" when talking about either DDI's or PHY's; it was always
easy to tell what terms like "Port A" were referring to from the
context.
Unfortunately this is starting to break down now that EHL allows PHY-A
to be driven by either DDI-A or DDI-D. Is a setup with DDI-D driving
PHY-A considered "Port A" or "Port D?" The answer depends on which
register we're working with, and even the bspec doesn't do a great job
of clarifying this.
Let's try to be more explicit about whether we're talking about the DDI
or the PHY on gen11+ by using 'port' to refer to the DDI and creating a
new 'enum phy' namespace to refer to the PHY in use.
This patch just adds the new PHY namespace, new phy-based versions of
intel_port_is_*(), and a helper to convert a port to a PHY.
Transitioning various areas of the code over to using the PHY namespace
will be done in subsequent patches to make review easier. We'll remove
the intel_port_is_*() functions at the end of the series when we
transition all callers over to using the PHY-based versions.
v2:
- Convert a few more 'port' uses to 'phy.' (Sparse)
v3:
- Switch DDI_CLK_SEL() back to 'port.' (Jose)
- Add a code comment clarifying why DPCLKA_CFGCR0_ICL needs to use PHY
for its bit definitions, even though the register description is
given in terms of DDI.
- To avoid confusion, switch CNL's DPCLKA_CFGCR0 defines back to using
port and create separate ICL+ definitions that work in terms of PHY.
v4:
- Rebase and resolve conflicts with Imre's TC series.
- This patch now just adds the namespace and a few convenience
functions; the important changes are now split out into separate
patches to make review easier.
Suggested-by: Ville Syrjala
Cc: José Roberto de Souza
Cc: Lucas De Marchi
Cc: Ville Syrjälä
Cc: Imre Deak
Cc: Jani Nikula
Signed-off-by: Matt Roper
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 32 +++-
drivers/gpu/drm/i915/display/intel_display.h | 16 ++
drivers/gpu/drm/i915/intel_drv.h | 2 ++
3 files changed, 49 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index f07081815b80..43caee6d3c2f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6685,6 +6685,20 @@ bool intel_port_is_combophy(struct drm_i915_private
*dev_priv, enum port port)
return false;
}
+bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
+{
+ if (phy == PHY_NONE)
+ return false;
+
+ if (IS_ELKHARTLAKE(dev_priv))
+ return phy <= PHY_C;
+
+ if (INTEL_GEN(dev_priv) >= 11)
+ return phy <= PHY_B;
+
+ return false;
+}
+
bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
{
if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
@@ -6693,9 +6707,25 @@ bool intel_port_is_tc(struct drm_i915_private *dev_priv,
enum port port)
return false;
}
+bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
+{
+ if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
+ return phy >= PHY_C && phy <= PHY_F;
+
+ return false;
+}
+
+enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
+{
+ if (IS_ELKHARTLAKE(i915) && port == PORT_D)
+ return PHY_A;
+
+ return (enum phy)port;
+}
+
enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port
port)
{
- if (!intel_port_is_tc(dev_priv, port))
+ if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
return PORT_TC_NONE;
return port - PORT_C;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index d296556ed82e..d53285fb883f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -228,6 +228,21 @@ struct intel_link_m_n {
u32 link_n;
};
+enum phy {
+ PHY_NONE = -1,
+
+ PHY_A = 0,
+ PHY_B,
+ PHY_C,
+ PHY_D,
+ PHY_E,
+ PHY_F,
+
+ I915_MAX_PHYS
+};
+
+#define phy_name(a) ((a) + 'A')
+
#define for_each_pipe(__dev_priv, __p) \
for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
@@ -356,5 +371,6 @@ void lpt_disable_clkout_dp(struct drm_i915_private
*dev_priv);
u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
u32 pixel_format, u64 modifier);
bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
+enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
#endif
diff --git a/drivers/gpu/drm/i915/intel_drv.h
[Intel-gfx] [PATCH v6 3/5] drm/i915/gen11: Convert combo PHY logic to use new 'enum phy' namespace
Convert the code that operates directly on gen11 combo PHY's to use the
new namespace. Combo PHY registers are those named "ICL_PORT_*" plus
ICL_DPHY_CHKN.
Note that a lot of the PHY programming happens in the MIPI DSI code.
For clarity I've added a for_each_dsi_phy() to loop over the phys used
by DSI. Since DSI always uses A & B on gen11, port=phy in all cases so
it doesn't actually matter which form we use in the DSI code. I've used
the phy iterator in code that's explicitly working with the combo PHY,
but left the rest of the DSI code using the port iterator and namespace
to minimize patch deltas. We can switch the rest of the DSI code over
to use phy terminology later if this winds up being too confusing.
v6: Drop an include of drm/i915_drm.h; that was previously included just
for the definition of 'enum port' which this patch removes the need
for. (Jose)
Cc: José Roberto de Souza
Signed-off-by: Matt Roper
Reviewed-by: Ville Syrjälä
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/icl_dsi.c| 127
.../gpu/drm/i915/display/intel_combo_phy.c| 143 +-
.../gpu/drm/i915/display/intel_combo_phy.h| 4 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 45 +++---
drivers/gpu/drm/i915/display/intel_display.h | 4 +
.../drm/i915/display/intel_display_power.c| 16 +-
drivers/gpu/drm/i915/display/intel_dsi.h | 12 +-
drivers/gpu/drm/i915/i915_reg.h | 74 -
8 files changed, 213 insertions(+), 212 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index 8f1324c2f539..4d952accfaaa 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -202,63 +202,62 @@ static void dsi_program_swing_and_deemphasis(struct
intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
- enum port port;
+ enum phy phy;
u32 tmp;
int lane;
- for_each_dsi_port(port, intel_dsi->ports) {
-
+ for_each_dsi_phy(phy, intel_dsi->phys) {
/*
* Program voltage swing and pre-emphasis level values as per
* table in BSPEC under DDI buffer programing
*/
- tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
+ tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK);
tmp |= SCALING_MODE_SEL(0x2);
tmp |= TAP2_DISABLE | TAP3_DISABLE;
tmp |= RTERM_SELECT(0x6);
- I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
+ I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp);
- tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
+ tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy));
tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK);
tmp |= SCALING_MODE_SEL(0x2);
tmp |= TAP2_DISABLE | TAP3_DISABLE;
tmp |= RTERM_SELECT(0x6);
- I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
+ I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp);
- tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
+ tmp = I915_READ(ICL_PORT_TX_DW2_LN0(phy));
tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
RCOMP_SCALAR_MASK);
tmp |= SWING_SEL_UPPER(0x2);
tmp |= SWING_SEL_LOWER(0x2);
tmp |= RCOMP_SCALAR(0x98);
- I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
+ I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), tmp);
- tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
+ tmp = I915_READ(ICL_PORT_TX_DW2_AUX(phy));
tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
RCOMP_SCALAR_MASK);
tmp |= SWING_SEL_UPPER(0x2);
tmp |= SWING_SEL_LOWER(0x2);
tmp |= RCOMP_SCALAR(0x98);
- I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
+ I915_WRITE(ICL_PORT_TX_DW2_AUX(phy), tmp);
- tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
+ tmp = I915_READ(ICL_PORT_TX_DW4_AUX(phy));
tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
CURSOR_COEFF_MASK);
tmp |= POST_CURSOR_1(0x0);
tmp |= POST_CURSOR_2(0x0);
tmp |= CURSOR_COEFF(0x3f);
- I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
+ I915_WRITE(ICL_PORT_TX_DW4_AUX(phy), tmp);
for (lane = 0; lane <= 3; lane++) {
/* Bspec: must not use GRP register for write */
- tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, port));
+ tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane,
[Intel-gfx] [PATCH v6 5/5] drm/i915/ehl: Enable DDI-D
EHL has four DDI's (DDI-A and DDI-D share combo PHY A).
Cc: José Roberto de Souza
Signed-off-by: Matt Roper
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index c2ed4bd8d56b..0286b97caa22 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15308,6 +15308,7 @@ static void intel_setup_outputs(struct drm_i915_private
*dev_priv)
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
intel_ddi_init(dev_priv, PORT_C);
+ intel_ddi_init(dev_priv, PORT_D);
icl_dsi_init(dev_priv);
} else if (INTEL_GEN(dev_priv) >= 11) {
intel_ddi_init(dev_priv, PORT_A);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 2/5] drm/i915/gen11: Program ICL_DPCLKA_CFGCR0 according to PHY
Although the register name implies that it operates on DDI's,
DPCLKA_CFGCR0_ICL actually needs to be programmed according to the PHY
that's in use. I.e., when using EHL's DDI-D on combo PHY A, the bits
described as "port A" in the bspec are what we need to set. The bspec
clarifies:
"[For EHL] DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA
Clock Select chooses the PLL for both DDIA and DDID and drives
port A in all cases."
Also, since the CNL DPCLKA_CFGCR0 bit defines are still port-based, we
create separate ICL-specific defines that accept the PHY rather than
trying to share the same bit definitions between CNL and ICL.
v5: Make icl_dpclka_cfgcr0_clk_off() take phy rather than port. When
splitting the original patch the hunk to handle this wound up too
late in the series. (Sparse)
v6: Since we're already changing this code,
s/DPCLKA_CFGCR0_ICL/ICL_DPCLKA_CFGCR0/ for consistency. (Jose)
Bspec: 33148
Cc: José Roberto de Souza
Signed-off-by: Matt Roper
Reviewed-by: Ville Syrjälä
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/icl_dsi.c | 33 ++
drivers/gpu/drm/i915/display/intel_ddi.c | 63
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 12 ++--
4 files changed, 67 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index 3cf95c34143c..8f1324c2f539 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -560,14 +560,16 @@ static void gen11_dsi_gate_clocks(struct intel_encoder
*encoder)
struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
u32 tmp;
enum port port;
+ enum phy phy;
mutex_lock(_priv->dpll_lock);
- tmp = I915_READ(DPCLKA_CFGCR0_ICL);
+ tmp = I915_READ(ICL_DPCLKA_CFGCR0);
for_each_dsi_port(port, intel_dsi->ports) {
- tmp |= DPCLKA_CFGCR0_DDI_CLK_OFF(port);
+ phy = intel_port_to_phy(dev_priv, port);
+ tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
}
- I915_WRITE(DPCLKA_CFGCR0_ICL, tmp);
+ I915_WRITE(ICL_DPCLKA_CFGCR0, tmp);
mutex_unlock(_priv->dpll_lock);
}
@@ -577,14 +579,16 @@ static void gen11_dsi_ungate_clocks(struct intel_encoder
*encoder)
struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
u32 tmp;
enum port port;
+ enum phy phy;
mutex_lock(_priv->dpll_lock);
- tmp = I915_READ(DPCLKA_CFGCR0_ICL);
+ tmp = I915_READ(ICL_DPCLKA_CFGCR0);
for_each_dsi_port(port, intel_dsi->ports) {
- tmp &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
+ phy = intel_port_to_phy(dev_priv, port);
+ tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
}
- I915_WRITE(DPCLKA_CFGCR0_ICL, tmp);
+ I915_WRITE(ICL_DPCLKA_CFGCR0, tmp);
mutex_unlock(_priv->dpll_lock);
}
@@ -595,23 +599,26 @@ static void gen11_dsi_map_pll(struct intel_encoder
*encoder,
struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
struct intel_shared_dpll *pll = crtc_state->shared_dpll;
enum port port;
+ enum phy phy;
u32 val;
mutex_lock(_priv->dpll_lock);
- val = I915_READ(DPCLKA_CFGCR0_ICL);
+ val = I915_READ(ICL_DPCLKA_CFGCR0);
for_each_dsi_port(port, intel_dsi->ports) {
- val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
- val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
+ phy = intel_port_to_phy(dev_priv, port);
+ val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+ val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
}
- I915_WRITE(DPCLKA_CFGCR0_ICL, val);
+ I915_WRITE(ICL_DPCLKA_CFGCR0, val);
for_each_dsi_port(port, intel_dsi->ports) {
- val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
+ phy = intel_port_to_phy(dev_priv, port);
+ val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
}
- I915_WRITE(DPCLKA_CFGCR0_ICL, val);
+ I915_WRITE(ICL_DPCLKA_CFGCR0, val);
- POSTING_READ(DPCLKA_CFGCR0_ICL);
+ POSTING_READ(ICL_DPCLKA_CFGCR0);
mutex_unlock(_priv->dpll_lock);
}
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 30e48609db1d..b5bc00c4e3fe 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2729,12 +2729,13 @@ u32 ddi_signal_levels(struct intel_dp *intel_dp)
static inline
u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
- enum port port)
+ enum phy phy)
{
- if (intel_port_is_combophy(dev_priv, port)) {
- return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
- } else if
[Intel-gfx] [PATCH v6 0/5] EHL port programming
Final revision which incorporates Jose's minor suggestions (renaming a register and dropping one #include) and triggers a final CI run. All patches are reviewed so this should be ready to apply once CI finishes. Previous series revisions were here: v4/5: https://lists.freedesktop.org/archives/intel-gfx/2019-July/204257.html v3: https://lists.freedesktop.org/archives/intel-gfx/2019-June/203287.html v1/2: https://lists.freedesktop.org/archives/intel-gfx/2019-June/202776.html Matt Roper (5): drm/i915/gen11: Start distinguishing 'phy' from 'port' drm/i915/gen11: Program ICL_DPCLKA_CFGCR0 according to PHY drm/i915/gen11: Convert combo PHY logic to use new 'enum phy' namespace drm/i915: Transition port type checks to phy checks drm/i915/ehl: Enable DDI-D drivers/gpu/drm/i915/display/icl_dsi.c| 152 +- drivers/gpu/drm/i915/display/intel_bios.c | 4 +- .../gpu/drm/i915/display/intel_combo_phy.c| 143 .../gpu/drm/i915/display/intel_combo_phy.h| 4 +- drivers/gpu/drm/i915/display/intel_ddi.c | 146 ++--- drivers/gpu/drm/i915/display/intel_display.c | 41 +++-- drivers/gpu/drm/i915/display/intel_display.h | 20 +++ .../drm/i915/display/intel_display_power.c| 20 +-- drivers/gpu/drm/i915/display/intel_dp.c | 15 +- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 11 +- drivers/gpu/drm/i915/display/intel_dsi.h | 12 +- drivers/gpu/drm/i915/i915_reg.h | 86 +- drivers/gpu/drm/i915/intel_drv.h | 4 +- 13 files changed, 365 insertions(+), 293 deletions(-) -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH xf86-video-intel v3 2/2] sna: Support 10bpc gamma via the GAMMA_LUT crtc property
Hi Ville,
now somebody just needs to merge these two 10 bit gamma lut patches
into intel-ddx?
thanks,
-mario
On Fri, May 17, 2019 at 3:51 PM Ville Syrjala
wrote:
>
> From: Ville Syrjälä
>
> Probe the GAMMA_LUT/GAMMA_LUT_SIZE props and utilize them when
> the running with > 8bpc.
>
> v2: s/sna_crtc_id/__sna_crtc_id/ in DBG since we have a sna_crtc
> v3: Fix the vg "bluered" typo (Mario)
> This time I even build tested with vg support
>
> Cc: Mario Kleiner
> Signed-off-by: Ville Syrjälä
> Reviewed-and-tested-by: Mario Kleiner
> ---
> src/sna/sna_display.c | 247 +++---
> 1 file changed, 208 insertions(+), 39 deletions(-)
>
> diff --git a/src/sna/sna_display.c b/src/sna/sna_display.c
> index 41edfec12839..d6210cc7bbc8 100644
> --- a/src/sna/sna_display.c
> +++ b/src/sna/sna_display.c
> @@ -127,6 +127,7 @@ struct local_mode_obj_get_properties {
> uint32_t obj_type;
> uint32_t pad;
> };
> +#define LOCAL_MODE_OBJECT_CRTC 0x
> #define LOCAL_MODE_OBJECT_PLANE 0x
>
> struct local_mode_set_plane {
> @@ -229,6 +230,11 @@ struct sna_crtc {
> } primary;
> struct list sprites;
>
> + struct drm_color_lut *gamma_lut;
> + uint64_t gamma_lut_prop;
> + uint64_t gamma_lut_blob;
> + uint32_t gamma_lut_size;
> +
> uint32_t mode_serial, flip_serial;
>
> uint32_t last_seq, wrap_seq;
> @@ -317,6 +323,9 @@ static void __sna_output_dpms(xf86OutputPtr output, int
> dpms, int fixup);
> static void sna_crtc_disable_cursor(struct sna *sna, struct sna_crtc *crtc);
> static bool sna_crtc_flip(struct sna *sna, struct sna_crtc *crtc,
> struct kgem_bo *bo, int x, int y);
> +static void sna_crtc_gamma_set(xf86CrtcPtr crtc,
> + CARD16 *red, CARD16 *green,
> + CARD16 *blue, int size);
>
> static bool is_zaphod(ScrnInfoPtr scrn)
> {
> @@ -3150,11 +3159,9 @@ sna_crtc_set_mode_major(xf86CrtcPtr crtc,
> DisplayModePtr mode,
>mode->VDisplay <= sna->mode.max_crtc_height);
>
> #if HAS_GAMMA
> - drmModeCrtcSetGamma(sna->kgem.fd, __sna_crtc_id(sna_crtc),
> - crtc->gamma_size,
> - crtc->gamma_red,
> - crtc->gamma_green,
> - crtc->gamma_blue);
> + sna_crtc_gamma_set(crtc,
> + crtc->gamma_red, crtc->gamma_green,
> + crtc->gamma_blue, crtc->gamma_size);
> #endif
>
> saved_kmode = sna_crtc->kmode;
> @@ -3212,12 +3219,44 @@ void sna_mode_adjust_frame(struct sna *sna, int x,
> int y)
>
> static void
> sna_crtc_gamma_set(xf86CrtcPtr crtc,
> - CARD16 *red, CARD16 *green, CARD16 *blue, int size)
> + CARD16 *red, CARD16 *green, CARD16 *blue, int size)
> {
> - assert(to_sna_crtc(crtc));
> - drmModeCrtcSetGamma(to_sna(crtc->scrn)->kgem.fd,
> - sna_crtc_id(crtc),
> - size, red, green, blue);
> + struct sna *sna = to_sna(crtc->scrn);
> + struct sna_crtc *sna_crtc = to_sna_crtc(crtc);
> + struct drm_color_lut *lut = sna_crtc->gamma_lut;
> + uint32_t blob_size = size * sizeof(lut[0]);
> + uint32_t blob_id;
> + int ret, i;
> +
> + DBG(("%s: gamma_size %d\n", __FUNCTION__, size));
> +
> + if (!lut) {
> + assert(size == 256);
> +
> + drmModeCrtcSetGamma(to_sna(crtc->scrn)->kgem.fd,
> + sna_crtc_id(crtc),
> + size, red, green, blue);
> + return;
> + }
> +
> + assert(size == sna_crtc->gamma_lut_size);
> +
> + for (i = 0; i < size; i++) {
> + lut[i].red = red[i];
> + lut[i].green = green[i];
> + lut[i].blue = blue[i];
> + }
> +
> + ret = drmModeCreatePropertyBlob(sna->kgem.fd, lut, blob_size,
> _id);
> + if (ret)
> + return;
> +
> + ret = drmModeObjectSetProperty(sna->kgem.fd,
> + sna_crtc->id, DRM_MODE_OBJECT_CRTC,
> + sna_crtc->gamma_lut_prop,
> + blob_id);
> +
> + drmModeDestroyPropertyBlob(sna->kgem.fd, blob_id);
> }
>
> static void
> @@ -3229,6 +3268,8 @@ sna_crtc_destroy(xf86CrtcPtr crtc)
> if (sna_crtc == NULL)
> return;
>
> + free(sna_crtc->gamma_lut);
> +
> list_for_each_entry_safe(sprite, sn, _crtc->sprites, link)
> free(sprite);
>
> @@ -3663,6 +3704,55 @@ bool sna_has_sprite_format(struct sna *sna, uint32_t
> format)
> return false;
> }
>
> +inline static bool prop_is_gamma_lut(const struct drm_mode_get_property
> *prop)
> +{
> + return prop_has_type_and_name(prop, 4, "GAMMA_LUT");
> +}
> +
> +inline static
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/userptr: Don't mark readonly objects as dirty
== Series Details == Series: drm/i915/userptr: Don't mark readonly objects as dirty URL : https://patchwork.freedesktop.org/series/63434/ State : success == Summary == CI Bug Log - changes from CI_DRM_6437_full -> Patchwork_13576_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13576_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#110854]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6437/shard-iclb2/igt@gem_exec_balan...@smoke.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13576/shard-iclb5/igt@gem_exec_balan...@smoke.html * igt@kms_cursor_crc@pipe-b-cursor-suspend: - shard-kbl: [PASS][3] -> [INCOMPLETE][4] ([fdo#103665]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6437/shard-kbl3/igt@kms_cursor_...@pipe-b-cursor-suspend.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13576/shard-kbl2/igt@kms_cursor_...@pipe-b-cursor-suspend.html * igt@kms_flip@2x-flip-vs-expired-vblank: - shard-glk: [PASS][5] -> [FAIL][6] ([fdo#105363]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6437/shard-glk1/igt@kms_f...@2x-flip-vs-expired-vblank.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13576/shard-glk3/igt@kms_f...@2x-flip-vs-expired-vblank.html * igt@kms_flip@modeset-vs-vblank-race: - shard-glk: [PASS][7] -> [FAIL][8] ([fdo#103060]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6437/shard-glk5/igt@kms_f...@modeset-vs-vblank-race.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13576/shard-glk6/igt@kms_f...@modeset-vs-vblank-race.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt: - shard-iclb: [PASS][9] -> [FAIL][10] ([fdo#103167]) +3 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6437/shard-iclb6/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-msflip-blt.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13576/shard-iclb2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-msflip-blt.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([fdo#108566]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6437/shard-apl2/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13576/shard-apl6/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-glk: [PASS][13] -> [INCOMPLETE][14] ([fdo#103359] / [k.org#198133]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6437/shard-glk6/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13576/shard-glk3/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html * igt@kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6437/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13576/shard-iclb5/igt@kms_psr@psr2_cursor_mmap_cpu.html * igt@kms_setmode@basic: - shard-kbl: [PASS][17] -> [FAIL][18] ([fdo#99912]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6437/shard-kbl4/igt@kms_setm...@basic.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13576/shard-kbl4/igt@kms_setm...@basic.html * igt@perf@blocking: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#110728]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6437/shard-skl6/igt@p...@blocking.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13576/shard-skl7/igt@p...@blocking.html * igt@perf_pmu@rc6: - shard-kbl: [PASS][21] -> [SKIP][22] ([fdo#109271]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6437/shard-kbl3/igt@perf_...@rc6.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13576/shard-kbl2/igt@perf_...@rc6.html Possible fixes * igt@gem_ctx_isolation@bcs0-s3: - shard-apl: [DMESG-WARN][23] ([fdo#108566]) -> [PASS][24] +3 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6437/shard-apl4/igt@gem_ctx_isolat...@bcs0-s3.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13576/shard-apl8/igt@gem_ctx_isolat...@bcs0-s3.html * igt@gem_softpin@noreloc-s3: - shard-skl: [INCOMPLETE][25] ([fdo#104108]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6437/shard-skl10/igt@gem_soft...@noreloc-s3.html [26]:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Initial support for Tiger Lake (rev3)
== Series Details == Series: Initial support for Tiger Lake (rev3) URL : https://patchwork.freedesktop.org/series/62726/ State : warning == Summary == $ dim checkpatch origin/drm-tip 5c5e5e6008d1 drm/i915: Add 4th pipe and transcoder 0cd4b6f0f2d1 drm/i915/tgl: add initial Tiger Lake definitions 777a2d8d8266 drm/i915/tgl: Introduce Tiger Lake PCH cb543d474e7a drm/i915/tgl: Add TGL PCH detection in virtualized environment 9b52a5d4d480 drm/i915/tgl: Add TGL PCI IDs -:34: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #34: FILE: include/drm/i915_pciids.h:587: +#define INTEL_TGL_12_IDS(info) \ + INTEL_VGA_DEVICE(0x9A49, info), \ + INTEL_VGA_DEVICE(0x9A40, info), \ + INTEL_VGA_DEVICE(0x9A59, info), \ + INTEL_VGA_DEVICE(0x9A60, info), \ + INTEL_VGA_DEVICE(0x9A68, info), \ + INTEL_VGA_DEVICE(0x9A70, info), \ + INTEL_VGA_DEVICE(0x9A78, info) -:34: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects? #34: FILE: include/drm/i915_pciids.h:587: +#define INTEL_TGL_12_IDS(info) \ + INTEL_VGA_DEVICE(0x9A49, info), \ + INTEL_VGA_DEVICE(0x9A40, info), \ + INTEL_VGA_DEVICE(0x9A59, info), \ + INTEL_VGA_DEVICE(0x9A60, info), \ + INTEL_VGA_DEVICE(0x9A68, info), \ + INTEL_VGA_DEVICE(0x9A70, info), \ + INTEL_VGA_DEVICE(0x9A78, info) total: 1 errors, 0 warnings, 1 checks, 21 lines checked 8e56a0e4bf92 x86/gpu: add TGL stolen memory support 7ad31e8ccdb5 drm/i915/tgl: Check if pipe D is fused 52cd60dca858 drm/i915/tgl: use TRANSCODER_EDP_VDSC on transcoder A 228a055462e0 drm/i915/tgl: Add power well support f5175d7ae1c3 drm/i915/tgl: Add power well to support 4th pipe 45b62a9eac96 drm/i915/tgl: Add new pll ids 91b16ba0eb18 drm/i915/tgl: Add pll manager 5e768170eebe drm/i915/tgl: Add additional ports for Tiger Lake 7787733b30b1 drm/i915/tgl: update ddi/tc clock_off bits -:24: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'port' - possible side-effects? #24: FILE: drivers/gpu/drm/i915/i915_reg.h:9726: +#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_C ? 24 : \ + (port) + 10)) -:26: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'tc_port' - possible side-effects? #26: FILE: drivers/gpu/drm/i915/i915_reg.h:9728: +#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < PORT_TC4 ? \ + (tc_port) + 12 : \ + (tc_port) - PORT_TC4 + 21)) total: 0 errors, 0 warnings, 2 checks, 14 lines checked 5ff6a19fe86f drm/i915/tgl: Add gmbus gpio pin to port mapping 93b16ee61a60 drm/i915/tgl: port to ddc pin mapping e7d46091155c drm/i915/tgl: select correct bit for port select 17b3e3c96fb6 drm/i915/tgl: extend intel_port_is_combophy/tc 33cbf7793050 drm/i915/tgl: init ddi port A-C for Tiger Lake 414c3ae9ddfd drm/i915/tgl: Add vbt value mapping for DDC Bus pin 9bb0ad3b4017 drm/i915/tgl: apply Display WA #1178 to fix type C dongles cd3414367161 drm/i915/gen12: MBUS B credit change a840d06f8c92 drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization cf688295aed2 drm/i915/tgl: Add DPLL registers 281d1bcfc226 drm/i915/tgl: Update DPLL clock reference register ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Record preemption counting for selftests (rev2)
== Series Details ==
Series: drm/i915/execlists: Record preemption counting for selftests (rev2)
URL : https://patchwork.freedesktop.org/series/63452/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6443 -> Patchwork_13587
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13587/
Known issues
Here are the changes found in Patchwork_13587 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_reloc@basic-softpin:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/fi-icl-u3/igt@gem_exec_re...@basic-softpin.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13587/fi-icl-u3/igt@gem_exec_re...@basic-softpin.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-dsi: [PASS][3] -> [FAIL][4] ([fdo#103167])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/fi-icl-dsi/igt@kms_frontbuffer_track...@basic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13587/fi-icl-dsi/igt@kms_frontbuffer_track...@basic.html
- fi-icl-u2: [PASS][5] -> [FAIL][6] ([fdo#103167])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13587/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@gem_mmap_gtt@basic-small-bo:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/fi-icl-u3/igt@gem_mmap_...@basic-small-bo.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13587/fi-icl-u3/igt@gem_mmap_...@basic-small-bo.html
* igt@i915_selftest@live_contexts:
- fi-skl-iommu: [INCOMPLETE][9] ([fdo#111050]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/fi-skl-iommu/igt@i915_selftest@live_contexts.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13587/fi-skl-iommu/igt@i915_selftest@live_contexts.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [FAIL][11] ([fdo#109635 ]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13587/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111050]: https://bugs.freedesktop.org/show_bug.cgi?id=111050
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
Participating hosts (51 -> 47)
--
Additional (1): fi-gdg-551
Missing(5): fi-kbl-soraka fi-byt-squawks fi-icl-y fi-byt-clapper
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6443 -> Patchwork_13587
CI_DRM_6443: 0a6f3e30283594af78f45c777d28c4d55ace9e35 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5092: 2a66ae6626d5583240509f84117d1345a799b75a @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13587: cbf17310d86913f03910528eb7570b3ed6d1c5dd @
git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13587/build_32bit.log
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1287: recipe for target 'modules' failed
make: *** [modules] Error 2
== Linux commits ==
cbf17310d869 drm/i915/execlists: Record preemption for selftests
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13587/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: add infrastructure to hold off preemption on a request
== Series Details ==
Series: drm/i915: add infrastructure to hold off preemption on a request
URL : https://patchwork.freedesktop.org/series/63451/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6443 -> Patchwork_13586
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13586/
Known issues
Here are the changes found in Patchwork_13586 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_create@basic-files:
- fi-icl-guc: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] /
[fdo#109100])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/fi-icl-guc/igt@gem_ctx_cre...@basic-files.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13586/fi-icl-guc/igt@gem_ctx_cre...@basic-files.html
* igt@i915_selftest@live_sanitycheck:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +1
similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/fi-icl-u3/igt@i915_selftest@live_sanitycheck.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13586/fi-icl-u3/igt@i915_selftest@live_sanitycheck.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: [PASS][5] -> [FAIL][6] ([fdo#103167])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13586/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@gem_mmap_gtt@basic-small-bo:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/fi-icl-u3/igt@gem_mmap_...@basic-small-bo.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13586/fi-icl-u3/igt@gem_mmap_...@basic-small-bo.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [FAIL][9] ([fdo#109635 ]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13586/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#111046 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111046
Participating hosts (51 -> 47)
--
Additional (1): fi-gdg-551
Missing(5): fi-kbl-soraka fi-byt-squawks fi-icl-y fi-byt-clapper
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6443 -> Patchwork_13586
CI_DRM_6443: 0a6f3e30283594af78f45c777d28c4d55ace9e35 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5092: 2a66ae6626d5583240509f84117d1345a799b75a @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13586: e5fe148bd5a7934037997b285221280a0f3b88ce @
git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13586/build_32bit.log
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1287: recipe for target 'modules' failed
make: *** [modules] Error 2
== Linux commits ==
e5fe148bd5a7 drm/i915: add infrastructure to hold off preemption on a request
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13586/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 2/2] drm/i915: Enable hotplug retry
On Tue, 2019-07-09 at 12:26 +0300, Timo Aaltonen wrote: > On 2.7.2019 23.41, Souza, Jose wrote: > > On Tue, 2019-07-02 at 23:29 +0300, Timo Aaltonen wrote: > > > On 2.7.2019 22.54, Souza, Jose wrote: > > > > Here a dmesg output of this patch working in a unpowered type-c > > > > dongle: > > > > https://gist.github.com/zehortigoza/93c54b03fb65237cc1a2e193acef61a8 > > > > > > > > With the latest type-c patches from Imre it is becoming really > > > > hard > > > > to > > > > reproduce this but is still possible, also looks like due some > > > > internal > > > > error on the dongle it being re-discovered by USB sub-system. > > > > > > > > I added this to the patches bellow have more log information: > > > > https://gist.github.com/zehortigoza/baecabeb7097b9322723b6caf5a9ced5 > > > > Let me know if you think this or something similar should be > > > > squashed > > > > to this patch, I think it is not necessary. > > > > > > FWIW, we've tested these on a WHL which is suffering from HDMI > > > unplug > > > still showing the display connected, and it's working fine now. > > > > > > > > > > Thanks, I will add your: > > > > Tested-by: Timo Aaltonen > > That's fine. When can we expect these to land on dinq? > > > As soon as someone reviews it. Imre can you review the the second patch? I will find someone to review the first one. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for Modular FIA (rev3)
== Series Details ==
Series: Modular FIA (rev3)
URL : https://patchwork.freedesktop.org/series/63175/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6443 -> Patchwork_13585
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/
Known issues
Here are the changes found in Patchwork_13585 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_create@basic-files:
- fi-icl-guc: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] /
[fdo#109100])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/fi-icl-guc/igt@gem_ctx_cre...@basic-files.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/fi-icl-guc/igt@gem_ctx_cre...@basic-files.html
* igt@i915_selftest@live_blt:
- fi-icl-dsi: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/fi-icl-dsi/igt@i915_selftest@live_blt.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/fi-icl-dsi/igt@i915_selftest@live_blt.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][5] -> [FAIL][6] ([fdo#109485])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: [PASS][7] -> [FAIL][8] ([fdo#103167])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@gem_mmap_gtt@basic-small-bo:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/fi-icl-u3/igt@gem_mmap_...@basic-small-bo.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/fi-icl-u3/igt@gem_mmap_...@basic-small-bo.html
* igt@i915_selftest@live_contexts:
- fi-skl-iommu: [INCOMPLETE][11] ([fdo#111050]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/fi-skl-iommu/igt@i915_selftest@live_contexts.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/fi-skl-iommu/igt@i915_selftest@live_contexts.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [FAIL][13] ([fdo#109635 ]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111050]: https://bugs.freedesktop.org/show_bug.cgi?id=111050
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
Participating hosts (51 -> 47)
--
Additional (1): fi-gdg-551
Missing(5): fi-kbl-soraka fi-byt-squawks fi-icl-y fi-byt-clapper
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6443 -> Patchwork_13585
CI_DRM_6443: 0a6f3e30283594af78f45c777d28c4d55ace9e35 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5092: 2a66ae6626d5583240509f84117d1345a799b75a @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13585: 6c698f3ecfafe1bdaf2926b97309135b7683923a @
git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/build_32bit.log
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1287: recipe for target 'modules' failed
make: *** [modules] Error 2
== Linux commits ==
6c698f3ecfaf drm/i915: Add modular FIA
63de0b2617be drm/i915: move
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Hold the vma manager lock while modifying mmap_offset (rev3)
== Series Details ==
Series: drm/i915/selftests: Hold the vma manager lock while modifying
mmap_offset (rev3)
URL : https://patchwork.freedesktop.org/series/63443/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6443 -> Patchwork_13584
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13584/
Known issues
Here are the changes found in Patchwork_13584 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_basic@bad-close:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/fi-icl-u3/igt@gem_ba...@bad-close.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13584/fi-icl-u3/igt@gem_ba...@bad-close.html
* igt@i915_module_load@reload:
- fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/fi-blb-e6850/igt@i915_module_l...@reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13584/fi-blb-e6850/igt@i915_module_l...@reload.html
Possible fixes
* igt@i915_selftest@live_contexts:
- fi-skl-iommu: [INCOMPLETE][5] ([fdo#111050]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/fi-skl-iommu/igt@i915_selftest@live_contexts.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13584/fi-skl-iommu/igt@i915_selftest@live_contexts.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [FAIL][7] ([fdo#109635 ]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13584/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111050]: https://bugs.freedesktop.org/show_bug.cgi?id=111050
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
Participating hosts (51 -> 46)
--
Additional (1): fi-gdg-551
Missing(6): fi-kbl-soraka fi-byt-squawks fi-icl-dsi fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6443 -> Patchwork_13584
CI_DRM_6443: 0a6f3e30283594af78f45c777d28c4d55ace9e35 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5092: 2a66ae6626d5583240509f84117d1345a799b75a @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13584: c4b219af1d649a7b25a4f993c581091febbcd41a @
git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13584/build_32bit.log
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1287: recipe for target 'modules' failed
make: *** [modules] Error 2
== Linux commits ==
c4b219af1d64 drm/i915/selftests: Hold the vma manager lock while modifying
mmap_offset
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13584/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fix reporting of size of created GEM object
== Series Details == Series: drm/i915: Fix reporting of size of created GEM object URL : https://patchwork.freedesktop.org/series/63421/ State : success == Summary == CI Bug Log - changes from CI_DRM_6436_full -> Patchwork_13575_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13575_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_tiled_swapping@non-threaded: - shard-glk: [PASS][1] -> [DMESG-WARN][2] ([fdo#108686]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6436/shard-glk5/igt@gem_tiled_swapp...@non-threaded.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13575/shard-glk3/igt@gem_tiled_swapp...@non-threaded.html * igt@i915_pm_rps@reset: - shard-iclb: [PASS][3] -> [FAIL][4] ([fdo#102250] / [fdo#108059]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6436/shard-iclb2/igt@i915_pm_...@reset.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13575/shard-iclb6/igt@i915_pm_...@reset.html * igt@i915_suspend@debugfs-reader: - shard-skl: [PASS][5] -> [INCOMPLETE][6] ([fdo#104108]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6436/shard-skl5/igt@i915_susp...@debugfs-reader.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13575/shard-skl6/igt@i915_susp...@debugfs-reader.html * igt@i915_suspend@sysfs-reader: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([fdo#108566]) +5 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6436/shard-apl4/igt@i915_susp...@sysfs-reader.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13575/shard-apl7/igt@i915_susp...@sysfs-reader.html * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy: - shard-glk: [PASS][9] -> [FAIL][10] ([fdo#104873]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6436/shard-glk8/igt@kms_cursor_leg...@2x-flip-vs-cursor-legacy.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13575/shard-glk2/igt@kms_cursor_leg...@2x-flip-vs-cursor-legacy.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([fdo#108566]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6436/shard-kbl3/igt@kms_f...@flip-vs-suspend-interruptible.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13575/shard-kbl2/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_flip@plain-flip-fb-recreate: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#100368]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6436/shard-skl7/igt@kms_f...@plain-flip-fb-recreate.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13575/shard-skl10/igt@kms_f...@plain-flip-fb-recreate.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt: - shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#103167]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6436/shard-iclb3/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-indfb-draw-blt.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13575/shard-iclb1/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-indfb-draw-blt.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108040]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6436/shard-skl8/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-indfb-draw-render.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13575/shard-skl10/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-indfb-draw-render.html * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6436/shard-skl8/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13575/shard-skl10/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145] / [fdo#110403]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6436/shard-skl1/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13575/shard-skl9/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html * igt@kms_psr@psr2_primary_mmap_cpu: - shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6436/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13575/shard-iclb1/igt@kms_psr@psr2_primary_mmap_cpu.html * igt@kms_rotation_crc@multiplane-rotation-cropping-top: -
[Intel-gfx] [PATCH v3 16/25] drm/i915/tgl: port to ddc pin mapping
Make the icl function generic so it is based on phy type and can be
applied to tgl as well.
I checked if this could not apply to EHL as well, but unfortunately
there the HPD and DDC/GMBUS pins for DDI C are mapped to TypeC Port 1
even though it doesn't have TC phy.
v2: don't add a separate function for TGL, but rather reuse the ICL one
(suggested by Rodrigo)
Cc: Anusha Srivatsa
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 34 +--
1 file changed, 7 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 0ebec69bbbfc..dfdcd25eda02 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2930,33 +2930,13 @@ static u8 cnp_port_to_ddc_pin(struct drm_i915_private
*dev_priv,
static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port
port)
{
- u8 ddc_pin;
+ if (intel_port_is_combophy(dev_priv, port))
+ return GMBUS_PIN_1_BXT + port;
+ else if (intel_port_is_tc(dev_priv, port))
+ return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port);
- switch (port) {
- case PORT_A:
- ddc_pin = GMBUS_PIN_1_BXT;
- break;
- case PORT_B:
- ddc_pin = GMBUS_PIN_2_BXT;
- break;
- case PORT_C:
- ddc_pin = GMBUS_PIN_9_TC1_ICP;
- break;
- case PORT_D:
- ddc_pin = GMBUS_PIN_10_TC2_ICP;
- break;
- case PORT_E:
- ddc_pin = GMBUS_PIN_11_TC3_ICP;
- break;
- case PORT_F:
- ddc_pin = GMBUS_PIN_12_TC4_ICP;
- break;
- default:
- MISSING_CASE(port);
- ddc_pin = GMBUS_PIN_2_BXT;
- break;
- }
- return ddc_pin;
+ WARN(1, "Unknown port:%c\n", port_name(port));
+ return GMBUS_PIN_2_BXT;
}
static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port
port)
@@ -3019,7 +2999,7 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private
*dev_priv,
if (HAS_PCH_MCC(dev_priv))
ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
- else if (HAS_PCH_ICP(dev_priv))
+ else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_ICP(dev_priv))
ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
else if (HAS_PCH_CNP(dev_priv))
ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
--
2.21.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/execlists: Record preemption for selftests
Put back the preemption counters lost in commit 22b7a426bbe1
("drm/i915/execlists: Preempt-to-busy") so that our selftests that
assert no preemption took place continue to function.
v2: But a timeslice is only a "soft" preemption!
Fixes: 22b7a426bbe1 ("drm/i915/execlists: Preempt-to-busy")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index d16d65e195b0..1121dba99c94 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -921,6 +921,11 @@ enable_timeslice(struct intel_engine_cs *engine)
return last && need_timeslice(engine, last);
}
+static void record_preemption(struct intel_engine_execlists *execlists)
+{
+ (void)I915_SELFTEST_ONLY(execlists->preempt_hang.count++);
+}
+
static void execlists_dequeue(struct intel_engine_cs *engine)
{
struct intel_engine_execlists * const execlists = >execlists;
@@ -989,6 +994,8 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
last->fence.seqno,
last->sched.attr.priority,
execlists->queue_priority_hint);
+ record_preemption(execlists);
+
/*
* Don't let the RING_HEAD advance past the breadcrumb
* as we unwind (and until we resubmit) so that we do
--
2.22.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/execlists: Record preemption counting for selftests
Put back the preemption counters lost in commit 22b7a426bbe1
("drm/i915/execlists: Preempt-to-busy") so that our selftests that
assert no preemption took place continue to function.
Fixes: 22b7a426bbe1 ("drm/i915/execlists: Preempt-to-busy")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index d16d65e195b0..955a7994cb7b 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -921,6 +921,11 @@ enable_timeslice(struct intel_engine_cs *engine)
return last && need_timeslice(engine, last);
}
+static void record_preemption(struct intel_engine_execlists *execlists)
+{
+ (void)I915_SELFTEST_ONLY(execlists->preempt_hang.count++);
+}
+
static void execlists_dequeue(struct intel_engine_cs *engine)
{
struct intel_engine_execlists * const execlists = >execlists;
@@ -989,6 +994,8 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
last->fence.seqno,
last->sched.attr.priority,
execlists->queue_priority_hint);
+ record_preemption(execlists);
+
/*
* Don't let the RING_HEAD advance past the breadcrumb
* as we unwind (and until we resubmit) so that we do
@@ -1022,6 +1029,7 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
last->fence.seqno,
last->sched.attr.priority,
execlists->queue_priority_hint);
+ record_preemption(execlists);
ring_set_paused(engine, 1);
defer_active(engine);
--
2.22.0
___
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[Intel-gfx] [PATCH] drm/i915: add infrastructure to hold off preemption on a request
From: Lionel Landwerlin
We want to set this flag in the next commit on requests containing
perf queries so that the result of the perf query can just be a delta
of global counters, rather than doing post processing of the OA
buffer.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
[ickle: add basic selftest for nopreempt]
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 11 ++
drivers/gpu/drm/i915/gt/selftest_lrc.c | 109
drivers/gpu/drm/i915/i915_priolist_types.h | 10 ++
drivers/gpu/drm/i915/i915_request.c | 4 +-
drivers/gpu/drm/i915/i915_request.h | 15 ++-
drivers/gpu/drm/i915/intel_guc_submission.c | 13 ++-
drivers/gpu/drm/i915/intel_pm.c | 5 +-
7 files changed, 161 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index e1ae1399c72b..d16d65e195b0 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -258,6 +258,17 @@ static int effective_prio(const struct i915_request *rq)
{
int prio = rq_prio(rq);
+ /*
+* If this request is special and must not be interrupted at any
+* cost, so be it. Note we are only checking the most recent request
+* in the context and so may be masking an earlier vip request. It
+* is hoped that under the conditions where nopreempt is used, this
+* will not matter (i.e. all requests to that context will be
+* nopreempt for as long as desired).
+*/
+ if (i915_request_has_nopreempt(rq))
+ prio = I915_PRIORITY_UNPREEMPTABLE;
+
/*
* On unwinding the active request, we give it a priority bump
* if it has completed waiting on any semaphore. If we know that
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 672bdaa66540..b9b881ab8e7c 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -721,6 +721,114 @@ static void preempt_client_fini(struct preempt_client *c)
kernel_context_close(c->ctx);
}
+static int live_nopreempt(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ struct intel_engine_cs *engine;
+ struct preempt_client a, b;
+ enum intel_engine_id id;
+ intel_wakeref_t wakeref;
+ int err = -ENOMEM;
+
+ /*
+* Verify that we can disable preemption for an individual request
+* that may be being observed and not want to be interrupted.
+*/
+
+ if (!HAS_LOGICAL_RING_PREEMPTION(i915))
+ return 0;
+
+ mutex_lock(>drm.struct_mutex);
+ wakeref = intel_runtime_pm_get(>runtime_pm);
+
+ if (preempt_client_init(i915, ))
+ goto err_unlock;
+ if (preempt_client_init(i915, ))
+ goto err_client_a;
+ b.ctx->sched.priority = I915_USER_PRIORITY(I915_PRIORITY_MAX);
+
+ for_each_engine(engine, i915, id) {
+ struct i915_request *rq_a, *rq_b;
+
+ if (!intel_engine_has_preemption(engine))
+ continue;
+
+ engine->execlists.preempt_hang.count = 0;
+
+ rq_a = igt_spinner_create_request(,
+ a.ctx, engine,
+ MI_ARB_CHECK);
+ if (IS_ERR(rq_a)) {
+ err = PTR_ERR(rq_a);
+ goto err_client_b;
+ }
+
+ /* Low priority client, but unpreemptable! */
+ rq_a->flags |= I915_REQUEST_NOPREEMPT;
+
+ i915_request_add(rq_a);
+ if (!igt_wait_for_spinner(, rq_a)) {
+ pr_err("First client failed to start\n");
+ goto err_wedged;
+ }
+
+ rq_b = igt_spinner_create_request(,
+ b.ctx, engine,
+ MI_ARB_CHECK);
+ if (IS_ERR(rq_b)) {
+ err = PTR_ERR(rq_b);
+ goto err_client_b;
+ }
+
+ i915_request_add(rq_b);
+
+ /* B is much more important than A! (But A is unpreemptable.) */
+ GEM_BUG_ON(rq_prio(rq_b) <= rq_prio(rq_a));
+
+ /* Wait long enough for preemption and timeslicing */
+ if (igt_wait_for_spinner(, rq_b)) {
+ pr_err("Second client started too early!\n");
+ goto err_wedged;
+ }
+
+ igt_spinner_end();
+
+ if (!igt_wait_for_spinner(, rq_b)) {
+ pr_err("Second client failed to start\n");
+ goto err_wedged;
+ }
+
+ igt_spinner_end();
+
+ if
Re: [Intel-gfx] [PATCH v2 16/25] drm/i915/tgl: port to ddc pin mapping
On Tue, Jul 09, 2019 at 05:11:08AM -0700, Rodrigo Vivi wrote:
On Mon, Jul 08, 2019 at 04:16:20PM -0700, Lucas De Marchi wrote:
From: Mahesh Kumar
Create a helper function to get ddc pin according to port number.
Could you please explain why we can't simply reuse the icl one?
I couldn't find a new table for tgl on bspec...
Cc: Anusha Srivatsa
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 0ebec69bbbfc..3b33e7626d7c 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2981,6 +2981,18 @@ static u8 mcc_port_to_ddc_pin(struct drm_i915_private
*dev_priv, enum port port)
return ddc_pin;
}
+static u8 tgp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
+ enum port port)
+{
+ if (intel_port_is_combophy(dev_priv, port))
+ return GMBUS_PIN_1_BXT + port;
+ else if (intel_port_is_tc(dev_priv, port))
+ return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port);
okay, this seems better than the table we have on icl func,
but couldn't we just change the icl one?
I think initially we had it implemented like in the icl function, and on
tgl we have the additional combo port. With the reworks to use
intel_port_to_tc() I didn't realize this now applies to icl as well.
I will change it in next version.
Thanks
Lucas De Marchi
+
+ WARN(1, "Unknown port:%c\n", port_name(port));
+ return GMBUS_PIN_2_BXT;
+}
+
static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
enum port port)
{
@@ -3017,7 +3029,9 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private
*dev_priv,
return info->alternate_ddc_pin;
}
- if (HAS_PCH_MCC(dev_priv))
+ if (HAS_PCH_TGP(dev_priv))
+ ddc_pin = tgp_port_to_ddc_pin(dev_priv, port);
+ else if (HAS_PCH_MCC(dev_priv))
ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
else if (HAS_PCH_ICP(dev_priv))
ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
--
2.21.0
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Re: [Intel-gfx] [PATCH v2 10/25] drm/i915/tgl: Add power well to support 4th pipe
On Tue, Jul 09, 2019 at 04:57:32AM -0700, Rodrigo Vivi wrote:
On Mon, Jul 08, 2019 at 04:16:14PM -0700, Lucas De Marchi wrote:
From: Mika Kahola
Add power well 5 to support 4th pipe and transcoder on TGL.
Cc: James Ausmus
Cc: Imre Deak
Signed-off-by: Mika Kahola
Signed-off-by: Lucas De Marchi
---
.../drm/i915/display/intel_display_power.c| 30 ---
.../drm/i915/display/intel_display_power.h| 3 ++
drivers/gpu/drm/i915/i915_reg.h | 3 +-
3 files changed, 31 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index c3f42169831f..455f9aab188d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -37,18 +37,24 @@ intel_display_power_domain_str(struct drm_i915_private
*i915,
return "PIPE_B";
case POWER_DOMAIN_PIPE_C:
return "PIPE_C";
+ case POWER_DOMAIN_PIPE_D:
+ return "PIPE_D";
case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
return "PIPE_A_PANEL_FITTER";
case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
return "PIPE_B_PANEL_FITTER";
case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
return "PIPE_C_PANEL_FITTER";
+ case POWER_DOMAIN_PIPE_D_PANEL_FITTER:
+ return "PIPE_D_PANEL_FITTER";
case POWER_DOMAIN_TRANSCODER_A:
return "TRANSCODER_A";
case POWER_DOMAIN_TRANSCODER_B:
return "TRANSCODER_B";
case POWER_DOMAIN_TRANSCODER_C:
return "TRANSCODER_C";
+ case POWER_DOMAIN_TRANSCODER_D:
+ return "TRANSCODER_D";
case POWER_DOMAIN_TRANSCODER_EDP:
return "TRANSCODER_EDP";
case POWER_DOMAIN_TRANSCODER_EDP_VDSC:
@@ -2451,7 +2457,6 @@ void intel_display_power_put(struct drm_i915_private
*dev_priv,
* - DDI_A
* - FBC
*/
-/* TODO: TGL_PW_5_POWER_DOMAINS: PIPE_D */
#define ICL_PW_4_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_C) | \
BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
@@ -2539,7 +2544,13 @@ void intel_display_power_put(struct drm_i915_private
*dev_priv,
#define ICL_AUX_TBT4_IO_POWER_DOMAINS (\
BIT_ULL(POWER_DOMAIN_AUX_TBT4))
+#define TGL_PW_5_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_D) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
#define TGL_PW_4_POWER_DOMAINS ( \
+ TGL_PW_5_POWER_DOMAINS |\
why?
not sure I understand this one. Are you saying we shouldn't have a new
power well for pipe d? How would we handle the different ctl?
BIT_ULL(POWER_DOMAIN_PIPE_C) | \
BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
BIT_ULL(POWER_DOMAIN_INIT))
@@ -2549,7 +2560,7 @@ void intel_display_power_put(struct drm_i915_private
*dev_priv,
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |\
BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |\
- /* TODO: TRANSCODER_D */\
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_D) |\
BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_LANES) | \
BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO) | \
@@ -3882,7 +3893,7 @@ static const struct i915_power_well_desc
tgl_power_wells[] = {
},
{
.name = "power well 4",
- .domains = ICL_PW_4_POWER_DOMAINS,
+ .domains = TGL_PW_4_POWER_DOMAINS,
why?
this is a leftover from v1 and should be squashed on previous patch, my
bad. In v1 we were reusing the ICL definitions. I changed in this
revision and forgot to squash this change there. I will send a new
version
thanks
Lucas De Marchi
.ops = _power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -3892,7 +3903,18 @@ static const struct i915_power_well_desc
tgl_power_wells[] = {
.hsw.irq_pipe_mask = BIT(PIPE_C),
}
},
- /* TODO: power well 5 for pipe D */
+ {
+ .name = "power well 5",
+ .domains = TGL_PW_5_POWER_DOMAINS,
+ .ops = _power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = _power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_PW_5,
+ .hsw.has_fuses = true,
+ .hsw.irq_pipe_mask = BIT(PIPE_D),
+ },
+ },
};
static int
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
b/drivers/gpu/drm/i915/display/intel_display_power.h
index
Re: [Intel-gfx] [PATCH v2 08/25] drm/i915/tgl: use TRANSCODER_EDP_VDSC on transcoder A
On Mon, Jul 08, 2019 at 06:07:17PM -0700, Jose Souza wrote:
On Mon, 2019-07-08 at 16:16 -0700, Lucas De Marchi wrote:
From: José Roberto de Souza
On TGL the special EDP transcoder is gone and it should be handled by
transcoder A.
v2 (Lucas):
- Reuse POWER_DOMAIN_TRANSCODER_EDP_VDSC (suggested by Ville)
- Use crtc->dev since new_crtc_state->state may be NULL on atomic
commit (suggested by Maarten)
As we are reusing would be nice also rename it to something like:
POWER_DOMAIN_TRANSCODER_VDSC_PW2
POWER_DOMAIN_LOW_POWER_TRANSCODER_VDSC /
POWER_DOMAIN_LP_TRANSCODER_VDSC
as it is still being used for EDP, I didn't think the rename was worth.
Lucas De Marchi
Cc: Imre Deak
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
b/drivers/gpu/drm/i915/display/intel_vdsc.c
index ffec807b8960..c27912f552f0 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -459,16 +459,19 @@ int intel_dp_compute_dsc_params(struct intel_dp
*intel_dp,
enum intel_display_power_domain
intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
{
+ struct drm_i915_private *i915 = to_i915(crtc_state->base.crtc-
>dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
/*
-* On ICL VDSC/joining for eDP transcoder uses a separate power
well PW2
-* This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
+* On ICL+ VDSC/joining for eDP/A transcoder uses a separate
power well
+* PW2. This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power
domain.
* For any other transcoder, VDSC/joining uses the power well
associated
* with the pipe/transcoder in use. Hence another reference on
the
* transcoder power domain will suffice.
*/
- if (cpu_transcoder == TRANSCODER_EDP)
+ if (INTEL_GEN(i915) >= 12 && cpu_transcoder == TRANSCODER_A)
+ return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
+ else if (cpu_transcoder == TRANSCODER_EDP)
return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
else
return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
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Re: [Intel-gfx] [PATCH v2 24/25] drm/i915/tgl: Add DPLL registers
On Tue, Jul 09, 2019 at 03:56:51PM +0300, Ville Syrjälä wrote:
On Mon, Jul 08, 2019 at 04:16:28PM -0700, Lucas De Marchi wrote:
On TGL the port programming for combophy is very similar to ICL, so
adapt the callers to possibly use the different register values.
Cc: Vandita Kulkarni
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 24 +++
drivers/gpu/drm/i915/i915_reg.h | 15
2 files changed, 34 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index ae1c552d7afb..330b42a1f54e 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3113,8 +3113,13 @@ static bool icl_pll_get_hw_state(struct drm_i915_private
*dev_priv,
if (!(val & PLL_ENABLE))
goto out;
- hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
- hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
+ if (INTEL_GEN(dev_priv) >= 12) {
+ hw_state->cfgcr0 = I915_READ(TGL_DPLL_CFGCR0(id));
+ hw_state->cfgcr1 = I915_READ(TGL_DPLL_CFGCR1(id));
+ } else {
+ hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
+ hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
+ }
ret = true;
out:
@@ -3148,10 +3153,19 @@ static void icl_dpll_write(struct drm_i915_private
*dev_priv,
{
struct intel_dpll_hw_state *hw_state = >state.hw_state;
const enum intel_dpll_id id = pll->info->id;
+ i915_reg_t cfgcr0_reg, cfgcr1_reg;
+
+ if (INTEL_GEN(dev_priv) >= 12) {
+ cfgcr0_reg = TGL_DPLL_CFGCR0(id);
+ cfgcr1_reg = TGL_DPLL_CFGCR1(id);
+ } else {
+ cfgcr0_reg = ICL_DPLL_CFGCR0(id);
+ cfgcr1_reg = ICL_DPLL_CFGCR1(id);
+ }
- I915_WRITE(ICL_DPLL_CFGCR0(id), hw_state->cfgcr0);
- I915_WRITE(ICL_DPLL_CFGCR1(id), hw_state->cfgcr1);
- POSTING_READ(ICL_DPLL_CFGCR1(id));
+ I915_WRITE(cfgcr0_reg, hw_state->cfgcr0);
+ I915_WRITE(cfgcr1_reg, hw_state->cfgcr1);
+ POSTING_READ(cfgcr1_reg);
}
static void icl_mg_pll_write(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fbcc7981c8c4..84c04ea67ec8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -242,6 +242,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
+#define _MMIO_PLL3(pll, a, b, c) _MMIO(_PICK(pll, a, b, c))
/*
* Device info offset array based helpers for groups of registers with unevenly
@@ -9958,6 +9959,20 @@ enum skl_power_gate {
#define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \
_ICL_DPLL1_CFGCR1)
+#define _TGL_DPLL0_CFGCR0 0x164284
+#define _TGL_DPLL1_CFGCR0 0x16428C
+#define _TGL_TBTPLL_CFGCR0 0x16429C
What about DPLL4?
not all TGL skus have DPLL4. The ones that do (and were not tested
here), are very different from what is done for EHL so we can't reuse
the implementation. I will leave the DPLL4 on TGL for later, when it
makes sense to add it.
Lucas De Marchi
In fact looks like the ICL counterparts are borked even for ehl DPLL4.
+#define TGL_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
+ _TGL_DPLL1_CFGCR0, \
+ _TGL_TBTPLL_CFGCR0)
+
+#define _TGL_DPLL0_CFGCR1 0x164288
+#define _TGL_DPLL1_CFGCR1 0x164290
+#define _TGL_TBTPLL_CFGCR1 0x1642A0
+#define TGL_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
+ _TGL_DPLL1_CFGCR1, \
+ _TGL_TBTPLL_CFGCR1)
+
/* BXT display engine PLL */
#define BXT_DE_PLL_CTL _MMIO(0x6d000)
#define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */
--
2.21.0
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v2 22/25] drm/i915/gen12: MBUS B credit change
On Mon, Jul 08, 2019 at 04:16:26PM -0700, Lucas De Marchi wrote:
> From: Rodrigo Vivi
>
> Previously, the recommended B credit for all platforms was 24 / number
> of pipes, which would give 6 for newer platforms with 4 pipes. However 6
> is not enough and we need 12 on these cases.
>
> We also need a different BW credit for these platforms.
>
> Cc: Arthur J Runyan
> Signed-off-by: Rodrigo Vivi
> Signed-off-by: Lucas De Marchi
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 10 --
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 9ccf58ff4dba..9a5d04a2ab3e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6423,8 +6423,14 @@ static void icl_pipe_mbus_enable(struct intel_crtc
> *crtc)
> u32 val;
>
> val = MBUS_DBOX_A_CREDIT(2);
> - val |= MBUS_DBOX_BW_CREDIT(1);
> - val |= MBUS_DBOX_B_CREDIT(8);
> +
> + if (INTEL_GEN(dev_priv) >= 12) {
> + val |= MBUS_DBOX_BW_CREDIT(2);
> + val |= MBUS_DBOX_B_CREDIT(12);
> + } else {
> + val |= MBUS_DBOX_BW_CREDIT(1);
> + val |= MBUS_DBOX_B_CREDIT(8);
> + }
>
> I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
> }
> --
> 2.21.0
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/2] drm/i915: Clear the shared PLL from the put_dplls() hook
On Tue, Jul 09, 2019 at 12:50:10AM +, Patchwork wrote: > == Series Details == > > Series: series starting with [v2,1/2] drm/i915: Clear the shared PLL from the > put_dplls() hook > URL : https://patchwork.freedesktop.org/series/63384/ > State : failure Thanks for the review pushed to -dinq. > > == Summary == > > CI Bug Log - changes from CI_DRM_6431_full -> Patchwork_13564_full > > > Summary > --- > > **FAILURE** > > Serious unknown changes coming with Patchwork_13564_full absolutely need to > be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_13564_full, please notify your bug team to allow > them > to document this new failure mode, which will reduce false positives in CI. > > > > Possible new issues > --- > > Here are the unknown changes that may have been introduced in > Patchwork_13564_full: > > ### IGT changes ### > > Possible regressions > > * igt@i915_selftest@live_mman: > - shard-iclb: [PASS][1] -> [DMESG-WARN][2] >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/shard-iclb8/igt@i915_selftest@live_mman.html >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13564/shard-iclb5/igt@i915_selftest@live_mman.html It's very likely unrelated AFAICS happening during driver loading before the first modeset, see the stacktrace below. Chris is working on a fix candidate: https://patchwork.freedesktop.org/patch/316784/?series=63443=3 <6> [93.046727] i915: Performing live selftests with st_random_seed=0x273bfdc9 st_timeout=1000 <6> [93.046730] i915: Running mman <6> [93.046747] i915: Running i915_gem_mman_live_selftests/igt_partial_tiling <7> [104.777473] check_partial_mapping: timed out before tiling=1 stride=261632 <7> [124.491128] check_partial_mapping: timed out before tiling=2 stride=262016 <6> [124.491156] i915: Running i915_gem_mman_live_selftests/igt_mmap_offset_exhaustion <7> [124.491236] [drm:intel_power_well_enable [i915]] enabling always-on <4> [124.645433] [ cut here ] <4> [124.645436] list_del corruption, c967b9c0->next is LIST_POISON1 (dead0100) <4> [124.645447] WARNING: CPU: 4 PID: 1583 at lib/list_debug.c:47 __list_del_entry_valid+0x4e/0x90 <4> [124.645448] Modules linked in: i915(+) snd_hda_codec_hdmi snd_hda_codec_realtek snd_hda_codec_generic x86_pkg_temp_thermal coretemp mei_hdcp crct10dif_pclmul e1000e snd_hda_codec cdc_ether crc32_pclmul usbnet mii snd_hwdep ghash_clmulni_intel snd_hda_core snd_pcm ptp pps_core mei_me mei prime_numbers [last unloaded: i915] <4> [124.645460] CPU: 4 PID: 1583 Comm: i915_selftest Tainted: G U 5.2.0-CI-Patchwork_13564+ #1 <4> [124.645461] Hardware name: Intel Corporation Ice Lake Client Platform/IceLake U DDR4 SODIMM PD RVP TLC, BIOS ICLSFWR1.R00.3234.A01.1906141750 06/14/2019 <4> [124.645463] RIP: 0010:__list_del_entry_valid+0x4e/0x90 <4> [124.645465] Code: 2e 48 8b 32 48 39 fe 75 3a 48 8b 50 08 48 39 f2 75 48 b8 01 00 00 00 c3 48 89 fe 48 89 c2 48 c7 c7 80 9f 0d 82 e8 12 44 bd ff <0f> 0b 31 c0 c3 48 89 fe 48 c7 c7 b8 9f 0d 82 e8 fe 43 bd ff 0f 0b <4> [124.645466] RSP: 0018:c967b910 EFLAGS: 00010286 <4> [124.645467] RAX: RBX: c967b990 RCX: <4> [124.645468] RDX: 0007 RSI: 8884809108e0 RDI: <4> [124.645469] RBP: 888496f61e28 R08: 789e198b R09: <4> [124.645470] R10: c967b968 R11: R12: c967b990 <4> [124.645472] R13: 888493ef7700 R14: 888496f61e10 R15: 88847faf8d40 <4> [124.645473] FS: 7fa107b16300() GS:88849fe0() knlGS: <4> [124.645474] CS: 0010 DS: ES: CR0: 80050033 <4> [124.645476] CR2: 55d84fe72748 CR3: 00047f502002 CR4: 00760ee0 <4> [124.645477] PKRU: 5554 <4> [124.645478] Call Trace: <4> [124.645481] rm_hole+0x17/0x80 <4> [124.645483] drm_mm_remove_node+0x23a/0x370 <4> [124.645534] igt_mmap_offset_exhaustion+0x34f/0x750 [i915] <4> [124.645582] __i915_subtests+0xb8/0x210 [i915] <4> [124.645621] ? i915_live_selftests+0x60/0x60 [i915] <4> [124.645690] ? __i915_nop_setup+0x10/0x10 [i915] <4> [124.645731] __run_selftests+0x112/0x170 [i915] <4> [124.645765] i915_live_selftests+0x2c/0x60 [i915] <4> [124.645800] i915_pci_probe+0x83/0x1a0 [i915] <4> [124.645803] ? _raw_spin_unlock_irqrestore+0x39/0x60 <4> [124.646414] pci_device_probe+0x9e/0x120 <4> [124.646417] really_probe+0xea/0x3c0 <4> [124.646420] driver_probe_device+0x10b/0x120 <4> [124.646422] device_driver_attach+0x4a/0x50 <4> [124.646425] __driver_attach+0x97/0x130 <4> [124.646427] ? device_driver_attach+0x50/0x50 <4> [124.646428] bus_for_each_dev+0x74/0xc0 <4> [124.646441] bus_add_driver+0x13f/0x210 <4> [124.646443] ? 0xa04bb000 <4>
[Intel-gfx] [PATCH v3 2/4] drm/i915: fix include order in intel_tc.*
Separate local includes with a blank line and sort the groups alphabetically. v2: don't make intel_tc.h be the first include v3: don't make local includes be included first Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_tc.c | 2 +- drivers/gpu/drm/i915/display/intel_tc.h | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c index 1a9dd32fb0a5..0c969f6fd714 100644 --- a/drivers/gpu/drm/i915/display/intel_tc.c +++ b/drivers/gpu/drm/i915/display/intel_tc.c @@ -3,9 +3,9 @@ * Copyright © 2019 Intel Corporation */ +#include "i915_drv.h" #include "intel_display.h" #include "intel_dp_mst.h" -#include "i915_drv.h" #include "intel_tc.h" static const char *tc_port_mode_name(enum tc_port_mode mode) diff --git a/drivers/gpu/drm/i915/display/intel_tc.h b/drivers/gpu/drm/i915/display/intel_tc.h index 0d8411d4a91d..706c5bc050a5 100644 --- a/drivers/gpu/drm/i915/display/intel_tc.h +++ b/drivers/gpu/drm/i915/display/intel_tc.h @@ -6,8 +6,9 @@ #ifndef __INTEL_TC_H__ #define __INTEL_TC_H__ -#include #include +#include + #include "intel_drv.h" bool intel_tc_port_connected(struct intel_digital_port *dig_port); -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 09/25] drm/i915/tgl: Add power well support
On Mon, Jul 08, 2019 at 04:16:13PM -0700, Lucas De Marchi wrote:
> From: Imre Deak
>
> The patch adds the new power wells introduced by TGL (GEN 12) and
> maps these to existing/new power domains. The changes for GEN 12 wrt
> to GEN 11 are the following:
>
> - Transcoder#EDP removed from power well#1 (Transcoder#A used in
> low-power mode instead)
> - Transcoder#A is now backed by power well#1 instead of power well#3
> - The DDI#B/C combo PHY ports are now backed by power well#1 instead of
> power well#3
> - New power well#5 added for pipe#D functionality (TODO)
> - 2 additional TC ports (TC#5-6) backed by power well#3, 2 port
> specific IO power wells (only for the non-TBT modes) and 4 port
> specific AUX power wells (2-2 for TBT vs. non-TBT modes)
> - Power well#2 backs now VDSC/joining for pipe#A instead of VDSC for
> eDP and MIPI DSI (TODO)
>
> On TGL Port DDI#C changed to be a combo PHY (native DP/HDMI) and
> BSpec has renamed ports DDI#D-F to TC#4-6 respectively. Thus on ICL we
> have the following naming for ports:
>
> - Combo PHYs (native DP/HDMI):
> DDI#A-B
> - TBT/non-TBT (TC altmode, native DP/HDMI) PHYs:
> DDI#C-F
>
> Starting from GEN 12 we have the following naming for ports:
> - Combo PHYs (native DP/HDMI):
> DDI#A-C
> - TBT/non-TBT (TC altmode, native DP/HDMI) PHYs:
> DDI TC#1-6
>
> To save some space in the power domain enum the power domain naming in
> the driver reflects the above change, that is power domains TC#1-3 are
> added as aliases for DDI#D-F and new power domains are reserved for
> TC#4-6.
>
> v2 (Lucas):
> - Separate out the bits and definitions for TGL from the ICL ones.
> Fix use of TRANSCODER_EDP_VDSC, that is now the correct define since
> we don't define TRANSCODER_A_VDSC power domain to spare a one bit in
> the bitmask (suggested by Ville)
>
> Cc: Ville Syrjälä
> Cc: Anusha Srivatsa
> Cc: Rodrigo Vivi
> Cc: José Roberto de Souza
> Signed-off-by: Imre Deak
> Signed-off-by: Lucas De Marchi
> ---
> .../drm/i915/display/intel_display_power.c| 480 +-
> .../drm/i915/display/intel_display_power.h| 26 +-
> drivers/gpu/drm/i915/i915_debugfs.c | 3 +-
> drivers/gpu/drm/i915/i915_reg.h | 18 +
> 4 files changed, 508 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 7437fc71d289..c3f42169831f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -23,8 +23,11 @@ bool intel_display_power_well_is_enabled(struct
> drm_i915_private *dev_priv,
>enum i915_power_well_id power_well_id);
>
> const char *
> -intel_display_power_domain_str(enum intel_display_power_domain domain)
> +intel_display_power_domain_str(struct drm_i915_private *i915,
> +enum intel_display_power_domain domain)
> {
> + bool ddi_tc_ports = IS_GEN(i915, 12);
> +
> switch (domain) {
> case POWER_DOMAIN_DISPLAY_CORE:
> return "DISPLAY_CORE";
> @@ -61,11 +64,23 @@ intel_display_power_domain_str(enum
> intel_display_power_domain domain)
> case POWER_DOMAIN_PORT_DDI_C_LANES:
> return "PORT_DDI_C_LANES";
> case POWER_DOMAIN_PORT_DDI_D_LANES:
> - return "PORT_DDI_D_LANES";
> + BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_D_LANES !=
> + POWER_DOMAIN_PORT_DDI_TC1_LANES);
> + return ddi_tc_ports ? "PORT_DDI_TC1_LANES" : "PORT_DDI_D_LANES";
> case POWER_DOMAIN_PORT_DDI_E_LANES:
> - return "PORT_DDI_E_LANES";
> + BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_E_LANES !=
> + POWER_DOMAIN_PORT_DDI_TC2_LANES);
> + return ddi_tc_ports ? "PORT_DDI_TC2_LANES" : "PORT_DDI_E_LANES";
> case POWER_DOMAIN_PORT_DDI_F_LANES:
> - return "PORT_DDI_F_LANES";
> + BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_F_LANES !=
> + POWER_DOMAIN_PORT_DDI_TC3_LANES);
> + return ddi_tc_ports ? "PORT_DDI_TC3_LANES" : "PORT_DDI_F_LANES";
> + case POWER_DOMAIN_PORT_DDI_TC4_LANES:
> + return "PORT_DDI_TC4_LANES";
> + case POWER_DOMAIN_PORT_DDI_TC5_LANES:
> + return "PORT_DDI_TC5_LANES";
> + case POWER_DOMAIN_PORT_DDI_TC6_LANES:
> + return "PORT_DDI_TC6_LANES";
> case POWER_DOMAIN_PORT_DDI_A_IO:
> return "PORT_DDI_A_IO";
> case POWER_DOMAIN_PORT_DDI_B_IO:
> @@ -73,11 +88,23 @@ intel_display_power_domain_str(enum
> intel_display_power_domain domain)
> case POWER_DOMAIN_PORT_DDI_C_IO:
> return "PORT_DDI_C_IO";
> case POWER_DOMAIN_PORT_DDI_D_IO:
> - return "PORT_DDI_D_IO";
> + BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_D_IO !=
> +
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Lock the engine while dumping the active request (rev2)
== Series Details == Series: drm/i915: Lock the engine while dumping the active request (rev2) URL : https://patchwork.freedesktop.org/series/63442/ State : success == Summary == CI Bug Log - changes from CI_DRM_6441 -> Patchwork_13583 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13583/ Known issues Here are the changes found in Patchwork_13583 that come from known issues: ### IGT changes ### Issues hit * igt@i915_module_load@reload-with-fault-injection: - fi-icl-dsi: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6441/fi-icl-dsi/igt@i915_module_l...@reload-with-fault-injection.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13583/fi-icl-dsi/igt@i915_module_l...@reload-with-fault-injection.html * igt@kms_frontbuffer_tracking@basic: - fi-icl-dsi: [PASS][3] -> [DMESG-WARN][4] ([fdo#106107]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6441/fi-icl-dsi/igt@kms_frontbuffer_track...@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13583/fi-icl-dsi/igt@kms_frontbuffer_track...@basic.html Possible fixes * igt@gem_ctx_create@basic-files: - fi-icl-guc: [INCOMPLETE][5] ([fdo#107713] / [fdo#109100]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6441/fi-icl-guc/igt@gem_ctx_cre...@basic-files.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13583/fi-icl-guc/igt@gem_ctx_cre...@basic-files.html * igt@kms_busy@basic-flip-a: - fi-icl-dsi: [DMESG-WARN][7] ([fdo#106107]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6441/fi-icl-dsi/igt@kms_b...@basic-flip-a.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13583/fi-icl-dsi/igt@kms_b...@basic-flip-a.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][9] ([fdo#109485]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6441/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13583/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100 [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485 Participating hosts (52 -> 47) -- Missing(5): fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_6441 -> Patchwork_13583 CI_DRM_6441: 9d31edef447734a1e5ece397367de6fa3cfde714 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5092: 2a66ae6626d5583240509f84117d1345a799b75a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13583: 1c428c60ed66d5546afd4d82e6299726885378f3 @ git://anongit.freedesktop.org/gfx-ci/linux == Kernel 32bit build == Warning: Kernel 32bit buildtest failed: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13583/build_32bit.log CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh CHK include/generated/compile.h Kernel: arch/x86/boot/bzImage is ready (#1) Building modules, stage 2. MODPOST 112 modules ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! scripts/Makefile.modpost:91: recipe for target '__modpost' failed make[1]: *** [__modpost] Error 1 Makefile:1287: recipe for target 'modules' failed make: *** [modules] Error 2 == Linux commits == 1c428c60ed66 drm/i915: Lock the engine while dumping the active request == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13583/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Hold the vma manager lock while modifying mmap_offset
== Series Details ==
Series: drm/i915/selftests: Hold the vma manager lock while modifying
mmap_offset
URL : https://patchwork.freedesktop.org/series/63443/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6440 -> Patchwork_13582
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13582/
Known issues
Here are the changes found in Patchwork_13582 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s4-devices:
- fi-kbl-7500u: [PASS][1] -> [DMESG-WARN][2] ([fdo#105128] /
[fdo#107139])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6440/fi-kbl-7500u/igt@gem_exec_susp...@basic-s4-devices.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13582/fi-kbl-7500u/igt@gem_exec_susp...@basic-s4-devices.html
* igt@gem_linear_blits@basic:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6440/fi-icl-u3/igt@gem_linear_bl...@basic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13582/fi-icl-u3/igt@gem_linear_bl...@basic.html
Possible fixes
* igt@gem_mmap_gtt@basic-short:
- fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6] +1
similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6440/fi-icl-u3/igt@gem_mmap_...@basic-short.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13582/fi-icl-u3/igt@gem_mmap_...@basic-short.html
* igt@i915_selftest@live_contexts:
- fi-skl-iommu: [INCOMPLETE][7] ([fdo#111050]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6440/fi-skl-iommu/igt@i915_selftest@live_contexts.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13582/fi-skl-iommu/igt@i915_selftest@live_contexts.html
Warnings
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-kbl-guc: [FAIL][9] ([fdo#110829]) -> [SKIP][10] ([fdo#109271])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6440/fi-kbl-guc/igt@i915_pm_...@basic-pci-d3-state.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13582/fi-kbl-guc/igt@i915_pm_...@basic-pci-d3-state.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
[fdo#105128]: https://bugs.freedesktop.org/show_bug.cgi?id=105128
[fdo#107139]: https://bugs.freedesktop.org/show_bug.cgi?id=107139
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#110829]: https://bugs.freedesktop.org/show_bug.cgi?id=110829
[fdo#111049]: https://bugs.freedesktop.org/show_bug.cgi?id=111049
[fdo#111050]: https://bugs.freedesktop.org/show_bug.cgi?id=111050
Participating hosts (51 -> 46)
--
Additional (2): fi-icl-dsi fi-pnv-d510
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-icl-guc fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6440 -> Patchwork_13582
CI_DRM_6440: f3ee9eaf13443e179a5ad263da0abe241ea04172 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5092: 2a66ae6626d5583240509f84117d1345a799b75a @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13582: 1fa777e846c7c8b77aef70183444bd5cc3cdea4b @
git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13582/build_32bit.log
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1287: recipe for target 'modules' failed
make: *** [modules] Error 2
== Linux commits ==
1fa777e846c7 drm/i915/selftests: Hold the vma manager lock while modifying
mmap_offset
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13582/
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Re: [Intel-gfx] [PATCH 05/11] drm/i915/gtt: Compute the radix for gen8 page table levels
Quoting Chris Wilson (2019-07-07 22:00:18)
> The radix levels of each page directory are easily determined so replace
> the numerous hardcoded constants with precomputed derived constants.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 39 +
> 1 file changed, 39 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 2fc60e8acd9a..271305705c1c 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -868,6 +868,45 @@ static int gen8_ppgtt_notify_vgt(struct i915_ppgtt
> *ppgtt, bool create)
> return 0;
> }
>
> +/* Index shifts into the pagetable are offset by GEN8_PTE_SHIFT [12] */
> +#define gen8_pd_shift(lvl) ((lvl) * ilog2(I915_PDES))
> +#define gen8_pd_index(i, lvl) i915_pde_index((i), gen8_pd_shift(lvl))
> +#define __gen8_pte_shift(lvl) (GEN8_PTE_SHIFT + gen8_pd_shift(lvl))
> +#define __gen8_pte_index(a, lvl) i915_pde_index((a), __gen8_pte_shift(lvl))
> +
> +static inline unsigned int
> +gen8_pd_range(u64 addr, u64 end, int lvl, unsigned int *idx)
> +{
> + const int shift = gen8_pd_shift(lvl);
> + const u64 mask = ~0ull << gen8_pd_shift(lvl + 1);
> +
> + GEM_BUG_ON(addr >= end);
> + end += ~mask >> gen8_pd_shift(1);
> +
> + *idx = i915_pde_index(addr, shift);
> + if ((addr ^ end) & mask)
> + return I915_PDES - *idx;
> + else
> + return i915_pde_index(end, shift) - *idx;
> +}
> +
> +static inline bool gen8_pd_subsumes(u64 addr, u64 end, int lvl)
> +{
> + const u64 mask = ~0ull << gen8_pd_shift(lvl + 1);
> +
> + GEM_BUG_ON(addr >= end);
> + return (addr ^ end) & mask && (addr & ~mask) == 0;
> +}
> +
> +static inline unsigned int gen8_pt_count(u64 addr, u64 end)
> +{
> + GEM_BUG_ON(addr >= end);
> + if ((addr ^ end) & ~I915_PDE_MASK)
> + return I915_PDES - (addr & I915_PDE_MASK);
> + else
> + return end - addr;
> +}
So this is the question, do you want these as 512 and 0x1ff?
Or just define gen8_pd_shift(lvl) as ((lvl) * ilog(512))
and work from there. Hmm.
-Chris
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[Intel-gfx] [PATCH v1] drm/i915/selftests: Hold the vma manager lock while modifying mmap_offset
Right idea, wrong lock. We already drop struct_mutex before we free the
mmap_offset when freeing the object, so we need to take the vma manager
lock when manipulating the mmap_offset address space for our selftests.
Fixes: 8221d21b0664 ("drm/i915/selftests: Lock the drm_mm while modifying")
Signed-off-by: Chris Wilson
Cc: Imre Deak
---
.../drm/i915/gem/selftests/i915_gem_mman.c| 20 +++
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index b95fdc2b6bfc..5635cbb4af22 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -401,6 +401,18 @@ static void restore_retire_worker(struct drm_i915_private
*i915)
i915_gem_shrinker_register(i915);
}
+static void mmap_offset_lock(struct drm_i915_private *i915)
+ __acquires(>drm.vma_offset_manager->vm_lock)
+{
+ write_lock(>drm.vma_offset_manager->vm_lock);
+}
+
+static void mmap_offset_unlock(struct drm_i915_private *i915)
+ __releases(>drm.vma_offset_manager->vm_lock)
+{
+ write_unlock(>drm.vma_offset_manager->vm_lock);
+}
+
static int igt_mmap_offset_exhaustion(void *arg)
{
struct drm_i915_private *i915 = arg;
@@ -419,9 +431,9 @@ static int igt_mmap_offset_exhaustion(void *arg)
drm_mm_for_each_hole(hole, mm, hole_start, hole_end) {
resv.start = hole_start;
resv.size = hole_end - hole_start - 1; /* PAGE_SIZE units */
- mutex_lock(>drm.struct_mutex);
+ mmap_offset_lock(i915);
err = drm_mm_reserve_node(mm, );
- mutex_unlock(>drm.struct_mutex);
+ mmap_offset_unlock(i915);
if (err) {
pr_err("Failed to trim VMA manager, err=%d\n", err);
goto out_park;
@@ -485,9 +497,9 @@ static int igt_mmap_offset_exhaustion(void *arg)
}
out:
- mutex_lock(>drm.struct_mutex);
+ mmap_offset_lock(i915);
drm_mm_remove_node();
- mutex_unlock(>drm.struct_mutex);
+ mmap_offset_unlock(i915);
out_park:
restore_retire_worker(i915);
return err;
--
2.22.0
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[Intel-gfx] [PATCH v1] drm/i915/selftests: Hold the vma manager lock while modifying mmap_offset
_ight idea, wrong lock. We already drop struct_mutex before we free the
mmap_offset when freeing the object, so we need to take the vma manager
lock when manipulating the mmap_offset address space for our selftests.
Fixes: 8221d21b0664 ("drm/i915/selftests: Lock the drm_mm while modifying")
Signed-off-by: Chris Wilson
Cc: Imre Deak
---
Keep sparse quiet with locking annotations.
-Chris
---
.../drm/i915/gem/selftests/i915_gem_mman.c| 20 +++
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index b95fdc2b6bfc..5635cbb4af22 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -401,6 +401,18 @@ static void restore_retire_worker(struct drm_i915_private
*i915)
i915_gem_shrinker_register(i915);
}
+static void mmap_offset_lock(struct drm_i915_private *i915)
+ __acquires(>drm.vma_offset_manager->vm_lock)
+{
+ write_lock(>drm.vma_offset_manager->vm_lock);
+}
+
+static void mmap_offset_unlock(struct drm_i915_private *i915)
+ __releases(>drm.vma_offset_manager->vm_lock)
+{
+ write_unlock(>drm.vma_offset_manager->vm_lock);
+}
+
static int igt_mmap_offset_exhaustion(void *arg)
{
struct drm_i915_private *i915 = arg;
@@ -419,9 +431,9 @@ static int igt_mmap_offset_exhaustion(void *arg)
drm_mm_for_each_hole(hole, mm, hole_start, hole_end) {
resv.start = hole_start;
resv.size = hole_end - hole_start - 1; /* PAGE_SIZE units */
- mutex_lock(>drm.struct_mutex);
+ mmap_offset_lock(i915);
err = drm_mm_reserve_node(mm, );
- mutex_unlock(>drm.struct_mutex);
+ mmap_offset_unlock(i915);
if (err) {
pr_err("Failed to trim VMA manager, err=%d\n", err);
goto out_park;
@@ -485,9 +497,9 @@ static int igt_mmap_offset_exhaustion(void *arg)
}
out:
- mutex_lock(>drm.struct_mutex);
+ mmap_offset_lock(i915);
drm_mm_remove_node();
- mutex_unlock(>drm.struct_mutex);
+ mmap_offset_unlock(i915);
out_park:
restore_retire_worker(i915);
return err;
--
2.22.0
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Re: [Intel-gfx] [igt-dev] [PATCH V6 i-g-t 1/6] lib/igt_kms: Add writeback support
On Tue, Jul 9, 2019 at 11:42 AM Ser, Simon wrote:
>
> On Tue, 2019-07-09 at 11:32 -0300, Rodrigo Siqueira wrote:
> > On Wed, Jul 3, 2019 at 9:15 AM Ser, Simon wrote:
> > > On Tue, 2019-06-18 at 18:56 -0300, Rodrigo Siqueira wrote:
> > > > On Thu, Jun 13, 2019 at 11:54 AM Liviu Dudau
> > > > wrote:
> > > > > On Wed, Jun 12, 2019 at 11:16:02PM -0300, Brian Starkey wrote:
> > > > > > Add support in igt_kms for writeback connectors, with the ability
> > > > > > to attach framebuffers.
> > > > > >
> > > > > > v5: Rebase and add DRM_CLIENT_CAP_WRITEBACK_CONNECTORS before
> > > > > > drmModeGetResources()
> > > > >
> > > > > Reviewed-by: Liviu Dudau
> > > > >
> > > > > Thanks for updating this! Given that I have done the last changes and
> > > > > this is
> > > > > mostly a refresh, not sure if I should add more Reviewed-by's to the
> > > > > other
> > > > > patches.
> > > >
> > > > Thanks Liviu!
> > > >
> > > > I just forgot to add my SoB, and for some reason, gmail does not allow
> > > > me to send an email on someone behalf.
> > >
> > > FWIW, that's a good thing, and it's required to pass DMARC checks.
> > >
> > > Instead, git-send-email should add a From line at the beginning of the
> > > message when sending a patch on behalf of someone else. I wonder what
> > > happened here.
> >
> > Thank you for your help.
> >
> > I’m using neomutt for sending patches, and I’ll take a look at
> > git-send-email. Additionally, it looks like Gmail requires that I add
> > a new account in order to allow me to send patches on someone behalf.
> > I’ll take some time to read about this issue, and I will try to resend
> > the patchset again.
>
> When sending a patch on someone else's behalf, you shouldn't send the
> e-mail with the sender (From header) set to someone else. You should
> use your normal address. The From line in the body of the message will
> make Git understand the author is someone else.
>
> So no new account setup required.
>
> I really recommend using git-send-email for patches. There are too many
> ways to make a mistake if you try sending emails manually. Here is a
> tutorial:
> https://git-send-email.io/
Thank you very much for the tutorial! I'll read it and prepare to
migrate from 'neomutt -H' to git-send-mail.
> > Btw, if you have time, could you take a look in this series?
>
> Sure, I've already began looking at the series. I'll continue soon.
Thank you again for your help.
> Thanks for your work!
>
> > Best regards
> >
> > > > Btw, I can fix it after
> > > > everybody agrees that the kms_writeback is ready for landing.
> > > >
> > > >
> > > > > Best regards,
> > > > > Liviu
> > > > >
> > > > > > Signed-off-by: Brian Starkey
> > > > > > [rebased and updated to the latest igt style]
> > > > > > Signed-off-by: Liviu Dudau
> > > > > > ---
> > > > > > lib/igt_kms.c | 57
> > > > > > +++
> > > > > > lib/igt_kms.h | 6 ++
> > > > > > 2 files changed, 63 insertions(+)
> > > > > >
> > > > > > diff --git a/lib/igt_kms.c b/lib/igt_kms.c
> > > > > > index da188a39..140db346 100644
> > > > > > --- a/lib/igt_kms.c
> > > > > > +++ b/lib/igt_kms.c
> > > > > > @@ -325,6 +325,9 @@ const char * const
> > > > > > igt_connector_prop_names[IGT_NUM_CONNECTOR_PROPS] = {
> > > > > > [IGT_CONNECTOR_BROADCAST_RGB] = "Broadcast RGB",
> > > > > > [IGT_CONNECTOR_CONTENT_PROTECTION] = "Content Protection",
> > > > > > [IGT_CONNECTOR_VRR_CAPABLE] = "vrr_capable",
> > > > > > + [IGT_CONNECTOR_WRITEBACK_PIXEL_FORMATS] =
> > > > > > "WRITEBACK_PIXEL_FORMATS",
> > > > > > + [IGT_CONNECTOR_WRITEBACK_FB_ID] = "WRITEBACK_FB_ID",
> > > > > > + [IGT_CONNECTOR_WRITEBACK_OUT_FENCE_PTR] =
> > > > > > "WRITEBACK_OUT_FENCE_PTR",
> > > > > > };
> > > > > >
> > > > > > /*
> > > > > > @@ -557,6 +560,7 @@ static const struct type_name
> > > > > > connector_type_names[] = {
> > > > > > { DRM_MODE_CONNECTOR_VIRTUAL, "Virtual" },
> > > > > > { DRM_MODE_CONNECTOR_DSI, "DSI" },
> > > > > > { DRM_MODE_CONNECTOR_DPI, "DPI" },
> > > > > > + { DRM_MODE_CONNECTOR_WRITEBACK, "Writeback" },
> > > > > > {}
> > > > > > };
> > > > > >
> > > > > > @@ -1889,6 +1893,12 @@ static void igt_output_reset(igt_output_t
> > > > > > *output)
> > > > > > if (igt_output_has_prop(output, IGT_CONNECTOR_BROADCAST_RGB))
> > > > > > igt_output_set_prop_value(output,
> > > > > > IGT_CONNECTOR_BROADCAST_RGB,
> > > > > > BROADCAST_RGB_FULL);
> > > > > > + if (igt_output_has_prop(output,
> > > > > > IGT_CONNECTOR_WRITEBACK_FB_ID))
> > > > > > + igt_output_set_prop_value(output,
> > > > > > IGT_CONNECTOR_WRITEBACK_FB_ID, 0);
> > > > > > + if (igt_output_has_prop(output,
> > > > > > IGT_CONNECTOR_WRITEBACK_OUT_FENCE_PTR)) {
> > > > > > + igt_output_clear_prop_changed(output,
> > > > > > IGT_CONNECTOR_WRITEBACK_OUT_FENCE_PTR);
> > > > > > +
Re: [Intel-gfx] [PATCH 03/11] drm/i915/gtt: Reorder gen8 ppgtt free/clear/alloc
Chris Wilson writes:
> In preparation for refactoring the free/clear/alloc, first move the code
> around so that we can avoid forward declarations in the next set of
> patches.
>
> Signed-off-by: Chris Wilson
Diff got funky at some point but after applying
end result looked good.
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 673 ++--
> 1 file changed, 337 insertions(+), 336 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 1fa93f56792e..da4db76ce054 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -831,6 +831,104 @@ static void mark_tlbs_dirty(struct i915_ppgtt *ppgtt)
> ppgtt->pd_dirty_engines = ALL_ENGINES;
> }
>
> +static int gen8_ppgtt_notify_vgt(struct i915_ppgtt *ppgtt, bool create)
> +{
> + struct i915_address_space *vm = >vm;
> + struct drm_i915_private *dev_priv = vm->i915;
> + enum vgt_g2v_type msg;
> + int i;
> +
> + if (create)
> + atomic_inc(px_used(ppgtt->pd)); /* never remove */
> + else
> + atomic_dec(px_used(ppgtt->pd));
> +
> + if (i915_vm_is_4lvl(vm)) {
> + const u64 daddr = px_dma(ppgtt->pd);
> +
> + I915_WRITE(vgtif_reg(pdp[0].lo), lower_32_bits(daddr));
> + I915_WRITE(vgtif_reg(pdp[0].hi), upper_32_bits(daddr));
> +
> + msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE :
> + VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY);
> + } else {
> + for (i = 0; i < GEN8_3LVL_PDPES; i++) {
> + const u64 daddr = i915_page_dir_dma_addr(ppgtt, i);
> +
> + I915_WRITE(vgtif_reg(pdp[i].lo), lower_32_bits(daddr));
> + I915_WRITE(vgtif_reg(pdp[i].hi), upper_32_bits(daddr));
> + }
> +
> + msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE :
> + VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY);
> + }
> +
> + I915_WRITE(vgtif_reg(g2v_notify), msg);
> +
> + return 0;
> +}
> +
> +static void gen8_free_page_tables(struct i915_address_space *vm,
> + struct i915_page_directory *pd)
> +{
> + int i;
> +
> + for (i = 0; i < I915_PDES; i++) {
> + if (pd->entry[i] != >scratch_pt)
> + free_pd(vm, pd->entry[i]);
> + }
> +}
> +
> +static void gen8_ppgtt_cleanup_3lvl(struct i915_address_space *vm,
> + struct i915_page_directory *pdp)
> +{
> + const unsigned int pdpes = i915_pdpes_per_pdp(vm);
> + int i;
> +
> + for (i = 0; i < pdpes; i++) {
> + if (pdp->entry[i] == >scratch_pd)
> + continue;
> +
> + gen8_free_page_tables(vm, pdp->entry[i]);
> + free_pd(vm, pdp->entry[i]);
> + }
> +
> + free_px(vm, pdp);
> +}
> +
> +static void gen8_ppgtt_cleanup_4lvl(struct i915_ppgtt *ppgtt)
> +{
> + struct i915_page_directory * const pml4 = ppgtt->pd;
> + int i;
> +
> + for (i = 0; i < GEN8_PML4ES_PER_PML4; i++) {
> + struct i915_page_directory *pdp = i915_pdp_entry(pml4, i);
> +
> + if (px_base(pdp) == >vm.scratch_pdp)
> + continue;
> +
> + gen8_ppgtt_cleanup_3lvl(>vm, pdp);
> + }
> +
> + free_px(>vm, pml4);
> +}
> +
> +static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
> +{
> + struct drm_i915_private *i915 = vm->i915;
> + struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
> +
> + if (intel_vgpu_active(i915))
> + gen8_ppgtt_notify_vgt(ppgtt, false);
> +
> + if (i915_vm_is_4lvl(vm))
> + gen8_ppgtt_cleanup_4lvl(ppgtt);
> + else
> + gen8_ppgtt_cleanup_3lvl(>vm, ppgtt->pd);
> +
> + free_scratch(vm);
> +}
> +
> /* Removes entries from a single page table, releasing it if it's empty.
> * Caller can use the return value to update higher-level entries.
> */
> @@ -917,95 +1015,265 @@ static void gen8_ppgtt_clear_4lvl(struct
> i915_address_space *vm,
> }
> }
>
> -static inline struct sgt_dma {
> - struct scatterlist *sg;
> - dma_addr_t dma, max;
> -} sgt_dma(struct i915_vma *vma) {
> - struct scatterlist *sg = vma->pages->sgl;
> - dma_addr_t addr = sg_dma_address(sg);
> - return (struct sgt_dma) { sg, addr, addr + sg->length };
> -}
> -
> -struct gen8_insert_pte {
> - u16 pml4e;
> - u16 pdpe;
> - u16 pde;
> - u16 pte;
> -};
>
> -static __always_inline struct gen8_insert_pte gen8_insert_pte(u64 start)
> +static int gen8_ppgtt_alloc_pd(struct i915_address_space *vm,
> +struct i915_page_directory *pd,
> +u64 start, u64 length)
> {
> - return (struct gen8_insert_pte) {
> - gen8_pml4e_index(start),
> - gen8_pdpe_index(start),
> - gen8_pde_index(start),
