Re: [Intel-gfx] [PATCH 2/2] drm/i915/guc: Turn on GuC/HuC auto mode
On 7/10/2019 10:27 PM, Michal Wajdeczko wrote: On Tue, 09 Jul 2019 16:17:02 +0200, Joonas Lahtinen wrote: Better subject would be: "Enable HuC (through GuC) on supported platforms" Such subject sounds better, but on one hand it does not reflect real code change (since we are not explicitly enabling HuC, but instead we are just letting the driver enable GuC/HuC to whatever mode it decides), but on other hand this is what actual outcome of the change is (as i915 currently enables GuC loading with HuC authentication on every platform where corresponding firmwares are defined/available, and nothing more). Please confirm if you still opt-in to use your subject. Quoting Michal Wajdeczko (2019-07-03 14:36:40) GuC firmware is now mature, so let it run by default. That's bit of a misleading statement (in more than one way). It's mature enough to perform HuC authentication, and we don't expect more from it ;) "Enable loading HuC firmware (through GuC) to unlock advanced video codecs on supported platforms. GuC firmware is required to authenticate the HuC firmware, which is a requirement for it to operate." To some extend this duplicates existing "DOC: HuC Firmware" Do we need to repeat that again here? Has the most recent firmware been merged to linux-firmware and is it present in our CI systems? My understanding is: No and Yes. Maybe Anusha can provide more details here. It would also be good to list what kind of tests have been run to ensure that there are no regressions, I'm afraid on IGT level we don't have HuC tests. But media team was using modparam override to force GuC/HuC for a while, Tony do you have such test list/results handy? HuC functionality has been tested with AVC VDENC/HEVC VDENC/VP9VDENC encoding test cases in regular CI. Thanks, -Tony and which platforms this change affects. This change affects all platforms where we have GuC/HuC firmwares defined, so: SKL, BXT, KBL, CFL, ICL. Note that we'll still have possibility to tweak that inside driver, as auto mode is just moving responsibility what can be enabled from the user to the i915. Regards, Joonas Note that today GuC is only used for HuC authentication. Signed-off-by: Michal Wajdeczko Cc: Daniele Ceraolo Spurio Cc: Joonas Lahtinen Cc: Chris Wilson --- drivers/gpu/drm/i915/i915_params.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index d29ade3b7de6..5736c55694fe 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -54,7 +54,7 @@ struct drm_printer; param(int, disable_power_well, -1) \ param(int, enable_ips, 1) \ param(int, invert_brightness, 0) \ - param(int, enable_guc, 0) \ + param(int, enable_guc, -1) \ param(int, guc_log_level, -1) \ param(char *, guc_firmware_path, NULL) \ param(char *, huc_firmware_path, NULL) \ -- 2.19.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✓ Fi.CI.IGT: success for EHL port programming (rev7)
On Wed, Jul 10, 2019 at 11:29:40AM +, Patchwork wrote: > == Series Details == > > Series: EHL port programming (rev7) > URL : https://patchwork.freedesktop.org/series/62492/ > State : success > > == Summary == > > CI Bug Log - changes from CI_DRM_6444_full -> Patchwork_13589_full > > > Summary > --- > > **SUCCESS** > > No regressions found. > Series pushed to dinq. Thanks Jose and Ville for the reviews. Matt > > > Known issues > > > Here are the changes found in Patchwork_13589_full that come from known > issues: > > ### IGT changes ### > > Issues hit > > * igt@gem_exec_parallel@bcs0: > - shard-hsw: [PASS][1] -> [INCOMPLETE][2] ([fdo#103540]) >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-hsw5/igt@gem_exec_paral...@bcs0.html >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-hsw5/igt@gem_exec_paral...@bcs0.html > > * igt@kms_color@pipe-c-ctm-green-to-red: > - shard-skl: [PASS][3] -> [FAIL][4] ([fdo#107201]) >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-skl10/igt@kms_co...@pipe-c-ctm-green-to-red.html >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-skl6/igt@kms_co...@pipe-c-ctm-green-to-red.html > > * igt@kms_flip@flip-vs-expired-vblank: > - shard-skl: [PASS][5] -> [FAIL][6] ([fdo#105363]) +1 similar > issue >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-skl5/igt@kms_f...@flip-vs-expired-vblank.html >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-skl3/igt@kms_f...@flip-vs-expired-vblank.html > > * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite: > - shard-iclb: [PASS][7] -> [FAIL][8] ([fdo#103167]) +3 similar > issues >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-iclb7/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-indfb-draw-pwrite.html >[8]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-iclb8/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-indfb-draw-pwrite.html > > * igt@kms_pipe_crc_basic@hang-read-crc-pipe-a: > - shard-snb: [PASS][9] -> [SKIP][10] ([fdo#109271]) +1 similar > issue >[9]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-snb5/igt@kms_pipe_crc_ba...@hang-read-crc-pipe-a.html >[10]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-snb5/igt@kms_pipe_crc_ba...@hang-read-crc-pipe-a.html > > * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: > - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([fdo#108566]) +5 > similar issues >[11]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-apl8/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html >[12]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-apl5/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html > > * igt@kms_psr@psr2_dpms: > - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#109441]) +1 similar > issue >[13]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-iclb2/igt@kms_psr@psr2_dpms.html >[14]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-iclb3/igt@kms_psr@psr2_dpms.html > > * igt@kms_rotation_crc@multiplane-rotation-cropping-top: > - shard-kbl: [PASS][15] -> [FAIL][16] ([fdo#109016]) >[15]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-kbl4/igt@kms_rotation_...@multiplane-rotation-cropping-top.html >[16]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-kbl3/igt@kms_rotation_...@multiplane-rotation-cropping-top.html > > * igt@kms_vblank@pipe-a-wait-forked-hang: > - shard-apl: [PASS][17] -> [INCOMPLETE][18] ([fdo#103927]) >[17]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-apl6/igt@kms_vbl...@pipe-a-wait-forked-hang.html >[18]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-apl7/igt@kms_vbl...@pipe-a-wait-forked-hang.html > > > Possible fixes > > * igt@i915_suspend@sysfs-reader: > - shard-apl: [DMESG-WARN][19] ([fdo#108566]) -> [PASS][20] +3 > similar issues >[19]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-apl2/igt@i915_susp...@sysfs-reader.html >[20]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-apl2/igt@i915_susp...@sysfs-reader.html > > * igt@kms_atomic_transition@1x-modeset-transitions-fencing: > - shard-iclb: [INCOMPLETE][21] ([fdo#107713]) -> [PASS][22] >[21]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-iclb4/igt@kms_atomic_transit...@1x-modeset-transitions-fencing.html >[22]: >
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,01/21] drm/i915: Add 4th pipe and transcoder
== Series Details == Series: series starting with [CI,01/21] drm/i915: Add 4th pipe and transcoder URL : https://patchwork.freedesktop.org/series/63528/ State : warning == Summary == $ dim checkpatch origin/drm-tip 8c5d9599c135 drm/i915: Add 4th pipe and transcoder e6e0cc3b8702 drm/i915/tgl: add initial Tiger Lake definitions 837c6de93950 drm/i915/tgl: Introduce Tiger Lake PCH 2803998164ad drm/i915/tgl: Add TGL PCH detection in virtualized environment 883553983e46 drm/i915/tgl: Add TGL PCI IDs -:35: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #35: FILE: include/drm/i915_pciids.h:587: +#define INTEL_TGL_12_IDS(info) \ + INTEL_VGA_DEVICE(0x9A49, info), \ + INTEL_VGA_DEVICE(0x9A40, info), \ + INTEL_VGA_DEVICE(0x9A59, info), \ + INTEL_VGA_DEVICE(0x9A60, info), \ + INTEL_VGA_DEVICE(0x9A68, info), \ + INTEL_VGA_DEVICE(0x9A70, info), \ + INTEL_VGA_DEVICE(0x9A78, info) -:35: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects? #35: FILE: include/drm/i915_pciids.h:587: +#define INTEL_TGL_12_IDS(info) \ + INTEL_VGA_DEVICE(0x9A49, info), \ + INTEL_VGA_DEVICE(0x9A40, info), \ + INTEL_VGA_DEVICE(0x9A59, info), \ + INTEL_VGA_DEVICE(0x9A60, info), \ + INTEL_VGA_DEVICE(0x9A68, info), \ + INTEL_VGA_DEVICE(0x9A70, info), \ + INTEL_VGA_DEVICE(0x9A78, info) total: 1 errors, 0 warnings, 1 checks, 21 lines checked 510219026ae8 drm/i915/tgl: Check if pipe D is fused 63934798206f drm/i915/tgl: rename TRANSCODER_EDP_VDSC to use on transcoder A 67a742c4d319 drm/i915/tgl: Add power well support a1a70f0c18c7 drm/i915/tgl: Add power well to support 4th pipe 1e13db2a45fa drm/i915/tgl: Add new pll ids 72bfafdc522e drm/i915/tgl: Add pll manager 029aa51a25e8 drm/i915/tgl: Add additional ports for Tiger Lake 0361ee034f15 drm/i915/tgl: extend intel_port_is_combophy/tc 7db88e58cf14 drm/i915/tgl: init ddi port A-C for Tiger Lake f0209d1b63ef drm/i915/tgl: apply Display WA #1178 to fix type C dongles 78d49928e5c7 drm/i915/gen12: MBUS B credit change 9d4f02efaaa7 drm/i915/tgl: Add gmbus gpio pin to port mapping 288bdf24ccf4 drm/i915/tgl: port to ddc pin mapping e18185cf695d drm/i915/tgl: Add vbt value mapping for DDC Bus pin d0629a9c04d0 drm/i915/tgl: Add DPLL registers 2a9ee472c270 drm/i915/tgl: Update DPLL clock reference register ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/gt: Drop the duplicate workaround
On Wed, Jul 10, 2019 at 09:04:28PM +0100, Chris Wilson wrote:
> The workarounds was revived in the backmerge that was meant to fix it!
>
> Fixes: 88c90e800675 ("Merge drm/drm-next into drm-intel-next-queued")
> Signed-off-by: Chris Wilson
> Cc: Rodrigo Vivi
Duh! Sorry about that and thanks for dropping the fixup from drm-rerere.
I was hopping the backmerge + push would fail when applying the fixup
so I would remove it. Instead it went through my scripts silently to the
end... :(
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 --
> 1 file changed, 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index f6fd6905ee6f..9e069286d3ce 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -531,12 +531,6 @@ static void icl_ctx_workarounds_init(struct
> intel_engine_cs *engine,
> {
> struct drm_i915_private *i915 = engine->i915;
>
> - /* WaDisableBankHangMode:icl */
> - wa_write(wal,
> - GEN8_L3CNTLREG,
> - intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) |
> - GEN8_ERRDETBCTRL);
> -
> /* WaDisableBankHangMode:icl */
> wa_write(wal,
>GEN8_L3CNTLREG,
> --
> 2.22.0
>
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[Intel-gfx] [CI 09/21] drm/i915/tgl: Add power well to support 4th pipe
From: Mika Kahola
Add power well 5 to support 4th pipe and transcoder on TGL.
Cc: James Ausmus
Cc: Imre Deak
Signed-off-by: Mika Kahola
Signed-off-by: Lucas De Marchi
Link:
https://patchwork.freedesktop.org/patch/msgid/20190708231629.9296-11-lucas.demar...@intel.com
Reviewed-by: Rodrigo Vivi
---
.../drm/i915/display/intel_display_power.c| 28 +--
.../drm/i915/display/intel_display_power.h| 3 ++
drivers/gpu/drm/i915/i915_reg.h | 1 +
3 files changed, 29 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index fead072afd96..659c0954eaf7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -37,18 +37,24 @@ intel_display_power_domain_str(struct drm_i915_private
*i915,
return "PIPE_B";
case POWER_DOMAIN_PIPE_C:
return "PIPE_C";
+ case POWER_DOMAIN_PIPE_D:
+ return "PIPE_D";
case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
return "PIPE_A_PANEL_FITTER";
case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
return "PIPE_B_PANEL_FITTER";
case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
return "PIPE_C_PANEL_FITTER";
+ case POWER_DOMAIN_PIPE_D_PANEL_FITTER:
+ return "PIPE_D_PANEL_FITTER";
case POWER_DOMAIN_TRANSCODER_A:
return "TRANSCODER_A";
case POWER_DOMAIN_TRANSCODER_B:
return "TRANSCODER_B";
case POWER_DOMAIN_TRANSCODER_C:
return "TRANSCODER_C";
+ case POWER_DOMAIN_TRANSCODER_D:
+ return "TRANSCODER_D";
case POWER_DOMAIN_TRANSCODER_EDP:
return "TRANSCODER_EDP";
case POWER_DOMAIN_TRANSCODER_VDSC_PW2:
@@ -2538,8 +2544,13 @@ void intel_display_power_put(struct drm_i915_private
*dev_priv,
#define ICL_AUX_TBT4_IO_POWER_DOMAINS (\
BIT_ULL(POWER_DOMAIN_AUX_TBT4))
-/* TODO: TGL_PW_5_POWER_DOMAINS: PIPE_D */
+#define TGL_PW_5_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_D) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
#define TGL_PW_4_POWER_DOMAINS ( \
+ TGL_PW_5_POWER_DOMAINS |\
BIT_ULL(POWER_DOMAIN_PIPE_C) | \
BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
BIT_ULL(POWER_DOMAIN_INIT))
@@ -2549,7 +2560,7 @@ void intel_display_power_put(struct drm_i915_private
*dev_priv,
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |\
BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |\
- /* TODO: TRANSCODER_D */\
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_D) |\
BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_LANES) | \
BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO) | \
@@ -3892,7 +3903,18 @@ static const struct i915_power_well_desc
tgl_power_wells[] = {
.hsw.irq_pipe_mask = BIT(PIPE_C),
}
},
- /* TODO: power well 5 for pipe D */
+ {
+ .name = "power well 5",
+ .domains = TGL_PW_5_POWER_DOMAINS,
+ .ops = _power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = _power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_PW_5,
+ .hsw.has_fuses = true,
+ .hsw.irq_pipe_mask = BIT(PIPE_D),
+ },
+ },
};
static int
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
b/drivers/gpu/drm/i915/display/intel_display_power.h
index 54ad4f0b0886..a264f18c95f1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -18,12 +18,15 @@ enum intel_display_power_domain {
POWER_DOMAIN_PIPE_A,
POWER_DOMAIN_PIPE_B,
POWER_DOMAIN_PIPE_C,
+ POWER_DOMAIN_PIPE_D,
POWER_DOMAIN_PIPE_A_PANEL_FITTER,
POWER_DOMAIN_PIPE_B_PANEL_FITTER,
POWER_DOMAIN_PIPE_C_PANEL_FITTER,
+ POWER_DOMAIN_PIPE_D_PANEL_FITTER,
POWER_DOMAIN_TRANSCODER_A,
POWER_DOMAIN_TRANSCODER_B,
POWER_DOMAIN_TRANSCODER_C,
+ POWER_DOMAIN_TRANSCODER_D,
POWER_DOMAIN_TRANSCODER_EDP,
/* VDSC/joining for TRANSCODER_EDP (ICL) or TRANSCODER_A (TGL) */
POWER_DOMAIN_TRANSCODER_VDSC_PW2,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 63238db21b44..5ca74eca05a4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9148,6 +9148,7 @@ enum {
#define SKL_PW_CTL_IDX_MISC_IO
[Intel-gfx] [CI 15/21] drm/i915/tgl: apply Display WA #1178 to fix type C dongles
Add port C to workaround to cover Tiger Lake.
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
Link:
https://patchwork.freedesktop.org/patch/msgid/20190708231629.9296-22-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/display/intel_display_power.c | 11 ---
drivers/gpu/drm/i915/i915_reg.h| 4 +++-
2 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 659c0954eaf7..b526eb6ea2ae 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -453,6 +453,7 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private
*dev_priv,
int pw_idx = power_well->desc->hsw.idx;
enum port port = ICL_AUX_PW_TO_PORT(pw_idx);
u32 val;
+ int wa_idx_max;
val = I915_READ(regs->driver);
I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
@@ -462,9 +463,13 @@ icl_combo_phy_aux_power_well_enable(struct
drm_i915_private *dev_priv,
hsw_wait_for_power_well_enable(dev_priv, power_well);
- /* Display WA #1178: icl */
- if (IS_ICELAKE(dev_priv) &&
- pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B &&
+ /* Display WA #1178: icl, tgl */
+ if (IS_TIGERLAKE(dev_priv))
+ wa_idx_max = ICL_PW_CTL_IDX_AUX_C;
+ else
+ wa_idx_max = ICL_PW_CTL_IDX_AUX_B;
+
+ if (pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= wa_idx_max &&
!intel_bios_is_port_edp(dev_priv, port)) {
val = I915_READ(ICL_AUX_ANAOVRD1(pw_idx));
val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5ca74eca05a4..d07e92678c41 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9244,9 +9244,11 @@ enum skl_power_gate {
#define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
#define _ICL_AUX_ANAOVRD1_A0x162398
#define _ICL_AUX_ANAOVRD1_B0x6C398
+#define _TGL_AUX_ANAOVRD1_C0x160398
#define ICL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \
_ICL_AUX_ANAOVRD1_A, \
- _ICL_AUX_ANAOVRD1_B))
+ _ICL_AUX_ANAOVRD1_B, \
+ _TGL_AUX_ANAOVRD1_C))
#define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7)
#define ICL_AUX_ANAOVRD1_ENABLE (1 << 0)
--
2.21.0
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[Intel-gfx] [CI 12/21] drm/i915/tgl: Add additional ports for Tiger Lake
From: Vandita Kulkarni
There are 2 new additional typeC ports in Tiger Lake and PORT-C is now a
combophy port. This results in 6 typeC ports and 3 combophy ports.
These 6 TC ports can be DP alternate mode, DP over thunderbolt, native
DP on legacy DP connector or native HDMI on legacy connector.
v2: Rebase on new modular FIA code (Lucas)
v3: Also add new port in port_identifier(), even though it can't
possibly be used there (requested by José)
Cc: Anusha Srivatsa
Signed-off-by: Vandita Kulkarni
Signed-off-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
Link:
https://patchwork.freedesktop.org/patch/msgid/20190708231629.9296-14-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/display/intel_ddi.c | 12
drivers/gpu/drm/i915/display/intel_display.h | 8
include/drm/i915_component.h | 2 +-
include/drm/i915_drm.h | 3 +++
4 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index ad638e7f27bb..55d996fefc3a 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4262,6 +4262,18 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
enum port port)
intel_dig_port->ddi_io_power_domain =
POWER_DOMAIN_PORT_DDI_F_IO;
break;
+ case PORT_G:
+ intel_dig_port->ddi_io_power_domain =
+ POWER_DOMAIN_PORT_DDI_G_IO;
+ break;
+ case PORT_H:
+ intel_dig_port->ddi_io_power_domain =
+ POWER_DOMAIN_PORT_DDI_H_IO;
+ break;
+ case PORT_I:
+ intel_dig_port->ddi_io_power_domain =
+ POWER_DOMAIN_PORT_DDI_I_IO;
+ break;
default:
MISSING_CASE(port);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index e781df463ffa..b0794f7c255d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -177,6 +177,12 @@ static inline const char *port_identifier(enum port port)
return "Port E";
case PORT_F:
return "Port F";
+ case PORT_G:
+ return "Port G";
+ case PORT_H:
+ return "Port H";
+ case PORT_I:
+ return "Port I";
default:
return "";
}
@@ -189,6 +195,8 @@ enum tc_port {
PORT_TC2,
PORT_TC3,
PORT_TC4,
+ PORT_TC5,
+ PORT_TC6,
I915_MAX_TC_PORTS
};
diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h
index dcb95bd9dee6..55c3b123581b 100644
--- a/include/drm/i915_component.h
+++ b/include/drm/i915_component.h
@@ -34,7 +34,7 @@ enum i915_component_type {
/* MAX_PORT is the number of port
* It must be sync with I915_MAX_PORTS defined i915_drv.h
*/
-#define MAX_PORTS 6
+#define MAX_PORTS 9
/**
* struct i915_audio_component - Used for direct communication between i915
and hda drivers
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index 7523e9a7b6e2..eb30062359d1 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -109,6 +109,9 @@ enum port {
PORT_D,
PORT_E,
PORT_F,
+ PORT_G,
+ PORT_H,
+ PORT_I,
I915_MAX_PORTS
};
--
2.21.0
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[Intel-gfx] [CI 14/21] drm/i915/tgl: init ddi port A-C for Tiger Lake
From: Mahesh Kumar
This patch initializes DDI PORT A, B & C for Tiger lake. Other
TC ports need to be initialized later once corresponding code is there.
Cc: Madhav Chauhan
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
Link:
https://patchwork.freedesktop.org/patch/msgid/20190708231629.9296-20-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/display/intel_display.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index a7b6a7918c3d..500bb3fd2939 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15300,12 +15300,17 @@ static void intel_setup_outputs(struct
drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv))
return;
- if (IS_ELKHARTLAKE(dev_priv)) {
+ if (INTEL_GEN(dev_priv) >= 12) {
+ /* TODO: initialize TC ports as well */
+ intel_ddi_init(dev_priv, PORT_A);
+ intel_ddi_init(dev_priv, PORT_B);
+ intel_ddi_init(dev_priv, PORT_C);
+ } else if (IS_ELKHARTLAKE(dev_priv)) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
intel_ddi_init(dev_priv, PORT_C);
icl_dsi_init(dev_priv);
- } else if (INTEL_GEN(dev_priv) >= 11) {
+ } else if (IS_GEN(dev_priv, 11)) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
intel_ddi_init(dev_priv, PORT_C);
--
2.21.0
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[Intel-gfx] [CI 05/21] drm/i915/tgl: Add TGL PCI IDs
Current list of PCI IDs for Tiger Lake.
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
Reviewed-by: Mika Kahola
Link:
https://patchwork.freedesktop.org/patch/msgid/20190708231629.9296-6-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
include/drm/i915_pciids.h | 10 ++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index da926485845d..e83c94cf2744 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -865,6 +865,7 @@ static const struct pci_device_id pciidlist[] = {
INTEL_CNL_IDS(_cannonlake_info),
INTEL_ICL_11_IDS(_icelake_11_info),
INTEL_EHL_IDS(_elkhartlake_info),
+ INTEL_TGL_12_IDS(_tigerlake_12_info),
{0, 0, 0}
};
MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 6c342ac470c8..a70c982ddff9 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -583,4 +583,14 @@
INTEL_VGA_DEVICE(0x4551, info), \
INTEL_VGA_DEVICE(0x4541, info)
+/* TGL */
+#define INTEL_TGL_12_IDS(info) \
+ INTEL_VGA_DEVICE(0x9A49, info), \
+ INTEL_VGA_DEVICE(0x9A40, info), \
+ INTEL_VGA_DEVICE(0x9A59, info), \
+ INTEL_VGA_DEVICE(0x9A60, info), \
+ INTEL_VGA_DEVICE(0x9A68, info), \
+ INTEL_VGA_DEVICE(0x9A70, info), \
+ INTEL_VGA_DEVICE(0x9A78, info)
+
#endif /* _I915_PCIIDS_H */
--
2.21.0
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[Intel-gfx] [CI 13/21] drm/i915/tgl: extend intel_port_is_combophy/tc
From: Mahesh Kumar
TGL has 3 combophy ports, so extend check for tigerlake in
intel_port_is_combophy/tc function.
Cc: Mika Kahola
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
Link:
https://patchwork.freedesktop.org/patch/msgid/20190708231629.9296-19-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/display/intel_display.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index db01ea08f30b..a7b6a7918c3d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6676,10 +6676,10 @@ bool intel_port_is_combophy(struct drm_i915_private
*dev_priv, enum port port)
if (port == PORT_NONE)
return false;
- if (IS_ELKHARTLAKE(dev_priv))
+ if (IS_ELKHARTLAKE(dev_priv) || INTEL_GEN(dev_priv) >= 12)
return port <= PORT_C;
- if (INTEL_GEN(dev_priv) >= 11)
+ if (IS_GEN(dev_priv, 11))
return port <= PORT_B;
return false;
@@ -6687,7 +6687,10 @@ bool intel_port_is_combophy(struct drm_i915_private
*dev_priv, enum port port)
bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
{
- if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
+ if (INTEL_GEN(dev_priv) >= 12)
+ return port >= PORT_D && port <= PORT_I;
+
+ if (IS_GEN(dev_priv, 11) && !IS_ELKHARTLAKE(dev_priv))
return port >= PORT_C && port <= PORT_F;
return false;
@@ -6698,6 +6701,9 @@ enum tc_port intel_port_to_tc(struct drm_i915_private
*dev_priv, enum port port)
if (!intel_port_is_tc(dev_priv, port))
return PORT_TC_NONE;
+ if (INTEL_GEN(dev_priv) >= 12)
+ return port - PORT_D;
+
return port - PORT_C;
}
--
2.21.0
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[Intel-gfx] [CI 11/21] drm/i915/tgl: Add pll manager
From: Vandita Kulkarni
Add a new pll array for Tiger Lake. The TC pll functions for type C will
be covered in later patches after its phy is implemented.
Cc: Madhav Chauhan
Cc: Rodrigo Vivi
Signed-off-by: Vandita Kulkarni
Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
Link:
https://patchwork.freedesktop.org/patch/msgid/20190708231629.9296-13-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 30d7500eb66c..3f68be716da9 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3465,6 +3465,21 @@ static const struct intel_dpll_mgr ehl_pll_mgr = {
.dump_hw_state = icl_dump_hw_state,
};
+static const struct dpll_info tgl_plls[] = {
+ { "DPLL 0", _pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
+ { "DPLL 1", _pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
+ { "TBT PLL", _pll_funcs, DPLL_ID_ICL_TBTPLL, 0 },
+ /* TODO: Add typeC plls */
+ { },
+};
+
+static const struct intel_dpll_mgr tgl_pll_mgr = {
+ .dpll_info = tgl_plls,
+ .get_dplls = icl_get_dplls,
+ .put_dplls = icl_put_dplls,
+ .dump_hw_state = icl_dump_hw_state,
+};
+
/**
* intel_shared_dpll_init - Initialize shared DPLLs
* @dev: drm device
@@ -3478,7 +3493,9 @@ void intel_shared_dpll_init(struct drm_device *dev)
const struct dpll_info *dpll_info;
int i;
- if (IS_ELKHARTLAKE(dev_priv))
+ if (INTEL_GEN(dev_priv) >= 12)
+ dpll_mgr = _pll_mgr;
+ else if (IS_ELKHARTLAKE(dev_priv))
dpll_mgr = _pll_mgr;
else if (INTEL_GEN(dev_priv) >= 11)
dpll_mgr = _pll_mgr;
--
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[Intel-gfx] [CI 03/21] drm/i915/tgl: Introduce Tiger Lake PCH
From: Radhakrishna Sripada
Add the enum additions to TGP.
Cc: Rodrigo Vivi
Cc: Joonas Lahtinen
Cc: David Weinehall
Cc: James Ausmus
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
Link:
https://patchwork.freedesktop.org/patch/msgid/20190708231629.9296-4-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 4
drivers/gpu/drm/i915/i915_drv.h | 3 +++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 794c6814a6d0..bcedd2d8e267 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -224,6 +224,10 @@ intel_pch_type(const struct drm_i915_private *dev_priv,
unsigned short id)
DRM_DEBUG_KMS("Found Mule Creek Canyon PCH\n");
WARN_ON(!IS_ELKHARTLAKE(dev_priv));
return PCH_MCC;
+ case INTEL_PCH_TGP_DEVICE_ID_TYPE:
+ DRM_DEBUG_KMS("Found Tiger Lake LP PCH\n");
+ WARN_ON(!IS_TIGERLAKE(dev_priv));
+ return PCH_TGP;
default:
return PCH_NONE;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 989ca1e02cc1..37d07a91b385 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -536,6 +536,7 @@ enum intel_pch {
PCH_CNP,/* Cannon/Comet Lake PCH */
PCH_ICP,/* Ice Lake PCH */
PCH_MCC,/* Mule Creek Canyon PCH */
+ PCH_TGP,/* Tiger Lake PCH */
};
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
@@ -2322,6 +2323,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480
#define INTEL_PCH_MCC_DEVICE_ID_TYPE 0x4B00
#define INTEL_PCH_MCC2_DEVICE_ID_TYPE 0x3880
+#define INTEL_PCH_TGP_DEVICE_ID_TYPE 0xA080
#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
#define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
@@ -2329,6 +2331,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
#define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
#define HAS_PCH_MCC(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MCC)
+#define HAS_PCH_TGP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_TGP)
#define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
#define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
#define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
--
2.21.0
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[Intel-gfx] [CI 21/21] drm/i915/tgl: Update DPLL clock reference register
From: José Roberto de Souza
This register definition changed from ICL and has now another meaning.
Use the right bits on TGL.
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
Reviewed-by: Ville Syrjälä
Link:
https://patchwork.freedesktop.org/patch/msgid/20190708231629.9296-26-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 8 ++--
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index cf5f6909ba9c..05e9986e392e 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2601,8 +2601,12 @@ static bool icl_calc_dpll_state(struct intel_crtc_state
*crtc_state,
cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params.qdiv_ratio) |
DPLL_CFGCR1_QDIV_MODE(pll_params.qdiv_mode) |
DPLL_CFGCR1_KDIV(pll_params.kdiv) |
-DPLL_CFGCR1_PDIV(pll_params.pdiv) |
-DPLL_CFGCR1_CENTRAL_FREQ_8400;
+DPLL_CFGCR1_PDIV(pll_params.pdiv);
+
+ if (INTEL_GEN(dev_priv) >= 12)
+ cfgcr1 |= TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL;
+ else
+ cfgcr1 |= DPLL_CFGCR1_CENTRAL_FREQ_8400;
memset(pll_state, 0, sizeof(*pll_state));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d290a6db2a14..0de3da8e89b5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9940,6 +9940,7 @@ enum skl_power_gate {
#define DPLL_CFGCR1_PDIV_7(8 << 2)
#define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0)
#define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0)
+#define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0)
#define CNL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR1,
_CNL_DPLL1_CFGCR1)
#define _ICL_DPLL0_CFGCR0 0x164000
--
2.21.0
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[Intel-gfx] [CI 19/21] drm/i915/tgl: Add vbt value mapping for DDC Bus pin
From: Mahesh Kumar
Add VBT-value to DDC bus pin mapping for the same.
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
Link:
https://patchwork.freedesktop.org/patch/msgid/20190708231629.9296-21-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/display/intel_bios.c | 17 -
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 3 +++
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 0c9808132d67..a08bc4f617c8 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1354,12 +1354,27 @@ static const u8 mcc_ddc_pin_map[] = {
[MCC_DDC_BUS_DDI_C] = GMBUS_PIN_9_TC1_ICP,
};
+static const u8 tgp_ddc_pin_map[] = {
+ [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
+ [ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT,
+ [TGL_DDC_BUS_DDI_C] = GMBUS_PIN_3_BXT,
+ [ICL_DDC_BUS_PORT_1] = GMBUS_PIN_9_TC1_ICP,
+ [ICL_DDC_BUS_PORT_2] = GMBUS_PIN_10_TC2_ICP,
+ [ICL_DDC_BUS_PORT_3] = GMBUS_PIN_11_TC3_ICP,
+ [ICL_DDC_BUS_PORT_4] = GMBUS_PIN_12_TC4_ICP,
+ [TGL_DDC_BUS_PORT_5] = GMBUS_PIN_13_TC5_TGP,
+ [TGL_DDC_BUS_PORT_6] = GMBUS_PIN_14_TC6_TGP,
+};
+
static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
{
const u8 *ddc_pin_map;
int n_entries;
- if (HAS_PCH_MCC(dev_priv)) {
+ if (HAS_PCH_TGP(dev_priv)) {
+ ddc_pin_map = tgp_ddc_pin_map;
+ n_entries = ARRAY_SIZE(tgp_ddc_pin_map);
+ } else if (HAS_PCH_MCC(dev_priv)) {
ddc_pin_map = mcc_ddc_pin_map;
n_entries = ARRAY_SIZE(mcc_ddc_pin_map);
} else if (HAS_PCH_ICP(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 2f4894e9a03d..93f5c9d204d6 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -310,10 +310,13 @@ enum vbt_gmbus_ddi {
DDC_BUS_DDI_F,
ICL_DDC_BUS_DDI_A = 0x1,
ICL_DDC_BUS_DDI_B,
+ TGL_DDC_BUS_DDI_C,
ICL_DDC_BUS_PORT_1 = 0x4,
ICL_DDC_BUS_PORT_2,
ICL_DDC_BUS_PORT_3,
ICL_DDC_BUS_PORT_4,
+ TGL_DDC_BUS_PORT_5,
+ TGL_DDC_BUS_PORT_6,
MCC_DDC_BUS_DDI_A = 0x1,
MCC_DDC_BUS_DDI_B,
MCC_DDC_BUS_DDI_C = 0x4,
--
2.21.0
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[Intel-gfx] [CI 20/21] drm/i915/tgl: Add DPLL registers
On TGL the port programming for combophy is very similar to ICL, so
adapt the callers to possibly use the different register values.
v2 (Lucas): Add TODO with about DPLL4 (requested by Ville)
Cc: Vandita Kulkarni
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
Reviewed-by: Ville Syrjälä
Link:
https://patchwork.freedesktop.org/patch/msgid/20190708231629.9296-25-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 24 +++
drivers/gpu/drm/i915/i915_reg.h | 17 +
2 files changed, 36 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 3f68be716da9..cf5f6909ba9c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3123,8 +3123,13 @@ static bool icl_pll_get_hw_state(struct drm_i915_private
*dev_priv,
if (!(val & PLL_ENABLE))
goto out;
- hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
- hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
+ if (INTEL_GEN(dev_priv) >= 12) {
+ hw_state->cfgcr0 = I915_READ(TGL_DPLL_CFGCR0(id));
+ hw_state->cfgcr1 = I915_READ(TGL_DPLL_CFGCR1(id));
+ } else {
+ hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
+ hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
+ }
ret = true;
out:
@@ -3158,10 +3163,19 @@ static void icl_dpll_write(struct drm_i915_private
*dev_priv,
{
struct intel_dpll_hw_state *hw_state = >state.hw_state;
const enum intel_dpll_id id = pll->info->id;
+ i915_reg_t cfgcr0_reg, cfgcr1_reg;
+
+ if (INTEL_GEN(dev_priv) >= 12) {
+ cfgcr0_reg = TGL_DPLL_CFGCR0(id);
+ cfgcr1_reg = TGL_DPLL_CFGCR1(id);
+ } else {
+ cfgcr0_reg = ICL_DPLL_CFGCR0(id);
+ cfgcr1_reg = ICL_DPLL_CFGCR1(id);
+ }
- I915_WRITE(ICL_DPLL_CFGCR0(id), hw_state->cfgcr0);
- I915_WRITE(ICL_DPLL_CFGCR1(id), hw_state->cfgcr1);
- POSTING_READ(ICL_DPLL_CFGCR1(id));
+ I915_WRITE(cfgcr0_reg, hw_state->cfgcr0);
+ I915_WRITE(cfgcr1_reg, hw_state->cfgcr1);
+ POSTING_READ(cfgcr1_reg);
}
static void icl_mg_pll_write(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 87f79dc8e0c3..d290a6db2a14 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -242,6 +242,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
+#define _MMIO_PLL3(pll, a, b, c) _MMIO(_PICK(pll, a, b, c))
/*
* Device info offset array based helpers for groups of registers with unevenly
@@ -9951,6 +9952,22 @@ enum skl_power_gate {
#define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \
_ICL_DPLL1_CFGCR1)
+#define _TGL_DPLL0_CFGCR0 0x164284
+#define _TGL_DPLL1_CFGCR0 0x16428C
+/* TODO: add DPLL4 */
+#define _TGL_TBTPLL_CFGCR0 0x16429C
+#define TGL_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
+ _TGL_DPLL1_CFGCR0, \
+ _TGL_TBTPLL_CFGCR0)
+
+#define _TGL_DPLL0_CFGCR1 0x164288
+#define _TGL_DPLL1_CFGCR1 0x164290
+/* TODO: add DPLL4 */
+#define _TGL_TBTPLL_CFGCR1 0x1642A0
+#define TGL_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
+ _TGL_DPLL1_CFGCR1, \
+ _TGL_TBTPLL_CFGCR1)
+
/* BXT display engine PLL */
#define BXT_DE_PLL_CTL _MMIO(0x6d000)
#define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */
--
2.21.0
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[Intel-gfx] [CI 02/21] drm/i915/tgl: add initial Tiger Lake definitions
From: Daniele Ceraolo Spurio
Tiger Lake is a Intel® Processor containing Intel® HD Graphics.
This is just an initial Tiger Lake definition. PCI IDs, generic support
and new features coming in following patches.
v2 (Lucas):
- Remove modular FIA - feature will be re-introduced in future
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
Reviewed-by: Anusha Srivatsa
Link:
https://patchwork.freedesktop.org/patch/msgid/20190708231629.9296-3-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_pci.c | 29
drivers/gpu/drm/i915/intel_device_info.c | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 2 ++
4 files changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f9878cbef4d9..989ca1e02cc1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2088,6 +2088,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_CANNONLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
#define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
#define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
+#define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev_priv) \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 94b588e0a1dd..da926485845d 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -765,6 +765,35 @@ static const struct intel_device_info
intel_elkhartlake_info = {
.ppgtt_size = 36,
};
+#define GEN12_FEATURES \
+ GEN11_FEATURES, \
+ GEN(12), \
+ .pipe_offsets = { \
+ [TRANSCODER_A] = PIPE_A_OFFSET, \
+ [TRANSCODER_B] = PIPE_B_OFFSET, \
+ [TRANSCODER_C] = PIPE_C_OFFSET, \
+ [TRANSCODER_D] = PIPE_D_OFFSET, \
+ [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
+ [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
+ }, \
+ .trans_offsets = { \
+ [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
+ [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
+ [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
+ [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
+ [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
+ [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
+ }
+
+static const struct intel_device_info intel_tigerlake_12_info = {
+ GEN12_FEATURES,
+ PLATFORM(INTEL_TIGERLAKE),
+ .num_pipes = 4,
+ .require_force_probe = 1,
+ .engine_mask =
+ BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
+};
+
#undef GEN
#undef PLATFORM
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index e64536e1fd1b..e0d9a7a37994 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -58,6 +58,7 @@ static const char * const platform_names[] = {
PLATFORM_NAME(CANNONLAKE),
PLATFORM_NAME(ICELAKE),
PLATFORM_NAME(ELKHARTLAKE),
+ PLATFORM_NAME(TIGERLAKE),
};
#undef PLATFORM_NAME
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index ddafc819bf30..468582484758 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -78,6 +78,8 @@ enum intel_platform {
/* gen11 */
INTEL_ICELAKE,
INTEL_ELKHARTLAKE,
+ /* gen12 */
+ INTEL_TIGERLAKE,
INTEL_MAX_PLATFORMS
};
--
2.21.0
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[Intel-gfx] [CI 10/21] drm/i915/tgl: Add new pll ids
From: Vandita Kulkarni
Add 2 new PLLs for additional TC ports. The names for the PLLs on TGL
changed, but most registers remained the same, like MGPLL5_ENABLE,
MGPLL6_ENABLE. So continue to use the name from ICL.
Cc: Madhav Chauhan
Cc: Rodrigo Vivi
Signed-off-by: Vandita Kulkarni
Signed-off-by: Lucas De Marchi
Reviewed-by: Anusha Srivatsa
Link:
https://patchwork.freedesktop.org/patch/msgid/20190708231629.9296-12-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 23 +++
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 4c2c5e93aff3..d0e14ed6e5f8 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -112,11 +112,11 @@ enum intel_dpll_id {
/**
-* @DPLL_ID_ICL_DPLL0: ICL combo PHY DPLL0
+* @DPLL_ID_ICL_DPLL0: ICL/TGL combo PHY DPLL0
*/
DPLL_ID_ICL_DPLL0 = 0,
/**
-* @DPLL_ID_ICL_DPLL1: ICL combo PHY DPLL1
+* @DPLL_ID_ICL_DPLL1: ICL/TGL combo PHY DPLL1
*/
DPLL_ID_ICL_DPLL1 = 1,
/**
@@ -124,27 +124,40 @@ enum intel_dpll_id {
*/
DPLL_ID_EHL_DPLL4 = 2,
/**
-* @DPLL_ID_ICL_TBTPLL: ICL TBT PLL
+* @DPLL_ID_ICL_TBTPLL: ICL/TGL TBT PLL
*/
DPLL_ID_ICL_TBTPLL = 2,
/**
-* @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C)
+* @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C),
+* TGL TC PLL 1 port 1 (TC1)
*/
DPLL_ID_ICL_MGPLL1 = 3,
/**
* @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D)
+* TGL TC PLL 1 port 2 (TC2)
*/
DPLL_ID_ICL_MGPLL2 = 4,
/**
* @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E)
+* TGL TC PLL 1 port 3 (TC3)
*/
DPLL_ID_ICL_MGPLL3 = 5,
/**
* @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F)
+* TGL TC PLL 1 port 4 (TC4)
*/
DPLL_ID_ICL_MGPLL4 = 6,
+ /**
+* @DPLL_ID_TGL_TCPLL5: TGL TC PLL port 5 (TC5)
+*/
+ DPLL_ID_TGL_MGPLL5 = 7,
+ /**
+* @DPLL_ID_TGL_TCPLL6: TGL TC PLL port 6 (TC6)
+*/
+ DPLL_ID_TGL_MGPLL6 = 8,
};
-#define I915_NUM_PLLS 7
+
+#define I915_NUM_PLLS 9
enum icl_port_dpll_id {
ICL_PORT_DPLL_DEFAULT,
--
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[Intel-gfx] [CI 17/21] drm/i915/tgl: Add gmbus gpio pin to port mapping
From: Mahesh Kumar
Add default GPIO pin mapping for all ports. Tiger Lake has 3 combophy
ports and 6 TC ports, gpio pin1-3 are mapped to combophy & pin9-14 are
mapped to TC ports.
Cc: Anusha Srivatsa
Cc: Rodrigo Vivi
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
Link:
https://patchwork.freedesktop.org/patch/msgid/20190708231629.9296-16-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/display/intel_display.h | 2 ++
drivers/gpu/drm/i915/display/intel_gmbus.c | 20 ++--
drivers/gpu/drm/i915/i915_reg.h | 4 +++-
3 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index b0794f7c255d..b224638e6f28 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -45,6 +45,8 @@ enum i915_gpio {
GPIOK,
GPIOL,
GPIOM,
+ GPION,
+ GPIOO,
};
/*
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c
b/drivers/gpu/drm/i915/display/intel_gmbus.c
index 4f6a9bd5af47..b42c79aea61a 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -94,11 +94,25 @@ static const struct gmbus_pin gmbus_pins_mcc[] = {
[GMBUS_PIN_9_TC1_ICP] = { "dpc", GPIOJ },
};
+static const struct gmbus_pin gmbus_pins_tgp[] = {
+ [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
+ [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
+ [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
+ [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
+ [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
+ [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
+ [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
+ [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION },
+ [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO },
+};
+
/* pin is expected to be valid */
static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
unsigned int pin)
{
- if (HAS_PCH_MCC(dev_priv))
+ if (HAS_PCH_TGP(dev_priv))
+ return _pins_tgp[pin];
+ else if (HAS_PCH_MCC(dev_priv))
return _pins_mcc[pin];
else if (HAS_PCH_ICP(dev_priv))
return _pins_icp[pin];
@@ -119,7 +133,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private
*dev_priv,
{
unsigned int size;
- if (HAS_PCH_MCC(dev_priv))
+ if (HAS_PCH_TGP(dev_priv))
+ size = ARRAY_SIZE(gmbus_pins_tgp);
+ else if (HAS_PCH_MCC(dev_priv))
size = ARRAY_SIZE(gmbus_pins_mcc);
else if (HAS_PCH_ICP(dev_priv))
size = ARRAY_SIZE(gmbus_pins_icp);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d07e92678c41..87f79dc8e0c3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3254,8 +3254,10 @@ enum i915_power_well_id {
#define GMBUS_PIN_10_TC2_ICP 10
#define GMBUS_PIN_11_TC3_ICP 11
#define GMBUS_PIN_12_TC4_ICP 12
+#define GMBUS_PIN_13_TC5_TGP 13
+#define GMBUS_PIN_14_TC6_TGP 14
-#define GMBUS_NUM_PINS 13 /* including 0 */
+#define GMBUS_NUM_PINS 15 /* including 0 */
#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /*
command/status */
#define GMBUS_SW_CLR_INT (1 << 31)
#define GMBUS_SW_RDY (1 << 30)
--
2.21.0
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[Intel-gfx] [CI 06/21] drm/i915/tgl: Check if pipe D is fused
From: José Roberto de Souza
On Tiger Lake there is one more pipe - check if it's fused.
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
Reviewed-by: Mika Kahola
Link:
https://patchwork.freedesktop.org/patch/msgid/20190708231629.9296-8-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_device_info.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 31c6c168dde2..08dc71e4b818 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7633,6 +7633,7 @@ enum {
#define SKL_DFSM_PIPE_A_DISABLE(1 << 30)
#define SKL_DFSM_PIPE_B_DISABLE(1 << 21)
#define SKL_DFSM_PIPE_C_DISABLE(1 << 28)
+#define TGL_DFSM_PIPE_D_DISABLE(1 << 22)
#define SKL_DSSM _MMIO(0x51004)
#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz(1 << 31)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index e0d9a7a37994..f99c9fd497b2 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -938,6 +938,9 @@ void intel_device_info_runtime_init(struct drm_i915_private
*dev_priv)
enabled_mask &= ~BIT(PIPE_B);
if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
enabled_mask &= ~BIT(PIPE_C);
+ if (INTEL_GEN(dev_priv) >= 12 &&
+ (dfsm & TGL_DFSM_PIPE_D_DISABLE))
+ enabled_mask &= ~BIT(PIPE_D);
/*
* At least one pipe should be enabled and if there are
--
2.21.0
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[Intel-gfx] [CI 16/21] drm/i915/gen12: MBUS B credit change
From: Rodrigo Vivi
Previously, the recommended B credit for all platforms was 24 / number
of pipes, which would give 6 for newer platforms with 4 pipes. However 6
is not enough and we need 12 on these cases.
We also need a different BW credit for these platforms.
Cc: Arthur J Runyan
Signed-off-by: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
Reviewed-by: Ville Syrjälä
Link:
https://patchwork.freedesktop.org/patch/msgid/20190708231629.9296-23-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/display/intel_display.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 500bb3fd2939..8ab6aef4a67c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6423,8 +6423,14 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
u32 val;
val = MBUS_DBOX_A_CREDIT(2);
- val |= MBUS_DBOX_BW_CREDIT(1);
- val |= MBUS_DBOX_B_CREDIT(8);
+
+ if (INTEL_GEN(dev_priv) >= 12) {
+ val |= MBUS_DBOX_BW_CREDIT(2);
+ val |= MBUS_DBOX_B_CREDIT(12);
+ } else {
+ val |= MBUS_DBOX_BW_CREDIT(1);
+ val |= MBUS_DBOX_B_CREDIT(8);
+ }
I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
}
--
2.21.0
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[Intel-gfx] [CI 18/21] drm/i915/tgl: port to ddc pin mapping
Make the icl function generic so it is based on phy type and can be
applied to tgl as well.
I checked if this could not apply to EHL as well, but unfortunately
there the HPD and DDC/GMBUS pins for DDI C are mapped to TypeC Port 1
even though it doesn't have TC phy.
v2: don't add a separate function for TGL, but rather reuse the ICL one
(suggested by Rodrigo)
Cc: Anusha Srivatsa
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
Link:
https://patchwork.freedesktop.org/patch/msgid/20190709170044.29489-1-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 34 +--
1 file changed, 7 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 0ebec69bbbfc..dfdcd25eda02 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2930,33 +2930,13 @@ static u8 cnp_port_to_ddc_pin(struct drm_i915_private
*dev_priv,
static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port
port)
{
- u8 ddc_pin;
+ if (intel_port_is_combophy(dev_priv, port))
+ return GMBUS_PIN_1_BXT + port;
+ else if (intel_port_is_tc(dev_priv, port))
+ return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port);
- switch (port) {
- case PORT_A:
- ddc_pin = GMBUS_PIN_1_BXT;
- break;
- case PORT_B:
- ddc_pin = GMBUS_PIN_2_BXT;
- break;
- case PORT_C:
- ddc_pin = GMBUS_PIN_9_TC1_ICP;
- break;
- case PORT_D:
- ddc_pin = GMBUS_PIN_10_TC2_ICP;
- break;
- case PORT_E:
- ddc_pin = GMBUS_PIN_11_TC3_ICP;
- break;
- case PORT_F:
- ddc_pin = GMBUS_PIN_12_TC4_ICP;
- break;
- default:
- MISSING_CASE(port);
- ddc_pin = GMBUS_PIN_2_BXT;
- break;
- }
- return ddc_pin;
+ WARN(1, "Unknown port:%c\n", port_name(port));
+ return GMBUS_PIN_2_BXT;
}
static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port
port)
@@ -3019,7 +2999,7 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private
*dev_priv,
if (HAS_PCH_MCC(dev_priv))
ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
- else if (HAS_PCH_ICP(dev_priv))
+ else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_ICP(dev_priv))
ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
else if (HAS_PCH_CNP(dev_priv))
ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
--
2.21.0
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[Intel-gfx] [CI 08/21] drm/i915/tgl: Add power well support
From: Imre Deak
The patch adds the new power wells introduced by TGL (GEN 12) and
maps these to existing/new power domains. The changes for GEN 12 wrt
to GEN 11 are the following:
- Transcoder#EDP removed from power well#1 (Transcoder#A used in
low-power mode instead)
- Transcoder#A is now backed by power well#1 instead of power well#3
- The DDI#B/C combo PHY ports are now backed by power well#1 instead of
power well#3
- New power well#5 added for pipe#D functionality (TODO)
- 2 additional TC ports (TC#5-6) backed by power well#3, 2 port
specific IO power wells (only for the non-TBT modes) and 4 port
specific AUX power wells (2-2 for TBT vs. non-TBT modes)
- Power well#2 backs now VDSC/joining for pipe#A instead of VDSC for
eDP and MIPI DSI (TODO)
On TGL Port DDI#C changed to be a combo PHY (native DP/HDMI) and
BSpec has renamed ports DDI#D-F to TC#4-6 respectively. Thus on ICL we
have the following naming for ports:
- Combo PHYs (native DP/HDMI):
DDI#A-B
- TBT/non-TBT (TC altmode, native DP/HDMI) PHYs:
DDI#C-F
Starting from GEN 12 we have the following naming for ports:
- Combo PHYs (native DP/HDMI):
DDI#A-C
- TBT/non-TBT (TC altmode, native DP/HDMI) PHYs:
DDI TC#1-6
To save some space in the power domain enum the power domain naming in
the driver reflects the above change, that is power domains TC#1-3 are
added as aliases for DDI#D-F and new power domains are reserved for
TC#4-6.
v2 (Lucas):
- Separate out the bits and definitions for TGL from the ICL ones.
Fix use of TRANSCODER_EDP_VDSC, that is now the correct define since
we don't define TRANSCODER_A_VDSC power domain to spare a one bit in
the bitmask (suggested by Ville)
v3 (Lucas):
- Fix missing squashes on v2
- Rebase on renamed TRANSCODER_EDP_VDSC
Cc: Ville Syrjälä
Cc: Anusha Srivatsa
Cc: Rodrigo Vivi
Cc: José Roberto de Souza
Signed-off-by: Imre Deak
Signed-off-by: Lucas De Marchi
Reviewed-by: Ville Syrjälä
Link:
https://patchwork.freedesktop.org/patch/msgid/20190708231629.9296-10-lucas.demar...@intel.com
---
.../drm/i915/display/intel_display_power.c| 474 +-
.../drm/i915/display/intel_display_power.h| 26 +-
drivers/gpu/drm/i915/i915_debugfs.c | 3 +-
drivers/gpu/drm/i915/i915_reg.h | 20 +-
4 files changed, 506 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 4f4c35a5ef2a..fead072afd96 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -23,8 +23,11 @@ bool intel_display_power_well_is_enabled(struct
drm_i915_private *dev_priv,
enum i915_power_well_id power_well_id);
const char *
-intel_display_power_domain_str(enum intel_display_power_domain domain)
+intel_display_power_domain_str(struct drm_i915_private *i915,
+ enum intel_display_power_domain domain)
{
+ bool ddi_tc_ports = IS_GEN(i915, 12);
+
switch (domain) {
case POWER_DOMAIN_DISPLAY_CORE:
return "DISPLAY_CORE";
@@ -61,11 +64,23 @@ intel_display_power_domain_str(enum
intel_display_power_domain domain)
case POWER_DOMAIN_PORT_DDI_C_LANES:
return "PORT_DDI_C_LANES";
case POWER_DOMAIN_PORT_DDI_D_LANES:
- return "PORT_DDI_D_LANES";
+ BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_D_LANES !=
+POWER_DOMAIN_PORT_DDI_TC1_LANES);
+ return ddi_tc_ports ? "PORT_DDI_TC1_LANES" : "PORT_DDI_D_LANES";
case POWER_DOMAIN_PORT_DDI_E_LANES:
- return "PORT_DDI_E_LANES";
+ BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_E_LANES !=
+POWER_DOMAIN_PORT_DDI_TC2_LANES);
+ return ddi_tc_ports ? "PORT_DDI_TC2_LANES" : "PORT_DDI_E_LANES";
case POWER_DOMAIN_PORT_DDI_F_LANES:
- return "PORT_DDI_F_LANES";
+ BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_F_LANES !=
+POWER_DOMAIN_PORT_DDI_TC3_LANES);
+ return ddi_tc_ports ? "PORT_DDI_TC3_LANES" : "PORT_DDI_F_LANES";
+ case POWER_DOMAIN_PORT_DDI_TC4_LANES:
+ return "PORT_DDI_TC4_LANES";
+ case POWER_DOMAIN_PORT_DDI_TC5_LANES:
+ return "PORT_DDI_TC5_LANES";
+ case POWER_DOMAIN_PORT_DDI_TC6_LANES:
+ return "PORT_DDI_TC6_LANES";
case POWER_DOMAIN_PORT_DDI_A_IO:
return "PORT_DDI_A_IO";
case POWER_DOMAIN_PORT_DDI_B_IO:
@@ -73,11 +88,23 @@ intel_display_power_domain_str(enum
intel_display_power_domain domain)
case POWER_DOMAIN_PORT_DDI_C_IO:
return "PORT_DDI_C_IO";
case POWER_DOMAIN_PORT_DDI_D_IO:
- return "PORT_DDI_D_IO";
+ BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_D_IO !=
+
[Intel-gfx] [CI 07/21] drm/i915/tgl: rename TRANSCODER_EDP_VDSC to use on transcoder A
From: José Roberto de Souza
On TGL the special EDP transcoder is gone and it should be handled by
transcoder A.
v2 (Lucas):
- Reuse POWER_DOMAIN_TRANSCODER_EDP_VDSC (suggested by Ville)
- Use crtc->dev since new_crtc_state->state may be NULL on atomic
commit (suggested by Maarten)
v3 (Lucas):
- Rename power domain so it's clear it can also be used for transcoder
A in TGL (requested by José and Manasi)
Cc: Imre Deak
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
Acked-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_display_power.c | 6 +++---
drivers/gpu/drm/i915/display/intel_display_power.h | 3 ++-
drivers/gpu/drm/i915/display/intel_vdsc.c | 14 ++
3 files changed, 15 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 7437fc71d289..4f4c35a5ef2a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -48,8 +48,8 @@ intel_display_power_domain_str(enum
intel_display_power_domain domain)
return "TRANSCODER_C";
case POWER_DOMAIN_TRANSCODER_EDP:
return "TRANSCODER_EDP";
- case POWER_DOMAIN_TRANSCODER_EDP_VDSC:
- return "TRANSCODER_EDP_VDSC";
+ case POWER_DOMAIN_TRANSCODER_VDSC_PW2:
+ return "TRANSCODER_VDSC_PW2";
case POWER_DOMAIN_TRANSCODER_DSI_A:
return "TRANSCODER_DSI_A";
case POWER_DOMAIN_TRANSCODER_DSI_C:
@@ -2448,7 +2448,7 @@ void intel_display_power_put(struct drm_i915_private
*dev_priv,
*/
#define ICL_PW_2_POWER_DOMAINS ( \
ICL_PW_3_POWER_DOMAINS |\
- BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
BIT_ULL(POWER_DOMAIN_INIT))
/*
* - KVMR (HW control)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
b/drivers/gpu/drm/i915/display/intel_display_power.h
index 8f43f7051a16..cc6956132ebc 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -25,7 +25,8 @@ enum intel_display_power_domain {
POWER_DOMAIN_TRANSCODER_B,
POWER_DOMAIN_TRANSCODER_C,
POWER_DOMAIN_TRANSCODER_EDP,
- POWER_DOMAIN_TRANSCODER_EDP_VDSC,
+ /* VDSC/joining for TRANSCODER_EDP (ICL) or TRANSCODER_A (TGL) */
+ POWER_DOMAIN_TRANSCODER_VDSC_PW2,
POWER_DOMAIN_TRANSCODER_DSI_A,
POWER_DOMAIN_TRANSCODER_DSI_C,
POWER_DOMAIN_PORT_DDI_A_LANES,
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
b/drivers/gpu/drm/i915/display/intel_vdsc.c
index ffec807b8960..4ab19c432ef5 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -459,17 +459,23 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
enum intel_display_power_domain
intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
{
+ struct drm_i915_private *i915 = to_i915(crtc_state->base.crtc->dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
/*
-* On ICL VDSC/joining for eDP transcoder uses a separate power well PW2
-* This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
+* On ICL VDSC/joining for eDP transcoder uses a separate power well,
+* PW2. This requires POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain.
* For any other transcoder, VDSC/joining uses the power well associated
* with the pipe/transcoder in use. Hence another reference on the
* transcoder power domain will suffice.
+*
+* On TGL we have the same mapping, but for transcoder A (the special
+* TRANSCODER_EDP is gone).
*/
- if (cpu_transcoder == TRANSCODER_EDP)
- return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
+ if (INTEL_GEN(i915) >= 12 && cpu_transcoder == TRANSCODER_A)
+ return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
+ else if (cpu_transcoder == TRANSCODER_EDP)
+ return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
else
return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
}
--
2.21.0
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[Intel-gfx] [CI 04/21] drm/i915/tgl: Add TGL PCH detection in virtualized environment
From: Mahesh Kumar Assume PCH_TGP when platform is TGL. Cc: Rodrigo Vivi Signed-off-by: Mahesh Kumar Signed-off-by: Lucas De Marchi Reviewed-by: Anusha Srivatsa Link: https://patchwork.freedesktop.org/patch/msgid/20190708231629.9296-5-lucas.demar...@intel.com --- drivers/gpu/drm/i915/i915_drv.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index bcedd2d8e267..926bbf2d169b 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -255,7 +255,9 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv) * make an educated guess as to which PCH is really there. */ - if (IS_ELKHARTLAKE(dev_priv)) + if (IS_TIGERLAKE(dev_priv)) + id = INTEL_PCH_TGP_DEVICE_ID_TYPE; + else if (IS_ELKHARTLAKE(dev_priv)) id = INTEL_PCH_MCC_DEVICE_ID_TYPE; else if (IS_ICELAKE(dev_priv)) id = INTEL_PCH_ICP_DEVICE_ID_TYPE; -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 01/21] drm/i915: Add 4th pipe and transcoder
Add pipe D and transcoder D to prepare for platforms having them.
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
Reviewed-by: Ville Syrjälä
Link:
https://patchwork.freedesktop.org/patch/msgid/20190708231629.9296-2-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
drivers/gpu/drm/i915/display/intel_display.h | 4
drivers/gpu/drm/i915/i915_reg.h | 3 +++
3 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index f07081815b80..db01ea08f30b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -17176,7 +17176,7 @@ struct intel_display_error_state {
u32 vtotal;
u32 vblank;
u32 vsync;
- } transcoder[4];
+ } transcoder[5];
};
struct intel_display_error_state *
@@ -17187,6 +17187,7 @@ intel_display_capture_error_state(struct
drm_i915_private *dev_priv)
TRANSCODER_A,
TRANSCODER_B,
TRANSCODER_C,
+ TRANSCODER_D,
TRANSCODER_EDP,
};
int i;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index d296556ed82e..e781df463ffa 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -58,6 +58,7 @@ enum pipe {
PIPE_A = 0,
PIPE_B,
PIPE_C,
+ PIPE_D,
_PIPE_EDP,
I915_MAX_PIPES = _PIPE_EDP
@@ -75,6 +76,7 @@ enum transcoder {
TRANSCODER_A = PIPE_A,
TRANSCODER_B = PIPE_B,
TRANSCODER_C = PIPE_C,
+ TRANSCODER_D = PIPE_D,
/*
* The following transcoders can map to any pipe, their enum value
@@ -98,6 +100,8 @@ static inline const char *transcoder_name(enum transcoder
transcoder)
return "B";
case TRANSCODER_C:
return "C";
+ case TRANSCODER_D:
+ return "D";
case TRANSCODER_EDP:
return "EDP";
case TRANSCODER_DSI_A:
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5898f59e3dd7..31c6c168dde2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4217,6 +4217,7 @@ enum {
#define TRANSCODER_B_OFFSET 0x61000
#define TRANSCODER_C_OFFSET 0x62000
#define CHV_TRANSCODER_C_OFFSET 0x63000
+#define TRANSCODER_D_OFFSET 0x63000
#define TRANSCODER_EDP_OFFSET 0x6f000
#define TRANSCODER_DSI0_OFFSET 0x6b000
#define TRANSCODER_DSI1_OFFSET 0x6b800
@@ -5763,6 +5764,7 @@ enum {
#define PIPE_A_OFFSET 0x7
#define PIPE_B_OFFSET 0x71000
#define PIPE_C_OFFSET 0x72000
+#define PIPE_D_OFFSET 0x73000
#define CHV_PIPE_C_OFFSET 0x74000
/*
* There's actually no pipe EDP. Some pipe registers have
@@ -9346,6 +9348,7 @@ enum skl_power_gate {
#define _TRANS_DDI_FUNC_CTL_A 0x60400
#define _TRANS_DDI_FUNC_CTL_B 0x61400
#define _TRANS_DDI_FUNC_CTL_C 0x62400
+#define _TRANS_DDI_FUNC_CTL_D 0x63400
#define _TRANS_DDI_FUNC_CTL_EDP0x6F400
#define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400
#define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00
--
2.21.0
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Re: [Intel-gfx] [PATCH v2 20/25] drm/i915/tgl: Add vbt value mapping for DDC Bus pin
On Mon, 2019-07-08 at 16:16 -0700, Lucas De Marchi wrote:
> From: Mahesh Kumar
>
> Add VBT-value to DDC bus pin mapping for the same.
We have almost the same information in 3 different places as per patch
15, 16 and this one =/
Anyways lets not block TGL to do refactors:
Reviewed-by: José Roberto de Souza
>
> Signed-off-by: Mahesh Kumar
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 17 -
> drivers/gpu/drm/i915/display/intel_vbt_defs.h | 3 +++
> 2 files changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index 0c9808132d67..a08bc4f617c8 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -1354,12 +1354,27 @@ static const u8 mcc_ddc_pin_map[] = {
> [MCC_DDC_BUS_DDI_C] = GMBUS_PIN_9_TC1_ICP,
> };
>
> +static const u8 tgp_ddc_pin_map[] = {
> + [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
> + [ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT,
> + [TGL_DDC_BUS_DDI_C] = GMBUS_PIN_3_BXT,
> + [ICL_DDC_BUS_PORT_1] = GMBUS_PIN_9_TC1_ICP,
> + [ICL_DDC_BUS_PORT_2] = GMBUS_PIN_10_TC2_ICP,
> + [ICL_DDC_BUS_PORT_3] = GMBUS_PIN_11_TC3_ICP,
> + [ICL_DDC_BUS_PORT_4] = GMBUS_PIN_12_TC4_ICP,
> + [TGL_DDC_BUS_PORT_5] = GMBUS_PIN_13_TC5_TGP,
> + [TGL_DDC_BUS_PORT_6] = GMBUS_PIN_14_TC6_TGP,
> +};
> +
> static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
> {
> const u8 *ddc_pin_map;
> int n_entries;
>
> - if (HAS_PCH_MCC(dev_priv)) {
> + if (HAS_PCH_TGP(dev_priv)) {
> + ddc_pin_map = tgp_ddc_pin_map;
> + n_entries = ARRAY_SIZE(tgp_ddc_pin_map);
> + } else if (HAS_PCH_MCC(dev_priv)) {
> ddc_pin_map = mcc_ddc_pin_map;
> n_entries = ARRAY_SIZE(mcc_ddc_pin_map);
> } else if (HAS_PCH_ICP(dev_priv)) {
> diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> index 2f4894e9a03d..93f5c9d204d6 100644
> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> @@ -310,10 +310,13 @@ enum vbt_gmbus_ddi {
> DDC_BUS_DDI_F,
> ICL_DDC_BUS_DDI_A = 0x1,
> ICL_DDC_BUS_DDI_B,
> + TGL_DDC_BUS_DDI_C,
> ICL_DDC_BUS_PORT_1 = 0x4,
> ICL_DDC_BUS_PORT_2,
> ICL_DDC_BUS_PORT_3,
> ICL_DDC_BUS_PORT_4,
> + TGL_DDC_BUS_PORT_5,
> + TGL_DDC_BUS_PORT_6,
> MCC_DDC_BUS_DDI_A = 0x1,
> MCC_DDC_BUS_DDI_B,
> MCC_DDC_BUS_DDI_C = 0x4,
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Re: [Intel-gfx] [PATCH v2 15/25] drm/i915/tgl: Add gmbus gpio pin to port mapping
On Mon, 2019-07-08 at 16:16 -0700, Lucas De Marchi wrote:
> From: Mahesh Kumar
>
> Add default GPIO pin mapping for all ports. Tiger Lake has 3 combophy
> ports and 6 TC ports, gpio pin1-3 are mapped to combophy & pin9-14
> are
> mapped to TC ports.
Reviewed-by: José Roberto de Souza
>
> Cc: Anusha Srivatsa
> Cc: Rodrigo Vivi
> Signed-off-by: Mahesh Kumar
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_display.h | 2 ++
> drivers/gpu/drm/i915/display/intel_gmbus.c | 20
> ++--
> drivers/gpu/drm/i915/i915_reg.h | 4 +++-
> 3 files changed, 23 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> b/drivers/gpu/drm/i915/display/intel_display.h
> index 270b1f18dedd..231d8595845a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -45,6 +45,8 @@ enum i915_gpio {
> GPIOK,
> GPIOL,
> GPIOM,
> + GPION,
> + GPIOO,
> };
>
> /*
> diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c
> b/drivers/gpu/drm/i915/display/intel_gmbus.c
> index 4f6a9bd5af47..b42c79aea61a 100644
> --- a/drivers/gpu/drm/i915/display/intel_gmbus.c
> +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
> @@ -94,11 +94,25 @@ static const struct gmbus_pin gmbus_pins_mcc[] =
> {
> [GMBUS_PIN_9_TC1_ICP] = { "dpc", GPIOJ },
> };
>
> +static const struct gmbus_pin gmbus_pins_tgp[] = {
> + [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
> + [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
> + [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
> + [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
> + [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
> + [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
> + [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
> + [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION },
> + [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO },
> +};
> +
> /* pin is expected to be valid */
> static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private
> *dev_priv,
>unsigned int pin)
> {
> - if (HAS_PCH_MCC(dev_priv))
> + if (HAS_PCH_TGP(dev_priv))
> + return _pins_tgp[pin];
> + else if (HAS_PCH_MCC(dev_priv))
> return _pins_mcc[pin];
> else if (HAS_PCH_ICP(dev_priv))
> return _pins_icp[pin];
> @@ -119,7 +133,9 @@ bool intel_gmbus_is_valid_pin(struct
> drm_i915_private *dev_priv,
> {
> unsigned int size;
>
> - if (HAS_PCH_MCC(dev_priv))
> + if (HAS_PCH_TGP(dev_priv))
> + size = ARRAY_SIZE(gmbus_pins_tgp);
> + else if (HAS_PCH_MCC(dev_priv))
> size = ARRAY_SIZE(gmbus_pins_mcc);
> else if (HAS_PCH_ICP(dev_priv))
> size = ARRAY_SIZE(gmbus_pins_icp);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 4588df9e11de..c554df69f289 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3254,8 +3254,10 @@ enum i915_power_well_id {
> #define GMBUS_PIN_10_TC2_ICP 10
> #define GMBUS_PIN_11_TC3_ICP 11
> #define GMBUS_PIN_12_TC4_ICP 12
> +#define GMBUS_PIN_13_TC5_TGP 13
> +#define GMBUS_PIN_14_TC6_TGP 14
>
> -#define GMBUS_NUM_PINS 13 /* including 0 */
> +#define GMBUS_NUM_PINS 15 /* including 0 */
> #define GMBUS1 _MMIO(dev_priv->gpio_mmio_base
> + 0x5104) /* command/status */
> #define GMBUS_SW_CLR_INT (1 << 31)
> #define GMBUS_SW_RDY (1 << 30)
___
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Re: [Intel-gfx] [PATCH v8 06/13] drm/i915/perf: implement active wait for noa configurations
On Tue, Jul 09, 2019 at 03:33:44PM +0300, Lionel Landwerlin wrote:
NOA configuration take some amount of time to apply. That amount of
time depends on the size of the GT. There is no documented time for
this. For example, past experimentations with powergating
configuration changes seem to indicate a 60~70us delay. We go with
500us as default for now which should be over the required amount of
time (according to HW architects).
v2: Don't forget to save/restore registers used for the wait (Chris)
v3: Name used CS_GPR registers (Chris)
Fix compile issue due to rebase (Lionel)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 24 ++
drivers/gpu/drm/i915/gt/intel_gt_types.h | 5 +
drivers/gpu/drm/i915/i915_debugfs.c | 31 +++
drivers/gpu/drm/i915/i915_drv.h | 8 +
drivers/gpu/drm/i915/i915_perf.c | 226 ++-
drivers/gpu/drm/i915/i915_reg.h | 4 +-
6 files changed, 295 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index e7eff9db343e..4a66af38c87b 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -151,6 +151,7 @@
#define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
#define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
#define MI_BATCH_RESOURCE_STREAMER (1<<10)
+#define MI_BATCH_PREDICATE (1 << 15) /* HSW+ on RCS only*/
/*
* 3D instructions used by the kernel
@@ -226,6 +227,29 @@
#define PIPE_CONTROL_DEPTH_CACHE_FLUSH(1<<0)
#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
+#define MI_MATH(x) MI_INSTR(0x1a, (x)-1)
+#define MI_ALU_OP(op, src1, src2) (((op) << 20) | ((src1) << 10) | (src2))
+/* operands */
+#define MI_ALU_OP_NOOP 0
+#define MI_ALU_OP_LOAD 128
+#define MI_ALU_OP_LOADINV 1152
+#define MI_ALU_OP_LOAD0129
+#define MI_ALU_OP_LOAD11153
+#define MI_ALU_OP_ADD 256
+#define MI_ALU_OP_SUB 257
+#define MI_ALU_OP_AND 258
+#define MI_ALU_OP_OR 259
+#define MI_ALU_OP_XOR 260
+#define MI_ALU_OP_STORE384
+#define MI_ALU_OP_STOREINV 1408
+/* sources */
+#define MI_ALU_SRC_REG(x) (x) /* 0 -> 15 */
+#define MI_ALU_SRC_SRCA32
+#define MI_ALU_SRC_SRCB33
+#define MI_ALU_SRC_ACCU49
+#define MI_ALU_SRC_ZF 50
+#define MI_ALU_SRC_CF 51
+
/*
* Commands used only by the command parser
*/
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 3563ce970102..a3141b79d344 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -73,6 +73,11 @@ enum intel_gt_scratch_field {
/* 8 bytes */
INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA = 256,
+ /* 6 * 8 bytes */
+ INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR = 2048,
+
+ /* 4 bytes */
+ INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1 = 2096,
};
#endif /* __INTEL_GT_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 3e4f58f19362..46fca53dfbda 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3653,6 +3653,36 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
i915_wedged_get, i915_wedged_set,
"%llu\n");
+static int
+i915_perf_noa_delay_set(void *data, u64 val)
+{
+ struct drm_i915_private *i915 = data;
+
+ /* This would lead to infinite waits as we're doing timestamp
+* difference on the CS with only 32bits.
+*/
+ if (val > ((1ul << 32) - 1) *
RUNTIME_INFO(i915)->cs_timestamp_frequency_khz)
+ return -EINVAL;
+
+ atomic64_set(>perf.oa.noa_programming_delay, val);
+ return 0;
+}
+
+static int
+i915_perf_noa_delay_get(void *data, u64 *val)
+{
+ struct drm_i915_private *i915 = data;
+
+ *val = atomic64_read(>perf.oa.noa_programming_delay);
+ return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(i915_perf_noa_delay_fops,
+ i915_perf_noa_delay_get,
+ i915_perf_noa_delay_set,
+ "%llu\n");
+
+
#define DROP_UNBOUNDBIT(0)
#define DROP_BOUND BIT(1)
#define DROP_RETIRE BIT(2)
@@ -4418,6 +4448,7 @@ static const struct i915_debugfs_files {
const char *name;
const struct file_operations *fops;
} i915_debugfs_files[] = {
+ {"i915_perf_noa_delay", _perf_noa_delay_fops},
{"i915_wedged", _wedged_fops},
{"i915_cache_sharing", _cache_sharing_fops},
{"i915_gem_drop_caches", _drop_caches_fops},
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0419dfd0dea3..b3c6dd72c7a1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1834,6
Re: [Intel-gfx] [PATCH] drm/i915/tgl: rename TRANSCODER_EDP_VDSC to use on transcoder A
On Wed, 2019-07-10 at 12:49 -0700, Lucas De Marchi wrote:
> From: José Roberto de Souza
>
> On TGL the special EDP transcoder is gone and it should be handled by
> transcoder A.
>
> v2 (Lucas):
> - Reuse POWER_DOMAIN_TRANSCODER_EDP_VDSC (suggested by Ville)
> - Use crtc->dev since new_crtc_state->state may be NULL on atomic
> commit (suggested by Maarten)
> v3 (Lucas):
> - Rename power domain so it's clear it can also be used for
> transcoder
> A in TGL (requested by José and Manasi)
>
Acked-by: José Roberto de Souza
> Cc: Imre Deak
> Signed-off-by: José Roberto de Souza
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_display_power.c | 6 +++---
> drivers/gpu/drm/i915/display/intel_display_power.h | 3 ++-
> drivers/gpu/drm/i915/display/intel_vdsc.c | 14 ++
>
> 3 files changed, 15 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 7437fc71d289..4f4c35a5ef2a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -48,8 +48,8 @@ intel_display_power_domain_str(enum
> intel_display_power_domain domain)
> return "TRANSCODER_C";
> case POWER_DOMAIN_TRANSCODER_EDP:
> return "TRANSCODER_EDP";
> - case POWER_DOMAIN_TRANSCODER_EDP_VDSC:
> - return "TRANSCODER_EDP_VDSC";
> + case POWER_DOMAIN_TRANSCODER_VDSC_PW2:
> + return "TRANSCODER_VDSC_PW2";
> case POWER_DOMAIN_TRANSCODER_DSI_A:
> return "TRANSCODER_DSI_A";
> case POWER_DOMAIN_TRANSCODER_DSI_C:
> @@ -2448,7 +2448,7 @@ void intel_display_power_put(struct
> drm_i915_private *dev_priv,
>*/
> #define ICL_PW_2_POWER_DOMAINS ( \
> ICL_PW_3_POWER_DOMAINS |\
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
> BIT_ULL(POWER_DOMAIN_INIT))
> /*
>* - KVMR (HW control)
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
> b/drivers/gpu/drm/i915/display/intel_display_power.h
> index 8f43f7051a16..cc6956132ebc 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -25,7 +25,8 @@ enum intel_display_power_domain {
> POWER_DOMAIN_TRANSCODER_B,
> POWER_DOMAIN_TRANSCODER_C,
> POWER_DOMAIN_TRANSCODER_EDP,
> - POWER_DOMAIN_TRANSCODER_EDP_VDSC,
> + /* VDSC/joining for TRANSCODER_EDP (ICL) or TRANSCODER_A (TGL)
> */
> + POWER_DOMAIN_TRANSCODER_VDSC_PW2,
> POWER_DOMAIN_TRANSCODER_DSI_A,
> POWER_DOMAIN_TRANSCODER_DSI_C,
> POWER_DOMAIN_PORT_DDI_A_LANES,
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index ffec807b8960..4ab19c432ef5 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -459,17 +459,23 @@ int intel_dp_compute_dsc_params(struct intel_dp
> *intel_dp,
> enum intel_display_power_domain
> intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
> {
> + struct drm_i915_private *i915 = to_i915(crtc_state->base.crtc-
> >dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>
> /*
> - * On ICL VDSC/joining for eDP transcoder uses a separate power
> well PW2
> - * This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
> + * On ICL VDSC/joining for eDP transcoder uses a separate power
> well,
> + * PW2. This requires POWER_DOMAIN_TRANSCODER_VDSC_PW2 power
> domain.
>* For any other transcoder, VDSC/joining uses the power well
> associated
>* with the pipe/transcoder in use. Hence another reference on
> the
>* transcoder power domain will suffice.
> + *
> + * On TGL we have the same mapping, but for transcoder A (the
> special
> + * TRANSCODER_EDP is gone).
>*/
> - if (cpu_transcoder == TRANSCODER_EDP)
> - return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
> + if (INTEL_GEN(i915) >= 12 && cpu_transcoder == TRANSCODER_A)
> + return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
> + else if (cpu_transcoder == TRANSCODER_EDP)
> + return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
> else
> return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
> }
___
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/dp/dsc: Add Support for all BPCs supported by TGL
== Series Details == Series: drm/dp/dsc: Add Support for all BPCs supported by TGL URL : https://patchwork.freedesktop.org/series/63526/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/dp/dsc: Add Support for all BPCs supported by TGL -O:drivers/gpu/drm/i915/display/intel_dp.c:1914:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/display/intel_dp.c:1916:31: warning: expression using sizeof(void) +drivers/gpu/drm/i915/display/intel_dp.c:1919:31: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: We don't need display's suspend/resume operations when !HAS_DISPLAY
On Thu, 2019-05-23 at 16:17 -0700, Rodrigo Vivi wrote:
> Suspend resume is broken if we try to enable/disable dc9 on
> cases with disabled displays.
>
> v2: Make checkpatch happy:
> - braces {} are not necessary for single statement blocks
>
> v3: Also move hsw/bdw PC8 sequences since they are related to
> display PM anyways. (Ville)
Reviewed-by: José Roberto de Souza
>
> Cc: Ville Syrjälä
> Cc: José Roberto de Souza
> Signed-off-by: Rodrigo Vivi
> Reviewed-by: José Roberto de Souza (v1)
> ---
> drivers/gpu/drm/i915/i915_drv.c | 117 +-
> --
> 1 file changed, 76 insertions(+), 41 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c
> b/drivers/gpu/drm/i915/i915_drv.c
> index 83d2eb9e74cb..bd73ce57741a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -2118,6 +2118,17 @@ get_suspend_mode(struct drm_i915_private
> *dev_priv, bool hibernate)
> return I915_DRM_SUSPEND_MEM;
> }
>
> +static void intel_display_suspend_late(struct drm_i915_private
> *dev_priv)
> +{
> + if (!HAS_DISPLAY(dev_priv))
> + return;
> +
> + if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv))
> + bxt_enable_dc9(dev_priv);
> + else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> + hsw_enable_pc8(dev_priv);
> +}
> +
> static int i915_drm_suspend_late(struct drm_device *dev, bool
> hibernation)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
> @@ -2133,12 +2144,10 @@ static int i915_drm_suspend_late(struct
> drm_device *dev, bool hibernation)
> intel_power_domains_suspend(dev_priv,
> get_suspend_mode(dev_priv,
> hibernation));
>
> + intel_display_suspend_late(dev_priv);
> +
> ret = 0;
> - if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv))
> - bxt_enable_dc9(dev_priv);
> - else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> - hsw_enable_pc8(dev_priv);
> - else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> ret = vlv_suspend_complete(dev_priv);
>
> if (ret) {
> @@ -2266,6 +2275,19 @@ static int i915_drm_resume(struct drm_device
> *dev)
> return 0;
> }
>
> +static void intel_display_resume_early(struct drm_i915_private
> *dev_priv)
> +{
> + if (!HAS_DISPLAY(dev_priv))
> + return;
> +
> + if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
> + gen9_sanitize_dc_state(dev_priv);
> + bxt_disable_dc9(dev_priv);
> + } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> + hsw_disable_pc8(dev_priv);
> + }
> +}
> +
> static int i915_drm_resume_early(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
> @@ -2328,12 +2350,7 @@ static int i915_drm_resume_early(struct
> drm_device *dev)
>
> i915_check_and_clear_faults(dev_priv);
>
> - if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
> - gen9_sanitize_dc_state(dev_priv);
> - bxt_disable_dc9(dev_priv);
> - } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> - hsw_disable_pc8(dev_priv);
> - }
> + intel_display_resume_early(dev_priv);
>
> intel_uncore_sanitize(dev_priv);
>
> @@ -2869,6 +2886,22 @@ static int vlv_resume_prepare(struct
> drm_i915_private *dev_priv,
> return ret;
> }
>
> +static void intel_runtime_display_suspend(struct drm_i915_private
> *dev_priv)
> +{
> + if (!HAS_DISPLAY(dev_priv))
> + return;
> +
> + if (INTEL_GEN(dev_priv) >= 11) {
> + icl_display_core_uninit(dev_priv);
> + bxt_enable_dc9(dev_priv);
> + } else if (IS_GEN9_LP(dev_priv)) {
> + bxt_display_core_uninit(dev_priv);
> + bxt_enable_dc9(dev_priv);
> + } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> + hsw_enable_pc8(dev_priv);
> + }
> +}
> +
> static int intel_runtime_suspend(struct device *kdev)
> {
> struct pci_dev *pdev = to_pci_dev(kdev);
> @@ -2898,18 +2931,11 @@ static int intel_runtime_suspend(struct
> device *kdev)
>
> intel_uncore_suspend(_priv->uncore);
>
> + intel_runtime_display_suspend(dev_priv);
> +
> ret = 0;
> - if (INTEL_GEN(dev_priv) >= 11) {
> - icl_display_core_uninit(dev_priv);
> - bxt_enable_dc9(dev_priv);
> - } else if (IS_GEN9_LP(dev_priv)) {
> - bxt_display_core_uninit(dev_priv);
> - bxt_enable_dc9(dev_priv);
> - } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> - hsw_enable_pc8(dev_priv);
> - } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> {
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> ret = vlv_suspend_complete(dev_priv);
> - }
>
> if
[Intel-gfx] [PATCH] drm/dp/dsc: Add Support for all BPCs supported by TGL
DSC engine on ICL supports only 8 and 10 BPC as the input
BPC. But DSC engine in TGL supports 8, 10 and 12 BPC.
Add 12 BPC support for DSC while calculating compression
configuration.
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dp.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 0bdb7ecc5a81..cd089643c80d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -71,6 +71,7 @@
#define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
#define DP_DSC_MIN_SUPPORTED_BPC 8
#define DP_DSC_MAX_SUPPORTED_BPC 10
+#define TGL_DP_DSC_MAX_SUPPORTED_BPC 12
/* DP DSC throughput values used for slice count calculations KPixels/s */
#define DP_DSC_PEAK_PIXEL_RATE 272
@@ -1911,8 +1912,12 @@ static int intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
if (!intel_dp_supports_dsc(intel_dp, pipe_config))
return -EINVAL;
- dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
- conn_state->max_requested_bpc);
+ if (INTEL_GEN(dev_priv) > 11)
+ dsc_max_bpc = min_t(u8, TGL_DP_DSC_MAX_SUPPORTED_BPC,
+ conn_state->max_requested_bpc);
+ else
+ dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
+ conn_state->max_requested_bpc);
pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) {
--
2.21.0
___
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[Intel-gfx] [PATCH] drm/i915/guc: Define GuC firmware version for Comet Lake
Load GuC for Comet Lake. Depending on the REVID,
we load either the KBL firmware or the CML firmware.
v2: Use CFL for CML platform check.(Michal)
v3: Use >=5 for future proofing(Michal, Daniele)
Cc: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_guc_fw.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c
b/drivers/gpu/drm/i915/intel_guc_fw.c
index db1e0daca7db..c8c94df1e5d0 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -58,6 +58,13 @@ MODULE_FIRMWARE(BXT_GUC_FIRMWARE_PATH);
#define KBL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(KBL)
MODULE_FIRMWARE(KBL_GUC_FIRMWARE_PATH);
+#define CML_GUC_FW_PREFIX cml
+#define CML_GUC_FW_MAJOR 33
+#define CML_GUC_FW_MINOR 0
+#define CML_GUC_FW_PATCH 0
+#define CML_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(CML)
+MODULE_FIRMWARE(CML_GUC_FIRMWARE_PATH);
+
#define GLK_GUC_FW_PREFIX glk
#define GLK_GUC_FW_MAJOR 33
#define GLK_GUC_FW_MINOR 0
@@ -94,7 +101,17 @@ static void guc_fw_select(struct intel_uc_fw *guc_fw)
guc_fw->path = GLK_GUC_FIRMWARE_PATH;
guc_fw->major_ver_wanted = GLK_GUC_FW_MAJOR;
guc_fw->minor_ver_wanted = GLK_GUC_FW_MINOR;
- } else if (IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) {
+ } else if (IS_COFFEELAKE(i915)) {
+ if (INTEL_REVID(i915) >= 5) {
+ guc_fw->path = CML_GUC_FIRMWARE_PATH;
+ guc_fw->major_ver_wanted = CML_GUC_FW_MAJOR;
+ guc_fw->minor_ver_wanted = CML_GUC_FW_MINOR;
+ } else {
+ guc_fw->path = KBL_GUC_FIRMWARE_PATH;
+ guc_fw->major_ver_wanted = KBL_GUC_FW_MAJOR;
+ guc_fw->minor_ver_wanted = KBL_GUC_FW_MINOR;
+ }
+ } else if (IS_KABYLAKE(i915)) {
guc_fw->path = KBL_GUC_FIRMWARE_PATH;
guc_fw->major_ver_wanted = KBL_GUC_FW_MAJOR;
guc_fw->minor_ver_wanted = KBL_GUC_FW_MINOR;
--
2.21.0
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Re: [Intel-gfx] [PATCH v2 17/25] drm/i915/tgl: select correct bit for port select
On Wed, Jul 10, 2019 at 09:40:05PM +0300, Ville Syrjälä wrote:
On Mon, Jul 08, 2019 at 04:16:21PM -0700, Lucas De Marchi wrote:
From: Mahesh Kumar
Bit definitions for port-select got changed for TRANS_CLK_SEL &
TRANS_DDI_FUNC_CTL registers in TGL.
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_ddi.c | 48 +++-
drivers/gpu/drm/i915/i915_reg.h | 5 +++
2 files changed, 43 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index e72cf0bb48a7..5125c31af6aa 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1771,7 +1771,10 @@ void intel_ddi_enable_transcoder_func(const struct
intel_crtc_state *crtc_state)
/* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
temp = TRANS_DDI_FUNC_ENABLE;
- temp |= TRANS_DDI_SELECT_PORT(port);
+ if (INTEL_GEN(dev_priv) >= 12)
+ temp |= TGL_TRANS_DDI_SELECT_PORT(port);
+ else
+ temp |= TRANS_DDI_SELECT_PORT(port);
switch (crtc_state->pipe_bpp) {
case 18:
@@ -1851,8 +1854,14 @@ void intel_ddi_disable_transcoder_func(const struct
intel_crtc_state *crtc_state
i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
u32 val = I915_READ(reg);
- val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK |
TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
- val |= TRANS_DDI_PORT_NONE;
+ if (INTEL_GEN(dev_priv) >= 12) {
+ val &= ~(TRANS_DDI_FUNC_ENABLE | TGL_TRANS_DDI_PORT_MASK |
+TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
+ } else {
+ val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK |
+TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
+ val |= TRANS_DDI_PORT_NONE;
A bit incosistent leaving the NONE thing here. Maybe just nuke that
entirely?
I can, but the diff is actually
-TRANS_DDI_PORT_MASK
+TGL_TRANS_DDI_PORT_MASK
Lucas De Marchi
Patch is
Reviewed-by: Ville Syrjälä
+ }
I915_WRITE(reg, val);
if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
@@ -2004,10 +2013,19 @@ static void intel_ddi_get_encoder_pipes(struct
intel_encoder *encoder,
mst_pipe_mask = 0;
for_each_pipe(dev_priv, p) {
enum transcoder cpu_transcoder = (enum transcoder)p;
+ unsigned int port_mask, ddi_select;
+
+ if (INTEL_GEN(dev_priv) >= 12) {
+ port_mask = TGL_TRANS_DDI_PORT_MASK;
+ ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
+ } else {
+ port_mask = TRANS_DDI_PORT_MASK;
+ ddi_select = TRANS_DDI_SELECT_PORT(port);
+ }
tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
- if ((tmp & TRANS_DDI_PORT_MASK) != TRANS_DDI_SELECT_PORT(port))
+ if ((tmp & port_mask) != ddi_select)
continue;
if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
@@ -2123,9 +2141,14 @@ void intel_ddi_enable_pipe_clock(const struct
intel_crtc_state *crtc_state)
enum port port = encoder->port;
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
- if (cpu_transcoder != TRANSCODER_EDP)
- I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
- TRANS_CLK_SEL_PORT(port));
+ if (cpu_transcoder != TRANSCODER_EDP) {
+ if (INTEL_GEN(dev_priv) >= 12)
+ I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
+ TGL_TRANS_CLK_SEL_PORT(port));
+ else
+ I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
+ TRANS_CLK_SEL_PORT(port));
+ }
}
void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
@@ -2133,9 +2156,14 @@ void intel_ddi_disable_pipe_clock(const struct
intel_crtc_state *crtc_state)
struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
- if (cpu_transcoder != TRANSCODER_EDP)
- I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
- TRANS_CLK_SEL_DISABLED);
+ if (cpu_transcoder != TRANSCODER_EDP) {
+ if (INTEL_GEN(dev_priv) >= 12)
+ I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
+ TGL_TRANS_CLK_SEL_DISABLED);
+ else
+ I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
+ TRANS_CLK_SEL_DISABLED);
+ }
}
static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c554df69f289..ccfb95e2aa03 100644
---
Re: [Intel-gfx] [RFC][PATCH 0/2] drm: PATH prop for all connectors?
(adding sunpeng...@amd.com to the thread here, since this is relevant to the DP aux device work) I mentioned this in IRC, but figured I should mention it on the ML as well so it can be discussed further. Honestly: I don't like the way we implement the path prop for MST. Mainly because * It looks ugly: mst:-- is ambiguous looking. I didn't even realize the first number was actually supposed to be the object ID until I looked at the code * I strongly doubt object IDs are consistent enough for the path prop to actually be as meaningful as it looks * Obviously we can't just remove the path property, since it's being used in userspace. This has me somewhat convinced that I think it might be a better idea to just make a whole new path_v2 prop, and document that the path prop was a bad idea and is now deprecated (but still functional). If we did this, we could come up with a much nicer MST naming scheme as well! Consider: For a connector with the RAD 0.1 living on the topology on DP-1 on card0: mst:DP-1:0.1 I see multiple benefits to this: * Look how easy it is to read! * DP-1 isn't guaranteed to be consistent, but it is certainly far more likely to be consistent than an object ID. * This seems a lot easier to write udev rules for, imho The only thing I'm not sure about whether or not we should also prepend the connector name with the device (e.g. card0, card1, etc.). I thought this might be necessary at first, but thinking about it - it shouldn't be hard to figure out the device in question from looking at sysfs since any userspace application will know which DRM fd the connector comes from. Does this sound like a good idea? If so, I'd be happy to write up some patches for this On Thu, 2019-06-13 at 21:43 +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > Here's a possible apporoach for providing userspace with > some stable connector identifiers. Combine with the bus > name of the GPU and you should have some kind of real > physical path description. Unfortunately the ship has > sailed for MST connectors because userspace is already > parsing the property and expects to find certain things > there. So if we want stable names for those we'd probably > have introduce another PATH prop (PHYS_PATH?). > > I suppose one alternative would to make the connector > type_id stable. Currently that is being populated by drm > core and it's just a global counter. Not sure how badly > things would turn out if we'd allow each driver to set > that. It could result in conflicting xrandr connector > names between different GPUs which I suppose would > confuse existing userspace? > > Cc: Daniel Vetter > Cc: Pekka Paalanen > Cc: Ilia Mirkin > > Ville Syrjälä (2): > drm: Improve PATH prop docs > drm/i915: Populate PATH prop for every connector > > drivers/gpu/drm/drm_connector.c| 13 -- > drivers/gpu/drm/i915/icl_dsi.c | 3 +++ > drivers/gpu/drm/i915/intel_connector.c | 20 +++ > drivers/gpu/drm/i915/intel_connector.h | 3 +++ > drivers/gpu/drm/i915/intel_crt.c | 2 ++ > drivers/gpu/drm/i915/intel_dp.c| 6 - > drivers/gpu/drm/i915/intel_dp_mst.c| 3 +-- > drivers/gpu/drm/i915/intel_dvo.c | 3 +++ > drivers/gpu/drm/i915/intel_hdmi.c | 4 +++ > drivers/gpu/drm/i915/intel_lvds.c | 2 ++ > drivers/gpu/drm/i915/intel_sdvo.c | 35 ++ > drivers/gpu/drm/i915/intel_tv.c| 2 ++ > drivers/gpu/drm/i915/vlv_dsi.c | 3 +++ > 13 files changed, 83 insertions(+), 16 deletions(-) > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC 7/7] drm/i915: Allow vdsc functions to be called without encoder.
On Tue, Jul 02, 2019 at 09:42:05PM +0200, Maarten Lankhorst wrote:
> This can be useful when calling the vdsc enable functions
> directly without encoder.
Would this be the case on the slave pipe where we need to enable DSC but there
is no transcoder enabled for that pipe?
Manasi
>
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/display/intel_vdsc.c | 8 +---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 419a77723894..f009524ab735 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -897,7 +897,7 @@ void intel_dsc_enable(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
> i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
> u32 dss_ctl1_val = 0;
> @@ -910,9 +910,11 @@ void intel_dsc_enable(struct intel_encoder *encoder,
> intel_display_power_get(dev_priv,
> intel_dsc_power_domain(crtc_state));
>
> - intel_configure_pps_for_dsc_encoder(encoder, crtc_state);
> + if (encoder) {
> + intel_configure_pps_for_dsc_encoder(encoder, crtc_state);
>
> - intel_dp_write_dsc_pps_sdp(encoder, crtc_state);
> + intel_dp_write_dsc_pps_sdp(encoder, crtc_state);
> + }
>
> if (crtc_state->cpu_transcoder == TRANSCODER_EDP) {
> dss_ctl1_reg = DSS_CTL1;
> --
> 2.20.1
>
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] screen freeze with 5.2-rc6 Dell XPS-13 skylake i915
On Wed, 2019-07-10 at 23:59 +0200, Paul Bolle wrote: > James Bottomley schreef op wo 10-07-2019 om 10:35 [-0700]: > > I can get back to it this afternoon, when I'm done with the meeting > > requirements and doing other dev stuff. > > I've started bisecting using your suggestion of that drm merge: > $ git bisect log > git bisect start > # good: [89c3b37af87ec183b666d83428cb28cc421671a6] Merge > git://git.kernel.org/pub/scm/linux/kernel/git/davem/ide > git bisect good 89c3b37af87ec183b666d83428cb28cc421671a6 > # bad: [a2d635decbfa9c1e4ae15cb05b68b2559f7f827c] Merge tag 'drm- > next-2019-05-09' of git://anongit.freedesktop.org/drm/drm > git bisect bad a2d635decbfa9c1e4ae15cb05b68b2559f7f827c > # bad: [ad2c467aa92e283e9e8009bb9eb29a5c6a2d1217] drm/i915: > Update DRIVER_DATE to 20190417 > git bisect bad ad2c467aa92e283e9e8009bb9eb29a5c6a2d1217 > > Git told me I have nine steps after this. So at two hours per step I > might > pinpoint the offending commit by Friday the 12th. If I'm lucky. > (There are > other things to do than bisecting this issue.) > > If you find that commit before I do, I'll be all ears. Sure ... I'm doing the holistic thing and looking at the tree in that branch. It seems to consist of 7 i915 updates c09d39166d8a3f3788680b32dbb0a40a70de32e2 DRIVER_DATE to 20190207 47ed55a9bb9e284d46d6f2489e32a53b59152809 DRIVER_DATE to 20190220 f4ecb8ae70de86710e85138ce49af5c689951953 DRIVER_DATE to 20190311 1284ec985572232ace4817476baeb2d82b60be7a DRIVER_DATE to 20190320 a01b2c6f47d86c7d1a9fa822b3b91ec233b61784 DRIVER_DATE to 20190328 28d618e9ab86f26a31af0b235ced55beb3e343c8 DRIVER_DATE to 20190404 ad2c467aa92e283e9e8009bb9eb29a5c6a2d1217 DRIVER_DATE to 20190417 So I figured I'd see if I can locate the problem by bisection of those plus inspection. James ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 1/2] drm/i915: Add support for retrying hotplug
On Wed, 2019-07-10 at 04:20 -0700, Rodrigo Vivi wrote:
> On Fri, Jun 28, 2019 at 02:39:20PM -0700, José Roberto de Souza
> wrote:
> > From: Imre Deak
> >
> > There is some scenarios that we are aware that sink probe can fail,
> > so lets add the infrastructure to let hotplug() hook to request
> > another probe after some time.
> >
> > v2: Handle shared HPD pins (Imre)
> > v3: Rebased
> >
> > Cc: Ville Syrjälä
> > Signed-off-by: José Roberto de Souza
> > Signed-off-by: Jani Nikula
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 12 ++--
> > drivers/gpu/drm/i915/display/intel_dp.c | 12 ++--
> > drivers/gpu/drm/i915/display/intel_hotplug.c | 59 +++-
> >
> > drivers/gpu/drm/i915/display/intel_hotplug.h | 5 +-
> > drivers/gpu/drm/i915/display/intel_sdvo.c| 8 ++-
> > drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
> > drivers/gpu/drm/i915/i915_drv.h | 3 +-
> > drivers/gpu/drm/i915/intel_drv.h | 11 +++-
> > 8 files changed, 80 insertions(+), 32 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 7925a176f900..53009984e046 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -4081,14 +4081,16 @@ static int intel_hdmi_reset_link(struct
> > intel_encoder *encoder,
> > return modeset_pipe(>base, ctx);
> > }
> >
> > -static bool intel_ddi_hotplug(struct intel_encoder *encoder,
> > - struct intel_connector *connector)
> > +static enum intel_hotplug_state
> > +intel_ddi_hotplug(struct intel_encoder *encoder,
> > + struct intel_connector *connector,
> > + bool irq_received)
> > {
> > struct drm_modeset_acquire_ctx ctx;
> > - bool changed;
> > + enum intel_hotplug_state state;
> > int ret;
> >
> > - changed = intel_encoder_hotplug(encoder, connector);
> > + state = intel_encoder_hotplug(encoder, connector,
> > irq_received);
> >
> > drm_modeset_acquire_init(, 0);
> >
> > @@ -4110,7 +4112,7 @@ static bool intel_ddi_hotplug(struct
> > intel_encoder *encoder,
> > drm_modeset_acquire_fini();
> > WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
> >
> > - return changed;
> > + return state;
> > }
> >
> > static struct intel_connector *
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 4336df46fe78..95d0da9d1bac 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -4878,14 +4878,16 @@ int intel_dp_retrain_link(struct
> > intel_encoder *encoder,
> > * retrain the link to get a picture. That's in case no
> > * userspace component reacted to intermittent HPD dip.
> > */
> > -static bool intel_dp_hotplug(struct intel_encoder *encoder,
> > -struct intel_connector *connector)
> > +static enum intel_hotplug_state
> > +intel_dp_hotplug(struct intel_encoder *encoder,
> > +struct intel_connector *connector,
> > +bool irq_received)
> > {
> > struct drm_modeset_acquire_ctx ctx;
> > - bool changed;
> > + enum intel_hotplug_state state;
> > int ret;
> >
> > - changed = intel_encoder_hotplug(encoder, connector);
> > + state = intel_encoder_hotplug(encoder, connector,
> > irq_received);
> >
> > drm_modeset_acquire_init(, 0);
> >
> > @@ -4904,7 +4906,7 @@ static bool intel_dp_hotplug(struct
> > intel_encoder *encoder,
> > drm_modeset_acquire_fini();
> > WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
> >
> > - return changed;
> > + return state;
> > }
> >
> > static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
> > diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c
> > b/drivers/gpu/drm/i915/display/intel_hotplug.c
> > index ea3de4acc850..3662966d366e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hotplug.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
> > @@ -112,6 +112,7 @@ enum hpd_pin intel_hpd_pin_default(struct
> > drm_i915_private *dev_priv,
> >
> > #define HPD_STORM_DETECT_PERIOD1000
> > #define HPD_STORM_REENABLE_DELAY (2 * 60 * 1000)
> > +#define HPD_RETRY_DELAY1000
> >
> > /**
> > * intel_hpd_irq_storm_detect - gather stats and detect HPD IRQ
> > storm on a pin
> > @@ -266,8 +267,10 @@ static void
> > intel_hpd_irq_storm_reenable_work(struct work_struct *work)
> > intel_runtime_pm_put(_priv->runtime_pm, wakeref);
> > }
> >
> > -bool intel_encoder_hotplug(struct intel_encoder *encoder,
> > - struct intel_connector *connector)
> > +enum intel_hotplug_state
> > +intel_encoder_hotplug(struct intel_encoder *encoder,
> > + struct intel_connector *connector,
> > + bool irq_received)
> > {
> > struct
[Intel-gfx] [PATCH v4 1/2] drm/i915: Add support for retrying hotplug
From: Imre Deak
There is some scenarios that we are aware that sink probe can fail,
so lets add the infrastructure to let hotplug() hook to request
another probe after some time.
v2: Handle shared HPD pins (Imre)
v3: Rebased
v4: Renamed INTEL_HOTPLUG_NOCHANGE to INTEL_HOTPLUG_UNCHANGED to keep
it consistent(Rodrigo)
Cc: Ville Syrjälä
Reviewed-by: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
Signed-off-by: Jani Nikula
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_ddi.c | 12 ++--
drivers/gpu/drm/i915/display/intel_dp.c | 12 ++--
drivers/gpu/drm/i915/display/intel_hotplug.c | 59 +++-
drivers/gpu/drm/i915/display/intel_hotplug.h | 5 +-
drivers/gpu/drm/i915/display/intel_sdvo.c| 8 ++-
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 3 +-
drivers/gpu/drm/i915/intel_drv.h | 11 +++-
8 files changed, 80 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index ad638e7f27bb..734c004800f8 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4047,14 +4047,16 @@ static int intel_hdmi_reset_link(struct intel_encoder
*encoder,
return modeset_pipe(>base, ctx);
}
-static bool intel_ddi_hotplug(struct intel_encoder *encoder,
- struct intel_connector *connector)
+static enum intel_hotplug_state
+intel_ddi_hotplug(struct intel_encoder *encoder,
+ struct intel_connector *connector,
+ bool irq_received)
{
struct drm_modeset_acquire_ctx ctx;
- bool changed;
+ enum intel_hotplug_state state;
int ret;
- changed = intel_encoder_hotplug(encoder, connector);
+ state = intel_encoder_hotplug(encoder, connector, irq_received);
drm_modeset_acquire_init(, 0);
@@ -4076,7 +4078,7 @@ static bool intel_ddi_hotplug(struct intel_encoder
*encoder,
drm_modeset_acquire_fini();
WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
- return changed;
+ return state;
}
static struct intel_connector *
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 0bdb7ecc5a81..4423abbc7907 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4853,14 +4853,16 @@ int intel_dp_retrain_link(struct intel_encoder *encoder,
* retrain the link to get a picture. That's in case no
* userspace component reacted to intermittent HPD dip.
*/
-static bool intel_dp_hotplug(struct intel_encoder *encoder,
-struct intel_connector *connector)
+static enum intel_hotplug_state
+intel_dp_hotplug(struct intel_encoder *encoder,
+struct intel_connector *connector,
+bool irq_received)
{
struct drm_modeset_acquire_ctx ctx;
- bool changed;
+ enum intel_hotplug_state state;
int ret;
- changed = intel_encoder_hotplug(encoder, connector);
+ state = intel_encoder_hotplug(encoder, connector, irq_received);
drm_modeset_acquire_init(, 0);
@@ -4879,7 +4881,7 @@ static bool intel_dp_hotplug(struct intel_encoder
*encoder,
drm_modeset_acquire_fini();
WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
- return changed;
+ return state;
}
static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c
b/drivers/gpu/drm/i915/display/intel_hotplug.c
index ea3de4acc850..2ca92780c659 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
@@ -112,6 +112,7 @@ enum hpd_pin intel_hpd_pin_default(struct drm_i915_private
*dev_priv,
#define HPD_STORM_DETECT_PERIOD1000
#define HPD_STORM_REENABLE_DELAY (2 * 60 * 1000)
+#define HPD_RETRY_DELAY1000
/**
* intel_hpd_irq_storm_detect - gather stats and detect HPD IRQ storm on a pin
@@ -266,8 +267,10 @@ static void intel_hpd_irq_storm_reenable_work(struct
work_struct *work)
intel_runtime_pm_put(_priv->runtime_pm, wakeref);
}
-bool intel_encoder_hotplug(struct intel_encoder *encoder,
- struct intel_connector *connector)
+enum intel_hotplug_state
+intel_encoder_hotplug(struct intel_encoder *encoder,
+ struct intel_connector *connector,
+ bool irq_received)
{
struct drm_device *dev = connector->base.dev;
enum drm_connector_status old_status;
@@ -279,7 +282,7 @@ bool intel_encoder_hotplug(struct intel_encoder *encoder,
drm_helper_probe_detect(>base, NULL, false);
if (old_status == connector->base.status)
- return false;
+ return INTEL_HOTPLUG_UNCHANGED;
[Intel-gfx] [PATCH v4 2/2] drm/i915: Enable hotplug retry
Right now we are aware of two cases that needs another hotplug retry:
- Unpowered type-c dongles
- HDMI slow unplug
Both have a complete explanation in the code to schedule another run
of the hotplug handler.
It could have more checks to just trigger the retry in those two
specific cases but why would sink signal a long pulse if there is
no change? Also the drawback of running the hotplug handler again
is really low and that could fix another cases that we are not
aware.
Also retrying for old DP ports(non-DDI) to make it consistent and not
cause CI failures if those systems are connected to chamelium boards
that will be used to simulate the issues reported in here.
v2: Also retrying for old DP ports(non-DDI)(Imre)
v4: Renamed INTEL_HOTPLUG_NOCHANGE to INTEL_HOTPLUG_UNCHANGED to keep
it consistent(Rodrigo)
Cc: Ville Syrjälä
Cc: Imre Deak
Cc: Jani Nikula
Reviewed-by: Imre Deak
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_ddi.c | 21 +
drivers/gpu/drm/i915/display/intel_dp.c | 7 ++
drivers/gpu/drm/i915/display/intel_hdmi.c | 28 ++-
3 files changed, 55 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 734c004800f8..ea6d1873f6cb 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4052,6 +4052,7 @@ intel_ddi_hotplug(struct intel_encoder *encoder,
struct intel_connector *connector,
bool irq_received)
{
+ struct intel_digital_port *dig_port = enc_to_dig_port(>base);
struct drm_modeset_acquire_ctx ctx;
enum intel_hotplug_state state;
int ret;
@@ -4078,6 +4079,26 @@ intel_ddi_hotplug(struct intel_encoder *encoder,
drm_modeset_acquire_fini();
WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
+ /*
+* Unpowered type-c dongles can take some time to boot and be
+* responsible, so here giving some time to those dongles to power up
+* and then retrying the probe.
+*
+* On many platforms the HDMI live state signal is known to be
+* unreliable, so we can't use it to detect if a sink is connected or
+* not. Instead we detect if it's connected based on whether we can
+* read the EDID or not. That in turn has a problem during disconnect,
+* since the HPD interrupt may be raised before the DDC lines get
+* disconnected (due to how the required length of DDC vs. HPD
+* connector pins are specified) and so we'll still be able to get a
+* valid EDID. To solve this schedule another detection cycle if this
+* time around we didn't detect any change in the sink's connection
+* status.
+*/
+ if (state == INTEL_HOTPLUG_UNCHANGED && irq_received &&
+ !dig_port->dp.is_mst)
+ state = INTEL_HOTPLUG_RETRY;
+
return state;
}
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 4423abbc7907..7106a2d80f79 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4881,6 +4881,13 @@ intel_dp_hotplug(struct intel_encoder *encoder,
drm_modeset_acquire_fini();
WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
+ /*
+* Keeping it consistent with intel_ddi_hotplug() and
+* intel_hdmi_hotplug().
+*/
+ if (state == INTEL_HOTPLUG_UNCHANGED && irq_received)
+ state = INTEL_HOTPLUG_RETRY;
+
return state;
}
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 0ebec69bbbfc..26c8556f6980 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -3143,6 +3143,32 @@ void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port,
DRM_DEBUG_KMS("CEC notifier get failed\n");
}
+static enum intel_hotplug_state
+intel_hdmi_hotplug(struct intel_encoder *encoder,
+ struct intel_connector *connector, bool irq_received)
+{
+ enum intel_hotplug_state state;
+
+ state = intel_encoder_hotplug(encoder, connector, irq_received);
+
+ /*
+* On many platforms the HDMI live state signal is known to be
+* unreliable, so we can't use it to detect if a sink is connected or
+* not. Instead we detect if it's connected based on whether we can
+* read the EDID or not. That in turn has a problem during disconnect,
+* since the HPD interrupt may be raised before the DDC lines get
+* disconnected (due to how the required length of DDC vs. HPD
+* connector pins are specified) and so we'll still be able to get a
+* valid EDID. To solve this schedule another detection cycle if this
+* time around we
Re: screen freeze with 5.2-rc6 Dell XPS-13 skylake i915
James Bottomley schreef op wo 10-07-2019 om 10:35 [-0700]: > I can get back to it this afternoon, when I'm done with the meeting > requirements and doing other dev stuff. I've started bisecting using your suggestion of that drm merge: $ git bisect log git bisect start # good: [89c3b37af87ec183b666d83428cb28cc421671a6] Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/ide git bisect good 89c3b37af87ec183b666d83428cb28cc421671a6 # bad: [a2d635decbfa9c1e4ae15cb05b68b2559f7f827c] Merge tag 'drm-next-2019-05-09' of git://anongit.freedesktop.org/drm/drm git bisect bad a2d635decbfa9c1e4ae15cb05b68b2559f7f827c # bad: [ad2c467aa92e283e9e8009bb9eb29a5c6a2d1217] drm/i915: Update DRIVER_DATE to 20190417 git bisect bad ad2c467aa92e283e9e8009bb9eb29a5c6a2d1217 Git told me I have nine steps after this. So at two hours per step I might pinpoint the offending commit by Friday the 12th. If I'm lucky. (There are other things to do than bisecting this issue.) If you find that commit before I do, I'll be all ears. Thanks, Paul Bolle
Re: [Intel-gfx] [PATCH 04/12] drm/i915/uc: introduce intel_uc_fw_supported
On 7/10/19 9:57 AM, Michal Wajdeczko wrote:
On Wed, 10 Jul 2019 02:54:29 +0200, Daniele Ceraolo Spurio
wrote:
Instead of always checking in the device config is GuC and HuC are
s/is/if
supported or not, we can save the state in the uc_fw structure and
avoid going through i915 every time from the low-level uc management
code. while at it FIRMWARE_NONE has been renamed to better indicate that
s/while/While
we haven't started the fetch/load yet, but we might have already selected
a blob.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
---
drivers/gpu/drm/i915/intel_guc_fw.c | 6 +-
drivers/gpu/drm/i915/intel_huc_fw.c | 6 +-
drivers/gpu/drm/i915/intel_uc.c | 25
drivers/gpu/drm/i915/intel_uc_fw.c | 4 +++-
drivers/gpu/drm/i915/intel_uc_fw.h | 30 -
5 files changed, 51 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c
b/drivers/gpu/drm/i915/intel_guc_fw.c
index db1e0daca7db..ee95d4960c5c 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -79,8 +79,12 @@ static void guc_fw_select(struct intel_uc_fw *guc_fw)
GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);
- if (!HAS_GUC(i915))
+ if (!HAS_GUC(i915)) {
+ guc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_SUPPORTED;
return;
+ }
+
+ guc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_STARTED;
if (i915_modparams.guc_firmware_path) {
guc_fw->path = i915_modparams.guc_firmware_path;
diff --git a/drivers/gpu/drm/i915/intel_huc_fw.c
b/drivers/gpu/drm/i915/intel_huc_fw.c
index 05cbf8338f53..06e726ba9863 100644
--- a/drivers/gpu/drm/i915/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/intel_huc_fw.c
@@ -73,8 +73,12 @@ static void huc_fw_select(struct intel_uc_fw *huc_fw)
GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
- if (!HAS_HUC(dev_priv))
+ if (!HAS_HUC(dev_priv)) {
+ huc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_SUPPORTED;
return;
+ }
+
+ huc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_STARTED;
if (i915_modparams.huc_firmware_path) {
huc_fw->path = i915_modparams.huc_firmware_path;
diff --git a/drivers/gpu/drm/i915/intel_uc.c
b/drivers/gpu/drm/i915/intel_uc.c
index 789b0bccfb41..ef2a864b8990 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -71,7 +71,8 @@ static int __get_default_guc_log_level(struct
drm_i915_private *i915)
{
int guc_log_level;
- if (!HAS_GUC(i915) || !intel_uc_is_using_guc(i915))
+ if (!intel_uc_fw_supported(>guc.fw) ||
this goes too far, we should limit number of direct accesses to .fw
maybe we can have:
inline bool intel_uc_has_guc(i915)
{
return intel_guc_is_present(>guc);
}
inline bool intel_guc_is_present(guc)
{
return intel_uc_fw_is_defined(>fw);
}
Maybe instead of saving this info in the uc_fw it'd be better to just
change guc_init_early to not do anything if !HAS_GUC and then do
something like:
bool intel_guc_is_present(guc)
{
return !!guc->send;
}
What do you think? otherwise I'll split it like you suggested
+ !intel_uc_is_using_guc(i915))
guc_log_level = GUC_LOG_LEVEL_DISABLED;
else if (IS_ENABLED(CONFIG_DRM_I915_DEBUG) ||
IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
@@ -119,16 +120,16 @@ static void sanitize_options_early(struct
drm_i915_private *i915)
if (intel_uc_is_using_guc(i915) &&
!intel_uc_fw_is_selected(guc_fw)) {
DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
"enable_guc", i915_modparams.enable_guc,
- !HAS_GUC(i915) ? "no GuC hardware" :
- "no GuC firmware");
+ !intel_uc_fw_supported(guc_fw) ?
+ "no GuC hardware" : "no GuC firmware");
}
/* Verify HuC firmware availability */
if (intel_uc_is_using_huc(i915) &&
!intel_uc_fw_is_selected(huc_fw)) {
DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
"enable_guc", i915_modparams.enable_guc,
- !HAS_HUC(i915) ? "no HuC hardware" :
- "no HuC firmware");
+ !intel_uc_fw_supported(huc_fw) ?
+ "no HuC hardware" : "no HuC firmware");
}
/* XXX: GuC submission is unavailable for now */
@@ -148,8 +149,8 @@ static void sanitize_options_early(struct
drm_i915_private *i915)
if (i915_modparams.guc_log_level > 0 &&
!intel_uc_is_using_guc(i915)) {
DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
"guc_log_level", i915_modparams.guc_log_level,
- !HAS_GUC(i915) ? "no GuC hardware" :
- "GuC not enabled");
+ !intel_uc_fw_supported(guc_fw) ?
+ "no GuC hardware" : "GuC not enabled");
i915_modparams.guc_log_level = 0;
}
@@ -376,7 +377,7 @@ int intel_uc_init(struct
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/2] drm/i915/display/icl: Bump up the vdisplay to reflect higher transcoder vertical limits
== Series Details == Series: series starting with [v3,1/2] drm/i915/display/icl: Bump up the vdisplay to reflect higher transcoder vertical limits URL : https://patchwork.freedesktop.org/series/63522/ State : warning == Summary == $ dim checkpatch origin/drm-tip 60f52512f495 drm/i915/display/icl: Bump up the vdisplay to reflect higher transcoder vertical limits -:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #10: On ICL+, the vertical limits for the transcoders are increased to 8192 so bump up total: 0 errors, 1 warnings, 0 checks, 15 lines checked 93a807e3e5c2 drm/i915/display/icl: Bump up the plane/fb height ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 2/2] drm/i915/display/icl: Bump up the plane/fb height
On ICL+, the max supported plane height is 4320, so bump it up
To support 4320, we need to increase the number of bits used to
read plane_height to 13 as opposed to older 12 bits.
v2:
* ICL plane height supported is 4320 (Ville)
* Add a new line between max width and max height (Jose)
Cc: Maarten Lankhorst
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_display.c | 22 ++--
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 9883f607bb88..e4915d68147a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3343,6 +3343,16 @@ static int icl_max_plane_width(const struct
drm_framebuffer *fb,
return 5120;
}
+static int skl_max_plane_height(void)
+{
+ return 4096;
+}
+
+static int icl_max_plane_height(void)
+{
+ return 4320;
+}
+
static bool skl_check_main_ccs_coordinates(struct intel_plane_state
*plane_state,
int main_x, int main_y, u32
main_offset)
{
@@ -3391,7 +3401,7 @@ static int skl_check_main_surface(struct
intel_plane_state *plane_state)
int w = drm_rect_width(_state->base.src) >> 16;
int h = drm_rect_height(_state->base.src) >> 16;
int max_width;
- int max_height = 4096;
+ int max_height;
u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset;
if (INTEL_GEN(dev_priv) >= 11)
@@ -3401,6 +3411,11 @@ static int skl_check_main_surface(struct
intel_plane_state *plane_state)
else
max_width = skl_max_plane_width(fb, 0, rotation);
+ if (INTEL_GEN(dev_priv) >= 11)
+ max_height = icl_max_plane_height();
+ else
+ max_height = skl_max_plane_height();
+
if (w > max_width || h > max_height) {
DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit
%dx%d)\n",
w, h, max_width, max_height);
@@ -9865,7 +9880,10 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
offset = I915_READ(PLANE_OFFSET(pipe, plane_id));
val = I915_READ(PLANE_SIZE(pipe, plane_id));
- fb->height = ((val >> 16) & 0xfff) + 1;
+ if (INTEL_GEN(dev_priv) >= 12)
+ fb->height = ((val >> 16) & 0x1fff) + 1;
+ else
+ fb->height = ((val >> 16) & 0xfff) + 1;
fb->width = ((val >> 0) & 0x1fff) + 1;
val = I915_READ(PLANE_STRIDE(pipe, plane_id));
--
2.19.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 1/2] drm/i915/display/icl: Bump up the vdisplay to reflect higher transcoder vertical limits
On ICL+, the vertical limits for the transcoders are increased to 8192 so bump
up
limits in intel_mode_valid()
v3:
* Supported starting ICL (Ville)
* Use the higher limits from TRANS_VTOTAL register (Ville)
v2:
* Checkpatch warning (Manasi)
Cc: Maarten Lankhorst
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_display.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index f07081815b80..9883f607bb88 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15764,8 +15764,13 @@ intel_mode_valid(struct drm_device *dev,
DRM_MODE_FLAG_CLKDIV2))
return MODE_BAD;
- if (INTEL_GEN(dev_priv) >= 9 ||
- IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
+ if (INTEL_GEN(dev_priv) >= 11) {
+ hdisplay_max = 8192;
+ vdisplay_max = 8192;
+ htotal_max = 8192;
+ vtotal_max = 8192;
+ } else if (INTEL_GEN(dev_priv) >= 9 ||
+ IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
vdisplay_max = 4096;
htotal_max = 8192;
--
2.19.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Initial support for Tiger Lake (rev6)
== Series Details == Series: Initial support for Tiger Lake (rev6) URL : https://patchwork.freedesktop.org/series/62726/ State : warning == Summary == $ dim checkpatch origin/drm-tip 84393d3db7c9 drm/i915: Add 4th pipe and transcoder a755f8c87f85 drm/i915/tgl: add initial Tiger Lake definitions ffc0dcf5fb65 drm/i915/tgl: Introduce Tiger Lake PCH c9e8ac767299 drm/i915/tgl: Add TGL PCH detection in virtualized environment 9dee5c2b7821 drm/i915/tgl: Add TGL PCI IDs -:34: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #34: FILE: include/drm/i915_pciids.h:587: +#define INTEL_TGL_12_IDS(info) \ + INTEL_VGA_DEVICE(0x9A49, info), \ + INTEL_VGA_DEVICE(0x9A40, info), \ + INTEL_VGA_DEVICE(0x9A59, info), \ + INTEL_VGA_DEVICE(0x9A60, info), \ + INTEL_VGA_DEVICE(0x9A68, info), \ + INTEL_VGA_DEVICE(0x9A70, info), \ + INTEL_VGA_DEVICE(0x9A78, info) -:34: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects? #34: FILE: include/drm/i915_pciids.h:587: +#define INTEL_TGL_12_IDS(info) \ + INTEL_VGA_DEVICE(0x9A49, info), \ + INTEL_VGA_DEVICE(0x9A40, info), \ + INTEL_VGA_DEVICE(0x9A59, info), \ + INTEL_VGA_DEVICE(0x9A60, info), \ + INTEL_VGA_DEVICE(0x9A68, info), \ + INTEL_VGA_DEVICE(0x9A70, info), \ + INTEL_VGA_DEVICE(0x9A78, info) total: 1 errors, 0 warnings, 1 checks, 21 lines checked f4bc08927341 x86/gpu: add TGL stolen memory support 83c4d1f873b5 drm/i915/tgl: Check if pipe D is fused 2ed955964046 drm/i915/tgl: rename TRANSCODER_EDP_VDSC to use on transcoder A 7da85cb1428c drm/i915/tgl: Add power well support 5389b91d4818 drm/i915/tgl: Add power well to support 4th pipe 823df8840f44 drm/i915/tgl: Add new pll ids 7c59befa3c4c drm/i915/tgl: Add pll manager 3302928f181c drm/i915/tgl: Add additional ports for Tiger Lake 3c4b2d16195c drm/i915/tgl: update ddi/tc clock_off bits -:24: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'port' - possible side-effects? #24: FILE: drivers/gpu/drm/i915/i915_reg.h:9726: +#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_C ? 24 : \ + (port) + 10)) -:26: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'tc_port' - possible side-effects? #26: FILE: drivers/gpu/drm/i915/i915_reg.h:9728: +#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < PORT_TC4 ? \ + (tc_port) + 12 : \ + (tc_port) - PORT_TC4 + 21)) total: 0 errors, 0 warnings, 2 checks, 14 lines checked 92d6c3891dab drm/i915/tgl: Add gmbus gpio pin to port mapping 2a57fe2608ac drm/i915/tgl: port to ddc pin mapping 3d15834d9ff4 drm/i915/tgl: select correct bit for port select 9781f9a6a87e drm/i915/tgl: extend intel_port_is_combophy/tc 96761325338d drm/i915/tgl: init ddi port A-C for Tiger Lake 998ef7f0436d drm/i915/tgl: Add vbt value mapping for DDC Bus pin d7de35fc7516 drm/i915/tgl: apply Display WA #1178 to fix type C dongles f4a17f51c2f6 drm/i915/gen12: MBUS B credit change 605688040111 drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization 4398be057620 drm/i915/tgl: Add DPLL registers 37e84ddbab72 drm/i915/tgl: Update DPLL clock reference register ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/gt: Drop the duplicate workaround
The workarounds was revived in the backmerge that was meant to fix it!
Fixes: 88c90e800675 ("Merge drm/drm-next into drm-intel-next-queued")
Signed-off-by: Chris Wilson
Cc: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index f6fd6905ee6f..9e069286d3ce 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -531,12 +531,6 @@ static void icl_ctx_workarounds_init(struct
intel_engine_cs *engine,
{
struct drm_i915_private *i915 = engine->i915;
- /* WaDisableBankHangMode:icl */
- wa_write(wal,
-GEN8_L3CNTLREG,
-intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) |
-GEN8_ERRDETBCTRL);
-
/* WaDisableBankHangMode:icl */
wa_write(wal,
GEN8_L3CNTLREG,
--
2.22.0
___
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[Intel-gfx] [PATCH v2] drm/i915/tgl: Add power well to support 4th pipe
From: Mika Kahola
Add power well 5 to support 4th pipe and transcoder on TGL.
v2: remove parts that should be squashed on the generic power well
support patch
Cc: James Ausmus
Cc: Imre Deak
Signed-off-by: Mika Kahola
Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
---
.../drm/i915/display/intel_display_power.c| 28 +--
.../drm/i915/display/intel_display_power.h| 3 ++
drivers/gpu/drm/i915/i915_reg.h | 1 +
3 files changed, 29 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index fead072afd96..659c0954eaf7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -37,18 +37,24 @@ intel_display_power_domain_str(struct drm_i915_private
*i915,
return "PIPE_B";
case POWER_DOMAIN_PIPE_C:
return "PIPE_C";
+ case POWER_DOMAIN_PIPE_D:
+ return "PIPE_D";
case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
return "PIPE_A_PANEL_FITTER";
case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
return "PIPE_B_PANEL_FITTER";
case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
return "PIPE_C_PANEL_FITTER";
+ case POWER_DOMAIN_PIPE_D_PANEL_FITTER:
+ return "PIPE_D_PANEL_FITTER";
case POWER_DOMAIN_TRANSCODER_A:
return "TRANSCODER_A";
case POWER_DOMAIN_TRANSCODER_B:
return "TRANSCODER_B";
case POWER_DOMAIN_TRANSCODER_C:
return "TRANSCODER_C";
+ case POWER_DOMAIN_TRANSCODER_D:
+ return "TRANSCODER_D";
case POWER_DOMAIN_TRANSCODER_EDP:
return "TRANSCODER_EDP";
case POWER_DOMAIN_TRANSCODER_VDSC_PW2:
@@ -2538,8 +2544,13 @@ void intel_display_power_put(struct drm_i915_private
*dev_priv,
#define ICL_AUX_TBT4_IO_POWER_DOMAINS (\
BIT_ULL(POWER_DOMAIN_AUX_TBT4))
-/* TODO: TGL_PW_5_POWER_DOMAINS: PIPE_D */
+#define TGL_PW_5_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_D) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
#define TGL_PW_4_POWER_DOMAINS ( \
+ TGL_PW_5_POWER_DOMAINS |\
BIT_ULL(POWER_DOMAIN_PIPE_C) | \
BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
BIT_ULL(POWER_DOMAIN_INIT))
@@ -2549,7 +2560,7 @@ void intel_display_power_put(struct drm_i915_private
*dev_priv,
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |\
BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |\
- /* TODO: TRANSCODER_D */\
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_D) |\
BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_LANES) | \
BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO) | \
@@ -3892,7 +3903,18 @@ static const struct i915_power_well_desc
tgl_power_wells[] = {
.hsw.irq_pipe_mask = BIT(PIPE_C),
}
},
- /* TODO: power well 5 for pipe D */
+ {
+ .name = "power well 5",
+ .domains = TGL_PW_5_POWER_DOMAINS,
+ .ops = _power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = _power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_PW_5,
+ .hsw.has_fuses = true,
+ .hsw.irq_pipe_mask = BIT(PIPE_D),
+ },
+ },
};
static int
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
b/drivers/gpu/drm/i915/display/intel_display_power.h
index 54ad4f0b0886..a264f18c95f1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -18,12 +18,15 @@ enum intel_display_power_domain {
POWER_DOMAIN_PIPE_A,
POWER_DOMAIN_PIPE_B,
POWER_DOMAIN_PIPE_C,
+ POWER_DOMAIN_PIPE_D,
POWER_DOMAIN_PIPE_A_PANEL_FITTER,
POWER_DOMAIN_PIPE_B_PANEL_FITTER,
POWER_DOMAIN_PIPE_C_PANEL_FITTER,
+ POWER_DOMAIN_PIPE_D_PANEL_FITTER,
POWER_DOMAIN_TRANSCODER_A,
POWER_DOMAIN_TRANSCODER_B,
POWER_DOMAIN_TRANSCODER_C,
+ POWER_DOMAIN_TRANSCODER_D,
POWER_DOMAIN_TRANSCODER_EDP,
/* VDSC/joining for TRANSCODER_EDP (ICL) or TRANSCODER_A (TGL) */
POWER_DOMAIN_TRANSCODER_VDSC_PW2,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 63238db21b44..5ca74eca05a4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9148,6 +9148,7 @@ enum {
#define SKL_PW_CTL_IDX_MISC_IO 0
/*
[Intel-gfx] [PATCH v3] drm/i915/tgl: Add power well support
From: Imre Deak
The patch adds the new power wells introduced by TGL (GEN 12) and
maps these to existing/new power domains. The changes for GEN 12 wrt
to GEN 11 are the following:
- Transcoder#EDP removed from power well#1 (Transcoder#A used in
low-power mode instead)
- Transcoder#A is now backed by power well#1 instead of power well#3
- The DDI#B/C combo PHY ports are now backed by power well#1 instead of
power well#3
- New power well#5 added for pipe#D functionality (TODO)
- 2 additional TC ports (TC#5-6) backed by power well#3, 2 port
specific IO power wells (only for the non-TBT modes) and 4 port
specific AUX power wells (2-2 for TBT vs. non-TBT modes)
- Power well#2 backs now VDSC/joining for pipe#A instead of VDSC for
eDP and MIPI DSI (TODO)
On TGL Port DDI#C changed to be a combo PHY (native DP/HDMI) and
BSpec has renamed ports DDI#D-F to TC#4-6 respectively. Thus on ICL we
have the following naming for ports:
- Combo PHYs (native DP/HDMI):
DDI#A-B
- TBT/non-TBT (TC altmode, native DP/HDMI) PHYs:
DDI#C-F
Starting from GEN 12 we have the following naming for ports:
- Combo PHYs (native DP/HDMI):
DDI#A-C
- TBT/non-TBT (TC altmode, native DP/HDMI) PHYs:
DDI TC#1-6
To save some space in the power domain enum the power domain naming in
the driver reflects the above change, that is power domains TC#1-3 are
added as aliases for DDI#D-F and new power domains are reserved for
TC#4-6.
v2 (Lucas):
- Separate out the bits and definitions for TGL from the ICL ones.
Fix use of TRANSCODER_EDP_VDSC, that is now the correct define since
we don't define TRANSCODER_A_VDSC power domain to spare a one bit in
the bitmask (suggested by Ville)
v3 (Lucas):
- Fix missing squashes on v2
- Rebase on renamed TRANSCODER_EDP_VDSC
Cc: Ville Syrjälä
Cc: Anusha Srivatsa
Cc: Rodrigo Vivi
Cc: José Roberto de Souza
Signed-off-by: Imre Deak
Signed-off-by: Lucas De Marchi
Reviewed-by: Ville Syrjälä
---
.../drm/i915/display/intel_display_power.c| 474 +-
.../drm/i915/display/intel_display_power.h| 26 +-
drivers/gpu/drm/i915/i915_debugfs.c | 3 +-
drivers/gpu/drm/i915/i915_reg.h | 20 +-
4 files changed, 506 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 89f68b05e5c0..4c8cbc16b501 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -23,8 +23,11 @@ bool intel_display_power_well_is_enabled(struct
drm_i915_private *dev_priv,
enum i915_power_well_id power_well_id);
const char *
-intel_display_power_domain_str(enum intel_display_power_domain domain)
+intel_display_power_domain_str(struct drm_i915_private *i915,
+ enum intel_display_power_domain domain)
{
+ bool ddi_tc_ports = IS_GEN(i915, 12);
+
switch (domain) {
case POWER_DOMAIN_DISPLAY_CORE:
return "DISPLAY_CORE";
@@ -61,11 +64,23 @@ intel_display_power_domain_str(enum
intel_display_power_domain domain)
case POWER_DOMAIN_PORT_DDI_C_LANES:
return "PORT_DDI_C_LANES";
case POWER_DOMAIN_PORT_DDI_D_LANES:
- return "PORT_DDI_D_LANES";
+ BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_D_LANES !=
+POWER_DOMAIN_PORT_DDI_TC1_LANES);
+ return ddi_tc_ports ? "PORT_DDI_TC1_LANES" : "PORT_DDI_D_LANES";
case POWER_DOMAIN_PORT_DDI_E_LANES:
- return "PORT_DDI_E_LANES";
+ BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_E_LANES !=
+POWER_DOMAIN_PORT_DDI_TC2_LANES);
+ return ddi_tc_ports ? "PORT_DDI_TC2_LANES" : "PORT_DDI_E_LANES";
case POWER_DOMAIN_PORT_DDI_F_LANES:
- return "PORT_DDI_F_LANES";
+ BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_F_LANES !=
+POWER_DOMAIN_PORT_DDI_TC3_LANES);
+ return ddi_tc_ports ? "PORT_DDI_TC3_LANES" : "PORT_DDI_F_LANES";
+ case POWER_DOMAIN_PORT_DDI_TC4_LANES:
+ return "PORT_DDI_TC4_LANES";
+ case POWER_DOMAIN_PORT_DDI_TC5_LANES:
+ return "PORT_DDI_TC5_LANES";
+ case POWER_DOMAIN_PORT_DDI_TC6_LANES:
+ return "PORT_DDI_TC6_LANES";
case POWER_DOMAIN_PORT_DDI_A_IO:
return "PORT_DDI_A_IO";
case POWER_DOMAIN_PORT_DDI_B_IO:
@@ -73,11 +88,23 @@ intel_display_power_domain_str(enum
intel_display_power_domain domain)
case POWER_DOMAIN_PORT_DDI_C_IO:
return "PORT_DDI_C_IO";
case POWER_DOMAIN_PORT_DDI_D_IO:
- return "PORT_DDI_D_IO";
+ BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_D_IO !=
+POWER_DOMAIN_PORT_DDI_TC1_IO);
+ return ddi_tc_ports ? "PORT_DDI_TC1_IO" : "PORT_DDI_D_IO";
case
[Intel-gfx] [PATCH] drm/i915/tgl: rename TRANSCODER_EDP_VDSC to use on transcoder A
From: José Roberto de Souza
On TGL the special EDP transcoder is gone and it should be handled by
transcoder A.
v2 (Lucas):
- Reuse POWER_DOMAIN_TRANSCODER_EDP_VDSC (suggested by Ville)
- Use crtc->dev since new_crtc_state->state may be NULL on atomic
commit (suggested by Maarten)
v3 (Lucas):
- Rename power domain so it's clear it can also be used for transcoder
A in TGL (requested by José and Manasi)
Cc: Imre Deak
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display_power.c | 6 +++---
drivers/gpu/drm/i915/display/intel_display_power.h | 3 ++-
drivers/gpu/drm/i915/display/intel_vdsc.c | 14 ++
3 files changed, 15 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 7437fc71d289..4f4c35a5ef2a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -48,8 +48,8 @@ intel_display_power_domain_str(enum
intel_display_power_domain domain)
return "TRANSCODER_C";
case POWER_DOMAIN_TRANSCODER_EDP:
return "TRANSCODER_EDP";
- case POWER_DOMAIN_TRANSCODER_EDP_VDSC:
- return "TRANSCODER_EDP_VDSC";
+ case POWER_DOMAIN_TRANSCODER_VDSC_PW2:
+ return "TRANSCODER_VDSC_PW2";
case POWER_DOMAIN_TRANSCODER_DSI_A:
return "TRANSCODER_DSI_A";
case POWER_DOMAIN_TRANSCODER_DSI_C:
@@ -2448,7 +2448,7 @@ void intel_display_power_put(struct drm_i915_private
*dev_priv,
*/
#define ICL_PW_2_POWER_DOMAINS ( \
ICL_PW_3_POWER_DOMAINS |\
- BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
BIT_ULL(POWER_DOMAIN_INIT))
/*
* - KVMR (HW control)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
b/drivers/gpu/drm/i915/display/intel_display_power.h
index 8f43f7051a16..cc6956132ebc 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -25,7 +25,8 @@ enum intel_display_power_domain {
POWER_DOMAIN_TRANSCODER_B,
POWER_DOMAIN_TRANSCODER_C,
POWER_DOMAIN_TRANSCODER_EDP,
- POWER_DOMAIN_TRANSCODER_EDP_VDSC,
+ /* VDSC/joining for TRANSCODER_EDP (ICL) or TRANSCODER_A (TGL) */
+ POWER_DOMAIN_TRANSCODER_VDSC_PW2,
POWER_DOMAIN_TRANSCODER_DSI_A,
POWER_DOMAIN_TRANSCODER_DSI_C,
POWER_DOMAIN_PORT_DDI_A_LANES,
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
b/drivers/gpu/drm/i915/display/intel_vdsc.c
index ffec807b8960..4ab19c432ef5 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -459,17 +459,23 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
enum intel_display_power_domain
intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
{
+ struct drm_i915_private *i915 = to_i915(crtc_state->base.crtc->dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
/*
-* On ICL VDSC/joining for eDP transcoder uses a separate power well PW2
-* This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
+* On ICL VDSC/joining for eDP transcoder uses a separate power well,
+* PW2. This requires POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain.
* For any other transcoder, VDSC/joining uses the power well associated
* with the pipe/transcoder in use. Hence another reference on the
* transcoder power domain will suffice.
+*
+* On TGL we have the same mapping, but for transcoder A (the special
+* TRANSCODER_EDP is gone).
*/
- if (cpu_transcoder == TRANSCODER_EDP)
- return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
+ if (INTEL_GEN(i915) >= 12 && cpu_transcoder == TRANSCODER_A)
+ return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
+ else if (cpu_transcoder == TRANSCODER_EDP)
+ return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
else
return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
}
--
2.21.0
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Re: [Intel-gfx] [PATCH 2/2] drm/i915/display/tgl: Bump up the plane/fb height to support 8K
On Wed, Jul 10, 2019 at 10:18:38PM +0300, Ville Syrjälä wrote:
> On Tue, Jul 09, 2019 at 02:47:35PM -0700, Manasi Navare wrote:
> > On TGL+, the plane height for 8K planes can be 4320, so bump it up
> > To support 4320, we need to increase the number of bits used to
> > read plane_height to 13 as opposed to older 12 bits.
> >
> > Cc: Maarten Lankhorst
> > Cc: Ville Syrjälä
> > Signed-off-by: Manasi Navare
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 21 ++--
> > 1 file changed, 19 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 0d5c8af01f54..be9a54cb5ecc 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -3343,6 +3343,16 @@ static int icl_max_plane_width(const struct
> > drm_framebuffer *fb,
> > return 5120;
> > }
> >
> > +static int skl_max_plane_height(void)
> > +{
> > + return 4096;
> > +}
> > +
> > +static int tgl_max_plane_height(void)
> > +{
> > + return 4320;
Yes icl does but we start supporting 8K from tgl, should this be changed to
icl_max_plane_height()
and return 4320?
Manasi
>
> icl has this limit already.
>
> > +}
> > +
> > static bool skl_check_main_ccs_coordinates(struct intel_plane_state
> > *plane_state,
> >int main_x, int main_y, u32
> > main_offset)
> > {
> > @@ -3391,9 +3401,13 @@ static int skl_check_main_surface(struct
> > intel_plane_state *plane_state)
> > int w = drm_rect_width(_state->base.src) >> 16;
> > int h = drm_rect_height(_state->base.src) >> 16;
> > int max_width;
> > - int max_height = 4096;
> > + int max_height;
> > u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset;
> >
> > + if (INTEL_GEN(dev_priv) >= 12)
> > + max_height = tgl_max_plane_height();
> > + else
> > + max_height = skl_max_plane_height();
> > if (INTEL_GEN(dev_priv) >= 11)
> > max_width = icl_max_plane_width(fb, 0, rotation);
> > else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> > @@ -9865,7 +9879,10 @@ skylake_get_initial_plane_config(struct intel_crtc
> > *crtc,
> > offset = I915_READ(PLANE_OFFSET(pipe, plane_id));
> >
> > val = I915_READ(PLANE_SIZE(pipe, plane_id));
> > - fb->height = ((val >> 16) & 0xfff) + 1;
> > + if (INTEL_GEN(dev_priv) >= 12)
> > + fb->height = ((val >> 16) & 0x1fff) + 1;
> > + else
> > + fb->height = ((val >> 16) & 0xfff) + 1;
> > fb->width = ((val >> 0) & 0x1fff) + 1;
> >
> > val = I915_READ(PLANE_STRIDE(pipe, plane_id));
> > --
> > 2.19.1
>
> --
> Ville Syrjälä
> Intel
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Re: [Intel-gfx] [PATCH v2 4/4] drm/i915: Add modular FIA
On Wed, Jul 10, 2019 at 12:22:51PM -0700, Lucas De Marchi wrote:
> On Wed, Jul 10, 2019 at 09:33:39PM +0300, Ville Syrjälä wrote:
> >On Mon, Jul 08, 2019 at 10:28:15AM -0700, Lucas De Marchi wrote:
> >> From: Anusha Srivatsa
> >>
> >> Some platforms may have Modular FIA. If Modular FIA is used in the SOC,
> >> then Display Driver will access the additional instances of
> >> FIA based on pre-assigned offset in GTTMADDR space.
> >>
> >> Each Modular FIA instance has its own IOSF Sideband Port ID
> >> and it houses only 2 Type-C Port. In SOC that has more than
> >> two Type-C Ports, there are multiple instances of Modular FIA.
> >> Gunit will need to use different destination ID when it access
> >> different pair of Type-C Port.
> >>
> >> The DFLEXDPSP register has Modular FIA bit starting on Tiger Lake. If
> >> Modular FIA is used in the SOC, this register bit exists in all the
> >> instances of Modular FIA. IOM FW is required to program only the MF bit
> >> in first FIA instance that houses the Type-C Port 0 and Port 1, for
> >> Display Driver to read from.
> >>
> >> v2 (Lucas):
> >> - Move all accesses to FIA to be contained in intel_tc.c, along with
> >> display_fia that is now called tc_phy_fia
> >> - Save the fia instance number on intel_digital_port, so we don't have
> >> to query if modular FIA is used on every access
> >> v3 (Lucas):
> >> - Make function static
> >>
> >> Cc: Jani Nikula
> >> Signed-off-by: Anusha Srivatsa
> >> Signed-off-by: Lucas De Marchi
> >> ---
> >> drivers/gpu/drm/i915/display/intel_tc.c | 49
> >> drivers/gpu/drm/i915/i915_reg.h | 13 +--
> >> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> >> drivers/gpu/drm/i915/intel_drv.h | 1 +
> >> 4 files changed, 52 insertions(+), 12 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
> >> b/drivers/gpu/drm/i915/display/intel_tc.c
> >> index f44ee4bfe7c8..671261b55d11 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> >> @@ -8,6 +8,12 @@
> >> #include "intel_dp_mst.h"
> >> #include "intel_tc.h"
> >>
> >> +enum phy_fia {
> >> + FIA1,
> >> + FIA2,
> >> + FIA3,
> >> +};
> >> +
> >> static const char *tc_port_mode_name(enum tc_port_mode mode)
> >> {
> >>static const char * const names[] = {
> >> @@ -22,6 +28,24 @@ static const char *tc_port_mode_name(enum tc_port_mode
> >> mode)
> >>return names[mode];
> >> }
> >>
> >> +static bool has_modular_fia(struct drm_i915_private *i915)
> >> +{
> >> + if (!INTEL_INFO(i915)->display.has_modular_fia)
> >> + return false;
> >> +
> >> + return intel_uncore_read(>uncore,
> >> + PORT_TX_DFLEXDPSP(FIA1)) & MODULAR_FIA_MASK;
> >> +}
> >> +
> >> +static enum phy_fia tc_port_to_fia(struct drm_i915_private *i915,
> >> + enum tc_port tc_port)
> >> +{
> >> + if (!has_modular_fia(i915))
> >> + return FIA1;
> >> +
> >> + return tc_port / 2;
> >> +}
> >> +
> >> u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
> >> {
> >>struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> >> @@ -29,7 +53,8 @@ u32 intel_tc_port_get_lane_mask(struct
> >> intel_digital_port *dig_port)
> >>struct intel_uncore *uncore = >uncore;
> >>u32 lane_mask;
> >>
> >> - lane_mask = intel_uncore_read(uncore, PORT_TX_DFLEXDPSP);
> >> + lane_mask = intel_uncore_read(uncore,
> >> +PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
> >>
> >>WARN_ON(lane_mask == 0x);
> >>
> >> @@ -78,7 +103,8 @@ void intel_tc_port_set_fia_lane_count(struct
> >> intel_digital_port *dig_port,
> >>
> >>WARN_ON(lane_reversal && dig_port->tc_mode != TC_PORT_LEGACY);
> >>
> >> - val = intel_uncore_read(uncore, PORT_TX_DFLEXDPMLE1);
> >> + val = intel_uncore_read(uncore,
> >> + PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia));
> >>val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
> >>
> >>switch (required_lanes) {
> >> @@ -97,7 +123,8 @@ void intel_tc_port_set_fia_lane_count(struct
> >> intel_digital_port *dig_port,
> >>MISSING_CASE(required_lanes);
> >>}
> >>
> >> - intel_uncore_write(uncore, PORT_TX_DFLEXDPMLE1, val);
> >> + intel_uncore_write(uncore,
> >> + PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia), val);
> >> }
> >>
> >> static void tc_port_fixup_legacy_flag(struct intel_digital_port *dig_port,
> >> @@ -129,7 +156,8 @@ static u32 tc_port_live_status_mask(struct
> >> intel_digital_port *dig_port)
> >>u32 mask = 0;
> >>u32 val;
> >>
> >> - val = intel_uncore_read(uncore, PORT_TX_DFLEXDPSP);
> >> + val = intel_uncore_read(uncore,
> >> + PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
> >>
> >>if (val == 0x) {
> >>DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, nothing connected\n",
> >> @@ -159,7 +187,8 @@ static bool
Re: [Intel-gfx] [PATCH v2] drm/i915/display/tgl: Bump up the mode vertical limits to support 8K
On Wed, Jul 10, 2019 at 12:24:15PM -0700, Manasi Navare wrote:
> On Wed, Jul 10, 2019 at 10:15:05PM +0300, Ville Syrjälä wrote:
> > On Tue, Jul 09, 2019 at 05:06:13PM -0700, Manasi Navare wrote:
> > > On TGL+ we support 8K display resolution, hence bump up the vertical
> > > active limits to 4320 in intel_mode_valid()
> > >
> > > v2:
> > > * Checkpatch warning (Manasi)
> > >
> > > Cc: Maarten Lankhorst
> > > Cc: Ville Syrjälä
> > > Signed-off-by: Manasi Navare
> > > ---
> > > drivers/gpu/drm/i915/display/intel_display.c | 9 +++--
> > > 1 file changed, 7 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > index f07081815b80..cfceb27e4b9e 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -15764,8 +15764,13 @@ intel_mode_valid(struct drm_device *dev,
> > > DRM_MODE_FLAG_CLKDIV2))
> > > return MODE_BAD;
> > >
> > > - if (INTEL_GEN(dev_priv) >= 9 ||
> > > - IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
> > > + if (INTEL_GEN(dev_priv) >= 12) {
> > > + hdisplay_max = 8192;
> > > + vdisplay_max = 4320;
> > > + htotal_max = 8192;
> > > + vtotal_max = 8192;
> >
> > I wonder if we can safely bump these before we get the joiner stuff sorted.
> > Hmm. I guess it should be fine as the limit that is supposed to overcome
> > is caused by the cdclk max frequency being too low to allow a single
> > pipe to push enough pixels. And since we check that in .mode_valid() we
> > shouldn't accidentally start to advertize support for modes we can't do.
>
> Yes the intel_dp_mode_valid() will still reject the modes until we have the
> support
> for big joiner, so allowing these limits should be fine here.
>
> Same for the plane size limits. Plane size limits bumping up is also
> needed in case of tiled 8K display with transcdoer port sync
>
> >
> > Which means these limits should actually be higher than this. 16k for
> > htotal+hdisplay and 8k for vtotal+vdisplay already on icl I believe.
>
> Where do we set htotal+hdisplay? And I added this for tgl, since we would be
> supporting the 8K res only on tgl onwards, correct?
We can do 8k on earlier platforms too, assuming the clock is low enough.
Also icl already can do the joining stuff no?
Anwyays these number are just the straight up transcoder max timings
from the spec, and that's what I think they should stay. If we need to
impose some other arbitrary limits for other reasons we should do that
separately.
Hmm. I guess planes is the other thing that's a problem for 8k and such.
The documented max width is too small for any single plane to cover
such a big pipe. We should perhaps be validating modes against the plane
limits as well...
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v2 4/4] drm/i915: Add modular FIA
On Wed, Jul 10, 2019 at 09:33:39PM +0300, Ville Syrjälä wrote:
On Mon, Jul 08, 2019 at 10:28:15AM -0700, Lucas De Marchi wrote:
From: Anusha Srivatsa
Some platforms may have Modular FIA. If Modular FIA is used in the SOC,
then Display Driver will access the additional instances of
FIA based on pre-assigned offset in GTTMADDR space.
Each Modular FIA instance has its own IOSF Sideband Port ID
and it houses only 2 Type-C Port. In SOC that has more than
two Type-C Ports, there are multiple instances of Modular FIA.
Gunit will need to use different destination ID when it access
different pair of Type-C Port.
The DFLEXDPSP register has Modular FIA bit starting on Tiger Lake. If
Modular FIA is used in the SOC, this register bit exists in all the
instances of Modular FIA. IOM FW is required to program only the MF bit
in first FIA instance that houses the Type-C Port 0 and Port 1, for
Display Driver to read from.
v2 (Lucas):
- Move all accesses to FIA to be contained in intel_tc.c, along with
display_fia that is now called tc_phy_fia
- Save the fia instance number on intel_digital_port, so we don't have
to query if modular FIA is used on every access
v3 (Lucas):
- Make function static
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_tc.c | 49
drivers/gpu/drm/i915/i915_reg.h | 13 +--
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/intel_drv.h | 1 +
4 files changed, 52 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
b/drivers/gpu/drm/i915/display/intel_tc.c
index f44ee4bfe7c8..671261b55d11 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -8,6 +8,12 @@
#include "intel_dp_mst.h"
#include "intel_tc.h"
+enum phy_fia {
+ FIA1,
+ FIA2,
+ FIA3,
+};
+
static const char *tc_port_mode_name(enum tc_port_mode mode)
{
static const char * const names[] = {
@@ -22,6 +28,24 @@ static const char *tc_port_mode_name(enum tc_port_mode mode)
return names[mode];
}
+static bool has_modular_fia(struct drm_i915_private *i915)
+{
+ if (!INTEL_INFO(i915)->display.has_modular_fia)
+ return false;
+
+ return intel_uncore_read(>uncore,
+PORT_TX_DFLEXDPSP(FIA1)) & MODULAR_FIA_MASK;
+}
+
+static enum phy_fia tc_port_to_fia(struct drm_i915_private *i915,
+ enum tc_port tc_port)
+{
+ if (!has_modular_fia(i915))
+ return FIA1;
+
+ return tc_port / 2;
+}
+
u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
@@ -29,7 +53,8 @@ u32 intel_tc_port_get_lane_mask(struct intel_digital_port
*dig_port)
struct intel_uncore *uncore = >uncore;
u32 lane_mask;
- lane_mask = intel_uncore_read(uncore, PORT_TX_DFLEXDPSP);
+ lane_mask = intel_uncore_read(uncore,
+ PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
WARN_ON(lane_mask == 0x);
@@ -78,7 +103,8 @@ void intel_tc_port_set_fia_lane_count(struct
intel_digital_port *dig_port,
WARN_ON(lane_reversal && dig_port->tc_mode != TC_PORT_LEGACY);
- val = intel_uncore_read(uncore, PORT_TX_DFLEXDPMLE1);
+ val = intel_uncore_read(uncore,
+ PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia));
val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
switch (required_lanes) {
@@ -97,7 +123,8 @@ void intel_tc_port_set_fia_lane_count(struct
intel_digital_port *dig_port,
MISSING_CASE(required_lanes);
}
- intel_uncore_write(uncore, PORT_TX_DFLEXDPMLE1, val);
+ intel_uncore_write(uncore,
+ PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia), val);
}
static void tc_port_fixup_legacy_flag(struct intel_digital_port *dig_port,
@@ -129,7 +156,8 @@ static u32 tc_port_live_status_mask(struct
intel_digital_port *dig_port)
u32 mask = 0;
u32 val;
- val = intel_uncore_read(uncore, PORT_TX_DFLEXDPSP);
+ val = intel_uncore_read(uncore,
+ PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
if (val == 0x) {
DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, nothing connected\n",
@@ -159,7 +187,8 @@ static bool icl_tc_phy_status_complete(struct
intel_digital_port *dig_port)
struct intel_uncore *uncore = >uncore;
u32 val;
- val = intel_uncore_read(uncore, PORT_TX_DFLEXDPPMS);
+ val = intel_uncore_read(uncore,
+ PORT_TX_DFLEXDPPMS(dig_port->tc_phy_fia));
if (val == 0x) {
DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, assuming not complete\n",
dig_port->tc_port_name);
@@ -177,7 +206,8 @@
Re: [Intel-gfx] [PATCH v2] drm/i915/display/tgl: Bump up the mode vertical limits to support 8K
On Wed, Jul 10, 2019 at 10:15:05PM +0300, Ville Syrjälä wrote:
> On Tue, Jul 09, 2019 at 05:06:13PM -0700, Manasi Navare wrote:
> > On TGL+ we support 8K display resolution, hence bump up the vertical
> > active limits to 4320 in intel_mode_valid()
> >
> > v2:
> > * Checkpatch warning (Manasi)
> >
> > Cc: Maarten Lankhorst
> > Cc: Ville Syrjälä
> > Signed-off-by: Manasi Navare
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 9 +++--
> > 1 file changed, 7 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index f07081815b80..cfceb27e4b9e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -15764,8 +15764,13 @@ intel_mode_valid(struct drm_device *dev,
> >DRM_MODE_FLAG_CLKDIV2))
> > return MODE_BAD;
> >
> > - if (INTEL_GEN(dev_priv) >= 9 ||
> > - IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
> > + if (INTEL_GEN(dev_priv) >= 12) {
> > + hdisplay_max = 8192;
> > + vdisplay_max = 4320;
> > + htotal_max = 8192;
> > + vtotal_max = 8192;
>
> I wonder if we can safely bump these before we get the joiner stuff sorted.
> Hmm. I guess it should be fine as the limit that is supposed to overcome
> is caused by the cdclk max frequency being too low to allow a single
> pipe to push enough pixels. And since we check that in .mode_valid() we
> shouldn't accidentally start to advertize support for modes we can't do.
Yes the intel_dp_mode_valid() will still reject the modes until we have the
support
for big joiner, so allowing these limits should be fine here.
Same for the plane size limits. Plane size limits bumping up is also
needed in case of tiled 8K display with transcdoer port sync
>
> Which means these limits should actually be higher than this. 16k for
> htotal+hdisplay and 8k for vtotal+vdisplay already on icl I believe.
Where do we set htotal+hdisplay? And I added this for tgl, since we would be
supporting the 8K res only on tgl onwards, correct?
Manasi
>
> > + } else if (INTEL_GEN(dev_priv) >= 9 ||
> > + IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
> > hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
> > vdisplay_max = 4096;
> > htotal_max = 8192;
> > --
> > 2.19.1
>
> --
> Ville Syrjälä
> Intel
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Re: [Intel-gfx] [PATCH 2/2] drm/i915/display/tgl: Bump up the plane/fb height to support 8K
On Tue, Jul 09, 2019 at 02:47:35PM -0700, Manasi Navare wrote:
> On TGL+, the plane height for 8K planes can be 4320, so bump it up
> To support 4320, we need to increase the number of bits used to
> read plane_height to 13 as opposed to older 12 bits.
>
> Cc: Maarten Lankhorst
> Cc: Ville Syrjälä
> Signed-off-by: Manasi Navare
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 21 ++--
> 1 file changed, 19 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 0d5c8af01f54..be9a54cb5ecc 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3343,6 +3343,16 @@ static int icl_max_plane_width(const struct
> drm_framebuffer *fb,
> return 5120;
> }
>
> +static int skl_max_plane_height(void)
> +{
> + return 4096;
> +}
> +
> +static int tgl_max_plane_height(void)
> +{
> + return 4320;
icl has this limit already.
> +}
> +
> static bool skl_check_main_ccs_coordinates(struct intel_plane_state
> *plane_state,
> int main_x, int main_y, u32
> main_offset)
> {
> @@ -3391,9 +3401,13 @@ static int skl_check_main_surface(struct
> intel_plane_state *plane_state)
> int w = drm_rect_width(_state->base.src) >> 16;
> int h = drm_rect_height(_state->base.src) >> 16;
> int max_width;
> - int max_height = 4096;
> + int max_height;
> u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset;
>
> + if (INTEL_GEN(dev_priv) >= 12)
> + max_height = tgl_max_plane_height();
> + else
> + max_height = skl_max_plane_height();
> if (INTEL_GEN(dev_priv) >= 11)
> max_width = icl_max_plane_width(fb, 0, rotation);
> else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> @@ -9865,7 +9879,10 @@ skylake_get_initial_plane_config(struct intel_crtc
> *crtc,
> offset = I915_READ(PLANE_OFFSET(pipe, plane_id));
>
> val = I915_READ(PLANE_SIZE(pipe, plane_id));
> - fb->height = ((val >> 16) & 0xfff) + 1;
> + if (INTEL_GEN(dev_priv) >= 12)
> + fb->height = ((val >> 16) & 0x1fff) + 1;
> + else
> + fb->height = ((val >> 16) & 0xfff) + 1;
> fb->width = ((val >> 0) & 0x1fff) + 1;
>
> val = I915_READ(PLANE_STRIDE(pipe, plane_id));
> --
> 2.19.1
--
Ville Syrjälä
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Re: [Intel-gfx] [PATCH v2] drm/i915/display/tgl: Bump up the mode vertical limits to support 8K
On Tue, Jul 09, 2019 at 05:06:13PM -0700, Manasi Navare wrote:
> On TGL+ we support 8K display resolution, hence bump up the vertical
> active limits to 4320 in intel_mode_valid()
>
> v2:
> * Checkpatch warning (Manasi)
>
> Cc: Maarten Lankhorst
> Cc: Ville Syrjälä
> Signed-off-by: Manasi Navare
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 9 +++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index f07081815b80..cfceb27e4b9e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -15764,8 +15764,13 @@ intel_mode_valid(struct drm_device *dev,
> DRM_MODE_FLAG_CLKDIV2))
> return MODE_BAD;
>
> - if (INTEL_GEN(dev_priv) >= 9 ||
> - IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
> + if (INTEL_GEN(dev_priv) >= 12) {
> + hdisplay_max = 8192;
> + vdisplay_max = 4320;
> + htotal_max = 8192;
> + vtotal_max = 8192;
I wonder if we can safely bump these before we get the joiner stuff sorted.
Hmm. I guess it should be fine as the limit that is supposed to overcome
is caused by the cdclk max frequency being too low to allow a single
pipe to push enough pixels. And since we check that in .mode_valid() we
shouldn't accidentally start to advertize support for modes we can't do.
Which means these limits should actually be higher than this. 16k for
htotal+hdisplay and 8k for vtotal+vdisplay already on icl I believe.
> + } else if (INTEL_GEN(dev_priv) >= 9 ||
> +IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
> hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
> vdisplay_max = 4096;
> htotal_max = 8192;
> --
> 2.19.1
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] PR- GUC v33 (BXT,SKL,GLK.KBL,ICL)
Hi Kyle, Ben, Josh, Can these i915 changes be merged to linux-firmware.git? Thanks, Anusha From: Srivatsa, Anusha Sent: Monday, July 8, 2019 2:54 PM To: linux-firmw...@kernel.org Cc: intel-gfx@lists.freedesktop.org Subject: PR- GUC v33 (BXT,SKL,GLK.KBL,ICL) Hi, Can these i915 changes be merged to the linux-firmware.git? The following changes since commit 70e43940b05e8d6e0c5f15b5e2d67760f1581ece: linux-firmware: rsi: add firmware image for redpine 9116 chipset (2019-06-28 07:41:20 -0400) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-firmware guc_v33 for you to fetch changes up to 05dbae6639f09c3e0a02e93de5f803db9aadedd1: drm/i915/firmware: Add v33 of GuC for ICL (2019-07-08 14:40:55 -0700) Anusha Srivatsa (5): drm/i915/firmware: Add v33 of GuC for BXT drm/i915/firmware: Add v33 of GuC for GLK drm/i915/firmware: Add v33 of GuC for SKL drm/i915/firmware: Add v33 of GuC for KBL drm/i915/firmware: Add v33 of GuC for ICL WHENCE | 15 +++ i915/bxt_guc_33.0.0.bin | Bin 0 -> 181888 bytes i915/glk_guc_33.0.0.bin | Bin 0 -> 182336 bytes i915/icl_guc_33.0.0.bin | Bin 0 -> 385280 bytes i915/kbl_guc_33.0.0.bin | Bin 0 -> 182912 bytes i915/skl_guc_33.0.0.bin | Bin 0 -> 182080 bytes 6 files changed, 15 insertions(+) create mode 100644 i915/bxt_guc_33.0.0.bin create mode 100644 i915/glk_guc_33.0.0.bin create mode 100644 i915/icl_guc_33.0.0.bin create mode 100644 i915/kbl_guc_33.0.0.bin create mode 100644 i915/skl_guc_33.0.0.bin Thanks, Anusha ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915/display/tgl: Bump up the mode vertical limits to support 8K
On Tue, Jul 09, 2019 at 04:04:58PM -0700, Souza, Jose wrote:
> On Tue, 2019-07-09 at 14:47 -0700, Manasi Navare wrote:
> > On TGL+ we support 8K display resolution, hence bump up the vertical
> > active limits to 4320 in intel_mode_valid()
> >
> > Cc: Maarten Lankhorst
> > Cc: Ville Syrjälä
> > Signed-off-by: Manasi Navare
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 9 +++--
> > 1 file changed, 7 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index f07081815b80..0d5c8af01f54 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -15764,8 +15764,13 @@ intel_mode_valid(struct drm_device *dev,
> >DRM_MODE_FLAG_CLKDIV2))
> > return MODE_BAD;
> >
> > - if (INTEL_GEN(dev_priv) >= 9 ||
> > - IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
> > + if (INTEL_GEN(dev_priv) >=12) {
>
>
> if (INTEL_GEN(dev_priv) >= 12) {
Yup already made this change in v2, r-b with this change?
Manasi
>
> > + hdisplay_max = 8192;
> > + vdisplay_max = 4320;
> > + htotal_max = 8192;
> > + vtotal_max = 8192;
> > + } else if (INTEL_GEN(dev_priv) >= 9 ||
> > + IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
> > hdisplay_max = 8192; /* FDI max 4096 handled elsewhere
> > */
> > vdisplay_max = 4096;
> > htotal_max = 8192;
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Re: [Intel-gfx] [PATCH 2/2] drm/i915/display/tgl: Bump up the plane/fb height to support 8K
On Tue, Jul 09, 2019 at 04:07:23PM -0700, Souza, Jose wrote:
> On Tue, 2019-07-09 at 14:47 -0700, Manasi Navare wrote:
> > On TGL+, the plane height for 8K planes can be 4320, so bump it up
> > To support 4320, we need to increase the number of bits used to
> > read plane_height to 13 as opposed to older 12 bits.
> >
> > Cc: Maarten Lankhorst
> > Cc: Ville Syrjälä
> > Signed-off-by: Manasi Navare
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 21
> > ++--
> > 1 file changed, 19 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 0d5c8af01f54..be9a54cb5ecc 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -3343,6 +3343,16 @@ static int icl_max_plane_width(const struct
> > drm_framebuffer *fb,
> > return 5120;
> > }
> >
> > +static int skl_max_plane_height(void)
> > +{
> > + return 4096;
> > +}
> > +
> > +static int tgl_max_plane_height(void)
> > +{
> > + return 4320;
> > +}
> > +
> > static bool skl_check_main_ccs_coordinates(struct intel_plane_state
> > *plane_state,
> >int main_x, int main_y, u32
> > main_offset)
> > {
> > @@ -3391,9 +3401,13 @@ static int skl_check_main_surface(struct
> > intel_plane_state *plane_state)
> > int w = drm_rect_width(_state->base.src) >> 16;
> > int h = drm_rect_height(_state->base.src) >> 16;
> > int max_width;
> > - int max_height = 4096;
> > + int max_height;
> > u32 alignment, offset, aux_offset = plane_state-
> > >color_plane[1].offset;
> >
> > + if (INTEL_GEN(dev_priv) >= 12)
> > + max_height = tgl_max_plane_height();
> > + else
> > + max_height = skl_max_plane_height();
>
> Give a line between max_width block, also I would move the height after
> the width.
Ok, will make this change, can I add your r-b with this change?
Manasi
>
> > if (INTEL_GEN(dev_priv) >= 11)
> > max_width = icl_max_plane_width(fb, 0, rotation);
> > else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> > @@ -9865,7 +9879,10 @@ skylake_get_initial_plane_config(struct
> > intel_crtc *crtc,
> > offset = I915_READ(PLANE_OFFSET(pipe, plane_id));
> >
> > val = I915_READ(PLANE_SIZE(pipe, plane_id));
> > - fb->height = ((val >> 16) & 0xfff) + 1;
> > + if (INTEL_GEN(dev_priv) >= 12)
> > + fb->height = ((val >> 16) & 0x1fff) + 1;
> > + else
> > + fb->height = ((val >> 16) & 0xfff) + 1;
> > fb->width = ((val >> 0) & 0x1fff) + 1;
> >
> > val = I915_READ(PLANE_STRIDE(pipe, plane_id));
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Re: [Intel-gfx] [PATCH] drm/i915/ehl: Add support for DPLL4 (v10)
On Wed, Jul 03, 2019 at 04:03:53PM -0700, Vivek Kasireddy wrote:
> This patch adds support for DPLL4 on EHL that include the
> following restrictions:
>
> - DPLL4 cannot be used with DDIA (combo port A internal eDP usage).
> DPLL4 can be used with other DDIs, including DDID
> (combo port A external usage).
>
> - DPLL4 cannot be enabled when DC5 or DC6 are enabled.
>
> - The DPLL4 enable, lock, power enabled, and power state are connected
> to the MGPLL1_ENABLE register.
>
> v2: (suggestions from Bob Paauwe)
> - Rework ehl_get_dpll() function to call intel_find_shared_dpll() and
> iterate twice: once for Combo plls and once for MG plls.
>
> - Use MG pll funcs for DPLL4 instead of creating new ones and modify
> mg_pll_enable to include the restrictions for EHL.
>
> v3: Fix compilation error
>
> v4: (suggestions from Lucas and Ville)
> - Treat DPLL4 as a combo phy PLL and not as MG PLL
> - Disable DC states when this DPLL is being enabled
> - Reuse icl_get_dpll instead of creating a separate one for EHL
>
> v5: (suggestion from Ville)
> - Refcount the DC OFF power domains during the enabling and disabling
> of this DPLL.
>
> v6: rebase
>
> v7: (suggestion from Imre)
> - Add a new power domain instead of iterating over the domains
> assoicated with DC OFF power well.
>
> v8: (Ville and Imre)
> - Rename POWER_DOMAIN_DPLL4 TO POWER_DOMAIN_DPLL_DC_OFF
> - Grab a reference in intel_modeset_setup_hw_state() if this
> DPLL was already enabled perhaps by BIOS.
> - Check for the port type instead of the encoder
>
> v9: (Ville)
> - Move the block of code that grabs a reference to the power domain
> POWER_DOMAIN_DPLL_DC_OFF to intel_modeset_readout_hw_state() to ensure
> that there is a reference present before this DPLL might get disabled.
>
> v10: rebase
>
> Cc: José Roberto de Souza
> Cc: Ville Syrjälä
> Cc: Matt Roper
> Cc: Imre Deak
> Signed-off-by: Vivek Kasireddy
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 7 +++
> .../drm/i915/display/intel_display_power.c| 3 ++
> .../drm/i915/display/intel_display_power.h| 1 +
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 47 +--
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 6 +++
> 5 files changed, 60 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 919f5ac844c8..557462208462 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -16653,6 +16653,13 @@ static void intel_modeset_readout_hw_state(struct
> drm_device *dev)
>
> pll->on = pll->info->funcs->get_hw_state(dev_priv, pll,
> >state.hw_state);
> +
> + if (IS_ELKHARTLAKE(dev_priv) && pll->on &&
> + pll->info->id == DPLL_ID_EHL_DPLL4) {
> + pll->wakeref = intel_display_power_get(dev_priv,
> +
> POWER_DOMAIN_DPLL_DC_OFF);
> + }
> +
> pll->state.crtc_mask = 0;
> for_each_intel_crtc(dev, crtc) {
> struct intel_crtc_state *crtc_state =
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index c19b958461ca..7437fc71d289 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -118,6 +118,8 @@ intel_display_power_domain_str(enum
> intel_display_power_domain domain)
> return "MODESET";
> case POWER_DOMAIN_GT_IRQ:
> return "GT_IRQ";
> + case POWER_DOMAIN_DPLL_DC_OFF:
> + return "DPLL_DC_OFF";
> default:
> MISSING_CASE(domain);
> return "?";
> @@ -2455,6 +2457,7 @@ void intel_display_power_put(struct drm_i915_private
> *dev_priv,
> ICL_PW_2_POWER_DOMAINS |\
> BIT_ULL(POWER_DOMAIN_MODESET) | \
> BIT_ULL(POWER_DOMAIN_AUX_A) | \
> + BIT_ULL(POWER_DOMAIN_DPLL_DC_OFF) | \
> BIT_ULL(POWER_DOMAIN_INIT))
>
> #define ICL_DDI_IO_A_POWER_DOMAINS ( \
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
> b/drivers/gpu/drm/i915/display/intel_display_power.h
> index ff57b0a7fe59..8f43f7051a16 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -59,6 +59,7 @@ enum intel_display_power_domain {
> POWER_DOMAIN_GMBUS,
> POWER_DOMAIN_MODESET,
> POWER_DOMAIN_GT_IRQ,
> + POWER_DOMAIN_DPLL_DC_OFF,
> POWER_DOMAIN_INIT,
>
> POWER_DOMAIN_NUM,
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index f953971e7c3b..67cfe836286e 100644
>
Re: [Intel-gfx] [PATCH v2 24/25] drm/i915/tgl: Add DPLL registers
On Tue, Jul 09, 2019 at 08:58:32AM -0700, Lucas De Marchi wrote:
> On Tue, Jul 09, 2019 at 03:56:51PM +0300, Ville Syrjälä wrote:
> >On Mon, Jul 08, 2019 at 04:16:28PM -0700, Lucas De Marchi wrote:
> >> On TGL the port programming for combophy is very similar to ICL, so
> >> adapt the callers to possibly use the different register values.
> >>
> >> Cc: Vandita Kulkarni
> >> Cc: Rodrigo Vivi
> >> Signed-off-by: Lucas De Marchi
> >> ---
> >> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 24 +++
> >> drivers/gpu/drm/i915/i915_reg.h | 15
> >> 2 files changed, 34 insertions(+), 5 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> >> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> >> index ae1c552d7afb..330b42a1f54e 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> >> @@ -3113,8 +3113,13 @@ static bool icl_pll_get_hw_state(struct
> >> drm_i915_private *dev_priv,
> >>if (!(val & PLL_ENABLE))
> >>goto out;
> >>
> >> - hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
> >> - hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
> >> + if (INTEL_GEN(dev_priv) >= 12) {
> >> + hw_state->cfgcr0 = I915_READ(TGL_DPLL_CFGCR0(id));
> >> + hw_state->cfgcr1 = I915_READ(TGL_DPLL_CFGCR1(id));
> >> + } else {
> >> + hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
> >> + hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
> >> + }
> >>
> >>ret = true;
> >> out:
> >> @@ -3148,10 +3153,19 @@ static void icl_dpll_write(struct drm_i915_private
> >> *dev_priv,
> >> {
> >>struct intel_dpll_hw_state *hw_state = >state.hw_state;
> >>const enum intel_dpll_id id = pll->info->id;
> >> + i915_reg_t cfgcr0_reg, cfgcr1_reg;
> >> +
> >> + if (INTEL_GEN(dev_priv) >= 12) {
> >> + cfgcr0_reg = TGL_DPLL_CFGCR0(id);
> >> + cfgcr1_reg = TGL_DPLL_CFGCR1(id);
> >> + } else {
> >> + cfgcr0_reg = ICL_DPLL_CFGCR0(id);
> >> + cfgcr1_reg = ICL_DPLL_CFGCR1(id);
> >> + }
> >>
> >> - I915_WRITE(ICL_DPLL_CFGCR0(id), hw_state->cfgcr0);
> >> - I915_WRITE(ICL_DPLL_CFGCR1(id), hw_state->cfgcr1);
> >> - POSTING_READ(ICL_DPLL_CFGCR1(id));
> >> + I915_WRITE(cfgcr0_reg, hw_state->cfgcr0);
> >> + I915_WRITE(cfgcr1_reg, hw_state->cfgcr1);
> >> + POSTING_READ(cfgcr1_reg);
> >> }
> >>
> >> static void icl_mg_pll_write(struct drm_i915_private *dev_priv,
> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> >> b/drivers/gpu/drm/i915/i915_reg.h
> >> index fbcc7981c8c4..84c04ea67ec8 100644
> >> --- a/drivers/gpu/drm/i915/i915_reg.h
> >> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> @@ -242,6 +242,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> >> #define _MMIO_PIPE3(pipe, a, b, c)_MMIO(_PICK(pipe, a, b, c))
> >> #define _MMIO_PORT3(pipe, a, b, c)_MMIO(_PICK(pipe, a, b, c))
> >> #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
> >> +#define _MMIO_PLL3(pll, a, b, c) _MMIO(_PICK(pll, a, b, c))
> >>
> >> /*
> >> * Device info offset array based helpers for groups of registers with
> >> unevenly
> >> @@ -9958,6 +9959,20 @@ enum skl_power_gate {
> >> #define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll,
> >> _ICL_DPLL0_CFGCR1, \
> >> _ICL_DPLL1_CFGCR1)
> >>
> >> +#define _TGL_DPLL0_CFGCR0 0x164284
> >> +#define _TGL_DPLL1_CFGCR0 0x16428C
> >> +#define _TGL_TBTPLL_CFGCR00x16429C
> >
> >What about DPLL4?
>
> not all TGL skus have DPLL4. The ones that do (and were not tested
> here), are very different from what is done for EHL so we can't reuse
> the implementation. I will leave the DPLL4 on TGL for later, when it
> makes sense to add it.
Fair enough. Could maybe use a FIXME/TODO somewhere maybe?
Reviewed-by: Ville Syrjälä
>
> Lucas De Marchi
>
> >
> >In fact looks like the ICL counterparts are borked even for ehl DPLL4.
> >
> >> +#define TGL_DPLL_CFGCR0(pll) _MMIO_PLL3(pll,
> >> _TGL_DPLL0_CFGCR0, \
> >> +_TGL_DPLL1_CFGCR0, \
> >> +_TGL_TBTPLL_CFGCR0)
> >> +
> >> +#define _TGL_DPLL0_CFGCR1 0x164288
> >> +#define _TGL_DPLL1_CFGCR1 0x164290
> >> +#define _TGL_TBTPLL_CFGCR10x1642A0
> >> +#define TGL_DPLL_CFGCR1(pll) _MMIO_PLL3(pll,
> >> _TGL_DPLL0_CFGCR1, \
> >> + _TGL_DPLL1_CFGCR1, \
> >> + _TGL_TBTPLL_CFGCR1)
> >> +
> >> /* BXT display engine PLL */
> >> #define BXT_DE_PLL_CTL_MMIO(0x6d000)
> >> #define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} *
> >> 19.2MHz */
> >> --
> >> 2.21.0
> >
> >--
> >Ville Syrjälä
> >Intel
--
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Re: [Intel-gfx] [PATCH v2 17/25] drm/i915/tgl: select correct bit for port select
On Mon, Jul 08, 2019 at 04:16:21PM -0700, Lucas De Marchi wrote:
> From: Mahesh Kumar
>
> Bit definitions for port-select got changed for TRANS_CLK_SEL &
> TRANS_DDI_FUNC_CTL registers in TGL.
>
> Signed-off-by: Mahesh Kumar
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 48 +++-
> drivers/gpu/drm/i915/i915_reg.h | 5 +++
> 2 files changed, 43 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index e72cf0bb48a7..5125c31af6aa 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1771,7 +1771,10 @@ void intel_ddi_enable_transcoder_func(const struct
> intel_crtc_state *crtc_state)
>
> /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
> temp = TRANS_DDI_FUNC_ENABLE;
> - temp |= TRANS_DDI_SELECT_PORT(port);
> + if (INTEL_GEN(dev_priv) >= 12)
> + temp |= TGL_TRANS_DDI_SELECT_PORT(port);
> + else
> + temp |= TRANS_DDI_SELECT_PORT(port);
>
> switch (crtc_state->pipe_bpp) {
> case 18:
> @@ -1851,8 +1854,14 @@ void intel_ddi_disable_transcoder_func(const struct
> intel_crtc_state *crtc_state
> i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
> u32 val = I915_READ(reg);
>
> - val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK |
> TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
> - val |= TRANS_DDI_PORT_NONE;
> + if (INTEL_GEN(dev_priv) >= 12) {
> + val &= ~(TRANS_DDI_FUNC_ENABLE | TGL_TRANS_DDI_PORT_MASK |
> + TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
> + } else {
> + val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK |
> + TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
> + val |= TRANS_DDI_PORT_NONE;
A bit incosistent leaving the NONE thing here. Maybe just nuke that
entirely?
Patch is
Reviewed-by: Ville Syrjälä
> + }
> I915_WRITE(reg, val);
>
> if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
> @@ -2004,10 +2013,19 @@ static void intel_ddi_get_encoder_pipes(struct
> intel_encoder *encoder,
> mst_pipe_mask = 0;
> for_each_pipe(dev_priv, p) {
> enum transcoder cpu_transcoder = (enum transcoder)p;
> + unsigned int port_mask, ddi_select;
> +
> + if (INTEL_GEN(dev_priv) >= 12) {
> + port_mask = TGL_TRANS_DDI_PORT_MASK;
> + ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
> + } else {
> + port_mask = TRANS_DDI_PORT_MASK;
> + ddi_select = TRANS_DDI_SELECT_PORT(port);
> + }
>
> tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
>
> - if ((tmp & TRANS_DDI_PORT_MASK) != TRANS_DDI_SELECT_PORT(port))
> + if ((tmp & port_mask) != ddi_select)
> continue;
>
> if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
> @@ -2123,9 +2141,14 @@ void intel_ddi_enable_pipe_clock(const struct
> intel_crtc_state *crtc_state)
> enum port port = encoder->port;
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>
> - if (cpu_transcoder != TRANSCODER_EDP)
> - I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
> -TRANS_CLK_SEL_PORT(port));
> + if (cpu_transcoder != TRANSCODER_EDP) {
> + if (INTEL_GEN(dev_priv) >= 12)
> + I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
> +TGL_TRANS_CLK_SEL_PORT(port));
> + else
> + I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
> +TRANS_CLK_SEL_PORT(port));
> + }
> }
>
> void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
> @@ -2133,9 +2156,14 @@ void intel_ddi_disable_pipe_clock(const struct
> intel_crtc_state *crtc_state)
> struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>
> - if (cpu_transcoder != TRANSCODER_EDP)
> - I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
> -TRANS_CLK_SEL_DISABLED);
> + if (cpu_transcoder != TRANSCODER_EDP) {
> + if (INTEL_GEN(dev_priv) >= 12)
> + I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
> +TGL_TRANS_CLK_SEL_DISABLED);
> + else
> + I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
> +TRANS_CLK_SEL_DISABLED);
> + }
> }
>
> static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c554df69f289..ccfb95e2aa03 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@
Re: [Intel-gfx] [PATCH 12/12] drm/i915/uc: kill uc_to_i915
On Wed, 10 Jul 2019 02:54:37 +0200, Daniele Ceraolo Spurio
wrote:
Get rid of them to avoid more users being added while the guc code
transitions to use gt more than i915.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
---
Acked-by: Michal Wajdeczko
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 8
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 3 ++-
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 13 +++--
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 ++--
drivers/gpu/drm/i915/i915_drv.h| 10 --
8 files changed, 18 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 6b56f39072b1..83f2c197375f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -77,7 +77,7 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
void intel_guc_init_early(struct intel_guc *guc)
{
- struct drm_i915_private *i915 = guc_to_i915(guc);
+ struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
intel_guc_fw_init_early(guc);
intel_guc_ct_init_early(>ct);
@@ -204,7 +204,7 @@ static u32 guc_ctl_feature_flags(struct intel_guc
*guc)
{
u32 flags = 0;
- if (!USES_GUC_SUBMISSION(guc_to_i915(guc)))
+ if (!intel_uc_is_using_guc_submission(_to_gt(guc)->uc))
flags |= GUC_CTL_DISABLE_SCHEDULER;
return flags;
@@ -214,7 +214,7 @@ static u32 guc_ctl_ctxinfo_flags(struct intel_guc
*guc)
{
u32 flags = 0;
- if (USES_GUC_SUBMISSION(guc_to_i915(guc))) {
+ if (intel_uc_is_using_guc_submission(_to_gt(guc)->uc)) {
u32 ctxnum, base;
base = intel_guc_ggtt_offset(guc, guc->stage_desc_pool);
@@ -414,7 +414,7 @@ int intel_guc_to_host_process_recv_msg(struct
intel_guc *guc,
int intel_guc_sample_forcewake(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915;
u32 action[2];
action[0] = INTEL_GUC_ACTION_SAMPLE_FORCEWAKE;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 69859d1e047f..a0da80241f22 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -22,6 +22,7 @@
*
*/
+#include "gt/intel_gt.h"
#include "intel_guc_ads.h"
#include "intel_uc.h"
#include "i915_drv.h"
@@ -85,7 +86,7 @@ struct __guc_ads_blob {
static void __guc_ads_init(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915;
struct __guc_ads_blob *blob = guc->ads_blob;
const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE +
LR_HW_CONTEXT_SIZE;
u32 base;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
index 98305e3fd42c..3dfa40fdbe99 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
@@ -76,7 +76,7 @@ MODULE_FIRMWARE(ICL_GUC_FIRMWARE_PATH);
static void guc_fw_select(struct intel_uc_fw *guc_fw)
{
struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
- struct drm_i915_private *i915 = guc_to_i915(guc);
+ struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
index 0355724ee997..52f814704d8e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
@@ -24,6 +24,7 @@
#include
+#include "gt/intel_gt.h"
#include "intel_guc_log.h"
#include "i915_drv.h"
@@ -215,7 +216,7 @@ static bool guc_check_log_buf_overflow(struct
intel_guc_log *log,
log->stats[type].sampled_overflow += 16;
}
- dev_notice_ratelimited(guc_to_i915(log_to_guc(log))->drm.dev,
+
dev_notice_ratelimited(guc_to_gt(log_to_guc(log))->i915->drm.dev,
"GuC log buffer overflow\n");
}
@@ -389,7 +390,7 @@ void intel_guc_log_init_early(struct intel_guc_log
*log)
static int guc_log_relay_create(struct intel_guc_log *log)
{
struct intel_guc *guc = log_to_guc(log);
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915;
struct rchan *guc_log_relay_chan;
size_t n_subbufs, subbuf_size;
int ret;
@@ -435,7 +436,7 @@ static void guc_log_relay_destroy(struct
intel_guc_log *log)
static void guc_log_capture_logs(struct intel_guc_log *log)
{
struct intel_guc *guc =
Re: [Intel-gfx] [PATCH 10/12] drm/i915/uc: prefer intel_gt over i915 in GuC/HuC paths
On Wed, 10 Jul 2019 02:54:35 +0200, Daniele Ceraolo Spurio
wrote:
With our HW interface logic moving from i915 to gt and with GuC and HuC
being part of the gt HW, it makes sense to use the intel_gt structure
instead of i915 as our reference object in GuC/HuC paths.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
---
drivers/gpu/drm/i915/gt/intel_gt.h| 10 +++
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 52 ++--
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 81 ++-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 43 +-
drivers/gpu/drm/i915/gt/uc/intel_huc.c| 22 ++---
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 4 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 8 +-
drivers/gpu/drm/i915/i915_gem_gtt.h | 4 +-
9 files changed, 120 insertions(+), 108 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
b/drivers/gpu/drm/i915/gt/intel_gt.h
index 880be05a3f4a..e182509d44ba 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -16,6 +16,16 @@ static inline struct intel_gt *uc_to_gt(struct
intel_uc *uc)
return container_of(uc, struct intel_gt, uc);
}
+static inline struct intel_gt *guc_to_gt(struct intel_guc *guc)
+{
+ return container_of(guc, struct intel_gt, uc.guc);
+}
+
+static inline struct intel_gt *huc_to_gt(struct intel_huc *huc)
+{
+ return container_of(huc, struct intel_gt, uc.huc);
+}
+
void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private
*i915);
void intel_gt_init_hw(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 4173b35bf104..6b56f39072b1 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -22,6 +22,7 @@
*
*/
+#include "gt/intel_gt.h"
#include "intel_guc.h"
#include "intel_guc_ads.h"
#include "intel_guc_submission.h"
@@ -29,16 +30,16 @@
static void gen8_guc_raise_irq(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct intel_gt *gt = guc_to_gt(guc);
- I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
+ intel_uncore_write(gt->uncore, GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
}
static void gen11_guc_raise_irq(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct intel_gt *gt = guc_to_gt(guc);
- I915_WRITE(GEN11_GUC_HOST_INTERRUPT, 0);
+ intel_uncore_write(gt->uncore, GEN11_GUC_HOST_INTERRUPT, 0);
}
static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
@@ -52,11 +53,11 @@ static inline i915_reg_t guc_send_reg(struct
intel_guc *guc, u32 i)
void intel_guc_init_send_regs(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct intel_gt *gt = guc_to_gt(guc);
enum forcewake_domains fw_domains = 0;
unsigned int i;
- if (INTEL_GEN(dev_priv) >= 11) {
+ if (INTEL_GEN(gt->i915) >= 11) {
guc->send_regs.base =
i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0));
guc->send_regs.count = GEN11_SOFT_SCRATCH_COUNT;
@@ -67,7 +68,7 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
}
for (i = 0; i < guc->send_regs.count; i++) {
- fw_domains |= intel_uncore_forcewake_for_reg(_priv->uncore,
+ fw_domains |= intel_uncore_forcewake_for_reg(gt->uncore,
guc_send_reg(guc, i),
FW_REG_READ | FW_REG_WRITE);
}
@@ -127,7 +128,7 @@ static void guc_shared_data_destroy(struct intel_guc
*guc)
int intel_guc_init(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct intel_gt *gt = guc_to_gt(guc);
int ret;
ret = intel_uc_fw_init(>fw);
@@ -153,7 +154,7 @@ int intel_guc_init(struct intel_guc *guc)
goto err_ads;
/* We need to notify the guc whenever we change the GGTT */
- i915_ggtt_enable_guc(dev_priv);
+ i915_ggtt_enable_guc(gt->ggtt);
return 0;
@@ -172,9 +173,9 @@ int intel_guc_init(struct intel_guc *guc)
void intel_guc_fini(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct intel_gt *gt = guc_to_gt(guc);
- i915_ggtt_disable_guc(dev_priv);
+ i915_ggtt_disable_guc(gt->ggtt);
intel_guc_ct_fini(>ct);
@@ -282,7 +283,7 @@ static u32 guc_ctl_ads_flags(struct intel_guc *guc)
*/
void intel_guc_init_params(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
u32 params[GUC_CTL_MAX_DWORDS];
int i;
@@ -302,14 +303,14 @@ void intel_guc_init_params(struct intel_guc *guc)
Re: [Intel-gfx] [PATCH v2 4/4] drm/i915: Add modular FIA
On Mon, Jul 08, 2019 at 10:28:15AM -0700, Lucas De Marchi wrote:
> From: Anusha Srivatsa
>
> Some platforms may have Modular FIA. If Modular FIA is used in the SOC,
> then Display Driver will access the additional instances of
> FIA based on pre-assigned offset in GTTMADDR space.
>
> Each Modular FIA instance has its own IOSF Sideband Port ID
> and it houses only 2 Type-C Port. In SOC that has more than
> two Type-C Ports, there are multiple instances of Modular FIA.
> Gunit will need to use different destination ID when it access
> different pair of Type-C Port.
>
> The DFLEXDPSP register has Modular FIA bit starting on Tiger Lake. If
> Modular FIA is used in the SOC, this register bit exists in all the
> instances of Modular FIA. IOM FW is required to program only the MF bit
> in first FIA instance that houses the Type-C Port 0 and Port 1, for
> Display Driver to read from.
>
> v2 (Lucas):
> - Move all accesses to FIA to be contained in intel_tc.c, along with
> display_fia that is now called tc_phy_fia
> - Save the fia instance number on intel_digital_port, so we don't have
> to query if modular FIA is used on every access
> v3 (Lucas):
> - Make function static
>
> Cc: Jani Nikula
> Signed-off-by: Anusha Srivatsa
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_tc.c | 49
> drivers/gpu/drm/i915/i915_reg.h | 13 +--
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> 4 files changed, 52 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
> b/drivers/gpu/drm/i915/display/intel_tc.c
> index f44ee4bfe7c8..671261b55d11 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -8,6 +8,12 @@
> #include "intel_dp_mst.h"
> #include "intel_tc.h"
>
> +enum phy_fia {
> + FIA1,
> + FIA2,
> + FIA3,
> +};
> +
> static const char *tc_port_mode_name(enum tc_port_mode mode)
> {
> static const char * const names[] = {
> @@ -22,6 +28,24 @@ static const char *tc_port_mode_name(enum tc_port_mode
> mode)
> return names[mode];
> }
>
> +static bool has_modular_fia(struct drm_i915_private *i915)
> +{
> + if (!INTEL_INFO(i915)->display.has_modular_fia)
> + return false;
> +
> + return intel_uncore_read(>uncore,
> + PORT_TX_DFLEXDPSP(FIA1)) & MODULAR_FIA_MASK;
> +}
> +
> +static enum phy_fia tc_port_to_fia(struct drm_i915_private *i915,
> +enum tc_port tc_port)
> +{
> + if (!has_modular_fia(i915))
> + return FIA1;
> +
> + return tc_port / 2;
> +}
> +
> u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
> {
> struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> @@ -29,7 +53,8 @@ u32 intel_tc_port_get_lane_mask(struct intel_digital_port
> *dig_port)
> struct intel_uncore *uncore = >uncore;
> u32 lane_mask;
>
> - lane_mask = intel_uncore_read(uncore, PORT_TX_DFLEXDPSP);
> + lane_mask = intel_uncore_read(uncore,
> + PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
>
> WARN_ON(lane_mask == 0x);
>
> @@ -78,7 +103,8 @@ void intel_tc_port_set_fia_lane_count(struct
> intel_digital_port *dig_port,
>
> WARN_ON(lane_reversal && dig_port->tc_mode != TC_PORT_LEGACY);
>
> - val = intel_uncore_read(uncore, PORT_TX_DFLEXDPMLE1);
> + val = intel_uncore_read(uncore,
> + PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia));
> val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
>
> switch (required_lanes) {
> @@ -97,7 +123,8 @@ void intel_tc_port_set_fia_lane_count(struct
> intel_digital_port *dig_port,
> MISSING_CASE(required_lanes);
> }
>
> - intel_uncore_write(uncore, PORT_TX_DFLEXDPMLE1, val);
> + intel_uncore_write(uncore,
> +PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia), val);
> }
>
> static void tc_port_fixup_legacy_flag(struct intel_digital_port *dig_port,
> @@ -129,7 +156,8 @@ static u32 tc_port_live_status_mask(struct
> intel_digital_port *dig_port)
> u32 mask = 0;
> u32 val;
>
> - val = intel_uncore_read(uncore, PORT_TX_DFLEXDPSP);
> + val = intel_uncore_read(uncore,
> + PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
>
> if (val == 0x) {
> DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, nothing connected\n",
> @@ -159,7 +187,8 @@ static bool icl_tc_phy_status_complete(struct
> intel_digital_port *dig_port)
> struct intel_uncore *uncore = >uncore;
> u32 val;
>
> - val = intel_uncore_read(uncore, PORT_TX_DFLEXDPPMS);
> + val = intel_uncore_read(uncore,
> + PORT_TX_DFLEXDPPMS(dig_port->tc_phy_fia));
> if (val == 0x) {
> DRM_DEBUG_KMS("Port
Re: [Intel-gfx] [PATCH 09/12] drm/i915/uc: Move intel functions to intel_uc
On Wed, 10 Jul 2019 02:54:34 +0200, Daniele Ceraolo Spurio
wrote:
All the intel_uc_* can now be moved to work on the intel_uc structure
for better encapsulation of uc-related actions.
Note: I've introduced uc_to_gt instead of uc_to_i915 because the aim is
to move everything to be gt-focused in the medium term, so we would've
had to replace it soon anyway.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 6 +-
drivers/gpu/drm/i915/gt/intel_gt.h | 5 +
drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 184 -
drivers/gpu/drm/i915/gt/uc/intel_uc.h | 34 ++---
drivers/gpu/drm/i915/i915_drv.c| 14 +-
drivers/gpu/drm/i915/i915_drv.h| 6 +-
drivers/gpu/drm/i915/i915_gem.c| 18 +--
8 files changed, 137 insertions(+), 132 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
index 4d774376f5b8..3c674c952a78 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
@@ -173,7 +173,7 @@ void i915_gem_suspend(struct drm_i915_private *i915)
i915_gem_drain_freed_objects(i915);
- intel_uc_suspend(i915);
+ intel_uc_suspend(>gt.uc);
}
static struct drm_i915_gem_object *first_mm_object(struct list_head
*list)
@@ -238,7 +238,7 @@ void i915_gem_suspend_late(struct drm_i915_private
*i915)
}
spin_unlock_irqrestore(>mm.obj_lock, flags);
- intel_uc_sanitize(i915);
+ intel_uc_sanitize(>gt.uc);
i915_gem_sanitize(i915);
}
@@ -265,7 +265,7 @@ void i915_gem_resume(struct drm_i915_private *i915)
if (intel_gt_resume(>gt))
goto err_wedged;
- intel_uc_resume(i915);
+ intel_uc_resume(>gt.uc);
/* Always reload a context for powersaving. */
if (!i915_gem_load_power_context(i915))
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
b/drivers/gpu/drm/i915/gt/intel_gt.h
index 1093dcf36f63..880be05a3f4a 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -11,6 +11,11 @@
struct drm_i915_private;
+static inline struct intel_gt *uc_to_gt(struct intel_uc *uc)
+{
+ return container_of(uc, struct intel_gt, uc);
+}
+
void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private
*i915);
void intel_gt_init_hw(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
b/drivers/gpu/drm/i915/gt/intel_reset.c
index ccedea636ba3..be23f4557111 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -720,7 +720,7 @@ static intel_engine_mask_t reset_prepare(struct
drm_i915_private *i915)
reset_prepare_engine(engine);
}
- intel_uc_reset_prepare(i915);
+ intel_uc_reset_prepare(>gt.uc);
return awake;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index e2080da2e1e4..2062e7ff05e8 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -22,19 +22,22 @@
*
*/
+#include "gt/intel_gt.h"
#include "gt/intel_reset.h"
-#include "intel_uc.h"
#include "intel_guc.h"
we don't need this, it's included by "intel_uc.h"
#include "intel_guc_ads.h"
#include "intel_guc_submission.h"
+#include "intel_uc.h"
+
#include "i915_drv.h"
static void guc_free_load_err_log(struct intel_guc *guc);
/* Reset GuC providing us with fresh state for both GuC and HuC.
*/
-static int __intel_uc_reset_hw(struct drm_i915_private *dev_priv)
+static int __intel_uc_reset_hw(struct intel_uc *uc)
{
+ struct drm_i915_private *dev_priv = uc_to_gt(uc)->i915;
int ret;
u32 guc_status;
@@ -52,10 +55,10 @@ static int __intel_uc_reset_hw(struct
drm_i915_private *dev_priv)
return ret;
}
-static int __get_platform_enable_guc(struct drm_i915_private *i915)
+static int __get_platform_enable_guc(struct intel_uc *uc)
{
- struct intel_uc_fw *guc_fw = >gt.uc.guc.fw;
- struct intel_uc_fw *huc_fw = >gt.uc.huc.fw;
+ struct intel_uc_fw *guc_fw = >guc.fw;
+ struct intel_uc_fw *huc_fw = >huc.fw;
int enable_guc = 0;
/* Default is to use HuC if we know GuC and HuC firmwares */
@@ -67,12 +70,11 @@ static int __get_platform_enable_guc(struct
drm_i915_private *i915)
return enable_guc;
}
-static int __get_default_guc_log_level(struct drm_i915_private *i915)
+static int __get_default_guc_log_level(struct intel_uc *uc)
{
int guc_log_level;
- if (!intel_uc_fw_supported(>gt.uc.guc.fw) ||
- !intel_uc_is_using_guc(i915))
+ if (!intel_uc_fw_supported(>guc.fw) || !intel_uc_is_using_guc(uc))
guc_log_level = GUC_LOG_LEVEL_DISABLED;
else if (IS_ENABLED(CONFIG_DRM_I915_DEBUG) ||
IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
@@ -87,7 +89,7 @@ static int
Re: [Intel-gfx] [PATCH 08/12] drm/i915/uc: move GuC/HuC inside intel_gt under a new intel_uc
On Wed, 10 Jul 2019 02:54:33 +0200, Daniele Ceraolo Spurio
wrote:
Being part of the GT HW, it make sense to keep the guc/huc structures
inside the GT structure. To help with the encapsulation work done by the
following patches, both structures are placed inside a new intel_uc
container. Although this results in code with ugly nested dereferences
(i915->gt.uc.guc...), it saves us the extra work required in moving
the structures twice (i915 -> gt -> uc). The following patches will
reduce the number of places where we try to access the guc/huc
structures directly from i915 and reduce the ugliness.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_gt_types.h | 4 ++
drivers/gpu/drm/i915/gt/intel_reset.c | 6 +--
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_huc.c| 4 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 52 +--
drivers/gpu/drm/i915/gt/uc/intel_uc.h | 5 ++
drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 4 +-
drivers/gpu/drm/i915/i915_debugfs.c | 26 +-
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 7 +--
drivers/gpu/drm/i915/i915_gpu_error.c | 11 ++--
drivers/gpu/drm/i915/i915_irq.c | 6 +--
drivers/gpu/drm/i915/intel_wopcm.c| 4 +-
13 files changed, 69 insertions(+), 64 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 3563ce970102..b711252ff427 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -13,6 +13,8 @@
#include
#include
+#include "uc/intel_uc.h"
+
#include "i915_vma.h"
#include "intel_wakeref.h"
@@ -25,6 +27,8 @@ struct intel_gt {
struct intel_uncore *uncore;
struct i915_ggtt *ggtt;
+ struct intel_uc uc;
+
struct intel_gt_timelines {
struct mutex mutex; /* protects list */
struct list_head active_list;
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
b/drivers/gpu/drm/i915/gt/intel_reset.c
index 9abfa28c3020..ccedea636ba3 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -1109,14 +1109,14 @@ int i915_reset_engine(struct intel_engine_cs
*engine, const char *msg)
"Resetting %s for %s\n", engine->name, msg);
error->reset_engine_count[engine->id]++;
- if (!engine->i915->guc.execbuf_client)
+ if (!engine->gt->uc.guc.execbuf_client)
ret = intel_gt_reset_engine(engine->i915, engine);
else
- ret = intel_guc_reset_engine(>i915->guc, engine);
+ ret = intel_guc_reset_engine(>gt->uc.guc, engine);
if (ret) {
/* If we fail here, we expect to fallback to a global reset */
DRM_DEBUG_DRIVER("%sFailed to reset %s, ret=%d\n",
-engine->i915->guc.execbuf_client ? "GuC " : "",
+engine->gt->uc.guc.execbuf_client ? "GuC " :
"",
maybe instead of doing 3x same deref, just add at the start:
struct intel_guc *guc = >gt->uc.guc;
engine->name, ret);
goto out;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index f015f7dee453..23906228b9b4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -509,7 +509,7 @@ static void guc_submit(struct intel_engine_cs
*engine,
struct i915_request **out,
struct i915_request **end)
{
- struct intel_guc *guc = >i915->guc;
+ struct intel_guc *guc = >gt->uc.guc;
struct intel_guc_client *client = guc->execbuf_client;
spin_lock(>wq_lock);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 2a41ee89a16d..581c9c3d4fc0 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -47,7 +47,7 @@ void intel_huc_init_early(struct intel_huc *huc)
static int intel_huc_rsa_data_create(struct intel_huc *huc)
{
struct drm_i915_private *i915 = huc_to_i915(huc);
- struct intel_guc *guc = >guc;
+ struct intel_guc *guc = >gt.uc.guc;
maybe we can avoid i915/gt dance with:
struct intel_guc *guc = huc_to_uc(huc)->guc;
struct i915_vma *vma;
void *vaddr;
@@ -113,7 +113,7 @@ void intel_huc_fini(struct intel_huc *huc)
int intel_huc_auth(struct intel_huc *huc)
{
struct drm_i915_private *i915 = huc_to_i915(huc);
- struct intel_guc *guc = >guc;
+ struct intel_guc *guc = >gt.uc.guc;
int ret;
if (huc->fw.load_status !=
Re: [Intel-gfx] [PATCH 07/12] drm/i915/uc: move GuC and HuC files under gt/uc/
On Wed, 10 Jul 2019 02:54:32 +0200, Daniele Ceraolo Spurio wrote: Both microcontrollers are part of the GT HW and are closely related to GT operations. To keep all the files cleanly together, they've been placed in their own subdir inside the gt/ folder Signed-off-by: Daniele Ceraolo Spurio Cc: Michal Wajdeczko Cc: Chris Wilson --- Acked-by: Michal Wajdeczko with some nits below diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 5266dbeab01f..524516251a40 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -139,16 +139,17 @@ i915-y += \ intel_wopcm.o # general-purpose microcontroller (GuC) support -i915-y += intel_uc.o \ - intel_uc_fw.o \ - intel_guc.o \ - intel_guc_ads.o \ - intel_guc_ct.o \ - intel_guc_fw.o \ - intel_guc_log.o \ - intel_guc_submission.o \ - intel_huc.o \ - intel_huc_fw.o +obj-y += gt/uc/ +i915-y += gt/uc/intel_uc.o \ nit: can we put first file on separate line as well, so i915-y += \ + gt/uc/intel_uc_fw.o \ + gt/uc/intel_guc.o \ + gt/uc/intel_guc_ads.o \ + gt/uc/intel_guc_ct.o \ + gt/uc/intel_guc_fw.o \ + gt/uc/intel_guc_log.o \ + gt/uc/intel_guc_submission.o \ + gt/uc/intel_huc.o \ + gt/uc/intel_huc_fw.o and iirc bkm is to order all files by name, so uc* should be last ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/guc: Turn on GuC/HuC auto mode
>-Original Message- >From: Wajdeczko, Michal >Sent: Wednesday, July 10, 2019 7:27 AM >To: intel-gfx@lists.freedesktop.org; Joonas Lahtinen >; Srivatsa, Anusha >; Ye, Tony >Cc: Ceraolo Spurio, Daniele ; Chris Wilson > >Subject: Re: [PATCH 2/2] drm/i915/guc: Turn on GuC/HuC auto mode > >On Tue, 09 Jul 2019 16:17:02 +0200, Joonas Lahtinen > wrote: > >> Better subject would be: "Enable HuC (through GuC) on supported >> platforms" > >Such subject sounds better, but on one hand it does not reflect real code >change >(since we are not explicitly enabling HuC, but instead we are just letting the >driver >enable GuC/HuC to whatever mode it decides), but on other hand this is what >actual outcome of the change is (as i915 currently enables GuC loading with HuC >authentication on every platform where corresponding firmwares are >defined/available, and nothing more). > >Please confirm if you still opt-in to use your subject. > >> >> Quoting Michal Wajdeczko (2019-07-03 14:36:40) >>> GuC firmware is now mature, so let it run by default. >> >> That's bit of a misleading statement (in more than one way). > >It's mature enough to perform HuC authentication, and we don't expect more >from it ;) > >> >> "Enable loading HuC firmware (through GuC) to unlock advanced video >> codecs on supported platforms. >> >> GuC firmware is required to authenticate the HuC firmware, which is a >> requirement for it to operate." > >To some extend this duplicates existing "DOC: HuC Firmware" >Do we need to repeat that again here? > >> >> Has the most recent firmware been merged to linux-firmware and is it >> present in our CI systems? > >My understanding is: No and Yes. >Maybe Anusha can provide more details here. Waiting on the firmware to get merged to linux-firmware. Sent the PR. The latest firmware is however available on our CI. Anusha >> >> It would also be good to list what kind of tests have been run to >> ensure that there are no regressions, > >I'm afraid on IGT level we don't have HuC tests. >But media team was using modparam override to force GuC/HuC for a while, >Tony do you have such test list/results handy? > >> and which platforms >> this change affects. > >This change affects all platforms where we have GuC/HuC firmwares defined, so: >SKL, BXT, KBL, CFL, ICL. > >Note that we'll still have possibility to tweak that inside driver, as auto >mode is >just moving responsibility what can be enabled from the user to the i915. > >> >> Regards, Joonas >> >>> Note that today GuC is only used for HuC authentication. >>> >>> Signed-off-by: Michal Wajdeczko >>> Cc: Daniele Ceraolo Spurio >>> Cc: Joonas Lahtinen >>> Cc: Chris Wilson >>> --- >>> drivers/gpu/drm/i915/i915_params.h | 2 +- >>> 1 file changed, 1 insertion(+), 1 deletion(-) >>> >>> diff --git a/drivers/gpu/drm/i915/i915_params.h >>> b/drivers/gpu/drm/i915/i915_params.h >>> index d29ade3b7de6..5736c55694fe 100644 >>> --- a/drivers/gpu/drm/i915/i915_params.h >>> +++ b/drivers/gpu/drm/i915/i915_params.h >>> @@ -54,7 +54,7 @@ struct drm_printer; >>> param(int, disable_power_well, -1) \ >>> param(int, enable_ips, 1) \ >>> param(int, invert_brightness, 0) \ >>> - param(int, enable_guc, 0) \ >>> + param(int, enable_guc, -1) \ >>> param(int, guc_log_level, -1) \ >>> param(char *, guc_firmware_path, NULL) \ >>> param(char *, huc_firmware_path, NULL) \ >>> -- >>> 2.19.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] screen freeze with 5.2-rc6 Dell XPS-13 skylake i915
On Wed, 2019-07-10 at 18:45 +0200, Paul Bolle wrote: > James Bottomley schreef op wo 10-07-2019 om 09:32 [-0700]: > > You seem to be getting it to happen much more often than I can. > > Last > > night, on the below pull request it took me a good hour to see the > > freeze. > > Yes. Sometimes within a minute of resuming. Typing stuff into > evolution seems to help with triggering this. It's all a bit > mysterious, but this message alone frooze my laptop a few times. > Seriously! > > > Sure, my current testing indicates it's somewhere inside this pull > > request: > > > > Merge: 89c3b37af87e eb85d03e01c3 > > Author: Linus Torvalds > > Date: Wed May 8 21:35:19 2019 -0700 > > > > Merge tag 'drm-next-2019-05-09' of > > git://anongit.freedesktop.org/drm/drm > > > > Pull drm updates from Dave Airlie: > > Lazy question: how does one determine the first and last commit > inside a merge request? Can I simply do > good a2d635decbfa9c1e4ae15cb05b68b2559f7f827c^ > bada2d635decbfa9c1e4ae15cb05b68b2559f7f827c > > for git bisect? I think so. I actually did bad a2d635decbfa9c1e4ae15cb05b68b2559f7f827c good89c3b37af87ec183b666d83428cb28cc421671a6 But I think ^ steps down in the main branch. Note, I've only done a couple of hours run on what I think is the good commit ... and actually I'd already marked a2d635decbfa9c1e4ae15cb05b68b2559f7f827c as good until the screen froze just after I'd built the new bisect kernel, so there's still some chance 89c3b37af87ec183b666d83428cb28cc421671a6 is bad. > > So I was about to test out the i915 changes in that but since my > > laptop is what I use for daily work, it's a bit hard (can't freeze > > up on video calls for instance). > > I usually use one of the ThinkPads from my embarrassing pile of > outdated hardware to do nasty bisects, but I'm not about to loose any > income if my much appreciated XPS 13 is out of order for a while. I can get back to it this afternoon, when I'm done with the meeting requirements and doing other dev stuff. James ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 07/11] drm/i915/gtt: Use NULL to encode scratch shadow entries
Quoting Mika Kuoppala (2019-07-10 17:21:15) > Chris Wilson writes: > > + pd = alloc_pd(vm); > > + if (IS_ERR(pd)) > > return pd; > > - } > > - > > - /* 3lvl */ > > - pd = __alloc_pd(); > > - if (!pd) > > - return ERR_PTR(-ENOMEM); > > - > > - pd->entry[GEN8_3LVL_PDPES] = NULL; > > Ok you dont like the sentry. Perhaps you could write > a few soothing words how noisily we crash if we > run long on this runway. If the tower sees and > sends firetrucks, it is fine. It's a tight allocation (or becomes one a patch or two down); you have to enable slab_debug to see fireworks in the redzone. Or kasan to detect the out-of-bounds write. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915: Copy name string into ring buffer for intel_update/disable_plane tracepoints
From: "Steven Rostedt (VMware)"
Currently the intel_update_plane and intel_disable_plane tracepoints record
the address of plane->name in the ring buffer, and then when reading the
ring buffer uses %s to get the name. The issue with this, is that those two
events can be minutes, hours or even days apart. It is very dangerous to
dereference a string pointer without knowing if it still exists or not.
The proper way to handle this is to use the __string() macro in the
tracepoint which will save the string into the ring buffer at the time of
recording. Then there's no worries if the original string still exists in
memory when the ring buffer is read.
Signed-off-by: Steven Rostedt (VMware)
[vsyrjala: Rebase on top of drm-tip]
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_trace.h | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_trace.h
b/drivers/gpu/drm/i915/i915_trace.h
index cce426b23a24..da18b8d6b80c 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -293,16 +293,16 @@ TRACE_EVENT(intel_update_plane,
TP_STRUCT__entry(
__field(enum pipe, pipe)
-__field(const char *, name)
__field(u32, frame)
__field(u32, scanline)
__array(int, src, 4)
__array(int, dst, 4)
+__string(name, plane->name)
),
TP_fast_assign(
+ __assign_str(name, plane->name);
__entry->pipe = crtc->pipe;
- __entry->name = plane->name;
__entry->frame = intel_crtc_get_vblank_counter(crtc);
__entry->scanline = intel_get_crtc_scanline(crtc);
memcpy(__entry->src, >state->src,
sizeof(__entry->src));
@@ -310,7 +310,7 @@ TRACE_EVENT(intel_update_plane,
),
TP_printk("pipe %c, plane %s, frame=%u, scanline=%u, "
DRM_RECT_FP_FMT " -> " DRM_RECT_FMT,
- pipe_name(__entry->pipe), __entry->name,
+ pipe_name(__entry->pipe), __get_str(name),
__entry->frame, __entry->scanline,
DRM_RECT_FP_ARG((const struct drm_rect *)__entry->src),
DRM_RECT_ARG((const struct drm_rect *)__entry->dst))
@@ -322,20 +322,20 @@ TRACE_EVENT(intel_disable_plane,
TP_STRUCT__entry(
__field(enum pipe, pipe)
-__field(const char *, name)
__field(u32, frame)
__field(u32, scanline)
+__string(name, plane->name)
),
TP_fast_assign(
+ __assign_str(name, plane->name);
__entry->pipe = crtc->pipe;
- __entry->name = plane->name;
__entry->frame = intel_crtc_get_vblank_counter(crtc);
__entry->scanline = intel_get_crtc_scanline(crtc);
),
TP_printk("pipe %c, plane %s, frame=%u, scanline=%u",
- pipe_name(__entry->pipe), __entry->name,
+ pipe_name(__entry->pipe), __get_str(name),
__entry->frame, __entry->scanline)
);
--
2.21.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 06/12] drm/i915/guc: unify guc irq handling
On Wed, 10 Jul 2019 02:54:31 +0200, Daniele Ceraolo Spurio
wrote:
The 16-bit guc irq vector is unchanged across gens, the only thing that
moved is its position (from the upper 16 bits of the PM regs to its own
register). Instead of duplicating all defines and functions to handle
the 2 different positions, we can work on the vector and shift it as
appropriate. While at it, update the handler to work on intel_guc.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
---
drivers/gpu/drm/i915/i915_irq.c | 24 -
drivers/gpu/drm/i915/i915_reg.h | 10 -
drivers/gpu/drm/i915/intel_guc_reg.h | 32 ++--
3 files changed, 25 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c
b/drivers/gpu/drm/i915/i915_irq.c
index 831d185c07d2..42d6d8bfac70 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -264,7 +264,7 @@ static void gen2_irq_init(struct intel_uncore
*uncore,
gen2_irq_init((uncore), imr_val, ier_val)
static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32
pm_iir);
-static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32
pm_iir);
+static void guc_irq_handler(struct intel_guc *guc, u16 guc_iir);
/* For display hotplug interrupt */
static inline void
@@ -658,8 +658,7 @@ void gen11_enable_guc_interrupts(struct intel_guc
*guc)
spin_lock_irq(_priv->irq_lock);
if (!guc->interrupts.enabled) {
- u32 events = REG_FIELD_PREP(ENGINE1_MASK,
- GEN11_GUC_INTR_GUC2HOST);
+ u32 events = REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST);
WARN_ON_ONCE(gen11_reset_one_iir(_priv->gt, 0, GEN11_GUC));
I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, events);
@@ -1656,7 +1655,7 @@ static void gen8_gt_irq_handler(struct
drm_i915_private *i915,
if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
gen6_rps_irq_handler(i915, gt_iir[2]);
- gen9_guc_irq_handler(i915, gt_iir[2]);
+ guc_irq_handler(>guc, gt_iir[2] >> 16);
}
}
@@ -1955,16 +1954,10 @@ static void gen6_rps_irq_handler(struct
drm_i915_private *dev_priv, u32 pm_iir)
DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
}
-static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32
gt_iir)
+static void guc_irq_handler(struct intel_guc *guc, u16 iir)
maybe it's the good time to move this handler out to intel_guc.c ?
{
- if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT)
- intel_guc_to_host_event_handler(_priv->guc);
-}
-
-static void gen11_guc_irq_handler(struct drm_i915_private *i915, u16
iir)
-{
- if (iir & GEN11_GUC_INTR_GUC2HOST)
- intel_guc_to_host_event_handler(>guc);
+ if (iir & GUC_INTR_GUC2HOST)
+ intel_guc_to_host_event_handler(guc);
}
static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
@@ -3092,7 +3085,7 @@ gen11_other_irq_handler(struct intel_gt *gt, const
u8 instance,
struct drm_i915_private *i915 = gt->i915;
if (instance == OTHER_GUC_INSTANCE)
- return gen11_guc_irq_handler(i915, iir);
+ return guc_irq_handler(>guc, iir);
if (instance == OTHER_GTPM_INSTANCE)
return gen11_rps_irq_handler(gt, iir);
@@ -4764,8 +4757,9 @@ void intel_irq_init(struct drm_i915_private
*dev_priv)
for (i = 0; i < MAX_L3_SLICES; ++i)
dev_priv->l3_parity.remap_info[i] = NULL;
+ /* pre-gen11 the guc irqs bits are in the upper 16 bits of the pm reg
*/
s/gen11/Gen11
s/guc/GuC
if (HAS_GUC_SCHED(dev_priv) && INTEL_GEN(dev_priv) < 11)
- dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT;
+ dev_priv->pm_guc_events = GUC_INTR_GUC2HOST << 16;
maybe we should add definition for this mask in PM register
#define GEN8_PM_IIR_GUC_MASK 0x
and then
dev_priv->pm_guc_events = REG_FIELD_PREP(GEN8_PM_IIR_GUC_MASK,
GUC_INTR_GUC2HOST)
and in gen8_gt_irq_handler() earlier above
guc_irq_handler(>guc, REG_FIELD_GET(GEN8_PM_IIR_GUC_MASK,
gt_iir[2]));
/* Let's track the enabled rps events */
if (IS_VALLEYVIEW(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_reg.h
b/drivers/gpu/drm/i915/i915_reg.h
index 5898f59e3dd7..4dc31e488b80 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7342,16 +7342,6 @@ enum {
#define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
#define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
-#define GEN9_GUC_TO_HOST_INT_EVENT (1 << 31)
-#define GEN9_GUC_EXEC_ERROR_EVENT (1 << 30)
-#define GEN9_GUC_DISPLAY_EVENT (1 << 29)
-#define GEN9_GUC_SEMA_SIGNAL_EVENT (1 << 28)
Re: [Intel-gfx] [PATCH 04/12] drm/i915/uc: introduce intel_uc_fw_supported
On Wed, 10 Jul 2019 02:54:29 +0200, Daniele Ceraolo Spurio
wrote:
Instead of always checking in the device config is GuC and HuC are
s/is/if
supported or not, we can save the state in the uc_fw structure and
avoid going through i915 every time from the low-level uc management
code. while at it FIRMWARE_NONE has been renamed to better indicate that
s/while/While
we haven't started the fetch/load yet, but we might have already selected
a blob.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
---
drivers/gpu/drm/i915/intel_guc_fw.c | 6 +-
drivers/gpu/drm/i915/intel_huc_fw.c | 6 +-
drivers/gpu/drm/i915/intel_uc.c | 25
drivers/gpu/drm/i915/intel_uc_fw.c | 4 +++-
drivers/gpu/drm/i915/intel_uc_fw.h | 30 -
5 files changed, 51 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c
b/drivers/gpu/drm/i915/intel_guc_fw.c
index db1e0daca7db..ee95d4960c5c 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -79,8 +79,12 @@ static void guc_fw_select(struct intel_uc_fw *guc_fw)
GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);
- if (!HAS_GUC(i915))
+ if (!HAS_GUC(i915)) {
+ guc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_SUPPORTED;
return;
+ }
+
+ guc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_STARTED;
if (i915_modparams.guc_firmware_path) {
guc_fw->path = i915_modparams.guc_firmware_path;
diff --git a/drivers/gpu/drm/i915/intel_huc_fw.c
b/drivers/gpu/drm/i915/intel_huc_fw.c
index 05cbf8338f53..06e726ba9863 100644
--- a/drivers/gpu/drm/i915/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/intel_huc_fw.c
@@ -73,8 +73,12 @@ static void huc_fw_select(struct intel_uc_fw *huc_fw)
GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
- if (!HAS_HUC(dev_priv))
+ if (!HAS_HUC(dev_priv)) {
+ huc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_SUPPORTED;
return;
+ }
+
+ huc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_STARTED;
if (i915_modparams.huc_firmware_path) {
huc_fw->path = i915_modparams.huc_firmware_path;
diff --git a/drivers/gpu/drm/i915/intel_uc.c
b/drivers/gpu/drm/i915/intel_uc.c
index 789b0bccfb41..ef2a864b8990 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -71,7 +71,8 @@ static int __get_default_guc_log_level(struct
drm_i915_private *i915)
{
int guc_log_level;
- if (!HAS_GUC(i915) || !intel_uc_is_using_guc(i915))
+ if (!intel_uc_fw_supported(>guc.fw) ||
this goes too far, we should limit number of direct accesses to .fw
maybe we can have:
inline bool intel_uc_has_guc(i915)
{
return intel_guc_is_present(>guc);
}
inline bool intel_guc_is_present(guc)
{
return intel_uc_fw_is_defined(>fw);
}
+ !intel_uc_is_using_guc(i915))
guc_log_level = GUC_LOG_LEVEL_DISABLED;
else if (IS_ENABLED(CONFIG_DRM_I915_DEBUG) ||
IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
@@ -119,16 +120,16 @@ static void sanitize_options_early(struct
drm_i915_private *i915)
if (intel_uc_is_using_guc(i915) && !intel_uc_fw_is_selected(guc_fw)) {
DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
"enable_guc", i915_modparams.enable_guc,
-!HAS_GUC(i915) ? "no GuC hardware" :
- "no GuC firmware");
+!intel_uc_fw_supported(guc_fw) ?
+ "no GuC hardware" : "no GuC firmware");
}
/* Verify HuC firmware availability */
if (intel_uc_is_using_huc(i915) && !intel_uc_fw_is_selected(huc_fw)) {
DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
"enable_guc", i915_modparams.enable_guc,
-!HAS_HUC(i915) ? "no HuC hardware" :
- "no HuC firmware");
+!intel_uc_fw_supported(huc_fw) ?
+ "no HuC hardware" : "no HuC firmware");
}
/* XXX: GuC submission is unavailable for now */
@@ -148,8 +149,8 @@ static void sanitize_options_early(struct
drm_i915_private *i915)
if (i915_modparams.guc_log_level > 0 && !intel_uc_is_using_guc(i915)) {
DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
"guc_log_level", i915_modparams.guc_log_level,
-!HAS_GUC(i915) ? "no GuC hardware" :
- "GuC not enabled");
+!intel_uc_fw_supported(guc_fw) ?
+ "no GuC hardware" : "GuC not enabled");
i915_modparams.guc_log_level = 0;
}
@@ -376,7
Re: screen freeze with 5.2-rc6 Dell XPS-13 skylake i915
James Bottomley schreef op wo 10-07-2019 om 09:32 [-0700]: > You seem to be getting it to happen much more often than I can. Last > night, on the below pull request it took me a good hour to see the > freeze. Yes. Sometimes within a minute of resuming. Typing stuff into evolution seems to help with triggering this. It's all a bit mysterious, but this message alone frooze my laptop a few times. Seriously! > Sure, my current testing indicates it's somewhere inside this pull > request: > > Merge: 89c3b37af87e eb85d03e01c3 > Author: Linus Torvalds > Date: Wed May 8 21:35:19 2019 -0700 > > Merge tag 'drm-next-2019-05-09' of git://anongit.freedesktop.org/drm/drm > > Pull drm updates from Dave Airlie: Lazy question: how does one determine the first and last commit inside a merge request? Can I simply do good a2d635decbfa9c1e4ae15cb05b68b2559f7f827c^ bada2d635decbfa9c1e4ae15cb05b68b2559f7f827c for git bisect? > So I was about to test out the i915 changes in that but since my laptop > is what I use for daily work, it's a bit hard (can't freeze up on video > calls for instance). I usually use one of the ThinkPads from my embarrassing pile of outdated hardware to do nasty bisects, but I'm not about to loose any income if my much appreciated XPS 13 is out of order for a while. Thanks, Paul Bolle
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Copy name string into ring buffer for intel_update/disable_plane tracepoints
== Series Details == Series: drm/i915: Copy name string into ring buffer for intel_update/disable_plane tracepoints URL : https://patchwork.freedesktop.org/series/63516/ State : failure == Summary == Applying: drm/i915: Copy name string into ring buffer for intel_update/disable_plane tracepoints Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/i915_trace.h Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/i915_trace.h CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_trace.h error: Failed to merge in the changes. hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0001 drm/i915: Copy name string into ring buffer for intel_update/disable_plane tracepoints When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for Need to remove char pointers from trace events
== Series Details == Series: Need to remove char pointers from trace events URL : https://patchwork.freedesktop.org/series/63513/ State : failure == Summary == Applying: Need to remove char pointers from trace events Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/i915_trace.h Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/i915_trace.h CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_trace.h error: Failed to merge in the changes. hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0001 Need to remove char pointers from trace events When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 10/25] drm/i915/tgl: Add power well to support 4th pipe
On Wed, Jul 10, 2019 at 09:02:22AM -0700, Lucas De Marchi wrote: > On Wed, Jul 10, 2019 at 04:04:29AM -0700, Rodrigo Vivi wrote: > > On Tue, Jul 09, 2019 at 09:20:42AM -0700, Lucas De Marchi wrote: > > > On Tue, Jul 09, 2019 at 04:57:32AM -0700, Rodrigo Vivi wrote: > > > > On Mon, Jul 08, 2019 at 04:16:14PM -0700, Lucas De Marchi wrote: > > > > > From: Mika Kahola > > > > > > > > > > Add power well 5 to support 4th pipe and transcoder on TGL. > > > > > > > > > > Cc: James Ausmus > > > > > Cc: Imre Deak > > > > > Signed-off-by: Mika Kahola > > > > > Signed-off-by: Lucas De Marchi > > > > > --- > > > > > .../drm/i915/display/intel_display_power.c| 30 > > > > > --- > > > > > .../drm/i915/display/intel_display_power.h| 3 ++ > > > > > drivers/gpu/drm/i915/i915_reg.h | 3 +- > > > > > 3 files changed, 31 insertions(+), 5 deletions(-) > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c > > > > > b/drivers/gpu/drm/i915/display/intel_display_power.c > > > > > index c3f42169831f..455f9aab188d 100644 > > > > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > > > > > @@ -37,18 +37,24 @@ intel_display_power_domain_str(struct > > > > > drm_i915_private *i915, > > > > > return "PIPE_B"; > > > > > case POWER_DOMAIN_PIPE_C: > > > > > return "PIPE_C"; > > > > > + case POWER_DOMAIN_PIPE_D: > > > > > + return "PIPE_D"; > > > > > case POWER_DOMAIN_PIPE_A_PANEL_FITTER: > > > > > return "PIPE_A_PANEL_FITTER"; > > > > > case POWER_DOMAIN_PIPE_B_PANEL_FITTER: > > > > > return "PIPE_B_PANEL_FITTER"; > > > > > case POWER_DOMAIN_PIPE_C_PANEL_FITTER: > > > > > return "PIPE_C_PANEL_FITTER"; > > > > > + case POWER_DOMAIN_PIPE_D_PANEL_FITTER: > > > > > + return "PIPE_D_PANEL_FITTER"; > > > > > case POWER_DOMAIN_TRANSCODER_A: > > > > > return "TRANSCODER_A"; > > > > > case POWER_DOMAIN_TRANSCODER_B: > > > > > return "TRANSCODER_B"; > > > > > case POWER_DOMAIN_TRANSCODER_C: > > > > > return "TRANSCODER_C"; > > > > > + case POWER_DOMAIN_TRANSCODER_D: > > > > > + return "TRANSCODER_D"; > > > > > case POWER_DOMAIN_TRANSCODER_EDP: > > > > > return "TRANSCODER_EDP"; > > > > > case POWER_DOMAIN_TRANSCODER_EDP_VDSC: > > > > > @@ -2451,7 +2457,6 @@ void intel_display_power_put(struct > > > > > drm_i915_private *dev_priv, > > > > > * - DDI_A > > > > > * - FBC > > > > > */ > > > > > -/* TODO: TGL_PW_5_POWER_DOMAINS: PIPE_D */ > > > > > #define ICL_PW_4_POWER_DOMAINS ( \ > > > > > BIT_ULL(POWER_DOMAIN_PIPE_C) | \ > > > > > BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ > > > > > @@ -2539,7 +2544,13 @@ void intel_display_power_put(struct > > > > > drm_i915_private *dev_priv, > > > > > #define ICL_AUX_TBT4_IO_POWER_DOMAINS ( \ > > > > > BIT_ULL(POWER_DOMAIN_AUX_TBT4)) > > > > > > > > > > +#define TGL_PW_5_POWER_DOMAINS ( \ > > > > > + BIT_ULL(POWER_DOMAIN_PIPE_D) | \ > > > > > + BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \ > > > > > + BIT_ULL(POWER_DOMAIN_INIT)) > > > > > + > > > > > #define TGL_PW_4_POWER_DOMAINS ( \ > > > > > + TGL_PW_5_POWER_DOMAINS |\ > > > > > > > > why? > > > > > > not sure I understand this one. Are you saying we shouldn't have a new > > > power well for pipe d? How would we handle the different ctl? > > > > We should have a new one. The above block who adds PW5 domains is okay. > > What I didn't understand is why to add pipe D also on PW4 > > as we chated on IRC, because there's this dependency on the enabling > sequence: > > PG0 -> PG1 -> PG2 -> PG3 -> PG4 -> PG5 > > So to enable PG5 I need to enable all the previous power wells. When we > lookup, say, POWER_DOMAIN_PIPE_D, the bit will be set on all the > power wells, which makes this happen. Thanks for the info here and on irc and sorry for my inverted confusion there ;) Reviewed-by: Rodrigo Vivi > > Lucas De Marchi > > > > > > > > > > > > > > > BIT_ULL(POWER_DOMAIN_PIPE_C) | \ > > > > > BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ > > > > > BIT_ULL(POWER_DOMAIN_INIT)) > > > > > @@ -2549,7 +2560,7 @@ void intel_display_power_put(struct > > > > > drm_i915_private *dev_priv, > > > > > BIT_ULL(POWER_DOMAIN_PIPE_B) | \ > > > > > BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |\ > > > > > BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |\ > > > > > - /* TODO: TRANSCODER_D */\ > > > > > + BIT_ULL(POWER_DOMAIN_TRANSCODER_D) |\ > > > > > BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER)
Re: [Intel-gfx] [PATCH] drm/vkms: prime import support
On Wed, Jul 10, 2019 at 03:38:13PM +, Vasilev, Oleg wrote: > On Wed, 2019-07-10 at 18:35 +0300, Oleg Vasilev wrote: > > On Wed, 2019-07-10 at 17:31 +0200, Daniel Vetter wrote: > > > On Thu, Jul 04, 2019 at 11:54:10AM +0300, Oleg Vasilev wrote: > > > > Bring dmabuf sharing through implementing prime_import_sg_table > > > > callback. > > > > This will help to validate userspace conformance in prime > > > > configurations > > > > without using any actual hardware (e.g. in the cloud). > > > > > > > > Cc: Rodrigo Siqueira > > > > Cc: Haneen Mohammed > > > > Cc: Daniel Vetter > > > > Signed-off-by: Oleg Vasilev > > > > > > Btw which igt testcases does this enable? Are the igt patches > > > already > > > merged (I think as-is the igt prime tests won't run on vkms). > > > > > > Imo for vkms we really want to make sure there's tests for > > > everything, > > > otherwise a fake driver for testing/validation is kinda pointless > > > ... > > > -Daniel > > > > I've submitted a patch to IGT, but it is not merged yet: > > https://patchwork.freedesktop.org/series/63213/ > > Oops, this one: > https://patchwork.freedesktop.org/patch/315659/?series=63216=1 Ah, replied there. Let's polish the testcase first, then land the kernel side. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] screen freeze with 5.2-rc6 Dell XPS-13 skylake i915
On Wed, 2019-07-10 at 18:16 +0200, Paul Bolle wrote: > Hi James, > > James Bottomley schreef op wo 10-07-2019 om 08:01 [-0700]: > > I've confirmed that 5.1 doesn't have the regression and I'm now > > trying to bisect the 5.2 merge window, but since the problem takes > > quite a while to manifest this will take some time. Any hints > > about specific patches that might be the problem would be welcome. > > (Perhaps my message of yesterday never reached you.) No, sorry, if the list is followup to list, I'm not subscribed. I see it now I look in the archives, though. --- > Upgrading to 5.2 (from 5.1.y) on a "Dell XPS 13 9350" (is that a > skylake too?) I believe so. My laptop is a 9350. I believe they're the earliest skylake produced. > showed similar symptoms. There's no pattern to the freezes that I > can see. They're rather frequent too (think every few minutes). Eg, > two freezes while composing this message! You seem to be getting it to happen much more often than I can. Last night, on the below pull request it took me a good hour to see the freeze. --- > It seems I hit this problem quite easily. Bisecting v5.1..v5.2 could > be a real chore, so perhaps we could coordinate efforts (off-list)? Sure, my current testing indicates it's somewhere inside this pull request: Merge: 89c3b37af87e eb85d03e01c3 Author: Linus Torvalds Date: Wed May 8 21:35:19 2019 -0700 Merge tag 'drm-next-2019-05-09' of git://anongit.freedesktop.org/drm/drm Pull drm updates from Dave Airlie: So I was about to test out the i915 changes in that but since my laptop is what I use for daily work, it's a bit hard (can't freeze up on video calls for instance). James ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 07/11] drm/i915/gtt: Use NULL to encode scratch shadow entries
Chris Wilson writes:
> We can simplify our gtt walking code by comparing against NULL for
> scratch entries as opposed to looking up the distinct per-level scratch
> pointer.
>
> The only caveat is to remember to protect external parties and map the
> NULL to the scratch top pd.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 124 +---
> drivers/gpu/drm/i915/i915_gem_gtt.h | 2 +-
> 2 files changed, 41 insertions(+), 85 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index b7882f06214a..a99b89502a90 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -596,18 +596,17 @@ static void cleanup_page_dma(struct i915_address_space
> *vm,
>
> #define kmap_atomic_px(px) kmap_atomic(px_base(px)->page)
>
> -#define fill_px(px, v) fill_page_dma(px_base(px), (v))
> -#define fill32_px(px, v) fill_page_dma_32(px_base(px), (v))
> -
> -static void fill_page_dma(struct i915_page_dma *p, const u64 val)
> +static void
> +fill_page_dma(struct i915_page_dma *p, const u64 val, unsigned int count)
> {
> - kunmap_atomic(memset64(kmap_atomic(p->page), val, I915_PDES));
> + kunmap_atomic(memset64(kmap_atomic(p->page), val, count));
> }
>
> -static void fill_page_dma_32(struct i915_page_dma *p, const u32 v)
> -{
> - fill_page_dma(p, (u64)v << 32 | v);
> -}
> +#define fill_px(px, v) fill_page_dma(px_base(px), (v), I915_PDES)
> +#define fill32_px(px, v) do { \
> + u64 vv = lower_32_bits(v); \
> + fill_px(px, vv << 32 | vv); \
> +} while (0)
>
> static int
> setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
> @@ -711,7 +710,6 @@ static struct i915_page_table *alloc_pt(struct
> i915_address_space *vm)
> }
>
> atomic_set(>used, 0);
> -
> return pt;
> }
>
> @@ -719,13 +717,11 @@ static struct i915_page_directory *__alloc_pd(void)
> {
> struct i915_page_directory *pd;
>
> - pd = kmalloc(sizeof(*pd), I915_GFP_ALLOW_FAIL);
> + pd = kzalloc(sizeof(*pd), I915_GFP_ALLOW_FAIL);
> if (unlikely(!pd))
> return NULL;
>
> - atomic_set(px_used(pd), 0);
> spin_lock_init(>lock);
> -
> return pd;
> }
>
> @@ -753,63 +749,56 @@ static void free_pd(struct i915_address_space *vm,
> struct i915_page_dma *pd)
>
> #define free_px(vm, px) free_pd(vm, px_base(px))
>
> -static void init_pd(struct i915_page_directory *pd,
> - struct i915_page_scratch *scratch)
> -{
> - fill_px(pd, scratch->encode);
> - memset_p(pd->entry, scratch, 512);
> -}
> -
> static inline void
> write_dma_entry(struct i915_page_dma * const pdma,
> - const unsigned short pde,
> + const unsigned short idx,
> const u64 encoded_entry)
> {
> u64 * const vaddr = kmap_atomic(pdma->page);
>
> - vaddr[pde] = encoded_entry;
> + vaddr[idx] = encoded_entry;
> kunmap_atomic(vaddr);
> }
>
> static inline void
> __set_pd_entry(struct i915_page_directory * const pd,
> -const unsigned short pde,
> +const unsigned short idx,
My excuse was that as it is a pd, the pde fits.
Considering that now it is at any level and pde
in bspec is reserved for the last level, idx
is better.
> struct i915_page_dma * const to,
> u64 (*encode)(const dma_addr_t, const enum i915_cache_level))
> {
> GEM_BUG_ON(atomic_read(px_used(pd)) > 512);
>
> atomic_inc(px_used(pd));
> - pd->entry[pde] = to;
> - write_dma_entry(px_base(pd), pde, encode(to->daddr, I915_CACHE_LLC));
> + pd->entry[idx] = to;
> + write_dma_entry(px_base(pd), idx, encode(to->daddr, I915_CACHE_LLC));
> }
>
> -#define set_pd_entry(pd, pde, to) \
> - __set_pd_entry((pd), (pde), px_base(to), gen8_pde_encode)
> +#define set_pd_entry(pd, idx, to) \
> + __set_pd_entry((pd), (idx), px_base(to), gen8_pde_encode)
>
> static inline void
> clear_pd_entry(struct i915_page_directory * const pd,
> -const unsigned short pde,
> -struct i915_page_scratch * const scratch)
> +const unsigned short idx,
> +const struct i915_page_scratch * const scratch)
> {
> GEM_BUG_ON(atomic_read(px_used(pd)) == 0);
>
> - write_dma_entry(px_base(pd), pde, scratch->encode);
> - pd->entry[pde] = scratch;
> + write_dma_entry(px_base(pd), idx, scratch->encode);
> + pd->entry[idx] = NULL;
> atomic_dec(px_used(pd));
> }
>
> static bool
> release_pd_entry(struct i915_page_directory * const pd,
> - const unsigned short pde,
> + const unsigned short idx,
>struct i915_page_table * const pt,
> - struct i915_page_scratch * const scratch)
> + const struct i915_page_scratch * const scratch)
> {
> bool free = false;
>
> spin_lock(>lock);
> if
Re: screen freeze with 5.2-rc6 Dell XPS-13 skylake i915
Hi James, James Bottomley schreef op wo 10-07-2019 om 08:01 [-0700]: > I've confirmed that 5.1 doesn't have the regression and I'm now trying > to bisect the 5.2 merge window, but since the problem takes quite a > while to manifest this will take some time. Any hints about specific > patches that might be the problem would be welcome. (Perhaps my message of yesterday never reached you.) It seems I hit this problem quite easily. Bisecting v5.1..v5.2 could be a real chore, so perhaps we could coordinate efforts (off-list)? Thanks, Paul Bolle
[Intel-gfx] [PATCH v2] drm/i915/selftests: Ensure we don't clamp a random offset to 32b
Specify that we do want a 64b value for sizeof(u32) as we want to compute the mask of the upper 62bits. v2: Use round_down() for automatic type promotion Signed-off-by: Chris Wilson Cc: Mika Kuoppala Reviewed-by: Mika Kuoppala --- drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 2 +- drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 7 +++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c index 3abe15a08b6d..695bfb18b0d4 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c @@ -1539,7 +1539,7 @@ static int igt_vm_isolation(void *arg) div64_u64_rem(i915_prandom_u64_state(), vm_total, ); - offset &= -sizeof(u32); + offset = round_down(offset, alignof_dword); offset += I915_GTT_PAGE_SIZE; err = write_to_scratch(ctx_a, engine, diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h index eec31e36aca7..69f34737325f 100644 --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h @@ -7,6 +7,13 @@ #ifndef _INTEL_GPU_COMMANDS_H_ #define _INTEL_GPU_COMMANDS_H_ +/* + * Target address alignments required for GPU access e.g. + * MI_STORE_DWORD_IMM. + */ +#define alignof_dword 4 +#define alignof_qword 8 + /* * Instruction field definitions used by the command parser */ -- 2.22.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 10/25] drm/i915/tgl: Add power well to support 4th pipe
On Wed, Jul 10, 2019 at 04:04:29AM -0700, Rodrigo Vivi wrote:
On Tue, Jul 09, 2019 at 09:20:42AM -0700, Lucas De Marchi wrote:
On Tue, Jul 09, 2019 at 04:57:32AM -0700, Rodrigo Vivi wrote:
> On Mon, Jul 08, 2019 at 04:16:14PM -0700, Lucas De Marchi wrote:
> > From: Mika Kahola
> >
> > Add power well 5 to support 4th pipe and transcoder on TGL.
> >
> > Cc: James Ausmus
> > Cc: Imre Deak
> > Signed-off-by: Mika Kahola
> > Signed-off-by: Lucas De Marchi
> > ---
> > .../drm/i915/display/intel_display_power.c| 30 ---
> > .../drm/i915/display/intel_display_power.h| 3 ++
> > drivers/gpu/drm/i915/i915_reg.h | 3 +-
> > 3 files changed, 31 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index c3f42169831f..455f9aab188d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -37,18 +37,24 @@ intel_display_power_domain_str(struct drm_i915_private
*i915,
> > return "PIPE_B";
> > case POWER_DOMAIN_PIPE_C:
> > return "PIPE_C";
> > + case POWER_DOMAIN_PIPE_D:
> > + return "PIPE_D";
> > case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
> > return "PIPE_A_PANEL_FITTER";
> > case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
> > return "PIPE_B_PANEL_FITTER";
> > case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
> > return "PIPE_C_PANEL_FITTER";
> > + case POWER_DOMAIN_PIPE_D_PANEL_FITTER:
> > + return "PIPE_D_PANEL_FITTER";
> > case POWER_DOMAIN_TRANSCODER_A:
> > return "TRANSCODER_A";
> > case POWER_DOMAIN_TRANSCODER_B:
> > return "TRANSCODER_B";
> > case POWER_DOMAIN_TRANSCODER_C:
> > return "TRANSCODER_C";
> > + case POWER_DOMAIN_TRANSCODER_D:
> > + return "TRANSCODER_D";
> > case POWER_DOMAIN_TRANSCODER_EDP:
> > return "TRANSCODER_EDP";
> > case POWER_DOMAIN_TRANSCODER_EDP_VDSC:
> > @@ -2451,7 +2457,6 @@ void intel_display_power_put(struct drm_i915_private
*dev_priv,
> > * - DDI_A
> > * - FBC
> > */
> > -/* TODO: TGL_PW_5_POWER_DOMAINS: PIPE_D */
> > #define ICL_PW_4_POWER_DOMAINS ( \
> > BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> > BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> > @@ -2539,7 +2544,13 @@ void intel_display_power_put(struct drm_i915_private
*dev_priv,
> > #define ICL_AUX_TBT4_IO_POWER_DOMAINS ( \
> > BIT_ULL(POWER_DOMAIN_AUX_TBT4))
> >
> > +#define TGL_PW_5_POWER_DOMAINS ( \
> > + BIT_ULL(POWER_DOMAIN_PIPE_D) | \
> > + BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \
> > + BIT_ULL(POWER_DOMAIN_INIT))
> > +
> > #define TGL_PW_4_POWER_DOMAINS ( \
> > + TGL_PW_5_POWER_DOMAINS |\
>
> why?
not sure I understand this one. Are you saying we shouldn't have a new
power well for pipe d? How would we handle the different ctl?
We should have a new one. The above block who adds PW5 domains is okay.
What I didn't understand is why to add pipe D also on PW4
as we chated on IRC, because there's this dependency on the enabling
sequence:
PG0 -> PG1 -> PG2 -> PG3 -> PG4 -> PG5
So to enable PG5 I need to enable all the previous power wells. When we
lookup, say, POWER_DOMAIN_PIPE_D, the bit will be set on all the
power wells, which makes this happen.
Lucas De Marchi
>
> > BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> > BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> > BIT_ULL(POWER_DOMAIN_INIT))
> > @@ -2549,7 +2560,7 @@ void intel_display_power_put(struct drm_i915_private
*dev_priv,
> > BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> > BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |\
> > BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |\
> > - /* TODO: TRANSCODER_D */\
> > + BIT_ULL(POWER_DOMAIN_TRANSCODER_D) |\
> > BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> > BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_LANES) | \
> > BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO) | \
> > @@ -3882,7 +3893,7 @@ static const struct i915_power_well_desc
tgl_power_wells[] = {
> > },
> > {
> > .name = "power well 4",
> > - .domains = ICL_PW_4_POWER_DOMAINS,
> > + .domains = TGL_PW_4_POWER_DOMAINS,
>
> why?
this is a leftover from v1 and should be squashed on previous patch, my
bad. In v1 we were reusing the ICL definitions. I changed in this
revision and forgot to squash this change there. I will send a new
version
thanks
Lucas De Marchi
>
> > .ops = _power_well_ops,
> > .id = DISP_PW_ID_NONE,
> > {
> > @@ -3892,7
[Intel-gfx] [PATCH] drm/i915: Copy name string into ring buffer for intel_update/disable_plane tracepoints
From: "Steven Rostedt (VMware)"
Currently the intel_update_plane and intel_disable_plane tracepoints record
the address of plane->name in the ring buffer, and then when reading the
ring buffer uses %s to get the name. The issue with this, is that those two
events can be minutes, hours or even days apart. It is very dangerous to
dereference a string pointer without knowing if it still exists or not.
The proper way to handle this is to use the __string() macro in the
tracepoint which will save the string into the ring buffer at the time of
recording. Then there's no worries if the original string still exists in
memory when the ring buffer is read.
Signed-off-by: Steven Rostedt (VMware)
---
drivers/gpu/drm/i915/i915_trace.h | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_trace.h
b/drivers/gpu/drm/i915/i915_trace.h
index 12893304c8f8..d41d914a16ca 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -298,16 +298,16 @@ TRACE_EVENT(intel_update_plane,
TP_STRUCT__entry(
__field(enum pipe, pipe)
-__field(const char *, name)
__field(u32, frame)
__field(u32, scanline)
__array(int, src, 4)
__array(int, dst, 4)
+__string(name, plane->name)
),
TP_fast_assign(
+ __assign_str(name, plane->name);
__entry->pipe = crtc->pipe;
- __entry->name = plane->name;
__entry->frame =
crtc->base.dev->driver->get_vblank_counter(crtc->base.dev,
crtc->pipe);
__entry->scanline = intel_get_crtc_scanline(crtc);
@@ -316,7 +316,7 @@ TRACE_EVENT(intel_update_plane,
),
TP_printk("pipe %c, plane %s, frame=%u, scanline=%u, "
DRM_RECT_FP_FMT " -> " DRM_RECT_FMT,
- pipe_name(__entry->pipe), __entry->name,
+ pipe_name(__entry->pipe), __get_str(name),
__entry->frame, __entry->scanline,
DRM_RECT_FP_ARG((const struct drm_rect *)__entry->src),
DRM_RECT_ARG((const struct drm_rect *)__entry->dst))
@@ -328,21 +328,21 @@ TRACE_EVENT(intel_disable_plane,
TP_STRUCT__entry(
__field(enum pipe, pipe)
-__field(const char *, name)
__field(u32, frame)
__field(u32, scanline)
+__string(name, plane->name)
),
TP_fast_assign(
+ __assign_str(name, plane->name);
__entry->pipe = crtc->pipe;
- __entry->name = plane->name;
__entry->frame =
crtc->base.dev->driver->get_vblank_counter(crtc->base.dev,
crtc->pipe);
__entry->scanline = intel_get_crtc_scanline(crtc);
),
TP_printk("pipe %c, plane %s, frame=%u, scanline=%u",
- pipe_name(__entry->pipe), __entry->name,
+ pipe_name(__entry->pipe), __get_str(name),
__entry->frame, __entry->scanline)
);
--
2.20.1
___
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Re: [Intel-gfx] Need to remove char pointers from trace events
On Wed, 10 Jul 2019 18:45:24 +0300
Ville Syrjälä wrote:
> > TP_printk("pipe %c, plane %s, frame=%u, scanline=%u",
> > pipe_name(__entry->pipe), __entry->name,
> > __entry->frame, __entry->scanline)
> >
> >
> > The issue here is that you record a pointer address to "plane->name"
> > and then sometime in the distant future access that same address.
> > There's usually no guarantee that the contents at that address will
> > exist when the buffer is read.
>
> The only way those can disappear is if the device goes away. But I have
> no problem going with your patch. Want to provide a proper commit message
> for it?
Sure, but does that mean the trace data will go away with the device?
If not, then you still have the issue.
Also note that perf and trace-cmd will not know how to read that data
either, so adding it to the ring buffer gives them access.
I'll send a patch next, thanks!
-- Steve
>
> >
> > The proper way to record strings, is to record the string into the ring
> > buffer itself, and not rely on it existing hours or days later.
> >
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Re: [Intel-gfx] [PATCH 02/12] drm/i915/guc: simplify guc client
On Tue, Jul 09, 2019 at 05:54:27PM -0700, Daniele Ceraolo Spurio wrote:
> We originally added support, in some cases partial, for different modes
> of operations via guc clients:
>
> - proxy vs direct submission;
> - variable engine mask per-client.
>
> We only ever used one flow (all submissions via a single proxy), so the
> other code paths haven't been exercised and are most likely
> non-functional. The guc firmware interface is also in the process of
> being updated to better fit the i915 flow and our client abstraction
> will need to change accordingly (or possibly go away entirely), so these
> old unused paths can be considered dead and removed.
>
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Chris Wilson
> Cc: Michal Wajdeczko
> Cc: Matthew Brost
> Cc: John Harrison
> Acked-by: Matthew Brost
drm/i915/guc: simplify guc client
^ Sentence case
Reviewed-by: Michał Winiarski
-Michał
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 3 +-
> drivers/gpu/drm/i915/intel_guc_submission.c | 73 ++---
> drivers/gpu/drm/i915/intel_guc_submission.h | 2 -
> drivers/gpu/drm/i915/selftests/intel_guc.c | 12 +---
> 4 files changed, 8 insertions(+), 82 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index b4d195677877..dc65a6131a5b 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2021,7 +2021,6 @@ static int i915_guc_stage_pool(struct seq_file *m, void
> *data)
> struct drm_i915_private *dev_priv = node_to_i915(m->private);
> const struct intel_guc *guc = _priv->guc;
> struct guc_stage_desc *desc = guc->stage_desc_pool_vaddr;
> - struct intel_guc_client *client = guc->execbuf_client;
> intel_engine_mask_t tmp;
> int index;
>
> @@ -2051,7 +2050,7 @@ static int i915_guc_stage_pool(struct seq_file *m, void
> *data)
> desc->wq_addr, desc->wq_size);
> seq_putc(m, '\n');
>
> - for_each_engine_masked(engine, dev_priv, client->engines, tmp) {
> + for_each_engine(engine, dev_priv, tmp) {
> u32 guc_engine_id = engine->guc_id;
> struct guc_execlist_context *lrc =
> >lrc[guc_engine_id];
> diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c
> b/drivers/gpu/drm/i915/intel_guc_submission.c
> index 8520bb224175..30692f8289bd 100644
> --- a/drivers/gpu/drm/i915/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/intel_guc_submission.c
> @@ -363,10 +363,7 @@ static void guc_stage_desc_pool_destroy(struct intel_guc
> *guc)
> static void guc_stage_desc_init(struct intel_guc_client *client)
> {
> struct intel_guc *guc = client->guc;
> - struct i915_gem_context *ctx = client->owner;
> - struct i915_gem_engines_iter it;
> struct guc_stage_desc *desc;
> - struct intel_context *ce;
> u32 gfx_addr;
>
> desc = __get_stage_desc(client);
> @@ -380,55 +377,6 @@ static void guc_stage_desc_init(struct intel_guc_client
> *client)
> desc->priority = client->priority;
> desc->db_id = client->doorbell_id;
>
> - for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
> - struct guc_execlist_context *lrc;
> -
> - if (!(ce->engine->mask & client->engines))
> - continue;
> -
> - /* TODO: We have a design issue to be solved here. Only when we
> - * receive the first batch, we know which engine is used by the
> - * user. But here GuC expects the lrc and ring to be pinned. It
> - * is not an issue for default context, which is the only one
> - * for now who owns a GuC client. But for future owner of GuC
> - * client, need to make sure lrc is pinned prior to enter here.
> - */
> - if (!ce->state)
> - break; /* XXX: continue? */
> -
> - /*
> - * XXX: When this is a GUC_STAGE_DESC_ATTR_KERNEL client (proxy
> - * submission or, in other words, not using a direct submission
> - * model) the KMD's LRCA is not used for any work submission.
> - * Instead, the GuC uses the LRCA of the user mode context (see
> - * guc_add_request below).
> - */
> - lrc = >lrc[ce->engine->guc_id];
> - lrc->context_desc = lower_32_bits(ce->lrc_desc);
> -
> - /* The state page is after PPHWSP */
> - lrc->ring_lrca = intel_guc_ggtt_offset(guc, ce->state) +
> - LRC_STATE_PN * PAGE_SIZE;
> -
> - /* XXX: In direct submission, the GuC wants the HW context id
> - * here. In proxy submission, it wants the stage id
> - */
> - lrc->context_id = (client->stage_id << GUC_ELC_CTXID_OFFSET) |
> -
Re: [Intel-gfx] [PATCH v7 0/4] Panel rotation patches
Hi Derek. On Tue, Jul 09, 2019 at 07:16:55PM -0700, Derek Basehore wrote: > This adds the plumbing for reading panel rotation from the devicetree > and sets up adding a panel property for the panel orientation on > Mediatek SoCs when a rotation is present. > > v7 changes: > -forgot to add static inline > > v6 changes: > -added enum declaration to drm_panel.h header > > v5 changes: > -rebased > > v4 changes: > -fixed some changes made to the i915 driver > -clarified comments on of orientation helper > > v3 changes: > -changed from attach/detach callbacks to directly setting fixed panel > values in drm_panel_attach > -removed update to Documentation > -added separate function for quirked panel orientation property init > > v2 changes: > fixed build errors in i915 > > Derek Basehore (4): > drm/panel: Add helper for reading DT rotation > drm/panel: set display info in panel attach > drm/connector: Split out orientation quirk detection > drm/mtk: add panel orientation property First two patches are: Reviewed-by: Sam Ravnborg Last two patches are: Acked-by: Sam Ravnborg Sam ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/selftests: Ensure we don't clamp a random offset to 32b
Chris Wilson writes: > Quoting Mika Kuoppala (2019-07-10 16:34:23) >> Chris Wilson writes: >> >> > Specify that we do want a 64b value for sizeof(u32) as we want to >> > compute the mask of the upper 62bits. >> > >> > Signed-off-by: Chris Wilson >> > Cc: Mika Kuoppala >> > --- >> > drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 2 +- >> > 1 file changed, 1 insertion(+), 1 deletion(-) >> > >> > diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c >> > b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c >> > index 3abe15a08b6d..275ec1bfc2be 100644 >> > --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c >> > +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c >> > @@ -1539,7 +1539,7 @@ static int igt_vm_isolation(void *arg) >> > >> > div64_u64_rem(i915_prandom_u64_state(), >> > vm_total, ); >> > - offset &= -sizeof(u32); >> > + offset &= -(u64)sizeof(u32); >> >> Taking a sizeof of something we know the size of. > > u32 is a proxy for dword, and I was just trying to be more expressive > that we want the address aligned to a dword for the MI_STORE_DWORD_IMM > used. alignof_dword maybe? I was being a bit snarky. It is more expressive than -4 indeed. Compromise as we dont have a define for natural aligment for command streamer memory access. -Mika ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 01/12] drm/i915/guc: Remove preemption support for current fw
On Tue, Jul 09, 2019 at 05:54:26PM -0700, Daniele Ceraolo Spurio wrote:
> From: Chris Wilson
>
> Preemption via GuC submission is not being supported with its current
> legacy incarnation. The current FW does support a similar pre-emption
> flow via H2G, but it is class-based instead of being instance-based,
> which doesn't fit well with the i915 tracking. To fix this, the
> firmware is being updated to better support our needs with a new flow,
> so we can safely remove the old code.
>
> v2 (Daniele): resurrect & rebase, reword commit message, remove
> preempt_context as well
>
> Signed-off-by: Chris Wilson
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Chris Wilson
> Cc: Michal Wajdeczko
> Cc: Matthew Brost
> Cc: John Harrison
> Acked-by: Matthew Brost
Reviewed-by: Michał Winiarski
-Michał
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 17 --
> drivers/gpu/drm/i915/gt/intel_engine_cs.c| 13 --
> drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 -
> drivers/gpu/drm/i915/gt/intel_gt_pm.c| 4 -
> drivers/gpu/drm/i915/i915_debugfs.c | 5 -
> drivers/gpu/drm/i915/i915_drv.h | 2 -
> drivers/gpu/drm/i915/intel_guc.c | 31 ---
> drivers/gpu/drm/i915/intel_guc.h | 9 -
> drivers/gpu/drm/i915/intel_guc_submission.c | 231 +--
> drivers/gpu/drm/i915/selftests/intel_guc.c | 31 +--
> 10 files changed, 14 insertions(+), 330 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index e367dce2a696..078592912d97 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -644,18 +644,12 @@ static void init_contexts(struct drm_i915_private *i915)
> init_llist_head(>contexts.free_list);
> }
>
> -static bool needs_preempt_context(struct drm_i915_private *i915)
> -{
> - return USES_GUC_SUBMISSION(i915);
> -}
> -
> int i915_gem_contexts_init(struct drm_i915_private *dev_priv)
> {
> struct i915_gem_context *ctx;
>
> /* Reassure ourselves we are only called once */
> GEM_BUG_ON(dev_priv->kernel_context);
> - GEM_BUG_ON(dev_priv->preempt_context);
>
> init_contexts(dev_priv);
>
> @@ -676,15 +670,6 @@ int i915_gem_contexts_init(struct drm_i915_private
> *dev_priv)
> GEM_BUG_ON(!atomic_read(>hw_id_pin_count));
> dev_priv->kernel_context = ctx;
>
> - /* highest priority; preempting task */
> - if (needs_preempt_context(dev_priv)) {
> - ctx = i915_gem_context_create_kernel(dev_priv, INT_MAX);
> - if (!IS_ERR(ctx))
> - dev_priv->preempt_context = ctx;
> - else
> - DRM_ERROR("Failed to create preempt context; disabling
> preemption\n");
> - }
> -
> DRM_DEBUG_DRIVER("%s context support initialized\n",
>DRIVER_CAPS(dev_priv)->has_logical_contexts ?
>"logical" : "fake");
> @@ -695,8 +680,6 @@ void i915_gem_contexts_fini(struct drm_i915_private *i915)
> {
> lockdep_assert_held(>drm.struct_mutex);
>
> - if (i915->preempt_context)
> - destroy_kernel_context(>preempt_context);
> destroy_kernel_context(>kernel_context);
>
> /* Must free all deferred contexts (via flush_workqueue) first */
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index bdf279fa3b2e..76b5c068a26d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -841,15 +841,6 @@ int intel_engine_init_common(struct intel_engine_cs
> *engine)
> if (ret)
> return ret;
>
> - /*
> - * Similarly the preempt context must always be available so that
> - * we can interrupt the engine at any time. However, as preemption
> - * is optional, we allow it to fail.
> - */
> - if (i915->preempt_context)
> - pin_context(i915->preempt_context, engine,
> - >preempt_context);
> -
> ret = measure_breadcrumb_dw(engine);
> if (ret < 0)
> goto err_unpin;
> @@ -861,8 +852,6 @@ int intel_engine_init_common(struct intel_engine_cs
> *engine)
> return 0;
>
> err_unpin:
> - if (engine->preempt_context)
> - intel_context_unpin(engine->preempt_context);
> intel_context_unpin(engine->kernel_context);
> return ret;
> }
> @@ -887,8 +876,6 @@ void intel_engine_cleanup_common(struct intel_engine_cs
> *engine)
> if (engine->default_state)
> i915_gem_object_put(engine->default_state);
>
> - if (engine->preempt_context)
> - intel_context_unpin(engine->preempt_context);
> intel_context_unpin(engine->kernel_context);
> GEM_BUG_ON(!llist_empty(>barrier_tasks));
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
>
Re: [Intel-gfx] Need to remove char pointers from trace events
On Wed, Jul 10, 2019 at 11:25:49AM -0400, Steven Rostedt wrote:
> I was doing a bit of an audit on trace events and found this:
>
> # cat /debug/tracing/events/i915/intel_disable_plane/format
> name: intel_disable_plane
> ID: 1358
> format:
> field:unsigned short common_type; offset:0; size:2;
> signed:0;
> field:unsigned char common_flags; offset:2; size:1;
> signed:0;
> field:unsigned char common_preempt_count; offset:3; size:1;
> signed:0;
> field:int common_pid; offset:4; size:4; signed:1;
>
> field:enum pipe pipe; offset:8; size:4; signed:1;
> field:const char * name;offset:16; size:8; signed:0;
> field:u32 frame;offset:24; size:4; signed:0;
> field:u32 scanline; offset:28; size:4; signed:0;
>
> print fmt: "pipe %c, plane %s, frame=%u, scanline=%u", ((REC->pipe) + 'A'),
> REC->name, REC->frame, REC->scanline
>
>
> Same goes for intel_update_plane.
>
>
> The problem here is:
>
> field:const char * name;offset:16; size:8; signed:0;
>
> print fmt: "pipe %c, plane %s, frame=%u, scanline=%u", ((REC->pipe) + 'A'),
> REC->name, REC->frame, REC->scanline
>
>
> Where the TRACE_EVENT() macro has:
>
> TP_fast_assign(
> __entry->pipe = crtc->pipe;
> __entry->name = plane->name;
> __entry->frame =
> crtc->base.dev->driver->get_vblank_counter(crtc->base.dev,
>
>crtc->pipe);
> __entry->scanline = intel_get_crtc_scanline(crtc);
> ),
>
> TP_printk("pipe %c, plane %s, frame=%u, scanline=%u",
> pipe_name(__entry->pipe), __entry->name,
> __entry->frame, __entry->scanline)
>
>
> The issue here is that you record a pointer address to "plane->name"
> and then sometime in the distant future access that same address.
> There's usually no guarantee that the contents at that address will
> exist when the buffer is read.
The only way those can disappear is if the device goes away. But I have
no problem going with your patch. Want to provide a proper commit message
for it?
>
> The proper way to record strings, is to record the string into the ring
> buffer itself, and not rely on it existing hours or days later.
>
> I recommend the following patch:
>
> -- Steve
>
> diff --git a/drivers/gpu/drm/i915/i915_trace.h
> b/drivers/gpu/drm/i915/i915_trace.h
> index 12893304c8f8..d41d914a16ca 100644
> --- a/drivers/gpu/drm/i915/i915_trace.h
> +++ b/drivers/gpu/drm/i915/i915_trace.h
> @@ -298,16 +298,16 @@ TRACE_EVENT(intel_update_plane,
>
> TP_STRUCT__entry(
>__field(enum pipe, pipe)
> - __field(const char *, name)
>__field(u32, frame)
>__field(u32, scanline)
>__array(int, src, 4)
>__array(int, dst, 4)
> + __string(name, plane->name)
>),
>
> TP_fast_assign(
> +__assign_str(name, plane->name);
> __entry->pipe = crtc->pipe;
> -__entry->name = plane->name;
> __entry->frame =
> crtc->base.dev->driver->get_vblank_counter(crtc->base.dev,
>
>crtc->pipe);
> __entry->scanline = intel_get_crtc_scanline(crtc);
> @@ -316,7 +316,7 @@ TRACE_EVENT(intel_update_plane,
> ),
>
> TP_printk("pipe %c, plane %s, frame=%u, scanline=%u, "
> DRM_RECT_FP_FMT " -> " DRM_RECT_FMT,
> - pipe_name(__entry->pipe), __entry->name,
> + pipe_name(__entry->pipe), __get_str(name),
> __entry->frame, __entry->scanline,
> DRM_RECT_FP_ARG((const struct drm_rect *)__entry->src),
> DRM_RECT_ARG((const struct drm_rect *)__entry->dst))
> @@ -328,21 +328,21 @@ TRACE_EVENT(intel_disable_plane,
>
> TP_STRUCT__entry(
>__field(enum pipe, pipe)
> - __field(const char *, name)
>__field(u32, frame)
>__field(u32, scanline)
> + __string(name, plane->name)
>),
>
> TP_fast_assign(
> +__assign_str(name, plane->name);
> __entry->pipe = crtc->pipe;
> -__entry->name = plane->name;
> __entry->frame =
> crtc->base.dev->driver->get_vblank_counter(crtc->base.dev,
>
Re: [Intel-gfx] [PATCH] drm/vkms: prime import support
On Wed, 2019-07-10 at 18:35 +0300, Oleg Vasilev wrote: > On Wed, 2019-07-10 at 17:31 +0200, Daniel Vetter wrote: > > On Thu, Jul 04, 2019 at 11:54:10AM +0300, Oleg Vasilev wrote: > > > Bring dmabuf sharing through implementing prime_import_sg_table > > > callback. > > > This will help to validate userspace conformance in prime > > > configurations > > > without using any actual hardware (e.g. in the cloud). > > > > > > Cc: Rodrigo Siqueira > > > Cc: Haneen Mohammed > > > Cc: Daniel Vetter > > > Signed-off-by: Oleg Vasilev > > > > Btw which igt testcases does this enable? Are the igt patches > > already > > merged (I think as-is the igt prime tests won't run on vkms). > > > > Imo for vkms we really want to make sure there's tests for > > everything, > > otherwise a fake driver for testing/validation is kinda pointless > > ... > > -Daniel > > I've submitted a patch to IGT, but it is not merged yet: > https://patchwork.freedesktop.org/series/63213/ Oops, this one: https://patchwork.freedesktop.org/patch/315659/?series=63216=1 > Oleg smime.p7s Description: S/MIME cryptographic signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/selftests: Ensure we don't clamp a random offset to 32b
Quoting Mika Kuoppala (2019-07-10 16:34:23) > Chris Wilson writes: > > > Specify that we do want a 64b value for sizeof(u32) as we want to > > compute the mask of the upper 62bits. > > > > Signed-off-by: Chris Wilson > > Cc: Mika Kuoppala > > --- > > drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c > > b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c > > index 3abe15a08b6d..275ec1bfc2be 100644 > > --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c > > +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c > > @@ -1539,7 +1539,7 @@ static int igt_vm_isolation(void *arg) > > > > div64_u64_rem(i915_prandom_u64_state(), > > vm_total, ); > > - offset &= -sizeof(u32); > > + offset &= -(u64)sizeof(u32); > > Taking a sizeof of something we know the size of. u32 is a proxy for dword, and I was just trying to be more expressive that we want the address aligned to a dword for the MI_STORE_DWORD_IMM used. alignof_dword maybe? -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/vkms: prime import support
On Wed, 2019-07-10 at 17:31 +0200, Daniel Vetter wrote:
> On Thu, Jul 04, 2019 at 11:54:10AM +0300, Oleg Vasilev wrote:
> > Bring dmabuf sharing through implementing prime_import_sg_table
> > callback.
> > This will help to validate userspace conformance in prime
> > configurations
> > without using any actual hardware (e.g. in the cloud).
> >
> > Cc: Rodrigo Siqueira
> > Cc: Haneen Mohammed
> > Cc: Daniel Vetter
> > Signed-off-by: Oleg Vasilev
>
> Btw which igt testcases does this enable? Are the igt patches already
> merged (I think as-is the igt prime tests won't run on vkms).
>
> Imo for vkms we really want to make sure there's tests for
> everything,
> otherwise a fake driver for testing/validation is kinda pointless ...
> -Daniel
I've submitted a patch to IGT, but it is not merged yet:
https://patchwork.freedesktop.org/series/63213/
Oleg
>
> > ---
> > drivers/gpu/drm/vkms/vkms_drv.c | 6 +
> > drivers/gpu/drm/vkms/vkms_drv.h | 9 +++
> > drivers/gpu/drm/vkms/vkms_gem.c | 46
> > +
> > 3 files changed, 61 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/vkms/vkms_drv.c
> > b/drivers/gpu/drm/vkms/vkms_drv.c
> > index cc53ef88a331..b71c16d9ca09 100644
> > --- a/drivers/gpu/drm/vkms/vkms_drv.c
> > +++ b/drivers/gpu/drm/vkms/vkms_drv.c
> > @@ -10,6 +10,7 @@
> > */
> >
> > #include
> > +#include
> > #include
> > #include
> > #include
> > @@ -96,6 +97,8 @@ static struct drm_driver vkms_driver = {
> > .gem_vm_ops = _gem_vm_ops,
> > .gem_free_object_unlocked = vkms_gem_free_object,
> > .get_vblank_timestamp = vkms_get_vblank_timestamp,
> > + .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
> > + .gem_prime_import_sg_table = vkms_prime_import_sg_table,
> >
> > .name = DRIVER_NAME,
> > .desc = DRIVER_DESC,
> > @@ -147,6 +150,9 @@ static int __init vkms_init(void)
> >
> > ret = drm_dev_init(_device->drm, _driver,
> >_device->platform->dev);
> > +
> > + dma_coerce_mask_and_coherent(vkms_device->drm.dev,
> > +DMA_BIT_MASK(64));
> > if (ret)
> > goto out_unregister;
> >
> > diff --git a/drivers/gpu/drm/vkms/vkms_drv.h
> > b/drivers/gpu/drm/vkms/vkms_drv.h
> > index 12b4db7ac641..fb15101c8f3e 100644
> > --- a/drivers/gpu/drm/vkms/vkms_drv.h
> > +++ b/drivers/gpu/drm/vkms/vkms_drv.h
> > @@ -126,6 +126,9 @@ struct drm_gem_object *vkms_gem_create(struct
> > drm_device *dev,
> >u32 *handle,
> >u64 size);
> >
> > +struct vkms_gem_object *vkms_gem_create_private(struct drm_device
> > *dev,
> > + u64 size);
> > +
> > vm_fault_t vkms_gem_fault(struct vm_fault *vmf);
> >
> > int vkms_dumb_create(struct drm_file *file, struct drm_device
> > *dev,
> > @@ -137,6 +140,12 @@ int vkms_gem_vmap(struct drm_gem_object *obj);
> >
> > void vkms_gem_vunmap(struct drm_gem_object *obj);
> >
> > +/* Prime */
> > +struct drm_gem_object *
> > +vkms_prime_import_sg_table(struct drm_device *dev,
> > + struct dma_buf_attachment *attach,
> > + struct sg_table *sg);
> > +
> > /* CRC Support */
> > const char *const *vkms_get_crc_sources(struct drm_crtc *crtc,
> > size_t *count);
> > diff --git a/drivers/gpu/drm/vkms/vkms_gem.c
> > b/drivers/gpu/drm/vkms/vkms_gem.c
> > index 69048e73377d..a1b837460f63 100644
> > --- a/drivers/gpu/drm/vkms/vkms_gem.c
> > +++ b/drivers/gpu/drm/vkms/vkms_gem.c
> > @@ -1,5 +1,6 @@
> > // SPDX-License-Identifier: GPL-2.0+
> >
> > +#include
> > #include
> >
> > #include "vkms_drv.h"
> > @@ -117,6 +118,25 @@ struct drm_gem_object *vkms_gem_create(struct
> > drm_device *dev,
> > return >gem;
> > }
> >
> > +struct vkms_gem_object *vkms_gem_create_private(struct drm_device
> > *dev,
> > + u64 size)
> > +{
> > + struct vkms_gem_object *obj;
> > +
> > + obj = kzalloc(sizeof(*obj), GFP_KERNEL);
> > +
> > + if (!obj)
> > + return ERR_PTR(-ENOMEM);
> > +
> > + size = roundup(size, PAGE_SIZE);
> > +
> > + drm_gem_private_object_init(dev, >gem, size);
> > +
> > + mutex_init(>pages_lock);
> > +
> > + return obj;
> > +}
> > +
> > int vkms_dumb_create(struct drm_file *file, struct drm_device
> > *dev,
> > struct drm_mode_create_dumb *args)
> > {
> > @@ -217,3 +237,29 @@ int vkms_gem_vmap(struct drm_gem_object *obj)
> > mutex_unlock(_obj->pages_lock);
> > return ret;
> > }
> > +
> > +struct drm_gem_object *
> > +vkms_prime_import_sg_table(struct drm_device *dev,
> > + struct dma_buf_attachment *attach,
> > + struct sg_table *sg)
> > +{
> > + struct vkms_gem_object *obj;
> > + int npages;
> > +
> > + obj = __vkms_gem_create(dev, attach->dmabuf->size);
Re: [Intel-gfx] [PATCH] drm/i915/selftests: Ensure we don't clamp a random offset to 32b
Chris Wilson writes: > Specify that we do want a 64b value for sizeof(u32) as we want to > compute the mask of the upper 62bits. > > Signed-off-by: Chris Wilson > Cc: Mika Kuoppala > --- > drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c > b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c > index 3abe15a08b6d..275ec1bfc2be 100644 > --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c > +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c > @@ -1539,7 +1539,7 @@ static int igt_vm_isolation(void *arg) > > div64_u64_rem(i915_prandom_u64_state(), > vm_total, ); > - offset &= -sizeof(u32); > + offset &= -(u64)sizeof(u32); Taking a sizeof of something we know the size of. Ok enough! Back to business: should be the same for 64bit, but make sure for 32. Reviewed-by: Mika Kuoppala > offset += I915_GTT_PAGE_SIZE; > > err = write_to_scratch(ctx_a, engine, > -- > 2.22.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [igt-dev] [PATCH V6 i-g-t 3/6] lib: Add function to hash a framebuffer
On Wed, 2019-07-10 at 15:30 +, Ser, Simon wrote:
> Mostly LGTM, here are a few nits.
>
> On Wed, 2019-06-12 at 23:17 -0300, Brian Starkey wrote:
> > To use writeback buffers as a CRC source, we need to be able to hash
> > them. Implement a simple FVA-1a hashing routine for this purpose.
> >
> > Doing a bytewise hash on the framebuffer directly can be very slow if
> > the memory is noncached. By making a copy of each line in the FB first
> > (which can take advantage of word-access speedup), we can do the hash
> > on a cached copy, which is much faster (10x speedup on my platform).
> >
> > v6: use igt_memcpy_from_wc() instead of plain memcpy, as suggested by
> > Chris Wilson
> >
> > Signed-off-by: Brian Starkey
> > [rebased and updated to the most recent API]
> > Signed-off-by: Liviu Dudau
> > ---
> > lib/igt_fb.c | 66
> > lib/igt_fb.h | 3 +++
> > 2 files changed, 69 insertions(+)
> >
> > diff --git a/lib/igt_fb.c b/lib/igt_fb.c
> > index 9d4f905e..d07dae39 100644
> > --- a/lib/igt_fb.c
> > +++ b/lib/igt_fb.c
> > @@ -3256,6 +3256,72 @@ bool igt_fb_supported_format(uint32_t drm_format)
> > return false;
> > }
> >
> > +/*
> > + * This implements the FNV-1a hashing algorithm instead of CRC, for
> > + * simplicity
> > + * http://www.isthe.com/chongo/tech/comp/fnv/index.html
> > + *
> > + * hash = offset_basis
> > + * for each octet_of_data to be hashed
> > + * hash = hash xor octet_of_data
> > + * hash = hash * FNV_prime
> > + * return hash
> > + *
> > + * 32 bit offset_basis = 2166136261
> > + * 32 bit FNV_prime = 224 + 28 + 0x93 = 16777619
> > + */
> > +int igt_fb_get_crc(struct igt_fb *fb, igt_crc_t *crc)
> > +{
> > +#define FNV1a_OFFSET_BIAS 2166136261
> > +#define FNV1a_PRIME 16777619
>
> I'd just use plain uint32_t variables for those, but no big deal.
>
> > + uint32_t hash;
> > + void *map;
> > + char *ptr, *line = NULL;
> > + int x, y, cpp = igt_drm_format_to_bpp(fb->drm_format) / 8;
> > + uint32_t stride = calc_plane_stride(fb, 0);
>
> We could return -EINVAL in case fb->num_planes != 1.
Let's not waste cycles. With this ^ fixed, this patch is:
Reviewed-by: Simon Ser
Other nits are optional.
> > + if (fb->is_dumb)
> > + map = kmstest_dumb_map_buffer(fb->fd, fb->gem_handle, fb->size,
> > + PROT_READ);
> > + else
> > + map = gem_mmap__gtt(fb->fd, fb->gem_handle, fb->size,
> > + PROT_READ);
> > + ptr = map;
>
> Nit: no need for this, can assign the result of mmap directly to ptr.
>
> > +
> > + /*
> > +* Framebuffers are often uncached, which can make byte-wise accesses
> > +* very slow. We copy each line of the FB into a local buffer to speed
> > +* up the hashing.
> > +*/
> > + line = malloc(stride);
> > + if (!line) {
> > + munmap(map, fb->size);
> > + return -ENOMEM;
> > + }
> > +
> > + hash = FNV1a_OFFSET_BIAS;
> > +
> > + for (y = 0; y < fb->height; y++, ptr += stride) {
> > +
> > + igt_memcpy_from_wc(line, ptr, stride);
>
> Nit: no need to copy the whole stride actually, we can just copy
> fb->width * cpp since we're only going to read that.
>
> > +
> > + for (x = 0; x < fb->width * cpp; x++) {
> > + hash ^= line[x];
> > + hash *= FNV1a_PRIME;
> > + }
> > + }
> > +
> > + crc->n_words = 1;
> > + crc->crc[0] = hash;
> > +
> > + free(line);
> > + munmap(map, fb->size);
> > +
> > + return 0;
> > +#undef FNV1a_OFFSET_BIAS
> > +#undef FNV1a_PRIME
> > +}
> > +
> > /**
> > * igt_format_is_yuv:
> > * @drm_format: drm fourcc
> > diff --git a/lib/igt_fb.h b/lib/igt_fb.h
> > index adefebe1..a2741c05 100644
> > --- a/lib/igt_fb.h
> > +++ b/lib/igt_fb.h
> > @@ -37,6 +37,7 @@
> > #include
> >
> > #include "igt_color_encoding.h"
> > +#include "igt_debugfs.h"
> >
> > /*
> > * Internal format to denote a buffer compatible with pixman's
> > @@ -194,5 +195,7 @@ int igt_format_plane_bpp(uint32_t drm_format, int
> > plane);
> > void igt_format_array_fill(uint32_t **formats_array, unsigned int *count,
> >bool allow_yuv);
> >
> > +int igt_fb_get_crc(struct igt_fb *fb, igt_crc_t *crc);
> > +
> > #endif /* __IGT_FB_H__ */
> >
> > ___
> > igt-dev mailing list
> > igt-...@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/igt-dev
> ___
> igt-dev mailing list
> igt-...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/vkms: prime import support
On Thu, Jul 04, 2019 at 11:54:10AM +0300, Oleg Vasilev wrote:
> Bring dmabuf sharing through implementing prime_import_sg_table callback.
> This will help to validate userspace conformance in prime configurations
> without using any actual hardware (e.g. in the cloud).
>
> Cc: Rodrigo Siqueira
> Cc: Haneen Mohammed
> Cc: Daniel Vetter
> Signed-off-by: Oleg Vasilev
Btw which igt testcases does this enable? Are the igt patches already
merged (I think as-is the igt prime tests won't run on vkms).
Imo for vkms we really want to make sure there's tests for everything,
otherwise a fake driver for testing/validation is kinda pointless ...
-Daniel
> ---
> drivers/gpu/drm/vkms/vkms_drv.c | 6 +
> drivers/gpu/drm/vkms/vkms_drv.h | 9 +++
> drivers/gpu/drm/vkms/vkms_gem.c | 46 +
> 3 files changed, 61 insertions(+)
>
> diff --git a/drivers/gpu/drm/vkms/vkms_drv.c b/drivers/gpu/drm/vkms/vkms_drv.c
> index cc53ef88a331..b71c16d9ca09 100644
> --- a/drivers/gpu/drm/vkms/vkms_drv.c
> +++ b/drivers/gpu/drm/vkms/vkms_drv.c
> @@ -10,6 +10,7 @@
> */
>
> #include
> +#include
> #include
> #include
> #include
> @@ -96,6 +97,8 @@ static struct drm_driver vkms_driver = {
> .gem_vm_ops = _gem_vm_ops,
> .gem_free_object_unlocked = vkms_gem_free_object,
> .get_vblank_timestamp = vkms_get_vblank_timestamp,
> + .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
> + .gem_prime_import_sg_table = vkms_prime_import_sg_table,
>
> .name = DRIVER_NAME,
> .desc = DRIVER_DESC,
> @@ -147,6 +150,9 @@ static int __init vkms_init(void)
>
> ret = drm_dev_init(_device->drm, _driver,
> _device->platform->dev);
> +
> + dma_coerce_mask_and_coherent(vkms_device->drm.dev,
> + DMA_BIT_MASK(64));
> if (ret)
> goto out_unregister;
>
> diff --git a/drivers/gpu/drm/vkms/vkms_drv.h b/drivers/gpu/drm/vkms/vkms_drv.h
> index 12b4db7ac641..fb15101c8f3e 100644
> --- a/drivers/gpu/drm/vkms/vkms_drv.h
> +++ b/drivers/gpu/drm/vkms/vkms_drv.h
> @@ -126,6 +126,9 @@ struct drm_gem_object *vkms_gem_create(struct drm_device
> *dev,
> u32 *handle,
> u64 size);
>
> +struct vkms_gem_object *vkms_gem_create_private(struct drm_device *dev,
> + u64 size);
> +
> vm_fault_t vkms_gem_fault(struct vm_fault *vmf);
>
> int vkms_dumb_create(struct drm_file *file, struct drm_device *dev,
> @@ -137,6 +140,12 @@ int vkms_gem_vmap(struct drm_gem_object *obj);
>
> void vkms_gem_vunmap(struct drm_gem_object *obj);
>
> +/* Prime */
> +struct drm_gem_object *
> +vkms_prime_import_sg_table(struct drm_device *dev,
> +struct dma_buf_attachment *attach,
> +struct sg_table *sg);
> +
> /* CRC Support */
> const char *const *vkms_get_crc_sources(struct drm_crtc *crtc,
> size_t *count);
> diff --git a/drivers/gpu/drm/vkms/vkms_gem.c b/drivers/gpu/drm/vkms/vkms_gem.c
> index 69048e73377d..a1b837460f63 100644
> --- a/drivers/gpu/drm/vkms/vkms_gem.c
> +++ b/drivers/gpu/drm/vkms/vkms_gem.c
> @@ -1,5 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0+
>
> +#include
> #include
>
> #include "vkms_drv.h"
> @@ -117,6 +118,25 @@ struct drm_gem_object *vkms_gem_create(struct drm_device
> *dev,
> return >gem;
> }
>
> +struct vkms_gem_object *vkms_gem_create_private(struct drm_device *dev,
> + u64 size)
> +{
> + struct vkms_gem_object *obj;
> +
> + obj = kzalloc(sizeof(*obj), GFP_KERNEL);
> +
> + if (!obj)
> + return ERR_PTR(-ENOMEM);
> +
> + size = roundup(size, PAGE_SIZE);
> +
> + drm_gem_private_object_init(dev, >gem, size);
> +
> + mutex_init(>pages_lock);
> +
> + return obj;
> +}
> +
> int vkms_dumb_create(struct drm_file *file, struct drm_device *dev,
>struct drm_mode_create_dumb *args)
> {
> @@ -217,3 +237,29 @@ int vkms_gem_vmap(struct drm_gem_object *obj)
> mutex_unlock(_obj->pages_lock);
> return ret;
> }
> +
> +struct drm_gem_object *
> +vkms_prime_import_sg_table(struct drm_device *dev,
> +struct dma_buf_attachment *attach,
> +struct sg_table *sg)
> +{
> + struct vkms_gem_object *obj;
> + int npages;
> +
> + obj = __vkms_gem_create(dev, attach->dmabuf->size);
> + if (IS_ERR(obj))
> + return ERR_CAST(obj);
> +
> + npages = PAGE_ALIGN(attach->dmabuf->size) / PAGE_SIZE;
> + DRM_DEBUG_PRIME("Importing %d pages\n", npages);
> +
> + obj->pages = kvmalloc_array(npages, sizeof(struct page *), GFP_KERNEL);
> + if (!obj->pages) {
> + vkms_gem_free_object(>gem);
> + return ERR_PTR(-ENOMEM);
> + }
> +
> +
Re: [Intel-gfx] [igt-dev] [PATCH V6 i-g-t 3/6] lib: Add function to hash a framebuffer
Mostly LGTM, here are a few nits.
On Wed, 2019-06-12 at 23:17 -0300, Brian Starkey wrote:
> To use writeback buffers as a CRC source, we need to be able to hash
> them. Implement a simple FVA-1a hashing routine for this purpose.
>
> Doing a bytewise hash on the framebuffer directly can be very slow if
> the memory is noncached. By making a copy of each line in the FB first
> (which can take advantage of word-access speedup), we can do the hash
> on a cached copy, which is much faster (10x speedup on my platform).
>
> v6: use igt_memcpy_from_wc() instead of plain memcpy, as suggested by
> Chris Wilson
>
> Signed-off-by: Brian Starkey
> [rebased and updated to the most recent API]
> Signed-off-by: Liviu Dudau
> ---
> lib/igt_fb.c | 66
> lib/igt_fb.h | 3 +++
> 2 files changed, 69 insertions(+)
>
> diff --git a/lib/igt_fb.c b/lib/igt_fb.c
> index 9d4f905e..d07dae39 100644
> --- a/lib/igt_fb.c
> +++ b/lib/igt_fb.c
> @@ -3256,6 +3256,72 @@ bool igt_fb_supported_format(uint32_t drm_format)
> return false;
> }
>
> +/*
> + * This implements the FNV-1a hashing algorithm instead of CRC, for
> + * simplicity
> + * http://www.isthe.com/chongo/tech/comp/fnv/index.html
> + *
> + * hash = offset_basis
> + * for each octet_of_data to be hashed
> + * hash = hash xor octet_of_data
> + * hash = hash * FNV_prime
> + * return hash
> + *
> + * 32 bit offset_basis = 2166136261
> + * 32 bit FNV_prime = 224 + 28 + 0x93 = 16777619
> + */
> +int igt_fb_get_crc(struct igt_fb *fb, igt_crc_t *crc)
> +{
> +#define FNV1a_OFFSET_BIAS 2166136261
> +#define FNV1a_PRIME 16777619
I'd just use plain uint32_t variables for those, but no big deal.
> + uint32_t hash;
> + void *map;
> + char *ptr, *line = NULL;
> + int x, y, cpp = igt_drm_format_to_bpp(fb->drm_format) / 8;
> + uint32_t stride = calc_plane_stride(fb, 0);
We could return -EINVAL in case fb->num_planes != 1.
> + if (fb->is_dumb)
> + map = kmstest_dumb_map_buffer(fb->fd, fb->gem_handle, fb->size,
> + PROT_READ);
> + else
> + map = gem_mmap__gtt(fb->fd, fb->gem_handle, fb->size,
> + PROT_READ);
> + ptr = map;
Nit: no need for this, can assign the result of mmap directly to ptr.
> +
> + /*
> + * Framebuffers are often uncached, which can make byte-wise accesses
> + * very slow. We copy each line of the FB into a local buffer to speed
> + * up the hashing.
> + */
> + line = malloc(stride);
> + if (!line) {
> + munmap(map, fb->size);
> + return -ENOMEM;
> + }
> +
> + hash = FNV1a_OFFSET_BIAS;
> +
> + for (y = 0; y < fb->height; y++, ptr += stride) {
> +
> + igt_memcpy_from_wc(line, ptr, stride);
Nit: no need to copy the whole stride actually, we can just copy
fb->width * cpp since we're only going to read that.
> +
> + for (x = 0; x < fb->width * cpp; x++) {
> + hash ^= line[x];
> + hash *= FNV1a_PRIME;
> + }
> + }
> +
> + crc->n_words = 1;
> + crc->crc[0] = hash;
> +
> + free(line);
> + munmap(map, fb->size);
> +
> + return 0;
> +#undef FNV1a_OFFSET_BIAS
> +#undef FNV1a_PRIME
> +}
> +
> /**
> * igt_format_is_yuv:
> * @drm_format: drm fourcc
> diff --git a/lib/igt_fb.h b/lib/igt_fb.h
> index adefebe1..a2741c05 100644
> --- a/lib/igt_fb.h
> +++ b/lib/igt_fb.h
> @@ -37,6 +37,7 @@
> #include
>
> #include "igt_color_encoding.h"
> +#include "igt_debugfs.h"
>
> /*
> * Internal format to denote a buffer compatible with pixman's
> @@ -194,5 +195,7 @@ int igt_format_plane_bpp(uint32_t drm_format, int plane);
> void igt_format_array_fill(uint32_t **formats_array, unsigned int *count,
> bool allow_yuv);
>
> +int igt_fb_get_crc(struct igt_fb *fb, igt_crc_t *crc);
> +
> #endif /* __IGT_FB_H__ */
>
> ___
> igt-dev mailing list
> igt-...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] Need to remove char pointers from trace events
I was doing a bit of an audit on trace events and found this:
# cat /debug/tracing/events/i915/intel_disable_plane/format
name: intel_disable_plane
ID: 1358
format:
field:unsigned short common_type; offset:0; size:2;
signed:0;
field:unsigned char common_flags; offset:2; size:1;
signed:0;
field:unsigned char common_preempt_count; offset:3; size:1;
signed:0;
field:int common_pid; offset:4; size:4; signed:1;
field:enum pipe pipe; offset:8; size:4; signed:1;
field:const char * name;offset:16; size:8; signed:0;
field:u32 frame;offset:24; size:4; signed:0;
field:u32 scanline; offset:28; size:4; signed:0;
print fmt: "pipe %c, plane %s, frame=%u, scanline=%u", ((REC->pipe) + 'A'),
REC->name, REC->frame, REC->scanline
Same goes for intel_update_plane.
The problem here is:
field:const char * name;offset:16; size:8; signed:0;
print fmt: "pipe %c, plane %s, frame=%u, scanline=%u", ((REC->pipe) + 'A'),
REC->name, REC->frame, REC->scanline
Where the TRACE_EVENT() macro has:
TP_fast_assign(
__entry->pipe = crtc->pipe;
__entry->name = plane->name;
__entry->frame =
crtc->base.dev->driver->get_vblank_counter(crtc->base.dev,
crtc->pipe);
__entry->scanline = intel_get_crtc_scanline(crtc);
),
TP_printk("pipe %c, plane %s, frame=%u, scanline=%u",
pipe_name(__entry->pipe), __entry->name,
__entry->frame, __entry->scanline)
The issue here is that you record a pointer address to "plane->name"
and then sometime in the distant future access that same address.
There's usually no guarantee that the contents at that address will
exist when the buffer is read.
The proper way to record strings, is to record the string into the ring
buffer itself, and not rely on it existing hours or days later.
I recommend the following patch:
-- Steve
diff --git a/drivers/gpu/drm/i915/i915_trace.h
b/drivers/gpu/drm/i915/i915_trace.h
index 12893304c8f8..d41d914a16ca 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -298,16 +298,16 @@ TRACE_EVENT(intel_update_plane,
TP_STRUCT__entry(
__field(enum pipe, pipe)
-__field(const char *, name)
__field(u32, frame)
__field(u32, scanline)
__array(int, src, 4)
__array(int, dst, 4)
+__string(name, plane->name)
),
TP_fast_assign(
+ __assign_str(name, plane->name);
__entry->pipe = crtc->pipe;
- __entry->name = plane->name;
__entry->frame =
crtc->base.dev->driver->get_vblank_counter(crtc->base.dev,
crtc->pipe);
__entry->scanline = intel_get_crtc_scanline(crtc);
@@ -316,7 +316,7 @@ TRACE_EVENT(intel_update_plane,
),
TP_printk("pipe %c, plane %s, frame=%u, scanline=%u, "
DRM_RECT_FP_FMT " -> " DRM_RECT_FMT,
- pipe_name(__entry->pipe), __entry->name,
+ pipe_name(__entry->pipe), __get_str(name),
__entry->frame, __entry->scanline,
DRM_RECT_FP_ARG((const struct drm_rect *)__entry->src),
DRM_RECT_ARG((const struct drm_rect *)__entry->dst))
@@ -328,21 +328,21 @@ TRACE_EVENT(intel_disable_plane,
TP_STRUCT__entry(
__field(enum pipe, pipe)
-__field(const char *, name)
__field(u32, frame)
__field(u32, scanline)
+__string(name, plane->name)
),
TP_fast_assign(
+ __assign_str(name, plane->name);
__entry->pipe = crtc->pipe;
- __entry->name = plane->name;
__entry->frame =
crtc->base.dev->driver->get_vblank_counter(crtc->base.dev,
crtc->pipe);
__entry->scanline = intel_get_crtc_scanline(crtc);
),
TP_printk("pipe %c, plane %s, frame=%u, scanline=%u",
- pipe_name(__entry->pipe), __entry->name,
+
