Re: [Intel-gfx] [PATCH v15 10/13] drm/i915/perf: execute OA configuration from command stream
Hi Lionel,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to v5.3-rc7 next-20190904]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Lionel-Landwerlin/drm-i915-Vulkan-performance-query-support/20190907-052009
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-b001-201935 (attached as .config)
compiler: gcc-7 (Debian 7.4.0-11) 7.4.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot
All errors (new ones prefixed by >>):
In file included from :0:0:
drivers/gpu/drm/i915/i915_perf_types.h:25:2: error: unknown type name
'i915_reg_t'
i915_reg_t addr;
^~
drivers/gpu/drm/i915/i915_perf_types.h:32:12: error: 'UUID_STRING_LEN'
undeclared here (not in a function); did you mean '_LINUX_STRING_H_'?
char uuid[UUID_STRING_LEN + 1];
^~~
_LINUX_STRING_H_
drivers/gpu/drm/i915/i915_perf_types.h:75:6: error: unknown type name
'poll_table'; did you mean 'poll_to_key'?
poll_table *wait);
^~
poll_to_key
drivers/gpu/drm/i915/i915_perf_types.h:128:2: error: unknown type name
'intel_wakeref_t'
intel_wakeref_t wakeref;
^~~
>> drivers/gpu/drm/i915/i915_perf_types.h:188:29: error: field
>> 'active_config_rq' has incomplete type
struct i915_active_request active_config_rq;
^~~~
vim +/active_config_rq +188 drivers/gpu/drm/i915/i915_perf_types.h
50
51 /**
52 * struct i915_perf_stream_ops - the OPs to support a specific stream
type
53 */
54 struct i915_perf_stream_ops {
55 /**
56 * @enable: Enables the collection of HW samples, either in
response to
57 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is
opened
58 * without `I915_PERF_FLAG_DISABLED`.
59 */
60 void (*enable)(struct i915_perf_stream *stream);
61
62 /**
63 * @disable: Disables the collection of HW samples, either in
response
64 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before
destroying
65 * the stream.
66 */
67 void (*disable)(struct i915_perf_stream *stream);
68
69 /**
70 * @poll_wait: Call poll_wait, passing a wait queue that will
be woken
71 * once there is something ready to read() for the stream
72 */
73 void (*poll_wait)(struct i915_perf_stream *stream,
74struct file *file,
> 75poll_table *wait);
76
77 /**
78 * @wait_unlocked: For handling a blocking read, wait until
there is
79 * something to ready to read() for the stream. E.g. wait on
the same
80 * wait queue that would be passed to poll_wait().
81 */
82 int (*wait_unlocked)(struct i915_perf_stream *stream);
83
84 /**
85 * @read: Copy buffered metrics as records to userspace
86 * **buf**: the userspace, destination buffer
87 * **count**: the number of bytes to copy, requested by
userspace
88 * **offset**: zero at the start of the read, updated as the
read
89 * proceeds, it represents how many bytes have been copied so
far and
90 * the buffer offset for copying the next record.
91 *
92 * Copy as many buffered i915 perf samples and records for this
stream
93 * to userspace as will fit in the given buffer.
94 *
95 * Only write complete records; returning -%ENOSPC if there
isn't room
96 * for a complete record.
97 *
98 * Return any error condition that results in a short read such
as
99 * -%ENOSPC or -%EFAULT, even though these may be squashed
before
100 * returning to userspace.
101 */
102 int (*read)(struct i915_perf_stream *stream,
103 char __user *buf,
104 size_t count,
105 size_t *offset);
106
107 /**
108 * @destroy: Cleanup any stream specific resources.
109 *
110 * The stream will always be disabled before this is called.
111 */
112 void (*destroy)(struct i915_perf_stream *stream);
113 };
114
115 /**
116 * struct i915_perf_stream - state for a single open stream FD
117 */
118 struct i915_perf_stream {
119
[Intel-gfx] ✓ Fi.CI.IGT: success for HuC updates (rev2)
== Series Details == Series: HuC updates (rev2) URL : https://patchwork.freedesktop.org/series/66361/ State : success == Summary == CI Bug Log - changes from CI_DRM_6848_full -> Patchwork_14306_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14306_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_schedule@preempt-bsd: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#111325]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6848/shard-iclb8/igt@gem_exec_sched...@preempt-bsd.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14306/shard-iclb2/igt@gem_exec_sched...@preempt-bsd.html * igt@gem_exec_schedule@preempt-queue-bsd1: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276]) +17 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6848/shard-iclb1/igt@gem_exec_sched...@preempt-queue-bsd1.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14306/shard-iclb7/igt@gem_exec_sched...@preempt-queue-bsd1.html * igt@i915_suspend@sysfs-reader: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([fdo#108566]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6848/shard-apl5/igt@i915_susp...@sysfs-reader.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14306/shard-apl5/igt@i915_susp...@sysfs-reader.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-iclb: [PASS][7] -> [INCOMPLETE][8] ([fdo#107713]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6848/shard-iclb6/igt@kms_cursor_...@pipe-c-cursor-suspend.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14306/shard-iclb5/igt@kms_cursor_...@pipe-c-cursor-suspend.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-glk: [PASS][9] -> [FAIL][10] ([fdo#105363]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6848/shard-glk7/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14306/shard-glk2/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite: - shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103167]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6848/shard-iclb8/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-shrfb-draw-pwrite.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14306/shard-iclb5/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-shrfb-draw-pwrite.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - shard-kbl: [PASS][13] -> [INCOMPLETE][14] ([fdo#103665]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6848/shard-kbl6/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14306/shard-kbl1/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c: - shard-apl: [PASS][15] -> [FAIL][16] ([fdo#103375]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6848/shard-apl6/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-c.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14306/shard-apl8/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-c.html * igt@kms_plane_lowres@pipe-a-tiling-y: - shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103166]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6848/shard-iclb4/igt@kms_plane_low...@pipe-a-tiling-y.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14306/shard-iclb7/igt@kms_plane_low...@pipe-a-tiling-y.html * igt@kms_psr2_su@page_flip: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109642] / [fdo#111068]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6848/shard-iclb2/igt@kms_psr2_su@page_flip.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14306/shard-iclb6/igt@kms_psr2_su@page_flip.html * igt@kms_psr@psr2_suspend: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6848/shard-iclb2/igt@kms_psr@psr2_suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14306/shard-iclb6/igt@kms_psr@psr2_suspend.html * igt@perf_pmu@enable-race-bcs0: - shard-apl: [PASS][23] -> [TIMEOUT][24] ([fdo#111545]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6848/shard-apl6/igt@perf_...@enable-race-bcs0.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14306/shard-apl8/igt@perf_...@enable-race-bcs0.html * igt@perf_pmu@render-node-busy-idle-bcs0: - shard-apl: [PASS][25] -> [FAIL][26] ([fdo#111545]) [25]:
Re: [Intel-gfx] [PATCH v15 06/13] drm/i915/perf: move perf types to their own header
Hi Lionel,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to v5.3-rc7]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Lionel-Landwerlin/drm-i915-Vulkan-performance-query-support/20190907-052009
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-b001-201935 (attached as .config)
compiler: gcc-7 (Debian 7.4.0-11) 7.4.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot
All errors (new ones prefixed by >>):
In file included from drivers/gpu/drm/i915/i915_perf.h:11:0,
from :0:
>> drivers/gpu/drm/i915/i915_perf_types.h:25:2: error: unknown type name
>> 'i915_reg_t'
i915_reg_t addr;
^~
>> drivers/gpu/drm/i915/i915_perf_types.h:30:12: error: 'UUID_STRING_LEN'
>> undeclared here (not in a function); did you mean '_LINUX_STRING_H_'?
char uuid[UUID_STRING_LEN + 1];
^~~
_LINUX_STRING_H_
>> drivers/gpu/drm/i915/i915_perf_types.h:73:6: error: unknown type name
>> 'poll_table'; did you mean 'poll_to_key'?
poll_table *wait);
^~
poll_to_key
>> drivers/gpu/drm/i915/i915_perf_types.h:126:2: error: unknown type name
>> 'intel_wakeref_t'
intel_wakeref_t wakeref;
^~~
vim +/i915_reg_t +25 drivers/gpu/drm/i915/i915_perf_types.h
23
24 struct i915_oa_reg {
> 25 i915_reg_t addr;
26 u32 value;
27 };
28
29 struct i915_oa_config {
> 30 char uuid[UUID_STRING_LEN + 1];
31 int id;
32
33 const struct i915_oa_reg *mux_regs;
34 u32 mux_regs_len;
35 const struct i915_oa_reg *b_counter_regs;
36 u32 b_counter_regs_len;
37 const struct i915_oa_reg *flex_regs;
38 u32 flex_regs_len;
39
40 struct attribute_group sysfs_metric;
41 struct attribute *attrs[2];
42 struct device_attribute sysfs_metric_id;
43
44 atomic_t ref_count;
45 };
46
47 struct i915_perf_stream;
48
49 /**
50 * struct i915_perf_stream_ops - the OPs to support a specific stream
type
51 */
52 struct i915_perf_stream_ops {
53 /**
54 * @enable: Enables the collection of HW samples, either in
response to
55 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is
opened
56 * without `I915_PERF_FLAG_DISABLED`.
57 */
58 void (*enable)(struct i915_perf_stream *stream);
59
60 /**
61 * @disable: Disables the collection of HW samples, either in
response
62 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before
destroying
63 * the stream.
64 */
65 void (*disable)(struct i915_perf_stream *stream);
66
67 /**
68 * @poll_wait: Call poll_wait, passing a wait queue that will
be woken
69 * once there is something ready to read() for the stream
70 */
71 void (*poll_wait)(struct i915_perf_stream *stream,
72struct file *file,
> 73poll_table *wait);
74
75 /**
76 * @wait_unlocked: For handling a blocking read, wait until
there is
77 * something to ready to read() for the stream. E.g. wait on
the same
78 * wait queue that would be passed to poll_wait().
79 */
80 int (*wait_unlocked)(struct i915_perf_stream *stream);
81
82 /**
83 * @read: Copy buffered metrics as records to userspace
84 * **buf**: the userspace, destination buffer
85 * **count**: the number of bytes to copy, requested by
userspace
86 * **offset**: zero at the start of the read, updated as the
read
87 * proceeds, it represents how many bytes have been copied so
far and
88 * the buffer offset for copying the next record.
89 *
90 * Copy as many buffered i915 perf samples and records for this
stream
91 * to userspace as will fit in the given buffer.
92 *
93 * Only write complete records; returning -%ENOSPC if there
isn't room
94 * for a complete record.
95 *
96 * Return any error condition that results in a short read such
as
97 * -%ENOSPC or -%EFAULT, even though these may be squashed
before
98 * returning to userspace.
99 */
100
Re: [Intel-gfx] [PATCH] drm/i915: Fix corruption lines on the screen on Gen9 chromebooks
Hi Gaurav,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to v5.3-rc7 next-20190904]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Gaurav-K-Singh/drm-i915-Fix-corruption-lines-on-the-screen-on-Gen9-chromebooks/20190905-052832
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-rhel (attached as .config)
compiler: gcc-7 (Debian 7.4.0-11) 7.4.0
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot
All errors (new ones prefixed by >>):
drivers/gpu/drm/i915/display/intel_fbc.c: In function 'intel_fbc_enable':
>> drivers/gpu/drm/i915/display/intel_fbc.c:1100:8: error: implicit declaration
>> of function 'IS_GEN9'; did you mean 'IS_GEN'?
>> [-Werror=implicit-function-declaration]
if (IS_GEN9(dev_priv))
^~~
IS_GEN
cc1: some warnings being treated as errors
vim +1100 drivers/gpu/drm/i915/display/intel_fbc.c
1071
1072 /**
1073 * intel_fbc_enable: tries to enable FBC on the CRTC
1074 * @crtc: the CRTC
1075 * @crtc_state: corresponding _crtc_state for @crtc
1076 * @plane_state: corresponding _plane_state for the primary plane
of @crtc
1077 *
1078 * This function checks if the given CRTC was chosen for FBC, then
enables it if
1079 * possible. Notice that it doesn't activate FBC. It is valid to call
1080 * intel_fbc_enable multiple times for the same pipe without an
1081 * intel_fbc_disable in the middle, as long as it is deactivated.
1082 */
1083 void intel_fbc_enable(struct intel_crtc *crtc,
1084struct intel_crtc_state *crtc_state,
1085struct intel_plane_state *plane_state)
1086 {
1087 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1088 struct intel_fbc *fbc = _priv->fbc;
1089
1090 if (!fbc_supported(dev_priv))
1091 return;
1092
1093 mutex_lock(>lock);
1094
1095 if (fbc->enabled) {
1096 WARN_ON(fbc->crtc == NULL);
1097 if (fbc->crtc == crtc) {
1098 WARN_ON(!crtc_state->enable_fbc);
1099 WARN_ON(fbc->active);
> 1100 if (IS_GEN9(dev_priv))
1101 intel_wait_for_vblank(dev_priv,
crtc->pipe);
1102 }
1103 goto out;
1104 }
1105
1106 if (!crtc_state->enable_fbc)
1107 goto out;
1108
1109 WARN_ON(fbc->active);
1110 WARN_ON(fbc->crtc != NULL);
1112 intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
1113 if (intel_fbc_alloc_cfb(crtc)) {
1114 fbc->no_fbc_reason = "not enough stolen memory";
1115 goto out;
1116 }
1117
1118 DRM_DEBUG_KMS("Enabling FBC on pipe %c\n",
pipe_name(crtc->pipe));
1119 fbc->no_fbc_reason = "FBC enabled but not active yet\n";
1120
1121 fbc->enabled = true;
1122 fbc->crtc = crtc;
1123 out:
1124 mutex_unlock(>lock);
1125 }
1126
---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
.config.gz
Description: application/gzip
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for cdclk consolidation and rework for BXT-TGL
== Series Details ==
Series: cdclk consolidation and rework for BXT-TGL
URL : https://patchwork.freedesktop.org/series/66365/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6848 -> Patchwork_14308
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14308 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14308, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14308/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14308:
### IGT changes ###
Possible regressions
* igt@runner@aborted:
- fi-bxt-dsi: NOTRUN -> [FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14308/fi-bxt-dsi/igt@run...@aborted.html
- fi-apl-guc: NOTRUN -> [FAIL][2]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14308/fi-apl-guc/igt@run...@aborted.html
Known issues
Here are the changes found in Patchwork_14308 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6848/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14308/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@kms_chamelium@dp-crc-fast:
- fi-cml-u2: [PASS][5] -> [FAIL][6] ([fdo#110627])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6848/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14308/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [PASS][7] -> [DMESG-WARN][8] ([fdo#102614])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6848/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14308/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][9] ([fdo#111096]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6848/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14308/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@prime_vgem@basic-fence-flip:
- fi-ilk-650: [DMESG-WARN][11] ([fdo#106387]) -> [PASS][12] +1
similar issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6848/fi-ilk-650/igt@prime_v...@basic-fence-flip.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14308/fi-ilk-650/igt@prime_v...@basic-fence-flip.html
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=106387
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#110627]: https://bugs.freedesktop.org/show_bug.cgi?id=110627
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
Participating hosts (50 -> 44)
--
Additional (2): fi-kbl-soraka fi-tgl-u
Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-pnv-d510 fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6848 -> Patchwork_14308
CI-20190529: 20190529
CI_DRM_6848: a1769d05ffa7fe6e4481131e97215f37b8f5ed4e @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5172: 073caf4acb7cac63abe7a5e1409ea27a764db5fd @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14308: f59e1b13e248d599f0c365b9d05a4b9a0f095268 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f59e1b13e248 drm/i915: Consolidate {bxt, cnl, icl}_init_cdclk
8d07a457135f drm/i915: Enhance cdclk sanitization
7bf020857c41 drm/i915: Add calc_voltage_level display vfunc
c3c5cd83bf04 drm/i915: Consolidate {bxt, cnl, icl}_uninit_cdclk
93848eb9fbee drm/i915: Kill cnl_sanitize_cdclk()
4cf0293d973c drm/i915: Combine bxt_set_cdclk and cnl_set_cdclk
1ccb1492f096 drm/i915: Use literal representation of cdclk tables
637dedda4030 drm/i915: Consolidate bxt/cnl/icl cdclk readout
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14308/
___
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Re: [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1409142259
On Fri, Sep 06, 2019 at 03:46:42PM -0700, Daniele Ceraolo Spurio wrote:
>
>
> On 9/6/19 3:41 PM, Radhakrishna Sripada wrote:
> > Disable CPS aware color pipe by setting chicken bit.
> >
> > BSpec: 52890
> > HSDES: 1409142259
> >
> > Cc: Stuart Summers
> > Cc: Matt Roper
> > Signed-off-by: Radhakrishna Sripada
> > ---
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > 2 files changed, 6 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 243d3f77be13..14e3f9677b06 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -894,6 +894,11 @@ icl_gt_workarounds_init(struct drm_i915_private *i915,
> > struct i915_wa_list *wal)
> > static void
> > tgl_gt_workarounds_init(struct drm_i915_private *i915, struct
> > i915_wa_list *wal)
> > {
> > + wa_init_mcr(i915, wal);
>
> this is not part of the WA you're trying to apply, right?
>
> > +
> > + /* Wa_1409142259 */
> > + WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
> > + GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
>
> AFAICS the register is part of the render context, so shouldn't we set this
> as part of the ctx_workarounds? that's what we do for another WA on the same
> register on ICL.
How do you usually determine if a register is part of the context or
not? This one doesn't have the "This Register is saved and restored as
part of Context" notation that other context registers have, so is there
somewhere else we're supposed to find that information?
Matt
>
> Daniele
>
> > }
> > static void
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 006cffd56be2..53e07882efb7 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7668,6 +7668,7 @@ enum {
> > #define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
> > #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC (1 << 11)
> > + #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE (1 << 9)
> > #define HIZ_CHICKEN _MMIO(0x7018)
> > # define CHV_HZ_8X8_MODE_IN_1X(1 << 15)
> >
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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Re: [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1409142259
On Fri, Sep 06, 2019 at 03:41:42PM -0700, Radhakrishna Sripada wrote:
> Disable CPS aware color pipe by setting chicken bit.
>
> BSpec: 52890
BSpec: 45829
as well ("This bit must be programmed to 1").
Reviewed-by: Matt Roper
> HSDES: 1409142259
>
> Cc: Stuart Summers
> Cc: Matt Roper
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 243d3f77be13..14e3f9677b06 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -894,6 +894,11 @@ icl_gt_workarounds_init(struct drm_i915_private *i915,
> struct i915_wa_list *wal)
> static void
> tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list
> *wal)
> {
> + wa_init_mcr(i915, wal);
> +
> + /* Wa_1409142259 */
> + WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
> + GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
> }
>
> static void
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 006cffd56be2..53e07882efb7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7668,6 +7668,7 @@ enum {
>
> #define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
>#define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC (1 << 11)
> + #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE (1 << 9)
>
> #define HIZ_CHICKEN _MMIO(0x7018)
> # define CHV_HZ_8X8_MODE_IN_1X (1 << 15)
> --
> 2.20.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for cdclk consolidation and rework for BXT-TGL
== Series Details ==
Series: cdclk consolidation and rework for BXT-TGL
URL : https://patchwork.freedesktop.org/series/66365/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
637dedda4030 drm/i915: Consolidate bxt/cnl/icl cdclk readout
-:72: CHECK:CAMELCASE: Avoid CamelCase:
#72: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:1272:
+ if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
total: 0 errors, 0 warnings, 1 checks, 412 lines checked
1ccb1492f096 drm/i915: Use literal representation of cdclk tables
4cf0293d973c drm/i915: Combine bxt_set_cdclk and cnl_set_cdclk
93848eb9fbee drm/i915: Kill cnl_sanitize_cdclk()
c3c5cd83bf04 drm/i915: Consolidate {bxt, cnl, icl}_uninit_cdclk
7bf020857c41 drm/i915: Add calc_voltage_level display vfunc
8d07a457135f drm/i915: Enhance cdclk sanitization
f59e1b13e248 drm/i915: Consolidate {bxt, cnl, icl}_init_cdclk
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[Intel-gfx] [PATCH 1/8] drm/i915: Consolidate bxt/cnl/icl cdclk readout
Aside from a few minor register changes and some different clock values,
cdclk design hasn't changed much since gen9lp. Let's consolidate the
handlers for bxt, cnl, and icl to keep the codeflow consistent.
Also, while we're at it, s/bxt_de_pll_update/bxt_de_pll_readout/ since
"update" makes me think we should be writing to hardware rather than
reading from it.
Cc: Ville Syrjälä
Suggested-by: Ville Syrjälä
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 325 +
1 file changed, 138 insertions(+), 187 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index d3e56628af70..e07de3b84cec 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1190,6 +1190,36 @@ static u8 bxt_calc_voltage_level(int cdclk)
return DIV_ROUND_UP(cdclk, 25000);
}
+static u8 cnl_calc_voltage_level(int cdclk)
+{
+ if (cdclk > 336000)
+ return 2;
+ else if (cdclk > 168000)
+ return 1;
+ else
+ return 0;
+}
+
+static u8 icl_calc_voltage_level(int cdclk)
+{
+ if (cdclk > 556800)
+ return 2;
+ else if (cdclk > 326400)
+ return 1;
+ else
+ return 0;
+}
+
+static u8 ehl_calc_voltage_level(int cdclk)
+{
+ if (cdclk > 326400)
+ return 2;
+ else if (cdclk > 18)
+ return 1;
+ else
+ return 0;
+}
+
static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
{
int ratio;
@@ -1236,23 +1266,69 @@ static int glk_de_pll_vco(struct drm_i915_private
*dev_priv, int cdclk)
return dev_priv->cdclk.hw.ref * ratio;
}
-static void bxt_de_pll_update(struct drm_i915_private *dev_priv,
- struct intel_cdclk_state *cdclk_state)
+static void cnl_readout_refclk(struct drm_i915_private *dev_priv,
+ struct intel_cdclk_state *cdclk_state)
{
- u32 val;
+ if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
+ cdclk_state->ref = 24000;
+ else
+ cdclk_state->ref = 19200;
+}
- cdclk_state->ref = 19200;
- cdclk_state->vco = 0;
+static void icl_readout_refclk(struct drm_i915_private *dev_priv,
+ struct intel_cdclk_state *cdclk_state)
+{
+ u32 dssm = I915_READ(SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK;
+
+ switch (dssm) {
+ default:
+ MISSING_CASE(dssm);
+ /* fall through */
+ case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
+ cdclk_state->ref = 24000;
+ break;
+ case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
+ cdclk_state->ref = 19200;
+ break;
+ case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
+ cdclk_state->ref = 38400;
+ break;
+ }
+}
+
+static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,
+ struct intel_cdclk_state *cdclk_state)
+{
+ u32 val, ratio;
+
+ if (INTEL_GEN(dev_priv) >= 11)
+ icl_readout_refclk(dev_priv, cdclk_state);
+ else if (IS_CANNONLAKE(dev_priv))
+ cnl_readout_refclk(dev_priv, cdclk_state);
+ else
+ cdclk_state->ref = 19200;
val = I915_READ(BXT_DE_PLL_ENABLE);
- if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
+ if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
+ (val & BXT_DE_PLL_LOCK) == 0) {
+ /*
+* CDCLK PLL is disabled, the VCO/ratio doesn't matter, but
+* setting it to zero is a way to signal that.
+*/
+ cdclk_state->vco = 0;
return;
+ }
- if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
- return;
+ /*
+* CNL+ have the ratio directly in the PLL enable register, gen9lp had
+* it in a separate PLL control register.
+*/
+ if (INTEL_GEN(dev_priv) >= 10)
+ ratio = val & BXT_DE_PLL_RATIO_MASK;
+ else
+ ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
- val = I915_READ(BXT_DE_PLL_CTL);
- cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
+ cdclk_state->vco = ratio * cdclk_state->ref;
}
static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
@@ -1261,12 +1337,18 @@ static void bxt_get_cdclk(struct drm_i915_private
*dev_priv,
u32 divider;
int div;
- bxt_de_pll_update(dev_priv, cdclk_state);
-
- cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
+ if (INTEL_GEN(dev_priv) >= 12)
+ cdclk_state->bypass = cdclk_state->ref / 2;
+ else if (INTEL_GEN(dev_priv) >= 11)
+ cdclk_state->bypass = 5;
+ else
+ cdclk_state->bypass =
[Intel-gfx] [PATCH 3/8] drm/i915: Combine bxt_set_cdclk and cnl_set_cdclk
We'd previously combined ICL/TGL logic into the cnl_set_cdclk function,
but BXT is pretty similar as well. Roll the cnl/icl/tgl logic back into
the bxt function; the only things we really need to handle separately
are punit notification and calling different functions to enable/disable
the cdclk PLL.
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 267 +
1 file changed, 119 insertions(+), 148 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 8ac31f8775f0..6b5b1328a3fa 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1449,6 +1449,39 @@ static void bxt_de_pll_enable(struct drm_i915_private
*dev_priv, int vco)
dev_priv->cdclk.hw.vco = vco;
}
+static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
+{
+ u32 val;
+
+ val = I915_READ(BXT_DE_PLL_ENABLE);
+ val &= ~BXT_DE_PLL_PLL_ENABLE;
+ I915_WRITE(BXT_DE_PLL_ENABLE, val);
+
+ /* Timeout 200us */
+ if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
+ DRM_ERROR("timeout waiting for CDCLK PLL unlock\n");
+
+ dev_priv->cdclk.hw.vco = 0;
+}
+
+static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
+{
+ int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
+ u32 val;
+
+ val = CNL_CDCLK_PLL_RATIO(ratio);
+ I915_WRITE(BXT_DE_PLL_ENABLE, val);
+
+ val |= BXT_DE_PLL_PLL_ENABLE;
+ I915_WRITE(BXT_DE_PLL_ENABLE, val);
+
+ /* Timeout 200us */
+ if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
+ DRM_ERROR("timeout waiting for CDCLK PLL lock\n");
+
+ dev_priv->cdclk.hw.vco = vco;
+}
+
static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
const struct intel_cdclk_state *cdclk_state,
enum pipe pipe)
@@ -1458,6 +1491,27 @@ static void bxt_set_cdclk(struct drm_i915_private
*dev_priv,
u32 val, divider;
int ret;
+ /* Inform power controller of upcoming frequency change. */
+ if (INTEL_GEN(dev_priv) >= 10)
+ ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
+ SKL_CDCLK_PREPARE_FOR_CHANGE,
+ SKL_CDCLK_READY_FOR_CHANGE,
+ SKL_CDCLK_READY_FOR_CHANGE, 3);
+ else
+ /*
+* BSpec requires us to wait up to 150usec, but that leads to
+* timeouts; the 2ms used here is based on experiment.
+*/
+ ret = sandybridge_pcode_write_timeout(dev_priv,
+
HSW_PCODE_DE_WRITE_FREQ_REQ,
+ 0x8000, 150, 2);
+
+ if (ret) {
+ DRM_ERROR("Failed to inform PCU about cdclk change (err %d,
freq %d)\n",
+ ret, cdclk);
+ return;
+ }
+
/* cdclk = vco / 2 / div{1,1.5,2,4} */
switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
default:
@@ -1468,63 +1522,82 @@ static void bxt_set_cdclk(struct drm_i915_private
*dev_priv,
divider = BXT_CDCLK_CD2X_DIV_SEL_1;
break;
case 3:
- WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
+ WARN(IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10,
+"Unsupported divider\n");
divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
break;
case 4:
divider = BXT_CDCLK_CD2X_DIV_SEL_2;
break;
case 8:
+ WARN(INTEL_GEN(dev_priv) >= 10, "Unsupported divider\n");
divider = BXT_CDCLK_CD2X_DIV_SEL_4;
break;
}
- /*
-* Inform power controller of upcoming frequency change. BSpec
-* requires us to wait up to 150usec, but that leads to timeouts;
-* the 2ms used here is based on experiment.
-*/
- ret = sandybridge_pcode_write_timeout(dev_priv,
- HSW_PCODE_DE_WRITE_FREQ_REQ,
- 0x8000, 150, 2);
- if (ret) {
- DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq
%d)\n",
- ret, cdclk);
- return;
- }
+ if (INTEL_GEN(dev_priv) >= 10) {
+ if (dev_priv->cdclk.hw.vco != 0 &&
+ dev_priv->cdclk.hw.vco != vco)
+ cnl_cdclk_pll_disable(dev_priv);
- if (dev_priv->cdclk.hw.vco != 0 &&
- dev_priv->cdclk.hw.vco != vco)
- bxt_de_pll_disable(dev_priv);
+ if (dev_priv->cdclk.hw.vco != vco)
+
[Intel-gfx] [PATCH 6/8] drm/i915: Add calc_voltage_level display vfunc
With all of the cdclk function consolidation, we can cut down on a lot
of platform if/else logic by creating a vfunc that's initialized at
startup.
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 76 --
drivers/gpu/drm/i915/i915_drv.h| 1 +
2 files changed, 28 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index a70fec82d2bc..a6696697a09f 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1403,18 +1403,8 @@ static void bxt_get_cdclk(struct drm_i915_private
*dev_priv,
* Can't read this out :( Let's assume it's
* at least what the CDCLK frequency requires.
*/
- if (IS_ELKHARTLAKE(dev_priv))
- cdclk_state->voltage_level =
- ehl_calc_voltage_level(cdclk_state->cdclk);
- else if (INTEL_GEN(dev_priv) >= 11)
- cdclk_state->voltage_level =
- icl_calc_voltage_level(cdclk_state->cdclk);
- else if (INTEL_GEN(dev_priv) >= 10)
- cdclk_state->voltage_level =
- cnl_calc_voltage_level(cdclk_state->cdclk);
- else
- cdclk_state->voltage_level =
- bxt_calc_voltage_level(cdclk_state->cdclk);
+ cdclk_state->voltage_level =
+ dev_priv->display.calc_voltage_level(cdclk_state->cdclk);
}
static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
@@ -1681,7 +1671,8 @@ static void bxt_init_cdclk(struct drm_i915_private
*dev_priv)
*/
cdclk_state.cdclk = calc_cdclk(dev_priv, 0);
cdclk_state.vco = calc_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
- cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);
+ cdclk_state.voltage_level =
+ dev_priv->display.calc_voltage_level(cdclk_state.cdclk);
bxt_set_cdclk(dev_priv, _state, INVALID_PIPE);
}
@@ -1692,18 +1683,8 @@ static void bxt_uninit_cdclk(struct drm_i915_private
*dev_priv)
cdclk_state.cdclk = cdclk_state.bypass;
cdclk_state.vco = 0;
- if (IS_ELKHARTLAKE(dev_priv))
- cdclk_state.voltage_level =
- ehl_calc_voltage_level(cdclk_state.cdclk);
- else if (INTEL_GEN(dev_priv) >= 11)
- cdclk_state.voltage_level =
- icl_calc_voltage_level(cdclk_state.cdclk);
- else if (INTEL_GEN(dev_priv) >= 10)
- cdclk_state.voltage_level =
- cnl_calc_voltage_level(cdclk_state.cdclk);
- else
- cdclk_state.voltage_level =
- bxt_calc_voltage_level(cdclk_state.cdclk);
+ cdclk_state.voltage_level =
+ dev_priv->display.calc_voltage_level(cdclk_state.cdclk);
bxt_set_cdclk(dev_priv, _state, INVALID_PIPE);
}
@@ -1739,12 +1720,8 @@ static void icl_init_cdclk(struct drm_i915_private
*dev_priv)
sanitized_state.cdclk = calc_cdclk(dev_priv, 0);
sanitized_state.vco = calc_cdclk_pll_vco(dev_priv,
sanitized_state.cdclk);
- if (IS_ELKHARTLAKE(dev_priv))
- sanitized_state.voltage_level =
- ehl_calc_voltage_level(sanitized_state.cdclk);
- else
- sanitized_state.voltage_level =
- icl_calc_voltage_level(sanitized_state.cdclk);
+ sanitized_state.voltage_level =
+ dev_priv->display.calc_voltage_level(sanitized_state.cdclk);
bxt_set_cdclk(dev_priv, _state, INVALID_PIPE);
}
@@ -1763,7 +1740,8 @@ static void cnl_init_cdclk(struct drm_i915_private
*dev_priv)
cdclk_state.cdclk = calc_cdclk(dev_priv, 0);
cdclk_state.vco = calc_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
- cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
+ cdclk_state.voltage_level =
+ dev_priv->display.calc_voltage_level(cdclk_state.cdclk);
bxt_set_cdclk(dev_priv, _state, INVALID_PIPE);
}
@@ -2255,7 +2233,7 @@ static int bxt_modeset_calc_cdclk(struct
intel_atomic_state *state)
state->cdclk.logical.vco = vco;
state->cdclk.logical.cdclk = cdclk;
state->cdclk.logical.voltage_level =
- bxt_calc_voltage_level(cdclk);
+ dev_priv->display.calc_voltage_level(cdclk);
if (!state->active_pipes) {
cdclk = calc_cdclk(dev_priv, state->cdclk.force_min_cdclk);
@@ -2264,7 +2242,7 @@ static int bxt_modeset_calc_cdclk(struct
intel_atomic_state *state)
state->cdclk.actual.vco = vco;
state->cdclk.actual.cdclk = cdclk;
state->cdclk.actual.voltage_level =
- bxt_calc_voltage_level(cdclk);
+ dev_priv->display.calc_voltage_level(cdclk);
[Intel-gfx] [PATCH 5/8] drm/i915: Consolidate {bxt, cnl, icl}_uninit_cdclk
The uninitialize flow is the same on all of these platforms, aside from
calculating a different frequency level.
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 48 +++---
1 file changed, 14 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index f8c2a706990b..a70fec82d2bc 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1692,7 +1692,18 @@ static void bxt_uninit_cdclk(struct drm_i915_private
*dev_priv)
cdclk_state.cdclk = cdclk_state.bypass;
cdclk_state.vco = 0;
- cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);
+ if (IS_ELKHARTLAKE(dev_priv))
+ cdclk_state.voltage_level =
+ ehl_calc_voltage_level(cdclk_state.cdclk);
+ else if (INTEL_GEN(dev_priv) >= 11)
+ cdclk_state.voltage_level =
+ icl_calc_voltage_level(cdclk_state.cdclk);
+ else if (INTEL_GEN(dev_priv) >= 10)
+ cdclk_state.voltage_level =
+ cnl_calc_voltage_level(cdclk_state.cdclk);
+ else
+ cdclk_state.voltage_level =
+ bxt_calc_voltage_level(cdclk_state.cdclk);
bxt_set_cdclk(dev_priv, _state, INVALID_PIPE);
}
@@ -1738,22 +1749,6 @@ static void icl_init_cdclk(struct drm_i915_private
*dev_priv)
bxt_set_cdclk(dev_priv, _state, INVALID_PIPE);
}
-static void icl_uninit_cdclk(struct drm_i915_private *dev_priv)
-{
- struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
-
- cdclk_state.cdclk = cdclk_state.bypass;
- cdclk_state.vco = 0;
- if (IS_ELKHARTLAKE(dev_priv))
- cdclk_state.voltage_level =
- ehl_calc_voltage_level(cdclk_state.cdclk);
- else
- cdclk_state.voltage_level =
- icl_calc_voltage_level(cdclk_state.cdclk);
-
- bxt_set_cdclk(dev_priv, _state, INVALID_PIPE);
-}
-
static void cnl_init_cdclk(struct drm_i915_private *dev_priv)
{
struct intel_cdclk_state cdclk_state;
@@ -1773,17 +1768,6 @@ static void cnl_init_cdclk(struct drm_i915_private
*dev_priv)
bxt_set_cdclk(dev_priv, _state, INVALID_PIPE);
}
-static void cnl_uninit_cdclk(struct drm_i915_private *dev_priv)
-{
- struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
-
- cdclk_state.cdclk = cdclk_state.bypass;
- cdclk_state.vco = 0;
- cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
-
- bxt_set_cdclk(dev_priv, _state, INVALID_PIPE);
-}
-
/**
* intel_cdclk_init - Initialize CDCLK
* @i915: i915 device
@@ -1814,14 +1798,10 @@ void intel_cdclk_init(struct drm_i915_private *i915)
*/
void intel_cdclk_uninit(struct drm_i915_private *i915)
{
- if (INTEL_GEN(i915) >= 11)
- icl_uninit_cdclk(i915);
- else if (IS_CANNONLAKE(i915))
- cnl_uninit_cdclk(i915);
+ if (IS_GEN9_LP(i915) || INTEL_GEN(i915) >= 10)
+ bxt_uninit_cdclk(i915);
else if (IS_GEN9_BC(i915))
skl_uninit_cdclk(i915);
- else if (IS_GEN9_LP(i915))
- bxt_uninit_cdclk(i915);
}
/**
--
2.20.1
___
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Intel-gfx@lists.freedesktop.org
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[Intel-gfx] [PATCH 2/8] drm/i915: Use literal representation of cdclk tables
The bspec lays out legal cdclk frequencies, PLL ratios, and CD2X
dividers in an easy-to-read table for most recent platforms. We've been
translating the data from that table into platform-specific code logic,
but it's easy to overlook an area we need to update when adding new
cdclk values or enabling new platforms. Let's just add a form of the
bspec table to the code and then adjust our functions to pull what they
need directly out of the table.
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 319 -
drivers/gpu/drm/i915/display/intel_cdclk.h | 8 +
drivers/gpu/drm/i915/i915_drv.h| 4 +
3 files changed, 126 insertions(+), 205 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index e07de3b84cec..8ac31f8775f0 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1161,28 +1161,97 @@ static void skl_uninit_cdclk(struct drm_i915_private
*dev_priv)
skl_set_cdclk(dev_priv, _state, INVALID_PIPE);
}
-static int bxt_calc_cdclk(int min_cdclk)
-{
- if (min_cdclk > 576000)
- return 624000;
- else if (min_cdclk > 384000)
- return 576000;
- else if (min_cdclk > 288000)
- return 384000;
- else if (min_cdclk > 144000)
- return 288000;
- else
- return 144000;
+static const struct intel_cdclk_vals bxt_cdclk_table[] = {
+ { 144000, 8, 60 },
+ { 288000, 4, 60 },
+ { 384000, 3, 60 },
+ { 576000, 2, 60 },
+ { 624000, 2, 65 },
+};
+
+static const struct intel_cdclk_vals glk_cdclk_table[] = {
+ { 79200, 8, 33 },
+ { 158400, 4, 33 },
+ { 316800, 2, 33 },
+};
+
+static const struct intel_cdclk_vals cnl_cdclk_table[] = {
+ { 168000, 4, 35, 28 },
+ { 336000, 2, 35, 28 },
+ { 528000, 2, 55, 44 },
+};
+
+static const struct intel_cdclk_vals icl_cdclk_table[] = {
+ { 172800, 2, 18, 0, 9 },
+ { 18, 2, 0, 15, 0 },
+ { 192000, 2, 20, 16, 10 },
+ { 307200, 2, 32, 0, 16 },
+ { 312000, 2, 0, 26, 0 },
+ { 324000, 4, 0, 54, 0 },
+ { 326400, 4, 68, 0, 34 },
+ { 552000, 2, 0, 46, 0 },
+ { 556800, 2, 58, 0, 29 },
+ { 648000, 2, 0, 54, 0 },
+ { 652800, 2, 68, 0, 34 },
+};
+
+static int calc_cdclk(struct drm_i915_private *dev_priv,
+ int min_cdclk)
+{
+ const struct intel_cdclk_vals *table = dev_priv->cdclk.table;
+ unsigned int ref = dev_priv->cdclk.hw.ref;
+ int best_cdclk = 0;
+ int i;
+
+ if (WARN_ON(ref != 19200 && ref != 24000 && ref != 38400))
+ ref = 19200;
+
+ for (i = 0; i < dev_priv->cdclk.table_size; i++) {
+ if (ref == 19200 && table[i].ratio_19 != 0)
+ best_cdclk = table[i].cdclk;
+ else if (ref == 24000 && table[i].ratio_24 != 0)
+ best_cdclk = table[i].cdclk;
+ else if (ref == 38400 && table[i].ratio_38 != 0)
+ best_cdclk = table[i].cdclk;
+
+ if (table[i].cdclk < min_cdclk)
+ return best_cdclk;
+ }
+
+ WARN(1, "Cannot satisfy minimum cdclk %d\n", min_cdclk);
+ return best_cdclk;
}
-static int glk_calc_cdclk(int min_cdclk)
+static int calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
{
- if (min_cdclk > 158400)
- return 316800;
- else if (min_cdclk > 79200)
- return 158400;
- else
- return 79200;
+ const struct intel_cdclk_vals *table = dev_priv->cdclk.table;
+ int ratio, best_ratio, i;
+
+ if (cdclk == dev_priv->cdclk.hw.bypass)
+ return 0;
+
+ for (i = 0; i < dev_priv->cdclk.table_size; i++) {
+ if (dev_priv->cdclk.hw.ref == 19200)
+ ratio = table[i].ratio_19;
+ else if (dev_priv->cdclk.hw.ref == 24000)
+ ratio = table[i].ratio_24;
+ else
+ ratio = table[i].ratio_38;
+
+ if (ratio == 0)
+ continue;
+ else
+ best_ratio = ratio;
+
+ if (table[i].cdclk == cdclk ||
+ WARN_ON(table[i].cdclk > cdclk))
+ return dev_priv->cdclk.hw.ref * ratio;
+ }
+
+ WARN(1, "cdclk %d not valid for refclk %d\n",
+cdclk, dev_priv->cdclk.hw.ref);
+
+ return dev_priv->cdclk.hw.ref * best_ratio;
}
static u8 bxt_calc_voltage_level(int cdclk)
@@ -1220,52 +1289,6 @@ static u8 ehl_calc_voltage_level(int cdclk)
return 0;
}
-static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
-{
- int ratio;
-
- if (cdclk == dev_priv->cdclk.hw.bypass)
-
[Intel-gfx] [PATCH 4/8] drm/i915: Kill cnl_sanitize_cdclk()
The CNL variant of this function is identical to the BXT variant aside
from not needing to handle SSA precharge.
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 46 +-
1 file changed, 2 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 6b5b1328a3fa..f8c2a706990b 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1645,7 +1645,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private
*dev_priv)
* Disable SSA Precharge when CD clock frequency < 500 MHz,
* enable otherwise.
*/
- if (dev_priv->cdclk.hw.cdclk >= 50)
+ if (IS_GEN9_LP(dev_priv) && dev_priv->cdclk.hw.cdclk >= 50)
expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
if (cdctl == expected)
@@ -1697,48 +1697,6 @@ static void bxt_uninit_cdclk(struct drm_i915_private
*dev_priv)
bxt_set_cdclk(dev_priv, _state, INVALID_PIPE);
}
-static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
-{
- u32 cdctl, expected;
-
- intel_update_cdclk(dev_priv);
- intel_dump_cdclk_state(_priv->cdclk.hw, "Current CDCLK");
-
- if (dev_priv->cdclk.hw.vco == 0 ||
- dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
- goto sanitize;
-
- /* DPLL okay; verify the cdclock
-*
-* Some BIOS versions leave an incorrect decimal frequency value and
-* set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
-* so sanitize this register.
-*/
- cdctl = I915_READ(CDCLK_CTL);
- /*
-* Let's ignore the pipe field, since BIOS could have configured the
-* dividers both synching to an active pipe, or asynchronously
-* (PIPE_NONE).
-*/
- cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
-
- expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
- skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
-
- if (cdctl == expected)
- /* All well; nothing to sanitize */
- return;
-
-sanitize:
- DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
-
- /* force cdclk programming */
- dev_priv->cdclk.hw.cdclk = 0;
-
- /* force full PLL disable + enable */
- dev_priv->cdclk.hw.vco = -1;
-}
-
static void icl_init_cdclk(struct drm_i915_private *dev_priv)
{
struct intel_cdclk_state sanitized_state;
@@ -1800,7 +1758,7 @@ static void cnl_init_cdclk(struct drm_i915_private
*dev_priv)
{
struct intel_cdclk_state cdclk_state;
- cnl_sanitize_cdclk(dev_priv);
+ bxt_sanitize_cdclk(dev_priv);
if (dev_priv->cdclk.hw.cdclk != 0 &&
dev_priv->cdclk.hw.vco != 0)
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 7/8] drm/i915: Enhance cdclk sanitization
When reading out the BIOS-programmed cdclk state, let's make sure that
the cdclk value is on the valid list for the platform, ensure that the
VCO matches the cdclk, and ensure that the CD2X divider was set
properly.
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 34 --
1 file changed, 32 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index a6696697a09f..356495591cf9 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1607,6 +1607,7 @@ static void bxt_set_cdclk(struct drm_i915_private
*dev_priv,
static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
{
u32 cdctl, expected;
+ int cdclk, vco;
intel_update_cdclk(dev_priv);
intel_dump_cdclk_state(_priv->cdclk.hw, "Current CDCLK");
@@ -1629,8 +1630,37 @@ static void bxt_sanitize_cdclk(struct drm_i915_private
*dev_priv)
*/
cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
- expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
- skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
+ /* Make sure this is a legal cdclk value for the platform */
+ cdclk = calc_cdclk(dev_priv, dev_priv->cdclk.hw.cdclk);
+ if (cdclk != dev_priv->cdclk.hw.cdclk)
+ goto sanitize;
+
+ /* Make sure the VCO is correct for the cdclk */
+ vco = calc_cdclk_pll_vco(dev_priv, cdclk);
+ if (vco != dev_priv->cdclk.hw.vco)
+ goto sanitize;
+
+ expected = skl_cdclk_decimal(cdclk);
+
+ /* Figure out what CD2X divider we should be using for this cdclk */
+ switch (DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.vco,
+ dev_priv->cdclk.hw.cdclk)) {
+ case 2:
+ expected |= BXT_CDCLK_CD2X_DIV_SEL_1;
+ break;
+ case 3:
+ expected |= BXT_CDCLK_CD2X_DIV_SEL_1_5;
+ break;
+ case 4:
+ expected |= BXT_CDCLK_CD2X_DIV_SEL_2;
+ break;
+ case 8:
+ expected |= BXT_CDCLK_CD2X_DIV_SEL_4;
+ break;
+ default:
+ goto sanitize;
+ }
+
/*
* Disable SSA Precharge when CD clock frequency < 500 MHz,
* enable otherwise.
--
2.20.1
___
Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 8/8] drm/i915: Consolidate {bxt, cnl, icl}_init_cdclk
The BXT and CNL functions were already basically identical, whereas
ICL's function tried to do its own sanitization rather than calling
bxt_sanitize_cdclk.
This should actually fix a bug in our ICL initialization where it would
consider the /2 CD2X divider invalid and force an unnecessary
sanitization (we now have valid clock frequencies that use this
divider).
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 65 +-
1 file changed, 2 insertions(+), 63 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 356495591cf9..0ad83d67932d 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1719,63 +1719,6 @@ static void bxt_uninit_cdclk(struct drm_i915_private
*dev_priv)
bxt_set_cdclk(dev_priv, _state, INVALID_PIPE);
}
-static void icl_init_cdclk(struct drm_i915_private *dev_priv)
-{
- struct intel_cdclk_state sanitized_state;
- u32 val;
-
- /* This sets dev_priv->cdclk.hw. */
- intel_update_cdclk(dev_priv);
- intel_dump_cdclk_state(_priv->cdclk.hw, "Current CDCLK");
-
- /* This means CDCLK disabled. */
- if (dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
- goto sanitize;
-
- val = I915_READ(CDCLK_CTL);
-
- if ((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0)
- goto sanitize;
-
- if ((val & CDCLK_FREQ_DECIMAL_MASK) !=
- skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk))
- goto sanitize;
-
- return;
-
-sanitize:
- DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
-
- sanitized_state.ref = dev_priv->cdclk.hw.ref;
- sanitized_state.cdclk = calc_cdclk(dev_priv, 0);
- sanitized_state.vco = calc_cdclk_pll_vco(dev_priv,
-sanitized_state.cdclk);
- sanitized_state.voltage_level =
- dev_priv->display.calc_voltage_level(sanitized_state.cdclk);
-
- bxt_set_cdclk(dev_priv, _state, INVALID_PIPE);
-}
-
-static void cnl_init_cdclk(struct drm_i915_private *dev_priv)
-{
- struct intel_cdclk_state cdclk_state;
-
- bxt_sanitize_cdclk(dev_priv);
-
- if (dev_priv->cdclk.hw.cdclk != 0 &&
- dev_priv->cdclk.hw.vco != 0)
- return;
-
- cdclk_state = dev_priv->cdclk.hw;
-
- cdclk_state.cdclk = calc_cdclk(dev_priv, 0);
- cdclk_state.vco = calc_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
- cdclk_state.voltage_level =
- dev_priv->display.calc_voltage_level(cdclk_state.cdclk);
-
- bxt_set_cdclk(dev_priv, _state, INVALID_PIPE);
-}
-
/**
* intel_cdclk_init - Initialize CDCLK
* @i915: i915 device
@@ -1787,14 +1730,10 @@ static void cnl_init_cdclk(struct drm_i915_private
*dev_priv)
*/
void intel_cdclk_init(struct drm_i915_private *i915)
{
- if (INTEL_GEN(i915) >= 11)
- icl_init_cdclk(i915);
- else if (IS_CANNONLAKE(i915))
- cnl_init_cdclk(i915);
+ if (IS_GEN9_LP(i915) || INTEL_GEN(i915) >= 10)
+ bxt_init_cdclk(i915);
else if (IS_GEN9_BC(i915))
skl_init_cdclk(i915);
- else if (IS_GEN9_LP(i915))
- bxt_init_cdclk(i915);
}
/**
--
2.20.1
___
Intel-gfx mailing list
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[Intel-gfx] [PATCH 0/8] cdclk consolidation and rework for BXT-TGL
cdclk design hasn't changed much from BXT onward, but we still have
a lot of different codepaths to handle the different platforms and in
some cases they've evolved in different directions. Let's try to
consolidate some of the common logic where it makes sense.
We also have some functions that are basically code repesentations of
tables in the bspec. As new cdclk values get added/removed from the
bspec over time, or new platforms get enabled, it's easy to overlook
some of the places that we need to update various functions to reflect
those changes. Let's try to address this by including a more literal
representation of the bspec tables in the driver and adapting our driver
to parse those tables to get the values they need.
Cc: Ville Syrjälä
Matt Roper (8):
drm/i915: Consolidate bxt/cnl/icl cdclk readout
drm/i915: Use literal representation of cdclk tables
drm/i915: Combine bxt_set_cdclk and cnl_set_cdclk
drm/i915: Kill cnl_sanitize_cdclk()
drm/i915: Consolidate {bxt,cnl,icl}_uninit_cdclk
drm/i915: Add calc_voltage_level display vfunc
drm/i915: Enhance cdclk sanitization
drm/i915: Consolidate {bxt,cnl,icl}_init_cdclk
drivers/gpu/drm/i915/display/intel_cdclk.c | 977 -
drivers/gpu/drm/i915/display/intel_cdclk.h | 8 +
drivers/gpu/drm/i915/i915_drv.h| 5 +
3 files changed, 358 insertions(+), 632 deletions(-)
--
2.20.1
___
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Re: [Intel-gfx] [PATCH v15 06/13] drm/i915/perf: move perf types to their own header
Hi Lionel, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on drm-intel/for-linux-next] [cannot apply to v5.3-rc7 next-20190904] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Lionel-Landwerlin/drm-i915-Vulkan-performance-query-support/20190907-052009 base: git://anongit.freedesktop.org/drm-intel for-linux-next reproduce: make htmldocs If you fix the issue, kindly add following tag Reported-by: kbuild test robot All warnings (new ones prefixed by >>): include/net/sock.h:233: warning: Function parameter or member 'skc_ipv6only' not described in 'sock_common' include/net/sock.h:233: warning: Function parameter or member 'skc_net_refcnt' not described in 'sock_common' include/net/sock.h:233: warning: Function parameter or member 'skc_v6_daddr' not described in 'sock_common' include/net/sock.h:233: warning: Function parameter or member 'skc_v6_rcv_saddr' not described in 'sock_common' include/net/sock.h:233: warning: Function parameter or member 'skc_cookie' not described in 'sock_common' include/net/sock.h:233: warning: Function parameter or member 'skc_listener' not described in 'sock_common' include/net/sock.h:233: warning: Function parameter or member 'skc_tw_dr' not described in 'sock_common' include/net/sock.h:233: warning: Function parameter or member 'skc_rcv_wnd' not described in 'sock_common' include/net/sock.h:233: warning: Function parameter or member 'skc_tw_rcv_nxt' not described in 'sock_common' include/net/sock.h:515: warning: Function parameter or member 'sk_rx_skb_cache' not described in 'sock' include/net/sock.h:515: warning: Function parameter or member 'sk_wq_raw' not described in 'sock' include/net/sock.h:515: warning: Function parameter or member 'tcp_rtx_queue' not described in 'sock' include/net/sock.h:515: warning: Function parameter or member 'sk_tx_skb_cache' not described in 'sock' include/net/sock.h:515: warning: Function parameter or member 'sk_route_forced_caps' not described in 'sock' include/net/sock.h:515: warning: Function parameter or member 'sk_txtime_report_errors' not described in 'sock' include/net/sock.h:515: warning: Function parameter or member 'sk_validate_xmit_skb' not described in 'sock' include/net/sock.h:515: warning: Function parameter or member 'sk_bpf_storage' not described in 'sock' include/net/sock.h:2439: warning: Function parameter or member 'tcp_rx_skb_cache_key' not described in 'DECLARE_STATIC_KEY_FALSE' include/net/sock.h:2439: warning: Excess function parameter 'sk' description in 'DECLARE_STATIC_KEY_FALSE' include/net/sock.h:2439: warning: Excess function parameter 'skb' description in 'DECLARE_STATIC_KEY_FALSE' include/linux/netdevice.h:2040: warning: Function parameter or member 'gso_partial_features' not described in 'net_device' include/linux/netdevice.h:2040: warning: Function parameter or member 'l3mdev_ops' not described in 'net_device' include/linux/netdevice.h:2040: warning: Function parameter or member 'xfrmdev_ops' not described in 'net_device' include/linux/netdevice.h:2040: warning: Function parameter or member 'tlsdev_ops' not described in 'net_device' include/linux/netdevice.h:2040: warning: Function parameter or member 'name_assign_type' not described in 'net_device' include/linux/netdevice.h:2040: warning: Function parameter or member 'ieee802154_ptr' not described in 'net_device' include/linux/netdevice.h:2040: warning: Function parameter or member 'mpls_ptr' not described in 'net_device' include/linux/netdevice.h:2040: warning: Function parameter or member 'xdp_prog' not described in 'net_device' include/linux/netdevice.h:2040: warning: Function parameter or member 'gro_flush_timeout' not described in 'net_device' include/linux/netdevice.h:2040: warning: Function parameter or member 'nf_hooks_ingress' not described in 'net_device' include/linux/netdevice.h:2040: warning: Function parameter or member 'cacheline_aligned_in_smp' not described in 'net_device' include/linux/netdevice.h:2040: warning: Function parameter or member 'qdisc_hash' not described in 'net_device' include/linux/netdevice.h:2040: warning: Function parameter or member 'xps_cpus_map' not described in 'net_device' include/linux/netdevice.h:2040: warning: Function parameter or member 'xps_rxqs_map' not described in 'net_device' include/linux/phylink.h:56: warning: Function parameter or member '__ETHTOOL_DECLARE_LINK_MODE_MASK(advertising' not described in 'phylink_link_state' include/linux/phylink.h:56: warning: Function parameter or member '__ETHTOOL_DECLARE_LINK_MODE_MASK(lp_advertising' not described in 'phylink_link_state' drivers/net/phy/phylink.c:593: warning: Function parameter or member 'config' not described in 'phylink_create' drivers/net/phy/phylink.c:593:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Implement Wa_1409142259
== Series Details ==
Series: drm/i915/tgl: Implement Wa_1409142259
URL : https://patchwork.freedesktop.org/series/66364/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6848 -> Patchwork_14307
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14307/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14307:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_suspend@basic-s3:
- {fi-tgl-u}: NOTRUN -> [DMESG-WARN][1] +1 similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14307/fi-tgl-u/igt@gem_exec_susp...@basic-s3.html
* igt@gem_sync@basic-all:
- {fi-tgl-u}: NOTRUN -> [INCOMPLETE][2]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14307/fi-tgl-u/igt@gem_s...@basic-all.html
Known issues
Here are the changes found in Patchwork_14307 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_param@basic:
- fi-apl-guc: [PASS][3] -> [INCOMPLETE][4] ([fdo#103927])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6848/fi-apl-guc/igt@gem_ctx_pa...@basic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14307/fi-apl-guc/igt@gem_ctx_pa...@basic.html
* igt@kms_chamelium@dp-edid-read:
- fi-kbl-7500u: [PASS][5] -> [WARN][6] ([fdo#109483])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6848/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14307/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- fi-icl-u3: [INCOMPLETE][7] ([fdo#107713] / [fdo#109100]) ->
[PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6848/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14307/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html
* igt@kms_busy@basic-flip-c:
- {fi-icl-u4}:[DMESG-WARN][9] ([fdo#105602]) -> [PASS][10] +5
similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6848/fi-icl-u4/igt@kms_b...@basic-flip-c.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14307/fi-icl-u4/igt@kms_b...@basic-flip-c.html
* igt@kms_chamelium@dp-crc-fast:
- fi-icl-u2: [FAIL][11] ([fdo#109635 ] / [fdo#110387]) ->
[PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6848/fi-icl-u2/igt@kms_chamel...@dp-crc-fast.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14307/fi-icl-u2/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_chamelium@hdmi-edid-read:
- {fi-icl-u4}:[FAIL][13] ([fdo#111045]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6848/fi-icl-u4/igt@kms_chamel...@hdmi-edid-read.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14307/fi-icl-u4/igt@kms_chamel...@hdmi-edid-read.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][15] ([fdo#111096]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6848/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14307/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@prime_vgem@basic-fence-flip:
- fi-ilk-650: [DMESG-WARN][17] ([fdo#106387]) -> [PASS][18] +1
similar issue
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6848/fi-ilk-650/igt@prime_v...@basic-fence-flip.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14307/fi-ilk-650/igt@prime_v...@basic-fence-flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=106387
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#110387]: https://bugs.freedesktop.org/show_bug.cgi?id=110387
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111049]: https://bugs.freedesktop.org/show_bug.cgi?id=111049
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#55]: https://bugs.freedesktop.org/show_bug.cgi?id=55
Participating hosts (50 -> 44)
--
Additional (2): fi-kbl-soraka
Re: [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1409142259
On 9/6/19 3:41 PM, Radhakrishna Sripada wrote:
Disable CPS aware color pipe by setting chicken bit.
BSpec: 52890
HSDES: 1409142259
Cc: Stuart Summers
Cc: Matt Roper
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 243d3f77be13..14e3f9677b06 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -894,6 +894,11 @@ icl_gt_workarounds_init(struct drm_i915_private *i915,
struct i915_wa_list *wal)
static void
tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list
*wal)
{
+ wa_init_mcr(i915, wal);
this is not part of the WA you're trying to apply, right?
+
+ /* Wa_1409142259 */
+ WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
+ GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
AFAICS the register is part of the render context, so shouldn't we set
this as part of the ctx_workarounds? that's what we do for another WA on
the same register on ICL.
Daniele
}
static void
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 006cffd56be2..53e07882efb7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7668,6 +7668,7 @@ enum {
#define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
#define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC (1 << 11)
+ #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE (1 << 9)
#define HIZ_CHICKEN _MMIO(0x7018)
# define CHV_HZ_8X8_MODE_IN_1X(1 << 15)
___
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[Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1409142259
Disable CPS aware color pipe by setting chicken bit.
BSpec: 52890
HSDES: 1409142259
Cc: Stuart Summers
Cc: Matt Roper
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 243d3f77be13..14e3f9677b06 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -894,6 +894,11 @@ icl_gt_workarounds_init(struct drm_i915_private *i915,
struct i915_wa_list *wal)
static void
tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list
*wal)
{
+ wa_init_mcr(i915, wal);
+
+ /* Wa_1409142259 */
+ WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
+ GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
}
static void
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 006cffd56be2..53e07882efb7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7668,6 +7668,7 @@ enum {
#define GEN11_COMMON_SLICE_CHICKEN3_MMIO(0x7304)
#define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC (1 << 11)
+ #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE (1 << 9)
#define HIZ_CHICKEN_MMIO(0x7018)
# define CHV_HZ_8X8_MODE_IN_1X (1 << 15)
--
2.20.1
___
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Re: [Intel-gfx] [PATCH] drm/i915: Don't unwedge if reset is disabled
On 9/5/19 2:09 AM, Janusz Krzysztofik wrote:
When trying to reset a device with reset capability disabled or not
supported while rings are full of requests, it has been observed when
running in execlists submission mode that command stream buffer tail
tends to be incremented by apparently still running GPU regardless of
all requests being already cancelled and command stream buffer pointers
reset. As a result, kernel panic on NULL pointer dereference occurs
when a trace_ports() helper is called with command stream buffer tail
incremented but request pointers being NULL during final
__intel_gt_set_wedged() operation called from intel_gt_reset().
Skip actual reset procedure if reset is disabled or not supported.
This last sentence is a bit confusing. You're not skipping the reset
procedure, you're skipping the attempt of unwedging and resetting again
after a reset & wedge already happened.
Suggested-by: Daniele Ceraolo Spurio
Signed-off-by: Janusz Krzysztofik
---
drivers/gpu/drm/i915/gt/intel_reset.c | 26 ++
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
b/drivers/gpu/drm/i915/gt/intel_reset.c
index b9d84d52e986..d75da124e280 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -932,25 +932,35 @@ void intel_gt_reset(struct intel_gt *gt,
GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, >reset.flags));
mutex_lock(>reset.mutex);
- /* Clear any previous failed attempts at recovery. Time to try again. */
- if (!__intel_gt_unset_wedged(gt))
- goto unlock;
-
Since you're anyway checking the wedged status and reset support
multiple times, wouldn't it have been better to just add a single check
at the beginning? e.g.
/* we can't recover a wedged GT without reset */
if (!intel_has_gpu_reset(gt->i915) && intel_gt_is_wedged(gt))
goto unlock;
Daniele
if (reason)
dev_notice(gt->i915->drm.dev,
"Resetting chip for %s\n", reason);
- atomic_inc(>i915->gpu_error.reset_count);
-
- awake = reset_prepare(gt);
if (!intel_has_gpu_reset(gt->i915)) {
if (i915_modparams.reset)
dev_err(gt->i915->drm.dev, "GPU reset not supported\n");
else
DRM_DEBUG_DRIVER("GPU reset disabled\n");
- goto error;
+
+ /*
+* Don't unwedge if reset is disabled or not supported
+* because we can't guarantee what the hardware status is.
+*/
+ if (intel_gt_is_wedged(gt))
+ goto unlock;
}
+ /* Clear any previous failed attempts at recovery. Time to try again. */
+ if (!__intel_gt_unset_wedged(gt))
+ goto unlock;
+
+ atomic_inc(>i915->gpu_error.reset_count);
+
+ awake = reset_prepare(gt);
+
+ if (!intel_has_gpu_reset(gt->i915))
+ goto error;
+
if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
intel_runtime_pm_disable_interrupts(gt->i915);
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Add more debug information to dp aux code
== Series Details == Series: drm/i915: Add more debug information to dp aux code URL : https://patchwork.freedesktop.org/series/66343/ State : success == Summary == CI Bug Log - changes from CI_DRM_6844_full -> Patchwork_14305_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14305_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_balancer@semaphore: - shard-apl: [PASS][1] -> [INCOMPLETE][2] ([fdo#103927]) +3 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6844/shard-apl6/igt@gem_exec_balan...@semaphore.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14305/shard-apl3/igt@gem_exec_balan...@semaphore.html * igt@gem_exec_reloc@basic-wc-cpu-active: - shard-skl: [PASS][3] -> [DMESG-WARN][4] ([fdo#106107]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6844/shard-skl10/igt@gem_exec_re...@basic-wc-cpu-active.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14305/shard-skl1/igt@gem_exec_re...@basic-wc-cpu-active.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6844/shard-iclb5/igt@gem_exec_sched...@preempt-other-chain-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14305/shard-iclb4/igt@gem_exec_sched...@preempt-other-chain-bsd.html * igt@gem_tiled_swapping@non-threaded: - shard-glk: [PASS][7] -> [DMESG-WARN][8] ([fdo#108686]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6844/shard-glk6/igt@gem_tiled_swapp...@non-threaded.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14305/shard-glk4/igt@gem_tiled_swapp...@non-threaded.html * igt@kms_busy@extended-modeset-hang-newfb-render-c: - shard-iclb: [PASS][9] -> [INCOMPLETE][10] ([fdo#107713]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6844/shard-iclb7/igt@kms_b...@extended-modeset-hang-newfb-render-c.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14305/shard-iclb1/igt@kms_b...@extended-modeset-hang-newfb-render-c.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic: - shard-hsw: [PASS][11] -> [FAIL][12] ([fdo#105767]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6844/shard-hsw4/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-atomic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14305/shard-hsw1/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-atomic.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-hsw: [PASS][13] -> [INCOMPLETE][14] ([fdo#103540]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6844/shard-hsw1/igt@kms_f...@flip-vs-suspend-interruptible.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14305/shard-hsw1/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-apl: [PASS][15] -> [DMESG-WARN][16] ([fdo#108566]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6844/shard-apl6/igt@kms_frontbuffer_track...@fbc-suspend.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14305/shard-apl1/igt@kms_frontbuffer_track...@fbc-suspend.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite: - shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103167]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6844/shard-iclb8/igt@kms_frontbuffer_track...@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14305/shard-iclb1/igt@kms_frontbuffer_track...@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite.html * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6844/shard-skl5/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14305/shard-skl7/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145] / [fdo#110403]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6844/shard-skl6/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14305/shard-skl9/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html * igt@kms_psr@psr2_primary_page_flip: - shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6844/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html [24]:
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Use engine relative LRIs on context setup (rev3)
== Series Details == Series: series starting with [1/2] drm/i915: Use engine relative LRIs on context setup (rev3) URL : https://patchwork.freedesktop.org/series/66335/ State : success == Summary == CI Bug Log - changes from CI_DRM_6844_full -> Patchwork_14304_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14304_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_switch@bcs0-heavy-queue: - shard-apl: [PASS][1] -> [INCOMPLETE][2] ([fdo#103927]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6844/shard-apl4/igt@gem_ctx_swi...@bcs0-heavy-queue.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14304/shard-apl5/igt@gem_ctx_swi...@bcs0-heavy-queue.html * igt@gem_exec_schedule@preemptive-hang-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#111325]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6844/shard-iclb3/igt@gem_exec_sched...@preemptive-hang-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14304/shard-iclb2/igt@gem_exec_sched...@preemptive-hang-bsd.html * igt@gem_exec_suspend@basic-s3: - shard-apl: [PASS][5] -> [FAIL][6] ([fdo#103375]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6844/shard-apl7/igt@gem_exec_susp...@basic-s3.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14304/shard-apl1/igt@gem_exec_susp...@basic-s3.html * igt@i915_pm_rc6_residency@rc6-accuracy: - shard-kbl: [PASS][7] -> [SKIP][8] ([fdo#109271]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6844/shard-kbl6/igt@i915_pm_rc6_reside...@rc6-accuracy.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14304/shard-kbl2/igt@i915_pm_rc6_reside...@rc6-accuracy.html * igt@i915_suspend@fence-restore-untiled: - shard-snb: [PASS][9] -> [FAIL][10] ([fdo#103375]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6844/shard-snb6/igt@i915_susp...@fence-restore-untiled.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14304/shard-snb4/igt@i915_susp...@fence-restore-untiled.html * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: - shard-glk: [PASS][11] -> [FAIL][12] ([fdo#105363]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6844/shard-glk1/igt@kms_f...@2x-flip-vs-expired-vblank-interruptible.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14304/shard-glk8/igt@kms_f...@2x-flip-vs-expired-vblank-interruptible.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#105363]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6844/shard-skl10/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14304/shard-skl9/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_flip@flip-vs-suspend: - shard-hsw: [PASS][15] -> [INCOMPLETE][16] ([fdo#103540]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6844/shard-hsw2/igt@kms_f...@flip-vs-suspend.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14304/shard-hsw1/igt@kms_f...@flip-vs-suspend.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-snb: [PASS][17] -> [INCOMPLETE][18] ([fdo#105411]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6844/shard-snb6/igt@kms_f...@flip-vs-suspend-interruptible.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14304/shard-snb1/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw: - shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103167]) +4 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6844/shard-iclb1/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14304/shard-iclb8/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-apl: [PASS][21] -> [DMESG-WARN][22] ([fdo#108566]) +5 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6844/shard-apl6/igt@kms_frontbuffer_track...@fbc-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14304/shard-apl3/igt@kms_frontbuffer_track...@fbc-suspend.html - shard-skl: [PASS][23] -> [INCOMPLETE][24] ([fdo#104108]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6844/shard-skl7/igt@kms_frontbuffer_track...@fbc-suspend.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14304/shard-skl8/igt@kms_frontbuffer_track...@fbc-suspend.html * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [PASS][25] -> [FAIL][26] ([fdo#108145])
[Intel-gfx] ✓ Fi.CI.BAT: success for HuC updates (rev2)
== Series Details == Series: HuC updates (rev2) URL : https://patchwork.freedesktop.org/series/66361/ State : success == Summary == CI Bug Log - changes from CI_DRM_6848 -> Patchwork_14306 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14306/ Known issues Here are the changes found in Patchwork_14306 that come from known issues: ### IGT changes ### Possible fixes * igt@gem_ctx_create@basic-files: - fi-icl-u3: [INCOMPLETE][1] ([fdo#107713] / [fdo#109100]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6848/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14306/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html * igt@kms_chamelium@dp-crc-fast: - fi-icl-u2: [FAIL][3] ([fdo#109635 ] / [fdo#110387]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6848/fi-icl-u2/igt@kms_chamel...@dp-crc-fast.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14306/fi-icl-u2/igt@kms_chamel...@dp-crc-fast.html * igt@prime_vgem@basic-fence-flip: - fi-ilk-650: [DMESG-WARN][5] ([fdo#106387]) -> [PASS][6] +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6848/fi-ilk-650/igt@prime_v...@basic-fence-flip.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14306/fi-ilk-650/igt@prime_v...@basic-fence-flip.html Warnings * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][7] ([fdo#111096]) -> [FAIL][8] ([fdo#111407]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6848/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14306/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=106387 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100 [fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635 [fdo#110387]: https://bugs.freedesktop.org/show_bug.cgi?id=110387 [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407 Participating hosts (50 -> 44) -- Additional (2): fi-kbl-soraka fi-tgl-u Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_6848 -> Patchwork_14306 CI-20190529: 20190529 CI_DRM_6848: a1769d05ffa7fe6e4481131e97215f37b8f5ed4e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5172: 073caf4acb7cac63abe7a5e1409ea27a764db5fd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_14306: d7b6d41814a6bc898ccf3804b4ca24518d8392e9 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == d7b6d41814a6 HAX: force enable_guc=2 3e74b63d4f55 drm/i915/firmware: Load v4.0.0 HuC for CML ef1541d9e17d drm/i915/firmware: Load v9.0.0 HuC for ICL df9774489411 drm/i915/firmware: CFL uses KBL firmware 797d4388aaba drm/i915/firmware: Load v4.0.0 HuC for GLK 7e5d47bb5187 drm/i915/firmware: Load v4.0.0 HuC for KBL 449762fd3f47 drm/i915/firmware: Load v2.0.0 HuC for BXT b5c155bdb7e8 drm/i915/firmware: Load v2.0.0 HuC for SKL 1d66bb74507d drm/i915/uc: Update MAKE_HUC_FW_PATH macro == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14306/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/9] drm/i915/uc: Update MAKE_HUC_FW_PATH macro
On 9/6/19 12:47 PM, Anusha Srivatsa wrote: Update MAKE_HUC_FW_PATH macro to follow the same convention as the MAKE_GUC_FW_PATH with the separator changing from "_" to "." and removing "ver". The current convention being: _uc_..patch.bin Suggested-by: Daniele Ceraolo Spurio Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c index 296a82603be0..16a5aa8fe15a 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c @@ -58,7 +58,7 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw, __MAKE_UC_FW_PATH(prefix_, "_guc_", ".", major_, minor_, patch_) #define MAKE_HUC_FW_PATH(prefix_, major_, minor_, bld_num_) \ - __MAKE_UC_FW_PATH(prefix_, "_huc_ver", "_", major_, minor_, bld_num_) + __MAKE_UC_FW_PATH(prefix_, "_huc_", ".", major_, minor_, bld_num_) Since the format is now the same between GuC and HuC we can stop passing the separator to __MAKE_UC_FW_PATH and just harcode "." in there. Daniele /* All blobs need to be declared via MODULE_FIRMWARE() */ #define INTEL_UC_MODULE_FW(platform_, revid_, guc_, huc_) \ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 0/9] HuC updates
On 9/6/19 12:47 PM, Anusha Srivatsa wrote: Updating HuC versions for gen9 and ICL platforms. Also updating MAKE_HUC_FW_PATH. The whole series needs to be squashed in a single patch, otherwise it won't work in the middle. Also, need to add a renamed EHL blob in the FW repo as well. I'm assuming that since we never actually shipped the EHL blob outside of our CI it is going to be ok if we break naming compatibility with older kernels, but if you want to be safe you can just add a link for it instead. Daniele From now on we can have same firmware name formats for both guC and HuC. Adding the new PR for the same: The following changes since commit 6ddb9d9704e2171d91439c9c42c5965bf3863de8: Merge branch 'for-upstream' of git://git.chelsio.net/pub/git/linux-firmware (2019-09-04 07:13:26 -0400) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-firmware huc_updates for you to fetch changes up to 02850d2cc1fe542b7f320cedc446cfefb92c083a: drm/i915/firmware: Add v9.0.0 of HuC for Icelake (2019-09-06 12:23:56 -0700) Anusha Srivatsa (6): drm/i915/firmware: Add v2.0.0 of HuC for Skylake drm/i915/firmware: Add v4.0.0 of HuC for Kabylake drm/i915/firmware: Add v2.0.0 of HuC for Broxton drm/i915/firmware: Add v4.0.0 of HuC for Geminilake drm/i915/firmware: Add v4.0.0 of HuC for Cometlake drm/i915/firmware: Add v9.0.0 of HuC for Icelake WHENCE | 19 +++ i915/bxt_huc_2.0.0.bin | Bin 0 -> 149824 bytes i915/cml_huc_4.0.0.bin | Bin 0 -> 226048 bytes i915/glk_huc_4.0.0.bin | Bin 0 -> 226048 bytes i915/icl_huc_9.0.0.bin | Bin 0 -> 498880 bytes i915/kbl_huc_4.0.0.bin | Bin 0 -> 226048 bytes i915/skl_huc_2.0.0.bin | Bin 0 -> 136320 bytes 7 files changed, 19 insertions(+) create mode 100644 i915/bxt_huc_2.0.0.bin create mode 100644 i915/cml_huc_4.0.0.bin create mode 100644 i915/glk_huc_4.0.0.bin create mode 100644 i915/icl_huc_9.0.0.bin create mode 100644 i915/kbl_huc_4.0.0.bin create mode 100644 i915/skl_huc_2.0.0.bin Anusha Srivatsa (9): drm/i915/uc: Update MAKE_HUC_FW_PATH macro drm/i915/firmware: Load v2.0.0 HuC for SKL drm/i915/firmware: Load v2.0.0 HuC for BXT drm/i915/firmware: Load v4.0.0 HuC for KBL drm/i915/firmware: Load v4.0.0 HuC for GLK drm/i915/firmware: CFL uses KBL firmware drm/i915/firmware: Load v9.0.0 HuC for ICL drm/i915/firmware: Load v4.0.0 HuC for CML HAX: force enable_guc=2 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 15 --- drivers/gpu/drm/i915/i915_params.h | 2 +- 2 files changed, 9 insertions(+), 8 deletions(-) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for HuC updates (rev2)
== Series Details == Series: HuC updates (rev2) URL : https://patchwork.freedesktop.org/series/66361/ State : warning == Summary == $ dim checkpatch origin/drm-tip 1d66bb74507d drm/i915/uc: Update MAKE_HUC_FW_PATH macro b5c155bdb7e8 drm/i915/firmware: Load v2.0.0 HuC for SKL 449762fd3f47 drm/i915/firmware: Load v2.0.0 HuC for BXT 7e5d47bb5187 drm/i915/firmware: Load v4.0.0 HuC for KBL 797d4388aaba drm/i915/firmware: Load v4.0.0 HuC for GLK df9774489411 drm/i915/firmware: CFL uses KBL firmware ef1541d9e17d drm/i915/firmware: Load v9.0.0 HuC for ICL 3e74b63d4f55 drm/i915/firmware: Load v4.0.0 HuC for CML d7b6d41814a6 HAX: force enable_guc=2 -:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one total: 0 errors, 1 warnings, 0 checks, 8 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/9] HuC updates
Updating HuC versions for gen9 and ICL platforms. Also updating MAKE_HUC_FW_PATH. From now on we can have same firmware name formats for both guC and HuC. Adding the new PR for the same: The following changes since commit 6ddb9d9704e2171d91439c9c42c5965bf3863de8: Merge branch 'for-upstream' of git://git.chelsio.net/pub/git/linux-firmware (2019-09-04 07:13:26 -0400) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-firmware huc_updates for you to fetch changes up to 02850d2cc1fe542b7f320cedc446cfefb92c083a: drm/i915/firmware: Add v9.0.0 of HuC for Icelake (2019-09-06 12:23:56 -0700) Anusha Srivatsa (6): drm/i915/firmware: Add v2.0.0 of HuC for Skylake drm/i915/firmware: Add v4.0.0 of HuC for Kabylake drm/i915/firmware: Add v2.0.0 of HuC for Broxton drm/i915/firmware: Add v4.0.0 of HuC for Geminilake drm/i915/firmware: Add v4.0.0 of HuC for Cometlake drm/i915/firmware: Add v9.0.0 of HuC for Icelake WHENCE | 19 +++ i915/bxt_huc_2.0.0.bin | Bin 0 -> 149824 bytes i915/cml_huc_4.0.0.bin | Bin 0 -> 226048 bytes i915/glk_huc_4.0.0.bin | Bin 0 -> 226048 bytes i915/icl_huc_9.0.0.bin | Bin 0 -> 498880 bytes i915/kbl_huc_4.0.0.bin | Bin 0 -> 226048 bytes i915/skl_huc_2.0.0.bin | Bin 0 -> 136320 bytes 7 files changed, 19 insertions(+) create mode 100644 i915/bxt_huc_2.0.0.bin create mode 100644 i915/cml_huc_4.0.0.bin create mode 100644 i915/glk_huc_4.0.0.bin create mode 100644 i915/icl_huc_9.0.0.bin create mode 100644 i915/kbl_huc_4.0.0.bin create mode 100644 i915/skl_huc_2.0.0.bin Anusha Srivatsa (9): drm/i915/uc: Update MAKE_HUC_FW_PATH macro drm/i915/firmware: Load v2.0.0 HuC for SKL drm/i915/firmware: Load v2.0.0 HuC for BXT drm/i915/firmware: Load v4.0.0 HuC for KBL drm/i915/firmware: Load v4.0.0 HuC for GLK drm/i915/firmware: CFL uses KBL firmware drm/i915/firmware: Load v9.0.0 HuC for ICL drm/i915/firmware: Load v4.0.0 HuC for CML HAX: force enable_guc=2 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 15 --- drivers/gpu/drm/i915/i915_params.h | 2 +- 2 files changed, 9 insertions(+), 8 deletions(-) -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 7/9] drm/i915/firmware: Load v9.0.0 HuC for ICL
Add support to load the latest version of HuC on ICL. Cc: Daniele Ceraolo Spurio Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c index 2614f36934e5..5994a41f47a8 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c @@ -40,7 +40,7 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw, */ #define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \ fw_def(ELKHARTLAKE, 0, guc_def(ehl, 33, 0, 4), huc_def(ehl, 9, 0, 0)) \ - fw_def(ICELAKE, 0, guc_def(icl, 33, 0, 0), huc_def(icl, 8, 4, 3238)) \ + fw_def(ICELAKE, 0, guc_def(icl, 33, 0, 0), huc_def(icl, 9, 0, 0)) \ fw_def(COFFEELAKE, 0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 4, 0, 0)) \ fw_def(GEMINILAKE, 0, guc_def(glk, 33, 0, 0), huc_def(glk, 4, 0, 0)) \ fw_def(KABYLAKE,0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 4, 0, 0)) \ -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/9] drm/i915/uc: Update MAKE_HUC_FW_PATH macro
Update MAKE_HUC_FW_PATH macro to follow the same convention as the MAKE_GUC_FW_PATH with the separator changing from "_" to "." and removing "ver". The current convention being: _uc_..patch.bin Suggested-by: Daniele Ceraolo Spurio Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c index 296a82603be0..16a5aa8fe15a 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c @@ -58,7 +58,7 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw, __MAKE_UC_FW_PATH(prefix_, "_guc_", ".", major_, minor_, patch_) #define MAKE_HUC_FW_PATH(prefix_, major_, minor_, bld_num_) \ - __MAKE_UC_FW_PATH(prefix_, "_huc_ver", "_", major_, minor_, bld_num_) + __MAKE_UC_FW_PATH(prefix_, "_huc_", ".", major_, minor_, bld_num_) /* All blobs need to be declared via MODULE_FIRMWARE() */ #define INTEL_UC_MODULE_FW(platform_, revid_, guc_, huc_) \ -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 9/9] HAX: force enable_guc=2
Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/i915_params.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index d29ade3b7de6..f9fbb1f2fabf 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -54,7 +54,7 @@ struct drm_printer; param(int, disable_power_well, -1) \ param(int, enable_ips, 1) \ param(int, invert_brightness, 0) \ - param(int, enable_guc, 0) \ + param(int, enable_guc, 2) \ param(int, guc_log_level, -1) \ param(char *, guc_firmware_path, NULL) \ param(char *, huc_firmware_path, NULL) \ -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 6/9] drm/i915/firmware: CFL uses KBL firmware
Add support to load the latest version of HuC on CFL. Cc: Daniele Ceraolo Spurio Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c index d590358193e4..2614f36934e5 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c @@ -41,7 +41,7 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw, #define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \ fw_def(ELKHARTLAKE, 0, guc_def(ehl, 33, 0, 4), huc_def(ehl, 9, 0, 0)) \ fw_def(ICELAKE, 0, guc_def(icl, 33, 0, 0), huc_def(icl, 8, 4, 3238)) \ - fw_def(COFFEELAKE, 0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 02, 00, 1810)) \ + fw_def(COFFEELAKE, 0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 4, 0, 0)) \ fw_def(GEMINILAKE, 0, guc_def(glk, 33, 0, 0), huc_def(glk, 4, 0, 0)) \ fw_def(KABYLAKE,0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 4, 0, 0)) \ fw_def(BROXTON, 0, guc_def(bxt, 33, 0, 0), huc_def(bxt, 2, 0, 0)) \ -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/9] drm/i915/firmware: Load v4.0.0 HuC for KBL
Add support to load the latest version of HuC on KBL. Cc: Daniele Ceraolo Spurio Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c index ab8fcd3e46ca..c631f1f81930 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c @@ -43,7 +43,7 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw, fw_def(ICELAKE, 0, guc_def(icl, 33, 0, 0), huc_def(icl, 8, 4, 3238)) \ fw_def(COFFEELAKE, 0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 02, 00, 1810)) \ fw_def(GEMINILAKE, 0, guc_def(glk, 33, 0, 0), huc_def(glk, 03, 01, 2893)) \ - fw_def(KABYLAKE,0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 02, 00, 1810)) \ + fw_def(KABYLAKE,0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 4, 0, 0)) \ fw_def(BROXTON, 0, guc_def(bxt, 33, 0, 0), huc_def(bxt, 2, 0, 0)) \ fw_def(SKYLAKE, 0, guc_def(skl, 33, 0, 0), huc_def(skl, 2, 0, 0)) -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/9] drm/i915/firmware: Load v2.0.0 HuC for BXT
Add support to load the latest version of HuC on BXT. Cc: Daniele Ceraolo Spurio Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c index 9bf6c415b4d8..ab8fcd3e46ca 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c @@ -44,7 +44,7 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw, fw_def(COFFEELAKE, 0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 02, 00, 1810)) \ fw_def(GEMINILAKE, 0, guc_def(glk, 33, 0, 0), huc_def(glk, 03, 01, 2893)) \ fw_def(KABYLAKE,0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 02, 00, 1810)) \ - fw_def(BROXTON, 0, guc_def(bxt, 33, 0, 0), huc_def(bxt, 01, 8, 2893)) \ + fw_def(BROXTON, 0, guc_def(bxt, 33, 0, 0), huc_def(bxt, 2, 0, 0)) \ fw_def(SKYLAKE, 0, guc_def(skl, 33, 0, 0), huc_def(skl, 2, 0, 0)) #define __MAKE_UC_FW_PATH(prefix_, name_, separator_, major_, minor_, patch_) \ -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/9] drm/i915/firmware: Load v2.0.0 HuC for SKL
Add support to load the latest version of HuC on SKL. Cc: Daniele Ceraolo Spurio Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c index 16a5aa8fe15a..9bf6c415b4d8 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c @@ -45,7 +45,7 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw, fw_def(GEMINILAKE, 0, guc_def(glk, 33, 0, 0), huc_def(glk, 03, 01, 2893)) \ fw_def(KABYLAKE,0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 02, 00, 1810)) \ fw_def(BROXTON, 0, guc_def(bxt, 33, 0, 0), huc_def(bxt, 01, 8, 2893)) \ - fw_def(SKYLAKE, 0, guc_def(skl, 33, 0, 0), huc_def(skl, 01, 07, 1398)) + fw_def(SKYLAKE, 0, guc_def(skl, 33, 0, 0), huc_def(skl, 2, 0, 0)) #define __MAKE_UC_FW_PATH(prefix_, name_, separator_, major_, minor_, patch_) \ "i915/" \ -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 8/9] drm/i915/firmware: Load v4.0.0 HuC for CML
Add support to load HuC on CML. Cc: Daniele Ceraolo Spurio Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c index 5994a41f47a8..6b832cdcea29 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c @@ -40,6 +40,7 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw, */ #define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \ fw_def(ELKHARTLAKE, 0, guc_def(ehl, 33, 0, 4), huc_def(ehl, 9, 0, 0)) \ + fw_def(COFFEELAKE, 0, guc_def(cml, 33, 0, 0), huc_def(cml, 4, 0, 0)) \ fw_def(ICELAKE, 0, guc_def(icl, 33, 0, 0), huc_def(icl, 9, 0, 0)) \ fw_def(COFFEELAKE, 0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 4, 0, 0)) \ fw_def(GEMINILAKE, 0, guc_def(glk, 33, 0, 0), huc_def(glk, 4, 0, 0)) \ -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/9] drm/i915/firmware: Load v4.0.0 HuC for GLK
Add support to load the latest version of HuC on GLK. Cc: Daniele Ceraolo Spurio Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c index c631f1f81930..d590358193e4 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c @@ -42,7 +42,7 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw, fw_def(ELKHARTLAKE, 0, guc_def(ehl, 33, 0, 4), huc_def(ehl, 9, 0, 0)) \ fw_def(ICELAKE, 0, guc_def(icl, 33, 0, 0), huc_def(icl, 8, 4, 3238)) \ fw_def(COFFEELAKE, 0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 02, 00, 1810)) \ - fw_def(GEMINILAKE, 0, guc_def(glk, 33, 0, 0), huc_def(glk, 03, 01, 2893)) \ + fw_def(GEMINILAKE, 0, guc_def(glk, 33, 0, 0), huc_def(glk, 4, 0, 0)) \ fw_def(KABYLAKE,0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 4, 0, 0)) \ fw_def(BROXTON, 0, guc_def(bxt, 33, 0, 0), huc_def(bxt, 2, 0, 0)) \ fw_def(SKYLAKE, 0, guc_def(skl, 33, 0, 0), huc_def(skl, 2, 0, 0)) -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 09/17] drm/i915: Push the ring creation flags to the backend
Quoting Tvrtko Ursulin (2019-09-02 14:59:16) > > On 05/08/2019 18:08, Andi Shyti wrote: > > Hi Chris, > > > > On Tue, Jul 30, 2019 at 02:30:27PM +0100, Chris Wilson wrote: > >> Push the ring creation flags from the outer GEM context to the inner > >> intel_cotnext to avoid an unsightly back-reference from inside the > >> backend. > >> > >> Signed-off-by: Chris Wilson > > > > looks nice! > > > > Reviewed-by: Andi Shyti > > I wish my complaints on this patch weren't just ignored. You wanted a union for a one-off value, and I disagreed as imo it overformalised the parameter passing and made it look like persistent state. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 9/9] drm/i915: Expand subslice mask
Quoting Tvrtko Ursulin (2019-09-02 14:42:44)
>
> On 24/07/2019 14:05, Tvrtko Ursulin wrote:
> >
> > On 23/07/2019 16:49, Stuart Summers wrote:
> >> +u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice)
> >> +{
> >> + int i, offset = slice * sseu->ss_stride;
> >> + u32 mask = 0;
> >> +
> >> + if (slice >= sseu->max_slices) {
> >> + DRM_ERROR("%s: invalid slice %d, max: %d\n",
> >> + __func__, slice, sseu->max_slices);
> >> + return 0;
> >> + }
> >> +
> >> + if (sseu->ss_stride > sizeof(mask)) {
> >> + DRM_ERROR("%s: invalid subslice stride %d, max: %lu\n",
> >> + __func__, sseu->ss_stride, sizeof(mask));
> >> + return 0;
> >> + }
> >> +
> >> + for (i = 0; i < sseu->ss_stride; i++)
> >> + mask |= (u32)sseu->subslice_mask[offset + i] <<
> >> + i * BITS_PER_BYTE;
> >> +
> >> + return mask;
> >> +}
> >
> > Why do you actually need these complications when the plan from the
> > start was that the driver and user sseu representation structures can be
> > different?
> >
> > I only gave it a quick look so I might be wrong, but why not just expand
> > the driver representations of subslice mask up from u8? Userspace API
> > should be able to cope with strides already.
>
> I never got an answer to this and the series was merged in the meantime.
>
> Maybe not much harm but I still don't understand why all the
> complications seemingly just to avoid bumping the *internal* ss mask up
> from u8. As long as the internal and abi sseu info struct are well
> separated and access point few and well controlled (I think they are)
> then I don't see why the internal side had to be converted to u8 and
> strides. But maybe I am missing something.
I looked at it and thought it was open-coding bitmap.h as well. I
accepted it in good faith that it improved certain use cases and should
even make tidying up the code without regressing those easier.
-Chris
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Re: [Intel-gfx] [PATCH v2] drm/connector: Allow max possible encoders to attach to a connector
On Fri, 2019-09-06 at 14:27 +0300, Ville Syrjälä wrote:
> On Thu, Sep 05, 2019 at 02:09:27PM -0700, José Roberto de Souza
> wrote:
> > From: Dhinakaran Pandiyan
> >
> > Currently we restrict the number of encoders that can be linked to
> > a connector to 3, increase it to match the maximum number of
> > encoders
> > that can be initialized(32).
> >
> > To more effiently do that lets switch from an array of encoder ids
> > to
> > bitmask.
> >
> > Also removing the best_encoder hook from the drivers that only have
> > one encoder per connector(this ones have one encoder in the whole
> > driver), pick_single_encoder_for_connector() will do the same job
> > with no functional change.
>
> I don't think non-atomic drivers have that fallback in place.
> They probable should...
Nice catch, thanks I will bring it back as it was removed from non-
atomic drivers.
>
> Apart from that lgtm
> Reviewed-by: Ville Syrjälä
>
> > v2: Fixing missed return on amdgpu_dm_connector_to_encoder()
> >
> > Suggested-by: Ville Syrjälä
> > Cc: Ville Syrjälä
> > Cc: Alex Deucher
> > Cc: dri-de...@lists.freedesktop.org
> > Cc: intel-gfx@lists.freedesktop.org
> > Cc: nouv...@lists.freedesktop.org
> > Cc: amd-...@lists.freedesktop.org
> > Signed-off-by: Dhinakaran Pandiyan
> > Signed-off-by: José Roberto de Souza
> > ---
> > .../gpu/drm/amd/amdgpu/amdgpu_connectors.c| 23 +-
> > drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 5 ++-
> > .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +++-
> > drivers/gpu/drm/ast/ast_mode.c| 12 ---
> > drivers/gpu/drm/drm_atomic_helper.c | 9 --
> > drivers/gpu/drm/drm_client_modeset.c | 3 +-
> > drivers/gpu/drm/drm_connector.c | 31 +
> > --
> > drivers/gpu/drm/drm_probe_helper.c| 3 +-
> > drivers/gpu/drm/mgag200/mgag200_mode.c| 11 ---
> > drivers/gpu/drm/nouveau/dispnv04/disp.c | 2 +-
> > drivers/gpu/drm/nouveau/dispnv50/disp.c | 2 +-
> > drivers/gpu/drm/nouveau/nouveau_connector.c | 7 ++---
> > drivers/gpu/drm/radeon/radeon_connectors.c| 27 ++-
> > -
> > drivers/gpu/drm/udl/udl_connector.c | 8 -
> > include/drm/drm_connector.h | 18 +--
> > 15 files changed, 53 insertions(+), 114 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
> > index ece55c8fa673..d8729285f731 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
> > @@ -217,11 +217,10 @@ amdgpu_connector_update_scratch_regs(struct
> > drm_connector *connector,
> > struct drm_encoder *encoder;
> > const struct drm_connector_helper_funcs *connector_funcs =
> > connector->helper_private;
> > bool connected;
> > - int i;
> >
> > best_encoder = connector_funcs->best_encoder(connector);
> >
> > - drm_connector_for_each_possible_encoder(connector, encoder, i)
> > {
> > + drm_connector_for_each_possible_encoder(connector, encoder) {
> > if ((encoder == best_encoder) && (status ==
> > connector_status_connected))
> > connected = true;
> > else
> > @@ -236,9 +235,8 @@ amdgpu_connector_find_encoder(struct
> > drm_connector *connector,
> >int encoder_type)
> > {
> > struct drm_encoder *encoder;
> > - int i;
> >
> > - drm_connector_for_each_possible_encoder(connector, encoder, i)
> > {
> > + drm_connector_for_each_possible_encoder(connector, encoder) {
> > if (encoder->encoder_type == encoder_type)
> > return encoder;
> > }
> > @@ -347,10 +345,9 @@ static struct drm_encoder *
> > amdgpu_connector_best_single_encoder(struct drm_connector
> > *connector)
> > {
> > struct drm_encoder *encoder;
> > - int i;
> >
> > /* pick the first one */
> > - drm_connector_for_each_possible_encoder(connector, encoder, i)
> > + drm_connector_for_each_possible_encoder(connector, encoder)
> > return encoder;
> >
> > return NULL;
> > @@ -1065,9 +1062,8 @@ amdgpu_connector_dvi_detect(struct
> > drm_connector *connector, bool force)
> > /* find analog encoder */
> > if (amdgpu_connector->dac_load_detect) {
> > struct drm_encoder *encoder;
> > - int i;
> >
> > - drm_connector_for_each_possible_encoder(connector,
> > encoder, i) {
> > + drm_connector_for_each_possible_encoder(connector,
> > encoder) {
> > if (encoder->encoder_type !=
> > DRM_MODE_ENCODER_DAC &&
> > encoder->encoder_type !=
> > DRM_MODE_ENCODER_TVDAC)
> > continue;
> > @@ -1117,9 +1113,8 @@ amdgpu_connector_dvi_encoder(struct
> > drm_connector *connector)
> > {
> > struct amdgpu_connector *amdgpu_connector =
> > to_amdgpu_connector(connector);
> >
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add more debug information to dp aux code
== Series Details == Series: drm/i915: Add more debug information to dp aux code URL : https://patchwork.freedesktop.org/series/66343/ State : success == Summary == CI Bug Log - changes from CI_DRM_6844 -> Patchwork_14305 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14305/ Known issues Here are the changes found in Patchwork_14305 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6844/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14305/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html * igt@kms_chamelium@dp-crc-fast: - fi-cml-u2: [PASS][3] -> [FAIL][4] ([fdo#110627]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6844/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14305/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html * igt@prime_vgem@basic-fence-flip: - fi-ilk-650: [PASS][5] -> [DMESG-WARN][6] ([fdo#106387]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6844/fi-ilk-650/igt@prime_v...@basic-fence-flip.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14305/fi-ilk-650/igt@prime_v...@basic-fence-flip.html Possible fixes * igt@i915_selftest@live_execlists: - fi-skl-gvtdvm: [DMESG-FAIL][7] ([fdo#08]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6844/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14305/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html * igt@kms_frontbuffer_tracking@basic: - fi-icl-u2: [FAIL][9] ([fdo#103167]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6844/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14305/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html Warnings * igt@kms_chamelium@common-hpd-after-suspend: - fi-icl-u2: [FAIL][11] ([fdo#109483]) -> [DMESG-WARN][12] ([fdo#102505] / [fdo#110390]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6844/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14305/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][13] ([fdo#111096]) -> [FAIL][14] ([fdo#111407]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6844/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14305/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505 [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=106387 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483 [fdo#110390]: https://bugs.freedesktop.org/show_bug.cgi?id=110390 [fdo#110627]: https://bugs.freedesktop.org/show_bug.cgi?id=110627 [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 [fdo#08]: https://bugs.freedesktop.org/show_bug.cgi?id=08 [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407 Participating hosts (53 -> 45) -- Additional (1): fi-bxt-dsi Missing(9): fi-ilk-m540 fi-tgl-u fi-cml-s fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_6844 -> Patchwork_14305 CI-20190529: 20190529 CI_DRM_6844: 7b96905a215c38f4cf53f51d864dcabbc2aa5b16 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5172: 073caf4acb7cac63abe7a5e1409ea27a764db5fd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_14305: 3bc28c373298043428a1aead30a5bdf6022b0e4a @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 3bc28c373298 drm/i915: Add more debug information to dp aux code == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14305/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PULL] gvt-next-fixes
On Fri, Sep 06, 2019 at 01:42:55PM +0800, Zhenyu Wang wrote: > > Hi, > > Here's gvt-next-fixes with two recent fixes, one for recent > guest hang regression and another for guest reset fix. > > Thanks. > -- > The following changes since commit c36beba6b296b3c05a0f29753b04775e5ae23886: > > drm/i915: Seal races between async GPU cancellation, retirement and > signaling (2019-05-13 13:53:35 +0300) > > are available in the Git repository at: > > https://github.com/intel/gvt-linux.git tags/gvt-next-fixes-2019-09-06 pulled, thanks > > for you to fetch changes up to 4a5322560aa235efa84c0aa34c00e5749a0792fd: > > drm/i915/gvt: update RING_START reg of vGPU when the context is submitted > to i915 (2019-09-06 13:39:09 +0800) > > > gvt-next-fixes-2019-09-06 > > - Fix guest context head pointer update for hang (Xiaolin) > - Fix guest context ring state for reset (Weinan) > > > Weinan Li (1): > drm/i915/gvt: update RING_START reg of vGPU when the context is > submitted to i915 > > Xiaolin Zhang (1): > drm/i915/gvt: update vgpu workload head pointer correctly > > drivers/gpu/drm/i915/gvt/scheduler.c | 45 > +--- > 1 file changed, 32 insertions(+), 13 deletions(-) > > > -- > Open Source Technology Center, Intel ltd. > > $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/tgl: Register state context definition for Gen12
Quoting Daniele Ceraolo Spurio (2019-09-06 16:42:50)
>
> > +static void gen12_init_reg_state(u32 * const regs,
> > + struct intel_context *ce,
> > + struct intel_engine_cs *engine,
> > + struct intel_ring *ring)
> > +{
> > + struct i915_ppgtt * const ppgtt = i915_vm_to_ppgtt(ce->vm);
> > + const bool rcs = engine->class == RENDER_CLASS;
> > + const u32 base = engine->mmio_base;
> > + const u32 lri_base = intel_engine_has_relative_mmio(engine) ?
> > + MI_LRI_CS_MMIO : 0;
> > +
> > + GEM_DEBUG_EXEC(DRM_INFO_ONCE("Using GEN12 Register State Context\n"));
> > +
> > + regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 11 : 9) |
>
> I would've kept a constant 13 here since we'll need to set the 13th
> register (that's the semaphore reg you had in the previous revision),
> but anyway we can bump it when that support is added in.
I left this for a future task. Early next week I hope to have a new
selftest ready that enforces that our init_reg_state() matches the HW
layout. For now, this gets us onto the next error we need to debug.
Thanks for the patches and reviewing,
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Use engine relative LRIs on context setup (rev3)
== Series Details ==
Series: series starting with [1/2] drm/i915: Use engine relative LRIs on
context setup (rev3)
URL : https://patchwork.freedesktop.org/series/66335/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6844 -> Patchwork_14304
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14304/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14304:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_sync@basic-all:
- {fi-tgl-u}: NOTRUN -> [INCOMPLETE][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14304/fi-tgl-u/igt@gem_s...@basic-all.html
Known issues
Here are the changes found in Patchwork_14304 that come from known issues:
### IGT changes ###
Possible fixes
* igt@gem_busy@busy-all:
- {fi-tgl-u}: [FAIL][2] ([fdo#111560]) -> [PASS][3]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6844/fi-tgl-u/igt@gem_b...@busy-all.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14304/fi-tgl-u/igt@gem_b...@busy-all.html
* igt@gem_close_race@basic-process:
- {fi-tgl-u}: [INCOMPLETE][4] -> [PASS][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6844/fi-tgl-u/igt@gem_close_r...@basic-process.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14304/fi-tgl-u/igt@gem_close_r...@basic-process.html
* igt@i915_selftest@live_execlists:
- fi-skl-gvtdvm: [DMESG-FAIL][6] ([fdo#08]) -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6844/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14304/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
Warnings
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-icl-u2: [FAIL][8] ([fdo#109483]) -> [DMESG-WARN][9]
([fdo#102505] / [fdo#110390])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6844/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14304/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][10] ([fdo#111096]) -> [FAIL][11] ([fdo#111407])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6844/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14304/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#110390]: https://bugs.freedesktop.org/show_bug.cgi?id=110390
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#08]: https://bugs.freedesktop.org/show_bug.cgi?id=08
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111560]: https://bugs.freedesktop.org/show_bug.cgi?id=111560
Participating hosts (53 -> 45)
--
Additional (1): fi-bxt-dsi
Missing(9): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-bdw-samus fi-icl-guc fi-byt-clapper fi-skl-6600u
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6844 -> Patchwork_14304
CI-20190529: 20190529
CI_DRM_6844: 7b96905a215c38f4cf53f51d864dcabbc2aa5b16 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5172: 073caf4acb7cac63abe7a5e1409ea27a764db5fd @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14304: bc7adb0fc5b7bc8e4e044e55d5879db939f02f21 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
bc7adb0fc5b7 drm/i915/tgl: Register state context definition for Gen12
49f66db7db65 drm/i915: Use engine relative LRIs on context setup
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14304/
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Re: [Intel-gfx] [PATCH 2/2] drm/i915/tgl: Register state context definition for Gen12
Quoting Daniele Ceraolo Spurio (2019-09-06 16:42:50)
>
> On 9/6/19 5:23 AM, Mika Kuoppala wrote:
> > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > @@ -808,8 +808,11 @@ static void virtual_update_register_offsets(u32 *regs,
> > {
> > u32 base = engine->mmio_base;
> >
> > + GEM_WARN_ON(engine->class == COPY_ENGINE_CLASS);
>
> Could use a comment up here to explain why, something like:
>
> /* HW doesn't not support relative MMIO on COPY_ENGINE and we don't
> implement offset remap for all gens in SW because there is only 1
> instance */
What's the point of the check anyway? If the LRI are not using
relative addressing, we need to fixup the offsets. Aiui, it should just
be GEM_BUG_ON(intel_engine_has_relative_mmio(engine)). That we have only
a single instance in a particular class just means we never even call
the update function currently.
-Chris
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Use engine relative LRIs on context setup (rev3)
== Series Details == Series: series starting with [1/2] drm/i915: Use engine relative LRIs on context setup (rev3) URL : https://patchwork.freedesktop.org/series/66335/ State : warning == Summary == $ dim checkpatch origin/drm-tip 49f66db7db65 drm/i915: Use engine relative LRIs on context setup -:62: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #62: FILE: drivers/gpu/drm/i915/gt/intel_gpu_commands.h:136: +#define MI_LRI_CS_MMIO (1<<19) ^ total: 0 errors, 0 warnings, 1 checks, 95 lines checked bc7adb0fc5b7 drm/i915/tgl: Register state context definition for Gen12 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 5/5] drm/i915/pmu: Support multiple GPUs
Peter, Thomas,
If you could spare a moment for some brainstorming on the topic of
uncore PMU and multiple providers it would be appreciated.
So from i915 we export some metrics as uncore PMU, which shows up under
/sys/devices/i915. Shortsightedness or what, we did not realize that one
day we could have more than one i915 device in a system which now
creates a problem, or at least raises a question on naming.
The patch below works around this by appending the PCI device name to
additional instances of i915 when it registers with perf_pmu_register.
Question is if there is a better solution, or if not, whether you are
aware of any plans to extend the perf core to better support this? Are
there any other uncore PMU providers in an identical situation?
Regards,
Tvrtko
On 01/08/2019 16:54, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
With discrete graphics system can have both integrated and discrete GPU
handled by i915.
Currently we use a fixed name ("i915") when registering as the uncore PMU
provider which stops working in this case.
To fix this we add the PCI device name string to non-integrated devices
handled by us. Integrated devices keep the legacy name preserving
backward compatibility.
v2:
* Detect IGP and keep legacy name. (Michal)
* Use PCI device name as suffix. (Michal, Chris)
v3:
* Constify the name. (Chris)
* Use pci_domain_nr. (Chris)
v4:
* Fix kfree_const usage. (Chris)
Signed-off-by: Tvrtko Ursulin
Cc: Chris Wilson
Cc: Michal Wajdeczko
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_pmu.c | 25 +++--
drivers/gpu/drm/i915/i915_pmu.h | 4
2 files changed, 27 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index e0e0180bca7c..e0fea227077e 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -1053,6 +1053,15 @@ static void i915_pmu_unregister_cpuhp_state(struct
i915_pmu *pmu)
cpuhp_remove_multi_state(cpuhp_slot);
}
+static bool is_igp(struct pci_dev *pdev)
+{
+ /* IGP is :00:02.0 */
+ return pci_domain_nr(pdev->bus) == 0 &&
+ pdev->bus->number == 0 &&
+ PCI_SLOT(pdev->devfn) == 2 &&
+ PCI_FUNC(pdev->devfn) == 0;
+}
+
void i915_pmu_register(struct drm_i915_private *i915)
{
struct i915_pmu *pmu = >pmu;
@@ -1083,10 +1092,19 @@ void i915_pmu_register(struct drm_i915_private *i915)
hrtimer_init(>timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
pmu->timer.function = i915_sample;
- ret = perf_pmu_register(>base, "i915", -1);
- if (ret)
+ if (!is_igp(i915->drm.pdev))
+ pmu->name = kasprintf(GFP_KERNEL,
+ "i915-%s",
+ dev_name(i915->drm.dev));
+ else
+ pmu->name = "i915";
+ if (!pmu->name)
goto err;
+ ret = perf_pmu_register(>base, pmu->name, -1);
+ if (ret)
+ goto err_name;
+
ret = i915_pmu_register_cpuhp_state(pmu);
if (ret)
goto err_unreg;
@@ -1095,6 +1113,8 @@ void i915_pmu_register(struct drm_i915_private *i915)
err_unreg:
perf_pmu_unregister(>base);
+err_name:
+ kfree_const(pmu->name);
err:
pmu->base.event_init = NULL;
free_event_attributes(pmu);
@@ -1116,5 +1136,6 @@ void i915_pmu_unregister(struct drm_i915_private *i915)
perf_pmu_unregister(>base);
pmu->base.event_init = NULL;
+ kfree_const(pmu->name);
free_event_attributes(pmu);
}
diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h
index 4fc4f2478301..ff24f3bb0102 100644
--- a/drivers/gpu/drm/i915/i915_pmu.h
+++ b/drivers/gpu/drm/i915/i915_pmu.h
@@ -46,6 +46,10 @@ struct i915_pmu {
* @base: PMU base.
*/
struct pmu base;
+ /**
+* @name: Name as registered with perf core.
+*/
+ const char *name;
/**
* @lock: Lock protecting enable mask and ref count handling.
*/
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Re: [Intel-gfx] [PATCH] drm/i915/tgl: Use refclk/2 as bypass frequency
On Fri, Sep 06, 2019 at 02:36:49PM +0300, Ville Syrjälä wrote:
> On Thu, Sep 05, 2019 at 11:13:37AM -0700, Matt Roper wrote:
> > Unlike gen11, which always ran at 50MHz when the cdclk PLL was disabled,
> > TGL runs at refclk/2. The 50MHz croclk/2 is only used by hardware
> > during some power state transitions.
> >
> > Bspec: 49201
> > Cc: José Roberto de Souza
> > Signed-off-by: Matt Roper
> > ---
> > drivers/gpu/drm/i915/display/intel_cdclk.c | 7 +--
> > 1 file changed, 5 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index 76f11d465e91..d3e56628af70 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -1855,8 +1855,6 @@ static void icl_get_cdclk(struct drm_i915_private
> > *dev_priv,
> > u32 val;
> > int div;
> >
> > - cdclk_state->bypass = 5;
> > -
> > val = I915_READ(SKL_DSSM);
> > switch (val & ICL_DSSM_CDCLK_PLL_REFCLK_MASK) {
> > default:
> > @@ -1873,6 +1871,11 @@ static void icl_get_cdclk(struct drm_i915_private
> > *dev_priv,
> > break;
> > }
> >
> > + if (INTEL_GEN(dev_priv) >= 12)
> > + cdclk_state->bypass = cdclk_state->ref / 2;
> > + else
> > + cdclk_state->bypass = 5;
>
> Reviewed-by: Ville Syrjälä
>
> PS. I'd still like to see a icl_cdclk_pll_update() so I wouldn't have to
> scratch my head why this looks so different to bxt/cnl code.
Applied to dinq; thanks for the review. As you mentioned, I'll look
into further updates to the ICL-style cdclk code to bring it more in
line with other platforms.
Matt
>
> > +
> > val = I915_READ(BXT_DE_PLL_ENABLE);
> > if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
> > (val & BXT_DE_PLL_LOCK) == 0) {
> > --
> > 2.20.1
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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Re: [Intel-gfx] [PATCH 2/2] drm/i915/tgl: Register state context definition for Gen12
On 9/6/19 5:23 AM, Mika Kuoppala wrote:
From: Michel Thierry
Gen12 has subtle changes in the reg state context offsets (some fields
are gone, some are in a different location), compared to previous Gens.
The simplest approach seems to be keeping Gen12 (and future platform)
changes apart from the previous gens, while keeping the registers that
are contiguous in functions we can reuse.
v2: alias, virtual engine, rpcs, prune unused regs
v3: use engine base (Daniele), take ctx_bb for all
Bspec: 46255
Cc: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: José Roberto de Souza
Signed-off-by: Michel Thierry
Signed-off-by: Lucas De Marchi
Signed-off-by: Mika Kuoppala
I've tested this on TGL, both the gem_ctx_switch that failed on ICL and
exec_balancer@nop passed for me.
Reviewed-by: Daniele Ceraolo Spurio
Tested-by: Daniele Ceraolo Spurio
A couple of non-blocking nits below.
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 196 +---
drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 6 +-
2 files changed, 147 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 6c68ed2bf3d2..e9c873877253 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -808,8 +808,11 @@ static void virtual_update_register_offsets(u32 *regs,
{
u32 base = engine->mmio_base;
+ GEM_WARN_ON(engine->class == COPY_ENGINE_CLASS);
Could use a comment up here to explain why, something like:
/* HW doesn't not support relative MMIO on COPY_ENGINE and we don't
implement offset remap for all gens in SW because there is only 1
instance */
+ > /* Must match execlists_init_reg_state()! */
+ /* Common part */
regs[CTX_CONTEXT_CONTROL] =
i915_mmio_reg_offset(RING_CONTEXT_CONTROL(base));
regs[CTX_RING_HEAD] = i915_mmio_reg_offset(RING_HEAD(base));
@@ -820,13 +823,16 @@ static void virtual_update_register_offsets(u32 *regs,
regs[CTX_BB_HEAD_U] = i915_mmio_reg_offset(RING_BBADDR_UDW(base));
regs[CTX_BB_HEAD_L] = i915_mmio_reg_offset(RING_BBADDR(base));
regs[CTX_BB_STATE] = i915_mmio_reg_offset(RING_BBSTATE(base));
+
regs[CTX_SECOND_BB_HEAD_U] =
i915_mmio_reg_offset(RING_SBBADDR_UDW(base));
regs[CTX_SECOND_BB_HEAD_L] = i915_mmio_reg_offset(RING_SBBADDR(base));
regs[CTX_SECOND_BB_STATE] = i915_mmio_reg_offset(RING_SBBSTATE(base));
+ /* PPGTT part */
regs[CTX_CTX_TIMESTAMP] =
i915_mmio_reg_offset(RING_CTX_TIMESTAMP(base));
+
regs[CTX_PDP3_UDW] = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 3));
regs[CTX_PDP3_LDW] = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 3));
regs[CTX_PDP2_UDW] = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 2));
@@ -3123,37 +3129,13 @@ static u32 intel_lr_indirect_ctx_offset(struct
intel_engine_cs *engine)
return indirect_ctx_offset;
}
-static struct i915_ppgtt *vm_alias(struct i915_address_space *vm)
-{
- if (i915_is_ggtt(vm))
- return i915_vm_to_ggtt(vm)->alias;
- else
- return i915_vm_to_ppgtt(vm);
-}
-static void execlists_init_reg_state(u32 *regs,
-struct intel_context *ce,
-struct intel_engine_cs *engine,
-struct intel_ring *ring)
+static void init_common_reg_state(u32 * const regs,
+ struct i915_ppgtt * const ppgtt,
+ struct intel_engine_cs *engine,
+ struct intel_ring *ring)
{
- struct i915_ppgtt *ppgtt = vm_alias(ce->vm);
- const bool rcs = engine->class == RENDER_CLASS;
const u32 base = engine->mmio_base;
- const u32 lri_base = intel_engine_has_relative_mmio(engine) ?
- MI_LRI_CS_MMIO : 0;
-
- /*
-* A context is actually a big batch buffer with several
-* MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The
-* values we are setting here are only for the first context restore:
-* on a subsequent save, the GPU will recreate this batchbuffer with new
-* values (including all the missing MI_LOAD_REGISTER_IMM commands that
-* we are not initializing here).
-*
-* Must keep consistent with virtual_update_register_offsets().
-*/
- regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) |
- MI_LRI_FORCE_POSTED | lri_base;
CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(base),
_MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT) |
@@ -3171,39 +3153,43 @@ static void execlists_init_reg_state(u32 *regs,
CTX_REG(regs, CTX_BB_HEAD_U, RING_BBADDR_UDW(base), 0);
CTX_REG(regs, CTX_BB_HEAD_L, RING_BBADDR(base), 0);
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Use engine relative LRIs on context setup
== Series Details == Series: series starting with [1/2] drm/i915: Use engine relative LRIs on context setup URL : https://patchwork.freedesktop.org/series/66335/ State : success == Summary == CI Bug Log - changes from CI_DRM_6841_full -> Patchwork_14302_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14302_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@rcs0-s3: - shard-skl: [PASS][1] -> [INCOMPLETE][2] ([fdo#104108]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/shard-skl7/igt@gem_ctx_isolat...@rcs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/shard-skl6/igt@gem_ctx_isolat...@rcs0-s3.html * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110841]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/shard-iclb3/igt@gem_ctx_sha...@exec-single-timeline-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/shard-iclb4/igt@gem_ctx_sha...@exec-single-timeline-bsd.html * igt@gem_exec_schedule@independent-bsd2: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276]) +12 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/shard-iclb2/igt@gem_exec_sched...@independent-bsd2.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/shard-iclb5/igt@gem_exec_sched...@independent-bsd2.html * igt@gem_exec_schedule@preempt-bsd: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#111325]) +4 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/shard-iclb7/igt@gem_exec_sched...@preempt-bsd.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/shard-iclb2/igt@gem_exec_sched...@preempt-bsd.html * igt@gem_exec_suspend@basic-s3-devices: - shard-apl: [PASS][9] -> [FAIL][10] ([fdo#111550]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/shard-apl4/igt@gem_exec_susp...@basic-s3-devices.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/shard-apl7/igt@gem_exec_susp...@basic-s3-devices.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][11] -> [INCOMPLETE][12] ([fdo#103927]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/shard-apl6/igt@gem_workarou...@suspend-resume-context.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/shard-apl2/igt@gem_workarou...@suspend-resume-context.html * igt@i915_pm_rpm@modeset-non-lpsp-stress: - shard-hsw: [PASS][13] -> [FAIL][14] ([fdo#111548]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/shard-hsw6/igt@i915_pm_...@modeset-non-lpsp-stress.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/shard-hsw2/igt@i915_pm_...@modeset-non-lpsp-stress.html * igt@i915_suspend@forcewake: - shard-snb: [PASS][15] -> [FAIL][16] ([fdo#103375]) +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/shard-snb7/igt@i915_susp...@forcewake.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/shard-snb4/igt@i915_susp...@forcewake.html - shard-kbl: [PASS][17] -> [FAIL][18] ([fdo#103375]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/shard-kbl2/igt@i915_susp...@forcewake.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/shard-kbl3/igt@i915_susp...@forcewake.html * igt@i915_suspend@sysfs-reader: - shard-apl: [PASS][19] -> [DMESG-WARN][20] ([fdo#108566]) +4 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/shard-apl4/igt@i915_susp...@sysfs-reader.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/shard-apl5/igt@i915_susp...@sysfs-reader.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][21] -> [FAIL][22] ([fdo#105363]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/shard-skl8/igt@kms_f...@flip-vs-expired-vblank.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/shard-skl5/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_flip@plain-flip-fb-recreate-interruptible: - shard-hsw: [PASS][23] -> [FAIL][24] ([fdo#100368]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/shard-hsw2/igt@kms_f...@plain-flip-fb-recreate-interruptible.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/shard-hsw2/igt@kms_f...@plain-flip-fb-recreate-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt: - shard-iclb: [PASS][25] -> [FAIL][26] ([fdo#103167]) +5 similar issues [25]:
[Intel-gfx] [PATCH v1] drm/i915: Add more debug information to dp aux code
Quite many issues currently happen during intel_dp_detect
during dpcd read. Sometimes we can only see that it had failed
in the logs, while no actual reason is available.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 5673ed75e428..2bf0451b3568 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1256,6 +1256,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
last_status = status;
}
+ WARN(1, "prev chan activity not finished after 3 retries");
ret = -EBUSY;
goto out;
}
@@ -1336,6 +1337,9 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
goto out;
}
+ if (!(status & DP_AUX_CH_CTL_DONE))
+ DRM_ERROR("Unknown dp aux ctl error status 0x%08x\n", status);
+
/* Unload any bytes sent back from the other side */
recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
@@ -1452,6 +1456,7 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct
drm_dp_aux_msg *msg)
break;
default:
+ WARN(1, "Unknown request type %d", msg->request &
~DP_AUX_I2C_MOT);
ret = -EINVAL;
break;
}
@@ -5028,8 +5033,10 @@ intel_dp_detect_dpcd(struct intel_dp *intel_dp)
if (lspcon->active)
lspcon_resume(lspcon);
- if (!intel_dp_get_dpcd(intel_dp))
+ if (!intel_dp_get_dpcd(intel_dp)) {
+ DRM_DEBUG_KMS("Could not get dpcd!");
return connector_status_disconnected;
+ }
/* if there's no downstream port, we're done */
if (!drm_dp_is_branch(dpcd))
--
2.17.1
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Use engine relative LRIs on context setup (rev2)
== Series Details ==
Series: series starting with [1/2] drm/i915: Use engine relative LRIs on
context setup (rev2)
URL : https://patchwork.freedesktop.org/series/66335/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6842 -> Patchwork_14303
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14303/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14303:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_suspend@basic-s4-devices:
- {fi-tgl-u}: [FAIL][1] ([fdo#111562]) -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6842/fi-tgl-u/igt@gem_exec_susp...@basic-s4-devices.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14303/fi-tgl-u/igt@gem_exec_susp...@basic-s4-devices.html
Known issues
Here are the changes found in Patchwork_14303 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_module_load@reload:
- fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6842/fi-blb-e6850/igt@i915_module_l...@reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14303/fi-blb-e6850/igt@i915_module_l...@reload.html
* igt@i915_selftest@live_execlists:
- fi-skl-gvtdvm: [PASS][5] -> [DMESG-FAIL][6] ([fdo#08])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6842/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14303/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][7] -> [FAIL][8] ([fdo#111407])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6842/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14303/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@prime_vgem@basic-gtt:
- fi-icl-u3: [PASS][9] -> [DMESG-WARN][10] ([fdo#107724])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6842/fi-icl-u3/igt@prime_v...@basic-gtt.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14303/fi-icl-u3/igt@prime_v...@basic-gtt.html
Possible fixes
* igt@gem_busy@busy-all:
- {fi-tgl-u}: [FAIL][11] ([fdo#111560]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6842/fi-tgl-u/igt@gem_b...@busy-all.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14303/fi-tgl-u/igt@gem_b...@busy-all.html
* igt@gem_close_race@basic-process:
- {fi-tgl-u}: [DMESG-FAIL][13] ([fdo#111562]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6842/fi-tgl-u/igt@gem_close_r...@basic-process.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14303/fi-tgl-u/igt@gem_close_r...@basic-process.html
* igt@gem_exec_suspend@basic-s3:
- {fi-tgl-u}: [FAIL][15] ([fdo#111562]) -> [PASS][16] +10 similar
issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6842/fi-tgl-u/igt@gem_exec_susp...@basic-s3.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14303/fi-tgl-u/igt@gem_exec_susp...@basic-s3.html
* igt@i915_selftest@live_hangcheck:
- {fi-icl-guc}: [INCOMPLETE][17] ([fdo#107713] / [fdo#108569]) ->
[PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6842/fi-icl-guc/igt@i915_selftest@live_hangcheck.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14303/fi-icl-guc/igt@i915_selftest@live_hangcheck.html
Warnings
* igt@i915_module_load@reload:
- fi-icl-u2: [DMESG-WARN][19] ([fdo#110595] / [fdo#111214]) ->
[DMESG-WARN][20] ([fdo#106107] / [fdo#110595] / [fdo#111214])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6842/fi-icl-u2/igt@i915_module_l...@reload.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14303/fi-icl-u2/igt@i915_module_l...@reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#110595]: https://bugs.freedesktop.org/show_bug.cgi?id=110595
[fdo#08]: https://bugs.freedesktop.org/show_bug.cgi?id=08
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Use engine relative LRIs on context setup (rev2)
== Series Details == Series: series starting with [1/2] drm/i915: Use engine relative LRIs on context setup (rev2) URL : https://patchwork.freedesktop.org/series/66335/ State : warning == Summary == $ dim checkpatch origin/drm-tip 319509655960 drm/i915: Use engine relative LRIs on context setup -:61: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #61: FILE: drivers/gpu/drm/i915/gt/intel_gpu_commands.h:136: +#define MI_LRI_CS_MMIO (1<<19) ^ total: 0 errors, 0 warnings, 1 checks, 96 lines checked 32997572cece drm/i915/tgl: Register state context definition for Gen12 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915: Use engine relative LRIs on context setup
Daniele pointed out that relative mmio works differently in
on context restore. Instead of adding the engine mmio base to offset,
it masks out the base and adds bits [12:2] to current engine base.
This should allow us to construct context register state to be
applicable to all instances, including virtual. And avoid the trouble
of updating the registers on virtual instances when submitting work.
v2: only enable for gen12 for now (Mika)
v3: make enabling readable (Chris)
Bspec: 20206
Cc: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Lucas De Marchi
Cc: John Harrison
Suggested-by: Daniele Ceraolo Spurio
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine_types.h | 7 ++
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 2 ++
drivers/gpu/drm/i915/gt/intel_lrc.c | 26 ++--
3 files changed, 27 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 15e02cb58a67..943f0663837e 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -481,6 +481,7 @@ struct intel_engine_cs {
#define I915_ENGINE_HAS_SEMAPHORES BIT(3)
#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(4)
#define I915_ENGINE_IS_VIRTUAL BIT(5)
+#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(6)
unsigned int flags;
/*
@@ -576,6 +577,12 @@ intel_engine_is_virtual(const struct intel_engine_cs
*engine)
return engine->flags & I915_ENGINE_IS_VIRTUAL;
}
+static inline bool
+intel_engine_has_relative_mmio(const struct intel_engine_cs * const engine)
+{
+ return engine->flags & I915_ENGINE_HAS_RELATIVE_MMIO;
+}
+
#define instdone_has_slice(dev_priv___, sseu___, slice___) \
((IS_GEN(dev_priv___, 7) ? 1 : ((sseu___)->slice_mask)) & BIT(slice___))
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 86e00a2db8a4..fbad403ab7ac 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -132,6 +132,8 @@
* address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
*/
#define MI_LOAD_REGISTER_IMM(x)MI_INSTR(0x22, 2*(x)-1)
+/* Gen11+. addr = base + (ctx_restore ? offset & GENMASK(12,2) : offset) */
+#define MI_LRI_CS_MMIO (1<<19)
#define MI_LRI_FORCE_POSTED (1<<12)
#define MI_STORE_REGISTER_MEMMI_INSTR(0x24, 1)
#define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 87b7473a6dfb..d8070b1aa829 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1214,7 +1214,10 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
unsigned int n;
GEM_BUG_ON(READ_ONCE(ve->context.inflight));
- virtual_update_register_offsets(regs, engine);
+
+ if (!intel_engine_has_relative_mmio(engine))
+ virtual_update_register_offsets(regs,
+ engine);
if (!list_empty(>context.signals))
virtual_xfer_breadcrumbs(ve, engine);
@@ -2939,6 +2942,9 @@ void intel_execlists_set_default_submission(struct
intel_engine_cs *engine)
if (HAS_LOGICAL_RING_PREEMPTION(engine->i915))
engine->flags |= I915_ENGINE_HAS_PREEMPTION;
}
+
+ if (engine->class != COPY_ENGINE_CLASS && INTEL_GEN(engine->i915) >= 12)
+ engine->flags |= I915_ENGINE_HAS_RELATIVE_MMIO;
}
static void execlists_destroy(struct intel_engine_cs *engine)
@@ -3130,8 +3136,10 @@ static void execlists_init_reg_state(u32 *regs,
struct intel_ring *ring)
{
struct i915_ppgtt *ppgtt = vm_alias(ce->vm);
- bool rcs = engine->class == RENDER_CLASS;
- u32 base = engine->mmio_base;
+ const bool rcs = engine->class == RENDER_CLASS;
+ const u32 base = engine->mmio_base;
+ const u32 lri_base = intel_engine_has_relative_mmio(engine) ?
+ MI_LRI_CS_MMIO : 0;
/*
* A context is actually a big batch buffer with several
@@ -3144,7 +3152,7 @@ static void execlists_init_reg_state(u32 *regs,
* Must keep consistent with virtual_update_register_offsets().
*/
regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) |
-MI_LRI_FORCE_POSTED;
+ MI_LRI_FORCE_POSTED | lri_base;
CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(base),
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Use engine relative LRIs on context setup
Quoting Mika Kuoppala (2019-09-06 14:31:45) > @@ -2939,6 +2942,10 @@ void intel_execlists_set_default_submission(struct > intel_engine_cs *engine) > if (HAS_LOGICAL_RING_PREEMPTION(engine->i915)) > engine->flags |= I915_ENGINE_HAS_PREEMPTION; > } > + > + engine->flags |= (engine->class != COPY_ENGINE_CLASS && > + INTEL_GEN(engine->i915) >= 12) ? > + I915_ENGINE_HAS_RELATIVE_MMIO : 0; Style nit, I would have stuck with a plain if (class != COPY && GEN >= 12) engine->flags |= I915_ENGINE_HAS_RELATIVE_MMIO; The flag takes care of the virtual engine switching nicely. Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915: Use engine relative LRIs on context setup
Daniele pointed out that relative mmio works differently in
on context restore. Instead of adding the engine mmio base to offset,
it masks out the base and adds bits [12:2] to current engine base.
This should allow us to construct context register state to be
applicable to all instances, including virtual. And avoid the trouble
of updating the registers on virtual instances when submitting work.
v2: only enable for gen12 for now (Mika)
Bspec: 20206
Cc: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Lucas De Marchi
Cc: John Harrison
Suggested-by: Daniele Ceraolo Spurio
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_engine_types.h | 7 +
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 2 ++
drivers/gpu/drm/i915/gt/intel_lrc.c | 27 ++--
3 files changed, 28 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 15e02cb58a67..943f0663837e 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -481,6 +481,7 @@ struct intel_engine_cs {
#define I915_ENGINE_HAS_SEMAPHORES BIT(3)
#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(4)
#define I915_ENGINE_IS_VIRTUAL BIT(5)
+#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(6)
unsigned int flags;
/*
@@ -576,6 +577,12 @@ intel_engine_is_virtual(const struct intel_engine_cs
*engine)
return engine->flags & I915_ENGINE_IS_VIRTUAL;
}
+static inline bool
+intel_engine_has_relative_mmio(const struct intel_engine_cs * const engine)
+{
+ return engine->flags & I915_ENGINE_HAS_RELATIVE_MMIO;
+}
+
#define instdone_has_slice(dev_priv___, sseu___, slice___) \
((IS_GEN(dev_priv___, 7) ? 1 : ((sseu___)->slice_mask)) & BIT(slice___))
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 86e00a2db8a4..fbad403ab7ac 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -132,6 +132,8 @@
* address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
*/
#define MI_LOAD_REGISTER_IMM(x)MI_INSTR(0x22, 2*(x)-1)
+/* Gen11+. addr = base + (ctx_restore ? offset & GENMASK(12,2) : offset) */
+#define MI_LRI_CS_MMIO (1<<19)
#define MI_LRI_FORCE_POSTED (1<<12)
#define MI_STORE_REGISTER_MEMMI_INSTR(0x24, 1)
#define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 87b7473a6dfb..856be8745fb2 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1214,7 +1214,10 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
unsigned int n;
GEM_BUG_ON(READ_ONCE(ve->context.inflight));
- virtual_update_register_offsets(regs, engine);
+
+ if (!intel_engine_has_relative_mmio(engine))
+ virtual_update_register_offsets(regs,
+ engine);
if (!list_empty(>context.signals))
virtual_xfer_breadcrumbs(ve, engine);
@@ -2939,6 +2942,10 @@ void intel_execlists_set_default_submission(struct
intel_engine_cs *engine)
if (HAS_LOGICAL_RING_PREEMPTION(engine->i915))
engine->flags |= I915_ENGINE_HAS_PREEMPTION;
}
+
+ engine->flags |= (engine->class != COPY_ENGINE_CLASS &&
+ INTEL_GEN(engine->i915) >= 12) ?
+ I915_ENGINE_HAS_RELATIVE_MMIO : 0;
}
static void execlists_destroy(struct intel_engine_cs *engine)
@@ -3130,8 +3137,10 @@ static void execlists_init_reg_state(u32 *regs,
struct intel_ring *ring)
{
struct i915_ppgtt *ppgtt = vm_alias(ce->vm);
- bool rcs = engine->class == RENDER_CLASS;
- u32 base = engine->mmio_base;
+ const bool rcs = engine->class == RENDER_CLASS;
+ const u32 base = engine->mmio_base;
+ const u32 lri_base = intel_engine_has_relative_mmio(engine) ?
+ MI_LRI_CS_MMIO : 0;
/*
* A context is actually a big batch buffer with several
@@ -3144,7 +3153,7 @@ static void execlists_init_reg_state(u32 *regs,
* Must keep consistent with virtual_update_register_offsets().
*/
regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) |
-MI_LRI_FORCE_POSTED;
+ MI_LRI_FORCE_POSTED | lri_base;
CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(base),
_MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT) |
@@ -3191,7 +3200,8 @@ static
Re: [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Use engine relative LRIs on context setup
Patchwork writes:
> == Series Details ==
>
> Series: series starting with [1/2] drm/i915: Use engine relative LRIs on
> context setup
> URL : https://patchwork.freedesktop.org/series/66335/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_6841 -> Patchwork_14302
>
>
> Summary
> ---
>
> **SUCCESS**
>
> No regressions found.
>
> External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/
>
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> Patchwork_14302:
>
> ### IGT changes ###
>
> Suppressed
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * igt@gem_sync@basic-all:
> - {fi-tgl-u}: NOTRUN -> [INCOMPLETE][1]
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/fi-tgl-u/igt@gem_s...@basic-all.html
>
>
> Known issues
>
>
> Here are the changes found in Patchwork_14302 that come from known issues:
>
> ### IGT changes ###
>
> Issues hit
>
> * igt@gem_ctx_exec@basic:
> - fi-apl-guc: [PASS][2] -> [INCOMPLETE][3] ([fdo#103927])
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-apl-guc/igt@gem_ctx_e...@basic.html
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/fi-apl-guc/igt@gem_ctx_e...@basic.html
>
> * igt@gem_ctx_switch@rcs0:
> - fi-icl-u2: [PASS][4] -> [INCOMPLETE][5] ([fdo#107713])
>[4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-icl-u2/igt@gem_ctx_swi...@rcs0.html
>[5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/fi-icl-u2/igt@gem_ctx_swi...@rcs0.html
Ok, disturbing enough. I will send v2 with relative offsets turned off
on icl.
Chris has selftest cooking so we can experiment with icl/cs_mmio on
later time.
-Mika
>
> * igt@kms_addfb_basic@tile-pitch-mismatch:
> - fi-icl-u3: [PASS][6] -> [DMESG-WARN][7] ([fdo#107724]) +1
> similar issue
>[6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-icl-u3/igt@kms_addfb_ba...@tile-pitch-mismatch.html
>[7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/fi-icl-u3/igt@kms_addfb_ba...@tile-pitch-mismatch.html
>
>
> Possible fixes
>
> * igt@i915_pm_rpm@basic-rte:
> - {fi-icl-guc}: [DMESG-WARN][8] -> [PASS][9]
>[8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-icl-guc/igt@i915_pm_...@basic-rte.html
>[9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/fi-icl-guc/igt@i915_pm_...@basic-rte.html
>
> * igt@i915_selftest@live_execlists:
> - fi-skl-gvtdvm: [DMESG-FAIL][10] ([fdo#08]) -> [PASS][11]
>[10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
>[11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
>
> * igt@kms_chamelium@dp-crc-fast:
> - fi-cml-u2: [FAIL][12] ([fdo#110627]) -> [PASS][13]
>[12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
>[13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
>
> * igt@kms_frontbuffer_tracking@basic:
> - {fi-icl-u4}:[FAIL][14] ([fdo#103167]) -> [PASS][15]
>[14]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
>[15]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
>
> * igt@vgem_basic@unload:
> - fi-icl-u3: [DMESG-WARN][16] ([fdo#107724]) -> [PASS][17]
>[16]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-icl-u3/igt@vgem_ba...@unload.html
>[17]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/fi-icl-u3/igt@vgem_ba...@unload.html
>
>
> Warnings
>
> * igt@kms_chamelium@hdmi-hpd-fast:
> - fi-kbl-7500u: [FAIL][18] ([fdo#111407]) -> [FAIL][19]
> ([fdo#111096])
>[18]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
>[19]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
>
>
> {name}: This element is suppressed. This means it is ignored when computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
> [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
> [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
> [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
> [fdo#110627]: https://bugs.freedesktop.org/show_bug.cgi?id=110627
> [fdo#111096]:
Re: [Intel-gfx] [PATCH v4 3/7] drm: Add DisplayPort colorspace property
On Fri, Sep 6, 2019 at 7:43 AM Ville Syrjälä wrote: > > On Fri, Sep 06, 2019 at 11:31:55AM +, Shankar, Uma wrote: > > > > > > >-Original Message- > > >From: Ilia Mirkin > > >Sent: Tuesday, September 3, 2019 6:12 PM > > >To: Mun, Gwan-gyeong > > >Cc: Intel Graphics Development ; Shankar, > > >Uma > > >; dri-devel > > >Subject: Re: [PATCH v4 3/7] drm: Add DisplayPort colorspace property > > > > > >So how would this work with a DP++ connector? Should it list the HDMI or DP > > >properties? Or do we need a custom property checker which is aware of what > > >is > > >currently plugged in to validate the values? > > > > AFAIU For DP++ cases, we detect what kind of sink its driving DP or HDMI > > (with a passive dongle). > > Based on the type of sink detected, we should expose DP or HDMI colorspaces > > to userspace. > > For i915 DP connector always drives DP mode, HDMI connector always drives > HDMI mode, even when the physical connector is DP++. Right, i915 creates 2 connectors, while nouveau, radeon, and amdgpu create 1 connector (not sure about other drivers) for a single physical DP++ socket. Since we supply the list of valid values at the time of creating the connector, we can't know at that point whether in the future a HDMI or DP will be plugged into it. -ilia ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: List modes, regardless of encoder presence (rev2)
== Series Details == Series: drm/i915: List modes, regardless of encoder presence (rev2) URL : https://patchwork.freedesktop.org/series/66330/ State : success == Summary == CI Bug Log - changes from CI_DRM_6841_full -> Patchwork_14301_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14301_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@rcs0-s3: - shard-snb: [PASS][1] -> [FAIL][2] ([fdo#103375]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/shard-snb2/igt@gem_ctx_isolat...@rcs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14301/shard-snb6/igt@gem_ctx_isolat...@rcs0-s3.html * igt@gem_exec_parallel@vecs0-fds: - shard-apl: [PASS][3] -> [INCOMPLETE][4] ([fdo#103927]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/shard-apl5/igt@gem_exec_paral...@vecs0-fds.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14301/shard-apl3/igt@gem_exec_paral...@vecs0-fds.html * igt@gem_exec_schedule@preempt-queue-bsd1: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276]) +23 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/shard-iclb4/igt@gem_exec_sched...@preempt-queue-bsd1.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14301/shard-iclb8/igt@gem_exec_sched...@preempt-queue-bsd1.html * igt@gem_exec_schedule@reorder-wide-bsd: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#111325]) +6 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/shard-iclb8/igt@gem_exec_sched...@reorder-wide-bsd.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14301/shard-iclb2/igt@gem_exec_sched...@reorder-wide-bsd.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic: - shard-glk: [PASS][9] -> [FAIL][10] ([fdo#104873]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/shard-glk3/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-atomic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14301/shard-glk7/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-atomic.html * igt@kms_flip@2x-flip-vs-expired-vblank: - shard-glk: [PASS][11] -> [FAIL][12] ([fdo#105363]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/shard-glk2/igt@kms_f...@2x-flip-vs-expired-vblank.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14301/shard-glk8/igt@kms_f...@2x-flip-vs-expired-vblank.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#105363]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/shard-skl8/igt@kms_f...@flip-vs-expired-vblank.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14301/shard-skl2/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite: - shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#103167]) +4 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/shard-iclb6/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-shrfb-draw-pwrite.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14301/shard-iclb7/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-shrfb-draw-pwrite.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-apl: [PASS][17] -> [DMESG-WARN][18] ([fdo#108566]) +9 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/shard-apl5/igt@kms_frontbuffer_track...@fbc-suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14301/shard-apl8/igt@kms_frontbuffer_track...@fbc-suspend.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-kbl: [PASS][19] -> [INCOMPLETE][20] ([fdo#103665]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/shard-kbl2/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14301/shard-kbl4/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt@kms_psr@psr2_sprite_mmap_gtt: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14301/shard-iclb5/igt@kms_psr@psr2_sprite_mmap_gtt.html * igt@kms_setmode@basic: - shard-hsw: [PASS][23] -> [FAIL][24] ([fdo#99912]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/shard-hsw7/igt@kms_setm...@basic.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14301/shard-hsw4/igt@kms_setm...@basic.html * igt@perf_pmu@rc6-runtime-pm-long: - shard-apl:
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Use engine relative LRIs on context setup
== Series Details ==
Series: series starting with [1/2] drm/i915: Use engine relative LRIs on
context setup
URL : https://patchwork.freedesktop.org/series/66335/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6841 -> Patchwork_14302
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14302:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_sync@basic-all:
- {fi-tgl-u}: NOTRUN -> [INCOMPLETE][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/fi-tgl-u/igt@gem_s...@basic-all.html
Known issues
Here are the changes found in Patchwork_14302 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_exec@basic:
- fi-apl-guc: [PASS][2] -> [INCOMPLETE][3] ([fdo#103927])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-apl-guc/igt@gem_ctx_e...@basic.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/fi-apl-guc/igt@gem_ctx_e...@basic.html
* igt@gem_ctx_switch@rcs0:
- fi-icl-u2: [PASS][4] -> [INCOMPLETE][5] ([fdo#107713])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-icl-u2/igt@gem_ctx_swi...@rcs0.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/fi-icl-u2/igt@gem_ctx_swi...@rcs0.html
* igt@kms_addfb_basic@tile-pitch-mismatch:
- fi-icl-u3: [PASS][6] -> [DMESG-WARN][7] ([fdo#107724]) +1
similar issue
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-icl-u3/igt@kms_addfb_ba...@tile-pitch-mismatch.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/fi-icl-u3/igt@kms_addfb_ba...@tile-pitch-mismatch.html
Possible fixes
* igt@i915_pm_rpm@basic-rte:
- {fi-icl-guc}: [DMESG-WARN][8] -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-icl-guc/igt@i915_pm_...@basic-rte.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/fi-icl-guc/igt@i915_pm_...@basic-rte.html
* igt@i915_selftest@live_execlists:
- fi-skl-gvtdvm: [DMESG-FAIL][10] ([fdo#08]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
* igt@kms_chamelium@dp-crc-fast:
- fi-cml-u2: [FAIL][12] ([fdo#110627]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_frontbuffer_tracking@basic:
- {fi-icl-u4}:[FAIL][14] ([fdo#103167]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
* igt@vgem_basic@unload:
- fi-icl-u3: [DMESG-WARN][16] ([fdo#107724]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-icl-u3/igt@vgem_ba...@unload.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/fi-icl-u3/igt@vgem_ba...@unload.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][18] ([fdo#111407]) -> [FAIL][19] ([fdo#111096])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14302/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#110627]: https://bugs.freedesktop.org/show_bug.cgi?id=110627
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#08]: https://bugs.freedesktop.org/show_bug.cgi?id=08
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
Participating hosts (53 -> 45)
--
Additional (1): fi-tgl-u
Missing(9): fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-byt-squawks
fi-bsw-cyan fi-bwr-2160 fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Use engine relative LRIs on context setup
== Series Details == Series: series starting with [1/2] drm/i915: Use engine relative LRIs on context setup URL : https://patchwork.freedesktop.org/series/66335/ State : warning == Summary == $ dim checkpatch origin/drm-tip 0441c15504e2 drm/i915: Use engine relative LRIs on context setup -:58: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #58: FILE: drivers/gpu/drm/i915/gt/intel_gpu_commands.h:136: +#define MI_LRI_CS_MMIO (1<<19) ^ total: 0 errors, 0 warnings, 1 checks, 96 lines checked 5f5d80a3dd01 drm/i915/tgl: Register state context definition for Gen12 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915/tgl: Register state context definition for Gen12
From: Michel Thierry
Gen12 has subtle changes in the reg state context offsets (some fields
are gone, some are in a different location), compared to previous Gens.
The simplest approach seems to be keeping Gen12 (and future platform)
changes apart from the previous gens, while keeping the registers that
are contiguous in functions we can reuse.
v2: alias, virtual engine, rpcs, prune unused regs
v3: use engine base (Daniele), take ctx_bb for all
Bspec: 46255
Cc: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: José Roberto de Souza
Signed-off-by: Michel Thierry
Signed-off-by: Lucas De Marchi
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 196 +---
drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 6 +-
2 files changed, 147 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 6c68ed2bf3d2..e9c873877253 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -808,8 +808,11 @@ static void virtual_update_register_offsets(u32 *regs,
{
u32 base = engine->mmio_base;
+ GEM_WARN_ON(engine->class == COPY_ENGINE_CLASS);
+
/* Must match execlists_init_reg_state()! */
+ /* Common part */
regs[CTX_CONTEXT_CONTROL] =
i915_mmio_reg_offset(RING_CONTEXT_CONTROL(base));
regs[CTX_RING_HEAD] = i915_mmio_reg_offset(RING_HEAD(base));
@@ -820,13 +823,16 @@ static void virtual_update_register_offsets(u32 *regs,
regs[CTX_BB_HEAD_U] = i915_mmio_reg_offset(RING_BBADDR_UDW(base));
regs[CTX_BB_HEAD_L] = i915_mmio_reg_offset(RING_BBADDR(base));
regs[CTX_BB_STATE] = i915_mmio_reg_offset(RING_BBSTATE(base));
+
regs[CTX_SECOND_BB_HEAD_U] =
i915_mmio_reg_offset(RING_SBBADDR_UDW(base));
regs[CTX_SECOND_BB_HEAD_L] = i915_mmio_reg_offset(RING_SBBADDR(base));
regs[CTX_SECOND_BB_STATE] = i915_mmio_reg_offset(RING_SBBSTATE(base));
+ /* PPGTT part */
regs[CTX_CTX_TIMESTAMP] =
i915_mmio_reg_offset(RING_CTX_TIMESTAMP(base));
+
regs[CTX_PDP3_UDW] = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 3));
regs[CTX_PDP3_LDW] = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 3));
regs[CTX_PDP2_UDW] = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 2));
@@ -3123,37 +3129,13 @@ static u32 intel_lr_indirect_ctx_offset(struct
intel_engine_cs *engine)
return indirect_ctx_offset;
}
-static struct i915_ppgtt *vm_alias(struct i915_address_space *vm)
-{
- if (i915_is_ggtt(vm))
- return i915_vm_to_ggtt(vm)->alias;
- else
- return i915_vm_to_ppgtt(vm);
-}
-static void execlists_init_reg_state(u32 *regs,
-struct intel_context *ce,
-struct intel_engine_cs *engine,
-struct intel_ring *ring)
+static void init_common_reg_state(u32 * const regs,
+ struct i915_ppgtt * const ppgtt,
+ struct intel_engine_cs *engine,
+ struct intel_ring *ring)
{
- struct i915_ppgtt *ppgtt = vm_alias(ce->vm);
- const bool rcs = engine->class == RENDER_CLASS;
const u32 base = engine->mmio_base;
- const u32 lri_base = intel_engine_has_relative_mmio(engine) ?
- MI_LRI_CS_MMIO : 0;
-
- /*
-* A context is actually a big batch buffer with several
-* MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The
-* values we are setting here are only for the first context restore:
-* on a subsequent save, the GPU will recreate this batchbuffer with new
-* values (including all the missing MI_LOAD_REGISTER_IMM commands that
-* we are not initializing here).
-*
-* Must keep consistent with virtual_update_register_offsets().
-*/
- regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) |
- MI_LRI_FORCE_POSTED | lri_base;
CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(base),
_MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT) |
@@ -3171,39 +3153,43 @@ static void execlists_init_reg_state(u32 *regs,
CTX_REG(regs, CTX_BB_HEAD_U, RING_BBADDR_UDW(base), 0);
CTX_REG(regs, CTX_BB_HEAD_L, RING_BBADDR(base), 0);
CTX_REG(regs, CTX_BB_STATE, RING_BBSTATE(base), RING_BB_PPGTT);
- CTX_REG(regs, CTX_SECOND_BB_HEAD_U, RING_SBBADDR_UDW(base), 0);
- CTX_REG(regs, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(base), 0);
- CTX_REG(regs, CTX_SECOND_BB_STATE, RING_SBBSTATE(base), 0);
- if (rcs) {
- struct i915_ctx_workarounds *wa_ctx = >wa_ctx;
-
- CTX_REG(regs, CTX_RCS_INDIRECT_CTX, RING_INDIRECT_CTX(base), 0);
- CTX_REG(regs,
[Intel-gfx] [PATCH 1/2] drm/i915: Use engine relative LRIs on context setup
Daniele pointed out that relative mmio works differently in
on context restore. Instead of adding the engine mmio base to offset,
it masks out the base and adds bits [12:2] to current engine base.
This should allow us to construct context register state to be
applicable to all instances, including virtual. And avoid the trouble
of updating the registers on virtual instances when submitting work.
Bspec: 20206
Cc: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Lucas De Marchi
Cc: John Harrison
Suggested-by: Daniele Ceraolo Spurio
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_engine_types.h | 7 +
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 2 ++
drivers/gpu/drm/i915/gt/intel_lrc.c | 27 ++--
3 files changed, 28 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 15e02cb58a67..943f0663837e 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -481,6 +481,7 @@ struct intel_engine_cs {
#define I915_ENGINE_HAS_SEMAPHORES BIT(3)
#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(4)
#define I915_ENGINE_IS_VIRTUAL BIT(5)
+#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(6)
unsigned int flags;
/*
@@ -576,6 +577,12 @@ intel_engine_is_virtual(const struct intel_engine_cs
*engine)
return engine->flags & I915_ENGINE_IS_VIRTUAL;
}
+static inline bool
+intel_engine_has_relative_mmio(const struct intel_engine_cs * const engine)
+{
+ return engine->flags & I915_ENGINE_HAS_RELATIVE_MMIO;
+}
+
#define instdone_has_slice(dev_priv___, sseu___, slice___) \
((IS_GEN(dev_priv___, 7) ? 1 : ((sseu___)->slice_mask)) & BIT(slice___))
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 86e00a2db8a4..e1b87a516ef8 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -132,6 +132,8 @@
* address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
*/
#define MI_LOAD_REGISTER_IMM(x)MI_INSTR(0x22, 2*(x)-1)
+/* Gen11+. addr = base + (ctx_restore ? offset & GENMASK(12:2) : offset) */
+#define MI_LRI_CS_MMIO (1<<19)
#define MI_LRI_FORCE_POSTED (1<<12)
#define MI_STORE_REGISTER_MEMMI_INSTR(0x24, 1)
#define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 87b7473a6dfb..6c68ed2bf3d2 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1214,7 +1214,10 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
unsigned int n;
GEM_BUG_ON(READ_ONCE(ve->context.inflight));
- virtual_update_register_offsets(regs, engine);
+
+ if (!intel_engine_has_relative_mmio(engine))
+ virtual_update_register_offsets(regs,
+ engine);
if (!list_empty(>context.signals))
virtual_xfer_breadcrumbs(ve, engine);
@@ -2939,6 +2942,10 @@ void intel_execlists_set_default_submission(struct
intel_engine_cs *engine)
if (HAS_LOGICAL_RING_PREEMPTION(engine->i915))
engine->flags |= I915_ENGINE_HAS_PREEMPTION;
}
+
+ engine->flags |= (engine->class != COPY_ENGINE_CLASS &&
+ INTEL_GEN(engine->i915) >= 11) ?
+ I915_ENGINE_HAS_RELATIVE_MMIO : 0;
}
static void execlists_destroy(struct intel_engine_cs *engine)
@@ -3130,8 +3137,10 @@ static void execlists_init_reg_state(u32 *regs,
struct intel_ring *ring)
{
struct i915_ppgtt *ppgtt = vm_alias(ce->vm);
- bool rcs = engine->class == RENDER_CLASS;
- u32 base = engine->mmio_base;
+ const bool rcs = engine->class == RENDER_CLASS;
+ const u32 base = engine->mmio_base;
+ const u32 lri_base = intel_engine_has_relative_mmio(engine) ?
+ MI_LRI_CS_MMIO : 0;
/*
* A context is actually a big batch buffer with several
@@ -3144,7 +3153,7 @@ static void execlists_init_reg_state(u32 *regs,
* Must keep consistent with virtual_update_register_offsets().
*/
regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) |
-MI_LRI_FORCE_POSTED;
+ MI_LRI_FORCE_POSTED | lri_base;
CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(base),
_MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT) |
@@ -3191,7 +3200,8 @@ static void execlists_init_reg_state(u32 *regs,
Re: [Intel-gfx] [PATCH 3/3] drm/i915/display: Extract chv_read_luts()
On Fri, 06 Sep 2019, Swati Sharma wrote:
> For cherryview, add hw read out to create hw blob of gamma
> lut values.
>
> Review comments from previous series:
> https://patchwork.freedesktop.org/patch/328252
>
> v4: -No need to initialize *blob [Jani]
> -Removed right shifts [Jani]
> -Dropped dev local var [Jani]
> v5: -Returned blob instead of assigning it internally within the
> function [Ville]
> -Renamed function cherryview_get_color_config() to chv_read_luts()
> -Renamed cherryview_get_gamma_config() to chv_read_cgm_gamma_lut()
> [Ville]
> v9: -80 character limit [Uma]
> -Made read func para as const [Ville, Uma]
> -Renamed chv_read_cgm_gamma_lut() to chv_read_cgm_gamma_lut()
> [Ville, Uma]
>
> Signed-off-by: Swati Sharma
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 43
> ++
> drivers/gpu/drm/i915/i915_reg.h| 3 +++
> 2 files changed, 46 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 17199a1..4473b54 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1612,6 +1612,48 @@ static void i965_read_luts(struct intel_crtc_state
> *crtc_state)
> }
>
> static struct drm_property_blob *
> +chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> + enum pipe pipe = crtc->pipe;
> + struct drm_property_blob *blob;
> + struct drm_color_lut *blob_data;
> + u32 i, val;
> +
> + blob = drm_property_create_blob(_priv->drm,
> + sizeof(struct drm_color_lut) * lut_size,
> + NULL);
> + if (IS_ERR(blob))
> + return NULL;
> +
> + blob_data = blob->data;
> +
> + for (i = 0; i < lut_size; i++) {
> + val = I915_READ(CGM_PIPE_GAMMA(pipe, i, 0));
> + blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
> +
> CGM_PIPE_GAMMA_GREEN_MASK, val), 10);
> + blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
> +
> CGM_PIPE_GAMMA_BLUE_MASK, val), 10);
> +
> + val = I915_READ(CGM_PIPE_GAMMA(pipe, i, 1));
> + blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
> +
> CGM_PIPE_GAMMA_RED_MASK, val), 10);
> + }
> +
> + return blob;
> +}
> +
> +static void chv_read_luts(struct intel_crtc_state *crtc_state)
> +{
> + if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> + crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
> + else
> + crtc_state->base.gamma_lut = chv_read_cgm_lut(crtc_state);
> +}
> +
> +static struct drm_property_blob *
> ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> @@ -1710,6 +1752,7 @@ void intel_color_init(struct intel_crtc *crtc)
> dev_priv->display.color_check = chv_color_check;
> dev_priv->display.color_commit = i9xx_color_commit;
> dev_priv->display.load_luts = chv_load_luts;
> + dev_priv->display.read_luts = chv_read_luts;
> } else if (INTEL_GEN(dev_priv) >= 4) {
> dev_priv->display.color_check = i9xx_color_check;
> dev_priv->display.color_commit = i9xx_color_commit;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1e58c6d..6ec56b1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10409,6 +10409,9 @@ enum skl_power_gate {
> #define CGM_PIPE_MODE_GAMMA(1 << 2)
> #define CGM_PIPE_MODE_CSC (1 << 1)
> #define CGM_PIPE_MODE_DEGAMMA (1 << 0)
> +#define CGM_PIPE_GAMMA_RED_MASK REG_GENMASK(9, 0)
> +#define CGM_PIPE_GAMMA_GREEN_MASK REG_GENMASK(25, 16)
> +#define CGM_PIPE_GAMMA_BLUE_MASK REG_GENMASK(9, 0)
>
> #define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900)
> #define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904)
--
Jani Nikula, Intel Open Source Graphics Center
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Re: [Intel-gfx] [PATCH 1/3] drm/i915/display: Add gamma precision function for CHV
On Fri, 06 Sep 2019, Swati Sharma wrote:
> intel_color_get_gamma_bit_precision() is extended for
> cherryview by adding chv_gamma_precision(), i965 will use existing
> i9xx_gamma_precision() func only.
>
> Signed-off-by: Swati Sharma
Could be part of patch 3/3, but no big deal,
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 25 +++--
> 1 file changed, 19 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 6d641e1..4d9a568 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1400,6 +1400,14 @@ static int ilk_gamma_precision(const struct
> intel_crtc_state *crtc_state)
> }
> }
>
> +static int chv_gamma_precision(const struct intel_crtc_state *crtc_state)
> +{
> + if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
> + return 10;
> + else
> + return i9xx_gamma_precision(crtc_state);
> +}
> +
> static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)
> {
> switch (crtc_state->gamma_mode) {
> @@ -1421,12 +1429,17 @@ int intel_color_get_gamma_bit_precision(const struct
> intel_crtc_state *crtc_stat
> if (!crtc_state->gamma_enable)
> return 0;
>
> - if (HAS_GMCH(dev_priv) && !IS_CHERRYVIEW(dev_priv))
> - return i9xx_gamma_precision(crtc_state);
> - else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
> - return glk_gamma_precision(crtc_state);
> - else if (IS_IRONLAKE(dev_priv))
> - return ilk_gamma_precision(crtc_state);
> + if (HAS_GMCH(dev_priv)) {
> + if (IS_CHERRYVIEW(dev_priv))
> + return chv_gamma_precision(crtc_state);
> + else
> + return i9xx_gamma_precision(crtc_state);
> + } else {
> + if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
> + return glk_gamma_precision(crtc_state);
> + else if (IS_IRONLAKE(dev_priv))
> + return ilk_gamma_precision(crtc_state);
> + }
>
> return 0;
> }
--
Jani Nikula, Intel Open Source Graphics Center
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Re: [Intel-gfx] [PATCH 2/3] drm/i915/display: Extract i965_read_luts()
On Fri, 06 Sep 2019, Swati Sharma wrote:
> For i965, add hw read out to create hw blob of gamma
> lut values.
>
> Review comments from old series:
> https://patchwork.freedesktop.org/series/58039/
>
> v4: -No need to initialize *blob [Jani]
> -Removed right shifts [Jani]
> -Dropped dev local var [Jani]
> v5: -Returned blob instead of assigning it internally
> within the function [Ville]
> -Renamed i965_get_color_config() to i965_read_lut() [Ville]
> -Renamed i965_get_gamma_config_10p6() to i965_read_gamma_lut_10p6()
> [Ville]
> v9: -Typo and 80 character limit [Uma]
> -Made read func para as const [Ville, Uma]
> -Renamed i965_read_gamma_lut_10p6() to i965_read_lut_10p6() [Ville, Uma]
> v10: -Swapped ldw and udw while creating hw blob [Jani]
>
> Signed-off-by: Swati Sharma
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 43
> ++
> drivers/gpu/drm/i915/i915_reg.h| 3 +++
> 2 files changed, 46 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 4d9a568..17199a1 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1570,6 +1570,48 @@ static void i9xx_read_luts(struct intel_crtc_state
> *crtc_state)
> }
>
> static struct drm_property_blob *
> +i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> + enum pipe pipe = crtc->pipe;
> + struct drm_property_blob *blob;
> + struct drm_color_lut *blob_data;
> + u32 i, val1, val2;
> +
> + blob = drm_property_create_blob(_priv->drm,
> + sizeof(struct drm_color_lut) * lut_size,
> + NULL);
> + if (IS_ERR(blob))
> + return NULL;
> +
> + blob_data = blob->data;
> +
> + for (i = 0; i < lut_size - 1; i++) {
> + val1 = I915_READ(PALETTE(pipe, 2 * i + 0));
> + val2 = I915_READ(PALETTE(pipe, 2 * i + 1));
> +
> + blob_data[i].red = REG_FIELD_GET(PALETTE_RED_MASK, val2) << 8 |
> +
> REG_FIELD_GET(PALETTE_RED_MASK, val1);
> + blob_data[i].green = REG_FIELD_GET(PALETTE_GREEN_MASK, val2) <<
> 8 |
> +
> REG_FIELD_GET(PALETTE_GREEN_MASK, val1);
> + blob_data[i].blue = REG_FIELD_GET(PALETTE_BLUE_MASK, val2) << 8
> |
> +
> REG_FIELD_GET(PALETTE_BLUE_MASK, val1);
> + }
I missed it in my earlier review, need to get the last index from
PIPEGCMAX. See i965_load_lut_10p6().
With that added,
Reviewed-by: Jani Nikula
> +
> + return blob;
> +}
> +
> +static void i965_read_luts(struct intel_crtc_state *crtc_state)
> +{
> + if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> + crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
> + else
> + crtc_state->base.gamma_lut = i965_read_lut_10p6(crtc_state);
> +}
> +
> +static struct drm_property_blob *
> ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> @@ -1672,6 +1714,7 @@ void intel_color_init(struct intel_crtc *crtc)
> dev_priv->display.color_check = i9xx_color_check;
> dev_priv->display.color_commit = i9xx_color_commit;
> dev_priv->display.load_luts = i965_load_luts;
> + dev_priv->display.read_luts = i965_read_luts;
> } else {
> dev_priv->display.color_check = i9xx_color_check;
> dev_priv->display.color_commit = i9xx_color_commit;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 45ed96d..1e58c6d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3558,6 +3558,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define _PALETTE_A 0xa000
> #define _PALETTE_B 0xa800
> #define _CHV_PALETTE_C 0xc000
> +#define PALETTE_RED_MASKREG_GENMASK(23, 16)
> +#define PALETTE_GREEN_MASK REG_GENMASK(15, 8)
> +#define PALETTE_BLUE_MASK REG_GENMASK(7, 0)
> #define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
> _PICK((pipe), _PALETTE_A, \
> _PALETTE_B, _CHV_PALETTE_C) + \
--
Jani Nikula, Intel Open Source Graphics Center
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: List modes, regardless of encoder presence (rev2)
== Series Details ==
Series: drm/i915: List modes, regardless of encoder presence (rev2)
URL : https://patchwork.freedesktop.org/series/66330/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6841 -> Patchwork_14301
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14301/
Known issues
Here are the changes found in Patchwork_14301 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14301/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@gem_mmap_gtt@basic-write-no-prefault:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +1
similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-icl-u3/igt@gem_mmap_...@basic-write-no-prefault.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14301/fi-icl-u3/igt@gem_mmap_...@basic-write-no-prefault.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-icl-u2: [PASS][5] -> [FAIL][6] ([fdo#109635 ])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-icl-u2/igt@kms_chamel...@hdmi-crc-fast.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14301/fi-icl-u2/igt@kms_chamel...@hdmi-crc-fast.html
Possible fixes
* igt@i915_pm_rpm@basic-rte:
- {fi-icl-guc}: [DMESG-WARN][7] -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-icl-guc/igt@i915_pm_...@basic-rte.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14301/fi-icl-guc/igt@i915_pm_...@basic-rte.html
* igt@i915_selftest@live_execlists:
- fi-skl-gvtdvm: [DMESG-FAIL][9] ([fdo#08]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14301/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
* igt@kms_chamelium@dp-crc-fast:
- fi-cml-u2: [FAIL][11] ([fdo#110627]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14301/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][13] ([fdo#111407]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14301/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_frontbuffer_tracking@basic:
- {fi-icl-u4}:[FAIL][15] ([fdo#103167]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14301/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
* igt@vgem_basic@unload:
- fi-icl-u3: [DMESG-WARN][17] ([fdo#107724]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-icl-u3/igt@vgem_ba...@unload.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14301/fi-icl-u3/igt@vgem_ba...@unload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#110627]: https://bugs.freedesktop.org/show_bug.cgi?id=110627
[fdo#08]: https://bugs.freedesktop.org/show_bug.cgi?id=08
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
Participating hosts (53 -> 47)
--
Additional (1): fi-tgl-u
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6841 -> Patchwork_14301
CI-20190529: 20190529
CI_DRM_6841: 5c24bcfb9c6036b32dbfdbc22d773473880ff498 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5171: 1911564805fe454919e8a5846534a0c1ef376a33 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14301: 81686dafe10427bc708ef7a1bd1e3592998c40b9 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
81686dafe104 drm/i915: List modes, regardless of encoder presence
== Logs ==
For more details see:
Re: [Intel-gfx] [PATCH v4 3/7] drm: Add DisplayPort colorspace property
On Fri, Sep 06, 2019 at 11:31:55AM +, Shankar, Uma wrote:
>
>
> >-Original Message-
> >From: Ilia Mirkin
> >Sent: Tuesday, September 3, 2019 6:12 PM
> >To: Mun, Gwan-gyeong
> >Cc: Intel Graphics Development ; Shankar,
> >Uma
> >; dri-devel
> >Subject: Re: [PATCH v4 3/7] drm: Add DisplayPort colorspace property
> >
> >So how would this work with a DP++ connector? Should it list the HDMI or DP
> >properties? Or do we need a custom property checker which is aware of what is
> >currently plugged in to validate the values?
>
> AFAIU For DP++ cases, we detect what kind of sink its driving DP or HDMI
> (with a passive dongle).
> Based on the type of sink detected, we should expose DP or HDMI colorspaces
> to userspace.
For i915 DP connector always drives DP mode, HDMI connector always drives
HDMI mode, even when the physical connector is DP++.
>
> >On Tue, Sep 3, 2019 at 5:12 AM Gwan-gyeong Mun
> >wrote:
> >>
> >> In order to use colorspace property to Display Port connectors, it
> >> extends DRM_MODE_CONNECTOR_DisplayPort connector_type on
> >> drm_mode_create_colorspace_property function.
> >>
> >> v3: Addressed review comments from Ville
> >> - Add new colorimetry options for DP 1.4a spec.
> >> - Separate set of colorimetry enum values for DP.
> >> v4: Add additional comments to struct drm_prop_enum_list.
> >> Polishing an enum string of struct drm_prop_enum_list
> >> Signed-off-by: Gwan-gyeong Mun
> >> Reviewed-by: Uma Shankar
> >> ---
> >> drivers/gpu/drm/drm_connector.c | 46 +
> >> include/drm/drm_connector.h | 8 ++
> >> 2 files changed, 54 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/drm_connector.c
> >> b/drivers/gpu/drm/drm_connector.c index 4c766624b20d..5834e6d330a0
> >> 100644
> >> --- a/drivers/gpu/drm/drm_connector.c
> >> +++ b/drivers/gpu/drm/drm_connector.c
> >> @@ -882,6 +882,44 @@ static const struct drm_prop_enum_list
> >hdmi_colorspaces[] = {
> >> { DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER,
> >> "DCI-P3_RGB_Theater" }, };
> >>
> >> +/*
> >> + * As per DP 1.4a spec, 2.2.5.7.5 VSC SDP Payload for Pixel
> >> +Encoding/Colorimetry
> >> + * Format Table 2-120
> >> + */
> >> +static const struct drm_prop_enum_list dp_colorspaces[] = {
> >> + /* For Default case, driver will set the colorspace */
> >> + { DRM_MODE_COLORIMETRY_DEFAULT, "Default" },
> >> + /* Colorimetry based on IEC 61966-2-1 */
> >> + { DRM_MODE_COLORIMETRY_SRGB, "sRGB" },
> >> + { DRM_MODE_COLORIMETRY_WIDE_GAMUT_FIXED_POINT_RGB,
> >"wide_gamut_fixed_point_RGB" },
> >> + /* Colorimetry based on IEC 61966-2-2, wide gamut floating point
> >> RGB */
> >> + { DRM_MODE_COLORIMETRY_SCRGB, "scRGB" },
> >> + { DRM_MODE_COLORIMETRY_ADOBE_RGB, "Adobe_RGB" },
> >> + /* Colorimetry based on SMPTE RP 431-2 */
> >> + { DRM_MODE_COLORIMETRY_DCP_P3_RGB, "DCI-P3_RGB" },
> >> + /* Colorimetry based on ITU-R BT.2020 */
> >> + { DRM_MODE_COLORIMETRY_BT2020_RGB, "BT2020_RGB" },
> >> + { DRM_MODE_COLORIMETRY_BT601_YCC, "BT601_YCC" },
> >> + { DRM_MODE_COLORIMETRY_BT709_YCC, "BT709_YCC" },
> >> + /* Standard Definition Colorimetry based on IEC 61966-2-4 */
> >> + { DRM_MODE_COLORIMETRY_XVYCC_601, "XVYCC_601" },
> >> + /* High Definition Colorimetry based on IEC 61966-2-4 */
> >> + { DRM_MODE_COLORIMETRY_XVYCC_709, "XVYCC_709" },
> >> + /* Colorimetry based on IEC 61966-2-1/Amendment 1 */
> >> + { DRM_MODE_COLORIMETRY_SYCC_601, "SYCC_601" },
> >> + /* Colorimetry based on IEC 61966-2-5 [33] */
> >> + { DRM_MODE_COLORIMETRY_OPYCC_601, "opYCC_601" },
> >> + /* Colorimetry based on ITU-R BT.2020 */
> >> + { DRM_MODE_COLORIMETRY_BT2020_CYCC, "BT2020_CYCC" },
> >> + /* Colorimetry based on ITU-R BT.2020 */
> >> + { DRM_MODE_COLORIMETRY_BT2020_YCC, "BT2020_YCC" },
> >> + /*
> >> +* Colorumetry based on Digital Imaging and Communications in
> >> Medicine
> >> +* (DICOM) Part 14: Grayscale Standard Display Function
> >> +*/
> >> + { DRM_MODE_COLORIMETRY_DICOM_PART_14_GRAYSCALE,
> >> +"DICOM_Part_14_Grayscale" }, };
> >> +
> >> /**
> >> * DOC: standard connector properties
> >> *
> >> @@ -1710,6 +1748,14 @@ int drm_mode_create_colorspace_property(struct
> >drm_connector *connector)
> >>
> >> ARRAY_SIZE(hdmi_colorspaces));
> >> if (!prop)
> >> return -ENOMEM;
> >> + } else if (connector->connector_type ==
> >DRM_MODE_CONNECTOR_DisplayPort ||
> >> + connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
> >> + prop = drm_property_create_enum(dev, DRM_MODE_PROP_ENUM,
> >> + "Colorspace",
> >> + dp_colorspaces,
> >> +
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: List modes, regardless of encoder presence (rev2)
== Series Details == Series: drm/i915: List modes, regardless of encoder presence (rev2) URL : https://patchwork.freedesktop.org/series/66330/ State : warning == Summary == $ dim checkpatch origin/drm-tip 81686dafe104 drm/i915: List modes, regardless of encoder presence -:22: WARNING:PREFER_SEQ_PUTS: Prefer seq_puts to seq_printf #22: FILE: drivers/gpu/drm/i915/i915_debugfs.c:2577: + seq_printf(m, "\tmodes:\n"); total: 0 errors, 1 warnings, 0 checks, 20 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/tgl: Use refclk/2 as bypass frequency
On Thu, Sep 05, 2019 at 11:13:37AM -0700, Matt Roper wrote:
> Unlike gen11, which always ran at 50MHz when the cdclk PLL was disabled,
> TGL runs at refclk/2. The 50MHz croclk/2 is only used by hardware
> during some power state transitions.
>
> Bspec: 49201
> Cc: José Roberto de Souza
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 7 +--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 76f11d465e91..d3e56628af70 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1855,8 +1855,6 @@ static void icl_get_cdclk(struct drm_i915_private
> *dev_priv,
> u32 val;
> int div;
>
> - cdclk_state->bypass = 5;
> -
> val = I915_READ(SKL_DSSM);
> switch (val & ICL_DSSM_CDCLK_PLL_REFCLK_MASK) {
> default:
> @@ -1873,6 +1871,11 @@ static void icl_get_cdclk(struct drm_i915_private
> *dev_priv,
> break;
> }
>
> + if (INTEL_GEN(dev_priv) >= 12)
> + cdclk_state->bypass = cdclk_state->ref / 2;
> + else
> + cdclk_state->bypass = 5;
Reviewed-by: Ville Syrjälä
PS. I'd still like to see a icl_cdclk_pll_update() so I wouldn't have to
scratch my head why this looks so different to bxt/cnl code.
> +
> val = I915_READ(BXT_DE_PLL_ENABLE);
> if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
> (val & BXT_DE_PLL_LOCK) == 0) {
> --
> 2.20.1
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 3/7] drm: Add DisplayPort colorspace property
>-Original Message-
>From: Ilia Mirkin
>Sent: Tuesday, September 3, 2019 6:12 PM
>To: Mun, Gwan-gyeong
>Cc: Intel Graphics Development ; Shankar, Uma
>; dri-devel
>Subject: Re: [PATCH v4 3/7] drm: Add DisplayPort colorspace property
>
>So how would this work with a DP++ connector? Should it list the HDMI or DP
>properties? Or do we need a custom property checker which is aware of what is
>currently plugged in to validate the values?
AFAIU For DP++ cases, we detect what kind of sink its driving DP or HDMI (with
a passive dongle).
Based on the type of sink detected, we should expose DP or HDMI colorspaces to
userspace.
>On Tue, Sep 3, 2019 at 5:12 AM Gwan-gyeong Mun
>wrote:
>>
>> In order to use colorspace property to Display Port connectors, it
>> extends DRM_MODE_CONNECTOR_DisplayPort connector_type on
>> drm_mode_create_colorspace_property function.
>>
>> v3: Addressed review comments from Ville
>> - Add new colorimetry options for DP 1.4a spec.
>> - Separate set of colorimetry enum values for DP.
>> v4: Add additional comments to struct drm_prop_enum_list.
>> Polishing an enum string of struct drm_prop_enum_list
>> Signed-off-by: Gwan-gyeong Mun
>> Reviewed-by: Uma Shankar
>> ---
>> drivers/gpu/drm/drm_connector.c | 46 +
>> include/drm/drm_connector.h | 8 ++
>> 2 files changed, 54 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/drm_connector.c
>> b/drivers/gpu/drm/drm_connector.c index 4c766624b20d..5834e6d330a0
>> 100644
>> --- a/drivers/gpu/drm/drm_connector.c
>> +++ b/drivers/gpu/drm/drm_connector.c
>> @@ -882,6 +882,44 @@ static const struct drm_prop_enum_list
>hdmi_colorspaces[] = {
>> { DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER,
>> "DCI-P3_RGB_Theater" }, };
>>
>> +/*
>> + * As per DP 1.4a spec, 2.2.5.7.5 VSC SDP Payload for Pixel
>> +Encoding/Colorimetry
>> + * Format Table 2-120
>> + */
>> +static const struct drm_prop_enum_list dp_colorspaces[] = {
>> + /* For Default case, driver will set the colorspace */
>> + { DRM_MODE_COLORIMETRY_DEFAULT, "Default" },
>> + /* Colorimetry based on IEC 61966-2-1 */
>> + { DRM_MODE_COLORIMETRY_SRGB, "sRGB" },
>> + { DRM_MODE_COLORIMETRY_WIDE_GAMUT_FIXED_POINT_RGB,
>"wide_gamut_fixed_point_RGB" },
>> + /* Colorimetry based on IEC 61966-2-2, wide gamut floating point RGB
>> */
>> + { DRM_MODE_COLORIMETRY_SCRGB, "scRGB" },
>> + { DRM_MODE_COLORIMETRY_ADOBE_RGB, "Adobe_RGB" },
>> + /* Colorimetry based on SMPTE RP 431-2 */
>> + { DRM_MODE_COLORIMETRY_DCP_P3_RGB, "DCI-P3_RGB" },
>> + /* Colorimetry based on ITU-R BT.2020 */
>> + { DRM_MODE_COLORIMETRY_BT2020_RGB, "BT2020_RGB" },
>> + { DRM_MODE_COLORIMETRY_BT601_YCC, "BT601_YCC" },
>> + { DRM_MODE_COLORIMETRY_BT709_YCC, "BT709_YCC" },
>> + /* Standard Definition Colorimetry based on IEC 61966-2-4 */
>> + { DRM_MODE_COLORIMETRY_XVYCC_601, "XVYCC_601" },
>> + /* High Definition Colorimetry based on IEC 61966-2-4 */
>> + { DRM_MODE_COLORIMETRY_XVYCC_709, "XVYCC_709" },
>> + /* Colorimetry based on IEC 61966-2-1/Amendment 1 */
>> + { DRM_MODE_COLORIMETRY_SYCC_601, "SYCC_601" },
>> + /* Colorimetry based on IEC 61966-2-5 [33] */
>> + { DRM_MODE_COLORIMETRY_OPYCC_601, "opYCC_601" },
>> + /* Colorimetry based on ITU-R BT.2020 */
>> + { DRM_MODE_COLORIMETRY_BT2020_CYCC, "BT2020_CYCC" },
>> + /* Colorimetry based on ITU-R BT.2020 */
>> + { DRM_MODE_COLORIMETRY_BT2020_YCC, "BT2020_YCC" },
>> + /*
>> +* Colorumetry based on Digital Imaging and Communications in
>> Medicine
>> +* (DICOM) Part 14: Grayscale Standard Display Function
>> +*/
>> + { DRM_MODE_COLORIMETRY_DICOM_PART_14_GRAYSCALE,
>> +"DICOM_Part_14_Grayscale" }, };
>> +
>> /**
>> * DOC: standard connector properties
>> *
>> @@ -1710,6 +1748,14 @@ int drm_mode_create_colorspace_property(struct
>drm_connector *connector)
>>
>> ARRAY_SIZE(hdmi_colorspaces));
>> if (!prop)
>> return -ENOMEM;
>> + } else if (connector->connector_type ==
>DRM_MODE_CONNECTOR_DisplayPort ||
>> + connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
>> + prop = drm_property_create_enum(dev, DRM_MODE_PROP_ENUM,
>> + "Colorspace",
>> + dp_colorspaces,
>> + ARRAY_SIZE(dp_colorspaces));
>> + if (!prop)
>> + return -ENOMEM;
>> } else {
>> DRM_DEBUG_KMS("Colorspace property not supported\n");
>> return 0;
>> diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
>> index 681cb590f952..8848e5d6b0c4 100644
>> --- a/include/drm/drm_connector.h
>> +++
[Intel-gfx] [PATCH v2] drm/i915: List modes, regardless of encoder presence
In certain situations encoder might be not present for connector, however might be useful to display probed modes for the connector, if any. v2: Fixed typo in the commit message Signed-off-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/i915_debugfs.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 9798f27a697a..8fa0510e897f 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2574,6 +2574,10 @@ static void intel_connector_info(struct seq_file *m, drm_get_subpixel_order_name(connector->display_info.subpixel_order)); seq_printf(m, "\tCEA rev: %d\n", connector->display_info.cea_rev); + seq_printf(m, "\tmodes:\n"); + list_for_each_entry(mode, >modes, head) + intel_seq_print_mode(m, 2, mode); + if (!intel_encoder) return; @@ -2597,10 +2601,6 @@ static void intel_connector_info(struct seq_file *m, default: break; } - - seq_printf(m, "\tmodes:\n"); - list_for_each_entry(mode, >modes, head) - intel_seq_print_mode(m, 2, mode); } static const char *plane_type(enum drm_plane_type type) -- 2.17.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/connector: Allow max possible encoders to attach to a connector
On Thu, Sep 05, 2019 at 02:09:27PM -0700, José Roberto de Souza wrote:
> From: Dhinakaran Pandiyan
>
> Currently we restrict the number of encoders that can be linked to
> a connector to 3, increase it to match the maximum number of encoders
> that can be initialized(32).
>
> To more effiently do that lets switch from an array of encoder ids to
> bitmask.
>
> Also removing the best_encoder hook from the drivers that only have
> one encoder per connector(this ones have one encoder in the whole
> driver), pick_single_encoder_for_connector() will do the same job
> with no functional change.
I don't think non-atomic drivers have that fallback in place.
They probable should...
Apart from that lgtm
Reviewed-by: Ville Syrjälä
>
> v2: Fixing missed return on amdgpu_dm_connector_to_encoder()
>
> Suggested-by: Ville Syrjälä
> Cc: Ville Syrjälä
> Cc: Alex Deucher
> Cc: dri-de...@lists.freedesktop.org
> Cc: intel-gfx@lists.freedesktop.org
> Cc: nouv...@lists.freedesktop.org
> Cc: amd-...@lists.freedesktop.org
> Signed-off-by: Dhinakaran Pandiyan
> Signed-off-by: José Roberto de Souza
> ---
> .../gpu/drm/amd/amdgpu/amdgpu_connectors.c| 23 +-
> drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 5 ++-
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +++-
> drivers/gpu/drm/ast/ast_mode.c| 12 ---
> drivers/gpu/drm/drm_atomic_helper.c | 9 --
> drivers/gpu/drm/drm_client_modeset.c | 3 +-
> drivers/gpu/drm/drm_connector.c | 31 +--
> drivers/gpu/drm/drm_probe_helper.c| 3 +-
> drivers/gpu/drm/mgag200/mgag200_mode.c| 11 ---
> drivers/gpu/drm/nouveau/dispnv04/disp.c | 2 +-
> drivers/gpu/drm/nouveau/dispnv50/disp.c | 2 +-
> drivers/gpu/drm/nouveau/nouveau_connector.c | 7 ++---
> drivers/gpu/drm/radeon/radeon_connectors.c| 27 ++--
> drivers/gpu/drm/udl/udl_connector.c | 8 -
> include/drm/drm_connector.h | 18 +--
> 15 files changed, 53 insertions(+), 114 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
> index ece55c8fa673..d8729285f731 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
> @@ -217,11 +217,10 @@ amdgpu_connector_update_scratch_regs(struct
> drm_connector *connector,
> struct drm_encoder *encoder;
> const struct drm_connector_helper_funcs *connector_funcs =
> connector->helper_private;
> bool connected;
> - int i;
>
> best_encoder = connector_funcs->best_encoder(connector);
>
> - drm_connector_for_each_possible_encoder(connector, encoder, i) {
> + drm_connector_for_each_possible_encoder(connector, encoder) {
> if ((encoder == best_encoder) && (status ==
> connector_status_connected))
> connected = true;
> else
> @@ -236,9 +235,8 @@ amdgpu_connector_find_encoder(struct drm_connector
> *connector,
> int encoder_type)
> {
> struct drm_encoder *encoder;
> - int i;
>
> - drm_connector_for_each_possible_encoder(connector, encoder, i) {
> + drm_connector_for_each_possible_encoder(connector, encoder) {
> if (encoder->encoder_type == encoder_type)
> return encoder;
> }
> @@ -347,10 +345,9 @@ static struct drm_encoder *
> amdgpu_connector_best_single_encoder(struct drm_connector *connector)
> {
> struct drm_encoder *encoder;
> - int i;
>
> /* pick the first one */
> - drm_connector_for_each_possible_encoder(connector, encoder, i)
> + drm_connector_for_each_possible_encoder(connector, encoder)
> return encoder;
>
> return NULL;
> @@ -1065,9 +1062,8 @@ amdgpu_connector_dvi_detect(struct drm_connector
> *connector, bool force)
> /* find analog encoder */
> if (amdgpu_connector->dac_load_detect) {
> struct drm_encoder *encoder;
> - int i;
>
> - drm_connector_for_each_possible_encoder(connector, encoder, i) {
> + drm_connector_for_each_possible_encoder(connector, encoder) {
> if (encoder->encoder_type != DRM_MODE_ENCODER_DAC &&
> encoder->encoder_type != DRM_MODE_ENCODER_TVDAC)
> continue;
> @@ -1117,9 +1113,8 @@ amdgpu_connector_dvi_encoder(struct drm_connector
> *connector)
> {
> struct amdgpu_connector *amdgpu_connector =
> to_amdgpu_connector(connector);
> struct drm_encoder *encoder;
> - int i;
>
> - drm_connector_for_each_possible_encoder(connector, encoder, i) {
> + drm_connector_for_each_possible_encoder(connector, encoder) {
> if (amdgpu_connector->use_digital == true) {
> if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
>
Re: [Intel-gfx] [PATCH v1] drm/i915: List modes, regardless of encoder presence
On Fri, 2019-09-06 at 14:23 +0300, Lionel Landwerlin wrote: > On 06/09/2019 14:14, Stanislav Lisovskiy wrote: > > In certain situations encoder might be not present for connector, > > however might be useful to displat probed modes for the connector, > > s/displat/display/ Thanks! :) - Stanislav > > > > if any. > > > > Signed-off-by: Stanislav Lisovskiy > > Tested-by: Lionel Landwerlin > > --- > > drivers/gpu/drm/i915/i915_debugfs.c | 8 > > 1 file changed, 4 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c > > b/drivers/gpu/drm/i915/i915_debugfs.c > > index 9798f27a697a..8fa0510e897f 100644 > > --- a/drivers/gpu/drm/i915/i915_debugfs.c > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > > @@ -2574,6 +2574,10 @@ static void intel_connector_info(struct > > seq_file *m, > >drm_get_subpixel_order_name(connector- > > >display_info.subpixel_order)); > > seq_printf(m, "\tCEA rev: %d\n", connector- > > >display_info.cea_rev); > > > > + seq_printf(m, "\tmodes:\n"); > > + list_for_each_entry(mode, >modes, head) > > + intel_seq_print_mode(m, 2, mode); > > + > > if (!intel_encoder) > > return; > > > > @@ -2597,10 +2601,6 @@ static void intel_connector_info(struct > > seq_file *m, > > default: > > break; > > } > > - > > - seq_printf(m, "\tmodes:\n"); > > - list_for_each_entry(mode, >modes, head) > > - intel_seq_print_mode(m, 2, mode); > > } > > > > static const char *plane_type(enum drm_plane_type type) > > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v1] drm/i915: List modes, regardless of encoder presence
On 06/09/2019 14:14, Stanislav Lisovskiy wrote: In certain situations encoder might be not present for connector, however might be useful to displat probed modes for the connector, s/displat/display/ if any. Signed-off-by: Stanislav Lisovskiy Tested-by: Lionel Landwerlin --- drivers/gpu/drm/i915/i915_debugfs.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 9798f27a697a..8fa0510e897f 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2574,6 +2574,10 @@ static void intel_connector_info(struct seq_file *m, drm_get_subpixel_order_name(connector->display_info.subpixel_order)); seq_printf(m, "\tCEA rev: %d\n", connector->display_info.cea_rev); + seq_printf(m, "\tmodes:\n"); + list_for_each_entry(mode, >modes, head) + intel_seq_print_mode(m, 2, mode); + if (!intel_encoder) return; @@ -2597,10 +2601,6 @@ static void intel_connector_info(struct seq_file *m, default: break; } - - seq_printf(m, "\tmodes:\n"); - list_for_each_entry(mode, >modes, head) - intel_seq_print_mode(m, 2, mode); } static const char *plane_type(enum drm_plane_type type) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Account for CD2X divider in ICL+ vco calculation
On Thu, Sep 05, 2019 at 02:38:24PM -0700, Matt Roper wrote:
> When calculating the PLL ratio we were still assuming that the CD2X
> divider is always /1. For the new frequencies that use a /2 divider
> that needs to be accounted for, otherwise our VCO result will be twice
> as large as it should be.
>
> Fixes: 3d1da92baffe ("drm/i915: Add 324mhz and 326.4mhz cdclks for gen11+")
> Cc: José Roberto de Souza
> Cc: Lucas De Marchi
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 17 ++---
> 1 file changed, 14 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 1329d3e60e26..55801aeefd1c 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1794,6 +1794,7 @@ static int icl_calc_cdclk(int min_cdclk, unsigned int
> ref)
>
> static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int
> cdclk)
> {
> + int cd2xdiv;
> int ratio;
>
> if (cdclk == dev_priv->cdclk.hw.bypass)
> @@ -1805,27 +1806,37 @@ static int icl_calc_cdclk_pll_vco(struct
> drm_i915_private *dev_priv, int cdclk)
> /* fall through */
> case 172800:
> case 307200:
> - case 326400:
> case 556800:
> case 652800:
> + cd2xdiv = 1;
> WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
> dev_priv->cdclk.hw.ref != 38400);
> break;
> case 18:
> case 312000:
> - case 324000:
> case 552000:
> case 648000:
> + cd2xdiv = 1;
> WARN_ON(dev_priv->cdclk.hw.ref != 24000);
> break;
> case 192000:
> + cd2xdiv = 1;
> WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
> dev_priv->cdclk.hw.ref != 38400 &&
> dev_priv->cdclk.hw.ref != 24000);
> break;
> + case 326400:
> + cd2xdiv = 2;
> + WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
> + dev_priv->cdclk.hw.ref != 38400);
> + break;
> + case 324000:
> + cd2xdiv = 2;
> + WARN_ON(dev_priv->cdclk.hw.ref != 24000);
> + break;
> }
>
> - ratio = cdclk / (dev_priv->cdclk.hw.ref / 2);
> + ratio = cdclk / (dev_priv->cdclk.hw.ref / cd2xdiv / 2);
>
> return dev_priv->cdclk.hw.ref * ratio;
Isn't that just cdclk*cd2xdiv*2 ?
I do kinda like the idea of not hardcoding the vco ratio here.
We should probably do the same for the older platforms as well...
> }
> --
> 2.20.1
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v1] drm/i915: List modes, regardless of encoder presence
In certain situations encoder might be not present for connector, however might be useful to displat probed modes for the connector, if any. Signed-off-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/i915_debugfs.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 9798f27a697a..8fa0510e897f 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2574,6 +2574,10 @@ static void intel_connector_info(struct seq_file *m, drm_get_subpixel_order_name(connector->display_info.subpixel_order)); seq_printf(m, "\tCEA rev: %d\n", connector->display_info.cea_rev); + seq_printf(m, "\tmodes:\n"); + list_for_each_entry(mode, >modes, head) + intel_seq_print_mode(m, 2, mode); + if (!intel_encoder) return; @@ -2597,10 +2601,6 @@ static void intel_connector_info(struct seq_file *m, default: break; } - - seq_printf(m, "\tmodes:\n"); - list_for_each_entry(mode, >modes, head) - intel_seq_print_mode(m, 2, mode); } static const char *plane_type(enum drm_plane_type type) -- 2.17.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for Send a hotplug when edid changes (rev7)
== Series Details == Series: Send a hotplug when edid changes (rev7) URL : https://patchwork.freedesktop.org/series/62816/ State : success == Summary == CI Bug Log - changes from CI_DRM_6841_full -> Patchwork_14299_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14299_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@rcs0-s3: - shard-iclb: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] / [fdo#109100]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/shard-iclb4/igt@gem_ctx_isolat...@rcs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14299/shard-iclb3/igt@gem_ctx_isolat...@rcs0-s3.html * igt@gem_exec_async@concurrent-writes-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#111325]) +4 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/shard-iclb8/igt@gem_exec_as...@concurrent-writes-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14299/shard-iclb2/igt@gem_exec_as...@concurrent-writes-bsd.html * igt@gem_exec_schedule@preempt-queue-bsd1: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276]) +21 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/shard-iclb4/igt@gem_exec_sched...@preempt-queue-bsd1.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14299/shard-iclb3/igt@gem_exec_sched...@preempt-queue-bsd1.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([fdo#108566]) +5 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/shard-apl8/igt@i915_susp...@fence-restore-tiled2untiled.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14299/shard-apl3/igt@i915_susp...@fence-restore-tiled2untiled.html * igt@kms_flip@dpms-vs-vblank-race: - shard-glk: [PASS][9] -> [FAIL][10] ([fdo#103060]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/shard-glk5/igt@kms_f...@dpms-vs-vblank-race.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14299/shard-glk9/igt@kms_f...@dpms-vs-vblank-race.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-skl: [PASS][11] -> [FAIL][12] ([fdo#105363]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/shard-skl5/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14299/shard-skl6/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt: - shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103167]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/shard-iclb8/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14299/shard-iclb2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff: - shard-skl: [PASS][15] -> [FAIL][16] ([fdo#103167]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/shard-skl5/igt@kms_frontbuffer_track...@psr-1p-primscrn-spr-indfb-onoff.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14299/shard-skl7/igt@kms_frontbuffer_track...@psr-1p-primscrn-spr-indfb-onoff.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/shard-skl5/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14299/shard-skl7/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html * igt@kms_plane_lowres@pipe-a-tiling-x: - shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103166]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/shard-iclb2/igt@kms_plane_low...@pipe-a-tiling-x.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14299/shard-iclb7/igt@kms_plane_low...@pipe-a-tiling-x.html * igt@kms_psr@psr2_sprite_mmap_gtt: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14299/shard-iclb5/igt@kms_psr@psr2_sprite_mmap_gtt.html * igt@kms_setmode@basic: - shard-hsw: [PASS][23] -> [FAIL][24] ([fdo#99912]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/shard-hsw7/igt@kms_setm...@basic.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14299/shard-hsw7/igt@kms_setm...@basic.html Possible fixes *
[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Vulkan performance query support (rev16)
== Series Details == Series: drm/i915: Vulkan performance query support (rev16) URL : https://patchwork.freedesktop.org/series/60916/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h AR drivers/gpu/drm/i915/built-in.a CC drivers/gpu/drm/i915/i915_perf_types.h.s In file included from :0:0: ./drivers/gpu/drm/i915/i915_perf_types.h:25:2: error: unknown type name ‘i915_reg_t’ i915_reg_t addr; ^~ ./drivers/gpu/drm/i915/i915_perf_types.h:32:12: error: ‘UUID_STRING_LEN’ undeclared here (not in a function); did you mean ‘_LINUX_STRING_H_’? char uuid[UUID_STRING_LEN + 1]; ^~~ _LINUX_STRING_H_ ./drivers/gpu/drm/i915/i915_perf_types.h:75:6: error: unknown type name ‘poll_table’; did you mean ‘PG_table’? poll_table *wait); ^~ PG_table ./drivers/gpu/drm/i915/i915_perf_types.h:128:2: error: unknown type name ‘intel_wakeref_t’ intel_wakeref_t wakeref; ^~~ ./drivers/gpu/drm/i915/i915_perf_types.h:196:29: error: field ‘active_config_rq’ has incomplete type struct i915_active_request active_config_rq; ^~~~ scripts/Makefile.build:308: recipe for target 'drivers/gpu/drm/i915/i915_perf_types.h.s' failed make[4]: *** [drivers/gpu/drm/i915/i915_perf_types.h.s] Error 1 scripts/Makefile.build:497: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:497: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:497: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1083: recipe for target 'drivers' failed make: *** [drivers] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v15 08/13] drm/i915/perf: implement active wait for noa configurations
NOA configuration take some amount of time to apply. That amount of
time depends on the size of the GT. There is no documented time for
this. For example, past experimentations with powergating
configuration changes seem to indicate a 60~70us delay. We go with
500us as default for now which should be over the required amount of
time (according to HW architects).
v2: Don't forget to save/restore registers used for the wait (Chris)
v3: Name used CS_GPR registers (Chris)
Fix compile issue due to rebase (Lionel)
v4: Fix save/restore helpers (Umesh)
v5: Move noa_wait from drm_i915_private to i915_perf_stream (Lionel)
v6: Add missing struct declarations in i915_perf.h
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson (v4)
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 24 ++
drivers/gpu/drm/i915/gt/intel_gt_types.h | 5 +
drivers/gpu/drm/i915/i915_debugfs.c | 31 +++
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_perf.c | 234 ++-
drivers/gpu/drm/i915/i915_perf_types.h | 6 +
drivers/gpu/drm/i915/i915_reg.h | 4 +-
7 files changed, 302 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index a7f1377a54a2..f133f8dbacb1 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -158,6 +158,7 @@
#define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
#define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
#define MI_BATCH_RESOURCE_STREAMER (1<<10)
+#define MI_BATCH_PREDICATE (1 << 15) /* HSW+ on RCS only*/
/*
* 3D instructions used by the kernel
@@ -236,6 +237,29 @@
#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
+#define MI_MATH(x) MI_INSTR(0x1a, (x)-1)
+#define MI_ALU_OP(op, src1, src2) (((op) << 20) | ((src1) << 10) | (src2))
+/* operands */
+#define MI_ALU_OP_NOOP 0
+#define MI_ALU_OP_LOAD 128
+#define MI_ALU_OP_LOADINV 1152
+#define MI_ALU_OP_LOAD0129
+#define MI_ALU_OP_LOAD11153
+#define MI_ALU_OP_ADD 256
+#define MI_ALU_OP_SUB 257
+#define MI_ALU_OP_AND 258
+#define MI_ALU_OP_OR 259
+#define MI_ALU_OP_XOR 260
+#define MI_ALU_OP_STORE384
+#define MI_ALU_OP_STOREINV 1408
+/* sources */
+#define MI_ALU_SRC_REG(x) (x) /* 0 -> 15 */
+#define MI_ALU_SRC_SRCA32
+#define MI_ALU_SRC_SRCB33
+#define MI_ALU_SRC_ACCU49
+#define MI_ALU_SRC_ZF 50
+#define MI_ALU_SRC_CF 51
+
/*
* Commands used only by the command parser
*/
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index dc295c196d11..f752b6cf9ea1 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -97,6 +97,11 @@ enum intel_gt_scratch_field {
/* 8 bytes */
INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA = 256,
+ /* 6 * 8 bytes */
+ INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR = 2048,
+
+ /* 4 bytes */
+ INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1 = 2096,
};
#endif /* __INTEL_GT_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 9798f27a697a..8bb15f899d97 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3572,6 +3572,36 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
i915_wedged_get, i915_wedged_set,
"%llu\n");
+static int
+i915_perf_noa_delay_set(void *data, u64 val)
+{
+ struct drm_i915_private *i915 = data;
+
+ /* This would lead to infinite waits as we're doing timestamp
+* difference on the CS with only 32bits.
+*/
+ if (val > mul_u32_u32(U32_MAX,
RUNTIME_INFO(i915)->cs_timestamp_frequency_khz))
+ return -EINVAL;
+
+ atomic64_set(>perf.noa_programming_delay, val);
+ return 0;
+}
+
+static int
+i915_perf_noa_delay_get(void *data, u64 *val)
+{
+ struct drm_i915_private *i915 = data;
+
+ *val = atomic64_read(>perf.noa_programming_delay);
+ return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(i915_perf_noa_delay_fops,
+ i915_perf_noa_delay_get,
+ i915_perf_noa_delay_set,
+ "%llu\n");
+
+
#define DROP_UNBOUND BIT(0)
#define DROP_BOUND BIT(1)
#define DROP_RETIREBIT(2)
@@ -4348,6 +4378,7 @@ static const struct i915_debugfs_files {
const char *name;
const struct file_operations *fops;
} i915_debugfs_files[] = {
+ {"i915_perf_noa_delay", _perf_noa_delay_fops},
{"i915_wedged", _wedged_fops},
{"i915_cache_sharing", _cache_sharing_fops},
{"i915_gem_drop_caches", _drop_caches_fops},
diff --git
[Intel-gfx] [PATCH v15 10/13] drm/i915/perf: execute OA configuration from command stream
We haven't run into issues with programming the global OA/NOA
registers configuration from CPU so far, but HW engineers actually
recommend doing this from the command streamer. On TGL in particular
one of the clock domain in which some of that programming goes might
not be powered when we poke things from the CPU.
Since we have a command buffer prepared for the execbuffer side of
things, we can reuse that approach here too.
This also allows us to significantly reduce the amount of time we hold
the main lock.
v2: Drop the global lock as much as possible
v3: Take global lock to pin global
v4: Create i915 request in emit_oa_config() to avoid deadlocks (Lionel)
v5: Move locking to the stream (Lionel)
v6: Move active reconfiguration request into i915_perf_stream (Lionel)
v7: Pin VMA outside request creation (Chris)
Lock VMA before move to active (Chris)
v8: Fix double free on stream->initial_oa_config_bo (Lionel)
Don't allow interruption when waiting on active config request
(Lionel)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 170 -
drivers/gpu/drm/i915/i915_perf_types.h | 13 +-
2 files changed, 122 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index f2b778d84b52..8e3532518139 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1558,18 +1558,23 @@ free_oa_configs(struct i915_perf_stream *stream)
static void i915_oa_stream_destroy(struct i915_perf_stream *stream)
{
struct drm_i915_private *dev_priv = stream->dev_priv;
+ int err;
BUG_ON(stream != dev_priv->perf.exclusive_stream);
- /*
-* Unset exclusive_stream first, it will be checked while disabling
-* the metric set on gen8+.
-*/
mutex_lock(_priv->drm.struct_mutex);
- dev_priv->perf.exclusive_stream = NULL;
+ mutex_lock(>config_mutex);
dev_priv->perf.ops.disable_metric_set(stream);
+ err = i915_active_request_retire(>active_config_rq, 0,
+>config_mutex);
+ mutex_unlock(>config_mutex);
+ dev_priv->perf.exclusive_stream = NULL;
mutex_unlock(_priv->drm.struct_mutex);
+ if (err)
+ DRM_ERROR("Failed to disable perf stream\n");
+
+
free_oa_buffer(stream);
free_noa_wait(stream);
@@ -1795,6 +1800,10 @@ static int alloc_noa_wait(struct i915_perf_stream
*stream)
return PTR_ERR(bo);
}
+ ret = i915_mutex_lock_interruptible(>drm);
+ if (ret)
+ goto err_unref;
+
/*
* We pin in GGTT because we jump into this buffer now because
* multiple OA config BOs will have a jump to this address and it
@@ -1802,10 +1811,13 @@ static int alloc_noa_wait(struct i915_perf_stream
*stream)
*/
vma = i915_gem_object_ggtt_pin(bo, NULL, 0, 4096, 0);
if (IS_ERR(vma)) {
+ mutex_unlock(>drm.struct_mutex);
ret = PTR_ERR(vma);
goto err_unref;
}
+ mutex_unlock(>drm.struct_mutex);
+
batch = cs = i915_gem_object_pin_map(bo, I915_MAP_WB);
if (IS_ERR(batch)) {
ret = PTR_ERR(batch);
@@ -1939,7 +1951,9 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
return 0;
err_unpin:
- __i915_vma_unpin(vma);
+ mutex_lock(>drm.struct_mutex);
+ i915_vma_unpin_and_release(, 0);
+ mutex_unlock(>drm.struct_mutex);
err_unref:
i915_gem_object_put(bo);
@@ -1947,50 +1961,73 @@ static int alloc_noa_wait(struct i915_perf_stream
*stream)
return ret;
}
-static void config_oa_regs(struct drm_i915_private *dev_priv,
- const struct i915_oa_reg *regs,
- u32 n_regs)
+static int emit_oa_config(struct drm_i915_private *i915,
+ struct i915_perf_stream *stream)
{
- u32 i;
+ struct i915_request *rq;
+ struct i915_vma *vma;
+ u32 *cs;
+ int err;
- for (i = 0; i < n_regs; i++) {
- const struct i915_oa_reg *reg = regs + i;
+ lockdep_assert_held(>config_mutex);
+
+ vma = i915_vma_instance(stream->initial_oa_config_bo,
+ >engine->gt->ggtt->vm, NULL);
+ if (unlikely(IS_ERR(vma)))
+ return PTR_ERR(vma);
- I915_WRITE(reg->addr, reg->value);
+ err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL);
+ if (err)
+ goto err_vma_unpin;
+
+ rq = i915_request_create(stream->engine->kernel_context);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto err_add_request;
}
-}
-static void delay_after_mux(void)
-{
- /*
-* It apparently takes a fairly long time for a new MUX
-* configuration to be be applied after these register writes.
-
[Intel-gfx] [PATCH v15 12/13] drm/i915/perf: allow holding preemption on filtered ctx
We would like to make use of perf in Vulkan. The Vulkan API is much
lower level than OpenGL, with applications directly exposed to the
concept of command buffers (pretty much equivalent to our batch
buffers). In Vulkan, queries are always limited in scope to a command
buffer. In OpenGL, the lack of command buffer concept meant that
queries' duration could span multiple command buffers.
With that restriction gone in Vulkan, we would like to simplify
measuring performance just by measuring the deltas between the counter
snapshots written by 2 MI_RECORD_PERF_COUNT commands, rather than the
more complex scheme we currently have in the GL driver, using 2
MI_RECORD_PERF_COUNT commands and doing some post processing on the
stream of OA reports, coming from the global OA buffer, to remove any
unrelated deltas in between the 2 MI_RECORD_PERF_COUNT.
Disabling preemption only apply to a single context with which want to
query performance counters for and is considered a privileged
operation, by default protected by CAP_SYS_ADMIN. It is possible to
enable it for a normal user by disabling the paranoid stream setting.
v2: Store preemption setting in intel_context (Chris)
v3: Use priorities to avoid preemption rather than the HW mechanism
v4: Just modify the port priority reporting function
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 8 +
drivers/gpu/drm/i915/i915_perf.c | 31 +--
drivers/gpu/drm/i915/i915_perf_types.h| 8 +
include/uapi/drm/i915_drm.h | 11 +++
4 files changed, 55 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index d416b60c94bb..33df58e681fe 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -2128,6 +2128,14 @@ static int eb_oa_config(struct i915_execbuffer *eb)
if (err)
goto out;
+ /*
+* If the perf stream was opened with hold preemption, flag the
+* request properly so that the priority of the request is bumped once
+* it reaches the execlist ports.
+*/
+ if (eb->i915->perf.exclusive_stream->hold_preemption)
+ eb->request->flags |= I915_REQUEST_NOPREEMPT;
+
/*
* If the config hasn't changed, skip reconfiguring the HW (this is
* subject to a delay we want to avoid has much as possible).
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 8e3532518139..7adc518912bb 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -343,6 +343,8 @@ static const struct i915_oa_format
gen8_plus_oa_formats[I915_OA_FORMAT_MAX] = {
* struct perf_open_properties - for validated properties given to open a
stream
* @sample_flags: `DRM_I915_PERF_PROP_SAMPLE_*` properties are tracked as flags
* @single_context: Whether a single or all gpu contexts should be monitored
+ * @hold_preemption: Whether the preemption is disabled for the filtered
+ * context
* @ctx_handle: A gem ctx handle for use with @single_context
* @metrics_set: An ID for an OA unit metric set advertised via sysfs
* @oa_format: An OA unit HW report format
@@ -357,6 +359,7 @@ struct perf_open_properties {
u32 sample_flags;
u64 single_context:1;
+ u64 hold_preemption:1;
u64 ctx_handle;
/* OA sampling state */
@@ -2632,6 +2635,8 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
if (WARN_ON(stream->oa_buffer.format_size == 0))
return -EINVAL;
+ stream->hold_preemption = props->hold_preemption;
+
stream->oa_buffer.format =
dev_priv->perf.oa_formats[props->oa_format].format;
@@ -3187,6 +3192,15 @@ i915_perf_open_ioctl_locked(struct drm_i915_private
*dev_priv,
}
}
+ if (props->hold_preemption) {
+ if (!props->single_context) {
+ DRM_DEBUG("preemption disable with no context\n");
+ ret = -EINVAL;
+ goto err;
+ }
+ privileged_op = true;
+ }
+
/*
* On Haswell the OA unit supports clock gating off for a specific
* context and in this mode there's no visibility of metrics for the
@@ -3201,8 +3215,9 @@ i915_perf_open_ioctl_locked(struct drm_i915_private
*dev_priv,
* MI_REPORT_PERF_COUNT commands and so consider it a privileged op to
* enable the OA unit by default.
*/
- if (IS_HASWELL(dev_priv) && specific_ctx)
+ if (IS_HASWELL(dev_priv) && specific_ctx && !props->hold_preemption) {
privileged_op = false;
+ }
/* Similar to perf's kernel.perf_paranoid_cpu sysctl option
* we check a
[Intel-gfx] [PATCH v15 13/13] drm/i915: add support for perf configuration queries
Listing configurations at the moment is supported only through sysfs.
This might cause issues for applications wanting to list
configurations from a container where sysfs isn't available.
This change adds a way to query the number of configurations and their
content through the i915 query uAPI.
v2: Fix sparse warnings (Lionel)
Add support to query configuration using uuid (Lionel)
v3: Fix some inconsistency in uapi header (Lionel)
Fix unlocking when not locked issue (Lionel)
Add debug messages (Lionel)
v4: Fix missing unlock (Dan)
v5: Drop lock when copying config content to userspace (Chris)
v6: Drop lock when copying config list to userspace (Chris)
Fix deadlock when calling i915_perf_get_oa_config() under
perf.metrics_lock (Lionel)
Add i915_oa_config_get() (Chris)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 6 +
drivers/gpu/drm/i915/i915_perf.c | 3 +
drivers/gpu/drm/i915/i915_query.c | 283 ++
include/uapi/drm/i915_drm.h | 65 ++-
4 files changed, 354 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2c6f37219dff..eab42269fc5b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1368,6 +1368,12 @@ struct drm_i915_private {
*/
struct idr metrics_idr;
+ /*
+* Number of dynamic configurations, you need to hold
+* dev_priv->perf.metrics_lock to access it.
+*/
+ u32 n_metrics;
+
/*
* Lock associated with anything below within this structure
* except exclusive_stream.
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 7adc518912bb..372cdf2e7ec8 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3915,6 +3915,8 @@ int i915_perf_add_config_ioctl(struct drm_device *dev,
void *data,
goto sysfs_err;
}
+ dev_priv->perf.n_metrics++;
+
mutex_unlock(_priv->perf.metrics_lock);
DRM_DEBUG("Added config %s id=%i\n", oa_config->uuid, oa_config->id);
@@ -3975,6 +3977,7 @@ int i915_perf_remove_config_ioctl(struct drm_device *dev,
void *data,
_config->sysfs_metric);
idr_remove(_priv->perf.metrics_idr, *arg);
+ dev_priv->perf.n_metrics--;
mutex_unlock(_priv->perf.metrics_lock);
diff --git a/drivers/gpu/drm/i915/i915_query.c
b/drivers/gpu/drm/i915/i915_query.c
index abac5042da2b..89b2821be4a0 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -7,6 +7,7 @@
#include
#include "i915_drv.h"
+#include "i915_perf.h"
#include "i915_query.h"
#include
@@ -140,10 +141,292 @@ query_engine_info(struct drm_i915_private *i915,
return len;
}
+static int can_copy_perf_config_registers_or_number(u32 user_n_regs,
+ u64 user_regs_ptr,
+ u32 kernel_n_regs)
+{
+ /*
+* We'll just put the number of registers, and won't copy the
+* register.
+*/
+ if (user_n_regs == 0)
+ return 0;
+
+ if (user_n_regs < kernel_n_regs)
+ return -EINVAL;
+
+ if (!access_ok(u64_to_user_ptr(user_regs_ptr),
+ 2 * sizeof(u32) * kernel_n_regs))
+ return -EFAULT;
+
+ return 0;
+}
+
+static int copy_perf_config_registers_or_number(const struct i915_oa_reg
*kernel_regs,
+ u32 kernel_n_regs,
+ u64 user_regs_ptr,
+ u32 *user_n_regs)
+{
+ u32 r;
+
+ if (*user_n_regs == 0) {
+ *user_n_regs = kernel_n_regs;
+ return 0;
+ }
+
+ *user_n_regs = kernel_n_regs;
+
+ for (r = 0; r < kernel_n_regs; r++) {
+ u32 __user *user_reg_ptr =
+ u64_to_user_ptr(user_regs_ptr + sizeof(u32) * r * 2);
+ u32 __user *user_val_ptr =
+ u64_to_user_ptr(user_regs_ptr + sizeof(u32) * r * 2 +
+ sizeof(u32));
+ int ret;
+
+ ret = __put_user(i915_mmio_reg_offset(kernel_regs[r].addr),
+user_reg_ptr);
+ if (ret)
+ return -EFAULT;
+
+ ret = __put_user(kernel_regs[r].value, user_val_ptr);
+ if (ret)
+ return -EFAULT;
+ }
+
+ return 0;
+}
+
+static int query_perf_config_data(struct drm_i915_private *i915,
+ struct drm_i915_query_item *query_item,
+ bool use_uuid)
[Intel-gfx] [PATCH v15 11/13] drm/i915: add a new perf configuration execbuf parameter
We want the ability to dispatch a set of command buffer to the
hardware, each with a different OA configuration. To achieve this, we
reuse a couple of fields from the execbuf2 struct (I CAN HAZ
execbuf3?) to notify what OA configuration should be used for a batch
buffer. This requires the process making the execbuf with this flag to
also own the perf fd at the time of execbuf.
v2: Add a emit_oa_config() vfunc in the intel_engine_cs (Chris)
Move oa_config vma to active (Chris)
v3: Don't drop the lock for engine lookup (Chris)
Move OA config vma to active before writing the ringbuffer (Chris)
v4: Reuse i915_user_extension_fn
Serialize requests with OA config updates
v5: Check that the chained extension is only present once (Chris)
Unpin oa_vma in main path (Chris)
v6: Use BIT_ULL (Chris)
v7: Hold drm.struct_mutex when serializing the request with OA config (Chris)
v8: Remove active request from engine (Lionel)
v9: Move fetching OA configuration pass engine pinning (Lionel)
Lock VMA before moving to active (Chris)
v10: Fix leak on perf_fd (Lionel)
Signed-off-by: Lionel Landwerlin
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 147 +-
drivers/gpu/drm/i915/i915_getparam.c | 4 +
include/uapi/drm/i915_drm.h | 39 +
3 files changed, 188 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 46ad8d9642d1..d416b60c94bb 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -24,6 +24,7 @@
#include "i915_gem_clflush.h"
#include "i915_gem_context.h"
#include "i915_gem_ioctls.h"
+#include "i915_perf.h"
#include "i915_trace.h"
#include "i915_user_extensions.h"
@@ -284,7 +285,12 @@ struct i915_execbuffer {
struct {
u64 flags; /** Available extensions parameters */
struct drm_i915_gem_execbuffer_ext_timeline_fences
timeline_fences;
+ struct drm_i915_gem_execbuffer_ext_perf perf_config;
} extensions;
+
+ struct file *perf_file;
+ struct i915_oa_config *oa_config; /** HW configuration for OA, NULL is
not needed. */
+ struct i915_vma *oa_vma;
};
#define exec_entry(EB, VMA) (&(EB)->exec[(VMA)->exec_flags - (EB)->flags])
@@ -1152,6 +1158,58 @@ static int reloc_move_to_gpu(struct i915_request *rq,
struct i915_vma *vma)
return err;
}
+
+static int
+eb_get_oa_config(struct i915_execbuffer *eb)
+{
+ struct drm_i915_gem_object *oa_bo;
+ int err = 0;
+
+ eb->perf_file = NULL;
+ eb->oa_config = NULL;
+ eb->oa_vma = NULL;
+
+ if ((eb->extensions.flags & BIT_ULL(DRM_I915_GEM_EXECBUFFER_EXT_PERF))
== 0)
+ return 0;
+
+ eb->perf_file = fget(eb->extensions.perf_config.perf_fd);
+ if (!eb->perf_file)
+ return -EINVAL;
+
+ err = i915_mutex_lock_interruptible(>i915->drm);
+ if (err)
+ return err;
+
+ if (eb->perf_file->private_data != eb->i915->perf.exclusive_stream)
+ err = -EINVAL;
+
+ mutex_unlock(>i915->drm.struct_mutex);
+
+ if (err)
+ return err;
+
+ if (eb->i915->perf.exclusive_stream->engine != eb->engine)
+ return -EINVAL;
+
+ err = i915_perf_get_oa_config_and_bo(
+ eb->i915->perf.exclusive_stream,
+ eb->extensions.perf_config.oa_config,
+ >oa_config, _bo);
+ if (err)
+ return err;
+
+ eb->oa_vma = i915_vma_instance(oa_bo,
+ >engine->gt->ggtt->vm, NULL);
+ i915_gem_object_put(oa_bo);
+ if (IS_ERR(eb->oa_vma)) {
+ err = PTR_ERR(eb->oa_vma);
+ eb->oa_vma = NULL;
+ return err;
+ }
+
+ return 0;
+}
+
static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
struct i915_vma *vma,
unsigned int len)
@@ -2051,6 +2109,54 @@ add_to_client(struct i915_request *rq, struct drm_file
*file)
spin_unlock(_priv->mm.lock);
}
+static int eb_oa_config(struct i915_execbuffer *eb)
+{
+ struct i915_perf_stream *perf_stream;
+ int err;
+
+ if (!eb->oa_config)
+ return 0;
+
+ perf_stream = eb->perf_file->private_data;
+
+ err = mutex_lock_interruptible(_stream->config_mutex);
+ if (err)
+ return err;
+
+ err = i915_active_request_set(_stream->active_config_rq,
+ eb->request);
+ if (err)
+ goto out;
+
+ /*
+* If the config hasn't changed, skip reconfiguring the HW (this is
+* subject to a delay we want to avoid has much as possible).
+*/
+ if (eb->oa_config == perf_stream->oa_config)
+ goto out;
+
+ i915_vma_lock(eb->oa_vma);
+
[Intel-gfx] [PATCH v15 09/13] drm/i915: add wait flags to i915_active_request_retire
An upcoming change needs not to be interrupted.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_active.c | 4 +++-
drivers/gpu/drm/i915/i915_active.h | 5 ++---
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_active.c
b/drivers/gpu/drm/i915/i915_active.c
index 6a447f1d0110..c808c28c9464 100644
--- a/drivers/gpu/drm/i915/i915_active.c
+++ b/drivers/gpu/drm/i915/i915_active.c
@@ -425,7 +425,9 @@ int i915_active_wait(struct i915_active *ref)
break;
}
- err = i915_active_request_retire(>base, BKL(ref));
+ err = i915_active_request_retire(>base,
+I915_WAIT_INTERRUPTIBLE,
+BKL(ref));
if (err)
break;
}
diff --git a/drivers/gpu/drm/i915/i915_active.h
b/drivers/gpu/drm/i915/i915_active.h
index f95058f99057..35a6089b44fd 100644
--- a/drivers/gpu/drm/i915/i915_active.h
+++ b/drivers/gpu/drm/i915/i915_active.h
@@ -309,6 +309,7 @@ i915_active_request_isset(const struct i915_active_request
*active)
*/
static inline int __must_check
i915_active_request_retire(struct i915_active_request *active,
+ unsigned int flags,
struct mutex *mutex)
{
struct i915_request *request;
@@ -318,9 +319,7 @@ i915_active_request_retire(struct i915_active_request
*active,
if (!request)
return 0;
- ret = i915_request_wait(request,
- I915_WAIT_INTERRUPTIBLE,
- MAX_SCHEDULE_TIMEOUT);
+ ret = i915_request_wait(request, flags, MAX_SCHEDULE_TIMEOUT);
if (ret < 0)
return ret;
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v15 07/13] drm/i915/perf: allow for CS OA configs to be created lazily
Here we introduce a mechanism by which the execbuf part of the i915
driver will be able to request that a batch buffer containing the
programming for a particular OA config be created.
We'll execute these OA configuration buffers right before executing a
set of userspace commands so that a particular user batchbuffer be
executed with a given OA configuration.
This mechanism essentially allows the userspace driver to go through
several OA configuration without having to open/close the i915/perf
stream.
v2: No need for locking on object OA config object creation (Chris)
Flush cpu mapping of OA config (Chris)
v3: Properly deal with the perf_metric lock (Chris/Lionel)
v4: Fix oa config unref/put when not found (Lionel)
v5: Allocate BOs for configurations on the stream instead of globally
(Lionel)
v6: Fix 64bit division (Chris)
v7: Store allocated config BOs into the stream (Lionel)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson (v4)
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
drivers/gpu/drm/i915/i915_drv.h | 4 +-
drivers/gpu/drm/i915/i915_perf.c | 270 ---
drivers/gpu/drm/i915/i915_perf.h | 26 ++
drivers/gpu/drm/i915/i915_perf_types.h | 15 +-
5 files changed, 273 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 86e00a2db8a4..a7f1377a54a2 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -133,6 +133,7 @@
*/
#define MI_LOAD_REGISTER_IMM(x)MI_INSTR(0x22, 2*(x)-1)
#define MI_LRI_FORCE_POSTED (1<<12)
+#define MI_LOAD_REGISTER_IMM_MAX_REGS (126)
#define MI_STORE_REGISTER_MEMMI_INSTR(0x24, 1)
#define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2)
#define MI_SRM_LRM_GLOBAL_GTT(1<<22)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f4145ae6ab6e..7eb31923cde9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1363,8 +1363,8 @@ struct drm_i915_private {
struct mutex metrics_lock;
/*
-* List of dynamic configurations, you need to hold
-* dev_priv->perf.metrics_lock to access it.
+* List of dynamic configurations (struct i915_oa_config), you
+* need to hold dev_priv->perf.metrics_lock to access it.
*/
struct idr metrics_idr;
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 40a1ec2bc96b..c9d0de3050fb 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -367,11 +367,19 @@ struct perf_open_properties {
struct intel_engine_cs *engine;
};
+struct i915_oa_config_bo {
+ struct list_head link;
+
+ struct i915_oa_config *oa_config;
+ struct drm_i915_gem_object *bo;
+};
+
static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer);
-static void free_oa_config(struct drm_i915_private *dev_priv,
- struct i915_oa_config *oa_config)
+void i915_oa_config_release(struct kref *ref)
{
+ struct i915_oa_config *oa_config = container_of(ref,
typeof(*oa_config), ref);
+
if (!PTR_ERR(oa_config->flex_regs))
kfree(oa_config->flex_regs);
if (!PTR_ERR(oa_config->b_counter_regs))
@@ -381,40 +389,194 @@ static void free_oa_config(struct drm_i915_private
*dev_priv,
kfree(oa_config);
}
-static void put_oa_config(struct drm_i915_private *dev_priv,
- struct i915_oa_config *oa_config)
+static u32 *write_cs_mi_lri(u32 *cs, const struct i915_oa_reg *reg_data, u32
n_regs)
{
- if (!atomic_dec_and_test(_config->ref_count))
- return;
+ u32 i;
+
+ for (i = 0; i < n_regs; i++) {
+ if ((i % MI_LOAD_REGISTER_IMM_MAX_REGS) == 0) {
+ u32 n_lri = min(n_regs - i,
+ (u32) MI_LOAD_REGISTER_IMM_MAX_REGS);
- free_oa_config(dev_priv, oa_config);
+ *cs++ = MI_LOAD_REGISTER_IMM(n_lri);
+ }
+ *cs++ = i915_mmio_reg_offset(reg_data[i].addr);
+ *cs++ = reg_data[i].value;
+ }
+
+ return cs;
}
-static int get_oa_config(struct drm_i915_private *dev_priv,
-int metrics_set,
-struct i915_oa_config **out_config)
+static struct i915_oa_config_bo* alloc_oa_config_buffer(struct
drm_i915_private *i915,
+ struct i915_oa_config
*oa_config)
{
- int ret;
+ struct i915_oa_config_bo *oa_bo;
+ size_t config_length = 0;
+ u32 *cs;
+ int err;
+
+ oa_bo = kzalloc(sizeof(*oa_bo), GFP_KERNEL);
+ if (!oa_bo)
+ return
[Intel-gfx] [PATCH v15 02/13] drm/i915: add syncobj timeline support
Introduces a new parameters to execbuf so that we can specify syncobj
handles as well as timeline points.
v2: Reuse i915_user_extension_fn
v3: Check that the chained extension is only present once (Chris)
v4: Check that dma_fence_chain_find_seqno returns a non NULL fence (Lionel)
v5: Use BIT_ULL (Chris)
v6: Fix issue with already signaled timeline points,
dma_fence_chain_find_seqno() setting fence to NULL (Chris)
v7: Report ENOENT with invalid syncobj handle (Lionel)
v8: Check for out of order timeline point insertion (Chris)
v9: After explanations on
https://lists.freedesktop.org/archives/dri-devel/2019-August/229287.html
drop the ordering check from v8 (Lionel)
v10: Set first extension enum item to 1 (Jason)
Signed-off-by: Lionel Landwerlin
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 307 ++
drivers/gpu/drm/i915/i915_drv.c | 3 +-
drivers/gpu/drm/i915/i915_getparam.c | 1 +
include/uapi/drm/i915_drm.h | 39 +++
4 files changed, 293 insertions(+), 57 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 4f5fd946ab28..46ad8d9642d1 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -214,6 +214,13 @@ enum {
* the batchbuffer in trusted mode, otherwise the ioctl is rejected.
*/
+struct i915_eb_fences {
+ struct drm_syncobj *syncobj; /* Use with ptr_mask_bits() */
+ struct dma_fence *dma_fence;
+ u64 value;
+ struct dma_fence_chain *chain_fence;
+};
+
struct i915_execbuffer {
struct drm_i915_private *i915; /** i915 backpointer */
struct drm_file *file; /** per-file lookup tables and limits */
@@ -276,6 +283,7 @@ struct i915_execbuffer {
struct {
u64 flags; /** Available extensions parameters */
+ struct drm_i915_gem_execbuffer_ext_timeline_fences
timeline_fences;
} extensions;
};
@@ -2320,67 +2328,217 @@ eb_pin_engine(struct i915_execbuffer *eb,
}
static void
-__free_fence_array(struct drm_syncobj **fences, unsigned int n)
+__free_fence_array(struct i915_eb_fences *fences, unsigned int n)
{
- while (n--)
- drm_syncobj_put(ptr_mask_bits(fences[n], 2));
+ while (n--) {
+ drm_syncobj_put(ptr_mask_bits(fences[n].syncobj, 2));
+ dma_fence_put(fences[n].dma_fence);
+ kfree(fences[n].chain_fence);
+ }
kvfree(fences);
}
-static struct drm_syncobj **
-get_fence_array(struct drm_i915_gem_execbuffer2 *args,
- struct drm_file *file)
+static struct i915_eb_fences *
+get_timeline_fence_array(struct i915_execbuffer *eb, int *out_n_fences)
+{
+ struct drm_i915_gem_execbuffer_ext_timeline_fences *timeline_fences =
+ >extensions.timeline_fences;
+ struct drm_i915_gem_exec_fence __user *user_fences;
+ struct i915_eb_fences *fences;
+ u64 __user *user_values;
+ u64 num_fences, num_user_fences = timeline_fences->fence_count;
+ unsigned long n;
+ int err;
+
+ /* Check multiplication overflow for access_ok() and kvmalloc_array() */
+ BUILD_BUG_ON(sizeof(size_t) > sizeof(unsigned long));
+ if (num_user_fences > min_t(unsigned long,
+ ULONG_MAX / sizeof(*user_fences),
+ SIZE_MAX / sizeof(*fences)))
+ return ERR_PTR(-EINVAL);
+
+ user_fences = u64_to_user_ptr(timeline_fences->handles_ptr);
+ if (!access_ok(user_fences, num_user_fences * sizeof(*user_fences)))
+ return ERR_PTR(-EFAULT);
+
+ user_values = u64_to_user_ptr(timeline_fences->values_ptr);
+ if (!access_ok(user_values, num_user_fences * sizeof(*user_values)))
+ return ERR_PTR(-EFAULT);
+
+ fences = kvmalloc_array(num_user_fences, sizeof(*fences),
+ __GFP_NOWARN | GFP_KERNEL);
+ if (!fences)
+ return ERR_PTR(-ENOMEM);
+
+ BUILD_BUG_ON(~(ARCH_KMALLOC_MINALIGN - 1) &
+~__I915_EXEC_FENCE_UNKNOWN_FLAGS);
+
+ for (n = 0, num_fences = 0; n < timeline_fences->fence_count; n++) {
+ struct drm_i915_gem_exec_fence user_fence;
+ struct drm_syncobj *syncobj;
+ struct dma_fence *fence = NULL;
+ u64 point;
+
+ if (__copy_from_user(_fence, user_fences++,
sizeof(user_fence))) {
+ err = -EFAULT;
+ goto err;
+ }
+
+ if (user_fence.flags & __I915_EXEC_FENCE_UNKNOWN_FLAGS) {
+ err = -EINVAL;
+ goto err;
+ }
+
+ if (__get_user(point, user_values++)) {
+ err = -EFAULT;
+ goto err;
+ }
+
+ syncobj
[Intel-gfx] [PATCH v15 01/13] drm/i915: introduce a mechanism to extend execbuf2
We're planning to use this for a couple of new feature where we need
to provide additional parameters to execbuf.
v2: Check for invalid flags in execbuffer2 (Lionel)
v3: Rename I915_EXEC_EXT -> I915_EXEC_USE_EXTENSIONS (Chris)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson (v1)
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 39 ++-
include/uapi/drm/i915_drm.h | 26 +++--
2 files changed, 61 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 27dbcb508055..4f5fd946ab28 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -25,6 +25,7 @@
#include "i915_gem_context.h"
#include "i915_gem_ioctls.h"
#include "i915_trace.h"
+#include "i915_user_extensions.h"
enum {
FORCE_CPU_RELOC = 1,
@@ -272,6 +273,10 @@ struct i915_execbuffer {
*/
int lut_size;
struct hlist_head *buckets; /** ht for relocation handles */
+
+ struct {
+ u64 flags; /** Available extensions parameters */
+ } extensions;
};
#define exec_entry(EB, VMA) (&(EB)->exec[(VMA)->exec_flags - (EB)->flags])
@@ -1940,7 +1945,8 @@ static bool i915_gem_check_execbuffer(struct
drm_i915_gem_execbuffer2 *exec)
return false;
/* Kernel clipping was a DRI1 misfeature */
- if (!(exec->flags & I915_EXEC_FENCE_ARRAY)) {
+ if (!(exec->flags & (I915_EXEC_FENCE_ARRAY |
+I915_EXEC_USE_EXTENSIONS))) {
if (exec->num_cliprects || exec->cliprects_ptr)
return false;
}
@@ -2442,6 +2448,33 @@ signal_fence_array(struct i915_execbuffer *eb,
}
}
+static const i915_user_extension_fn execbuf_extensions[] = {
+};
+
+static int
+parse_execbuf2_extensions(struct drm_i915_gem_execbuffer2 *args,
+ struct i915_execbuffer *eb)
+{
+ eb->extensions.flags = 0;
+
+ if (!(args->flags & I915_EXEC_USE_EXTENSIONS))
+ return 0;
+
+ /* The execbuf2 extension mechanism reuses cliprects_ptr. So we cannot
+* have another flag also using it at the same time.
+*/
+ if (eb->args->flags & I915_EXEC_FENCE_ARRAY)
+ return -EINVAL;
+
+ if (args->num_cliprects != 0)
+ return -EINVAL;
+
+ return i915_user_extensions(u64_to_user_ptr(args->cliprects_ptr),
+ execbuf_extensions,
+ ARRAY_SIZE(execbuf_extensions),
+ eb);
+}
+
static int
i915_gem_do_execbuffer(struct drm_device *dev,
struct drm_file *file,
@@ -2488,6 +2521,10 @@ i915_gem_do_execbuffer(struct drm_device *dev,
if (args->flags & I915_EXEC_IS_PINNED)
eb.batch_flags |= I915_DISPATCH_PINNED;
+ err = parse_execbuf2_extensions(args, );
+ if (err)
+ return err;
+
if (args->flags & I915_EXEC_FENCE_IN) {
in_fence = sync_file_get_fence(lower_32_bits(args->rsvd2));
if (!in_fence)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 469dc512cca3..0a99c26730e1 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1007,6 +1007,10 @@ struct drm_i915_gem_exec_fence {
__u32 flags;
};
+enum drm_i915_gem_execbuffer_ext {
+ DRM_I915_GEM_EXECBUFFER_EXT_MAX /* non-ABI */
+};
+
struct drm_i915_gem_execbuffer2 {
/**
* List of gem_exec_object2 structs
@@ -1023,8 +1027,15 @@ struct drm_i915_gem_execbuffer2 {
__u32 num_cliprects;
/**
* This is a struct drm_clip_rect *cliprects if I915_EXEC_FENCE_ARRAY
-* is not set. If I915_EXEC_FENCE_ARRAY is set, then this is a
-* struct drm_i915_gem_exec_fence *fences.
+* & I915_EXEC_USE_EXTENSIONS are not set.
+*
+* If I915_EXEC_FENCE_ARRAY is set, then this is a pointer to an array
+* of struct drm_i915_gem_exec_fence and num_cliprects is the length
+* of the array.
+*
+* If I915_EXEC_USE_EXTENSIONS is set, then this is a pointer to a
+* single struct drm_i915_gem_base_execbuffer_ext and num_cliprects is
+* 0.
*/
__u64 cliprects_ptr;
#define I915_EXEC_RING_MASK (0x3f)
@@ -1142,7 +1153,16 @@ struct drm_i915_gem_execbuffer2 {
*/
#define I915_EXEC_FENCE_SUBMIT (1 << 20)
-#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SUBMIT << 1))
+/*
+ * Setting I915_EXEC_USE_EXTENSIONS implies that
+ * drm_i915_gem_execbuffer2.cliprects_ptr is treated as a pointer to an linked
+ * list of i915_user_extension. Each i915_user_extension node is the base of a
+ * larger structure. The list of supported structures are listed in the
+ * drm_i915_gem_execbuffer_ext enum.
+ */
+#define
[Intel-gfx] [PATCH v15 03/13] drm/i915/perf: drop list of streams
At some point in time there was the idea that we could have multiple
stream from the same piece of HW but that never materialized and given
the hard time we already have making everything work with the
submission side, there is no real point having this list of 1 element
around.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 6 --
drivers/gpu/drm/i915/i915_perf.c | 16 +---
2 files changed, 1 insertion(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index db7480831e52..75607450ba00 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1082,11 +1082,6 @@ struct i915_perf_stream {
*/
struct drm_i915_private *dev_priv;
- /**
-* @link: Links the stream into ``_i915_private->streams``
-*/
- struct list_head link;
-
/**
* @wakeref: As we keep the device awake while the perf stream is
* active, we track our runtime pm reference for later release.
@@ -1671,7 +1666,6 @@ struct drm_i915_private {
* except exclusive_stream.
*/
struct mutex lock;
- struct list_head streams;
/*
* The stream currently using the OA unit. If accessed
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index c1b764233761..d18cd332afb7 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1435,9 +1435,6 @@ static void gen7_init_oa_buffer(struct i915_perf_stream
*stream)
*/
memset(stream->oa_buffer.vaddr, 0, OA_BUFFER_SIZE);
- /* Maybe make ->pollin per-stream state if we support multiple
-* concurrent streams in the future.
-*/
stream->pollin = false;
}
@@ -1494,10 +1491,6 @@ static void gen8_init_oa_buffer(struct i915_perf_stream
*stream)
*/
memset(stream->oa_buffer.vaddr, 0, OA_BUFFER_SIZE);
- /*
-* Maybe make ->pollin per-stream state if we support multiple
-* concurrent streams in the future.
-*/
stream->pollin = false;
}
@@ -2633,8 +2626,6 @@ static void i915_perf_destroy_locked(struct
i915_perf_stream *stream)
if (stream->ops->destroy)
stream->ops->destroy(stream);
- list_del(>link);
-
if (stream->ctx)
i915_gem_context_put(stream->ctx);
@@ -2783,8 +2774,6 @@ i915_perf_open_ioctl_locked(struct drm_i915_private
*dev_priv,
goto err_flags;
}
- list_add(>link, _priv->perf.streams);
-
if (param->flags & I915_PERF_FLAG_FD_CLOEXEC)
f_flags |= O_CLOEXEC;
if (param->flags & I915_PERF_FLAG_FD_NONBLOCK)
@@ -2793,7 +2782,7 @@ i915_perf_open_ioctl_locked(struct drm_i915_private
*dev_priv,
stream_fd = anon_inode_getfd("[i915_perf]", , stream, f_flags);
if (stream_fd < 0) {
ret = stream_fd;
- goto err_open;
+ goto err_flags;
}
if (!(param->flags & I915_PERF_FLAG_DISABLED))
@@ -2806,8 +2795,6 @@ i915_perf_open_ioctl_locked(struct drm_i915_private
*dev_priv,
return stream_fd;
-err_open:
- list_del(>link);
err_flags:
if (stream->ops->destroy)
stream->ops->destroy(stream);
@@ -3643,7 +3630,6 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
}
if (dev_priv->perf.ops.enable_metric_set) {
- INIT_LIST_HEAD(_priv->perf.streams);
mutex_init(_priv->perf.lock);
oa_sample_rate_hard_limit = 1000 *
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v15 05/13] drm/i915/perf: introduce a versioning of the i915-perf uapi
Reporting this version will help application figure out what level of
the support the running kernel provides.
v2: Add i915_perf_ioctl_version() (Chris)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_getparam.c | 4
drivers/gpu/drm/i915/i915_perf.c | 10 ++
drivers/gpu/drm/i915/i915_perf.h | 1 +
include/uapi/drm/i915_drm.h | 20
4 files changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_getparam.c
b/drivers/gpu/drm/i915/i915_getparam.c
index da6faa84e5b8..bd41cc5ce906 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -5,6 +5,7 @@
#include "gt/intel_engine_user.h"
#include "i915_drv.h"
+#include "i915_perf.h"
int i915_getparam_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv)
@@ -157,6 +158,9 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
case I915_PARAM_MMAP_GTT_COHERENT:
value = INTEL_INFO(i915)->has_coherent_ggtt;
break;
+ case I915_PARAM_PERF_REVISION:
+ value = i915_perf_ioctl_version();
+ break;
default:
DRM_DEBUG("Unknown parameter %d\n", param->param);
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 9d5a3522aa35..40a1ec2bc96b 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3697,3 +3697,13 @@ void i915_perf_fini(struct drm_i915_private *dev_priv)
dev_priv->perf.initialized = false;
}
+
+/**
+ * i915_perf_ioctl_version - Version of the i915-perf subsystem
+ *
+ * This version number is used by userspace to detect available features.
+ */
+int i915_perf_ioctl_version(void)
+{
+ return 1;
+}
diff --git a/drivers/gpu/drm/i915/i915_perf.h b/drivers/gpu/drm/i915/i915_perf.h
index a412b16d9ffc..95549de65212 100644
--- a/drivers/gpu/drm/i915/i915_perf.h
+++ b/drivers/gpu/drm/i915/i915_perf.h
@@ -18,6 +18,7 @@ void i915_perf_init(struct drm_i915_private *i915);
void i915_perf_fini(struct drm_i915_private *i915);
void i915_perf_register(struct drm_i915_private *i915);
void i915_perf_unregister(struct drm_i915_private *i915);
+int i915_perf_ioctl_version(void);
int i915_perf_open_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 3d031e81648b..e98c9a7baa91 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -618,6 +618,12 @@ typedef struct drm_i915_irq_wait {
*/
#define I915_PARAM_HAS_EXEC_TIMELINE_FENCES 54
+/*
+ * Revision of the i915-perf uAPI. The value returned helps determine what
+ * i915-perf features are available. See drm_i915_perf_property_id.
+ */
+#define I915_PARAM_PERF_REVISION 55
+
/* Must be kept compact -- no holes and well documented */
typedef struct drm_i915_getparam {
@@ -1903,23 +1909,31 @@ enum drm_i915_perf_property_id {
* Open the stream for a specific context handle (as used with
* execbuffer2). A stream opened for a specific context this way
* won't typically require root privileges.
+*
+* This property is available in perf revision 1.
*/
DRM_I915_PERF_PROP_CTX_HANDLE = 1,
/**
* A value of 1 requests the inclusion of raw OA unit reports as
* part of stream samples.
+*
+* This property is available in perf revision 1.
*/
DRM_I915_PERF_PROP_SAMPLE_OA,
/**
* The value specifies which set of OA unit metrics should be
* be configured, defining the contents of any OA unit reports.
+*
+* This property is available in perf revision 1.
*/
DRM_I915_PERF_PROP_OA_METRICS_SET,
/**
* The value specifies the size and layout of OA unit reports.
+*
+* This property is available in perf revision 1.
*/
DRM_I915_PERF_PROP_OA_FORMAT,
@@ -1929,6 +1943,8 @@ enum drm_i915_perf_property_id {
* from this exponent as follows:
*
* 80ns * 2^(period_exponent + 1)
+*
+* This property is available in perf revision 1.
*/
DRM_I915_PERF_PROP_OA_EXPONENT,
@@ -1960,6 +1976,8 @@ struct drm_i915_perf_open_param {
* to close and re-open a stream with the same configuration.
*
* It's undefined whether any pending data for the stream will be lost.
+ *
+ * This ioctl is available in perf revision 1.
*/
#define I915_PERF_IOCTL_ENABLE _IO('i', 0x0)
@@ -1967,6 +1985,8 @@ struct drm_i915_perf_open_param {
* Disable data capture for a stream.
*
* It is an error to try and read a stream that is disabled.
+ *
+ * This ioctl is available in perf revision 1.
*/
#define I915_PERF_IOCTL_DISABLE_IO('i',
[Intel-gfx] [PATCH v15 06/13] drm/i915/perf: move perf types to their own header
Following a pattern used throughout the driver.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h| 300 +--
drivers/gpu/drm/i915/i915_perf.h | 2 +
drivers/gpu/drm/i915/i915_perf_types.h | 318 +
3 files changed, 321 insertions(+), 299 deletions(-)
create mode 100644 drivers/gpu/drm/i915/i915_perf_types.h
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 274a1193d4f0..f4145ae6ab6e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -92,6 +92,7 @@
#include "i915_gem_fence_reg.h"
#include "i915_gem_gtt.h"
#include "i915_gpu_error.h"
+#include "i915_perf_types.h"
#include "i915_request.h"
#include "i915_scheduler.h"
#include "gt/intel_timeline.h"
@@ -979,305 +980,6 @@ struct intel_wm_config {
bool sprites_scaled;
};
-struct i915_oa_format {
- u32 format;
- int size;
-};
-
-struct i915_oa_reg {
- i915_reg_t addr;
- u32 value;
-};
-
-struct i915_oa_config {
- char uuid[UUID_STRING_LEN + 1];
- int id;
-
- const struct i915_oa_reg *mux_regs;
- u32 mux_regs_len;
- const struct i915_oa_reg *b_counter_regs;
- u32 b_counter_regs_len;
- const struct i915_oa_reg *flex_regs;
- u32 flex_regs_len;
-
- struct attribute_group sysfs_metric;
- struct attribute *attrs[2];
- struct device_attribute sysfs_metric_id;
-
- atomic_t ref_count;
-};
-
-struct i915_perf_stream;
-
-/**
- * struct i915_perf_stream_ops - the OPs to support a specific stream type
- */
-struct i915_perf_stream_ops {
- /**
-* @enable: Enables the collection of HW samples, either in response to
-* `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
-* without `I915_PERF_FLAG_DISABLED`.
-*/
- void (*enable)(struct i915_perf_stream *stream);
-
- /**
-* @disable: Disables the collection of HW samples, either in response
-* to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
-* the stream.
-*/
- void (*disable)(struct i915_perf_stream *stream);
-
- /**
-* @poll_wait: Call poll_wait, passing a wait queue that will be woken
-* once there is something ready to read() for the stream
-*/
- void (*poll_wait)(struct i915_perf_stream *stream,
- struct file *file,
- poll_table *wait);
-
- /**
-* @wait_unlocked: For handling a blocking read, wait until there is
-* something to ready to read() for the stream. E.g. wait on the same
-* wait queue that would be passed to poll_wait().
-*/
- int (*wait_unlocked)(struct i915_perf_stream *stream);
-
- /**
-* @read: Copy buffered metrics as records to userspace
-* **buf**: the userspace, destination buffer
-* **count**: the number of bytes to copy, requested by userspace
-* **offset**: zero at the start of the read, updated as the read
-* proceeds, it represents how many bytes have been copied so far and
-* the buffer offset for copying the next record.
-*
-* Copy as many buffered i915 perf samples and records for this stream
-* to userspace as will fit in the given buffer.
-*
-* Only write complete records; returning -%ENOSPC if there isn't room
-* for a complete record.
-*
-* Return any error condition that results in a short read such as
-* -%ENOSPC or -%EFAULT, even though these may be squashed before
-* returning to userspace.
-*/
- int (*read)(struct i915_perf_stream *stream,
- char __user *buf,
- size_t count,
- size_t *offset);
-
- /**
-* @destroy: Cleanup any stream specific resources.
-*
-* The stream will always be disabled before this is called.
-*/
- void (*destroy)(struct i915_perf_stream *stream);
-};
-
-/**
- * struct i915_perf_stream - state for a single open stream FD
- */
-struct i915_perf_stream {
- /**
-* @dev_priv: i915 drm device
-*/
- struct drm_i915_private *dev_priv;
-
- /**
-* @wakeref: As we keep the device awake while the perf stream is
-* active, we track our runtime pm reference for later release.
-*/
- intel_wakeref_t wakeref;
-
- /**
-* @engine: Engine associated with this performance stream.
-*/
- struct intel_engine_cs *engine;
-
- /**
-* @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
-* properties given when opening a stream, representing the contents
-* of a single sample as read() by userspace.
-*/
- u32 sample_flags;
-
- /**
-* @sample_size: Considering the configured contents of
[Intel-gfx] [PATCH v15 00/13] drm/i915: Vulkan performance query support
Hi all, The series is gaining one patch, splitting away the i915_perf types into their own header file. The CI reported compilation issues and I figured as well as fixing them, we could reduce the size of i915_drv.h a bit more. No other change apart from the rippling changes from the moving the types around. Cheers, Lionel Landwerlin (13): drm/i915: introduce a mechanism to extend execbuf2 drm/i915: add syncobj timeline support drm/i915/perf: drop list of streams drm/i915/perf: store the associated engine of a stream drm/i915/perf: introduce a versioning of the i915-perf uapi drm/i915/perf: move perf types to their own header drm/i915/perf: allow for CS OA configs to be created lazily drm/i915/perf: implement active wait for noa configurations drm/i915: add wait flags to i915_active_request_retire drm/i915/perf: execute OA configuration from command stream drm/i915: add a new perf configuration execbuf parameter drm/i915/perf: allow holding preemption on filtered ctx drm/i915: add support for perf configuration queries .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 501 ++-- drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 25 + drivers/gpu/drm/i915/gt/intel_gt_types.h | 5 + drivers/gpu/drm/i915/i915_active.c| 4 +- drivers/gpu/drm/i915/i915_active.h| 5 +- drivers/gpu/drm/i915/i915_debugfs.c | 31 + drivers/gpu/drm/i915/i915_drv.c | 3 +- drivers/gpu/drm/i915/i915_drv.h | 313 +--- drivers/gpu/drm/i915/i915_getparam.c | 9 + drivers/gpu/drm/i915/i915_perf.c | 717 +++--- drivers/gpu/drm/i915/i915_perf.h | 29 + drivers/gpu/drm/i915/i915_perf_types.h| 356 + drivers/gpu/drm/i915/i915_query.c | 283 +++ drivers/gpu/drm/i915/i915_reg.h | 4 +- include/uapi/drm/i915_drm.h | 196 - 15 files changed, 2001 insertions(+), 480 deletions(-) create mode 100644 drivers/gpu/drm/i915/i915_perf_types.h -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v15 04/13] drm/i915/perf: store the associated engine of a stream
We'll use this information later to verify that a client trying to
reconfigure the stream does so on the right engine.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 5 +
drivers/gpu/drm/i915/i915_perf.c | 7 +++
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 75607450ba00..274a1193d4f0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1088,6 +1088,11 @@ struct i915_perf_stream {
*/
intel_wakeref_t wakeref;
+ /**
+* @engine: Engine associated with this performance stream.
+*/
+ struct intel_engine_cs *engine;
+
/**
* @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
* properties given when opening a stream, representing the contents
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index d18cd332afb7..9d5a3522aa35 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -363,6 +363,8 @@ struct perf_open_properties {
int oa_format;
bool oa_periodic;
int oa_period_exponent;
+
+ struct intel_engine_cs *engine;
};
static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer);
@@ -2201,6 +2203,8 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
format_size = dev_priv->perf.oa_formats[props->oa_format].size;
+ stream->engine = props->engine;
+
stream->sample_flags |= SAMPLE_OA_REPORT;
stream->sample_size += format_size;
@@ -2843,6 +2847,9 @@ static int read_properties_unlocked(struct
drm_i915_private *dev_priv,
return -EINVAL;
}
+ /* At the moment we only support using i915-perf on the RCS. */
+ props->engine = dev_priv->engine[RCS0];
+
/* Considering that ID = 0 is reserved and assuming that we don't
* (currently) expect any configurations to ever specify duplicate
* values for a particular property ID then the last _PROP_MAX value is
--
2.23.0
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[Intel-gfx] ✓ Fi.CI.BAT: success for Send a hotplug when edid changes (rev7)
== Series Details ==
Series: Send a hotplug when edid changes (rev7)
URL : https://patchwork.freedesktop.org/series/62816/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6841 -> Patchwork_14299
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14299/
Known issues
Here are the changes found in Patchwork_14299 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s4-devices:
- fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14299/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html
* igt@i915_selftest@live_gem_contexts:
- fi-kbl-guc: [PASS][3] -> [INCOMPLETE][4] ([fdo#111519])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-kbl-guc/igt@i915_selftest@live_gem_contexts.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14299/fi-kbl-guc/igt@i915_selftest@live_gem_contexts.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: [PASS][5] -> [FAIL][6] ([fdo#103167])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14299/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@i915_pm_rpm@basic-rte:
- {fi-icl-guc}: [DMESG-WARN][7] -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-icl-guc/igt@i915_pm_...@basic-rte.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14299/fi-icl-guc/igt@i915_pm_...@basic-rte.html
* igt@i915_selftest@live_execlists:
- fi-skl-gvtdvm: [DMESG-FAIL][9] ([fdo#08]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14299/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
* igt@kms_chamelium@dp-crc-fast:
- fi-cml-u2: [FAIL][11] ([fdo#110627]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14299/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_frontbuffer_tracking@basic:
- {fi-icl-u4}:[FAIL][13] ([fdo#103167]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14299/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
* igt@vgem_basic@unload:
- fi-icl-u3: [DMESG-WARN][15] ([fdo#107724]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6841/fi-icl-u3/igt@vgem_ba...@unload.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14299/fi-icl-u3/igt@vgem_ba...@unload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#110627]: https://bugs.freedesktop.org/show_bug.cgi?id=110627
[fdo#08]: https://bugs.freedesktop.org/show_bug.cgi?id=08
[fdo#111519]: https://bugs.freedesktop.org/show_bug.cgi?id=111519
Participating hosts (53 -> 47)
--
Additional (1): fi-tgl-u
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6841 -> Patchwork_14299
CI-20190529: 20190529
CI_DRM_6841: 5c24bcfb9c6036b32dbfdbc22d773473880ff498 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5171: 1911564805fe454919e8a5846534a0c1ef376a33 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14299: 610c89a4b314bc74f621f97988ea5e309399fccd @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
610c89a4b314 drm/i915: Send hotplug event if edid had changed
701f9863dd56 drm: Introduce epoch counter to drm_connector
c2072e1d23ff drm: Add helper to compare edids.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14299/
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Send a hotplug when edid changes (rev7)
== Series Details ==
Series: Send a hotplug when edid changes (rev7)
URL : https://patchwork.freedesktop.org/series/62816/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c2072e1d23ff drm: Add helper to compare edids.
-:32: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "edid1"
#32: FILE: drivers/gpu/drm/drm_edid.c:1375:
+ bool edid1_present = edid1 != NULL;
-:33: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "edid2"
#33: FILE: drivers/gpu/drm/drm_edid.c:1376:
+ bool edid2_present = edid2 != NULL;
-:39: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#39: FILE: drivers/gpu/drm/drm_edid.c:1382:
+ if (edid1) {
+
-:54: CHECK:LINE_SPACING: Please don't use multiple blank lines
#54: FILE: drivers/gpu/drm/drm_edid.c:1397:
+
+
total: 0 errors, 0 warnings, 4 checks, 54 lines checked
701f9863dd56 drm: Introduce epoch counter to drm_connector
-:55: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#55: FILE: drivers/gpu/drm/drm_connector.c:1897:
+ DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Edid was
changed.\n",
+ connector->base.id, connector->name);
-:59: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#59: FILE: drivers/gpu/drm/drm_connector.c:1901:
+ DRM_DEBUG_KMS("Updating change counter to
%llu\n",
+ connector->epoch_counter);
-:119: CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u64' over 'uint64_t'
#119: FILE: drivers/gpu/drm/drm_probe_helper.c:788:
+ uint64_t old_epoch_counter;
-:150: WARNING:BRACES: braces {} are not necessary for single statement blocks
#150: FILE: drivers/gpu/drm/drm_probe_helper.c:824:
+ if (old_epoch_counter != connector->epoch_counter) {
changed = true;
+ }
-:174: CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u64' over 'uint64_t'
#174: FILE: include/drm/drm_connector.h:1292:
+ uint64_t epoch_counter;
total: 0 errors, 1 warnings, 4 checks, 128 lines checked
610c89a4b314 drm/i915: Send hotplug event if edid had changed
-:61: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#61: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:299:
+ DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to
%s(epoch counter %llu)\n",
connector->base.base.id,
total: 0 errors, 0 warnings, 1 checks, 36 lines checked
___
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[Intel-gfx] [PATCH v6 0/3] Send a hotplug when edid changes
This series introduce to drm a way to determine if something else except connection_status had changed during probing, which can be used by other drivers as well. Another i915 specific part uses this approach to determine if edid had changed without changing the connection status and send a hotplug event. Stanislav Lisovskiy (3): drm: Add helper to compare edids. drm: Introduce epoch counter to drm_connector drm/i915: Send hotplug event if edid had changed drivers/gpu/drm/drm_connector.c | 16 + drivers/gpu/drm/drm_edid.c | 36 +++ drivers/gpu/drm/drm_probe_helper.c | 38 +--- drivers/gpu/drm/i915/display/intel_hotplug.c | 18 +++--- include/drm/drm_connector.h | 3 ++ include/drm/drm_edid.h | 9 + 6 files changed, 110 insertions(+), 10 deletions(-) -- 2.17.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 2/3] drm: Introduce epoch counter to drm_connector
This counter will be used by drm_helper_probe_detect caller to determine
if anything had changed(including edid, connection status and etc).
Hardware specific driver detect hooks are responsible for updating this
counter when some change is detected to notify the drm part,
which can trigger for example hotplug event.
Also now call drm_connector_update_edid_property
right after we get edid always to make sure there is a
unified way to handle edid change, without having to
change tons of source code as currently
drm_connector_update_edid_property is called only in
certain cases like reprobing and not right after edid is
actually updated.
v2: Added documentation for the new counter. Rename change_counter to
epoch_counter.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105540
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/drm_connector.c| 16 +
drivers/gpu/drm/drm_edid.c | 3 +++
drivers/gpu/drm/drm_probe_helper.c | 38 ++
include/drm/drm_connector.h| 3 +++
4 files changed, 55 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 4c766624b20d..98fd236acc57 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -246,6 +246,7 @@ int drm_connector_init(struct drm_device *dev,
INIT_LIST_HEAD(>modes);
mutex_init(>mutex);
connector->edid_blob_ptr = NULL;
+ connector->epoch_counter = 0;
connector->tile_blob_ptr = NULL;
connector->status = connector_status_unknown;
connector->display_info.panel_orientation =
@@ -1866,6 +1867,7 @@ int drm_connector_update_edid_property(struct
drm_connector *connector,
struct drm_device *dev = connector->dev;
size_t size = 0;
int ret;
+ const struct edid *old_edid;
/* ignore requests to set edid when overridden */
if (connector->override_edid)
@@ -1887,6 +1889,20 @@ int drm_connector_update_edid_property(struct
drm_connector *connector,
else
drm_reset_display_info(connector);
+ if (connector->edid_blob_ptr) {
+ old_edid = (const struct edid *)connector->edid_blob_ptr->data;
+ if (old_edid) {
+ if (!drm_edid_are_equal(edid, old_edid)) {
+ DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Edid was
changed.\n",
+ connector->base.id, connector->name);
+
+ connector->epoch_counter += 1;
+ DRM_DEBUG_KMS("Updating change counter to
%llu\n",
+ connector->epoch_counter);
+ }
+ }
+ }
+
drm_object_property_set_value(>base,
dev->mode_config.non_desktop_property,
connector->display_info.non_desktop);
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 0639db9fd23f..48b716abc9ef 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1803,6 +1803,9 @@ struct edid *drm_get_edid(struct drm_connector *connector,
edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
if (edid)
drm_get_displayid(connector, edid);
+
+ drm_connector_update_edid_property(connector, edid);
+
return edid;
}
EXPORT_SYMBOL(drm_get_edid);
diff --git a/drivers/gpu/drm/drm_probe_helper.c
b/drivers/gpu/drm/drm_probe_helper.c
index 351cbc40f0f8..b2b6385cfed3 100644
--- a/drivers/gpu/drm/drm_probe_helper.c
+++ b/drivers/gpu/drm/drm_probe_helper.c
@@ -287,6 +287,9 @@ drm_helper_probe_detect_ctx(struct drm_connector
*connector, bool force)
if (WARN_ON(ret < 0))
ret = connector_status_unknown;
+ if (ret != connector->status)
+ connector->epoch_counter += 1;
+
drm_modeset_drop_locks();
drm_modeset_acquire_fini();
@@ -320,11 +323,16 @@ drm_helper_probe_detect(struct drm_connector *connector,
return ret;
if (funcs->detect_ctx)
- return funcs->detect_ctx(connector, ctx, force);
+ ret = funcs->detect_ctx(connector, ctx, force);
else if (connector->funcs->detect)
- return connector->funcs->detect(connector, force);
+ ret = connector->funcs->detect(connector, force);
else
- return connector_status_connected;
+ ret = connector_status_connected;
+
+ if (ret != connector->status)
+ connector->epoch_counter += 1;
+
+ return ret;
}
EXPORT_SYMBOL(drm_helper_probe_detect);
@@ -777,6 +785,7 @@ bool drm_helper_hpd_irq_event(struct drm_device *dev)
struct drm_connector_list_iter conn_iter;
enum drm_connector_status old_status;
bool changed = false;
+ uint64_t old_epoch_counter;
[Intel-gfx] [PATCH v6 3/3] drm/i915: Send hotplug event if edid had changed
Added epoch counter checking to intel_encoder_hotplug
in order to be able process all the connector changes,
besides connection status. Also now any change in connector
would result in epoch counter change, so no multiple checks
are needed.
v2: Renamed change counter to epoch counter. Fixed type name.
v3: Fixed rebase conflict
v4: Remove duplicate drm_edid_equal checks from hdmi and dp,
lets use only once edid property is getting updated and
increment epoch counter from there.
Also lets now call drm_connector_update_edid_property
right after we get edid always to make sure there is a
unified way to handle edid change, without having to
change tons of source code as currently
drm_connector_update_edid_property is called only in
certain cases like reprobing and not right after edid is
actually updated.
v5: Fixed const modifiers, removed blank line
v6: Removed drm specific part from this patch, leaving only
i915 specific changes here.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_hotplug.c | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c
b/drivers/gpu/drm/i915/display/intel_hotplug.c
index fc29046d48ea..1e3e425dd78d 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
@@ -280,23 +280,31 @@ intel_encoder_hotplug(struct intel_encoder *encoder,
{
struct drm_device *dev = connector->base.dev;
enum drm_connector_status old_status;
+ u64 old_epoch_counter;
+ bool ret = false;
WARN_ON(!mutex_is_locked(>mode_config.mutex));
old_status = connector->base.status;
+ old_epoch_counter = connector->base.epoch_counter;
+
connector->base.status =
drm_helper_probe_detect(>base, NULL, false);
- if (old_status == connector->base.status)
- return INTEL_HOTPLUG_UNCHANGED;
+ if (old_epoch_counter != connector->base.epoch_counter)
+ ret = true;
- DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
+ if (ret) {
+ DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to
%s(epoch counter %llu)\n",
connector->base.base.id,
connector->base.name,
drm_get_connector_status_name(old_status),
- drm_get_connector_status_name(connector->base.status));
+ drm_get_connector_status_name(connector->base.status),
+ connector->base.epoch_counter);
+ return INTEL_HOTPLUG_CHANGED;
+ }
- return INTEL_HOTPLUG_CHANGED;
+ return INTEL_HOTPLUG_UNCHANGED;
}
static bool intel_encoder_has_hpd_pulse(struct intel_encoder *encoder)
--
2.17.1
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[Intel-gfx] [PATCH v6 1/3] drm: Add helper to compare edids.
Many drivers would benefit from using
drm helper to compare edid, rather
than bothering with own implementation.
v2: Added documentation for this function.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/drm_edid.c | 33 +
include/drm/drm_edid.h | 9 +
2 files changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 82a4ceed3fcf..0639db9fd23f 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1362,6 +1362,39 @@ static bool drm_edid_is_zero(const u8 *in_edid, int
length)
return true;
}
+/**
+ * drm_edid_are_equal - compare two edid blobs.
+ * @edid1: pointer to first blob
+ * @edid2: pointer to second blob
+ * This helper can be used during probing to determine if
+ * edid had changed.
+ */
+bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2)
+{
+ int edid1_len, edid2_len;
+ bool edid1_present = edid1 != NULL;
+ bool edid2_present = edid2 != NULL;
+
+ if (edid1_present != edid2_present)
+ return false;
+
+ if (edid1) {
+
+ edid1_len = EDID_LENGTH * (1 + edid1->extensions);
+ edid2_len = EDID_LENGTH * (1 + edid2->extensions);
+
+ if (edid1_len != edid2_len)
+ return false;
+
+ if (memcmp(edid1, edid2, edid1_len))
+ return false;
+ }
+
+ return true;
+}
+EXPORT_SYMBOL(drm_edid_are_equal);
+
+
/**
* drm_edid_block_valid - Sanity check the EDID block (base or extension)
* @raw_edid: pointer to raw EDID block
diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
index b9719418c3d2..b0c68b2d79ed 100644
--- a/include/drm/drm_edid.h
+++ b/include/drm/drm_edid.h
@@ -354,6 +354,15 @@ drm_load_edid_firmware(struct drm_connector *connector)
}
#endif
+/**
+ * drm_edid_are_equal - compare two edid blobs.
+ * @edid1: pointer to first blob
+ * @edid2: pointer to second blob
+ * This helper can be used during probing to determine if
+ * edid had changed.
+ */
+bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2);
+
int
drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
struct drm_connector *connector,
--
2.17.1
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