[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Don't disable interrupts independently of the lock (rev4)
== Series Details ==
Series: drm/i915: Don't disable interrupts independently of the lock (rev4)
URL : https://patchwork.freedesktop.org/series/59289/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7122_full -> Patchwork_14862_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14862_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_cursor_crc@pipe-d-cursor-512x170-offscreen}:
- {shard-tglb}: NOTRUN -> [SKIP][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14862/shard-tglb5/igt@kms_cursor_...@pipe-d-cursor-512x170-offscreen.html
* {igt@kms_cursor_crc@pipe-d-cursor-64x21-onscreen}:
- {shard-tglb}: NOTRUN -> [FAIL][2] +4 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14862/shard-tglb2/igt@kms_cursor_...@pipe-d-cursor-64x21-onscreen.html
* igt@perf_pmu@enable-race-vcs1:
- {shard-tglb}: NOTRUN -> [INCOMPLETE][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14862/shard-tglb4/igt@perf_...@enable-race-vcs1.html
Known issues
Here are the changes found in Patchwork_14862_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [PASS][4] -> [SKIP][5] ([fdo#110841])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/shard-iclb8/igt@gem_ctx_sha...@exec-single-timeline-bsd.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14862/shard-iclb2/igt@gem_ctx_sha...@exec-single-timeline-bsd.html
* igt@gem_eio@unwedge-stress:
- shard-snb: [PASS][6] -> [FAIL][7] ([fdo#109661])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/shard-snb1/igt@gem_...@unwedge-stress.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14862/shard-snb6/igt@gem_...@unwedge-stress.html
* igt@gem_exec_balancer@smoke:
- shard-iclb: [PASS][8] -> [SKIP][9] ([fdo#110854])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/shard-iclb4/igt@gem_exec_balan...@smoke.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14862/shard-iclb6/igt@gem_exec_balan...@smoke.html
* igt@gem_exec_schedule@out-order-bsd2:
- shard-iclb: [PASS][10] -> [SKIP][11] ([fdo#109276]) +14 similar
issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/shard-iclb4/igt@gem_exec_sched...@out-order-bsd2.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14862/shard-iclb6/igt@gem_exec_sched...@out-order-bsd2.html
* igt@gem_exec_schedule@preempt-hang-bsd:
- shard-iclb: [PASS][12] -> [SKIP][13] ([fdo#111325]) +2 similar
issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/shard-iclb6/igt@gem_exec_sched...@preempt-hang-bsd.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14862/shard-iclb1/igt@gem_exec_sched...@preempt-hang-bsd.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-snb: [PASS][14] -> [DMESG-WARN][15] ([fdo#110789] /
[fdo#111870])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/shard-snb5/igt@gem_userptr_bl...@dmabuf-unsync.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14862/shard-snb2/igt@gem_userptr_bl...@dmabuf-unsync.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-snb: [PASS][16] -> [DMESG-WARN][17] ([fdo#111870])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/shard-snb6/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14862/shard-snb4/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html
* igt@i915_selftest@live_hangcheck:
- shard-snb: [PASS][18] -> [INCOMPLETE][19] ([fdo#105411])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/shard-snb2/igt@i915_selftest@live_hangcheck.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14862/shard-snb6/igt@i915_selftest@live_hangcheck.html
* igt@kms_color@pipe-c-ctm-blue-to-red:
- shard-skl: [PASS][20] -> [DMESG-WARN][21] ([fdo#106107])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/shard-skl9/igt@kms_co...@pipe-c-ctm-blue-to-red.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14862/shard-skl2/igt@kms_co...@pipe-c-ctm-blue-to-red.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-apl: [PASS][22] -> [DMESG-WARN][23] ([fdo#108566]) +3
similar issues
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/shard-apl8/igt@kms_cursor_...@pipe-c-cursor-suspend.html
[23]:
https://intel-gfx-ci.01.org/tree/drm
Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/aml: Allow SPT PCH for all AML devices (rev2)
> -Original Message-
> From: Intel-gfx On Behalf Of
> Patchwork
> Sent: perjantai 18. lokakuuta 2019 6.33
> To: Ausmus, James
> Cc: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/aml: Allow SPT PCH for
> all AML
> devices (rev2)
>
> == Series Details ==
>
> Series: drm/i915/aml: Allow SPT PCH for all AML devices (rev2)
> URL : https://patchwork.freedesktop.org/series/68176/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7125 -> Patchwork_14872
>
>
> Summary
> ---
>
> **SUCCESS**
>
> No regressions found.
>
> External URL: https://intel-gfx-ci.01.org/tree/drm-
> tip/Patchwork_14872/index.html
>
> Known issues
>
>
> Here are the changes found in Patchwork_14872 that come from known issues:
>
> ### IGT changes ###
>
> Issues hit
>
> * igt@i915_selftest@live_execlists:
> - fi-skl-lmem:[PASS][1] -> [INCOMPLETE][2] ([fdo#111934])
>[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-skl-
> lmem/igt@i915_selftest@live_execlists.html
>[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14872/fi-skl-
> lmem/igt@i915_selftest@live_execlists.html
If 111934 is fixed (resolved) how this can be happening? @Vudum, Lakshminarayana
>
> * igt@prime_vgem@basic-fence-flip:
> - fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +1
> similar issue
>[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-
> u3/igt@prime_v...@basic-fence-flip.html
>[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14872/fi-icl-
> u3/igt@prime_v...@basic-fence-flip.html
>
>
> Possible fixes
>
> * igt@gem_exec_suspend@basic-s4-devices:
> - fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6] +1
> similar issue
>[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-
> u3/igt@gem_exec_susp...@basic-s4-devices.html
>[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14872/fi-icl-
> u3/igt@gem_exec_susp...@basic-s4-devices.html
>
> * igt@i915_selftest@live_execlists:
> - fi-icl-u2: [INCOMPLETE][7] ([fdo#107713]) -> [PASS][8]
>[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-
> u2/igt@i915_selftest@live_execlists.html
>[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14872/fi-icl-
> u2/igt@i915_selftest@live_execlists.html
> - fi-apl-guc: [DMESG-FAIL][9] -> [PASS][10]
>[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-apl-
> guc/igt@i915_selftest@live_execlists.html
>[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14872/fi-apl-
> guc/igt@i915_selftest@live_execlists.html
>
> * igt@i915_selftest@live_hangcheck:
> - fi-icl-u3: [INCOMPLETE][11] ([fdo#107713] / [fdo#108569]) ->
> [PASS][12]
>[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-
> u3/igt@i915_selftest@live_hangcheck.html
>[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14872/fi-icl-
> u3/igt@i915_selftest@live_hangcheck.html
>
>
> {name}: This element is suppressed. This means it is ignored when computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
> [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
> [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
> [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
> [fdo#111887]: https://bugs.freedesktop.org/show_bug.cgi?id=111887
> [fdo#111934]: https://bugs.freedesktop.org/show_bug.cgi?id=111934
>
>
> Participating hosts (53 -> 44)
> --
>
> Missing(9): fi-icl-u4 fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
> fi-bsw-cyan fi-byt-
> clapper fi-icl-y fi-icl-dsi fi-bdw-samus
>
>
> Build changes
> -
>
> * CI: CI-20190529 -> None
> * Linux: CI_DRM_7125 -> Patchwork_14872
>
> CI-20190529: 20190529
> CI_DRM_7125: f1ac92f5feb18678a3191a45be0ee4a4d255fc61 @
> git://anongit.freedesktop.org/gfx-ci/linux
> IGT_5232: bb5735423eaf6fdbf6b2f94ef0b8520e74eab993 @
> git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> Patchwork_14872: 22a8727caa6d0720da77b693cdf317d8fc1b4054 @
> git://anongit.freedesktop.org/gfx-ci/linux
>
>
> == Linux commits ==
>
> 22a8727caa6d drm/i915/aml: Allow SPT PCH for all AML devices
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-
> tip/Patchwork_14872/index.html
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/5] drm/i915: simplify setting of ddi_io_power_domain (rev3)
Hi,
> -Original Message-
> From: Intel-gfx On Behalf Of
> Patchwork
> Sent: perjantai 18. lokakuuta 2019 5.42
> To: De Marchi, Lucas
> Cc: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/5]
> drm/i915:
> simplify setting of ddi_io_power_domain (rev3)
>
> == Series Details ==
>
> Series: series starting with [CI,1/5] drm/i915: simplify setting of
> ddi_io_power_domain (rev3)
> URL : https://patchwork.freedesktop.org/series/68069/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7125 -> Patchwork_14870
>
>
> Summary
> ---
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_14870 absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_14870, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL: https://intel-gfx-ci.01.org/tree/drm-
> tip/Patchwork_14870/index.html
>
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> Patchwork_14870:
>
> ### IGT changes ###
>
> Possible regressions
>
> * igt@i915_selftest@live_execlists:
> - fi-icl-u3: NOTRUN -> [DMESG-FAIL][1]
>[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14870/fi-icl-
> u3/igt@i915_selftest@live_execlists.html
> - fi-glk-dsi: [PASS][2] -> [DMESG-FAIL][3]
>[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-glk-
> dsi/igt@i915_selftest@live_execlists.html
>[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14870/fi-glk-
> dsi/igt@i915_selftest@live_execlists.html
> - fi-kbl-x1275: [PASS][4] -> [DMESG-FAIL][5]
>[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-kbl-
> x1275/igt@i915_selftest@live_execlists.html
>[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14870/fi-kbl-
> x1275/igt@i915_selftest@live_execlists.html
> - fi-skl-6770hq: [PASS][6] -> [DMESG-FAIL][7]
>[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-skl-
> 6770hq/igt@i915_selftest@live_execlists.html
>[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14870/fi-skl-
> 6770hq/igt@i915_selftest@live_execlists.html
>
Same here again, what is really causing these ?
>
> Suppressed
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * {igt@i915_selftest@live_perf}:
> - {fi-tgl-u2}:NOTRUN -> [INCOMPLETE][8]
>[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14870/fi-tgl-
> u2/igt@i915_selftest@live_perf.html
>
>
> Known issues
>
>
> Here are the changes found in Patchwork_14870 that come from known issues:
>
> ### IGT changes ###
>
> Issues hit
>
> * igt@gem_ctx_create@basic-files:
> - fi-bxt-dsi: [PASS][9] -> [INCOMPLETE][10] ([fdo#103927])
>[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-bxt-
> dsi/igt@gem_ctx_cre...@basic-files.html
>[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14870/fi-bxt-
> dsi/igt@gem_ctx_cre...@basic-files.html
>
>
> Possible fixes
>
> * igt@gem_mmap_gtt@basic-small-bo:
> - fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12]
>[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-
> u3/igt@gem_mmap_...@basic-small-bo.html
>[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14870/fi-icl-
> u3/igt@gem_mmap_...@basic-small-bo.html
>
> * igt@i915_selftest@live_execlists:
> - fi-icl-u2: [INCOMPLETE][13] ([fdo#107713]) -> [PASS][14]
>[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-
> u2/igt@i915_selftest@live_execlists.html
>[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14870/fi-icl-
> u2/igt@i915_selftest@live_execlists.html
> - fi-apl-guc: [DMESG-FAIL][15] -> [PASS][16]
>[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-apl-
> guc/igt@i915_selftest@live_execlists.html
>[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14870/fi-apl-
> guc/igt@i915_selftest@live_execlists.html
> - {fi-icl-dsi}: [DMESG-FAIL][17] -> [PASS][18]
>[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-
> dsi/igt@i915_selftest@live_execlists.html
>[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14870/fi-icl-
> dsi/igt@i915_selftest@live_execlists.html
> - fi-skl-6260u: [DMESG-FAIL][19] -> [PASS][20]
>[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-skl-
> 6260u/igt@i915_selftest@live_execlists.html
>[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14870/fi-skl-
> 6260u/igt@i915_selftest@live_execlists.html
>
> * igt@i915_selftest@
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/aml: Allow SPT PCH for all AML devices
Hi,
> -Original Message-
> From: Intel-gfx On Behalf Of James
> Ausmus
> Sent: perjantai 18. lokakuuta 2019 4.19
> To: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/aml: Allow SPT PCH
> for all
> AML devices
>
> On Fri, Oct 18, 2019 at 01:00:59AM +, Patchwork wrote:
> > == Series Details ==
> >
> > Series: drm/i915/aml: Allow SPT PCH for all AML devices
> > URL : https://patchwork.freedesktop.org/series/68176/
> > State : failure
> >
> > == Summary ==
> >
> > CI Bug Log - changes from CI_DRM_7125 -> Patchwork_14867
> >
> >
> > Summary
> > ---
> >
> > **FAILURE**
> >
> > Serious unknown changes coming with Patchwork_14867 absolutely need to be
> > verified manually.
> >
> > If you think the reported changes have nothing to do with the changes
> > introduced in Patchwork_14867, please notify your bug team to allow them
> > to document this new failure mode, which will reduce false positives in
> > CI.
> >
> > External URL:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/index.html
> >
> > Possible new issues
> > ---
> >
> > Here are the unknown changes that may have been introduced in
> Patchwork_14867:
> >
> > ### IGT changes ###
> >
> > Possible regressions
> >
> > * igt@i915_selftest@live_execlists:
> > - fi-icl-u3: NOTRUN -> [DMESG-FAIL][1]
> >[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/fi-icl-
> u3/igt@i915_selftest@live_execlists.html
> > - fi-skl-6600u: [PASS][2] -> [DMESG-FAIL][3]
> >[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-skl-
> 6600u/igt@i915_selftest@live_execlists.html
> >[3]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/fi-skl-6600u/
> > igt@i915_selftest@live_execlists.html
>
> Not related at all to this patch, hitting the retest button...
Yes, and if you look pretty much all series on BAT these
igt@i915_selftest@live_execlists and
@live_gem_contexts seems to blow lately, Chris, do we know reason why?
>
> -James
>
> >
> >
> > Known issues
> >
> >
> > Here are the changes found in Patchwork_14867 that come from known issues:
> >
> > ### IGT changes ###
> >
> > Issues hit
> >
> > * igt@gem_mmap_gtt@basic-read-write:
> > - fi-icl-u3: [PASS][4] -> [DMESG-WARN][5] ([fdo#107724])
> >[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-
> u3/igt@gem_mmap_...@basic-read-write.html
> >[5]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/fi-icl-u3/igt
> > @gem_mmap_...@basic-read-write.html
> >
> >
> > Possible fixes
> >
> > * igt@gem_mmap_gtt@basic-small-bo:
> > - fi-icl-u3: [DMESG-WARN][6] ([fdo#107724]) -> [PASS][7]
> >[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-
> u3/igt@gem_mmap_...@basic-small-bo.html
> >[7]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/fi-icl-u3/igt
> > @gem_mmap_...@basic-small-bo.html
> >
> > * igt@i915_selftest@live_execlists:
> > - fi-icl-u2: [INCOMPLETE][8] ([fdo#107713]) -> [PASS][9]
> >[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-
> u2/igt@i915_selftest@live_execlists.html
> >[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/fi-icl-
> u2/igt@i915_selftest@live_execlists.html
> > - fi-apl-guc: [DMESG-FAIL][10] -> [PASS][11]
> >[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-apl-
> guc/igt@i915_selftest@live_execlists.html
> >[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/fi-apl-
> guc/igt@i915_selftest@live_execlists.html
> > - fi-skl-6260u: [DMESG-FAIL][12] -> [PASS][13]
> >[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-skl-
> 6260u/igt@i915_selftest@live_execlists.html
> >[13]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/fi-skl-6260u/
> > igt@i915_selftest@live_execlists.html
> >
> > * igt@i915_selftest@live_hangcheck:
> > - fi-icl-u3: [INCOMPLETE][14] ([fdo#107713] / [fdo#108569]) ->
> > [PASS][15]
> >[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-
> u3/igt@i915_selftest@live_hangcheck.html
> >[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/fi-icl-
> u3/igt@i915_selftest@live_hangcheck.html
> > - {fi-icl-u4}:[INCOMPLETE][16] ([fdo#107713] / [fdo#108569]) ->
> > [PASS][17]
> >[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-
> u4/igt@i915_selftest@live_hangcheck.html
> >[17]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/fi-icl-u4/igt
> > @i915_selftest@live_hangcheck.html
> >
> > * igt@kms_chamelium@common-hpd-after-suspend:
> > - fi-icl-u2: [DMESG-WARN][18] ([fdo#102505] / [fdo#110390]) ->
> > [PASS][19]
> >[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-
> u2/
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Correct the PCH type in irq postinstall (rev2)
== Series Details ==
Series: drm/i915: Correct the PCH type in irq postinstall (rev2)
URL : https://patchwork.freedesktop.org/series/68116/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7122_full -> Patchwork_14860_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14860_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14860_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14860_full:
### IGT changes ###
Possible regressions
* igt@gem_persistent_relocs@forked-interruptible-thrash-inactive:
- shard-kbl: [PASS][1] -> [TIMEOUT][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/shard-kbl1/igt@gem_persistent_rel...@forked-interruptible-thrash-inactive.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14860/shard-kbl6/igt@gem_persistent_rel...@forked-interruptible-thrash-inactive.html
* igt@gem_persistent_relocs@forked-interruptible-thrashing:
- shard-iclb: [PASS][3] -> [FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/shard-iclb8/igt@gem_persistent_rel...@forked-interruptible-thrashing.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14860/shard-iclb3/igt@gem_persistent_rel...@forked-interruptible-thrashing.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_cursor_crc@pipe-d-cursor-128x42-sliding}:
- {shard-tglb}: NOTRUN -> [FAIL][5] +4 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14860/shard-tglb1/igt@kms_cursor_...@pipe-d-cursor-128x42-sliding.html
* {igt@kms_cursor_crc@pipe-d-cursor-512x170-offscreen}:
- {shard-tglb}: NOTRUN -> [SKIP][6] +2 similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14860/shard-tglb5/igt@kms_cursor_...@pipe-d-cursor-512x170-offscreen.html
New tests
-
New tests have been introduced between CI_DRM_7122_full and
Patchwork_14860_full:
### New Piglit tests (3) ###
* spec@arb_texture_compression@fbo-generatemipmap-formats:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_texture_compression_bptc@fbo-generatemipmap-formats float:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_texture_compression_bptc@fbo-generatemipmap-formats unorm:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_14860_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_schedule@preempt-queue-chain-bsd2:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276]) +12 similar
issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/shard-iclb1/igt@gem_exec_sched...@preempt-queue-chain-bsd2.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14860/shard-iclb8/igt@gem_exec_sched...@preempt-queue-chain-bsd2.html
* igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#111325]) +3 similar
issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/shard-iclb7/igt@gem_exec_sched...@preempt-queue-contexts-chain-bsd.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14860/shard-iclb1/igt@gem_exec_sched...@preempt-queue-contexts-chain-bsd.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-snb: [PASS][11] -> [DMESG-WARN][12] ([fdo#111870])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/shard-snb5/igt@gem_userptr_bl...@dmabuf-unsync.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14860/shard-snb2/igt@gem_userptr_bl...@dmabuf-unsync.html
* igt@gem_userptr_blits@sync-unmap-after-close:
- shard-apl: [PASS][13] -> [DMESG-WARN][14] ([fdo#109385] /
[fdo#111870])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/shard-apl8/igt@gem_userptr_bl...@sync-unmap-after-close.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14860/shard-apl4/igt@gem_userptr_bl...@sync-unmap-after-close.html
* igt@i915_pm_rpm@i2c:
- shard-glk: [PASS][15] -> [FAIL][16] ([fdo#104097])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/shard-glk4/igt@i915_pm_...@i2c.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14860/shard-glk8/igt@i915_pm_...@i2c.html
* igt@kms_color@pipe-b-ctm-blue-to-red:
- shard-skl: [PASS][17] -> [DMESG-WARN][18] ([fdo#106107])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/shar
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/aml: Allow SPT PCH for all AML devices (rev2)
== Series Details ==
Series: drm/i915/aml: Allow SPT PCH for all AML devices (rev2)
URL : https://patchwork.freedesktop.org/series/68176/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7125 -> Patchwork_14872
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14872/index.html
Known issues
Here are the changes found in Patchwork_14872 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_execlists:
- fi-skl-lmem:[PASS][1] -> [INCOMPLETE][2] ([fdo#111934])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-skl-lmem/igt@i915_selftest@live_execlists.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14872/fi-skl-lmem/igt@i915_selftest@live_execlists.html
* igt@prime_vgem@basic-fence-flip:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +1
similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u3/igt@prime_v...@basic-fence-flip.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14872/fi-icl-u3/igt@prime_v...@basic-fence-flip.html
Possible fixes
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6] +1
similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14872/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
* igt@i915_selftest@live_execlists:
- fi-icl-u2: [INCOMPLETE][7] ([fdo#107713]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u2/igt@i915_selftest@live_execlists.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14872/fi-icl-u2/igt@i915_selftest@live_execlists.html
- fi-apl-guc: [DMESG-FAIL][9] -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-apl-guc/igt@i915_selftest@live_execlists.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14872/fi-apl-guc/igt@i915_selftest@live_execlists.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u3: [INCOMPLETE][11] ([fdo#107713] / [fdo#108569]) ->
[PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14872/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#111887]: https://bugs.freedesktop.org/show_bug.cgi?id=111887
[fdo#111934]: https://bugs.freedesktop.org/show_bug.cgi?id=111934
Participating hosts (53 -> 44)
--
Missing(9): fi-icl-u4 fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-byt-clapper fi-icl-y fi-icl-dsi fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7125 -> Patchwork_14872
CI-20190529: 20190529
CI_DRM_7125: f1ac92f5feb18678a3191a45be0ee4a4d255fc61 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5232: bb5735423eaf6fdbf6b2f94ef0b8520e74eab993 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14872: 22a8727caa6d0720da77b693cdf317d8fc1b4054 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
22a8727caa6d drm/i915/aml: Allow SPT PCH for all AML devices
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14872/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v2,1/3] drm/i915/perf: Add helper macros for comparing with whitelisted registers
== Series Details ==
Series: series starting with [v2,1/3] drm/i915/perf: Add helper macros for
comparing with whitelisted registers
URL : https://patchwork.freedesktop.org/series/68180/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7125 -> Patchwork_14871
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14871 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14871, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14871/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14871:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_execlists:
- fi-glk-dsi: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-glk-dsi/igt@i915_selftest@live_execlists.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14871/fi-glk-dsi/igt@i915_selftest@live_execlists.html
Warnings
* igt@i915_selftest@live_execlists:
- fi-icl-u2: [INCOMPLETE][3] ([fdo#107713]) -> [DMESG-FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u2/igt@i915_selftest@live_execlists.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14871/fi-icl-u2/igt@i915_selftest@live_execlists.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live_execlists:
- {fi-cml-s}: [PASS][5] -> [DMESG-FAIL][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-cml-s/igt@i915_selftest@live_execlists.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14871/fi-cml-s/igt@i915_selftest@live_execlists.html
Known issues
Here are the changes found in Patchwork_14871 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_mmap_gtt@basic-read-write:
- fi-icl-u3: [PASS][7] -> [DMESG-WARN][8] ([fdo#107724])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u3/igt@gem_mmap_...@basic-read-write.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14871/fi-icl-u3/igt@gem_mmap_...@basic-read-write.html
Possible fixes
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10] +1
similar issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14871/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
* igt@i915_selftest@live_execlists:
- fi-apl-guc: [DMESG-FAIL][11] -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-apl-guc/igt@i915_selftest@live_execlists.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14871/fi-apl-guc/igt@i915_selftest@live_execlists.html
- fi-skl-6260u: [DMESG-FAIL][13] -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-skl-6260u/igt@i915_selftest@live_execlists.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14871/fi-skl-6260u/igt@i915_selftest@live_execlists.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u3: [INCOMPLETE][15] ([fdo#107713] / [fdo#108569]) ->
[PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14871/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
- {fi-icl-u4}:[INCOMPLETE][17] ([fdo#107713] / [fdo#108569]) ->
[PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14871/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][19] ([fdo#111407]) -> [FAIL][20] ([fdo#111045]
/ [fdo#111096])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14871/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=1085
[Intel-gfx] ✗ Fi.CI.IGT: failure for mdev based hardware virtio offloading support (rev5)
== Series Details ==
Series: mdev based hardware virtio offloading support (rev5)
URL : https://patchwork.freedesktop.org/series/66989/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7122_full -> Patchwork_14857_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14857_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14857_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14857_full:
### IGT changes ###
Possible regressions
* igt@gem_persistent_relocs@forked-thrashing:
- shard-snb: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/shard-snb5/igt@gem_persistent_rel...@forked-thrashing.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14857/shard-snb7/igt@gem_persistent_rel...@forked-thrashing.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_cursor_crc@pipe-d-cursor-256x256-sliding}:
- {shard-tglb}: NOTRUN -> [FAIL][3] +4 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14857/shard-tglb1/igt@kms_cursor_...@pipe-d-cursor-256x256-sliding.html
* {igt@kms_cursor_crc@pipe-d-cursor-512x170-offscreen}:
- {shard-tglb}: NOTRUN -> [SKIP][4]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14857/shard-tglb1/igt@kms_cursor_...@pipe-d-cursor-512x170-offscreen.html
* {igt@perf_pmu@semaphore-busy-bcs0}:
- shard-skl: [PASS][5] -> [DMESG-WARN][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/shard-skl4/igt@perf_...@semaphore-busy-bcs0.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14857/shard-skl2/igt@perf_...@semaphore-busy-bcs0.html
Known issues
Here are the changes found in Patchwork_14857_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_reuse@single:
- shard-iclb: [PASS][7] -> [INCOMPLETE][8] ([fdo#107713] /
[fdo#109100])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/shard-iclb7/igt@gem_exec_re...@single.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14857/shard-iclb7/igt@gem_exec_re...@single.html
* igt@gem_exec_schedule@preempt-queue-bsd:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#111325]) +6 similar
issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/shard-iclb5/igt@gem_exec_sched...@preempt-queue-bsd.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14857/shard-iclb2/igt@gem_exec_sched...@preempt-queue-bsd.html
* igt@gem_exec_schedule@preempt-queue-chain-bsd2:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109276]) +9 similar
issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/shard-iclb1/igt@gem_exec_sched...@preempt-queue-chain-bsd2.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14857/shard-iclb5/igt@gem_exec_sched...@preempt-queue-chain-bsd2.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-hsw: [PASS][13] -> [DMESG-WARN][14] ([fdo#111870])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/shard-hsw4/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14857/shard-hsw5/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html
* igt@gem_userptr_blits@sync-unmap-after-close:
- shard-snb: [PASS][15] -> [DMESG-WARN][16] ([fdo#111870])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/shard-snb1/igt@gem_userptr_bl...@sync-unmap-after-close.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14857/shard-snb2/igt@gem_userptr_bl...@sync-unmap-after-close.html
* igt@i915_selftest@live_hangcheck:
- shard-hsw: [PASS][17] -> [DMESG-FAIL][18] ([fdo#111991])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/shard-hsw5/igt@i915_selftest@live_hangcheck.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14857/shard-hsw7/igt@i915_selftest@live_hangcheck.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-snb: [PASS][19] -> [DMESG-WARN][20] ([fdo#102365])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/shard-snb6/igt@i915_susp...@fence-restore-tiled2untiled.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14857/shard-snb4/igt@i915_susp...@fence-restore-tiled2untiled.html
* igt@kms_cursor_crc@pipe-b-cursor-256x85-sliding:
- shard-skl: [PASS][21] -> [FAIL]
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/5] drm/i915: simplify setting of ddi_io_power_domain (rev3)
== Series Details ==
Series: series starting with [CI,1/5] drm/i915: simplify setting of
ddi_io_power_domain (rev3)
URL : https://patchwork.freedesktop.org/series/68069/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7125 -> Patchwork_14870
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14870 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14870, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14870/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14870:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_execlists:
- fi-icl-u3: NOTRUN -> [DMESG-FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14870/fi-icl-u3/igt@i915_selftest@live_execlists.html
- fi-glk-dsi: [PASS][2] -> [DMESG-FAIL][3]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-glk-dsi/igt@i915_selftest@live_execlists.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14870/fi-glk-dsi/igt@i915_selftest@live_execlists.html
- fi-kbl-x1275: [PASS][4] -> [DMESG-FAIL][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-kbl-x1275/igt@i915_selftest@live_execlists.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14870/fi-kbl-x1275/igt@i915_selftest@live_execlists.html
- fi-skl-6770hq: [PASS][6] -> [DMESG-FAIL][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-skl-6770hq/igt@i915_selftest@live_execlists.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14870/fi-skl-6770hq/igt@i915_selftest@live_execlists.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@i915_selftest@live_perf}:
- {fi-tgl-u2}:NOTRUN -> [INCOMPLETE][8]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14870/fi-tgl-u2/igt@i915_selftest@live_perf.html
Known issues
Here are the changes found in Patchwork_14870 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_create@basic-files:
- fi-bxt-dsi: [PASS][9] -> [INCOMPLETE][10] ([fdo#103927])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-bxt-dsi/igt@gem_ctx_cre...@basic-files.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14870/fi-bxt-dsi/igt@gem_ctx_cre...@basic-files.html
Possible fixes
* igt@gem_mmap_gtt@basic-small-bo:
- fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u3/igt@gem_mmap_...@basic-small-bo.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14870/fi-icl-u3/igt@gem_mmap_...@basic-small-bo.html
* igt@i915_selftest@live_execlists:
- fi-icl-u2: [INCOMPLETE][13] ([fdo#107713]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u2/igt@i915_selftest@live_execlists.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14870/fi-icl-u2/igt@i915_selftest@live_execlists.html
- fi-apl-guc: [DMESG-FAIL][15] -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-apl-guc/igt@i915_selftest@live_execlists.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14870/fi-apl-guc/igt@i915_selftest@live_execlists.html
- {fi-icl-dsi}: [DMESG-FAIL][17] -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-dsi/igt@i915_selftest@live_execlists.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14870/fi-icl-dsi/igt@i915_selftest@live_execlists.html
- fi-skl-6260u: [DMESG-FAIL][19] -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-skl-6260u/igt@i915_selftest@live_execlists.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14870/fi-skl-6260u/igt@i915_selftest@live_execlists.html
* igt@i915_selftest@live_hangcheck:
- {fi-tgl-u2}:[INCOMPLETE][21] ([fdo#111747]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-tgl-u2/igt@i915_selftest@live_hangcheck.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14870/fi-tgl-u2/igt@i915_selftest@live_hangcheck.html
- fi-icl-u3: [INCOMPLETE][23] ([fdo#107713] / [fdo#108569]) ->
[PASS][24]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14870/fi-icl-u3/igt@i915_self
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v2,1/3] drm/i915/perf: Add helper macros for comparing with whitelisted registers
== Series Details == Series: series starting with [v2,1/3] drm/i915/perf: Add helper macros for comparing with whitelisted registers URL : https://patchwork.freedesktop.org/series/68180/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.6.0 Commit: drm/i915/perf: Add helper macros for comparing with whitelisted registers Okay! Commit: drm/i915/perf: enable OAR context save/restore of performance counters Okay! Commit: drm/i915/tgl: Add perf support on TGL +drivers/gpu/drm/i915/i915_perf.c:2441:85: warning: dubious: x | !y ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/3] drm/i915/perf: Add helper macros for comparing with whitelisted registers
== Series Details == Series: series starting with [v2,1/3] drm/i915/perf: Add helper macros for comparing with whitelisted registers URL : https://patchwork.freedesktop.org/series/68180/ State : warning == Summary == $ dim checkpatch origin/drm-tip 8537fc751bda drm/i915/perf: Add helper macros for comparing with whitelisted registers -:21: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'addr' - possible side-effects? #21: FILE: drivers/gpu/drm/i915/i915_perf.c:3517: +#define ADDR_IN_RANGE(addr, start, end) \ + ((addr) >= (start) && \ +(addr) <= (end)) -:25: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'addr' - possible side-effects? #25: FILE: drivers/gpu/drm/i915/i915_perf.c:3521: +#define REG_IN_RANGE(addr, start, end) \ + ((addr) >= i915_mmio_reg_offset(start) && \ +(addr) <= i915_mmio_reg_offset(end)) total: 0 errors, 0 warnings, 2 checks, 98 lines checked 6dd750d75570 drm/i915/perf: enable OAR context save/restore of performance counters -:81: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "oa_config" #81: FILE: drivers/gpu/drm/i915/i915_perf.c:1921: + err = gen12_emit_oar_config(rq, ce, oa_config != NULL); -:85: CHECK:BRACES: Blank lines aren't necessary before a close brace '}' #85: FILE: drivers/gpu/drm/i915/i915_perf.c:1925: + + } total: 0 errors, 0 warnings, 2 checks, 61 lines checked d6c3a1a90470 drm/i915/tgl: Add perf support on TGL -:737: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #737: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 788 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/5] drm/i915: simplify setting of ddi_io_power_domain (rev3)
== Series Details == Series: series starting with [CI,1/5] drm/i915: simplify setting of ddi_io_power_domain (rev3) URL : https://patchwork.freedesktop.org/series/68069/ State : warning == Summary == $ dim checkpatch origin/drm-tip da7092cd71c4 drm/i915: simplify setting of ddi_io_power_domain f7755e120d58 drm/i915: fix port checks for MST support on gen >= 11 04b343b84c42 drm/i915: remove extra new line on pipe_config mismatch -:52: WARNING:LONG_LINE: line over 100 characters #52: FILE: drivers/gpu/drm/i915/display/intel_display.c:12613: +"unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \ total: 0 errors, 1 warnings, 0 checks, 88 lines checked fb53a11c4765 drm/i915: add pipe id/name to pipe mismatch logs 94aeb3b30d41 drm/i915: prettify MST debug message ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [RESEND,1/2] drm/i915/guc: Enable guc logging on guc log relay write
== Series Details ==
Series: series starting with [RESEND,1/2] drm/i915/guc: Enable guc logging on
guc log relay write
URL : https://patchwork.freedesktop.org/series/68179/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7125 -> Patchwork_14869
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14869 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14869, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14869/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14869:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_execlists:
- fi-kbl-x1275: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-kbl-x1275/igt@i915_selftest@live_execlists.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14869/fi-kbl-x1275/igt@i915_selftest@live_execlists.html
- fi-cml-u2: [PASS][3] -> [DMESG-FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-cml-u2/igt@i915_selftest@live_execlists.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14869/fi-cml-u2/igt@i915_selftest@live_execlists.html
Known issues
Here are the changes found in Patchwork_14869 that come from known issues:
### IGT changes ###
Possible fixes
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6] +1
similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14869/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
* igt@i915_selftest@live_execlists:
- fi-icl-u2: [INCOMPLETE][7] ([fdo#107713]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u2/igt@i915_selftest@live_execlists.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14869/fi-icl-u2/igt@i915_selftest@live_execlists.html
- fi-apl-guc: [DMESG-FAIL][9] -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-apl-guc/igt@i915_selftest@live_execlists.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14869/fi-apl-guc/igt@i915_selftest@live_execlists.html
- fi-skl-6260u: [DMESG-FAIL][11] -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-skl-6260u/igt@i915_selftest@live_execlists.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14869/fi-skl-6260u/igt@i915_selftest@live_execlists.html
* igt@i915_selftest@live_hangcheck:
- {fi-tgl-u2}:[INCOMPLETE][13] ([fdo#111747]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-tgl-u2/igt@i915_selftest@live_hangcheck.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14869/fi-tgl-u2/igt@i915_selftest@live_hangcheck.html
- fi-icl-u3: [INCOMPLETE][15] ([fdo#107713] / [fdo#108569]) ->
[PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14869/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
- {fi-icl-u4}:[INCOMPLETE][17] ([fdo#107713] / [fdo#108569]) ->
[PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14869/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][19] ([fdo#111407]) -> [FAIL][20] ([fdo#111045]
/ [fdo#111096])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14869/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111747]: https://bugs.freedesktop.org/sho
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v2,1/3] drm/i915/perf: Add helper macros for comparing with whitelisted registers
== Series Details ==
Series: series starting with [v2,1/3] drm/i915/perf: Add helper macros for
comparing with whitelisted registers
URL : https://patchwork.freedesktop.org/series/68178/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7125 -> Patchwork_14868
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14868 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14868, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14868/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14868:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_execlists:
- fi-bxt-dsi: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-bxt-dsi/igt@i915_selftest@live_execlists.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14868/fi-bxt-dsi/igt@i915_selftest@live_execlists.html
Known issues
Here are the changes found in Patchwork_14868 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_create@basic-files:
- fi-icl-u3: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713] /
[fdo#109100])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14868/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html
- fi-apl-guc: [PASS][5] -> [INCOMPLETE][6] ([fdo#103927])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-apl-guc/igt@gem_ctx_cre...@basic-files.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14868/fi-apl-guc/igt@gem_ctx_cre...@basic-files.html
Possible fixes
* igt@i915_selftest@live_hangcheck:
- {fi-icl-u4}:[INCOMPLETE][7] ([fdo#107713] / [fdo#108569]) ->
[PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14868/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
[fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
[fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850
Participating hosts (53 -> 46)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7125 -> Patchwork_14868
CI-20190529: 20190529
CI_DRM_7125: f1ac92f5feb18678a3191a45be0ee4a4d255fc61 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5232: bb5735423eaf6fdbf6b2f94ef0b8520e74eab993 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14868: e77274f9357c88635ff612e7511ad5c4433b1b55 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
e77274f9357c drm/i915/tgl: Add perf support on TGL
2fbac0aa101f drm/i915/perf: enable OAR context save/restore of performance
counters
be37b0df8d67 drm/i915/perf: Add helper macros for comparing with whitelisted
registers
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14868/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/aml: Allow SPT PCH for all AML devices
On Fri, Oct 18, 2019 at 01:00:59AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/aml: Allow SPT PCH for all AML devices
> URL : https://patchwork.freedesktop.org/series/68176/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7125 -> Patchwork_14867
>
>
> Summary
> ---
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_14867 absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_14867, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/index.html
>
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> Patchwork_14867:
>
> ### IGT changes ###
>
> Possible regressions
>
> * igt@i915_selftest@live_execlists:
> - fi-icl-u3: NOTRUN -> [DMESG-FAIL][1]
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/fi-icl-u3/igt@i915_selftest@live_execlists.html
> - fi-skl-6600u: [PASS][2] -> [DMESG-FAIL][3]
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-skl-6600u/igt@i915_selftest@live_execlists.html
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/fi-skl-6600u/igt@i915_selftest@live_execlists.html
Not related at all to this patch, hitting the retest button...
-James
>
>
> Known issues
>
>
> Here are the changes found in Patchwork_14867 that come from known issues:
>
> ### IGT changes ###
>
> Issues hit
>
> * igt@gem_mmap_gtt@basic-read-write:
> - fi-icl-u3: [PASS][4] -> [DMESG-WARN][5] ([fdo#107724])
>[4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u3/igt@gem_mmap_...@basic-read-write.html
>[5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/fi-icl-u3/igt@gem_mmap_...@basic-read-write.html
>
>
> Possible fixes
>
> * igt@gem_mmap_gtt@basic-small-bo:
> - fi-icl-u3: [DMESG-WARN][6] ([fdo#107724]) -> [PASS][7]
>[6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u3/igt@gem_mmap_...@basic-small-bo.html
>[7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/fi-icl-u3/igt@gem_mmap_...@basic-small-bo.html
>
> * igt@i915_selftest@live_execlists:
> - fi-icl-u2: [INCOMPLETE][8] ([fdo#107713]) -> [PASS][9]
>[8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u2/igt@i915_selftest@live_execlists.html
>[9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/fi-icl-u2/igt@i915_selftest@live_execlists.html
> - fi-apl-guc: [DMESG-FAIL][10] -> [PASS][11]
>[10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-apl-guc/igt@i915_selftest@live_execlists.html
>[11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/fi-apl-guc/igt@i915_selftest@live_execlists.html
> - fi-skl-6260u: [DMESG-FAIL][12] -> [PASS][13]
>[12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-skl-6260u/igt@i915_selftest@live_execlists.html
>[13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/fi-skl-6260u/igt@i915_selftest@live_execlists.html
>
> * igt@i915_selftest@live_hangcheck:
> - fi-icl-u3: [INCOMPLETE][14] ([fdo#107713] / [fdo#108569]) ->
> [PASS][15]
>[14]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
>[15]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
> - {fi-icl-u4}:[INCOMPLETE][16] ([fdo#107713] / [fdo#108569]) ->
> [PASS][17]
>[16]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
>[17]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
>
> * igt@kms_chamelium@common-hpd-after-suspend:
> - fi-icl-u2: [DMESG-WARN][18] ([fdo#102505] / [fdo#110390]) ->
> [PASS][19]
>[18]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html
>[19]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html
>
>
> Warnings
>
> * igt@kms_chamelium@common-hpd-after-suspend:
> - fi-kbl-7500u: [DMESG-WARN][20] ([fdo#102505] / [fdo#103558] /
> [fdo#105079] / [fdo#105602]) -> [DMESG-FAIL][21] ([fdo#102505] / [fdo#103375]
> / [fdo#105079])
>[20]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html
>[21]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_1486
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v2,1/3] drm/i915/perf: Add helper macros for comparing with whitelisted registers
== Series Details == Series: series starting with [v2,1/3] drm/i915/perf: Add helper macros for comparing with whitelisted registers URL : https://patchwork.freedesktop.org/series/68178/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.6.0 Commit: drm/i915/perf: Add helper macros for comparing with whitelisted registers Okay! Commit: drm/i915/perf: enable OAR context save/restore of performance counters Okay! Commit: drm/i915/tgl: Add perf support on TGL +drivers/gpu/drm/i915/i915_perf.c:2433:85: warning: dubious: x | !y ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/3] drm/i915/perf: Add helper macros for comparing with whitelisted registers
== Series Details == Series: series starting with [v2,1/3] drm/i915/perf: Add helper macros for comparing with whitelisted registers URL : https://patchwork.freedesktop.org/series/68178/ State : warning == Summary == $ dim checkpatch origin/drm-tip be37b0df8d67 drm/i915/perf: Add helper macros for comparing with whitelisted registers -:21: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'addr' - possible side-effects? #21: FILE: drivers/gpu/drm/i915/i915_perf.c:3517: +#define ADDR_IN_RANGE(addr, start, end) \ + ((addr) >= (start) && \ +(addr) <= (end)) -:25: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'addr' - possible side-effects? #25: FILE: drivers/gpu/drm/i915/i915_perf.c:3521: +#define REG_IN_RANGE(addr, start, end) \ + ((addr) >= i915_mmio_reg_offset(start) && \ +(addr) <= i915_mmio_reg_offset(end)) total: 0 errors, 0 warnings, 2 checks, 98 lines checked 2fbac0aa101f drm/i915/perf: enable OAR context save/restore of performance counters -:81: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "oa_config" #81: FILE: drivers/gpu/drm/i915/i915_perf.c:1921: + err = gen12_emit_oar_config(rq, ce, oa_config != NULL); -:85: CHECK:BRACES: Blank lines aren't necessary before a close brace '}' #85: FILE: drivers/gpu/drm/i915/i915_perf.c:1925: + + } total: 0 errors, 0 warnings, 2 checks, 61 lines checked e77274f9357c drm/i915/tgl: Add perf support on TGL -:719: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #719: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 771 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/aml: Allow SPT PCH for all AML devices
== Series Details ==
Series: drm/i915/aml: Allow SPT PCH for all AML devices
URL : https://patchwork.freedesktop.org/series/68176/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7125 -> Patchwork_14867
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14867 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14867, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14867:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_execlists:
- fi-icl-u3: NOTRUN -> [DMESG-FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/fi-icl-u3/igt@i915_selftest@live_execlists.html
- fi-skl-6600u: [PASS][2] -> [DMESG-FAIL][3]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-skl-6600u/igt@i915_selftest@live_execlists.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/fi-skl-6600u/igt@i915_selftest@live_execlists.html
Known issues
Here are the changes found in Patchwork_14867 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_mmap_gtt@basic-read-write:
- fi-icl-u3: [PASS][4] -> [DMESG-WARN][5] ([fdo#107724])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u3/igt@gem_mmap_...@basic-read-write.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/fi-icl-u3/igt@gem_mmap_...@basic-read-write.html
Possible fixes
* igt@gem_mmap_gtt@basic-small-bo:
- fi-icl-u3: [DMESG-WARN][6] ([fdo#107724]) -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u3/igt@gem_mmap_...@basic-small-bo.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/fi-icl-u3/igt@gem_mmap_...@basic-small-bo.html
* igt@i915_selftest@live_execlists:
- fi-icl-u2: [INCOMPLETE][8] ([fdo#107713]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u2/igt@i915_selftest@live_execlists.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/fi-icl-u2/igt@i915_selftest@live_execlists.html
- fi-apl-guc: [DMESG-FAIL][10] -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-apl-guc/igt@i915_selftest@live_execlists.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/fi-apl-guc/igt@i915_selftest@live_execlists.html
- fi-skl-6260u: [DMESG-FAIL][12] -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-skl-6260u/igt@i915_selftest@live_execlists.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/fi-skl-6260u/igt@i915_selftest@live_execlists.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u3: [INCOMPLETE][14] ([fdo#107713] / [fdo#108569]) ->
[PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
- {fi-icl-u4}:[INCOMPLETE][16] ([fdo#107713] / [fdo#108569]) ->
[PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-icl-u2: [DMESG-WARN][18] ([fdo#102505] / [fdo#110390]) ->
[PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html
Warnings
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7500u: [DMESG-WARN][20] ([fdo#102505] / [fdo#103558] /
[fdo#105079] / [fdo#105602]) -> [DMESG-FAIL][21] ([fdo#102505] / [fdo#103375] /
[fdo#105079])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#103558]: https://bu
[Intel-gfx] [PATCH v2 2/3] drm/i915/perf: enable OAR context save/restore of performance counters
From: Lionel Landwerlin
We want this so we can preempt performance queries and keep the system
responsive even when long running queries are ongoing. We avoid doing
it for all contexts.
v2: use LRI to modify context control (Chris)
v3: use MASKED_FIELD to program just the masked bits (Chris)
v4: reuse request created during emit_oa_config (Lionel)
Signed-off-by: Lionel Landwerlin
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_lrc.h | 1 +
drivers/gpu/drm/i915/i915_perf.c| 35 -
2 files changed, 35 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.h
b/drivers/gpu/drm/i915/gt/intel_lrc.h
index 99dc576a4e25..b6daac712c9e 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.h
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.h
@@ -43,6 +43,7 @@ struct intel_engine_cs;
#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT (1 << 0)
#define CTX_CTRL_RS_CTX_ENABLE (1 << 1)
#define CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT (1 << 2)
+#define GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE (1 << 8)
#define RING_CONTEXT_STATUS_PTR(base) _MMIO((base) + 0x3a0)
#define RING_EXECLIST_SQ_CONTENTS(base)_MMIO((base) + 0x510)
#define RING_EXECLIST_CONTROL(base)_MMIO((base) + 0x550)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 91707558a0f5..ce97af484a32 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1862,14 +1862,36 @@ get_oa_vma(struct i915_perf_stream *stream, struct
i915_oa_config *oa_config)
return i915_vma_get(oa_bo->vma);
}
+static int gen12_emit_oar_config(struct i915_request *rq,
+struct intel_context *ce,
+bool enable)
+{
+ u32 *cs;
+
+ cs = intel_ring_begin(rq, 4);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
+ *cs++ = MI_LOAD_REGISTER_IMM(1);
+ *cs++ =
i915_mmio_reg_offset(RING_CONTEXT_CONTROL(ce->engine->mmio_base));
+ *cs++ = _MASKED_FIELD(GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE,
+ enable ? GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE : 0);
+ *cs++ = MI_NOOP;
+
+ intel_ring_advance(rq, cs);
+
+ return 0;
+}
+
static int emit_oa_config(struct i915_perf_stream *stream,
struct intel_context *ce)
{
+ struct i915_oa_config *oa_config = stream->oa_config;
struct i915_request *rq;
struct i915_vma *vma;
int err;
- vma = get_oa_vma(stream, stream->oa_config);
+ vma = get_oa_vma(stream, oa_config);
if (IS_ERR(vma))
return PTR_ERR(vma);
@@ -1891,6 +1913,17 @@ static int emit_oa_config(struct i915_perf_stream
*stream,
if (err)
goto err_add_request;
+ /*
+* For Gen12, performance counters are context saved/restored.
+* Only enable it for the context that requested this.
+*/
+ if (ce == stream->pinned_ctx && IS_GEN(stream->perf->i915, 12)) {
+ err = gen12_emit_oar_config(rq, ce, oa_config != NULL);
+ if (err)
+ goto err_add_request;
+
+ }
+
err = rq->engine->emit_bb_start(rq,
vma->node.start, 0,
I915_DISPATCH_SECURE);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH V3 0/7] mdev based hardware virtio offloading support
On Thu, Oct 17, 2019 at 09:42:53AM +0800, Jason Wang wrote: > > On 2019/10/15 下午10:37, Stefan Hajnoczi wrote: > > On Tue, Oct 15, 2019 at 11:37:17AM +0800, Jason Wang wrote: > > > On 2019/10/15 上午1:49, Stefan Hajnoczi wrote: > > > > On Fri, Oct 11, 2019 at 04:15:50PM +0800, Jason Wang wrote: > > > > > There are hardware that can do virtio datapath offloading while having > > > > > its own control path. This path tries to implement a mdev based > > > > > unified API to support using kernel virtio driver to drive those > > > > > devices. This is done by introducing a new mdev transport for virtio > > > > > (virtio_mdev) and register itself as a new kind of mdev driver. Then > > > > > it provides a unified way for kernel virtio driver to talk with mdev > > > > > device implementation. > > > > > > > > > > Though the series only contains kernel driver support, the goal is to > > > > > make the transport generic enough to support userspace drivers. This > > > > > means vhost-mdev[1] could be built on top as well by resuing the > > > > > transport. > > > > > > > > > > A sample driver is also implemented which simulate a virito-net > > > > > loopback ethernet device on top of vringh + workqueue. This could be > > > > > used as a reference implementation for real hardware driver. > > > > > > > > > > Consider mdev framework only support VFIO device and driver right now, > > > > > this series also extend it to support other types. This is done > > > > > through introducing class id to the device and pairing it with > > > > > id_talbe claimed by the driver. On top, this seris also decouple > > > > > device specific parents ops out of the common ones. > > > > I was curious so I took a quick look and posted comments. > > > > > > > > I guess this driver runs inside the guest since it registers virtio > > > > devices? > > > > > > It could run in either guest or host. But the main focus is to run in the > > > host then we can use virtio drivers in containers. > > > > > > > > > > If this is used with physical PCI devices that support datapath > > > > offloading then how are physical devices presented to the guest without > > > > SR-IOV? > > > > > > We will do control path meditation through vhost-mdev[1] and > > > vhost-vfio[2]. > > > Then we will present a full virtio compatible ethernet device for guest. > > > > > > SR-IOV is not a must, any mdev device that implements the API defined in > > > patch 5 can be used by this framework. > > What I'm trying to understand is: if you want to present a virtio-pci > > device to the guest (e.g. using vhost-mdev or vhost-vfio), then how is > > that related to this patch series? > > > This series introduce some infrastructure that would be used by vhost-mdev: > > 1) allow new type of mdev devices/drivers other than vfio (through class_id > and device ops) > > 2) a set of virtio specific callbacks that will be used by both vhost-mdev > and virtio-mdev defined in patch 5 > > Then vhost-mdev can be implemented on top: a new mdev class id but reuse the > callback defined in 2. Through this way the parent can provides a single set > of callbacks (device ops) for both kernel virtio driver (through > virtio-mdev) or userspace virtio driver (through vhost-mdev). Okay, thanks for explaining! Stefan signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 3/3] drm/i915/tgl: Add perf support on TGL
From: Lionel Landwerlin
The design of the OA unit has been split into several units. We now
have a global unit (OAG) and a render specific unit (OAR). This leads
to some changes on how we program things. Some details :
OAR:
- has its own set of counter registers, they are per-context
saved/restored
- counters are not written to the circular OA buffer
- a snapshot of the counters can be acquired with
MI_RECORD_PERF_COUNT, or a single counter can be read with
MI_STORE_REGISTER_MEM.
OAG:
- has global counters that increment across context switches
- counters are written into the circular OA buffer (if requested)
v2: Fix checkpatch warnings on code style (Lucas)
v3: (Umesh)
- Update register from which tail, status and head are read
- Update logic to sample context reports
- Update whitelist mux and b counter regs
v4: Fix a bug when updating context image for new contexts (Umesh)
BSpec: 28727, 30021
Signed-off-by: Lionel Landwerlin
Signed-off-by: Umesh Nerlige Ramappa
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/i915_perf.c | 292 +++---
drivers/gpu/drm/i915/i915_reg.h | 103 +
drivers/gpu/drm/i915/oa/i915_oa_tgl.c | 121 +++
drivers/gpu/drm/i915/oa/i915_oa_tgl.h | 16 ++
5 files changed, 500 insertions(+), 35 deletions(-)
create mode 100644 drivers/gpu/drm/i915/oa/i915_oa_tgl.c
create mode 100644 drivers/gpu/drm/i915/oa/i915_oa_tgl.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index e791d9323b51..0ec9fee58baa 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -242,7 +242,8 @@ i915-y += \
oa/i915_oa_cflgt2.o \
oa/i915_oa_cflgt3.o \
oa/i915_oa_cnl.o \
- oa/i915_oa_icl.o
+ oa/i915_oa_icl.o \
+ oa/i915_oa_tgl.o
i915-y += i915_perf.o
# Post-mortem debug and GPU hang state capture
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index ce97af484a32..3ce7c2607316 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -217,6 +217,7 @@
#include "oa/i915_oa_cflgt3.h"
#include "oa/i915_oa_cnl.h"
#include "oa/i915_oa_icl.h"
+#include "oa/i915_oa_tgl.h"
/* HW requires this to be a power of two, between 128k and 16M, though driver
* is currently generally designed assuming the largest 16M size is used such
@@ -292,7 +293,8 @@ static u32 i915_perf_stream_paranoid = true;
#define INVALID_CTX_ID 0x
/* On Gen8+ automatically triggered OA reports include a 'reason' field... */
-#define OAREPORT_REASON_MASK 0x3f
+#define OAREPORT_REASON_MASK (IS_GEN(stream->perf->i915, 12) ? \
+ 0x7f : 0x3f)
#define OAREPORT_REASON_SHIFT 19
#define OAREPORT_REASON_TIMER (1<<0)
#define OAREPORT_REASON_CTX_SWITCH (1<<3)
@@ -338,6 +340,10 @@ static const struct i915_oa_format
gen8_plus_oa_formats[I915_OA_FORMAT_MAX] = {
[I915_OA_FORMAT_C4_B8] = { 7, 64 },
};
+static const struct i915_oa_format gen12_oa_formats[I915_OA_FORMAT_MAX] = {
+ [I915_OA_FORMAT_A32u40_A4u32_B8_C8] = { 5, 256 },
+};
+
#define SAMPLE_OA_REPORT (1<<0)
/**
@@ -418,6 +424,14 @@ static void free_oa_config_bo(struct i915_oa_config_bo
*oa_bo)
kfree(oa_bo);
}
+static u32 gen12_oa_hw_tail_read(struct i915_perf_stream *stream)
+{
+ struct intel_uncore *uncore = stream->uncore;
+
+ return intel_uncore_read(uncore, GEN12_OAG_OATAILPTR) &
+ GEN12_OAG_OATAILPTR_MASK;
+}
+
static u32 gen8_oa_hw_tail_read(struct i915_perf_stream *stream)
{
struct intel_uncore *uncore = stream->uncore;
@@ -538,7 +552,7 @@ static bool oa_buffer_check_unlocked(struct
i915_perf_stream *stream)
aging_tail = hw_tail;
stream->oa_buffer.aging_timestamp = now;
} else {
- DRM_ERROR("Ignoring spurious out of range OA buffer
tail pointer = %u\n",
+ DRM_ERROR("Ignoring spurious out of range OA buffer
tail pointer = %x\n",
hw_tail);
}
}
@@ -757,7 +771,8 @@ static int gen8_append_oa_reports(struct i915_perf_stream
*stream,
* Note: that we don't clear the valid_ctx_bit so userspace can
* understand that the ID has been squashed by the kernel.
*/
- if (!(report32[0] & stream->perf->gen8_valid_ctx_bit))
+ if (!(report32[0] & stream->perf->gen8_valid_ctx_bit) &&
+ INTEL_GEN(stream->perf->i915) <= 11)
ctx_id = report32[2] = INVALID_CTX_ID;
/*
@@ -824,6 +839,11 @@ static int gen8_append_oa_reports(struct i915_perf_stream
*stream,
}
if (start_offset != *offset) {
+ i915_reg_t oaheadptr
[Intel-gfx] [PATCH v2 1/3] drm/i915/perf: Add helper macros for comparing with whitelisted registers
Add helper macros for range and equality comparisons and use them to
check with whitelisted registers in oa configurations.
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 54 +---
1 file changed, 28 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 54ec1c4190ac..91707558a0f5 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3514,56 +3514,58 @@ static bool gen8_is_valid_flex_addr(struct i915_perf
*perf, u32 addr)
return false;
}
+#define ADDR_IN_RANGE(addr, start, end) \
+ ((addr) >= (start) && \
+(addr) <= (end))
+
+#define REG_IN_RANGE(addr, start, end) \
+ ((addr) >= i915_mmio_reg_offset(start) && \
+(addr) <= i915_mmio_reg_offset(end))
+
+#define REG_EQUAL(addr, mmio) \
+ ((addr) == i915_mmio_reg_offset(mmio))
+
static bool gen7_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
{
- return (addr >= i915_mmio_reg_offset(OASTARTTRIG1) &&
- addr <= i915_mmio_reg_offset(OASTARTTRIG8)) ||
- (addr >= i915_mmio_reg_offset(OAREPORTTRIG1) &&
-addr <= i915_mmio_reg_offset(OAREPORTTRIG8)) ||
- (addr >= i915_mmio_reg_offset(OACEC0_0) &&
-addr <= i915_mmio_reg_offset(OACEC7_1));
+ return REG_IN_RANGE(addr, OASTARTTRIG1, OASTARTTRIG8) ||
+ REG_IN_RANGE(addr, OAREPORTTRIG1, OAREPORTTRIG8) ||
+ REG_IN_RANGE(addr, OACEC0_0, OACEC7_1);
}
static bool gen7_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
{
- return addr == i915_mmio_reg_offset(HALF_SLICE_CHICKEN2) ||
- (addr >= i915_mmio_reg_offset(MICRO_BP0_0) &&
-addr <= i915_mmio_reg_offset(NOA_WRITE)) ||
- (addr >= i915_mmio_reg_offset(OA_PERFCNT1_LO) &&
-addr <= i915_mmio_reg_offset(OA_PERFCNT2_HI)) ||
- (addr >= i915_mmio_reg_offset(OA_PERFMATRIX_LO) &&
-addr <= i915_mmio_reg_offset(OA_PERFMATRIX_HI));
+ return REG_EQUAL(addr, HALF_SLICE_CHICKEN2) ||
+ REG_IN_RANGE(addr, MICRO_BP0_0, NOA_WRITE) ||
+ REG_IN_RANGE(addr, OA_PERFCNT1_LO, OA_PERFCNT2_HI) ||
+ REG_IN_RANGE(addr, OA_PERFMATRIX_LO, OA_PERFMATRIX_HI);
}
static bool gen8_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
{
return gen7_is_valid_mux_addr(perf, addr) ||
- addr == i915_mmio_reg_offset(WAIT_FOR_RC6_EXIT) ||
- (addr >= i915_mmio_reg_offset(RPM_CONFIG0) &&
-addr <= i915_mmio_reg_offset(NOA_CONFIG(8)));
+ REG_EQUAL(addr, WAIT_FOR_RC6_EXIT) ||
+ REG_IN_RANGE(addr, RPM_CONFIG0, NOA_CONFIG(8));
}
static bool gen10_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
{
return gen8_is_valid_mux_addr(perf, addr) ||
- addr == i915_mmio_reg_offset(GEN10_NOA_WRITE_HIGH) ||
- (addr >= i915_mmio_reg_offset(OA_PERFCNT3_LO) &&
-addr <= i915_mmio_reg_offset(OA_PERFCNT4_HI));
+ REG_EQUAL(addr, GEN10_NOA_WRITE_HIGH) ||
+ REG_IN_RANGE(addr, OA_PERFCNT3_LO, OA_PERFCNT4_HI);
}
static bool hsw_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
{
return gen7_is_valid_mux_addr(perf, addr) ||
- (addr >= 0x25100 && addr <= 0x2FF90) ||
- (addr >= i915_mmio_reg_offset(HSW_MBVID2_NOA0) &&
-addr <= i915_mmio_reg_offset(HSW_MBVID2_NOA9)) ||
- addr == i915_mmio_reg_offset(HSW_MBVID2_MISR0);
+ ADDR_IN_RANGE(addr, 0x25100, 0x2FF90) ||
+ REG_IN_RANGE(addr, HSW_MBVID2_NOA0, HSW_MBVID2_NOA9) ||
+ REG_EQUAL(addr, HSW_MBVID2_MISR0);
}
static bool chv_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
{
return gen7_is_valid_mux_addr(perf, addr) ||
- (addr >= 0x182300 && addr <= 0x1823A4);
+ ADDR_IN_RANGE(addr, 0x182300, 0x1823A4);
}
static u32 mask_reg_value(u32 reg, u32 val)
@@ -3572,14 +3574,14 @@ static u32 mask_reg_value(u32 reg, u32 val)
* WaDisableSTUnitPowerOptimization workaround. Make sure the value
* programmed by userspace doesn't change this.
*/
- if (i915_mmio_reg_offset(HALF_SLICE_CHICKEN2) == reg)
+ if (REG_EQUAL(reg, HALF_SLICE_CHICKEN2))
val = val & ~_MASKED_BIT_ENABLE(GEN8_ST_PO_DISABLE);
/* WAIT_FOR_RC6_EXIT has only one bit fullfilling the function
* indicated by its name and a bunch of selection fields used by OA
* configs.
*/
- if (i915_mmio_reg_offset(WAIT_FOR_RC6_EXIT) == reg)
+ if (REG_EQUAL(reg, WAIT_FOR_RC6_EXIT))
val = val & ~_MASKED_BIT_ENABLE(HSW_WAIT_FOR_RC6_EXIT_ENABLE);
return val;
--
2.20.1
___
Intel-gfx mailin
Re: [Intel-gfx] [PATCH V3 4/7] mdev: introduce device specific ops
> -Original Message-
> From: Alex Williamson
> Sent: Wednesday, October 16, 2019 5:38 PM
> To: Parav Pandit
> Cc: Cornelia Huck ; Jason Wang
> ; k...@vger.kernel.org; linux-s...@vger.kernel.org;
> linux-ker...@vger.kernel.org; dri-de...@lists.freedesktop.org; intel-
> g...@lists.freedesktop.org; intel-gvt-...@lists.freedesktop.org;
> kwankh...@nvidia.com; m...@redhat.com; tiwei@intel.com;
> virtualizat...@lists.linux-foundation.org; net...@vger.kernel.org;
> maxime.coque...@redhat.com; cunming.li...@intel.com;
> zhihong.w...@intel.com; rob.mil...@broadcom.com; xiao.w.w...@intel.com;
> haotian.w...@sifive.com; zhen...@linux.intel.com; zhi.a.w...@intel.com;
> jani.nik...@linux.intel.com; joonas.lahti...@linux.intel.com;
> rodrigo.v...@intel.com; airl...@linux.ie; dan...@ffwll.ch;
> far...@linux.ibm.com; pa...@linux.ibm.com; seb...@linux.ibm.com;
> ober...@linux.ibm.com; heiko.carst...@de.ibm.com; g...@linux.ibm.com;
> borntrae...@de.ibm.com; akrow...@linux.ibm.com; fre...@linux.ibm.com;
> lingshan@intel.com; Ido Shamay ;
> epere...@redhat.com; l...@redhat.com; christophe.de.dinec...@gmail.com;
> kevin.t...@intel.com
> Subject: Re: [PATCH V3 4/7] mdev: introduce device specific ops
>
> On Wed, 16 Oct 2019 20:48:06 +
> Parav Pandit wrote:
>
> > > From: Alex Williamson On Wed, 16 Oct
> > > 2019 15:31:25 + Parav Pandit wrote:
> > > > > From: Cornelia Huck Parav Pandit
> > > > > wrote:
> > > > > > > From: Alex Williamson On Tue,
> > > > > > > 15 Oct 2019 20:17:01 +0800 Jason Wang
> > > > > > > wrote:
> > > > > > >
> > > > > > > > On 2019/10/15 下午6:41, Cornelia Huck wrote:
> > > > > > > > > Apologies if that has already been discussed, but do we
> > > > > > > > > want a
> > > > > > > > > 1:1 relationship between id and ops, or can different
> > > > > > > > > devices with the same id register different ops?
> > > > > > > >
> > > > > > > >
> > > > > > > > I think we have a N:1 mapping between id and ops, e.g we
> > > > > > > > want both virtio-mdev and vhost-mdev use a single set of device
> ops.
> > > > > > >
> > > > > > > The contents of the ops structure is essentially defined by
> > > > > > > the id, which is why I was leaning towards them being defined
> together.
> > > > > > > They are effectively interlocked, the id defines which mdev
> "endpoint"
> > > > > > > driver is loaded and that driver requires mdev_get_dev_ops()
> > > > > > > to return the structure required by the driver. I wish
> > > > > > > there was a way we could incorporate type checking here. We
> > > > > > > toyed with the idea of having the class in the same
> > > > > > > structure as the ops, but I think this approach was chosen
> > > > > > > for simplicity. We could still do
> > > something like:
> > > > > > >
> > > > > > > int mdev_set_class_struct(struct device *dev, const struct
> > > > > > > mdev_class_struct *class);
> > > > > > >
> > > > > > > struct mdev_class_struct {
> > > > > > > u16 id;
> > > > > > > union {
> > > > > > > struct vfio_mdev_ops vfio_ops;
> > > > > > > struct virtio_mdev_ops virtio_ops;
> > > > > > > };
> > > > > > > };
> > > > > > >
> > > > > > > Maybe even:
> > > > > > >
> > > > > > > struct vfio_mdev_ops *mdev_get_vfio_ops(struct mdev_device
> > > > > > > *mdev)
> > > {
> > > > > > > BUG_ON(mdev->class.id != MDEV_ID_VFIO);
> > > > > > > return &mdev->class.vfio_ops; }
> > > > > > >
> > > > > > > The match callback would of course just use the mdev->class.id
> value.
> > > > > > > Functionally equivalent, but maybe better type characteristics.
> > > > > > > Thanks,
> > > > > > >
> > > > > > > Alex
> > > > > >
> > > > > > We have 3 use cases of mdev.
> > > > > > 1. current mdev binding to vfio_mdev 2. mdev binding to virtio 3.
> > > > > > mdev binding to mlx5_core without dev_ops
> > > > > >
> > > > > > Also
> > > > > > (a) a given parent may serve multiple types of classes in future.
> > > > > > (b) number of classes may not likely explode, they will be
> > > > > > handful of them. (vfio_mdev, virtio)
> > > > > >
> > > > > > So, instead of making copies of this dev_ops pointer in each
> > > > > > mdev, it is better
> > > > > to keep const multiple ops in their parent device.
> > > > > > Something like below,
> > > > > >
> > > > > > struct mdev_parent {
> > > > > > [..]
> > > > > > struct mdev_parent_ops *parent_ops; /* create, remove */
> > > > > > struct vfio_mdev_ops *vfio_ops; /* read,write, ioctl etc */
> > > > > > struct virtio_mdev_ops *virtio_ops; /* virtio ops */ };
> > > > >
> > > > > That feels a bit odd. Why should the parent carry pointers to
> > > > > every possible version of ops?
> > > > >
> > > > How many are we expecting? I envisioned handful of them.
> > > > It carries because parent is few, mdevs are several hundreds.
> > > > It makes sense to keep few copies, instead of several hundred
> > > > copies and it doesn't need to setup on every mdev creation.
> > >
> > > It does need setup on every mdev creation
Re: [Intel-gfx] [PATCH V3 4/7] mdev: introduce device specific ops
> -Original Message- > From: Alex Williamson > Sent: Wednesday, October 16, 2019 11:53 AM > To: Parav Pandit > Cc: Cornelia Huck ; Jason Wang > ; k...@vger.kernel.org; linux-s...@vger.kernel.org; > linux-ker...@vger.kernel.org; dri-de...@lists.freedesktop.org; intel- > g...@lists.freedesktop.org; intel-gvt-...@lists.freedesktop.org; > kwankh...@nvidia.com; m...@redhat.com; tiwei@intel.com; > virtualizat...@lists.linux-foundation.org; net...@vger.kernel.org; > maxime.coque...@redhat.com; cunming.li...@intel.com; > zhihong.w...@intel.com; rob.mil...@broadcom.com; xiao.w.w...@intel.com; > haotian.w...@sifive.com; zhen...@linux.intel.com; zhi.a.w...@intel.com; > jani.nik...@linux.intel.com; joonas.lahti...@linux.intel.com; > rodrigo.v...@intel.com; airl...@linux.ie; dan...@ffwll.ch; > far...@linux.ibm.com; pa...@linux.ibm.com; seb...@linux.ibm.com; > ober...@linux.ibm.com; heiko.carst...@de.ibm.com; g...@linux.ibm.com; > borntrae...@de.ibm.com; akrow...@linux.ibm.com; fre...@linux.ibm.com; > lingshan@intel.com; Ido Shamay ; > epere...@redhat.com; l...@redhat.com; christophe.de.dinec...@gmail.com; > kevin.t...@intel.com > Subject: Re: [PATCH V3 4/7] mdev: introduce device specific ops > > On Wed, 16 Oct 2019 15:31:25 + > Parav Pandit wrote: > > > > -Original Message- > > > From: Cornelia Huck > > > Sent: Wednesday, October 16, 2019 3:53 AM > > > To: Parav Pandit > > > Cc: Alex Williamson ; Jason Wang > > > ; k...@vger.kernel.org; > > > linux-s...@vger.kernel.org; linux-ker...@vger.kernel.org; > > > dri-de...@lists.freedesktop.org; intel- g...@lists.freedesktop.org; > > > intel-gvt-...@lists.freedesktop.org; > > > kwankh...@nvidia.com; m...@redhat.com; tiwei@intel.com; > > > virtualizat...@lists.linux-foundation.org; net...@vger.kernel.org; > > > maxime.coque...@redhat.com; cunming.li...@intel.com; > > > zhihong.w...@intel.com; rob.mil...@broadcom.com; > > > xiao.w.w...@intel.com; haotian.w...@sifive.com; > > > zhen...@linux.intel.com; zhi.a.w...@intel.com; > > > jani.nik...@linux.intel.com; joonas.lahti...@linux.intel.com; > > > rodrigo.v...@intel.com; airl...@linux.ie; dan...@ffwll.ch; > > > far...@linux.ibm.com; pa...@linux.ibm.com; seb...@linux.ibm.com; > > > ober...@linux.ibm.com; heiko.carst...@de.ibm.com; g...@linux.ibm.com; > > > borntrae...@de.ibm.com; akrow...@linux.ibm.com; > > > fre...@linux.ibm.com; lingshan@intel.com; Ido Shamay > > > ; epere...@redhat.com; l...@redhat.com; > > > christophe.de.dinec...@gmail.com; kevin.t...@intel.com > > > Subject: Re: [PATCH V3 4/7] mdev: introduce device specific ops > > > > > > On Wed, 16 Oct 2019 05:50:08 + > > > Parav Pandit wrote: > > > > > > > Hi Alex, > > > > > > > > > -Original Message- > > > > > From: Alex Williamson > > > > > Sent: Tuesday, October 15, 2019 12:27 PM > > > > > To: Jason Wang > > > > > Cc: Cornelia Huck ; k...@vger.kernel.org; > > > > > linux- s...@vger.kernel.org; linux-ker...@vger.kernel.org; dri- > > > > > de...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; > > > > > intel-gvt- d...@lists.freedesktop.org; kwankh...@nvidia.com; > > > > > m...@redhat.com; tiwei@intel.com; > > > > > virtualizat...@lists.linux-foundation.org; > > > > > net...@vger.kernel.org; maxime.coque...@redhat.com; > > > > > cunming.li...@intel.com; zhihong.w...@intel.com; > > > > > rob.mil...@broadcom.com; xiao.w.w...@intel.com; > > > > > haotian.w...@sifive.com; zhen...@linux.intel.com; > > > > > zhi.a.w...@intel.com; jani.nik...@linux.intel.com; > > > > > joonas.lahti...@linux.intel.com; rodrigo.v...@intel.com; > > > > > airl...@linux.ie; dan...@ffwll.ch; far...@linux.ibm.com; > > > > > pa...@linux.ibm.com; seb...@linux.ibm.com; > > > > > ober...@linux.ibm.com; heiko.carst...@de.ibm.com; > > > > > g...@linux.ibm.com; borntrae...@de.ibm.com; > > > > > akrow...@linux.ibm.com; fre...@linux.ibm.com; > > > > > lingshan@intel.com; Ido Shamay ; > > > > > epere...@redhat.com; l...@redhat.com; Parav Pandit > > > > > ; christophe.de.dinec...@gmail.com; > > > > > kevin.t...@intel.com > > > > > Subject: Re: [PATCH V3 4/7] mdev: introduce device specific ops > > > > > > > > > > On Tue, 15 Oct 2019 20:17:01 +0800 Jason Wang > > > > > wrote: > > > > > > > > > > > On 2019/10/15 下午6:41, Cornelia Huck wrote: > > > > > > > On Fri, 11 Oct 2019 16:15:54 +0800 Jason Wang > > > > > > > wrote: > > > > > > > > > >> @@ -167,9 +176,10 @@ register itself with the mdev core driver:: > > > > > > >> extern int mdev_register_device(struct device *dev, > > > > > > >> const struct > > > > > > >> mdev_parent_ops *ops); > > > > > > >> > > > > > > >> -It is also required to specify the class_id through:: > > > > > > >> +It is also required to specify the class_id and device > > > > > > >> +specific ops > > > > > through:: > > > > > > >> > > > > > > >> -extern int mdev_set_class(struct device *dev, u16 id); > > > > > > >> +extern int mdev_set_class(struct de
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Do not end i915 batch buffers prematurely
== Series Details ==
Series: drm/i915: Do not end i915 batch buffers prematurely
URL : https://patchwork.freedesktop.org/series/68175/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7125 -> Patchwork_14866
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14866 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14866, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14866/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14866:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-8109u: [PASS][1] -> [DMESG-FAIL][2] +1 similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14866/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
Known issues
Here are the changes found in Patchwork_14866 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_switch@rcs0:
- fi-apl-guc: [PASS][3] -> [INCOMPLETE][4] ([fdo#103927])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-apl-guc/igt@gem_ctx_swi...@rcs0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14866/fi-apl-guc/igt@gem_ctx_swi...@rcs0.html
* igt@kms_addfb_basic@too-high:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724]) +1
similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u3/igt@kms_addfb_ba...@too-high.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14866/fi-icl-u3/igt@kms_addfb_ba...@too-high.html
Possible fixes
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8] +1
similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14866/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
* igt@i915_selftest@live_execlists:
- fi-icl-u2: [INCOMPLETE][9] ([fdo#107713]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u2/igt@i915_selftest@live_execlists.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14866/fi-icl-u2/igt@i915_selftest@live_execlists.html
- {fi-icl-dsi}: [DMESG-FAIL][11] -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-dsi/igt@i915_selftest@live_execlists.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14866/fi-icl-dsi/igt@i915_selftest@live_execlists.html
- fi-skl-6260u: [DMESG-FAIL][13] -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-skl-6260u/igt@i915_selftest@live_execlists.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14866/fi-skl-6260u/igt@i915_selftest@live_execlists.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u3: [INCOMPLETE][15] ([fdo#107713] / [fdo#108569]) ->
[PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14866/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][17] ([fdo#111407]) -> [FAIL][18] ([fdo#111045]
/ [fdo#111096])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14866/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
Participating hosts (53 -> 46)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
*
[Intel-gfx] [RESEND PATCH 2/2] drm/i915/guc: Update H2G enable logging action definition
GuC enable logging H2G action definition changed some time ago from 0xE000
to 0x40. All current GuC FW blobs use this definition, so fix the action
definition in driver to match.
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Signed-off-by: Robert M. Fosha
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index 1d3cdd67ca2f..a26a85d50209 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -548,6 +548,7 @@ enum intel_guc_action {
INTEL_GUC_ACTION_ALLOCATE_DOORBELL = 0x10,
INTEL_GUC_ACTION_DEALLOCATE_DOORBELL = 0x20,
INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE = 0x30,
+ INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x40,
INTEL_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH = 0x302,
INTEL_GUC_ACTION_ENTER_S_STATE = 0x501,
INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
@@ -556,7 +557,6 @@ enum intel_guc_action {
INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505,
INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 0x4506,
- INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
INTEL_GUC_ACTION_LIMIT
};
--
2.21.0.5.gaeb582a983
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RESEND PATCH 1/2] drm/i915/guc: Enable guc logging on guc log relay write
Creating and opening the GuC log relay file enables and starts
the relay potentially before the caller is ready to consume logs.
Change the behavior so that relay starts only on an explicit call
to the write function (with a value of '1'). Other values flush
the log relay as before.
v2: Style changes and fix typos. Add guc_log_relay_stop()
function. (Daniele)
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Signed-off-by: Robert M. Fosha
Reviewed-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 53 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_log.h | 4 +-
drivers/gpu/drm/i915/i915_debugfs.c| 22 +++--
3 files changed, 62 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
index 2cf2d3314f62..caed0d57e704 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
@@ -226,7 +226,7 @@ static void guc_read_update_log_buffer(struct intel_guc_log
*log)
mutex_lock(&log->relay.lock);
- if (WARN_ON(!intel_guc_log_relay_enabled(log)))
+ if (WARN_ON(!intel_guc_log_relay_created(log)))
goto out_unlock;
/* Get the pointer to shared GuC log buffer */
@@ -361,6 +361,7 @@ void intel_guc_log_init_early(struct intel_guc_log *log)
{
mutex_init(&log->relay.lock);
INIT_WORK(&log->relay.flush_work, capture_logs_work);
+ log->relay.started = false;
}
static int guc_log_relay_create(struct intel_guc_log *log)
@@ -546,7 +547,7 @@ int intel_guc_log_set_level(struct intel_guc_log *log, u32
level)
return ret;
}
-bool intel_guc_log_relay_enabled(const struct intel_guc_log *log)
+bool intel_guc_log_relay_created(const struct intel_guc_log *log)
{
return log->relay.buf_addr;
}
@@ -560,7 +561,7 @@ int intel_guc_log_relay_open(struct intel_guc_log *log)
mutex_lock(&log->relay.lock);
- if (intel_guc_log_relay_enabled(log)) {
+ if (intel_guc_log_relay_created(log)) {
ret = -EEXIST;
goto out_unlock;
}
@@ -585,6 +586,21 @@ int intel_guc_log_relay_open(struct intel_guc_log *log)
mutex_unlock(&log->relay.lock);
+ return 0;
+
+out_relay:
+ guc_log_relay_destroy(log);
+out_unlock:
+ mutex_unlock(&log->relay.lock);
+
+ return ret;
+}
+
+int intel_guc_log_relay_start(struct intel_guc_log *log)
+{
+ if (log->relay.started)
+ return -EEXIST;
+
guc_log_enable_flush_events(log);
/*
@@ -594,14 +610,9 @@ int intel_guc_log_relay_open(struct intel_guc_log *log)
*/
queue_work(system_highpri_wq, &log->relay.flush_work);
- return 0;
-
-out_relay:
- guc_log_relay_destroy(log);
-out_unlock:
- mutex_unlock(&log->relay.lock);
+ log->relay.started = true;
- return ret;
+ return 0;
}
void intel_guc_log_relay_flush(struct intel_guc_log *log)
@@ -609,6 +620,9 @@ void intel_guc_log_relay_flush(struct intel_guc_log *log)
struct intel_guc *guc = log_to_guc(log);
intel_wakeref_t wakeref;
+ if (!log->relay.started)
+ return;
+
/*
* Before initiating the forceful flush, wait for any pending/ongoing
* flush to complete otherwise forceful flush may not actually happen.
@@ -622,18 +636,33 @@ void intel_guc_log_relay_flush(struct intel_guc_log *log)
guc_log_capture_logs(log);
}
-void intel_guc_log_relay_close(struct intel_guc_log *log)
+/*
+ * Stops the relay log. Called from intel_guc_log_relay_close(), so no
+ * possibility of race with start/flush since relay_write cannot race
+ * relay_close.
+ */
+static void guc_log_relay_stop(struct intel_guc_log *log)
{
struct intel_guc *guc = log_to_guc(log);
struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
+ if (!log->relay.started)
+ return;
+
guc_log_disable_flush_events(log);
intel_synchronize_irq(i915);
flush_work(&log->relay.flush_work);
+ log->relay.started = false;
+}
+
+void intel_guc_log_relay_close(struct intel_guc_log *log)
+{
+ guc_log_relay_stop(log);
+
mutex_lock(&log->relay.lock);
- GEM_BUG_ON(!intel_guc_log_relay_enabled(log));
+ GEM_BUG_ON(!intel_guc_log_relay_created(log));
guc_log_unmap(log);
guc_log_relay_destroy(log);
mutex_unlock(&log->relay.lock);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.h
index 6f764879acb1..c252c022c5fc 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.h
@@ -47,6 +47,7 @@ struct intel_guc_log {
struct i915_vma *vma;
struct {
void *buf_addr;
+ bool started;
struct work_struct flush_work;
struct rchan *channel;
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/4] drm/i915: Add memory region information to device_info
== Series Details ==
Series: series starting with [1/4] drm/i915: Add memory region information to
device_info
URL : https://patchwork.freedesktop.org/series/68171/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7124 -> Patchwork_14865
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14865 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14865, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14865/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14865:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_execlists:
- fi-kbl-x1275: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7124/fi-kbl-x1275/igt@i915_selftest@live_execlists.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14865/fi-kbl-x1275/igt@i915_selftest@live_execlists.html
- fi-bxt-dsi: NOTRUN -> [DMESG-FAIL][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14865/fi-bxt-dsi/igt@i915_selftest@live_execlists.html
- fi-skl-6260u: [PASS][4] -> [DMESG-FAIL][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7124/fi-skl-6260u/igt@i915_selftest@live_execlists.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14865/fi-skl-6260u/igt@i915_selftest@live_execlists.html
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-8109u: [PASS][6] -> [DMESG-FAIL][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7124/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14865/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
Known issues
Here are the changes found in Patchwork_14865 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_mmap_gtt@basic-write-no-prefault:
- fi-icl-u3: [PASS][8] -> [DMESG-WARN][9] ([fdo#107724]) +1
similar issue
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7124/fi-icl-u3/igt@gem_mmap_...@basic-write-no-prefault.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14865/fi-icl-u3/igt@gem_mmap_...@basic-write-no-prefault.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][10] -> [FAIL][11] ([fdo#111407])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7124/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14865/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
Possible fixes
* igt@gem_mmap@basic:
- fi-icl-u3: [DMESG-WARN][12] ([fdo#107724]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7124/fi-icl-u3/igt@gem_m...@basic.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14865/fi-icl-u3/igt@gem_m...@basic.html
* igt@i915_selftest@live_execlists:
- {fi-icl-guc}: [DMESG-FAIL][14] -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7124/fi-icl-guc/igt@i915_selftest@live_execlists.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14865/fi-icl-guc/igt@i915_selftest@live_execlists.html
- fi-skl-6770hq: [DMESG-FAIL][16] -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7124/fi-skl-6770hq/igt@i915_selftest@live_execlists.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14865/fi-skl-6770hq/igt@i915_selftest@live_execlists.html
- fi-cfl-8109u: [DMESG-FAIL][18] -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7124/fi-cfl-8109u/igt@i915_selftest@live_execlists.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14865/fi-cfl-8109u/igt@i915_selftest@live_execlists.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u2: [INCOMPLETE][20] ([fdo#107713] / [fdo#108569]) ->
[PASS][21]
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7124/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14865/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
* igt@kms_busy@basic-flip-a:
- {fi-tgl-u2}:[DMESG-WARN][22] ([fdo#111600]) -> [PASS][23]
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7124/fi-tgl-u2/igt@kms_b...@basic-flip-a.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14865/fi-tgl-u2/igt@kms_b...@basic-flip-a.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/sho
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/execlists: Don't merely skip submission if maybe timeslicing (rev5)
== Series Details ==
Series: drm/i915/execlists: Don't merely skip submission if maybe timeslicing
(rev5)
URL : https://patchwork.freedesktop.org/series/68122/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7124 -> Patchwork_14864
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14864 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14864, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14864/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14864:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_coherency:
- fi-cfl-8109u: [PASS][1] -> [TIMEOUT][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7124/fi-cfl-8109u/igt@i915_selftest@live_coherency.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14864/fi-cfl-8109u/igt@i915_selftest@live_coherency.html
* igt@i915_selftest@live_execlists:
- fi-kbl-guc: [PASS][3] -> [DMESG-FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7124/fi-kbl-guc/igt@i915_selftest@live_execlists.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14864/fi-kbl-guc/igt@i915_selftest@live_execlists.html
* igt@runner@aborted:
- fi-cfl-8109u: NOTRUN -> [FAIL][5]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14864/fi-cfl-8109u/igt@run...@aborted.html
Known issues
Here are the changes found in Patchwork_14864 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_mmap_gtt@basic-copy:
- fi-icl-u3: [PASS][6] -> [DMESG-WARN][7] ([fdo#107724]) +1
similar issue
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7124/fi-icl-u3/igt@gem_mmap_...@basic-copy.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14864/fi-icl-u3/igt@gem_mmap_...@basic-copy.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-icl-u2: [PASS][8] -> [FAIL][9] ([fdo#109635 ])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7124/fi-icl-u2/igt@kms_chamel...@hdmi-crc-fast.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14864/fi-icl-u2/igt@kms_chamel...@hdmi-crc-fast.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][10] -> [FAIL][11] ([fdo#111045] / [fdo#111096])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7124/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14864/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
Possible fixes
* igt@gem_mmap@basic:
- fi-icl-u3: [DMESG-WARN][12] ([fdo#107724]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7124/fi-icl-u3/igt@gem_m...@basic.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14864/fi-icl-u3/igt@gem_m...@basic.html
* igt@i915_selftest@live_execlists:
- {fi-icl-guc}: [DMESG-FAIL][14] -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7124/fi-icl-guc/igt@i915_selftest@live_execlists.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14864/fi-icl-guc/igt@i915_selftest@live_execlists.html
- fi-skl-6770hq: [DMESG-FAIL][16] -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7124/fi-skl-6770hq/igt@i915_selftest@live_execlists.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14864/fi-skl-6770hq/igt@i915_selftest@live_execlists.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u2: [INCOMPLETE][18] ([fdo#107713] / [fdo#108569]) ->
[PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7124/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14864/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
Participating hosts (53 -> 44)
--
Missing(9): fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-byt-squawks
fi-bsw-cyan fi-icl-y fi-blb-e6850 fi
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915: Add memory region information to device_info
== Series Details == Series: series starting with [1/4] drm/i915: Add memory region information to device_info URL : https://patchwork.freedesktop.org/series/68171/ State : warning == Summary == $ dim checkpatch origin/drm-tip 3b8fea96a159 drm/i915: Add memory region information to device_info 0d21626545cb drm/i915: enumerate and init each supported region 01e2151dde9b drm/i915: treat shmem as a region -:413: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #413: FILE: drivers/gpu/drm/i915/intel_memory_region.c:10: +#define REGION_MAP(type, inst) \ + BIT((type) + INTEL_MEMORY_TYPE_SHIFT) | BIT(inst) total: 1 errors, 0 warnings, 0 checks, 417 lines checked a8d8adbbdef4 drm/i915: treat stolen as a region ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 2/3] drm/i915/perf: enable OAR context save/restore of performance counters
From: Lionel Landwerlin
We want this so we can preempt performance queries and keep the system
responsive even when long running queries are ongoing. We avoid doing
it for all contexts.
v2: use LRI to modify context control (Chris)
v3: use MASKED_FIELD to program just the masked bits (Chris)
v4: reuse request created during emit_oa_config (Lionel)
Signed-off-by: Lionel Landwerlin
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_lrc.h | 1 +
drivers/gpu/drm/i915/i915_perf.c| 35 -
2 files changed, 35 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.h
b/drivers/gpu/drm/i915/gt/intel_lrc.h
index 99dc576a4e25..b6daac712c9e 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.h
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.h
@@ -43,6 +43,7 @@ struct intel_engine_cs;
#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT (1 << 0)
#define CTX_CTRL_RS_CTX_ENABLE (1 << 1)
#define CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT (1 << 2)
+#define GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE (1 << 8)
#define RING_CONTEXT_STATUS_PTR(base) _MMIO((base) + 0x3a0)
#define RING_EXECLIST_SQ_CONTENTS(base)_MMIO((base) + 0x510)
#define RING_EXECLIST_CONTROL(base)_MMIO((base) + 0x550)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 91707558a0f5..ce97af484a32 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1862,14 +1862,36 @@ get_oa_vma(struct i915_perf_stream *stream, struct
i915_oa_config *oa_config)
return i915_vma_get(oa_bo->vma);
}
+static int gen12_emit_oar_config(struct i915_request *rq,
+struct intel_context *ce,
+bool enable)
+{
+ u32 *cs;
+
+ cs = intel_ring_begin(rq, 4);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
+ *cs++ = MI_LOAD_REGISTER_IMM(1);
+ *cs++ =
i915_mmio_reg_offset(RING_CONTEXT_CONTROL(ce->engine->mmio_base));
+ *cs++ = _MASKED_FIELD(GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE,
+ enable ? GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE : 0);
+ *cs++ = MI_NOOP;
+
+ intel_ring_advance(rq, cs);
+
+ return 0;
+}
+
static int emit_oa_config(struct i915_perf_stream *stream,
struct intel_context *ce)
{
+ struct i915_oa_config *oa_config = stream->oa_config;
struct i915_request *rq;
struct i915_vma *vma;
int err;
- vma = get_oa_vma(stream, stream->oa_config);
+ vma = get_oa_vma(stream, oa_config);
if (IS_ERR(vma))
return PTR_ERR(vma);
@@ -1891,6 +1913,17 @@ static int emit_oa_config(struct i915_perf_stream
*stream,
if (err)
goto err_add_request;
+ /*
+* For Gen12, performance counters are context saved/restored.
+* Only enable it for the context that requested this.
+*/
+ if (ce == stream->pinned_ctx && IS_GEN(stream->perf->i915, 12)) {
+ err = gen12_emit_oar_config(rq, ce, oa_config != NULL);
+ if (err)
+ goto err_add_request;
+
+ }
+
err = rq->engine->emit_bb_start(rq,
vma->node.start, 0,
I915_DISPATCH_SECURE);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 1/3] drm/i915/perf: Add helper macros for comparing with whitelisted registers
Add helper macros for range and equality comparisons and use them to
check with whitelisted registers in oa configurations.
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 54 +---
1 file changed, 28 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 54ec1c4190ac..91707558a0f5 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3514,56 +3514,58 @@ static bool gen8_is_valid_flex_addr(struct i915_perf
*perf, u32 addr)
return false;
}
+#define ADDR_IN_RANGE(addr, start, end) \
+ ((addr) >= (start) && \
+(addr) <= (end))
+
+#define REG_IN_RANGE(addr, start, end) \
+ ((addr) >= i915_mmio_reg_offset(start) && \
+(addr) <= i915_mmio_reg_offset(end))
+
+#define REG_EQUAL(addr, mmio) \
+ ((addr) == i915_mmio_reg_offset(mmio))
+
static bool gen7_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
{
- return (addr >= i915_mmio_reg_offset(OASTARTTRIG1) &&
- addr <= i915_mmio_reg_offset(OASTARTTRIG8)) ||
- (addr >= i915_mmio_reg_offset(OAREPORTTRIG1) &&
-addr <= i915_mmio_reg_offset(OAREPORTTRIG8)) ||
- (addr >= i915_mmio_reg_offset(OACEC0_0) &&
-addr <= i915_mmio_reg_offset(OACEC7_1));
+ return REG_IN_RANGE(addr, OASTARTTRIG1, OASTARTTRIG8) ||
+ REG_IN_RANGE(addr, OAREPORTTRIG1, OAREPORTTRIG8) ||
+ REG_IN_RANGE(addr, OACEC0_0, OACEC7_1);
}
static bool gen7_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
{
- return addr == i915_mmio_reg_offset(HALF_SLICE_CHICKEN2) ||
- (addr >= i915_mmio_reg_offset(MICRO_BP0_0) &&
-addr <= i915_mmio_reg_offset(NOA_WRITE)) ||
- (addr >= i915_mmio_reg_offset(OA_PERFCNT1_LO) &&
-addr <= i915_mmio_reg_offset(OA_PERFCNT2_HI)) ||
- (addr >= i915_mmio_reg_offset(OA_PERFMATRIX_LO) &&
-addr <= i915_mmio_reg_offset(OA_PERFMATRIX_HI));
+ return REG_EQUAL(addr, HALF_SLICE_CHICKEN2) ||
+ REG_IN_RANGE(addr, MICRO_BP0_0, NOA_WRITE) ||
+ REG_IN_RANGE(addr, OA_PERFCNT1_LO, OA_PERFCNT2_HI) ||
+ REG_IN_RANGE(addr, OA_PERFMATRIX_LO, OA_PERFMATRIX_HI);
}
static bool gen8_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
{
return gen7_is_valid_mux_addr(perf, addr) ||
- addr == i915_mmio_reg_offset(WAIT_FOR_RC6_EXIT) ||
- (addr >= i915_mmio_reg_offset(RPM_CONFIG0) &&
-addr <= i915_mmio_reg_offset(NOA_CONFIG(8)));
+ REG_EQUAL(addr, WAIT_FOR_RC6_EXIT) ||
+ REG_IN_RANGE(addr, RPM_CONFIG0, NOA_CONFIG(8));
}
static bool gen10_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
{
return gen8_is_valid_mux_addr(perf, addr) ||
- addr == i915_mmio_reg_offset(GEN10_NOA_WRITE_HIGH) ||
- (addr >= i915_mmio_reg_offset(OA_PERFCNT3_LO) &&
-addr <= i915_mmio_reg_offset(OA_PERFCNT4_HI));
+ REG_EQUAL(addr, GEN10_NOA_WRITE_HIGH) ||
+ REG_IN_RANGE(addr, OA_PERFCNT3_LO, OA_PERFCNT4_HI);
}
static bool hsw_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
{
return gen7_is_valid_mux_addr(perf, addr) ||
- (addr >= 0x25100 && addr <= 0x2FF90) ||
- (addr >= i915_mmio_reg_offset(HSW_MBVID2_NOA0) &&
-addr <= i915_mmio_reg_offset(HSW_MBVID2_NOA9)) ||
- addr == i915_mmio_reg_offset(HSW_MBVID2_MISR0);
+ ADDR_IN_RANGE(addr, 0x25100, 0x2FF90) ||
+ REG_IN_RANGE(addr, HSW_MBVID2_NOA0, HSW_MBVID2_NOA9) ||
+ REG_EQUAL(addr, HSW_MBVID2_MISR0);
}
static bool chv_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
{
return gen7_is_valid_mux_addr(perf, addr) ||
- (addr >= 0x182300 && addr <= 0x1823A4);
+ ADDR_IN_RANGE(addr, 0x182300, 0x1823A4);
}
static u32 mask_reg_value(u32 reg, u32 val)
@@ -3572,14 +3574,14 @@ static u32 mask_reg_value(u32 reg, u32 val)
* WaDisableSTUnitPowerOptimization workaround. Make sure the value
* programmed by userspace doesn't change this.
*/
- if (i915_mmio_reg_offset(HALF_SLICE_CHICKEN2) == reg)
+ if (REG_EQUAL(reg, HALF_SLICE_CHICKEN2))
val = val & ~_MASKED_BIT_ENABLE(GEN8_ST_PO_DISABLE);
/* WAIT_FOR_RC6_EXIT has only one bit fullfilling the function
* indicated by its name and a bunch of selection fields used by OA
* configs.
*/
- if (i915_mmio_reg_offset(WAIT_FOR_RC6_EXIT) == reg)
+ if (REG_EQUAL(reg, WAIT_FOR_RC6_EXIT))
val = val & ~_MASKED_BIT_ENABLE(HSW_WAIT_FOR_RC6_EXIT_ENABLE);
return val;
--
2.20.1
___
Intel-gfx mailin
[Intel-gfx] [PATCH v2 3/3] drm/i915/tgl: Add perf support on TGL
From: Lionel Landwerlin
The design of the OA unit has been split into several units. We now
have a global unit (OAG) and a render specific unit (OAR). This leads
to some changes on how we program things. Some details :
OAR:
- has its own set of counter registers, they are per-context
saved/restored
- counters are not written to the circular OA buffer
- a snapshot of the counters can be acquired with
MI_RECORD_PERF_COUNT, or a single counter can be read with
MI_STORE_REGISTER_MEM.
OAG:
- has global counters that increment across context switches
- counters are written into the circular OA buffer (if requested)
v2: Fix checkpatch warnings on code style (Lucas)
v3: (Umesh)
- Update register from which tail, status and head are read
- Update logic to sample context reports
- Update whitelist mux and b counter regs
BSpec: 28727, 30021
Signed-off-by: Lionel Landwerlin
Signed-off-by: Umesh Nerlige Ramappa
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/i915_perf.c | 276 +++---
drivers/gpu/drm/i915/i915_reg.h | 103 ++
drivers/gpu/drm/i915/oa/i915_oa_tgl.c | 121 +++
drivers/gpu/drm/i915/oa/i915_oa_tgl.h | 16 ++
5 files changed, 488 insertions(+), 31 deletions(-)
create mode 100644 drivers/gpu/drm/i915/oa/i915_oa_tgl.c
create mode 100644 drivers/gpu/drm/i915/oa/i915_oa_tgl.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index e791d9323b51..0ec9fee58baa 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -242,7 +242,8 @@ i915-y += \
oa/i915_oa_cflgt2.o \
oa/i915_oa_cflgt3.o \
oa/i915_oa_cnl.o \
- oa/i915_oa_icl.o
+ oa/i915_oa_icl.o \
+ oa/i915_oa_tgl.o
i915-y += i915_perf.o
# Post-mortem debug and GPU hang state capture
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index ce97af484a32..2229a7bf9d1b 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -217,6 +217,7 @@
#include "oa/i915_oa_cflgt3.h"
#include "oa/i915_oa_cnl.h"
#include "oa/i915_oa_icl.h"
+#include "oa/i915_oa_tgl.h"
/* HW requires this to be a power of two, between 128k and 16M, though driver
* is currently generally designed assuming the largest 16M size is used such
@@ -292,7 +293,8 @@ static u32 i915_perf_stream_paranoid = true;
#define INVALID_CTX_ID 0x
/* On Gen8+ automatically triggered OA reports include a 'reason' field... */
-#define OAREPORT_REASON_MASK 0x3f
+#define OAREPORT_REASON_MASK (IS_GEN(stream->perf->i915, 12) ? \
+ 0x7f : 0x3f)
#define OAREPORT_REASON_SHIFT 19
#define OAREPORT_REASON_TIMER (1<<0)
#define OAREPORT_REASON_CTX_SWITCH (1<<3)
@@ -338,6 +340,10 @@ static const struct i915_oa_format
gen8_plus_oa_formats[I915_OA_FORMAT_MAX] = {
[I915_OA_FORMAT_C4_B8] = { 7, 64 },
};
+static const struct i915_oa_format gen12_oa_formats[I915_OA_FORMAT_MAX] = {
+ [I915_OA_FORMAT_A32u40_A4u32_B8_C8] = { 5, 256 },
+};
+
#define SAMPLE_OA_REPORT (1<<0)
/**
@@ -418,6 +424,14 @@ static void free_oa_config_bo(struct i915_oa_config_bo
*oa_bo)
kfree(oa_bo);
}
+static u32 gen12_oa_hw_tail_read(struct i915_perf_stream *stream)
+{
+ struct intel_uncore *uncore = stream->uncore;
+
+ return intel_uncore_read(uncore, GEN12_OAG_OATAILPTR) &
+ GEN12_OAG_OATAILPTR_MASK;
+}
+
static u32 gen8_oa_hw_tail_read(struct i915_perf_stream *stream)
{
struct intel_uncore *uncore = stream->uncore;
@@ -538,7 +552,7 @@ static bool oa_buffer_check_unlocked(struct
i915_perf_stream *stream)
aging_tail = hw_tail;
stream->oa_buffer.aging_timestamp = now;
} else {
- DRM_ERROR("Ignoring spurious out of range OA buffer
tail pointer = %u\n",
+ DRM_ERROR("Ignoring spurious out of range OA buffer
tail pointer = %x\n",
hw_tail);
}
}
@@ -757,7 +771,8 @@ static int gen8_append_oa_reports(struct i915_perf_stream
*stream,
* Note: that we don't clear the valid_ctx_bit so userspace can
* understand that the ID has been squashed by the kernel.
*/
- if (!(report32[0] & stream->perf->gen8_valid_ctx_bit))
+ if (!(report32[0] & stream->perf->gen8_valid_ctx_bit) &&
+ INTEL_GEN(stream->perf->i915) <= 11)
ctx_id = report32[2] = INVALID_CTX_ID;
/*
@@ -824,6 +839,11 @@ static int gen8_append_oa_reports(struct i915_perf_stream
*stream,
}
if (start_offset != *offset) {
+ i915_reg_t oaheadptr;
+
+ oaheadptr = IS_GEN(stream->perf->i915, 12) ?
+
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/execlists: Don't merely skip submission if maybe timeslicing (rev5)
== Series Details == Series: drm/i915/execlists: Don't merely skip submission if maybe timeslicing (rev5) URL : https://patchwork.freedesktop.org/series/68122/ State : warning == Summary == $ dim checkpatch origin/drm-tip ba69a7485401 drm/i915/execlists: Don't merely skip submission if maybe timeslicing -:270: CHECK:LINE_SPACING: Please don't use multiple blank lines #270: FILE: drivers/gpu/drm/i915/gt/selftest_lrc.c:629: + + total: 0 errors, 0 warnings, 1 checks, 304 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v4,1/2] drm/i915: Make for_each_engine_masked work on intel_gt (rev4)
== Series Details ==
Series: series starting with [v4,1/2] drm/i915: Make for_each_engine_masked
work on intel_gt (rev4)
URL : https://patchwork.freedesktop.org/series/68142/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7124 -> Patchwork_14863
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14863 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14863, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14863/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14863:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_execlists:
- fi-icl-u2: NOTRUN -> [DMESG-FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14863/fi-icl-u2/igt@i915_selftest@live_execlists.html
- fi-icl-u3: [PASS][2] -> [DMESG-FAIL][3]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7124/fi-icl-u3/igt@i915_selftest@live_execlists.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14863/fi-icl-u3/igt@i915_selftest@live_execlists.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live_execlists:
- {fi-icl-dsi}: [PASS][4] -> [DMESG-FAIL][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7124/fi-icl-dsi/igt@i915_selftest@live_execlists.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14863/fi-icl-dsi/igt@i915_selftest@live_execlists.html
* igt@i915_selftest@live_requests:
- {fi-tgl-u}: [PASS][6] -> [INCOMPLETE][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7124/fi-tgl-u/igt@i915_selftest@live_requests.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14863/fi-tgl-u/igt@i915_selftest@live_requests.html
Known issues
Here are the changes found in Patchwork_14863 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_flink_basic@flink-lifetime:
- fi-icl-u3: [PASS][8] -> [DMESG-WARN][9] ([fdo#107724]) +1
similar issue
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7124/fi-icl-u3/igt@gem_flink_ba...@flink-lifetime.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14863/fi-icl-u3/igt@gem_flink_ba...@flink-lifetime.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][10] -> [FAIL][11] ([fdo#111045] / [fdo#111096])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7124/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14863/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
Possible fixes
* igt@gem_mmap@basic:
- fi-icl-u3: [DMESG-WARN][12] ([fdo#107724]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7124/fi-icl-u3/igt@gem_m...@basic.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14863/fi-icl-u3/igt@gem_m...@basic.html
* igt@i915_selftest@live_execlists:
- {fi-icl-guc}: [DMESG-FAIL][14] -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7124/fi-icl-guc/igt@i915_selftest@live_execlists.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14863/fi-icl-guc/igt@i915_selftest@live_execlists.html
- fi-skl-6770hq: [DMESG-FAIL][16] -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7124/fi-skl-6770hq/igt@i915_selftest@live_execlists.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14863/fi-skl-6770hq/igt@i915_selftest@live_execlists.html
- fi-cfl-8109u: [DMESG-FAIL][18] -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7124/fi-cfl-8109u/igt@i915_selftest@live_execlists.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14863/fi-cfl-8109u/igt@i915_selftest@live_execlists.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u2: [INCOMPLETE][20] ([fdo#107713] / [fdo#108569]) ->
[PASS][21]
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7124/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14863/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[f
Re: [Intel-gfx] [PATCH] drm/i915/aml: Allow SPT PCH for all AML devices
Hey! work brought this issue to my attention, so I figured I'd help speed
things up and review this :)
Anyway-looks fine to me
Reviewed-by: Lyude Paul
On Thu, 2019-10-17 at 12:42 -0700, James Ausmus wrote:
> Even the AML devices that behave like CFLs can be paired with an SPT
> PCH. Allow this to happen without blowing up dmesg.
>
> BSpec: 33665
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112013
> Cc: Quanxian Wang
> Cc: Rodrigo Vivi
> Signed-off-by: James Ausmus
> ---
> drivers/gpu/drm/i915/intel_pch.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pch.c
> b/drivers/gpu/drm/i915/intel_pch.c
> index 1035d3d46fd8..bb1cb6f12a50 100644
> --- a/drivers/gpu/drm/i915/intel_pch.c
> +++ b/drivers/gpu/drm/i915/intel_pch.c
> @@ -52,7 +52,8 @@ intel_pch_type(const struct drm_i915_private *dev_priv,
> unsigned short id)
> return PCH_SPT;
> case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE:
> DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
> - WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
> + WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) &&
> + !IS_COFFEELAKE(dev_priv));
> return PCH_SPT;
> case INTEL_PCH_KBP_DEVICE_ID_TYPE:
> DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
--
Cheers,
Lyude Paul
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v4,1/2] drm/i915: Make for_each_engine_masked work on intel_gt (rev4)
== Series Details == Series: series starting with [v4,1/2] drm/i915: Make for_each_engine_masked work on intel_gt (rev4) URL : https://patchwork.freedesktop.org/series/68142/ State : warning == Summary == $ dim checkpatch origin/drm-tip d956d416d5b5 drm/i915: Make for_each_engine_masked work on intel_gt -:301: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'gt__' - possible side-effects? #301: FILE: drivers/gpu/drm/i915/i915_drv.h:1418: +#define for_each_engine_masked(engine__, gt__, mask__, tmp__) \ + for ((tmp__) = (mask__) & INTEL_INFO((gt__)->i915)->engine_mask; \ (tmp__) ? \ +((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \ 0;) -:301: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'tmp__' - possible side-effects? #301: FILE: drivers/gpu/drm/i915/i915_drv.h:1418: +#define for_each_engine_masked(engine__, gt__, mask__, tmp__) \ + for ((tmp__) = (mask__) & INTEL_INFO((gt__)->i915)->engine_mask; \ (tmp__) ? \ +((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \ 0;) total: 0 errors, 0 warnings, 2 checks, 211 lines checked 0fad377701e2 drm/i915: Pass in intel_gt at some for_each_engine sites ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 2/2] drm/i915: Restrict qgv points which don't have enough bandwidth.
On Tue, Oct 15, 2019 at 04:50:13PM +0300, Stanislav Lisovskiy wrote:
> According to BSpec 53998, we should try to
> restrict qgv points, which can't provide
> enough bandwidth for desired display configuration.
>
> Currently we are just comparing against all of
> those and take minimum(worst case).
>
> v2: Fixed wrong PCode reply mask, removed hardcoded
> values.
>
> v3: Forbid simultaneous legacy SAGV PCode requests and
> restricting qgv points. Put the actual restriction
> to commit function, added serialization(thanks to Ville)
> to prevent commit being applied out of order in case of
> nonblocking and/or nomodeset commits.
>
> v4:
> - Minor code refactoring, fixed few typos(thanks to James Ausmus)
> - Change the naming of qgv point
> masking/unmasking functions(James Ausmus).
> - Simplify the masking/unmasking operation itself,
> as we don't need to mask only single point per request(James Ausmus)
> - Reject and stick to highest bandwidth point if SAGV
> can't be enabled(BSpec)
>
> Signed-off-by: Stanislav Lisovskiy
> Cc: Ville Syrjälä
> Cc: James Ausmus
> ---
> drivers/gpu/drm/i915/display/intel_atomic.c | 16 +++
> drivers/gpu/drm/i915/display/intel_atomic.h | 3 +
> drivers/gpu/drm/i915/display/intel_bw.c | 105 ++
> drivers/gpu/drm/i915/display/intel_bw.h | 2 +
> drivers/gpu/drm/i915/display/intel_display.c | 58 +-
> .../drm/i915/display/intel_display_types.h| 3 +
> drivers/gpu/drm/i915/i915_drv.h | 2 +
> drivers/gpu/drm/i915/i915_reg.h | 3 +
> 8 files changed, 166 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
> b/drivers/gpu/drm/i915/display/intel_atomic.c
> index c5a552a69752..b3f4f02f380b 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> @@ -207,6 +207,22 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
> return &crtc_state->base;
> }
>
> +int intel_atomic_serialize_global_state(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_crtc *crtc;
> +
> + for_each_intel_crtc(&dev_priv->drm, crtc) {
> + struct intel_crtc_state *crtc_state;
> +
> + crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
> + if (IS_ERR(crtc_state))
> + return PTR_ERR(crtc_state);
> + }
> +
> + return 0;
> +}
> +
> /**
> * intel_crtc_destroy_state - destroy crtc state
> * @crtc: drm crtc
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h
> b/drivers/gpu/drm/i915/display/intel_atomic.h
> index 58065d3161a3..fd17b3ca257f 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.h
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.h
> @@ -7,6 +7,7 @@
> #define __INTEL_ATOMIC_H__
>
> #include
> +#include "intel_display_types.h"
>
> struct drm_atomic_state;
> struct drm_connector;
> @@ -38,6 +39,8 @@ void intel_crtc_destroy_state(struct drm_crtc *crtc,
> struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
> void intel_atomic_state_clear(struct drm_atomic_state *state);
>
> +int intel_atomic_serialize_global_state(struct intel_atomic_state *state);
> +
> struct intel_crtc_state *
> intel_atomic_get_crtc_state(struct drm_atomic_state *state,
> struct intel_crtc *crtc);
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index 22e83f857de8..09f786cfdfaa 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -8,6 +8,8 @@
> #include "intel_bw.h"
> #include "intel_display_types.h"
> #include "intel_sideband.h"
> +#include "intel_atomic.h"
> +#include "intel_pm.h"
>
> /* Parameters for Qclk Geyserville (QGV) */
> struct intel_qgv_point {
> @@ -113,6 +115,27 @@ static int icl_pcode_read_qgv_point_info(struct
> drm_i915_private *dev_priv,
> return 0;
> }
>
> +int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
> + u32 points_mask)
> +{
> + int ret;
> +
> + /* bspec says to keep retrying for at least 1 ms */
> + ret = skl_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
> + points_mask,
> + GEN11_PCODE_POINTS_RESTRICTED_MASK,
> + GEN11_PCODE_POINTS_RESTRICTED,
> + 1);
> +
> + if (ret < 0) {
> + DRM_ERROR("Failed to disable qgv points (%d)\n", ret);
This could also be enabling qgv points, so this might better be "Failed
to set qgv point mask".
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +
> static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
> struct intel_qgv_inf
Re: [Intel-gfx] [PATCH v4 1/2] drm/i915: Refactor intel_can_enable_sagv
On Tue, Oct 15, 2019 at 04:50:12PM +0300, Stanislav Lisovskiy wrote:
> Currently intel_can_enable_sagv function contains
> a mix of workarounds for different platforms
> some of them are not valid for gens >= 11 already,
> so lets split it into separate functions.
>
> Signed-off-by: Stanislav Lisovskiy
> Cc: Ville Syrjälä
> Cc: James Ausmus
> ---
> drivers/gpu/drm/i915/intel_pm.c | 73 +++--
> 1 file changed, 70 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 67d171456f59..662a36ff2f43 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3750,7 +3750,7 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
> return 0;
> }
>
> -bool intel_can_enable_sagv(struct intel_atomic_state *state)
> +bool skl_can_enable_sagv(struct intel_atomic_state *state)
> {
> struct drm_device *dev = state->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> @@ -3801,8 +3801,8 @@ bool intel_can_enable_sagv(struct intel_atomic_state
> *state)
>
> if (skl_needs_memory_bw_wa(dev_priv) &&
> plane->base.state->fb->modifier ==
> - I915_FORMAT_MOD_X_TILED)
> - latency += 15;
> + I915_FORMAT_MOD_X_TILED)
> + latency += 15;
This whitespace change doesn't look right
>
> /*
>* If any of the planes on this pipe don't enable wm levels that
> @@ -3816,6 +3816,73 @@ bool intel_can_enable_sagv(struct intel_atomic_state
> *state)
> return true;
> }
>
> +bool icl_can_enable_sagv(struct intel_atomic_state *state)
> +{
> + struct drm_device *dev = state->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_crtc *crtc;
> + struct intel_crtc_state *new_crtc_state;
> + int level, latency;
> + int i;
> + int plane_id;
> +
> + if (!intel_has_sagv(dev_priv))
> + return false;
> +
> + /*
> + * If there are no active CRTCs, no additional checks need be performed
> + */
> + if (hweight8(state->active_pipes) == 0)
> + return true;
> +
> + for_each_new_intel_crtc_in_state(state, crtc,
> + new_crtc_state, i) {
> +
> + if (crtc->base.state->adjusted_mode.flags &
> DRM_MODE_FLAG_INTERLACE)
> + return false;
> +
> + if (!new_crtc_state->base.enable)
> + continue;
> +
> + for_each_plane_id_on_crtc(crtc, plane_id) {
> + struct skl_plane_wm *wm =
> +
> &new_crtc_state->wm.skl.optimal.planes[plane_id];
> +
> + /* Skip this plane if it's not enabled */
> + if (!wm->wm[0].plane_en)
> + continue;
> +
> + /* Find the highest enabled wm level for this plane */
> + for (level = ilk_wm_max_level(dev_priv);
> + !wm->wm[level].plane_en; --level)
> + { }
> +
> + latency = dev_priv->wm.skl_latency[level];
This isn't exactly the same for TGL. From BSpec 49325, "Calculate
watermark level 0 with level 0 latency + SAGV block time. If the result
can be supported (does not exceed maximum), then the plane can tolerate
SAGV", so I think it can be simplified for Gen12+ by not having to loop
through all the wm levels.
-James
> +
> + /*
> + * If any of the planes on this pipe don't enable wm
> levels that
> + * incur memory latencies higher than
> sagv_block_time_us we
> + * can't enable SAGV.
> + */
> + if (latency < dev_priv->sagv_block_time_us)
> + return false;
> + }
> + }
> +
> + return true;
> +}
> +
> +bool intel_can_enable_sagv(struct intel_atomic_state *state)
> +{
> + struct drm_device *dev = state->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> +
> + if (INTEL_GEN(dev_priv) >= 11)
> + return icl_can_enable_sagv(state);
> +
> + return skl_can_enable_sagv(state);
> +}
> +
> static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
> const struct intel_crtc_state *crtc_state,
> const u64 total_data_rate,
> --
> 2.17.1
>
___
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Re: [Intel-gfx] [PATCH] drm/i915: Do not end i915 batch buffers prematurely
On 10/17/19 12:37 PM, Stuart Summers wrote: During engine initialization in i915 load, the batch buffers being used to set up the initial context are being prematurely ended. In most scenarios, this does not cause a problem, but That's not a batch that we add the BBEND to, that's the context itself. in the rare event the engine expects the context to be added without an explicit MI_BATCH_BUFFER_END instruction, do not insert this instruction prematurely. We only add the BBEND when there is no state to restore, so why would the engine expect to execute a bunch of no-ops? Daniele Signed-off-by: Stuart Summers --- drivers/gpu/drm/i915/gt/intel_lrc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index e9fe9f79cedd..ec067c29ac65 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -3805,7 +3805,7 @@ populate_lr_context(struct intel_context *ce, /* The second page of the context object contains some fields which must * be set up prior to the first execution. */ regs = vaddr + LRC_STATE_PN * PAGE_SIZE; - execlists_init_reg_state(regs, ce, engine, ring, inhibit); + execlists_init_reg_state(regs, ce, engine, ring, false); if (inhibit) regs[CTX_CONTEXT_CONTROL] |= _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 1/2] drm/i915: Make for_each_engine_masked work on intel_gt
Quoting Tvrtko Ursulin (2019-10-17 17:18:52) > From: Tvrtko Ursulin > > Medium term goal is to eliminate the i915->engine[] array and to get there > we have recently introduced equivalent array in intel_gt. Now we need to > migrate the code further towards this state. > > This next step is to eliminate usage of i915->engines[] from the > for_each_engine_masked iterator. > > For this to work we also need to use engine->id as index when populating > the gt->engine[] array and adjust the default engine set indexing to use > engine->legacy_idx instead of assuming gt->engines[] indexing. > > v2: > * Populate gt->engine[] earlier. > * Check that we don't duplicate engine->legacy_idx > > v3: > * Work around the initialization order issue between default_engines() > and intel_engines_driver_register() which sets engine->legacy_idx for > now. It will be fixed properly later. > > v4: > * Merge with forgotten v2.5. > > Signed-off-by: Tvrtko Ursulin > Cc: Chris Wilson Reviewed-by: Chris Wilson * fingers crossed -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Don't disable interrupts independently of the lock (rev4)
== Series Details ==
Series: drm/i915: Don't disable interrupts independently of the lock (rev4)
URL : https://patchwork.freedesktop.org/series/59289/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7122 -> Patchwork_14862
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14862/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14862:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live_execlists:
- {fi-kbl-soraka}:[PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-kbl-soraka/igt@i915_selftest@live_execlists.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14862/fi-kbl-soraka/igt@i915_selftest@live_execlists.html
- {fi-icl-u4}:[PASS][3] -> [DMESG-FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-icl-u4/igt@i915_selftest@live_execlists.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14862/fi-icl-u4/igt@i915_selftest@live_execlists.html
Known issues
Here are the changes found in Patchwork_14862 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_addfb_basic@addfb25-y-tiled:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724]) +1
similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-icl-u3/igt@kms_addfb_ba...@addfb25-y-tiled.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14862/fi-icl-u3/igt@kms_addfb_ba...@addfb25-y-tiled.html
Possible fixes
* igt@gem_ctx_switch@rcs0:
- {fi-icl-guc}: [INCOMPLETE][7] ([fdo#107713]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-icl-guc/igt@gem_ctx_swi...@rcs0.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14862/fi-icl-guc/igt@gem_ctx_swi...@rcs0.html
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10] +2
similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14862/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
* igt@i915_selftest@live_execlists:
- fi-icl-u3: [DMESG-FAIL][11] -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-icl-u3/igt@i915_selftest@live_execlists.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14862/fi-icl-u3/igt@i915_selftest@live_execlists.html
- fi-cfl-8109u: [DMESG-FAIL][13] -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-cfl-8109u/igt@i915_selftest@live_execlists.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14862/fi-cfl-8109u/igt@i915_selftest@live_execlists.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111647]: https://bugs.freedesktop.org/show_bug.cgi?id=111647
Participating hosts (53 -> 46)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7122 -> Patchwork_14862
CI-20190529: 20190529
CI_DRM_7122: c2f6bdc09f8f046cd38e3c39c92e14e6033dbd44 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5232: bb5735423eaf6fdbf6b2f94ef0b8520e74eab993 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14862: a33b99af68b77e1b6852d4329e74bed3861968f9 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
a33b99af68b7 drm/i915: Don't disable interrupts independently of the lock
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14862/index.html
___
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dsb: Remove PIN_MAPPABLE from the DSB object VMA
== Series Details ==
Series: drm/i915/dsb: Remove PIN_MAPPABLE from the DSB object VMA
URL : https://patchwork.freedesktop.org/series/68162/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7122 -> Patchwork_14861
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14861 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14861, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14861/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14861:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_execlists:
- fi-skl-6260u: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-skl-6260u/igt@i915_selftest@live_execlists.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14861/fi-skl-6260u/igt@i915_selftest@live_execlists.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live_requests:
- {fi-tgl-u2}:[PASS][3] -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-tgl-u2/igt@i915_selftest@live_requests.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14861/fi-tgl-u2/igt@i915_selftest@live_requests.html
Known issues
Here are the changes found in Patchwork_14861 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_switch@legacy-render:
- fi-bxt-dsi: [PASS][5] -> [INCOMPLETE][6] ([fdo#103927] /
[fdo#111381])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14861/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
Possible fixes
* igt@gem_ctx_switch@rcs0:
- {fi-icl-guc}: [INCOMPLETE][7] ([fdo#107713]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-icl-guc/igt@gem_ctx_swi...@rcs0.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14861/fi-icl-guc/igt@gem_ctx_swi...@rcs0.html
* igt@i915_selftest@live_execlists:
- fi-cfl-8109u: [DMESG-FAIL][9] -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-cfl-8109u/igt@i915_selftest@live_execlists.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14861/fi-cfl-8109u/igt@i915_selftest@live_execlists.html
* igt@i915_selftest@live_hangcheck:
- {fi-tgl-u}: [INCOMPLETE][11] ([fdo#111747]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-tgl-u/igt@i915_selftest@live_hangcheck.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14861/fi-tgl-u/igt@i915_selftest@live_hangcheck.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][13] ([fdo#111407]) -> [FAIL][14] ([fdo#111045]
/ [fdo#111096])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14861/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
Participating hosts (53 -> 45)
--
Missing(8): fi-ilk-m540 fi-bdw-5557u fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7122 -> Patchwork_14861
CI-20190529: 20190529
CI_DRM_7122: c2f6bdc09f8f046cd38e3c39c92e14e6033dbd44 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5232: bb5735423eaf6fdbf6b2f94ef0b8520e74eab993 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14861: 426b4ee113b4bddf0be1d86df50111019fb9c226 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
426b4ee113b4 drm/i915/dsb: Remove PIN_MAPPABLE from the DSB object VMA
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/
[Intel-gfx] [PULL] drm-misc-fixes
Hi Dave/Daniel, Guest-Maxime here with a drm-misc-fixes pull. Interesting stuff has been highlighted below in the tag. I realized that we have Steven's stopped job patch in both -next and -fixes, so we'll need to watch out for conflicts when they come together. drm-misc-fixes-2019-10-17: -dma-resv: Change shared_count to post-increment to fix lima crash (Qiang) -ttm: A couple fixes related to lifetime and restore prefault behavior (Christian & Thomas) -panfrost: Fill in missing feature reg values and fix stoppedjob timeouts (Steven) Cc: Qiang Yu Cc: Thomas Hellstrom Cc: Christian König Cc: Steven Price Cheers, Sean The following changes since commit fd70c7755bf0172ddd33b558aef69c322de3b5cf: drm/bridge: tc358767: fix max_tu_symbol value (2019-10-10 11:15:45 +0200) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-fixes-2019-10-17 for you to fetch changes up to 5b3ec8134f5f9fa1ed0a538441a495521078bbee: drm/panfrost: Handle resetting on timeout better (2019-10-15 11:38:22 -0500) -dma-resv: Change shared_count to post-increment to fix lima crash (Qiang) -ttm: A couple fixes related to lifetime and restore prefault behavior (Christian & Thomas) -panfrost: Fill in missing feature reg values and fix stoppedjob timeouts (Steven) Cc: Qiang Yu Cc: Thomas Hellstrom Cc: Christian König Cc: Steven Price Christian König (2): drm/ttm: fix busy reference in ttm_mem_evict_first drm/ttm: fix handling in ttm_bo_add_mem_to_lru Jeffrey Hugo (1): drm/msm/dsi: Implement reset correctly Kai-Heng Feng (1): drm/edid: Add 6 bpc quirk for SDC panel in Lenovo G50 Qiang Yu (1): dma-buf/resv: fix exclusive fence get Steven Price (2): drm/panfrost: Add missing GPU feature registers drm/panfrost: Handle resetting on timeout better Thomas Hellstrom (1): drm/ttm: Restore ttm prefaulting Ulf Magnusson (1): drm/tiny: Kconfig: Remove always-y THERMAL dep. from TINYDRM_REPAPER drivers/dma-buf/dma-resv.c | 2 +- drivers/gpu/drm/drm_edid.c | 3 +++ drivers/gpu/drm/msm/dsi/dsi_host.c | 6 -- drivers/gpu/drm/panfrost/panfrost_gpu.c | 3 +++ drivers/gpu/drm/panfrost/panfrost_job.c | 16 +++- drivers/gpu/drm/tiny/Kconfig| 1 - drivers/gpu/drm/ttm/ttm_bo.c| 9 + drivers/gpu/drm/ttm/ttm_bo_vm.c | 16 +++- 8 files changed, 34 insertions(+), 22 deletions(-) -- Sean Paul, Software Engineer, Google / Chromium OS ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/4] drm/i915: Add memory region information to device_info
Quoting Matthew Auld (2019-10-17 18:45:41) > From: Abdiel Janulgue > > Exposes available regions for the platform. Needed in later patches. > > Signed-off-by: Abdiel Janulgue > Signed-off-by: Matthew Auld Squash this into patch 2. I do not see any value in this patch alone. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/4] drm/i915: treat shmem as a region
Quoting Matthew Auld (2019-10-17 18:45:43)
> @@ -434,9 +439,9 @@ const struct drm_i915_gem_object_ops i915_gem_shmem_ops =
> {
> .release = shmem_release,
> };
>
> -static int create_shmem(struct drm_i915_private *i915,
> - struct drm_gem_object *obj,
> - size_t size)
> +static int __create_shmem(struct drm_i915_private *i915,
> + struct drm_gem_object *obj,
> + size_t size)
I would feel happier if our interface was consistent, right up until the
moment it met drm, i.e. resource_size_t size.
> {
> unsigned long flags = VM_NORESERVE;
> struct file *filp;
> @@ -455,31 +460,23 @@ static int create_shmem(struct drm_i915_private *i915,
> return 0;
> }
>
> -struct drm_i915_gem_object *
> -i915_gem_object_create_shmem(struct drm_i915_private *i915, u64 size)
> +static struct drm_i915_gem_object *
> +create_shmem(struct intel_memory_region *mem,
> +resource_size_t size,
> +unsigned int flags)
> {
> + struct drm_i915_private *i915 = mem->i915;
> struct drm_i915_gem_object *obj;
> struct address_space *mapping;
> unsigned int cache_level;
> gfp_t mask;
> int ret;
>
> - /* There is a prevalence of the assumption that we fit the object's
> -* page count inside a 32bit _signed_ variable. Let's document this
> and
> -* catch if we ever need to fix it. In the meantime, if you do spot
> -* such a local variable, please consider fixing!
> -*/
> - if (size >> PAGE_SHIFT > INT_MAX)
> - return ERR_PTR(-E2BIG);
> -
> - if (overflows_type(size, obj->base.size))
> - return ERR_PTR(-E2BIG);
> -
> obj = i915_gem_object_alloc();
> if (!obj)
> return ERR_PTR(-ENOMEM);
>
> - ret = create_shmem(i915, &obj->base, size);
> + ret = __create_shmem(i915, &obj->base, size);
> if (ret)
> goto fail;
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/selftests: Teach requests to use all available engines
Quoting Tvrtko Ursulin (2019-10-17 17:54:55) > Will we end up with a for_each_uabi_engine_idx iterator? And storing the > num_uabi_engines in somewhere? I see the repetition, yeah, not convinced from this set that we want to proliferate the magic macros. I expect you will notice in future if the pattern continues to hold, and I might not then have a good excuse to be lazy. Hopefully someone else gets caught out first :) -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Correct the PCH type in irq postinstall (rev2)
== Series Details ==
Series: drm/i915: Correct the PCH type in irq postinstall (rev2)
URL : https://patchwork.freedesktop.org/series/68116/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7122 -> Patchwork_14860
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14860/index.html
Known issues
Here are the changes found in Patchwork_14860 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_switch@legacy-render:
- fi-icl-u2: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] /
[fdo#111381])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-icl-u2/igt@gem_ctx_swi...@legacy-render.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14860/fi-icl-u2/igt@gem_ctx_swi...@legacy-render.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [PASS][3] -> [DMESG-WARN][4] ([fdo#102614])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14860/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
* igt@prime_vgem@basic-fence-wait-default:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724]) +2
similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-icl-u3/igt@prime_v...@basic-fence-wait-default.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14860/fi-icl-u3/igt@prime_v...@basic-fence-wait-default.html
Possible fixes
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8] +2
similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14860/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
* igt@i915_selftest@live_execlists:
- fi-cfl-8109u: [DMESG-FAIL][9] -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-cfl-8109u/igt@i915_selftest@live_execlists.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14860/fi-cfl-8109u/igt@i915_selftest@live_execlists.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
[fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
[fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
Participating hosts (53 -> 42)
--
Missing(11): fi-icl-u4 fi-bxt-dsi fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-pnv-d510 fi-icl-y fi-icl-guc fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7122 -> Patchwork_14860
CI-20190529: 20190529
CI_DRM_7122: c2f6bdc09f8f046cd38e3c39c92e14e6033dbd44 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5232: bb5735423eaf6fdbf6b2f94ef0b8520e74eab993 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14860: 44f036318c26aba453888e79cedbe7f64b54bde7 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
44f036318c26 drm/i915: Correct the PCH type in irq postinstall
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14860/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/2] drm/i915/execlists: Don't merely skip submission if maybe timeslicing
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/execlists: Don't merely skip
submission if maybe timeslicing
URL : https://patchwork.freedesktop.org/series/68160/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7122 -> Patchwork_14859
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14859 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14859, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14859/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14859:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_execlists:
- fi-skl-iommu: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-skl-iommu/igt@i915_selftest@live_execlists.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14859/fi-skl-iommu/igt@i915_selftest@live_execlists.html
- fi-cml-u: [PASS][3] -> [DMESG-FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-cml-u/igt@i915_selftest@live_execlists.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14859/fi-cml-u/igt@i915_selftest@live_execlists.html
- fi-kbl-guc: [PASS][5] -> [DMESG-FAIL][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-kbl-guc/igt@i915_selftest@live_execlists.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14859/fi-kbl-guc/igt@i915_selftest@live_execlists.html
- fi-skl-lmem:[PASS][7] -> [DMESG-FAIL][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-skl-lmem/igt@i915_selftest@live_execlists.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14859/fi-skl-lmem/igt@i915_selftest@live_execlists.html
Known issues
Here are the changes found in Patchwork_14859 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_flink_basic@bad-open:
- fi-icl-u3: [PASS][9] -> [DMESG-WARN][10] ([fdo#107724])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-icl-u3/igt@gem_flink_ba...@bad-open.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14859/fi-icl-u3/igt@gem_flink_ba...@bad-open.html
Possible fixes
* igt@gem_ctx_switch@rcs0:
- {fi-icl-guc}: [INCOMPLETE][11] ([fdo#107713]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-icl-guc/igt@gem_ctx_swi...@rcs0.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14859/fi-icl-guc/igt@gem_ctx_swi...@rcs0.html
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u3: [DMESG-WARN][13] ([fdo#107724]) -> [PASS][14] +2
similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14859/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
* igt@i915_selftest@live_execlists:
- fi-icl-u3: [DMESG-FAIL][15] -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-icl-u3/igt@i915_selftest@live_execlists.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14859/fi-icl-u3/igt@i915_selftest@live_execlists.html
- fi-cfl-8109u: [DMESG-FAIL][17] -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-cfl-8109u/igt@i915_selftest@live_execlists.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14859/fi-cfl-8109u/igt@i915_selftest@live_execlists.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
Participating hosts (53 -> 45)
--
Missing(8): fi-ilk-m540 fi-hsw-4200u fi-bsw-n3050 fi-byt-squawks
fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7122 -> Patchwork_14859
CI-20190529: 20190529
CI_DRM_7122: c2f6bdc09f8f046cd38e3c39c92e14e6033dbd44 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5232: bb5735423eaf6fdbf6b2f94ef0b8520e74eab993 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14859: e5053550c86d0f63067b7f1df5f0f2c589ca6455 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
e5053550c86d drm/i915: Don't disable interrupts independently of the lock
0
[Intel-gfx] [PATCH] drm/i915/aml: Allow SPT PCH for all AML devices
Even the AML devices that behave like CFLs can be paired with an SPT
PCH. Allow this to happen without blowing up dmesg.
BSpec: 33665
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112013
Cc: Quanxian Wang
Cc: Rodrigo Vivi
Signed-off-by: James Ausmus
---
drivers/gpu/drm/i915/intel_pch.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c
index 1035d3d46fd8..bb1cb6f12a50 100644
--- a/drivers/gpu/drm/i915/intel_pch.c
+++ b/drivers/gpu/drm/i915/intel_pch.c
@@ -52,7 +52,8 @@ intel_pch_type(const struct drm_i915_private *dev_priv,
unsigned short id)
return PCH_SPT;
case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE:
DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
- WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
+ WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) &&
+ !IS_COFFEELAKE(dev_priv));
return PCH_SPT;
case INTEL_PCH_KBP_DEVICE_ID_TYPE:
DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Do not end i915 batch buffers prematurely
During engine initialization in i915 load, the batch buffers being used to set up the initial context are being prematurely ended. In most scenarios, this does not cause a problem, but in the rare event the engine expects the context to be added without an explicit MI_BATCH_BUFFER_END instruction, do not insert this instruction prematurely. Signed-off-by: Stuart Summers --- drivers/gpu/drm/i915/gt/intel_lrc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index e9fe9f79cedd..ec067c29ac65 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -3805,7 +3805,7 @@ populate_lr_context(struct intel_context *ce, /* The second page of the context object contains some fields which must * be set up prior to the first execution. */ regs = vaddr + LRC_STATE_PN * PAGE_SIZE; - execlists_init_reg_state(regs, ce, engine, ring, inhibit); + execlists_init_reg_state(regs, ce, engine, ring, false); if (inhibit) regs[CTX_CONTEXT_CONTROL] |= _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); -- 2.22.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PULL] drm-misc-next
Hi Dave/Daniel, Apologies for this being a day late, I wanted to get the dt-bindings for the malidp QoS change before sending this. Most of the volume is incremental this week, there's some new HW features enabled which I've called out below. As for the uapi changes, well it's interesting timing with your RFC the other day :) I think the error code changes are well-scrutinized so I don't have much concern for those. The omap OMAP_BO_MEM_* changes though I don't think have really reached non-TI eyes. There's no link in the commit message to a UAPI implementation and the only reference I could find is libkmsxx which can set them through the python bindings. Since this is TI-specific gunk in TI-specific headers I'm inclined to let it pass, but I would have liked to have this conversation upfront. I figured I'd call this out so you have final say. drm-misc-next-2019-10-17: drm-misc-next for 5.5: UAPI Changes: -omap: -Add OMAP_BO_MEM_* flags to specify how to allocate BO (Tomi) -Reorder OMAP_BO_* #defines, no functional change (Tomi) -Change unsupported error code from EINVAL to EOPNOTSUPP for: (Rodrigo) -drm_wait_vblank_ioctl -drm_crtc_get_sequence_ioctl -drm_crtc_queue_sequence_ioctl Cross-subsystem Changes: -None Core Changes: -Delete drmP.h \o/ (Sam) -kerneldoc clarifications on zpos collisions and plane rects (Simon & Maarten) -dp_helpers: Add link training repeater definitions added in DP 1.4 (Rodrigo) -TODO: Add item to convert fbdev drivers to drm (Thomas) -prime: Add mmap to drm_gem_object_funcs giving more control than vm_ops (Gerd) -shmem/ttm/vram: Use new mmap gem_object callback (Gerd) Driver Changes: -malidp: Add display QoS configuration via devicetree (Wen) -vkms: Add prime import support (Oleg) -panfrost: Properly handle job timeouts when cancelling them (Steven) -rockchip/meson/sun4i(via dw-hdmi): Add Dynamic Range and Mastering infoframe support (Jonas) -mxsfb: Add bridge support to accommodate dsi outputs (Robert) -vboxvideo: Drop hand-rolled implementations and use fbdev emulation, dirtyfb and drm_framebuffer struct from core/core helpers (Thomas) -komeda: Add D71-specific line sizes and respect connector color fmt (Lowry) -lima: Use shmem and reservation lock helpers from gem (Qiang) -rockchip: Add gamma LUT support on vop crtcs (Ezequiel) -omap: -Use refcount_t instead of rolling custom refcounting (Jean-Jacques) Cc: Wen He Cc: Sam Ravnborg Cc: Rodrigo Siqueira Cc: Oleg Vasilev Cc: Steven Price Cc: Jonas Karlman Cc: Maarten Lankhorst Cc: Simon Ser Cc: Robert Chiras Cc: Thomas Zimmermann Cc: Lowry Li Cc: Gerd Hoffmann Cc: Qiang Yu Cc: Tomi Valkeinen Cc: Ezequiel Garcia Cc: Jean-Jacques Hiblot Cheers, Sean The following changes since commit 354c2d310082d1c384213ba76c3757dd3cd8755d: drm: damage_helper: Fix race checking plane->state->fb (2019-10-08 09:41:06 -0400) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-next-2019-10-17 for you to fetch changes up to e30b38b71294849c018322d85e90ec056438fe43: drm/lima: add __GFP_NOWARN flag to all dma_alloc_wc (2019-10-17 23:42:02 +0800) drm-misc-next for 5.5: UAPI Changes: -omap: -Add OMAP_BO_MEM_* flags to specify how to allocate BO (Tomi) -Reorder OMAP_BO_* #defines, no functional change (Tomi) -Change unsupported error code from EINVAL to EOPNOTSUPP for: (Rodrigo) -drm_wait_vblank_ioctl -drm_crtc_get_sequence_ioctl -drm_crtc_queue_sequence_ioctl Cross-subsystem Changes: -None Core Changes: -Delete drmP.h \o/ (Sam) -kerneldoc clarifications on zpos collisions and plane rects (Simon & Maarten) -dp_helpers: Add link training repeater definitions added in DP 1.4 (Rodrigo) -TODO: Add item to convert fbdev drivers to drm (Thomas) -prime: Add mmap to drm_gem_object_funcs giving more control than vm_ops (Gerd) -shmem/ttm/vram: Use new mmap gem_object callback (Gerd) Driver Changes: -malidp: Add display QoS configuration via devicetree (Wen) -vkms: Add prime import support (Oleg) -panfrost: Properly handle job timeouts when cancelling them (Steven) trockchip/meson/sun4i(via dw-hdmi): Add Dynamic Range and Mastering infoframe support (Jonas) -mxsfb: Add bridge support to accommodate dsi outputs (Robert) -vboxvideo: Drop hand-rolled implementations and use fbdev emulation, dirtyfb and drm_framebuffer struct from core/core helpers (Thomas) -komeda: Add D71-specific line sizes and respect connector color fmt (Lowry) -lima: Use shmem and reservation lock helpers from gem (Qiang) -rockchip: Add gamma LUT support on vop crtcs (Ezequiel) -omap: -Use refcount_t instead of rolling custom refcounting (Jean-Jacques) Cc: Wen He Cc: Sam Ravnborg Cc: Rodrigo Siqueira Cc: Oleg Vasilev Cc: Steven Price Cc: Jonas Karlman Cc: Maarten Lankhorst Cc: Simon Ser Cc: Robert C
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/2] drm/i915/execlists: Don't merely skip submission if maybe timeslicing
== Series Details == Series: series starting with [CI,1/2] drm/i915/execlists: Don't merely skip submission if maybe timeslicing URL : https://patchwork.freedesktop.org/series/68160/ State : warning == Summary == $ dim checkpatch origin/drm-tip 0da8e6764433 drm/i915/execlists: Don't merely skip submission if maybe timeslicing -:269: CHECK:LINE_SPACING: Please don't use multiple blank lines #269: FILE: drivers/gpu/drm/i915/gt/selftest_lrc.c:628: + + total: 0 errors, 0 warnings, 1 checks, 303 lines checked e5053550c86d drm/i915: Don't disable interrupts independently of the lock ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [01/14] drm/i915: Rework watermark readout to use plane api
== Series Details == Series: series starting with [01/14] drm/i915: Rework watermark readout to use plane api URL : https://patchwork.freedesktop.org/series/68154/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7122 -> Patchwork_14858 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_14858 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_14858, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_14858: ### IGT changes ### Possible regressions * igt@kms_force_connector_basic@force-connector-state: - fi-gdg-551: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-gdg-551/igt@kms_force_connector_ba...@force-connector-state.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/fi-gdg-551/igt@kms_force_connector_ba...@force-connector-state.html * igt@kms_force_connector_basic@force-load-detect: - fi-hsw-4770:[PASS][3] -> [DMESG-WARN][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-hsw-4770/igt@kms_force_connector_ba...@force-load-detect.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/fi-hsw-4770/igt@kms_force_connector_ba...@force-load-detect.html - fi-ivb-3770:[PASS][5] -> [DMESG-WARN][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-ivb-3770/igt@kms_force_connector_ba...@force-load-detect.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/fi-ivb-3770/igt@kms_force_connector_ba...@force-load-detect.html - fi-byt-j1900: [PASS][7] -> [DMESG-WARN][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-byt-j1900/igt@kms_force_connector_ba...@force-load-detect.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/fi-byt-j1900/igt@kms_force_connector_ba...@force-load-detect.html - fi-blb-e6850: [PASS][9] -> [DMESG-WARN][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-blb-e6850/igt@kms_force_connector_ba...@force-load-detect.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/fi-blb-e6850/igt@kms_force_connector_ba...@force-load-detect.html - fi-bwr-2160:[PASS][11] -> [DMESG-WARN][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-bwr-2160/igt@kms_force_connector_ba...@force-load-detect.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/fi-bwr-2160/igt@kms_force_connector_ba...@force-load-detect.html - fi-snb-2600:[PASS][13] -> [DMESG-WARN][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-snb-2600/igt@kms_force_connector_ba...@force-load-detect.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/fi-snb-2600/igt@kms_force_connector_ba...@force-load-detect.html - fi-elk-e7500: [PASS][15] -> [DMESG-WARN][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-elk-e7500/igt@kms_force_connector_ba...@force-load-detect.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/fi-elk-e7500/igt@kms_force_connector_ba...@force-load-detect.html - fi-ilk-650: [PASS][17] -> [DMESG-WARN][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-ilk-650/igt@kms_force_connector_ba...@force-load-detect.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/fi-ilk-650/igt@kms_force_connector_ba...@force-load-detect.html - fi-pnv-d510:[PASS][19] -> [DMESG-WARN][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-pnv-d510/igt@kms_force_connector_ba...@force-load-detect.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/fi-pnv-d510/igt@kms_force_connector_ba...@force-load-detect.html - fi-snb-2520m: [PASS][21] -> [DMESG-WARN][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-snb-2520m/igt@kms_force_connector_ba...@force-load-detect.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/fi-snb-2520m/igt@kms_force_connector_ba...@force-load-detect.html * igt@runner@aborted: - fi-ilk-650: NOTRUN -> [FAIL][23] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/fi-ilk-650/igt@run...@aborted.html - fi-pnv-d510:NOTRUN -> [FAIL][24] [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/fi-pnv-d510/igt@run...@aborted.html - fi-gdg-551: NOTRUN -> [FAIL][25] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/fi-gdg-551/igt@run...@aborted.html
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/14] drm/i915: Rework watermark readout to use plane api
== Series Details ==
Series: series starting with [01/14] drm/i915: Rework watermark readout to use
plane api
URL : https://patchwork.freedesktop.org/series/68154/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
aaabe4f7c23f drm/i915: Rework watermark readout to use plane api
4a9053bede2d drm/i915: Introduce intel_atomic_get_plane_state_after_check(), v2.
-:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#10:
In case of intel_modeset_all_pipes() this is not yet done after atomic_check,
-:87: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#87: FILE: drivers/gpu/drm/i915/display/intel_atomic.c:387:
+ DRM_DEBUG_KMS("Failed to add [PLANE:%d]
to drm_state: %li\n",
+ plane->base.base.id,
PTR_ERR(plane_state));
total: 0 errors, 1 warnings, 1 checks, 185 lines checked
5970fb0393f3 drm/i915: Handle a few more cases for crtc hw/uapi split, v2.
574fdacfb67f drm/i915: Add aliases for uapi and hw to crtc_state
-:67: WARNING:LONG_LINE: line over 100 characters
#67: FILE: drivers/gpu/drm/i915/display/intel_display.h:450:
+
to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state,
&plane->base
total: 0 errors, 1 warnings, 0 checks, 83 lines checked
957c3b363e99 drm/i915: Perform manual conversions for crtc uapi/hw split
57f6e64288f6 drm/i915: Perform automated conversions for crtc uapi/hw split,
base -> hw.
-:7: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#7:
Split up crtc_state->base to hw where appropriate. This is done using the
following patch:
-:1382: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#1382: FILE: drivers/gpu/drm/i915/display/intel_display.c:16667:
+ crtc_state->hw.active = crtc_state->hw.enable =
total: 0 errors, 1 warnings, 1 checks, 2055 lines checked
cefea1fe68bc drm/i915: Perform automated conversions for crtc uapi/hw split,
base -> uapi.
-:18: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#18:
identifier x =~
"^(active|enable|degamma_lut|gamma_lut|ctm|mode|adjusted_mode)$";
-:2352: ERROR:CODE_INDENT: code indent should use tabs where possible
#2352: FILE: drivers/gpu/drm/i915/display/intel_sprite.c:211:
+^I^I^I^I new_crtc_state->uapi.event);$
-:2352: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#2352: FILE: drivers/gpu/drm/i915/display/intel_sprite.c:211:
+ drm_crtc_arm_vblank_event(&crtc->base,
+ new_crtc_state->uapi.event);
total: 1 errors, 1 warnings, 1 checks, 2514 lines checked
a17e5b0b742a drm/i915: Complete crtc hw/uapi split, v2.
-:15: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#15:
- Clear crtc_state->hw on disable, instead of using clear_intel_crtc_state().
total: 0 errors, 1 warnings, 0 checks, 206 lines checked
38d025aa4709 drm/i915: Add aliases for uapi and hw to plane_state
-:49: WARNING:LINE_SPACING: Missing a blank line after declarations
#49: FILE: drivers/gpu/drm/i915/display/intel_atomic_plane.c:112:
+ struct intel_plane_state *plane_state = to_intel_plane_state(state);
+ WARN_ON(plane_state->vma);
total: 0 errors, 1 warnings, 0 checks, 59 lines checked
2b1622595030 drm/i915: Perform manual conversions for plane uapi/hw split
0fae6c91760b drm/i915: Perform automated conversions for plane uapi/hw split,
base -> hw.
-:11: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#11:
identifier x =~
"^(crtc|fb|alpha|pixel_blend_mode|rotation|color_encoding|color_range)$";
-:832: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written
"plane_state->hw.fb"
#832: FILE: drivers/gpu/drm/i915/intel_pm.c:813:
+ return plane_state->hw.fb != NULL;
total: 0 errors, 1 warnings, 1 checks, 836 lines checked
60d57b430c96 drm/i915: Perform automated conversions for plane uapi/hw split,
base -> uapi.
-:713: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned'
#713: FILE: drivers/gpu/drm/i915/display/intel_display.c:10962:
+ unsigned width = drm_rect_width(&plane_state->uapi.dst);
-:714: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned'
#714: FILE: drivers/gpu/drm/i915/display/intel_display.c:10963:
+ unsigned height = drm_rect_height(&plane_state->uapi.dst);
-:782: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#782: FILE: drivers/gpu/drm/i915/display/intel_display.c:11565:
+ plane_state->uapi.visible = visible = false;
-:1510: WARNING:LONG_LINE: line over 100 characters
#1510: FILE: drivers/gpu/drm/i915/intel_pm.c:3112:
+
[Intel-gfx] ✓ Fi.CI.BAT: success for mdev based hardware virtio offloading support (rev5)
== Series Details ==
Series: mdev based hardware virtio offloading support (rev5)
URL : https://patchwork.freedesktop.org/series/66989/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7122 -> Patchwork_14857
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14857/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14857:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live_execlists:
- {fi-kbl-soraka}:[PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-kbl-soraka/igt@i915_selftest@live_execlists.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14857/fi-kbl-soraka/igt@i915_selftest@live_execlists.html
- {fi-icl-dsi}: [PASS][3] -> [DMESG-FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-icl-dsi/igt@i915_selftest@live_execlists.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14857/fi-icl-dsi/igt@i915_selftest@live_execlists.html
- {fi-icl-u4}:[PASS][5] -> [DMESG-FAIL][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-icl-u4/igt@i915_selftest@live_execlists.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14857/fi-icl-u4/igt@i915_selftest@live_execlists.html
Known issues
Here are the changes found in Patchwork_14857 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [PASS][7] -> [DMESG-WARN][8] ([fdo#102614])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14857/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@gem_ctx_switch@rcs0:
- {fi-icl-guc}: [INCOMPLETE][9] ([fdo#107713]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-icl-guc/igt@gem_ctx_swi...@rcs0.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14857/fi-icl-guc/igt@gem_ctx_swi...@rcs0.html
* igt@i915_selftest@live_execlists:
- fi-cfl-8109u: [DMESG-FAIL][11] -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-cfl-8109u/igt@i915_selftest@live_execlists.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14857/fi-cfl-8109u/igt@i915_selftest@live_execlists.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][13] ([fdo#111407]) -> [FAIL][14] ([fdo#111045]
/ [fdo#111096])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14857/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
Participating hosts (53 -> 43)
--
Missing(10): fi-ilk-m540 fi-tgl-u2 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-skl-6260u fi-icl-u3 fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7122 -> Patchwork_14857
CI-20190529: 20190529
CI_DRM_7122: c2f6bdc09f8f046cd38e3c39c92e14e6033dbd44 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5232: bb5735423eaf6fdbf6b2f94ef0b8520e74eab993 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14857: 5dd612418610a446ab5fa70114a8dbc4be483e2b @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
5dd612418610 docs: sample driver to demonstrate how to implement virtio-mdev
framework
7566405601ce virtio: introduce a mdev based transport
0cf5dbea3c83 mdev: introduce virtio device and its device ops
1c27243b07bd mdev: introduce device specific ops
335f12f84dd7 modpost: add support for mdev class id
2d2711d83299 mdev: class id support
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14857/index.html
___
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Re: [Intel-gfx] [PATCH V4 4/6] mdev: introduce virtio device and its device ops
On Thu, 17 Oct 2019 18:48:34 +0800
Jason Wang wrote:
> This patch implements basic support for mdev driver that supports
> virtio transport for kernel virtio driver.
>
> Signed-off-by: Jason Wang
> ---
> drivers/vfio/mdev/mdev_core.c | 12 +++
> include/linux/mdev.h | 4 +
> include/linux/virtio_mdev.h | 151 ++
> 3 files changed, 167 insertions(+)
> create mode 100644 include/linux/virtio_mdev.h
>
> diff --git a/drivers/vfio/mdev/mdev_core.c b/drivers/vfio/mdev/mdev_core.c
> index d0f3113c8071..5834f6b7c7a5 100644
> --- a/drivers/vfio/mdev/mdev_core.c
> +++ b/drivers/vfio/mdev/mdev_core.c
> @@ -57,6 +57,18 @@ void mdev_set_vfio_ops(struct mdev_device *mdev,
> }
> EXPORT_SYMBOL(mdev_set_vfio_ops);
>
> +/* Specify the virtio device ops for the mdev device, this
> + * must be called during create() callback for virtio mdev device.
> + */
> +void mdev_set_virtio_ops(struct mdev_device *mdev,
> + const struct virtio_mdev_device_ops *virtio_ops)
> +{
> + BUG_ON(mdev->class_id);
Nit, this one is a BUG_ON, but the vfio one is a WARN_ON. Thanks,
Alex
> + mdev->class_id = MDEV_CLASS_ID_VIRTIO;
> + mdev->device_ops = virtio_ops;
> +}
> +EXPORT_SYMBOL(mdev_set_virtio_ops);
> +
> const void *mdev_get_dev_ops(struct mdev_device *mdev)
> {
> return mdev->device_ops;
> diff --git a/include/linux/mdev.h b/include/linux/mdev.h
> index 3d29e09e20c9..13e045e09d3b 100644
> --- a/include/linux/mdev.h
> +++ b/include/linux/mdev.h
> @@ -17,6 +17,7 @@
>
> struct mdev_device;
> struct vfio_mdev_device_ops;
> +struct virtio_mdev_device_ops;
>
> /*
> * Called by the parent device driver to set the device which represents
> @@ -111,6 +112,8 @@ void mdev_set_drvdata(struct mdev_device *mdev, void
> *data);
> const guid_t *mdev_uuid(struct mdev_device *mdev);
> void mdev_set_vfio_ops(struct mdev_device *mdev,
> const struct vfio_mdev_device_ops *vfio_ops);
> +void mdev_set_virtio_ops(struct mdev_device *mdev,
> + const struct virtio_mdev_device_ops *virtio_ops);
> const void *mdev_get_dev_ops(struct mdev_device *mdev);
>
> extern struct bus_type mdev_bus_type;
> @@ -127,6 +130,7 @@ struct mdev_device *mdev_from_dev(struct device *dev);
>
> enum {
> MDEV_CLASS_ID_VFIO = 1,
> + MDEV_CLASS_ID_VIRTIO = 2,
> /* New entries must be added here */
> };
>
> diff --git a/include/linux/virtio_mdev.h b/include/linux/virtio_mdev.h
> new file mode 100644
> index ..b965b50f9b24
> --- /dev/null
> +++ b/include/linux/virtio_mdev.h
> @@ -0,0 +1,151 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Virtio mediated device driver
> + *
> + * Copyright 2019, Red Hat Corp.
> + * Author: Jason Wang
> + */
> +#ifndef _LINUX_VIRTIO_MDEV_H
> +#define _LINUX_VIRTIO_MDEV_H
> +
> +#include
> +#include
> +#include
> +
> +#define VIRTIO_MDEV_DEVICE_API_STRING"virtio-mdev"
> +#define VIRTIO_MDEV_F_VERSION_1 0x1
> +
> +struct virtio_mdev_callback {
> + irqreturn_t (*callback)(void *data);
> + void *private;
> +};
> +
> +/**
> + * struct vfio_mdev_device_ops - Structure to be registered for each
> + * mdev device to register the device to virtio-mdev module.
> + *
> + * @set_vq_address: Set the address of virtqueue
> + * @mdev: mediated device
> + * @idx: virtqueue index
> + * @desc_area: address of desc area
> + * @driver_area: address of driver area
> + * @device_area: address of device area
> + * Returns integer: success (0) or error (< 0)
> + * @set_vq_num: Set the size of virtqueue
> + * @mdev: mediated device
> + * @idx: virtqueue index
> + * @num: the size of virtqueue
> + * @kick_vq: Kick the virtqueue
> + * @mdev: mediated device
> + * @idx: virtqueue index
> + * @set_vq_cb: Set the interrupt callback function for
> + * a virtqueue
> + * @mdev: mediated device
> + * @idx: virtqueue index
> + * @cb: virtio-mdev interrupt callback structure
> + * @set_vq_ready:Set ready status for a virtqueue
> + * @mdev: mediated device
> + * @idx: virtqueue index
> + * @ready: ready (true) not ready(false)
> + * @get_vq_ready:Get ready status for a virtqueue
> + * @mdev: mediated device
> + * @idx: virtqueue index
> + * Returns boolean: ready (true) or not (false)
> + * @set_vq_state:Set the state for a virtqueu
Re: [Intel-gfx] [PATCH V4 3/6] mdev: introduce device specific ops
On Thu, 17 Oct 2019 17:07:55 +0200 Cornelia Huck wrote: > On Thu, 17 Oct 2019 18:48:33 +0800 > Jason Wang wrote: > > > Currently, except for the create and remove, the rest of > > mdev_parent_ops is designed for vfio-mdev driver only and may not help > > for kernel mdev driver. With the help of class id, this patch > > introduces device specific callbacks inside mdev_device > > structure. This allows different set of callback to be used by > > vfio-mdev and virtio-mdev. > > > > Signed-off-by: Jason Wang > > --- > > .../driver-api/vfio-mediated-device.rst | 25 + > > MAINTAINERS | 1 + > > drivers/gpu/drm/i915/gvt/kvmgt.c | 18 --- > > drivers/s390/cio/vfio_ccw_ops.c | 18 --- > > drivers/s390/crypto/vfio_ap_ops.c | 14 +++-- > > drivers/vfio/mdev/mdev_core.c | 18 +-- > > drivers/vfio/mdev/mdev_private.h | 1 + > > drivers/vfio/mdev/vfio_mdev.c | 37 ++--- > > include/linux/mdev.h | 45 > > include/linux/vfio_mdev.h | 52 +++ > > samples/vfio-mdev/mbochs.c| 20 --- > > samples/vfio-mdev/mdpy.c | 20 --- > > samples/vfio-mdev/mtty.c | 18 --- > > 13 files changed, 184 insertions(+), 103 deletions(-) > > create mode 100644 include/linux/vfio_mdev.h > > > > diff --git a/Documentation/driver-api/vfio-mediated-device.rst > > b/Documentation/driver-api/vfio-mediated-device.rst > > index f9a78d75a67a..0cca84d19603 100644 > > --- a/Documentation/driver-api/vfio-mediated-device.rst > > +++ b/Documentation/driver-api/vfio-mediated-device.rst > > @@ -152,11 +152,22 @@ callbacks per mdev parent device, per mdev type, or > > any other categorization. > > Vendor drivers are expected to be fully asynchronous in this respect or > > provide their own internal resource protection.) > > > > -The callbacks in the mdev_parent_ops structure are as follows: > > - > > -* open: open callback of mediated device > > -* close: close callback of mediated device > > -* ioctl: ioctl callback of mediated device > > +As multiple types of mediated devices may be supported, the device > > +must set up the class id and the device specific callbacks in create() > > s/in create()/in the create()/ > > > +callback. E.g for vfio-mdev device it needs to be done through: > > "Each class provides a helper function to do so; e.g. for vfio-mdev > devices, the function to be called is:" > > ? > > > + > > +int mdev_set_vfio_ops(struct mdev_device *mdev, > > + const struct vfio_mdev_ops *vfio_ops); > > + > > +The class id (set to MDEV_CLASS_ID_VFIO) is used to match a device > > "(set by this helper function to MDEV_CLASS_ID_VFIO)" ? > > > +with an mdev driver via its id table. The device specific callbacks > > +(specified in *ops) are obtainable via mdev_get_dev_ops() (for use by > > "(specified in *vfio_ops by the caller)" ? > > > +the mdev bus driver). A vfio-mdev device (class id MDEV_CLASS_ID_VFIO) > > +uses the following device-specific ops: > > + > > +* open: open callback of vfio mediated device > > +* close: close callback of vfio mediated device > > +* ioctl: ioctl callback of vfio mediated device > > * read : read emulation callback > > * write: write emulation callback > > * mmap: mmap emulation callback > > @@ -167,10 +178,6 @@ register itself with the mdev core driver:: > > extern int mdev_register_device(struct device *dev, > > const struct mdev_parent_ops *ops); > > > > -It is also required to specify the class_id in create() callback through:: > > - > > - int mdev_set_class(struct mdev_device *mdev, u16 id); > > - > > I'm wondering if this patch set should start out with introducing > helper functions already (i.e. don't introduce mdev_set_class(), but > start out with mdev_set_class_vfio() which will gain the *vfio_ops > argument in this patch.) Yes, it would be cleaner, but is it really worth the churn? Correct me if I'm wrong, but I think we get to the same point after this patch and aside from the function name itself, the difference is really just that the class_id is briefly exposed to the parent driver, right? Thanks, Alex > > However, the mdev_parent_ops structure is not required in the function call > > that a driver should use to unregister itself with the mdev core driver:: > > > > (...) > > > diff --git a/drivers/vfio/mdev/mdev_core.c b/drivers/vfio/mdev/mdev_core.c > > index 3a9c52d71b4e..d0f3113c8071 100644 > > --- a/drivers/vfio/mdev/mdev_core.c > > +++ b/drivers/vfio/mdev/mdev_core.c > > @@ -45,15 +45,23 @@ void mdev_set_drvdata(struct mdev_device *mdev, void > > *data) > > } > > EXPORT_SYMBOL(mdev_set_drvdata); > > > > -/* Specify the class for the mdev device, this must be called during > >
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for mdev based hardware virtio offloading support (rev5)
== Series Details == Series: mdev based hardware virtio offloading support (rev5) URL : https://patchwork.freedesktop.org/series/66989/ State : warning == Summary == $ dim checkpatch origin/drm-tip 2d2711d83299 mdev: class id support 335f12f84dd7 modpost: add support for mdev class id 1c27243b07bd mdev: introduce device specific ops -:468: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #468: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 590 lines checked 0cf5dbea3c83 mdev: introduce virtio device and its device ops -:25: WARNING:AVOID_BUG: Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON() #25: FILE: drivers/vfio/mdev/mdev_core.c:66: + BUG_ON(mdev->class_id); -:51: ERROR:CODE_INDENT: code indent should use tabs where possible #51: FILE: include/linux/mdev.h:116: + const struct virtio_mdev_device_ops *virtio_ops);$ -:51: WARNING:LEADING_SPACE: please, no spaces at the start of a line #51: FILE: include/linux/mdev.h:116: + const struct virtio_mdev_device_ops *virtio_ops);$ -:64: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #64: new file mode 100644 -:155: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #155: FILE: include/linux/virtio_mdev.h:87: + * @get_status: ^I^IGet the device status$ -:158: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #158: FILE: include/linux/virtio_mdev.h:90: + * @set_status: ^I^ISet the device status$ -:161: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #161: FILE: include/linux/virtio_mdev.h:93: + * @get_config: ^I^IRead from device specific configuration space$ -:168: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #168: FILE: include/linux/virtio_mdev.h:100: + * @set_config: ^I^IWrite to device specific configuration space$ total: 1 errors, 7 warnings, 0 checks, 191 lines checked 7566405601ce virtio: introduce a mdev based transport -:26: WARNING:CONFIG_DESCRIPTION: please write a paragraph that describes the config symbol fully #26: FILE: drivers/virtio/Kconfig:46: +config VIRTIO_MDEV_DEVICE -:46: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #46: new file mode 100644 -:106: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned' #106: FILE: drivers/virtio/virtio_mdev.c:56: +static void virtio_mdev_get(struct virtio_device *vdev, unsigned offset, -:107: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned' #107: FILE: drivers/virtio/virtio_mdev.c:57: + void *buf, unsigned len) -:115: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned' #115: FILE: drivers/virtio/virtio_mdev.c:65: +static void virtio_mdev_set(struct virtio_device *vdev, unsigned offset, -:116: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned' #116: FILE: drivers/virtio/virtio_mdev.c:66: + const void *buf, unsigned len) -:183: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned' #183: FILE: drivers/virtio/virtio_mdev.c:133: +virtio_mdev_setup_vq(struct virtio_device *vdev, unsigned index, -:262: CHECK:BRACES: Blank lines aren't necessary before a close brace '}' #262: FILE: drivers/virtio/virtio_mdev.c:212: + +} -:294: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned' #294: FILE: drivers/virtio/virtio_mdev.c:244: +static int virtio_mdev_find_vqs(struct virtio_device *vdev, unsigned nvqs, total: 0 errors, 8 warnings, 1 checks, 426 lines checked 5dd612418610 docs: sample driver to demonstrate how to implement virtio-mdev framework -:39: WARNING:CONFIG_DESCRIPTION: please write a paragraph that describes the config symbol fully #39: FILE: samples/Kconfig:134: +config SAMPLE_VIRTIO_MDEV_NET -:59: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #59: new file mode 100644 -:147: CHECK:UNCOMMENTED_DEFINITION: spinlock_t definition without comment #147: FILE: samples/vfio-mdev/mvnet.c:84: + spinlock_t lock; -:180: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #180: FILE: samples/vfio-mdev/mvnet.c:117: + vringh_init_kern(&vq->vring, mvnet_features, MVNET_QUEUE_MAX, + false, 0, 0, 0); -:285: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "!addr" #285: FILE: samples/vfio-mdev/mvnet.c:222: + if (addr == NULL) -:288: CHECK:SPACING: No space is necessary after a cast #288: FILE: samples/vfio-mdev/mvnet.c:225: + *dma_addr = (dma_addr_t) addr; -:318: CHECK:ALLOC_SIZEOF_STRUCT: Prefer kzalloc(sizeof(*mvnet)...) over kzalloc(sizeof(struct mvnet_state)...) #318: FILE: samples/vfio-mdev/mvnet.c:255: + mvnet = kzalloc(sizeof(struct mvnet_state), GFP_KERNEL); -:319: CHECK:COMPARISON_TO_NULL: Comparison to NULL
[Intel-gfx] [PATCH 2/4] drm/i915: enumerate and init each supported region
From: Abdiel Janulgue
Nothing to enumerate yet...
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_drv.h | 5 ++
drivers/gpu/drm/i915/i915_gem_gtt.c | 56 ---
drivers/gpu/drm/i915/intel_memory_region.h| 4 ++
.../gpu/drm/i915/selftests/mock_gem_device.c | 6 ++
4 files changed, 64 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2dab731c1e80..b983187b45cf 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -684,6 +684,8 @@ struct i915_gem_mm {
*/
struct vfsmount *gemfs;
+ struct intel_memory_region *regions[INTEL_REGION_UNKNOWN];
+
struct notifier_block oom_notifier;
struct notifier_block vmap_notifier;
struct shrinker shrinker;
@@ -2003,6 +2005,9 @@ int __must_check i915_gem_evict_for_node(struct
i915_address_space *vm,
unsigned int flags);
int i915_gem_evict_vm(struct i915_address_space *vm);
+void i915_gem_cleanup_memory_regions(struct drm_i915_private *i915);
+int i915_gem_init_memory_regions(struct drm_i915_private *i915);
+
/* i915_gem_internal.c */
struct drm_i915_gem_object *
i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 7b15bb891970..7b8e30c72f86 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2744,6 +2744,52 @@ int i915_init_ggtt(struct drm_i915_private *i915)
return 0;
}
+void i915_gem_cleanup_memory_regions(struct drm_i915_private *i915)
+{
+ int i;
+
+ i915_gem_cleanup_stolen(i915);
+
+ for (i = 0; i < INTEL_REGION_UNKNOWN; i++) {
+ struct intel_memory_region *region = i915->mm.regions[i];
+
+ if (region)
+ intel_memory_region_put(region);
+ }
+}
+
+int i915_gem_init_memory_regions(struct drm_i915_private *i915)
+{
+ int err, i;
+
+ /*
+* Initialise stolen early so that we may reserve preallocated
+* objects for the BIOS to KMS transition.
+*/
+ /* XXX: stolen will become a region at some point */
+ err = i915_gem_init_stolen(i915);
+ if (err)
+ return err;
+
+ for (i = 0; i < INTEL_REGION_UNKNOWN; i++) {
+ struct intel_memory_region *mem = ERR_PTR(-ENODEV);
+
+ if (!HAS_REGION(i915, BIT(i)))
+ continue;
+
+ if (IS_ERR(mem)) {
+ err = PTR_ERR(mem);
+ goto out_cleanup;
+ }
+ }
+
+ return 0;
+
+out_cleanup:
+ i915_gem_cleanup_memory_regions(i915);
+ return err;
+}
+
static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
{
struct i915_vma *vma, *vn;
@@ -2781,6 +2827,8 @@ void i915_ggtt_driver_release(struct drm_i915_private
*i915)
{
struct pagevec *pvec;
+ i915_gem_cleanup_memory_regions(i915);
+
fini_aliasing_ppgtt(&i915->ggtt);
ggtt_cleanup_hw(&i915->ggtt);
@@ -2790,8 +2838,6 @@ void i915_ggtt_driver_release(struct drm_i915_private
*i915)
set_pages_array_wb(pvec->pages, pvec->nr);
__pagevec_release(pvec);
}
-
- i915_gem_cleanup_stolen(i915);
}
static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
@@ -3240,11 +3286,7 @@ int i915_ggtt_init_hw(struct drm_i915_private *dev_priv)
if (ret)
return ret;
- /*
-* Initialise stolen early so that we may reserve preallocated
-* objects for the BIOS to KMS transition.
-*/
- ret = i915_gem_init_stolen(dev_priv);
+ ret = i915_gem_init_memory_regions(dev_priv);
if (ret)
goto out_gtt_cleanup;
diff --git a/drivers/gpu/drm/i915/intel_memory_region.h
b/drivers/gpu/drm/i915/intel_memory_region.h
index 52c141b6108c..2c165a7a5ab4 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.h
+++ b/drivers/gpu/drm/i915/intel_memory_region.h
@@ -18,6 +18,10 @@ struct drm_i915_gem_object;
struct intel_memory_region;
struct sg_table;
+enum intel_region_id {
+ INTEL_REGION_UNKNOWN = 0, /* Should be last */
+};
+
#define I915_ALLOC_MIN_PAGE_SIZE BIT(0)
#define I915_ALLOC_CONTIGUOUS BIT(1)
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 9c22d41b30cd..bc5e3c67409f 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -74,6 +74,8 @@ static void mock_device_release(struct drm_device *dev)
i915_gemfs_fini(i915);
+ i915_gem_cleanup_memory_regions(i915);
+
drm_mode_config_cleanup(&i915->drm);
drm_dev_fini(&i915->drm);
@@ -196,6 +198,10 @@ s
[Intel-gfx] [PATCH 1/4] drm/i915: Add memory region information to device_info
From: Abdiel Janulgue
Exposes available regions for the platform. Needed in later patches.
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_device_info.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 88956f37d96c..2dab731c1e80 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1783,6 +1783,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
+#define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
+
#define HAS_GT_UC(dev_priv)(INTEL_INFO(dev_priv)->has_gt_uc)
/* Having GuC is not the same as using GuC */
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 0cdc2465534b..e9940f932d26 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -160,6 +160,8 @@ struct intel_device_info {
unsigned int page_sizes; /* page sizes supported by the HW */
+ u32 memory_regions; /* regions supported by the HW */
+
u32 display_mmio_offset;
u8 pipe_mask;
--
2.20.1
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[Intel-gfx] [PATCH 4/4] drm/i915: treat stolen as a region
Convert stolen memory over to a region object. Still leaves open the
question with what to do with pre-allocated objects...
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 65 +++---
drivers/gpu/drm/i915/gem/i915_gem_stolen.h | 3 +-
drivers/gpu/drm/i915/i915_gem_gtt.c| 14 +
drivers/gpu/drm/i915/i915_pci.c| 2 +-
4 files changed, 61 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index c76260ce13e3..0b6c45edbf96 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -10,6 +10,7 @@
#include
#include
+#include "gem/i915_gem_region.h"
#include "i915_drv.h"
#include "i915_gem_stolen.h"
@@ -150,7 +151,7 @@ static int i915_adjust_stolen(struct drm_i915_private
*dev_priv,
return 0;
}
-void i915_gem_cleanup_stolen(struct drm_i915_private *dev_priv)
+static void i915_gem_cleanup_stolen(struct drm_i915_private *dev_priv)
{
if (!drm_mm_initialized(&dev_priv->mm.stolen))
return;
@@ -355,7 +356,7 @@ static void icl_get_stolen_reserved(struct drm_i915_private
*i915,
}
}
-int i915_gem_init_stolen(struct drm_i915_private *dev_priv)
+static int i915_gem_init_stolen(struct drm_i915_private *dev_priv)
{
resource_size_t reserved_base, stolen_top;
resource_size_t reserved_total, reserved_size;
@@ -539,6 +540,9 @@ i915_gem_object_release_stolen(struct drm_i915_gem_object
*obj)
i915_gem_stolen_remove_node(dev_priv, stolen);
kfree(stolen);
+
+ if (obj->mm.region)
+ i915_gem_object_release_memory_region(obj);
}
static const struct drm_i915_gem_object_ops i915_gem_object_stolen_ops = {
@@ -548,8 +552,9 @@ static const struct drm_i915_gem_object_ops
i915_gem_object_stolen_ops = {
};
static struct drm_i915_gem_object *
-_i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
- struct drm_mm_node *stolen)
+__i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
+ struct drm_mm_node *stolen,
+ struct intel_memory_region *mem)
{
struct drm_i915_gem_object *obj;
unsigned int cache_level;
@@ -571,6 +576,9 @@ _i915_gem_object_create_stolen(struct drm_i915_private
*dev_priv,
if (err)
goto cleanup;
+ if (mem)
+ i915_gem_object_init_memory_region(obj, mem, 0);
+
return obj;
cleanup:
@@ -579,10 +587,12 @@ _i915_gem_object_create_stolen(struct drm_i915_private
*dev_priv,
return ERR_PTR(err);
}
-struct drm_i915_gem_object *
-i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
- resource_size_t size)
+static struct drm_i915_gem_object *
+_i915_gem_object_create_stolen(struct intel_memory_region *mem,
+ resource_size_t size,
+ unsigned int flags)
{
+ struct drm_i915_private *dev_priv = mem->i915;
struct drm_i915_gem_object *obj;
struct drm_mm_node *stolen;
int ret;
@@ -603,7 +613,7 @@ i915_gem_object_create_stolen(struct drm_i915_private
*dev_priv,
goto err_free;
}
- obj = _i915_gem_object_create_stolen(dev_priv, stolen);
+ obj = __i915_gem_object_create_stolen(dev_priv, stolen, mem);
if (IS_ERR(obj))
goto err_remove;
@@ -616,6 +626,43 @@ i915_gem_object_create_stolen(struct drm_i915_private
*dev_priv,
return obj;
}
+struct drm_i915_gem_object *
+i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
+ resource_size_t size)
+{
+ return
i915_gem_object_create_region(dev_priv->mm.regions[INTEL_REGION_STOLEN],
+size, I915_BO_ALLOC_CONTIGUOUS);
+}
+
+static int init_stolen(struct intel_memory_region *mem)
+{
+ /*
+* Initialise stolen early so that we may reserve preallocated
+* objects for the BIOS to KMS transition.
+*/
+ return i915_gem_init_stolen(mem->i915);
+}
+
+static void release_stolen(struct intel_memory_region *mem)
+{
+ i915_gem_cleanup_stolen(mem->i915);
+}
+
+static const struct intel_memory_region_ops i915_region_stolen_ops = {
+ .init = init_stolen,
+ .release = release_stolen,
+ .create_object = _i915_gem_object_create_stolen,
+};
+
+struct intel_memory_region *i915_gem_stolen_setup(struct drm_i915_private
*i915)
+{
+ return intel_memory_region_create(i915,
+ intel_graphics_stolen_res.start,
+
resource_size(&intel_graphics_stolen_res),
+ I915_GTT_PAGE_SIZE_4K, 0,
+
[Intel-gfx] [PATCH 3/4] drm/i915: treat shmem as a region
Convert shmem to an intel_memory_region.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
---
drivers/gpu/drm/i915/gem/i915_gem_phys.c | 5 +-
drivers/gpu/drm/i915/gem/i915_gem_region.c| 7 +-
drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 74 ++-
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_gem.c | 9 ---
drivers/gpu/drm/i915/i915_gem_gtt.c | 15
drivers/gpu/drm/i915/i915_pci.c | 29 ++--
drivers/gpu/drm/i915/intel_memory_region.c| 10 +++
drivers/gpu/drm/i915/intel_memory_region.h| 28 ++-
.../gpu/drm/i915/selftests/mock_gem_device.c | 7 +-
10 files changed, 143 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_phys.c
b/drivers/gpu/drm/i915/gem/i915_gem_phys.c
index 768356908160..8043ff63d73f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_phys.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_phys.c
@@ -16,6 +16,7 @@
#include "gt/intel_gt.h"
#include "i915_drv.h"
#include "i915_gem_object.h"
+#include "i915_gem_region.h"
#include "i915_scatterlist.h"
static int i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
@@ -191,8 +192,10 @@ int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj, int align)
/* Perma-pin (until release) the physical set of pages */
__i915_gem_object_pin_pages(obj);
- if (!IS_ERR_OR_NULL(pages))
+ if (!IS_ERR_OR_NULL(pages)) {
i915_gem_shmem_ops.put_pages(obj, pages);
+ i915_gem_object_release_memory_region(obj);
+ }
mutex_unlock(&obj->mm.lock);
return 0;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c
b/drivers/gpu/drm/i915/gem/i915_gem_region.c
index d3f7733bc7ed..2f7bcfb9c964 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
@@ -6,6 +6,7 @@
#include "intel_memory_region.h"
#include "i915_gem_region.h"
#include "i915_drv.h"
+#include "i915_trace.h"
void
i915_gem_object_put_pages_buddy(struct drm_i915_gem_object *obj,
@@ -165,5 +166,9 @@ i915_gem_object_create_region(struct intel_memory_region
*mem,
if (overflows_type(size, obj->base.size))
return ERR_PTR(-E2BIG);
- return mem->ops->create_object(mem, size, flags);
+ obj = mem->ops->create_object(mem, size, flags);
+ if (!IS_ERR(obj))
+ trace_i915_gem_object_create(obj);
+
+ return obj;
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
index 4c4954e8ce0a..c3bde41de505 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
@@ -7,7 +7,9 @@
#include
#include
+#include "gem/i915_gem_region.h"
#include "i915_drv.h"
+#include "i915_gemfs.h"
#include "i915_gem_object.h"
#include "i915_scatterlist.h"
#include "i915_trace.h"
@@ -26,6 +28,7 @@ static void check_release_pagevec(struct pagevec *pvec)
static int shmem_get_pages(struct drm_i915_gem_object *obj)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
+ struct intel_memory_region *mem = obj->mm.region;
const unsigned long page_count = obj->base.size / PAGE_SIZE;
unsigned long i;
struct address_space *mapping;
@@ -52,7 +55,7 @@ static int shmem_get_pages(struct drm_i915_gem_object *obj)
* If there's no chance of allocating enough pages for the whole
* object, bail early.
*/
- if (page_count > totalram_pages())
+ if (obj->base.size > resource_size(&mem->region))
return -ENOMEM;
st = kmalloc(sizeof(*st), GFP_KERNEL);
@@ -417,6 +420,8 @@ shmem_pwrite(struct drm_i915_gem_object *obj,
static void shmem_release(struct drm_i915_gem_object *obj)
{
+ i915_gem_object_release_memory_region(obj);
+
fput(obj->base.filp);
}
@@ -434,9 +439,9 @@ const struct drm_i915_gem_object_ops i915_gem_shmem_ops = {
.release = shmem_release,
};
-static int create_shmem(struct drm_i915_private *i915,
- struct drm_gem_object *obj,
- size_t size)
+static int __create_shmem(struct drm_i915_private *i915,
+ struct drm_gem_object *obj,
+ size_t size)
{
unsigned long flags = VM_NORESERVE;
struct file *filp;
@@ -455,31 +460,23 @@ static int create_shmem(struct drm_i915_private *i915,
return 0;
}
-struct drm_i915_gem_object *
-i915_gem_object_create_shmem(struct drm_i915_private *i915, u64 size)
+static struct drm_i915_gem_object *
+create_shmem(struct intel_memory_region *mem,
+resource_size_t size,
+unsigned int flags)
{
+ struct drm_i915_private *i915 = mem->i915;
struct drm_i915_gem_object *obj;
struct address_space *mapping;
unsigned int cache_level;
gfp_t mask;
int
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v3,1/3] drm/i915: Add microcontrollers documentation section
On 10/14/19 3:04 PM, Patchwork wrote:
== Series Details ==
Series: series starting with [v3,1/3] drm/i915: Add microcontrollers
documentation section
URL : https://patchwork.freedesktop.org/series/67986/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7090 -> Patchwork_14796
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14796 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14796, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14796/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14796:
### IGT changes ###
Possible regressions
* igt@runner@aborted:
- fi-bsw-kefka: NOTRUN -> [FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14796/fi-bsw-kefka/igt@run...@aborted.html
Unrelated lockep error:
<4>[8.389133]CPU0CPU1
<4>[8.389139]
<4>[8.389144] lock(&vm->mutex);
<4>[8.389150]lock(fs_reclaim);
<4>[8.389157]lock(&vm->mutex);
<4>[8.389164] lock(cpu_hotplug_lock.rw_sem);
BAT is enough since the series only changed comments, so pushed. I'm not
seeing the lockdep splat on more recent runs, was it already fixed or do
we need an fdo?
Daniele
Known issues
Here are the changes found in Patchwork_14796 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u3: [PASS][2] -> [DMESG-WARN][3] ([fdo#107724]) +2
similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7090/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14796/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
Possible fixes
* igt@gem_ctx_switch@legacy-render:
- fi-bxt-dsi: [INCOMPLETE][4] ([fdo#103927] / [fdo#111381]) ->
[PASS][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7090/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14796/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
* igt@gem_mmap_gtt@basic-write-gtt:
- fi-icl-u3: [DMESG-WARN][6] ([fdo#107724]) -> [PASS][7] +1
similar issue
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7090/fi-icl-u3/igt@gem_mmap_...@basic-write-gtt.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14796/fi-icl-u3/igt@gem_mmap_...@basic-write-gtt.html
* igt@gem_ringfill@basic-default-fd:
- {fi-icl-dsi}: [DMESG-WARN][8] ([fdo#106107]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7090/fi-icl-dsi/igt@gem_ringf...@basic-default-fd.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14796/fi-icl-dsi/igt@gem_ringf...@basic-default-fd.html
* igt@kms_busy@basic-flip-a:
- {fi-tgl-u2}:[DMESG-WARN][10] ([fdo#111600]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7090/fi-tgl-u2/igt@kms_b...@basic-flip-a.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14796/fi-tgl-u2/igt@kms_b...@basic-flip-a.html
* igt@kms_chamelium@dp-crc-fast:
- fi-icl-u2: [FAIL][12] ([fdo#109635 ] / [fdo#110387]) ->
[PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7090/fi-icl-u2/igt@kms_chamel...@dp-crc-fast.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14796/fi-icl-u2/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-blb-e6850: [INCOMPLETE][14] ([fdo#107718]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7090/fi-blb-e6850/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14796/fi-blb-e6850/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][16] ([fdo#111407]) -> [FAIL][17]
([fdo#111045] / [fdo#111096])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7090/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14796/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#106107]: http
Re: [Intel-gfx] [PATCH] drm/i915/selftests: Teach requests to use all available engines
On 16/10/2019 13:52, Chris Wilson wrote:
The request selftests straddle the boundary between checking the driver
and the hardware. They are subject to the quirks of the underlying HW,
but operate on top of the backend abstractions. The tests focus on the
scheduler elements and so should check for interactions of the scheduler
across all exposed engines.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/selftests/i915_request.c | 276 +++---
1 file changed, 170 insertions(+), 106 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c
b/drivers/gpu/drm/i915/selftests/i915_request.c
index 0897a7b04944..b95a0e8431ab 100644
--- a/drivers/gpu/drm/i915/selftests/i915_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_request.c
@@ -37,6 +37,18 @@
#include "mock_drm.h"
#include "mock_gem_device.h"
+static unsigned int num_uabi_engines(struct drm_i915_private *i915)
+{
+ struct intel_engine_cs *engine;
+ unsigned int count;
+
+ count = 0;
+ for_each_uabi_engine(engine, i915)
+ count++;
+
+ return count;
+}
+
static int igt_add_request(void *arg)
{
struct drm_i915_private *i915 = arg;
@@ -511,15 +523,15 @@ static int live_nop_request(void *arg)
struct drm_i915_private *i915 = arg;
struct intel_engine_cs *engine;
struct igt_live_test t;
- unsigned int id;
int err = -ENODEV;
- /* Submit various sized batches of empty requests, to each engine
+ /*
+* Submit various sized batches of empty requests, to each engine
* (individually), and wait for the batch to complete. We can check
* the overhead of submitting requests to the hardware.
*/
- for_each_engine(engine, i915, id) {
+ for_each_uabi_engine(engine, i915) {
unsigned long n, prime;
IGT_TIMEOUT(end_time);
ktime_t times[2] = {};
@@ -539,7 +551,8 @@ static int live_nop_request(void *arg)
if (IS_ERR(request))
return PTR_ERR(request);
-/* This space is left intentionally blank.
+ /*
+* This space is left intentionally blank.
*
* We do not actually want to perform any
* action with this request, we just want
@@ -657,10 +670,10 @@ static int live_empty_request(void *arg)
struct intel_engine_cs *engine;
struct igt_live_test t;
struct i915_vma *batch;
- unsigned int id;
int err = 0;
- /* Submit various sized batches of empty requests, to each engine
+ /*
+* Submit various sized batches of empty requests, to each engine
* (individually), and wait for the batch to complete. We can check
* the overhead of submitting requests to the hardware.
*/
@@ -669,7 +682,7 @@ static int live_empty_request(void *arg)
if (IS_ERR(batch))
return PTR_ERR(batch);
- for_each_engine(engine, i915, id) {
+ for_each_uabi_engine(engine, i915) {
IGT_TIMEOUT(end_time);
struct i915_request *request;
unsigned long n, prime;
@@ -801,63 +814,73 @@ static int recursive_batch_resolve(struct i915_vma *batch)
static int live_all_engines(void *arg)
{
struct drm_i915_private *i915 = arg;
+ const unsigned int nengines = num_uabi_engines(i915);
struct intel_engine_cs *engine;
- struct i915_request *request[I915_NUM_ENGINES];
+ struct i915_request **request;
struct igt_live_test t;
struct i915_vma *batch;
- unsigned int id;
+ unsigned int idx;
int err;
- /* Check we can submit requests to all engines simultaneously. We
+ /*
+* Check we can submit requests to all engines simultaneously. We
* send a recursive batch to each engine - checking that we don't
* block doing so, and that they don't complete too soon.
*/
+ request = kmalloc_array(nengines, sizeof(*request), GFP_KERNEL);
__GFP_ZERO as live_sequential for error unwind to work, I think.
+ if (!request)
+ return -ENOMEM;
+
err = igt_live_test_begin(&t, i915, __func__, "");
if (err)
- return err;
+ goto out_free;
batch = recursive_batch(i915);
if (IS_ERR(batch)) {
err = PTR_ERR(batch);
pr_err("%s: Unable to create batch, err=%d\n", __func__, err);
- return err;
+ goto out_free;
}
- for_each_engine(engine, i915, id) {
- request[id] = i915_request_create(engine->kernel_context);
- if (IS_ERR(request[id])) {
- err = PTR_ERR(request[id]);
+ idx = 0;
+ for_each_uabi_engine(engi
[Intel-gfx] [CI] drm/i915/execlists: Don't merely skip submission if maybe timeslicing
Normally, we try and skip submission if ELSP[1] is filled. However, we
may desire to enable timeslicing due to the queue priority, even if
ELSP[1] itself does not require timeslicing. That is the queue is equal
priority to ELSP[0] and higher priority then ELSP[1]. Previously, we
would wait until the context switch to preempt the current ELSP[1], but
with timeslicing, we want to preempt ELSP[0] and replace it with the
queue.
In writing the test case, it become quickly apparent that we were also
suppressing the tasklet during promotion and so failing to notice when
the queue started requiring timeslicing.
Fixes: 2229adc81380 ("drm/i915/execlist: Trim immediate timeslice expiry")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_lrc.c| 22 +++-
drivers/gpu/drm/i915/gt/selftest_lrc.c | 165 -
drivers/gpu/drm/i915/i915_scheduler.c | 17 ++-
drivers/gpu/drm/i915/i915_scheduler.h | 18 ---
4 files changed, 193 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index e9fe9f79cedd..d0088d020220 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -352,10 +352,15 @@ static inline bool need_preempt(const struct
intel_engine_cs *engine,
* However, the priority hint is a mere hint that we may need to
* preempt. If that hint is stale or we may be trying to preempt
* ourselves, ignore the request.
+*
+* More naturally we would write
+* prio >= max(0, last);
+* except that we wish to prevent triggering preemption at the same
+* priority level: the task that is running should remain running
+* to preserve FIFO ordering of dependencies.
*/
- last_prio = effective_prio(rq);
- if (!i915_scheduler_need_preempt(engine->execlists.queue_priority_hint,
-last_prio))
+ last_prio = max(effective_prio(rq), I915_PRIORITY_NORMAL - 1);
+ if (engine->execlists.queue_priority_hint <= last_prio)
return false;
/*
@@ -1509,8 +1514,17 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
* submission.
*/
if (!list_is_last(&last->sched.link,
- &engine->active.requests))
+ &engine->active.requests)) {
+ /*
+* Even if ELSP[1] is occupied and not worthy
+* of timeslices, our queue might be.
+*/
+ if (!execlists->timer.expires &&
+ need_timeslice(engine, last))
+ mod_timer(&execlists->timer,
+ jiffies + 1);
return;
+ }
/*
* WaIdleLiteRestore:bdw,skl
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 2868371c609e..7e79a05e653f 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -325,7 +325,13 @@ semaphore_queue(struct intel_engine_cs *engine, struct
i915_vma *vma, int idx)
if (IS_ERR(rq))
goto out_ctx;
- err = emit_semaphore_chain(rq, vma, idx);
+ err = 0;
+ if (rq->engine->emit_init_breadcrumb)
+ err = rq->engine->emit_init_breadcrumb(rq);
+ if (err == 0)
+ err = emit_semaphore_chain(rq, vma, idx);
+ if (err == 0)
+ i915_request_get(rq);
i915_request_add(rq);
if (err)
rq = ERR_PTR(err);
@@ -338,10 +344,10 @@ semaphore_queue(struct intel_engine_cs *engine, struct
i915_vma *vma, int idx)
static int
release_queue(struct intel_engine_cs *engine,
struct i915_vma *vma,
- int idx)
+ int idx, int prio)
{
struct i915_sched_attr attr = {
- .priority = I915_USER_PRIORITY(I915_PRIORITY_MAX),
+ .priority = prio,
};
struct i915_request *rq;
u32 *cs;
@@ -362,9 +368,15 @@ release_queue(struct intel_engine_cs *engine,
*cs++ = 1;
intel_ring_advance(rq, cs);
+
+ i915_request_get(rq);
i915_request_add(rq);
+ local_bh_disable();
engine->schedule(rq, &attr);
+ local_bh_enable(); /* kick tasklet */
+
+ i915_request_put(rq);
return 0;
}
@@ -383,7 +395,6 @@ slice_semaphore_queue(struct intel_engine_cs *outer,
if (IS_ERR(head))
return PTR_ERR(head);
- i915_request_get(head);
for_each_engine(engine, outer->i915, id) {
for (i = 0; i < coun
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/execlists: Don't merely skip submission if maybe timeslicing (rev4)
== Series Details ==
Series: drm/i915/execlists: Don't merely skip submission if maybe timeslicing
(rev4)
URL : https://patchwork.freedesktop.org/series/68122/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7120 -> Patchwork_14856
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14856 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14856, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14856/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14856:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_execlists:
- fi-skl-6260u: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7120/fi-skl-6260u/igt@i915_selftest@live_execlists.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14856/fi-skl-6260u/igt@i915_selftest@live_execlists.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live_requests:
- {fi-tgl-u}: NOTRUN -> [INCOMPLETE][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14856/fi-tgl-u/igt@i915_selftest@live_requests.html
Known issues
Here are the changes found in Patchwork_14856 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_chamelium@dp-crc-fast:
- fi-icl-u2: [PASS][4] -> [FAIL][5] ([fdo#109635 ] / [fdo#110387])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7120/fi-icl-u2/igt@kms_chamel...@dp-crc-fast.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14856/fi-icl-u2/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][6] -> [FAIL][7] ([fdo#111045] / [fdo#111096])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7120/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14856/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [PASS][8] -> [DMESG-WARN][9] ([fdo#102614])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7120/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14856/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@gem_sync@basic-many-each:
- {fi-tgl-u2}:[INCOMPLETE][10] ([fdo#111647]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7120/fi-tgl-u2/igt@gem_s...@basic-many-each.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14856/fi-tgl-u2/igt@gem_s...@basic-many-each.html
- {fi-tgl-u}: [INCOMPLETE][12] ([fdo#111880]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7120/fi-tgl-u/igt@gem_s...@basic-many-each.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14856/fi-tgl-u/igt@gem_s...@basic-many-each.html
* igt@i915_selftest@live_execlists:
- fi-whl-u: [DMESG-FAIL][14] -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7120/fi-whl-u/igt@i915_selftest@live_execlists.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14856/fi-whl-u/igt@i915_selftest@live_execlists.html
- fi-skl-6600u: [DMESG-FAIL][16] -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7120/fi-skl-6600u/igt@i915_selftest@live_execlists.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14856/fi-skl-6600u/igt@i915_selftest@live_execlists.html
- fi-bxt-dsi: [DMESG-FAIL][18] -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7120/fi-bxt-dsi/igt@i915_selftest@live_execlists.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14856/fi-bxt-dsi/igt@i915_selftest@live_execlists.html
* igt@i915_selftest@live_requests:
- {fi-icl-guc}: [INCOMPLETE][20] ([fdo#107713] / [fdo#109644] /
[fdo#110464]) -> [PASS][21]
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7120/fi-icl-guc/igt@i915_selftest@live_requests.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14856/fi-icl-guc/igt@i915_selftest@live_requests.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108569]: https://bugs.freedeskt
[Intel-gfx] [PATCH v4 1/2] drm/i915: Make for_each_engine_masked work on intel_gt
From: Tvrtko Ursulin
Medium term goal is to eliminate the i915->engine[] array and to get there
we have recently introduced equivalent array in intel_gt. Now we need to
migrate the code further towards this state.
This next step is to eliminate usage of i915->engines[] from the
for_each_engine_masked iterator.
For this to work we also need to use engine->id as index when populating
the gt->engine[] array and adjust the default engine set indexing to use
engine->legacy_idx instead of assuming gt->engines[] indexing.
v2:
* Populate gt->engine[] earlier.
* Check that we don't duplicate engine->legacy_idx
v3:
* Work around the initialization order issue between default_engines()
and intel_engines_driver_register() which sets engine->legacy_idx for
now. It will be fixed properly later.
v4:
* Merge with forgotten v2.5.
Signed-off-by: Tvrtko Ursulin
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 13 ++---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 5 +
drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
drivers/gpu/drm/i915/gt/intel_engine_user.c | 18 +-
drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_hangcheck.c| 2 +-
drivers/gpu/drm/i915/gt/intel_reset.c| 12 ++--
drivers/gpu/drm/i915/gvt/execlist.c | 4 ++--
drivers/gpu/drm/i915/gvt/scheduler.c | 2 +-
drivers/gpu/drm/i915/i915_active.c | 4 ++--
drivers/gpu/drm/i915/i915_drv.h | 6 +++---
11 files changed, 37 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 5d8221c7ba83..7b01f4605f21 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -203,15 +203,22 @@ static struct i915_gem_engines *default_engines(struct
i915_gem_context *ctx)
for_each_engine(engine, gt, id) {
struct intel_context *ce;
+ if (engine->legacy_idx == INVALID_ENGINE)
+ continue;
+
+ GEM_BUG_ON(engine->legacy_idx >= I915_NUM_ENGINES);
+ GEM_BUG_ON(e->engines[engine->legacy_idx]);
+
ce = intel_context_create(ctx, engine);
if (IS_ERR(ce)) {
- __free_engines(e, id);
+ __free_engines(e, e->num_engines + 1);
return ERR_CAST(ce);
}
- e->engines[id] = ce;
- e->num_engines = id + 1;
+ e->engines[engine->legacy_idx] = ce;
+ e->num_engines = max(e->num_engines, engine->legacy_idx);
}
+ e->num_engines++;
return e;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 5051a1fd2565..e514c68b0713 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -277,6 +277,9 @@ static int intel_engine_setup(struct intel_gt *gt, enum
intel_engine_id id)
BUILD_BUG_ON(MAX_ENGINE_CLASS >= BIT(GEN11_ENGINE_CLASS_WIDTH));
BUILD_BUG_ON(MAX_ENGINE_INSTANCE >= BIT(GEN11_ENGINE_INSTANCE_WIDTH));
+ if (GEM_DEBUG_WARN_ON(id >= ARRAY_SIZE(gt->engine)))
+ return -EINVAL;
+
if (GEM_DEBUG_WARN_ON(info->class > MAX_ENGINE_CLASS))
return -EINVAL;
@@ -293,6 +296,7 @@ static int intel_engine_setup(struct intel_gt *gt, enum
intel_engine_id id)
BUILD_BUG_ON(BITS_PER_TYPE(engine->mask) < I915_NUM_ENGINES);
engine->id = id;
+ engine->legacy_idx = INVALID_ENGINE;
engine->mask = BIT(id);
engine->i915 = gt->i915;
engine->gt = gt;
@@ -328,6 +332,7 @@ static int intel_engine_setup(struct intel_gt *gt, enum
intel_engine_id id)
intel_engine_sanitize_mmio(engine);
gt->engine_class[info->class][info->instance] = engine;
+ gt->engine[id] = engine;
intel_engine_add_user(engine);
gt->i915->engine[id] = engine;
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 6199064f332b..3451be034caf 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -148,6 +148,7 @@ enum intel_engine_id {
VECS1,
#define _VECS(n) (VECS0 + (n))
I915_NUM_ENGINES
+#define INVALID_ENGINE ((enum intel_engine_id)-1)
};
struct st_preempt_hang {
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c
b/drivers/gpu/drm/i915/gt/intel_engine_user.c
index 77cd5de83930..7f7150a733f4 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
@@ -160,10 +160,10 @@ static int legacy_ring_idx(const struct legacy_ring *ring)
};
if (GEM_DEBUG_WARN_ON(ring->class >= ARRAY_SIZE(map)))
- return -1;
+
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Correct the PCH type in irq postinstall
On Thu, Oct 17, 2019 at 09:03:20AM -0700, Saarinen, Jani wrote:
>
>
> > -Original Message-
> > From: Intel-gfx On Behalf Of Matt
> > Roper
> > Sent: torstai 17. lokakuuta 2019 18.47
> > To: intel-gfx@lists.freedesktop.org
> > Subject: Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Correct the PCH
> > type in irq
> > postinstall
> >
> > On Thu, Oct 17, 2019 at 01:35:20AM +, Patchwork wrote:
> > > == Series Details ==
> > >
> > > Series: drm/i915: Correct the PCH type in irq postinstall
> > > URL : https://patchwork.freedesktop.org/series/68116/
> > > State : failure
> > >
> > > == Summary ==
> > >
> > > CI Bug Log - changes from CI_DRM_7114 -> Patchwork_14843
> > >
> > >
> > > Summary
> > > ---
> > >
> > > **FAILURE**
> > >
> > > Serious unknown changes coming with Patchwork_14843 absolutely need to
> > > be
> > > verified manually.
> > >
> > > If you think the reported changes have nothing to do with the changes
> > > introduced in Patchwork_14843, please notify your bug team to allow them
> > > to document this new failure mode, which will reduce false positives in
> > > CI.
> > >
> > > External URL:
> > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14843/index.html
> > >
> > > Possible new issues
> > > ---
> > >
> > > Here are the unknown changes that may have been introduced in
> > Patchwork_14843:
> > >
> > > ### IGT changes ###
> > >
> > > Possible regressions
> > >
> > > * igt@i915_selftest@live_execlists:
> > > - fi-icl-u2: [PASS][1] -> [DMESG-FAIL][2]
> > >[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7114/fi-icl-
> > u2/igt@i915_selftest@live_execlists.html
> > >[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14843/fi-icl-
> > u2/igt@i915_selftest@live_execlists.html
> > > - fi-icl-u3: [PASS][3] -> [DMESG-FAIL][4]
> > >[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7114/fi-icl-
> > u3/igt@i915_selftest@live_execlists.html
> > >[4]:
> > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14843/fi-icl-u3/igt
> > > @i915_selftest@live_execlists.html
> >
> > These appear to be a GPU hang and "i915/intel_execlists_live_selftests:
> > live_timeslice_preempt failed with error -5;" not related to the PCH fix in
> > this patch.
>
> These are seen lately on many series, don’t we have bug about these?
It matches the title of
https://bugs.freedesktop.org/show_bug.cgi?id=111872 which is already
resolved, but I don't have enough GEM insight to know if it's truly the
same root cause or not?
> >
> > >
> > > * igt@i915_selftest@live_gem_contexts:
> > > - fi-cfl-8109u: [PASS][5] -> [DMESG-FAIL][6]
> > >[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7114/fi-cfl-
> > 8109u/igt@i915_selftest@live_gem_contexts.html
> > >[6]:
> > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14843/fi-cfl-8109u/
> > > igt@i915_selftest@live_gem_contexts.html
> >
> >
> > This is some kind of a timeout during a GEM selftest
> > ("i915/i915_gem_context_live_selftests: live_parallel_switch failed with
> > error -62").
> > Errno -62 is -ETIME. Also not related to this patch.
> Same this too.
>
I don't see anything obvious in the bug list that matches this one.
Matt
>
> >
> > Will poke CI for a retest.
> >
> >
> > Matt
> >
> >
> > >
> > >
> > > Known issues
> > >
> > >
> > > Here are the changes found in Patchwork_14843 that come from known
> > > issues:
> > >
> > > ### IGT changes ###
> > >
> > > Issues hit
> > >
> > > * igt@prime_busy@basic-wait-after-default:
> > > - fi-icl-u3: [PASS][7] -> [DMESG-WARN][8] ([fdo#107724]) +2
> > > similar issues
> > >[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7114/fi-icl-
> > u3/igt@prime_b...@basic-wait-after-default.html
> > >[8]:
> > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14843/fi-icl-u3/igt
> > > @prime_b...@basic-wait-after-default.html
> > >
> > >
> > > Possible fixes
> > >
> > > * igt@gem_ctx_create@basic-files:
> > > - fi-bdw-gvtdvm: [DMESG-WARN][9] -> [PASS][10]
> > >[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7114/fi-bdw-
> > gvtdvm/igt@gem_ctx_cre...@basic-files.html
> > >[10]:
> > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14843/fi-bdw-gvtdvm
> > > /igt@gem_ctx_cre...@basic-files.html
> > >
> > > * igt@gem_flink_basic@double-flink:
> > > - fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12]
> > > +2 similar
> > issues
> > >[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7114/fi-icl-
> > u3/igt@gem_flink_ba...@double-flink.html
> > >[12]:
> > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14843/fi-icl-u3/igt
> > > @gem_flink_ba...@double-flink.html
> > >
> > > * igt@i915_selftest@live_execlists:
> > > - fi-cfl-guc: [DMESG-FAIL][13] -> [PASS][14]
> > >[13]: https://intel-
[Intel-gfx] [PATCH v3] drm/i915: Don't disable interrupts independently of the lock
The locks (active.lock and rq->lock) need to be taken with disabled
interrupts. This is done in i915_request_retire() by disabling the
interrupts independently of the locks itself.
While local_irq_disable()+spin_lock() equals spin_lock_irq() on vanilla
it does not on PREEMPT_RT.
Chris Wilson confirmed that local_irq_disable() was just introduced as
an optimisation to avoid enabling/disabling interrupts during
lock/unlock combo.
Enable/disable interrupts as part of the locking instruction.
Cc: Chris Wilson
Reviewed-by: Chris Wilson
Signed-off-by: Sebastian Andrzej Siewior
---
v2…v3: Rebase on top of drm-intel-next-queued
v1…v2: Rebase to v5.4-rc3
drivers/gpu/drm/i915/i915_request.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index f1cadad4e81ca..4575f368455d5 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -206,14 +206,14 @@ static void remove_from_engine(struct i915_request *rq)
* check that the rq still belongs to the newly locked engine.
*/
locked = READ_ONCE(rq->engine);
- spin_lock(&locked->active.lock);
+ spin_lock_irq(&locked->active.lock);
while (unlikely(locked != (engine = READ_ONCE(rq->engine {
spin_unlock(&locked->active.lock);
spin_lock(&engine->active.lock);
locked = engine;
}
list_del(&rq->sched.link);
- spin_unlock(&locked->active.lock);
+ spin_unlock_irq(&locked->active.lock);
}
bool i915_request_retire(struct i915_request *rq)
@@ -242,8 +242,6 @@ bool i915_request_retire(struct i915_request *rq)
&i915_request_timeline(rq)->requests));
rq->ring->head = rq->postfix;
- local_irq_disable();
-
/*
* We only loosely track inflight requests across preemption,
* and so we may find ourselves attempting to retire a _completed_
@@ -252,7 +250,7 @@ bool i915_request_retire(struct i915_request *rq)
*/
remove_from_engine(rq);
- spin_lock(&rq->lock);
+ spin_lock_irq(&rq->lock);
i915_request_mark_complete(rq);
if (!i915_request_signaled(rq))
dma_fence_signal_locked(&rq->fence);
@@ -267,9 +265,7 @@ bool i915_request_retire(struct i915_request *rq)
__notify_execute_cb(rq);
}
GEM_BUG_ON(!list_empty(&rq->execute_cb));
- spin_unlock(&rq->lock);
-
- local_irq_enable();
+ spin_unlock_irq(&rq->lock);
remove_from_client(rq);
list_del(&rq->link);
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Correct the PCH type in irq postinstall
> -Original Message-
> From: Intel-gfx On Behalf Of Matt
> Roper
> Sent: torstai 17. lokakuuta 2019 18.47
> To: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Correct the PCH
> type in irq
> postinstall
>
> On Thu, Oct 17, 2019 at 01:35:20AM +, Patchwork wrote:
> > == Series Details ==
> >
> > Series: drm/i915: Correct the PCH type in irq postinstall
> > URL : https://patchwork.freedesktop.org/series/68116/
> > State : failure
> >
> > == Summary ==
> >
> > CI Bug Log - changes from CI_DRM_7114 -> Patchwork_14843
> >
> >
> > Summary
> > ---
> >
> > **FAILURE**
> >
> > Serious unknown changes coming with Patchwork_14843 absolutely need to be
> > verified manually.
> >
> > If you think the reported changes have nothing to do with the changes
> > introduced in Patchwork_14843, please notify your bug team to allow them
> > to document this new failure mode, which will reduce false positives in
> > CI.
> >
> > External URL:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14843/index.html
> >
> > Possible new issues
> > ---
> >
> > Here are the unknown changes that may have been introduced in
> Patchwork_14843:
> >
> > ### IGT changes ###
> >
> > Possible regressions
> >
> > * igt@i915_selftest@live_execlists:
> > - fi-icl-u2: [PASS][1] -> [DMESG-FAIL][2]
> >[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7114/fi-icl-
> u2/igt@i915_selftest@live_execlists.html
> >[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14843/fi-icl-
> u2/igt@i915_selftest@live_execlists.html
> > - fi-icl-u3: [PASS][3] -> [DMESG-FAIL][4]
> >[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7114/fi-icl-
> u3/igt@i915_selftest@live_execlists.html
> >[4]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14843/fi-icl-u3/igt
> > @i915_selftest@live_execlists.html
>
> These appear to be a GPU hang and "i915/intel_execlists_live_selftests:
> live_timeslice_preempt failed with error -5;" not related to the PCH fix in
> this patch.
These are seen lately on many series, don’t we have bug about these?
>
> >
> > * igt@i915_selftest@live_gem_contexts:
> > - fi-cfl-8109u: [PASS][5] -> [DMESG-FAIL][6]
> >[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7114/fi-cfl-
> 8109u/igt@i915_selftest@live_gem_contexts.html
> >[6]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14843/fi-cfl-8109u/
> > igt@i915_selftest@live_gem_contexts.html
>
>
> This is some kind of a timeout during a GEM selftest
> ("i915/i915_gem_context_live_selftests: live_parallel_switch failed with
> error -62").
> Errno -62 is -ETIME. Also not related to this patch.
Same this too.
>
> Will poke CI for a retest.
>
>
> Matt
>
>
> >
> >
> > Known issues
> >
> >
> > Here are the changes found in Patchwork_14843 that come from known issues:
> >
> > ### IGT changes ###
> >
> > Issues hit
> >
> > * igt@prime_busy@basic-wait-after-default:
> > - fi-icl-u3: [PASS][7] -> [DMESG-WARN][8] ([fdo#107724]) +2
> > similar issues
> >[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7114/fi-icl-
> u3/igt@prime_b...@basic-wait-after-default.html
> >[8]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14843/fi-icl-u3/igt
> > @prime_b...@basic-wait-after-default.html
> >
> >
> > Possible fixes
> >
> > * igt@gem_ctx_create@basic-files:
> > - fi-bdw-gvtdvm: [DMESG-WARN][9] -> [PASS][10]
> >[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7114/fi-bdw-
> gvtdvm/igt@gem_ctx_cre...@basic-files.html
> >[10]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14843/fi-bdw-gvtdvm
> > /igt@gem_ctx_cre...@basic-files.html
> >
> > * igt@gem_flink_basic@double-flink:
> > - fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12] +2
> > similar
> issues
> >[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7114/fi-icl-
> u3/igt@gem_flink_ba...@double-flink.html
> >[12]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14843/fi-icl-u3/igt
> > @gem_flink_ba...@double-flink.html
> >
> > * igt@i915_selftest@live_execlists:
> > - fi-cfl-guc: [DMESG-FAIL][13] -> [PASS][14]
> >[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7114/fi-cfl-
> guc/igt@i915_selftest@live_execlists.html
> >[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14843/fi-cfl-
> guc/igt@i915_selftest@live_execlists.html
> > - fi-cml-u: [DMESG-FAIL][15] -> [PASS][16]
> >[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7114/fi-cml-
> u/igt@i915_selftest@live_execlists.html
> >[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14843/fi-cml-
> u/igt@i915_selftest@live_execlists.html
> > - fi-whl-u: [INCOMPLETE][17] -> [PASS][18]
> >[17]: https://intel-gfx-ci.01.org/tree/d
[Intel-gfx] [PATCH] drm/i915/dsb: Remove PIN_MAPPABLE from the DSB object VMA
From: Tvrtko Ursulin
It sounds like the hardware only needs the DSB object to be in global GTT
and not in the mappable region.
Signed-off-by: Tvrtko Ursulin
Cc: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index bb5a0e91b370..d8ad5fe1efef 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -119,7 +119,7 @@ intel_dsb_get(struct intel_crtc *crtc)
goto err;
}
- vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
+ vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0);
if (IS_ERR(vma)) {
DRM_ERROR("Vma creation failed\n");
i915_gem_object_put(obj);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Correct the PCH type in irq postinstall
On Thu, Oct 17, 2019 at 01:35:20AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Correct the PCH type in irq postinstall
> URL : https://patchwork.freedesktop.org/series/68116/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7114 -> Patchwork_14843
>
>
> Summary
> ---
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_14843 absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_14843, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14843/index.html
>
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> Patchwork_14843:
>
> ### IGT changes ###
>
> Possible regressions
>
> * igt@i915_selftest@live_execlists:
> - fi-icl-u2: [PASS][1] -> [DMESG-FAIL][2]
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7114/fi-icl-u2/igt@i915_selftest@live_execlists.html
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14843/fi-icl-u2/igt@i915_selftest@live_execlists.html
> - fi-icl-u3: [PASS][3] -> [DMESG-FAIL][4]
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7114/fi-icl-u3/igt@i915_selftest@live_execlists.html
>[4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14843/fi-icl-u3/igt@i915_selftest@live_execlists.html
These appear to be a GPU hang and "i915/intel_execlists_live_selftests:
live_timeslice_preempt failed with error -5;" not related to the PCH
fix in this patch.
>
> * igt@i915_selftest@live_gem_contexts:
> - fi-cfl-8109u: [PASS][5] -> [DMESG-FAIL][6]
>[5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7114/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
>[6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14843/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
This is some kind of a timeout during a GEM selftest
("i915/i915_gem_context_live_selftests: live_parallel_switch failed with
error -62"). Errno -62 is -ETIME. Also not related to this patch.
Will poke CI for a retest.
Matt
>
>
> Known issues
>
>
> Here are the changes found in Patchwork_14843 that come from known issues:
>
> ### IGT changes ###
>
> Issues hit
>
> * igt@prime_busy@basic-wait-after-default:
> - fi-icl-u3: [PASS][7] -> [DMESG-WARN][8] ([fdo#107724]) +2
> similar issues
>[7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7114/fi-icl-u3/igt@prime_b...@basic-wait-after-default.html
>[8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14843/fi-icl-u3/igt@prime_b...@basic-wait-after-default.html
>
>
> Possible fixes
>
> * igt@gem_ctx_create@basic-files:
> - fi-bdw-gvtdvm: [DMESG-WARN][9] -> [PASS][10]
>[9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7114/fi-bdw-gvtdvm/igt@gem_ctx_cre...@basic-files.html
>[10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14843/fi-bdw-gvtdvm/igt@gem_ctx_cre...@basic-files.html
>
> * igt@gem_flink_basic@double-flink:
> - fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12] +2
> similar issues
>[11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7114/fi-icl-u3/igt@gem_flink_ba...@double-flink.html
>[12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14843/fi-icl-u3/igt@gem_flink_ba...@double-flink.html
>
> * igt@i915_selftest@live_execlists:
> - fi-cfl-guc: [DMESG-FAIL][13] -> [PASS][14]
>[13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7114/fi-cfl-guc/igt@i915_selftest@live_execlists.html
>[14]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14843/fi-cfl-guc/igt@i915_selftest@live_execlists.html
> - fi-cml-u: [DMESG-FAIL][15] -> [PASS][16]
>[15]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7114/fi-cml-u/igt@i915_selftest@live_execlists.html
>[16]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14843/fi-cml-u/igt@i915_selftest@live_execlists.html
> - fi-whl-u: [INCOMPLETE][17] -> [PASS][18]
>[17]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7114/fi-whl-u/igt@i915_selftest@live_execlists.html
>[18]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14843/fi-whl-u/igt@i915_selftest@live_execlists.html
>
> * igt@i915_selftest@live_gtt:
> - {fi-icl-guc}: [INCOMPLETE][19] ([fdo#107713]) -> [PASS][20]
>[19]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7114/fi-icl-guc/igt@i915_selftest@live_gtt.html
>[20]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14843/fi-icl-guc/igt@i915_selftest@live_gtt.html
>
> * igt@kms_busy@basic-flip-a:
> - {fi-tg
[Intel-gfx] [CI 2/2] drm/i915: Don't disable interrupts independently of the lock
From: Sebastian Andrzej Siewior
The locks (active.lock and rq->lock) need to be taken with disabled
interrupts. This is done in i915_request_retire() by disabling the
interrupts independently of the locks itself.
While local_irq_disable()+spin_lock() equals spin_lock_irq() on vanilla
it does not on PREEMPT_RT.
Chris Wilson confirmed that local_irq_disable() was just introduced as
an optimisation to avoid enabling/disabling interrupts during
lock/unlock combo.
Enable/disable interrupts as part of the locking instruction.
Cc: Chris Wilson
Signed-off-by: Sebastian Andrzej Siewior
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_request.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index f1cadad4e81c..4575f368455d 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -206,14 +206,14 @@ static void remove_from_engine(struct i915_request *rq)
* check that the rq still belongs to the newly locked engine.
*/
locked = READ_ONCE(rq->engine);
- spin_lock(&locked->active.lock);
+ spin_lock_irq(&locked->active.lock);
while (unlikely(locked != (engine = READ_ONCE(rq->engine {
spin_unlock(&locked->active.lock);
spin_lock(&engine->active.lock);
locked = engine;
}
list_del(&rq->sched.link);
- spin_unlock(&locked->active.lock);
+ spin_unlock_irq(&locked->active.lock);
}
bool i915_request_retire(struct i915_request *rq)
@@ -242,8 +242,6 @@ bool i915_request_retire(struct i915_request *rq)
&i915_request_timeline(rq)->requests));
rq->ring->head = rq->postfix;
- local_irq_disable();
-
/*
* We only loosely track inflight requests across preemption,
* and so we may find ourselves attempting to retire a _completed_
@@ -252,7 +250,7 @@ bool i915_request_retire(struct i915_request *rq)
*/
remove_from_engine(rq);
- spin_lock(&rq->lock);
+ spin_lock_irq(&rq->lock);
i915_request_mark_complete(rq);
if (!i915_request_signaled(rq))
dma_fence_signal_locked(&rq->fence);
@@ -267,9 +265,7 @@ bool i915_request_retire(struct i915_request *rq)
__notify_execute_cb(rq);
}
GEM_BUG_ON(!list_empty(&rq->execute_cb));
- spin_unlock(&rq->lock);
-
- local_irq_enable();
+ spin_unlock_irq(&rq->lock);
remove_from_client(rq);
list_del(&rq->link);
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 1/2] drm/i915/execlists: Don't merely skip submission if maybe timeslicing
Normally, we try and skip submission if ELSP[1] is filled. However, we
may desire to enable timeslicing due to the queue priority, even if
ELSP[1] itself does not require timeslicing. That is the queue is equal
priority to ELSP[0] and higher priority then ELSP[1]. Previously, we
would wait until the context switch to preempt the current ELSP[1], but
with timeslicing, we want to preempt ELSP[0] and replace it with the
queue.
In writing the test case, it become quickly apparent that we were also
suppressing the tasklet during promotion and so failing to notice when
the queue started requiring timeslicing.
Fixes: 2229adc81380 ("drm/i915/execlist: Trim immediate timeslice expiry")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_lrc.c| 22 +++-
drivers/gpu/drm/i915/gt/selftest_lrc.c | 164 -
drivers/gpu/drm/i915/i915_scheduler.c | 17 ++-
drivers/gpu/drm/i915/i915_scheduler.h | 18 ---
4 files changed, 192 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index e9fe9f79cedd..d0088d020220 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -352,10 +352,15 @@ static inline bool need_preempt(const struct
intel_engine_cs *engine,
* However, the priority hint is a mere hint that we may need to
* preempt. If that hint is stale or we may be trying to preempt
* ourselves, ignore the request.
+*
+* More naturally we would write
+* prio >= max(0, last);
+* except that we wish to prevent triggering preemption at the same
+* priority level: the task that is running should remain running
+* to preserve FIFO ordering of dependencies.
*/
- last_prio = effective_prio(rq);
- if (!i915_scheduler_need_preempt(engine->execlists.queue_priority_hint,
-last_prio))
+ last_prio = max(effective_prio(rq), I915_PRIORITY_NORMAL - 1);
+ if (engine->execlists.queue_priority_hint <= last_prio)
return false;
/*
@@ -1509,8 +1514,17 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
* submission.
*/
if (!list_is_last(&last->sched.link,
- &engine->active.requests))
+ &engine->active.requests)) {
+ /*
+* Even if ELSP[1] is occupied and not worthy
+* of timeslices, our queue might be.
+*/
+ if (!execlists->timer.expires &&
+ need_timeslice(engine, last))
+ mod_timer(&execlists->timer,
+ jiffies + 1);
return;
+ }
/*
* WaIdleLiteRestore:bdw,skl
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 2868371c609e..5bcfe4a2466f 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -325,7 +325,13 @@ semaphore_queue(struct intel_engine_cs *engine, struct
i915_vma *vma, int idx)
if (IS_ERR(rq))
goto out_ctx;
- err = emit_semaphore_chain(rq, vma, idx);
+ err = 0;
+ if (rq->engine->emit_init_breadcrumb)
+ err = rq->engine->emit_init_breadcrumb(rq);
+ if (err == 0)
+ err = emit_semaphore_chain(rq, vma, idx);
+ if (err == 0)
+ i915_request_get(rq);
i915_request_add(rq);
if (err)
rq = ERR_PTR(err);
@@ -338,10 +344,10 @@ semaphore_queue(struct intel_engine_cs *engine, struct
i915_vma *vma, int idx)
static int
release_queue(struct intel_engine_cs *engine,
struct i915_vma *vma,
- int idx)
+ int idx, int prio)
{
struct i915_sched_attr attr = {
- .priority = I915_USER_PRIORITY(I915_PRIORITY_MAX),
+ .priority = prio,
};
struct i915_request *rq;
u32 *cs;
@@ -362,9 +368,15 @@ release_queue(struct intel_engine_cs *engine,
*cs++ = 1;
intel_ring_advance(rq, cs);
+
+ i915_request_get(rq);
i915_request_add(rq);
+ local_bh_disable();
engine->schedule(rq, &attr);
+ local_bh_enable(); /* kick tasklet */
+
+ i915_request_put(rq);
return 0;
}
@@ -383,7 +395,6 @@ slice_semaphore_queue(struct intel_engine_cs *outer,
if (IS_ERR(head))
return PTR_ERR(head);
- i915_request_get(head);
for_each_engine(engine, outer->i915, id) {
for (i = 0; i < coun
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: Add coverage of mocs registers (rev2)
== Series Details ==
Series: drm/i915/selftests: Add coverage of mocs registers (rev2)
URL : https://patchwork.freedesktop.org/series/68135/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7120 -> Patchwork_14855
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14855 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14855, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14855/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14855:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_execlists:
- fi-icl-u2: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7120/fi-icl-u2/igt@i915_selftest@live_execlists.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14855/fi-icl-u2/igt@i915_selftest@live_execlists.html
- fi-apl-guc: [PASS][3] -> [DMESG-FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7120/fi-apl-guc/igt@i915_selftest@live_execlists.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14855/fi-apl-guc/igt@i915_selftest@live_execlists.html
- fi-skl-6260u: [PASS][5] -> [DMESG-FAIL][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7120/fi-skl-6260u/igt@i915_selftest@live_execlists.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14855/fi-skl-6260u/igt@i915_selftest@live_execlists.html
- fi-cfl-8109u: [PASS][7] -> [DMESG-FAIL][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7120/fi-cfl-8109u/igt@i915_selftest@live_execlists.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14855/fi-cfl-8109u/igt@i915_selftest@live_execlists.html
New tests
-
New tests have been introduced between CI_DRM_7120 and Patchwork_14855:
### New IGT tests (1) ###
* igt@i915_selftest@live_gt_mocs:
- Statuses : 44 pass(s)
- Exec time: [0.39, 2.47] s
Known issues
Here are the changes found in Patchwork_14855 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- fi-kbl-r: [PASS][9] -> [INCOMPLETE][10] ([fdo#112002])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7120/fi-kbl-r/igt@gem_exec_susp...@basic-s3.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14855/fi-kbl-r/igt@gem_exec_susp...@basic-s3.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][11] -> [FAIL][12] ([fdo#111045] / [fdo#111096])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7120/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14855/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [PASS][13] -> [DMESG-WARN][14] ([fdo#102614])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7120/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14855/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@gem_sync@basic-many-each:
- {fi-tgl-u2}:[INCOMPLETE][15] ([fdo#111647]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7120/fi-tgl-u2/igt@gem_s...@basic-many-each.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14855/fi-tgl-u2/igt@gem_s...@basic-many-each.html
- {fi-tgl-u}: [INCOMPLETE][17] ([fdo#111880]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7120/fi-tgl-u/igt@gem_s...@basic-many-each.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14855/fi-tgl-u/igt@gem_s...@basic-many-each.html
* igt@i915_selftest@live_execlists:
- fi-whl-u: [DMESG-FAIL][19] -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7120/fi-whl-u/igt@i915_selftest@live_execlists.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14855/fi-whl-u/igt@i915_selftest@live_execlists.html
- fi-skl-6600u: [DMESG-FAIL][21] -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7120/fi-skl-6600u/igt@i915_selftest@live_execlists.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14855/fi-skl-6600u/igt@i915_selftest@live_execlists.html
- fi-bxt-dsi: [DMESG-FAIL][23] -> [PASS][24]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7120/fi-bxt-dsi/igt@i915_selftest@live_execlists.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14855/fi-bxt-dsi/igt@i915_selftest@live_execli
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/execlists: Don't merely skip submission if maybe timeslicing (rev4)
== Series Details == Series: drm/i915/execlists: Don't merely skip submission if maybe timeslicing (rev4) URL : https://patchwork.freedesktop.org/series/68122/ State : warning == Summary == $ dim checkpatch origin/drm-tip 169736609c98 drm/i915/execlists: Don't merely skip submission if maybe timeslicing -:269: CHECK:LINE_SPACING: Please don't use multiple blank lines #269: FILE: drivers/gpu/drm/i915/gt/selftest_lrc.c:628: + + total: 0 errors, 0 warnings, 1 checks, 303 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH V4 3/6] mdev: introduce device specific ops
On Thu, 17 Oct 2019 18:48:33 +0800
Jason Wang wrote:
> Currently, except for the create and remove, the rest of
> mdev_parent_ops is designed for vfio-mdev driver only and may not help
> for kernel mdev driver. With the help of class id, this patch
> introduces device specific callbacks inside mdev_device
> structure. This allows different set of callback to be used by
> vfio-mdev and virtio-mdev.
>
> Signed-off-by: Jason Wang
> ---
> .../driver-api/vfio-mediated-device.rst | 25 +
> MAINTAINERS | 1 +
> drivers/gpu/drm/i915/gvt/kvmgt.c | 18 ---
> drivers/s390/cio/vfio_ccw_ops.c | 18 ---
> drivers/s390/crypto/vfio_ap_ops.c | 14 +++--
> drivers/vfio/mdev/mdev_core.c | 18 +--
> drivers/vfio/mdev/mdev_private.h | 1 +
> drivers/vfio/mdev/vfio_mdev.c | 37 ++---
> include/linux/mdev.h | 45
> include/linux/vfio_mdev.h | 52 +++
> samples/vfio-mdev/mbochs.c| 20 ---
> samples/vfio-mdev/mdpy.c | 20 ---
> samples/vfio-mdev/mtty.c | 18 ---
> 13 files changed, 184 insertions(+), 103 deletions(-)
> create mode 100644 include/linux/vfio_mdev.h
>
> diff --git a/Documentation/driver-api/vfio-mediated-device.rst
> b/Documentation/driver-api/vfio-mediated-device.rst
> index f9a78d75a67a..0cca84d19603 100644
> --- a/Documentation/driver-api/vfio-mediated-device.rst
> +++ b/Documentation/driver-api/vfio-mediated-device.rst
> @@ -152,11 +152,22 @@ callbacks per mdev parent device, per mdev type, or any
> other categorization.
> Vendor drivers are expected to be fully asynchronous in this respect or
> provide their own internal resource protection.)
>
> -The callbacks in the mdev_parent_ops structure are as follows:
> -
> -* open: open callback of mediated device
> -* close: close callback of mediated device
> -* ioctl: ioctl callback of mediated device
> +As multiple types of mediated devices may be supported, the device
> +must set up the class id and the device specific callbacks in create()
s/in create()/in the create()/
> +callback. E.g for vfio-mdev device it needs to be done through:
"Each class provides a helper function to do so; e.g. for vfio-mdev
devices, the function to be called is:"
?
> +
> +int mdev_set_vfio_ops(struct mdev_device *mdev,
> + const struct vfio_mdev_ops *vfio_ops);
> +
> +The class id (set to MDEV_CLASS_ID_VFIO) is used to match a device
"(set by this helper function to MDEV_CLASS_ID_VFIO)" ?
> +with an mdev driver via its id table. The device specific callbacks
> +(specified in *ops) are obtainable via mdev_get_dev_ops() (for use by
"(specified in *vfio_ops by the caller)" ?
> +the mdev bus driver). A vfio-mdev device (class id MDEV_CLASS_ID_VFIO)
> +uses the following device-specific ops:
> +
> +* open: open callback of vfio mediated device
> +* close: close callback of vfio mediated device
> +* ioctl: ioctl callback of vfio mediated device
> * read : read emulation callback
> * write: write emulation callback
> * mmap: mmap emulation callback
> @@ -167,10 +178,6 @@ register itself with the mdev core driver::
> extern int mdev_register_device(struct device *dev,
>const struct mdev_parent_ops *ops);
>
> -It is also required to specify the class_id in create() callback through::
> -
> - int mdev_set_class(struct mdev_device *mdev, u16 id);
> -
I'm wondering if this patch set should start out with introducing
helper functions already (i.e. don't introduce mdev_set_class(), but
start out with mdev_set_class_vfio() which will gain the *vfio_ops
argument in this patch.)
> However, the mdev_parent_ops structure is not required in the function call
> that a driver should use to unregister itself with the mdev core driver::
>
(...)
> diff --git a/drivers/vfio/mdev/mdev_core.c b/drivers/vfio/mdev/mdev_core.c
> index 3a9c52d71b4e..d0f3113c8071 100644
> --- a/drivers/vfio/mdev/mdev_core.c
> +++ b/drivers/vfio/mdev/mdev_core.c
> @@ -45,15 +45,23 @@ void mdev_set_drvdata(struct mdev_device *mdev, void
> *data)
> }
> EXPORT_SYMBOL(mdev_set_drvdata);
>
> -/* Specify the class for the mdev device, this must be called during
> - * create() callback.
> +/* Specify the VFIO device ops for the mdev device, this
> + * must be called during create() callback for VFIO mdev device.
> */
/*
* Specify the mdev device to be a VFIO mdev device, and set the
* VFIO devices ops for it. This must be called from the create()
* callback for VFIO mdev devices.
*/
?
> -void mdev_set_class(struct mdev_device *mdev, u16 id)
> +void mdev_set_vfio_ops(struct mdev_device *mdev,
> +const struct vfio_mdev_device_ops *vfio_ops)
> {
> WARN_ON(mdev->class_id);
> - mdev->class_
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Add coverage of mocs registers (rev2)
== Series Details ==
Series: drm/i915/selftests: Add coverage of mocs registers (rev2)
URL : https://patchwork.freedesktop.org/series/68135/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
716eba73b16f drm/i915/selftests: Add coverage of mocs registers
-:28: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#28:
new file mode 100644
-:33: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier
tag in line 1
#33: FILE: drivers/gpu/drm/i915/gt/selftest_mocs.c:1:
+/*
-:34: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use
line 1 instead
#34: FILE: drivers/gpu/drm/i915/gt/selftest_mocs.c:2:
+ * SPDX-License-Identifier: MIT
-:217: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#217: FILE: drivers/gpu/drm/i915/gt/selftest_mocs.c:185:
+ memset32(arg->vaddr, STACK_MAGIC, PAGE_SIZE/sizeof(u32));
^
-:226: ERROR:SPACING: space required before the open parenthesis '('
#226: FILE: drivers/gpu/drm/i915/gt/selftest_mocs.c:194:
+ if(err)
-:283: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#283: FILE: drivers/gpu/drm/i915/gt/selftest_mocs.c:251:
+
+}
-:284: CHECK:LINE_SPACING: Please use a blank line after
function/struct/union/enum declarations
#284: FILE: drivers/gpu/drm/i915/gt/selftest_mocs.c:252:
+}
+static int live_mocs_reset(void *arg)
total: 1 errors, 3 warnings, 3 checks, 323 lines checked
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Don't disable interrupts independently of the lock (rev3)
== Series Details == Series: drm/i915: Don't disable interrupts independently of the lock (rev3) URL : https://patchwork.freedesktop.org/series/59289/ State : failure == Summary == Applying: drm/i915: Don't disable interrupts independently of the lock Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/i915_request.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/i915_request.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_request.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0001 drm/i915: Don't disable interrupts independently of the lock When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 02/15] drm/i915/dsb: DSB context creation.
On 17/10/2019 14:53, Animesh Manna wrote: On 10/17/2019 6:39 PM, Tvrtko Ursulin wrote: On 17/10/2019 13:52, Animesh Manna wrote: On 10/17/2019 2:05 PM, Tvrtko Ursulin wrote: On 22/08/2019 13:09, Chris Wilson wrote: Quoting Animesh Manna (2019-08-22 13:05:06) Hi, On 8/21/2019 11:41 PM, Chris Wilson wrote: Quoting Animesh Manna (2019-08-21 07:32:22) + vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE); Only this (currently) still requires struct_mutex Sure will add. Does it have to mappable? Is that the HW constraint? Yes, as per HW design need a cpu mapped buffer to write opcode+data from driver. PIN_MAPPABLE refers to the iomem aperture portion of the Global GTT (i.e. the low 64-512MiB). You never use a GGTT mmap for your CPU access, so the placement should be entirely dictated by the DSB requirements. If you don't need to be in the low region, don't force it to be, so we have less congestion for the objects that have to be placed in that region. I was doing a mini audit of what uses the aperture these days and noticed this code has been merged in the meantime, but AFAICS this question from Chris hasn't been answered? At least not on the mailing list. So does it need to be in the aperture region or not? Hi, Based on recommendation from H/w team used PIN_MAPPABLE, not very sure about internal details. What did the recommendation exactly say? That it has to be in GGTT or aperture? It said: "GMM to allocate buffer from global GTT, get CPU mapped address as well (not stolen memory) ... ". So it's possible you don't need PIN_MAPPABLE. Do we have some test coverage for this? In other words if I send a patch which removes it, will we know if the feature is healthy? Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] i915: Exercise preemption timeout controls in sysfs
Dynamic subtests!
Signed-off-by: Chris Wilson
---
lib/i915/gem_context.c| 40 +
lib/i915/gem_context.h| 2 +
tests/Makefile.sources| 1 +
tests/i915/sysfs_preemption_timeout.c | 203 ++
tests/meson.build | 1 +
5 files changed, 247 insertions(+)
create mode 100644 tests/i915/sysfs_preemption_timeout.c
diff --git a/lib/i915/gem_context.c b/lib/i915/gem_context.c
index 1fae5191f..a627a5c7b 100644
--- a/lib/i915/gem_context.c
+++ b/lib/i915/gem_context.c
@@ -403,3 +403,43 @@ bool gem_context_has_engine(int fd, uint32_t ctx, uint64_t
engine)
return __gem_execbuf(fd, &execbuf) == -ENOENT;
}
+
+static int create_ext_ioctl(int i915,
+ struct drm_i915_gem_context_create_ext *arg)
+{
+ int err;
+
+ err = 0;
+ if (igt_ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT, arg)) {
+ err = -errno;
+ igt_assume(err);
+ }
+
+ errno = 0;
+ return err;
+}
+
+uint32_t gem_context_create_for_engine(int i915, unsigned int class, unsigned
int inst)
+{
+ I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = {
+ .engines = { { .engine_class = class, .engine_instance = inst }
}
+ };
+ struct drm_i915_gem_context_create_ext_setparam p_engines = {
+ .base = {
+ .name = I915_CONTEXT_CREATE_EXT_SETPARAM,
+ .next_extension = 0, /* end of chain */
+ },
+ .param = {
+ .param = I915_CONTEXT_PARAM_ENGINES,
+ .value = to_user_pointer(&engines),
+ .size = sizeof(engines),
+ },
+ };
+ struct drm_i915_gem_context_create_ext create = {
+ .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
+ .extensions = to_user_pointer(&p_engines),
+ };
+
+ igt_assert_eq(create_ext_ioctl(i915, &create), 0);
+ return create.ctx_id;
+}
diff --git a/lib/i915/gem_context.h b/lib/i915/gem_context.h
index c0d4c9615..9e0a083f0 100644
--- a/lib/i915/gem_context.h
+++ b/lib/i915/gem_context.h
@@ -34,6 +34,8 @@ int __gem_context_create(int fd, uint32_t *ctx_id);
void gem_context_destroy(int fd, uint32_t ctx_id);
int __gem_context_destroy(int fd, uint32_t ctx_id);
+uint32_t gem_context_create_for_engine(int fd, unsigned int class, unsigned
int inst);
+
int __gem_context_clone(int i915,
uint32_t src, unsigned int share,
unsigned int flags,
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 093eb57f3..dff7dac06 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -98,6 +98,7 @@ TESTS_progs = \
tools_test \
vgem_basic \
vgem_slow \
+ i915/sysfs_preemption_timeout \
$(NULL)
TESTS_progs += gem_bad_reloc
diff --git a/tests/i915/sysfs_preemption_timeout.c
b/tests/i915/sysfs_preemption_timeout.c
new file mode 100644
index 0..a798345b1
--- /dev/null
+++ b/tests/i915/sysfs_preemption_timeout.c
@@ -0,0 +1,203 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "drmtest.h" /* gem_quiescent_gpu()! */
+#include "igt_dummyload.h"
+#include "igt_sysfs.h"
+#include "ioctl_wrappers.h" /* igt_require_gem()! */
+#include "sw_sync.h"
+
+#include "igt_debugfs.h"
+
+static bool __enable_hangcheck(int dir, bool state)
+{
+ return igt_sysfs_set(dir, "enable_hangcheck", state ? "1" : "0");
+}
+
+static bool enable_hangcheck(int i915, bool state)
+{
+ bool success;
+ int dir;
+
+ dir = igt_sysfs_open_parameters(i915);
+ if (dir < 0) /* no parameters, must be default! */
+ retu
Re: [Intel-gfx] [PATCH 01/14] drm/i915: Rework watermark readout to use plane api
Op 17-10-2019 om 15:37 schreef Ville Syrjälä: > On Thu, Oct 17, 2019 at 03:20:52PM +0200, Maarten Lankhorst wrote: >> Instead of unconditionally verifying the cursor plane, handle it in the >> same way as any other plane, and use our existing api to verify. >> >> While at it, ensure that on gen9+ we verify active_planes mask as well. >> This should give the correct results for planar YUV planes too, as we >> update active_planes for them. > Why is that hidden in the watermark verification code? We already have > intel_verify_planes() which seems like a better fit. Wasn't aware of it, mostly. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PULL] drm-intel-fixes
Hi Dave and Daniel, Here goes drm-intel-fixes-2019-10-17: - Display fix on handling VBT information. - Important circular locking fix - Fix for preemption vs resubmission on virtual requests - and a prep patch to make this last one to apply cleanly Thanks, Rodrigo. The following changes since commit 4f5cafb5cb8471e54afdc9054d973535614f7675: Linux 5.4-rc3 (2019-10-13 16:37:36 -0700) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2019-10-17 for you to fetch changes up to 0a544a2a728e2e33bb7fc38dd542ecb90ee393eb: drm/i915: Fixup preempt-to-busy vs resubmission of a virtual request (2019-10-16 10:57:33 -0700) - Display fix on handling VBT information. - Important circular locking fix - Fix for preemption vs resubmission on virtual requests - and a prep patch to make this last one to apply cleanly Chris Wilson (3): drm/i915/execlists: Refactor -EIO markup of hung requests drm/i915/userptr: Never allow userptr into the mappable GGTT drm/i915: Fixup preempt-to-busy vs resubmission of a virtual request Ville Syrjälä (1): drm/i915: Favor last VBT child device with conflicting AUX ch/DDC pin drivers/gpu/drm/i915/display/intel_bios.c| 22 ++--- drivers/gpu/drm/i915/gem/i915_gem_mman.c | 7 +++ drivers/gpu/drm/i915/gem/i915_gem_object.h | 6 +++ drivers/gpu/drm/i915/gem/i915_gem_object_types.h | 3 +- drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 1 + drivers/gpu/drm/i915/gt/intel_lrc.c | 63 drivers/gpu/drm/i915/i915_gem.c | 3 ++ 7 files changed, 78 insertions(+), 27 deletions(-) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 02/15] drm/i915/dsb: DSB context creation.
On 10/17/2019 6:39 PM, Tvrtko Ursulin wrote: On 17/10/2019 13:52, Animesh Manna wrote: On 10/17/2019 2:05 PM, Tvrtko Ursulin wrote: On 22/08/2019 13:09, Chris Wilson wrote: Quoting Animesh Manna (2019-08-22 13:05:06) Hi, On 8/21/2019 11:41 PM, Chris Wilson wrote: Quoting Animesh Manna (2019-08-21 07:32:22) + vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE); Only this (currently) still requires struct_mutex Sure will add. Does it have to mappable? Is that the HW constraint? Yes, as per HW design need a cpu mapped buffer to write opcode+data from driver. PIN_MAPPABLE refers to the iomem aperture portion of the Global GTT (i.e. the low 64-512MiB). You never use a GGTT mmap for your CPU access, so the placement should be entirely dictated by the DSB requirements. If you don't need to be in the low region, don't force it to be, so we have less congestion for the objects that have to be placed in that region. I was doing a mini audit of what uses the aperture these days and noticed this code has been merged in the meantime, but AFAICS this question from Chris hasn't been answered? At least not on the mailing list. So does it need to be in the aperture region or not? Hi, Based on recommendation from H/w team used PIN_MAPPABLE, not very sure about internal details. What did the recommendation exactly say? That it has to be in GGTT or aperture? It said: "GMM to allocate buffer from global GTT, get CPU mapped address as well (not stolen memory) ... ". Regards, Animesh Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 1/2] drm/i915: Make for_each_engine_masked work on intel_gt
Quoting Tvrtko Ursulin (2019-10-17 14:45:31)
> From: Tvrtko Ursulin
>
> Medium term goal is to eliminate the i915->engine[] array and to get there
> we have recently introduced equivalent array in intel_gt. Now we need to
> migrate the code further towards this state.
>
> This next step is to eliminate usage of i915->engines[] from the
> for_each_engine_masked iterator.
>
> For this to work we also need to use engine->id as index when populating
> the gt->engine[] array and adjust the default engine set indexing to use
> engine->legacy_idx instead of assuming gt->engines[] indexing.
>
> v2:
> * Populate gt->engine[] earlier.
>
> v3:
> * Work around the initialization order issue between default_engines()
>and intel_engines_driver_register() which sets engine->legacy_idx for
>now. It will be fixed properly later.
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Chris Wilson
> Reviewed-by: Chris Wilson # v1
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 7 +--
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4
> drivers/gpu/drm/i915/gt/intel_engine_user.c | 2 --
> drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_hangcheck.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_reset.c | 12 ++--
> drivers/gpu/drm/i915/gvt/execlist.c | 4 ++--
> drivers/gpu/drm/i915/gvt/scheduler.c| 2 +-
> drivers/gpu/drm/i915/i915_active.c | 4 ++--
> drivers/gpu/drm/i915/i915_drv.h | 6 +++---
> 10 files changed, 25 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index 5d8221c7ba83..87d66d8faff1 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -203,14 +203,17 @@ static struct i915_gem_engines *default_engines(struct
> i915_gem_context *ctx)
> for_each_engine(engine, gt, id) {
> struct intel_context *ce;
>
> + if (engine->legacy_idx == -1)
> + continue;
> +
> ce = intel_context_create(ctx, engine);
> if (IS_ERR(ce)) {
> __free_engines(e, id);
> return ERR_CAST(ce);
> }
>
> - e->engines[id] = ce;
> - e->num_engines = id + 1;
> + e->engines[engine->legacy_idx] = ce;
> + e->num_engines = engine->legacy_idx + 1;
e->num_engines = max(e->num_engines, engine->legacy_idx + 1);
and remove id above.
Please take the v2.5, throw in the legacy_idx=-1 and remove bits until
you are happy :)
-Chris
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[Intel-gfx] [PATCH v3 1/2] drm/i915: Make for_each_engine_masked work on intel_gt
From: Tvrtko Ursulin
Medium term goal is to eliminate the i915->engine[] array and to get there
we have recently introduced equivalent array in intel_gt. Now we need to
migrate the code further towards this state.
This next step is to eliminate usage of i915->engines[] from the
for_each_engine_masked iterator.
For this to work we also need to use engine->id as index when populating
the gt->engine[] array and adjust the default engine set indexing to use
engine->legacy_idx instead of assuming gt->engines[] indexing.
v2:
* Populate gt->engine[] earlier.
v3:
* Work around the initialization order issue between default_engines()
and intel_engines_driver_register() which sets engine->legacy_idx for
now. It will be fixed properly later.
Signed-off-by: Tvrtko Ursulin
Cc: Chris Wilson
Reviewed-by: Chris Wilson # v1
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 7 +--
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4
drivers/gpu/drm/i915/gt/intel_engine_user.c | 2 --
drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_hangcheck.c | 2 +-
drivers/gpu/drm/i915/gt/intel_reset.c | 12 ++--
drivers/gpu/drm/i915/gvt/execlist.c | 4 ++--
drivers/gpu/drm/i915/gvt/scheduler.c| 2 +-
drivers/gpu/drm/i915/i915_active.c | 4 ++--
drivers/gpu/drm/i915/i915_drv.h | 6 +++---
10 files changed, 25 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 5d8221c7ba83..87d66d8faff1 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -203,14 +203,17 @@ static struct i915_gem_engines *default_engines(struct
i915_gem_context *ctx)
for_each_engine(engine, gt, id) {
struct intel_context *ce;
+ if (engine->legacy_idx == -1)
+ continue;
+
ce = intel_context_create(ctx, engine);
if (IS_ERR(ce)) {
__free_engines(e, id);
return ERR_CAST(ce);
}
- e->engines[id] = ce;
- e->num_engines = id + 1;
+ e->engines[engine->legacy_idx] = ce;
+ e->num_engines = engine->legacy_idx + 1;
}
return e;
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 5051a1fd2565..d1a752a664ec 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -293,6 +293,7 @@ static int intel_engine_setup(struct intel_gt *gt, enum
intel_engine_id id)
BUILD_BUG_ON(BITS_PER_TYPE(engine->mask) < I915_NUM_ENGINES);
engine->id = id;
+ engine->legacy_idx = -1;
engine->mask = BIT(id);
engine->i915 = gt->i915;
engine->gt = gt;
@@ -330,7 +331,10 @@ static int intel_engine_setup(struct intel_gt *gt, enum
intel_engine_id id)
gt->engine_class[info->class][info->instance] = engine;
intel_engine_add_user(engine);
+ GEM_BUG_ON(id >= ARRAY_SIZE(gt->i915->engine));
gt->i915->engine[id] = engine;
+ GEM_BUG_ON(id >= ARRAY_SIZE(gt->engine));
+ gt->engine[id] = engine;
return 0;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c
b/drivers/gpu/drm/i915/gt/intel_engine_user.c
index 77cd5de83930..e9f3fbaa74a8 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
@@ -183,8 +183,6 @@ static void add_legacy_ring(struct legacy_ring *ring,
if (unlikely(idx == -1))
return;
- GEM_BUG_ON(idx >= ARRAY_SIZE(ring->gt->engine));
- ring->gt->engine[idx] = engine;
ring->instance++;
engine->legacy_idx = idx;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index b3619a2a5d0e..c99b6b2f38c2 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -186,7 +186,7 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
struct intel_engine_cs *engine;
enum intel_engine_id id;
- for_each_engine_masked(engine, i915, engine_mask, id)
+ for_each_engine_masked(engine, gt, engine_mask, id)
gen8_clear_engine_error_register(engine);
}
}
diff --git a/drivers/gpu/drm/i915/gt/intel_hangcheck.c
b/drivers/gpu/drm/i915/gt/intel_hangcheck.c
index c14dbeb3ccc3..b2af73984f93 100644
--- a/drivers/gpu/drm/i915/gt/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/intel_hangcheck.c
@@ -237,7 +237,7 @@ static void hangcheck_declare_hang(struct intel_gt *gt,
hung &= ~stuck;
len = scnprintf(msg, sizeof(msg),
"%s on ", stuck == hung ? "no progress" : "hang");
- for_each_engine_masked(engine, gt->i915, hung, tmp)
+ for_ea
Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] i915/gem_persistent_relocs: Manage the domain for the GGTT access
On 16/10/2019 19:56, Chris Wilson wrote: Since the GGTT fault will overlap with the pwrite access, there is no implicit moment at which the kernel will automagically flush the backing store. Userspace has to be explicit in its domain control, or do itself. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112037 Signed-off-by: Chris Wilson --- tests/i915/gem_persistent_relocs.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tests/i915/gem_persistent_relocs.c b/tests/i915/gem_persistent_relocs.c index 2ab7091ad..20ee03027 100644 --- a/tests/i915/gem_persistent_relocs.c +++ b/tests/i915/gem_persistent_relocs.c @@ -224,8 +224,11 @@ static void do_test(int fd, bool faulting_reloc) relocs_bo_handle[i] = gem_create(fd, 4096); gem_write(fd, relocs_bo_handle[i], 0, reloc, sizeof(reloc)); + gtt_relocs_ptr[i] = gem_mmap__gtt(fd, relocs_bo_handle[i], 4096, PROT_READ | PROT_WRITE); + gem_set_domain(fd, relocs_bo_handle[i], + I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT); } /* repeat must be smaller than 4096/small_pitch */ Reviewed-by: Tvrtko Ursulin Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 01/14] drm/i915: Rework watermark readout to use plane api
On Thu, Oct 17, 2019 at 03:20:52PM +0200, Maarten Lankhorst wrote:
> Instead of unconditionally verifying the cursor plane, handle it in the
> same way as any other plane, and use our existing api to verify.
>
> While at it, ensure that on gen9+ we verify active_planes mask as well.
> This should give the correct results for planar YUV planes too, as we
> update active_planes for them.
Why is that hidden in the watermark verification code? We already have
intel_verify_planes() which seems like a better fit.
>
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 83 ++--
> 1 file changed, 23 insertions(+), 60 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 164ded862148..945ab2180614 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -12932,7 +12932,8 @@ static void verify_wm_state(struct intel_crtc *crtc,
> struct skl_pipe_wm *sw_wm;
> struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
> const enum pipe pipe = crtc->pipe;
> - int plane, level, max_level = ilk_wm_max_level(dev_priv);
> + int level, max_level = ilk_wm_max_level(dev_priv);
> + struct intel_plane *plane;
>
> if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->base.active)
> return;
> @@ -12956,63 +12957,25 @@ static void verify_wm_state(struct intel_crtc *crtc,
> hw->ddb.enabled_slices);
>
> /* planes */
> - for_each_universal_plane(dev_priv, pipe, plane) {
> + for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
> struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
> + enum pipe plane_pipe = pipe;
>
> - hw_plane_wm = &hw->wm.planes[plane];
> - sw_plane_wm = &sw_wm->planes[plane];
> -
> - /* Watermarks */
> - for (level = 0; level <= max_level; level++) {
> - if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> - &sw_plane_wm->wm[level]))
> - continue;
> -
> - DRM_ERROR("mismatch in WM pipe %c plane %d level %d
> (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
> - pipe_name(pipe), plane + 1, level,
> - sw_plane_wm->wm[level].plane_en,
> - sw_plane_wm->wm[level].plane_res_b,
> - sw_plane_wm->wm[level].plane_res_l,
> - hw_plane_wm->wm[level].plane_en,
> - hw_plane_wm->wm[level].plane_res_b,
> - hw_plane_wm->wm[level].plane_res_l);
> - }
> + hw_plane_wm = &hw->wm.planes[plane->id];
> + sw_plane_wm = &sw_wm->planes[plane->id];
>
> - if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
> - &sw_plane_wm->trans_wm)) {
> - DRM_ERROR("mismatch in trans WM pipe %c plane %d
> (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
> - pipe_name(pipe), plane + 1,
> - sw_plane_wm->trans_wm.plane_en,
> - sw_plane_wm->trans_wm.plane_res_b,
> - sw_plane_wm->trans_wm.plane_res_l,
> - hw_plane_wm->trans_wm.plane_en,
> - hw_plane_wm->trans_wm.plane_res_b,
> - hw_plane_wm->trans_wm.plane_res_l);
> - }
> -
> - /* DDB */
> - hw_ddb_entry = &hw->ddb_y[plane];
> - sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane];
> -
> - if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
> - DRM_ERROR("mismatch in DDB state pipe %c plane %d
> (expected (%u,%u), found (%u,%u))\n",
> - pipe_name(pipe), plane + 1,
> - sw_ddb_entry->start, sw_ddb_entry->end,
> - hw_ddb_entry->start, hw_ddb_entry->end);
> + if (!plane->get_hw_state(plane, &plane_pipe)) {
> + WARN(new_crtc_state->active_planes & BIT(plane->id),
> + "pipe %c %s should be visible, but isn't\n",
> + pipe_name(pipe), plane->base.name);
> + continue;
> }
> - }
>
> - /*
> - * cursor
> - * If the cursor plane isn't active, we may not have updated it's ddb
> - * allocation. In that case since the ddb allocation will be updated
> - * once the plane becomes visible, we can skip this check
> - */
> - if (1) {
> - struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
> + WARN_ON(plane_pipe != p
Re: [Intel-gfx] [PATCH 1/5] drm/i915: Shrink eDRAM ways/sets arrays
On 2019-10-17 at 15:54:46 +0300, Ville Syrjälä wrote:
> On Thu, Oct 17, 2019 at 01:28:29PM +0530, Ramalingam C wrote:
> > On 2019-10-10 at 17:51:23 +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > Make the ways/sets arrays static cosnt u8 to shrink things a bit.
> > >
> > > text data bss dec hex filename
> > > - 23935 629 128 246926074 i915_drv.o
> > > + 23818 629 128 245755fff i915_drv.o
> > >
> > > Signed-off-by: Ville Syrjälä
Looks good to me.
Reviewed-by: Ramalingam C
> > > ---
> > > drivers/gpu/drm/i915/i915_drv.c | 4 ++--
> > > 1 file changed, 2 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.c
> > > b/drivers/gpu/drm/i915/i915_drv.c
> > > index f02a34722217..0b8c13ae4857 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.c
> > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > @@ -1073,8 +1073,8 @@ intel_get_dram_info(struct drm_i915_private
> > > *dev_priv)
> > >
> > > static u32 gen9_edram_size_mb(struct drm_i915_private *dev_priv, u32 cap)
> > > {
> > > - const unsigned int ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
> > > - const unsigned int sets[4] = { 1, 1, 2, 2 };
> > > + static const u8 ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
> > > + static const u8 sets[4] = { 1, 1, 2, 2 };
> > Asking for my understanding. unsigned int -> u8 make sense to shrink the
> > size. Could you please add reasoning for adding static? moving it into
> > data segment hence reducing the stack?
>
> Possibly. My usual approach is to just make all such things
> static const unless there is a real reason not to.
Ok. Thanks.
-Ram
>
> >
> > -Ram
> > >
> > > return EDRAM_NUM_BANKS(cap) *
> > > ways[EDRAM_WAYS_IDX(cap)] *
> > > --
> > > 2.21.0
> > >
> > > ___
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel
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[Intel-gfx] [PATCH 08/14] drm/i915: Complete crtc hw/uapi split, v2.
Now that we separated everything into uapi and hw, it's
time to make the split definitive. Remove the union and
make a copy of the hw state on modeset and fastset.
Color blobs are copied in crtc atomic_check(), right
before color management is checked.
Changes since v1:
- Copy all blobs immediately after drm_atomic_helper_check_modeset().
- Clear crtc_state->hw on disable, instead of using clear_intel_crtc_state().
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_atomic.c | 44 ++
drivers/gpu/drm/i915/display/intel_atomic.h | 2 +
drivers/gpu/drm/i915/display/intel_display.c | 45 ---
.../drm/i915/display/intel_display_types.h| 9 ++--
4 files changed, 89 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
b/drivers/gpu/drm/i915/display/intel_atomic.c
index 7cf13b9c7d38..266d0ce9d03d 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -195,6 +195,14 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
__drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->uapi);
+ /* copy color blobs */
+ if (crtc_state->hw.degamma_lut)
+ drm_property_blob_get(crtc_state->hw.degamma_lut);
+ if (crtc_state->hw.ctm)
+ drm_property_blob_get(crtc_state->hw.ctm);
+ if (crtc_state->hw.gamma_lut)
+ drm_property_blob_get(crtc_state->hw.gamma_lut);
+
crtc_state->update_pipe = false;
crtc_state->disable_lp_wm = false;
crtc_state->disable_cxsr = false;
@@ -208,6 +216,41 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
return &crtc_state->uapi;
}
+static void intel_crtc_put_color_blobs(struct intel_crtc_state *crtc_state)
+{
+ drm_property_blob_put(crtc_state->hw.degamma_lut);
+ drm_property_blob_put(crtc_state->hw.gamma_lut);
+ drm_property_blob_put(crtc_state->hw.ctm);
+}
+
+void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state)
+{
+ intel_crtc_put_color_blobs(crtc_state);
+}
+
+void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state)
+{
+ intel_crtc_put_color_blobs(crtc_state);
+
+ if (crtc_state->uapi.degamma_lut)
+ crtc_state->hw.degamma_lut =
+ drm_property_blob_get(crtc_state->uapi.degamma_lut);
+ else
+ crtc_state->hw.degamma_lut = NULL;
+
+ if (crtc_state->uapi.gamma_lut)
+ crtc_state->hw.gamma_lut =
+ drm_property_blob_get(crtc_state->uapi.gamma_lut);
+ else
+ crtc_state->hw.gamma_lut = NULL;
+
+ if (crtc_state->uapi.ctm)
+ crtc_state->hw.ctm =
+ drm_property_blob_get(crtc_state->uapi.ctm);
+ else
+ crtc_state->hw.ctm = NULL;
+}
+
/**
* intel_crtc_destroy_state - destroy crtc state
* @crtc: drm crtc
@@ -223,6 +266,7 @@ intel_crtc_destroy_state(struct drm_crtc *crtc,
struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);
__drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
+ intel_crtc_free_hw_state(crtc_state);
kfree(crtc_state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h
b/drivers/gpu/drm/i915/display/intel_atomic.h
index 58065d3161a3..42be91e0772a 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic.h
@@ -35,6 +35,8 @@ intel_digital_connector_duplicate_state(struct drm_connector
*connector);
struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
void intel_crtc_destroy_state(struct drm_crtc *crtc,
struct drm_crtc_state *state);
+void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state);
+void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state);
struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
void intel_atomic_state_clear(struct drm_atomic_state *state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 06c593d56d92..c009489641bd 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -114,6 +114,7 @@ static const u64 cursor_format_modifiers[] = {
DRM_FORMAT_MOD_INVALID
};
+static void copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state);
static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config);
static void ironlake_pch_clock_get(struct intel_crtc *crtc,
@@ -7041,6 +7042,7 @@ static void intel_crtc_disable_noatomic(struct drm_crtc
*crtc,
crtc->enabled = false;
crtc->state->connector_mask = 0;
crtc->state->encoder_mask = 0;
+ copy_uapi_to_hw_state(to_intel_crtc_state(crtc->state));
for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
[Intel-gfx] [PATCH 10/14] drm/i915: Perform manual conversions for plane uapi/hw split
get_crtc_from_states() is called before plane_state is copied to uapi,
so use the uapi state there.
intel_legacy_cursor_update() could probably get away with looking at
the hw state, but for clarity look at the uapi state always
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_atomic_plane.c | 8
drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 4b12eeb6850d..0db20da7781c 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -186,11 +186,11 @@ static struct intel_crtc *
get_crtc_from_states(const struct intel_plane_state *old_plane_state,
const struct intel_plane_state *new_plane_state)
{
- if (new_plane_state->base.crtc)
- return to_intel_crtc(new_plane_state->base.crtc);
+ if (new_plane_state->uapi.crtc)
+ return to_intel_crtc(new_plane_state->uapi.crtc);
- if (old_plane_state->base.crtc)
- return to_intel_crtc(old_plane_state->base.crtc);
+ if (old_plane_state->uapi.crtc)
+ return to_intel_crtc(old_plane_state->uapi.crtc);
return NULL;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index c009489641bd..76402df8e698 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14748,12 +14748,12 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
* take the slowpath. Only changing fb or position should be
* in the fastpath.
*/
- if (old_plane_state->base.crtc != &crtc->base ||
+ if (old_plane_state->uapi.crtc != &crtc->base ||
old_plane_state->base.src_w != src_w ||
old_plane_state->base.src_h != src_h ||
old_plane_state->base.crtc_w != crtc_w ||
old_plane_state->base.crtc_h != crtc_h ||
- !old_plane_state->base.fb != !fb)
+ !old_plane_state->uapi.fb != !fb)
goto slow;
new_plane_state =
to_intel_plane_state(intel_plane_duplicate_state(&plane->base));
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 11/14] drm/i915: Perform automated conversions for plane uapi/hw split, base -> hw.
Split up plane_state->base to hw. This is done using the following patch:
@@
struct intel_plane_state *T;
identifier x =~
"^(crtc|fb|alpha|pixel_blend_mode|rotation|color_encoding|color_range)$";
@@
-T->base.x
+T->hw.x
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_atomic.c | 6 +-
.../gpu/drm/i915/display/intel_atomic_plane.c | 6 +-
drivers/gpu/drm/i915/display/intel_display.c | 127 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 8 +-
drivers/gpu/drm/i915/display/intel_overlay.c | 2 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 76 +--
drivers/gpu/drm/i915/intel_pm.c | 36 ++---
7 files changed, 131 insertions(+), 130 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
b/drivers/gpu/drm/i915/display/intel_atomic.c
index 266d0ce9d03d..9ba50fd1116c 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -296,9 +296,9 @@ static void intel_atomic_setup_scaler(struct
intel_crtc_scaler_state *scaler_sta
return;
/* set scaler mode */
- if (plane_state && plane_state->base.fb &&
- plane_state->base.fb->format->is_yuv &&
- plane_state->base.fb->format->num_planes > 1) {
+ if (plane_state && plane_state->hw.fb &&
+ plane_state->hw.fb->format->is_yuv &&
+ plane_state->hw.fb->format->num_planes > 1) {
struct intel_plane *plane =
to_intel_plane(plane_state->base.plane);
if (IS_GEN(dev_priv, 9) &&
!IS_GEMINILAKE(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 0db20da7781c..fd5a8012859c 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -118,7 +118,7 @@ intel_plane_destroy_state(struct drm_plane *plane,
unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
- const struct drm_framebuffer *fb = plane_state->base.fb;
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
unsigned int cpp;
if (!plane_state->base.visible)
@@ -144,7 +144,7 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
struct intel_plane_state
*new_plane_state)
{
struct intel_plane *plane = to_intel_plane(new_plane_state->base.plane);
- const struct drm_framebuffer *fb = new_plane_state->base.fb;
+ const struct drm_framebuffer *fb = new_plane_state->hw.fb;
int ret;
new_crtc_state->active_planes &= ~BIT(plane->id);
@@ -153,7 +153,7 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
new_crtc_state->data_rate[plane->id] = 0;
new_plane_state->base.visible = false;
- if (!new_plane_state->base.crtc && !old_plane_state->base.crtc)
+ if (!new_plane_state->hw.crtc && !old_plane_state->hw.crtc)
return 0;
ret = plane->check_plane(new_crtc_state, new_plane_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 76402df8e698..91e9fb2b4df8 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2189,7 +2189,7 @@ u32 intel_fb_xy_to_linear(int x, int y,
const struct intel_plane_state *state,
int color_plane)
{
- const struct drm_framebuffer *fb = state->base.fb;
+ const struct drm_framebuffer *fb = state->hw.fb;
unsigned int cpp = fb->format->cpp[color_plane];
unsigned int pitch = state->color_plane[color_plane].stride;
@@ -2290,8 +2290,8 @@ static u32 intel_plane_adjust_aligned_offset(int *x, int
*y,
int color_plane,
u32 old_offset, u32 new_offset)
{
- return intel_adjust_aligned_offset(x, y, state->base.fb, color_plane,
- state->base.rotation,
+ return intel_adjust_aligned_offset(x, y, state->hw.fb, color_plane,
+ state->hw.rotation,
state->color_plane[color_plane].stride,
old_offset, new_offset);
}
@@ -2367,8 +2367,8 @@ static u32 intel_plane_compute_aligned_offset(int *x, int
*y,
{
struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
- const struct drm_framebuffer *fb = state->base.fb;
- unsigned int rotation = state->base.rotation;
+ const struct drm_framebuffer *fb = state->hw.fb;
+ un
[Intel-gfx] [PATCH 14/14] drm/i915: Remove special case slave handling during hw programming, v2.
Now that we split plane_state which I didn't want to do yet, we can
program the slave plane without requiring the master plane.
This is useful for programming bigjoiner slave planes as well. We
will no longer need the master's plane_state.
Changes since v1:
- set src/dst rectangles after copy_uapi_to_hw_state.
Signed-off-by: Maarten Lankhorst
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 30 +-
.../gpu/drm/i915/display/intel_atomic_plane.h | 3 -
drivers/gpu/drm/i915/display/intel_display.c | 18 ++
.../drm/i915/display/intel_display_types.h| 6 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 55 ++-
5 files changed, 39 insertions(+), 73 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index d9b65e9c45fc..54d112408716 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -309,16 +309,6 @@ void intel_update_plane(struct intel_plane *plane,
plane->update_plane(plane, crtc_state, plane_state);
}
-void intel_update_slave(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state)
-{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-
- trace_intel_update_plane(&plane->base, crtc);
- plane->update_slave(plane, crtc_state, plane_state);
-}
-
void intel_disable_plane(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state)
{
@@ -351,25 +341,9 @@ void skl_update_planes_on_crtc(struct intel_atomic_state
*state,
struct intel_plane_state *new_plane_state =
intel_atomic_get_new_plane_state(state, plane);
- if (new_plane_state->uapi.visible) {
+ if (new_plane_state->uapi.visible ||
+ new_plane_state->planar_slave) {
intel_update_plane(plane, new_crtc_state,
new_plane_state);
- } else if (new_plane_state->planar_slave) {
- struct intel_plane *master =
- new_plane_state->planar_linked_plane;
-
- /*
-* We update the slave plane from this function because
-* programming it from the master plane's update_plane
-* callback runs into issues when the Y plane is
-* reassigned, disabled or used by a different plane.
-*
-* The slave plane is updated with the master plane's
-* plane_state.
-*/
- new_plane_state =
- intel_atomic_get_new_plane_state(state, master);
-
- intel_update_slave(plane, new_crtc_state,
new_plane_state);
} else {
intel_disable_plane(plane, new_crtc_state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index 123404a9cf23..726ececd6abd 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -25,9 +25,6 @@ void intel_plane_copy_uapi_to_hw_state(struct
intel_plane_state *plane_state,
void intel_update_plane(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
-void intel_update_slave(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state);
void intel_disable_plane(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state);
struct intel_plane *intel_plane_alloc(void);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index de520d5f1374..88f149cac198 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11768,6 +11768,24 @@ static int icl_check_nv12_planes(struct
intel_crtc_state *crtc_state)
crtc_state->active_planes |= BIT(linked->id);
crtc_state->update_planes |= BIT(linked->id);
DRM_DEBUG_KMS("Using %s as Y plane for %s\n",
linked->base.name, plane->base.name);
+
+ /* Copy parameters to slave plane */
+ linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
+ linked_state->color_ctl = plane_state->color_ctl;
+ linked_state->color_plane[0] = plane_state->color_plane[0];
+
+ intel_plane_copy_uapi_to_hw_state(linked_state, plane_state);
+ linked_state->uapi.src = plane_state->ua
[Intel-gfx] [PATCH 13/14] drm/i915: Complete plane hw and uapi split, v2.
Splitting plane state is easier than splitting crtc_state,
before plane check we copy the drm properties to hw so we can
do the same in bigjoiner later on.
We copy the state after we did all the modeset handling, but fortunately
i915 seems to be split correctly and nothing during modeset looks
at plane_state.
Changes since v1:
- Do not clear hw state on duplication.
Signed-off-by: Maarten Lankhorst
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 37 ++-
.../gpu/drm/i915/display/intel_atomic_plane.h | 2 +
drivers/gpu/drm/i915/display/intel_display.c | 1 +
.../drm/i915/display/intel_display_types.h| 23 +---
4 files changed, 57 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index e4044abc2d21..d9b65e9c45fc 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -93,6 +93,10 @@ intel_plane_duplicate_state(struct drm_plane *plane)
intel_state->vma = NULL;
intel_state->flags = 0;
+ /* add reference to fb */
+ if (intel_state->hw.fb)
+ drm_framebuffer_get(intel_state->hw.fb);
+
return &intel_state->uapi;
}
@@ -112,6 +116,8 @@ intel_plane_destroy_state(struct drm_plane *plane,
WARN_ON(plane_state->vma);
__drm_atomic_helper_plane_destroy_state(&plane_state->uapi);
+ if (plane_state->hw.fb)
+ drm_framebuffer_put(plane_state->hw.fb);
kfree(plane_state);
}
@@ -138,15 +144,44 @@ unsigned int intel_plane_data_rate(const struct
intel_crtc_state *crtc_state,
return cpp * crtc_state->pixel_rate;
}
+static void intel_plane_clear_hw_state(struct intel_plane_state *plane_state)
+{
+ if (plane_state->hw.fb)
+ drm_framebuffer_put(plane_state->hw.fb);
+
+ memset(&plane_state->hw, 0, sizeof(plane_state->hw));
+}
+
+void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
+ const struct intel_plane_state
*from_plane_state)
+{
+ intel_plane_clear_hw_state(plane_state);
+
+ plane_state->hw.crtc = from_plane_state->uapi.crtc;
+ plane_state->hw.fb = from_plane_state->uapi.fb;
+ if (plane_state->hw.fb)
+ drm_framebuffer_get(plane_state->hw.fb);
+
+ plane_state->hw.alpha = from_plane_state->uapi.alpha;
+ plane_state->hw.pixel_blend_mode =
+ from_plane_state->uapi.pixel_blend_mode;
+ plane_state->hw.rotation = from_plane_state->uapi.rotation;
+ plane_state->hw.color_encoding = from_plane_state->uapi.color_encoding;
+ plane_state->hw.color_range = from_plane_state->uapi.color_range;
+}
+
int intel_plane_atomic_check_with_state(const struct intel_crtc_state
*old_crtc_state,
struct intel_crtc_state *new_crtc_state,
const struct intel_plane_state
*old_plane_state,
struct intel_plane_state
*new_plane_state)
{
struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
- const struct drm_framebuffer *fb = new_plane_state->hw.fb;
+ const struct drm_framebuffer *fb;
int ret;
+ intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state);
+ fb = new_plane_state->hw.fb;
+
new_crtc_state->active_planes &= ~BIT(plane->id);
new_crtc_state->nv12_planes &= ~BIT(plane->id);
new_crtc_state->c8_planes &= ~BIT(plane->id);
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index dc85af02e9b7..123404a9cf23 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -20,6 +20,8 @@ extern const struct drm_plane_helper_funcs
intel_plane_helper_funcs;
unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
+void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
+ const struct intel_plane_state
*from_plane_state);
void intel_update_plane(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index a09034a1241f..de520d5f1374 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3254,6 +3254,7 @@ intel_find_initial_plane_obj(struct intel_crtc
*intel_crtc,
plane_state->fb = fb;
plane_state->crtc = &intel_crtc->base;
+ intel_plane_copy_uapi_to_hw_state(intel_state, intel_state);
atomi
[Intel-gfx] [PATCH 06/14] drm/i915: Perform automated conversions for crtc uapi/hw split, base -> hw.
Split up crtc_state->base to hw where appropriate. This is done using the
following patch:
@@
struct intel_crtc_state *T;
identifier x =~
"^(active|enable|degamma_lut|gamma_lut|ctm|mode|adjusted_mode)$";
@@
-T->base.x
+T->hw.x
@@
struct drm_crtc_state *T;
identifier x =~
"^(active|enable|degamma_lut|gamma_lut|ctm|mode|adjusted_mode)$";
@@
-to_intel_crtc_state(T)->base.x
+to_intel_crtc_state(T)->hw.x
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/icl_dsi.c| 12 +-
drivers/gpu/drm/i915/display/intel_audio.c| 4 +-
drivers/gpu/drm/i915/display/intel_cdclk.c| 8 +-
drivers/gpu/drm/i915/display/intel_color.c| 108
drivers/gpu/drm/i915/display/intel_crt.c | 18 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 18 +-
drivers/gpu/drm/i915/display/intel_display.c | 252 +-
drivers/gpu/drm/i915/display/intel_dp.c | 22 +-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 6 +-
drivers/gpu/drm/i915/display/intel_dvo.c | 12 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 20 +-
drivers/gpu/drm/i915/display/intel_lspcon.c | 4 +-
drivers/gpu/drm/i915/display/intel_lvds.c | 8 +-
drivers/gpu/drm/i915/display/intel_panel.c| 8 +-
drivers/gpu/drm/i915/display/intel_pipe_crc.c | 2 +-
drivers/gpu/drm/i915/display/intel_psr.c | 12 +-
drivers/gpu/drm/i915/display/intel_sdvo.c | 16 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 8 +-
drivers/gpu/drm/i915/display/intel_tv.c | 4 +-
drivers/gpu/drm/i915/display/intel_vdsc.c | 4 +-
drivers/gpu/drm/i915/display/vlv_dsi.c| 10 +-
drivers/gpu/drm/i915/i915_debugfs.c | 8 +-
drivers/gpu/drm/i915/intel_pm.c | 62 ++---
24 files changed, 316 insertions(+), 312 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index 6e398c33a524..4ec493e4755b 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -276,7 +276,7 @@ static void configure_dual_link_mode(struct intel_encoder
*encoder,
if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
const struct drm_display_mode *adjusted_mode =
- &pipe_config->base.adjusted_mode;
+ &pipe_config->hw.adjusted_mode;
u32 dss_ctl2;
u16 hactive = adjusted_mode->crtc_hdisplay;
u16 dl_buffer_depth;
@@ -768,7 +768,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder
*encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
const struct drm_display_mode *adjusted_mode =
- &pipe_config->base.adjusted_mode;
+ &pipe_config->hw.adjusted_mode;
enum port port;
enum transcoder dsi_trans;
/* horizontal timings */
@@ -1216,7 +1216,7 @@ static void gen11_dsi_get_timings(struct intel_encoder
*encoder,
{
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
struct drm_display_mode *adjusted_mode =
- &pipe_config->base.adjusted_mode;
+ &pipe_config->hw.adjusted_mode;
if (intel_dsi->dual_link) {
adjusted_mode->crtc_hdisplay *= 2;
@@ -1249,9 +1249,9 @@ static void gen11_dsi_get_config(struct intel_encoder
*encoder,
pipe_config->port_clock =
cnl_calc_wrpll_link(dev_priv, &pipe_config->dpll_hw_state);
- pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;
+ pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk;
if (intel_dsi->dual_link)
- pipe_config->base.adjusted_mode.crtc_clock *= 2;
+ pipe_config->hw.adjusted_mode.crtc_clock *= 2;
gen11_dsi_get_timings(encoder, pipe_config);
pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
@@ -1269,7 +1269,7 @@ static int gen11_dsi_compute_config(struct intel_encoder
*encoder,
const struct drm_display_mode *fixed_mode =
intel_connector->panel.fixed_mode;
struct drm_display_mode *adjusted_mode =
- &pipe_config->base.adjusted_mode;
+ &pipe_config->hw.adjusted_mode;
pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
intel_fixed_panel_mode(fixed_mode, adjusted_mode);
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
b/drivers/gpu/drm/i915/display/intel_audio.c
index ed18511befa3..6a58e8ad86f8 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -233,7 +233,7 @@ static const struct hdmi_aud_ncts
[Intel-gfx] [PATCH 09/14] drm/i915: Add aliases for uapi and hw to plane_state
Prepare to split up hw and uapi machinally, by adding a uapi and
hw alias. We will remove the base in a bit. This is a split from the
original uapi/hw patch, which did it all in one go.
Signed-off-by: Maarten Lankhorst
---
.../gpu/drm/i915/display/intel_atomic_plane.c| 16
.../gpu/drm/i915/display/intel_display_types.h | 8 ++--
2 files changed, 14 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index d92c185d4b4a..4b12eeb6850d 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -80,22 +80,20 @@ void intel_plane_free(struct intel_plane *plane)
struct drm_plane_state *
intel_plane_duplicate_state(struct drm_plane *plane)
{
- struct drm_plane_state *state;
struct intel_plane_state *intel_state;
- intel_state = kmemdup(plane->state, sizeof(*intel_state), GFP_KERNEL);
+ intel_state = to_intel_plane_state(plane->state);
+ intel_state = kmemdup(intel_state, sizeof(*intel_state), GFP_KERNEL);
if (!intel_state)
return NULL;
- state = &intel_state->base;
-
- __drm_atomic_helper_plane_duplicate_state(plane, state);
+ __drm_atomic_helper_plane_duplicate_state(plane, &intel_state->base);
intel_state->vma = NULL;
intel_state->flags = 0;
- return state;
+ return &intel_state->base;
}
/**
@@ -110,9 +108,11 @@ void
intel_plane_destroy_state(struct drm_plane *plane,
struct drm_plane_state *state)
{
- WARN_ON(to_intel_plane_state(state)->vma);
+ struct intel_plane_state *plane_state = to_intel_plane_state(state);
+ WARN_ON(plane_state->vma);
- drm_atomic_helper_plane_destroy_state(plane, state);
+ __drm_atomic_helper_plane_destroy_state(&plane_state->base);
+ kfree(plane_state);
}
unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 41d471ab9a64..9cae42e6520f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -515,7 +515,11 @@ struct intel_atomic_state {
};
struct intel_plane_state {
- struct drm_plane_state base;
+ union {
+ struct drm_plane_state base;
+ struct drm_plane_state uapi;
+ struct drm_plane_state hw;
+ };
struct i915_ggtt_view view;
struct i915_vma *vma;
unsigned long flags;
@@ -1125,7 +1129,7 @@ struct cxsr_latency {
#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
#define to_intel_plane(x) container_of(x, struct intel_plane, base)
-#define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
+#define to_intel_plane_state(x) container_of(x, struct intel_plane_state, uapi)
#define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
struct intel_hdmi {
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 12/14] drm/i915: Perform automated conversions for plane uapi/hw split, base -> uapi.
Split up plane_state->base to uapi. This is done using the following patch,
ran after the previous commit that splits out any hw references:
@@
struct intel_plane_state *T;
identifier x;
@@
-T->base.x
+T->uapi.x
@@
struct intel_plane_state *T;
@@
-T->base
+T->uapi
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_atomic.c | 2 +-
.../gpu/drm/i915/display/intel_atomic_plane.c | 28 +-
drivers/gpu/drm/i915/display/intel_display.c | 290 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 12 +-
drivers/gpu/drm/i915/display/intel_overlay.c | 2 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 114 +++
drivers/gpu/drm/i915/intel_pm.c | 57 ++--
7 files changed, 254 insertions(+), 251 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
b/drivers/gpu/drm/i915/display/intel_atomic.c
index 9ba50fd1116c..4783d7ff4fcf 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -299,7 +299,7 @@ static void intel_atomic_setup_scaler(struct
intel_crtc_scaler_state *scaler_sta
if (plane_state && plane_state->hw.fb &&
plane_state->hw.fb->format->is_yuv &&
plane_state->hw.fb->format->num_planes > 1) {
- struct intel_plane *plane =
to_intel_plane(plane_state->base.plane);
+ struct intel_plane *plane =
to_intel_plane(plane_state->uapi.plane);
if (IS_GEN(dev_priv, 9) &&
!IS_GEMINILAKE(dev_priv)) {
mode = SKL_PS_SCALER_MODE_NV12;
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index fd5a8012859c..e4044abc2d21 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -56,7 +56,7 @@ struct intel_plane *intel_plane_alloc(void)
return ERR_PTR(-ENOMEM);
}
- __drm_atomic_helper_plane_reset(&plane->base, &plane_state->base);
+ __drm_atomic_helper_plane_reset(&plane->base, &plane_state->uapi);
plane_state->scaler_id = -1;
return plane;
@@ -88,12 +88,12 @@ intel_plane_duplicate_state(struct drm_plane *plane)
if (!intel_state)
return NULL;
- __drm_atomic_helper_plane_duplicate_state(plane, &intel_state->base);
+ __drm_atomic_helper_plane_duplicate_state(plane, &intel_state->uapi);
intel_state->vma = NULL;
intel_state->flags = 0;
- return &intel_state->base;
+ return &intel_state->uapi;
}
/**
@@ -111,7 +111,7 @@ intel_plane_destroy_state(struct drm_plane *plane,
struct intel_plane_state *plane_state = to_intel_plane_state(state);
WARN_ON(plane_state->vma);
- __drm_atomic_helper_plane_destroy_state(&plane_state->base);
+ __drm_atomic_helper_plane_destroy_state(&plane_state->uapi);
kfree(plane_state);
}
@@ -121,7 +121,7 @@ unsigned int intel_plane_data_rate(const struct
intel_crtc_state *crtc_state,
const struct drm_framebuffer *fb = plane_state->hw.fb;
unsigned int cpp;
- if (!plane_state->base.visible)
+ if (!plane_state->uapi.visible)
return 0;
cpp = fb->format->cpp[0];
@@ -143,7 +143,7 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
const struct intel_plane_state
*old_plane_state,
struct intel_plane_state
*new_plane_state)
{
- struct intel_plane *plane = to_intel_plane(new_plane_state->base.plane);
+ struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
const struct drm_framebuffer *fb = new_plane_state->hw.fb;
int ret;
@@ -151,7 +151,7 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
new_crtc_state->nv12_planes &= ~BIT(plane->id);
new_crtc_state->c8_planes &= ~BIT(plane->id);
new_crtc_state->data_rate[plane->id] = 0;
- new_plane_state->base.visible = false;
+ new_plane_state->uapi.visible = false;
if (!new_plane_state->hw.crtc && !old_plane_state->hw.crtc)
return 0;
@@ -161,18 +161,18 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
return ret;
/* FIXME pre-g4x don't work like this */
- if (new_plane_state->base.visible)
+ if (new_plane_state->uapi.visible)
new_crtc_state->active_planes |= BIT(plane->id);
- if (new_plane_state->base.visible &&
+ if (new_plane_state->uapi.visible &&
drm_format_info_is_yuv_semiplanar(fb->format))
new_crtc_state->nv12_planes |= BIT(plane->id);
- if (new_plane_state->base.visible &&
+ if (new_plane_state->uapi.visible &&
fb->format->format == DRM_FORMAT_C8)
[Intel-gfx] [PATCH 02/14] drm/i915: Introduce intel_atomic_get_plane_state_after_check(), v2.
Use this in all the places where we try to acquire planes after the planes
atomic_check().
In case of intel_modeset_all_pipes() this is not yet done after atomic_check,
but seems like it will be in the future. To add some paranoia, add all planes
rather than active planes, because of bigjoiner and planar YUV support having
extra planes outside of the core's view that wouldn't be added otherwise.
Changes since v1:
- Always add all planes, to handle force plane updates to work correctly
with a disabled cursor plane.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_atomic.c | 41 +--
.../gpu/drm/i915/display/intel_atomic_plane.c | 15 +++
drivers/gpu/drm/i915/display/intel_cdclk.c| 15 ---
drivers/gpu/drm/i915/display/intel_color.c| 7 ++--
.../drm/i915/display/intel_display_types.h| 6 +++
drivers/gpu/drm/i915/intel_pm.c | 14 ---
6 files changed, 62 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
b/drivers/gpu/drm/i915/display/intel_atomic.c
index c5a552a69752..e6cb85d41c8d 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -313,13 +313,10 @@ int intel_atomic_setup_scalers(struct drm_i915_private
*dev_priv,
struct intel_crtc *intel_crtc,
struct intel_crtc_state *crtc_state)
{
- struct drm_plane *plane = NULL;
- struct intel_plane *intel_plane;
- struct intel_plane_state *plane_state = NULL;
struct intel_crtc_scaler_state *scaler_state =
&crtc_state->scaler_state;
struct drm_atomic_state *drm_state = crtc_state->base.state;
- struct intel_atomic_state *intel_state =
to_intel_atomic_state(drm_state);
+ struct intel_atomic_state *state = to_intel_atomic_state(drm_state);
int num_scalers_need;
int i;
@@ -346,6 +343,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private
*dev_priv,
/* walkthrough scaler_users bits and start assigning scalers */
for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) {
+ struct intel_plane_state *plane_state = NULL;
int *scaler_id;
const char *name;
int idx;
@@ -361,19 +359,16 @@ int intel_atomic_setup_scalers(struct drm_i915_private
*dev_priv,
/* panel fitter case: assign as a crtc scaler */
scaler_id = &scaler_state->scaler_id;
} else {
- name = "PLANE";
+ struct intel_plane *plane;
/* plane scaler case: assign as a plane scaler */
/* find the plane that set the bit as scaler_user */
- plane = drm_state->planes[i].ptr;
/*
* to enable/disable hq mode, add planes that are using
scaler
* into this transaction
*/
- if (!plane) {
- struct drm_plane_state *state;
-
+ if (!drm_state->planes[i].ptr) {
/*
* GLK+ scalers don't have a HQ mode so it
* isn't necessary to change between HQ and dyn
mode
@@ -382,24 +377,28 @@ int intel_atomic_setup_scalers(struct drm_i915_private
*dev_priv,
if (INTEL_GEN(dev_priv) >= 10 ||
IS_GEMINILAKE(dev_priv))
continue;
- plane = drm_plane_from_index(&dev_priv->drm, i);
- state = drm_atomic_get_plane_state(drm_state,
plane);
- if (IS_ERR(state)) {
- DRM_DEBUG_KMS("Failed to add [PLANE:%d]
to drm_state\n",
- plane->base.id);
- return PTR_ERR(state);
+ plane =
to_intel_plane(drm_plane_from_index(&dev_priv->drm, i));
+ plane_state =
+
intel_atomic_get_plane_state_after_check(state,
+
crtc_state,
+
plane);
+ if (IS_ERR(plane_state)) {
+ DRM_DEBUG_KMS("Failed to add [PLANE:%d]
to drm_state: %li\n",
+ plane->base.base.id,
PTR_ERR(plane_state));
+ return PTR_ERR(plane_state);
}
+ } else {
+ plane =
to_intel_plane(drm_state->pl
[Intel-gfx] [PATCH 05/14] drm/i915: Perform manual conversions for crtc uapi/hw split
intel_get_load_detect_pipe() needs to set uapi active,
uapi enable is set by the call to drm_atomic_set_mode_for_crtc(),
so we can remove it.
intel_pipe_config_compare() needs to look at hw state, but I didn't
change spatch to look at it. It's easy enough to do manually.
intel_atomic_check() definitely needs to check for uapi enable,
otherwise intel_modeset_pipe_config cannot copy uapi state to hw.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 42 ++--
1 file changed, 21 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index fa0abfdff2ae..adb70d76a61c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11214,7 +11214,7 @@ int intel_get_load_detect_pipe(struct drm_connector
*connector,
goto fail;
}
- crtc_state->base.active = crtc_state->base.enable = true;
+ crtc_state->hw.active = true;
if (!mode)
mode = &load_detect_mode;
@@ -12754,19 +12754,19 @@ intel_pipe_config_compare(const struct
intel_crtc_state *current_config,
PIPE_CONF_CHECK_X(output_types);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
PIPE_CONF_CHECK_I(pixel_multiplier);
PIPE_CONF_CHECK_I(output_format);
@@ -12783,17 +12783,17 @@ intel_pipe_config_compare(const struct
intel_crtc_state *current_config,
PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
- PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
+ PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
DRM_MODE_FLAG_INTERLACE);
if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
- PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
+ PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
DRM_MODE_FLAG_PHSYNC);
- PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
+ PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
DRM_MODE_FLAG_NHSYNC);
- PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
+ PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
DRM_MODE_FLAG_PVSYNC);
- PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
+ PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
DRM_MODE_FLAG_NVSYNC);
}
@@ -12832,7 +12832,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
if (bp_gamma)
- PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, base.gamma_lut,
bp_gamma);
+ PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut,
bp_gamma);
}
@@ -12877,7 +12877,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
PIPE_CONF_CHECK_I(pipe_bpp);
- PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
+ PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
PIPE_CONF_CHECK_I(min_voltage_level);
@@ -13572,7 +13572,7 @@ static int intel_atomic_check(struct drm_device *dev,
if (!needs_modeset(new_crtc_state))
continue;
- if (!new_crtc_s
