[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: add basic selftests for rc6 (rev7)
== Series Details == Series: drm/i915/selftests: add basic selftests for rc6 (rev7) URL : https://patchwork.freedesktop.org/series/69825/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7874 -> Patchwork_16452 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_16452 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_16452, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16452/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_16452: ### IGT changes ### Possible regressions * igt@i915_selftest@live_gt_pm: - fi-cfl-8700k: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-cfl-8700k/igt@i915_selftest@live_gt_pm.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16452/fi-cfl-8700k/igt@i915_selftest@live_gt_pm.html - fi-kbl-r: [PASS][3] -> [DMESG-FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-kbl-r/igt@i915_selftest@live_gt_pm.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16452/fi-kbl-r/igt@i915_selftest@live_gt_pm.html - fi-byt-j1900: [PASS][5] -> [DMESG-FAIL][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-byt-j1900/igt@i915_selftest@live_gt_pm.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16452/fi-byt-j1900/igt@i915_selftest@live_gt_pm.html - fi-kbl-x1275: [PASS][7] -> [DMESG-FAIL][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-kbl-x1275/igt@i915_selftest@live_gt_pm.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16452/fi-kbl-x1275/igt@i915_selftest@live_gt_pm.html - fi-kbl-guc: [PASS][9] -> [DMESG-FAIL][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-kbl-guc/igt@i915_selftest@live_gt_pm.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16452/fi-kbl-guc/igt@i915_selftest@live_gt_pm.html - fi-skl-guc: [PASS][11] -> [DMESG-FAIL][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-skl-guc/igt@i915_selftest@live_gt_pm.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16452/fi-skl-guc/igt@i915_selftest@live_gt_pm.html - fi-icl-u3: [PASS][13] -> [DMESG-FAIL][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-icl-u3/igt@i915_selftest@live_gt_pm.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16452/fi-icl-u3/igt@i915_selftest@live_gt_pm.html - fi-bdw-5557u: [PASS][15] -> [DMESG-FAIL][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-bdw-5557u/igt@i915_selftest@live_gt_pm.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16452/fi-bdw-5557u/igt@i915_selftest@live_gt_pm.html - fi-snb-2600:[PASS][17] -> [DMESG-FAIL][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-snb-2600/igt@i915_selftest@live_gt_pm.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16452/fi-snb-2600/igt@i915_selftest@live_gt_pm.html - fi-glk-dsi: [PASS][19] -> [DMESG-FAIL][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-glk-dsi/igt@i915_selftest@live_gt_pm.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16452/fi-glk-dsi/igt@i915_selftest@live_gt_pm.html - fi-icl-guc: [PASS][21] -> [DMESG-FAIL][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-icl-guc/igt@i915_selftest@live_gt_pm.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16452/fi-icl-guc/igt@i915_selftest@live_gt_pm.html - fi-skl-6700k2: [PASS][23] -> [DMESG-FAIL][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-skl-6700k2/igt@i915_selftest@live_gt_pm.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16452/fi-skl-6700k2/igt@i915_selftest@live_gt_pm.html - fi-bsw-n3050: [PASS][25] -> [DMESG-FAIL][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-bsw-n3050/igt@i915_selftest@live_gt_pm.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16452/fi-bsw-n3050/igt@i915_selftest@live_gt_pm.html - fi-whl-u: [PASS][27] -> [DMESG-FAIL][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-whl-u/igt@i915_selftest@live_gt_pm.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16452/fi-whl-u/igt@i915_selftest@live_gt_pm.html - fi-skl-6770hq: [PASS][29] -> [DMESG-FAIL][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-skl-6770hq/igt@i915_selftest@live_gt_pm.html [30]:
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/3] drm/i915/display/fbc: Make fences a nice-to-have for GEN11+
== Series Details == Series: series starting with [v2,1/3] drm/i915/display/fbc: Make fences a nice-to-have for GEN11+ URL : https://patchwork.freedesktop.org/series/73070/ State : success == Summary == CI Bug Log - changes from CI_DRM_7874 -> Patchwork_16451 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16451/index.html Known issues Here are the changes found in Patchwork_16451 that come from known issues: ### IGT changes ### Issues hit * igt@gem_close_race@basic-threads: - fi-byt-n2820: [PASS][1] -> [INCOMPLETE][2] ([i915#45]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-byt-n2820/igt@gem_close_r...@basic-threads.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16451/fi-byt-n2820/igt@gem_close_r...@basic-threads.html * igt@i915_pm_rpm@basic-pci-d3-state: - fi-skl-6770hq: [PASS][3] -> [INCOMPLETE][4] ([i915#151]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-skl-6770hq/igt@i915_pm_...@basic-pci-d3-state.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16451/fi-skl-6770hq/igt@i915_pm_...@basic-pci-d3-state.html * igt@i915_selftest@live_execlists: - fi-icl-y: [PASS][5] -> [DMESG-FAIL][6] ([fdo#108569]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-icl-y/igt@i915_selftest@live_execlists.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16451/fi-icl-y/igt@i915_selftest@live_execlists.html * igt@i915_selftest@live_gem_contexts: - fi-byt-j1900: [PASS][7] -> [DMESG-FAIL][8] ([i915#1052]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16451/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html - fi-cfl-8700k: [PASS][9] -> [DMESG-FAIL][10] ([i915#623]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16451/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html * igt@i915_selftest@live_gtt: - fi-kbl-7500u: [PASS][11] -> [TIMEOUT][12] ([fdo#112271]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-kbl-7500u/igt@i915_selftest@live_gtt.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16451/fi-kbl-7500u/igt@i915_selftest@live_gtt.html * igt@prime_self_import@basic-with_one_bo_two_files: - fi-tgl-y: [PASS][13] -> [DMESG-WARN][14] ([CI#94] / [i915#402]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16451/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html Possible fixes * igt@kms_addfb_basic@addfb25-bad-modifier: - fi-tgl-y: [DMESG-WARN][15] ([CI#94] / [i915#402]) -> [PASS][16] +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-tgl-y/igt@kms_addfb_ba...@addfb25-bad-modifier.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16451/fi-tgl-y/igt@kms_addfb_ba...@addfb25-bad-modifier.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-icl-u2: [DMESG-WARN][17] ([IGT#4] / [i915#263]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16451/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@hdmi-crc-fast: - fi-icl-u2: [FAIL][19] ([fdo#109635] / [i915#217]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-icl-u2/igt@kms_chamel...@hdmi-crc-fast.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16451/fi-icl-u2/igt@kms_chamel...@hdmi-crc-fast.html Warnings * igt@gem_exec_parallel@contexts: - fi-byt-j1900: [TIMEOUT][21] ([fdo#112271] / [i915#1084]) -> [FAIL][22] ([i915#694]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-byt-j1900/igt@gem_exec_paral...@contexts.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16451/fi-byt-j1900/igt@gem_exec_paral...@contexts.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][23] ([fdo#111096] / [i915#323]) -> [FAIL][24] ([fdo#111407]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16451/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94 [IGT#4]:
[Intel-gfx] [drm-tip:drm-tip 6/9] drivers/gpu/drm/i915/display/intel_display.c:17667:12: error: 'sanitize_watermarks_add_affected' defined but not used
tree: git://anongit.freedesktop.org/drm/drm-tip drm-tip
head: aed2ea22e07850d8f5fae07fcf3db8adf694b3d9
commit: 9c654e423507127b37b32e15543b2e04a719eab2 [6/9] Merge remote-tracking
branch 'drm-intel/drm-intel-next-queued' into drm-tip
config: i386-randconfig-g002-20200206 (attached as .config)
compiler: gcc-7 (Debian 7.5.0-3) 7.5.0
reproduce:
git checkout 9c654e423507127b37b32e15543b2e04a719eab2
# save the attached .config to linux build tree
make ARCH=i386
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot
All errors (new ones prefixed by >>):
drivers/gpu/drm/i915/display/intel_display.c:17691:12: error: redefinition
of 'sanitize_watermarks_add_affected'
static int sanitize_watermarks_add_affected(struct drm_atomic_state *state)
^~~~
drivers/gpu/drm/i915/display/intel_display.c:17667:12: note: previous
definition of 'sanitize_watermarks_add_affected' was here
static int sanitize_watermarks_add_affected(struct drm_atomic_state *state)
^~~~
>> drivers/gpu/drm/i915/display/intel_display.c:17667:12: error:
>> 'sanitize_watermarks_add_affected' defined but not used
>> [-Werror=unused-function]
cc1: all warnings being treated as errors
vim +/sanitize_watermarks_add_affected +17667
drivers/gpu/drm/i915/display/intel_display.c
17666
17667 static int sanitize_watermarks_add_affected(struct drm_atomic_state
*state)
17668 {
17669 struct drm_plane *plane;
17670 struct drm_crtc *crtc;
17671
17672 drm_for_each_crtc(crtc, state->dev) {
17673 struct drm_crtc_state *crtc_state;
17674
17675 crtc_state = drm_atomic_get_crtc_state(state, crtc);
17676 if (IS_ERR(crtc_state))
17677 return PTR_ERR(crtc_state);
17678 }
17679
17680 drm_for_each_plane(plane, state->dev) {
17681 struct drm_plane_state *plane_state;
17682
17683 plane_state = drm_atomic_get_plane_state(state, plane);
17684 if (IS_ERR(plane_state))
17685 return PTR_ERR(plane_state);
17686 }
17687
17688 return 0;
17689 }
17690
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org Intel Corporation
.config.gz
Description: application/gzip
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/3] drm/i915/display/fbc: Make fences a nice-to-have for GEN11+
== Series Details == Series: series starting with [v2,1/3] drm/i915/display/fbc: Make fences a nice-to-have for GEN11+ URL : https://patchwork.freedesktop.org/series/73070/ State : warning == Summary == $ dim checkpatch origin/drm-tip 33582ba1b9a2 drm/i915/display/fbc: Make fences a nice-to-have for GEN11+ -:152: CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u64' over 'uint64_t' #152: FILE: drivers/gpu/drm/i915/i915_drv.h:416: + uint64_t modifier; total: 0 errors, 0 warnings, 1 checks, 97 lines checked 5f1785f24440 drm/i915/display: Do not write in removed FBC fence registers ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/gt: Tweak gen7 xcs flushing
== Series Details == Series: series starting with [1/3] drm/i915/gt: Tweak gen7 xcs flushing URL : https://patchwork.freedesktop.org/series/73068/ State : success == Summary == CI Bug Log - changes from CI_DRM_7874 -> Patchwork_16450 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/index.html Known issues Here are the changes found in Patchwork_16450 that come from known issues: ### IGT changes ### Issues hit * igt@gem_close_race@basic-threads: - fi-byt-j1900: [PASS][1] -> [INCOMPLETE][2] ([i915#45]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-byt-j1900/igt@gem_close_r...@basic-threads.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/fi-byt-j1900/igt@gem_close_r...@basic-threads.html * igt@gem_flink_basic@bad-flink: - fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([CI#94] / [i915#402]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-tgl-y/igt@gem_flink_ba...@bad-flink.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/fi-tgl-y/igt@gem_flink_ba...@bad-flink.html * igt@i915_selftest@live_blt: - fi-hsw-4770:[PASS][5] -> [DMESG-FAIL][6] ([i915#553] / [i915#725]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-hsw-4770/igt@i915_selftest@live_blt.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/fi-hsw-4770/igt@i915_selftest@live_blt.html Possible fixes * igt@gem_exec_suspend@basic-s4-devices: - fi-tgl-y: [FAIL][7] ([CI#94]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-tgl-y/igt@gem_exec_susp...@basic-s4-devices.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/fi-tgl-y/igt@gem_exec_susp...@basic-s4-devices.html * igt@i915_selftest@live_gem_contexts: - fi-byt-n2820: [DMESG-FAIL][9] ([i915#722]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html * igt@kms_addfb_basic@addfb25-bad-modifier: - fi-tgl-y: [DMESG-WARN][11] ([CI#94] / [i915#402]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-tgl-y/igt@kms_addfb_ba...@addfb25-bad-modifier.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/fi-tgl-y/igt@kms_addfb_ba...@addfb25-bad-modifier.html * igt@kms_chamelium@hdmi-crc-fast: - fi-icl-u2: [FAIL][13] ([fdo#109635] / [i915#217]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-icl-u2/igt@kms_chamel...@hdmi-crc-fast.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/fi-icl-u2/igt@kms_chamel...@hdmi-crc-fast.html Warnings * igt@gem_exec_parallel@contexts: - fi-byt-n2820: [TIMEOUT][15] ([fdo#112271] / [i915#1084]) -> [FAIL][16] ([i915#694]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-byt-n2820/igt@gem_exec_paral...@contexts.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16450/fi-byt-n2820/igt@gem_exec_paral...@contexts.html [CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94 [fdo#109635]: https://bugs.freedesktop.org/show_bug.cgi?id=109635 [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271 [i915#1084]: https://gitlab.freedesktop.org/drm/intel/issues/1084 [i915#217]: https://gitlab.freedesktop.org/drm/intel/issues/217 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45 [i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553 [i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694 [i915#722]: https://gitlab.freedesktop.org/drm/intel/issues/722 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 Participating hosts (51 -> 42) -- Missing(9): fi-bsw-n3050 fi-byt-squawks fi-bsw-cyan fi-cfl-8109u fi-kbl-7560u fi-byt-clapper fi-bsw-nick fi-bdw-samus fi-kbl-r Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7874 -> Patchwork_16450 CI-20190529: 20190529 CI_DRM_7874: 3f234d1ab91ec2321312150116c1285bcb0a260b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5420: 497e13d2b4c1053bcd01bd15739fef55e7694a03 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16450: 9a7a58a2f90a9615540ad59a219bbfcb92ef66fa @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 9a7a58a2f90a drm/i915/gt: Stop invalidating the PD cachelines for gen7 ffb456a12e2a drm/i915/gt: Set the PP_DIR registers upon enabling ring submission be0c11af059b drm/i915/gt: Tweak gen7 xcs flushing ==
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Tweak gen7 xcs flushing
== Series Details == Series: drm/i915/gt: Tweak gen7 xcs flushing URL : https://patchwork.freedesktop.org/series/73067/ State : success == Summary == CI Bug Log - changes from CI_DRM_7874 -> Patchwork_16449 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16449/index.html Known issues Here are the changes found in Patchwork_16449 that come from known issues: ### IGT changes ### Issues hit * igt@gem_close_race@basic-threads: - fi-hsw-peppy: [PASS][1] -> [INCOMPLETE][2] ([i915#694] / [i915#816]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-hsw-peppy/igt@gem_close_r...@basic-threads.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16449/fi-hsw-peppy/igt@gem_close_r...@basic-threads.html - fi-byt-j1900: [PASS][3] -> [INCOMPLETE][4] ([i915#45]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-byt-j1900/igt@gem_close_r...@basic-threads.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16449/fi-byt-j1900/igt@gem_close_r...@basic-threads.html - fi-byt-n2820: [PASS][5] -> [INCOMPLETE][6] ([i915#45]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-byt-n2820/igt@gem_close_r...@basic-threads.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16449/fi-byt-n2820/igt@gem_close_r...@basic-threads.html * igt@i915_getparams_basic@basic-subslice-total: - fi-tgl-y: [PASS][7] -> [DMESG-WARN][8] ([CI#94] / [i915#402]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16449/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html * igt@i915_pm_rpm@module-reload: - fi-skl-6770hq: [PASS][9] -> [FAIL][10] ([i915#178]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-skl-6770hq/igt@i915_pm_...@module-reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16449/fi-skl-6770hq/igt@i915_pm_...@module-reload.html * igt@i915_selftest@live_gtt: - fi-icl-guc: [PASS][11] -> [TIMEOUT][12] ([fdo#112271]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-icl-guc/igt@i915_selftest@live_gtt.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16449/fi-icl-guc/igt@i915_selftest@live_gtt.html Possible fixes * igt@kms_addfb_basic@addfb25-bad-modifier: - fi-tgl-y: [DMESG-WARN][13] ([CI#94] / [i915#402]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-tgl-y/igt@kms_addfb_ba...@addfb25-bad-modifier.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16449/fi-tgl-y/igt@kms_addfb_ba...@addfb25-bad-modifier.html * igt@kms_chamelium@hdmi-crc-fast: - fi-icl-u2: [FAIL][15] ([fdo#109635] / [i915#217]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-icl-u2/igt@kms_chamel...@hdmi-crc-fast.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16449/fi-icl-u2/igt@kms_chamel...@hdmi-crc-fast.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][17] ([fdo#111096] / [i915#323]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16449/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94 [fdo#109635]: https://bugs.freedesktop.org/show_bug.cgi?id=109635 [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271 [i915#178]: https://gitlab.freedesktop.org/drm/intel/issues/178 [i915#217]: https://gitlab.freedesktop.org/drm/intel/issues/217 [i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45 [i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694 [i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816 Participating hosts (51 -> 42) -- Missing(9): fi-bdw-samus fi-byt-squawks fi-bsw-cyan fi-snb-2520m fi-ivb-3770 fi-kbl-7560u fi-byt-clapper fi-skl-6600u fi-snb-2600 Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7874 -> Patchwork_16449 CI-20190529: 20190529 CI_DRM_7874: 3f234d1ab91ec2321312150116c1285bcb0a260b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5420: 497e13d2b4c1053bcd01bd15739fef55e7694a03 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16449: 21f74c3d2a5bba1ef56875eed16d0ddec7bb4494 @ git://anongit.freedesktop.org/gfx-ci/linux ==
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/gt: Tweak gen7 xcs flushing
== Series Details == Series: series starting with [1/3] drm/i915/gt: Tweak gen7 xcs flushing URL : https://patchwork.freedesktop.org/series/73068/ State : warning == Summary == $ dim checkpatch origin/drm-tip be0c11af059b drm/i915/gt: Tweak gen7 xcs flushing -:51: WARNING:LONG_LINE: line over 100 characters #51: FILE: drivers/gpu/drm/i915/gt/intel_ring_submission.c:472: + GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); total: 0 errors, 1 warnings, 0 checks, 47 lines checked ffb456a12e2a drm/i915/gt: Set the PP_DIR registers upon enabling ring submission 9a7a58a2f90a drm/i915/gt: Stop invalidating the PD cachelines for gen7 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: Trim blitter block size
== Series Details == Series: drm/i915/selftests: Trim blitter block size URL : https://patchwork.freedesktop.org/series/73066/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7874 -> Patchwork_16448 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_16448 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_16448, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16448/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_16448: ### IGT changes ### Possible regressions * igt@i915_selftest@live_blt: - fi-whl-u: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-whl-u/igt@i915_selftest@live_blt.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16448/fi-whl-u/igt@i915_selftest@live_blt.html - fi-bdw-5557u: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-bdw-5557u/igt@i915_selftest@live_blt.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16448/fi-bdw-5557u/igt@i915_selftest@live_blt.html - fi-icl-u3: [PASS][5] -> [INCOMPLETE][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-icl-u3/igt@i915_selftest@live_blt.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16448/fi-icl-u3/igt@i915_selftest@live_blt.html - fi-cfl-8109u: [PASS][7] -> [INCOMPLETE][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-cfl-8109u/igt@i915_selftest@live_blt.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16448/fi-cfl-8109u/igt@i915_selftest@live_blt.html - fi-kbl-7500u: [PASS][9] -> [INCOMPLETE][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-kbl-7500u/igt@i915_selftest@live_blt.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16448/fi-kbl-7500u/igt@i915_selftest@live_blt.html - fi-kbl-guc: [PASS][11] -> [INCOMPLETE][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-kbl-guc/igt@i915_selftest@live_blt.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16448/fi-kbl-guc/igt@i915_selftest@live_blt.html - fi-kbl-8809g: [PASS][13] -> [INCOMPLETE][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-kbl-8809g/igt@i915_selftest@live_blt.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16448/fi-kbl-8809g/igt@i915_selftest@live_blt.html - fi-icl-guc: [PASS][15] -> [INCOMPLETE][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-icl-guc/igt@i915_selftest@live_blt.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16448/fi-icl-guc/igt@i915_selftest@live_blt.html - fi-kbl-r: [PASS][17] -> [INCOMPLETE][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-kbl-r/igt@i915_selftest@live_blt.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16448/fi-kbl-r/igt@i915_selftest@live_blt.html - fi-cfl-8700k: [PASS][19] -> [INCOMPLETE][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-cfl-8700k/igt@i915_selftest@live_blt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16448/fi-cfl-8700k/igt@i915_selftest@live_blt.html - fi-icl-u2: [PASS][21] -> [INCOMPLETE][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-icl-u2/igt@i915_selftest@live_blt.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16448/fi-icl-u2/igt@i915_selftest@live_blt.html - fi-kbl-x1275: [PASS][23] -> [INCOMPLETE][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-kbl-x1275/igt@i915_selftest@live_blt.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16448/fi-kbl-x1275/igt@i915_selftest@live_blt.html - fi-icl-dsi: [PASS][25] -> [INCOMPLETE][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-icl-dsi/igt@i915_selftest@live_blt.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16448/fi-icl-dsi/igt@i915_selftest@live_blt.html - fi-cfl-guc: [PASS][27] -> [INCOMPLETE][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-cfl-guc/igt@i915_selftest@live_blt.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16448/fi-cfl-guc/igt@i915_selftest@live_blt.html - fi-skl-6600u: [PASS][29] -> [DMESG-FAIL][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7874/fi-skl-6600u/igt@i915_selftest@live_blt.html [30]:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Trim blitter block size
== Series Details == Series: drm/i915/selftests: Trim blitter block size URL : https://patchwork.freedesktop.org/series/73066/ State : warning == Summary == $ dim checkpatch origin/drm-tip b4454179762f drm/i915/selftests: Trim blitter block size -:39: WARNING:MEMORY_BARRIER: memory barrier without comment #39: FILE: drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c:286: + mb(); -:68: WARNING:MEMORY_BARRIER: memory barrier without comment #68: FILE: drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c:410: + mb(); total: 0 errors, 2 warnings, 0 checks, 55 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Fix redefinition of sanitize_watermarks_add_affected
== Series Details == Series: drm/i915: Fix redefinition of sanitize_watermarks_add_affected URL : https://patchwork.freedesktop.org/series/73065/ State : failure == Summary == Applying: drm/i915: Fix redefinition of sanitize_watermarks_add_affected Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/display/intel_display.c Falling back to patching base and 3-way merge... No changes -- Patch already applied. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5] drm/i915/selftests: add basic selftests for rc6
From: Andi Shyti
Add three basic tests for rc6 power status:
1. live_rc6_basic - simply checks if rc6 works when it's enabled
or stops when it's disabled.
2. live_rc6_threshold - rc6 should not work when the evaluation
interval is less than the threshold and should work otherwise.
3. live_rc6_busy - keeps the gpu busy and then goes in idle;
checks that we don't fall in rc6 when busy and that we do fall
in rc6 when idling.
The three tests are added as sutest of the bigger live_late_gt_pm
selftest.
The basic rc6 functionality is tested by checking the reference
counter within the evaluation interval.
Signed-off-by: Andi Shyti
Cc: Chris Wilson
---
I sent the wrong patch, sorry, this is the right one.
Andi
Changelog:
* v4 -> v5:
- added changes in v4 which I forgot to include
- a small renaming and refactoring suggested by Mika to
make clear the purpose of the test function. Now it's
called "is_rc6_active" in a question format (and I
believe Chris won't like my creativity) and it returns
true if rc6 is active and false otherwise. Thanks, Mika!
- fixed a couple of typos.
* v3 -> v4:
- just a small refactoring where test_rc6 becomes a
measure function while another test_rc6 checks the
return value from the measure.
* v2 -> v3:
- rebased on top of the latest drm-tip
- fixed exiting order in rc6_basic to avoid exiting
without releasing the pm reference
* v1 -> v2:
- some changes from Chris (thank you!).
drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 2 +
drivers/gpu/drm/i915/gt/selftest_rc6.c | 179 +++
drivers/gpu/drm/i915/gt/selftest_rc6.h | 2 +
3 files changed, 183 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
index 09ff8e4f88af..5c7b92301a14 100644
--- a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
@@ -52,6 +52,8 @@ int intel_gt_pm_live_selftests(struct drm_i915_private *i915)
{
static const struct i915_subtest tests[] = {
SUBTEST(live_rc6_manual),
+ SUBTEST(live_rc6_threshold),
+ SUBTEST(live_rc6_busy),
SUBTEST(live_gt_resume),
};
diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c
b/drivers/gpu/drm/i915/gt/selftest_rc6.c
index 5f7e2dcf5686..7b5d476a8ad1 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rc6.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c
@@ -11,6 +11,7 @@
#include "selftest_rc6.h"
#include "selftests/i915_random.h"
+#include "selftests/igt_spinner.h"
int live_rc6_manual(void *arg)
{
@@ -202,3 +203,181 @@ int live_rc6_ctx_wa(void *arg)
kfree(engines);
return err;
}
+
+static u32 measure_rc6(struct intel_uncore *uncore, u32 interval)
+{
+ u32 ec1, ec2;
+
+ ec1 = intel_uncore_read(uncore, GEN6_GT_GFX_RC6);
+
+ /*
+* It's not important to precisely wait the interval time.
+* I'll wait at least twice the time in order to be sure
+* that the counting happens in the reference counter.
+*/
+ msleep(interval);
+
+ ec2 = intel_uncore_read(uncore, GEN6_GT_GFX_RC6);
+
+ pr_info("interval:%x [%dms], threshold:%x, rc6:%x\n",
+ intel_uncore_read(uncore, GEN6_RC_EVALUATION_INTERVAL),
+ interval,
+ intel_uncore_read(uncore, GEN6_RC6_THRESHOLD),
+ ec2 - ec1);
+
+ /* paranoia? ec2 is always supposed to be bigger */
+ return (ec2 >= ec1) ? ec2 - ec1 : 0;
+}
+
+static bool is_rc6_active(struct intel_rc6 *rc6)
+{
+ struct intel_uncore *uncore = rc6_to_uncore(rc6);
+ intel_wakeref_t wakeref;
+ u32 interval;
+
+ wakeref = intel_runtime_pm_get(uncore->rpm);
+
+ interval = intel_uncore_read(uncore, GEN6_RC_EVALUATION_INTERVAL);
+
+ /*
+* the interval is stored in steps of 1.28us
+*/
+ interval = div_u64(mul_u32_u32(interval, 128),
+ 100 * 1000); /* => milliseconds */
+
+ intel_runtime_pm_put(uncore->rpm, wakeref);
+
+ return !!measure_rc6(uncore, 2 * interval);
+}
+
+int live_rc6_threshold(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_uncore *uncore = gt->uncore;
+ struct intel_rc6 *rc6 = >rc6;
+ intel_wakeref_t wakeref;
+ u32 threshold, interval;
+ u32 t_orig, i_orig;
+ int err = 0;
+
+ if (!rc6->manual) /* No interfering PCU! */
+ return 0;
+
+ wakeref = intel_runtime_pm_get(uncore->rpm);
+
+ __intel_rc6_disable(rc6); /* stop before adjusting thresholds */
+
+ t_orig = intel_uncore_read(uncore, GEN6_RC6_THRESHOLD);
+ i_orig = intel_uncore_read(uncore, GEN6_RC_EVALUATION_INTERVAL);
+
+ /*
+* set the threshold to 50ms
+*
+* 50ms * 1000 = 5us
+* 5 / (1.28 * 100) / 100
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: add basic selftests for rc6 (rev6)
== Series Details == Series: drm/i915/selftests: add basic selftests for rc6 (rev6) URL : https://patchwork.freedesktop.org/series/69825/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7871 -> Patchwork_16446 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_16446 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_16446, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16446/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_16446: ### IGT changes ### Possible regressions * igt@i915_selftest@live_gt_pm: - fi-cfl-8700k: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-cfl-8700k/igt@i915_selftest@live_gt_pm.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16446/fi-cfl-8700k/igt@i915_selftest@live_gt_pm.html - fi-icl-u2: [PASS][3] -> [DMESG-FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-icl-u2/igt@i915_selftest@live_gt_pm.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16446/fi-icl-u2/igt@i915_selftest@live_gt_pm.html - fi-bsw-nick:[PASS][5] -> [DMESG-FAIL][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-bsw-nick/igt@i915_selftest@live_gt_pm.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16446/fi-bsw-nick/igt@i915_selftest@live_gt_pm.html - fi-icl-y: [PASS][7] -> [DMESG-FAIL][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-icl-y/igt@i915_selftest@live_gt_pm.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16446/fi-icl-y/igt@i915_selftest@live_gt_pm.html - fi-kbl-x1275: [PASS][9] -> [DMESG-FAIL][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-kbl-x1275/igt@i915_selftest@live_gt_pm.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16446/fi-kbl-x1275/igt@i915_selftest@live_gt_pm.html - fi-kbl-guc: [PASS][11] -> [DMESG-FAIL][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-kbl-guc/igt@i915_selftest@live_gt_pm.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16446/fi-kbl-guc/igt@i915_selftest@live_gt_pm.html - fi-skl-guc: [PASS][13] -> [DMESG-FAIL][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-skl-guc/igt@i915_selftest@live_gt_pm.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16446/fi-skl-guc/igt@i915_selftest@live_gt_pm.html - fi-icl-u3: [PASS][15] -> [DMESG-FAIL][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-icl-u3/igt@i915_selftest@live_gt_pm.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16446/fi-icl-u3/igt@i915_selftest@live_gt_pm.html - fi-glk-dsi: [PASS][17] -> [DMESG-FAIL][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-glk-dsi/igt@i915_selftest@live_gt_pm.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16446/fi-glk-dsi/igt@i915_selftest@live_gt_pm.html - fi-bsw-kefka: [PASS][19] -> [DMESG-FAIL][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-bsw-kefka/igt@i915_selftest@live_gt_pm.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16446/fi-bsw-kefka/igt@i915_selftest@live_gt_pm.html - fi-hsw-4770r: [PASS][21] -> [DMESG-FAIL][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-hsw-4770r/igt@i915_selftest@live_gt_pm.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16446/fi-hsw-4770r/igt@i915_selftest@live_gt_pm.html - fi-icl-guc: [PASS][23] -> [DMESG-FAIL][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-icl-guc/igt@i915_selftest@live_gt_pm.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16446/fi-icl-guc/igt@i915_selftest@live_gt_pm.html - fi-byt-n2820: NOTRUN -> [DMESG-FAIL][25] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16446/fi-byt-n2820/igt@i915_selftest@live_gt_pm.html - fi-bsw-n3050: [PASS][26] -> [DMESG-FAIL][27] [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-bsw-n3050/igt@i915_selftest@live_gt_pm.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16446/fi-bsw-n3050/igt@i915_selftest@live_gt_pm.html - fi-whl-u: [PASS][28] -> [DMESG-FAIL][29] [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-whl-u/igt@i915_selftest@live_gt_pm.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16446/fi-whl-u/igt@i915_selftest@live_gt_pm.html - fi-skl-6770hq:
[Intel-gfx] [PATCH v2 3/3] drm/i915: Fix redefinition of sanitize_watermarks_add_affected
Commit 44a67719497b ("drm/i915: Fix modeset locks in sanitize_watermarks()")
that added this function is correctly, this issue was introduced when
resolving the merge conflict.
Fixes: 9c654e423507 ("Merge remote-tracking branch
'drm-intel/drm-intel-next-queued' into drm-tip")
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_display.c | 24
1 file changed, 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index cde10b536a91..80eebdc4c670 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -17688,30 +17688,6 @@ static int sanitize_watermarks_add_affected(struct
drm_atomic_state *state)
return 0;
}
-static int sanitize_watermarks_add_affected(struct drm_atomic_state *state)
-{
- struct drm_plane *plane;
- struct drm_crtc *crtc;
-
- drm_for_each_crtc(crtc, state->dev) {
- struct drm_crtc_state *crtc_state;
-
- crtc_state = drm_atomic_get_crtc_state(state, crtc);
- if (IS_ERR(crtc_state))
- return PTR_ERR(crtc_state);
- }
-
- drm_for_each_plane(plane, state->dev) {
- struct drm_plane_state *plane_state;
-
- plane_state = drm_atomic_get_plane_state(state, plane);
- if (IS_ERR(plane_state))
- return PTR_ERR(plane_state);
- }
-
- return 0;
-}
-
/*
* Calculate what we think the watermarks should be for the state we've read
* out of the hardware and then immediately program those watermarks so that
--
2.25.0
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[Intel-gfx] [PATCH v2 2/3] drm/i915/display: Do not write in removed FBC fence registers
From: Radhakrishna Sripada
Platforms without fences don't have FBC host tracking and those
registers are marked as reserved in those platforms.
v2: checking num_fences to write to FBC fence registers (Ville)
Cc: Rodrigo Vivi
Cc: Matt Roper
Cc: Dhinakaran Pandiyan
Cc: Ville Syrjälä
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Lucas De Marchi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_fbc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 3a9e41e93ebf..fa8fca1a6b7c 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -320,7 +320,7 @@ static void gen7_fbc_activate(struct drm_i915_private
*dev_priv)
SNB_CPU_FENCE_ENABLE | params->fence_id);
intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET,
params->crtc.fence_y_offset);
- } else {
+ } else if (dev_priv->ggtt.num_fences) {
intel_de_write(dev_priv, SNB_DPFC_CTL_SA, 0);
intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET, 0);
}
--
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[Intel-gfx] [PATCH v2 1/3] drm/i915/display/fbc: Make fences a nice-to-have for GEN11+
dGFX have local memory so it do not have aperture and do not support
CPU fences but even for iGFX it have a small number of fences.
As replacement for fences to track frontbuffer modifications by CPU
we have a software tracking that is already in used by FBC and PSR.
PSR don't support fences so it shows that this tracking is reliable.
So lets make fences a nice-to-have to activate FBC for GEN11+, this
will allow us to enable FBC for dGFXs and iGFXs even when there is no
available fence.
We do not set fences to rotated planes but FBC only have restrictions
against 16bpp, so adding it here.
Also adding a new check for the tiling format, fences are only set
to X and Y tiled planes but again FBC don't have any restrictions
against tiling so adding linear as supported as well, other formats
should be added after tested but IGT only supports drawing in thse
3 formats.
intel_fbc_hw_tracking_covers_screen() maybe can also have the same
treatment as fences but BSpec is not clear if the size limitation is
for hardware tracking or general use of FBC and I don't have a 5K
display to test it, so keeping as is for safety.
v2:
- Added tiling and pixel format rotation checks
- Changed the GEN version not requiring fences to 11 from 9, DDX
needs some changes but it don't have support for GEN11+
Cc: Daniel Vetter
Cc: Dhinakaran Pandiyan
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_fbc.c | 42
drivers/gpu/drm/i915/i915_drv.h | 1 +
2 files changed, 36 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index ddf8d3bb7a7d..3a9e41e93ebf 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -585,7 +585,7 @@ static bool stride_is_valid(struct drm_i915_private
*dev_priv,
}
static bool pixel_format_is_valid(struct drm_i915_private *dev_priv,
- u32 pixel_format)
+ u32 pixel_format, unsigned int rotation)
{
switch (pixel_format) {
case DRM_FORMAT_XRGB:
@@ -599,6 +599,9 @@ static bool pixel_format_is_valid(struct drm_i915_private
*dev_priv,
/* WaFbcOnly1to1Ratio:ctg */
if (IS_G4X(dev_priv))
return false;
+ if ((rotation & (DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270)) &&
+ INTEL_GEN(dev_priv) >= 9)
+ return false;
return true;
default:
return false;
@@ -639,6 +642,18 @@ static bool intel_fbc_hw_tracking_covers_screen(struct
intel_crtc *crtc)
return effective_w <= max_w && effective_h <= max_h;
}
+static bool tiling_is_valid(uint64_t modifier)
+{
+ switch (modifier) {
+ case DRM_FORMAT_MOD_LINEAR:
+ case I915_FORMAT_MOD_X_TILED:
+ case I915_FORMAT_MOD_Y_TILED:
+ return true;
+ default:
+ return false;
+ }
+}
+
static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
const struct intel_crtc_state
*crtc_state,
const struct intel_plane_state
*plane_state)
@@ -672,6 +687,7 @@ static void intel_fbc_update_state_cache(struct intel_crtc
*crtc,
cache->fb.format = fb->format;
cache->fb.stride = fb->pitches[0];
+ cache->fb.modifier = fb->modifier;
drm_WARN_ON(_priv->drm, plane_state->flags & PLANE_HAS_FENCE &&
!plane_state->vma->fence);
@@ -720,23 +736,34 @@ static bool intel_fbc_can_activate(struct intel_crtc
*crtc)
return false;
}
- /* The use of a CPU fence is mandatory in order to detect writes
-* by the CPU to the scanout and trigger updates to the FBC.
+ /* The use of a CPU fence is one of two ways to detect writes by the
+* CPU to the scanout and trigger updates to the FBC.
+*
+* The other method is by software tracking(see
+* intel_fbc_invalidate/flush()), it will manually notify FBC and nuke
+* the current compressed buffer and recompress it.
*
* Note that is possible for a tiled surface to be unmappable (and
-* so have no fence associated with it) due to aperture constaints
+* so have no fence associated with it) due to aperture constraints
* at the time of pinning.
*
* FIXME with 90/270 degree rotation we should use the fence on
* the normal GTT view (the rotated view doesn't even have a
* fence). Would need changes to the FBC fence Y offset as well.
-* For now this will effecively disable FBC with 90/270 degree
+* For now this will effectively disable FBC with 90/270 degree
* rotation.
*/
- if (cache->fence_id < 0) {
+ if (INTEL_GEN(dev_priv) < 11 &&
[Intel-gfx] [PATCH 2/3] drm/i915/gt: Set the PP_DIR registers upon enabling ring submission
Always prime the page table registers before starting the ring. Even
though we will update these to the per-context page tables during
dispatch, it is prudent to ensure that the registers always point to a
valid PD.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
.../gpu/drm/i915/gt/intel_ring_submission.c | 40 ---
1 file changed, 26 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 42168d7cf5b5..f915a63e1110 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -635,6 +635,27 @@ static bool stop_ring(struct intel_engine_cs *engine)
return (ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) == 0;
}
+static struct i915_address_space *vm_alias(struct i915_address_space *vm)
+{
+ if (i915_is_ggtt(vm))
+ vm = _vm_to_ggtt(vm)->alias->vm;
+
+ return vm;
+}
+
+static void set_pp_dir(struct intel_engine_cs *engine)
+{
+ struct i915_address_space *vm = vm_alias(engine->gt->vm);
+
+ if (vm) {
+ struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
+
+ ENGINE_WRITE(engine, RING_PP_DIR_DCLV, PP_DIR_DCLV_2G);
+ ENGINE_WRITE(engine, RING_PP_DIR_BASE,
+px_base(ppgtt->pd)->ggtt_offset << 10);
+ }
+}
+
static int xcs_resume(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
@@ -693,6 +714,8 @@ static int xcs_resume(struct intel_engine_cs *engine)
GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail));
intel_ring_update_space(ring);
+ set_pp_dir(engine);
+
/* First wake the ring up to an empty/idle ring */
ENGINE_WRITE(engine, RING_HEAD, ring->head);
ENGINE_WRITE(engine, RING_TAIL, ring->head);
@@ -1169,23 +1192,12 @@ static void ring_context_destroy(struct kref *ref)
intel_context_free(ce);
}
-static struct i915_address_space *vm_alias(struct intel_context *ce)
-{
- struct i915_address_space *vm;
-
- vm = ce->vm;
- if (i915_is_ggtt(vm))
- vm = _vm_to_ggtt(vm)->alias->vm;
-
- return vm;
-}
-
static int __context_pin_ppgtt(struct intel_context *ce)
{
struct i915_address_space *vm;
int err = 0;
- vm = vm_alias(ce);
+ vm = vm_alias(ce->vm);
if (vm)
err = gen6_ppgtt_pin(i915_vm_to_ppgtt((vm)));
@@ -1196,7 +1208,7 @@ static void __context_unpin_ppgtt(struct intel_context
*ce)
{
struct i915_address_space *vm;
- vm = vm_alias(ce);
+ vm = vm_alias(ce->vm);
if (vm)
gen6_ppgtt_unpin(i915_vm_to_ppgtt(vm));
}
@@ -1553,7 +1565,7 @@ static int switch_context(struct i915_request *rq)
GEM_BUG_ON(HAS_EXECLISTS(rq->i915));
- ret = switch_mm(rq, vm_alias(ce));
+ ret = switch_mm(rq, vm_alias(ce->vm));
if (ret)
return ret;
--
2.25.0
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[Intel-gfx] [PATCH 3/3] drm/i915/gt: Stop invalidating the PD cachelines for gen7
Trust that the HW does the right thing after simply updating the PD_DIR_BASE? Signed-off-by: Chris Wilson Cc: Mika Kuoppala --- drivers/gpu/drm/i915/gt/intel_ring_submission.c | 10 +- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c index f915a63e1110..23f4fc2669d1 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c @@ -1341,14 +1341,10 @@ static int load_pd_dir(struct i915_request *rq, const struct intel_engine_cs * const engine = rq->engine; u32 *cs; - cs = intel_ring_begin(rq, 12); + cs = intel_ring_begin(rq, 6); if (IS_ERR(cs)) return PTR_ERR(cs); - *cs++ = MI_LOAD_REGISTER_IMM(1); - *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base)); - *cs++ = valid; - *cs++ = MI_LOAD_REGISTER_IMM(1); *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); *cs++ = px_base(ppgtt->pd)->ggtt_offset << 10; @@ -1359,10 +1355,6 @@ static int load_pd_dir(struct i915_request *rq, *cs++ = intel_gt_scratch_offset(engine->gt, INTEL_GT_SCRATCH_FIELD_DEFAULT); - *cs++ = MI_LOAD_REGISTER_IMM(1); - *cs++ = i915_mmio_reg_offset(RING_INSTPM(engine->mmio_base)); - *cs++ = _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE); - intel_ring_advance(rq, cs); return rq->engine->emit_flush(rq, EMIT_FLUSH); -- 2.25.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/3] drm/i915/gt: Tweak gen7 xcs flushing
Don't immediately write the seqno into the breadcrumb slot, but wait
until we've attempted to flush the writes; that is we need to ensure the
memory is coherent prior to updating the breadcrumb so that any
observers who see the new seqno can proceed.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gt/intel_ring_submission.c | 24 ---
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 9537d4912225..42168d7cf5b5 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -446,31 +446,39 @@ static u32 *gen6_xcs_emit_breadcrumb(struct i915_request
*rq, u32 *cs)
return cs;
}
-#define GEN7_XCS_WA 32
-static u32 *gen7_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
+#define GEN7_XCS_WA 8
+static u32 *
+__gen7_xcs_emit_breadcrumb(struct i915_request *rq, u32 addr, u32 *cs)
{
int i;
- GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt !=
rq->engine->status_page.vma);
-
GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) !=
I915_GEM_HWS_SEQNO_ADDR);
-
*cs++ = MI_FLUSH_DW | MI_INVALIDATE_TLB |
MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX;
- *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT;
+ *cs++ = addr | MI_FLUSH_DW_USE_GTT;
*cs++ = rq->fence.seqno;
for (i = 0; i < GEN7_XCS_WA; i++) {
*cs++ = MI_STORE_DWORD_INDEX;
- *cs++ = I915_GEM_HWS_SEQNO_ADDR;
+ *cs++ = addr;
*cs++ = rq->fence.seqno;
}
+ return cs;
+}
+
+static u32 *gen7_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
+{
+ GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt !=
rq->engine->status_page.vma);
+
GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) !=
I915_GEM_HWS_SEQNO_ADDR);
+
+ cs = __gen7_xcs_emit_breadcrumb(rq, I915_GEM_HWS_SEQNO_ADDR + 4, cs);
+ cs = __gen7_xcs_emit_breadcrumb(rq, I915_GEM_HWS_SEQNO_ADDR, cs);
+
*cs++ = MI_FLUSH_DW;
*cs++ = 0;
*cs++ = 0;
*cs++ = MI_USER_INTERRUPT;
- *cs++ = MI_NOOP;
rq->tail = intel_ring_offset(rq, cs);
assert_ring_tail_valid(rq->ring, rq->tail);
--
2.25.0
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [v3] drm/i915/display: Force the state compute phase once to enable PSR
Hi Ross I'm unable to reproduce this issue, could you share the complete dmesg? On Wed, 2020-02-05 at 16:01 -0700, Ross Zwisler wrote: > On Mon, Jan 06, 2020 at 07:21:28AM -0800, José Roberto de Souza > wrote: > > Recent improvements in the state tracking in i915 caused PSR to not > > be > > enabled when reusing firmware/BIOS modeset, this is due to all > > initial > > commits returning ealier in intel_atomic_check() as needs_modeset() > > is always false. > > > > To fix that here forcing the state compute phase in CRTC that is > > driving the eDP that supports PSR once. Enable or disable PSR do > > not > > require a fullmodeset, so user will still experience glitch free > > boot > > process plus the power savings that PSR brings. > > > > It was tried to set mode_changed in intel_initial_commit() but at > > this point the connectors are not registered causing a crash when > > computing encoder state. > > > > v2: > > - removed function return > > - change arguments to match intel_hdcp_atomic_check > > > > v3: > > - replaced drm includes in intel_psr.h by forward declaration(Jani) > > > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112253 > > Reported-by: > > Cc: Gwan-gyeong Mun > > Cc: Jani Nikula > > Signed-off-by: José Roberto de Souza > > Reviewed-by: Gwan-gyeong Mun > > --- > > With the current linux/master: > > 6992ca0dd017e Merge branch 'parisc-5.6-1' of > git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux > > my system fails to boot, and I bisected the failure to this > commit. Here are > the relevant messages from dmesg, passed through kasan_symbolize.py: > > i915 :00:02.0: vgaarb: deactivate vga console > [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). > [drm] Driver supports precise vblank timestamp query. > resource sanity check: requesting [mem 0x000c-0x000d], which > spans more than PCI Bus :00 [mem 0x000c-0x000c3fff > window] > caller pci_map_rom+0x6a/0x17d mapping multiple BARs > i915 :00:02.0: Invalid PCI ROM data signature: expecting > 0x52494350, got 0xe937aa55 > [drm] Failed to find VBIOS tables (VBT) > i915 :00:02.0: vgaarb: changed VGA decodes: > olddecodes=io+mem,decodes=io+mem:owns=io+mem > [ cut here ] > WARNING: CPU: 0 PID: 1 at > drivers/gpu/drm/drm_atomic.c:296[] > drm_atomic_get_crtc_state+0xf8/0x110 drivers/gpu/drm/drm_atomic.c:304 > Modules linked in: > CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.5.0-rc1-00573- > g60c6a14b489ba #31 > Hardware name: GOOGLE Samus, BIOS 05/14/2019 > RIP: 0010:drm_atomic_get_crtc_state+0xf8/0x110 > Code: 89 2c 11 48 89 98 f0 01 00 00 48 8b 4d 20 8b 55 60 e8 5c aa 00 > 00 48 8b 04 24 48 83 c4 08 5b 5d 41 5c c3 48 98 e9 4e ff ff > ff <0f> 0b e9 28 ff ff ff 48 c7 c0 f4 ff ff ff e9 3b ff ff ff 0f 1f > 44 > RSP: :ab4b80017970 EFLAGS: 00010246 > RAX: RBX: 93c1a69ca000 RCX: 93c1ab69b8c0 > RDX: 002d RSI: RDI: 93c1a69ca000 > RBP: 93c1a6944000 R08: 0079 R09: 0079 > R10: 002d R11: 0005 R12: > R13: 93c1a6944000 R14: 0005 R15: 93c1a6979c00 > FS: () GS:93c1aec0() > knlGS: > CS: 0010 DS: ES: CR0: 80050033 > CR2: 93c0f5201000 CR3: 0003b3e0c001 CR4: 003606f0 > Call Trace: > [ ] > drm_atomic_add_affected_connectors+0x2e/0x110 > drivers/gpu/drm/drm_atomic.c:1046 > [ ] drm_atomic_helper_check_modeset+0x4a1/0xa70 > drivers/gpu/drm/drm_atomic_helper.c:703 > [ ] intel_atomic_check+0x96/0x2510 > drivers/gpu/drm/i915/display/intel_display.c:14603 > ?[< inline >] kmemdup ./include/linux/string.h:453 > ?[ ] > intel_digital_connector_duplicate_state+0x21/0x40 > drivers/gpu/drm/i915/display/intel_atomic.c:171 > ?[< inline >] spin_unlock_irqrestore > ./include/linux/spinlock.h:393 > ?[ ] drm_connector_list_iter_next+0x88/0xb0 > drivers/gpu/drm/drm_connector.c:689 > [< inline >] sanitize_watermarks > drivers/gpu/drm/i915/display/intel_display.c:17359 > [ ] intel_modeset_init+0x10a8/0x1d50 > drivers/gpu/drm/i915/display/intel_display.c:17602 > [< inline >] i915_driver_modeset_probe > drivers/gpu/drm/i915/i915_drv.c:311 > [ ] i915_driver_probe+0xa4e/0x1410 > drivers/gpu/drm/i915/i915_drv.c:1528 > ?[ ] __kernfs_new_node+0x159/0x1c0 > fs/kernfs/dir.c:666 > [ ] i915_pci_probe+0x54/0x138 > drivers/gpu/drm/i915/i915_pci.c:994 > [ ] local_pci_probe+0x42/0x80 drivers/pci/pci- > driver.c:306 > [< inline >] pci_call_probe drivers/pci/pci-driver.c:361 > [< inline >] __pci_device_probe drivers/pci/pci-driver.c:386 > [ ] pci_device_probe+0x107/0x1a0
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/gt: Set the PP_DIR registers upon enabling ring submission
== Series Details == Series: series starting with [1/2] drm/i915/gt: Set the PP_DIR registers upon enabling ring submission URL : https://patchwork.freedesktop.org/series/73059/ State : success == Summary == CI Bug Log - changes from CI_DRM_7871 -> Patchwork_16445 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16445/index.html Known issues Here are the changes found in Patchwork_16445 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_parallel@fds: - fi-hsw-4770r: [PASS][1] -> [INCOMPLETE][2] ([i915#694]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-hsw-4770r/igt@gem_exec_paral...@fds.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16445/fi-hsw-4770r/igt@gem_exec_paral...@fds.html * igt@gem_mmap_gtt@basic: - fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([CI#94] / [i915#402]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-tgl-y/igt@gem_mmap_...@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16445/fi-tgl-y/igt@gem_mmap_...@basic.html * igt@i915_selftest@live_blt: - fi-ivb-3770:[PASS][5] -> [DMESG-FAIL][6] ([i915#725]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-ivb-3770/igt@i915_selftest@live_blt.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16445/fi-ivb-3770/igt@i915_selftest@live_blt.html Possible fixes * igt@i915_selftest@live_gtt: - fi-icl-guc: [TIMEOUT][7] ([fdo#112271]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-icl-guc/igt@i915_selftest@live_gtt.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16445/fi-icl-guc/igt@i915_selftest@live_gtt.html * igt@kms_addfb_basic@bad-pitch-128: - fi-tgl-y: [DMESG-WARN][9] ([CI#94] / [i915#402]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-tgl-y/igt@kms_addfb_ba...@bad-pitch-128.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16445/fi-tgl-y/igt@kms_addfb_ba...@bad-pitch-128.html [CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94 [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 Participating hosts (45 -> 43) -- Additional (6): fi-bdw-5557u fi-hsw-peppy fi-bwr-2160 fi-ilk-650 fi-kbl-7500u fi-gdg-551 Missing(8): fi-kbl-soraka fi-skl-6770hq fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-bsw-kefka fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7871 -> Patchwork_16445 CI-20190529: 20190529 CI_DRM_7871: c9b0237ee7ffb1bbb62f864f0b2d7b290ee1313d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5419: 44913a91e77434b03001bb9ea53216cd03c476e6 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16445: df55045a913e542322e952f262b34bc9437d6f48 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == df55045a913e drm/i915/gt: Stop invalidating the PD cachelines for gen7 ceceb2b0658f drm/i915/gt: Set the PP_DIR registers upon enabling ring submission == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16445/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Expose exec parameter to force non IA-Coherent for Gen9+
== Series Details == Series: drm/i915: Expose exec parameter to force non IA-Coherent for Gen9+ URL : https://patchwork.freedesktop.org/series/2428/ State : failure == Summary == CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp_cm.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_mpc.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_opp.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubbub.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_optc.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_mmhubbub.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_stream_encoder.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_link_encoder.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dccg.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_vmid.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dwb.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dwb_scl.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dsc.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dsc/dc_dsc.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dsc/rc_calc.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dsc/rc_calc_dpi.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_init.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_resource.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_ipp.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer_debug.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_dpp.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_opp.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_optc.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hubp.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_mpc.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_dpp_dscl.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_dpp_cm.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_cm_common.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hubbub.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_stream_encoder.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_link_encoder.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_rq_dlg_helpers.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dml1_display_rq_dlg_calc.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dml_common_defs.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_vba.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_mode_vba_20.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20v2.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_mode_vba_20v2.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn21/display_rq_dlg_calc_21.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn21/display_mode_vba_21.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_init.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_hubp.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_hubbub.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_hwseq.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_link_encoder.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce120/dce120_resource.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce120/dce120_timing_generator.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce120/dce120_hw_sequencer.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce112/dce112_compressor.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce112/dce112_hw_sequencer.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce112/dce112_resource.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_timing_generator.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_compressor.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_hw_sequencer.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_resource.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_opp_regamma_v.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_opp_csc_v.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_timing_generator_v.o CC [M]
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dc3co: Add description of how it works
== Series Details == Series: drm/i915/dc3co: Add description of how it works URL : https://patchwork.freedesktop.org/series/73058/ State : success == Summary == CI Bug Log - changes from CI_DRM_7871 -> Patchwork_16444 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16444/index.html Known issues Here are the changes found in Patchwork_16444 that come from known issues: ### IGT changes ### Issues hit * igt@i915_getparams_basic@basic-eu-total: - fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([CI#94] / [i915#402]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-tgl-y/igt@i915_getparams_ba...@basic-eu-total.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16444/fi-tgl-y/igt@i915_getparams_ba...@basic-eu-total.html * igt@i915_module_load@reload: - fi-skl-6770hq: [PASS][3] -> [DMESG-WARN][4] ([i915#92]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-skl-6770hq/igt@i915_module_l...@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16444/fi-skl-6770hq/igt@i915_module_l...@reload.html * igt@i915_selftest@live_blt: - fi-hsw-4770r: [PASS][5] -> [DMESG-FAIL][6] ([i915#725]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-hsw-4770r/igt@i915_selftest@live_blt.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16444/fi-hsw-4770r/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_execlists: - fi-icl-y: [PASS][7] -> [DMESG-FAIL][8] ([fdo#108569]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-icl-y/igt@i915_selftest@live_execlists.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16444/fi-icl-y/igt@i915_selftest@live_execlists.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-icl-u2: [PASS][9] -> [FAIL][10] ([i915#217]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16444/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-skl-6770hq: [PASS][11] -> [SKIP][12] ([fdo#109271]) +4 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-skl-6770hq/igt@kms_pipe_crc_ba...@read-crc-pipe-a-frame-sequence.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16444/fi-skl-6770hq/igt@kms_pipe_crc_ba...@read-crc-pipe-a-frame-sequence.html * igt@kms_pipe_crc_basic@read-crc-pipe-c: - fi-skl-6770hq: [PASS][13] -> [DMESG-WARN][14] ([i915#106] / [i915#188]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-skl-6770hq/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16444/fi-skl-6770hq/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html Possible fixes * igt@i915_selftest@live_gtt: - fi-icl-guc: [TIMEOUT][15] ([fdo#112271]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-icl-guc/igt@i915_selftest@live_gtt.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16444/fi-icl-guc/igt@i915_selftest@live_gtt.html * igt@kms_addfb_basic@bad-pitch-128: - fi-tgl-y: [DMESG-WARN][17] ([CI#94] / [i915#402]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-tgl-y/igt@kms_addfb_ba...@bad-pitch-128.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16444/fi-tgl-y/igt@kms_addfb_ba...@bad-pitch-128.html [CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271 [i915#106]: https://gitlab.freedesktop.org/drm/intel/issues/106 [i915#188]: https://gitlab.freedesktop.org/drm/intel/issues/188 [i915#217]: https://gitlab.freedesktop.org/drm/intel/issues/217 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 Participating hosts (45 -> 39) -- Additional (5): fi-bdw-5557u fi-ilk-650 fi-kbl-7500u fi-gdg-551 fi-kbl-7560u Missing(11): fi-kbl-soraka fi-bdw-samus fi-bsw-n3050 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-ivb-3770 fi-blb-e6850 fi-byt-clapper fi-skl-6600u fi-snb-2600 Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7871 -> Patchwork_16444 CI-20190529: 20190529 CI_DRM_7871: c9b0237ee7ffb1bbb62f864f0b2d7b290ee1313d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5419: 44913a91e77434b03001bb9ea53216cd03c476e6 @
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm: Add a detailed DP HDMI branch info on debugfs
== Series Details == Series: series starting with [1/2] drm: Add a detailed DP HDMI branch info on debugfs URL : https://patchwork.freedesktop.org/series/72914/ State : success == Summary == CI Bug Log - changes from CI_DRM_7859_full -> Patchwork_16392_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_16392_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@rcs0-s3: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7859/shard-apl2/igt@gem_ctx_isolat...@rcs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16392/shard-apl7/igt@gem_ctx_isolat...@rcs0-s3.html * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110841]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7859/shard-iclb5/igt@gem_ctx_sha...@exec-single-timeline-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16392/shard-iclb1/igt@gem_ctx_sha...@exec-single-timeline-bsd.html * igt@gem_exec_flush@basic-batch-kernel-default-cmd: - shard-hsw: [PASS][5] -> [FAIL][6] ([i915#694]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7859/shard-hsw6/igt@gem_exec_fl...@basic-batch-kernel-default-cmd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16392/shard-hsw8/igt@gem_exec_fl...@basic-batch-kernel-default-cmd.html * igt@gem_exec_schedule@in-order-bsd: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#112146]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7859/shard-iclb8/igt@gem_exec_sched...@in-order-bsd.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16392/shard-iclb2/igt@gem_exec_sched...@in-order-bsd.html * igt@gem_exec_schedule@promotion-bsd1: - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109276]) +13 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7859/shard-iclb1/igt@gem_exec_sched...@promotion-bsd1.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16392/shard-iclb8/igt@gem_exec_sched...@promotion-bsd1.html * igt@gem_exec_suspend@basic-s3: - shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([i915#180]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7859/shard-kbl7/igt@gem_exec_susp...@basic-s3.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16392/shard-kbl1/igt@gem_exec_susp...@basic-s3.html * igt@gem_ppgtt@flink-and-close-vma-leak: - shard-glk: [PASS][13] -> [FAIL][14] ([i915#644]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7859/shard-glk8/igt@gem_pp...@flink-and-close-vma-leak.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16392/shard-glk8/igt@gem_pp...@flink-and-close-vma-leak.html * igt@i915_suspend@forcewake: - shard-skl: [PASS][15] -> [INCOMPLETE][16] ([i915#69]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7859/shard-skl6/igt@i915_susp...@forcewake.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16392/shard-skl4/igt@i915_susp...@forcewake.html * igt@kms_big_fb@x-tiled-64bpp-rotate-0: - shard-iclb: [PASS][17] -> [SKIP][18] ([i915#1140]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7859/shard-iclb2/igt@kms_big...@x-tiled-64bpp-rotate-0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16392/shard-iclb5/igt@kms_big...@x-tiled-64bpp-rotate-0.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#79]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7859/shard-skl7/igt@kms_f...@flip-vs-expired-vblank.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16392/shard-skl3/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-apl: [PASS][21] -> [FAIL][22] ([i915#79]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7859/shard-apl7/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16392/shard-apl2/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_psr@psr2_cursor_plane_move: - shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7859/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16392/shard-iclb5/igt@kms_psr@psr2_cursor_plane_move.html * igt@kms_setmode@basic: - shard-glk: [PASS][25] -> [FAIL][26] ([i915#31]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7859/shard-glk4/igt@kms_setm...@basic.html [26]:
[Intel-gfx] [PATCH] drm/i915/gt: Tweak gen7 xcs flushing
Don't immediately write the seqno into the breadcrumb slot, but wait
until we've attempted to flush the writes; that is we need to ensure the
memory is coherent prior to updating the breadcrumb so that any
observers who see the new seqno can proceed.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_ring_submission.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index b5a4b3d4ba6a..4a4792149ad6 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -446,7 +446,7 @@ static u32 *gen6_xcs_emit_breadcrumb(struct i915_request
*rq, u32 *cs)
return cs;
}
-#define GEN7_XCS_WA 32
+#define GEN7_XCS_WA 8
static u32 *gen7_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
{
int i;
@@ -454,6 +454,11 @@ static u32 *gen7_xcs_emit_breadcrumb(struct i915_request
*rq, u32 *cs)
GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt !=
rq->engine->status_page.vma);
GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) !=
I915_GEM_HWS_SEQNO_ADDR);
+ *cs++ = MI_FLUSH_DW | MI_INVALIDATE_TLB |
+ MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX;
+ *cs++ = (I915_GEM_HWS_SEQNO_ADDR + 4) | MI_FLUSH_DW_USE_GTT;
+ *cs++ = rq->fence.seqno;
+
*cs++ = MI_FLUSH_DW | MI_INVALIDATE_TLB |
MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX;
*cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT;
@@ -461,7 +466,7 @@ static u32 *gen7_xcs_emit_breadcrumb(struct i915_request
*rq, u32 *cs)
for (i = 0; i < GEN7_XCS_WA; i++) {
*cs++ = MI_STORE_DWORD_INDEX;
- *cs++ = I915_GEM_HWS_SEQNO_ADDR;
+ *cs++ = I915_GEM_HWS_SEQNO_ADDR + 4;
*cs++ = rq->fence.seqno;
}
@@ -470,7 +475,6 @@ static u32 *gen7_xcs_emit_breadcrumb(struct i915_request
*rq, u32 *cs)
*cs++ = 0;
*cs++ = MI_USER_INTERRUPT;
- *cs++ = MI_NOOP;
rq->tail = intel_ring_offset(rq, cs);
assert_ring_tail_valid(rq->ring, rq->tail);
--
2.25.0
___
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[Intel-gfx] [PATCH] drm/i915/selftests: Trim blitter block size
Reduce the amount of work we do to verify client blt correctness as
currently our 0.5s subtests takes about 15s on slower devices!
Signed-off-by: Chris Wilson
---
.../i915/gem/selftests/i915_gem_object_blt.c | 24 ---
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
index 62077fe46715..cebbe3c3ca86 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
@@ -226,7 +226,7 @@ static int igt_fill_blt_thread(void *arg)
GEM_BUG_ON(IS_ERR(ce));
do {
- const u32 max_block_size = S16_MAX * PAGE_SIZE;
+ const u32 max_block_size = SZ_64M; /* max S16_MAX * PAGE_SIZE */
u32 val = prandom_u32_state(prng);
u64 total = ce->vm->total;
u32 phys_sz;
@@ -276,13 +276,16 @@ static int igt_fill_blt_thread(void *arg)
if (err)
goto err_unpin;
- i915_gem_object_lock(obj);
- err = i915_gem_object_set_to_cpu_domain(obj, false);
- i915_gem_object_unlock(obj);
+ err = i915_gem_object_wait(obj, I915_WAIT_ALL, HZ / 2);
if (err)
goto err_unpin;
- for (i = 0; i < huge_gem_object_phys_size(obj) / sizeof(u32);
++i) {
+ for (i = 0; i < huge_gem_object_phys_size(obj) / sizeof(u32); i
+= 17) {
+ if (!(obj->cache_coherent &
I915_BO_CACHE_COHERENT_FOR_READ)) {
+ clflush([i]);
+ mb();
+ }
+
if (vaddr[i] != val) {
pr_err("vaddr[%u]=%x, expected=%x\n", i,
vaddr[i], val);
@@ -335,7 +338,7 @@ static int igt_copy_blt_thread(void *arg)
GEM_BUG_ON(IS_ERR(ce));
do {
- const u32 max_block_size = S16_MAX * PAGE_SIZE;
+ const u32 max_block_size = SZ_64M; /* max S16_MAX * PAGE_SIZE */
u32 val = prandom_u32_state(prng);
u64 total = ce->vm->total;
u32 phys_sz;
@@ -397,13 +400,16 @@ static int igt_copy_blt_thread(void *arg)
if (err)
goto err_unpin;
- i915_gem_object_lock(dst);
- err = i915_gem_object_set_to_cpu_domain(dst, false);
- i915_gem_object_unlock(dst);
+ err = i915_gem_object_wait(dst, I915_WAIT_ALL, HZ / 2);
if (err)
goto err_unpin;
for (i = 0; i < huge_gem_object_phys_size(dst) / sizeof(u32);
++i) {
+ if (!(dst->cache_coherent &
I915_BO_CACHE_COHERENT_FOR_READ)) {
+ clflush([i]);
+ mb();
+ }
+
if (vaddr[i] != val) {
pr_err("vaddr[%u]=%x, expected=%x\n", i,
vaddr[i], val);
--
2.25.0
___
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[Intel-gfx] [PATCH] drm/i915: Fix redefinition of sanitize_watermarks_add_affected
Commit 44a67719497b ("drm/i915: Fix modeset locks in sanitize_watermarks()")
that added this function is correctly, this issue was introduced when
resolving the merge conflict.
Fixes: 9c654e423507 ("Merge remote-tracking branch
'drm-intel/drm-intel-next-queued' into drm-tip")
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_display.c | 24
1 file changed, 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index cde10b536a91..80eebdc4c670 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -17688,30 +17688,6 @@ static int sanitize_watermarks_add_affected(struct
drm_atomic_state *state)
return 0;
}
-static int sanitize_watermarks_add_affected(struct drm_atomic_state *state)
-{
- struct drm_plane *plane;
- struct drm_crtc *crtc;
-
- drm_for_each_crtc(crtc, state->dev) {
- struct drm_crtc_state *crtc_state;
-
- crtc_state = drm_atomic_get_crtc_state(state, crtc);
- if (IS_ERR(crtc_state))
- return PTR_ERR(crtc_state);
- }
-
- drm_for_each_plane(plane, state->dev) {
- struct drm_plane_state *plane_state;
-
- plane_state = drm_atomic_get_plane_state(state, plane);
- if (IS_ERR(plane_state))
- return PTR_ERR(plane_state);
- }
-
- return 0;
-}
-
/*
* Calculate what we think the watermarks should be for the state we've read
* out of the hardware and then immediately program those watermarks so that
--
2.25.0
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display/ehl: Add HBR2 and HBR3 voltage swing table
== Series Details == Series: drm/i915/display/ehl: Add HBR2 and HBR3 voltage swing table URL : https://patchwork.freedesktop.org/series/73055/ State : success == Summary == CI Bug Log - changes from CI_DRM_7871 -> Patchwork_16443 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16443/index.html Known issues Here are the changes found in Patchwork_16443 that come from known issues: ### IGT changes ### Issues hit * igt@i915_module_load@reload: - fi-skl-6770hq: [PASS][1] -> [DMESG-WARN][2] ([i915#92]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-skl-6770hq/igt@i915_module_l...@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16443/fi-skl-6770hq/igt@i915_module_l...@reload.html * igt@i915_selftest@live_blt: - fi-hsw-4770r: [PASS][3] -> [DMESG-FAIL][4] ([i915#725]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-hsw-4770r/igt@i915_selftest@live_blt.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16443/fi-hsw-4770r/igt@i915_selftest@live_blt.html - fi-ivb-3770:[PASS][5] -> [DMESG-FAIL][6] ([i915#725]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-ivb-3770/igt@i915_selftest@live_blt.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16443/fi-ivb-3770/igt@i915_selftest@live_blt.html - fi-hsw-4770:[PASS][7] -> [DMESG-FAIL][8] ([i915#725]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-hsw-4770/igt@i915_selftest@live_blt.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16443/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-skl-6770hq: [PASS][9] -> [SKIP][10] ([fdo#109271]) +4 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-skl-6770hq/igt@kms_pipe_crc_ba...@read-crc-pipe-a-frame-sequence.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16443/fi-skl-6770hq/igt@kms_pipe_crc_ba...@read-crc-pipe-a-frame-sequence.html * igt@kms_pipe_crc_basic@read-crc-pipe-c: - fi-skl-6770hq: [PASS][11] -> [DMESG-WARN][12] ([i915#106] / [i915#188]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-skl-6770hq/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16443/fi-skl-6770hq/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html * igt@prime_self_import@basic-llseek-size: - fi-tgl-y: [PASS][13] -> [DMESG-WARN][14] ([CI#94] / [i915#402]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-tgl-y/igt@prime_self_imp...@basic-llseek-size.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16443/fi-tgl-y/igt@prime_self_imp...@basic-llseek-size.html Possible fixes * igt@gem_close_race@basic-threads: - fi-byt-n2820: [INCOMPLETE][15] ([i915#45]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-byt-n2820/igt@gem_close_r...@basic-threads.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16443/fi-byt-n2820/igt@gem_close_r...@basic-threads.html * igt@gem_exec_suspend@basic-s4-devices: - fi-tgl-y: [FAIL][17] ([CI#94]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-tgl-y/igt@gem_exec_susp...@basic-s4-devices.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16443/fi-tgl-y/igt@gem_exec_susp...@basic-s4-devices.html * igt@i915_selftest@live_gtt: - fi-icl-guc: [TIMEOUT][19] ([fdo#112271]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-icl-guc/igt@i915_selftest@live_gtt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16443/fi-icl-guc/igt@i915_selftest@live_gtt.html * igt@kms_addfb_basic@bad-pitch-128: - fi-tgl-y: [DMESG-WARN][21] ([CI#94] / [i915#402]) -> [PASS][22] +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-tgl-y/igt@kms_addfb_ba...@bad-pitch-128.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16443/fi-tgl-y/igt@kms_addfb_ba...@bad-pitch-128.html Warnings * igt@runner@aborted: - fi-byt-n2820: [FAIL][23] ([i915#816]) -> [FAIL][24] ([i915#999]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-byt-n2820/igt@run...@aborted.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16443/fi-byt-n2820/igt@run...@aborted.html [CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271 [i915#106]: https://gitlab.freedesktop.org/drm/intel/issues/106 [i915#188]:
Re: [Intel-gfx] [PATCH v5 i-g-t 2/2] tests/kms_getfb: Add getfb2 tests
On Wed, 2020-01-22 at 15:16 -0800, Juston Li wrote:
> From: Daniel Stone
>
> Mirroring addfb2, add tests for the new ioctl which will return us
> information about framebuffers containing multiple buffers, as well
> as
> modifiers.
>
> Changes since v4:
> - Remove unnecessary bo creation for getfb2-handle-closed subtest
>
> Changes since v3:
> - Add subtests to ensure handles aren't returned for non-root and
> non-master callers
>
> Changes since v1:
> - Add test that uses getfb2 output to call addfb2 as suggested by
> Ville
>
> Signed-off-by: Daniel Stone
> Signed-off-by: Juston Li
> Reviewed-by: Ville Syrjälä
> ---
> tests/kms_getfb.c | 156
> ++
> 1 file changed, 156 insertions(+)
>
> diff --git a/tests/kms_getfb.c b/tests/kms_getfb.c
> index 292679ad3eb9..e046a43a1555 100644
> --- a/tests/kms_getfb.c
> +++ b/tests/kms_getfb.c
> @@ -40,6 +40,8 @@
> #include "drm.h"
> #include "drm_fourcc.h"
>
> +#include "igt_device.h"
> +
> static bool has_getfb_iface(int fd)
> {
> struct drm_mode_fb_cmd arg = { };
> @@ -252,6 +254,154 @@ static void test_duplicate_handles(int fd)
> }
> }
>
> +static void test_getfb2(int fd)
> +{
> + struct drm_mode_fb_cmd2 add_basic = {};
> +
> + igt_fixture {
> + struct drm_mode_fb_cmd2 get = {};
> +
> + add_basic.width = 1024;
> + add_basic.height = 1024;
> + add_basic.pixel_format = DRM_FORMAT_XRGB;
> + add_basic.pitches[0] = 1024*4;
> + add_basic.handles[0] =
> igt_create_bo_with_dimensions(fd, 1024, 1024,
> + DRM_FORMAT_XRGB, 0, 0, NULL, NULL, NULL);
> + igt_assert(add_basic.handles[0]);
> + do_ioctl(fd, DRM_IOCTL_MODE_ADDFB2, _basic);
> +
> + get.fb_id = add_basic.fb_id;
> + do_ioctl(fd, DRM_IOCTL_MODE_GETFB2, );
> + igt_assert_neq_u32(get.handles[0], 0);
> + gem_close(fd, get.handles[0]);
> + }
> +
> + igt_subtest("getfb2-handle-zero") {
> + struct drm_mode_fb_cmd2 get = {};
> + do_ioctl_err(fd, DRM_IOCTL_MODE_GETFB2, , ENOENT);
> + }
> +
> + igt_subtest("getfb2-handle-closed") {
> + struct drm_mode_fb_cmd2 add = add_basic;
> + struct drm_mode_fb_cmd2 get = { };
> +
> + do_ioctl(fd, DRM_IOCTL_MODE_ADDFB2, );
> + do_ioctl(fd, DRM_IOCTL_MODE_RMFB, _id);
> +
> + get.fb_id = add.fb_id;
> + do_ioctl_err(fd, DRM_IOCTL_MODE_GETFB2, , ENOENT);
> + }
> +
> + igt_subtest("getfb2-handle-not-fb") {
> + struct drm_mode_fb_cmd2 get = { .fb_id =
> get_any_prop_id(fd) };
> + igt_require(get.fb_id > 0);
> + do_ioctl_err(fd, DRM_IOCTL_MODE_GETFB2, , ENOENT);
> + }
> +
> + igt_subtest("getfb2-accept-ccs") {
> + struct drm_mode_fb_cmd2 add_ccs = { };
> + struct drm_mode_fb_cmd2 get = { };
> + int i;
> +
> + get_ccs_fb(fd, _ccs);
> + igt_require(add_ccs.fb_id != 0);
> + get.fb_id = add_ccs.fb_id;
> + do_ioctl(fd, DRM_IOCTL_MODE_GETFB2, );
> +
> + igt_assert_eq_u32(get.width, add_ccs.width);
> + igt_assert_eq_u32(get.height, add_ccs.height);
> + igt_assert(get.flags & DRM_MODE_FB_MODIFIERS);
> +
> + for (i = 0; i < ARRAY_SIZE(get.handles); i++) {
> + igt_assert_eq_u32(get.pitches[i],
> add_ccs.pitches[i]);
> + igt_assert_eq_u32(get.offsets[i],
> add_ccs.offsets[i]);
> + if (add_ccs.handles[i] != 0) {
> + igt_assert_neq_u32(get.handles[i], 0);
> + igt_assert_neq_u32(get.handles[i],
> +add_ccs.handles[i]);
> + igt_assert_eq_u64(get.modifier[i],
> + add_ccs.modifier[i]);
> + } else {
> + igt_assert_eq_u32(get.handles[i], 0);
> + igt_assert_eq_u64(get.modifier[i], 0);
> + }
> + }
> + igt_assert_eq_u32(get.handles[0], get.handles[1]);
> +
> + do_ioctl(fd, DRM_IOCTL_MODE_RMFB, _id);
> + gem_close(fd, add_ccs.handles[0]);
> + gem_close(fd, get.handles[0]);
> + }
> +
> + igt_subtest("getfb2-into-addfb2") {
> + struct drm_mode_fb_cmd2 cmd = { };
> +
> + cmd.fb_id = add_basic.fb_id;
> + do_ioctl(fd, DRM_IOCTL_MODE_GETFB2, );
> + do_ioctl(fd, DRM_IOCTL_MODE_ADDFB2, );
> +
> + do_ioctl(fd, DRM_IOCTL_MODE_RMFB, _id);
> + gem_close(fd, cmd.handles[0]);
> + }
> +
> + igt_fixture {
> + do_ioctl(fd, DRM_IOCTL_MODE_RMFB, _basic.fb_id);
> + gem_close(fd, add_basic.handles[0]);
Re: [Intel-gfx] [PATCH v5] drm/i915/selftests: add basic selftests for rc6
Quoting Andi Shyti (2020-02-05 22:49:49)
> +int live_rc6_busy(void *arg)
> +{
> + struct intel_gt *gt = arg;
> + struct intel_rc6 *rc6 = >rc6;
> + struct intel_engine_cs *engine;
> + struct igt_spinner spin;
> + intel_wakeref_t wakeref;
> + enum intel_engine_id id;
> + int err;
> +
> + if (!rc6->supported)
> + return 0;
> +
> + err = igt_spinner_init(, gt);
> + if (err)
> + return err;
> +
> + wakeref = intel_runtime_pm_get(gt->uncore->rpm);
> + for_each_engine(engine, gt, id) {
> + struct i915_request *rq;
> +
> + rq = igt_spinner_create_request(,
> + engine->kernel_context,
> + MI_NOOP);
> + if (IS_ERR(rq)) {
> + err = PTR_ERR(rq);
> + break;
> + }
> +
> + i915_request_get(rq);
> + i915_request_add(rq);
> +
> + igt_wait_for_spinner(, rq); /* it's enough waiting */
> +
> + /* gpu is busy, we shouldn't be in rc6 */
> + if (is_rc6_active(rc6)) {
> + pr_err("%s: never busy enough for having a nap\n",
> + engine->name);
> + err = -EINVAL;
> + }
> +
> + igt_spinner_end();
> + if (i915_request_wait(rq, 0, HZ / 5) < 0)
> + err = -ETIME;
> + i915_request_put(rq);
> + if (err)
> + break;
> +
> + intel_gt_wait_for_idle(gt, HZ / 5);
> + intel_gt_pm_wait_for_idle(gt);
> +
> + /* gpu is idle, we should be in rc6 */
> + if (!is_rc6_active(rc6)) {
> + pr_err("%s is idle but doesn't go in rc6\n",
> + engine->name);
> + err = -EINVAL;
> + break;
> + }
> + }
> + intel_runtime_pm_put(gt->uncore->rpm, wakeref);
> +
> + igt_spinner_fini();
> + return err;
I'm afraid I think we should split the patch one more time, and push
ahead with live_rc6_busy() as that should be working regardless of our
discovery process around the thresholds.
-Chris
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[Intel-gfx] [PATCH v4] drm/i915/selftests: add basic selftests for rc6
From: Andi Shyti
Add three basic tests for rc6 power status:
1. live_rc6_basic - simply checks if rc6 works when it's enabled
or stops when it's disabled.
2. live_rc6_threshold - rc6 should not work when the evaluation
interval is less than the threshold and should work otherwise.
3. live_rc6_busy - keeps the gpu busy and then goes in idle;
checks that we don't fall in rc6 when busy and that we do fall
in rc6 when idling.
The three tests are added as sutest of the bigger live_late_gt_pm
selftest.
The basic rc6 functionality is tested by checking the reference
counter within the evaluation interval.
Signed-off-by: Andi Shyti
Cc: Chris Wilson
---
Hi,
just resending this patch that was going in decomposition. It's
rebased on top of drm-tip.
Andi
Changelog:
* v3 -> v4:
- just a small refactoring where test_rc6 becomes a
measure function while another test_rc6 checks the
return value from the measure.
* v2 -> v3:
- rebased on top of the latest drm-tip
- fixed exiting order in rc6_basic to avoid exiting
without releasing the pm reference
* v1 -> v2:
- some changes from Chris (thank you!).
drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 3 +
drivers/gpu/drm/i915/gt/selftest_rc6.c | 190 +++
drivers/gpu/drm/i915/gt/selftest_rc6.h | 3 +
3 files changed, 196 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
index 09ff8e4f88af..84d1a58cfa28 100644
--- a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
@@ -51,6 +51,9 @@ static int live_gt_resume(void *arg)
int intel_gt_pm_live_selftests(struct drm_i915_private *i915)
{
static const struct i915_subtest tests[] = {
+ SUBTEST(live_rc6_basic),
+ SUBTEST(live_rc6_threshold),
+ SUBTEST(live_rc6_busy),
SUBTEST(live_rc6_manual),
SUBTEST(live_gt_resume),
};
diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c
b/drivers/gpu/drm/i915/gt/selftest_rc6.c
index 5f7e2dcf5686..bd0e75421a4a 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rc6.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c
@@ -11,6 +11,7 @@
#include "selftest_rc6.h"
#include "selftests/i915_random.h"
+#include "selftests/igt_spinner.h"
int live_rc6_manual(void *arg)
{
@@ -202,3 +203,192 @@ int live_rc6_ctx_wa(void *arg)
kfree(engines);
return err;
}
+
+static bool test_rc6(struct intel_rc6 *rc6, bool enabled)
+{
+ struct intel_uncore *uncore = rc6_to_uncore(rc6);
+ intel_wakeref_t wakeref;
+ u32 ec1, ec2;
+ u32 interval;
+
+ wakeref = intel_runtime_pm_get(uncore->rpm);
+
+ interval = intel_uncore_read(uncore, GEN6_RC_EVALUATION_INTERVAL);
+
+ /*
+* the interval is stored in steps of 1.28us
+*/
+ interval = div_u64(mul_u32_u32(interval, 128),
+ 100 * 1000); /* => miliseconds */
+
+ ec1 = intel_uncore_read(uncore, GEN6_GT_GFX_RC6);
+
+ /*
+* It's not important to precisely wait the interval time.
+* I'll wait at least twice the time in order to be sure
+* that the counting happens in the reference counter.
+*/
+ msleep(2 * interval);
+
+ ec2 = intel_uncore_read(uncore, GEN6_GT_GFX_RC6);
+
+ intel_runtime_pm_put(uncore->rpm, wakeref);
+
+ return enabled != (ec1 >= ec2);
+}
+
+int live_rc6_basic(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_rc6 *rc6 = >rc6;
+ intel_wakeref_t wakeref;
+ int i, err = 0;
+
+ if (!rc6->supported)
+ return 0;
+
+ wakeref = intel_runtime_pm_get(gt->uncore->rpm);
+
+ /*
+* the two loops test rc6 both in case it's enabled
+* and in the case it's disabled. It restores the prvious
+* status
+*/
+ for (i = 0; i < 2; i++) {
+ if (!test_rc6(rc6, rc6->enabled)) {
+ err = -EINVAL;
+
+ /* restore before leaving */
+ if (!i)
+ goto exit;
+ }
+
+ if (rc6->enabled)
+ intel_rc6_disable(>rc6);
+ else
+ intel_rc6_enable(>rc6);
+ }
+
+exit:
+ intel_runtime_pm_put(gt->uncore->rpm, wakeref);
+ return err;
+}
+
+int live_rc6_threshold(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_uncore *uncore = gt->uncore;
+ struct intel_rc6 *rc6 = >rc6;
+ intel_wakeref_t wakeref;
+ u32 threshold, interval;
+ u32 t_orig, i_orig;
+ int err = 0;
+
+ if (!rc6->supported)
+ return 0;
+
+ wakeref = intel_runtime_pm_get(uncore->rpm);
+
+ t_orig = intel_uncore_read(uncore, GEN6_RC6_THRESHOLD);
+ i_orig = intel_uncore_read(uncore,
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gem: Don't leak non-persistent requests on changing engines (rev4)
== Series Details == Series: drm/i915/gem: Don't leak non-persistent requests on changing engines (rev4) URL : https://patchwork.freedesktop.org/series/73023/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7871 -> Patchwork_16442 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_16442 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_16442, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16442/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_16442: ### IGT changes ### Possible regressions * igt@i915_selftest@live_gem_contexts: - fi-kbl-x1275: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-kbl-x1275/igt@i915_selftest@live_gem_contexts.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16442/fi-kbl-x1275/igt@i915_selftest@live_gem_contexts.html Known issues Here are the changes found in Patchwork_16442 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_blt: - fi-hsw-4770r: [PASS][3] -> [DMESG-FAIL][4] ([i915#553] / [i915#725]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-hsw-4770r/igt@i915_selftest@live_blt.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16442/fi-hsw-4770r/igt@i915_selftest@live_blt.html - fi-hsw-4770:[PASS][5] -> [DMESG-FAIL][6] ([i915#725]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-hsw-4770/igt@i915_selftest@live_blt.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16442/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_execlists: - fi-icl-y: [PASS][7] -> [DMESG-FAIL][8] ([fdo#108569]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-icl-y/igt@i915_selftest@live_execlists.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16442/fi-icl-y/igt@i915_selftest@live_execlists.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-icl-u2: [PASS][9] -> [FAIL][10] ([i915#217]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16442/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html * igt@prime_self_import@basic-llseek-size: - fi-tgl-y: [PASS][11] -> [DMESG-WARN][12] ([CI#94] / [i915#402]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-tgl-y/igt@prime_self_imp...@basic-llseek-size.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16442/fi-tgl-y/igt@prime_self_imp...@basic-llseek-size.html Possible fixes * igt@i915_selftest@live_gtt: - fi-icl-guc: [TIMEOUT][13] ([fdo#112271]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-icl-guc/igt@i915_selftest@live_gtt.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16442/fi-icl-guc/igt@i915_selftest@live_gtt.html * igt@kms_addfb_basic@bad-pitch-128: - fi-tgl-y: [DMESG-WARN][15] ([CI#94] / [i915#402]) -> [PASS][16] +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-tgl-y/igt@kms_addfb_ba...@bad-pitch-128.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16442/fi-tgl-y/igt@kms_addfb_ba...@bad-pitch-128.html [CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271 [i915#217]: https://gitlab.freedesktop.org/drm/intel/issues/217 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 Participating hosts (45 -> 42) -- Additional (5): fi-bdw-5557u fi-hsw-peppy fi-bwr-2160 fi-ilk-650 fi-kbl-7500u Missing(8): fi-bsw-n3050 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-ivb-3770 fi-byt-clapper fi-bdw-samus fi-kbl-r Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7871 -> Patchwork_16442 CI-20190529: 20190529 CI_DRM_7871: c9b0237ee7ffb1bbb62f864f0b2d7b290ee1313d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5419: 44913a91e77434b03001bb9ea53216cd03c476e6 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16442: 66727965053c0e896d166743999590651bf4ca80 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 66727965053c
Re: [Intel-gfx] [PATCH] drm/i915/display/ehl: Add HBR2 and HBR3 voltage swing table
On Wed, Feb 05, 2020 at 12:56:47PM -0800, José Roberto de Souza wrote:
> EHL only differs from ICL on the voltage swing table for HBR2 and
> HBR3.
>
> BSpec: 21257
> Cc: Matt Roper
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 34 +++-
> 1 file changed, 33 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 1ab638e17046..3060cc37e1d2 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -568,6 +568,20 @@ static const struct cnl_ddi_buf_trans
> icl_combo_phy_ddi_translations_hdmi[] = {
> { 0x6, 0x7F, 0x35, 0x00, 0x0A },/* 600 850 3.0 */
> };
>
> +static const struct cnl_ddi_buf_trans
> ehl_combo_phy_ddi_translations_hbr2_hbr3[] = {
> + /* NT mV Trans mV db*/
> + { 0xA, 0x33, 0x3F, 0x00, 0x00 },/* 350 350 0.0 */
> + { 0xA, 0x47, 0x36, 0x00, 0x09 },/* 350 500 3.1 */
> + { 0xC, 0x64, 0x30, 0x00, 0x0F },/* 350 700 6.0 */
> + { 0x6, 0x7F, 0x2C, 0x00, 0x13 },/* 350 900 8.2 */
> + { 0xA, 0x46, 0x3F, 0x00, 0x00 },/* 500 500 0.0 */
> + { 0xC, 0x64, 0x36, 0x00, 0x09 },/* 500 700 2.9 */
> + { 0x6, 0x7F, 0x30, 0x00, 0x0F },/* 500 900 5.1 */
> + { 0xC, 0x61, 0x3F, 0x00, 0x00 },/* 650 700 0.6 */
> + { 0x6, 0x7F, 0x37, 0x00, 0x08 },/* 600 900 3.5 */
> + { 0x6, 0x7F, 0x3F, 0x00, 0x00 },/* 900 900 0.0 */
> +};
> +
> struct icl_mg_phy_ddi_buf_trans {
> u32 cri_txdeemph_override_5_0;
> u32 cri_txdeemph_override_11_6;
> @@ -929,6 +943,18 @@ icl_get_combo_buf_trans(struct drm_i915_private
> *dev_priv, int type, int rate,
> return icl_combo_phy_ddi_translations_dp_hbr2;
> }
>
> +static const struct cnl_ddi_buf_trans *
> +ehl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int
> rate,
> + int *n_entries)
> +{
> + if (type == INTEL_OUTPUT_DP && rate > 27) {
> + *n_entries =
> ARRAY_SIZE(ehl_combo_phy_ddi_translations_hbr2_hbr3);
> + return ehl_combo_phy_ddi_translations_hbr2_hbr3;
> + }
> +
> + return icl_get_combo_buf_trans(dev_priv, type, rate, n_entries);
> +}
> +
> static const struct cnl_ddi_buf_trans *
> tgl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int
> rate,
> int *n_entries)
> @@ -2415,7 +2441,10 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder
> *encoder)
> else
> n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans);
> } else if (INTEL_GEN(dev_priv) == 11) {
> - if (intel_phy_is_combo(dev_priv, phy))
> + if (IS_ELKHARTLAKE(dev_priv))
> + ehl_get_combo_buf_trans(dev_priv, encoder->type,
> + intel_dp->link_rate,
> _entries);
Might be more natural to promote this to the outer if/else (before the
general gen11 case).
But your table matches the bspec and the logic looks correct, so either
way,
Reviewed-by: Matt Roper
> + else if (intel_phy_is_combo(dev_priv, phy))
> icl_get_combo_buf_trans(dev_priv, encoder->type,
> intel_dp->link_rate,
> _entries);
> else
> @@ -2608,6 +2637,9 @@ static void icl_ddi_combo_vswing_program(struct
> drm_i915_private *dev_priv,
> if (INTEL_GEN(dev_priv) >= 12)
> ddi_translations = tgl_get_combo_buf_trans(dev_priv, type, rate,
> _entries);
> + else if (IS_ELKHARTLAKE(dev_priv))
> + ddi_translations = ehl_get_combo_buf_trans(dev_priv, type, rate,
> +_entries);
> else
> ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate,
> _entries);
> --
> 2.25.0
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
___
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[Intel-gfx] [PATCH 1/2] drm/i915/gt: Set the PP_DIR registers upon enabling ring submission
Always prime the page table registers before starting the ring. Even
though we will update these to the per-context page tables during
dispatch, it is prudent to ensure that the registers always point to a
valid PD.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
.../gpu/drm/i915/gt/intel_ring_submission.c | 40 ---
1 file changed, 26 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 9537d4912225..f70b903a98bc 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -627,6 +627,27 @@ static bool stop_ring(struct intel_engine_cs *engine)
return (ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) == 0;
}
+static struct i915_address_space *vm_alias(struct i915_address_space *vm)
+{
+ if (i915_is_ggtt(vm))
+ vm = _vm_to_ggtt(vm)->alias->vm;
+
+ return vm;
+}
+
+static void set_pp_dir(struct intel_engine_cs *engine)
+{
+ struct i915_address_space *vm = vm_alias(engine->gt->vm);
+
+ if (vm) {
+ struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
+
+ ENGINE_WRITE(engine, RING_PP_DIR_DCLV, PP_DIR_DCLV_2G);
+ ENGINE_WRITE(engine, RING_PP_DIR_BASE,
+px_base(ppgtt->pd)->ggtt_offset << 10);
+ }
+}
+
static int xcs_resume(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
@@ -685,6 +706,8 @@ static int xcs_resume(struct intel_engine_cs *engine)
GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail));
intel_ring_update_space(ring);
+ set_pp_dir(engine);
+
/* First wake the ring up to an empty/idle ring */
ENGINE_WRITE(engine, RING_HEAD, ring->head);
ENGINE_WRITE(engine, RING_TAIL, ring->head);
@@ -1161,23 +1184,12 @@ static void ring_context_destroy(struct kref *ref)
intel_context_free(ce);
}
-static struct i915_address_space *vm_alias(struct intel_context *ce)
-{
- struct i915_address_space *vm;
-
- vm = ce->vm;
- if (i915_is_ggtt(vm))
- vm = _vm_to_ggtt(vm)->alias->vm;
-
- return vm;
-}
-
static int __context_pin_ppgtt(struct intel_context *ce)
{
struct i915_address_space *vm;
int err = 0;
- vm = vm_alias(ce);
+ vm = vm_alias(ce->vm);
if (vm)
err = gen6_ppgtt_pin(i915_vm_to_ppgtt((vm)));
@@ -1188,7 +1200,7 @@ static void __context_unpin_ppgtt(struct intel_context
*ce)
{
struct i915_address_space *vm;
- vm = vm_alias(ce);
+ vm = vm_alias(ce->vm);
if (vm)
gen6_ppgtt_unpin(i915_vm_to_ppgtt(vm));
}
@@ -1545,7 +1557,7 @@ static int switch_context(struct i915_request *rq)
GEM_BUG_ON(HAS_EXECLISTS(rq->i915));
- ret = switch_mm(rq, vm_alias(ce));
+ ret = switch_mm(rq, vm_alias(ce->vm));
if (ret)
return ret;
--
2.25.0
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[Intel-gfx] [PATCH 2/2] drm/i915/gt: Stop invalidating the PD cachelines for gen7
Trust that the HW does the right thing after simply updating the PD_DIR_BASE? Signed-off-by: Chris Wilson Cc: Mika Kuoppala --- drivers/gpu/drm/i915/gt/intel_ring_submission.c | 10 +- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c index f70b903a98bc..b5a4b3d4ba6a 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c @@ -1333,14 +1333,10 @@ static int load_pd_dir(struct i915_request *rq, const struct intel_engine_cs * const engine = rq->engine; u32 *cs; - cs = intel_ring_begin(rq, 12); + cs = intel_ring_begin(rq, 6); if (IS_ERR(cs)) return PTR_ERR(cs); - *cs++ = MI_LOAD_REGISTER_IMM(1); - *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base)); - *cs++ = valid; - *cs++ = MI_LOAD_REGISTER_IMM(1); *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); *cs++ = px_base(ppgtt->pd)->ggtt_offset << 10; @@ -1351,10 +1347,6 @@ static int load_pd_dir(struct i915_request *rq, *cs++ = intel_gt_scratch_offset(engine->gt, INTEL_GT_SCRATCH_FIELD_DEFAULT); - *cs++ = MI_LOAD_REGISTER_IMM(1); - *cs++ = i915_mmio_reg_offset(RING_INSTPM(engine->mmio_base)); - *cs++ = _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE); - intel_ring_advance(rq, cs); return rq->engine->emit_flush(rq, EMIT_FLUSH); -- 2.25.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gem: Don't leak non-persistent requests on changing engines (rev4)
== Series Details == Series: drm/i915/gem: Don't leak non-persistent requests on changing engines (rev4) URL : https://patchwork.freedesktop.org/series/73023/ State : warning == Summary == $ dim checkpatch origin/drm-tip 66727965053c drm/i915/gem: Don't leak non-persistent requests on changing engines -:248: WARNING:USE_SPINLOCK_T: struct spinlock should be spinlock_t #248: FILE: drivers/gpu/drm/i915/gem/i915_gem_context_types.h:183: + struct spinlock stale_lock; total: 0 errors, 1 warnings, 0 checks, 240 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Hotplug cleanups (rev3)
== Series Details == Series: drm/i915: Hotplug cleanups (rev3) URL : https://patchwork.freedesktop.org/series/72348/ State : success == Summary == CI Bug Log - changes from CI_DRM_7871 -> Patchwork_16441 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16441/index.html Known issues Here are the changes found in Patchwork_16441 that come from known issues: ### IGT changes ### Issues hit * igt@i915_getparams_basic@basic-eu-total: - fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([CI#94] / [i915#402]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-tgl-y/igt@i915_getparams_ba...@basic-eu-total.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16441/fi-tgl-y/igt@i915_getparams_ba...@basic-eu-total.html * igt@i915_pm_rpm@basic-pci-d3-state: - fi-skl-6770hq: [PASS][3] -> [INCOMPLETE][4] ([i915#151]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-skl-6770hq/igt@i915_pm_...@basic-pci-d3-state.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16441/fi-skl-6770hq/igt@i915_pm_...@basic-pci-d3-state.html * igt@i915_selftest@live_blt: - fi-ivb-3770:[PASS][5] -> [DMESG-FAIL][6] ([i915#725]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-ivb-3770/igt@i915_selftest@live_blt.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16441/fi-ivb-3770/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_gem_contexts: - fi-cfl-guc: [PASS][7] -> [INCOMPLETE][8] ([fdo#106070] / [i915#424]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16441/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html Possible fixes * igt@i915_selftest@live_gtt: - fi-icl-guc: [TIMEOUT][9] ([fdo#112271]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-icl-guc/igt@i915_selftest@live_gtt.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16441/fi-icl-guc/igt@i915_selftest@live_gtt.html * igt@kms_addfb_basic@bad-pitch-128: - fi-tgl-y: [DMESG-WARN][11] ([CI#94] / [i915#402]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-tgl-y/igt@kms_addfb_ba...@bad-pitch-128.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16441/fi-tgl-y/igt@kms_addfb_ba...@bad-pitch-128.html Warnings * igt@i915_pm_rpm@basic-rte: - fi-kbl-guc: [SKIP][13] ([fdo#109271]) -> [FAIL][14] ([i915#579]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-kbl-guc/igt@i915_pm_...@basic-rte.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16441/fi-kbl-guc/igt@i915_pm_...@basic-rte.html [CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94 [fdo#106070]: https://bugs.freedesktop.org/show_bug.cgi?id=106070 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271 [i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#424]: https://gitlab.freedesktop.org/drm/intel/issues/424 [i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 Participating hosts (45 -> 36) -- Additional (4): fi-hsw-peppy fi-gdg-551 fi-bwr-2160 fi-kbl-7500u Missing(13): fi-cml-u2 fi-cml-s fi-bsw-n3050 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-whl-u fi-cfl-8109u fi-elk-e7500 fi-bsw-kefka fi-blb-e6850 fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7871 -> Patchwork_16441 CI-20190529: 20190529 CI_DRM_7871: c9b0237ee7ffb1bbb62f864f0b2d7b290ee1313d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5419: 44913a91e77434b03001bb9ea53216cd03c476e6 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16441: 610422e9de7a75cd4d4307d81c9fc4238e3d2950 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 610422e9de7a drm/i915: Use stashed away hpd isr bits in intel_digital_port_connected() f047f639c34b drm/i915: Stash hpd status bits under dev_priv 639d24713693 drm/i915: Turn intel_digital_port_connected() in a vfunc 96826f6b281d drm/i915: Mark all HPD capabled connectors as such ad091ae4f127 drm/i915/hpd: Replace the loop-within-loop with two independent loops == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16441/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/dc3co: Add description of how it works
Add a basic description about how DC3CO works to help people not
familiar with it.
While at it, I also improved the delayed work handle and function
names and removed a debug message that is ambiguous and not much
useful, no changes in behavior here.
Cc: Anshuman Gupta
Cc: Imre Deak
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_psr.c | 31 +---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
2 files changed, 23 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index db3d1561e9bf..273c4896eb57 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -59,6 +59,20 @@
* get called by the frontbuffer tracking code. Note that because of locking
* issues the self-refresh re-enable code is done from a work queue, which
* must be correctly synchronized/cancelled when shutting down the pipe."
+ *
+ * DC3CO (DC3 clock off)
+ *
+ * On top of PSR2, GEN12 adds a intermediate power savings state that turns
+ * clock off automatically during PSR2 idle state.
+ *
+ * Every time a flips occurs PSR2 will get out of deep sleep state(if it was),
+ * so DC3CO is enabled and tgl_dc3co_disable_work is schedule to run after 6
+ * frames, if no other flip occurs and the function above is executed, DC3CO is
+ * disabled and PSR2 is configured to enter deep sleep, resetting again in case
+ * of another flip.
+ * Front buffer modifications do not trigger DC3CO activation on purpose as it
+ * would bring a lot of complexity and most of the moderns systems will only
+ * use page flips.
*/
static bool psr_global_enabled(u32 debug)
@@ -583,17 +597,16 @@ static void tgl_psr2_disable_dc3co(struct
drm_i915_private *dev_priv)
psr2_program_idle_frames(dev_priv, psr_compute_idle_frames(intel_dp));
}
-static void tgl_dc5_idle_thread(struct work_struct *work)
+static void tgl_dc3co_disable_work(struct work_struct *work)
{
struct drm_i915_private *dev_priv =
- container_of(work, typeof(*dev_priv), psr.idle_work.work);
+ container_of(work, typeof(*dev_priv), psr.dc3co_work.work);
mutex_lock(_priv->psr.lock);
/* If delayed work is pending, it is not idle */
- if (delayed_work_pending(_priv->psr.idle_work))
+ if (delayed_work_pending(_priv->psr.dc3co_work))
goto unlock;
- drm_dbg_kms(_priv->drm, "DC5/6 idle thread\n");
tgl_psr2_disable_dc3co(dev_priv);
unlock:
mutex_unlock(_priv->psr.lock);
@@ -604,7 +617,7 @@ static void tgl_disallow_dc3co_on_psr2_exit(struct
drm_i915_private *dev_priv)
if (!dev_priv->psr.dc3co_enabled)
return;
- cancel_delayed_work(_priv->psr.idle_work);
+ cancel_delayed_work(_priv->psr.dc3co_work);
/* Before PSR2 exit disallow dc3co*/
tgl_psr2_disable_dc3co(dev_priv);
}
@@ -1040,7 +1053,7 @@ void intel_psr_disable(struct intel_dp *intel_dp,
mutex_unlock(_priv->psr.lock);
cancel_work_sync(_priv->psr.work);
- cancel_delayed_work_sync(_priv->psr.idle_work);
+ cancel_delayed_work_sync(_priv->psr.dc3co_work);
}
static void psr_force_hw_tracking_exit(struct drm_i915_private *dev_priv)
@@ -1350,7 +1363,7 @@ void intel_psr_invalidate(struct drm_i915_private
*dev_priv,
* When we will be completely rely on PSR2 S/W tracking in future,
* intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP
* event also therefore tgl_dc3co_flush() require to be changed
- * accrodingly in future.
+ * accordingly in future.
*/
static void
tgl_dc3co_flush(struct drm_i915_private *dev_priv,
@@ -1373,7 +1386,7 @@ tgl_dc3co_flush(struct drm_i915_private *dev_priv,
goto unlock;
tgl_psr2_enable_dc3co(dev_priv);
- mod_delayed_work(system_wq, _priv->psr.idle_work,
+ mod_delayed_work(system_wq, _priv->psr.dc3co_work,
dev_priv->psr.dc3co_exit_delay);
unlock:
@@ -1458,7 +1471,7 @@ void intel_psr_init(struct drm_i915_private *dev_priv)
dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;
INIT_WORK(_priv->psr.work, intel_psr_work);
- INIT_DELAYED_WORK(_priv->psr.idle_work, tgl_dc5_idle_thread);
+ INIT_DELAYED_WORK(_priv->psr.dc3co_work, tgl_dc3co_disable_work);
mutex_init(_priv->psr.lock);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3452926d7b77..da509d9b8895 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -504,7 +504,7 @@ struct i915_psr {
u16 su_x_granularity;
bool dc3co_enabled;
u32 dc3co_exit_delay;
- struct delayed_work idle_work;
+ struct delayed_work dc3co_work;
bool initially_probed;
};
--
2.25.0
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for Introduce CAP_PERFMON to secure system performance monitoring and observability (rev3)
== Series Details == Series: Introduce CAP_PERFMON to secure system performance monitoring and observability (rev3) URL : https://patchwork.freedesktop.org/series/72273/ State : success == Summary == CI Bug Log - changes from CI_DRM_7871 -> Patchwork_16439 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16439/index.html Known issues Here are the changes found in Patchwork_16439 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_blt: - fi-bsw-nick:[PASS][1] -> [INCOMPLETE][2] ([i915#392]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-bsw-nick/igt@i915_selftest@live_blt.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16439/fi-bsw-nick/igt@i915_selftest@live_blt.html - fi-hsw-4770r: [PASS][3] -> [DMESG-FAIL][4] ([i915#725]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-hsw-4770r/igt@i915_selftest@live_blt.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16439/fi-hsw-4770r/igt@i915_selftest@live_blt.html - fi-ivb-3770:[PASS][5] -> [DMESG-FAIL][6] ([i915#725]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-ivb-3770/igt@i915_selftest@live_blt.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16439/fi-ivb-3770/igt@i915_selftest@live_blt.html * igt@kms_chamelium@dp-edid-read: - fi-cml-u2: [PASS][7] -> [FAIL][8] ([i915#217] / [i915#976]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-cml-u2/igt@kms_chamel...@dp-edid-read.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16439/fi-cml-u2/igt@kms_chamel...@dp-edid-read.html * igt@vgem_basic@debugfs: - fi-tgl-y: [PASS][9] -> [DMESG-WARN][10] ([CI#94] / [i915#402]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-tgl-y/igt@vgem_ba...@debugfs.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16439/fi-tgl-y/igt@vgem_ba...@debugfs.html Possible fixes * igt@gem_exec_suspend@basic-s4-devices: - fi-tgl-y: [FAIL][11] ([CI#94]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-tgl-y/igt@gem_exec_susp...@basic-s4-devices.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16439/fi-tgl-y/igt@gem_exec_susp...@basic-s4-devices.html * igt@i915_selftest@live_gtt: - fi-icl-guc: [TIMEOUT][13] ([fdo#112271]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-icl-guc/igt@i915_selftest@live_gtt.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16439/fi-icl-guc/igt@i915_selftest@live_gtt.html * igt@kms_addfb_basic@bad-pitch-128: - fi-tgl-y: [DMESG-WARN][15] ([CI#94] / [i915#402]) -> [PASS][16] +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-tgl-y/igt@kms_addfb_ba...@bad-pitch-128.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16439/fi-tgl-y/igt@kms_addfb_ba...@bad-pitch-128.html [CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94 [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271 [i915#217]: https://gitlab.freedesktop.org/drm/intel/issues/217 [i915#392]: https://gitlab.freedesktop.org/drm/intel/issues/392 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 [i915#976]: https://gitlab.freedesktop.org/drm/intel/issues/976 Participating hosts (45 -> 47) -- Additional (7): fi-bdw-5557u fi-hsw-peppy fi-bwr-2160 fi-ilk-650 fi-kbl-7500u fi-gdg-551 fi-kbl-7560u Missing(5): fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7871 -> Patchwork_16439 CI-20190529: 20190529 CI_DRM_7871: c9b0237ee7ffb1bbb62f864f0b2d7b290ee1313d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5419: 44913a91e77434b03001bb9ea53216cd03c476e6 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16439: 8b8a811f8a617ad2a567f9502178826467119a9e @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 8b8a811f8a61 drivers/oprofile: open access for CAP_PERFMON privileged process 2206ed8dc834 drivers/perf: open access for CAP_PERFMON privileged process cbc0778c54e6 parisc/perf: open access for CAP_PERFMON privileged process 2040d2804af8 powerpc/perf: open access for CAP_PERFMON privileged process 1c9f2c014756 trace/bpf_trace: open access for CAP_PERFMON privileged process 633358b87a0b drm/i915/perf: open access for CAP_PERFMON privileged process ded14abe26f6 perf tool: extend Perf tool with CAP_PERFMON capability support 7aa9d11056aa perf/core: open access to probes for CAP_PERFMON privileged process
[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm: Introduce struct drm_device based WARN* and use them in i915 (rev6)
== Series Details == Series: drm: Introduce struct drm_device based WARN* and use them in i915 (rev6) URL : https://patchwork.freedesktop.org/series/72035/ State : failure == Summary == Applying: drm/i915/display/cdclk: Make WARN* drm specific where drm_priv ptr is available Applying: drm/i915/display/ddi: Make WARN* drm specific where drm_device ptr is available Applying: drm/i915/display/display: Make WARN* drm specific where drm_device ptr is available Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/display/intel_display.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/display/intel_display.c Applying: drm/i915/display/power: Make WARN* drm specific where drm_priv ptr is available Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/display/intel_display_power.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/display/intel_display_power.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/display/intel_display_power.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0004 drm/i915/display/power: Make WARN* drm specific where drm_priv ptr is available When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/selftests: add basic selftests for rc6
Quoting Andi Shyti (2020-02-05 18:40:55) > Hi Mika, > > > I have a faint memory that the interval was not always 1.28us > > but gen dependant. > > 1.28 is the incremental step and I haven't seen any different > value in the docs. Have you? The rc6 residency counter does flip over to a different clock on vlv/bsw. But the lack of information abounds, and I haven't seen anything that suggests these registers are anything but units of 1280ns. If we get to the point where we can differentiate between 833ns or 1280ns that will be very impressive. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/selftests: add basic selftests for rc6
Hi Mika,
> > +static bool test_rc6(struct intel_rc6 *rc6, bool enabled)
> > +{
> > + struct intel_uncore *uncore = rc6_to_uncore(rc6);
> > + intel_wakeref_t wakeref;
> > + u32 ec1, ec2;
> > + u32 interval;
> > +
> > + wakeref = intel_runtime_pm_get(uncore->rpm);
> > +
> > + interval = intel_uncore_read(uncore, GEN6_RC_EVALUATION_INTERVAL);
> > +
> > + /*
> > +* the interval is stored in steps of 1.28us
> > +*/
> > + interval = div_u64(mul_u32_u32(interval, 128),
> > + 100 * 1000); /* => miliseconds */
> > +
>
> s/miliseconds/milliseconds.
thanks!
> I have a faint memory that the interval was not always 1.28us
> but gen dependant.
1.28 is the incremental step and I haven't seen any different
value in the docs. Have you?
> > + pr_info("interval:%x [%dms], threshold:%x, rc6:%x, enabled?:%s\n",
> > + intel_uncore_read(uncore, GEN6_RC_EVALUATION_INTERVAL),
> > + interval,
> > + intel_uncore_read(uncore, GEN6_RC6_THRESHOLD),
> > + ec2 - ec1,
> > + yesno(enabled));
> > +
> > + intel_runtime_pm_put(uncore->rpm, wakeref);
> > +
> > + return enabled != (ec1 >= ec2);
>
> Wrap?
actually here I forgot a couple of things that went forgotten in
my git repo.
Anyway, do you mean with "wrap" to add parenthesis?
> > + intel_rc6_unpark(rc6);
> > +
> > + /* interval < threshold */
> > + if (!test_rc6(rc6, false)) {
>
> consider removing the assertion of 'activeness' in parameter
> and just if (!rc6_active(rc6)). Or am I missing something in here?
yes, you are right, it's misleading. I will make it more clear.
The basic idea is:
1. disable rc6
2. check whether it's disabled test_rc6(rc6, false)
or
1. enable rc6
2. check if it's enabled test_rc6(rc6, true)
Chris was skeptical about the naming as well.
Thanks!
Andi
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce CAP_PERFMON to secure system performance monitoring and observability (rev3)
== Series Details == Series: Introduce CAP_PERFMON to secure system performance monitoring and observability (rev3) URL : https://patchwork.freedesktop.org/series/72273/ State : warning == Summary == $ dim checkpatch origin/drm-tip afa7aa8e74c6 capabilities: introduce CAP_PERFMON to kernel and user space -:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #13: is available to a CAP_SYS_ADMIN privileged process [2]. Providing the access total: 0 errors, 1 warnings, 0 checks, 36 lines checked c97b60885c20 perf/core: open access to the core for CAP_PERFMON privileged process -:9: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #9: CAP_PERFMON capability singly, without the rest of CAP_SYS_ADMIN credentials, total: 0 errors, 1 warnings, 0 checks, 32 lines checked 7aa9d11056aa perf/core: open access to probes for CAP_PERFMON privileged process -:18: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #18: monitoring and observability operations (POSIX IEEE 1003.1e 2.2.2.39 principle total: 0 errors, 1 warnings, 0 checks, 16 lines checked ded14abe26f6 perf tool: extend Perf tool with CAP_PERFMON capability support 633358b87a0b drm/i915/perf: open access for CAP_PERFMON privileged process 1c9f2c014756 trace/bpf_trace: open access for CAP_PERFMON privileged process 2040d2804af8 powerpc/perf: open access for CAP_PERFMON privileged process cbc0778c54e6 parisc/perf: open access for CAP_PERFMON privileged process 2206ed8dc834 drivers/perf: open access for CAP_PERFMON privileged process 8b8a811f8a61 drivers/oprofile: open access for CAP_PERFMON privileged process ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/display/ehl: Add HBR2 and HBR3 voltage swing table
EHL only differs from ICL on the voltage swing table for HBR2 and
HBR3.
BSpec: 21257
Cc: Matt Roper
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_ddi.c | 34 +++-
1 file changed, 33 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 1ab638e17046..3060cc37e1d2 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -568,6 +568,20 @@ static const struct cnl_ddi_buf_trans
icl_combo_phy_ddi_translations_hdmi[] = {
{ 0x6, 0x7F, 0x35, 0x00, 0x0A },/* 600 850 3.0 */
};
+static const struct cnl_ddi_buf_trans
ehl_combo_phy_ddi_translations_hbr2_hbr3[] = {
+ /* NT mV Trans mV db*/
+ { 0xA, 0x33, 0x3F, 0x00, 0x00 },/* 350 350 0.0 */
+ { 0xA, 0x47, 0x36, 0x00, 0x09 },/* 350 500 3.1 */
+ { 0xC, 0x64, 0x30, 0x00, 0x0F },/* 350 700 6.0 */
+ { 0x6, 0x7F, 0x2C, 0x00, 0x13 },/* 350 900 8.2 */
+ { 0xA, 0x46, 0x3F, 0x00, 0x00 },/* 500 500 0.0 */
+ { 0xC, 0x64, 0x36, 0x00, 0x09 },/* 500 700 2.9 */
+ { 0x6, 0x7F, 0x30, 0x00, 0x0F },/* 500 900 5.1 */
+ { 0xC, 0x61, 0x3F, 0x00, 0x00 },/* 650 700 0.6 */
+ { 0x6, 0x7F, 0x37, 0x00, 0x08 },/* 600 900 3.5 */
+ { 0x6, 0x7F, 0x3F, 0x00, 0x00 },/* 900 900 0.0 */
+};
+
struct icl_mg_phy_ddi_buf_trans {
u32 cri_txdeemph_override_5_0;
u32 cri_txdeemph_override_11_6;
@@ -929,6 +943,18 @@ icl_get_combo_buf_trans(struct drm_i915_private *dev_priv,
int type, int rate,
return icl_combo_phy_ddi_translations_dp_hbr2;
}
+static const struct cnl_ddi_buf_trans *
+ehl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
+ int *n_entries)
+{
+ if (type == INTEL_OUTPUT_DP && rate > 27) {
+ *n_entries =
ARRAY_SIZE(ehl_combo_phy_ddi_translations_hbr2_hbr3);
+ return ehl_combo_phy_ddi_translations_hbr2_hbr3;
+ }
+
+ return icl_get_combo_buf_trans(dev_priv, type, rate, n_entries);
+}
+
static const struct cnl_ddi_buf_trans *
tgl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
int *n_entries)
@@ -2415,7 +2441,10 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder
*encoder)
else
n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans);
} else if (INTEL_GEN(dev_priv) == 11) {
- if (intel_phy_is_combo(dev_priv, phy))
+ if (IS_ELKHARTLAKE(dev_priv))
+ ehl_get_combo_buf_trans(dev_priv, encoder->type,
+ intel_dp->link_rate,
_entries);
+ else if (intel_phy_is_combo(dev_priv, phy))
icl_get_combo_buf_trans(dev_priv, encoder->type,
intel_dp->link_rate,
_entries);
else
@@ -2608,6 +2637,9 @@ static void icl_ddi_combo_vswing_program(struct
drm_i915_private *dev_priv,
if (INTEL_GEN(dev_priv) >= 12)
ddi_translations = tgl_get_combo_buf_trans(dev_priv, type, rate,
_entries);
+ else if (IS_ELKHARTLAKE(dev_priv))
+ ddi_translations = ehl_get_combo_buf_trans(dev_priv, type, rate,
+ _entries);
else
ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate,
_entries);
--
2.25.0
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[Intel-gfx] ✗ Fi.CI.BAT: failure for In order to readout DP SDPs, refactors the handling of DP SDPs (rev4)
== Series Details == Series: In order to readout DP SDPs, refactors the handling of DP SDPs (rev4) URL : https://patchwork.freedesktop.org/series/72853/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7871 -> Patchwork_16438 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_16438 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_16438, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16438/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_16438: ### IGT changes ### Possible regressions * igt@gem_exec_suspend@basic-s0: - fi-cfl-8109u: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-cfl-8109u/igt@gem_exec_susp...@basic-s0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16438/fi-cfl-8109u/igt@gem_exec_susp...@basic-s0.html Known issues Here are the changes found in Patchwork_16438 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s0: - fi-skl-6770hq: [PASS][3] -> [INCOMPLETE][4] ([i915#198]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-skl-6770hq/igt@gem_exec_susp...@basic-s0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16438/fi-skl-6770hq/igt@gem_exec_susp...@basic-s0.html - fi-apl-guc: [PASS][5] -> [INCOMPLETE][6] ([fdo#103927]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-apl-guc/igt@gem_exec_susp...@basic-s0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16438/fi-apl-guc/igt@gem_exec_susp...@basic-s0.html * igt@i915_selftest@live_execlists: - fi-icl-y: [PASS][7] -> [DMESG-FAIL][8] ([fdo#108569]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-icl-y/igt@i915_selftest@live_execlists.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16438/fi-icl-y/igt@i915_selftest@live_execlists.html Warnings * igt@runner@aborted: - fi-kbl-soraka: [FAIL][9] ([fdo#109383] / [fdo#111012]) -> [FAIL][10] ([i915#192] / [i915#193] / [i915#194]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-kbl-soraka/igt@run...@aborted.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16438/fi-kbl-soraka/igt@run...@aborted.html - fi-cml-s: [FAIL][11] ([fdo#111012] / [fdo#111764] / [i915#577]) -> [FAIL][12] ([i915#577]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-cml-s/igt@run...@aborted.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16438/fi-cml-s/igt@run...@aborted.html [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#109383]: https://bugs.freedesktop.org/show_bug.cgi?id=109383 [fdo#111012]: https://bugs.freedesktop.org/show_bug.cgi?id=111012 [fdo#111764]: https://bugs.freedesktop.org/show_bug.cgi?id=111764 [i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192 [i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193 [i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#577]: https://gitlab.freedesktop.org/drm/intel/issues/577 Participating hosts (45 -> 38) -- Additional (6): fi-bdw-5557u fi-hsw-peppy fi-bwr-2160 fi-ilk-650 fi-kbl-7500u fi-gdg-551 Missing(13): fi-byt-j1900 fi-glk-dsi fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-hsw-4770 fi-whl-u fi-ivb-3770 fi-elk-e7500 fi-bdw-samus fi-byt-clapper fi-skl-6600u fi-snb-2600 Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7871 -> Patchwork_16438 CI-20190529: 20190529 CI_DRM_7871: c9b0237ee7ffb1bbb62f864f0b2d7b290ee1313d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5419: 44913a91e77434b03001bb9ea53216cd03c476e6 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16438: f4f8b0f85ef923faf6fed29687c3a926209695cd @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == f4f8b0f85ef9 drm/i915/psr: Use new DP VSC SDP compute routine on PSR 64b807768c4c drm/i915/dp: Add compute routine for DP PSR VSC SDP 279ec55c845f drm/i915: Stop sending DP SDPs on intel_ddi_post_disable_dp() a483a4881789 drm/i915: Program DP SDPs on pipe updates 12492e08c39d drm/i915: Add state readout for DP VSC SDP f5aeba2edcb3 drm/i915: Add state readout for DP HDR Metadata Infoframe SDP 5070b80edd7a drm/i915: Program DP SDPs with computed configs 5716f680b4a0 drm/i915: Include DP VSC SDP in
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dsb: Pre allocate and late cleanup of cmd buffer
== Series Details ==
Series: drm/i915/dsb: Pre allocate and late cleanup of cmd buffer
URL : https://patchwork.freedesktop.org/series/73036/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7871 -> Patchwork_16437
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16437/index.html
Known issues
Here are the changes found in Patchwork_16437 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_module_load@reload:
- fi-tgl-y: [PASS][1] -> [INCOMPLETE][2] ([CI#94] / [i915#472])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-tgl-y/igt@i915_module_l...@reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16437/fi-tgl-y/igt@i915_module_l...@reload.html
* igt@i915_selftest@live_blt:
- fi-hsw-4770r: [PASS][3] -> [DMESG-FAIL][4] ([i915#553] / [i915#725])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-hsw-4770r/igt@i915_selftest@live_blt.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16437/fi-hsw-4770r/igt@i915_selftest@live_blt.html
- fi-ivb-3770:[PASS][5] -> [DMESG-FAIL][6] ([i915#770])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-ivb-3770/igt@i915_selftest@live_blt.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16437/fi-ivb-3770/igt@i915_selftest@live_blt.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-skl-6700k2: [PASS][7] -> [INCOMPLETE][8] ([i915#69])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-skl-6700k2/igt@kms_chamel...@common-hpd-after-suspend.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16437/fi-skl-6700k2/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@prime_self_import@basic-llseek-size:
- fi-tgl-y: [PASS][9] -> [DMESG-WARN][10] ([CI#94] / [i915#402])
+1 similar issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-tgl-y/igt@prime_self_imp...@basic-llseek-size.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16437/fi-tgl-y/igt@prime_self_imp...@basic-llseek-size.html
Possible fixes
* igt@gem_close_race@basic-threads:
- fi-byt-n2820: [INCOMPLETE][11] ([i915#45]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-byt-n2820/igt@gem_close_r...@basic-threads.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16437/fi-byt-n2820/igt@gem_close_r...@basic-threads.html
* igt@gem_exec_suspend@basic-s4-devices:
- fi-tgl-y: [FAIL][13] ([CI#94]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-tgl-y/igt@gem_exec_susp...@basic-s4-devices.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16437/fi-tgl-y/igt@gem_exec_susp...@basic-s4-devices.html
* igt@i915_selftest@live_gtt:
- fi-icl-guc: [TIMEOUT][15] ([fdo#112271]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-icl-guc/igt@i915_selftest@live_gtt.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16437/fi-icl-guc/igt@i915_selftest@live_gtt.html
* igt@kms_addfb_basic@bad-pitch-128:
- fi-tgl-y: [DMESG-WARN][17] ([CI#94] / [i915#402]) -> [PASS][18]
+1 similar issue
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/fi-tgl-y/igt@kms_addfb_ba...@bad-pitch-128.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16437/fi-tgl-y/igt@kms_addfb_ba...@bad-pitch-128.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94
[fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45
[i915#472]: https://gitlab.freedesktop.org/drm/intel/issues/472
[i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
[i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725
[i915#770]: https://gitlab.freedesktop.org/drm/intel/issues/770
Participating hosts (45 -> 46)
--
Additional (6): fi-bdw-5557u fi-hsw-peppy fi-bwr-2160 fi-ilk-650 fi-kbl-7500u
fi-gdg-551
Missing(5): fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper
fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7871 -> Patchwork_16437
CI-20190529: 20190529
CI_DRM_7871: c9b0237ee7ffb1bbb62f864f0b2d7b290ee1313d @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5419: 44913a91e77434b03001bb9ea53216cd03c476e6 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Re: [Intel-gfx] [PATCH v2 01/10] drm/i915/debugfs: Pass guc_log struct to i915_guc_log_info
On 2/4/20 11:58 PM, Jani Nikula wrote:
On Tue, 04 Feb 2020, "Michal Wajdeczko" wrote:
On Tue, 04 Feb 2020 00:28:29 +0100, Daniele Ceraolo Spurio
wrote:
The log struct is the only thing the function needs (apart from
the seq_file), so we can pass just that instead of the whole dev_priv.
v2: Split this change to its own patch (Michal)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Cc: John Harrison
Cc: Matthew Brost
---
drivers/gpu/drm/i915/i915_debugfs.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index e75e8212f03b..7264c0ff766c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1753,10 +1753,8 @@ stringify_guc_log_type(enum guc_log_buffer_type
type)
return "";
}
-static void i915_guc_log_info(struct seq_file *m,
- struct drm_i915_private *dev_priv)
+static void i915_guc_log_info(struct seq_file *m, struct intel_guc_log
*log)
maybe to avoid polluting i915_debugfs.c we should move this function to
gt/uc/intel_guc_log.c as universal printer:
On that note, I'm going to split display bits from i915_debugfs.c to a
file of its own under display/ [1]. I think there's enough guc/huc stuff
to warrant moving them to a separate file maybe under gt/uc/.
Andi is already looking at moving all the GT bits under gt/, so the uc
functions will move as part of that.
Daniele
BR,
Jani.
[1]
http://patchwork.freedesktop.org/patch/msgid/20200204151810.8189-1-jani.nik...@intel.com
void intel_guc_log_info(struct intel_guc_log *log, struct drm_printer *p)
{
- struct intel_guc_log *log = _priv->gt.uc.guc.log;
enum guc_log_buffer_type type;
if (!intel_guc_log_relay_created(log)) {
@@ -1784,7 +1782,7 @@ static int i915_guc_info(struct seq_file *m, void
*data)
if (!USES_GUC(dev_priv))
return -ENODEV;
- i915_guc_log_info(m, dev_priv);
+ i915_guc_log_info(m, _priv->gt.uc.guc.log);
too many dots ... this is "guc" info function, maybe we should have:
struct intel_guc *guc = _priv->gt.uc.guc;
or
struct intel_gt *gt = _priv->gt;
struct intel_uc *uc = >uc;
struct intel_guc *guc = >guc;
as that "guc" is likely to be reused in "more" below
/* Add more as required ... */
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[Intel-gfx] [PATCH] drm/i915/gem: Don't leak non-persistent requests on changing engines
If we have a set of active engines marked as being non-persistent, we
lose track of those if the user replaces those engines with
I915_CONTEXT_PARAM_ENGINES. As part of our uABI contract is that
non-persistent requests are terminated if they are no longer being
tracked by the user's context (in order to prevent a lost request
causing an untracked and so unstoppable GPU hang), we need to apply the
same context cancellation upon changing engines.
v2: Track stale engines[] so we only reap at context closure.
Fixes: a0e047156cde ("drm/i915/gem: Make context persistence optional")
Testcase: igt/gem_ctx_peristence/replace
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 118 --
.../gpu/drm/i915/gem/i915_gem_context_types.h | 11 +-
drivers/gpu/drm/i915/i915_sw_fence.c | 15 ++-
drivers/gpu/drm/i915/i915_sw_fence.h | 2 +-
4 files changed, 133 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 52a749691a8d..21ce84cc1f68 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -270,7 +270,8 @@ static struct i915_gem_engines *default_engines(struct
i915_gem_context *ctx)
if (!e)
return ERR_PTR(-ENOMEM);
- init_rcu_head(>rcu);
+ e->ctx = ctx;
+
for_each_engine(engine, gt, id) {
struct intel_context *ce;
@@ -450,7 +451,7 @@ static struct intel_engine_cs *active_engine(struct
intel_context *ce)
return engine;
}
-static void kill_context(struct i915_gem_context *ctx)
+static void kill_engines(struct i915_gem_engines *engines)
{
struct i915_gem_engines_iter it;
struct intel_context *ce;
@@ -462,7 +463,7 @@ static void kill_context(struct i915_gem_context *ctx)
* However, we only care about pending requests, so only include
* engines on which there are incomplete requests.
*/
- for_each_gem_engine(ce, __context_engines_static(ctx), it) {
+ for_each_gem_engine(ce, engines, it) {
struct intel_engine_cs *engine;
if (intel_context_set_banned(ce))
@@ -484,10 +485,41 @@ static void kill_context(struct i915_gem_context *ctx)
* the context from the GPU, we have to resort to a full
* reset. We hope the collateral damage is worth it.
*/
- __reset_context(ctx, engine);
+ __reset_context(engines->ctx, engine);
+ }
+}
+
+static void kill_stale_engines(struct i915_gem_context *ctx)
+{
+ if (!list_empty(>stale_list)) {
+ struct i915_gem_engines *pos, *next;
+ unsigned long flags;
+
+ spin_lock_irqsave(>stale_lock, flags);
+ list_for_each_entry_safe(pos, next, >stale_list, link) {
+ if (!i915_sw_fence_await(>fence))
+ continue;
+
+ spin_unlock_irqrestore(>stale_lock, flags);
+
+ kill_engines(pos);
+
+ spin_lock_irqsave(>stale_lock, flags);
+ list_safe_reset_next(pos, next, link);
+ list_del_init(>link);
+
+ i915_sw_fence_complete(>fence);
+ }
+ spin_unlock_irqrestore(>stale_lock, flags);
}
}
+static void kill_context(struct i915_gem_context *ctx)
+{
+ kill_stale_engines(ctx);
+ kill_engines(__context_engines_static(ctx));
+}
+
static void set_closed_name(struct i915_gem_context *ctx)
{
char *s;
@@ -602,6 +634,9 @@ __create_context(struct drm_i915_private *i915)
ctx->sched.priority = I915_USER_PRIORITY(I915_PRIORITY_NORMAL);
mutex_init(>mutex);
+ INIT_LIST_HEAD(>stale_list);
+ spin_lock_init(>stale_lock);
+
mutex_init(>engines_mutex);
e = default_engines(ctx);
if (IS_ERR(e)) {
@@ -1529,6 +1564,71 @@ static const i915_user_extension_fn
set_engines__extensions[] = {
[I915_CONTEXT_ENGINES_EXT_BOND] = set_engines__bond,
};
+static int engines_notify(struct i915_sw_fence *fence,
+ enum i915_sw_fence_notify state)
+{
+ struct i915_gem_engines *engines =
+ container_of(fence, typeof(*engines), fence);
+
+ switch (state) {
+ case FENCE_COMPLETE:
+ if (!list_empty(>link)) {
+ struct i915_gem_context *ctx = engines->ctx;
+ unsigned long flags;
+
+ spin_lock_irqsave(>stale_lock, flags);
+ list_del(>link);
+ spin_unlock_irqrestore(>stale_lock, flags);
+ }
+ break;
+
+ case FENCE_FREE:
+ init_rcu_head(>rcu);
+ call_rcu(>rcu,
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for In order to readout DP SDPs, refactors the handling of DP SDPs (rev4)
== Series Details ==
Series: In order to readout DP SDPs, refactors the handling of DP SDPs (rev4)
URL : https://patchwork.freedesktop.org/series/72853/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
337be6e4a25e drm: add DP 1.4 VSC SDP Payload related enums and a structure
8e6cf3c5fe7f drm/i915/dp: Add compute routine for DP VSC SDP
e34ff27be612 drm/i915/dp: Add compute routine for DP HDR Metadata Infoframe SDP
e92dd2d13e47 drm/i915/dp: Add writing of DP SDPs (Secondary Data Packet)
d587ae502b80 video/hdmi: Add Unpack only function for DRM infoframe
7fc4c0069309 drm/i915/dp: Read out DP SDPs (Secondary Data Packet)
c754babdda67 drm: Add logging function for DP VSC SDP
60f01133b46c drm/i915: Include HDMI DRM infoframe in the crtc state dump
983f664b850e drm/i915: Include DP HDR Metadata Infoframe SDP in the crtc state
dump
5716f680b4a0 drm/i915: Include DP VSC SDP in the crtc state dump
5070b80edd7a drm/i915: Program DP SDPs with computed configs
f5aeba2edcb3 drm/i915: Add state readout for DP HDR Metadata Infoframe SDP
12492e08c39d drm/i915: Add state readout for DP VSC SDP
-:81: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible
side-effects?
#81: FILE: drivers/gpu/drm/i915/display/intel_display.c:13895:
+#define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
+ if (!intel_compare_dp_vsc_sdp(_config->infoframes.name, \
+ _config->infoframes.name)) { \
+ pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset,
__stringify(name), \
+
_config->infoframes.name, \
+ _config->infoframes.name);
\
+ ret = false; \
+ } \
+} while (0)
total: 0 errors, 0 warnings, 1 checks, 74 lines checked
a483a4881789 drm/i915: Program DP SDPs on pipe updates
279ec55c845f drm/i915: Stop sending DP SDPs on intel_ddi_post_disable_dp()
64b807768c4c drm/i915/dp: Add compute routine for DP PSR VSC SDP
f4f8b0f85ef9 drm/i915/psr: Use new DP VSC SDP compute routine on PSR
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[Intel-gfx] [PATCH] drm/i915/gem: Don't leak non-persistent requests on changing engines
If we have a set of active engines marked as being non-persistent, we
lose track of those if the user replaces those engines with
I915_CONTEXT_PARAM_ENGINES. As part of our uABI contract is that
non-persistent requests are terminated if they are no longer being
tracked by the user's context (in order to prevent a lost request
causing an untracked and so unstoppable GPU hang), we need to apply the
same context cancellation upon changing engines.
v2: Track stale engines[] so we only reap at context closure.
Fixes: a0e047156cde ("drm/i915/gem: Make context persistence optional")
Testcase: igt/gem_ctx_peristence/replace
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 109 --
.../gpu/drm/i915/gem/i915_gem_context_types.h | 11 +-
drivers/gpu/drm/i915/i915_sw_fence.c | 15 ++-
drivers/gpu/drm/i915/i915_sw_fence.h | 2 +-
4 files changed, 124 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 52a749691a8d..01ffb1d1c6a0 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -270,7 +270,8 @@ static struct i915_gem_engines *default_engines(struct
i915_gem_context *ctx)
if (!e)
return ERR_PTR(-ENOMEM);
- init_rcu_head(>rcu);
+ e->ctx = ctx;
+
for_each_engine(engine, gt, id) {
struct intel_context *ce;
@@ -450,7 +451,7 @@ static struct intel_engine_cs *active_engine(struct
intel_context *ce)
return engine;
}
-static void kill_context(struct i915_gem_context *ctx)
+static void kill_engines(struct i915_gem_engines *engines)
{
struct i915_gem_engines_iter it;
struct intel_context *ce;
@@ -462,7 +463,7 @@ static void kill_context(struct i915_gem_context *ctx)
* However, we only care about pending requests, so only include
* engines on which there are incomplete requests.
*/
- for_each_gem_engine(ce, __context_engines_static(ctx), it) {
+ for_each_gem_engine(ce, engines, it) {
struct intel_engine_cs *engine;
if (intel_context_set_banned(ce))
@@ -484,8 +485,32 @@ static void kill_context(struct i915_gem_context *ctx)
* the context from the GPU, we have to resort to a full
* reset. We hope the collateral damage is worth it.
*/
- __reset_context(ctx, engine);
+ __reset_context(engines->ctx, engine);
+ }
+}
+
+static void kill_context(struct i915_gem_context *ctx)
+{
+ struct i915_gem_engines *pos, *next;
+
+ spin_lock(>stale_lock);
+ list_for_each_entry_safe(pos, next, >stale_list, link) {
+ if (!i915_sw_fence_await(>fence))
+ continue;
+
+ spin_unlock(>stale_lock);
+
+ kill_engines(pos);
+
+ spin_lock(>stale_lock);
+ list_safe_reset_next(pos, next, link);
+ list_del_init(>link);
+
+ i915_sw_fence_complete(>fence);
}
+ spin_unlock(>stale_lock);
+
+ kill_engines(__context_engines_static(ctx));
}
static void set_closed_name(struct i915_gem_context *ctx)
@@ -602,6 +627,9 @@ __create_context(struct drm_i915_private *i915)
ctx->sched.priority = I915_USER_PRIORITY(I915_PRIORITY_NORMAL);
mutex_init(>mutex);
+ INIT_LIST_HEAD(>stale_list);
+ spin_lock_init(>stale_lock);
+
mutex_init(>engines_mutex);
e = default_engines(ctx);
if (IS_ERR(e)) {
@@ -1529,6 +1557,66 @@ static const i915_user_extension_fn
set_engines__extensions[] = {
[I915_CONTEXT_ENGINES_EXT_BOND] = set_engines__bond,
};
+static int engines_notify(struct i915_sw_fence *fence,
+ enum i915_sw_fence_notify state)
+{
+ struct i915_gem_engines *engines =
+ container_of(fence, typeof(*engines), fence);
+
+ switch (state) {
+ case FENCE_COMPLETE:
+ if (!list_empty(>link)) {
+ spin_lock(>ctx->stale_lock);
+ list_del(>link);
+ spin_unlock(>ctx->stale_lock);
+ }
+ break;
+
+ case FENCE_FREE:
+ init_rcu_head(>rcu);
+ call_rcu(>rcu, free_engines_rcu);
+ break;
+ }
+
+ return NOTIFY_DONE;
+}
+
+static int engines_listen(struct i915_gem_engines *engines)
+{
+ struct i915_gem_engines_iter it;
+ struct intel_context *ce;
+
+ GEM_BUG_ON(!engines);
+ i915_sw_fence_init(>fence, engines_notify);
+
+ for_each_gem_engine(ce, engines, it) {
+ struct dma_fence *fence;
+ int err;
+
+ if (!ce->timeline)
+ continue;
+
+ fence
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Relax timeout for error-interrupt reset processing
== Series Details == Series: drm/i915/selftests: Relax timeout for error-interrupt reset processing URL : https://patchwork.freedesktop.org/series/73032/ State : success == Summary == CI Bug Log - changes from CI_DRM_7870 -> Patchwork_16436 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16436/index.html Known issues Here are the changes found in Patchwork_16436 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_parallel@contexts: - fi-byt-n2820: [PASS][1] -> [FAIL][2] ([i915#694]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7870/fi-byt-n2820/igt@gem_exec_paral...@contexts.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16436/fi-byt-n2820/igt@gem_exec_paral...@contexts.html * igt@i915_selftest@live_active: - fi-icl-u2: [PASS][3] -> [DMESG-FAIL][4] ([i915#765]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7870/fi-icl-u2/igt@i915_selftest@live_active.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16436/fi-icl-u2/igt@i915_selftest@live_active.html * igt@i915_selftest@live_gem_contexts: - fi-hsw-peppy: [PASS][5] -> [DMESG-FAIL][6] ([i915#722]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7870/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16436/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html * igt@kms_addfb_basic@bad-pitch-0: - fi-tgl-y: [PASS][7] -> [DMESG-WARN][8] ([CI#94] / [i915#402]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7870/fi-tgl-y/igt@kms_addfb_ba...@bad-pitch-0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16436/fi-tgl-y/igt@kms_addfb_ba...@bad-pitch-0.html * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [PASS][9] -> [FAIL][10] ([fdo#109635] / [i915#217]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7870/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16436/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html * igt@kms_frontbuffer_tracking@basic: - fi-hsw-peppy: [PASS][11] -> [DMESG-WARN][12] ([i915#44]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7870/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16436/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html Possible fixes * igt@gem_exec_suspend@basic-s4-devices: - fi-tgl-y: [FAIL][13] ([CI#94]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7870/fi-tgl-y/igt@gem_exec_susp...@basic-s4-devices.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16436/fi-tgl-y/igt@gem_exec_susp...@basic-s4-devices.html * igt@i915_getparams_basic@basic-subslice-total: - fi-tgl-y: [DMESG-WARN][15] ([CI#94] / [i915#402]) -> [PASS][16] +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7870/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16436/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html * igt@i915_pm_rpm@module-reload: - fi-skl-6770hq: [FAIL][17] ([i915#178]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7870/fi-skl-6770hq/igt@i915_pm_...@module-reload.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16436/fi-skl-6770hq/igt@i915_pm_...@module-reload.html * igt@i915_selftest@live_blt: - fi-byt-n2820: [DMESG-FAIL][19] ([i915#725]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7870/fi-byt-n2820/igt@i915_selftest@live_blt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16436/fi-byt-n2820/igt@i915_selftest@live_blt.html - fi-hsw-4770:[DMESG-FAIL][21] ([i915#563]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7870/fi-hsw-4770/igt@i915_selftest@live_blt.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16436/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][23] ([fdo#111096] / [i915#323]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7870/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16436/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94 [fdo#109635]: https://bugs.freedesktop.org/show_bug.cgi?id=109635 [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 [i915#178]: https://gitlab.freedesktop.org/drm/intel/issues/178 [i915#217]:
Re: [Intel-gfx] [PATCH v17 0/6] Enable second DBuf slice for ICL and TGL
On Mon, Feb 03, 2020 at 01:06:24AM +0200, Stanislav Lisovskiy wrote: > Those patch series, do some initial preparation DBuf manipulating code > cleanups, i.e remove redundant structures/code, switch to mask > based DBuf manupulation, get into use DBuf assignment according to > BSpec rules. > > Stanislav Lisovskiy (6): > drm/i915: Remove skl_ddl_allocation struct > drm/i915: Move dbuf slice update to proper place > drm/i915: Update dbuf slices only with full modeset > drm/i915: Introduce parameterized DBUF_CTL > drm/i915: Manipulate DBuf slices properly > drm/i915: Correctly map DBUF slices to pipes Pushed the lot to dinq. Thanks for the patches and reviews. > > drivers/gpu/drm/i915/display/intel_display.c | 54 ++- > .../drm/i915/display/intel_display_power.c| 100 ++-- > .../drm/i915/display/intel_display_power.h| 5 + > .../drm/i915/display/intel_display_types.h| 4 +- > drivers/gpu/drm/i915/gvt/handlers.c | 2 +- > drivers/gpu/drm/i915/i915_drv.h | 11 +- > drivers/gpu/drm/i915/i915_pci.c | 5 +- > drivers/gpu/drm/i915/i915_reg.h | 6 +- > drivers/gpu/drm/i915/intel_device_info.h | 1 + > drivers/gpu/drm/i915/intel_pm.c | 449 +++--- > drivers/gpu/drm/i915/intel_pm.h | 5 +- > 11 files changed, 479 insertions(+), 163 deletions(-) > > -- > 2.24.1.485.gad05a3d8e5 -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915/gem: Don't leak non-persistent requests on changing engines
Quoting Tvrtko Ursulin (2020-02-05 18:33:57)
>
> On 05/02/2020 16:44, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2020-02-05 16:22:34)
> >> On 05/02/2020 12:13, Chris Wilson wrote:
> >>> If we have a set of active engines marked as being non-persistent, we
> >>> lose track of those if the user replaces those engines with
> >>> I915_CONTEXT_PARAM_ENGINES. As part of our uABI contract is that
> >>> non-persistent requests are terminated if they are no longer being
> >>> tracked by the user's context (in order to prevent a lost request
> >>> causing an untracked and so unstoppable GPU hang), we need to apply the
> >>> same context cancellation upon changing engines.
> >>>
> >>> Fixes: a0e047156cde ("drm/i915/gem: Make context persistence optional")
> >>> Testcase: XXX
> >>> Signed-off-by: Chris Wilson
> >>> Cc: Tvrtko Ursulin
> >>> ---
> >>>drivers/gpu/drm/i915/gem/i915_gem_context.c | 7 +++
> >>>1 file changed, 7 insertions(+)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> >>> b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> >>> index 52a749691a8d..20f1d3e0221f 100644
> >>> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> >>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> >>> @@ -1624,11 +1624,18 @@ set_engines(struct i915_gem_context *ctx,
> >>>
> >>>replace:
> >>>mutex_lock(>engines_mutex);
> >>> +
> >>> + /* Flush stale requests off the old engines if required */
> >>> + if (!i915_gem_context_is_persistent(ctx) ||
> >>> + !i915_modparams.enable_hangcheck)
> >>> + kill_context(ctx);
> >>
> >> Is the negative effect of this is legit contexts can't keep submitting
> >> and changing the map? Only if PREEMPT_TIMEOUT is disabled I think but
> >> still. Might break legitimate userspace. Not that I offer solutions.. :(
> >> Banning changing engines once context went non-persistent? That too can
> >> break someone.
> >
> > It closes the hole we have. To do otherwise, we need to keep track of
> > the old engines. Not an impossible task, certainly inconvenient.
> >
> > struct old_engines {
> > struct i915_active active;
> > struct list_head link;
> > struct i915_gem_context *ctx;
> > void *engines;
> > int num_engines;
> > };
> >
> > With a list+spinlock in the ctx that we can work in kill_context.
> >
> > The biggest catch there is actually worrying about attaching the active
> > to already executing request, and making sure the coupling doesn't bug
> > on a concurrent completion. Hmm, it's just a completion callback, but
> > more convenient to use a ready made one.
>
> What would you do with old engines? We don't have a mechanism to mark
> intel_context closed. Hm, right, it would get unreachable by definition.
> But how to terminate it if it doesn't play nicely?
Wait 30 minutes (if it passes the tests) and you'll find out :)
-Chris
___
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[Intel-gfx] [PATCH v2 0/5] drm/i915: Hotplug cleanups
From: Ville Syrjälä Remainder of the earlier hotplug cleanups. This time without exposing functions between ddi and dp code, and instead we just duplicate a few of them. Ville Syrjälä (5): drm/i915/hpd: Replace the loop-within-loop with two independent loops drm/i915: Mark all HPD capabled connectors as such drm/i915: Turn intel_digital_port_connected() in a vfunc drm/i915: Stash hpd status bits under dev_priv drm/i915: Use stashed away hpd isr bits in intel_digital_port_connected() drivers/gpu/drm/i915/display/intel_crt.c | 1 + drivers/gpu/drm/i915/display/intel_ddi.c | 41 .../drm/i915/display/intel_display_types.h| 1 + drivers/gpu/drm/i915/display/intel_dp.c | 189 ++--- drivers/gpu/drm/i915/display/intel_hdmi.c | 1 + drivers/gpu/drm/i915/display/intel_hotplug.c | 52 ++--- drivers/gpu/drm/i915/display/intel_sdvo.c | 1 + drivers/gpu/drm/i915/display/intel_tc.c | 7 +- drivers/gpu/drm/i915/display/intel_tc.h | 3 +- drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/i915_irq.c | 198 ++ 11 files changed, 207 insertions(+), 289 deletions(-) -- 2.24.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 3/5] drm/i915: Turn intel_digital_port_connected() in a vfunc
From: Ville Syrjälä
Let's get rid of the platform if ladders in
intel_digital_port_connected() and make it a vfunc. Now the if
ladders are at the encoder initialization which makes them a bit
less convoluted.
v2: Add forward decl for intel_encoder in intel_tc.h
v3: Duplicate stuff to avoid exposing platform specific
functions across files (Jani)
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 109 +
.../drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 147 +++---
drivers/gpu/drm/i915/display/intel_tc.c | 3 +-
drivers/gpu/drm/i915/display/intel_tc.h | 3 +-
5 files changed, 135 insertions(+), 128 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 1ab638e17046..dff228e73f35 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4608,6 +4608,96 @@ intel_ddi_hotplug(struct intel_encoder *encoder,
return state;
}
+static bool lpt_digital_port_connected(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ u32 bit;
+
+ switch (encoder->hpd_pin) {
+ case HPD_PORT_B:
+ bit = SDE_PORTB_HOTPLUG_CPT;
+ break;
+ case HPD_PORT_C:
+ bit = SDE_PORTC_HOTPLUG_CPT;
+ break;
+ case HPD_PORT_D:
+ bit = SDE_PORTD_HOTPLUG_CPT;
+ break;
+ default:
+ MISSING_CASE(encoder->hpd_pin);
+ return false;
+ }
+
+ return intel_de_read(dev_priv, SDEISR) & bit;
+}
+
+static bool spt_digital_port_connected(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ u32 bit;
+
+ switch (encoder->hpd_pin) {
+ case HPD_PORT_A:
+ bit = SDE_PORTA_HOTPLUG_SPT;
+ break;
+ case HPD_PORT_E:
+ bit = SDE_PORTE_HOTPLUG_SPT;
+ break;
+ default:
+ return lpt_digital_port_connected(encoder);
+ }
+
+ return intel_de_read(dev_priv, SDEISR) & bit;
+}
+
+static bool hsw_digital_port_connected(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
+ return intel_de_read(dev_priv, DEISR) & DE_DP_A_HOTPLUG_IVB;
+}
+
+static bool bdw_digital_port_connected(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
+ return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) &
GEN8_PORT_DP_A_HOTPLUG;
+}
+
+static bool bxt_digital_port_connected(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ u32 bit;
+
+ switch (encoder->hpd_pin) {
+ case HPD_PORT_A:
+ bit = BXT_DE_PORT_HP_DDIA;
+ break;
+ case HPD_PORT_B:
+ bit = BXT_DE_PORT_HP_DDIB;
+ break;
+ case HPD_PORT_C:
+ bit = BXT_DE_PORT_HP_DDIC;
+ break;
+ default:
+ MISSING_CASE(encoder->hpd_pin);
+ return false;
+ }
+
+ return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit;
+}
+
+static bool icp_digital_port_connected(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+
+ if (HAS_PCH_MCC(dev_priv) && phy == PHY_C)
+ return intel_de_read(dev_priv, SDEISR) &
SDE_TC_HOTPLUG_ICP(PORT_TC1);
+
+ return intel_de_read(dev_priv, SDEISR) & SDE_DDI_HOTPLUG_ICP(phy);
+}
+
static struct intel_connector *
intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
{
@@ -4798,6 +4888,25 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
enum port port)
port_name(port));
}
+ if (INTEL_GEN(dev_priv) >= 11) {
+ if (intel_phy_is_tc(dev_priv, phy))
+ intel_dig_port->connected = intel_tc_port_connected;
+ else
+ intel_dig_port->connected = icp_digital_port_connected;
+ } else if (IS_GEN9_LP(dev_priv)) {
+ intel_dig_port->connected = bxt_digital_port_connected;
+ } else if (port == PORT_A) {
+ if (INTEL_GEN(dev_priv) >= 8)
+ intel_dig_port->connected = bdw_digital_port_connected;
+ else
+ intel_dig_port->connected = hsw_digital_port_connected;
+ } else {
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
+ intel_dig_port->connected = spt_digital_port_connected;
+ else
+ intel_dig_port->connected = lpt_digital_port_connected;
+ }
+
[Intel-gfx] [PATCH v2 2/5] drm/i915: Mark all HPD capabled connectors as such
From: Ville Syrjälä
Currently we only set the DRM_CONNECTOR_POLL_{DISCONNECT,CONNECT}
bits in intel_connector->polled (the base setting), leading to
some confusing looking code to reset drm_connector->polled
(the actual setting) to DRM_CONNECTOR_POLL_HPD. Let's set
intel_connector->polled = DRM_CONNECTOR_POLL_HPD for all hpd
capable connectors, and then we don't need so many special
cases in the hotplug code.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_crt.c | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 1 +
drivers/gpu/drm/i915/display/intel_hdmi.c| 1 +
drivers/gpu/drm/i915/display/intel_hotplug.c | 17 -
drivers/gpu/drm/i915/display/intel_sdvo.c| 1 +
5 files changed, 12 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c
b/drivers/gpu/drm/i915/display/intel_crt.c
index 0e2f63b0d458..ba0717d8c248 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -1033,6 +1033,7 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
!dmi_check_system(intel_spurious_crt_detect)) {
crt->base.hpd_pin = HPD_CRT;
crt->base.hotplug = intel_encoder_hotplug;
+ intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
} else {
intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
}
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index f4dede6253f8..4dfb26b2b2f7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -7576,6 +7576,7 @@ intel_dp_init_connector(struct intel_digital_port
*intel_dig_port,
connector->ycbcr_420_allowed = true;
intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
+ intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
intel_dp_aux_init(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index e68bafb76cb1..1a9a3b23cae4 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -3180,6 +3180,7 @@ void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port,
connector->ycbcr_420_allowed = true;
intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
+ intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
if (HAS_DDI(dev_priv))
intel_connector->get_hw_state =
intel_ddi_connector_get_hw_state;
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c
b/drivers/gpu/drm/i915/display/intel_hotplug.c
index 531021002e34..8af0ae61e1bb 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
@@ -262,8 +262,6 @@ static void intel_hpd_irq_storm_reenable_work(struct
work_struct *work)
DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
connector->base.name);
connector->base.polled = connector->polled;
- if (!connector->base.polled)
- connector->base.polled = DRM_CONNECTOR_POLL_HPD;
}
drm_connector_list_iter_end(_iter);
@@ -620,16 +618,17 @@ static void i915_hpd_poll_init_work(struct work_struct
*work)
drm_connector_list_iter_begin(dev, _iter);
for_each_intel_connector_iter(connector, _iter) {
- enum hpd_pin pin = intel_connector_hpd_pin(connector);
+ enum hpd_pin pin;
+
+ pin = intel_connector_hpd_pin(connector);
+ if (pin == HPD_NONE)
+ continue;
connector->base.polled = connector->polled;
- if (pin != HPD_NONE && I915_HAS_HOTPLUG(dev_priv) &&
- !connector->base.polled)
- connector->base.polled = enabled ?
- DRM_CONNECTOR_POLL_CONNECT |
- DRM_CONNECTOR_POLL_DISCONNECT :
- DRM_CONNECTOR_POLL_HPD;
+ if (enabled && connector->base.polled == DRM_CONNECTOR_POLL_HPD)
+ connector->base.polled = DRM_CONNECTOR_POLL_CONNECT |
+ DRM_CONNECTOR_POLL_DISCONNECT;
}
drm_connector_list_iter_end(_iter);
diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c
b/drivers/gpu/drm/i915/display/intel_sdvo.c
index a4921b549f8b..b0588150752c 100644
--- a/drivers/gpu/drm/i915/display/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
@@ -2721,6 +2721,7 @@ intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int
device)
* Some SDVO devices have one-shot hotplug interrupts.
* Ensure that they get re-enabled when an interrupt happens.
*/
+ intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
[Intel-gfx] [PATCH v2 5/5] drm/i915: Use stashed away hpd isr bits in intel_digital_port_connected()
From: Ville Syrjälä
Get rid of several platform specific variants of
intel_digital_port_connected() and just use the ISR bits we've
stashed away.
v2: Duplicate stuff to avoid exposing platform specific
functions across files (Jani)
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 88 +++-
drivers/gpu/drm/i915/display/intel_dp.c | 59 ++--
drivers/gpu/drm/i915/display/intel_tc.c | 4 +-
3 files changed, 17 insertions(+), 134 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index dff228e73f35..4555707df565 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4611,41 +4611,7 @@ intel_ddi_hotplug(struct intel_encoder *encoder,
static bool lpt_digital_port_connected(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- u32 bit;
-
- switch (encoder->hpd_pin) {
- case HPD_PORT_B:
- bit = SDE_PORTB_HOTPLUG_CPT;
- break;
- case HPD_PORT_C:
- bit = SDE_PORTC_HOTPLUG_CPT;
- break;
- case HPD_PORT_D:
- bit = SDE_PORTD_HOTPLUG_CPT;
- break;
- default:
- MISSING_CASE(encoder->hpd_pin);
- return false;
- }
-
- return intel_de_read(dev_priv, SDEISR) & bit;
-}
-
-static bool spt_digital_port_connected(struct intel_encoder *encoder)
-{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- u32 bit;
-
- switch (encoder->hpd_pin) {
- case HPD_PORT_A:
- bit = SDE_PORTA_HOTPLUG_SPT;
- break;
- case HPD_PORT_E:
- bit = SDE_PORTE_HOTPLUG_SPT;
- break;
- default:
- return lpt_digital_port_connected(encoder);
- }
+ u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin];
return intel_de_read(dev_priv, SDEISR) & bit;
}
@@ -4653,51 +4619,19 @@ static bool spt_digital_port_connected(struct
intel_encoder *encoder)
static bool hsw_digital_port_connected(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
- return intel_de_read(dev_priv, DEISR) & DE_DP_A_HOTPLUG_IVB;
+ return intel_de_read(dev_priv, DEISR) & bit;
}
static bool bdw_digital_port_connected(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-
- return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) &
GEN8_PORT_DP_A_HOTPLUG;
-}
-
-static bool bxt_digital_port_connected(struct intel_encoder *encoder)
-{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- u32 bit;
-
- switch (encoder->hpd_pin) {
- case HPD_PORT_A:
- bit = BXT_DE_PORT_HP_DDIA;
- break;
- case HPD_PORT_B:
- bit = BXT_DE_PORT_HP_DDIB;
- break;
- case HPD_PORT_C:
- bit = BXT_DE_PORT_HP_DDIC;
- break;
- default:
- MISSING_CASE(encoder->hpd_pin);
- return false;
- }
+ u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit;
}
-static bool icp_digital_port_connected(struct intel_encoder *encoder)
-{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
-
- if (HAS_PCH_MCC(dev_priv) && phy == PHY_C)
- return intel_de_read(dev_priv, SDEISR) &
SDE_TC_HOTPLUG_ICP(PORT_TC1);
-
- return intel_de_read(dev_priv, SDEISR) & SDE_DDI_HOTPLUG_ICP(phy);
-}
-
static struct intel_connector *
intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
{
@@ -4892,17 +4826,15 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
enum port port)
if (intel_phy_is_tc(dev_priv, phy))
intel_dig_port->connected = intel_tc_port_connected;
else
- intel_dig_port->connected = icp_digital_port_connected;
- } else if (IS_GEN9_LP(dev_priv)) {
- intel_dig_port->connected = bxt_digital_port_connected;
- } else if (port == PORT_A) {
- if (INTEL_GEN(dev_priv) >= 8)
+ intel_dig_port->connected = lpt_digital_port_connected;
+ } else if (INTEL_GEN(dev_priv) >= 8) {
+ if (port == PORT_A || IS_GEN9_LP(dev_priv))
intel_dig_port->connected = bdw_digital_port_connected;
else
- intel_dig_port->connected = hsw_digital_port_connected;
+ intel_dig_port->connected = lpt_digital_port_connected;
} else {
- if
[Intel-gfx] [PATCH v2 1/5] drm/i915/hpd: Replace the loop-within-loop with two independent loops
From: Ville Syrjälä
No point in looping over all connectors for each hpd pin. Just loop
over each connector first and deal with each one's hpd pin. Then
loop over all the hpd pins to mark them as enabled again.
Also get rid of the MST special case as MST encoders simply don't
have a HPD pin and will get naturally fitered out.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_hotplug.c | 39 +++-
1 file changed, 21 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c
b/drivers/gpu/drm/i915/display/intel_hotplug.c
index 127a2f28c1ac..531021002e34 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
@@ -242,36 +242,39 @@ static void intel_hpd_irq_storm_reenable_work(struct
work_struct *work)
container_of(work, typeof(*dev_priv),
hotplug.reenable_work.work);
struct drm_device *dev = _priv->drm;
+ struct drm_connector_list_iter conn_iter;
+ struct intel_connector *connector;
intel_wakeref_t wakeref;
enum hpd_pin pin;
wakeref = intel_runtime_pm_get(_priv->runtime_pm);
spin_lock_irq(_priv->irq_lock);
- for_each_hpd_pin(pin) {
- struct drm_connector_list_iter conn_iter;
- struct intel_connector *connector;
- if (dev_priv->hotplug.stats[pin].state != HPD_DISABLED)
+ drm_connector_list_iter_begin(dev, _iter);
+ for_each_intel_connector_iter(connector, _iter) {
+ pin = intel_connector_hpd_pin(connector);
+ if (pin == HPD_NONE ||
+ dev_priv->hotplug.stats[pin].state != HPD_DISABLED)
continue;
- dev_priv->hotplug.stats[pin].state = HPD_ENABLED;
-
- drm_connector_list_iter_begin(dev, _iter);
- for_each_intel_connector_iter(connector, _iter) {
- if (intel_connector_hpd_pin(connector) == pin) {
- if (connector->base.polled != connector->polled)
- DRM_DEBUG_DRIVER("Reenabling HPD on
connector %s\n",
-connector->base.name);
- connector->base.polled = connector->polled;
- if (!connector->base.polled)
- connector->base.polled =
DRM_CONNECTOR_POLL_HPD;
- }
- }
- drm_connector_list_iter_end(_iter);
+ if (connector->base.polled != connector->polled)
+ DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
+connector->base.name);
+ connector->base.polled = connector->polled;
+ if (!connector->base.polled)
+ connector->base.polled = DRM_CONNECTOR_POLL_HPD;
+ }
+ drm_connector_list_iter_end(_iter);
+
+ for_each_hpd_pin(pin) {
+ if (dev_priv->hotplug.stats[pin].state == HPD_DISABLED)
+ dev_priv->hotplug.stats[pin].state = HPD_ENABLED;
}
+
if (dev_priv->display_irqs_enabled && dev_priv->display.hpd_irq_setup)
dev_priv->display.hpd_irq_setup(dev_priv);
+
spin_unlock_irq(_priv->irq_lock);
intel_runtime_pm_put(_priv->runtime_pm, wakeref);
--
2.24.1
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[Intel-gfx] [PATCH v2 4/5] drm/i915: Stash hpd status bits under dev_priv
From: Ville Syrjälä
Instead of constnantly having to figure out which hpd status bit
array to use let's store them under dev_priv.
Should perhaps take this further and stash even more stuff to
make the hpd handling more abstract yet.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_irq.c | 198 ++--
2 files changed, 111 insertions(+), 89 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3452926d7b77..6dd98e3af1f3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -145,6 +145,8 @@ enum hpd_pin {
struct i915_hotplug {
struct delayed_work hotplug_work;
+ const u32 *hpd, *pch_hpd;
+
struct {
unsigned long last_jiffies;
int count;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 3d0cd0960bd2..76cc85f370a3 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -125,7 +125,6 @@ static const u32 hpd_status_i915[HPD_NUM_PINS] = {
[HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS,
};
-/* BXT hpd list */
static const u32 hpd_bxt[HPD_NUM_PINS] = {
[HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
[HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
@@ -169,6 +168,44 @@ static const u32 hpd_tgp[HPD_NUM_PINS] = {
[HPD_PORT_I] = SDE_TC_HOTPLUG_ICP(PORT_TC6),
};
+static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
+{
+ struct i915_hotplug *hpd = _priv->hotplug;
+
+ if (HAS_GMCH(dev_priv)) {
+ if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
+ IS_CHERRYVIEW(dev_priv))
+ hpd->hpd = hpd_status_g4x;
+ else
+ hpd->hpd = hpd_status_i915;
+ return;
+ }
+
+ if (INTEL_GEN(dev_priv) >= 12)
+ hpd->hpd = hpd_gen12;
+ else if (INTEL_GEN(dev_priv) >= 11)
+ hpd->hpd = hpd_gen11;
+ else if (IS_GEN9_LP(dev_priv))
+ hpd->hpd = hpd_bxt;
+ else if (INTEL_GEN(dev_priv) >= 8)
+ hpd->hpd = hpd_bdw;
+ else if (INTEL_GEN(dev_priv) >= 7)
+ hpd->hpd = hpd_ivb;
+ else
+ hpd->hpd = hpd_ilk;
+
+ if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv))
+ hpd->pch_hpd = hpd_tgp;
+ else if (HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
+ hpd->pch_hpd = hpd_icp;
+ else if (HAS_PCH_SPT(dev_priv))
+ hpd->pch_hpd = hpd_spt;
+ else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_CPT(dev_priv))
+ hpd->pch_hpd = hpd_cpt;
+ else if (HAS_PCH_IBX(dev_priv))
+ hpd->pch_hpd = hpd_ibx;
+}
+
void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
i915_reg_t iir, i915_reg_t ier)
{
@@ -1487,33 +1524,27 @@ static void i9xx_hpd_irq_handler(struct
drm_i915_private *dev_priv,
u32 hotplug_status)
{
u32 pin_mask = 0, long_mask = 0;
+ u32 hotplug_trigger;
- if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
- IS_CHERRYVIEW(dev_priv)) {
- u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
-
- if (hotplug_trigger) {
- intel_get_hpd_pins(dev_priv, _mask, _mask,
- hotplug_trigger, hotplug_trigger,
- hpd_status_g4x,
- i9xx_port_hotplug_long_detect);
+ if (IS_G4X(dev_priv) ||
+ IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+ hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
+ else
+ hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
- intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
- }
+ if (hotplug_trigger) {
+ intel_get_hpd_pins(dev_priv, _mask, _mask,
+ hotplug_trigger, hotplug_trigger,
+ dev_priv->hotplug.hpd,
+ i9xx_port_hotplug_long_detect);
- if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
- dp_aux_irq_handler(dev_priv);
- } else {
- u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
-
- if (hotplug_trigger) {
- intel_get_hpd_pins(dev_priv, _mask, _mask,
- hotplug_trigger, hotplug_trigger,
- hpd_status_i915,
- i9xx_port_hotplug_long_detect);
- intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
- }
+ intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
Re: [Intel-gfx] [PATCH v2] drm/i915/gem: Don't leak non-persistent requests on changing engines
On 05/02/2020 16:44, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2020-02-05 16:22:34)
On 05/02/2020 12:13, Chris Wilson wrote:
If we have a set of active engines marked as being non-persistent, we
lose track of those if the user replaces those engines with
I915_CONTEXT_PARAM_ENGINES. As part of our uABI contract is that
non-persistent requests are terminated if they are no longer being
tracked by the user's context (in order to prevent a lost request
causing an untracked and so unstoppable GPU hang), we need to apply the
same context cancellation upon changing engines.
Fixes: a0e047156cde ("drm/i915/gem: Make context persistence optional")
Testcase: XXX
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 52a749691a8d..20f1d3e0221f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1624,11 +1624,18 @@ set_engines(struct i915_gem_context *ctx,
replace:
mutex_lock(>engines_mutex);
+
+ /* Flush stale requests off the old engines if required */
+ if (!i915_gem_context_is_persistent(ctx) ||
+ !i915_modparams.enable_hangcheck)
+ kill_context(ctx);
Is the negative effect of this is legit contexts can't keep submitting
and changing the map? Only if PREEMPT_TIMEOUT is disabled I think but
still. Might break legitimate userspace. Not that I offer solutions.. :(
Banning changing engines once context went non-persistent? That too can
break someone.
It closes the hole we have. To do otherwise, we need to keep track of
the old engines. Not an impossible task, certainly inconvenient.
struct old_engines {
struct i915_active active;
struct list_head link;
struct i915_gem_context *ctx;
void *engines;
int num_engines;
};
With a list+spinlock in the ctx that we can work in kill_context.
The biggest catch there is actually worrying about attaching the active
to already executing request, and making sure the coupling doesn't bug
on a concurrent completion. Hmm, it's just a completion callback, but
more convenient to use a ready made one.
What would you do with old engines? We don't have a mechanism to mark
intel_context closed. Hm, right, it would get unreachable by definition.
But how to terminate it if it doesn't play nicely?
Regards,
Tvrtko
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Mark i915.reset as unsigned
== Series Details == Series: drm/i915: Mark i915.reset as unsigned URL : https://patchwork.freedesktop.org/series/73024/ State : success == Summary == CI Bug Log - changes from CI_DRM_7869 -> Patchwork_16435 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16435/index.html Known issues Here are the changes found in Patchwork_16435 that come from known issues: ### IGT changes ### Issues hit * igt@gem_close_race@basic-threads: - fi-byt-j1900: [PASS][1] -> [INCOMPLETE][2] ([i915#45]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-byt-j1900/igt@gem_close_r...@basic-threads.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16435/fi-byt-j1900/igt@gem_close_r...@basic-threads.html * igt@i915_selftest@live_blt: - fi-hsw-4770r: [PASS][3] -> [DMESG-FAIL][4] ([i915#553] / [i915#725]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-hsw-4770r/igt@i915_selftest@live_blt.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16435/fi-hsw-4770r/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_gt_heartbeat: - fi-bsw-kefka: [PASS][5] -> [DMESG-FAIL][6] ([i915#541]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-bsw-kefka/igt@i915_selftest@live_gt_heartbeat.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16435/fi-bsw-kefka/igt@i915_selftest@live_gt_heartbeat.html * igt@kms_addfb_basic@bad-pitch-63: - fi-tgl-y: [PASS][7] -> [DMESG-WARN][8] ([CI#94] / [i915#402]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-tgl-y/igt@kms_addfb_ba...@bad-pitch-63.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16435/fi-tgl-y/igt@kms_addfb_ba...@bad-pitch-63.html * igt@kms_frontbuffer_tracking@basic: - fi-hsw-peppy: [PASS][9] -> [DMESG-WARN][10] ([i915#44]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16435/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html Possible fixes * igt@gem_close_race@basic-threads: - fi-byt-n2820: [INCOMPLETE][11] ([i915#45]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-byt-n2820/igt@gem_close_r...@basic-threads.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16435/fi-byt-n2820/igt@gem_close_r...@basic-threads.html * igt@gem_exec_parallel@fds: - fi-icl-u3: [INCOMPLETE][13] -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-icl-u3/igt@gem_exec_paral...@fds.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16435/fi-icl-u3/igt@gem_exec_paral...@fds.html * igt@i915_getparams_basic@basic-subslice-total: - fi-tgl-y: [DMESG-WARN][15] ([CI#94] / [i915#402]) -> [PASS][16] +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16435/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html * igt@kms_chamelium@hdmi-crc-fast: - fi-kbl-7500u: [FAIL][17] ([fdo#109635] / [i915#217]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16435/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][19] ([fdo#111096] / [i915#323]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16435/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94 [fdo#109635]: https://bugs.freedesktop.org/show_bug.cgi?id=109635 [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 [i915#217]: https://gitlab.freedesktop.org/drm/intel/issues/217 [i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#44]: https://gitlab.freedesktop.org/drm/intel/issues/44 [i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45 [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541 [i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 Participating hosts (49 -> 41) -- Additional (2): fi-gdg-551 fi-snb-2520m Missing(10): fi-hsw-4200u fi-skl-6770hq fi-glk-dsi fi-bsw-cyan fi-ctg-p8600 fi-hsw-4770 fi-byt-clapper
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/6] drm/i915: Hold reference to previous active fence as we queue
== Series Details == Series: series starting with [1/6] drm/i915: Hold reference to previous active fence as we queue URL : https://patchwork.freedesktop.org/series/72906/ State : success == Summary == CI Bug Log - changes from CI_DRM_7857_full -> Patchwork_16390_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_16390_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_busy@busy-vcs1: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#112080]) +3 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb4/igt@gem_b...@busy-vcs1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16390/shard-iclb3/igt@gem_b...@busy-vcs1.html * igt@gem_exec_schedule@preempt-queue-chain-bsd2: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276]) +7 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb4/igt@gem_exec_sched...@preempt-queue-chain-bsd2.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16390/shard-iclb3/igt@gem_exec_sched...@preempt-queue-chain-bsd2.html * igt@gem_exec_schedule@preempt-queue-contexts-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#112146]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb8/igt@gem_exec_sched...@preempt-queue-contexts-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16390/shard-iclb1/igt@gem_exec_sched...@preempt-queue-contexts-bsd.html * igt@gem_ppgtt@flink-and-close-vma-leak: - shard-tglb: [PASS][7] -> [FAIL][8] ([i915#644]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-tglb7/igt@gem_pp...@flink-and-close-vma-leak.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16390/shard-tglb8/igt@gem_pp...@flink-and-close-vma-leak.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#180]) +4 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-apl7/igt@kms_cursor_...@pipe-c-cursor-suspend.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16390/shard-apl4/igt@kms_cursor_...@pipe-c-cursor-suspend.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic: - shard-glk: [PASS][11] -> [FAIL][12] ([i915#72]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-glk9/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-atomic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16390/shard-glk2/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-atomic.html * igt@kms_draw_crc@draw-method-xrgb-blt-ytiled: - shard-skl: [PASS][13] -> [FAIL][14] ([i915#52] / [i915#54]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl2/igt@kms_draw_...@draw-method-xrgb-blt-ytiled.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16390/shard-skl5/igt@kms_draw_...@draw-method-xrgb-blt-ytiled.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc: - shard-glk: [PASS][15] -> [FAIL][16] ([i915#49]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-glk8/igt@kms_frontbuffer_track...@fbc-1p-primscrn-spr-indfb-draw-mmap-wc.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16390/shard-glk1/igt@kms_frontbuffer_track...@fbc-1p-primscrn-spr-indfb-draw-mmap-wc.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#49]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl2/igt@kms_frontbuffer_track...@psr-1p-primscrn-shrfb-plflip-blt.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16390/shard-skl5/igt@kms_frontbuffer_track...@psr-1p-primscrn-shrfb-plflip-blt.html * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl2/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16390/shard-skl5/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145] / [i915#265]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl7/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16390/shard-skl1/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html * igt@kms_psr@psr2_no_drrs: - shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) +3 similar issues [23]:
[Intel-gfx] [PATCH v6 7/7] drm/i915/display/hdcp: Make WARN* drm specific where drm_priv ptr is available
drm specific WARN* calls include device information in the
backtrace, so we know what device the warnings originate from.
Covert all the calls of WARN* with device specific drm_WARN*
variants in functions where drm_i915_private struct pointer is readily
available.
The conversion was done automatically with below coccinelle semantic
patch. checkpatch errors/warnings are fixed manually.
@rule1@
identifier func, T;
@@
func(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-WARN(
+drm_WARN(>drm,
...)
|
-WARN_ON(
+drm_WARN_ON(>drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(>drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(>drm,
...)
)
...+>
}
@rule2@
identifier func, T;
@@
func(struct drm_i915_private *T,...) {
<+...
(
-WARN(
+drm_WARN(>drm,
...)
|
-WARN_ON(
+drm_WARN_ON(>drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(>drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(>drm,
...)
)
...+>
}
Signed-off-by: Pankaj Bharadiya
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 20
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 4d1a33d13105..b30859c79924 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -872,7 +872,8 @@ static int intel_hdcp_check_link(struct intel_connector
*connector)
goto out;
}
- if (WARN_ON(!intel_hdcp_in_use(dev_priv, cpu_transcoder, port))) {
+ if (drm_WARN_ON(_priv->drm,
+ !intel_hdcp_in_use(dev_priv, cpu_transcoder, port))) {
drm_err(_priv->drm,
"%s:%d HDCP link stopped encryption,%x\n",
connector->base.name, connector->base.base.id,
@@ -1561,8 +1562,9 @@ static int hdcp2_enable_encryption(struct intel_connector
*connector)
enum transcoder cpu_transcoder = hdcp->cpu_transcoder;
int ret;
- WARN_ON(intel_de_read(dev_priv, HDCP2_STATUS(dev_priv, cpu_transcoder,
port)) &
- LINK_ENCRYPTION_STATUS);
+ drm_WARN_ON(_priv->drm,
+ intel_de_read(dev_priv, HDCP2_STATUS(dev_priv,
cpu_transcoder, port)) &
+ LINK_ENCRYPTION_STATUS);
if (hdcp->shim->toggle_signalling) {
ret = hdcp->shim->toggle_signalling(intel_dig_port, true);
if (ret) {
@@ -1599,8 +1601,8 @@ static int hdcp2_disable_encryption(struct
intel_connector *connector)
enum transcoder cpu_transcoder = hdcp->cpu_transcoder;
int ret;
- WARN_ON(!(intel_de_read(dev_priv, HDCP2_STATUS(dev_priv,
cpu_transcoder, port)) &
- LINK_ENCRYPTION_STATUS));
+ drm_WARN_ON(_priv->drm, !(intel_de_read(dev_priv,
HDCP2_STATUS(dev_priv, cpu_transcoder, port)) &
+ LINK_ENCRYPTION_STATUS));
intel_de_write(dev_priv, HDCP2_CTL(dev_priv, cpu_transcoder, port),
intel_de_read(dev_priv, HDCP2_CTL(dev_priv,
cpu_transcoder, port)) & ~CTL_LINK_ENCRYPTION_REQ);
@@ -1720,7 +1722,8 @@ static int intel_hdcp2_check_link(struct intel_connector
*connector)
goto out;
}
- if (WARN_ON(!intel_hdcp2_in_use(dev_priv, cpu_transcoder, port))) {
+ if (drm_WARN_ON(_priv->drm,
+ !intel_hdcp2_in_use(dev_priv, cpu_transcoder, port))) {
drm_err(_priv->drm,
"HDCP2.2 link stopped the encryption, %x\n",
intel_de_read(dev_priv, HDCP2_STATUS(dev_priv,
cpu_transcoder, port)));
@@ -1916,7 +1919,7 @@ void intel_hdcp_component_init(struct drm_i915_private
*dev_priv)
return;
mutex_lock(_priv->hdcp_comp_mutex);
- WARN_ON(dev_priv->hdcp_comp_added);
+ drm_WARN_ON(_priv->drm, dev_priv->hdcp_comp_added);
dev_priv->hdcp_comp_added = true;
mutex_unlock(_priv->hdcp_comp_mutex);
@@ -1990,7 +1993,8 @@ int intel_hdcp_enable(struct intel_connector *connector,
return -ENOENT;
mutex_lock(>mutex);
- WARN_ON(hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED);
+ drm_WARN_ON(_priv->drm,
+ hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED);
hdcp->content_type = content_type;
if (INTEL_GEN(dev_priv) >= 12) {
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 1/7] drm/i915/display/cdclk: Make WARN* drm specific where drm_priv ptr is available
drm specific WARN* calls include device information in the
backtrace, so we know what device the warnings originate from.
Covert all the calls of WARN* with device specific drm_WARN*
variants in functions where drm_i915_private struct pointer is readily
available.
The conversion was done automatically with below coccinelle semantic
patch. checkpatch errors/warnings are fixed manually.
@rule1@
identifier func, T;
@@
func(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-WARN(
+drm_WARN(>drm,
...)
|
-WARN_ON(
+drm_WARN_ON(>drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(>drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(>drm,
...)
)
...+>
}
@rule2@
identifier func, T;
@@
func(struct drm_i915_private *T,...) {
<+...
(
-WARN(
+drm_WARN(>drm,
...)
|
-WARN_ON(
+drm_WARN_ON(>drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(>drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(>drm,
...)
)
...+>
}
Signed-off-by: Pankaj Bharadiya
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 85 +-
1 file changed, 49 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 7154a2288310..9c97d230720a 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -525,7 +525,8 @@ static void vlv_program_pfi_credits(struct drm_i915_private
*dev_priv)
* FIXME is this guaranteed to clear
* immediately or should we poll for it?
*/
- WARN_ON(intel_de_read(dev_priv, GCI_CONTROL) & PFI_CREDIT_RESEND);
+ drm_WARN_ON(_priv->drm,
+ intel_de_read(dev_priv, GCI_CONTROL) & PFI_CREDIT_RESEND);
}
static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
@@ -727,12 +728,14 @@ static void bdw_set_cdclk(struct drm_i915_private
*dev_priv,
u32 val;
int ret;
- if (WARN((intel_de_read(dev_priv, LCPLL_CTL) &
- (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
- LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
- LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
- LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
-"trying to change cdclk frequency with cdclk not enabled\n"))
+ if (drm_WARN(_priv->drm, (intel_de_read(dev_priv, LCPLL_CTL) &
+ (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
+ LCPLL_CD_CLOCK_DISABLE |
+ LCPLL_ROOT_CD_CLOCK_DISABLE |
+ LCPLL_CD2X_CLOCK_DISABLE |
+ LCPLL_POWER_DOWN_ALLOW |
+ LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
+"trying to change cdclk frequency with cdclk not
enabled\n"))
return;
ret = sandybridge_pcode_write(dev_priv,
@@ -842,15 +845,16 @@ static void skl_dpll0_update(struct drm_i915_private
*dev_priv,
if ((val & LCPLL_PLL_ENABLE) == 0)
return;
- if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
+ if (drm_WARN_ON(_priv->drm, (val & LCPLL_PLL_LOCK) == 0))
return;
val = intel_de_read(dev_priv, DPLL_CTRL1);
- if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
- DPLL_CTRL1_SSC(SKL_DPLL0) |
- DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
- DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
+ if (drm_WARN_ON(_priv->drm,
+ (val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
+ DPLL_CTRL1_SSC(SKL_DPLL0) |
+ DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
+ DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
return;
switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
@@ -952,7 +956,7 @@ static void skl_dpll0_enable(struct drm_i915_private
*dev_priv, int vco)
{
u32 val;
- WARN_ON(vco != 810 && vco != 864);
+ drm_WARN_ON(_priv->drm, vco != 810 && vco != 864);
/*
* We always enable DPLL0 with the lowest link rate possible, but still
@@ -1017,7 +1021,8 @@ static void skl_set_cdclk(struct drm_i915_private
*dev_priv,
* use the corresponding VCO freq as that always leads to using the
* minimum 308MHz CDCLK.
*/
- WARN_ON_ONCE(IS_SKYLAKE(dev_priv) && vco == 864);
+ drm_WARN_ON_ONCE(_priv->drm,
+IS_SKYLAKE(dev_priv) && vco == 864);
ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
SKL_CDCLK_PREPARE_FOR_CHANGE,
@@ -1032,8 +1037,9 @@ static void skl_set_cdclk(struct drm_i915_private
*dev_priv,
/* Choose frequency for this cdclk */
switch (cdclk) {
default:
- WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
- WARN_ON(vco != 0);
+ drm_WARN_ON(_priv->drm,
+
[Intel-gfx] [PATCH v6 6/7] drm/i915/display/global_state: Make WARN* drm specific where drm_device ptr is available
drm specific WARN* calls include device information in the
backtrace, so we know what device the warnings originate from.
Covert all the calls of WARN* with device specific drm_WARN*
variants in functions where drm_device or drm_i915_private struct
pointer is readily available.
The conversion was done automatically with below coccinelle semantic
patch.
@rule1@
identifier func, T;
@@
func(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-WARN(
+drm_WARN(>drm,
...)
|
-WARN_ON(
+drm_WARN_ON(>drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(>drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(>drm,
...)
)
...+>
}
@rule2@
identifier func, T;
@@
func(struct drm_i915_private *T,...) {
<+...
(
-WARN(
+drm_WARN(>drm,
...)
|
-WARN_ON(
+drm_WARN_ON(>drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(>drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(>drm,
...)
)
...+>
}
Signed-off-by: Pankaj Bharadiya
---
drivers/gpu/drm/i915/display/intel_global_state.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_global_state.c
b/drivers/gpu/drm/i915/display/intel_global_state.c
index a0cc894c3868..ede39c2f2e1d 100644
--- a/drivers/gpu/drm/i915/display/intel_global_state.c
+++ b/drivers/gpu/drm/i915/display/intel_global_state.c
@@ -64,7 +64,7 @@ static void assert_global_state_read_locked(struct
intel_atomic_state *state)
return;
}
- WARN(1, "Global state not read locked\n");
+ drm_WARN(_priv->drm, 1, "Global state not read locked\n");
}
struct intel_global_state *
@@ -147,7 +147,7 @@ void intel_atomic_swap_global_state(struct
intel_atomic_state *state)
for_each_oldnew_global_obj_in_state(state, obj, old_obj_state,
new_obj_state, i) {
- WARN_ON(obj->state != old_obj_state);
+ drm_WARN_ON(_priv->drm, obj->state != old_obj_state);
/*
* If the new state wasn't modified (and properly
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 2/7] drm/i915/display/ddi: Make WARN* drm specific where drm_device ptr is available
drm specific WARN* calls include device information in the
backtrace, so we know what device the warnings originate from.
Covert all the calls of WARN* with device specific drm_WARN*
variants in functions where drm_device or drm_i915_private struct
pointer is readily available.
The conversion was done automatically with below coccinelle semantic
patch. checkpatch errors/warnings are fixed manually.
@rule1@
identifier func, T;
@@
func(...) {
...
struct drm_device *T = ...;
<...
(
-WARN(
+drm_WARN(T,
...)
|
-WARN_ON(
+drm_WARN_ON(T,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(T,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(T,
...)
)
...>
}
@rule2@
identifier func, T;
@@
func(struct drm_device *T,...) {
<...
(
-WARN(
+drm_WARN(T,
...)
|
-WARN_ON(
+drm_WARN_ON(T,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(T,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(T,
...)
)
...>
}
@rule3@
identifier func, T;
@@
func(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-WARN(
+drm_WARN(>drm,
...)
|
-WARN_ON(
+drm_WARN_ON(>drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(>drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(>drm,
...)
)
...+>
}
@rule4@
identifier func, T;
@@
func(struct drm_i915_private *T,...) {
<+...
(
-WARN(
+drm_WARN(>drm,
...)
|
-WARN_ON(
+drm_WARN_ON(>drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(>drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(>drm,
...)
)
...+>
}
Signed-off-by: Pankaj Bharadiya
---
drivers/gpu/drm/i915/display/intel_ddi.c | 92 +---
1 file changed, 51 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 1ab638e17046..9ffcee8523b6 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -980,18 +980,18 @@ static int intel_ddi_hdmi_level(struct intel_encoder
*encoder)
intel_ddi_get_buf_trans_hdmi(dev_priv, _entries);
default_entry = 6;
} else {
- WARN(1, "ddi translation table missing\n");
+ drm_WARN(_priv->drm, 1, "ddi translation table missing\n");
return 0;
}
- if (WARN_ON_ONCE(n_entries == 0))
+ if (drm_WARN_ON_ONCE(_priv->drm, n_entries == 0))
return 0;
level = intel_bios_hdmi_level_shift(encoder);
if (level < 0)
level = default_entry;
- if (WARN_ON_ONCE(level >= n_entries))
+ if (drm_WARN_ON_ONCE(_priv->drm, level >= n_entries))
level = n_entries - 1;
return level;
@@ -1049,9 +1049,9 @@ static void intel_prepare_hdmi_ddi_buffers(struct
intel_encoder *encoder,
ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, _entries);
- if (WARN_ON_ONCE(!ddi_translations))
+ if (drm_WARN_ON_ONCE(_priv->drm, !ddi_translations))
return;
- if (WARN_ON_ONCE(level >= n_entries))
+ if (drm_WARN_ON_ONCE(_priv->drm, level >= n_entries))
level = n_entries - 1;
/* If we're boosting the current, set bit 31 of trans1 */
@@ -1182,7 +1182,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
/* Configure Port Clock Select */
ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
intel_de_write(dev_priv, PORT_CLK_SEL(PORT_E), ddi_pll_sel);
- WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
+ drm_WARN_ON(_priv->drm, ddi_pll_sel != PORT_CLK_SEL_SPLL);
/* Start the training iterating through available voltages and emphasis,
* testing each value twice. */
@@ -1291,8 +1291,9 @@ intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
}
if (num_encoders != 1)
- WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
-pipe_name(crtc->pipe));
+ drm_WARN(dev, 1, "%d encoders on crtc for pipe %c\n",
+num_encoders,
+pipe_name(crtc->pipe));
BUG_ON(ret == NULL);
return ret;
@@ -1450,7 +1451,7 @@ int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
- if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
+ if (drm_WARN_ON(_priv->drm, p0 == 0 || p1 == 0 || p2 == 0))
return 0;
return dco_freq / (p0 * p1 * p2 * 5);
@@ -1638,7 +1639,7 @@ static void cnl_ddi_clock_get(struct intel_encoder
*encoder,
link_clock = 405000;
break;
default:
- WARN(1, "Unsupported link rate\n");
+ drm_WARN(_priv->drm, 1, "Unsupported link rate\n");
break;
}
link_clock *= 2;
@@ -1730,12 +1731,12 @@ static void hsw_ddi_clock_get(struct intel_encoder
*encoder,
else if (pll == SPLL_FREQ_2700MHz)
[Intel-gfx] [PATCH v6 5/7] drm/i915/display/dp: Make WARN* drm specific where drm_device ptr is available
drm specific WARN* calls include device information in the
backtrace, so we know what device the warnings originate from.
Covert all the calls of WARN* with device specific drm_WARN*
variants in functions where drm_device or drm_i915_private struct
pointer is readily available.
The conversion was done automatically with below coccinelle semantic
patch. checkpatch errors/warnings are fixed manually.
@rule1@
identifier func, T;
@@
func(...) {
...
struct drm_device *T = ...;
<...
(
-WARN(
+drm_WARN(T,
...)
|
-WARN_ON(
+drm_WARN_ON(T,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(T,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(T,
...)
)
...>
}
@rule2@
identifier func, T;
@@
func(struct drm_device *T,...) {
<...
(
-WARN(
+drm_WARN(T,
...)
|
-WARN_ON(
+drm_WARN_ON(T,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(T,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(T,
...)
)
...>
}
@rule3@
identifier func, T;
@@
func(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-WARN(
+drm_WARN(>drm,
...)
|
-WARN_ON(
+drm_WARN_ON(>drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(>drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(>drm,
...)
)
...+>
}
@rule4@
identifier func, T;
@@
func(struct drm_i915_private *T,...) {
<+...
(
-WARN(
+drm_WARN(>drm,
...)
|
-WARN_ON(
+drm_WARN_ON(>drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(>drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(>drm,
...)
)
...+>
}
Signed-off-by: Pankaj Bharadiya
---
drivers/gpu/drm/i915/display/intel_dp.c | 118 ++--
1 file changed, 67 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index f4dede6253f8..a276e06c31b5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -324,7 +324,8 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
int size, max_rate = 0, vbt_max_rate;
/* This should only be done once */
- WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
+ drm_WARN_ON(_priv->drm,
+ intel_dp->source_rates || intel_dp->num_source_rates);
if (INTEL_GEN(dev_priv) >= 10) {
source_rates = cnl_rates;
@@ -756,10 +757,11 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp)
enum dpio_channel ch = vlv_pipe_to_channel(pipe);
u32 DP;
- if (WARN(intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN,
-"skipping pipe %c power sequencer kick due to [ENCODER:%d:%s]
being active\n",
-pipe_name(pipe), intel_dig_port->base.base.base.id,
-intel_dig_port->base.base.name))
+ if (drm_WARN(_priv->drm,
+intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN,
+"skipping pipe %c power sequencer kick due to
[ENCODER:%d:%s] being active\n",
+pipe_name(pipe), intel_dig_port->base.base.base.id,
+intel_dig_port->base.base.name))
return;
drm_dbg_kms(_priv->drm,
@@ -835,13 +837,16 @@ static enum pipe vlv_find_free_pps(struct
drm_i915_private *dev_priv)
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
if (encoder->type == INTEL_OUTPUT_EDP) {
- WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
- intel_dp->active_pipe != intel_dp->pps_pipe);
+ drm_WARN_ON(_priv->drm,
+ intel_dp->active_pipe != INVALID_PIPE &&
+ intel_dp->active_pipe !=
+ intel_dp->pps_pipe);
if (intel_dp->pps_pipe != INVALID_PIPE)
pipes &= ~(1 << intel_dp->pps_pipe);
} else {
- WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
+ drm_WARN_ON(_priv->drm,
+ intel_dp->pps_pipe != INVALID_PIPE);
if (intel_dp->active_pipe != INVALID_PIPE)
pipes &= ~(1 << intel_dp->active_pipe);
@@ -864,10 +869,10 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
lockdep_assert_held(_priv->pps_mutex);
/* We should never land here with regular DP ports */
- WARN_ON(!intel_dp_is_edp(intel_dp));
+ drm_WARN_ON(_priv->drm, !intel_dp_is_edp(intel_dp));
- WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
- intel_dp->active_pipe != intel_dp->pps_pipe);
+ drm_WARN_ON(_priv->drm, intel_dp->active_pipe != INVALID_PIPE &&
+ intel_dp->active_pipe != intel_dp->pps_pipe);
if (intel_dp->pps_pipe != INVALID_PIPE)
return intel_dp->pps_pipe;
@@ -878,7 +883,7 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
* Didn't find one. This should not happen since there
* are two power sequencers and up to two eDP ports.
*/
- if (WARN_ON(pipe ==
[Intel-gfx] [PATCH v6 0/7] drm: Introduce struct drm_device based WARN* and use them in i915
Device specific dev_WARN and dev_WARN_ONCE macros available in kernel include device information in the backtrace, so we know what device the warnings originate from. Similar to this, add new struct drm_device based drm_WARN* macros. These macros include device information in the backtrace, so we know what device the warnings originate from. Knowing the device specific information in the backtrace would be helpful in development all around. This patch series aims to convert calls of WARN(), WARN_ON(), WARN_ONCE() and WARN_ON_ONCE() in i915 driver to use the drm device-specific variants automatically wherever struct device pointer is available. To do this, this patch series - - introduces new struct drm_device based WARN* macros - automatically converts WARN* with device specific dev_WARN* variants using coccinelle semantic patch scripts. The goal is to convert all the calls of WARN* with drm_WARN* in i915, but there are still cases where device pointer is not readily available in some functions (or I missed them somehow) using WARN* hence some manual churning is needed. Handle such remaining cases separately later. changes since v5: - rebase unmerged patches onto drm-tip (db0579be2554 drm-tip: 2020y-02m-05d-10h-51m-13s UTC integration manifest) changes since v4: - Address Jani's comment - split major i915/display related conversions per file into seperate patches so that non conflicting patches can be merged. changes since v3: - rebase pending unmerged patches on drm-tip (bc626bbb5b6e drm-tip: 2020y-01m-25d-14h-28m-41s UTC integration manifest) changes since v2: - rebase pending unmerged patches on drm-tip changes since v1: - Address Jani's review comments - Fix typo in comment of patch 0001 - Get rid of helper functions - Split patches by directory Changes since RFC at [1] - Introduce drm_WARN* macros and use them as suggested by Sam and Jani - Get rid of extra local variables [1] https://patchwork.freedesktop.org/series/71668/ *** BLURB HERE *** Pankaj Bharadiya (7): drm/i915/display/cdclk: Make WARN* drm specific where drm_priv ptr is available drm/i915/display/ddi: Make WARN* drm specific where drm_device ptr is available drm/i915/display/display: Make WARN* drm specific where drm_device ptr is available drm/i915/display/power: Make WARN* drm specific where drm_priv ptr is available drm/i915/display/dp: Make WARN* drm specific where drm_device ptr is available drm/i915/display/global_state: Make WARN* drm specific where drm_device ptr is available drm/i915/display/hdcp: Make WARN* drm specific where drm_priv ptr is available drivers/gpu/drm/i915/display/intel_cdclk.c| 85 --- drivers/gpu/drm/i915/display/intel_ddi.c | 92 --- drivers/gpu/drm/i915/display/intel_display.c | 238 ++ .../drm/i915/display/intel_display_power.c| 174 +++-- drivers/gpu/drm/i915/display/intel_dp.c | 118 + .../gpu/drm/i915/display/intel_global_state.c | 4 +- drivers/gpu/drm/i915/display/intel_hdcp.c | 20 +- 7 files changed, 417 insertions(+), 314 deletions(-) -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 4/7] drm/i915/display/power: Make WARN* drm specific where drm_priv ptr is available
drm specific WARN* calls include device information in the
backtrace, so we know what device the warnings originate from.
Covert all the calls of WARN* with device specific drm_WARN*
variants in functions where drm_i915_private struct pointer is readily
available.
The conversion was done automatically with below coccinelle semantic
patch. checkpatch errors/warnings are fixed manually.
@rule1@
identifier func, T;
@@
func(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-WARN(
+drm_WARN(>drm,
...)
|
-WARN_ON(
+drm_WARN_ON(>drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(>drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(>drm,
...)
)
...+>
}
@rule2@
identifier func, T;
@@
func(struct drm_i915_private *T,...) {
<+...
(
-WARN(
+drm_WARN(>drm,
...)
|
-WARN_ON(
+drm_WARN_ON(>drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(>drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(>drm,
...)
)
...+>
}
Signed-off-by: Pankaj Bharadiya
---
.../drm/i915/display/intel_display_power.c| 174 ++
1 file changed, 101 insertions(+), 73 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 41aec2998ada..4643f92f7434 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -182,8 +182,9 @@ static void intel_power_well_get(struct drm_i915_private
*dev_priv,
static void intel_power_well_put(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- WARN(!power_well->count, "Use count on power well %s is already zero",
-power_well->desc->name);
+ drm_WARN(_priv->drm, !power_well->count,
+"Use count on power well %s is already zero",
+power_well->desc->name);
if (!--power_well->count)
intel_power_well_disable(dev_priv, power_well);
@@ -293,7 +294,7 @@ static void hsw_wait_for_power_well_enable(struct
drm_i915_private *dev_priv,
power_well->desc->name);
/* An AUX timeout is expected if the TBT DP tunnel is down. */
- WARN_ON(!power_well->desc->hsw.is_tc_tbt);
+ drm_WARN_ON(_priv->drm, !power_well->desc->hsw.is_tc_tbt);
}
}
@@ -346,8 +347,9 @@ static void gen9_wait_for_power_well_fuses(struct
drm_i915_private *dev_priv,
enum skl_power_gate pg)
{
/* Timeout 5us for PG#0, for other PGs 1us */
- WARN_ON(intel_de_wait_for_set(dev_priv, SKL_FUSE_STATUS,
- SKL_FUSE_PG_DIST_STATUS(pg), 1));
+ drm_WARN_ON(_priv->drm,
+ intel_de_wait_for_set(dev_priv, SKL_FUSE_STATUS,
+ SKL_FUSE_PG_DIST_STATUS(pg), 1));
}
static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
@@ -422,7 +424,7 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private
*dev_priv,
enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx);
u32 val;
- WARN_ON(!IS_ICELAKE(dev_priv));
+ drm_WARN_ON(_priv->drm, !IS_ICELAKE(dev_priv));
val = intel_de_read(dev_priv, regs->driver);
intel_de_write(dev_priv, regs->driver,
@@ -454,7 +456,7 @@ icl_combo_phy_aux_power_well_disable(struct
drm_i915_private *dev_priv,
enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx);
u32 val;
- WARN_ON(!IS_ICELAKE(dev_priv));
+ drm_WARN_ON(_priv->drm, !IS_ICELAKE(dev_priv));
val = intel_de_read(dev_priv, ICL_PORT_CL_DW12(phy));
intel_de_write(dev_priv, ICL_PORT_CL_DW12(phy),
@@ -492,7 +494,7 @@ static int power_well_async_ref_count(struct
drm_i915_private *dev_priv,
int refs = hweight64(power_well->desc->domains &
async_put_domains_mask(_priv->power_domains));
- WARN_ON(refs > power_well->count);
+ drm_WARN_ON(_priv->drm, refs > power_well->count);
return refs;
}
@@ -522,7 +524,7 @@ static void icl_tc_port_assert_ref_held(struct
drm_i915_private *dev_priv,
continue;
dig_port = enc_to_dig_port(encoder);
- if (WARN_ON(!dig_port))
+ if (drm_WARN_ON(_priv->drm, !dig_port))
continue;
if (dig_port->aux_ch != aux_ch) {
@@ -533,10 +535,10 @@ static void icl_tc_port_assert_ref_held(struct
drm_i915_private *dev_priv,
break;
}
- if (WARN_ON(!dig_port))
+ if (drm_WARN_ON(_priv->drm, !dig_port))
return;
- WARN_ON(!intel_tc_port_ref_held(dig_port));
+ drm_WARN_ON(_priv->drm, !intel_tc_port_ref_held(dig_port));
}
#else
@@ -622,15 +624,19 @@ static bool hsw_power_well_enabled(struct
drm_i915_private *dev_priv,
static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
{
- WARN_ONCE((intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_DC9),
-
[Intel-gfx] [PATCH v6 3/7] drm/i915/display/display: Make WARN* drm specific where drm_device ptr is available
drm specific WARN* calls include device information in the
backtrace, so we know what device the warnings originate from.
Covert all the calls of WARN* with device specific drm_WARN*
variants in functions where drm_device or drm_i915_private struct
pointer is readily available.
The conversion was done automatically with below coccinelle semantic
patch. checkpatch errors/warnings are fixed manually.
@rule1@
identifier func, T;
@@
func(...) {
...
struct drm_device *T = ...;
<...
(
-WARN(
+drm_WARN(T,
...)
|
-WARN_ON(
+drm_WARN_ON(T,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(T,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(T,
...)
)
...>
}
@rule2@
identifier func, T;
@@
func(struct drm_device *T,...) {
<...
(
-WARN(
+drm_WARN(T,
...)
|
-WARN_ON(
+drm_WARN_ON(T,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(T,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(T,
...)
)
...>
}
@rule3@
identifier func, T;
@@
func(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-WARN(
+drm_WARN(>drm,
...)
|
-WARN_ON(
+drm_WARN_ON(>drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(>drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(>drm,
...)
)
...+>
}
@rule4@
identifier func, T;
@@
func(struct drm_i915_private *T,...) {
<+...
(
-WARN(
+drm_WARN(>drm,
...)
|
-WARN_ON(
+drm_WARN_ON(>drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(>drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(>drm,
...)
)
...+>
}
Signed-off-by: Pankaj Bharadiya
---
drivers/gpu/drm/i915/display/intel_display.c | 238 +++
1 file changed, 135 insertions(+), 103 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 368e481d45ee..969134ba82e1 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -203,9 +203,9 @@ int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
val = vlv_cck_read(dev_priv, reg);
divider = val & CCK_FREQUENCY_VALUES;
- WARN((val & CCK_FREQUENCY_STATUS) !=
-(divider << CCK_FREQUENCY_STATUS_SHIFT),
-"%s change in progress\n", name);
+ drm_WARN(_priv->drm, (val & CCK_FREQUENCY_STATUS) !=
+(divider << CCK_FREQUENCY_STATUS_SHIFT),
+"%s change in progress\n", name);
return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
}
@@ -882,7 +882,7 @@ static bool vlv_PLL_is_optimal(struct drm_device *dev, int
target_freq,
return calculated_clock->p > best_clock->p;
}
- if (WARN_ON_ONCE(!target_freq))
+ if (drm_WARN_ON_ONCE(dev, !target_freq))
return false;
*error_ppm = div_u64(100ULL *
@@ -1090,7 +1090,8 @@ intel_wait_for_pipe_off(const struct intel_crtc_state
*old_crtc_state)
/* Wait for the Pipe State to go off */
if (intel_de_wait_for_clear(dev_priv, reg,
I965_PIPECONF_ACTIVE, 100))
- WARN(1, "pipe_off wait timed out\n");
+ drm_WARN(_priv->drm, 1,
+"pipe_off wait timed out\n");
} else {
intel_wait_for_pipe_scanline_stopped(crtc);
}
@@ -1205,7 +1206,7 @@ void assert_panel_unlocked(struct drm_i915_private
*dev_priv, enum pipe pipe)
enum pipe panel_pipe = INVALID_PIPE;
bool locked = true;
- if (WARN_ON(HAS_DDI(dev_priv)))
+ if (drm_WARN_ON(_priv->drm, HAS_DDI(dev_priv)))
return;
if (HAS_PCH_SPLIT(dev_priv)) {
@@ -1241,7 +1242,8 @@ void assert_panel_unlocked(struct drm_i915_private
*dev_priv, enum pipe pipe)
pp_reg = PP_CONTROL(0);
port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) &
PANEL_PORT_SELECT_MASK;
- WARN_ON(port_sel != PANEL_PORT_SELECT_LVDS);
+ drm_WARN_ON(_priv->drm,
+ port_sel != PANEL_PORT_SELECT_LVDS);
intel_lvds_port_enabled(dev_priv, LVDS, _pipe);
}
@@ -1482,7 +1484,9 @@ static void chv_enable_pll(struct intel_crtc *crtc,
* DPLLB VGA mode also seems to cause problems.
* We should always have it disabled.
*/
- WARN_ON((intel_de_read(dev_priv, DPLL(PIPE_B)) &
DPLL_VGA_MODE_DIS) == 0);
+ drm_WARN_ON(_priv->drm,
+ (intel_de_read(dev_priv, DPLL(PIPE_B)) &
+DPLL_VGA_MODE_DIS) == 0);
} else {
intel_de_write(dev_priv, DPLL_MD(pipe),
pipe_config->dpll_hw_state.dpll_md);
@@ -1630,10 +1634,11 @@ void vlv_wait_port_ready(struct drm_i915_private
*dev_priv,
if (intel_de_wait_for_register(dev_priv, dpll_reg,
port_mask, expected_mask, 1000))
- WARN(1, "timed out waiting for [ENCODER:%d:%s] port ready: got
0x%x, expected 0x%x\n",
-dport->base.base.base.id, dport->base.base.name,
-
[Intel-gfx] [PATCH v6 10/10] drivers/oprofile: open access for CAP_PERFMON privileged process
Open access to monitoring for CAP_PERFMON privileged process.
Providing the access under CAP_PERFMON capability singly, without
the rest of CAP_SYS_ADMIN credentials, excludes chances to misuse
the credentials and makes operation more secure.
CAP_PERFMON implements the principal of least privilege for performance
monitoring and observability operations (POSIX IEEE 1003.1e 2.2.2.39
principle of least privilege: A security design principle that states
that a process or program be granted only those privileges (e.g.,
capabilities) necessary to accomplish its legitimate function, and only
for the time that such privileges are actually required)
For backward compatibility reasons access to the monitoring remains
open for CAP_SYS_ADMIN privileged processes but CAP_SYS_ADMIN usage
for secure monitoring is discouraged with respect to CAP_PERFMON
capability.
Signed-off-by: Alexey Budankov
---
drivers/oprofile/event_buffer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/oprofile/event_buffer.c b/drivers/oprofile/event_buffer.c
index 12ea4a4ad607..6c9edc8bbc95 100644
--- a/drivers/oprofile/event_buffer.c
+++ b/drivers/oprofile/event_buffer.c
@@ -113,7 +113,7 @@ static int event_buffer_open(struct inode *inode, struct
file *file)
{
int err = -EPERM;
- if (!capable(CAP_SYS_ADMIN))
+ if (!perfmon_capable())
return -EPERM;
if (test_and_set_bit_lock(0, _opened))
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 09/10] drivers/perf: open access for CAP_PERFMON privileged process
Open access to monitoring for CAP_PERFMON privileged process. Providing the access under CAP_PERFMON capability singly, without the rest of CAP_SYS_ADMIN credentials, excludes chances to misuse the credentials and makes operation more secure. CAP_PERFMON implements the principal of least privilege for performance monitoring and observability operations (POSIX IEEE 1003.1e 2.2.2.39 principle of least privilege: A security design principle that states that a process or program be granted only those privileges (e.g., capabilities) necessary to accomplish its legitimate function, and only for the time that such privileges are actually required) For backward compatibility reasons access to the monitoring remains open for CAP_SYS_ADMIN privileged processes but CAP_SYS_ADMIN usage for secure monitoring is discouraged with respect to CAP_PERFMON capability. Signed-off-by: Alexey Budankov --- drivers/perf/arm_spe_pmu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index 4e4984a55cd1..5dff81bc3324 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -274,7 +274,7 @@ static u64 arm_spe_event_to_pmscr(struct perf_event *event) if (!attr->exclude_kernel) reg |= BIT(SYS_PMSCR_EL1_E1SPE_SHIFT); - if (IS_ENABLED(CONFIG_PID_IN_CONTEXTIDR) && capable(CAP_SYS_ADMIN)) + if (IS_ENABLED(CONFIG_PID_IN_CONTEXTIDR) && perfmon_capable()) reg |= BIT(SYS_PMSCR_EL1_CX_SHIFT); return reg; @@ -700,7 +700,7 @@ static int arm_spe_pmu_event_init(struct perf_event *event) return -EOPNOTSUPP; reg = arm_spe_event_to_pmscr(event); - if (!capable(CAP_SYS_ADMIN) && + if (!perfmon_capable() && (reg & (BIT(SYS_PMSCR_EL1_PA_SHIFT) | BIT(SYS_PMSCR_EL1_CX_SHIFT) | BIT(SYS_PMSCR_EL1_PCT_SHIFT -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 07/10] powerpc/perf: open access for CAP_PERFMON privileged process
Open access to monitoring for CAP_PERFMON privileged process. Providing the access under CAP_PERFMON capability singly, without the rest of CAP_SYS_ADMIN credentials, excludes chances to misuse the credentials and makes operation more secure. CAP_PERFMON implements the principal of least privilege for performance monitoring and observability operations (POSIX IEEE 1003.1e 2.2.2.39 principle of least privilege: A security design principle that states that a process or program be granted only those privileges (e.g., capabilities) necessary to accomplish its legitimate function, and only for the time that such privileges are actually required) For backward compatibility reasons access to the monitoring remains open for CAP_SYS_ADMIN privileged processes but CAP_SYS_ADMIN usage for secure monitoring is discouraged with respect to CAP_PERFMON capability. Signed-off-by: Alexey Budankov --- arch/powerpc/perf/imc-pmu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/perf/imc-pmu.c b/arch/powerpc/perf/imc-pmu.c index cb50a9e1fd2d..e837717492e4 100644 --- a/arch/powerpc/perf/imc-pmu.c +++ b/arch/powerpc/perf/imc-pmu.c @@ -898,7 +898,7 @@ static int thread_imc_event_init(struct perf_event *event) if (event->attr.type != event->pmu->type) return -ENOENT; - if (!capable(CAP_SYS_ADMIN)) + if (!perfmon_capable()) return -EACCES; /* Sampling not supported */ @@ -1307,7 +1307,7 @@ static int trace_imc_event_init(struct perf_event *event) if (event->attr.type != event->pmu->type) return -ENOENT; - if (!capable(CAP_SYS_ADMIN)) + if (!perfmon_capable()) return -EACCES; /* Return if this is a couting event */ -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 08/10] parisc/perf: open access for CAP_PERFMON privileged process
Open access to monitoring for CAP_PERFMON privileged process. Providing the access under CAP_PERFMON capability singly, without the rest of CAP_SYS_ADMIN credentials, excludes chances to misuse the credentials and makes operation more secure. CAP_PERFMON implements the principal of least privilege for performance monitoring and observability operations (POSIX IEEE 1003.1e 2.2.2.39 principle of least privilege: A security design principle that states that a process or program be granted only those privileges (e.g., capabilities) necessary to accomplish its legitimate function, and only for the time that such privileges are actually required) For backward compatibility reasons access to the monitoring remains open for CAP_SYS_ADMIN privileged processes but CAP_SYS_ADMIN usage for secure monitoring is discouraged with respect to CAP_PERFMON capability. Signed-off-by: Alexey Budankov --- arch/parisc/kernel/perf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/parisc/kernel/perf.c b/arch/parisc/kernel/perf.c index 676683641d00..c4208d027794 100644 --- a/arch/parisc/kernel/perf.c +++ b/arch/parisc/kernel/perf.c @@ -300,7 +300,7 @@ static ssize_t perf_write(struct file *file, const char __user *buf, else return -EFAULT; - if (!capable(CAP_SYS_ADMIN)) + if (!perfmon_capable()) return -EACCES; if (count != sizeof(uint32_t)) -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 06/10] trace/bpf_trace: open access for CAP_PERFMON privileged process
Open access to bpf_trace monitoring for CAP_PERFMON privileged process. Providing the access under CAP_PERFMON capability singly, without the rest of CAP_SYS_ADMIN credentials, excludes chances to misuse the credentials and makes operation more secure. CAP_PERFMON implements the principal of least privilege for performance monitoring and observability operations (POSIX IEEE 1003.1e 2.2.2.39 principle of least privilege: A security design principle that states that a process or program be granted only those privileges (e.g., capabilities) necessary to accomplish its legitimate function, and only for the time that such privileges are actually required) For backward compatibility reasons access to bpf_trace monitoring remains open for CAP_SYS_ADMIN privileged processes but CAP_SYS_ADMIN usage for secure bpf_trace monitoring is discouraged with respect to CAP_PERFMON capability. Signed-off-by: Alexey Budankov --- kernel/trace/bpf_trace.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/trace/bpf_trace.c b/kernel/trace/bpf_trace.c index e5ef4ae9edb5..334f1d71ebb1 100644 --- a/kernel/trace/bpf_trace.c +++ b/kernel/trace/bpf_trace.c @@ -1395,7 +1395,7 @@ int perf_event_query_prog_array(struct perf_event *event, void __user *info) u32 *ids, prog_cnt, ids_len; int ret; - if (!capable(CAP_SYS_ADMIN)) + if (!perfmon_capable()) return -EPERM; if (event->attr.type != PERF_TYPE_TRACEPOINT) return -EINVAL; -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 05/10] drm/i915/perf: open access for CAP_PERFMON privileged process
Open access to i915_perf monitoring for CAP_PERFMON privileged process.
Providing the access under CAP_PERFMON capability singly, without the
rest of CAP_SYS_ADMIN credentials, excludes chances to misuse the
credentials and makes operation more secure.
CAP_PERFMON implements the principal of least privilege for performance
monitoring and observability operations (POSIX IEEE 1003.1e 2.2.2.39
principle of least privilege: A security design principle that states that
a process or program be granted only those privileges (e.g., capabilities)
necessary to accomplish its legitimate function, and only for the time
that such privileges are actually required)
For backward compatibility reasons access to i915_perf subsystem remains
open for CAP_SYS_ADMIN privileged processes but CAP_SYS_ADMIN usage for
secure i915_perf monitoring is discouraged with respect to CAP_PERFMON
capability.
Signed-off-by: Alexey Budankov
---
drivers/gpu/drm/i915/i915_perf.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 2ae14bc14931..d89347861b7d 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3375,10 +3375,10 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
/* Similar to perf's kernel.perf_paranoid_cpu sysctl option
* we check a dev.i915.perf_stream_paranoid sysctl option
* to determine if it's ok to access system wide OA counters
-* without CAP_SYS_ADMIN privileges.
+* without CAP_PERFMON or CAP_SYS_ADMIN privileges.
*/
if (privileged_op &&
- i915_perf_stream_paranoid && !capable(CAP_SYS_ADMIN)) {
+ i915_perf_stream_paranoid && !perfmon_capable()) {
DRM_DEBUG("Insufficient privileges to open i915 perf stream\n");
ret = -EACCES;
goto err_ctx;
@@ -3571,9 +3571,8 @@ static int read_properties_unlocked(struct i915_perf
*perf,
} else
oa_freq_hz = 0;
- if (oa_freq_hz > i915_oa_max_sample_rate &&
- !capable(CAP_SYS_ADMIN)) {
- DRM_DEBUG("OA exponent would exceed the max
sampling frequency (sysctl dev.i915.oa_max_sample_rate) %uHz without root
privileges\n",
+ if (oa_freq_hz > i915_oa_max_sample_rate &&
!perfmon_capable()) {
+ DRM_DEBUG("OA exponent would exceed the max
sampling frequency (sysctl dev.i915.oa_max_sample_rate) %uHz without
CAP_PERFMON or CAP_SYS_ADMIN privileges\n",
i915_oa_max_sample_rate);
return -EACCES;
}
@@ -3994,7 +3993,7 @@ int i915_perf_add_config_ioctl(struct drm_device *dev,
void *data,
return -EINVAL;
}
- if (i915_perf_stream_paranoid && !capable(CAP_SYS_ADMIN)) {
+ if (i915_perf_stream_paranoid && !perfmon_capable()) {
DRM_DEBUG("Insufficient privileges to add i915 OA config\n");
return -EACCES;
}
@@ -4141,7 +4140,7 @@ int i915_perf_remove_config_ioctl(struct drm_device *dev,
void *data,
return -ENOTSUPP;
}
- if (i915_perf_stream_paranoid && !capable(CAP_SYS_ADMIN)) {
+ if (i915_perf_stream_paranoid && !perfmon_capable()) {
DRM_DEBUG("Insufficient privileges to remove i915 OA config\n");
return -EACCES;
}
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 04/10] perf tool: extend Perf tool with CAP_PERFMON capability support
Extend error messages to mention CAP_PERFMON capability as an option
to substitute CAP_SYS_ADMIN capability for secure system performance
monitoring and observability operations. Make perf_event_paranoid_check()
and __cmd_ftrace() to be aware of CAP_PERFMON capability.
CAP_PERFMON implements the principal of least privilege for performance
monitoring and observability operations (POSIX IEEE 1003.1e 2.2.2.39
principle of least privilege: A security design principle that states
that a process or program be granted only those privileges (e.g.,
capabilities) necessary to accomplish its legitimate function, and only
for the time that such privileges are actually required)
For backward compatibility reasons access to perf_events subsystem remains
open for CAP_SYS_ADMIN privileged processes but CAP_SYS_ADMIN usage for
secure perf_events monitoring is discouraged with respect to CAP_PERFMON
capability.
Signed-off-by: Alexey Budankov
---
tools/perf/builtin-ftrace.c | 5 +++--
tools/perf/design.txt | 3 ++-
tools/perf/util/cap.h | 4
tools/perf/util/evsel.c | 10 +-
tools/perf/util/util.c | 1 +
5 files changed, 15 insertions(+), 8 deletions(-)
diff --git a/tools/perf/builtin-ftrace.c b/tools/perf/builtin-ftrace.c
index d5adc417a4ca..55eda54240fb 100644
--- a/tools/perf/builtin-ftrace.c
+++ b/tools/perf/builtin-ftrace.c
@@ -284,10 +284,11 @@ static int __cmd_ftrace(struct perf_ftrace *ftrace, int
argc, const char **argv)
.events = POLLIN,
};
- if (!perf_cap__capable(CAP_SYS_ADMIN)) {
+ if (!(perf_cap__capable(CAP_PERFMON) ||
+ perf_cap__capable(CAP_SYS_ADMIN))) {
pr_err("ftrace only works for %s!\n",
#ifdef HAVE_LIBCAP_SUPPORT
- "users with the SYS_ADMIN capability"
+ "users with the CAP_PERFMON or CAP_SYS_ADMIN capability"
#else
"root"
#endif
diff --git a/tools/perf/design.txt b/tools/perf/design.txt
index 0453ba26cdbd..a42fab308ff6 100644
--- a/tools/perf/design.txt
+++ b/tools/perf/design.txt
@@ -258,7 +258,8 @@ gets schedule to. Per task counters can be created by any
user, for
their own tasks.
A 'pid == -1' and 'cpu == x' counter is a per CPU counter that counts
-all events on CPU-x. Per CPU counters need CAP_SYS_ADMIN privilege.
+all events on CPU-x. Per CPU counters need CAP_PERFMON or CAP_SYS_ADMIN
+privilege.
The 'flags' parameter is currently unused and must be zero.
diff --git a/tools/perf/util/cap.h b/tools/perf/util/cap.h
index 051dc590ceee..ae52878c0b2e 100644
--- a/tools/perf/util/cap.h
+++ b/tools/perf/util/cap.h
@@ -29,4 +29,8 @@ static inline bool perf_cap__capable(int cap __maybe_unused)
#define CAP_SYSLOG 34
#endif
+#ifndef CAP_PERFMON
+#define CAP_PERFMON38
+#endif
+
#endif /* __PERF_CAP_H */
diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c
index a69e64236120..a35f17723dd3 100644
--- a/tools/perf/util/evsel.c
+++ b/tools/perf/util/evsel.c
@@ -2491,14 +2491,14 @@ int perf_evsel__open_strerror(struct evsel *evsel,
struct target *target,
"You may not have permission to collect %sstats.\n\n"
"Consider tweaking /proc/sys/kernel/perf_event_paranoid,\n"
"which controls use of the performance events system by\n"
-"unprivileged users (without CAP_SYS_ADMIN).\n\n"
+"unprivileged users (without CAP_PERFMON or
CAP_SYS_ADMIN).\n\n"
"The current value is %d:\n\n"
" -1: Allow use of (almost) all events by all users\n"
" Ignore mlock limit after perf_event_mlock_kb without
CAP_IPC_LOCK\n"
-">= 0: Disallow ftrace function tracepoint by users without
CAP_SYS_ADMIN\n"
-" Disallow raw tracepoint access by users without
CAP_SYS_ADMIN\n"
-">= 1: Disallow CPU event access by users without
CAP_SYS_ADMIN\n"
-">= 2: Disallow kernel profiling by users without
CAP_SYS_ADMIN\n\n"
+">= 0: Disallow ftrace function tracepoint by users without
CAP_PERFMON or CAP_SYS_ADMIN\n"
+" Disallow raw tracepoint access by users without
CAP_SYS_PERFMON or CAP_SYS_ADMIN\n"
+">= 1: Disallow CPU event access by users without CAP_PERFMON
or CAP_SYS_ADMIN\n"
+">= 2: Disallow kernel profiling by users without CAP_PERFMON
or CAP_SYS_ADMIN\n\n"
"To make this setting permanent, edit /etc/sysctl.conf too,
e.g.:\n\n"
" kernel.perf_event_paranoid = -1\n" ,
target->system_wide ? "system-wide " : "",
diff --git a/tools/perf/util/util.c b/tools/perf/util/util.c
index 969ae560dad9..51cf3071db74 100644
--- a/tools/perf/util/util.c
+++ b/tools/perf/util/util.c
@@ -272,6 +272,7 @@ int perf_event_paranoid(void)
bool perf_event_paranoid_check(int max_level)
{
return
[Intel-gfx] [PATCH v6 03/10] perf/core: open access to probes for CAP_PERFMON privileged process
Open access to monitoring via kprobes and uprobes and eBPF tracing for CAP_PERFMON privileged process. Providing the access under CAP_PERFMON capability singly, without the rest of CAP_SYS_ADMIN credentials, excludes chances to misuse the credentials and makes operation more secure. perf kprobes and uprobes are used by ftrace and eBPF. perf probe uses ftrace to define new kprobe events, and those events are treated as tracepoint events. eBPF defines new probes via perf_event_open interface and then the probes are used in eBPF tracing. CAP_PERFMON implements the principal of least privilege for performance monitoring and observability operations (POSIX IEEE 1003.1e 2.2.2.39 principle of least privilege: A security design principle that states that a process or program be granted only those privileges (e.g., capabilities) necessary to accomplish its legitimate function, and only for the time that such privileges are actually required) For backward compatibility reasons access to perf_events subsystem remains open for CAP_SYS_ADMIN privileged processes but CAP_SYS_ADMIN usage for secure perf_events monitoring is discouraged with respect to CAP_PERFMON capability. Signed-off-by: Alexey Budankov --- kernel/events/core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/kernel/events/core.c b/kernel/events/core.c index d956c81bd310..c6453320ffea 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -9088,7 +9088,7 @@ static int perf_kprobe_event_init(struct perf_event *event) if (event->attr.type != perf_kprobe.type) return -ENOENT; - if (!capable(CAP_SYS_ADMIN)) + if (!perfmon_capable()) return -EACCES; /* @@ -9148,7 +9148,7 @@ static int perf_uprobe_event_init(struct perf_event *event) if (event->attr.type != perf_uprobe.type) return -ENOENT; - if (!capable(CAP_SYS_ADMIN)) + if (!perfmon_capable()) return -EACCES; /* -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 02/10] perf/core: open access to the core for CAP_PERFMON privileged process
Open access to monitoring of kernel code, cpus, tracepoints and namespaces
data for a CAP_PERFMON privileged process. Providing the access under
CAP_PERFMON capability singly, without the rest of CAP_SYS_ADMIN credentials,
excludes chances to misuse the credentials and makes operation more secure.
CAP_PERFMON implements the principal of least privilege for performance
monitoring and observability operations (POSIX IEEE 1003.1e 2.2.2.39 principle
of least privilege: A security design principle that states that a process or
program be granted only those privileges (e.g., capabilities) necessary to
accomplish its legitimate function, and only for the time that such privileges
are actually required)
For backward compatibility reasons access to perf_events subsystem remains
open for CAP_SYS_ADMIN privileged processes but CAP_SYS_ADMIN usage for secure
perf_events monitoring is discouraged with respect to CAP_PERFMON capability.
Signed-off-by: Alexey Budankov
---
include/linux/perf_event.h | 6 +++---
kernel/events/core.c | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
index 6d4c22aee384..730469babcc2 100644
--- a/include/linux/perf_event.h
+++ b/include/linux/perf_event.h
@@ -1285,7 +1285,7 @@ static inline int perf_is_paranoid(void)
static inline int perf_allow_kernel(struct perf_event_attr *attr)
{
- if (sysctl_perf_event_paranoid > 1 && !capable(CAP_SYS_ADMIN))
+ if (sysctl_perf_event_paranoid > 1 && !perfmon_capable())
return -EACCES;
return security_perf_event_open(attr, PERF_SECURITY_KERNEL);
@@ -1293,7 +1293,7 @@ static inline int perf_allow_kernel(struct
perf_event_attr *attr)
static inline int perf_allow_cpu(struct perf_event_attr *attr)
{
- if (sysctl_perf_event_paranoid > 0 && !capable(CAP_SYS_ADMIN))
+ if (sysctl_perf_event_paranoid > 0 && !perfmon_capable())
return -EACCES;
return security_perf_event_open(attr, PERF_SECURITY_CPU);
@@ -1301,7 +1301,7 @@ static inline int perf_allow_cpu(struct perf_event_attr
*attr)
static inline int perf_allow_tracepoint(struct perf_event_attr *attr)
{
- if (sysctl_perf_event_paranoid > -1 && !capable(CAP_SYS_ADMIN))
+ if (sysctl_perf_event_paranoid > -1 && !perfmon_capable())
return -EPERM;
return security_perf_event_open(attr, PERF_SECURITY_TRACEPOINT);
diff --git a/kernel/events/core.c b/kernel/events/core.c
index 2173c23c25b4..d956c81bd310 100644
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -11186,7 +11186,7 @@ SYSCALL_DEFINE5(perf_event_open,
}
if (attr.namespaces) {
- if (!capable(CAP_SYS_ADMIN))
+ if (!perfmon_capable())
return -EACCES;
}
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 01/10] capabilities: introduce CAP_PERFMON to kernel and user space
Introduce CAP_PERFMON capability designed to secure system performance
monitoring and observability operations so that CAP_PERFMON would assist
CAP_SYS_ADMIN capability in its governing role for performance monitoring
and observability subsystems.
CAP_PERFMON hardens system security and integrity during performance
monitoring and observability operations by decreasing attack surface that
is available to a CAP_SYS_ADMIN privileged process [2]. Providing the access
to system performance monitoring and observability operations under CAP_PERFMON
capability singly, without the rest of CAP_SYS_ADMIN credentials, excludes
chances to misuse the credentials and makes the operation more secure.
Thus, CAP_PERFMON implements the principal of least privilege for performance
monitoring and observability operations (POSIX IEEE 1003.1e: 2.2.2.39 principle
of least privilege: A security design principle that states that a process
or program be granted only those privileges (e.g., capabilities) necessary
to accomplish its legitimate function, and only for the time that such
privileges are actually required)
CAP_PERFMON meets the demand to secure system performance monitoring and
observability operations for adoption in security sensitive, restricted,
multiuser production environments (e.g. HPC clusters, cloud and virtual compute
environments), where root or CAP_SYS_ADMIN credentials are not available to
mass users of a system, and securely unblocks accessibility of system
performance monitoring and observability operations beyond root and
CAP_SYS_ADMIN use cases.
CAP_PERFMON takes over CAP_SYS_ADMIN credentials related to system performance
monitoring and observability operations and balances amount of CAP_SYS_ADMIN
credentials following the recommendations in the capabilities man page [1]
for CAP_SYS_ADMIN: "Note: this capability is overloaded; see Notes to kernel
developers, below." For backward compatibility reasons access to system
performance monitoring and observability subsystems of the kernel remains
open for CAP_SYS_ADMIN privileged processes but CAP_SYS_ADMIN capability
usage for secure system performance monitoring and observability operations
is discouraged with respect to the designed CAP_PERFMON capability.
Although the software running under CAP_PERFMON can not ensure avoidance
of related hardware issues, the software can still mitigate these issues
following the official hardware issues mitigation procedure [2]. The bugs
in the software itself can be fixed following the standard kernel development
process [3] to maintain and harden security of system performance monitoring
and observability operations.
[1] http://man7.org/linux/man-pages/man7/capabilities.7.html
[2]
https://www.kernel.org/doc/html/latest/process/embargoed-hardware-issues.html
[3] https://www.kernel.org/doc/html/latest/admin-guide/security-bugs.html
Signed-off-by: Alexey Budankov
---
include/linux/capability.h | 4
include/uapi/linux/capability.h | 8 +++-
security/selinux/include/classmap.h | 4 ++--
3 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/include/linux/capability.h b/include/linux/capability.h
index ecce0f43c73a..027d7e4a853b 100644
--- a/include/linux/capability.h
+++ b/include/linux/capability.h
@@ -251,6 +251,10 @@ extern bool privileged_wrt_inode_uidgid(struct
user_namespace *ns, const struct
extern bool capable_wrt_inode_uidgid(const struct inode *inode, int cap);
extern bool file_ns_capable(const struct file *file, struct user_namespace
*ns, int cap);
extern bool ptracer_capable(struct task_struct *tsk, struct user_namespace
*ns);
+static inline bool perfmon_capable(void)
+{
+ return capable(CAP_PERFMON) || capable(CAP_SYS_ADMIN);
+}
/* audit system wants to get cap info from files as well */
extern int get_vfs_caps_from_disk(const struct dentry *dentry, struct
cpu_vfs_cap_data *cpu_caps);
diff --git a/include/uapi/linux/capability.h b/include/uapi/linux/capability.h
index 240fdb9a60f6..8b416e5f3afa 100644
--- a/include/uapi/linux/capability.h
+++ b/include/uapi/linux/capability.h
@@ -366,8 +366,14 @@ struct vfs_ns_cap_data {
#define CAP_AUDIT_READ 37
+/*
+ * Allow system performance and observability privileged operations
+ * using perf_events, i915_perf and other kernel subsystems
+ */
+
+#define CAP_PERFMON38
-#define CAP_LAST_CAP CAP_AUDIT_READ
+#define CAP_LAST_CAP CAP_PERFMON
#define cap_valid(x) ((x) >= 0 && (x) <= CAP_LAST_CAP)
diff --git a/security/selinux/include/classmap.h
b/security/selinux/include/classmap.h
index 7db24855e12d..c599b0c2b0e7 100644
--- a/security/selinux/include/classmap.h
+++ b/security/selinux/include/classmap.h
@@ -27,9 +27,9 @@
"audit_control", "setfcap"
#define COMMON_CAP2_PERMS "mac_override", "mac_admin", "syslog", \
- "wake_alarm", "block_suspend", "audit_read"
+ "wake_alarm", "block_suspend", "audit_read", "perfmon"
-#if
[Intel-gfx] [PATCH v6 00/10] Introduce CAP_PERFMON to secure system performance monitoring and observability
Currently access to perf_events, i915_perf and other performance monitoring and observability subsystems of the kernel is open only for a privileged process [1] with CAP_SYS_ADMIN capability enabled in the process effective set [2]. This patch set introduces CAP_PERFMON capability designed to secure system performance monitoring and observability operations so that CAP_PERFMON would assist CAP_SYS_ADMIN capability in its governing role for performance monitoring and observability subsystems of the kernel. CAP_PERFMON intends to harden system security and integrity during performance monitoring and observability operations by decreasing attack surface that is available to a CAP_SYS_ADMIN privileged process [2]. Providing the access to performance monitoring and observability operations under CAP_PERFMON capability singly, without the rest of CAP_SYS_ADMIN credentials, excludes chances to misuse the credentials and makes the operation more secure. Thus, CAP_PERFMON implements the principal of least privilege for performance monitoring and observability operations (POSIX IEEE 1003.1e: 2.2.2.39 principle of least privilege: A security design principle that states that a process or program be granted only those privileges (e.g., capabilities) necessary to accomplish its legitimate function, and only for the time that such privileges are actually required) CAP_PERFMON intends to meet the demand to secure system performance monitoring and observability operations for adoption in security sensitive, restricted, multiuser production environments (e.g. HPC clusters, cloud and virtual compute environments), where root or CAP_SYS_ADMIN credentials are not available to mass users of a system, and securely unblock accessibility of system performance monitoring and observability operations beyond root and CAP_SYS_ADMIN use cases. CAP_PERFMON intends to take over CAP_SYS_ADMIN credentials related to system performance monitoring and observability operations and balance amount of CAP_SYS_ADMIN credentials following the recommendations in the capabilities man page [2] for CAP_SYS_ADMIN: "Note: this capability is overloaded; see Notes to kernel developers, below." For backward compatibility reasons access to system performance monitoring and observability subsystems of the kernel remains open for CAP_SYS_ADMIN privileged processes but CAP_SYS_ADMIN capability usage for secure system performance monitoring and observability operations is discouraged with respect to the designed CAP_PERFMON capability. Possible alternative solution to this system security hardening, capabilities balancing task of making performance monitoring and observability operations more secure and accessible could be to use the existing CAP_SYS_PTRACE capability to govern system performance monitoring and observability subsystems. However CAP_SYS_PTRACE capability still provides users with more credentials than are required for secure performance monitoring and observability operations and this excess is avoided by the designed CAP_PERFMON capability. Although software running under CAP_PERFMON can not ensure avoidance of related hardware issues, the software can still mitigate those issues following the official hardware issues mitigation procedure [3]. The bugs in the software itself can be fixed following the standard kernel development process [4] to maintain and harden security of system performance monitoring and observability operations. Finally, the patch set is shaped in the way that simplifies backtracking procedure of possible induced issues [5] as much as possible. The patch set is for tip perf/core repository: git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip perf/core sha1: 0cc4bd8f70d1ea2940295f1050508c663fe9eff9 --- Changes in v6: - avoided noaudit checks in perfmon_capable() to explicitly advertise CAP_PERFMON usage thru audit logs to secure system performance monitoring and observability Changes in v5: - renamed CAP_SYS_PERFMON to CAP_PERFMON - extended perfmon_capable() with noaudit checks Changes in v4: - converted perfmon_capable() into an inline function - made perf_events kprobes, uprobes, hw breakpoints and namespaces data available to CAP_SYS_PERFMON privileged processes - applied perfmon_capable() to drivers/perf and drivers/oprofile - extended __cmd_ftrace() with support of CAP_SYS_PERFMON Changes in v3: - implemented perfmon_capable() macros aggregating required capabilities checks Changes in v2: - made perf_events trace points available to CAP_SYS_PERFMON privileged processes - made perf_event_paranoid_check() treat CAP_SYS_PERFMON equally to CAP_SYS_ADMIN - applied CAP_SYS_PERFMON to i915_perf, bpf_trace, powerpc and parisc system performance monitoring and observability related subsystems --- Alexey Budankov (10): capabilities: introduce CAP_PERFMON to kernel and user space perf/core: open access to the core for CAP_PERFMON privileged process perf/core: open access to probes for
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gem: Don't leak non-persistent requests on changing engines (rev2)
== Series Details == Series: drm/i915/gem: Don't leak non-persistent requests on changing engines (rev2) URL : https://patchwork.freedesktop.org/series/73023/ State : success == Summary == CI Bug Log - changes from CI_DRM_7869 -> Patchwork_16434 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16434/index.html Known issues Here are the changes found in Patchwork_16434 that come from known issues: ### IGT changes ### Issues hit * igt@gem_close_race@basic-threads: - fi-byt-j1900: [PASS][1] -> [INCOMPLETE][2] ([i915#45]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-byt-j1900/igt@gem_close_r...@basic-threads.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16434/fi-byt-j1900/igt@gem_close_r...@basic-threads.html * igt@i915_selftest@live_execlists: - fi-icl-y: [PASS][3] -> [DMESG-FAIL][4] ([fdo#108569]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-icl-y/igt@i915_selftest@live_execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16434/fi-icl-y/igt@i915_selftest@live_execlists.html * igt@i915_selftest@live_gem_contexts: - fi-kbl-x1275: [PASS][5] -> [INCOMPLETE][6] ([i915#504]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-kbl-x1275/igt@i915_selftest@live_gem_contexts.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16434/fi-kbl-x1275/igt@i915_selftest@live_gem_contexts.html * igt@i915_selftest@live_gtt: - fi-bdw-5557u: [PASS][7] -> [TIMEOUT][8] ([fdo#112271]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-bdw-5557u/igt@i915_selftest@live_gtt.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16434/fi-bdw-5557u/igt@i915_selftest@live_gtt.html * igt@prime_self_import@basic-llseek-bad: - fi-tgl-y: [PASS][9] -> [DMESG-WARN][10] ([CI#94] / [i915#402]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-tgl-y/igt@prime_self_imp...@basic-llseek-bad.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16434/fi-tgl-y/igt@prime_self_imp...@basic-llseek-bad.html Possible fixes * igt@gem_exec_parallel@fds: - fi-icl-u3: [INCOMPLETE][11] -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-icl-u3/igt@gem_exec_paral...@fds.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16434/fi-icl-u3/igt@gem_exec_paral...@fds.html * igt@gem_exec_suspend@basic-s4-devices: - fi-tgl-y: [FAIL][13] ([CI#94]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-tgl-y/igt@gem_exec_susp...@basic-s4-devices.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16434/fi-tgl-y/igt@gem_exec_susp...@basic-s4-devices.html * igt@i915_getparams_basic@basic-subslice-total: - fi-tgl-y: [DMESG-WARN][15] ([CI#94] / [i915#402]) -> [PASS][16] +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16434/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html * igt@i915_module_load@reload: - fi-skl-6770hq: [DMESG-WARN][17] ([i915#92]) -> [PASS][18] +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-skl-6770hq/igt@i915_module_l...@reload.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16434/fi-skl-6770hq/igt@i915_module_l...@reload.html * igt@i915_selftest@live_blt: - fi-ivb-3770:[DMESG-FAIL][19] ([i915#725]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-ivb-3770/igt@i915_selftest@live_blt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16434/fi-ivb-3770/igt@i915_selftest@live_blt.html * igt@kms_chamelium@hdmi-crc-fast: - fi-kbl-7500u: [FAIL][21] ([fdo#109635] / [i915#217]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16434/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][23] ([fdo#111096] / [i915#323]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16434/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-skl-6770hq: [SKIP][25] ([fdo#109271]) -> [PASS][26] +4 similar issues [25]:
Re: [Intel-gfx] [PATCH v3 17/17] drm/i915/psr: Use new DP VSC SDP compute routine on PSR
> -Original Message-
> From: Intel-gfx On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fb...@vger.kernel.org; dri-de...@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3 17/17] drm/i915/psr: Use new DP VSC SDP compute
> routine on PSR
>
> In order to use a common VSC SDP Colorimetry calculating code on PSR, it uses
> a
> new psr vsc sdp compute routine.
> Because PSR routine has its own scenario and timings of writing a VSC SDP, the
> current PSR routine needs to have its own drm_dp_vsc_sdp structure member
> variable on struct i915_psr.
>
> In order to calculate colorimetry information, intel_psr_update() function and
> intel_psr_enable() function extend a drm_connector_state argument.
>
> There are no changes to PSR mechanism.
>
> v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
Looks good.
Reviewed-by: Uma Shankar
Note: Please rebase, fix the comments and resend to trigger a full CI run.
> Signed-off-by: Gwan-gyeong Mun
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 54 +++-
> drivers/gpu/drm/i915/display/intel_psr.h | 6 ++-
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> 4 files changed, 22 insertions(+), 43 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 8509cd33569e..00b46c45f6a8 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3901,7 +3901,7 @@ static void intel_enable_ddi_dp(struct intel_encoder
> *encoder,
> intel_dp_stop_link_train(intel_dp);
>
> intel_edp_backlight_on(crtc_state, conn_state);
> - intel_psr_enable(intel_dp, crtc_state);
> + intel_psr_enable(intel_dp, crtc_state, conn_state);
> intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
> intel_edp_drrs_enable(intel_dp, crtc_state);
>
> @@ -4063,7 +4063,7 @@ static void intel_ddi_update_pipe_dp(struct
> intel_encoder
> *encoder,
>
> intel_ddi_set_dp_msa(crtc_state, conn_state);
>
> - intel_psr_update(intel_dp, crtc_state);
> + intel_psr_update(intel_dp, crtc_state, conn_state);
> intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
> intel_edp_drrs_enable(intel_dp, crtc_state);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index e41ed962aa80..a4564607b6c5 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -330,39 +330,6 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
> }
> }
>
> -static void intel_psr_setup_vsc(struct intel_dp *intel_dp,
> - const struct intel_crtc_state *crtc_state)
> -{
> - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - struct dp_sdp psr_vsc;
> -
> - if (dev_priv->psr.psr2_enabled) {
> - /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
> - memset(_vsc, 0, sizeof(psr_vsc));
> - psr_vsc.sdp_header.HB0 = 0;
> - psr_vsc.sdp_header.HB1 = 0x7;
> - if (dev_priv->psr.colorimetry_support) {
> - psr_vsc.sdp_header.HB2 = 0x5;
> - psr_vsc.sdp_header.HB3 = 0x13;
> - } else {
> - psr_vsc.sdp_header.HB2 = 0x4;
> - psr_vsc.sdp_header.HB3 = 0xe;
> - }
> - } else {
> - /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
> - memset(_vsc, 0, sizeof(psr_vsc));
> - psr_vsc.sdp_header.HB0 = 0;
> - psr_vsc.sdp_header.HB1 = 0x7;
> - psr_vsc.sdp_header.HB2 = 0x2;
> - psr_vsc.sdp_header.HB3 = 0x8;
> - }
> -
> - intel_dig_port->write_infoframe(_dig_port->base,
> - crtc_state,
> - DP_SDP_VSC, _vsc, sizeof(psr_vsc));
> -}
> -
> static void hsw_psr_setup_aux(struct intel_dp *intel_dp) {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); @@ -841,9
> +808,12 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, }
>
> static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
> - const struct intel_crtc_state *crtc_state)
> + const struct intel_crtc_state *crtc_state,
> + const struct drm_connector_state
> *conn_state)
> {
> struct intel_dp *intel_dp = dev_priv->psr.dp;
> + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> + struct intel_encoder *encoder = _dig_port->base;
> u32 val;
>
> WARN_ON(dev_priv->psr.enabled);
> @@ -881,7 +851,9 @@
Re: [Intel-gfx] [PATCH v3 16/17] drm/i915/dp: Add compute routine for DP PSR VSC SDP
> -Original Message-
> From: dri-devel On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fb...@vger.kernel.org; dri-de...@lists.freedesktop.org
> Subject: [PATCH v3 16/17] drm/i915/dp: Add compute routine for DP PSR VSC SDP
>
> In order to use a common VSC SDP Colorimetry calculating code on PSR, it adds
> a
> compute routine for PSR VSC SDP.
> As PSR routine can not use infoframes.vsc of crtc state, it also adds new
> writing of
> DP SDPs (Secondary Data Packet) for PSR.
> PSR routine has its own scenario and timings of writing a VSC SDP.
>
> v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
Looks good to me.
Reviewed-by: Uma Shankar
> Signed-off-by: Gwan-gyeong Mun
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 53 +
> drivers/gpu/drm/i915/display/intel_dp.h | 8
> 2 files changed, 61 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index cffb77daec96..4d65ef36577f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2463,6 +2463,42 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp
> *intel_dp,
>_state->infoframes.vsc);
> }
>
> +void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
> + const struct intel_crtc_state *crtc_state,
> + const struct drm_connector_state *conn_state,
> + struct drm_dp_vsc_sdp *vsc)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> + vsc->sdp_type = DP_SDP_VSC;
> +
> + if (dev_priv->psr.psr2_enabled) {
> + if (dev_priv->psr.colorimetry_support &&
> + intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
> + /* [PSR2, +Colorimetry] */
> + intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
> + vsc);
> + } else {
> + /*
> + * [PSR2, -Colorimetry]
> + * Prepare VSC Header for SU as per eDP 1.4 spec, Table
> 6-
> 11
> + * 3D stereo + PSR/PSR2 + Y-coordinate.
> + */
> + vsc->revision = 0x4;
> + vsc->length = 0xe;
> + }
> + } else {
> + /*
> + * [PSR1]
> + * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> + * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
> + * higher).
> + */
> + vsc->revision = 0x2;
> + vsc->length = 0x8;
> + }
> +}
> +
> static void
> intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_crtc_state
> *crtc_state,
> const struct drm_connector_state
> *conn_state) @@ -4889,6 +4925,23 @@ static void intel_write_dp_sdp(struct
> intel_encoder *encoder,
> intel_dig_port->write_infoframe(encoder, crtc_state, type, , len);
> }
>
> +void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state,
> + struct drm_dp_vsc_sdp *vsc)
> +{
> + struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
> + struct dp_sdp sdp = {};
> + ssize_t len;
> +
> + len = intel_dp_vsc_sdp_pack(vsc, , sizeof(sdp));
> +
> + if (WARN_ON(len < 0))
> + return;
> +
> + intel_dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
> + , len);
> +}
> +
> void intel_dp_set_infoframes(struct intel_encoder *encoder,
>bool enable,
>const struct intel_crtc_state *crtc_state, diff
> --git
> a/drivers/gpu/drm/i915/display/intel_dp.h
> b/drivers/gpu/drm/i915/display/intel_dp.h
> index 6562bb8edeba..5074e52722c0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -18,6 +18,7 @@ struct drm_connector_state; struct drm_encoder; struct
> drm_i915_private; struct drm_modeset_acquire_ctx;
> +struct drm_dp_vsc_sdp;
> struct intel_connector;
> struct intel_crtc_state;
> struct intel_digital_port;
> @@ -110,6 +111,13 @@ int intel_dp_link_required(int pixel_clock, int bpp);
> int
> intel_dp_max_data_rate(int max_link_clock, int max_lanes); bool
> intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
> const struct drm_connector_state *conn_state);
> +void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
> + const struct intel_crtc_state *crtc_state,
> + const struct drm_connector_state *conn_state,
> +
Re: [Intel-gfx] [PATCH v3 15/17] drm/i915: Stop sending DP SDPs on intel_ddi_post_disable_dp()
> -Original Message- > From: dri-devel On Behalf Of Gwan- > gyeong Mun > Sent: Tuesday, February 4, 2020 4:50 AM > To: intel-gfx@lists.freedesktop.org > Cc: linux-fb...@vger.kernel.org; dri-de...@lists.freedesktop.org > Subject: [PATCH v3 15/17] drm/i915: Stop sending DP SDPs on > intel_ddi_post_disable_dp() Just say " Stop sending DP SDPs on ddi disable" > Call intel_dp_set_infoframes(false) function on intel_ddi_post_disable_dp() > to make > sure not to send VSC SDP and HDR Metadata Infoframe SDP. With the above fixed. Reviewed-by: Uma Shankar > Signed-off-by: Gwan-gyeong Mun > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > b/drivers/gpu/drm/i915/display/intel_ddi.c > index 69073a15edb8..8509cd33569e 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -3713,6 +3713,8 @@ static void intel_ddi_post_disable_dp(struct > intel_encoder > *encoder, > INTEL_OUTPUT_DP_MST); > enum phy phy = intel_port_to_phy(dev_priv, encoder->port); > > + intel_dp_set_infoframes(encoder, false, old_crtc_state, > +old_conn_state); > + > /* >* Power down sink before disabling the port, otherwise we end >* up getting interrupts from the sink on detecting link loss. > -- > 2.24.1 > > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 14/17] drm/i915: Program DP SDPs on pipe updates
> -Original Message- > From: dri-devel On Behalf Of Gwan- > gyeong Mun > Sent: Tuesday, February 4, 2020 4:50 AM > To: intel-gfx@lists.freedesktop.org > Cc: linux-fb...@vger.kernel.org; dri-de...@lists.freedesktop.org > Subject: [PATCH v3 14/17] drm/i915: Program DP SDPs on pipe updates > > Call intel_dp_set_infoframes() function on pipe updates to make sure that we > send > VSC SDP and HDR Metadata Infoframe SDP (when applicable) on fastsets. Looks good to me. Reviewed-by: Uma Shankar > Signed-off-by: Gwan-gyeong Mun > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > b/drivers/gpu/drm/i915/display/intel_ddi.c > index 64e4edefa998..69073a15edb8 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -4062,6 +4062,7 @@ static void intel_ddi_update_pipe_dp(struct > intel_encoder > *encoder, > intel_ddi_set_dp_msa(crtc_state, conn_state); > > intel_psr_update(intel_dp, crtc_state); > + intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); > intel_edp_drrs_enable(intel_dp, crtc_state); > > intel_panel_update_backlight(encoder, crtc_state, conn_state); > -- > 2.24.1 > > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 13/17] drm/i915: Add state readout for DP VSC SDP
> -Original Message-
> From: dri-devel On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fb...@vger.kernel.org; dri-de...@lists.freedesktop.org
> Subject: [PATCH v3 13/17] drm/i915: Add state readout for DP VSC SDP
>
> Added state readout for DP VSC SDP and enabled state validation for DP VSC
> SDP.
>
> v2: Minor style fix
> v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
Looks good.
Reviewed-by: Uma Shankar
> Signed-off-by: Gwan-gyeong Mun
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
> drivers/gpu/drm/i915/display/intel_display.c | 42
> 2 files changed, 43 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index a9eaf7a6bc15..64e4edefa998 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4391,6 +4391,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
>_config->infoframes.drm);
>
> intel_read_dp_sdp(encoder, pipe_config,
> HDMI_PACKET_TYPE_GAMUT_METADATA);
> + intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
> }
>
> static enum intel_output_type
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 4f187fd330e8..02471c7aa6e7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -13503,6 +13503,13 @@ intel_compare_infoframe(const union
> hdmi_infoframe *a,
> return memcmp(a, b, sizeof(*a)) == 0;
> }
>
> +static bool
> +intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
> + const struct drm_dp_vsc_sdp *b)
> +{
> + return memcmp(a, b, sizeof(*a)) == 0;
> +}
> +
> static void
> pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
> bool fastset, const char *name, @@ -13528,6
> +13535,30 @@ pipe_config_infoframe_mismatch(struct drm_i915_private
> *dev_priv,
> }
> }
>
> +static void
> +pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
> + bool fastset, const char *name,
> + const struct drm_dp_vsc_sdp *a,
> + const struct drm_dp_vsc_sdp *b)
> +{
> + if (fastset) {
> + if (!drm_debug_enabled(DRM_UT_KMS))
> + return;
> +
> + DRM_DEBUG_KMS("fastset mismatch in %s dp sdp\n", name);
> + DRM_DEBUG_KMS("expected:\n");
> + drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
> + DRM_DEBUG_KMS("found:\n");
> + drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
> + } else {
> + DRM_ERROR("mismatch in %s dp sdp\n", name);
> + DRM_ERROR("expected:\n");
> + drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
> + DRM_ERROR("found:\n");
> + drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
> + }
> +}
> +
> static void __printf(4, 5)
> pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
>const char *name, const char *format, ...) @@ -13729,6
> +13760,16 @@ intel_pipe_config_compare(const struct intel_crtc_state
> *current_config,
> } \
> } while (0)
>
> +#define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
> + if (!intel_compare_dp_vsc_sdp(_config->infoframes.name, \
> + _config->infoframes.name)) { \
> + pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset,
> __stringify(name), \
> + _config-
> >infoframes.name, \
> + _config->infoframes.name);
> \
> + ret = false; \
> + } \
> +} while (0)
> +
> #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
> if (current_config->name1 != pipe_config->name1) { \
> pipe_config_mismatch(fastset, crtc, __stringify(name1), \ @@ -
> 13902,6 +13943,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
> *current_config,
> PIPE_CONF_CHECK_INFOFRAME(spd);
> PIPE_CONF_CHECK_INFOFRAME(hdmi);
> PIPE_CONF_CHECK_INFOFRAME(drm);
> + PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
>
> PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
> PIPE_CONF_CHECK_I(master_transcoder);
> --
> 2.24.1
>
> ___
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Re: [Intel-gfx] [PATCH v3 12/17] drm/i915: Add state readout for DP HDR Metadata Infoframe SDP
> -Original Message- > From: Intel-gfx On Behalf Of Gwan- > gyeong Mun > Sent: Tuesday, February 4, 2020 4:50 AM > To: intel-gfx@lists.freedesktop.org > Cc: linux-fb...@vger.kernel.org; dri-de...@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH v3 12/17] drm/i915: Add state readout for DP HDR > Metadata Infoframe SDP > > Added state readout for DP HDR Metadata Infoframe SDP. Looks good. Reviewed-by: Uma Shankar > Signed-off-by: Gwan-gyeong Mun > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 8 > 1 file changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > b/drivers/gpu/drm/i915/display/intel_ddi.c > index 374ab6a3757c..a9eaf7a6bc15 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -4322,6 +4322,9 @@ void intel_ddi_get_config(struct intel_encoder *encoder, > pipe_config->fec_enable); > } > > + pipe_config->infoframes.enable |= > + intel_hdmi_infoframes_enabled(encoder, pipe_config); > + > break; > case TRANS_DDI_MODE_SELECT_DP_MST: > pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); @@ - > 4333,6 +4336,9 @@ void intel_ddi_get_config(struct intel_encoder *encoder, > > REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); > > intel_dp_get_m_n(intel_crtc, pipe_config); > + > + pipe_config->infoframes.enable |= > + intel_hdmi_infoframes_enabled(encoder, pipe_config); > break; > default: > break; > @@ -4383,6 +4389,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder, > intel_read_infoframe(encoder, pipe_config, >HDMI_INFOFRAME_TYPE_DRM, >_config->infoframes.drm); > + > + intel_read_dp_sdp(encoder, pipe_config, > +HDMI_PACKET_TYPE_GAMUT_METADATA); > } > > static enum intel_output_type > -- > 2.24.1 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 11/17] drm/i915: Program DP SDPs with computed configs
> -Original Message-
> From: Intel-gfx On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fb...@vger.kernel.org; dri-de...@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3 11/17] drm/i915: Program DP SDPs with computed
> configs
>
> In order to use computed config for DP SDPs (DP VSC SDP and DP HDR Metadata
> Infoframe SDP), it replaces intel_dp_vsc_enable() function and
> intel_dp_hdr_metadata_enable() function to intel_dp_set_infoframes() function.
>
> Before applying it, routines of program SDP always calculated configs when
> they
> called. And it removes unused functions.
Fix the sentence, seems unclear.
With that fixed,
Reviewed-by: Uma Shankar
>
> v3: Rebased
>
> Signed-off-by: Gwan-gyeong Mun
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 3 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 226 ---
> drivers/gpu/drm/i915/display/intel_dp.h | 6 -
> 3 files changed, 1 insertion(+), 234 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index c96f629cddc3..374ab6a3757c 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3900,8 +3900,7 @@ static void intel_enable_ddi_dp(struct intel_encoder
> *encoder,
>
> intel_edp_backlight_on(crtc_state, conn_state);
> intel_psr_enable(intel_dp, crtc_state);
> - intel_dp_vsc_enable(intel_dp, crtc_state, conn_state);
> - intel_dp_hdr_metadata_enable(intel_dp, crtc_state, conn_state);
> + intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
> intel_edp_drrs_enable(intel_dp, crtc_state);
>
> if (crtc_state->has_audio)
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index d4ece0a824c0..cffb77daec96 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -5095,232 +5095,6 @@ void intel_read_dp_sdp(struct intel_encoder *encoder,
> }
> }
>
> -static void
> -intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
> -const struct intel_crtc_state *crtc_state,
> -const struct drm_connector_state *conn_state)
> -{
> - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> - struct dp_sdp vsc_sdp = {};
> -
> - /* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 */
> - vsc_sdp.sdp_header.HB0 = 0;
> - vsc_sdp.sdp_header.HB1 = 0x7;
> -
> - /*
> - * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> - * Colorimetry Format indication.
> - */
> - vsc_sdp.sdp_header.HB2 = 0x5;
> -
> - /*
> - * VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/
> - * Colorimetry Format indication (HB2 = 05h).
> - */
> - vsc_sdp.sdp_header.HB3 = 0x13;
> -
> - /* DP 1.4a spec, Table 2-120 */
> - switch (crtc_state->output_format) {
> - case INTEL_OUTPUT_FORMAT_YCBCR444:
> - vsc_sdp.db[16] = 0x1 << 4; /* YCbCr 444 : DB16[7:4] = 1h */
> - break;
> - case INTEL_OUTPUT_FORMAT_YCBCR420:
> - vsc_sdp.db[16] = 0x3 << 4; /* YCbCr 420 : DB16[7:4] = 3h */
> - break;
> - case INTEL_OUTPUT_FORMAT_RGB:
> - default:
> - /* RGB: DB16[7:4] = 0h */
> - break;
> - }
> -
> - switch (conn_state->colorspace) {
> - case DRM_MODE_COLORIMETRY_BT709_YCC:
> - vsc_sdp.db[16] |= 0x1;
> - break;
> - case DRM_MODE_COLORIMETRY_XVYCC_601:
> - vsc_sdp.db[16] |= 0x2;
> - break;
> - case DRM_MODE_COLORIMETRY_XVYCC_709:
> - vsc_sdp.db[16] |= 0x3;
> - break;
> - case DRM_MODE_COLORIMETRY_SYCC_601:
> - vsc_sdp.db[16] |= 0x4;
> - break;
> - case DRM_MODE_COLORIMETRY_OPYCC_601:
> - vsc_sdp.db[16] |= 0x5;
> - break;
> - case DRM_MODE_COLORIMETRY_BT2020_CYCC:
> - case DRM_MODE_COLORIMETRY_BT2020_RGB:
> - vsc_sdp.db[16] |= 0x6;
> - break;
> - case DRM_MODE_COLORIMETRY_BT2020_YCC:
> - vsc_sdp.db[16] |= 0x7;
> - break;
> - case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
> - case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
> - vsc_sdp.db[16] |= 0x4; /* DCI-P3 (SMPTE RP 431-2) */
> - break;
> - default:
> - /* sRGB (IEC 61966-2-1) / ITU-R BT.601: DB16[0:3] = 0h */
> -
> - /* RGB->YCBCR color conversion uses the BT.709 color space. */
> - if (crtc_state->output_format ==
> INTEL_OUTPUT_FORMAT_YCBCR420)
> - vsc_sdp.db[16] |= 0x1; /* 0x1, ITU-R BT.709 */
> - break;
> - }
> -
> - /*
> - * For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and Y Only,
> - * the following Component Bit Depth
Re: [Intel-gfx] [PATCH v3 10/17] drm/i915: Include DP VSC SDP in the crtc state dump
> -Original Message-
> From: dri-devel On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fb...@vger.kernel.org; dri-de...@lists.freedesktop.org
> Subject: [PATCH v3 10/17] drm/i915: Include DP VSC SDP in the crtc state dump
>
> Dump out the DP VSC SDP in the normal crtc state dump
>
> v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
> Use drm core's DP VSC SDP logging function
Looks good to me.
Reviewed-by: Uma Shankar
> Signed-off-by: Gwan-gyeong Mun
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 13 +
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 593c63f51210..4f187fd330e8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -12878,6 +12878,16 @@ intel_dump_infoframe(struct drm_i915_private
> *dev_priv,
> hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame); }
>
> +static void
> +intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv,
> + const struct drm_dp_vsc_sdp *vsc) {
> + if (!drm_debug_enabled(DRM_UT_KMS))
> + return;
> +
> + drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc); }
> +
> #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
>
> static const char * const output_type_str[] = { @@ -13036,6 +13046,9 @@
> static
> void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
> if (pipe_config->infoframes.enable &
> intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
> intel_dump_infoframe(dev_priv, _config->infoframes.drm);
> + if (pipe_config->infoframes.enable &
> + intel_hdmi_infoframe_enable(DP_SDP_VSC))
> + intel_dump_dp_vsc_sdp(dev_priv, _config->infoframes.vsc);
>
> drm_dbg_kms(_priv->drm, "requested mode:\n");
> drm_mode_debug_printmodeline(_config->hw.mode);
> --
> 2.24.1
>
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Re: [Intel-gfx] [PATCH v3 09/17] drm/i915: Include DP HDR Metadata Infoframe SDP in the crtc state dump
> -Original Message- > From: dri-devel On Behalf Of Gwan- > gyeong Mun > Sent: Tuesday, February 4, 2020 4:50 AM > To: intel-gfx@lists.freedesktop.org > Cc: linux-fb...@vger.kernel.org; dri-de...@lists.freedesktop.org > Subject: [PATCH v3 09/17] drm/i915: Include DP HDR Metadata Infoframe SDP in > the > crtc state dump > > Dump out the DP HDR Metadata Infoframe SDP in the normal crtc state dump. > > HDMI Dynamic Range and Mastering (DRM) infoframe and DP HDR Metadata > Infoframe SDP use the same member variable in infoframes of crtc state. Looks good to me. Reviewed-by: Uma Shankar > Signed-off-by: Gwan-gyeong Mun > --- > drivers/gpu/drm/i915/display/intel_display.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > b/drivers/gpu/drm/i915/display/intel_display.c > index 239861bcedba..593c63f51210 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -13033,6 +13033,9 @@ static void intel_dump_pipe_config(const struct > intel_crtc_state *pipe_config, > if (pipe_config->infoframes.enable & > intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM)) > intel_dump_infoframe(dev_priv, _config->infoframes.drm); > + if (pipe_config->infoframes.enable & > + intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA)) > + intel_dump_infoframe(dev_priv, _config->infoframes.drm); > > drm_dbg_kms(_priv->drm, "requested mode:\n"); > drm_mode_debug_printmodeline(_config->hw.mode); > -- > 2.24.1 > > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915/gem: Don't leak non-persistent requests on changing engines
Quoting Tvrtko Ursulin (2020-02-05 16:22:34)
>
>
> On 05/02/2020 12:13, Chris Wilson wrote:
> > If we have a set of active engines marked as being non-persistent, we
> > lose track of those if the user replaces those engines with
> > I915_CONTEXT_PARAM_ENGINES. As part of our uABI contract is that
> > non-persistent requests are terminated if they are no longer being
> > tracked by the user's context (in order to prevent a lost request
> > causing an untracked and so unstoppable GPU hang), we need to apply the
> > same context cancellation upon changing engines.
> >
> > Fixes: a0e047156cde ("drm/i915/gem: Make context persistence optional")
> > Testcase: XXX
> > Signed-off-by: Chris Wilson
> > Cc: Tvrtko Ursulin
> > ---
> > drivers/gpu/drm/i915/gem/i915_gem_context.c | 7 +++
> > 1 file changed, 7 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > index 52a749691a8d..20f1d3e0221f 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > @@ -1624,11 +1624,18 @@ set_engines(struct i915_gem_context *ctx,
> >
> > replace:
> > mutex_lock(>engines_mutex);
> > +
> > + /* Flush stale requests off the old engines if required */
> > + if (!i915_gem_context_is_persistent(ctx) ||
> > + !i915_modparams.enable_hangcheck)
> > + kill_context(ctx);
>
> Is the negative effect of this is legit contexts can't keep submitting
> and changing the map? Only if PREEMPT_TIMEOUT is disabled I think but
> still. Might break legitimate userspace. Not that I offer solutions.. :(
> Banning changing engines once context went non-persistent? That too can
> break someone.
It closes the hole we have. To do otherwise, we need to keep track of
the old engines. Not an impossible task, certainly inconvenient.
struct old_engines {
struct i915_active active;
struct list_head link;
struct i915_gem_context *ctx;
void *engines;
int num_engines;
};
With a list+spinlock in the ctx that we can work in kill_context.
The biggest catch there is actually worrying about attaching the active
to already executing request, and making sure the coupling doesn't bug
on a concurrent completion. Hmm, it's just a completion callback, but
more convenient to use a ready made one.
-Chris
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: align dumb buffer stride to page_sz of the region
== Series Details == Series: drm/i915: align dumb buffer stride to page_sz of the region URL : https://patchwork.freedesktop.org/series/73021/ State : success == Summary == CI Bug Log - changes from CI_DRM_7869 -> Patchwork_16433 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16433/index.html Known issues Here are the changes found in Patchwork_16433 that come from known issues: ### IGT changes ### Issues hit * igt@gem_close_race@basic-threads: - fi-byt-j1900: [PASS][1] -> [INCOMPLETE][2] ([i915#45]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-byt-j1900/igt@gem_close_r...@basic-threads.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16433/fi-byt-j1900/igt@gem_close_r...@basic-threads.html * igt@i915_selftest@live_blt: - fi-hsw-4770r: [PASS][3] -> [DMESG-FAIL][4] ([i915#563]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-hsw-4770r/igt@i915_selftest@live_blt.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16433/fi-hsw-4770r/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_gem_contexts: - fi-hsw-peppy: [PASS][5] -> [DMESG-FAIL][6] ([i915#722]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16433/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html * igt@kms_addfb_basic@bad-pitch-128: - fi-tgl-y: [PASS][7] -> [DMESG-WARN][8] ([CI#94] / [i915#402]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-tgl-y/igt@kms_addfb_ba...@bad-pitch-128.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16433/fi-tgl-y/igt@kms_addfb_ba...@bad-pitch-128.html Possible fixes * igt@gem_close_race@basic-threads: - fi-byt-n2820: [INCOMPLETE][9] ([i915#45]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-byt-n2820/igt@gem_close_r...@basic-threads.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16433/fi-byt-n2820/igt@gem_close_r...@basic-threads.html * igt@gem_exec_parallel@fds: - fi-icl-u3: [INCOMPLETE][11] -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-icl-u3/igt@gem_exec_paral...@fds.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16433/fi-icl-u3/igt@gem_exec_paral...@fds.html * igt@gem_exec_suspend@basic-s3: - fi-cml-s: [INCOMPLETE][13] ([i915#1078] / [i915#283]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-cml-s/igt@gem_exec_susp...@basic-s3.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16433/fi-cml-s/igt@gem_exec_susp...@basic-s3.html * igt@i915_getparams_basic@basic-subslice-total: - fi-tgl-y: [DMESG-WARN][15] ([CI#94] / [i915#402]) -> [PASS][16] +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16433/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html * igt@i915_module_load@reload: - fi-skl-6770hq: [DMESG-WARN][17] ([i915#92]) -> [PASS][18] +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-skl-6770hq/igt@i915_module_l...@reload.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16433/fi-skl-6770hq/igt@i915_module_l...@reload.html * igt@i915_selftest@live_blt: - fi-bsw-nick:[INCOMPLETE][19] ([i915#392]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-bsw-nick/igt@i915_selftest@live_blt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16433/fi-bsw-nick/igt@i915_selftest@live_blt.html - fi-ivb-3770:[DMESG-FAIL][21] ([i915#725]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-ivb-3770/igt@i915_selftest@live_blt.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16433/fi-ivb-3770/igt@i915_selftest@live_blt.html * igt@kms_chamelium@hdmi-crc-fast: - fi-kbl-7500u: [FAIL][23] ([fdo#109635] / [i915#217]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16433/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][25] ([fdo#111096] / [i915#323]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7869/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16433/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
Re: [Intel-gfx] [PATCH v3 08/17] drm/i915: Include HDMI DRM infoframe in the crtc state dump
> -Original Message- > From: dri-devel On Behalf Of Gwan- > gyeong Mun > Sent: Tuesday, February 4, 2020 4:50 AM > To: intel-gfx@lists.freedesktop.org > Cc: linux-fb...@vger.kernel.org; dri-de...@lists.freedesktop.org > Subject: [PATCH v3 08/17] drm/i915: Include HDMI DRM infoframe in the crtc > state > dump > > Dump out the HDMI Dynamic Range and Mastering (DRM) infoframe in the normal > crtc state dump. Looks good to me. Reviewed-by: Uma Shankar > Signed-off-by: Gwan-gyeong Mun > --- > drivers/gpu/drm/i915/display/intel_display.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > b/drivers/gpu/drm/i915/display/intel_display.c > index c0e5002ce64c..239861bcedba 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -13030,6 +13030,9 @@ static void intel_dump_pipe_config(const struct > intel_crtc_state *pipe_config, > if (pipe_config->infoframes.enable & > intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR)) > intel_dump_infoframe(dev_priv, _config->infoframes.hdmi); > + if (pipe_config->infoframes.enable & > + intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM)) > + intel_dump_infoframe(dev_priv, _config->infoframes.drm); > > drm_dbg_kms(_priv->drm, "requested mode:\n"); > drm_mode_debug_printmodeline(_config->hw.mode); > -- > 2.24.1 > > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 07/17] drm: Add logging function for DP VSC SDP
> -Original Message-
> From: Intel-gfx On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fb...@vger.kernel.org; dri-de...@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3 07/17] drm: Add logging function for DP VSC SDP
>
> When receiving video it is very useful to be able to log DP VSC SDP.
> This greatly simplifies debugging.
>
> v2: Minor style fix
> v3: Move logging functions to drm core [Jani N]
Looks good to me.
Reviewed-by: Uma Shankar
> Signed-off-by: Gwan-gyeong Mun
> ---
> drivers/gpu/drm/drm_dp_helper.c | 174
> include/drm/drm_dp_helper.h | 3 +
> 2 files changed, 177 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index 5a103e9b3c86..5e3aef8c32e0 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -1395,3 +1395,177 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8
> dsc_dpcd[DP_DSC_RECEIVER_CAP_S
> return num_bpc;
> }
> EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
> +
> +static const char *dp_colorspace_get_name(enum dp_colorspace
> +colorspace) {
> + if (colorspace < 0 || colorspace > DP_COLORSPACE_RESERVED)
> + return "Invalid";
> +
> + switch (colorspace) {
> + case DP_COLORSPACE_RGB:
> + return "RGB";
> + case DP_COLORSPACE_YUV444:
> + return "YUV444";
> + case DP_COLORSPACE_YUV422:
> + return "YUV422";
> + case DP_COLORSPACE_YUV420:
> + return "YUV420";
> + case DP_COLORSPACE_Y_ONLY:
> + return "Y_ONLY";
> + case DP_COLORSPACE_RAW:
> + return "RAW";
> + default:
> + return "Reserved";
> + }
> +}
> +
> +static const char *dp_colorimetry_get_name(enum dp_colorspace colorspace,
> +enum dp_colorimetry colorimetry) {
> + if (colorspace < 0 || colorspace > DP_COLORSPACE_RESERVED)
> + return "Invalid";
> +
> + switch (colorimetry) {
> + case DP_COLORIMETRY_DEFAULT:
> + switch (colorspace) {
> + case DP_COLORSPACE_RGB:
> + return "sRGB";
> + case DP_COLORSPACE_YUV444:
> + case DP_COLORSPACE_YUV422:
> + case DP_COLORSPACE_YUV420:
> + return "BT.601";
> + case DP_COLORSPACE_Y_ONLY:
> + return "DICOM PS3.14";
> + case DP_COLORSPACE_RAW:
> + return "Custom Color Profile";
> + default:
> + return "Reserved";
> + }
> + case DP_COLORIMETRY_RGB_WIDE_FIXED: /* and
> DP_COLORIMETRY_BT709_YCC */
> + switch (colorspace) {
> + case DP_COLORSPACE_RGB:
> + return "Wide Fixed";
> + case DP_COLORSPACE_YUV444:
> + case DP_COLORSPACE_YUV422:
> + case DP_COLORSPACE_YUV420:
> + return "BT.709";
> + default:
> + return "Reserved";
> + }
> + case DP_COLORIMETRY_RGB_WIDE_FLOAT: /* and
> DP_COLORIMETRY_XVYCC_601 */
> + switch (colorspace) {
> + case DP_COLORSPACE_RGB:
> + return "Wide Float";
> + case DP_COLORSPACE_YUV444:
> + case DP_COLORSPACE_YUV422:
> + case DP_COLORSPACE_YUV420:
> + return "xvYCC 601";
> + default:
> + return "Reserved";
> + }
> + case DP_COLORIMETRY_OPRGB: /* and DP_COLORIMETRY_XVYCC_709 */
> + switch (colorspace) {
> + case DP_COLORSPACE_RGB:
> + return "OpRGB";
> + case DP_COLORSPACE_YUV444:
> + case DP_COLORSPACE_YUV422:
> + case DP_COLORSPACE_YUV420:
> + return "xvYCC 709";
> + default:
> + return "Reserved";
> + }
> + case DP_COLORIMETRY_DCI_P3_RGB: /* and DP_COLORIMETRY_SYCC_601
> */
> + switch (colorspace) {
> + case DP_COLORSPACE_RGB:
> + return "DCI-P3";
> + case DP_COLORSPACE_YUV444:
> + case DP_COLORSPACE_YUV422:
> + case DP_COLORSPACE_YUV420:
> + return "sYCC 601";
> + default:
> + return "Reserved";
> + }
> + case DP_COLORIMETRY_RGB_CUSTOM: /* and
> DP_COLORIMETRY_OPYCC_601 */
> + switch (colorspace) {
> + case DP_COLORSPACE_RGB:
> + return "Custom Profile";
> + case DP_COLORSPACE_YUV444:
> + case DP_COLORSPACE_YUV422:
> + case DP_COLORSPACE_YUV420:
> + return "OpYCC 601";
> + default:
> + return "Reserved";
> + }
>
Re: [Intel-gfx] [PATCH v3 06/17] drm/i915/dp: Read out DP SDPs (Secondary Data Packet)
> -Original Message-
> From: dri-devel On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fb...@vger.kernel.org; dri-de...@lists.freedesktop.org
> Subject: [PATCH v3 06/17] drm/i915/dp: Read out DP SDPs (Secondary Data
> Packet)
Drop the content in bracket.
> It adds code to read the DP SDPs from the video DIP and unpack them into the
> crtc
> state.
>
> It adds routines that read out DP VSC SDP and DP HDR Metadata Infoframe SDP In
> order to unpack DP VSC SDP, it adds intel_dp_vsc_sdp_unpack() function.
> It follows DP 1.4a spec. [Table 2-116: VSC SDP Header Bytes] and [Table
> 2-117: VSC
> SDP Payload for DB16 through DB18]
>
> In order to unpack DP HDR Metadata Infoframe SDP, it adds
> intel_dp_hdr_metadata_infoframe_sdp_unpack(). And it follows DP 1.4a spec.
> ([Table 2-125: INFOFRAME SDP v1.2 Header Bytes] and [Table 2-126: INFOFRAME
> SDP v1.2 Payload Data Bytes - DB0 through DB31]) and CTA-861-G spec. [Table-42
> Dynamic Range and Mastering InfoFrame].
>
> A nameing rule and style of intel_read_dp_sdp() function references
Typo in naming.
> intel_read_infoframe() function of intel_hdmi.c
>
> v2: Minor style fix
> v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
>
> Signed-off-by: Gwan-gyeong Mun
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 170
> drivers/gpu/drm/i915/display/intel_dp.h | 3 +
> 2 files changed, 173 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index dd7e5588001e..d4ece0a824c0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4925,6 +4925,176 @@ void intel_dp_set_infoframes(struct intel_encoder
> *encoder,
> intel_write_dp_sdp(encoder, crtc_state,
> HDMI_PACKET_TYPE_GAMUT_METADATA); }
>
> +static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
> +const void *buffer, size_t size) {
> + const struct dp_sdp *sdp = buffer;
> +
> + if (size < sizeof(struct dp_sdp))
> + return -EINVAL;
> +
> + memset(vsc, 0, size);
> +
> + if (sdp->sdp_header.HB0 != 0)
> + return -EINVAL;
> +
> + if (sdp->sdp_header.HB1 != DP_SDP_VSC)
> + return -EINVAL;
> + vsc->sdp_type = sdp->sdp_header.HB1;
> +
> + if (sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) {
> + vsc->revision = sdp->sdp_header.HB2;
> + vsc->length = sdp->sdp_header.HB3;
> + } else if (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe) {
> + vsc->revision = sdp->sdp_header.HB2;
> + vsc->length = sdp->sdp_header.HB3;
> + } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
> + vsc->revision = sdp->sdp_header.HB2;
> + vsc->length = sdp->sdp_header.HB3;
The above 2 lines can be done unconditionally, may be combine the if checks.
> + vsc->colorspace = (sdp->db[16] >> 4) & 0xf;
> + vsc->colorimetry = sdp->db[16] & 0xf;
> + vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
> +
> + switch (sdp->db[17] & 0x7) {
> + case 0x1:
> + vsc->bpc = 8;
> + break;
> + case 0x2:
> + vsc->bpc = 10;
> + break;
> + case 0x3:
> + vsc->bpc = 12;
> + break;
> + case 0x4:
> + vsc->bpc = 16;
> + break;
> + default:
> + MISSING_CASE(sdp->db[17] & 0x7);
Handle 6bpc case as well.
> + return -EINVAL;
> + }
> +
> + vsc->content_type = sdp->db[18] & 0x7;
> + } else {
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static int
> +intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe
> *drm_infoframe,
> +const void *buffer, size_t size) {
> + int ret;
> +
> + const struct dp_sdp *sdp = buffer;
> +
> + if (size < sizeof(struct dp_sdp))
> + return -EINVAL;
> +
> + if (sdp->sdp_header.HB0 != 0)
> + return -EINVAL;
> +
> + if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
> + return -EINVAL;
> +
> + /*
> + * Least Significant Eight Bits of (Data Byte Count – 1)
> + * 1Dh (i.e., Data Byte Count = 30 bytes).
> + */
> + if (sdp->sdp_header.HB2 != 0x1D)
> + return -EINVAL;
> +
> + /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
> + if ((sdp->sdp_header.HB3 & 0x3) != 0)
> + return -EINVAL;
> +
> + /* INFOFRAME SDP Version Number */
> + if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
> + return -EINVAL;
> +
> + /* CTA
Re: [Intel-gfx] [PATCH v2] drm/i915/gem: Don't leak non-persistent requests on changing engines
On 05/02/2020 12:13, Chris Wilson wrote:
If we have a set of active engines marked as being non-persistent, we
lose track of those if the user replaces those engines with
I915_CONTEXT_PARAM_ENGINES. As part of our uABI contract is that
non-persistent requests are terminated if they are no longer being
tracked by the user's context (in order to prevent a lost request
causing an untracked and so unstoppable GPU hang), we need to apply the
same context cancellation upon changing engines.
Fixes: a0e047156cde ("drm/i915/gem: Make context persistence optional")
Testcase: XXX
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 52a749691a8d..20f1d3e0221f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1624,11 +1624,18 @@ set_engines(struct i915_gem_context *ctx,
replace:
mutex_lock(>engines_mutex);
+
+ /* Flush stale requests off the old engines if required */
+ if (!i915_gem_context_is_persistent(ctx) ||
+ !i915_modparams.enable_hangcheck)
+ kill_context(ctx);
Is the negative effect of this is legit contexts can't keep submitting
and changing the map? Only if PREEMPT_TIMEOUT is disabled I think but
still. Might break legitimate userspace. Not that I offer solutions.. :(
Banning changing engines once context went non-persistent? That too can
break someone.
Regards,
Tvrtko
+
if (args->size)
i915_gem_context_set_user_engines(ctx);
else
i915_gem_context_clear_user_engines(ctx);
set.engines = rcu_replace_pointer(ctx->engines, set.engines, 1);
+
mutex_unlock(>engines_mutex);
call_rcu(>rcu, free_engines_rcu);
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 05/17] video/hdmi: Add Unpack only function for DRM infoframe
> -Original Message-
> From: Intel-gfx On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fb...@vger.kernel.org; dri-de...@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3 05/17] video/hdmi: Add Unpack only function
> for DRM
> infoframe
>
> It adds an unpack only function for DRM infoframe for dynamic range and
> mastering
> infoframe readout.
> It unpacks the information data block contained in the binary buffer into a
> structured
> frame of the HDMI Dynamic Range and Mastering (DRM) information frame.
>
> In contrast to hdmi_drm_infoframe_unpack() function, it does not verify a
> checksum.
>
> It can be used for unpacking a DP HDR Metadata Infoframe SDP case.
> DP HDR Metadata Infoframe SDP uses the same Dynamic Range and Mastering
> (DRM) information (CTA-861-G spec.) such as HDMI DRM infoframe.
> But DP SDP header and payload structure are different from HDMI DRM Infoframe.
> Therefore unpacking DRM infoframe for DP requires skipping of a verifying
> checksum.
Looks good to me.
Reviewed-by: Uma Shankar
> Signed-off-by: Gwan-gyeong Mun
> ---
> drivers/video/hdmi.c | 58 +++-
> include/linux/hdmi.h | 2 ++
> 2 files changed, 43 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c index
> 9c82e2a0a411..9818836d82b7 100644
> --- a/drivers/video/hdmi.c
> +++ b/drivers/video/hdmi.c
> @@ -1775,20 +1775,18 @@ hdmi_vendor_any_infoframe_unpack(union
> hdmi_vendor_any_infoframe *frame, }
>
> /**
> - * hdmi_drm_infoframe_unpack() - unpack binary buffer to a HDMI DRM infoframe
> + * hdmi_drm_infoframe_unpack_only() - unpack binary buffer to a HDMI
> + DRM infoframe
> * @frame: HDMI DRM infoframe
> * @buffer: source buffer
> * @size: size of buffer
> *
> - * Unpacks the information contained in binary @buffer into a structured
> + * Unpacks the information data block contained in binary @buffer into
> + a structured
> * @frame of the HDMI Dynamic Range and Mastering (DRM) information frame.
> - * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4
> - * specification.
> *
> * Returns 0 on success or a negative error code on failure.
> */
> -static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
> - const void *buffer, size_t size)
> +int hdmi_drm_infoframe_unpack_only(struct hdmi_drm_infoframe *frame,
> +const void *buffer, size_t size)
> {
> const u8 *ptr = buffer;
> const u8 *temp;
> @@ -1797,23 +1795,13 @@ static int hdmi_drm_infoframe_unpack(struct
> hdmi_drm_infoframe *frame,
> int ret;
> int i;
>
> - if (size < HDMI_INFOFRAME_SIZE(DRM))
> - return -EINVAL;
> -
> - if (ptr[0] != HDMI_INFOFRAME_TYPE_DRM ||
> - ptr[1] != 1 ||
> - ptr[2] != HDMI_DRM_INFOFRAME_SIZE)
> - return -EINVAL;
> -
> - if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(DRM)) != 0)
> + if (size < HDMI_DRM_INFOFRAME_SIZE)
> return -EINVAL;
>
> ret = hdmi_drm_infoframe_init(frame);
> if (ret)
> return ret;
>
> - ptr += HDMI_INFOFRAME_HEADER_SIZE;
> -
> frame->eotf = ptr[0] & 0x7;
> frame->metadata_type = ptr[1] & 0x7;
>
> @@ -1837,6 +1825,42 @@ static int hdmi_drm_infoframe_unpack(struct
> hdmi_drm_infoframe *frame,
>
> return 0;
> }
> +EXPORT_SYMBOL(hdmi_drm_infoframe_unpack_only);
> +
> +/**
> + * hdmi_drm_infoframe_unpack() - unpack binary buffer to a HDMI DRM
> +infoframe
> + * @frame: HDMI DRM infoframe
> + * @buffer: source buffer
> + * @size: size of buffer
> + *
> + * Unpacks the information contained in binary @buffer into a
> +structured
> + * @frame of the HDMI Dynamic Range and Mastering (DRM) information frame.
> + * Also verifies the checksum as required by section 5.3.5 of the HDMI
> +1.4
> + * specification.
> + *
> + * Returns 0 on success or a negative error code on failure.
> + */
> +static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
> + const void *buffer, size_t size) {
> + const u8 *ptr = buffer;
> + int ret;
> +
> + if (size < HDMI_INFOFRAME_SIZE(DRM))
> + return -EINVAL;
> +
> + if (ptr[0] != HDMI_INFOFRAME_TYPE_DRM ||
> + ptr[1] != 1 ||
> + ptr[2] != HDMI_DRM_INFOFRAME_SIZE)
> + return -EINVAL;
> +
> + if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(DRM)) != 0)
> + return -EINVAL;
> +
> + ret = hdmi_drm_infoframe_unpack_only(frame, ptr +
> HDMI_INFOFRAME_HEADER_SIZE,
> + size - HDMI_INFOFRAME_HEADER_SIZE);
> + return ret;
> +}
>
> /**
> * hdmi_infoframe_unpack() - unpack binary buffer to a HDMI infoframe diff
> --git
> a/include/linux/hdmi.h b/include/linux/hdmi.h index
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/display: Defer application of initial chv_phy_control
== Series Details == Series: series starting with [1/3] drm/i915/display: Defer application of initial chv_phy_control URL : https://patchwork.freedesktop.org/series/72905/ State : success == Summary == CI Bug Log - changes from CI_DRM_7857_full -> Patchwork_16389_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_16389_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_busy@busy-vcs1: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#112080]) +11 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb4/igt@gem_b...@busy-vcs1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16389/shard-iclb6/igt@gem_b...@busy-vcs1.html * igt@gem_ctx_isolation@rcs0-s3: - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +9 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-kbl6/igt@gem_ctx_isolat...@rcs0-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16389/shard-kbl4/igt@gem_ctx_isolat...@rcs0-s3.html * igt@gem_exec_schedule@independent-bsd2: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276]) +20 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb2/igt@gem_exec_sched...@independent-bsd2.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16389/shard-iclb7/igt@gem_exec_sched...@independent-bsd2.html * igt@gem_exec_schedule@reorder-wide-bsd: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#112146]) +7 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb3/igt@gem_exec_sched...@reorder-wide-bsd.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16389/shard-iclb2/igt@gem_exec_sched...@reorder-wide-bsd.html * igt@gem_partial_pwrite_pread@write: - shard-hsw: [PASS][9] -> [FAIL][10] ([i915#694]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-hsw5/igt@gem_partial_pwrite_pr...@write.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16389/shard-hsw2/igt@gem_partial_pwrite_pr...@write.html * igt@gem_softpin@noreloc-s3: - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#180]) +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-apl3/igt@gem_soft...@noreloc-s3.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16389/shard-apl6/igt@gem_soft...@noreloc-s3.html * igt@gen9_exec_parse@allowed-single: - shard-skl: [PASS][13] -> [TIMEOUT][14] ([i915#716]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl4/igt@gen9_exec_pa...@allowed-single.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16389/shard-skl3/igt@gen9_exec_pa...@allowed-single.html * igt@kms_color@pipe-b-ctm-0-5: - shard-skl: [PASS][15] -> [DMESG-WARN][16] ([i915#109]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl2/igt@kms_co...@pipe-b-ctm-0-5.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16389/shard-skl5/igt@kms_co...@pipe-b-ctm-0-5.html * igt@kms_flip@2x-flip-vs-expired-vblank: - shard-glk: [PASS][17] -> [FAIL][18] ([i915#79]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-glk3/igt@kms_f...@2x-flip-vs-expired-vblank.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16389/shard-glk8/igt@kms_f...@2x-flip-vs-expired-vblank.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#79]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl10/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16389/shard-skl6/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_flip@plain-flip-fb-recreate-interruptible: - shard-skl: [PASS][21] -> [FAIL][22] ([i915#34]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl6/igt@kms_f...@plain-flip-fb-recreate-interruptible.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16389/shard-skl10/igt@kms_f...@plain-flip-fb-recreate-interruptible.html * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-blt: - shard-tglb: [PASS][23] -> [SKIP][24] ([i915#668]) +5 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-tglb8/igt@kms_frontbuffer_track...@psr-rgb101010-draw-blt.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16389/shard-tglb3/igt@kms_frontbuffer_track...@psr-rgb101010-draw-blt.html * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping: - shard-snb: [PASS][25] -> [SKIP][26] ([fdo#109271]) [25]:
Re: [Intel-gfx] [PATCH v3 04/17] drm/i915/dp: Add writing of DP SDPs (Secondary Data Packet)
> -Original Message-
> From: dri-devel On Behalf Of Gwan-
> gyeong Mun
> Sent: Tuesday, February 4, 2020 4:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: linux-fb...@vger.kernel.org; dri-de...@lists.freedesktop.org
> Subject: [PATCH v3 04/17] drm/i915/dp: Add writing of DP SDPs (Secondary Data
> Packet)
Drop things in (), not needed.
> It adds routines that write DP VSC SDP and DP HDR Metadata Infoframe SDP.
> In order to pack DP VSC SDP, it adds intel_dp_vsc_sdp_pack() function.
> It follows DP 1.4a spec. [Table 2-116: VSC SDP Header Bytes] and [Table
> 2-117: VSC
> SDP Payload for DB16 through DB18]
>
> In order to pack DP HDR Metadata Infoframe SDP, it adds
> intel_dp_hdr_metadata_infoframe_sdp_pack() function.
> And it follows DP 1.4a spec.
> ([Table 2-125: INFOFRAME SDP v1.2 Header Bytes] and [Table 2-126: INFOFRAME
> SDP v1.2 Payload Data Bytes - DB0 through DB31]) and CTA-861-G spec. [Table-42
> Dynamic Range and Mastering InfoFrame].
>
> A machanism and a naming rule of intel_dp_set_infoframes() function references
Typo in mechanism.
> intel_encoder->set_infoframes() of intel_hdmi.c .
> VSC SDP is used for PSR and Pixel Encoding and Colorimetry Formats cases.
> Because PSR routine has its own routine of writing a VSC SDP, when the PSR is
> enabled, intel_dp_set_infoframes() does not write a VSC SDP.
>
> v3:
> - Explicitly disable unused DIPs (AVI, GCP, VS, SPD, DRM. They will be
> used for HDMI), when intel_dp_set_infoframes() function will be called.
> - Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp.
>
> Signed-off-by: Gwan-gyeong Mun
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 194
> drivers/gpu/drm/i915/display/intel_dp.h | 3 +
> 2 files changed, 197 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index b265b5c599f2..dd7e5588001e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4731,6 +4731,200 @@ intel_dp_needs_vsc_sdp(const struct intel_crtc_state
> *crtc_state,
> return false;
> }
>
> +static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
> + struct dp_sdp *sdp, size_t size) {
> + size_t length = sizeof(struct dp_sdp);
> +
> + if (size < length)
> + return -ENOSPC;
> +
> + memset(sdp, 0, size);
> +
> + /*
> + * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
> + * VSC SDP Header Bytes
> + */
> + sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
> + sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
> + sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
> + sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
> +
> + /* VSC SDP Payload for DB16 through DB18 */
> + /* Pixel Encoding and Colorimetry Formats */
> + sdp->db[16] = (vsc->colorspace & 0xf) << 4; /* DB16[7:4] */
> + sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
> +
> + switch (vsc->bpc) {
> + case 8:
> + sdp->db[17] = 0x1; /* DB17[3:0] */
> + break;
> + case 10:
> + sdp->db[17] = 0x2;
> + break;
> + case 12:
> + sdp->db[17] = 0x3;
> + break;
> + case 16:
> + sdp->db[17] = 0x4;
> + break;
> + default:
> + MISSING_CASE(vsc->bpc);
6bpc is not handled here, add that as well.
> + break;
> + }
> + /* Dynamic Range and Component Bit Depth */
> + if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
> + sdp->db[17] |= 0x80; /* DB17[7] */
> +
> + /* Content Type */
> + sdp->db[18] = vsc->content_type & 0x7;
> +
> + return length;
> +}
> +
> +static ssize_t
> +intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe
> *drm_infoframe,
> + struct dp_sdp *sdp,
> + size_t size)
> +{
> + size_t length = sizeof(struct dp_sdp);
> + const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE +
> HDMI_DRM_INFOFRAME_SIZE;
> + unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE +
> HDMI_DRM_INFOFRAME_SIZE];
> + ssize_t len;
> +
> + if (size < length)
> + return -ENOSPC;
> +
> + memset(sdp, 0, size);
> +
> + len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
> + if (len < 0) {
> + DRM_DEBUG_KMS("buffer size is smaller than hdr metadata
> infoframe\n");
> + return -ENOSPC;
> + }
> +
> + if (len != infoframe_size) {
> + DRM_DEBUG_KMS("wrong static hdr metadata size\n");
> + return -ENOSPC;
> + }
> +
> + /*
> + * Set up the infoframe sdp packet for HDR static metadata.
> + * Prepare VSC Header for SU as per DP 1.4a spec,
> + * Table 2-100 and Table 2-101
>
Re: [Intel-gfx] [PATCH i-g-t] i915/gem_ctx_persistence: Check that we cannot hide hangs on old engines
On 05/02/2020 13:48, Chris Wilson wrote:
As the kernel loses track of the context's old engines, if we request
that the context is non-persistent then any request on the untracked
engines must be cancelled.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
tests/i915/gem_ctx_persistence.c | 60 +++-
1 file changed, 59 insertions(+), 1 deletion(-)
diff --git a/tests/i915/gem_ctx_persistence.c b/tests/i915/gem_ctx_persistence.c
index c54797e9b..04a6c179e 100644
--- a/tests/i915/gem_ctx_persistence.c
+++ b/tests/i915/gem_ctx_persistence.c
@@ -761,6 +761,49 @@ static void smoketest(int i915)
gem_quiescent_gpu(i915);
}
+static void replace_engines_hostile(int i915,
+ const struct intel_execution_engine2 *e)
+{
+ I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = {
+ .engines = {{ e->class, e->instance }}
+ };
+ struct drm_i915_gem_context_param param = {
+ .ctx_id = gem_context_create(i915),
+ .param = I915_CONTEXT_PARAM_ENGINES,
+ .value = to_user_pointer(),
+ .size = sizeof(engines),
+ };
+ igt_spin_t *spin[2];
+ int64_t timeout;
+
+ /*
+* Suppose the user tries to hide a hanging batch by replacing
+* the set of engines on the context so that it's not visible
+* at the time of closure? Then we must act when they replace
+* the engines!
+*/
+
+ gem_context_set_persistence(i915, param.ctx_id, false);
+
+ gem_context_set_param(i915, );
+ spin[0] = igt_spin_new(i915, param.ctx_id);
+
+ gem_context_set_param(i915, );
+ spin[1] = igt_spin_new(i915, param.ctx_id);
+
+ gem_context_destroy(i915, param.ctx_id);
At this point context_close() -> kill_context() but spin[0]
intel_context no longer in ctx->engines so hangs. spin[1] is terminated.
+
+ timeout = reset_timeout_ms * NSEC_PER_MSEC;
+ igt_assert_eq(gem_wait(i915, spin[1]->handle, ), 0);
+
+ timeout = reset_timeout_ms * NSEC_PER_MSEC;
+ igt_assert_eq(gem_wait(i915, spin[0]->handle, ), 0);
+
+ igt_spin_free(i915, spin[1]);
+ igt_spin_free(i915, spin[0]);
+ gem_quiescent_gpu(i915);
+}
+
int i915;
static void exit_handler(int sig)
@@ -793,10 +836,10 @@ igt_main
igt_assert(igt_sysfs_set_parameter
(i915, "reset", "%d", -1 /* any [default] reset */));
- igt_require(has_persistence(i915));
enable_hangcheck(i915);
igt_install_exit_handler(exit_handler);
+ igt_require(has_persistence(i915));
igt_allow_hang(i915, 0, 0);
}
@@ -861,6 +904,21 @@ igt_main
smoketest(i915);
}
+ /* Check interactions with set-engines */
+ igt_subtest_group {
+ const struct intel_execution_engine2 *e;
+
+ igt_fixture
+ gem_require_contexts(i915);
+
+ igt_subtest_with_dynamic("replace-hostile") {
+ __for_each_physical_engine(i915, e) {
+ igt_dynamic_f("%s", e->name)
+ replace_engines_hostile(i915, e);
+ }
+ }
+ }
+
igt_fixture {
close(i915);
}
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
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