[Intel-gfx] [PATCH 1/3] kernel: move use_mm/unuse_mm to kthread.c
These helpers are only for use with kernel threads, and I will tie them more into the kthread infrastructure going forward. Also move the prototypes to kthread.h - mmu_context.h was a little weird to start with as it otherwise contains very low-level MM bits. Signed-off-by: Christoph Hellwig Acked-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h| 1 + .../drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c | 1 - .../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c| 1 - .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 2 - .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 2 - .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 2 - drivers/gpu/drm/i915/gvt/kvmgt.c | 2 +- drivers/usb/gadget/function/f_fs.c| 2 +- drivers/usb/gadget/legacy/inode.c | 2 +- drivers/vfio/vfio_iommu_type1.c | 2 +- drivers/vhost/vhost.c | 1 - fs/aio.c | 1 - fs/io-wq.c| 1 - fs/io_uring.c | 1 - include/linux/kthread.h | 5 ++ include/linux/mmu_context.h | 5 -- kernel/kthread.c | 56 mm/Makefile | 2 +- mm/mmu_context.c | 64 --- 19 files changed, 67 insertions(+), 86 deletions(-) delete mode 100644 mm/mmu_context.c diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 13feb313e9b3..b820c8fc689f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -27,6 +27,7 @@ #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c index 6529caca88fe..35d4a5ab0228 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include "amdgpu.h" #include "amdgpu_amdkfd.h" diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c index 4ec6d0c03201..b1655054b919 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c @@ -19,7 +19,6 @@ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ -#include #include "amdgpu.h" #include "amdgpu_amdkfd.h" #include "gc/gc_10_1_0_offset.h" diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c index 0b7e78748540..7d01420c0c85 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c @@ -20,8 +20,6 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include - #include "amdgpu.h" #include "amdgpu_amdkfd.h" #include "cikd.h" diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c index ccd635b812b5..635cd1a26bed 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c @@ -20,8 +20,6 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include - #include "amdgpu.h" #include "amdgpu_amdkfd.h" #include "gfx_v8_0.h" diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c index df841c2ac5e7..c7fd0c47b254 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c @@ -19,8 +19,6 @@ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ -#include - #include "amdgpu.h" #include "amdgpu_amdkfd.h" #include "gc/gc_9_0_offset.h" diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c index 074c4efb58eb..ca1dd6e6f395 100644 --- a/drivers/gpu/drm/i915/gvt/kvmgt.c +++ b/drivers/gpu/drm/i915/gvt/kvmgt.c @@ -31,7 +31,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/usb/gadget/function/f_fs.c b/drivers/usb/gadget/function/f_fs.c index c81023b195c3..c57b1b2507c6 100644 --- a/drivers/usb/gadget/function/f_fs.c +++ b/drivers/usb/gadget/function/f_fs.c @@ -32,7 +32,7 @@ #include #include -#include +#include #include #include diff --git a/drivers/usb/gadget/legacy/inode.c b/drivers/usb/gadget/legacy/inode.c index aa0de9e35afa..8b5233888bf8 100644 --- a/drivers/usb/gadget/legacy/inode.c +++ b/drivers/usb/gadget/legacy/inode.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/vfio/vfio_iommu_type1.c
[Intel-gfx] improve use_mm / unuse_mm v2
Hi all, this series improves the use_mm / unuse_mm interface by better documenting the assumptions, and my taking the set_fs manipulations spread over the callers into the core API. Changes since v1: - drop a few patches - fix a comment typo - cover the newly merged use_mm/unuse_mm caller in vfio ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/3] kernel: better document the use_mm/unuse_mm API contract
Switch the function documentation to kerneldoc comments, and add
WARN_ON_ONCE asserts that the calling thread is a kernel thread and
does not have ->mm set (or has ->mm set in the case of unuse_mm).
Also give the functions a kthread_ prefix to better document the
use case.
Signed-off-by: Christoph Hellwig
Acked-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 4 +--
drivers/gpu/drm/i915/gvt/kvmgt.c | 4 +--
drivers/usb/gadget/function/f_fs.c | 4 +--
drivers/usb/gadget/legacy/inode.c | 4 +--
drivers/vfio/vfio_iommu_type1.c| 4 +--
drivers/vhost/vhost.c | 4 +--
fs/io-wq.c | 6 ++--
fs/io_uring.c | 6 ++--
include/linux/kthread.h| 4 +--
kernel/kthread.c | 33 +++---
mm/oom_kill.c | 6 ++--
mm/vmacache.c | 4 +--
12 files changed, 41 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index b820c8fc689f..b063bd7f41d8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -192,9 +192,9 @@ uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev
*dst, struct kgd_dev *s
if ((mmptr) == current->mm) { \
valid = !get_user((dst), (wptr)); \
} else if (current->mm == NULL) { \
- use_mm(mmptr); \
+ kthread_use_mm(mmptr); \
valid = !get_user((dst), (wptr)); \
- unuse_mm(mmptr);\
+ kthread_unuse_mm(mmptr);\
} \
pagefault_enable(); \
} \
diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index ca1dd6e6f395..f2927575b793 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -2048,7 +2048,7 @@ static int kvmgt_rw_gpa(unsigned long handle, unsigned
long gpa,
if (kthread) {
if (!mmget_not_zero(kvm->mm))
return -EFAULT;
- use_mm(kvm->mm);
+ kthread_use_mm(kvm->mm);
}
idx = srcu_read_lock(>srcu);
@@ -2057,7 +2057,7 @@ static int kvmgt_rw_gpa(unsigned long handle, unsigned
long gpa,
srcu_read_unlock(>srcu, idx);
if (kthread) {
- unuse_mm(kvm->mm);
+ kthread_unuse_mm(kvm->mm);
mmput(kvm->mm);
}
diff --git a/drivers/usb/gadget/function/f_fs.c
b/drivers/usb/gadget/function/f_fs.c
index c57b1b2507c6..d9e48bd7c692 100644
--- a/drivers/usb/gadget/function/f_fs.c
+++ b/drivers/usb/gadget/function/f_fs.c
@@ -827,9 +827,9 @@ static void ffs_user_copy_worker(struct work_struct *work)
mm_segment_t oldfs = get_fs();
set_fs(USER_DS);
- use_mm(io_data->mm);
+ kthread_use_mm(io_data->mm);
ret = ffs_copy_to_iter(io_data->buf, ret, _data->data);
- unuse_mm(io_data->mm);
+ kthread_unuse_mm(io_data->mm);
set_fs(oldfs);
}
diff --git a/drivers/usb/gadget/legacy/inode.c
b/drivers/usb/gadget/legacy/inode.c
index 8b5233888bf8..a05552bc2ff8 100644
--- a/drivers/usb/gadget/legacy/inode.c
+++ b/drivers/usb/gadget/legacy/inode.c
@@ -462,9 +462,9 @@ static void ep_user_copy_worker(struct work_struct *work)
struct kiocb *iocb = priv->iocb;
size_t ret;
- use_mm(mm);
+ kthread_use_mm(mm);
ret = copy_to_iter(priv->buf, priv->actual, >to);
- unuse_mm(mm);
+ kthread_unuse_mm(mm);
if (!ret)
ret = -EFAULT;
diff --git a/drivers/vfio/vfio_iommu_type1.c b/drivers/vfio/vfio_iommu_type1.c
index 5f50866a8b01..2eb105aa9723 100644
--- a/drivers/vfio/vfio_iommu_type1.c
+++ b/drivers/vfio/vfio_iommu_type1.c
@@ -2333,7 +2333,7 @@ static int vfio_iommu_type1_dma_rw_chunk(struct
vfio_iommu *iommu,
return -EPERM;
if (kthread)
- use_mm(mm);
+ kthread_use_mm(mm);
else if (current->mm != mm)
goto out;
@@ -2351,7 +2351,7 @@ static int vfio_iommu_type1_dma_rw_chunk(struct
vfio_iommu *iommu,
*copied = __copy_from_user(data, (void __user *)vaddr,
count) ? 0 : count;
if (kthread)
- unuse_mm(mm);
+ kthread_unuse_mm(mm);
out:
[Intel-gfx] [PATCH 3/3] kernel: set USER_DS in kthread_use_mm
Some architectures like arm64 and s390 require USER_DS to be set for
kernel threads to access user address space, which is the whole purpose
of kthread_use_mm, but other like x86 don't. That has lead to a huge
mess where some callers are fixed up once they are tested on said
architectures, while others linger around and yet other like io_uring
try to do "clever" optimizations for what usually is just a trivial
asignment to a member in the thread_struct for most architectures.
Make kthread_use_mm set USER_DS, and kthread_unuse_mm restore to the
previous value instead.
Signed-off-by: Christoph Hellwig
Acked-by: Michael S. Tsirkin [vhost]
---
drivers/usb/gadget/function/f_fs.c | 4
drivers/vhost/vhost.c | 3 ---
fs/io-wq.c | 8 ++--
fs/io_uring.c | 4
kernel/kthread.c | 6 ++
5 files changed, 8 insertions(+), 17 deletions(-)
diff --git a/drivers/usb/gadget/function/f_fs.c
b/drivers/usb/gadget/function/f_fs.c
index d9e48bd7c692..a1198f4c527c 100644
--- a/drivers/usb/gadget/function/f_fs.c
+++ b/drivers/usb/gadget/function/f_fs.c
@@ -824,13 +824,9 @@ static void ffs_user_copy_worker(struct work_struct *work)
bool kiocb_has_eventfd = io_data->kiocb->ki_flags & IOCB_EVENTFD;
if (io_data->read && ret > 0) {
- mm_segment_t oldfs = get_fs();
-
- set_fs(USER_DS);
kthread_use_mm(io_data->mm);
ret = ffs_copy_to_iter(io_data->buf, ret, _data->data);
kthread_unuse_mm(io_data->mm);
- set_fs(oldfs);
}
io_data->kiocb->ki_complete(io_data->kiocb, ret, ret);
diff --git a/drivers/vhost/vhost.c b/drivers/vhost/vhost.c
index 17d598e74780..b2abfbdf3cb2 100644
--- a/drivers/vhost/vhost.c
+++ b/drivers/vhost/vhost.c
@@ -329,9 +329,7 @@ static int vhost_worker(void *data)
struct vhost_dev *dev = data;
struct vhost_work *work, *work_next;
struct llist_node *node;
- mm_segment_t oldfs = get_fs();
- set_fs(USER_DS);
kthread_use_mm(dev->mm);
for (;;) {
@@ -361,7 +359,6 @@ static int vhost_worker(void *data)
}
}
kthread_unuse_mm(dev->mm);
- set_fs(oldfs);
return 0;
}
diff --git a/fs/io-wq.c b/fs/io-wq.c
index 748621f7391e..a5e90ac39e4d 100644
--- a/fs/io-wq.c
+++ b/fs/io-wq.c
@@ -169,7 +169,6 @@ static bool __io_worker_unuse(struct io_wqe *wqe, struct
io_worker *worker)
dropped_lock = true;
}
__set_current_state(TASK_RUNNING);
- set_fs(KERNEL_DS);
kthread_unuse_mm(worker->mm);
mmput(worker->mm);
worker->mm = NULL;
@@ -421,14 +420,11 @@ static void io_wq_switch_mm(struct io_worker *worker,
struct io_wq_work *work)
mmput(worker->mm);
worker->mm = NULL;
}
- if (!work->mm) {
- set_fs(KERNEL_DS);
+ if (!work->mm)
return;
- }
+
if (mmget_not_zero(work->mm)) {
kthread_use_mm(work->mm);
- if (!worker->mm)
- set_fs(USER_DS);
worker->mm = work->mm;
/* hang on to this mm */
work->mm = NULL;
diff --git a/fs/io_uring.c b/fs/io_uring.c
index 8a8148512da7..40f90b98a18a 100644
--- a/fs/io_uring.c
+++ b/fs/io_uring.c
@@ -5908,15 +5908,12 @@ static int io_sq_thread(void *data)
struct io_ring_ctx *ctx = data;
struct mm_struct *cur_mm = NULL;
const struct cred *old_cred;
- mm_segment_t old_fs;
DEFINE_WAIT(wait);
unsigned long timeout;
int ret = 0;
complete(>completions[1]);
- old_fs = get_fs();
- set_fs(USER_DS);
old_cred = override_creds(ctx->creds);
timeout = jiffies + ctx->sq_thread_idle;
@@ -6023,7 +6020,6 @@ static int io_sq_thread(void *data)
if (current->task_works)
task_work_run();
- set_fs(old_fs);
if (cur_mm) {
kthread_unuse_mm(cur_mm);
mmput(cur_mm);
diff --git a/kernel/kthread.c b/kernel/kthread.c
index 8ed4b4fbec7c..86357cd38eb2 100644
--- a/kernel/kthread.c
+++ b/kernel/kthread.c
@@ -52,6 +52,7 @@ struct kthread {
unsigned long flags;
unsigned int cpu;
void *data;
+ mm_segment_t oldfs;
struct completion parked;
struct completion exited;
#ifdef CONFIG_BLK_CGROUP
@@ -1235,6 +1236,9 @@ void kthread_use_mm(struct mm_struct *mm)
if (active_mm != mm)
mmdrop(active_mm);
+
+ to_kthread(tsk)->oldfs = get_fs();
+ set_fs(USER_DS);
}
EXPORT_SYMBOL_GPL(kthread_use_mm);
@@ -1249,6 +1253,8 @@ void kthread_unuse_mm(struct mm_struct *mm)
WARN_ON_ONCE(!(tsk->flags & PF_KTHREAD));
WARN_ON_ONCE(!tsk->mm);
+ set_fs(to_kthread(tsk)->oldfs);
+
[Intel-gfx] ✗ Fi.CI.BUILD: failure for sna: fix --enable-debug=full
== Series Details == Series: sna: fix --enable-debug=full URL : https://patchwork.freedesktop.org/series/76002/ State : failure == Summary == Applying: sna: fix --enable-debug=full error: sha1 information is lacking or useless (src/sna/compiler.h). error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0001 sna: fix --enable-debug=full When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [patch xf86-video-intel] sna: fix --enable-debug=full
From: Alexei Podtelezhnikov
Once a typo is fixed, the debug build triggers an assertion failure.
Given that the normal build is just fine, the assert might be wrong.
Signed-off-by: Alexei Podtelezhnikov
---
src/sna/compiler.h | 2 +-
src/sna/sna_accel.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/sna/compiler.h b/src/sna/compiler.h
index 2e579b15..c3d98797 100644
--- a/src/sna/compiler.h
+++ b/src/sna/compiler.h
@@ -50,7 +50,7 @@
#define must_check
#define constant
#define pure
-#define tighly_packed
+#define tightly_packed
#define flatten
#define nonnull
#define page_aligned
diff --git a/src/sna/sna_accel.c b/src/sna/sna_accel.c
index ee857a14..bf1edec8 100644
--- a/src/sna/sna_accel.c
+++ b/src/sna/sna_accel.c
@@ -17410,7 +17410,7 @@ void sna_accel_flush(struct sna *sna)
assert(!priv->flush);
ret = sna_pixmap_move_to_cpu(priv->pixmap,
MOVE_READ | MOVE_WRITE);
- assert(!ret || priv->gpu_bo == NULL);
+ assert(ret || priv->gpu_bo == NULL);
if (priv->pixmap->refcnt == 0) {
sna_damage_destroy(>cpu_damage);
__sna_free_pixmap(sna, priv->pixmap, priv);
--
2.26
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] drm/i915/display: Load DP_TP_CTL/STATUS offset before use it
On Tue, Apr 14, 2020 at 04:04:40PM -0700, José Roberto de Souza wrote:
> Right now dp.regs.dp_tp_ctl/status are only set during the encoder
> pre_enable() hook, what is causing all reads and writes to those
> registers to go to offset 0x0 before pre_enable() is executed.
>
> So if i915 takes the BIOS state and don't do a modeset any following
> link retraing will fail.
>
> In the case that i915 needs to do a modeset, the DDI disable sequence
> will write to a wrong register not disabling DP 'Transport Enable' in
> DP_TP_CTL, making a HDMI modeset in the same port/transcoder to
> not light up the monitor.
So to clarify I understand the problematic sequence properly:
* i915 inherits already-enabled display from BIOS; pre_enable is never
called
* we do a modeset, so we have to disable the display and then try to re-enable
- intel_disable_ddi_buf() writes to offset 0 rather than the proper
register offset when attempting to reprogram DP_TP_CTL and
disable DP
- when we re-enable, the old, still-active DP settings in hardware
cause problems and the display doesn't light up
A couple clarifying questions:
- It seems like we should have seen unclaimed register warnings from
the bogus writes to offset 0 during disable. Any idea why those
didn't show up?
- In the commit message you mention that it's the DP Transport Enable
that's the culprit here, which breaks future attempts to light up
HDMI. I assume this means that we're also switching which pipe
we're driving the port with, not just doing any modeset? Otherwise
DP would stay DP, HDMI would stay HDMI, and we wouldn't see this
problem with DP being active on an HDMI monitor (although we'd still
be writing to an invalid register offset during our first DP disable
which might cause other problems). Might be worth adding a mention
of the pipe change to the commit message to clarify.
The changes here look correct to me; we'll ensure the DP registers have
proper offsets before we do our first modeset, and then the rest of the
runtime behavior thereafter should be unchanged. So
Reviewed-by: Matt Roper
>
> So here for GENs older than 12, that have those registers fixed at
> port offset range it is loading at encoder/port init while for GEN12
> it will keep setting it at encoder pre_enable() and during HW state
> readout.
>
> Fixes: df6e205b ("drm/i915/tgl: move DP_TP_* to transcoder")
> Cc: Matt Roper
> Cc: Lucas De Marchi
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 14 +++---
> drivers/gpu/drm/i915/display/intel_dp.c | 5 ++---
> 2 files changed, 13 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index be6c61bcbc9c..1aab93a94f40 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3252,9 +3252,6 @@ static void hsw_ddi_pre_enable_dp(struct
> intel_atomic_state *state,
> intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
>crtc_state->lane_count, is_mst);
>
> - intel_dp->regs.dp_tp_ctl = DP_TP_CTL(port);
> - intel_dp->regs.dp_tp_status = DP_TP_STATUS(port);
> -
> intel_edp_panel_on(intel_dp);
>
> intel_ddi_clk_select(encoder, crtc_state);
> @@ -4061,12 +4058,18 @@ void intel_ddi_get_config(struct intel_encoder
> *encoder,
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
> enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> u32 temp, flags = 0;
>
> /* XXX: DSI transcoder paranoia */
> if (drm_WARN_ON(_priv->drm, transcoder_is_dsi(cpu_transcoder)))
> return;
>
> + if (INTEL_GEN(dev_priv) >= 12) {
> + intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(cpu_transcoder);
> + intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(cpu_transcoder);
> + }
> +
> intel_dsc_get_config(encoder, pipe_config);
>
> temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
> @@ -4396,6 +4399,7 @@ static const struct drm_encoder_funcs intel_ddi_funcs =
> {
> static struct intel_connector *
> intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
> {
> + struct drm_i915_private *dev_priv =
> to_i915(intel_dig_port->base.base.dev);
> struct intel_connector *connector;
> enum port port = intel_dig_port->base.port;
>
> @@ -4406,6 +4410,10 @@ intel_ddi_init_dp_connector(struct intel_digital_port
> *intel_dig_port)
> intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
> intel_dig_port->dp.prepare_link_retrain =
> intel_ddi_prepare_link_retrain;
> + if (INTEL_GEN(dev_priv) < 12) {
> +
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gt: Update PMINTRMSK holding fw
== Series Details == Series: drm/i915/gt: Update PMINTRMSK holding fw URL : https://patchwork.freedesktop.org/series/75958/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8298_full -> Patchwork_17305_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_17305_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17305_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_17305_full: ### IGT changes ### Possible regressions * igt@perf_pmu@cpu-hotplug: - shard-tglb: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17305/shard-tglb1/igt@perf_...@cpu-hotplug.html New tests - New tests have been introduced between CI_DRM_8298_full and Patchwork_17305_full: ### New IGT tests (27) ### * igt@kms_plane_cursor@pipe-a-overlay-size-128: - Statuses : 7 pass(s) - Exec time: [1.65, 3.64] s * igt@kms_plane_cursor@pipe-a-overlay-size-256: - Statuses : 8 pass(s) - Exec time: [1.65, 3.66] s * igt@kms_plane_cursor@pipe-a-overlay-size-64: - Statuses : 8 pass(s) - Exec time: [1.65, 3.67] s * igt@kms_plane_cursor@pipe-a-primary-size-128: - Statuses : 8 pass(s) - Exec time: [1.64, 3.44] s * igt@kms_plane_cursor@pipe-a-primary-size-256: - Statuses : 8 pass(s) - Exec time: [1.63, 3.45] s * igt@kms_plane_cursor@pipe-a-primary-size-64: - Statuses : 8 pass(s) - Exec time: [1.63, 3.43] s * igt@kms_plane_cursor@pipe-a-viewport-size-128: - Statuses : 8 pass(s) - Exec time: [1.65, 3.70] s * igt@kms_plane_cursor@pipe-a-viewport-size-256: - Statuses : 7 pass(s) - Exec time: [2.19, 3.69] s * igt@kms_plane_cursor@pipe-a-viewport-size-64: - Statuses : 8 pass(s) - Exec time: [1.65, 3.61] s * igt@kms_plane_cursor@pipe-b-overlay-size-128: - Statuses : 8 pass(s) - Exec time: [2.22, 4.87] s * igt@kms_plane_cursor@pipe-b-overlay-size-256: - Statuses : 8 pass(s) - Exec time: [2.22, 4.85] s * igt@kms_plane_cursor@pipe-b-overlay-size-64: - Statuses : 8 pass(s) - Exec time: [2.22, 4.83] s * igt@kms_plane_cursor@pipe-b-primary-size-128: - Statuses : 8 pass(s) - Exec time: [2.21, 4.67] s * igt@kms_plane_cursor@pipe-b-primary-size-256: - Statuses : 8 pass(s) - Exec time: [2.20, 4.70] s * igt@kms_plane_cursor@pipe-b-primary-size-64: - Statuses : 8 pass(s) - Exec time: [2.21, 4.61] s * igt@kms_plane_cursor@pipe-b-viewport-size-128: - Statuses : - Exec time: [None] s * igt@kms_plane_cursor@pipe-b-viewport-size-256: - Statuses : 8 pass(s) - Exec time: [2.22, 4.88] s * igt@kms_plane_cursor@pipe-b-viewport-size-64: - Statuses : 8 pass(s) - Exec time: [2.22, 4.92] s * igt@kms_plane_cursor@pipe-c-overlay-size-128: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.92] s * igt@kms_plane_cursor@pipe-c-overlay-size-256: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.91] s * igt@kms_plane_cursor@pipe-c-overlay-size-64: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.91] s * igt@kms_plane_cursor@pipe-c-primary-size-128: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.56] s * igt@kms_plane_cursor@pipe-c-primary-size-256: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.68] s * igt@kms_plane_cursor@pipe-c-primary-size-64: - Statuses : 6 pass(s) 1 skip(s) - Exec time: [0.0, 2.77] s * igt@kms_plane_cursor@pipe-c-viewport-size-128: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.87] s * igt@kms_plane_cursor@pipe-c-viewport-size-256: - Statuses : 6 pass(s) 1 skip(s) - Exec time: [0.0, 4.83] s * igt@kms_plane_cursor@pipe-c-viewport-size-64: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.84] s Known issues Here are the changes found in Patchwork_17305_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_balancer@semaphore: - shard-glk: [PASS][2] -> [INCOMPLETE][3] ([i915#58] / [k.org#198133]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-glk6/igt@gem_exec_balan...@semaphore.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17305/shard-glk1/igt@gem_exec_balan...@semaphore.html * igt@gem_exec_create@madvise: - shard-hsw: [PASS][4] -> [INCOMPLETE][5] ([i915#61]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-hsw1/igt@gem_exec_cre...@madvise.html [5]:
[Intel-gfx] linux-next: manual merge of the drm-misc tree with Linus' tree
Hi all,
Today's linux-next merge of the drm-misc tree got a conflict in:
MAINTAINERS
between commits:
4400b7d68f6e ("MAINTAINERS: sort entries by entry name")
3b50142d8528 ("MAINTAINERS: sort field names for all entries")
from Linus' tree and commits:
5304058b1526 ("dt-bindings: display: convert arm,versatile-tft-panel to DT
Schema")
c1eb28405d3a ("dt-bindings: display: convert boe,himax8279d to DT Schema")
1aa3bf853cb4 ("dt-bindings: display: convert raydium,rm67191 to DT Schema")
8b9e7ace123d ("dt-bindings: display: convert olimex,lcd-olinuxino to DT
Schema")
from the drm-misc tree.
I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging. You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.
--
Cheers,
Stephen Rothwell
diff --cc MAINTAINERS
index a7f3c96eb61e,ccd0ccfce4eb..
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@@ -5037,14 -5019,32 +5037,14 @@@ M: Sumit Semwal
-R:Andrew F. Davis
-R:Benjamin Gaignard
-R:Liam Mark
-R:Laura Abbott
-R:Brian Starkey
-R:John Stultz
-S:Maintained
-L:linux-me...@vger.kernel.org
-L:dri-de...@lists.freedesktop.org
-L:linaro-mm-...@lists.linaro.org (moderated for non-subscribers)
-F:include/uapi/linux/dma-heap.h
-F:include/linux/dma-heap.h
-F:drivers/dma-buf/dma-heap.c
-F:drivers/dma-buf/heaps/*
-T:git git://anongit.freedesktop.org/drm/drm-misc
DMA GENERIC OFFLOAD ENGINE SUBSYSTEM
M:Vinod Koul
@@@ -5255,10 -5226,15 +5255,10 @@@ F: drivers/gpu/drm/pl111
DRM DRIVER FOR ARM VERSATILE TFT PANELS
M:Linus Walleij
-T:git git://anongit.freedesktop.org/drm/drm-misc
S:Maintained
-F:drivers/gpu/drm/panel/panel-arm-versatile.c
+T:git git://anongit.freedesktop.org/drm/drm-misc
- F:
Documentation/devicetree/bindings/display/panel/arm,versatile-tft-panel.txt
+ F:
Documentation/devicetree/bindings/display/panel/arm,versatile-tft-panel.yaml
-
-DRM DRIVER FOR AST SERVER GRAPHICS CHIPS
-M:Dave Airlie
-S:Odd Fixes
-F:drivers/gpu/drm/ast/
+F:drivers/gpu/drm/panel/panel-arm-versatile.c
DRM DRIVER FOR ASPEED BMC GFX
M:Joel Stanley
@@@ -5283,8 -5254,8 +5283,8 @@@ F: drivers/gpu/drm/bochs
DRM DRIVER FOR BOE HIMAX8279D PANELS
M:Jerry Han
S:Maintained
- F:Documentation/devicetree/bindings/display/panel/boe,himax8279d.txt
-F:drivers/gpu/drm/panel/panel-boe-himax8279d.c
+ F:Documentation/devicetree/bindings/display/panel/boe,himax8279d.yaml
+F:drivers/gpu/drm/panel/panel-boe-himax8279d.c
DRM DRIVER FOR FARADAY TVE200 TV ENCODER
M:Linus Walleij
@@@ -5301,8 -5272,8 +5301,8 @@@ F: drivers/gpu/drm/panel/panel-feixin-k
DRM DRIVER FOR FEIYANG FY07024DI26A30-D MIPI-DSI LCD PANELS
M:Jagan Teki
S:Maintained
- F:
Documentation/devicetree/bindings/display/panel/feiyang,fy07024di26a30d.txt
-F:drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c
+ F:
Documentation/devicetree/bindings/display/panel/feiyang,fy07024di26a30d.yaml
+F:drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c
DRM DRIVER FOR GRAIN MEDIA GM12U320 PROJECTORS
M:Hans de Goede
@@@ -5384,8 -5355,8 +5384,8 @@@ F: include/uapi/drm/nouveau_drm.
DRM DRIVER FOR OLIMEX LCD-OLINUXINO PANELS
M:Stefan Mavrodiev
S:Maintained
- F:Documentation/devicetree/bindings/display/panel/olimex,lcd-olinuxino.txt
-F:drivers/gpu/drm/panel/panel-olimex-lcd-olinuxino.c
+ F:
Documentation/devicetree/bindings/display/panel/olimex,lcd-olinuxino.yaml
+F:drivers/gpu/drm/panel/panel-olimex-lcd-olinuxino.c
DRM DRIVER FOR PERVASIVE DISPLAYS REPAPER PANELS
M:Noralf Trønnes
@@@ -5418,12 -5395,6 +5418,12 @@@ S:Orphan / Obsolet
F:drivers/gpu/drm/r128/
F:include/uapi/drm/r128_drm.h
+DRM DRIVER FOR RAYDIUM RM67191 PANELS
+M:Robert Chiras
+S:Maintained
- F:Documentation/devicetree/bindings/display/panel/raydium,rm67191.txt
++F:Documentation/devicetree/bindings/display/panel/raydium,rm67191.yaml
+F:drivers/gpu/drm/panel/panel-raydium-rm67191.c
+
DRM DRIVER FOR ROCKTECH JH057N00900 PANELS
M:Guido Günther
R:Purism Kernel Team
@@@ -5441,18 -5412,18 +5441,18 @@@ S: Orphan / Obsolet
F:drivers/gpu/drm/sis/
F:include/uapi/drm/sis_drm.h
-DRM DRIVER FOR SITRONIX ST7701 PANELS
-M:Jagan Teki
-S:Maintained
-F:drivers/gpu/drm/panel/panel-sitronix-st7701.c
-F:Documentation/devicetree/bindings/display/panel/sitronix,st7701.yaml
-
DRM DRIVER FOR SITRONIX ST7586 PANELS
M:David Lechner
-T:git git://anongit.freedesktop.org/drm/drm-misc
S:Maintained
-F:drivers/gpu/drm/tiny/st7586.c
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/tgl: TBT AUX should use TC power well ops
== Series Details == Series: series starting with [1/2] drm/i915/tgl: TBT AUX should use TC power well ops URL : https://patchwork.freedesktop.org/series/75998/ State : success == Summary == CI Bug Log - changes from CI_DRM_8305 -> Patchwork_17319 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17319/index.html Known issues Here are the changes found in Patchwork_17319 that come from known issues: ### IGT changes ### Issues hit * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-skl-6770hq: [PASS][1] -> [SKIP][2] ([fdo#109271]) +20 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8305/fi-skl-6770hq/igt@kms_pipe_crc_ba...@read-crc-pipe-a-frame-sequence.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17319/fi-skl-6770hq/igt@kms_pipe_crc_ba...@read-crc-pipe-a-frame-sequence.html Warnings * igt@i915_pm_rpm@module-reload: - fi-kbl-x1275: [SKIP][3] ([fdo#109271]) -> [FAIL][4] ([i915#62]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8305/fi-kbl-x1275/igt@i915_pm_...@module-reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17319/fi-kbl-x1275/igt@i915_pm_...@module-reload.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 Participating hosts (51 -> 45) -- Missing(6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8305 -> Patchwork_17319 CI-20190529: 20190529 CI_DRM_8305: 6f16366a3061bc52af7a7ab423b08cc8cb8bf039 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5591: f57b7fdbe8d04ce3edf0433a03c7d9d5c3d96680 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17319: 6e0eb59bceddb6427bad5934c8664b8c19f3765c @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 6e0eb59bcedd drm/i915: Use single set of AUX powerwell ops for gen11+ 91ebcb9b39b9 drm/i915/tgl: TBT AUX should use TC power well ops == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17319/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [1/2] drm/i915/tgl: TBT AUX should use TC power well ops
== Series Details == Series: series starting with [1/2] drm/i915/tgl: TBT AUX should use TC power well ops URL : https://patchwork.freedesktop.org/series/75998/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 /home/cidrm/kernel/Documentation/gpu/i915.rst:610: WARNING: duplicate label gpu/i915:layout, other instance in /home/cidrm/kernel/Documentation/gpu/i915.rst ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915/tgl: TBT AUX should use TC power well ops
On Wed, 2020-04-15 at 16:34 -0700, Matt Roper wrote:
> As on ICL, we want to use the Type-C aux handlers for the TBT aux
> wells
> to ensure the DP_AUX_CH_CTL_TBT_IO flag is set properly.
Reviewed-by: José Roberto de Souza
>
> Fixes: 656409bbaf87 ("drm/i915/tgl: Add power well support")
> Cc: José Roberto de Souza
> Cc: Imre Deak
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_display_power.c | 12 ++--
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 6cc0e23ca566..03bdde19c8c9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -4147,7 +4147,7 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> {
> .name = "AUX D TBT1",
> .domains = TGL_AUX_D_TBT1_IO_POWER_DOMAINS,
> - .ops = _power_well_ops,
> + .ops = _tc_phy_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = _aux_power_well_regs,
> @@ -4158,7 +4158,7 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> {
> .name = "AUX E TBT2",
> .domains = TGL_AUX_E_TBT2_IO_POWER_DOMAINS,
> - .ops = _power_well_ops,
> + .ops = _tc_phy_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = _aux_power_well_regs,
> @@ -4169,7 +4169,7 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> {
> .name = "AUX F TBT3",
> .domains = TGL_AUX_F_TBT3_IO_POWER_DOMAINS,
> - .ops = _power_well_ops,
> + .ops = _tc_phy_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = _aux_power_well_regs,
> @@ -4180,7 +4180,7 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> {
> .name = "AUX G TBT4",
> .domains = TGL_AUX_G_TBT4_IO_POWER_DOMAINS,
> - .ops = _power_well_ops,
> + .ops = _tc_phy_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = _aux_power_well_regs,
> @@ -4191,7 +4191,7 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> {
> .name = "AUX H TBT5",
> .domains = TGL_AUX_H_TBT5_IO_POWER_DOMAINS,
> - .ops = _power_well_ops,
> + .ops = _tc_phy_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = _aux_power_well_regs,
> @@ -4202,7 +4202,7 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> {
> .name = "AUX I TBT6",
> .domains = TGL_AUX_I_TBT6_IO_POWER_DOMAINS,
> - .ops = _power_well_ops,
> + .ops = _tc_phy_aux_power_well_ops,
> .id = DISP_PW_ID_NONE,
> {
> .hsw.regs = _aux_power_well_regs,
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Wa_14011059788 (rev2)
== Series Details == Series: drm/i915/tgl: Wa_14011059788 (rev2) URL : https://patchwork.freedesktop.org/series/75990/ State : success == Summary == CI Bug Log - changes from CI_DRM_8304 -> Patchwork_17318 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17318/index.html Known issues Here are the changes found in Patchwork_17318 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@sanitycheck: - fi-bwr-2160:[PASS][1] -> [INCOMPLETE][2] ([i915#489]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8304/fi-bwr-2160/igt@i915_selftest@l...@sanitycheck.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17318/fi-bwr-2160/igt@i915_selftest@l...@sanitycheck.html Possible fixes * igt@i915_pm_rpm@module-reload: - fi-icl-dsi: [INCOMPLETE][3] ([i915#189]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8304/fi-icl-dsi/igt@i915_pm_...@module-reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17318/fi-icl-dsi/igt@i915_pm_...@module-reload.html * igt@i915_selftest@live@active: - fi-ivb-3770:[INCOMPLETE][5] -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8304/fi-ivb-3770/igt@i915_selftest@l...@active.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17318/fi-ivb-3770/igt@i915_selftest@l...@active.html [i915#189]: https://gitlab.freedesktop.org/drm/intel/issues/189 [i915#489]: https://gitlab.freedesktop.org/drm/intel/issues/489 Participating hosts (52 -> 46) -- Missing(6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8304 -> Patchwork_17318 CI-20190529: 20190529 CI_DRM_8304: 15c218df10592f30afd812717fc49838c88d555d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5591: f57b7fdbe8d04ce3edf0433a03c7d9d5c3d96680 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17318: 60cd385712c0b8996c168ca4bfdedb9cdf1f51ac @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 60cd385712c0 drm/i915/tgl: Wa_14011059788 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17318/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for devm_drm_dev_alloc, v2
== Series Details == Series: devm_drm_dev_alloc, v2 URL : https://patchwork.freedesktop.org/series/75956/ State : success == Summary == CI Bug Log - changes from CI_DRM_8298_full -> Patchwork_17304_full Summary --- **SUCCESS** No regressions found. New tests - New tests have been introduced between CI_DRM_8298_full and Patchwork_17304_full: ### New IGT tests (27) ### * igt@kms_plane_cursor@pipe-a-overlay-size-128: - Statuses : 8 pass(s) - Exec time: [1.65, 3.69] s * igt@kms_plane_cursor@pipe-a-overlay-size-256: - Statuses : 8 pass(s) - Exec time: [1.64, 3.68] s * igt@kms_plane_cursor@pipe-a-overlay-size-64: - Statuses : 8 pass(s) - Exec time: [1.65, 3.68] s * igt@kms_plane_cursor@pipe-a-primary-size-128: - Statuses : 8 pass(s) - Exec time: [1.64, 3.43] s * igt@kms_plane_cursor@pipe-a-primary-size-256: - Statuses : 8 pass(s) - Exec time: [1.63, 3.43] s * igt@kms_plane_cursor@pipe-a-primary-size-64: - Statuses : 8 pass(s) - Exec time: [1.63, 3.50] s * igt@kms_plane_cursor@pipe-a-viewport-size-128: - Statuses : 8 pass(s) - Exec time: [1.65, 3.65] s * igt@kms_plane_cursor@pipe-a-viewport-size-256: - Statuses : 8 pass(s) - Exec time: [1.64, 3.68] s * igt@kms_plane_cursor@pipe-a-viewport-size-64: - Statuses : 8 pass(s) - Exec time: [1.65, 3.69] s * igt@kms_plane_cursor@pipe-b-overlay-size-128: - Statuses : 8 pass(s) - Exec time: [2.21, 4.80] s * igt@kms_plane_cursor@pipe-b-overlay-size-256: - Statuses : 8 pass(s) - Exec time: [2.24, 4.84] s * igt@kms_plane_cursor@pipe-b-overlay-size-64: - Statuses : 8 pass(s) - Exec time: [2.21, 4.86] s * igt@kms_plane_cursor@pipe-b-primary-size-128: - Statuses : 8 pass(s) - Exec time: [2.20, 4.62] s * igt@kms_plane_cursor@pipe-b-primary-size-256: - Statuses : 8 pass(s) - Exec time: [2.21, 4.58] s * igt@kms_plane_cursor@pipe-b-primary-size-64: - Statuses : 8 pass(s) - Exec time: [2.21, 4.62] s * igt@kms_plane_cursor@pipe-b-viewport-size-128: - Statuses : - Exec time: [None] s * igt@kms_plane_cursor@pipe-b-viewport-size-256: - Statuses : 8 pass(s) - Exec time: [2.23, 4.86] s * igt@kms_plane_cursor@pipe-b-viewport-size-64: - Statuses : 8 pass(s) - Exec time: [2.28, 4.82] s * igt@kms_plane_cursor@pipe-c-overlay-size-128: - Statuses : 6 pass(s) 1 skip(s) - Exec time: [0.0, 3.59] s * igt@kms_plane_cursor@pipe-c-overlay-size-256: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.87] s * igt@kms_plane_cursor@pipe-c-overlay-size-64: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.87] s * igt@kms_plane_cursor@pipe-c-primary-size-128: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.62] s * igt@kms_plane_cursor@pipe-c-primary-size-256: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.62] s * igt@kms_plane_cursor@pipe-c-primary-size-64: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.71] s * igt@kms_plane_cursor@pipe-c-viewport-size-128: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.86] s * igt@kms_plane_cursor@pipe-c-viewport-size-256: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.85] s * igt@kms_plane_cursor@pipe-c-viewport-size-64: - Statuses : 6 pass(s) 1 skip(s) - Exec time: [0.0, 4.90] s Known issues Here are the changes found in Patchwork_17304_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_mmap_wc@bad-object: - shard-hsw: [PASS][1] -> [INCOMPLETE][2] ([i915#61]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-hsw1/igt@gem_mmap...@bad-object.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17304/shard-hsw4/igt@gem_mmap...@bad-object.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-apl1/igt@gem_workarou...@suspend-resume-context.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17304/shard-apl4/igt@gem_workarou...@suspend-resume-context.html * igt@i915_pm_rc6_residency@rc6-idle: - shard-snb: [PASS][5] -> [FAIL][6] ([i915#1066]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-snb2/igt@i915_pm_rc6_reside...@rc6-idle.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17304/shard-snb5/igt@i915_pm_rc6_reside...@rc6-idle.html * igt@i915_selftest@live@requests: - shard-tglb: [PASS][7] -> [INCOMPLETE][8] ([i915#1531] / [i915#1658]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-tglb1/igt@i915_selftest@l...@requests.html [8]:
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/tgl: Wa_14011059788 (rev2)
== Series Details == Series: drm/i915/tgl: Wa_14011059788 (rev2) URL : https://patchwork.freedesktop.org/series/75990/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 /home/cidrm/kernel/Documentation/gpu/i915.rst:610: WARNING: duplicate label gpu/i915:layout, other instance in /home/cidrm/kernel/Documentation/gpu/i915.rst ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [CI 1/2] drm/i915/selftests: Exercise basic RPS interrupt generation
Hi Chris, On Wed, Apr 15, 2020 at 06:03:17PM +0100, Chris Wilson wrote: > Since we depend upon RPS generating interrupts after evaluation > intervals to determine when to up/down clock the GPU, it is imperative > that we successfully enable interrupt generation! Verify that we do see > an interrupt if we keep the GPU busy for an entire EI. > > Signed-off-by: Chris Wilson Looks correct to me, Reviewed-by: Andi Shyti Thanks, Andi ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/tgl: TBT AUX should use TC power well ops
As on ICL, we want to use the Type-C aux handlers for the TBT aux wells
to ensure the DP_AUX_CH_CTL_TBT_IO flag is set properly.
Fixes: 656409bbaf87 ("drm/i915/tgl: Add power well support")
Cc: José Roberto de Souza
Cc: Imre Deak
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_display_power.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 6cc0e23ca566..03bdde19c8c9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4147,7 +4147,7 @@ static const struct i915_power_well_desc
tgl_power_wells[] = {
{
.name = "AUX D TBT1",
.domains = TGL_AUX_D_TBT1_IO_POWER_DOMAINS,
- .ops = _power_well_ops,
+ .ops = _tc_phy_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
.hsw.regs = _aux_power_well_regs,
@@ -4158,7 +4158,7 @@ static const struct i915_power_well_desc
tgl_power_wells[] = {
{
.name = "AUX E TBT2",
.domains = TGL_AUX_E_TBT2_IO_POWER_DOMAINS,
- .ops = _power_well_ops,
+ .ops = _tc_phy_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
.hsw.regs = _aux_power_well_regs,
@@ -4169,7 +4169,7 @@ static const struct i915_power_well_desc
tgl_power_wells[] = {
{
.name = "AUX F TBT3",
.domains = TGL_AUX_F_TBT3_IO_POWER_DOMAINS,
- .ops = _power_well_ops,
+ .ops = _tc_phy_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
.hsw.regs = _aux_power_well_regs,
@@ -4180,7 +4180,7 @@ static const struct i915_power_well_desc
tgl_power_wells[] = {
{
.name = "AUX G TBT4",
.domains = TGL_AUX_G_TBT4_IO_POWER_DOMAINS,
- .ops = _power_well_ops,
+ .ops = _tc_phy_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
.hsw.regs = _aux_power_well_regs,
@@ -4191,7 +4191,7 @@ static const struct i915_power_well_desc
tgl_power_wells[] = {
{
.name = "AUX H TBT5",
.domains = TGL_AUX_H_TBT5_IO_POWER_DOMAINS,
- .ops = _power_well_ops,
+ .ops = _tc_phy_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
.hsw.regs = _aux_power_well_regs,
@@ -4202,7 +4202,7 @@ static const struct i915_power_well_desc
tgl_power_wells[] = {
{
.name = "AUX I TBT6",
.domains = TGL_AUX_I_TBT6_IO_POWER_DOMAINS,
- .ops = _power_well_ops,
+ .ops = _tc_phy_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
.hsw.regs = _aux_power_well_regs,
--
2.24.1
___
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[Intel-gfx] [PATCH 2/2] drm/i915: Use single set of AUX powerwell ops for gen11+
AUX power wells sometimes need additional handling besides just
programming the specific power well registers:
* Type-C PHY's also require additional Type-C register programming
* ICL combo PHY's require additional workarounds
* TGL & EHL combo PHY's can be treated like any other power well
Today we have dedicated aux ops for the ICL combo PHY and Type-C cases.
This works fine, but means that when a new platform shows up with
identical general power well handling, but different types of PHYs on
its outputs, we have to define an entire new power well table for that
platform and can't just re-use the table from the earlier platform -- as
an example, see ehl_power_wells[], which is a subset of
icl_power_wells[], *except* that we need to specify different AUX ops
for the third display.
If we instead create a single set of top-level aux ops that will check
the PHY type and then dispatch to the appropriate handlers, we can get
more reuse out of our power well definitions. This allows us to
immediately eliminate ehl_power_wells[] and simply reuse the ICL table;
if future platforms follow the same general power well assignments as
either ICL or TGL, we'll be able to re-use those tables in the same way.
Note that I've only changed ICL+ platforms over to using the new icl_aux
ops; at this point it's unlikely that we'll have any new platforms that
re-use gen9 or earlier power well configurations.
v2:
- ICL_AUX_PW_TO_PHY() won't return the proper PHY for TBT AUX power
wells. But we know those wells will only used on Type-C outputs
anyway, so we can just check is is_tc_tbt flag in the condition.
(Jose).
Cc: José Roberto de Souza
Signed-off-by: Matt Roper
---
.../drm/i915/display/intel_display_power.c| 244 +-
1 file changed, 62 insertions(+), 182 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 03bdde19c8c9..f72935146778 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -593,6 +593,40 @@ icl_tc_phy_aux_power_well_disable(struct drm_i915_private
*dev_priv,
hsw_power_well_disable(dev_priv, power_well);
}
+static void
+icl_aux_power_well_enable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ int pw_idx = power_well->desc->hsw.idx;
+ enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx); /* non-TBT only */
+ bool is_tbt = power_well->desc->hsw.is_tc_tbt;
+
+ if (is_tbt || intel_phy_is_tc(dev_priv, phy))
+ return icl_tc_phy_aux_power_well_enable(dev_priv, power_well);
+ else if (IS_ICELAKE(dev_priv))
+ return icl_combo_phy_aux_power_well_enable(dev_priv,
+ power_well);
+ else
+ return hsw_power_well_enable(dev_priv, power_well);
+}
+
+static void
+icl_aux_power_well_disable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ int pw_idx = power_well->desc->hsw.idx;
+ enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx); /* non-TBT only */
+ bool is_tbt = power_well->desc->hsw.is_tc_tbt;
+
+ if (is_tbt || intel_phy_is_tc(dev_priv, phy))
+ return icl_tc_phy_aux_power_well_disable(dev_priv, power_well);
+ else if (IS_ICELAKE(dev_priv))
+ return icl_combo_phy_aux_power_well_disable(dev_priv,
+ power_well);
+ else
+ return hsw_power_well_disable(dev_priv, power_well);
+}
+
/*
* We should only use the power well if we explicitly asked the hardware to
* enable it, so check if it's enabled and also check if we've requested it to
@@ -3503,17 +3537,10 @@ static const struct i915_power_well_desc
cnl_power_wells[] = {
},
};
-static const struct i915_power_well_ops icl_combo_phy_aux_power_well_ops = {
- .sync_hw = hsw_power_well_sync_hw,
- .enable = icl_combo_phy_aux_power_well_enable,
- .disable = icl_combo_phy_aux_power_well_disable,
- .is_enabled = hsw_power_well_enabled,
-};
-
-static const struct i915_power_well_ops icl_tc_phy_aux_power_well_ops = {
+static const struct i915_power_well_ops icl_aux_power_well_ops = {
.sync_hw = hsw_power_well_sync_hw,
- .enable = icl_tc_phy_aux_power_well_enable,
- .disable = icl_tc_phy_aux_power_well_disable,
+ .enable = icl_aux_power_well_enable,
+ .disable = icl_aux_power_well_disable,
.is_enabled = hsw_power_well_enabled,
};
@@ -3643,7 +3670,7 @@ static const struct i915_power_well_desc
icl_power_wells[] = {
{
.name = "AUX A",
.domains = ICL_AUX_A_IO_POWER_DOMAINS,
- .ops = _combo_phy_aux_power_well_ops,
+ .ops = _aux_power_well_ops,
.id = DISP_PW_ID_NONE,
Re: [Intel-gfx] [PATCH 1/3] drm/i915/perf: Reduce cpu overhead for blocking perf OA reads
On Wed, Apr 15, 2020 at 10:16:59PM +0300, Lionel Landwerlin wrote:
On 15/04/2020 21:55, Umesh Nerlige Ramappa wrote:
On Wed, Apr 15, 2020 at 01:00:30PM +0300, Lionel Landwerlin wrote:
On 13/04/2020 18:48, Umesh Nerlige Ramappa wrote:
A condition in wait_event_interruptible seems to be checked
twice before
waiting on the event to occur. These checks are redundant when hrtimer
events will call oa_buffer_check_unlocked to update the oa_buffer tail
pointers. The redundant checks add cpu overhead. Simplify the check
to reduce cpu overhead when using blocking io to read oa buffer
reports.
Signed-off-by: Umesh Nerlige Ramappa
I cherry picked this patch alone and it seems to break the
disabled-read-error test.
Strange. I don't see it fail on my CFL. I am apply this on the
latest drm-tip from yesterday.
The patch still checks if reports are available before blocking. The
behavior should still be the same w.r.t this test.
What machine did you run it on? I will try on the same. Any chance
you have the debug output from the test?
Thanks,
Umesh
I got that on SKL GT4 : http://paste.debian.net/1140604/
Fails always on SKL GT4. Thanks for catching this :)
Also fails without this patch if this test were to use NONBLOCKing IO.
This has to do with being able to read reports at sampling frequencies
as high as 5 us (on some platforms, I guess).
Will look into it further and repost the series. Let me know if you have
any other thoughts on this.
Thanks,
Umesh
Thanks,
-Lionel
---
drivers/gpu/drm/i915/i915_perf.c | 28 +++-
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c
b/drivers/gpu/drm/i915/i915_perf.c
index 5cde3e4e7be6..e28a3ab83fde 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -541,6 +541,32 @@ static bool oa_buffer_check_unlocked(struct
i915_perf_stream *stream)
return pollin;
}
+/**
+ * oa_buffer_check_reports - quick check if reports are available
+ * @stream: i915 stream instance
+ *
+ * The return from this function is used as a condition for
+ * wait_event_interruptible in blocking read. This is used to detect
+ * available reports.
+ *
+ * A condition in wait_event_interruptible seems to be checked
twice before
+ * waiting on an event to occur. These checks are redundant
when hrtimer events
+ * will call oa_buffer_check_unlocked to update the oa_buffer
tail pointers. The
+ * redundant checks add cpu overhead. We simplify the check to
reduce cpu
+ * overhead.
+ */
+static bool oa_buffer_check_reports(struct i915_perf_stream *stream)
+{
+ unsigned long flags;
+ bool available;
+
+ spin_lock_irqsave(>oa_buffer.ptr_lock, flags);
+ available = stream->oa_buffer.tail != stream->oa_buffer.head;
+ spin_unlock_irqrestore(>oa_buffer.ptr_lock, flags);
+
+ return available;
+}
+
/**
* append_oa_status - Appends a status record to a userspace
read() buffer.
* @stream: An i915-perf stream opened for OA metrics
@@ -1150,7 +1176,7 @@ static int i915_oa_wait_unlocked(struct
i915_perf_stream *stream)
return -EIO;
return wait_event_interruptible(stream->poll_wq,
- oa_buffer_check_unlocked(stream));
+ oa_buffer_check_reports(stream));
}
/**
___
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[Intel-gfx] [PATCH v2] drm/i915/tgl: Wa_14011059788
Reflect recent Bspec changes v2: fix whitespace, typo Signed-off-by: Matt Atwood --- drivers/gpu/drm/i915/intel_pm.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index b632b6bb9c3e..3d12a0617c84 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -6854,6 +6854,10 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv) if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0)) I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) | TGL_VRH_GATING_DIS); + + /* Wa_14011059788:tgl */ + intel_uncore_rmw(_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN, +0, DFR_DISABLE); } static void cnp_init_clock_gating(struct drm_i915_private *dev_priv) -- 2.21.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✓ Fi.CI.IGT: success for Tigerlake workaround updates
On Wed, Apr 15, 2020 at 09:47:21PM +, Patchwork wrote:
> == Series Details ==
>
> Series: Tigerlake workaround updates
> URL : https://patchwork.freedesktop.org/series/75944/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_8298_full -> Patchwork_17302_full
>
>
> Summary
> ---
>
> **SUCCESS**
>
> No regressions found.
Switched the order of patch 1 and 2 as suggested by Jose and applied to
dinq. Thanks Jose for the reviews.
Matt
>
>
>
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> Patchwork_17302_full:
>
> ### IGT changes ###
>
> Suppressed
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * {igt@gem_exec_parallel@engines@fds}:
> - shard-skl: [PASS][1] -> [FAIL][2] +1 similar issue
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-skl7/igt@gem_exec_parallel@engi...@fds.html
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17302/shard-skl8/igt@gem_exec_parallel@engi...@fds.html
>
>
> New tests
> -
>
> New tests have been introduced between CI_DRM_8298_full and
> Patchwork_17302_full:
>
> ### New IGT tests (27) ###
>
> * igt@kms_plane_cursor@pipe-a-overlay-size-128:
> - Statuses : 8 pass(s)
> - Exec time: [1.66, 3.66] s
>
> * igt@kms_plane_cursor@pipe-a-overlay-size-256:
> - Statuses : 8 pass(s)
> - Exec time: [1.64, 3.64] s
>
> * igt@kms_plane_cursor@pipe-a-overlay-size-64:
> - Statuses : 8 pass(s)
> - Exec time: [1.65, 3.65] s
>
> * igt@kms_plane_cursor@pipe-a-primary-size-128:
> - Statuses : 8 pass(s)
> - Exec time: [1.64, 3.49] s
>
> * igt@kms_plane_cursor@pipe-a-primary-size-256:
> - Statuses : 8 pass(s)
> - Exec time: [1.64, 3.47] s
>
> * igt@kms_plane_cursor@pipe-a-primary-size-64:
> - Statuses : 8 pass(s)
> - Exec time: [1.63, 3.34] s
>
> * igt@kms_plane_cursor@pipe-a-viewport-size-128:
> - Statuses : 8 pass(s)
> - Exec time: [1.65, 3.69] s
>
> * igt@kms_plane_cursor@pipe-a-viewport-size-256:
> - Statuses : 8 pass(s)
> - Exec time: [1.64, 3.69] s
>
> * igt@kms_plane_cursor@pipe-a-viewport-size-64:
> - Statuses : 8 pass(s)
> - Exec time: [1.64, 3.66] s
>
> * igt@kms_plane_cursor@pipe-b-overlay-size-128:
> - Statuses : 8 pass(s)
> - Exec time: [2.21, 4.86] s
>
> * igt@kms_plane_cursor@pipe-b-overlay-size-256:
> - Statuses : 8 pass(s)
> - Exec time: [2.23, 4.91] s
>
> * igt@kms_plane_cursor@pipe-b-overlay-size-64:
> - Statuses : 8 pass(s)
> - Exec time: [2.23, 4.82] s
>
> * igt@kms_plane_cursor@pipe-b-primary-size-128:
> - Statuses : 8 pass(s)
> - Exec time: [2.21, 4.65] s
>
> * igt@kms_plane_cursor@pipe-b-primary-size-256:
> - Statuses : 8 pass(s)
> - Exec time: [2.21, 4.63] s
>
> * igt@kms_plane_cursor@pipe-b-primary-size-64:
> - Statuses : 8 pass(s)
> - Exec time: [2.20, 4.65] s
>
> * igt@kms_plane_cursor@pipe-b-viewport-size-128:
> - Statuses :
> - Exec time: [None] s
>
> * igt@kms_plane_cursor@pipe-b-viewport-size-256:
> - Statuses : 8 pass(s)
> - Exec time: [2.22, 4.86] s
>
> * igt@kms_plane_cursor@pipe-b-viewport-size-64:
> - Statuses : 8 pass(s)
> - Exec time: [2.23, 4.91] s
>
> * igt@kms_plane_cursor@pipe-c-overlay-size-128:
> - Statuses : 7 pass(s) 1 skip(s)
> - Exec time: [0.0, 4.79] s
>
> * igt@kms_plane_cursor@pipe-c-overlay-size-256:
> - Statuses : 7 pass(s) 1 skip(s)
> - Exec time: [0.0, 4.88] s
>
> * igt@kms_plane_cursor@pipe-c-overlay-size-64:
> - Statuses : 7 pass(s) 1 skip(s)
> - Exec time: [0.0, 4.85] s
>
> * igt@kms_plane_cursor@pipe-c-primary-size-128:
> - Statuses : 7 pass(s) 1 skip(s)
> - Exec time: [0.0, 4.66] s
>
> * igt@kms_plane_cursor@pipe-c-primary-size-256:
> - Statuses : 7 pass(s) 1 skip(s)
> - Exec time: [0.0, 4.74] s
>
> * igt@kms_plane_cursor@pipe-c-primary-size-64:
> - Statuses : 7 pass(s) 1 skip(s)
> - Exec time: [0.0, 4.56] s
>
> * igt@kms_plane_cursor@pipe-c-viewport-size-128:
> - Statuses : 7 pass(s) 1 skip(s)
> - Exec time: [0.0, 4.85] s
>
> * igt@kms_plane_cursor@pipe-c-viewport-size-256:
> - Statuses : 7 pass(s) 1 skip(s)
> - Exec time: [0.0, 4.89] s
>
> * igt@kms_plane_cursor@pipe-c-viewport-size-64:
> - Statuses : 7 pass(s) 1 skip(s)
> - Exec time: [0.0, 4.86] s
>
>
>
> Known issues
>
>
> Here are the changes found in Patchwork_17302_full that come from known
> issues:
>
> ### IGT changes ###
>
> Issues hit
>
> * igt@gem_ctx_exec@basic-norecovery:
> - shard-skl: [PASS][3] -> [SKIP][4] ([fdo#109271]) +4 similar
> issues
>[3]:
>
[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/tgl: Wa_14011059788
== Series Details == Series: drm/i915/tgl: Wa_14011059788 URL : https://patchwork.freedesktop.org/series/75990/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h CC [M] drivers/gpu/drm/i915/intel_pm.o drivers/gpu/drm/i915/intel_pm.c: In function ‘tgl_init_clock_gating’: drivers/gpu/drm/i915/intel_pm.c:6861:1: error: expected ‘;’ before ‘}’ token } ^ scripts/Makefile.build:266: recipe for target 'drivers/gpu/drm/i915/intel_pm.o' failed make[4]: *** [drivers/gpu/drm/i915/intel_pm.o] Error 1 scripts/Makefile.build:488: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:488: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:488: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1722: recipe for target 'drivers' failed make: *** [drivers] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/display: Load DP_TP_CTL/STATUS offset before use it
== Series Details == Series: series starting with [1/3] drm/i915/display: Load DP_TP_CTL/STATUS offset before use it URL : https://patchwork.freedesktop.org/series/75946/ State : success == Summary == CI Bug Log - changes from CI_DRM_8298_full -> Patchwork_17303_full Summary --- **SUCCESS** No regressions found. New tests - New tests have been introduced between CI_DRM_8298_full and Patchwork_17303_full: ### New IGT tests (27) ### * igt@kms_plane_cursor@pipe-a-overlay-size-128: - Statuses : 8 pass(s) - Exec time: [1.66, 3.65] s * igt@kms_plane_cursor@pipe-a-overlay-size-256: - Statuses : 8 pass(s) - Exec time: [1.65, 3.69] s * igt@kms_plane_cursor@pipe-a-overlay-size-64: - Statuses : 8 pass(s) - Exec time: [1.65, 3.68] s * igt@kms_plane_cursor@pipe-a-primary-size-128: - Statuses : 8 pass(s) - Exec time: [1.63, 3.38] s * igt@kms_plane_cursor@pipe-a-primary-size-256: - Statuses : 8 pass(s) - Exec time: [1.63, 3.45] s * igt@kms_plane_cursor@pipe-a-primary-size-64: - Statuses : 8 pass(s) - Exec time: [1.63, 3.41] s * igt@kms_plane_cursor@pipe-a-viewport-size-128: - Statuses : 8 pass(s) - Exec time: [1.65, 3.67] s * igt@kms_plane_cursor@pipe-a-viewport-size-256: - Statuses : 8 pass(s) - Exec time: [1.64, 3.64] s * igt@kms_plane_cursor@pipe-a-viewport-size-64: - Statuses : 8 pass(s) - Exec time: [1.65, 3.69] s * igt@kms_plane_cursor@pipe-b-overlay-size-128: - Statuses : 8 pass(s) - Exec time: [2.22, 4.84] s * igt@kms_plane_cursor@pipe-b-overlay-size-256: - Statuses : 8 pass(s) - Exec time: [2.23, 4.89] s * igt@kms_plane_cursor@pipe-b-overlay-size-64: - Statuses : 8 pass(s) - Exec time: [2.23, 4.85] s * igt@kms_plane_cursor@pipe-b-primary-size-128: - Statuses : 8 pass(s) - Exec time: [2.20, 4.62] s * igt@kms_plane_cursor@pipe-b-primary-size-256: - Statuses : 8 pass(s) - Exec time: [2.21, 4.61] s * igt@kms_plane_cursor@pipe-b-primary-size-64: - Statuses : 8 pass(s) - Exec time: [2.21, 4.70] s * igt@kms_plane_cursor@pipe-b-viewport-size-128: - Statuses : - Exec time: [None] s * igt@kms_plane_cursor@pipe-b-viewport-size-256: - Statuses : 8 pass(s) - Exec time: [2.23, 4.88] s * igt@kms_plane_cursor@pipe-b-viewport-size-64: - Statuses : 8 pass(s) - Exec time: [2.23, 4.82] s * igt@kms_plane_cursor@pipe-c-overlay-size-128: - Statuses : 6 pass(s) 1 skip(s) - Exec time: [0.0, 4.83] s * igt@kms_plane_cursor@pipe-c-overlay-size-256: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 5.04] s * igt@kms_plane_cursor@pipe-c-overlay-size-64: - Statuses : 6 pass(s) 1 skip(s) - Exec time: [0.0, 3.60] s * igt@kms_plane_cursor@pipe-c-primary-size-128: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.57] s * igt@kms_plane_cursor@pipe-c-primary-size-256: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.63] s * igt@kms_plane_cursor@pipe-c-primary-size-64: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.60] s * igt@kms_plane_cursor@pipe-c-viewport-size-128: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.83] s * igt@kms_plane_cursor@pipe-c-viewport-size-256: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.82] s * igt@kms_plane_cursor@pipe-c-viewport-size-64: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.88] s Known issues Here are the changes found in Patchwork_17303_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_softpin@noreloc-s3: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-apl4/igt@gem_soft...@noreloc-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17303/shard-apl4/igt@gem_soft...@noreloc-s3.html * igt@i915_pm_rc6_residency@rc6-idle: - shard-snb: [PASS][3] -> [FAIL][4] ([i915#1066]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-snb2/igt@i915_pm_rc6_reside...@rc6-idle.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17303/shard-snb5/igt@i915_pm_rc6_reside...@rc6-idle.html - shard-hsw: [PASS][5] -> [FAIL][6] ([i915#1066]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-hsw6/igt@i915_pm_rc6_reside...@rc6-idle.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17303/shard-hsw4/igt@i915_pm_rc6_reside...@rc6-idle.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([i915#180]) +5 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-kbl3/igt@kms_cursor_...@pipe-c-cursor-suspend.html [8]:
[Intel-gfx] [PATCH] drm/i915/tgl: Wa_14011059788
Reflect recent Bspec changes Signed-off-by: Matt Atwood --- drivers/gpu/drm/i915/intel_pm.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index b632b6bb9c3e..30b45c0de6fb 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -6854,6 +6854,10 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv) if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0)) I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) | TGL_VRH_GATING_DIS); + + /* Wa_14011059788:tgl */ + intel_uncore_rmw(_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN, +0, DFR_DISABLE) } static void cnp_init_clock_gating(struct drm_i915_private *dev_priv) -- 2.21.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for Tigerlake workaround updates
== Series Details ==
Series: Tigerlake workaround updates
URL : https://patchwork.freedesktop.org/series/75944/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8298_full -> Patchwork_17302_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_17302_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_exec_parallel@engines@fds}:
- shard-skl: [PASS][1] -> [FAIL][2] +1 similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-skl7/igt@gem_exec_parallel@engi...@fds.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17302/shard-skl8/igt@gem_exec_parallel@engi...@fds.html
New tests
-
New tests have been introduced between CI_DRM_8298_full and
Patchwork_17302_full:
### New IGT tests (27) ###
* igt@kms_plane_cursor@pipe-a-overlay-size-128:
- Statuses : 8 pass(s)
- Exec time: [1.66, 3.66] s
* igt@kms_plane_cursor@pipe-a-overlay-size-256:
- Statuses : 8 pass(s)
- Exec time: [1.64, 3.64] s
* igt@kms_plane_cursor@pipe-a-overlay-size-64:
- Statuses : 8 pass(s)
- Exec time: [1.65, 3.65] s
* igt@kms_plane_cursor@pipe-a-primary-size-128:
- Statuses : 8 pass(s)
- Exec time: [1.64, 3.49] s
* igt@kms_plane_cursor@pipe-a-primary-size-256:
- Statuses : 8 pass(s)
- Exec time: [1.64, 3.47] s
* igt@kms_plane_cursor@pipe-a-primary-size-64:
- Statuses : 8 pass(s)
- Exec time: [1.63, 3.34] s
* igt@kms_plane_cursor@pipe-a-viewport-size-128:
- Statuses : 8 pass(s)
- Exec time: [1.65, 3.69] s
* igt@kms_plane_cursor@pipe-a-viewport-size-256:
- Statuses : 8 pass(s)
- Exec time: [1.64, 3.69] s
* igt@kms_plane_cursor@pipe-a-viewport-size-64:
- Statuses : 8 pass(s)
- Exec time: [1.64, 3.66] s
* igt@kms_plane_cursor@pipe-b-overlay-size-128:
- Statuses : 8 pass(s)
- Exec time: [2.21, 4.86] s
* igt@kms_plane_cursor@pipe-b-overlay-size-256:
- Statuses : 8 pass(s)
- Exec time: [2.23, 4.91] s
* igt@kms_plane_cursor@pipe-b-overlay-size-64:
- Statuses : 8 pass(s)
- Exec time: [2.23, 4.82] s
* igt@kms_plane_cursor@pipe-b-primary-size-128:
- Statuses : 8 pass(s)
- Exec time: [2.21, 4.65] s
* igt@kms_plane_cursor@pipe-b-primary-size-256:
- Statuses : 8 pass(s)
- Exec time: [2.21, 4.63] s
* igt@kms_plane_cursor@pipe-b-primary-size-64:
- Statuses : 8 pass(s)
- Exec time: [2.20, 4.65] s
* igt@kms_plane_cursor@pipe-b-viewport-size-128:
- Statuses :
- Exec time: [None] s
* igt@kms_plane_cursor@pipe-b-viewport-size-256:
- Statuses : 8 pass(s)
- Exec time: [2.22, 4.86] s
* igt@kms_plane_cursor@pipe-b-viewport-size-64:
- Statuses : 8 pass(s)
- Exec time: [2.23, 4.91] s
* igt@kms_plane_cursor@pipe-c-overlay-size-128:
- Statuses : 7 pass(s) 1 skip(s)
- Exec time: [0.0, 4.79] s
* igt@kms_plane_cursor@pipe-c-overlay-size-256:
- Statuses : 7 pass(s) 1 skip(s)
- Exec time: [0.0, 4.88] s
* igt@kms_plane_cursor@pipe-c-overlay-size-64:
- Statuses : 7 pass(s) 1 skip(s)
- Exec time: [0.0, 4.85] s
* igt@kms_plane_cursor@pipe-c-primary-size-128:
- Statuses : 7 pass(s) 1 skip(s)
- Exec time: [0.0, 4.66] s
* igt@kms_plane_cursor@pipe-c-primary-size-256:
- Statuses : 7 pass(s) 1 skip(s)
- Exec time: [0.0, 4.74] s
* igt@kms_plane_cursor@pipe-c-primary-size-64:
- Statuses : 7 pass(s) 1 skip(s)
- Exec time: [0.0, 4.56] s
* igt@kms_plane_cursor@pipe-c-viewport-size-128:
- Statuses : 7 pass(s) 1 skip(s)
- Exec time: [0.0, 4.85] s
* igt@kms_plane_cursor@pipe-c-viewport-size-256:
- Statuses : 7 pass(s) 1 skip(s)
- Exec time: [0.0, 4.89] s
* igt@kms_plane_cursor@pipe-c-viewport-size-64:
- Statuses : 7 pass(s) 1 skip(s)
- Exec time: [0.0, 4.86] s
Known issues
Here are the changes found in Patchwork_17302_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_exec@basic-norecovery:
- shard-skl: [PASS][3] -> [SKIP][4] ([fdo#109271]) +4 similar
issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-skl7/igt@gem_ctx_e...@basic-norecovery.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17302/shard-skl8/igt@gem_ctx_e...@basic-norecovery.html
* igt@gem_exec_create@madvise:
- shard-hsw: [PASS][5] -> [INCOMPLETE][6] ([i915#61]) +1 similar
issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-hsw1/igt@gem_exec_cre...@madvise.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17302/shard-hsw4/igt@gem_exec_cre...@madvise.html
*
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Use single set of AUX powerwell ops for gen11+
== Series Details == Series: drm/i915: Use single set of AUX powerwell ops for gen11+ URL : https://patchwork.freedesktop.org/series/75943/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8298_full -> Patchwork_17301_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_17301_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17301_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_17301_full: ### IGT changes ### Possible regressions * igt@kms_dp_aux_dev: - shard-iclb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-iclb5/igt@kms_dp_aux_dev.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17301/shard-iclb8/igt@kms_dp_aux_dev.html New tests - New tests have been introduced between CI_DRM_8298_full and Patchwork_17301_full: ### New IGT tests (27) ### * igt@kms_plane_cursor@pipe-a-overlay-size-128: - Statuses : 8 pass(s) - Exec time: [1.66, 3.69] s * igt@kms_plane_cursor@pipe-a-overlay-size-256: - Statuses : 8 pass(s) - Exec time: [1.65, 3.65] s * igt@kms_plane_cursor@pipe-a-overlay-size-64: - Statuses : 8 pass(s) - Exec time: [1.65, 3.66] s * igt@kms_plane_cursor@pipe-a-primary-size-128: - Statuses : 8 pass(s) - Exec time: [1.63, 3.48] s * igt@kms_plane_cursor@pipe-a-primary-size-256: - Statuses : 8 pass(s) - Exec time: [1.63, 3.40] s * igt@kms_plane_cursor@pipe-a-primary-size-64: - Statuses : 7 pass(s) - Exec time: [1.63, 2.59] s * igt@kms_plane_cursor@pipe-a-viewport-size-128: - Statuses : 8 pass(s) - Exec time: [1.65, 3.68] s * igt@kms_plane_cursor@pipe-a-viewport-size-256: - Statuses : 8 pass(s) - Exec time: [1.64, 3.67] s * igt@kms_plane_cursor@pipe-a-viewport-size-64: - Statuses : 8 pass(s) - Exec time: [1.64, 3.68] s * igt@kms_plane_cursor@pipe-b-overlay-size-128: - Statuses : 8 pass(s) - Exec time: [2.22, 4.90] s * igt@kms_plane_cursor@pipe-b-overlay-size-256: - Statuses : 8 pass(s) - Exec time: [2.22, 4.83] s * igt@kms_plane_cursor@pipe-b-overlay-size-64: - Statuses : 8 pass(s) - Exec time: [2.22, 4.85] s * igt@kms_plane_cursor@pipe-b-primary-size-128: - Statuses : 8 pass(s) - Exec time: [2.21, 4.66] s * igt@kms_plane_cursor@pipe-b-primary-size-256: - Statuses : 8 pass(s) - Exec time: [2.21, 4.61] s * igt@kms_plane_cursor@pipe-b-primary-size-64: - Statuses : 8 pass(s) - Exec time: [2.20, 4.60] s * igt@kms_plane_cursor@pipe-b-viewport-size-128: - Statuses : - Exec time: [None] s * igt@kms_plane_cursor@pipe-b-viewport-size-256: - Statuses : 8 pass(s) - Exec time: [2.23, 4.84] s * igt@kms_plane_cursor@pipe-b-viewport-size-64: - Statuses : 8 pass(s) - Exec time: [2.26, 4.86] s * igt@kms_plane_cursor@pipe-c-overlay-size-128: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.80] s * igt@kms_plane_cursor@pipe-c-overlay-size-256: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.89] s * igt@kms_plane_cursor@pipe-c-overlay-size-64: - Statuses : 6 pass(s) 1 skip(s) - Exec time: [0.0, 3.65] s * igt@kms_plane_cursor@pipe-c-primary-size-128: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.66] s * igt@kms_plane_cursor@pipe-c-primary-size-256: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.57] s * igt@kms_plane_cursor@pipe-c-primary-size-64: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.64] s * igt@kms_plane_cursor@pipe-c-viewport-size-128: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.89] s * igt@kms_plane_cursor@pipe-c-viewport-size-256: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.89] s * igt@kms_plane_cursor@pipe-c-viewport-size-64: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.83] s Known issues Here are the changes found in Patchwork_17301_full that come from known issues: ### IGT changes ### Issues hit * igt@i915_pm_rpm@i2c: - shard-iclb: [PASS][3] -> [INCOMPLETE][4] ([i915#189]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-iclb1/igt@i915_pm_...@i2c.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17301/shard-iclb7/igt@i915_pm_...@i2c.html * igt@i915_selftest@live@active: - shard-glk: [PASS][5] -> [DMESG-FAIL][6] ([i915#666] / [i915#765]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-glk8/igt@i915_selftest@l...@active.html [6]:
Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/ehl: extended Wa_2006604312 to ehl
On Wed, Apr 15, 2020 at 12:19:05PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/ehl: extended Wa_2006604312 to ehl
> URL : https://patchwork.freedesktop.org/series/75894/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_8298_full -> Patchwork_17290_full
>
>
> Summary
> ---
>
> **SUCCESS**
>
> No regressions found.
>
Applied to dinq. Thanks for the patch.
Matt
>
>
> Known issues
>
>
> Here are the changes found in Patchwork_17290_full that come from known
> issues:
>
> ### IGT changes ###
>
> Issues hit
>
> * igt@gen9_exec_parse@allowed-all:
> - shard-skl: [PASS][1] -> [DMESG-WARN][2] ([i915#716])
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-skl8/igt@gen9_exec_pa...@allowed-all.html
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17290/shard-skl3/igt@gen9_exec_pa...@allowed-all.html
>
> * igt@kms_flip@plain-flip-fb-recreate:
> - shard-skl: [PASS][3] -> [FAIL][4] ([i915#34])
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-skl8/igt@kms_f...@plain-flip-fb-recreate.html
>[4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17290/shard-skl7/igt@kms_f...@plain-flip-fb-recreate.html
>
> * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
> - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) +3
> similar issues
>[5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-kbl4/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-c.html
>[6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17290/shard-kbl1/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-c.html
>
> * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
> - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([i915#180] /
> [i915#95])
>[7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-apl1/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html
>[8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17290/shard-apl1/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html
>
> * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
> - shard-skl: [PASS][9] -> [FAIL][10] ([fdo#108145] / [i915#265])
> +1 similar issue
>[9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-skl3/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html
>[10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17290/shard-skl4/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html
>
> * igt@kms_psr@psr2_primary_page_flip:
> - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109441])
>[11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
>[12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17290/shard-iclb1/igt@kms_psr@psr2_primary_page_flip.html
>
> * igt@kms_setmode@basic:
> - shard-skl: [PASS][13] -> [FAIL][14] ([i915#31])
>[13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-skl7/igt@kms_setm...@basic.html
>[14]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17290/shard-skl7/igt@kms_setm...@basic.html
>
> * igt@kms_vblank@pipe-a-ts-continuation-suspend:
> - shard-apl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +1
> similar issue
>[15]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-apl6/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html
>[16]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17290/shard-apl8/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html
>
>
> Possible fixes
>
> * {igt@gem_wait@write-wait@all}:
> - shard-skl: [FAIL][17] ([i915#1676]) -> [PASS][18]
>[17]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-skl2/igt@gem_wait@write-w...@all.html
>[18]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17290/shard-skl6/igt@gem_wait@write-w...@all.html
>
> * igt@i915_suspend@debugfs-reader:
> - shard-apl: [DMESG-WARN][19] ([i915#180]) -> [PASS][20] +2
> similar issues
>[19]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-apl1/igt@i915_susp...@debugfs-reader.html
>[20]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17290/shard-apl3/igt@i915_susp...@debugfs-reader.html
>
> * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
> - shard-glk: [FAIL][21] ([i915#72]) -> [PASS][22]
>[21]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-glk6/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html
>[22]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17290/shard-glk7/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html
>
> * igt@kms_hdr@bpc-switch-dpms:
> - shard-skl: [FAIL][23] ([i915#1188]) -> [PASS][24] +1 similar
> issue
>[23]:
>
[Intel-gfx] [PULL] drm-intel-fixes
Hi Dave and Daniel, Here goes drm-intel-fixes-2020-04-15: - Fix guest page access by using the brand new VFIO dma r/w interface (Yan) - Fix for i915 perf read buffers (Ashutosh) Thanks, Rodrigo. The following changes since commit 8f3d9f354286745c751374f5f1fcafee6b3f3136: Linux 5.7-rc1 (2020-04-12 12:35:55 -0700) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2020-04-15 for you to fetch changes up to 5809e8f8ee42db54c283c3a6bcfcbbdbfd888f5c: Merge tag 'gvt-fixes-2020-04-14' of https://github.com/intel/gvt-linux into drm-intel-fixes (2020-04-14 06:02:53 -0700) - Fix guest page access by using the brand new VFIO dma r/w interface (Yan) - Fix for i915 perf read buffers (Ashutosh) Ashutosh Dixit (1): drm/i915/perf: Do not clear pollin for small user read buffers Rodrigo Vivi (1): Merge tag 'gvt-fixes-2020-04-14' of https://github.com/intel/gvt-linux into drm-intel-fixes Yan Zhao (3): drm/i915/gvt: hold reference of VFIO group during opening of vgpu drm/i915/gvt: subsitute kvm_read/write_guest with vfio_dma_rw drm/i915/gvt: switch to user vfio_group_pin/upin_pages drivers/gpu/drm/i915/gvt/kvmgt.c | 46 ++-- drivers/gpu/drm/i915/i915_perf.c | 65 +++- 2 files changed, 33 insertions(+), 78 deletions(-) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915: Add missing deinitialization cases of load failure
Quoting José Roberto de Souza (2020-04-15 20:14:08) > The intel_display_power_put_async() used in TC cold sequences made > easy to hit the missing deinitialization of driver in case of load > failure as seen in the stack trace bellow. > > intel_modeset_driver_remove_noirq() had to be removed from > i915_driver_modeset_remove_noirq() as those are different > initialialition steps with IRQ and GEM initialization in between then. > > [drm:__intel_engine_init_ctx_wa [i915]] Initialized 3 context workarounds on > rcs'0 > [drm:__i915_inject_probe_error [i915]] Injecting failure -19 at checkpoint 36 > [__uc_init:294] > [drm:i915_hdcp_component_unbind [i915]] I915 HDCP comp unbind > [drm:edp_panel_vdd_off_sync [i915]] Turning [ENCODER:275:DDI A] VDD off > [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x PP_CONTROL: > 0x0060 > [drm:intel_power_well_disable [i915]] disabling AUX A > general protection fault, probably for non-canonical address > 0x6b6b6b6b6b6b6b6b: [#1] PREEMPT SMP NOPTI > CPU: 3 PID: 1142 Comm: kworker/u16:20 Tainted: G U > 5.6.0-CI-Patchwork_17226+ #1 > Hardware name: Intel Corporation Tiger Lake Client Platform/TigerLake U DDR4 > SODIMM RVP, BIOS TGLSFWI1.R00.2457.A16.1912270059 12/27/2019 > Workqueue: events_unbound intel_display_power_put_async_work [i915] > RIP: 0010:__intel_display_power_put_domain+0xa5/0x180 [i915] > Code: 48 85 c0 78 54 44 89 e1 41 bd 01 00 00 00 49 c7 c4 80 44 41 a0 49 d3 e5 > eb 0d 48 83 eb 10 48 3b 9d 08 ad 00 00 78 32 48 8b 03 <4c> 85 68 10 74 ea 8b > 53 08 85 d2 74 2d 83 ea 01 85 d2 89 53 08 75 > RSP: 0018:c961fdb0 EFLAGS: 00010206 > RAX: 6b6b6b6b6b6b6b6b RBX: 8884948f5df0 RCX: 003d > RDX: 8001 RSI: RDI: > RBP: 888479be R08: 88849a180920 R09: > R10: R11: R12: a0414480 > R13: 2000 R14: 888479beb320 R15: 2000 > FS: () GS:88849ff8() knlGS: > CS: 0010 DS: ES: CR0: 80050033 > CR2: 5634fa8ed670 CR3: 05610004 CR4: 00760ee0 > PKRU: 5554 > Call Trace: > release_async_put_domains+0x9b/0x110 [i915] > intel_display_power_put_async_work+0x91/0xf0 [i915] > process_one_work+0x260/0x600 > ? worker_thread+0xc9/0x380 > worker_thread+0x37/0x380 > ? process_one_work+0x600/0x600 > kthread+0x119/0x130 > ? kthread_park+0x80/0x80 > ret_from_fork+0x24/0x50 > Modules linked in: i915(+) vgem snd_hda_codec_hdmi mei_hdcp > x86_pkg_temp_thermal coretemp crct10dif_pclmul crc32_pclmul cdc_ether usbnet > mii snd_intel_dspcfg ghash_clmulni_intel snd_hda_codec snd_hwdep snd_hda_core > e1000e ptp mei_me snd_pcm pps_core mei intel_lpss_pci prime_numbers [last > unloaded: i915] > ---[ end trace b402d1b4060f8b97 ]--- > BUG: sleeping function called from invalid context at > kernel/sched/completion.c:99 > in_atomic(): 0, irqs_disabled(): 0, non_block: 0, pid: 1142, name: > kworker/u16:20 > INFO: lockdep is turned off. > Preemption disabled at: > [<>] 0x0 > CPU: 3 PID: 1142 Comm: kworker/u16:20 Tainted: G UD > 5.6.0-CI-Patchwork_17226+ #1 > Hardware name: Intel Corporation Tiger Lake Client Platform/TigerLake U DDR4 > SODIMM RVP, BIOS TGLSFWI1.R00.2457.A16.1912270059 12/27/2019 > Workqueue: events_unbound intel_display_power_put_async_work [i915] > Call Trace: > dump_stack+0x71/0x9b > ___might_sleep+0x178/0x260 > wait_for_completion+0x37/0x1a0 > virt_efi_query_variable_info+0x161/0x1b0 > efi_query_variable_store+0xb3/0x1a0 > ? efivar_entry_set_safe+0x19c/0x220 > efivar_entry_set_safe+0x19c/0x220 > ? efi_pstore_write+0x10b/0x150 > ? efi_pstore_write+0xa0/0x150 > efi_pstore_write+0x10b/0x150 > pstore_dump+0x123/0x340 > kmsg_dump+0x87/0x1b0 > oops_end+0x3e/0x90 > do_general_protection+0x1c3/0x2f0 > general_protection+0x2d/0x40 > RIP: 0010:__intel_display_power_put_domain+0xa5/0x180 [i915] > Code: 48 85 c0 78 54 44 89 e1 41 bd 01 00 00 00 49 c7 c4 80 44 41 a0 49 d3 e5 > eb 0d 48 83 eb 10 48 3b 9d 08 ad 00 00 78 32 48 8b 03 <4c> 85 68 10 74 ea 8b > 53 08 85 d2 74 2d 83 ea 01 85 d2 89 53 08 75 > RSP: 0018:c961fdb0 EFLAGS: 00010206 > RAX: 6b6b6b6b6b6b6b6b RBX: 8884948f5df0 RCX: 003d > RDX: 8001 RSI: RDI: > RBP: 888479be R08: 88849a180920 R09: > R10: R11: R12: a0414480 > R13: 2000 R14: 888479beb320 R15: 2000 > release_async_put_domains+0x9b/0x110 [i915] > intel_display_power_put_async_work+0x91/0xf0 [i915] > process_one_work+0x260/0x600 > ? worker_thread+0xc9/0x380 > worker_thread+0x37/0x380 > ? process_one_work+0x600/0x600 > kthread+0x119/0x130 > ? kthread_park+0x80/0x80 > ret_from_fork+0x24/0x50 > [ cut here ] > WARNING: CPU: 3 PID: 1142 at
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add missing deinitialization cases of load failure
== Series Details == Series: drm/i915: Add missing deinitialization cases of load failure URL : https://patchwork.freedesktop.org/series/75987/ State : success == Summary == CI Bug Log - changes from CI_DRM_8302 -> Patchwork_17316 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17316/index.html Known issues Here are the changes found in Patchwork_17316 that come from known issues: ### IGT changes ### Warnings * igt@i915_pm_rpm@module-reload: - fi-kbl-x1275: [FAIL][1] ([i915#62] / [i915#95]) -> [SKIP][2] ([fdo#109271]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/fi-kbl-x1275/igt@i915_pm_...@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17316/fi-kbl-x1275/igt@i915_pm_...@module-reload.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (52 -> 45) -- Missing(7): fi-hsw-4200u fi-skl-6770hq fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8302 -> Patchwork_17316 CI-20190529: 20190529 CI_DRM_8302: e022648f1633f24b4ec326805f1de22209826519 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5591: f57b7fdbe8d04ce3edf0433a03c7d9d5c3d96680 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17316: 40cdb21a2c1ee7f94a8f8754870d0d3ee3b85f11 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 40cdb21a2c1e drm/i915: Add missing deinitialization cases of load failure == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17316/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Add missing deinitialization cases of load failure
== Series Details == Series: drm/i915: Add missing deinitialization cases of load failure URL : https://patchwork.freedesktop.org/series/75987/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 /home/cidrm/kernel/Documentation/gpu/i915.rst:610: WARNING: duplicate label gpu/i915:layout, other instance in /home/cidrm/kernel/Documentation/gpu/i915.rst ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915: Add missing deinitialization cases of load failure
Quoting José Roberto de Souza (2020-04-15 20:14:08) > + i915_reset_error_state(i915); If you are bored, we should move this to unregister as that is the last point at which it can be accessed from userspace. Hopefully I remember next time we are rearranging this sequence. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add missing deinitialization cases of load failure
== Series Details == Series: drm/i915: Add missing deinitialization cases of load failure URL : https://patchwork.freedesktop.org/series/75987/ State : warning == Summary == $ dim checkpatch origin/drm-tip 40cdb21a2c1e drm/i915: Add missing deinitialization cases of load failure -:17: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #17: [drm:__intel_engine_init_ctx_wa [i915]] Initialized 3 context workarounds on rcs'0 total: 0 errors, 1 warnings, 0 checks, 59 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] drm/i915/perf: Reduce cpu overhead for blocking perf OA reads
On 15/04/2020 21:55, Umesh Nerlige Ramappa wrote:
On Wed, Apr 15, 2020 at 01:00:30PM +0300, Lionel Landwerlin wrote:
On 13/04/2020 18:48, Umesh Nerlige Ramappa wrote:
A condition in wait_event_interruptible seems to be checked twice
before
waiting on the event to occur. These checks are redundant when hrtimer
events will call oa_buffer_check_unlocked to update the oa_buffer tail
pointers. The redundant checks add cpu overhead. Simplify the check
to reduce cpu overhead when using blocking io to read oa buffer
reports.
Signed-off-by: Umesh Nerlige Ramappa
I cherry picked this patch alone and it seems to break the
disabled-read-error test.
Strange. I don't see it fail on my CFL. I am apply this on the latest
drm-tip from yesterday.
The patch still checks if reports are available before blocking. The
behavior should still be the same w.r.t this test.
What machine did you run it on? I will try on the same. Any chance you
have the debug output from the test?
Thanks,
Umesh
I got that on SKL GT4 : http://paste.debian.net/1140604/
Thanks,
-Lionel
---
drivers/gpu/drm/i915/i915_perf.c | 28 +++-
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c
b/drivers/gpu/drm/i915/i915_perf.c
index 5cde3e4e7be6..e28a3ab83fde 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -541,6 +541,32 @@ static bool oa_buffer_check_unlocked(struct
i915_perf_stream *stream)
return pollin;
}
+/**
+ * oa_buffer_check_reports - quick check if reports are available
+ * @stream: i915 stream instance
+ *
+ * The return from this function is used as a condition for
+ * wait_event_interruptible in blocking read. This is used to detect
+ * available reports.
+ *
+ * A condition in wait_event_interruptible seems to be checked
twice before
+ * waiting on an event to occur. These checks are redundant when
hrtimer events
+ * will call oa_buffer_check_unlocked to update the oa_buffer tail
pointers. The
+ * redundant checks add cpu overhead. We simplify the check to
reduce cpu
+ * overhead.
+ */
+static bool oa_buffer_check_reports(struct i915_perf_stream *stream)
+{
+ unsigned long flags;
+ bool available;
+
+ spin_lock_irqsave(>oa_buffer.ptr_lock, flags);
+ available = stream->oa_buffer.tail != stream->oa_buffer.head;
+ spin_unlock_irqrestore(>oa_buffer.ptr_lock, flags);
+
+ return available;
+}
+
/**
* append_oa_status - Appends a status record to a userspace read()
buffer.
* @stream: An i915-perf stream opened for OA metrics
@@ -1150,7 +1176,7 @@ static int i915_oa_wait_unlocked(struct
i915_perf_stream *stream)
return -EIO;
return wait_event_interruptible(stream->poll_wq,
- oa_buffer_check_unlocked(stream));
+ oa_buffer_check_reports(stream));
}
/**
___
Intel-gfx mailing list
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Re: [Intel-gfx] [PATCH] drm/i915/gt: Update PMINTRMSK holding fw
Chris Wilson writes:
> If we use a non-forcewaked write to PMINTRMSK, it does not take effect
> until much later, if at all, causing a loss of RPS interrupts and no GPU
> reclocking, leaving the GPU running at the wrong frequency for long
> periods of time.
>
> Reported-by: Francisco Jerez
> Suggested-by: Francisco Jerez
> Fixes: 35cc7f32c298 ("drm/i915/gt: Use non-forcewake writes for RPS")
> Signed-off-by: Chris Wilson
Reviewed-by: Francisco Jerez
> Cc: Francisco Jerez
> Cc: Mika Kuoppala
> Cc: Andi Shyti
> Cc: # v5.6+
> ---
> drivers/gpu/drm/i915/gt/intel_rps.c | 9 ++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
> b/drivers/gpu/drm/i915/gt/intel_rps.c
> index 86110458e2a7..6a3505467406 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -81,13 +81,14 @@ static void rps_enable_interrupts(struct intel_rps *rps)
> events = (GEN6_PM_RP_UP_THRESHOLD |
> GEN6_PM_RP_DOWN_THRESHOLD |
> GEN6_PM_RP_DOWN_TIMEOUT);
> -
> WRITE_ONCE(rps->pm_events, events);
> +
> spin_lock_irq(>irq_lock);
> gen6_gt_pm_enable_irq(gt, rps->pm_events);
> spin_unlock_irq(>irq_lock);
>
> - set(gt->uncore, GEN6_PMINTRMSK, rps_pm_mask(rps, rps->cur_freq));
> + intel_uncore_write(gt->uncore,
> + GEN6_PMINTRMSK, rps_pm_mask(rps, rps->last_freq));
> }
>
> static void gen6_rps_reset_interrupts(struct intel_rps *rps)
> @@ -120,7 +121,9 @@ static void rps_disable_interrupts(struct intel_rps *rps)
> struct intel_gt *gt = rps_to_gt(rps);
>
> WRITE_ONCE(rps->pm_events, 0);
> - set(gt->uncore, GEN6_PMINTRMSK, rps_pm_sanitize_mask(rps, ~0u));
> +
> + intel_uncore_write(gt->uncore,
> + GEN6_PMINTRMSK, rps_pm_sanitize_mask(rps, ~0u));
>
> spin_lock_irq(>irq_lock);
> gen6_gt_pm_disable_irq(gt, GEN6_PM_RPS_EVENTS);
> --
> 2.20.1
signature.asc
Description: PGP signature
___
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[Intel-gfx] [PATCH v2] drm/i915: Add missing deinitialization cases of load failure
The intel_display_power_put_async() used in TC cold sequences made easy to hit the missing deinitialization of driver in case of load failure as seen in the stack trace bellow. intel_modeset_driver_remove_noirq() had to be removed from i915_driver_modeset_remove_noirq() as those are different initialialition steps with IRQ and GEM initialization in between then. [drm:__intel_engine_init_ctx_wa [i915]] Initialized 3 context workarounds on rcs'0 [drm:__i915_inject_probe_error [i915]] Injecting failure -19 at checkpoint 36 [__uc_init:294] [drm:i915_hdcp_component_unbind [i915]] I915 HDCP comp unbind [drm:edp_panel_vdd_off_sync [i915]] Turning [ENCODER:275:DDI A] VDD off [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x PP_CONTROL: 0x0060 [drm:intel_power_well_disable [i915]] disabling AUX A general protection fault, probably for non-canonical address 0x6b6b6b6b6b6b6b6b: [#1] PREEMPT SMP NOPTI CPU: 3 PID: 1142 Comm: kworker/u16:20 Tainted: G U 5.6.0-CI-Patchwork_17226+ #1 Hardware name: Intel Corporation Tiger Lake Client Platform/TigerLake U DDR4 SODIMM RVP, BIOS TGLSFWI1.R00.2457.A16.1912270059 12/27/2019 Workqueue: events_unbound intel_display_power_put_async_work [i915] RIP: 0010:__intel_display_power_put_domain+0xa5/0x180 [i915] Code: 48 85 c0 78 54 44 89 e1 41 bd 01 00 00 00 49 c7 c4 80 44 41 a0 49 d3 e5 eb 0d 48 83 eb 10 48 3b 9d 08 ad 00 00 78 32 48 8b 03 <4c> 85 68 10 74 ea 8b 53 08 85 d2 74 2d 83 ea 01 85 d2 89 53 08 75 RSP: 0018:c961fdb0 EFLAGS: 00010206 RAX: 6b6b6b6b6b6b6b6b RBX: 8884948f5df0 RCX: 003d RDX: 8001 RSI: RDI: RBP: 888479be R08: 88849a180920 R09: R10: R11: R12: a0414480 R13: 2000 R14: 888479beb320 R15: 2000 FS: () GS:88849ff8() knlGS: CS: 0010 DS: ES: CR0: 80050033 CR2: 5634fa8ed670 CR3: 05610004 CR4: 00760ee0 PKRU: 5554 Call Trace: release_async_put_domains+0x9b/0x110 [i915] intel_display_power_put_async_work+0x91/0xf0 [i915] process_one_work+0x260/0x600 ? worker_thread+0xc9/0x380 worker_thread+0x37/0x380 ? process_one_work+0x600/0x600 kthread+0x119/0x130 ? kthread_park+0x80/0x80 ret_from_fork+0x24/0x50 Modules linked in: i915(+) vgem snd_hda_codec_hdmi mei_hdcp x86_pkg_temp_thermal coretemp crct10dif_pclmul crc32_pclmul cdc_ether usbnet mii snd_intel_dspcfg ghash_clmulni_intel snd_hda_codec snd_hwdep snd_hda_core e1000e ptp mei_me snd_pcm pps_core mei intel_lpss_pci prime_numbers [last unloaded: i915] ---[ end trace b402d1b4060f8b97 ]--- BUG: sleeping function called from invalid context at kernel/sched/completion.c:99 in_atomic(): 0, irqs_disabled(): 0, non_block: 0, pid: 1142, name: kworker/u16:20 INFO: lockdep is turned off. Preemption disabled at: [<>] 0x0 CPU: 3 PID: 1142 Comm: kworker/u16:20 Tainted: G UD 5.6.0-CI-Patchwork_17226+ #1 Hardware name: Intel Corporation Tiger Lake Client Platform/TigerLake U DDR4 SODIMM RVP, BIOS TGLSFWI1.R00.2457.A16.1912270059 12/27/2019 Workqueue: events_unbound intel_display_power_put_async_work [i915] Call Trace: dump_stack+0x71/0x9b ___might_sleep+0x178/0x260 wait_for_completion+0x37/0x1a0 virt_efi_query_variable_info+0x161/0x1b0 efi_query_variable_store+0xb3/0x1a0 ? efivar_entry_set_safe+0x19c/0x220 efivar_entry_set_safe+0x19c/0x220 ? efi_pstore_write+0x10b/0x150 ? efi_pstore_write+0xa0/0x150 efi_pstore_write+0x10b/0x150 pstore_dump+0x123/0x340 kmsg_dump+0x87/0x1b0 oops_end+0x3e/0x90 do_general_protection+0x1c3/0x2f0 general_protection+0x2d/0x40 RIP: 0010:__intel_display_power_put_domain+0xa5/0x180 [i915] Code: 48 85 c0 78 54 44 89 e1 41 bd 01 00 00 00 49 c7 c4 80 44 41 a0 49 d3 e5 eb 0d 48 83 eb 10 48 3b 9d 08 ad 00 00 78 32 48 8b 03 <4c> 85 68 10 74 ea 8b 53 08 85 d2 74 2d 83 ea 01 85 d2 89 53 08 75 RSP: 0018:c961fdb0 EFLAGS: 00010206 RAX: 6b6b6b6b6b6b6b6b RBX: 8884948f5df0 RCX: 003d RDX: 8001 RSI: RDI: RBP: 888479be R08: 88849a180920 R09: R10: R11: R12: a0414480 R13: 2000 R14: 888479beb320 R15: 2000 release_async_put_domains+0x9b/0x110 [i915] intel_display_power_put_async_work+0x91/0xf0 [i915] process_one_work+0x260/0x600 ? worker_thread+0xc9/0x380 worker_thread+0x37/0x380 ? process_one_work+0x600/0x600 kthread+0x119/0x130 ? kthread_park+0x80/0x80 ret_from_fork+0x24/0x50 [ cut here ] WARNING: CPU: 3 PID: 1142 at kernel/rcu/tree_plugin.h:293 rcu_note_context_switch+0x87/0x650 Modules linked in: i915(+) vgem snd_hda_codec_hdmi mei_hdcp x86_pkg_temp_thermal coretemp crct10dif_pclmul crc32_pclmul cdc_ether usbnet mii snd_intel_dspcfg ghash_clmulni_intel snd_hda_codec snd_hwdep
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915/selftests: Exercise basic RPS interrupt generation
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/selftests: Exercise basic RPS
interrupt generation
URL : https://patchwork.freedesktop.org/series/75983/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8302 -> Patchwork_17314
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17314/index.html
Known issues
Here are the changes found in Patchwork_17314 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@gt_contexts:
- fi-bwr-2160:[PASS][1] -> [INCOMPLETE][2] ([i915#1726])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/fi-bwr-2160/igt@i915_selftest@live@gt_contexts.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17314/fi-bwr-2160/igt@i915_selftest@live@gt_contexts.html
* igt@i915_selftest@live@gt_pm:
- fi-tgl-y: [PASS][3] -> [DMESG-FAIL][4] ([i915#1725])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/fi-tgl-y/igt@i915_selftest@live@gt_pm.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17314/fi-tgl-y/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@hangcheck:
- fi-icl-guc: [PASS][5] -> [INCOMPLETE][6] ([i915#1580])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/fi-icl-guc/igt@i915_selftest@l...@hangcheck.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17314/fi-icl-guc/igt@i915_selftest@l...@hangcheck.html
Warnings
* igt@i915_pm_rpm@module-reload:
- fi-kbl-x1275: [FAIL][7] ([i915#62] / [i915#95]) -> [SKIP][8]
([fdo#109271])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/fi-kbl-x1275/igt@i915_pm_...@module-reload.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17314/fi-kbl-x1275/igt@i915_pm_...@module-reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1580]: https://gitlab.freedesktop.org/drm/intel/issues/1580
[i915#1725]: https://gitlab.freedesktop.org/drm/intel/issues/1725
[i915#1726]: https://gitlab.freedesktop.org/drm/intel/issues/1726
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (52 -> 45)
--
Missing(7): fi-hsw-4200u fi-skl-6770hq fi-byt-squawks fi-bsw-cyan
fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_8302 -> Patchwork_17314
CI-20190529: 20190529
CI_DRM_8302: e022648f1633f24b4ec326805f1de22209826519 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5591: f57b7fdbe8d04ce3edf0433a03c7d9d5c3d96680 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17314: 8f0a2624ce986e0756ec6cf5148ca50c29b2c14f @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
8f0a2624ce98 drm/i915/gt: Update PMINTRMSK holding fw
fbb035e1d2f5 drm/i915/selftests: Exercise basic RPS interrupt generation
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17314/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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Re: [Intel-gfx] [PATCH 1/3] drm/i915/perf: Reduce cpu overhead for blocking perf OA reads
On Wed, Apr 15, 2020 at 01:00:30PM +0300, Lionel Landwerlin wrote:
On 13/04/2020 18:48, Umesh Nerlige Ramappa wrote:
A condition in wait_event_interruptible seems to be checked twice before
waiting on the event to occur. These checks are redundant when hrtimer
events will call oa_buffer_check_unlocked to update the oa_buffer tail
pointers. The redundant checks add cpu overhead. Simplify the check
to reduce cpu overhead when using blocking io to read oa buffer reports.
Signed-off-by: Umesh Nerlige Ramappa
I cherry picked this patch alone and it seems to break the
disabled-read-error test.
Strange. I don't see it fail on my CFL. I am apply this on the latest
drm-tip from yesterday.
The patch still checks if reports are available before blocking. The
behavior should still be the same w.r.t this test.
What machine did you run it on? I will try on the same. Any chance you
have the debug output from the test?
Thanks,
Umesh
---
drivers/gpu/drm/i915/i915_perf.c | 28 +++-
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 5cde3e4e7be6..e28a3ab83fde 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -541,6 +541,32 @@ static bool oa_buffer_check_unlocked(struct
i915_perf_stream *stream)
return pollin;
}
+/**
+ * oa_buffer_check_reports - quick check if reports are available
+ * @stream: i915 stream instance
+ *
+ * The return from this function is used as a condition for
+ * wait_event_interruptible in blocking read. This is used to detect
+ * available reports.
+ *
+ * A condition in wait_event_interruptible seems to be checked twice before
+ * waiting on an event to occur. These checks are redundant when hrtimer events
+ * will call oa_buffer_check_unlocked to update the oa_buffer tail pointers.
The
+ * redundant checks add cpu overhead. We simplify the check to reduce cpu
+ * overhead.
+ */
+static bool oa_buffer_check_reports(struct i915_perf_stream *stream)
+{
+ unsigned long flags;
+ bool available;
+
+ spin_lock_irqsave(>oa_buffer.ptr_lock, flags);
+ available = stream->oa_buffer.tail != stream->oa_buffer.head;
+ spin_unlock_irqrestore(>oa_buffer.ptr_lock, flags);
+
+ return available;
+}
+
/**
* append_oa_status - Appends a status record to a userspace read() buffer.
* @stream: An i915-perf stream opened for OA metrics
@@ -1150,7 +1176,7 @@ static int i915_oa_wait_unlocked(struct i915_perf_stream
*stream)
return -EIO;
return wait_event_interruptible(stream->poll_wq,
- oa_buffer_check_unlocked(stream));
+ oa_buffer_check_reports(stream));
}
/**
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for i915 lpsp support for lpsp igt (rev9)
== Series Details ==
Series: i915 lpsp support for lpsp igt (rev9)
URL : https://patchwork.freedesktop.org/series/74648/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8302 -> Patchwork_17315
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17315/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_17315:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@debugfs_test@read_all_entries:
- {fi-ehl-1}: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/fi-ehl-1/igt@debugfs_test@read_all_entries.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17315/fi-ehl-1/igt@debugfs_test@read_all_entries.html
* igt@runner@aborted:
- {fi-ehl-1}: NOTRUN -> [FAIL][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17315/fi-ehl-1/igt@run...@aborted.html
Known issues
Here are the changes found in Patchwork_17315 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_pm_rpm@module-reload:
- fi-kbl-8809g: [PASS][4] -> [SKIP][5] ([fdo#109271])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/fi-kbl-8809g/igt@i915_pm_...@module-reload.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17315/fi-kbl-8809g/igt@i915_pm_...@module-reload.html
Warnings
* igt@i915_pm_rpm@module-reload:
- fi-kbl-x1275: [FAIL][6] ([i915#62] / [i915#95]) -> [SKIP][7]
([fdo#109271])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/fi-kbl-x1275/igt@i915_pm_...@module-reload.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17315/fi-kbl-x1275/igt@i915_pm_...@module-reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (52 -> 45)
--
Missing(7): fi-hsw-4200u fi-skl-6770hq fi-byt-squawks fi-bsw-cyan
fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* IGT: IGT_5591 -> IGTPW_4467
* Linux: CI_DRM_8302 -> Patchwork_17315
CI-20190529: 20190529
CI_DRM_8302: e022648f1633f24b4ec326805f1de22209826519 @
git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_4467: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4467/index.html
IGT_5591: f57b7fdbe8d04ce3edf0433a03c7d9d5c3d96680 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17315: 533d9b6137fff01ee750d8b8cab83c0bd926951b @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
533d9b6137ff drm/i915: Add i915_lpsp_status debugfs attribute
a0136f3b2b9d drm/i915: Add connector dbgfs for all connectors
743a1164e90d drm/i915: Add i915_lpsp_capability debugfs
2c368e8194f9 drm/i915: Power well id for ICL PG3
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17315/index.html
___
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[Intel-gfx] ✗ Fi.CI.DOCS: warning for i915 lpsp support for lpsp igt (rev9)
== Series Details == Series: i915 lpsp support for lpsp igt (rev9) URL : https://patchwork.freedesktop.org/series/74648/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 /home/cidrm/kernel/Documentation/gpu/i915.rst:610: WARNING: duplicate label gpu/i915:layout, other instance in /home/cidrm/kernel/Documentation/gpu/i915.rst ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/2] drm/i915/selftests: Exercise basic RPS interrupt generation
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/selftests: Exercise basic RPS
interrupt generation
URL : https://patchwork.freedesktop.org/series/75983/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8302 -> Patchwork_17314
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_17314 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_17314, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17314/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_17314:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live@gt_contexts:
- fi-bwr-2160:[PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/fi-bwr-2160/igt@i915_selftest@live@gt_contexts.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17314/fi-bwr-2160/igt@i915_selftest@live@gt_contexts.html
* igt@i915_selftest@live@gt_pm:
- fi-tgl-y: [PASS][3] -> [DMESG-FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/fi-tgl-y/igt@i915_selftest@live@gt_pm.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17314/fi-tgl-y/igt@i915_selftest@live@gt_pm.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@gt_pm:
- {fi-tgl-u}: [PASS][5] -> [DMESG-FAIL][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/fi-tgl-u/igt@i915_selftest@live@gt_pm.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17314/fi-tgl-u/igt@i915_selftest@live@gt_pm.html
- {fi-tgl-dsi}: [PASS][7] -> [DMESG-FAIL][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/fi-tgl-dsi/igt@i915_selftest@live@gt_pm.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17314/fi-tgl-dsi/igt@i915_selftest@live@gt_pm.html
Known issues
Here are the changes found in Patchwork_17314 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@hangcheck:
- fi-icl-guc: [PASS][9] -> [INCOMPLETE][10] ([i915#1580])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/fi-icl-guc/igt@i915_selftest@l...@hangcheck.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17314/fi-icl-guc/igt@i915_selftest@l...@hangcheck.html
Warnings
* igt@i915_pm_rpm@module-reload:
- fi-kbl-x1275: [FAIL][11] ([i915#62] / [i915#95]) -> [SKIP][12]
([fdo#109271])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8302/fi-kbl-x1275/igt@i915_pm_...@module-reload.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17314/fi-kbl-x1275/igt@i915_pm_...@module-reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1580]: https://gitlab.freedesktop.org/drm/intel/issues/1580
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (52 -> 45)
--
Missing(7): fi-hsw-4200u fi-skl-6770hq fi-byt-squawks fi-bsw-cyan
fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_8302 -> Patchwork_17314
CI-20190529: 20190529
CI_DRM_8302: e022648f1633f24b4ec326805f1de22209826519 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5591: f57b7fdbe8d04ce3edf0433a03c7d9d5c3d96680 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17314: 8f0a2624ce986e0756ec6cf5148ca50c29b2c14f @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
8f0a2624ce98 drm/i915/gt: Update PMINTRMSK holding fw
fbb035e1d2f5 drm/i915/selftests: Exercise basic RPS interrupt generation
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17314/index.html
___
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Re: [Intel-gfx] [PATCH i-g-t] lib: Use read() for timerfd timeout detection
On Wed, 15 Apr 2020 07:39:00 -0700, Chris Wilson wrote:
>
> The poll() is proving unreliable, where our tests timeout without the
> spinner being terminated. Let's try a blocking read instead!
>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1676
> Signed-off-by: Chris Wilson
> Cc: "Dixit, Ashutosh"
Reviewed-by: Ashutosh Dixit
> ---
> lib/igt_dummyload.c | 12 ++--
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
> index 99ca84ad8..ae0fb9378 100644
> --- a/lib/igt_dummyload.c
> +++ b/lib/igt_dummyload.c
> @@ -399,14 +399,14 @@ igt_spin_factory(int fd, const struct igt_spin_factory
> *opts)
> static void *timer_thread(void *data)
> {
> igt_spin_t *spin = data;
> - struct pollfd pfd = {
> - .fd = spin->timerfd,
> - .events = POLLIN,
> - };
> + uint64_t overruns = 0;
>
> - if (poll(, 1, -1) >= 0)
> - igt_spin_end(spin);
> + /* Wait until we see the timer fire, or we get cancelled */
> + do {
> + read(spin->timerfd, , sizeof(overruns));
> + } while (!overruns);
>
> + igt_spin_end(spin);
> return NULL;
> }
>
> --
> 2.26.0
>
___
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[Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [CI,1/2] drm/i915/selftests: Exercise basic RPS interrupt generation
== Series Details == Series: series starting with [CI,1/2] drm/i915/selftests: Exercise basic RPS interrupt generation URL : https://patchwork.freedesktop.org/series/75983/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 /home/cidrm/kernel/Documentation/gpu/i915.rst:610: WARNING: duplicate label gpu/i915:layout, other instance in /home/cidrm/kernel/Documentation/gpu/i915.rst ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 05/59] drm/vboxvidoe: use managed pci functions
On Wed, Apr 15, 2020 at 05:03:55PM +0200, Hans de Goede wrote:
> Hi,
>
> On 4/15/20 9:39 AM, Daniel Vetter wrote:
> > Allows us to drop the cleanup code on the floor.
> >
> > Sam noticed in his review:
> > > With this change we avoid calling pci_disable_device()
> > > twise in case vbox_mm_init() fails.
> > > Once in vbox_hw_fini() and once in the error path.
> >
> > v2: Include Sam's review remarks
> >
> > Acked-by: Sam Ravnborg
> > Signed-off-by: Daniel Vetter
> > Cc: Hans de Goede
> > ---
> > drivers/gpu/drm/vboxvideo/vbox_drv.c | 6 ++
> > drivers/gpu/drm/vboxvideo/vbox_main.c | 7 +--
> > 2 files changed, 3 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/vboxvideo/vbox_drv.c
> > b/drivers/gpu/drm/vboxvideo/vbox_drv.c
> > index cfa4639c5142..cf2e3e6a2388 100644
> > --- a/drivers/gpu/drm/vboxvideo/vbox_drv.c
> > +++ b/drivers/gpu/drm/vboxvideo/vbox_drv.c
> > @@ -55,13 +55,13 @@ static int vbox_pci_probe(struct pci_dev *pdev, const
> > struct pci_device_id *ent)
> > pci_set_drvdata(pdev, vbox);
> > mutex_init(>hw_mutex);
> > - ret = pci_enable_device(pdev);
> > + ret = pcim_enable_device(pdev);
> > if (ret)
> > return ret;
> > ret = vbox_hw_init(vbox);
> > if (ret)
> > - goto err_pci_disable;
> > + return ret;
> > ret = vbox_mm_init(vbox);
> > if (ret)
> > @@ -91,8 +91,6 @@ static int vbox_pci_probe(struct pci_dev *pdev, const
> > struct pci_device_id *ent)
> > vbox_mm_fini(vbox);
> > err_hw_fini:
> > vbox_hw_fini(vbox);
> > -err_pci_disable:
> > - pci_disable_device(pdev);
> > return ret;
> > }
> > diff --git a/drivers/gpu/drm/vboxvideo/vbox_main.c
> > b/drivers/gpu/drm/vboxvideo/vbox_main.c
> > index 9dcab115a261..1336ab9795fc 100644
> > --- a/drivers/gpu/drm/vboxvideo/vbox_main.c
> > +++ b/drivers/gpu/drm/vboxvideo/vbox_main.c
> > @@ -71,8 +71,6 @@ static void vbox_accel_fini(struct vbox_private *vbox)
> > for (i = 0; i < vbox->num_crtcs; ++i)
> > vbva_disable(>vbva_info[i], vbox->guest_pool, i);
> > -
> > - pci_iounmap(vbox->ddev.pdev, vbox->vbva_buffers);
> > }
> > /* Do we support the 4.3 plus mode hint reporting interface? */
>
> This seems to be missing the conversion of the iomap_range call to
> the devm equivalent ? :
>
> drivers/gpu/drm/vboxvideo/vbox_main.c
> 44: vbox->vbva_buffers = pci_iomap_range(vbox->ddev.pdev, 0, ...
pcim_enable_device is pure magic, it converts _all_ pci_ calls on that
device to the managed version. There's no other manged pci_ functions (ok
1-2 more, but they're rather special).
-Daniel
>
> Regards,
>
> Hans
>
>
>
>
>
> > @@ -125,7 +123,7 @@ int vbox_hw_init(struct vbox_private *vbox)
> > /* Create guest-heap mem-pool use 2^4 = 16 byte chunks */
> > vbox->guest_pool = gen_pool_create(4, -1);
> > if (!vbox->guest_pool)
> > - goto err_unmap_guest_heap;
> > + return -ENOMEM;
> > ret = gen_pool_add_virt(vbox->guest_pool,
> > (unsigned long)vbox->guest_heap,
> > @@ -168,8 +166,6 @@ int vbox_hw_init(struct vbox_private *vbox)
> > err_destroy_guest_pool:
> > gen_pool_destroy(vbox->guest_pool);
> > -err_unmap_guest_heap:
> > - pci_iounmap(vbox->ddev.pdev, vbox->guest_heap);
> > return ret;
> > }
> > @@ -177,5 +173,4 @@ void vbox_hw_fini(struct vbox_private *vbox)
> > {
> > vbox_accel_fini(vbox);
> > gen_pool_destroy(vbox->guest_pool);
> > - pci_iounmap(vbox->ddev.pdev, vbox->guest_heap);
> > }
> >
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/2] drm/i915/selftests: Exercise basic RPS interrupt generation
== Series Details == Series: series starting with [CI,1/2] drm/i915/selftests: Exercise basic RPS interrupt generation URL : https://patchwork.freedesktop.org/series/75983/ State : warning == Summary == $ dim checkpatch origin/drm-tip fbb035e1d2f5 drm/i915/selftests: Exercise basic RPS interrupt generation -:46: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #46: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 255 lines checked 8f0a2624ce98 drm/i915/gt: Update PMINTRMSK holding fw ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 05/59] drm/vboxvidoe: use managed pci functions
The commit's headline says 'vboxvidoe'.
Am 15.04.20 um 09:39 schrieb Daniel Vetter:
> Allows us to drop the cleanup code on the floor.
>
> Sam noticed in his review:
>> With this change we avoid calling pci_disable_device()
>> twise in case vbox_mm_init() fails.
>> Once in vbox_hw_fini() and once in the error path.
>
> v2: Include Sam's review remarks
>
> Acked-by: Sam Ravnborg
> Signed-off-by: Daniel Vetter
> Cc: Hans de Goede
> ---
> drivers/gpu/drm/vboxvideo/vbox_drv.c | 6 ++
> drivers/gpu/drm/vboxvideo/vbox_main.c | 7 +--
> 2 files changed, 3 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/vboxvideo/vbox_drv.c
> b/drivers/gpu/drm/vboxvideo/vbox_drv.c
> index cfa4639c5142..cf2e3e6a2388 100644
> --- a/drivers/gpu/drm/vboxvideo/vbox_drv.c
> +++ b/drivers/gpu/drm/vboxvideo/vbox_drv.c
> @@ -55,13 +55,13 @@ static int vbox_pci_probe(struct pci_dev *pdev, const
> struct pci_device_id *ent)
> pci_set_drvdata(pdev, vbox);
> mutex_init(>hw_mutex);
>
> - ret = pci_enable_device(pdev);
> + ret = pcim_enable_device(pdev);
> if (ret)
> return ret;
>
> ret = vbox_hw_init(vbox);
> if (ret)
> - goto err_pci_disable;
> + return ret;
>
> ret = vbox_mm_init(vbox);
> if (ret)
> @@ -91,8 +91,6 @@ static int vbox_pci_probe(struct pci_dev *pdev, const
> struct pci_device_id *ent)
> vbox_mm_fini(vbox);
> err_hw_fini:
> vbox_hw_fini(vbox);
> -err_pci_disable:
> - pci_disable_device(pdev);
> return ret;
> }
>
> diff --git a/drivers/gpu/drm/vboxvideo/vbox_main.c
> b/drivers/gpu/drm/vboxvideo/vbox_main.c
> index 9dcab115a261..1336ab9795fc 100644
> --- a/drivers/gpu/drm/vboxvideo/vbox_main.c
> +++ b/drivers/gpu/drm/vboxvideo/vbox_main.c
> @@ -71,8 +71,6 @@ static void vbox_accel_fini(struct vbox_private *vbox)
>
> for (i = 0; i < vbox->num_crtcs; ++i)
> vbva_disable(>vbva_info[i], vbox->guest_pool, i);
> -
> - pci_iounmap(vbox->ddev.pdev, vbox->vbva_buffers);
> }
>
> /* Do we support the 4.3 plus mode hint reporting interface? */
> @@ -125,7 +123,7 @@ int vbox_hw_init(struct vbox_private *vbox)
> /* Create guest-heap mem-pool use 2^4 = 16 byte chunks */
> vbox->guest_pool = gen_pool_create(4, -1);
> if (!vbox->guest_pool)
> - goto err_unmap_guest_heap;
> + return -ENOMEM;
>
> ret = gen_pool_add_virt(vbox->guest_pool,
> (unsigned long)vbox->guest_heap,
> @@ -168,8 +166,6 @@ int vbox_hw_init(struct vbox_private *vbox)
>
> err_destroy_guest_pool:
> gen_pool_destroy(vbox->guest_pool);
> -err_unmap_guest_heap:
> - pci_iounmap(vbox->ddev.pdev, vbox->guest_heap);
> return ret;
> }
>
> @@ -177,5 +173,4 @@ void vbox_hw_fini(struct vbox_private *vbox)
> {
> vbox_accel_fini(vbox);
> gen_pool_destroy(vbox->guest_pool);
> - pci_iounmap(vbox->ddev.pdev, vbox->guest_heap);
> }
>
--
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Maxfeldstr. 5, 90409 Nürnberg, Germany
(HRB 36809, AG Nürnberg)
Geschäftsführer: Felix Imendörffer
signature.asc
Description: OpenPGP digital signature
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[Intel-gfx] [PATCH v5 2/4] drm/i915: Add i915_lpsp_capability debugfs
New i915_pm_lpsp igt solution approach relies on connector specific
debugfs attribute i915_lpsp_capability, it exposes whether an output is
capable of driving lpsp.
v2:
- CI fixup.
v3:
- register i915_lpsp_info only for supported connector. [Jani]
- use intel_display_power_well_is_enabled() instead of looking
inside power_well count. [Jani]
- fixes the lpsp capable conditional logic. [Jani]
- combined the lpsp capable and enable info. [Jani]
v4:
- Separate out connector based debugfs i915_lpsp_capability
lpsp enable status would be exposes by different entry. [Animesh]
v5:
- Add Platform Gen condition to add i915_lpsp_capability
and some cosmetic nitpick changes. [Animesh]
Reviewed-by: Animesh Manna
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_debugfs.c | 53 +++
1 file changed, 53 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index bdeea2e02642..ea48de3cac24 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -1991,6 +1991,48 @@ static int i915_hdcp_sink_capability_show(struct
seq_file *m, void *data)
}
DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability);
+#define LPSP_CAPABLE(COND) (COND ? seq_puts(m, "LPSP: capable\n") : \
+ seq_puts(m, "LPSP: incapable\n"))
+
+static int i915_lpsp_capability_show(struct seq_file *m, void *data)
+{
+ struct drm_connector *connector = m->private;
+ struct intel_encoder *encoder =
+ intel_attached_encoder(to_intel_connector(connector));
+ struct drm_i915_private *i915 = to_i915(connector->dev);
+
+ if (connector->status != connector_status_connected)
+ return -ENODEV;
+
+ switch (INTEL_GEN(i915)) {
+ case 12:
+ /*
+* Actually TGL can drive LPSP on port till DDI_C
+* but there is no physical connected DDI_C on TGL sku's,
+* even driver is not initilizing DDI_C port for gen12.
+*/
+ LPSP_CAPABLE(encoder->port <= PORT_B);
+ break;
+ case 11:
+ LPSP_CAPABLE(connector->connector_type ==
DRM_MODE_CONNECTOR_DSI ||
+connector->connector_type ==
DRM_MODE_CONNECTOR_eDP);
+ break;
+ case 10:
+ case 9:
+ LPSP_CAPABLE(encoder->port == PORT_A &&
+(connector->connector_type ==
DRM_MODE_CONNECTOR_DSI ||
+connector->connector_type ==
DRM_MODE_CONNECTOR_eDP ||
+connector->connector_type ==
DRM_MODE_CONNECTOR_DisplayPort));
+ break;
+ default:
+ if (IS_HASWELL(i915) || IS_BROADWELL(i915))
+ LPSP_CAPABLE(connector->connector_type ==
DRM_MODE_CONNECTOR_eDP);
+ }
+
+ return 0;
+}
+DEFINE_SHOW_ATTRIBUTE(i915_lpsp_capability);
+
static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
{
struct drm_connector *connector = m->private;
@@ -2134,5 +2176,16 @@ int intel_connector_debugfs_add(struct drm_connector
*connector)
debugfs_create_file("i915_dsc_fec_support", S_IRUGO, root,
connector, _dsc_fec_support_fops);
+ /* Legacy panels doesn't lpsp on any platform */
+ if ((INTEL_GEN(dev_priv) >= 9 || IS_HASWELL(dev_priv) ||
+IS_BROADWELL(dev_priv)) &&
+(connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
+connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
+connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
+connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
+connector->connector_type == DRM_MODE_CONNECTOR_HDMIB))
+ debugfs_create_file("i915_lpsp_capability", 0444, root,
+ connector, _lpsp_capability_fops);
+
return 0;
}
--
2.26.0
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[Intel-gfx] [PATCH v5 1/4] drm/i915: Power well id for ICL PG3
Gen11 onwards PG3 is contains functions for pipe B,
external displays, and VGA. It make sense to add
a power well id with name ICL_DISP_PW_3 rather then
TGL_DISP_PW_3, Also PG3 power well id requires to
know if lpsp is enabled.
Reviewed-by: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display_power.c | 6 +++---
drivers/gpu/drm/i915/display/intel_display_power.h | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 433e5a81dd4d..3672c00be94a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -943,7 +943,7 @@ static void assert_can_enable_dc5(struct drm_i915_private
*dev_priv)
/* Power wells at this level and above must be disabled for DC5 entry */
if (INTEL_GEN(dev_priv) >= 12)
- high_pg = TGL_DISP_PW_3;
+ high_pg = ICL_DISP_PW_3;
else
high_pg = SKL_DISP_PW_2;
@@ -3571,7 +3571,7 @@ static const struct i915_power_well_desc
icl_power_wells[] = {
.name = "power well 3",
.domains = ICL_PW_3_POWER_DOMAINS,
.ops = _power_well_ops,
- .id = DISP_PW_ID_NONE,
+ .id = ICL_DISP_PW_3,
{
.hsw.regs = _power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_PW_3,
@@ -3949,7 +3949,7 @@ static const struct i915_power_well_desc
tgl_power_wells[] = {
.name = "power well 3",
.domains = TGL_PW_3_POWER_DOMAINS,
.ops = _power_well_ops,
- .id = TGL_DISP_PW_3,
+ .id = ICL_DISP_PW_3,
{
.hsw.regs = _power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_PW_3,
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
b/drivers/gpu/drm/i915/display/intel_display_power.h
index da64a5edae7a..56cbae6327b7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -100,7 +100,7 @@ enum i915_power_well_id {
SKL_DISP_PW_MISC_IO,
SKL_DISP_PW_1,
SKL_DISP_PW_2,
- TGL_DISP_PW_3,
+ ICL_DISP_PW_3,
SKL_DISP_DC_OFF,
};
--
2.26.0
___
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[Intel-gfx] [PATCH v5 0/4] i915 lpsp support for lpsp igt
v5 has fixed the review comment for [PATCH 2/4] provided by animesh and rebased the series. Test-with: 20200409053951.26929-2-anshuman.gu...@intel.com Anshuman Gupta (4): drm/i915: Power well id for ICL PG3 drm/i915: Add i915_lpsp_capability debugfs drm/i915: Add connector dbgfs for all connectors drm/i915: Add i915_lpsp_status debugfs attribute .../gpu/drm/i915/display/intel_connector.c| 3 + .../drm/i915/display/intel_display_debugfs.c | 100 ++ .../drm/i915/display/intel_display_power.c| 6 +- .../drm/i915/display/intel_display_power.h| 4 +- drivers/gpu/drm/i915/display/intel_dp.c | 3 - drivers/gpu/drm/i915/display/intel_hdmi.c | 3 - 6 files changed, 109 insertions(+), 10 deletions(-) -- 2.26.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5 3/4] drm/i915: Add connector dbgfs for all connectors
Add connector debugfs attributes for each intel connector which is getting register. v2: - adding connector debugfs for each connector in intel_connector_register() to fix CI failure for legacy connectors. Reviewed-by: Jani Nikula Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/display/intel_connector.c | 3 +++ drivers/gpu/drm/i915/display/intel_dp.c| 3 --- drivers/gpu/drm/i915/display/intel_hdmi.c | 3 --- 3 files changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_connector.c b/drivers/gpu/drm/i915/display/intel_connector.c index 98ec2ea86c7c..406e96785c76 100644 --- a/drivers/gpu/drm/i915/display/intel_connector.c +++ b/drivers/gpu/drm/i915/display/intel_connector.c @@ -33,6 +33,7 @@ #include "i915_drv.h" #include "intel_connector.h" +#include "intel_display_debugfs.h" #include "intel_display_types.h" #include "intel_hdcp.h" @@ -123,6 +124,8 @@ int intel_connector_register(struct drm_connector *connector) goto err_backlight; } + intel_connector_debugfs_add(connector); + return 0; err_backlight: diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index d4fcc9583869..48397b2c08cf 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -48,7 +48,6 @@ #include "intel_audio.h" #include "intel_connector.h" #include "intel_ddi.h" -#include "intel_display_debugfs.h" #include "intel_display_types.h" #include "intel_dp.h" #include "intel_dp_link_training.h" @@ -6451,8 +6450,6 @@ intel_dp_connector_register(struct drm_connector *connector) if (ret) return ret; - intel_connector_debugfs_add(connector); - drm_dbg_kms(>drm, "registering %s bus for %s\n", intel_dp->aux.name, connector->kdev->kobj.name); diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 011d83c2a1e3..0ca8bf62cb8e 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -44,7 +44,6 @@ #include "intel_audio.h" #include "intel_connector.h" #include "intel_ddi.h" -#include "intel_display_debugfs.h" #include "intel_display_types.h" #include "intel_dp.h" #include "intel_dpio_phy.h" @@ -2877,8 +2876,6 @@ intel_hdmi_connector_register(struct drm_connector *connector) if (ret) return ret; - intel_connector_debugfs_add(connector); - intel_hdmi_create_i2c_symlink(connector); return ret; -- 2.26.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5 4/4] drm/i915: Add i915_lpsp_status debugfs attribute
It requires a separate debugfs attribute to expose lpsp
status to user space, as there may be display less configuration
without any valid connected output, those configuration will not be
able to test lpsp status, if lpsp status exposed from a connector
based debugfs attribute.
Reviewed-by: Animesh Manna
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_debugfs.c | 47 +++
.../drm/i915/display/intel_display_power.h| 2 +
2 files changed, 49 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index ea48de3cac24..70525623bcdf 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -9,6 +9,7 @@
#include "i915_debugfs.h"
#include "intel_csr.h"
#include "intel_display_debugfs.h"
+#include "intel_display_power.h"
#include "intel_display_types.h"
#include "intel_dp.h"
#include "intel_fbc.h"
@@ -1143,6 +1144,51 @@ static int i915_drrs_status(struct seq_file *m, void
*unused)
return 0;
}
+#define LPSP_STATUS(COND) (COND ? seq_puts(m, "LPSP: enabled\n") : \
+ seq_puts(m, "LPSP: disabled\n"))
+
+static bool
+intel_lpsp_power_well_enabled(struct drm_i915_private *i915,
+ enum i915_power_well_id power_well_id)
+{
+ intel_wakeref_t wakeref;
+ bool is_enabled;
+
+ wakeref = intel_runtime_pm_get(>runtime_pm);
+ is_enabled = intel_display_power_well_is_enabled(i915,
+power_well_id);
+ intel_runtime_pm_put(>runtime_pm, wakeref);
+
+ return is_enabled;
+}
+
+static int i915_lpsp_status(struct seq_file *m, void *unused)
+{
+ struct drm_i915_private *i915 = node_to_i915(m->private);
+
+ switch (INTEL_GEN(i915)) {
+ case 12:
+ case 11:
+ LPSP_STATUS(!intel_lpsp_power_well_enabled(i915,
ICL_DISP_PW_3));
+ break;
+ case 10:
+ case 9:
+ LPSP_STATUS(!intel_lpsp_power_well_enabled(i915,
SKL_DISP_PW_2));
+ break;
+ default:
+ /*
+* Apart from HASWELL/BROADWELL other legacy platform doesn't
+* support lpsp.
+*/
+ if (IS_HASWELL(i915) || IS_BROADWELL(i915))
+ LPSP_STATUS(!intel_lpsp_power_well_enabled(i915,
HSW_DISP_PW_GLOBAL));
+ else
+ seq_puts(m, "LPSP: not supported\n");
+ }
+
+ return 0;
+}
+
static int i915_dp_mst_info(struct seq_file *m, void *unused)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -1910,6 +1956,7 @@ static const struct drm_info_list
intel_display_debugfs_list[] = {
{"i915_dp_mst_info", i915_dp_mst_info, 0},
{"i915_ddb_info", i915_ddb_info, 0},
{"i915_drrs_status", i915_drrs_status, 0},
+ {"i915_lpsp_status", i915_lpsp_status, 0},
};
static const struct {
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
b/drivers/gpu/drm/i915/display/intel_display_power.h
index 56cbae6327b7..14c5ad20287f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -266,6 +266,8 @@ intel_display_power_domain_str(enum
intel_display_power_domain domain);
bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain);
+bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
+enum i915_power_well_id power_well_id);
bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain);
intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv,
--
2.26.0
___
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[Intel-gfx] [CI 1/2] drm/i915/selftests: Exercise basic RPS interrupt generation
Since we depend upon RPS generating interrupts after evaluation
intervals to determine when to up/down clock the GPU, it is imperative
that we successfully enable interrupt generation! Verify that we do see
an interrupt if we keep the GPU busy for an entire EI.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_rps.c | 4 +
drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 2 +
drivers/gpu/drm/i915/gt/selftest_rps.c | 223 +++
drivers/gpu/drm/i915/gt/selftest_rps.h | 11 ++
4 files changed, 240 insertions(+)
create mode 100644 drivers/gpu/drm/i915/gt/selftest_rps.c
create mode 100644 drivers/gpu/drm/i915/gt/selftest_rps.h
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 86110458e2a7..d19161c7a3d8 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -1923,3 +1923,7 @@ bool i915_gpu_turbo_disable(void)
return ret;
}
EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
+
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftest_rps.c"
+#endif
diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
index 09ff8e4f88af..c50bb502fe03 100644
--- a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
@@ -7,6 +7,7 @@
#include "selftest_llc.h"
#include "selftest_rc6.h"
+#include "selftest_rps.h"
static int live_gt_resume(void *arg)
{
@@ -52,6 +53,7 @@ int intel_gt_pm_live_selftests(struct drm_i915_private *i915)
{
static const struct i915_subtest tests[] = {
SUBTEST(live_rc6_manual),
+ SUBTEST(live_rps_interrupt),
SUBTEST(live_gt_resume),
};
diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c
b/drivers/gpu/drm/i915/gt/selftest_rps.c
new file mode 100644
index ..26aadc2ae3be
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
@@ -0,0 +1,223 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#include "intel_engine_pm.h"
+#include "intel_gt_pm.h"
+#include "intel_rc6.h"
+#include "selftest_rps.h"
+#include "selftests/igt_flush_test.h"
+#include "selftests/igt_spinner.h"
+
+static void dummy_rps_work(struct work_struct *wrk)
+{
+}
+
+static int __rps_up_interrupt(struct intel_rps *rps,
+ struct intel_engine_cs *engine,
+ struct igt_spinner *spin)
+{
+ struct intel_uncore *uncore = engine->uncore;
+ struct i915_request *rq;
+ u32 timeout;
+
+ if (!intel_engine_can_store_dword(engine))
+ return 0;
+
+ intel_gt_pm_wait_for_idle(engine->gt);
+ GEM_BUG_ON(rps->active);
+
+ rps->pm_iir = 0;
+ rps->cur_freq = rps->min_freq;
+
+ rq = igt_spinner_create_request(spin, engine->kernel_context, MI_NOOP);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ i915_request_get(rq);
+ i915_request_add(rq);
+
+ if (!igt_wait_for_spinner(spin, rq)) {
+ pr_err("%s: RPS spinner did not start\n",
+ engine->name);
+ i915_request_put(rq);
+ intel_gt_set_wedged(engine->gt);
+ return -EIO;
+ }
+
+ if (!rps->active) {
+ pr_err("%s: RPS not enabled on starting spinner\n",
+ engine->name);
+ igt_spinner_end(spin);
+ i915_request_put(rq);
+ return -EINVAL;
+ }
+
+ if (!(rps->pm_events & GEN6_PM_RP_UP_THRESHOLD)) {
+ pr_err("%s: RPS did not register UP interrupt\n",
+ engine->name);
+ i915_request_put(rq);
+ return -EINVAL;
+ }
+
+ if (rps->last_freq != rps->min_freq) {
+ pr_err("%s: RPS did not program min frequency\n",
+ engine->name);
+ i915_request_put(rq);
+ return -EINVAL;
+ }
+
+ timeout = intel_uncore_read(uncore, GEN6_RP_UP_EI);
+ timeout = GT_PM_INTERVAL_TO_US(engine->i915, timeout);
+
+ usleep_range(2 * timeout, 3 * timeout);
+ GEM_BUG_ON(i915_request_completed(rq));
+
+ igt_spinner_end(spin);
+ i915_request_put(rq);
+
+ if (rps->cur_freq != rps->min_freq) {
+ pr_err("%s: Frequency unexpectedly changed [up], now %d!\n",
+ engine->name, intel_rps_read_actual_frequency(rps));
+ return -EINVAL;
+ }
+
+ if (!(rps->pm_iir & GEN6_PM_RP_UP_THRESHOLD)) {
+ pr_err("%s: UP interrupt not recorded for spinner, pm_iir:%x,
prev_up:%x, up_threshold:%x, up_ei:%x\n",
+ engine->name, rps->pm_iir,
+ intel_uncore_read(uncore, GEN6_RP_PREV_UP),
+ intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD),
+ intel_uncore_read(uncore, GEN6_RP_UP_EI));
+ return
[Intel-gfx] [CI 2/2] drm/i915/gt: Update PMINTRMSK holding fw
If we use a non-forcewaked write to PMINTRMSK, it does not take effect
until much later, if at all, causing a loss of RPS interrupts and no GPU
reclocking, leaving the GPU running at the wrong frequency for long
periods of time.
Reported-by: Francisco Jerez
Suggested-by: Francisco Jerez
Fixes: 35cc7f32c298 ("drm/i915/gt: Use non-forcewake writes for RPS")
Signed-off-by: Chris Wilson
Cc: Francisco Jerez
Cc: Mika Kuoppala
Cc: Andi Shyti
Reviewed-by: Mika Kuoppala
Reviewed-by: Andi Shyti
Cc: # v5.6+
---
drivers/gpu/drm/i915/gt/intel_rps.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index d19161c7a3d8..4dcfae16a7ce 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -81,13 +81,14 @@ static void rps_enable_interrupts(struct intel_rps *rps)
events = (GEN6_PM_RP_UP_THRESHOLD |
GEN6_PM_RP_DOWN_THRESHOLD |
GEN6_PM_RP_DOWN_TIMEOUT);
-
WRITE_ONCE(rps->pm_events, events);
+
spin_lock_irq(>irq_lock);
gen6_gt_pm_enable_irq(gt, rps->pm_events);
spin_unlock_irq(>irq_lock);
- set(gt->uncore, GEN6_PMINTRMSK, rps_pm_mask(rps, rps->cur_freq));
+ intel_uncore_write(gt->uncore,
+ GEN6_PMINTRMSK, rps_pm_mask(rps, rps->last_freq));
}
static void gen6_rps_reset_interrupts(struct intel_rps *rps)
@@ -120,7 +121,9 @@ static void rps_disable_interrupts(struct intel_rps *rps)
struct intel_gt *gt = rps_to_gt(rps);
WRITE_ONCE(rps->pm_events, 0);
- set(gt->uncore, GEN6_PMINTRMSK, rps_pm_sanitize_mask(rps, ~0u));
+
+ intel_uncore_write(gt->uncore,
+ GEN6_PMINTRMSK, rps_pm_sanitize_mask(rps, ~0u));
spin_lock_irq(>irq_lock);
gen6_gt_pm_disable_irq(gt, GEN6_PM_RPS_EVENTS);
--
2.20.1
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Re: [Intel-gfx] [PATCH 1/3] drm/i915/display: Load DP_TP_CTL/STATUS offset before use it
On Tue, 2020-04-14 at 22:33 -0700, Lucas De Marchi wrote:
> On Tue, Apr 14, 2020 at 4:03 PM José Roberto de Souza
> wrote:
> > Right now dp.regs.dp_tp_ctl/status are only set during the encoder
> > pre_enable() hook, what is causing all reads and writes to those
> > registers to go to offset 0x0 before pre_enable() is executed.
> >
> > So if i915 takes the BIOS state and don't do a modeset any
> > following
> > link retraing will fail.
> >
> > In the case that i915 needs to do a modeset, the DDI disable
> > sequence
> > will write to a wrong register not disabling DP 'Transport Enable'
> > in
> > DP_TP_CTL, making a HDMI modeset in the same port/transcoder to
> > not light up the monitor.
> >
> > So here for GENs older than 12, that have those registers fixed at
> > port offset range it is loading at encoder/port init while for
> > GEN12
> > it will keep setting it at encoder pre_enable() and during HW state
> > readout.
> >
> > Fixes: df6e205b ("drm/i915/tgl: move DP_TP_* to transcoder")
> > Cc: Matt Roper
> > Cc: Lucas De Marchi
> > Signed-off-by: José Roberto de Souza
> > ---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 14 +++---
> > drivers/gpu/drm/i915/display/intel_dp.c | 5 ++---
> > 2 files changed, 13 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index be6c61bcbc9c..1aab93a94f40 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -3252,9 +3252,6 @@ static void hsw_ddi_pre_enable_dp(struct
> > intel_atomic_state *state,
> > intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
> > crtc_state->lane_count, is_mst);
> >
> > - intel_dp->regs.dp_tp_ctl = DP_TP_CTL(port);
> > - intel_dp->regs.dp_tp_status = DP_TP_STATUS(port);
>
> reason to be where it was is because of MST. I think what you are
> doing here will break it since now this is set for the port and not
> transcoder.
> intel_mst_pre_enable_dp() would call here only for the first stream,
> so all the others would use this same transcoder.
For TGL+ it moved to transcoder but for other it is still on port and
it is kept in this patch. The fix here for TGL+ is load those 2 during
HW state readout.
Inside MST code it will continue to get from
intel_mst->primary.dp.
>
> Lucas De Marchi
>
> > -
> > intel_edp_panel_on(intel_dp);
> >
> > intel_ddi_clk_select(encoder, crtc_state);
> > @@ -4061,12 +4058,18 @@ void intel_ddi_get_config(struct
> > intel_encoder *encoder,
> > struct drm_i915_private *dev_priv = to_i915(encoder-
> > >base.dev);
> > struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config-
> > >uapi.crtc);
> > enum transcoder cpu_transcoder = pipe_config-
> > >cpu_transcoder;
> > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > u32 temp, flags = 0;
> >
> > /* XXX: DSI transcoder paranoia */
> > if (drm_WARN_ON(_priv->drm,
> > transcoder_is_dsi(cpu_transcoder)))
> > return;
> >
> > + if (INTEL_GEN(dev_priv) >= 12) {
> > + intel_dp->regs.dp_tp_ctl =
> > TGL_DP_TP_CTL(cpu_transcoder);
> > + intel_dp->regs.dp_tp_status =
> > TGL_DP_TP_STATUS(cpu_transcoder);
> > + }
> > +
> > intel_dsc_get_config(encoder, pipe_config);
> >
> > temp = intel_de_read(dev_priv,
> > TRANS_DDI_FUNC_CTL(cpu_transcoder));
> > @@ -4396,6 +4399,7 @@ static const struct drm_encoder_funcs
> > intel_ddi_funcs = {
> > static struct intel_connector *
> > intel_ddi_init_dp_connector(struct intel_digital_port
> > *intel_dig_port)
> > {
> > + struct drm_i915_private *dev_priv = to_i915(intel_dig_port-
> > >base.base.dev);
> > struct intel_connector *connector;
> > enum port port = intel_dig_port->base.port;
> >
> > @@ -4406,6 +4410,10 @@ intel_ddi_init_dp_connector(struct
> > intel_digital_port *intel_dig_port)
> > intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
> > intel_dig_port->dp.prepare_link_retrain =
> > intel_ddi_prepare_link_retrain;
> > + if (INTEL_GEN(dev_priv) < 12) {
> > + intel_dig_port->dp.regs.dp_tp_ctl =
> > DP_TP_CTL(port);
> > + intel_dig_port->dp.regs.dp_tp_status =
> > DP_TP_STATUS(port);
> > + }
> >
> > if (!intel_dp_init_connector(intel_dig_port, connector)) {
> > kfree(connector);
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index d4fcc9583869..03591ab76b0d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -2671,9 +2671,6 @@ static void intel_dp_prepare(struct
> > intel_encoder *encoder,
> > intel_crtc_has_type(pipe_config,
> >
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with drm/i915/selftests: Exercise basic RPS interrupt generation (rev3)
== Series Details ==
Series: series starting with drm/i915/selftests: Exercise basic RPS interrupt
generation (rev3)
URL : https://patchwork.freedesktop.org/series/75973/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8301 -> Patchwork_17313
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_17313 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_17313, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17313/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_17313:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live@gt_pm:
- fi-tgl-y: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/fi-tgl-y/igt@i915_selftest@live@gt_pm.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17313/fi-tgl-y/igt@i915_selftest@live@gt_pm.html
- fi-snb-2520m: [PASS][3] -> [DMESG-FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/fi-snb-2520m/igt@i915_selftest@live@gt_pm.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17313/fi-snb-2520m/igt@i915_selftest@live@gt_pm.html
- fi-snb-2600:[PASS][5] -> [DMESG-FAIL][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/fi-snb-2600/igt@i915_selftest@live@gt_pm.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17313/fi-snb-2600/igt@i915_selftest@live@gt_pm.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@gt_pm:
- {fi-tgl-dsi}: [PASS][7] -> [DMESG-FAIL][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/fi-tgl-dsi/igt@i915_selftest@live@gt_pm.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17313/fi-tgl-dsi/igt@i915_selftest@live@gt_pm.html
- {fi-tgl-u}: [PASS][9] -> [DMESG-FAIL][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/fi-tgl-u/igt@i915_selftest@live@gt_pm.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17313/fi-tgl-u/igt@i915_selftest@live@gt_pm.html
Known issues
Here are the changes found in Patchwork_17313 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_pm_rpm@module-reload:
- fi-icl-dsi: [PASS][11] -> [INCOMPLETE][12] ([i915#189])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/fi-icl-dsi/igt@i915_pm_...@module-reload.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17313/fi-icl-dsi/igt@i915_pm_...@module-reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#189]: https://gitlab.freedesktop.org/drm/intel/issues/189
Participating hosts (50 -> 46)
--
Additional (2): fi-skl-6770hq fi-cfl-8700k
Missing(6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_8301 -> Patchwork_17313
CI-20190529: 20190529
CI_DRM_8301: 7d2bdd2df0d18945bb274de8bc7560e14779e346 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5590: c7b4a43942be32245b1c00b5b4a38401d8ca6e0d @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17313: 8c90502c194a05a684e39b7fdc7cb87207b4fad4 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
8c90502c194a drm/i915/gt: Update PMINTRMSK holding fw
0454a6c7dd1e drm/i915/selftests: Exercise basic RPS interrupt generation
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17313/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with drm/i915/selftests: Exercise basic RPS interrupt generation (rev3)
== Series Details == Series: series starting with drm/i915/selftests: Exercise basic RPS interrupt generation (rev3) URL : https://patchwork.freedesktop.org/series/75973/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 /home/cidrm/kernel/Documentation/gpu/i915.rst:610: WARNING: duplicate label gpu/i915:layout, other instance in /home/cidrm/kernel/Documentation/gpu/i915.rst ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with drm/i915/selftests: Exercise basic RPS interrupt generation (rev3)
== Series Details == Series: series starting with drm/i915/selftests: Exercise basic RPS interrupt generation (rev3) URL : https://patchwork.freedesktop.org/series/75973/ State : warning == Summary == $ dim checkpatch origin/drm-tip 0454a6c7dd1e drm/i915/selftests: Exercise basic RPS interrupt generation -:46: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #46: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 252 lines checked 8c90502c194a drm/i915/gt: Update PMINTRMSK holding fw -:39: ERROR:CODE_INDENT: code indent should use tabs where possible #39: FILE: drivers/gpu/drm/i915/gt/intel_rps.c:91: + GEN6_PMINTRMSK, rps_pm_mask(rps, rps->last_freq));$ -:39: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #39: FILE: drivers/gpu/drm/i915/gt/intel_rps.c:91: + intel_uncore_write(gt->uncore, + GEN6_PMINTRMSK, rps_pm_mask(rps, rps->last_freq)); -:39: WARNING:LEADING_SPACE: please, no spaces at the start of a line #39: FILE: drivers/gpu/drm/i915/gt/intel_rps.c:91: + GEN6_PMINTRMSK, rps_pm_mask(rps, rps->last_freq));$ -:50: ERROR:CODE_INDENT: code indent should use tabs where possible #50: FILE: drivers/gpu/drm/i915/gt/intel_rps.c:126: + GEN6_PMINTRMSK, rps_pm_sanitize_mask(rps, ~0u));$ -:50: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #50: FILE: drivers/gpu/drm/i915/gt/intel_rps.c:126: + intel_uncore_write(gt->uncore, + GEN6_PMINTRMSK, rps_pm_sanitize_mask(rps, ~0u)); -:50: WARNING:LEADING_SPACE: please, no spaces at the start of a line #50: FILE: drivers/gpu/drm/i915/gt/intel_rps.c:126: + GEN6_PMINTRMSK, rps_pm_sanitize_mask(rps, ~0u));$ total: 2 errors, 2 warnings, 2 checks, 26 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for SAGV support for Gen12+ (rev21)
== Series Details == Series: SAGV support for Gen12+ (rev21) URL : https://patchwork.freedesktop.org/series/75129/ State : success == Summary == CI Bug Log - changes from CI_DRM_8301 -> Patchwork_17312 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17312/index.html Known issues Here are the changes found in Patchwork_17312 that come from known issues: ### IGT changes ### Issues hit * igt@kms_chamelium@dp-crc-fast: - fi-cml-u2: [PASS][1] -> [FAIL][2] ([i915#262]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17312/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html * igt@kms_chamelium@dp-edid-read: - fi-kbl-7500u: [PASS][3] -> [FAIL][4] ([i915#976]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17312/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262 [i915#976]: https://gitlab.freedesktop.org/drm/intel/issues/976 Participating hosts (50 -> 46) -- Additional (2): fi-skl-6770hq fi-cfl-8700k Missing(6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8301 -> Patchwork_17312 CI-20190529: 20190529 CI_DRM_8301: 7d2bdd2df0d18945bb274de8bc7560e14779e346 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5590: c7b4a43942be32245b1c00b5b4a38401d8ca6e0d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17312: 3c3c3aee4a13b8d753382a38abac2e0e584a289c @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 3c3c3aee4a13 drm/i915: Enable SAGV support for Gen12 1d0b2628bf63 drm/i915: Restrict qgv points which don't have enough bandwidth. 2bcb0ac00e91 drm/i915: Rename bw_state to new_bw_state 87e08994a2d3 drm/i915: Added required new PCode commands 58e617a267af drm/i915: Add TGL+ SAGV support 72a0e43e6287 drm/i915: Separate icl and skl SAGV checking 817a1d87036f drm/i915: Use bw state for per crtc SAGV evaluation 98e73fa91e4b drm/i915: Add pre/post plane updates for SAGV 908804d8526f drm/i915: Prepare to extract gen specific functions from intel_can_enable_sagv 6e5b0cfb1a19 drm/i915: Add intel_atomic_get_bw_*_state helpers 6626e1b28f68 drm/i915: Introduce skl_plane_wm_level accessor. == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17312/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v5,1/8] drm/i915/display: Move out code to return the digital_port of the aux ch
== Series Details == Series: series starting with [v5,1/8] drm/i915/display: Move out code to return the digital_port of the aux ch URL : https://patchwork.freedesktop.org/series/75941/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8298_full -> Patchwork_17300_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_17300_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17300_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_17300_full: ### IGT changes ### Possible regressions * igt@i915_module_load@reload-with-fault-injection: - shard-tglb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-tglb5/igt@i915_module_l...@reload-with-fault-injection.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17300/shard-tglb7/igt@i915_module_l...@reload-with-fault-injection.html New tests - New tests have been introduced between CI_DRM_8298_full and Patchwork_17300_full: ### New IGT tests (27) ### * igt@kms_plane_cursor@pipe-a-overlay-size-128: - Statuses : 7 pass(s) - Exec time: [1.66, 3.68] s * igt@kms_plane_cursor@pipe-a-overlay-size-256: - Statuses : 8 pass(s) - Exec time: [1.65, 3.65] s * igt@kms_plane_cursor@pipe-a-overlay-size-64: - Statuses : 8 pass(s) - Exec time: [1.65, 3.66] s * igt@kms_plane_cursor@pipe-a-primary-size-128: - Statuses : 8 pass(s) - Exec time: [1.63, 3.46] s * igt@kms_plane_cursor@pipe-a-primary-size-256: - Statuses : 8 pass(s) - Exec time: [1.63, 3.44] s * igt@kms_plane_cursor@pipe-a-primary-size-64: - Statuses : 8 pass(s) - Exec time: [1.63, 3.55] s * igt@kms_plane_cursor@pipe-a-viewport-size-128: - Statuses : 8 pass(s) - Exec time: [1.65, 3.67] s * igt@kms_plane_cursor@pipe-a-viewport-size-256: - Statuses : 8 pass(s) - Exec time: [1.65, 3.68] s * igt@kms_plane_cursor@pipe-a-viewport-size-64: - Statuses : 8 pass(s) - Exec time: [1.64, 3.67] s * igt@kms_plane_cursor@pipe-b-overlay-size-128: - Statuses : 8 pass(s) - Exec time: [2.22, 4.88] s * igt@kms_plane_cursor@pipe-b-overlay-size-256: - Statuses : 8 pass(s) - Exec time: [2.22, 4.88] s * igt@kms_plane_cursor@pipe-b-overlay-size-64: - Statuses : 8 pass(s) - Exec time: [2.23, 4.83] s * igt@kms_plane_cursor@pipe-b-primary-size-128: - Statuses : 8 pass(s) - Exec time: [2.22, 4.68] s * igt@kms_plane_cursor@pipe-b-primary-size-256: - Statuses : 8 pass(s) - Exec time: [2.19, 4.67] s * igt@kms_plane_cursor@pipe-b-primary-size-64: - Statuses : 8 pass(s) - Exec time: [2.21, 4.60] s * igt@kms_plane_cursor@pipe-b-viewport-size-128: - Statuses : - Exec time: [None] s * igt@kms_plane_cursor@pipe-b-viewport-size-256: - Statuses : 8 pass(s) - Exec time: [2.23, 4.87] s * igt@kms_plane_cursor@pipe-b-viewport-size-64: - Statuses : 8 pass(s) - Exec time: [2.27, 4.85] s * igt@kms_plane_cursor@pipe-c-overlay-size-128: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.86] s * igt@kms_plane_cursor@pipe-c-overlay-size-256: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.94] s * igt@kms_plane_cursor@pipe-c-overlay-size-64: - Statuses : 6 pass(s) 1 skip(s) - Exec time: [0.0, 3.60] s * igt@kms_plane_cursor@pipe-c-primary-size-128: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.61] s * igt@kms_plane_cursor@pipe-c-primary-size-256: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.70] s * igt@kms_plane_cursor@pipe-c-primary-size-64: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.66] s * igt@kms_plane_cursor@pipe-c-viewport-size-128: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.87] s * igt@kms_plane_cursor@pipe-c-viewport-size-256: - Statuses : 6 pass(s) 1 skip(s) - Exec time: [0.0, 4.82] s * igt@kms_plane_cursor@pipe-c-viewport-size-64: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.96] s Known issues Here are the changes found in Patchwork_17300_full that come from known issues: ### IGT changes ### Issues hit * igt@kms_atomic_transition@1x-modeset-transitions: - shard-snb: [PASS][3] -> [SKIP][4] ([fdo#109271]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-snb2/igt@kms_atomic_transit...@1x-modeset-transitions.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17300/shard-snb6/igt@kms_atomic_transit...@1x-modeset-transitions.html *
[Intel-gfx] ✗ Fi.CI.DOCS: warning for SAGV support for Gen12+ (rev21)
== Series Details == Series: SAGV support for Gen12+ (rev21) URL : https://patchwork.freedesktop.org/series/75129/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 /home/cidrm/kernel/Documentation/gpu/i915.rst:610: WARNING: duplicate label gpu/i915:layout, other instance in /home/cidrm/kernel/Documentation/gpu/i915.rst ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/icl: Update forcewake firmware ranges
> -Original Message-
> From: Roper, Matthew D
> Sent: Wednesday, April 15, 2020 7:52 AM
> To: Sripada, Radhakrishna
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/i915/icl: Update forcewake firmware ranges
>
> On Wed, Apr 15, 2020 at 07:28:18AM -0700, Sripada, Radhakrishna wrote:
> > Hi Matt,
> >
> > > -Original Message-
> > > From: Roper, Matthew D
> > > Sent: Tuesday, April 14, 2020 11:40 AM
> > > To: Sripada, Radhakrishna
> > > Cc: intel-gfx@lists.freedesktop.org
> > > Subject: Re: [PATCH] drm/i915/icl: Update forcewake firmware ranges
> > >
> > > On Mon, Apr 13, 2020 at 02:00:03AM -0700, Radhakrishna Sripada wrote:
> > > > Some workarounds are not sticking across suspend resume cycles.
> > > > The forcewake ranges table has been updated and would reflect the
> > > > hardware appropriately.
> > > >
> > > > Closes: https://gitlab.freedesktop.org/drm/intel/issues/1222
> > >
> > > It's unfortunate that they still haven't updated the bspec for this yet.
> > > A few comments below based on my understanding of the document we
> > > received from the hardware team.
> > >
> > > >
> > > > Cc: Matt Roper
> > > > Signed-off-by: Radhakrishna Sripada
> > > >
> > > > ---
> > > > drivers/gpu/drm/i915/intel_uncore.c | 55
> > > > +
> > > > 1 file changed, 41 insertions(+), 14 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c
> > > > b/drivers/gpu/drm/i915/intel_uncore.c
> > > > index fa86b7ab2d99..c0e21697a44c 100644
> > > > --- a/drivers/gpu/drm/i915/intel_uncore.c
> > > > +++ b/drivers/gpu/drm/i915/intel_uncore.c
> > > > @@ -1098,32 +1098,59 @@ static const struct intel_forcewake_range
> > > > __gen11_fw_ranges[] = {
> > >
> > > Looks like the first range in this table (0x0 - 0xaff) needs to be
> > > changed to '0' (or rather combined with the following entry for a
> > > combined 0x0 - 0x1fff range set to '0')
> >
> > Comparing with previous gens, my understanding is the '0' is
> > indicative of uncore range Of registers. The reserved ranges are
> > marked with "Blitter" force wake range. Am I in the right Path making that
> assumption? Hence made all the subsequent changes according to the
> assumption.
>
> The final parameter of GEN_FW_RANGE() is a bitmask of domains that we need
> to make sure are powered up when we're going to access a register in that
> range. So a 0 means no domains need to be powered up for registers in that
> range. That might be because it's a range that contains no registers at all
> (reserved range), or it may be that the registers in that range simply aren't
> part
> of the blitter, render, media, etc. power wells and we don't have to worry
> about
> powering anything up.
>
> In cases where there are no actual registers (i.e., reserved ranges), it
> doesn't
> really matter what you put since there shouldn't be any register reads/writes
> in
> that range. So for those we'll often combine them with one of the surrounding
> ranges just to keep the overall forcewake table smaller and make lookups
> faster.
>
Thank you for the explanation Matt. I will update the patch and send the next
version.
- RK
>
> Matt
>
> >
> > Thanks,
> > Radhakrishna(RK) Sripada
> > >
> > >
> > > > GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
> > > > GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
> > > > GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
> > > > - GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
> > > > + GEN_FW_RANGE(0x5200, 0x53ff, FORCEWAKE_RENDER),
> > > > + GEN_FW_RANGE(0x5400, 0x54ff, FORCEWAKE_BLITTER),
> > >
> > > In the version of the document I'm looking at, the wake target for
> > > this entry is blank, which usually means no wake target is required.
> > > AFAICS, no registers actually fall in this range on gen11, so I'd
> > > either set this to '0' to explicitly match the document, or just
> > > leave it combined with the two surrounding render ranges for simplicity
> > > (and
> smaller table size).
> > >
> > > > + GEN_FW_RANGE(0x5500, 0x7fff, FORCEWAKE_RENDER),
> > > > GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_BLITTER),
> > > > GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
> > > > GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
> > > > GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
> > > > - GEN_FW_RANGE(0x8500, 0x8bff, FORCEWAKE_BLITTER),
> > > > + GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_BLITTER),
> > > > + GEN_FW_RANGE(0x8800, 0x883f, 0),
> > > > + GEN_FW_RANGE(0x8840, 0x8bff, FORCEWAKE_BLITTER),
> > >
> > > I see 0x8840 - 0x8bff as a reserved range with no forcewake target
> > > so we should be able to combine it with the range before it.
> > >
> > > > GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
> > > > - GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
> > > > - GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_ALL),
> > > > -
[Intel-gfx] [PATCH] drm/i915/selftests: Exercise basic RPS interrupt generation
Since we depend upon RPS generating interrupts after evaluation
intervals to determine when to up/down clock the GPU, it is imperative
that we successfully enable interrupt generation! Verify that we do see
an interrupt if we keep the GPU busy for an entire EI.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_rps.c | 4 +
drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 2 +
drivers/gpu/drm/i915/gt/selftest_rps.c | 220 +++
drivers/gpu/drm/i915/gt/selftest_rps.h | 11 ++
4 files changed, 237 insertions(+)
create mode 100644 drivers/gpu/drm/i915/gt/selftest_rps.c
create mode 100644 drivers/gpu/drm/i915/gt/selftest_rps.h
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 86110458e2a7..d19161c7a3d8 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -1923,3 +1923,7 @@ bool i915_gpu_turbo_disable(void)
return ret;
}
EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
+
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftest_rps.c"
+#endif
diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
index 09ff8e4f88af..c50bb502fe03 100644
--- a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
@@ -7,6 +7,7 @@
#include "selftest_llc.h"
#include "selftest_rc6.h"
+#include "selftest_rps.h"
static int live_gt_resume(void *arg)
{
@@ -52,6 +53,7 @@ int intel_gt_pm_live_selftests(struct drm_i915_private *i915)
{
static const struct i915_subtest tests[] = {
SUBTEST(live_rc6_manual),
+ SUBTEST(live_rps_interrupt),
SUBTEST(live_gt_resume),
};
diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c
b/drivers/gpu/drm/i915/gt/selftest_rps.c
new file mode 100644
index ..26a83c4e30ce
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
@@ -0,0 +1,220 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#include "intel_engine_pm.h"
+#include "intel_gt_pm.h"
+#include "intel_rc6.h"
+#include "selftest_rps.h"
+#include "selftests/igt_flush_test.h"
+#include "selftests/igt_spinner.h"
+
+static void dummy_rps_work(struct work_struct *wrk)
+{
+}
+
+static int __rps_up_interrupt(struct intel_rps *rps,
+ struct intel_engine_cs *engine,
+ struct igt_spinner *spin)
+{
+ struct intel_uncore *uncore = engine->uncore;
+ struct i915_request *rq;
+ u32 timeout;
+
+ intel_gt_pm_wait_for_idle(engine->gt);
+ GEM_BUG_ON(rps->active);
+
+ rps->pm_iir = 0;
+ rps->cur_freq = rps->min_freq;
+
+ rq = igt_spinner_create_request(spin, engine->kernel_context, MI_NOOP);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ i915_request_get(rq);
+ i915_request_add(rq);
+
+ if (!igt_wait_for_spinner(spin, rq)) {
+ pr_err("%s: RPS spinner did not start\n",
+ engine->name);
+ i915_request_put(rq);
+ intel_gt_set_wedged(engine->gt);
+ return -EIO;
+ }
+
+ if (!rps->active) {
+ pr_err("%s: RPS not enabled on starting spinner\n",
+ engine->name);
+ igt_spinner_end(spin);
+ i915_request_put(rq);
+ return -EINVAL;
+ }
+
+ if (!(rps->pm_events & GEN6_PM_RP_UP_THRESHOLD)) {
+ pr_err("%s: RPS did not register UP interrupt\n",
+ engine->name);
+ i915_request_put(rq);
+ return -EINVAL;
+ }
+
+ if (rps->last_freq != rps->min_freq) {
+ pr_err("%s: RPS did not program min frequency\n",
+ engine->name);
+ i915_request_put(rq);
+ return -EINVAL;
+ }
+
+ timeout = intel_uncore_read(uncore, GEN6_RP_UP_EI);
+ timeout = GT_PM_INTERVAL_TO_US(engine->i915, timeout);
+
+ usleep_range(2 * timeout, 3 * timeout);
+ GEM_BUG_ON(i915_request_completed(rq));
+
+ igt_spinner_end(spin);
+ i915_request_put(rq);
+
+ if (rps->cur_freq != rps->min_freq) {
+ pr_err("%s: Frequency unexpectedly changed [up], now %d!\n",
+ engine->name, intel_rps_read_actual_frequency(rps));
+ return -EINVAL;
+ }
+
+ if (!(rps->pm_iir & GEN6_PM_RP_UP_THRESHOLD)) {
+ pr_err("%s: UP interrupt not recorded for spinner, pm_iir:%x,
prev_up:%x, up_threshold:%x, up_ei:%x\n",
+ engine->name, rps->pm_iir,
+ intel_uncore_read(uncore, GEN6_RP_PREV_UP),
+ intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD),
+ intel_uncore_read(uncore, GEN6_RP_UP_EI));
+ return -EINVAL;
+ }
+
+ intel_gt_pm_wait_for_idle(engine->gt);
+
[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with drm/i915/selftests: Exercise basic RPS interrupt generation (rev2)
== Series Details == Series: series starting with drm/i915/selftests: Exercise basic RPS interrupt generation (rev2) URL : https://patchwork.freedesktop.org/series/75973/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h CC [M] drivers/gpu/drm/i915/gt/intel_rps.o In file included from ./arch/x86/include/asm/mmu.h:7:0, from ./include/linux/mm_types.h:18, from ./include/linux/mmzone.h:21, from ./include/linux/gfp.h:6, from ./include/linux/slab.h:15, from ./include/linux/io-mapping.h:10, from ./drivers/gpu/drm/i915/i915_drv.h:36, from drivers/gpu/drm/i915/gt/intel_rps.c:9: drivers/gpu/drm/i915/gt/selftest_rps.c: In function ‘__rps_down_interrupt’: drivers/gpu/drm/i915/gt/selftest_rps.c:102:17: error: ‘struct intel_rps’ has no member named ‘mutex’ mutex_lock(>mutex); ^ ./include/linux/mutex.h:156:44: note: in definition of macro ‘mutex_lock’ #define mutex_lock(lock) mutex_lock_nested(lock, 0) ^~~~ In file included from drivers/gpu/drm/i915/gt/intel_rps.c:1931:0: drivers/gpu/drm/i915/gt/selftest_rps.c:105:19: error: ‘struct intel_rps’ has no member named ‘mutex’ mutex_unlock(>mutex); ^~ scripts/Makefile.build:266: recipe for target 'drivers/gpu/drm/i915/gt/intel_rps.o' failed make[4]: *** [drivers/gpu/drm/i915/gt/intel_rps.o] Error 1 scripts/Makefile.build:488: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:488: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:488: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1722: recipe for target 'drivers' failed make: *** [drivers] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Move the batch buffer pool from the engine to the gt
== Series Details == Series: drm/i915/gt: Move the batch buffer pool from the engine to the gt URL : https://patchwork.freedesktop.org/series/75979/ State : success == Summary == CI Bug Log - changes from CI_DRM_8301 -> Patchwork_17310 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17310/index.html Known issues Here are the changes found in Patchwork_17310 that come from known issues: ### IGT changes ### Warnings * igt@i915_pm_rpm@module-reload: - fi-kbl-x1275: [SKIP][1] ([fdo#109271]) -> [FAIL][2] ([i915#62]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/fi-kbl-x1275/igt@i915_pm_...@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17310/fi-kbl-x1275/igt@i915_pm_...@module-reload.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 Participating hosts (50 -> 46) -- Additional (2): fi-skl-6770hq fi-cfl-8700k Missing(6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8301 -> Patchwork_17310 CI-20190529: 20190529 CI_DRM_8301: 7d2bdd2df0d18945bb274de8bc7560e14779e346 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5590: c7b4a43942be32245b1c00b5b4a38401d8ca6e0d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17310: 4498659d60153dd53b6ead50a87f5b5221d2a670 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 4498659d6015 drm/i915/gt: Move the batch buffer pool from the engine to the gt == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17310/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/gt: Move the batch buffer pool from the engine to the gt
== Series Details == Series: drm/i915/gt: Move the batch buffer pool from the engine to the gt URL : https://patchwork.freedesktop.org/series/75979/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 /home/cidrm/kernel/Documentation/gpu/i915.rst:610: WARNING: duplicate label gpu/i915:layout, other instance in /home/cidrm/kernel/Documentation/gpu/i915.rst ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/gt: Try to smooth RPS spikes
== Series Details == Series: series starting with [1/2] drm/i915/gt: Try to smooth RPS spikes URL : https://patchwork.freedesktop.org/series/75927/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8298_full -> Patchwork_17298_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_17298_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17298_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_17298_full: ### IGT changes ### Possible regressions * igt@i915_pm_rps@min-max-config-loaded: - shard-snb: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-snb4/igt@i915_pm_...@min-max-config-loaded.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17298/shard-snb2/igt@i915_pm_...@min-max-config-loaded.html - shard-hsw: [PASS][3] -> [FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-hsw6/igt@i915_pm_...@min-max-config-loaded.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17298/shard-hsw4/igt@i915_pm_...@min-max-config-loaded.html New tests - New tests have been introduced between CI_DRM_8298_full and Patchwork_17298_full: ### New IGT tests (27) ### * igt@kms_plane_cursor@pipe-a-overlay-size-128: - Statuses : 7 pass(s) - Exec time: [1.67, 3.71] s * igt@kms_plane_cursor@pipe-a-overlay-size-256: - Statuses : 8 pass(s) - Exec time: [1.64, 3.65] s * igt@kms_plane_cursor@pipe-a-overlay-size-64: - Statuses : 7 pass(s) - Exec time: [1.65, 3.68] s * igt@kms_plane_cursor@pipe-a-primary-size-128: - Statuses : 8 pass(s) - Exec time: [1.66, 3.46] s * igt@kms_plane_cursor@pipe-a-primary-size-256: - Statuses : 8 pass(s) - Exec time: [1.64, 3.45] s * igt@kms_plane_cursor@pipe-a-primary-size-64: - Statuses : 8 pass(s) - Exec time: [1.63, 3.41] s * igt@kms_plane_cursor@pipe-a-viewport-size-128: - Statuses : 8 pass(s) - Exec time: [1.65, 3.64] s * igt@kms_plane_cursor@pipe-a-viewport-size-256: - Statuses : 8 pass(s) - Exec time: [1.64, 3.67] s * igt@kms_plane_cursor@pipe-a-viewport-size-64: - Statuses : 8 pass(s) - Exec time: [1.64, 3.69] s * igt@kms_plane_cursor@pipe-b-overlay-size-128: - Statuses : 8 pass(s) - Exec time: [2.22, 4.77] s * igt@kms_plane_cursor@pipe-b-overlay-size-256: - Statuses : 8 pass(s) - Exec time: [2.22, 4.81] s * igt@kms_plane_cursor@pipe-b-overlay-size-64: - Statuses : 8 pass(s) - Exec time: [2.21, 4.84] s * igt@kms_plane_cursor@pipe-b-primary-size-128: - Statuses : 8 pass(s) - Exec time: [2.20, 4.68] s * igt@kms_plane_cursor@pipe-b-primary-size-256: - Statuses : 8 pass(s) - Exec time: [2.21, 4.54] s * igt@kms_plane_cursor@pipe-b-primary-size-64: - Statuses : 8 pass(s) - Exec time: [2.20, 4.67] s * igt@kms_plane_cursor@pipe-b-viewport-size-128: - Statuses : - Exec time: [None] s * igt@kms_plane_cursor@pipe-b-viewport-size-256: - Statuses : 8 pass(s) - Exec time: [2.21, 4.86] s * igt@kms_plane_cursor@pipe-b-viewport-size-64: - Statuses : 8 pass(s) - Exec time: [2.27, 4.85] s * igt@kms_plane_cursor@pipe-c-overlay-size-128: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.86] s * igt@kms_plane_cursor@pipe-c-overlay-size-256: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.88] s * igt@kms_plane_cursor@pipe-c-overlay-size-64: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.84] s * igt@kms_plane_cursor@pipe-c-primary-size-128: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.67] s * igt@kms_plane_cursor@pipe-c-primary-size-256: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.58] s * igt@kms_plane_cursor@pipe-c-primary-size-64: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.71] s * igt@kms_plane_cursor@pipe-c-viewport-size-128: - Statuses : 6 pass(s) 1 skip(s) - Exec time: [0.0, 5.06] s * igt@kms_plane_cursor@pipe-c-viewport-size-256: - Statuses : 6 pass(s) 1 skip(s) - Exec time: [0.0, 4.89] s * igt@kms_plane_cursor@pipe-c-viewport-size-64: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.91] s Known issues Here are the changes found in Patchwork_17298_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_softpin@noreloc-s3: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) +1 similar issue [5]:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Move the batch buffer pool from the engine to the gt
== Series Details == Series: drm/i915/gt: Move the batch buffer pool from the engine to the gt URL : https://patchwork.freedesktop.org/series/75979/ State : warning == Summary == $ dim checkpatch origin/drm-tip 4498659d6015 drm/i915/gt: Move the batch buffer pool from the engine to the gt -:14: WARNING:TYPO_SPELLING: 'hierachy' may be misspelled - perhaps 'hierarchy'? #14: retirement order easier to track), we can move it up the hierachy to the -:289: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #289: deleted file mode 100644 -:596: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #596: FILE: drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.h:1: +/* -:597: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead #597: FILE: drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.h:2: + * SPDX-License-Identifier: MIT total: 0 errors, 4 warnings, 0 checks, 559 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BUILD: failure for i915 lpsp support for lpsp igt (rev8)
== Series Details == Series: i915 lpsp support for lpsp igt (rev8) URL : https://patchwork.freedesktop.org/series/74648/ State : failure == Summary == Applying: drm/i915: Power well id for ICL PG3 Applying: drm/i915: Add i915_lpsp_capability debugfs Applying: drm/i915: Add connector dbgfs for all connectors Applying: drm/i915: Add i915_lpsp_status debugfs attribute Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/display/intel_display_debugfs.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/display/intel_display_debugfs.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/display/intel_display_debugfs.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0004 drm/i915: Add i915_lpsp_status debugfs attribute When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 22/59] drm/gm12u320: Don't use drm_device->dev_private
Hi,
On 4/15/20 9:39 AM, Daniel Vetter wrote:
Upcasting using a container_of macro is more typesafe, faster and
easier for the compiler to optimize.
Acked-by: Sam Ravnborg
Signed-off-by: Daniel Vetter
Cc: Hans de Goede
LGTM:
Reviewed-by: Hans de Goede
Regards,
Hans
---
drivers/gpu/drm/tiny/gm12u320.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/tiny/gm12u320.c b/drivers/gpu/drm/tiny/gm12u320.c
index 907739a67bf6..cc397671f689 100644
--- a/drivers/gpu/drm/tiny/gm12u320.c
+++ b/drivers/gpu/drm/tiny/gm12u320.c
@@ -98,6 +98,8 @@ struct gm12u320_device {
} fb_update;
};
+#define to_gm12u320(__dev) container_of(__dev, struct gm12u320_device, dev)
+
static const char cmd_data[CMD_SIZE] = {
0x55, 0x53, 0x42, 0x43, 0x00, 0x00, 0x00, 0x00,
0x68, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x10, 0xff,
@@ -408,7 +410,7 @@ static void gm12u320_fb_update_work(struct work_struct
*work)
static void gm12u320_fb_mark_dirty(struct drm_framebuffer *fb,
struct drm_rect *dirty)
{
- struct gm12u320_device *gm12u320 = fb->dev->dev_private;
+ struct gm12u320_device *gm12u320 = to_gm12u320(fb->dev);
struct drm_framebuffer *old_fb = NULL;
bool wakeup = false;
@@ -558,7 +560,7 @@ static void gm12u320_pipe_enable(struct drm_simple_display_pipe *pipe,
struct drm_plane_state *plane_state)
{
struct drm_rect rect = { 0, 0, GM12U320_USER_WIDTH, GM12U320_HEIGHT };
- struct gm12u320_device *gm12u320 = pipe->crtc.dev->dev_private;
+ struct gm12u320_device *gm12u320 = to_gm12u320(pipe->crtc.dev);
gm12u320->fb_update.draw_status_timeout = FIRST_FRAME_TIMEOUT;
gm12u320_fb_mark_dirty(plane_state->fb, );
@@ -566,7 +568,7 @@ static void gm12u320_pipe_enable(struct
drm_simple_display_pipe *pipe,
static void gm12u320_pipe_disable(struct drm_simple_display_pipe *pipe)
{
- struct gm12u320_device *gm12u320 = pipe->crtc.dev->dev_private;
+ struct gm12u320_device *gm12u320 = to_gm12u320(pipe->crtc.dev);
gm12u320_stop_fb_update(gm12u320);
}
@@ -641,7 +643,6 @@ static int gm12u320_usb_probe(struct usb_interface
*interface,
mutex_init(>fb_update.lock);
dev = >dev;
- dev->dev_private = gm12u320;
ret = drmm_mode_config_init(dev);
if (ret)
@@ -706,7 +707,7 @@ static __maybe_unused int gm12u320_suspend(struct
usb_interface *interface,
static __maybe_unused int gm12u320_resume(struct usb_interface *interface)
{
struct drm_device *dev = usb_get_intfdata(interface);
- struct gm12u320_device *gm12u320 = dev->dev_private;
+ struct gm12u320_device *gm12u320 = to_gm12u320(dev);
gm12u320_set_ecomode(gm12u320);
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 21/59] drm/gm12u320: Use devm_drm_dev_alloc
Hi,
On 4/15/20 9:39 AM, Daniel Vetter wrote:
Already using devm_drm_dev_init, so very simple replacment.
Acked-by: Sam Ravnborg
Signed-off-by: Daniel Vetter
Cc: Hans de Goede
LGTM:
Reviewed-by: Hans de Goede
Regards,
Hans
---
drivers/gpu/drm/tiny/gm12u320.c | 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/tiny/gm12u320.c b/drivers/gpu/drm/tiny/gm12u320.c
index 6f0ea2827d62..907739a67bf6 100644
--- a/drivers/gpu/drm/tiny/gm12u320.c
+++ b/drivers/gpu/drm/tiny/gm12u320.c
@@ -631,22 +631,17 @@ static int gm12u320_usb_probe(struct usb_interface
*interface,
if (interface->cur_altsetting->desc.bInterfaceNumber != 0)
return -ENODEV;
- gm12u320 = kzalloc(sizeof(*gm12u320), GFP_KERNEL);
- if (gm12u320 == NULL)
- return -ENOMEM;
+ gm12u320 = devm_drm_dev_alloc(>dev, _drm_driver,
+ struct gm12u320_device, dev);
+ if (IS_ERR(gm12u320))
+ return PTR_ERR(gm12u320);
gm12u320->udev = interface_to_usbdev(interface);
INIT_DELAYED_WORK(>fb_update.work, gm12u320_fb_update_work);
mutex_init(>fb_update.lock);
dev = >dev;
- ret = devm_drm_dev_init(>dev, dev, _drm_driver);
- if (ret) {
- kfree(gm12u320);
- return ret;
- }
dev->dev_private = gm12u320;
- drmm_add_final_kfree(dev, gm12u320);
ret = drmm_mode_config_init(dev);
if (ret)
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 06/59] drm/vboxvideo: Use devm_gen_pool_create
Hi,
On 4/15/20 9:39 AM, Daniel Vetter wrote:
Aside from deleting all the cleanup code we're now also setting a name
for the pool
Acked-by: Sam Ravnborg
Signed-off-by: Daniel Vetter
Cc: Hans de Goede
LGTM:
Reviewed-by: Hans de Goede
Regards,
Hans
---
drivers/gpu/drm/vboxvideo/vbox_main.c | 22 --
1 file changed, 8 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/vboxvideo/vbox_main.c
b/drivers/gpu/drm/vboxvideo/vbox_main.c
index 1336ab9795fc..d68d9bad7674 100644
--- a/drivers/gpu/drm/vboxvideo/vbox_main.c
+++ b/drivers/gpu/drm/vboxvideo/vbox_main.c
@@ -121,7 +121,8 @@ int vbox_hw_init(struct vbox_private *vbox)
return -ENOMEM;
/* Create guest-heap mem-pool use 2^4 = 16 byte chunks */
- vbox->guest_pool = gen_pool_create(4, -1);
+ vbox->guest_pool = devm_gen_pool_create(vbox->ddev.dev, 4, -1,
+ "vboxvideo-accel");
if (!vbox->guest_pool)
return -ENOMEM;
@@ -130,12 +131,12 @@ int vbox_hw_init(struct vbox_private *vbox)
GUEST_HEAP_OFFSET(vbox),
GUEST_HEAP_USABLE_SIZE, -1);
if (ret)
- goto err_destroy_guest_pool;
+ return ret;
ret = hgsmi_test_query_conf(vbox->guest_pool);
if (ret) {
DRM_ERROR("vboxvideo: hgsmi_test_query_conf failed\n");
- goto err_destroy_guest_pool;
+ return ret;
}
/* Reduce available VRAM size to reflect the guest heap. */
@@ -147,30 +148,23 @@ int vbox_hw_init(struct vbox_private *vbox)
if (!have_hgsmi_mode_hints(vbox)) {
ret = -ENOTSUPP;
- goto err_destroy_guest_pool;
+ return ret;
}
vbox->last_mode_hints = devm_kcalloc(vbox->ddev.dev, vbox->num_crtcs,
sizeof(struct vbva_modehint),
GFP_KERNEL);
- if (!vbox->last_mode_hints) {
- ret = -ENOMEM;
- goto err_destroy_guest_pool;
- }
+ if (!vbox->last_mode_hints)
+ return -ENOMEM;
ret = vbox_accel_init(vbox);
if (ret)
- goto err_destroy_guest_pool;
+ return ret;
return 0;
-
-err_destroy_guest_pool:
- gen_pool_destroy(vbox->guest_pool);
- return ret;
}
void vbox_hw_fini(struct vbox_private *vbox)
{
vbox_accel_fini(vbox);
- gen_pool_destroy(vbox->guest_pool);
}
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v24 05/11] drm/i915: Use bw state for per crtc SAGV evaluation
Future platforms require per-crtc SAGV evaluation
and serializing global state when those are changed
from different commits.
v2: - Add has_sagv check to intel_crtc_can_enable_sagv
so that it sets bit in reject mask.
- Use bw_state in intel_pre/post_plane_enable_sagv
instead of atomic state
v3: - Fixed rebase conflict, now using
intel_atomic_crtc_state_for_each_plane_state in
order to call it from atomic check
v4: - Use fb modifier from plane state
Signed-off-by: Stanislav Lisovskiy
Cc: Ville Syrjälä
Cc: James Ausmus
---
drivers/gpu/drm/i915/display/intel_bw.h | 6 ++
drivers/gpu/drm/i915/intel_pm.c | 118 ++--
drivers/gpu/drm/i915/intel_pm.h | 4 +-
3 files changed, 97 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h
b/drivers/gpu/drm/i915/display/intel_bw.h
index ac004d6f4276..d6df91058223 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -18,6 +18,12 @@ struct intel_crtc_state;
struct intel_bw_state {
struct intel_global_state base;
+ /*
+* Contains a bit mask, used to determine, whether correspondent
+* pipe allows SAGV or not.
+*/
+ u8 pipe_sagv_reject;
+
unsigned int data_rate[I915_MAX_PIPES];
u8 num_active_planes[I915_MAX_PIPES];
};
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b0810d76ad47..65fd5a3571e4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -43,6 +43,7 @@
#include "i915_fixed.h"
#include "i915_irq.h"
#include "i915_trace.h"
+#include "display/intel_bw.h"
#include "intel_pm.h"
#include "intel_sideband.h"
#include "../../../platform/x86/intel_ips.h"
@@ -3634,7 +3635,7 @@ static bool skl_needs_memory_bw_wa(struct
drm_i915_private *dev_priv)
return IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv);
}
-static bool
+bool
intel_has_sagv(struct drm_i915_private *dev_priv)
{
/* HACK! */
@@ -3760,34 +3761,78 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ const struct intel_bw_state *new_bw_state = NULL;
- if (!intel_can_enable_sagv(state))
+ /*
+* Just return if we can't control SAGV or don't have it.
+* This is different from situation when we have SAGV but just can't
+* afford it due to DBuf limitation - in case if SAGV is completely
+* disabled in a BIOS, we are not even allowed to send a PCode request,
+* as it will throw an error. So have to check it here.
+*/
+ if (!intel_has_sagv(dev_priv))
+ return;
+
+ new_bw_state = intel_atomic_get_new_bw_state(state);
+ if (!new_bw_state)
+ return;
+
+ if (!intel_can_enable_sagv(new_bw_state))
intel_disable_sagv(dev_priv);
}
void intel_sagv_post_plane_update(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ const struct intel_bw_state *new_bw_state = NULL;
- if (intel_can_enable_sagv(state))
+ /*
+* Just return if we can't control SAGV or don't have it.
+* This is different from situation when we have SAGV but just can't
+* afford it due to DBuf limitation - in case if SAGV is completely
+* disabled in a BIOS, we are not even allowed to send a PCode request,
+* as it will throw an error. So have to check it here.
+*/
+ if (!intel_has_sagv(dev_priv))
+ return;
+
+ new_bw_state = intel_atomic_get_new_bw_state(state);
+ if (!new_bw_state)
+ return;
+
+ if (intel_can_enable_sagv(new_bw_state))
intel_enable_sagv(dev_priv);
}
static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state
*crtc_state)
{
- struct drm_device *dev = crtc_state->uapi.crtc->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_atomic_state *state =
to_intel_atomic_state(crtc_state->uapi.state);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct intel_plane *plane;
+ const struct intel_plane_state *plane_state;
int level, latency;
+ if (!intel_has_sagv(dev_priv))
+ return false;
+
if (!crtc_state->hw.active)
return true;
- if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
+ /*
+* SKL+ workaround: bspec recommends we disable SAGV when we have
+* more then one pipe enabled
+*/
+ if (hweight8(state->active_pipes) > 1)
return false;
- for_each_intel_plane_on_crtc(dev, crtc, plane)
Re: [Intel-gfx] [PATCH 05/59] drm/vboxvidoe: use managed pci functions
Hi,
On 4/15/20 9:39 AM, Daniel Vetter wrote:
Allows us to drop the cleanup code on the floor.
Sam noticed in his review:
With this change we avoid calling pci_disable_device()
twise in case vbox_mm_init() fails.
Once in vbox_hw_fini() and once in the error path.
v2: Include Sam's review remarks
Acked-by: Sam Ravnborg
Signed-off-by: Daniel Vetter
Cc: Hans de Goede
---
drivers/gpu/drm/vboxvideo/vbox_drv.c | 6 ++
drivers/gpu/drm/vboxvideo/vbox_main.c | 7 +--
2 files changed, 3 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/vboxvideo/vbox_drv.c
b/drivers/gpu/drm/vboxvideo/vbox_drv.c
index cfa4639c5142..cf2e3e6a2388 100644
--- a/drivers/gpu/drm/vboxvideo/vbox_drv.c
+++ b/drivers/gpu/drm/vboxvideo/vbox_drv.c
@@ -55,13 +55,13 @@ static int vbox_pci_probe(struct pci_dev *pdev, const
struct pci_device_id *ent)
pci_set_drvdata(pdev, vbox);
mutex_init(>hw_mutex);
- ret = pci_enable_device(pdev);
+ ret = pcim_enable_device(pdev);
if (ret)
return ret;
ret = vbox_hw_init(vbox);
if (ret)
- goto err_pci_disable;
+ return ret;
ret = vbox_mm_init(vbox);
if (ret)
@@ -91,8 +91,6 @@ static int vbox_pci_probe(struct pci_dev *pdev, const struct
pci_device_id *ent)
vbox_mm_fini(vbox);
err_hw_fini:
vbox_hw_fini(vbox);
-err_pci_disable:
- pci_disable_device(pdev);
return ret;
}
diff --git a/drivers/gpu/drm/vboxvideo/vbox_main.c b/drivers/gpu/drm/vboxvideo/vbox_main.c
index 9dcab115a261..1336ab9795fc 100644
--- a/drivers/gpu/drm/vboxvideo/vbox_main.c
+++ b/drivers/gpu/drm/vboxvideo/vbox_main.c
@@ -71,8 +71,6 @@ static void vbox_accel_fini(struct vbox_private *vbox)
for (i = 0; i < vbox->num_crtcs; ++i)
vbva_disable(>vbva_info[i], vbox->guest_pool, i);
-
- pci_iounmap(vbox->ddev.pdev, vbox->vbva_buffers);
}
/* Do we support the 4.3 plus mode hint reporting interface? */
This seems to be missing the conversion of the iomap_range call to
the devm equivalent ? :
drivers/gpu/drm/vboxvideo/vbox_main.c
44: vbox->vbva_buffers = pci_iomap_range(vbox->ddev.pdev, 0, ...
Regards,
Hans
@@ -125,7 +123,7 @@ int vbox_hw_init(struct vbox_private *vbox)
/* Create guest-heap mem-pool use 2^4 = 16 byte chunks */
vbox->guest_pool = gen_pool_create(4, -1);
if (!vbox->guest_pool)
- goto err_unmap_guest_heap;
+ return -ENOMEM;
ret = gen_pool_add_virt(vbox->guest_pool,
(unsigned long)vbox->guest_heap,
@@ -168,8 +166,6 @@ int vbox_hw_init(struct vbox_private *vbox)
err_destroy_guest_pool:
gen_pool_destroy(vbox->guest_pool);
-err_unmap_guest_heap:
- pci_iounmap(vbox->ddev.pdev, vbox->guest_heap);
return ret;
}
@@ -177,5 +173,4 @@ void vbox_hw_fini(struct vbox_private *vbox)
{
vbox_accel_fini(vbox);
gen_pool_destroy(vbox->guest_pool);
- pci_iounmap(vbox->ddev.pdev, vbox->guest_heap);
}
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 03/59] drm/vboxvideo: Use devm_drm_dev_alloc
Hi,
On 4/15/20 9:39 AM, Daniel Vetter wrote:
Straightforward conversion.
Signed-off-by: Daniel Vetter
Cc: Hans de Goede
LGTM:
Reviewed-by: Hans de Goede
Regards,
Hans
---
drivers/gpu/drm/vboxvideo/vbox_drv.c | 19 +--
1 file changed, 5 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/vboxvideo/vbox_drv.c
b/drivers/gpu/drm/vboxvideo/vbox_drv.c
index 282348e071fe..7dd25c7a3768 100644
--- a/drivers/gpu/drm/vboxvideo/vbox_drv.c
+++ b/drivers/gpu/drm/vboxvideo/vbox_drv.c
@@ -46,25 +46,19 @@ static int vbox_pci_probe(struct pci_dev *pdev, const
struct pci_device_id *ent)
if (ret)
return ret;
- vbox = kzalloc(sizeof(*vbox), GFP_KERNEL);
- if (!vbox)
- return -ENOMEM;
-
- ret = drm_dev_init(>ddev, , >dev);
- if (ret) {
- kfree(vbox);
- return ret;
- }
+ vbox = devm_drm_dev_alloc(>dev, ,
+ struct vbox_private, ddev);
+ if (IS_ERR(vbox))
+ return PTR_ERR(vbox);
vbox->ddev.pdev = pdev;
vbox->ddev.dev_private = vbox;
pci_set_drvdata(pdev, vbox);
- drmm_add_final_kfree(>ddev, vbox);
mutex_init(>hw_mutex);
ret = pci_enable_device(pdev);
if (ret)
- goto err_dev_put;
+ return ret;
ret = vbox_hw_init(vbox);
if (ret)
@@ -100,8 +94,6 @@ static int vbox_pci_probe(struct pci_dev *pdev, const struct
pci_device_id *ent)
vbox_hw_fini(vbox);
err_pci_disable:
pci_disable_device(pdev);
-err_dev_put:
- drm_dev_put(>ddev);
return ret;
}
@@ -114,7 +106,6 @@ static void vbox_pci_remove(struct pci_dev *pdev)
vbox_mode_fini(vbox);
vbox_mm_fini(vbox);
vbox_hw_fini(vbox);
- drm_dev_put(>ddev);
}
#ifdef CONFIG_PM_SLEEP
___
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Re: [Intel-gfx] [PATCH 04/59] drm/vboxvideo: Stop using drm_device->dev_private
Hi,
On 4/15/20 9:39 AM, Daniel Vetter wrote:
We use the baseclass pattern here, so lets to the proper (and more
typesafe) upcasting.
Acked-by: Sam Ravnborg
Acked-by: Thomas Zimmermann
Signed-off-by: Daniel Vetter
Cc: Hans de Goede
LGTM:
Reviewed-by: Hans de Goede
Regards,
Hans
---
drivers/gpu/drm/vboxvideo/vbox_drv.c | 1 -
drivers/gpu/drm/vboxvideo/vbox_drv.h | 1 +
drivers/gpu/drm/vboxvideo/vbox_irq.c | 2 +-
drivers/gpu/drm/vboxvideo/vbox_mode.c | 10 +-
4 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/vboxvideo/vbox_drv.c
b/drivers/gpu/drm/vboxvideo/vbox_drv.c
index 7dd25c7a3768..cfa4639c5142 100644
--- a/drivers/gpu/drm/vboxvideo/vbox_drv.c
+++ b/drivers/gpu/drm/vboxvideo/vbox_drv.c
@@ -52,7 +52,6 @@ static int vbox_pci_probe(struct pci_dev *pdev, const struct
pci_device_id *ent)
return PTR_ERR(vbox);
vbox->ddev.pdev = pdev;
- vbox->ddev.dev_private = vbox;
pci_set_drvdata(pdev, vbox);
mutex_init(>hw_mutex);
diff --git a/drivers/gpu/drm/vboxvideo/vbox_drv.h b/drivers/gpu/drm/vboxvideo/vbox_drv.h
index 87421903816c..ac7c2effc46f 100644
--- a/drivers/gpu/drm/vboxvideo/vbox_drv.h
+++ b/drivers/gpu/drm/vboxvideo/vbox_drv.h
@@ -127,6 +127,7 @@ struct vbox_encoder {
#define to_vbox_crtc(x) container_of(x, struct vbox_crtc, base)
#define to_vbox_connector(x) container_of(x, struct vbox_connector, base)
#define to_vbox_encoder(x) container_of(x, struct vbox_encoder, base)
+#define to_vbox_dev(x) container_of(x, struct vbox_private, ddev)
bool vbox_check_supported(u16 id);
int vbox_hw_init(struct vbox_private *vbox);
diff --git a/drivers/gpu/drm/vboxvideo/vbox_irq.c
b/drivers/gpu/drm/vboxvideo/vbox_irq.c
index 16a1e29f5292..631657fa554f 100644
--- a/drivers/gpu/drm/vboxvideo/vbox_irq.c
+++ b/drivers/gpu/drm/vboxvideo/vbox_irq.c
@@ -34,7 +34,7 @@ void vbox_report_hotplug(struct vbox_private *vbox)
irqreturn_t vbox_irq_handler(int irq, void *arg)
{
struct drm_device *dev = (struct drm_device *)arg;
- struct vbox_private *vbox = (struct vbox_private *)dev->dev_private;
+ struct vbox_private *vbox = to_vbox_dev(dev);
u32 host_flags = vbox_get_flags(vbox);
if (!(host_flags & HGSMIHOSTFLAGS_IRQ))
diff --git a/drivers/gpu/drm/vboxvideo/vbox_mode.c
b/drivers/gpu/drm/vboxvideo/vbox_mode.c
index 0883a435e62b..d9a5af62af89 100644
--- a/drivers/gpu/drm/vboxvideo/vbox_mode.c
+++ b/drivers/gpu/drm/vboxvideo/vbox_mode.c
@@ -36,7 +36,7 @@ static void vbox_do_modeset(struct drm_crtc *crtc)
u16 flags;
s32 x_offset, y_offset;
- vbox = crtc->dev->dev_private;
+ vbox = to_vbox_dev(crtc->dev);
width = vbox_crtc->width ? vbox_crtc->width : 640;
height = vbox_crtc->height ? vbox_crtc->height : 480;
bpp = fb ? fb->format->cpp[0] * 8 : 32;
@@ -77,7 +77,7 @@ static void vbox_do_modeset(struct drm_crtc *crtc)
static int vbox_set_view(struct drm_crtc *crtc)
{
struct vbox_crtc *vbox_crtc = to_vbox_crtc(crtc);
- struct vbox_private *vbox = crtc->dev->dev_private;
+ struct vbox_private *vbox = to_vbox_dev(crtc->dev);
struct vbva_infoview *p;
/*
@@ -174,7 +174,7 @@ static void vbox_crtc_set_base_and_mode(struct drm_crtc
*crtc,
int x, int y)
{
struct drm_gem_vram_object *gbo = drm_gem_vram_of_gem(fb->obj[0]);
- struct vbox_private *vbox = crtc->dev->dev_private;
+ struct vbox_private *vbox = to_vbox_dev(crtc->dev);
struct vbox_crtc *vbox_crtc = to_vbox_crtc(crtc);
bool needs_modeset = drm_atomic_crtc_needs_modeset(crtc->state);
@@ -272,7 +272,7 @@ static void vbox_primary_atomic_update(struct drm_plane *plane,
{
struct drm_crtc *crtc = plane->state->crtc;
struct drm_framebuffer *fb = plane->state->fb;
- struct vbox_private *vbox = fb->dev->dev_private;
+ struct vbox_private *vbox = to_vbox_dev(fb->dev);
struct drm_mode_rect *clips;
uint32_t num_clips, i;
@@ -704,7 +704,7 @@ static int vbox_get_modes(struct drm_connector *connector)
int preferred_width, preferred_height;
vbox_connector = to_vbox_connector(connector);
- vbox = connector->dev->dev_private;
+ vbox = to_vbox_dev(connector->dev);
hgsmi_report_flags_location(vbox->guest_pool, GUEST_HEAP_OFFSET(vbox) +
HOST_FLAGS_OFFSET);
___
Intel-gfx mailing list
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Re: [Intel-gfx] [PATCH 02/59] drm/vboxvideo: drop DRM_MTRR_WC #define
Hi,
On 4/15/20 9:39 AM, Daniel Vetter wrote:
Doesn't apply to upstream kernels since a rather long time.
Acked-by: Sam Ravnborg
Signed-off-by: Daniel Vetter
Cc: Hans de Goede
LGTM:
Reviewed-by: Hans de Goede
Regards,
Hans
---
drivers/gpu/drm/vboxvideo/vbox_ttm.c | 12
1 file changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/vboxvideo/vbox_ttm.c
b/drivers/gpu/drm/vboxvideo/vbox_ttm.c
index 976423d0c3cc..f5a06675da43 100644
--- a/drivers/gpu/drm/vboxvideo/vbox_ttm.c
+++ b/drivers/gpu/drm/vboxvideo/vbox_ttm.c
@@ -24,25 +24,13 @@ int vbox_mm_init(struct vbox_private *vbox)
return ret;
}
-#ifdef DRM_MTRR_WC
- vbox->fb_mtrr = drm_mtrr_add(pci_resource_start(dev->pdev, 0),
-pci_resource_len(dev->pdev, 0),
-DRM_MTRR_WC);
-#else
vbox->fb_mtrr = arch_phys_wc_add(pci_resource_start(dev->pdev, 0),
pci_resource_len(dev->pdev, 0));
-#endif
return 0;
}
void vbox_mm_fini(struct vbox_private *vbox)
{
-#ifdef DRM_MTRR_WC
- drm_mtrr_del(vbox->fb_mtrr,
-pci_resource_start(vbox->ddev.pdev, 0),
-pci_resource_len(vbox->ddev.pdev, 0), DRM_MTRR_WC);
-#else
arch_phys_wc_del(vbox->fb_mtrr);
-#endif
drm_vram_helper_release_mm(>ddev);
}
___
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[Intel-gfx] [PATCH v24 03/11] drm/i915: Prepare to extract gen specific functions from intel_can_enable_sagv
Addressing one of the comments, recommending to extract platform
specific code from intel_can_enable_sagv as a preparation, before
we are going to add support for tgl+.
v2: - Removed whitespace
v3: - Removed premature debug and new cycle introduction(Ville)
- Added missing no active pipes check(Ville)
v4: - Fixed stupid mistake with plane_state caused by stupid macro change
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/intel_pm.c | 61 +++--
1 file changed, 36 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bd57f0bb8a54..cda2bc954193 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3757,42 +3757,22 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
return 0;
}
-bool intel_can_enable_sagv(struct intel_atomic_state *state)
+static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state
*crtc_state)
{
- struct drm_device *dev = state->base.dev;
+ struct drm_device *dev = crtc_state->uapi.crtc->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_crtc *crtc;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct intel_plane *plane;
- struct intel_crtc_state *crtc_state;
- enum pipe pipe;
int level, latency;
- if (!intel_has_sagv(dev_priv))
- return false;
-
- /*
-* If there are no active CRTCs, no additional checks need be performed
-*/
- if (hweight8(state->active_pipes) == 0)
+ if (!crtc_state->hw.active)
return true;
- /*
-* SKL+ workaround: bspec recommends we disable SAGV when we have
-* more then one pipe enabled
-*/
- if (hweight8(state->active_pipes) > 1)
- return false;
-
- /* Since we're now guaranteed to only have one active CRTC... */
- pipe = ffs(state->active_pipes) - 1;
- crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
- crtc_state = to_intel_crtc_state(crtc->base.state);
-
if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
return false;
for_each_intel_plane_on_crtc(dev, crtc, plane) {
- struct skl_plane_wm *wm =
+ const struct skl_plane_wm *wm =
_state->wm.skl.optimal.planes[plane->id];
/* Skip this plane if it's not enabled */
@@ -3823,6 +3803,37 @@ bool intel_can_enable_sagv(struct intel_atomic_state
*state)
return true;
}
+bool intel_can_enable_sagv(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc *crtc;
+ const struct intel_crtc_state *crtc_state;
+ enum pipe pipe;
+
+ if (!intel_has_sagv(dev_priv))
+ return false;
+
+ /*
+* If there are no active CRTCs, no additional checks need be performed
+*/
+ if (hweight8(state->active_pipes) == 0)
+ return true;
+
+ /*
+* SKL+ workaround: bspec recommends we disable SAGV when we have
+* more then one pipe enabled
+*/
+ if (hweight8(state->active_pipes) > 1)
+ return false;
+
+ /* Since we're now guaranteed to only have one active CRTC... */
+ pipe = ffs(state->active_pipes) - 1;
+ crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
+ crtc_state = to_intel_crtc_state(crtc->base.state);
+
+ return intel_crtc_can_enable_sagv(crtc_state);
+}
+
/*
* Calculate initial DBuf slice offset, based on slice size
* and mask(i.e if slice size is 1024 and second slice is enabled
--
2.24.1.485.gad05a3d8e5
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/selftests: Exercise basic RPS interrupt generation
Since we depend upon RPS generating interrupts after evaluation
intervals to determine when to up/down clock the GPU, it is imperative
that we successfully enable interrupt generation! Verify that we do see
an interrupt if we keep the GPU busy for an entire EI.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_rps.c | 4 +
drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 2 +
drivers/gpu/drm/i915/gt/selftest_rps.c | 220 +++
drivers/gpu/drm/i915/gt/selftest_rps.h | 11 ++
4 files changed, 237 insertions(+)
create mode 100644 drivers/gpu/drm/i915/gt/selftest_rps.c
create mode 100644 drivers/gpu/drm/i915/gt/selftest_rps.h
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 86110458e2a7..d19161c7a3d8 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -1923,3 +1923,7 @@ bool i915_gpu_turbo_disable(void)
return ret;
}
EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
+
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftest_rps.c"
+#endif
diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
index 09ff8e4f88af..c50bb502fe03 100644
--- a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
@@ -7,6 +7,7 @@
#include "selftest_llc.h"
#include "selftest_rc6.h"
+#include "selftest_rps.h"
static int live_gt_resume(void *arg)
{
@@ -52,6 +53,7 @@ int intel_gt_pm_live_selftests(struct drm_i915_private *i915)
{
static const struct i915_subtest tests[] = {
SUBTEST(live_rc6_manual),
+ SUBTEST(live_rps_interrupt),
SUBTEST(live_gt_resume),
};
diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c
b/drivers/gpu/drm/i915/gt/selftest_rps.c
new file mode 100644
index ..19e3fafe4dce
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
@@ -0,0 +1,220 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#include "intel_engine_pm.h"
+#include "intel_gt_pm.h"
+#include "intel_rc6.h"
+#include "selftest_rps.h"
+#include "selftests/igt_flush_test.h"
+#include "selftests/igt_spinner.h"
+
+static void dummy_rps_work(struct work_struct *wrk)
+{
+}
+
+static int __rps_up_interrupt(struct intel_rps *rps,
+ struct intel_engine_cs *engine,
+ struct igt_spinner *spin)
+{
+ struct intel_uncore *uncore = engine->uncore;
+ struct i915_request *rq;
+ u32 timeout;
+
+ intel_gt_pm_wait_for_idle(engine->gt);
+ GEM_BUG_ON(rps->active);
+
+ rps->pm_iir = 0;
+ rps->cur_freq = rps->min_freq;
+
+ rq = igt_spinner_create_request(spin, engine->kernel_context, MI_NOOP);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ i915_request_get(rq);
+ i915_request_add(rq);
+
+ if (!igt_wait_for_spinner(spin, rq)) {
+ pr_err("%s: RPS spinner did not start\n",
+ engine->name);
+ i915_request_put(rq);
+ intel_gt_set_wedged(engine->gt);
+ return -EIO;
+ }
+
+ if (!rps->active) {
+ pr_err("%s: RPS not enabled on starting spinner\n",
+ engine->name);
+ igt_spinner_end(spin);
+ i915_request_put(rq);
+ return -EINVAL;
+ }
+
+ if (!(rps->pm_events & GEN6_PM_RP_UP_THRESHOLD)) {
+ pr_err("%s: RPS did not register UP interrupt\n",
+ engine->name);
+ i915_request_put(rq);
+ return -EINVAL;
+ }
+
+ if (rps->last_freq != rps->min_freq) {
+ pr_err("%s: RPS did not program min frequency\n",
+ engine->name);
+ i915_request_put(rq);
+ return -EINVAL;
+ }
+
+ timeout = intel_uncore_read(uncore, GEN6_RP_UP_EI);
+ timeout = GT_PM_INTERVAL_TO_US(engine->i915, timeout);
+
+ usleep_range(2 * timeout, 3 * timeout);
+ GEM_BUG_ON(i915_request_completed(rq));
+
+ igt_spinner_end(spin);
+ i915_request_put(rq);
+
+ if (rps->cur_freq != rps->min_freq) {
+ pr_err("%s: Frequency unexpectedly changed [up], now %d!\n",
+ engine->name, intel_rps_read_actual_frequency(rps));
+ return -EINVAL;
+ }
+
+ if (!(rps->pm_iir & GEN6_PM_RP_UP_THRESHOLD)) {
+ pr_err("%s: UP interrupt not recorded for spinner, pm_iir:%x,
prev_up:%x, up_threshold:%x, up_ei:%x\n",
+ engine->name, rps->pm_iir,
+ intel_uncore_read(uncore, GEN6_RP_PREV_UP),
+ intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD),
+ intel_uncore_read(uncore, GEN6_RP_UP_EI));
+ return -EINVAL;
+ }
+
+ intel_gt_pm_wait_for_idle(engine->gt);
+
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Always defer fenced work to the worker
== Series Details == Series: drm/i915: Always defer fenced work to the worker URL : https://patchwork.freedesktop.org/series/75917/ State : success == Summary == CI Bug Log - changes from CI_DRM_8298_full -> Patchwork_17295_full Summary --- **SUCCESS** No regressions found. New tests - New tests have been introduced between CI_DRM_8298_full and Patchwork_17295_full: ### New IGT tests (27) ### * igt@kms_plane_cursor@pipe-a-overlay-size-128: - Statuses : 7 pass(s) - Exec time: [1.66, 2.72] s * igt@kms_plane_cursor@pipe-a-overlay-size-256: - Statuses : 8 pass(s) - Exec time: [1.65, 3.59] s * igt@kms_plane_cursor@pipe-a-overlay-size-64: - Statuses : 7 pass(s) - Exec time: [1.65, 2.73] s * igt@kms_plane_cursor@pipe-a-primary-size-128: - Statuses : 8 pass(s) - Exec time: [1.64, 3.34] s * igt@kms_plane_cursor@pipe-a-primary-size-256: - Statuses : 8 pass(s) - Exec time: [1.64, 3.50] s * igt@kms_plane_cursor@pipe-a-primary-size-64: - Statuses : 8 pass(s) - Exec time: [1.63, 3.36] s * igt@kms_plane_cursor@pipe-a-viewport-size-128: - Statuses : 8 pass(s) - Exec time: [1.65, 3.67] s * igt@kms_plane_cursor@pipe-a-viewport-size-256: - Statuses : 8 pass(s) - Exec time: [1.64, 3.66] s * igt@kms_plane_cursor@pipe-a-viewport-size-64: - Statuses : 8 pass(s) - Exec time: [1.65, 3.69] s * igt@kms_plane_cursor@pipe-b-overlay-size-128: - Statuses : 8 pass(s) - Exec time: [2.23, 4.87] s * igt@kms_plane_cursor@pipe-b-overlay-size-256: - Statuses : 8 pass(s) - Exec time: [2.22, 4.81] s * igt@kms_plane_cursor@pipe-b-overlay-size-64: - Statuses : 8 pass(s) - Exec time: [2.23, 4.81] s * igt@kms_plane_cursor@pipe-b-primary-size-128: - Statuses : 8 pass(s) - Exec time: [2.20, 4.64] s * igt@kms_plane_cursor@pipe-b-primary-size-256: - Statuses : 8 pass(s) - Exec time: [2.21, 4.67] s * igt@kms_plane_cursor@pipe-b-primary-size-64: - Statuses : 8 pass(s) - Exec time: [2.21, 4.67] s * igt@kms_plane_cursor@pipe-b-viewport-size-128: - Statuses : - Exec time: [None] s * igt@kms_plane_cursor@pipe-b-viewport-size-256: - Statuses : 8 pass(s) - Exec time: [2.23, 4.83] s * igt@kms_plane_cursor@pipe-b-viewport-size-64: - Statuses : 8 pass(s) - Exec time: [2.23, 4.86] s * igt@kms_plane_cursor@pipe-c-overlay-size-128: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.86] s * igt@kms_plane_cursor@pipe-c-overlay-size-256: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.87] s * igt@kms_plane_cursor@pipe-c-overlay-size-64: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.84] s * igt@kms_plane_cursor@pipe-c-primary-size-128: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.79] s * igt@kms_plane_cursor@pipe-c-primary-size-256: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.65] s * igt@kms_plane_cursor@pipe-c-primary-size-64: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.63] s * igt@kms_plane_cursor@pipe-c-viewport-size-128: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.82] s * igt@kms_plane_cursor@pipe-c-viewport-size-256: - Statuses : 6 pass(s) 1 skip(s) - Exec time: [0.0, 3.60] s * igt@kms_plane_cursor@pipe-c-viewport-size-64: - Statuses : 7 pass(s) 1 skip(s) - Exec time: [0.0, 4.86] s Known issues Here are the changes found in Patchwork_17295_full that come from known issues: ### IGT changes ### Issues hit * igt@i915_pm_backlight@fade_with_suspend: - shard-skl: [PASS][1] -> [INCOMPLETE][2] ([i915#69]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-skl8/igt@i915_pm_backlight@fade_with_suspend.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17295/shard-skl4/igt@i915_pm_backlight@fade_with_suspend.html * igt@kms_atomic_transition@1x-modeset-transitions: - shard-snb: [PASS][3] -> [SKIP][4] ([fdo#109271]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-snb2/igt@kms_atomic_transit...@1x-modeset-transitions.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17295/shard-snb4/igt@kms_atomic_transit...@1x-modeset-transitions.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-kbl2/igt@kms_cursor_...@pipe-a-cursor-suspend.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17295/shard-kbl2/igt@kms_cursor_...@pipe-a-cursor-suspend.html * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: - shard-glk: [PASS][7] -> [FAIL][8] ([i915#79]) [7]:
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: Exercise basic RPS interrupt generation (rev5)
== Series Details == Series: drm/i915/selftests: Exercise basic RPS interrupt generation (rev5) URL : https://patchwork.freedesktop.org/series/75966/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8301 -> Patchwork_17308 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_17308 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17308, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17308/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_17308: ### IGT changes ### Possible regressions * igt@i915_selftest@live@gt_pm: - fi-cml-s: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/fi-cml-s/igt@i915_selftest@live@gt_pm.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17308/fi-cml-s/igt@i915_selftest@live@gt_pm.html - fi-icl-y: [PASS][3] -> [DMESG-FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/fi-icl-y/igt@i915_selftest@live@gt_pm.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17308/fi-icl-y/igt@i915_selftest@live@gt_pm.html - fi-cfl-guc: [PASS][5] -> [DMESG-FAIL][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/fi-cfl-guc/igt@i915_selftest@live@gt_pm.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17308/fi-cfl-guc/igt@i915_selftest@live@gt_pm.html - fi-skl-6700k2: [PASS][7] -> [DMESG-FAIL][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/fi-skl-6700k2/igt@i915_selftest@live@gt_pm.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17308/fi-skl-6700k2/igt@i915_selftest@live@gt_pm.html - fi-bsw-n3050: [PASS][9] -> [INCOMPLETE][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/fi-bsw-n3050/igt@i915_selftest@live@gt_pm.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17308/fi-bsw-n3050/igt@i915_selftest@live@gt_pm.html - fi-skl-guc: [PASS][11] -> [DMESG-FAIL][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/fi-skl-guc/igt@i915_selftest@live@gt_pm.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17308/fi-skl-guc/igt@i915_selftest@live@gt_pm.html - fi-icl-dsi: [PASS][13] -> [DMESG-FAIL][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/fi-icl-dsi/igt@i915_selftest@live@gt_pm.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17308/fi-icl-dsi/igt@i915_selftest@live@gt_pm.html - fi-kbl-x1275: [PASS][15] -> [INCOMPLETE][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/fi-kbl-x1275/igt@i915_selftest@live@gt_pm.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17308/fi-kbl-x1275/igt@i915_selftest@live@gt_pm.html - fi-bsw-kefka: [PASS][17] -> [INCOMPLETE][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/fi-bsw-kefka/igt@i915_selftest@live@gt_pm.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17308/fi-bsw-kefka/igt@i915_selftest@live@gt_pm.html - fi-tgl-y: [PASS][19] -> [DMESG-FAIL][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/fi-tgl-y/igt@i915_selftest@live@gt_pm.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17308/fi-tgl-y/igt@i915_selftest@live@gt_pm.html - fi-cfl-8700k: NOTRUN -> [DMESG-FAIL][21] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17308/fi-cfl-8700k/igt@i915_selftest@live@gt_pm.html - fi-icl-u2: [PASS][22] -> [DMESG-FAIL][23] [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/fi-icl-u2/igt@i915_selftest@live@gt_pm.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17308/fi-icl-u2/igt@i915_selftest@live@gt_pm.html - fi-skl-6600u: [PASS][24] -> [INCOMPLETE][25] [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/fi-skl-6600u/igt@i915_selftest@live@gt_pm.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17308/fi-skl-6600u/igt@i915_selftest@live@gt_pm.html - fi-cfl-8109u: [PASS][26] -> [DMESG-FAIL][27] [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/fi-cfl-8109u/igt@i915_selftest@live@gt_pm.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17308/fi-cfl-8109u/igt@i915_selftest@live@gt_pm.html - fi-bsw-nick:[PASS][28] -> [INCOMPLETE][29] [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8301/fi-bsw-nick/igt@i915_selftest@live@gt_pm.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17308/fi-bsw-nick/igt@i915_selftest@live@gt_pm.html -
Re: [Intel-gfx] [PATCH] drm/i915/icl: Update forcewake firmware ranges
On Wed, Apr 15, 2020 at 07:28:18AM -0700, Sripada, Radhakrishna wrote:
> Hi Matt,
>
> > -Original Message-
> > From: Roper, Matthew D
> > Sent: Tuesday, April 14, 2020 11:40 AM
> > To: Sripada, Radhakrishna
> > Cc: intel-gfx@lists.freedesktop.org
> > Subject: Re: [PATCH] drm/i915/icl: Update forcewake firmware ranges
> >
> > On Mon, Apr 13, 2020 at 02:00:03AM -0700, Radhakrishna Sripada wrote:
> > > Some workarounds are not sticking across suspend resume cycles. The
> > > forcewake ranges table has been updated and would reflect the hardware
> > > appropriately.
> > >
> > > Closes: https://gitlab.freedesktop.org/drm/intel/issues/1222
> >
> > It's unfortunate that they still haven't updated the bspec for this yet.
> > A few comments below based on my understanding of the document we
> > received from the hardware team.
> >
> > >
> > > Cc: Matt Roper
> > > Signed-off-by: Radhakrishna Sripada
> > > ---
> > > drivers/gpu/drm/i915/intel_uncore.c | 55
> > > +
> > > 1 file changed, 41 insertions(+), 14 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c
> > > b/drivers/gpu/drm/i915/intel_uncore.c
> > > index fa86b7ab2d99..c0e21697a44c 100644
> > > --- a/drivers/gpu/drm/i915/intel_uncore.c
> > > +++ b/drivers/gpu/drm/i915/intel_uncore.c
> > > @@ -1098,32 +1098,59 @@ static const struct intel_forcewake_range
> > > __gen11_fw_ranges[] = {
> >
> > Looks like the first range in this table (0x0 - 0xaff) needs to be changed
> > to '0' (or
> > rather combined with the following entry for a combined 0x0 - 0x1fff range
> > set
> > to '0')
>
> Comparing with previous gens, my understanding is the '0' is indicative of
> uncore range
> Of registers. The reserved ranges are marked with "Blitter" force wake range.
> Am I in the right
> Path making that assumption? Hence made all the subsequent changes according
> to the assumption.
The final parameter of GEN_FW_RANGE() is a bitmask of domains that we
need to make sure are powered up when we're going to access a register
in that range. So a 0 means no domains need to be powered up for
registers in that range. That might be because it's a range that
contains no registers at all (reserved range), or it may be that the
registers in that range simply aren't part of the blitter, render,
media, etc. power wells and we don't have to worry about powering
anything up.
In cases where there are no actual registers (i.e., reserved ranges), it
doesn't really matter what you put since there shouldn't be any register
reads/writes in that range. So for those we'll often combine them with
one of the surrounding ranges just to keep the overall forcewake table
smaller and make lookups faster.
Matt
>
> Thanks,
> Radhakrishna(RK) Sripada
> >
> >
> > > GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
> > > GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
> > > GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
> > > - GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
> > > + GEN_FW_RANGE(0x5200, 0x53ff, FORCEWAKE_RENDER),
> > > + GEN_FW_RANGE(0x5400, 0x54ff, FORCEWAKE_BLITTER),
> >
> > In the version of the document I'm looking at, the wake target for this
> > entry is
> > blank, which usually means no wake target is required. AFAICS, no registers
> > actually fall in this range on gen11, so I'd either set this to '0' to
> > explicitly match
> > the document, or just leave it combined with the two surrounding render
> > ranges
> > for simplicity (and smaller table size).
> >
> > > + GEN_FW_RANGE(0x5500, 0x7fff, FORCEWAKE_RENDER),
> > > GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_BLITTER),
> > > GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
> > > GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
> > > GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
> > > - GEN_FW_RANGE(0x8500, 0x8bff, FORCEWAKE_BLITTER),
> > > + GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_BLITTER),
> > > + GEN_FW_RANGE(0x8800, 0x883f, 0),
> > > + GEN_FW_RANGE(0x8840, 0x8bff, FORCEWAKE_BLITTER),
> >
> > I see 0x8840 - 0x8bff as a reserved range with no forcewake target so we
> > should
> > be able to combine it with the range before it.
> >
> > > GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
> > > - GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
> > > - GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_ALL),
> > > - GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
> > > + GEN_FW_RANGE(0x8d00, 0x94cf, FORCEWAKE_BLITTER),
> > > + GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER),
> > > + GEN_FW_RANGE(0x9560, 0x95ff, 0),
> > > + GEN_FW_RANGE(0x9600, 0xafff, FORCEWAKE_BLITTER),
> > > GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
> > > GEN_FW_RANGE(0xb480, 0xdeff, FORCEWAKE_BLITTER),
> > > GEN_FW_RANGE(0xdf00, 0xe8ff, FORCEWAKE_RENDER),
> > > GEN_FW_RANGE(0xe900, 0x16dff, FORCEWAKE_BLITTER),
> > > GEN_FW_RANGE(0x16e00, 0x19fff, FORCEWAKE_RENDER),
> > > - GEN_FW_RANGE(0x1a000, 0x243ff, FORCEWAKE_BLITTER),
> > > - GEN_FW_RANGE(0x24400,
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Fix indirect context size calculation
== Series Details == Series: drm/i915: Fix indirect context size calculation URL : https://patchwork.freedesktop.org/series/75916/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8298_full -> Patchwork_17294_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_17294_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17294_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Changes --- No changes found Participating hosts (10 -> 2) -- ERROR: It appears as if the changes made in Patchwork_17294_full prevented too many machines from booting. Missing(8): shard-skl shard-tglb shard-iclb shard-apl shard-glk shard-hsw shard-kbl shard-snb Build changes - * CI: CI-20190529 -> None * IGT: IGT_5589 -> None * Linux: CI_DRM_8298 -> Patchwork_17294 CI-20190529: 20190529 CI_DRM_8298: 17f82f0c2857d0b442adbdb62eb44b61d0f5b775 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5589: 31962324ac86f029e2841e56e97c42cf9d572956 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17294: 098eb3c86877f4db93ddb01876f0e4479c3782d9 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17294/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/gt: Move the batch buffer pool from the engine to the gt
Since the introduction of 'soft-rc6', we aim to park the device quickly
and that results in frequent idling of the whole device. Currently upon
idling we free the batch buffer pool, and so this renders the cache
ineffective for many workloads. If we want to have an effective cache of
recently allocated buffers available for reuse, we need to decouple that
cache from the engine powermanagement and make it timer based. As there
is no reason then to keep it within the engine (where it once made
retirement order easier to track), we can move it up the hierachy to the
owner of the memory allocations.
Signed-off-by: Chris Wilson
Cc: Maarten Lankhorst
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/Makefile | 2 +-
.../gpu/drm/i915/gem/i915_gem_client_blt.c| 1 -
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 20 ++--
.../gpu/drm/i915/gem/i915_gem_object_blt.c| 18 +--
.../gpu/drm/i915/gem/i915_gem_object_blt.h| 1 -
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 -
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 2 -
drivers/gpu/drm/i915/gt/intel_engine_pool.h | 34 --
drivers/gpu/drm/i915/gt/intel_engine_types.h | 8 --
drivers/gpu/drm/i915/gt/intel_gt.c| 3 +
...l_engine_pool.c => intel_gt_buffer_pool.c} | 104 --
.../gpu/drm/i915/gt/intel_gt_buffer_pool.h| 37 +++
...l_types.h => intel_gt_buffer_pool_types.h} | 15 ++-
drivers/gpu/drm/i915/gt/intel_gt_types.h | 11 ++
drivers/gpu/drm/i915/gt/mock_engine.c | 2 -
15 files changed, 148 insertions(+), 114 deletions(-)
delete mode 100644 drivers/gpu/drm/i915/gt/intel_engine_pool.h
rename drivers/gpu/drm/i915/gt/{intel_engine_pool.c => intel_gt_buffer_pool.c}
(55%)
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.h
rename drivers/gpu/drm/i915/gt/{intel_engine_pool_types.h =>
intel_gt_buffer_pool_types.h} (54%)
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 44c506b7e117..1e9eb26912c3 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -86,11 +86,11 @@ gt-y += \
gt/intel_engine_cs.o \
gt/intel_engine_heartbeat.o \
gt/intel_engine_pm.o \
- gt/intel_engine_pool.o \
gt/intel_engine_user.o \
gt/intel_ggtt.o \
gt/intel_ggtt_fencing.o \
gt/intel_gt.o \
+ gt/intel_gt_buffer_pool.o \
gt/intel_gt_irq.o \
gt/intel_gt_pm.o \
gt/intel_gt_pm_irq.o \
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
index 0598e5382a1d..3a146aa2593b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
@@ -6,7 +6,6 @@
#include "i915_drv.h"
#include "gt/intel_context.h"
#include "gt/intel_engine_pm.h"
-#include "gt/intel_engine_pool.h"
#include "i915_gem_client_blt.h"
#include "i915_gem_object_blt.h"
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 517898aa634c..042916ad3629 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -15,8 +15,8 @@
#include "gem/i915_gem_ioctls.h"
#include "gt/intel_context.h"
-#include "gt/intel_engine_pool.h"
#include "gt/intel_gt.h"
+#include "gt/intel_gt_buffer_pool.h"
#include "gt/intel_gt_pm.h"
#include "gt/intel_ring.h"
@@ -1194,13 +1194,13 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
unsigned int len)
{
struct reloc_cache *cache = >reloc_cache;
- struct intel_engine_pool_node *pool;
+ struct intel_gt_buffer_pool_node *pool;
struct i915_request *rq;
struct i915_vma *batch;
u32 *cmd;
int err;
- pool = intel_engine_get_pool(eb->engine, PAGE_SIZE);
+ pool = intel_gt_get_buffer_pool(eb->engine->gt, PAGE_SIZE);
if (IS_ERR(pool))
return PTR_ERR(pool);
@@ -1229,7 +1229,7 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
goto err_unpin;
}
- err = intel_engine_pool_mark_active(pool, rq);
+ err = intel_gt_buffer_pool_mark_active(pool, rq);
if (err)
goto err_request;
@@ -1270,7 +1270,7 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
err_unmap:
i915_gem_object_unpin_map(pool->obj);
out_pool:
- intel_engine_pool_put(pool);
+ intel_gt_buffer_pool_put(pool);
return err;
}
@@ -1887,7 +1887,7 @@ static int eb_parse_pipeline(struct i915_execbuffer *eb,
static int eb_parse(struct i915_execbuffer *eb)
{
struct drm_i915_private *i915 = eb->i915;
- struct intel_engine_pool_node *pool;
+ struct intel_gt_buffer_pool_node *pool;
struct i915_vma *shadow, *trampoline;
unsigned int len;
int err;
@@ -1910,7 +1910,7 @@ static int eb_parse(struct
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/selftests: Exercise basic RPS interrupt generation (rev5)
== Series Details == Series: drm/i915/selftests: Exercise basic RPS interrupt generation (rev5) URL : https://patchwork.freedesktop.org/series/75966/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 /home/cidrm/kernel/Documentation/gpu/i915.rst:610: WARNING: duplicate label gpu/i915:layout, other instance in /home/cidrm/kernel/Documentation/gpu/i915.rst ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v24 04/11] drm/i915: Add pre/post plane updates for SAGV
Lets have a unified way to handle SAGV changes,
espoecially considering the upcoming Gen12 changes.
Current "standard" way of doing this in commit_tail
is pre/post plane updates, when everything which
has to be forbidden and not supported in new config
has to be restricted before update and relaxed after
plane update.
v2: - Removed unneeded returns(Ville)
Reviewed-by: Ville Syrjälä
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_display.c | 13 -
drivers/gpu/drm/i915/intel_pm.c | 16
drivers/gpu/drm/i915/intel_pm.h | 2 ++
3 files changed, 22 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 70ec301fe6e3..ac7f600c84ca 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15349,12 +15349,7 @@ static void intel_atomic_commit_tail(struct
intel_atomic_state *state)
intel_set_cdclk_pre_plane_update(state);
- /*
-* SKL workaround: bspec recommends we disable the SAGV when we
-* have more then one pipe enabled
-*/
- if (!intel_can_enable_sagv(state))
- intel_disable_sagv(dev_priv);
+ intel_sagv_pre_plane_update(state);
intel_modeset_verify_disabled(dev_priv, state);
}
@@ -15451,11 +15446,11 @@ static void intel_atomic_commit_tail(struct
intel_atomic_state *state)
intel_check_cpu_fifo_underruns(dev_priv);
intel_check_pch_fifo_underruns(dev_priv);
- if (state->modeset)
+ if (state->modeset) {
intel_verify_planes(state);
- if (state->modeset && intel_can_enable_sagv(state))
- intel_enable_sagv(dev_priv);
+ intel_sagv_post_plane_update(state);
+ }
drm_atomic_helper_commit_hw_done(>base);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a0958f40e161..83a0aac31aa8 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3757,6 +3757,22 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
return 0;
}
+void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+
+ if (!intel_can_enable_sagv(state))
+ intel_disable_sagv(dev_priv);
+}
+
+void intel_sagv_post_plane_update(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+
+ if (intel_can_enable_sagv(state))
+ intel_enable_sagv(dev_priv);
+}
+
static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state
*crtc_state)
{
struct drm_device *dev = crtc_state->uapi.crtc->dev;
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index d60a85421c5a..9a6036ab0f90 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -44,6 +44,8 @@ void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
bool intel_can_enable_sagv(struct intel_atomic_state *state);
int intel_enable_sagv(struct drm_i915_private *dev_priv);
int intel_disable_sagv(struct drm_i915_private *dev_priv);
+void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
+void intel_sagv_post_plane_update(struct intel_atomic_state *state);
bool skl_wm_level_equals(const struct skl_wm_level *l1,
const struct skl_wm_level *l2);
bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
--
2.24.1.485.gad05a3d8e5
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v24 00/11] SAGV support for Gen12+
For Gen11+ platforms BSpec suggests disabling specific QGV points separately, depending on bandwidth limitations and current display configuration. Thus it required adding a new PCode request for disabling QGV points and some refactoring of already existing SAGV code. Also had to refactor intel_can_enable_sagv function, as current seems to be outdated and using skl specific workarounds, also not following BSpec for Gen11+. Stanislav Lisovskiy (11): drm/i915: Introduce skl_plane_wm_level accessor. drm/i915: Add intel_atomic_get_bw_*_state helpers drm/i915: Prepare to extract gen specific functions from intel_can_enable_sagv drm/i915: Add pre/post plane updates for SAGV drm/i915: Use bw state for per crtc SAGV evaluation drm/i915: Separate icl and skl SAGV checking drm/i915: Add TGL+ SAGV support drm/i915: Added required new PCode commands drm/i915: Rename bw_state to new_bw_state drm/i915: Restrict qgv points which don't have enough bandwidth. drm/i915: Enable SAGV support for Gen12 drivers/gpu/drm/i915/display/intel_bw.c | 187 ++-- drivers/gpu/drm/i915/display/intel_bw.h | 24 + drivers/gpu/drm/i915/display/intel_display.c | 21 +- .../drm/i915/display/intel_display_types.h| 6 + drivers/gpu/drm/i915/i915_reg.h | 5 + drivers/gpu/drm/i915/intel_pm.c | 421 -- drivers/gpu/drm/i915/intel_pm.h | 8 +- drivers/gpu/drm/i915/intel_sideband.c | 2 + 8 files changed, 565 insertions(+), 109 deletions(-) -- 2.24.1.485.gad05a3d8e5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v24 02/11] drm/i915: Add intel_atomic_get_bw_*_state helpers
Add correspondent helpers to be able to get old/new bandwidth
global state object.
v2: - Fixed typo in function call
v3: - Changed new functions naming to use convention proposed
by Jani Nikula, i.e intel_bw_* in intel_bw.c file.
v4: - Change function naming back to intel_atomic* pattern,
was decided to rename in a separate patch series.
v5: - Fix function naming to match existing practices(Ville)
v6: - Removed spurious whitespace
v7: - Removed bw_state NULL checks(Ville)
Reviewed-by: Ville Syrjälä
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 24 +++-
drivers/gpu/drm/i915/display/intel_bw.h | 9 +
2 files changed, 32 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index 88f367eb28ea..4aa54fcb0629 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -375,7 +375,29 @@ static unsigned int intel_bw_data_rate(struct
drm_i915_private *dev_priv,
return data_rate;
}
-static struct intel_bw_state *
+struct intel_bw_state *
+intel_atomic_get_old_bw_state(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_global_state *bw_state;
+
+ bw_state = intel_atomic_get_old_global_obj_state(state,
_priv->bw_obj);
+
+ return to_intel_bw_state(bw_state);
+}
+
+struct intel_bw_state *
+intel_atomic_get_new_bw_state(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_global_state *bw_state;
+
+ bw_state = intel_atomic_get_new_global_obj_state(state,
_priv->bw_obj);
+
+ return to_intel_bw_state(bw_state);
+}
+
+struct intel_bw_state *
intel_atomic_get_bw_state(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h
b/drivers/gpu/drm/i915/display/intel_bw.h
index a8aa7624c5aa..ac004d6f4276 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -24,6 +24,15 @@ struct intel_bw_state {
#define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)
+struct intel_bw_state *
+intel_atomic_get_old_bw_state(struct intel_atomic_state *state);
+
+struct intel_bw_state *
+intel_atomic_get_new_bw_state(struct intel_atomic_state *state);
+
+struct intel_bw_state *
+intel_atomic_get_bw_state(struct intel_atomic_state *state);
+
void intel_bw_init_hw(struct drm_i915_private *dev_priv);
int intel_bw_init(struct drm_i915_private *dev_priv);
int intel_bw_atomic_check(struct intel_atomic_state *state);
--
2.24.1.485.gad05a3d8e5
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v24 11/11] drm/i915: Enable SAGV support for Gen12
Flip the switch and enable SAGV support
for Gen12 also.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/intel_pm.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1ab466e4a0c6..dfe511ab2d3b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3638,10 +3638,6 @@ static bool skl_needs_memory_bw_wa(struct
drm_i915_private *dev_priv)
bool
intel_has_sagv(struct drm_i915_private *dev_priv)
{
- /* HACK! */
- if (IS_GEN(dev_priv, 12))
- return false;
-
return (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) &&
dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
}
--
2.24.1.485.gad05a3d8e5
___
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[Intel-gfx] [PATCH v24 09/11] drm/i915: Rename bw_state to new_bw_state
That is a preparation patch before next one where we
introduce old_bw_state and a bunch of other changes
as well.
In a review comment it was suggested to split out
at least that renaming into a separate patch, what
is done here.
v2: Removed spurious space
Reviewed-by: Ville Syrjälä
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index 4aa54fcb0629..6e7cc3a4f1aa 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -414,7 +414,7 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc_state *new_crtc_state, *old_crtc_state;
- struct intel_bw_state *bw_state = NULL;
+ struct intel_bw_state *new_bw_state = NULL;
unsigned int data_rate, max_data_rate;
unsigned int num_active_planes;
struct intel_crtc *crtc;
@@ -443,29 +443,29 @@ int intel_bw_atomic_check(struct intel_atomic_state
*state)
old_active_planes == new_active_planes)
continue;
- bw_state = intel_atomic_get_bw_state(state);
- if (IS_ERR(bw_state))
- return PTR_ERR(bw_state);
+ new_bw_state = intel_atomic_get_bw_state(state);
+ if (IS_ERR(new_bw_state))
+ return PTR_ERR(new_bw_state);
- bw_state->data_rate[crtc->pipe] = new_data_rate;
- bw_state->num_active_planes[crtc->pipe] = new_active_planes;
+ new_bw_state->data_rate[crtc->pipe] = new_data_rate;
+ new_bw_state->num_active_planes[crtc->pipe] = new_active_planes;
drm_dbg_kms(_priv->drm,
"pipe %c data rate %u num active planes %u\n",
pipe_name(crtc->pipe),
- bw_state->data_rate[crtc->pipe],
- bw_state->num_active_planes[crtc->pipe]);
+ new_bw_state->data_rate[crtc->pipe],
+ new_bw_state->num_active_planes[crtc->pipe]);
}
- if (!bw_state)
+ if (!new_bw_state)
return 0;
- ret = intel_atomic_lock_global_state(_state->base);
+ ret = intel_atomic_lock_global_state(_bw_state->base);
if (ret)
return ret;
- data_rate = intel_bw_data_rate(dev_priv, bw_state);
- num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state);
+ data_rate = intel_bw_data_rate(dev_priv, new_bw_state);
+ num_active_planes = intel_bw_num_active_planes(dev_priv, new_bw_state);
max_data_rate = intel_max_data_rate(dev_priv, num_active_planes);
--
2.24.1.485.gad05a3d8e5
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v24 10/11] drm/i915: Restrict qgv points which don't have enough bandwidth.
According to BSpec 53998, we should try to restrict qgv points, which can't provide enough bandwidth for desired display configuration. Currently we are just comparing against all of those and take minimum(worst case). v2: Fixed wrong PCode reply mask, removed hardcoded values. v3: Forbid simultaneous legacy SAGV PCode requests and restricting qgv points. Put the actual restriction to commit function, added serialization(thanks to Ville) to prevent commit being applied out of order in case of nonblocking and/or nomodeset commits. v4: - Minor code refactoring, fixed few typos(thanks to James Ausmus) - Change the naming of qgv point masking/unmasking functions(James Ausmus). - Simplify the masking/unmasking operation itself, as we don't need to mask only single point per request(James Ausmus) - Reject and stick to highest bandwidth point if SAGV can't be enabled(BSpec) v5: - Add new mailbox reply codes, which seems to happen during boot time for TGL and indicate that QGV setting is not yet available. v6: - Increase number of supported QGV points to be in sync with BSpec. v7: - Rebased and resolved conflict to fix build failure. - Fix NUM_QGV_POINTS to 8 and moved that to header file(James Ausmus) v8: - Don't report an error if we can't restrict qgv points, as SAGV can be disabled by BIOS, which is completely legal. So don't make CI panic. Instead if we detect that there is only 1 QGV point accessible just analyze if we can fit the required bandwidth requirements, but no need in restricting. v9: - Fix wrong QGV transition if we have 0 planes and no SAGV simultaneously. v10: - Fix CDCLK corruption, because of global state getting serialized without modeset, which caused copying of non-calculated cdclk to be copied to dev_priv(thanks to Ville for the hint). v11: - Remove unneeded headers and spaces(Matthew Roper) - Remove unneeded intel_qgv_info qi struct from bw check and zero out the needed one(Matthew Roper) - Changed QGV error message to have more clear meaning(Matthew Roper) - Use state->modeset_set instead of any_ms(Matthew Roper) - Moved NUM_SAGV_POINTS from i915_reg.h to i915_drv.h where it's used - Keep using crtc_state->hw.active instead of .enable(Matthew Roper) - Moved unrelated changes to other patch(using latency as parameter for plane wm calculation, moved to SAGV refactoring patch) v12: - Fix rebase conflict with own temporary SAGV/QGV fix. - Remove unnecessary mask being zero check when unmasking qgv points as this is completely legal(Matt Roper) - Check if we are setting the same mask as already being set in hardware to prevent error from PCode. - Fix error message when restricting/unrestricting qgv points to "mask/unmask" which sounds more accurate(Matt Roper) - Move sagv status setting to icl_get_bw_info from atomic check as this should be calculated only once.(Matt Roper) - Edited comments for the case when we can't enable SAGV and use only 1 QGV point with highest bandwidth to be more understandable.(Matt Roper) v13: - Moved max_data_rate in bw check to closer scope(Ville Syrjälä) - Changed comment for zero new_mask in qgv points masking function to better reflect reality(Ville Syrjälä) - Simplified bit mask operation in qgv points masking function (Ville Syrjälä) - Moved intel_qgv_points_mask closer to gen11 SAGV disabling, however this still can't be under modeset condition(Ville Syrjälä) - Packed qgv_points_mask as u8 and moved closer to pipe_sagv_mask (Ville Syrjälä) - Extracted PCode changes to separate patch.(Ville Syrjälä) - Now treat num_planes 0 same as 1 to avoid confusion and returning max_bw as 0, which would prevent choosing QGV point having max bandwidth in case if SAGV is not allowed, as per BSpec(Ville Syrjälä) - Do the actual qgv_points_mask swap in the same place as all other global state parts like cdclk are swapped. In the next patch, this all will be moved to bw state as global state, once new global state patch series from Ville lands v14: - Now using global state to serialize access to qgv points - Added global state locking back, otherwise we seem to read bw state in a wrong way. v15: - Added TODO comment for near atomic global state locking in bw code. v16: - Fixed intel_atomic_bw_* functions to be intel_bw_* as discussed with Jani Nikula. - Take bw_state_changed flag into use. v17: - Moved qgv point related manipulations next to SAGV code, as those are semantically related(Ville Syrjälä) - Renamed those into intel_sagv_(pre)|(post)_plane_update (Ville Syrjälä) v18: - Move sagv related calls from commit tail into intel_sagv_(pre)|(post)_plane_update(Ville
[Intel-gfx] [PATCH v24 07/11] drm/i915: Add TGL+ SAGV support
Starting from TGL we need to have a separate wm0
values for SAGV and non-SAGV which affects
how calculations are done.
v2: Remove long lines
v3: Removed COLOR_PLANE enum references
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_display.c | 8 +-
.../drm/i915/display/intel_display_types.h| 3 +
drivers/gpu/drm/i915/intel_pm.c | 128 +-
3 files changed, 130 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index ac7f600c84ca..a591e35d9ac4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13932,7 +13932,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
/* Watermarks */
for (level = 0; level <= max_level; level++) {
if (skl_wm_level_equals(_plane_wm->wm[level],
- _plane_wm->wm[level]))
+ _plane_wm->wm[level]) ||
+ (level == 0 &&
skl_wm_level_equals(_plane_wm->wm[level],
+
_plane_wm->sagv_wm0)))
continue;
drm_err(_priv->drm,
@@ -13987,7 +13989,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
/* Watermarks */
for (level = 0; level <= max_level; level++) {
if (skl_wm_level_equals(_plane_wm->wm[level],
- _plane_wm->wm[level]))
+ _plane_wm->wm[level]) ||
+ (level == 0 &&
skl_wm_level_equals(_plane_wm->wm[level],
+
_plane_wm->sagv_wm0)))
continue;
drm_err(_priv->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index ba8c08145c88..23a425e565a8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -688,11 +688,14 @@ struct skl_plane_wm {
struct skl_wm_level wm[8];
struct skl_wm_level uv_wm[8];
struct skl_wm_level trans_wm;
+ struct skl_wm_level sagv_wm0;
+ struct skl_wm_level uv_sagv_wm0;
bool is_planar;
};
struct skl_pipe_wm {
struct skl_plane_wm planes[I915_MAX_PLANES];
+ bool can_sagv;
};
enum vlv_wm_level {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3c682684807b..7d629489a325 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3874,6 +3874,9 @@ static bool icl_crtc_can_enable_sagv(const struct
intel_crtc_state *crtc_state)
return intel_crtc_can_enable_sagv(crtc_state);
}
+static bool
+tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state);
+
bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
{
return bw_state->pipe_sagv_reject == 0;
@@ -3884,7 +3887,7 @@ static int intel_compute_sagv_mask(struct
intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
int ret;
struct intel_crtc *crtc;
- const struct intel_crtc_state *new_crtc_state;
+ struct intel_crtc_state *new_crtc_state;
struct intel_bw_state *new_bw_state = NULL;
const struct intel_bw_state *old_bw_state = NULL;
int i;
@@ -3899,7 +3902,9 @@ static int intel_compute_sagv_mask(struct
intel_atomic_state *state)
old_bw_state = intel_atomic_get_old_bw_state(state);
- if (INTEL_GEN(dev_priv) >= 11)
+ if (INTEL_GEN(dev_priv) >= 12)
+ can_sagv = tgl_crtc_can_enable_sagv(new_crtc_state);
+ else if (INTEL_GEN(dev_priv) >= 11)
can_sagv = icl_crtc_can_enable_sagv(new_crtc_state);
else
can_sagv = skl_crtc_can_enable_sagv(new_crtc_state);
@@ -3913,6 +3918,24 @@ static int intel_compute_sagv_mask(struct
intel_atomic_state *state)
if (!old_bw_state)
return 0;
+ for_each_new_intel_crtc_in_state(state, crtc,
+new_crtc_state, i) {
+ struct skl_pipe_wm *pipe_wm = _crtc_state->wm.skl.optimal;
+
+ /*
+* Due to drm limitation at commit state, when
+* changes are written the whole atomic state is
+* zeroed away => which prevents from using it,
+* so just sticking it into pipe wm state for
+* keeping it simple - anyway this is related to wm.
+* Proper way in ideal universe would be of course not
+
[Intel-gfx] [PATCH v24 05/11] drm/i915: Use bw state for per crtc SAGV evaluation
Future platforms require per-crtc SAGV evaluation
and serializing global state when those are changed
from different commits.
v2: - Add has_sagv check to intel_crtc_can_enable_sagv
so that it sets bit in reject mask.
- Use bw_state in intel_pre/post_plane_enable_sagv
instead of atomic state
v3: - Fixed rebase conflict, now using
intel_atomic_crtc_state_for_each_plane_state in
order to call it from atomic check
Signed-off-by: Stanislav Lisovskiy
Cc: Ville Syrjälä
Cc: James Ausmus
---
drivers/gpu/drm/i915/display/intel_bw.h | 6 ++
drivers/gpu/drm/i915/intel_pm.c | 115 ++--
drivers/gpu/drm/i915/intel_pm.h | 4 +-
3 files changed, 95 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h
b/drivers/gpu/drm/i915/display/intel_bw.h
index ac004d6f4276..d6df91058223 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -18,6 +18,12 @@ struct intel_crtc_state;
struct intel_bw_state {
struct intel_global_state base;
+ /*
+* Contains a bit mask, used to determine, whether correspondent
+* pipe allows SAGV or not.
+*/
+ u8 pipe_sagv_reject;
+
unsigned int data_rate[I915_MAX_PIPES];
u8 num_active_planes[I915_MAX_PIPES];
};
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 83a0aac31aa8..65fd5a3571e4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -43,6 +43,7 @@
#include "i915_fixed.h"
#include "i915_irq.h"
#include "i915_trace.h"
+#include "display/intel_bw.h"
#include "intel_pm.h"
#include "intel_sideband.h"
#include "../../../platform/x86/intel_ips.h"
@@ -3634,7 +3635,7 @@ static bool skl_needs_memory_bw_wa(struct
drm_i915_private *dev_priv)
return IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv);
}
-static bool
+bool
intel_has_sagv(struct drm_i915_private *dev_priv)
{
/* HACK! */
@@ -3760,35 +3761,78 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ const struct intel_bw_state *new_bw_state = NULL;
- if (!intel_can_enable_sagv(state))
+ /*
+* Just return if we can't control SAGV or don't have it.
+* This is different from situation when we have SAGV but just can't
+* afford it due to DBuf limitation - in case if SAGV is completely
+* disabled in a BIOS, we are not even allowed to send a PCode request,
+* as it will throw an error. So have to check it here.
+*/
+ if (!intel_has_sagv(dev_priv))
+ return;
+
+ new_bw_state = intel_atomic_get_new_bw_state(state);
+ if (!new_bw_state)
+ return;
+
+ if (!intel_can_enable_sagv(new_bw_state))
intel_disable_sagv(dev_priv);
}
void intel_sagv_post_plane_update(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ const struct intel_bw_state *new_bw_state = NULL;
- if (intel_can_enable_sagv(state))
+ /*
+* Just return if we can't control SAGV or don't have it.
+* This is different from situation when we have SAGV but just can't
+* afford it due to DBuf limitation - in case if SAGV is completely
+* disabled in a BIOS, we are not even allowed to send a PCode request,
+* as it will throw an error. So have to check it here.
+*/
+ if (!intel_has_sagv(dev_priv))
+ return;
+
+ new_bw_state = intel_atomic_get_new_bw_state(state);
+ if (!new_bw_state)
+ return;
+
+ if (intel_can_enable_sagv(new_bw_state))
intel_enable_sagv(dev_priv);
}
static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state
*crtc_state)
{
- struct drm_device *dev = crtc_state->uapi.crtc->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_atomic_state *state =
to_intel_atomic_state(crtc_state->uapi.state);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct intel_plane *plane;
const struct intel_plane_state *plane_state;
int level, latency;
+ if (!intel_has_sagv(dev_priv))
+ return false;
+
if (!crtc_state->hw.active)
return true;
- if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
+ /*
+* SKL+ workaround: bspec recommends we disable SAGV when we have
+* more then one pipe enabled
+*/
+ if (hweight8(state->active_pipes) > 1)
return false;
- for_each_intel_plane_on_crtc(dev, crtc, plane) {
+ if
[Intel-gfx] [PATCH v24 08/11] drm/i915: Added required new PCode commands
We need a new PCode request commands and reply codes
to be added as a prepartion patch for QGV points
restricting for new SAGV support.
v2: - Extracted those changes into separate patch
(Ville Syrjälä)
v3: - Moved new PCode masks to another place from
PCode commands(Ville)
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/i915_reg.h | 5 +
drivers/gpu/drm/i915/intel_sideband.c | 2 ++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0b39b9abf8a4..a3cdb22826d9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9085,6 +9085,7 @@ enum {
#define GEN7_PCODE_ILLEGAL_DATA0x3
#define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4
#define GEN11_PCODE_LOCKED 0x6
+#define GEN11_PCODE_REJECTED 0x11
#define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
#define GEN6_PCODE_WRITE_RC6VIDS 0x4
#define GEN6_PCODE_READ_RC6VIDS 0x5
@@ -9106,6 +9107,7 @@ enum {
#define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
#define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
#define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point)(((point) <<
16) | (0x1 << 8))
+#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
#define GEN6_PCODE_READ_D_COMP 0x10
#define GEN6_PCODE_WRITE_D_COMP 0x11
#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
@@ -9134,6 +9136,9 @@ enum {
#define GEN8_GT_SLICE_INFO _MMIO(0x138064)
#define GEN8_LSLICESTAT_MASK 0x7
+#define GEN11_PCODE_POINTS_RESTRICTED 0x0
+#define GEN11_PCODE_POINTS_RESTRICTED_MASK 0x1
+
#define CHV_POWER_SS0_SIG1 _MMIO(0xa720)
#define CHV_POWER_SS1_SIG1 _MMIO(0xa728)
#define CHV_SS_PG_ENABLE (1 << 1)
diff --git a/drivers/gpu/drm/i915/intel_sideband.c
b/drivers/gpu/drm/i915/intel_sideband.c
index 3f13baaef058..b01f15017ae4 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -371,6 +371,8 @@ static inline int gen7_check_mailbox_status(u32 mbox)
return -ENXIO;
case GEN11_PCODE_LOCKED:
return -EBUSY;
+ case GEN11_PCODE_REJECTED:
+ return -EACCES;
case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
return -EOVERFLOW;
default:
--
2.24.1.485.gad05a3d8e5
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v24 03/11] drm/i915: Prepare to extract gen specific functions from intel_can_enable_sagv
Addressing one of the comments, recommending to extract platform
specific code from intel_can_enable_sagv as a preparation, before
we are going to add support for tgl+.
v2: - Removed whitespace
v3: - Removed premature debug and new cycle introduction(Ville)
- Added missing no active pipes check(Ville)
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/intel_pm.c | 64 +++--
1 file changed, 38 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bd57f0bb8a54..a0958f40e161 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3757,42 +3757,23 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
return 0;
}
-bool intel_can_enable_sagv(struct intel_atomic_state *state)
+static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state
*crtc_state)
{
- struct drm_device *dev = state->base.dev;
+ struct drm_device *dev = crtc_state->uapi.crtc->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_crtc *crtc;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct intel_plane *plane;
- struct intel_crtc_state *crtc_state;
- enum pipe pipe;
+ const struct intel_plane_state *plane_state;
int level, latency;
- if (!intel_has_sagv(dev_priv))
- return false;
-
- /*
-* If there are no active CRTCs, no additional checks need be performed
-*/
- if (hweight8(state->active_pipes) == 0)
+ if (!crtc_state->hw.active)
return true;
- /*
-* SKL+ workaround: bspec recommends we disable SAGV when we have
-* more then one pipe enabled
-*/
- if (hweight8(state->active_pipes) > 1)
- return false;
-
- /* Since we're now guaranteed to only have one active CRTC... */
- pipe = ffs(state->active_pipes) - 1;
- crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
- crtc_state = to_intel_crtc_state(crtc->base.state);
-
if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
return false;
for_each_intel_plane_on_crtc(dev, crtc, plane) {
- struct skl_plane_wm *wm =
+ const struct skl_plane_wm *wm =
_state->wm.skl.optimal.planes[plane->id];
/* Skip this plane if it's not enabled */
@@ -3807,7 +3788,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state
*state)
latency = dev_priv->wm.skl_latency[level];
if (skl_needs_memory_bw_wa(dev_priv) &&
- plane->base.state->fb->modifier ==
+ plane_state->uapi.fb->modifier ==
I915_FORMAT_MOD_X_TILED)
latency += 15;
@@ -3823,6 +3804,37 @@ bool intel_can_enable_sagv(struct intel_atomic_state
*state)
return true;
}
+bool intel_can_enable_sagv(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc *crtc;
+ const struct intel_crtc_state *crtc_state;
+ enum pipe pipe;
+
+ if (!intel_has_sagv(dev_priv))
+ return false;
+
+ /*
+* If there are no active CRTCs, no additional checks need be performed
+*/
+ if (hweight8(state->active_pipes) == 0)
+ return true;
+
+ /*
+* SKL+ workaround: bspec recommends we disable SAGV when we have
+* more then one pipe enabled
+*/
+ if (hweight8(state->active_pipes) > 1)
+ return false;
+
+ /* Since we're now guaranteed to only have one active CRTC... */
+ pipe = ffs(state->active_pipes) - 1;
+ crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
+ crtc_state = to_intel_crtc_state(crtc->base.state);
+
+ return intel_crtc_can_enable_sagv(crtc_state);
+}
+
/*
* Calculate initial DBuf slice offset, based on slice size
* and mask(i.e if slice size is 1024 and second slice is enabled
--
2.24.1.485.gad05a3d8e5
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v24 06/11] drm/i915: Separate icl and skl SAGV checking
Introduce platform dependent SAGV checking in
combination with bandwidth state pipe SAGV mask.
v2, v3: Fix rebase conflict
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/intel_pm.c | 38 -
1 file changed, 28 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 65fd5a3571e4..3c682684807b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3806,7 +3806,6 @@ void intel_sagv_post_plane_update(struct
intel_atomic_state *state)
static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state
*crtc_state)
{
- struct intel_atomic_state *state =
to_intel_atomic_state(crtc_state->uapi.state);
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct intel_plane *plane;
@@ -3819,13 +3818,6 @@ static bool intel_crtc_can_enable_sagv(const struct
intel_crtc_state *crtc_state
if (!crtc_state->hw.active)
return true;
- /*
-* SKL+ workaround: bspec recommends we disable SAGV when we have
-* more then one pipe enabled
-*/
- if (hweight8(state->active_pipes) > 1)
- return false;
-
if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
DRM_DEBUG_KMS("No SAGV for interlaced mode on pipe %c\n",
pipe_name(crtc->pipe));
@@ -3864,6 +3856,24 @@ static bool intel_crtc_can_enable_sagv(const struct
intel_crtc_state *crtc_state
return true;
}
+static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_atomic_state *state =
to_intel_atomic_state(crtc_state->uapi.state);
+ /*
+* SKL+ workaround: bspec recommends we disable SAGV when we have
+* more then one pipe enabled
+*/
+ if (hweight8(state->active_pipes) > 1)
+ return false;
+
+ return intel_crtc_can_enable_sagv(crtc_state);
+}
+
+static bool icl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
+{
+ return intel_crtc_can_enable_sagv(crtc_state);
+}
+
bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
{
return bw_state->pipe_sagv_reject == 0;
@@ -3871,22 +3881,30 @@ bool intel_can_enable_sagv(const struct intel_bw_state
*bw_state)
static int intel_compute_sagv_mask(struct intel_atomic_state *state)
{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
int ret;
struct intel_crtc *crtc;
- struct intel_crtc_state *new_crtc_state;
+ const struct intel_crtc_state *new_crtc_state;
struct intel_bw_state *new_bw_state = NULL;
const struct intel_bw_state *old_bw_state = NULL;
int i;
for_each_new_intel_crtc_in_state(state, crtc,
new_crtc_state, i) {
+ bool can_sagv;
+
new_bw_state = intel_atomic_get_bw_state(state);
if (IS_ERR(new_bw_state))
return PTR_ERR(new_bw_state);
old_bw_state = intel_atomic_get_old_bw_state(state);
- if (intel_crtc_can_enable_sagv(new_crtc_state))
+ if (INTEL_GEN(dev_priv) >= 11)
+ can_sagv = icl_crtc_can_enable_sagv(new_crtc_state);
+ else
+ can_sagv = skl_crtc_can_enable_sagv(new_crtc_state);
+
+ if (can_sagv)
new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
else
new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
--
2.24.1.485.gad05a3d8e5
___
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[Intel-gfx] [PATCH v24 01/11] drm/i915: Introduce skl_plane_wm_level accessor.
For future Gen12 SAGV implementation we need to
seemlessly alter wm levels calculated, depending
on whether we are allowed to enable SAGV or not.
So this accessor will give additional flexibility
to do that.
Currently this accessor is still simply working
as "pass-through" function. This will be changed
in next coming patches from this series.
v2: - plane_id -> plane->id(Ville Syrjälä)
- Moved wm_level var to have more local scope
(Ville Syrjälä)
- Renamed yuv to color_plane(Ville Syrjälä) in
skl_plane_wm_level
v3: - plane->id -> plane_id(this time for real, Ville Syrjälä)
- Changed colorplane id type from boolean to int as index
(Ville Syrjälä)
- Moved crtc_state param so that it is first now
(Ville Syrjälä)
- Moved wm_level declaration to tigher scope in
skl_write_plane_wm(Ville Syrjälä)
v4: - Started to use enum values for color plane
- Do sizeof for a type what we are memset'ing
- Zero out wm_uv as well(Ville Syrjälä)
v5: - Fixed rebase conflict caused by COLOR_PLANE_*
enum removal
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/intel_pm.c | 85 ++---
1 file changed, 67 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b632b6bb9c3e..bd57f0bb8a54 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4547,6 +4547,18 @@ icl_get_total_relative_data_rate(struct intel_crtc_state
*crtc_state,
return total_data_rate;
}
+static const struct skl_wm_level *
+skl_plane_wm_level(const struct intel_crtc_state *crtc_state,
+ enum plane_id plane_id,
+ int level,
+ int color_plane)
+{
+ const struct skl_plane_wm *wm =
+ _state->wm.skl.optimal.planes[plane_id];
+
+ return color_plane == 0 ? >wm[level] : >uv_wm[level];
+}
+
static int
skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
{
@@ -4606,22 +4618,28 @@ skl_allocate_pipe_ddb(struct intel_crtc_state
*crtc_state)
*/
for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) {
blocks = 0;
+
for_each_plane_id_on_crtc(crtc, plane_id) {
- const struct skl_plane_wm *wm =
- _state->wm.skl.optimal.planes[plane_id];
+ const struct skl_wm_level *wm_level;
+ const struct skl_wm_level *wm_uv_level;
+
+ wm_level = skl_plane_wm_level(crtc_state, plane_id,
+ level, 0);
+ wm_uv_level = skl_plane_wm_level(crtc_state, plane_id,
+level, 1);
if (plane_id == PLANE_CURSOR) {
- if (wm->wm[level].min_ddb_alloc >
total[PLANE_CURSOR]) {
+ if (wm_level->min_ddb_alloc >
total[PLANE_CURSOR]) {
drm_WARN_ON(_priv->drm,
- wm->wm[level].min_ddb_alloc
!= U16_MAX);
+ wm_level->min_ddb_alloc !=
U16_MAX);
blocks = U32_MAX;
break;
}
continue;
}
- blocks += wm->wm[level].min_ddb_alloc;
- blocks += wm->uv_wm[level].min_ddb_alloc;
+ blocks += wm_level->min_ddb_alloc;
+ blocks += wm_uv_level->min_ddb_alloc;
}
if (blocks <= alloc_size) {
@@ -4644,11 +4662,16 @@ skl_allocate_pipe_ddb(struct intel_crtc_state
*crtc_state)
* proportional to its relative data rate.
*/
for_each_plane_id_on_crtc(crtc, plane_id) {
- const struct skl_plane_wm *wm =
- _state->wm.skl.optimal.planes[plane_id];
+ const struct skl_wm_level *wm_level;
+ const struct skl_wm_level *wm_uv_level;
u64 rate;
u16 extra;
+ wm_level = skl_plane_wm_level(crtc_state, plane_id,
+ level, 0);
+ wm_uv_level = skl_plane_wm_level(crtc_state, plane_id,
+level, 1);
+
if (plane_id == PLANE_CURSOR)
continue;
@@ -4663,7 +4686,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
extra = min_t(u16, alloc_size,
DIV64_U64_ROUND_UP(alloc_size * rate,
total_data_rate));
- total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
+
[Intel-gfx] [PATCH i-g-t] lib: Use read() for timerfd timeout detection
The poll() is proving unreliable, where our tests timeout without the
spinner being terminated. Let's try a blocking read instead!
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1676
Signed-off-by: Chris Wilson
Cc: "Dixit, Ashutosh"
---
lib/igt_dummyload.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
index 99ca84ad8..ae0fb9378 100644
--- a/lib/igt_dummyload.c
+++ b/lib/igt_dummyload.c
@@ -399,14 +399,14 @@ igt_spin_factory(int fd, const struct igt_spin_factory
*opts)
static void *timer_thread(void *data)
{
igt_spin_t *spin = data;
- struct pollfd pfd = {
- .fd = spin->timerfd,
- .events = POLLIN,
- };
+ uint64_t overruns = 0;
- if (poll(, 1, -1) >= 0)
- igt_spin_end(spin);
+ /* Wait until we see the timer fire, or we get cancelled */
+ do {
+ read(spin->timerfd, , sizeof(overruns));
+ } while (!overruns);
+ igt_spin_end(spin);
return NULL;
}
--
2.26.0
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Exercise basic RPS interrupt generation (rev5)
== Series Details == Series: drm/i915/selftests: Exercise basic RPS interrupt generation (rev5) URL : https://patchwork.freedesktop.org/series/75966/ State : warning == Summary == $ dim checkpatch origin/drm-tip ff4a038bdd9a drm/i915/selftests: Exercise basic RPS interrupt generation -:46: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #46: new file mode 100644 -:233: CHECK:LINE_SPACING: Please don't use multiple blank lines #233: FILE: drivers/gpu/drm/i915/gt/selftest_rps.c:183: + + total: 0 errors, 1 warnings, 1 checks, 252 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/icl: Update forcewake firmware ranges
Hi Matt,
> -Original Message-
> From: Roper, Matthew D
> Sent: Tuesday, April 14, 2020 11:40 AM
> To: Sripada, Radhakrishna
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/i915/icl: Update forcewake firmware ranges
>
> On Mon, Apr 13, 2020 at 02:00:03AM -0700, Radhakrishna Sripada wrote:
> > Some workarounds are not sticking across suspend resume cycles. The
> > forcewake ranges table has been updated and would reflect the hardware
> > appropriately.
> >
> > Closes: https://gitlab.freedesktop.org/drm/intel/issues/1222
>
> It's unfortunate that they still haven't updated the bspec for this yet.
> A few comments below based on my understanding of the document we
> received from the hardware team.
>
> >
> > Cc: Matt Roper
> > Signed-off-by: Radhakrishna Sripada
> > ---
> > drivers/gpu/drm/i915/intel_uncore.c | 55
> > +
> > 1 file changed, 41 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_uncore.c
> > b/drivers/gpu/drm/i915/intel_uncore.c
> > index fa86b7ab2d99..c0e21697a44c 100644
> > --- a/drivers/gpu/drm/i915/intel_uncore.c
> > +++ b/drivers/gpu/drm/i915/intel_uncore.c
> > @@ -1098,32 +1098,59 @@ static const struct intel_forcewake_range
> > __gen11_fw_ranges[] = {
>
> Looks like the first range in this table (0x0 - 0xaff) needs to be changed to
> '0' (or
> rather combined with the following entry for a combined 0x0 - 0x1fff range set
> to '0')
Comparing with previous gens, my understanding is the '0' is indicative of
uncore range
Of registers. The reserved ranges are marked with "Blitter" force wake range.
Am I in the right
Path making that assumption? Hence made all the subsequent changes according to
the assumption.
Thanks,
Radhakrishna(RK) Sripada
>
>
> > GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
> > GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
> > GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
> > - GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
> > + GEN_FW_RANGE(0x5200, 0x53ff, FORCEWAKE_RENDER),
> > + GEN_FW_RANGE(0x5400, 0x54ff, FORCEWAKE_BLITTER),
>
> In the version of the document I'm looking at, the wake target for this entry
> is
> blank, which usually means no wake target is required. AFAICS, no registers
> actually fall in this range on gen11, so I'd either set this to '0' to
> explicitly match
> the document, or just leave it combined with the two surrounding render ranges
> for simplicity (and smaller table size).
>
> > + GEN_FW_RANGE(0x5500, 0x7fff, FORCEWAKE_RENDER),
> > GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_BLITTER),
> > GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
> > GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
> > GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
> > - GEN_FW_RANGE(0x8500, 0x8bff, FORCEWAKE_BLITTER),
> > + GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_BLITTER),
> > + GEN_FW_RANGE(0x8800, 0x883f, 0),
> > + GEN_FW_RANGE(0x8840, 0x8bff, FORCEWAKE_BLITTER),
>
> I see 0x8840 - 0x8bff as a reserved range with no forcewake target so we
> should
> be able to combine it with the range before it.
>
> > GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
> > - GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
> > - GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_ALL),
> > - GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
> > + GEN_FW_RANGE(0x8d00, 0x94cf, FORCEWAKE_BLITTER),
> > + GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER),
> > + GEN_FW_RANGE(0x9560, 0x95ff, 0),
> > + GEN_FW_RANGE(0x9600, 0xafff, FORCEWAKE_BLITTER),
> > GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
> > GEN_FW_RANGE(0xb480, 0xdeff, FORCEWAKE_BLITTER),
> > GEN_FW_RANGE(0xdf00, 0xe8ff, FORCEWAKE_RENDER),
> > GEN_FW_RANGE(0xe900, 0x16dff, FORCEWAKE_BLITTER),
> > GEN_FW_RANGE(0x16e00, 0x19fff, FORCEWAKE_RENDER),
> > - GEN_FW_RANGE(0x1a000, 0x243ff, FORCEWAKE_BLITTER),
> > - GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
> > - GEN_FW_RANGE(0x24800, 0x3, FORCEWAKE_BLITTER),
> > + GEN_FW_RANGE(0x1a000, 0x23fff, FORCEWAKE_BLITTER),
> > + GEN_FW_RANGE(0x24000, 0x2407f, 0),
> > + GEN_FW_RANGE(0x24080, 0x2417f, FORCEWAKE_BLITTER),
> > + GEN_FW_RANGE(0x24180, 0x242ff, FORCEWAKE_RENDER),
> > + GEN_FW_RANGE(0x24300, 0x243ff, FORCEWAKE_BLITTER),
> > + GEN_FW_RANGE(0x24400, 0x245ff, FORCEWAKE_RENDER),
> > + GEN_FW_RANGE(0x24600, 0x2467f, FORCEWAKE_BLITTER),
>
> This one is a reserved range with no registers, so we can just squash it into
> the
> two render ranges on either side of it.
>
> > + GEN_FW_RANGE(0x24680, 0x247ff, FORCEWAKE_RENDER),
> > + GEN_FW_RANGE(0x24800, 0x249ff, FORCEWAKE_BLITTER),
>
> Also reserved with no registers.
>
> > + GEN_FW_RANGE(0x24a00, 0x24a7f, FORCEWAKE_RENDER),
> > + GEN_FW_RANGE(0x24a80, 0x24dff, FORCEWAKE_BLITTER),
>
> Also reserved with no registers.
>
> So I think we should be able to have just use one render range that runs from
> 0x24400 - 0x24fff.
>
> >
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v4,1/3] drm/dp: DRM DP helper for reading Ignore MSA from DPCD
== Series Details == Series: series starting with [v4,1/3] drm/dp: DRM DP helper for reading Ignore MSA from DPCD URL : https://patchwork.freedesktop.org/series/75899/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8298_full -> Patchwork_17293_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_17293_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17293_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_17293_full: ### IGT changes ### Possible regressions * igt@perf_pmu@cpu-hotplug: - shard-tglb: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17293/shard-tglb8/igt@perf_...@cpu-hotplug.html Known issues Here are the changes found in Patchwork_17293_full that come from known issues: ### IGT changes ### Issues hit * igt@i915_pm_rc6_residency@rc6-idle: - shard-snb: [PASS][2] -> [FAIL][3] ([i915#1066]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-snb2/igt@i915_pm_rc6_reside...@rc6-idle.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17293/shard-snb6/igt@i915_pm_rc6_reside...@rc6-idle.html * igt@i915_pm_rpm@basic-rte: - shard-glk: [PASS][4] -> [INCOMPLETE][5] ([i915#58] / [k.org#198133]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-glk6/igt@i915_pm_...@basic-rte.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17293/shard-glk1/igt@i915_pm_...@basic-rte.html * igt@kms_flip@plain-flip-fb-recreate-interruptible: - shard-skl: [PASS][6] -> [FAIL][7] ([i915#34]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-skl10/igt@kms_f...@plain-flip-fb-recreate-interruptible.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17293/shard-skl7/igt@kms_f...@plain-flip-fb-recreate-interruptible.html * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt: - shard-tglb: [PASS][8] -> [SKIP][9] ([i915#668]) +7 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-tglb2/igt@kms_frontbuffer_track...@psr-1p-offscren-pri-shrfb-draw-blt.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17293/shard-tglb6/igt@kms_frontbuffer_track...@psr-1p-offscren-pri-shrfb-draw-blt.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - shard-apl: [PASS][10] -> [DMESG-WARN][11] ([i915#180]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-apl4/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-b.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17293/shard-apl2/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-b.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-kbl: [PASS][12] -> [DMESG-WARN][13] ([i915#180] / [i915#93] / [i915#95]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-kbl3/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17293/shard-kbl4/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][14] -> [FAIL][15] ([fdo#108145] / [i915#265]) +1 similar issue [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-skl3/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17293/shard-skl2/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html * igt@kms_psr@psr2_primary_page_flip: - shard-iclb: [PASS][16] -> [SKIP][17] ([fdo#109441]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17293/shard-iclb1/igt@kms_psr@psr2_primary_page_flip.html * igt@kms_setmode@basic: - shard-skl: [PASS][18] -> [FAIL][19] ([i915#31]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-skl7/igt@kms_setm...@basic.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17293/shard-skl6/igt@kms_setm...@basic.html * igt@kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [PASS][20] -> [DMESG-WARN][21] ([i915#180]) +4 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/shard-kbl7/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17293/shard-kbl6/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html Possible
