Re: [Intel-gfx] [PATCH] drm: Replace drm_modeset_lock/unlock_all with DRM_MODESET_LOCK_ALL_* helpers
On 04.05.2020 13:53, Daniel Vetter wrote:
> On Fri, May 01, 2020 at 05:49:33PM +0200, Michał Orzeł wrote:
>>
>>
>> On 30.04.2020 20:30, Daniel Vetter wrote:
>>> On Thu, Apr 30, 2020 at 5:38 PM Sean Paul wrote:
On Wed, Apr 29, 2020 at 4:57 AM Jani Nikula
wrote:
>
> On Tue, 28 Apr 2020, Michal Orzel wrote:
>> As suggested by the TODO list for the kernel DRM subsystem, replace
>> the deprecated functions that take/drop modeset locks with new helpers.
>>
>> Signed-off-by: Michal Orzel
>> ---
>> drivers/gpu/drm/drm_mode_object.c | 10 ++
>> 1 file changed, 6 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/drm_mode_object.c
>> b/drivers/gpu/drm/drm_mode_object.c
>> index 35c2719..901b078 100644
>> --- a/drivers/gpu/drm/drm_mode_object.c
>> +++ b/drivers/gpu/drm/drm_mode_object.c
>> @@ -402,12 +402,13 @@ int drm_mode_obj_get_properties_ioctl(struct
>> drm_device *dev, void *data,
>> {
>> struct drm_mode_obj_get_properties *arg = data;
>> struct drm_mode_object *obj;
>> + struct drm_modeset_acquire_ctx ctx;
>> int ret = 0;
>>
>> if (!drm_core_check_feature(dev, DRIVER_MODESET))
>> return -EOPNOTSUPP;
>>
>> - drm_modeset_lock_all(dev);
>> + DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx, 0, ret);
>
> I cry a little every time I look at the DRM_MODESET_LOCK_ALL_BEGIN and
> DRM_MODESET_LOCK_ALL_END macros. :(
>
> Currently only six users... but there are ~60 calls to
> drm_modeset_lock_all{,_ctx} that I presume are to be replaced. I wonder
> if this will come back and haunt us.
>
What's the alternative? Seems like the options without the macros is
to use incorrect scope or have a bunch of retry/backoff cargo-cult
everywhere (and hope the copy source is done correctly).
>>>
>>> Yeah Sean & me had a bunch of bikesheds and this is the least worst
>>> option we could come up with. You can't make it a function because of
>>> the control flow. You don't want to open code this because it's tricky
>>> to get right, if all you want is to just grab all locks. But it is
>>> magic hidden behind a macro, which occasionally ends up hurting.
>>> -Daniel
>> So what are we doing with this problem? Should we replace at once approx. 60
>> calls?
>
> I'm confused by your question - dradual conversion is entirely orthogonal
> to what exactly we're converting too. All I added here is that we've
> discussed this at length, and the macro is the best thing we've come up
> with. I still think it's the best compromise.
>
> Flag-day conversion for over 60 calls doesn't work, no matter what.
> -Daniel
>
I agree with that. All I wanted to ask was whether I should add something
additional to this patch or not.
Thanks,
Michal
>>
>> Michal
>>>
Sean
> BR,
> Jani.
>
>
>>
>> obj = drm_mode_object_find(dev, file_priv, arg->obj_id,
>> arg->obj_type);
>> if (!obj) {
>> @@ -427,7 +428,7 @@ int drm_mode_obj_get_properties_ioctl(struct
>> drm_device *dev, void *data,
>> out_unref:
>> drm_mode_object_put(obj);
>> out:
>> - drm_modeset_unlock_all(dev);
>> + DRM_MODESET_LOCK_ALL_END(ctx, ret);
>> return ret;
>> }
>>
>> @@ -449,12 +450,13 @@ static int set_property_legacy(struct
>> drm_mode_object *obj,
>> {
>> struct drm_device *dev = prop->dev;
>> struct drm_mode_object *ref;
>> + struct drm_modeset_acquire_ctx ctx;
>> int ret = -EINVAL;
>>
>> if (!drm_property_change_valid_get(prop, prop_value, &ref))
>> return -EINVAL;
>>
>> - drm_modeset_lock_all(dev);
>> + DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx, 0, ret);
>> switch (obj->type) {
>> case DRM_MODE_OBJECT_CONNECTOR:
>> ret = drm_connector_set_obj_prop(obj, prop, prop_value);
>> @@ -468,7 +470,7 @@ static int set_property_legacy(struct
>> drm_mode_object *obj,
>> break;
>> }
>> drm_property_change_valid_put(prop, ref);
>> - drm_modeset_unlock_all(dev);
>> + DRM_MODESET_LOCK_ALL_END(ctx, ret);
>>
>> return ret;
>> }
>
> --
> Jani Nikula, Intel Open Source Graphics Center
>>>
>>>
>>>
>
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Re: [Intel-gfx] [PATCH v2 08/22] drm/i915/rkl: Add power well support
On 2020-05-04 at 15:52:13 -0700, Matt Roper wrote:
> RKL power wells are similar to TGL power wells, but have some important
> differences:
>
> * PG1 now has pipe A's VDSC (rather than sticking it in PG2)
> * PG2 no longer exists
> * DDI-C (aka TC-1) moves from PG1 -> PG3
> * PG5 no longer exists due to the lack of a fourth pipe
>
> Also note that what we refer to as 'DDI-C' and 'DDI-D' need to actually
> be programmed as TC-1 and TC-2 even though this platform doesn't have TC
> outputs.
>
> Bspec: 49234
> Cc: Imre Deak
> Cc: Lucas De Marchi
> Cc: Anshuman Gupta
> Signed-off-by: Matt Roper
> ---
> .../drm/i915/display/intel_display_power.c| 185 +-
> drivers/gpu/drm/i915/display/intel_vdsc.c | 4 +-
> 2 files changed, 186 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 49998906cc61..71691919d101 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -2913,6 +2913,53 @@ void intel_display_power_put(struct drm_i915_private
> *dev_priv,
> BIT_ULL(POWER_DOMAIN_AUX_I_TBT) | \
> BIT_ULL(POWER_DOMAIN_TC_COLD_OFF))
>
> +#define RKL_PW_4_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |\
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define RKL_PW_3_POWER_DOMAINS ( \
> + RKL_PW_4_POWER_DOMAINS |\
> + BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO) | \
> + BIT_ULL(POWER_DOMAIN_VGA) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |\
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |\
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) |\
> + BIT_ULL(POWER_DOMAIN_AUX_D) | \
> + BIT_ULL(POWER_DOMAIN_AUX_E) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +/*
> + * There is no PW_2/PG_2 on RKL.
> + *
> + * RKL PW_1/PG_1 domains (under HW/DMC control):
> + * - DBUF function (note: registers are in PW0)
> + * - PIPE_A and its planes and VDSC/joining, except VGA
> + * - transcoder A
> + * - DDI_A and DDI_B
> + * - FBC
> + *
> + * RKL PW_0/PG_0 domains (under HW/DMC control):
> + * - PCI
> + * - clocks except port PLL
> + * - shared functions:
> + * * interrupts except pipe interrupts
> + * * MBus except PIPE_MBUS_DBOX_CTL
> + * * DBUF registers
> + * - central power except FBC
> + * - top-level GTC (DDI-level GTC is in the well associated with the DDI)
> + */
> +
> +#define RKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> + RKL_PW_3_POWER_DOMAINS |\
> + BIT_ULL(POWER_DOMAIN_MODESET) | \
> + BIT_ULL(POWER_DOMAIN_AUX_A) | \
> + BIT_ULL(POWER_DOMAIN_AUX_B) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
> .sync_hw = i9xx_power_well_sync_hw_noop,
> .enable = i9xx_always_on_power_well_noop,
> @@ -4283,6 +4330,140 @@ static const struct i915_power_well_desc
> tgl_power_wells[] = {
> },
> };
>
> +static const struct i915_power_well_desc rkl_power_wells[] = {
> + {
> + .name = "always-on",
> + .always_on = true,
> + .domains = POWER_DOMAIN_MASK,
> + .ops = &i9xx_always_on_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + },
> + {
> + .name = "power well 1",
> + /* Handled by the DMC firmware */
> + .always_on = true,
> + .domains = 0,
> + .ops = &hsw_power_well_ops,
> + .id = SKL_DISP_PW_1,
> + {
> + .hsw.regs = &hsw_power_well_regs,
> + .hsw.idx = ICL_PW_CTL_IDX_PW_1,
> + .hsw.has_fuses = true,
> + },
> + },
> + {
> + .name = "DC off",
> + .domains = RKL_DISPLAY_DC_OFF_POWER_DOMAINS,
> + .ops = &gen9_dc_off_power_well_ops,
> + .id = SKL_DISP_DC_OFF,
> + },
> + {
> + .name = "power well 3",
> + .domains = RKL_PW_3_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = ICL_DISP_PW_3,
> + {
> + .hsw.regs = &hsw_power_well_regs,
> + .hsw.idx = ICL_PW_CTL_IDX_PW_3,
> + .hsw.irq_pipe_mask = BIT(PIPE_B),
> + .hsw.has_vga = true,
> + .hsw.has_fuses = true,
> + },
> + },
> + {
> + .name = "power well 4",
> + .dom
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gem: Implement legacy MI_STORE_DATA_IMM (rev2)
== Series Details == Series: drm/i915/gem: Implement legacy MI_STORE_DATA_IMM (rev2) URL : https://patchwork.freedesktop.org/series/76866/ State : success == Summary == CI Bug Log - changes from CI_DRM_8419_full -> Patchwork_17570_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_17570_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@in-flight-suspend: - shard-skl: [PASS][1] -> [INCOMPLETE][2] ([i915#69]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8419/shard-skl5/igt@gem_...@in-flight-suspend.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17570/shard-skl9/igt@gem_...@in-flight-suspend.html * igt@gen9_exec_parse@allowed-all: - shard-skl: [PASS][3] -> [DMESG-WARN][4] ([i915#716]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8419/shard-skl8/igt@gen9_exec_pa...@allowed-all.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17570/shard-skl4/igt@gen9_exec_pa...@allowed-all.html - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#716]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8419/shard-apl4/igt@gen9_exec_pa...@allowed-all.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17570/shard-apl7/igt@gen9_exec_pa...@allowed-all.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([i915#180]) +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8419/shard-apl2/igt@i915_susp...@fence-restore-tiled2untiled.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17570/shard-apl1/igt@i915_susp...@fence-restore-tiled2untiled.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([i915#180]) +3 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8419/shard-kbl7/igt@kms_cursor_...@pipe-a-cursor-suspend.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17570/shard-kbl6/igt@kms_cursor_...@pipe-a-cursor-suspend.html * igt@kms_cursor_edge_walk@pipe-a-256x256-bottom-edge: - shard-apl: [PASS][11] -> [FAIL][12] ([i915#70] / [i915#95]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8419/shard-apl2/igt@kms_cursor_edge_w...@pipe-a-256x256-bottom-edge.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17570/shard-apl1/igt@kms_cursor_edge_w...@pipe-a-256x256-bottom-edge.html * igt@kms_draw_crc@draw-method-rgb565-pwrite-untiled: - shard-glk: [PASS][13] -> [FAIL][14] ([i915#177] / [i915#52] / [i915#54]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8419/shard-glk6/igt@kms_draw_...@draw-method-rgb565-pwrite-untiled.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17570/shard-glk4/igt@kms_draw_...@draw-method-rgb565-pwrite-untiled.html * igt@kms_draw_crc@draw-method-xrgb2101010-pwrite-xtiled: - shard-snb: [PASS][15] -> [SKIP][16] ([fdo#109271]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8419/shard-snb2/igt@kms_draw_...@draw-method-xrgb2101010-pwrite-xtiled.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17570/shard-snb2/igt@kms_draw_...@draw-method-xrgb2101010-pwrite-xtiled.html * igt@kms_draw_crc@draw-method-xrgb-pwrite-untiled: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#177] / [i915#52] / [i915#54]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8419/shard-skl10/igt@kms_draw_...@draw-method-xrgb-pwrite-untiled.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17570/shard-skl8/igt@kms_draw_...@draw-method-xrgb-pwrite-untiled.html * igt@kms_flip_tiling@flip-changes-tiling-y: - shard-apl: [PASS][19] -> [FAIL][20] ([i915#95]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8419/shard-apl8/igt@kms_flip_til...@flip-changes-tiling-y.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17570/shard-apl7/igt@kms_flip_til...@flip-changes-tiling-y.html - shard-kbl: [PASS][21] -> [FAIL][22] ([i915#699] / [i915#93] / [i915#95]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8419/shard-kbl3/igt@kms_flip_til...@flip-changes-tiling-y.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17570/shard-kbl7/igt@kms_flip_til...@flip-changes-tiling-y.html * igt@kms_hdr@bpc-switch: - shard-skl: [PASS][23] -> [FAIL][24] ([i915#1188]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8419/shard-skl10/igt@kms_...@bpc-switch.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17570/shard-skl8/igt@kms_...@bpc-switch.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][25] -> [FAIL][26] ([fdo#108145] / [i915#265]) [25]: https://intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [01/22] drm/i915: Allow some leniency in PCU reads (rev2)
== Series Details == Series: series starting with [01/22] drm/i915: Allow some leniency in PCU reads (rev2) URL : https://patchwork.freedesktop.org/series/76885/ State : success == Summary == CI Bug Log - changes from CI_DRM_8418_full -> Patchwork_17568_full Summary --- **SUCCESS** No regressions found. New tests - New tests have been introduced between CI_DRM_8418_full and Patchwork_17568_full: ### New IGT tests (1) ### * igt@dmabuf@all@dma_fence_proxy: - Statuses : 7 pass(s) - Exec time: [0.04, 0.11] s Known issues Here are the changes found in Patchwork_17568_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_workarounds@suspend-resume: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8418/shard-apl6/igt@gem_workarou...@suspend-resume.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17568/shard-apl6/igt@gem_workarou...@suspend-resume.html * igt@i915_suspend@debugfs-reader: - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8418/shard-kbl2/igt@i915_susp...@debugfs-reader.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17568/shard-kbl4/igt@i915_susp...@debugfs-reader.html * igt@kms_cursor_edge_walk@pipe-a-256x256-bottom-edge: - shard-apl: [PASS][5] -> [FAIL][6] ([i915#70] / [i915#95]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8418/shard-apl6/igt@kms_cursor_edge_w...@pipe-a-256x256-bottom-edge.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17568/shard-apl6/igt@kms_cursor_edge_w...@pipe-a-256x256-bottom-edge.html * igt@kms_draw_crc@draw-method-rgb565-pwrite-untiled: - shard-glk: [PASS][7] -> [FAIL][8] ([i915#177] / [i915#52] / [i915#54]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8418/shard-glk8/igt@kms_draw_...@draw-method-rgb565-pwrite-untiled.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17568/shard-glk4/igt@kms_draw_...@draw-method-rgb565-pwrite-untiled.html * igt@kms_draw_crc@draw-method-xrgb-pwrite-untiled: - shard-skl: [PASS][9] -> [FAIL][10] ([i915#177] / [i915#52] / [i915#54]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8418/shard-skl4/igt@kms_draw_...@draw-method-xrgb-pwrite-untiled.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17568/shard-skl8/igt@kms_draw_...@draw-method-xrgb-pwrite-untiled.html * igt@kms_flip_tiling@flip-changes-tiling-y: - shard-apl: [PASS][11] -> [FAIL][12] ([i915#95]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8418/shard-apl4/igt@kms_flip_til...@flip-changes-tiling-y.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17568/shard-apl3/igt@kms_flip_til...@flip-changes-tiling-y.html - shard-kbl: [PASS][13] -> [FAIL][14] ([i915#699] / [i915#93] / [i915#95]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8418/shard-kbl3/igt@kms_flip_til...@flip-changes-tiling-y.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17568/shard-kbl2/igt@kms_flip_til...@flip-changes-tiling-y.html * igt@kms_hdr@bpc-switch-dpms: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#1188]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8418/shard-skl5/igt@kms_...@bpc-switch-dpms.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17568/shard-skl6/igt@kms_...@bpc-switch-dpms.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145] / [i915#265]) +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8418/shard-skl2/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17568/shard-skl5/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html * igt@kms_psr2_su@frontbuffer: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109642] / [fdo#111068]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8418/shard-iclb2/igt@kms_psr2...@frontbuffer.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17568/shard-iclb1/igt@kms_psr2...@frontbuffer.html * igt@kms_psr@psr2_primary_page_flip: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +3 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8418/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17568/shard-iclb7/igt@kms_psr@psr2_primary_page_flip.html Possible fixes * igt@gen9_exec_parse@allowed-all: - shard-apl: [DMESG-WARN][23] ([i915#716]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8418/s
Re: [Intel-gfx] [PATCH] drm/i915/tgl: Put HDC flush pipe_control bit in the right dword
On Monday, May 4, 2020 5:01:46 PM PDT D Scott Phillips wrote: > Previously we set HDC_PIPELINE_FLUSH in dword 1 of gen12 > pipe_control commands. HDC Pipeline flush actually resides in > dword 0, and the bit we were setting in dword 1 was Indirect State > Pointers Disable, which invalidates indirect state in the render > context. This causes failures for userspace, as things like push > constant state gets invalidated. > > Cc: Mika Kuoppala > Cc: Chris Wilson > Signed-off-by: D Scott Phillips > --- > drivers/gpu/drm/i915/gt/intel_engine.h | 23 +-- > drivers/gpu/drm/i915/gt/intel_lrc.c| 11 ++- > 2 files changed, 23 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h > b/drivers/gpu/drm/i915/gt/intel_engine.h > index 19d0b8830905..8338be338ec8 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine.h > +++ b/drivers/gpu/drm/i915/gt/intel_engine.h > @@ -241,19 +241,24 @@ void intel_engine_fini_breadcrumbs(struct > intel_engine_cs *engine); > void intel_engine_print_breadcrumbs(struct intel_engine_cs *engine, > struct drm_printer *p); > > -static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset) > +static inline u32 *gen12_emit_pipe_control(u32 *batch, u32 flags0, u32 > flags1, u32 offset) Great find! It looks like HDC_PIPELINE_FLUSH moved from bit 41 to bit 9 even on Icelake / Gen11 - so it might make sense to call this gen11_emit_pipe_control() and use it on the Icelake functions. That said, i915 never sets HDC_PIPELINE_FLUSH until Gen12, so we don't actually have a bug to fix on Icelake today. But if someone started trying to set it on Gen11, we would have a bug - hence the suggestion. With or without any changes, Reviewed-by: Kenneth Graunke and thanks so much for tracking this down! signature.asc Description: This is a digitally signed message part. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Put HDC flush pipe_control bit in the right dword
== Series Details == Series: drm/i915/tgl: Put HDC flush pipe_control bit in the right dword URL : https://patchwork.freedesktop.org/series/76925/ State : success == Summary == CI Bug Log - changes from CI_DRM_8424 -> Patchwork_17578 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17578/index.html Known issues Here are the changes found in Patchwork_17578 that come from known issues: ### IGT changes ### Warnings * igt@i915_pm_rpm@module-reload: - fi-kbl-x1275: [FAIL][1] ([i915#62]) -> [SKIP][2] ([fdo#109271]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/fi-kbl-x1275/igt@i915_pm_...@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17578/fi-kbl-x1275/igt@i915_pm_...@module-reload.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 Participating hosts (51 -> 44) -- Additional (1): fi-kbl-7560u Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-tgl-y fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8424 -> Patchwork_17578 CI-20190529: 20190529 CI_DRM_8424: 69ecf47ef1aabcdc8a4e070584d0a717bbabf4fe @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5628: 652a3fd8966345fa5498904ce80a2027a6782783 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17578: f3eb1ee5e0b9a5156d1253dc3dbf86049d9d4d69 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == f3eb1ee5e0b9 drm/i915/tgl: Put HDC flush pipe_control bit in the right dword == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17578/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gem: Specify address type for chained reloc batches
== Series Details == Series: drm/i915/gem: Specify address type for chained reloc batches URL : https://patchwork.freedesktop.org/series/76904/ State : success == Summary == CI Bug Log - changes from CI_DRM_8418_full -> Patchwork_17567_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_17567_full that come from known issues: ### IGT changes ### Issues hit * igt@kms_cursor_edge_walk@pipe-a-256x256-bottom-edge: - shard-apl: [PASS][1] -> [FAIL][2] ([i915#70] / [i915#95]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8418/shard-apl6/igt@kms_cursor_edge_w...@pipe-a-256x256-bottom-edge.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17567/shard-apl4/igt@kms_cursor_edge_w...@pipe-a-256x256-bottom-edge.html * igt@kms_flip_tiling@flip-changes-tiling-y: - shard-apl: [PASS][3] -> [FAIL][4] ([i915#95]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8418/shard-apl4/igt@kms_flip_til...@flip-changes-tiling-y.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17567/shard-apl1/igt@kms_flip_til...@flip-changes-tiling-y.html - shard-kbl: [PASS][5] -> [FAIL][6] ([i915#699] / [i915#93] / [i915#95]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8418/shard-kbl3/igt@kms_flip_til...@flip-changes-tiling-y.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17567/shard-kbl2/igt@kms_flip_til...@flip-changes-tiling-y.html * igt@kms_hdr@bpc-switch-dpms: - shard-skl: [PASS][7] -> [FAIL][8] ([i915#1188]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8418/shard-skl5/igt@kms_...@bpc-switch-dpms.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17567/shard-skl10/igt@kms_...@bpc-switch-dpms.html * igt@kms_hdr@bpc-switch-suspend: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#180]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8418/shard-apl4/igt@kms_...@bpc-switch-suspend.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17567/shard-apl1/igt@kms_...@bpc-switch-suspend.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([i915#180]) +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8418/shard-kbl3/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17567/shard-kbl2/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#108145] / [i915#265]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8418/shard-skl2/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17567/shard-skl2/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html * igt@kms_psr@psr2_primary_page_flip: - shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441]) +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8418/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17567/shard-iclb7/igt@kms_psr@psr2_primary_page_flip.html * igt@kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#180] / [i915#93] / [i915#95]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8418/shard-kbl7/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17567/shard-kbl6/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html Possible fixes * igt@gen9_exec_parse@allowed-all: - shard-apl: [DMESG-WARN][19] ([i915#716]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8418/shard-apl6/igt@gen9_exec_pa...@allowed-all.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17567/shard-apl4/igt@gen9_exec_pa...@allowed-all.html * igt@kms_atomic_interruptible@atomic-setmode: - shard-snb: [SKIP][21] ([fdo#109271]) -> [PASS][22] +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8418/shard-snb2/igt@kms_atomic_interrupti...@atomic-setmode.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17567/shard-snb5/igt@kms_atomic_interrupti...@atomic-setmode.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-apl: [DMESG-WARN][23] ([i915#180]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8418/shard-apl6/igt@kms_cursor_...@pipe-a-cursor-suspend.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17567/shard-apl4/igt@kms_cursor_...@pipe-a-cursor-suspend.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: - shard-g
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tgl: Put HDC flush pipe_control bit in the right dword
== Series Details == Series: drm/i915/tgl: Put HDC flush pipe_control bit in the right dword URL : https://patchwork.freedesktop.org/series/76925/ State : warning == Summary == $ dim checkpatch origin/drm-tip f3eb1ee5e0b9 drm/i915/tgl: Put HDC flush pipe_control bit in the right dword -:112: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #112: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:4767: + cs = gen12_emit_ggtt_write_rcs(cs, request->fence.seqno, total: 0 errors, 0 warnings, 1 checks, 93 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/tgl: Put HDC flush pipe_control bit in the right dword
D Scott Phillips writes:
> Previously we set HDC_PIPELINE_FLUSH in dword 1 of gen12
> pipe_control commands. HDC Pipeline flush actually resides in
> dword 0, and the bit we were setting in dword 1 was Indirect State
> Pointers Disable, which invalidates indirect state in the render
> context. This causes failures for userspace, as things like push
> constant state gets invalidated.
>
> Cc: Mika Kuoppala
> Cc: Chris Wilson
> Signed-off-by: D Scott Phillips
also,
Fixes: 4aa0b5d457f5 ("drm/i915/tgl: Add HDC Pipeline Flush")
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/tgl: Put HDC flush pipe_control bit in the right dword
Previously we set HDC_PIPELINE_FLUSH in dword 1 of gen12
pipe_control commands. HDC Pipeline flush actually resides in
dword 0, and the bit we were setting in dword 1 was Indirect State
Pointers Disable, which invalidates indirect state in the render
context. This causes failures for userspace, as things like push
constant state gets invalidated.
Cc: Mika Kuoppala
Cc: Chris Wilson
Signed-off-by: D Scott Phillips
---
drivers/gpu/drm/i915/gt/intel_engine.h | 23 +--
drivers/gpu/drm/i915/gt/intel_lrc.c| 11 ++-
2 files changed, 23 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index 19d0b8830905..8338be338ec8 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -241,19 +241,24 @@ void intel_engine_fini_breadcrumbs(struct intel_engine_cs
*engine);
void intel_engine_print_breadcrumbs(struct intel_engine_cs *engine,
struct drm_printer *p);
-static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset)
+static inline u32 *gen12_emit_pipe_control(u32 *batch, u32 flags0, u32 flags1,
u32 offset)
{
memset(batch, 0, 6 * sizeof(u32));
- batch[0] = GFX_OP_PIPE_CONTROL(6);
- batch[1] = flags;
+ batch[0] = GFX_OP_PIPE_CONTROL(6) | flags0;
+ batch[1] = flags1;
batch[2] = offset;
return batch + 6;
}
+static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset)
+{
+ return gen12_emit_pipe_control(batch, 0, flags, offset);
+}
+
static inline u32 *
-gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
+gen12_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags0, u32
flags1)
{
/* We're using qword write, offset should be aligned to 8 bytes. */
GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
@@ -262,8 +267,8 @@ gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32
gtt_offset, u32 flags)
* need a prior CS_STALL, which is emitted by the flush
* following the batch.
*/
- *cs++ = GFX_OP_PIPE_CONTROL(6);
- *cs++ = flags | PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_GLOBAL_GTT_IVB;
+ *cs++ = GFX_OP_PIPE_CONTROL(6) | flags0;
+ *cs++ = flags1 | PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_GLOBAL_GTT_IVB;
*cs++ = gtt_offset;
*cs++ = 0;
*cs++ = value;
@@ -273,6 +278,12 @@ gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32
gtt_offset, u32 flags)
return cs;
}
+static inline u32 *
+gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
+{
+ return gen12_emit_ggtt_write_rcs(cs, value, gtt_offset, 0, flags);
+}
+
static inline u32 *
gen8_emit_ggtt_write(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index d4ef344657b0..af7790ac9f6a 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -4549,6 +4549,7 @@ static int gen12_emit_flush_render(struct i915_request
*request,
u32 mode)
{
if (mode & EMIT_FLUSH) {
+ u32 flags0 = 0;
u32 flags = 0;
u32 *cs;
@@ -4559,7 +4560,7 @@ static int gen12_emit_flush_render(struct i915_request
*request,
flags |= PIPE_CONTROL_DEPTH_STALL;
flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
flags |= PIPE_CONTROL_FLUSH_ENABLE;
- flags |= PIPE_CONTROL_HDC_PIPELINE_FLUSH;
+ flags0 |= PIPE_CONTROL_HDC_PIPELINE_FLUSH;
flags |= PIPE_CONTROL_STORE_DATA_INDEX;
flags |= PIPE_CONTROL_QW_WRITE;
@@ -4570,7 +4571,7 @@ static int gen12_emit_flush_render(struct i915_request
*request,
if (IS_ERR(cs))
return PTR_ERR(cs);
- cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR);
+ cs = gen12_emit_pipe_control(cs, flags0, flags,
LRC_PPHWSP_SCRATCH_ADDR);
intel_ring_advance(request, cs);
}
@@ -4762,9 +4763,10 @@ static u32 *gen12_emit_fini_breadcrumb(struct
i915_request *request, u32 *cs)
static u32 *
gen12_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs)
{
- cs = gen8_emit_ggtt_write_rcs(cs,
+ cs = gen12_emit_ggtt_write_rcs(cs,
request->fence.seqno,
i915_request_active_timeline(request)->hwsp_offset,
+ PIPE_CONTROL_HDC_PIPELINE_FLUSH,
PIPE_CONTROL_CS_STALL |
PIPE_CONTROL_TILE_CACHE_FLUSH |
PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
@@ -4772,8 +4774,7 @@ gen12_emit_fini_breadcrumb_rcs(struct i915_request
*request, u32 *cs)
Re: [Intel-gfx] [PATCH v2 2/3] drm/i915: Setup MCR steering for RCS engine workarounds
On Mon, May 04, 2020 at 12:43:54PM +0100, Tvrtko Ursulin wrote:
>
> On 02/05/2020 05:57, Matt Roper wrote:
> > Reads of multicast registers give the value associated with
> > slice/subslice 0 by default unless we manually steer the reads to a
> > different slice/subslice. If slice/subslice 0 are fused off in hardware,
> > performing unsteered reads of multicast registers will return a value of
> > 0 rather than the value we wrote into the multicast register.
> >
> > To ensure we can properly readback and verify workarounds that touch
> > registers in a multicast range, we currently setup MCR steering to a
> > known-valid slice/subslice as the very first item in the GT workaround
> > list for gen10+. That steering will then be in place as we verify the
> > rest of the registers that show up in the GT workaround list, and at
> > initialization the steering will also still be in effect when we move on
> > to applying and verifying the workarounds in the RCS engine's workaround
> > list (which is where most of the multicast registers actually show up).
> >
> > However we seem run into problems during resets where RCS engine
> > workarounds are applied without being preceded by application of the GT
> > workaround list and the steering isn't in place. Let's add the same MCR
> > steering to the beginning of the RCS engine's workaround list to ensure
> > that it's always in place and we don't get erroneous messages about RCS
> > engine workarounds failing to apply.
> >
> > References: https://gitlab.freedesktop.org/drm/intel/issues/1222
> > Cc: Tvrtko Ursulin
> > Cc: ch...@chris-wilson.co.uk
> > Signed-off-by: Matt Roper
> > ---
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 4a255de13394..b11b83546696 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -1345,6 +1345,9 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> > struct i915_wa_list *wal)
> > {
> > struct drm_i915_private *i915 = engine->i915;
> > + if (INTEL_GEN(i915) >= 10)
> > + wa_init_mcr(i915, wal);
> > +
> > if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
> > /*
> > * Wa_1607138336:tgl
> >
>
> No complaints, only a question - is live_engine_reset_workarounds able to
> catch this, presumably sporadic, 0xfdc loss after engine reset?
>From what I can see, it looks like that selftests uses a separate
ring-based approach to handling the workarounds rather than using the
CPU. It looks like that selftest just skips all MCR registers since we
can't steer ring accesses the way we can with the CPU.
Matt
>
> Regards,
>
> Tvrtko
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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[Intel-gfx] ✓ Fi.CI.BAT: success for Introduce Rocket Lake (rev4)
== Series Details == Series: Introduce Rocket Lake (rev4) URL : https://patchwork.freedesktop.org/series/76826/ State : success == Summary == CI Bug Log - changes from CI_DRM_8424 -> Patchwork_17577 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17577/index.html Known issues Here are the changes found in Patchwork_17577 that come from known issues: ### IGT changes ### Warnings * igt@i915_pm_rpm@module-reload: - fi-kbl-x1275: [FAIL][1] ([i915#62]) -> [FAIL][2] ([i915#62] / [i915#95]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/fi-kbl-x1275/igt@i915_pm_...@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17577/fi-kbl-x1275/igt@i915_pm_...@module-reload.html [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (51 -> 44) -- Additional (1): fi-kbl-7560u Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-tgl-y fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8424 -> Patchwork_17577 CI-20190529: 20190529 CI_DRM_8424: 69ecf47ef1aabcdc8a4e070584d0a717bbabf4fe @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5628: 652a3fd8966345fa5498904ce80a2027a6782783 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17577: 9b58f54fa37eab9fb17fe54e748b8194eac9f57b @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 9b58f54fa37e drm/i915/rkl: Add initial workarounds 0126c509f30f drm/i915/rkl: Disable PSR2 8b97223a1c60 drm/i915/rkl: Handle HTI 69bfbb9c7a02 drm/i915/rkl: Add DPLL4 support 5018930e1944 drm/i915/rkl: Handle comp master/slave relationships for PHYs 6906840e8b24 drm/i915/rkl: Don't try to read out DSI transcoders b8b1dbd88b20 drm/i915/rkl: Don't try to access transcoder D 3c2d8a199e89 drm/i915/rkl: Add DDC pin mapping 196dbf07dad1 drm/i915/rkl: provide port/phy mapping for vbt a8c3d67dc688 drm/i915/rkl: Setup ports/phys 1c3381316fe1 drm/i915/rkl: Check proper SDEISR bits for TC1 and TC2 outputs 02aa4c0c4f8f drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout 7846d1a805b9 drm/i915/rkl: RKL only uses PHY_MISC for PHY's A and B fda2d4b25173 drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2 f02fc9990788 drm/i915/rkl: Add power well support a445dde7ad9f drm/i915/rkl: Limit number of universal planes to 5 dc4048963014 drm/i915/rkl: Update memory bandwidth parameters 1c85ab4847be drm/i915/rkl: Add PCH support 90f79585717f drm/i915/rkl: Load DMC firmware for Rocket Lake 630f1d4d8718 drm/i915/rkl: Re-use TGL GuC/HuC firmware 803b4f04888a x86/gpu: add RKL stolen memory support e6bef4e2c937 drm/i915/rkl: Add RKL platform info and PCI ids == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17577/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Rocket Lake (rev4)
== Series Details ==
Series: Introduce Rocket Lake (rev4)
URL : https://patchwork.freedesktop.org/series/76826/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e6bef4e2c937 drm/i915/rkl: Add RKL platform info and PCI ids
-:35: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#35: FILE: drivers/gpu/drm/i915/i915_drv.h:1522:
+#define IS_RKL_REVID(p, since, until) \
+ (IS_ROCKETLAKE(p) && IS_REVID(p, since, until))
-:102: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in
parentheses
#102: FILE: include/drm/i915_pciids.h:609:
+#define INTEL_RKL_IDS(info) \
+ INTEL_VGA_DEVICE(0x4C80, info), \
+ INTEL_VGA_DEVICE(0x4C8A, info), \
+ INTEL_VGA_DEVICE(0x4C8B, info), \
+ INTEL_VGA_DEVICE(0x4C8C, info), \
+ INTEL_VGA_DEVICE(0x4C90, info), \
+ INTEL_VGA_DEVICE(0x4C9A, info)
-:102: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible
side-effects?
#102: FILE: include/drm/i915_pciids.h:609:
+#define INTEL_RKL_IDS(info) \
+ INTEL_VGA_DEVICE(0x4C80, info), \
+ INTEL_VGA_DEVICE(0x4C8A, info), \
+ INTEL_VGA_DEVICE(0x4C8B, info), \
+ INTEL_VGA_DEVICE(0x4C8C, info), \
+ INTEL_VGA_DEVICE(0x4C90, info), \
+ INTEL_VGA_DEVICE(0x4C9A, info)
total: 1 errors, 0 warnings, 2 checks, 69 lines checked
803b4f04888a x86/gpu: add RKL stolen memory support
630f1d4d8718 drm/i915/rkl: Re-use TGL GuC/HuC firmware
90f79585717f drm/i915/rkl: Load DMC firmware for Rocket Lake
1c85ab4847be drm/i915/rkl: Add PCH support
dc4048963014 drm/i915/rkl: Update memory bandwidth parameters
a445dde7ad9f drm/i915/rkl: Limit number of universal planes to 5
f02fc9990788 drm/i915/rkl: Add power well support
fda2d4b25173 drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2
-:36: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#36: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:5261:
+ min_buddy = max_buddy = 0;
total: 0 errors, 0 warnings, 1 checks, 84 lines checked
7846d1a805b9 drm/i915/rkl: RKL only uses PHY_MISC for PHY's A and B
02aa4c0c4f8f drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout
1c3381316fe1 drm/i915/rkl: Check proper SDEISR bits for TC1 and TC2 outputs
a8c3d67dc688 drm/i915/rkl: Setup ports/phys
196dbf07dad1 drm/i915/rkl: provide port/phy mapping for vbt
-:17: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#17:
[drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:275:DDI A]
total: 0 errors, 1 warnings, 0 checks, 104 lines checked
3c2d8a199e89 drm/i915/rkl: Add DDC pin mapping
b8b1dbd88b20 drm/i915/rkl: Don't try to access transcoder D
6906840e8b24 drm/i915/rkl: Don't try to read out DSI transcoders
5018930e1944 drm/i915/rkl: Handle comp master/slave relationships for PHYs
69bfbb9c7a02 drm/i915/rkl: Add DPLL4 support
8b97223a1c60 drm/i915/rkl: Handle HTI
-:92: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#92: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:274:
+{
+
-:154: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#154: FILE: drivers/gpu/drm/i915/i915_reg.h:2903:
+#define HDPORT_PHY_USED_DP(phy) REG_BIT(2*phy + 2)
^
-:154: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'phy' may be better as
'(phy)' to avoid precedence issues
#154: FILE: drivers/gpu/drm/i915/i915_reg.h:2903:
+#define HDPORT_PHY_USED_DP(phy) REG_BIT(2*phy + 2)
-:155: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#155: FILE: drivers/gpu/drm/i915/i915_reg.h:2904:
+#define HDPORT_PHY_USED_HDMI(phy)REG_BIT(2*phy + 1)
^
-:155: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'phy' may be better as
'(phy)' to avoid precedence issues
#155: FILE: drivers/gpu/drm/i915/i915_reg.h:2904:
+#define HDPORT_PHY_USED_HDMI(phy)REG_BIT(2*phy + 1)
total: 0 errors, 0 warnings, 5 checks, 116 lines checked
0126c509f30f drm/i915/rkl: Disable PSR2
9b58f54fa37e drm/i915/rkl: Add initial workarounds
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[Intel-gfx] [PATCH v2 02/22] x86/gpu: add RKL stolen memory support
RKL re-uses the same stolen memory registers as TGL and ICL.
Bspec: 52055
Bspec: 49589
Bspec: 49636
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
---
arch/x86/kernel/early-quirks.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 2f9ec14be3b1..a4b5af03dcc1 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -550,6 +550,7 @@ static const struct pci_device_id intel_early_ids[]
__initconst = {
INTEL_ICL_11_IDS(&gen11_early_ops),
INTEL_EHL_IDS(&gen11_early_ops),
INTEL_TGL_12_IDS(&gen11_early_ops),
+ INTEL_RKL_IDS(&gen11_early_ops),
};
struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0,
0);
--
2.24.1
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[Intel-gfx] [PATCH v2 08/22] drm/i915/rkl: Add power well support
RKL power wells are similar to TGL power wells, but have some important
differences:
* PG1 now has pipe A's VDSC (rather than sticking it in PG2)
* PG2 no longer exists
* DDI-C (aka TC-1) moves from PG1 -> PG3
* PG5 no longer exists due to the lack of a fourth pipe
Also note that what we refer to as 'DDI-C' and 'DDI-D' need to actually
be programmed as TC-1 and TC-2 even though this platform doesn't have TC
outputs.
Bspec: 49234
Cc: Imre Deak
Cc: Lucas De Marchi
Cc: Anshuman Gupta
Signed-off-by: Matt Roper
---
.../drm/i915/display/intel_display_power.c| 185 +-
drivers/gpu/drm/i915/display/intel_vdsc.c | 4 +-
2 files changed, 186 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 49998906cc61..71691919d101 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -2913,6 +2913,53 @@ void intel_display_power_put(struct drm_i915_private
*dev_priv,
BIT_ULL(POWER_DOMAIN_AUX_I_TBT) | \
BIT_ULL(POWER_DOMAIN_TC_COLD_OFF))
+#define RKL_PW_4_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_C) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |\
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define RKL_PW_3_POWER_DOMAINS ( \
+ RKL_PW_4_POWER_DOMAINS |\
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO) | \
+ BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |\
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |\
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) |\
+ BIT_ULL(POWER_DOMAIN_AUX_D) | \
+ BIT_ULL(POWER_DOMAIN_AUX_E) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+/*
+ * There is no PW_2/PG_2 on RKL.
+ *
+ * RKL PW_1/PG_1 domains (under HW/DMC control):
+ * - DBUF function (note: registers are in PW0)
+ * - PIPE_A and its planes and VDSC/joining, except VGA
+ * - transcoder A
+ * - DDI_A and DDI_B
+ * - FBC
+ *
+ * RKL PW_0/PG_0 domains (under HW/DMC control):
+ * - PCI
+ * - clocks except port PLL
+ * - shared functions:
+ * * interrupts except pipe interrupts
+ * * MBus except PIPE_MBUS_DBOX_CTL
+ * * DBUF registers
+ * - central power except FBC
+ * - top-level GTC (DDI-level GTC is in the well associated with the DDI)
+ */
+
+#define RKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
+ RKL_PW_3_POWER_DOMAINS |\
+ BIT_ULL(POWER_DOMAIN_MODESET) | \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
.sync_hw = i9xx_power_well_sync_hw_noop,
.enable = i9xx_always_on_power_well_noop,
@@ -4283,6 +4330,140 @@ static const struct i915_power_well_desc
tgl_power_wells[] = {
},
};
+static const struct i915_power_well_desc rkl_power_wells[] = {
+ {
+ .name = "always-on",
+ .always_on = true,
+ .domains = POWER_DOMAIN_MASK,
+ .ops = &i9xx_always_on_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ },
+ {
+ .name = "power well 1",
+ /* Handled by the DMC firmware */
+ .always_on = true,
+ .domains = 0,
+ .ops = &hsw_power_well_ops,
+ .id = SKL_DISP_PW_1,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_1,
+ .hsw.has_fuses = true,
+ },
+ },
+ {
+ .name = "DC off",
+ .domains = RKL_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .ops = &gen9_dc_off_power_well_ops,
+ .id = SKL_DISP_DC_OFF,
+ },
+ {
+ .name = "power well 3",
+ .domains = RKL_PW_3_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = ICL_DISP_PW_3,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_3,
+ .hsw.irq_pipe_mask = BIT(PIPE_B),
+ .hsw.has_vga = true,
+ .hsw.has_fuses = true,
+ },
+ },
+ {
+ .name = "power well 4",
+ .domains = RKL_PW_4_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &hs
[Intel-gfx] [PATCH v2 05/22] drm/i915/rkl: Add PCH support
Rocket Lake can pair with either TGP or CMP. Cc: Lucas De Marchi Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/intel_pch.c | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c index 20ab9a5023b5..102b03d24f90 100644 --- a/drivers/gpu/drm/i915/intel_pch.c +++ b/drivers/gpu/drm/i915/intel_pch.c @@ -88,7 +88,8 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) case INTEL_PCH_CMP_DEVICE_ID_TYPE: case INTEL_PCH_CMP2_DEVICE_ID_TYPE: drm_dbg_kms(&dev_priv->drm, "Found Comet Lake PCH (CMP)\n"); - drm_WARN_ON(&dev_priv->drm, !IS_COFFEELAKE(dev_priv)); + drm_WARN_ON(&dev_priv->drm, !IS_COFFEELAKE(dev_priv) && + !IS_ROCKETLAKE(dev_priv)); /* CometPoint is CNP Compatible */ return PCH_CNP; case INTEL_PCH_CMP_V_DEVICE_ID_TYPE: @@ -107,7 +108,8 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) case INTEL_PCH_TGP_DEVICE_ID_TYPE: case INTEL_PCH_TGP2_DEVICE_ID_TYPE: drm_dbg_kms(&dev_priv->drm, "Found Tiger Lake LP PCH\n"); - drm_WARN_ON(&dev_priv->drm, !IS_TIGERLAKE(dev_priv)); + drm_WARN_ON(&dev_priv->drm, !IS_TIGERLAKE(dev_priv) && + !IS_ROCKETLAKE(dev_priv)); return PCH_TGP; case INTEL_PCH_JSP_DEVICE_ID_TYPE: case INTEL_PCH_JSP2_DEVICE_ID_TYPE: @@ -141,7 +143,7 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv) * make an educated guess as to which PCH is really there. */ - if (IS_TIGERLAKE(dev_priv)) + if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv)) id = INTEL_PCH_TGP_DEVICE_ID_TYPE; else if (IS_ELKHARTLAKE(dev_priv)) id = INTEL_PCH_MCC_DEVICE_ID_TYPE; -- 2.24.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 20/22] drm/i915/rkl: Handle HTI
If HTI (also sometimes called HDPORT) is enabled at startup, it may be
using some of the PHYs and DPLLs making them unavailable for general
usage. Let's read out the HDPORT_STATE register and avoid making use of
resources that HTI is already using.
Bspec: 49189
Bspec: 53707
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_display.c | 30 ---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 22 ++
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 1 +
drivers/gpu/drm/i915/i915_drv.h | 3 ++
drivers/gpu/drm/i915/i915_reg.h | 6
5 files changed, 58 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index e63221b8a9a6..12cdb1b77f64 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -46,6 +46,7 @@
#include "display/intel_ddi.h"
#include "display/intel_dp.h"
#include "display/intel_dp_mst.h"
+#include "display/intel_dpll_mgr.h"
#include "display/intel_dsi.h"
#include "display/intel_dvo.h"
#include "display/intel_gmbus.h"
@@ -16687,6 +16688,13 @@ static void intel_pps_init(struct drm_i915_private
*dev_priv)
intel_pps_unlock_regs_wa(dev_priv);
}
+static bool hti_uses_phy(u32 hdport_state, enum phy phy)
+{
+ return hdport_state & HDPORT_ENABLED &&
+ (hdport_state & HDPORT_PHY_USED_DP(phy) ||
+hdport_state & HDPORT_PHY_USED_HDMI(phy));
+}
+
static void intel_setup_outputs(struct drm_i915_private *dev_priv)
{
struct intel_encoder *encoder;
@@ -16698,10 +16706,22 @@ static void intel_setup_outputs(struct
drm_i915_private *dev_priv)
return;
if (IS_ROCKETLAKE(dev_priv)) {
- intel_ddi_init(dev_priv, PORT_A);
- intel_ddi_init(dev_priv, PORT_B);
- intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */
- intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */
+ /*
+* If HTI (aka HDPORT) is enabled at boot, it may have taken
+* over some of the PHYs and made them unavailable to the
+* driver. In that case we should skip initializing the
+* corresponding outputs.
+*/
+ u32 hdport_state = intel_de_read(dev_priv, HDPORT_STATE);
+
+ if (!hti_uses_phy(hdport_state, PHY_A))
+ intel_ddi_init(dev_priv, PORT_A);
+ if (!hti_uses_phy(hdport_state, PHY_B))
+ intel_ddi_init(dev_priv, PORT_B);
+ if (!hti_uses_phy(hdport_state, PHY_C))
+ intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */
+ if (!hti_uses_phy(hdport_state, PHY_D))
+ intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */
} else if (INTEL_GEN(dev_priv) >= 12) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
@@ -18220,6 +18240,8 @@ static void intel_modeset_readout_hw_state(struct
drm_device *dev)
intel_dpll_readout_hw_state(dev_priv);
+ dev_priv->hti_pll_mask = intel_get_hti_plls(dev_priv);
+
for_each_intel_encoder(dev, encoder) {
pipe = 0;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 196d9eb3a77b..f8078a288379 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -265,6 +265,25 @@ void intel_disable_shared_dpll(const struct
intel_crtc_state *crtc_state)
mutex_unlock(&dev_priv->dpll.lock);
}
+/*
+ * HTI (aka HDPORT) may be using some of the platform's PLL's, making them
+ * unavailable for use.
+ */
+u32 intel_get_hti_plls(struct drm_i915_private *dev_priv)
+{
+
+ u32 hdport_state;
+
+ if (!IS_ROCKETLAKE(dev_priv))
+ return 0;
+
+ hdport_state = intel_de_read(dev_priv, HDPORT_STATE);
+ if (!(hdport_state & HDPORT_ENABLED))
+ return 0;
+
+ return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, hdport_state);
+}
+
static struct intel_shared_dpll *
intel_find_shared_dpll(struct intel_atomic_state *state,
const struct intel_crtc *crtc,
@@ -280,6 +299,9 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
drm_WARN_ON(&dev_priv->drm, dpll_mask & ~(BIT(I915_NUM_PLLS) - 1));
+ /* Eliminate DPLLs from consideration if reserved by HTI */
+ dpll_mask &= ~dev_priv->hti_pll_mask;
+
for_each_set_bit(i, &dpll_mask, I915_NUM_PLLS) {
pll = &dev_priv->dpll.shared_dplls[i];
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 5d9a2bc371e7..ac2238646fe7 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/dr
[Intel-gfx] [PATCH v2 21/22] drm/i915/rkl: Disable PSR2
From: José Roberto de Souza
RKL doesn't have PSR2 HW tracking, it was replaced by software/manual
tracking. The driver is required to track the areas that needs update
and program hardware to send selective updates.
So until the software tracking is implemented, PSR2 needs to be disabled
for platforms without PSR2 HW tracking.
BSpec: 50422
BSpec: 50424
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_psr.c | 15 +++
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 3 +++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
4 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index a0569fdfeb16..31a04570d262 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -678,6 +678,21 @@ static bool intel_psr2_config_valid(struct intel_dp
*intel_dp,
return false;
}
+ /*
+* Some platforms lack PSR2 HW tracking and instead require manual
+* tracking by software. In this case, the driver is required to track
+* the areas that need updates and program hardware to send selective
+* updates.
+*
+* So until the software tracking is implemented, PSR2 needs to be
+* disabled for platforms without PSR2 HW tracking.
+*/
+ if (!HAS_PSR_HW_TRACKING(dev_priv)) {
+ drm_dbg_kms(&dev_priv->drm,
+ "No PSR2 HW tracking in the platform\n");
+ return false;
+ }
+
/*
* DSC and PSR2 cannot be enabled simultaneously. If a requested
* resolution requires DSC to be enabled, priority is given to DSC
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 06802f2f1cd5..88b524399c8f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1618,6 +1618,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg)
#define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
+#define HAS_PSR_HW_TRACKING(dev_priv) \
+ (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
#define HAS_TRANSCODER(dev_priv, trans)
((INTEL_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0)
#define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 5a470bab2214..2c3b0a7d577d 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -536,6 +536,7 @@ static const struct intel_device_info vlv_info = {
.display.has_ddi = 1, \
.has_fpga_dbg = 1, \
.display.has_psr = 1, \
+ .display.has_psr_hw_tracking = 1, \
.display.has_dp_mst = 1, \
.has_rc6p = 0 /* RC6p removed-by HSW */, \
HSW_PIPE_OFFSETS, \
@@ -690,6 +691,7 @@ static const struct intel_device_info skl_gt4_info = {
.display.has_fbc = 1, \
.display.has_hdcp = 1, \
.display.has_psr = 1, \
+ .display.has_psr_hw_tracking = 1, \
.has_runtime_pm = 1, \
.display.has_csr = 1, \
.has_rc6 = 1, \
@@ -868,6 +870,7 @@ static const struct intel_device_info rkl_info = {
PLATFORM(INTEL_ROCKETLAKE),
.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
.require_force_probe = 1,
+ .display.has_psr_hw_tracking = 0,
.engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
};
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index a126984cef7f..b336b50d3e0b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -147,6 +147,7 @@ enum intel_ppgtt_type {
func(has_modular_fia); \
func(has_overlay); \
func(has_psr); \
+ func(has_psr_hw_tracking); \
func(overlay_needs_physical); \
func(supports_tv);
--
2.24.1
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[Intel-gfx] [PATCH v2 17/22] drm/i915/rkl: Don't try to read out DSI transcoders
From: Aditya Swarup RKL doesn't have DSI outputs, so we shouldn't try to read out the DSI transcoder registers. Signed-off-by: Aditya Swarup Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 2eeafda82188..e63221b8a9a6 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -10901,7 +10901,7 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc, intel_wakeref_t wf; u32 tmp; - if (INTEL_GEN(dev_priv) >= 11) + if (!IS_ROCKETLAKE(dev_priv) && INTEL_GEN(dev_priv) >= 11) panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1); -- 2.24.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 09/22] drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2
RKL uses the same BW_BUDDY programming table as TGL, but programs the
values into a single set BUDDY0 set of registers rather than the
BUDDY1/BUDDY2 sets used by TGL.
Bspec: 49218
Cc: Aditya Swarup
Signed-off-by: Matt Roper
---
.../drm/i915/display/intel_display_power.c| 44 +++
drivers/gpu/drm/i915/i915_reg.h | 14 --
2 files changed, 35 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 71691919d101..a83e1bc0e3a7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5249,7 +5249,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private
*dev_priv)
enum intel_dram_type type = dev_priv->dram_info.type;
u8 num_channels = dev_priv->dram_info.num_channels;
const struct buddy_page_mask *table;
- int i;
+ int config, min_buddy, max_buddy, i;
if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
/* Wa_1409767108: tgl */
@@ -5257,29 +5257,35 @@ static void tgl_bw_buddy_init(struct drm_i915_private
*dev_priv)
else
table = tgl_buddy_page_masks;
- for (i = 0; table[i].page_mask != 0; i++)
- if (table[i].num_channels == num_channels &&
- table[i].type == type)
+ if (IS_ROCKETLAKE(dev_priv)) {
+ min_buddy = max_buddy = 0;
+ } else {
+ min_buddy = 1;
+ max_buddy = 2;
+ }
+
+ for (config = 0; table[config].page_mask != 0; config++)
+ if (table[config].num_channels == num_channels &&
+ table[config].type == type)
break;
- if (table[i].page_mask == 0) {
+ if (table[config].page_mask == 0) {
drm_dbg(&dev_priv->drm,
"Unknown memory configuration; disabling address buddy
logic.\n");
- intel_de_write(dev_priv, BW_BUDDY1_CTL, BW_BUDDY_DISABLE);
- intel_de_write(dev_priv, BW_BUDDY2_CTL, BW_BUDDY_DISABLE);
+ for (i = min_buddy; i <= max_buddy; i++)
+ intel_de_write(dev_priv, BW_BUDDY_CTL(i),
+ BW_BUDDY_DISABLE);
} else {
- intel_de_write(dev_priv, BW_BUDDY1_PAGE_MASK,
- table[i].page_mask);
- intel_de_write(dev_priv, BW_BUDDY2_PAGE_MASK,
- table[i].page_mask);
-
- /* Wa_22010178259:tgl */
- intel_de_rmw(dev_priv, BW_BUDDY1_CTL,
-BW_BUDDY_TLB_REQ_TIMER_MASK,
-REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8));
- intel_de_rmw(dev_priv, BW_BUDDY2_CTL,
-BW_BUDDY_TLB_REQ_TIMER_MASK,
-REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8));
+ for (i = min_buddy; i <= max_buddy; i++) {
+ intel_de_write(dev_priv, BW_BUDDY_PAGE_MASK(i),
+ table[config].page_mask);
+
+ /* Wa_22010178259:tgl,rkl */
+ intel_de_rmw(dev_priv, BW_BUDDY_CTL(i),
+BW_BUDDY_TLB_REQ_TIMER_MASK,
+REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK,
+ 0x8));
+ }
}
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 59c1d527cf13..2266f9fc2d79 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7832,13 +7832,19 @@ enum {
#define WAIT_FOR_PCH_RESET_ACK(1 << 1)
#define WAIT_FOR_PCH_FLR_ACK (1 << 0)
-#define BW_BUDDY1_CTL _MMIO(0x45140)
-#define BW_BUDDY2_CTL _MMIO(0x45150)
+#define _BW_BUDDY0_CTL 0x45130
+#define _BW_BUDDY1_CTL 0x45140
+#define BW_BUDDY_CTL(x)_MMIO(_PICK_EVEN(x, \
+_BW_BUDDY0_CTL, \
+_BW_BUDDY1_CTL))
#define BW_BUDDY_DISABLE REG_BIT(31)
#define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16)
-#define BW_BUDDY1_PAGE_MASK_MMIO(0x45144)
-#define BW_BUDDY2_PAGE_MASK_MMIO(0x45154)
+#define _BW_BUDDY0_PAGE_MASK 0x45134
+#define _BW_BUDDY1_PAGE_MASK 0x45144
+#define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \
+_BW_BUDDY0_PAGE_MASK, \
+_BW_BUDDY1_PAGE_MASK))
#define HSW_NDE_RSTWRN_OPT _MMIO(0x46408)
#define RESET_PCH_HANDSHAKE_ENABLE(1 << 4)
--
2.24.1
[Intel-gfx] [PATCH v2 00/22] Introduce Rocket Lake
Only minor changes since v1, but patchwork got confused by the updates, so sending the whole series again to ensure proper CI testing. v2 changes: - Drop the cdclk patch. The bspec was updated since I originally wrote that and now RKL's table is identical to the one we use on TGL and ICL. No RKL-specific driver changes are necessary now. - Fix a botched mask in the DPCLKA_CFGCR0 clock selection. See the cover letter from v1 for other details: https://lists.freedesktop.org/archives/intel-gfx/2020-May/238498.html Aditya Swarup (1): drm/i915/rkl: Don't try to read out DSI transcoders José Roberto de Souza (1): drm/i915/rkl: Disable PSR2 Lucas De Marchi (1): drm/i915/rkl: provide port/phy mapping for vbt Matt Roper (19): drm/i915/rkl: Add RKL platform info and PCI ids x86/gpu: add RKL stolen memory support drm/i915/rkl: Re-use TGL GuC/HuC firmware drm/i915/rkl: Load DMC firmware for Rocket Lake drm/i915/rkl: Add PCH support drm/i915/rkl: Update memory bandwidth parameters drm/i915/rkl: Limit number of universal planes to 5 drm/i915/rkl: Add power well support drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2 drm/i915/rkl: RKL only uses PHY_MISC for PHY's A and B drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout drm/i915/rkl: Check proper SDEISR bits for TC1 and TC2 outputs drm/i915/rkl: Setup ports/phys drm/i915/rkl: Add DDC pin mapping drm/i915/rkl: Don't try to access transcoder D drm/i915/rkl: Handle comp master/slave relationships for PHYs drm/i915/rkl: Add DPLL4 support drm/i915/rkl: Handle HTI drm/i915/rkl: Add initial workarounds arch/x86/kernel/early-quirks.c| 1 + drivers/gpu/drm/i915/display/intel_bios.c | 72 -- drivers/gpu/drm/i915/display/intel_bw.c | 10 +- .../gpu/drm/i915/display/intel_combo_phy.c| 55 +++-- drivers/gpu/drm/i915/display/intel_csr.c | 10 +- drivers/gpu/drm/i915/display/intel_ddi.c | 18 +- drivers/gpu/drm/i915/display/intel_display.c | 82 +-- .../drm/i915/display/intel_display_power.c| 229 -- drivers/gpu/drm/i915/display/intel_dp.c | 8 +- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 50 +++- drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 1 + drivers/gpu/drm/i915/display/intel_hdmi.c | 22 +- drivers/gpu/drm/i915/display/intel_psr.c | 15 ++ drivers/gpu/drm/i915/display/intel_sprite.c | 22 +- drivers/gpu/drm/i915/display/intel_sprite.h | 11 +- drivers/gpu/drm/i915/display/intel_vdsc.c | 4 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 88 --- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 3 + drivers/gpu/drm/i915/i915_drv.h | 13 + drivers/gpu/drm/i915/i915_irq.c | 10 +- drivers/gpu/drm/i915/i915_pci.c | 13 + drivers/gpu/drm/i915/i915_reg.h | 35 ++- drivers/gpu/drm/i915/intel_device_info.c | 6 +- drivers/gpu/drm/i915/intel_device_info.h | 2 + drivers/gpu/drm/i915/intel_pch.c | 8 +- include/drm/i915_pciids.h | 9 + 26 files changed, 656 insertions(+), 141 deletions(-) -- 2.24.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 04/22] drm/i915/rkl: Load DMC firmware for Rocket Lake
Cc: Anusha Srivatsa
Signed-off-by: Matt Roper
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_csr.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_csr.c
b/drivers/gpu/drm/i915/display/intel_csr.c
index 3112572cfb7d..319932b03e88 100644
--- a/drivers/gpu/drm/i915/display/intel_csr.c
+++ b/drivers/gpu/drm/i915/display/intel_csr.c
@@ -40,6 +40,10 @@
#define GEN12_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE
+#define RKL_CSR_PATH "i915/rkl_dmc_ver2_01.bin"
+#define RKL_CSR_VERSION_REQUIRED CSR_VERSION(2, 1)
+MODULE_FIRMWARE(RKL_CSR_PATH);
+
#define TGL_CSR_PATH "i915/tgl_dmc_ver2_06.bin"
#define TGL_CSR_VERSION_REQUIRED CSR_VERSION(2, 6)
#define TGL_CSR_MAX_FW_SIZE0x6000
@@ -682,7 +686,11 @@ void intel_csr_ucode_init(struct drm_i915_private
*dev_priv)
*/
intel_csr_runtime_pm_get(dev_priv);
- if (INTEL_GEN(dev_priv) >= 12) {
+ if (IS_ROCKETLAKE(dev_priv)) {
+ csr->fw_path = RKL_CSR_PATH;
+ csr->required_version = RKL_CSR_VERSION_REQUIRED;
+ csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
+ } else if (INTEL_GEN(dev_priv) >= 12) {
csr->fw_path = TGL_CSR_PATH;
csr->required_version = TGL_CSR_VERSION_REQUIRED;
/* Allow to load fw via parameter using the last known size */
--
2.24.1
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[Intel-gfx] [PATCH v2 15/22] drm/i915/rkl: Add DDC pin mapping
The pin mapping for the final two outputs varies according to which PCH
is present on the platform: with TGP the pins are remapped into the TC
range, whereas with CMP they stay in the traditional combo output range.
Bspec: 49181
Cc: Aditya Swarup
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 010f37240710..a31a98d26882 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -3082,6 +3082,24 @@ static u8 mcc_port_to_ddc_pin(struct drm_i915_private
*dev_priv, enum port port)
return ddc_pin;
}
+static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port
port)
+{
+ enum phy phy = intel_port_to_phy(dev_priv, port);
+
+ WARN_ON(port == PORT_C);
+
+ /*
+* Pin mapping for RKL depends on which PCH is present. With TGP, the
+* final two outputs use type-c pins, even though they're actually
+* combo outputs. With CMP, the traditional DDI A-D pins are used for
+* all outputs.
+*/
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C)
+ return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
+
+ return GMBUS_PIN_1_BXT + phy;
+}
+
static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
enum port port)
{
@@ -3119,7 +3137,9 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder
*encoder)
return ddc_pin;
}
- if (HAS_PCH_MCC(dev_priv))
+ if (IS_ROCKETLAKE(dev_priv))
+ ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
+ else if (HAS_PCH_MCC(dev_priv))
ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
--
2.24.1
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[Intel-gfx] [PATCH v2 06/22] drm/i915/rkl: Update memory bandwidth parameters
The RKL platform has different memory characteristics from past
platforms. Update the values used by our memory bandwidth calculations
accordingly.
Bspec: 53998
Cc: James Ausmus
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_bw.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index 6e7cc3a4f1aa..d435cc6019e4 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -176,6 +176,12 @@ static const struct intel_sa_info tgl_sa_info = {
.displayrtids = 256,
};
+static const struct intel_sa_info rkl_sa_info = {
+ .deburst = 16,
+ .deprogbwlimit = 20, /* GB/s */
+ .displayrtids = 128,
+};
+
static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct
intel_sa_info *sa)
{
struct intel_qgv_info qi = {};
@@ -271,7 +277,9 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv))
return;
- if (IS_GEN(dev_priv, 12))
+ if (IS_ROCKETLAKE(dev_priv))
+ icl_get_bw_info(dev_priv, &rkl_sa_info);
+ else if (IS_GEN(dev_priv, 12))
icl_get_bw_info(dev_priv, &tgl_sa_info);
else if (IS_GEN(dev_priv, 11))
icl_get_bw_info(dev_priv, &icl_sa_info);
--
2.24.1
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[Intel-gfx] [PATCH v2 22/22] drm/i915/rkl: Add initial workarounds
RKL and TGL share some general gen12 workarounds, but each platform also
has its own platform-specific workarounds.
Cc: Matt Atwood
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_sprite.c | 5 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 88 +
2 files changed, 59 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index 571c36f929bd..20eea81118da 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2842,8 +2842,9 @@ static bool skl_plane_format_mod_supported(struct
drm_plane *_plane,
static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
enum plane_id plane_id)
{
- /* Wa_14010477008:tgl[a0..c0] */
- if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
+ /* Wa_14010477008:tgl[a0..c0],rkl[all] */
+ if (IS_ROCKETLAKE(dev_priv) ||
+ IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
return false;
return plane_id < PLANE_SPRITE4;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index aa90e6b7a118..0132728c4e60 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -575,8 +575,8 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs
*engine,
wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU);
}
-static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
-struct i915_wa_list *wal)
+static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,
+ struct i915_wa_list *wal)
{
/*
* Wa_1409142259:tgl
@@ -586,12 +586,28 @@ static void tgl_ctx_workarounds_init(struct
intel_engine_cs *engine,
* Wa_1409207793:tgl
* Wa_1409178076:tgl
* Wa_1408979724:tgl
+* Wa_14010443199:rkl
+* Wa_14010698770:rkl
*/
WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
+ /* WaDisableGPGPUMidThreadPreemption:gen12 */
+ WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
+ GEN9_PREEMPT_GPGPU_LEVEL_MASK,
+ GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
+}
+
+static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
+struct i915_wa_list *wal)
+{
+ gen12_ctx_workarounds_init(engine, wal);
+
/*
-* Wa_1604555607:gen12 and Wa_1608008084:gen12
+* Wa_1604555607:tgl
+*
+* Note that the implementation of this workaround is further modified
+* according to the FF_MODE2 guidance given by Wa_1608008084:gen12.
* FF_MODE2 register will return the wrong value when read. The default
* value for this register is zero for all fields and there are no bit
* masks. So instead of doing a RMW we should just write the TDS timer
@@ -599,11 +615,6 @@ static void tgl_ctx_workarounds_init(struct
intel_engine_cs *engine,
*/
wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK,
FF_MODE2_TDS_TIMER_128, 0);
-
- /* WaDisableGPGPUMidThreadPreemption:tgl */
- WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
- GEN9_PREEMPT_GPGPU_LEVEL_MASK,
- GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
}
static void
@@ -618,8 +629,10 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
wa_init_start(wal, name, engine->name);
- if (IS_GEN(i915, 12))
+ if (IS_TIGERLAKE(i915))
tgl_ctx_workarounds_init(engine, wal);
+ else if (IS_GEN(i915, 12))
+ gen12_ctx_workarounds_init(engine, wal);
else if (IS_GEN(i915, 11))
icl_ctx_workarounds_init(engine, wal);
else if (IS_CANNONLAKE(i915))
@@ -924,9 +937,16 @@ icl_gt_workarounds_init(struct drm_i915_private *i915,
struct i915_wa_list *wal)
}
static void
-tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list
*wal)
+gen12_gt_workarounds_init(struct drm_i915_private *i915,
+ struct i915_wa_list *wal)
{
wa_init_mcr(i915, wal);
+}
+
+static void
+tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list
*wal)
+{
+ gen12_gt_workarounds_init(i915, wal);
/* Wa_1409420604:tgl */
if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
@@ -944,8 +964,10 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915,
struct i915_wa_list *wal)
static void
gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
- if (IS_GEN(i915, 12))
+ if (IS_TIGERLAKE(i915))
tgl_gt_workarounds_init(i915, wal);
+ else if (
[Intel-gfx] [PATCH v2 16/22] drm/i915/rkl: Don't try to access transcoder D
There are a couple places in our driver that loop over transcoders A..D
for gen11+; since RKL only has three pipes/transcoders, this can lead to
unclaimed register reads/writes. We should add checks for transcoder
existence where appropriate.
Cc: Aditya Swarup
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_display.c | 3 +++
drivers/gpu/drm/i915/i915_irq.c | 6 ++
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index fcfc3812ef28..2eeafda82188 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11007,6 +11007,9 @@ static bool bxt_get_dsi_transcoder_state(struct
intel_crtc *crtc,
else
cpu_transcoder = TRANSCODER_DSI_C;
+ if (!HAS_TRANSCODER(dev_priv, cpu_transcoder))
+ continue;
+
power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
drm_WARN_ON(dev, *power_domain_mask & BIT_ULL(power_domain));
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 622986759ec6..1381cb530c2f 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2849,6 +2849,9 @@ static void gen11_display_irq_reset(struct
drm_i915_private *dev_priv)
for (trans = TRANSCODER_A; trans <= TRANSCODER_D; trans++) {
enum intel_display_power_domain domain;
+ if (!HAS_TRANSCODER(dev_priv, trans))
+ continue;
+
domain = POWER_DOMAIN_TRANSCODER(trans);
if (!intel_display_power_is_enabled(dev_priv, domain))
continue;
@@ -3399,6 +3402,9 @@ static void gen8_de_irq_postinstall(struct
drm_i915_private *dev_priv)
for (trans = TRANSCODER_A; trans <= TRANSCODER_D; trans++) {
enum intel_display_power_domain domain;
+ if (!HAS_TRANSCODER(dev_priv, trans))
+ continue;
+
domain = POWER_DOMAIN_TRANSCODER(trans);
if (!intel_display_power_is_enabled(dev_priv, domain))
continue;
--
2.24.1
___
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[Intel-gfx] [PATCH v2 01/22] drm/i915/rkl: Add RKL platform info and PCI ids
Introduce the basic platform definition, macros, and PCI IDs.
Bspec: 44501
Cc: Lucas De Marchi
Cc: Caz Yokoyama
Cc: Aditya Swarup
Signed-off-by: Matt Roper
Acked-by: Caz Yokoyama
---
drivers/gpu/drm/i915/i915_drv.h | 8
drivers/gpu/drm/i915/i915_pci.c | 10 ++
drivers/gpu/drm/i915/intel_device_info.c | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 1 +
include/drm/i915_pciids.h| 9 +
5 files changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6af69555733e..1ba77283123d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1406,6 +1406,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
#define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
#define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
+#define IS_ROCKETLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev_priv) \
@@ -1514,6 +1515,13 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_TGL_REVID(p, since, until) \
(IS_TIGERLAKE(p) && IS_REVID(p, since, until))
+#define RKL_REVID_A0 0x0
+#define RKL_REVID_B0 0x1
+#define RKL_REVID_C0 0x4
+
+#define IS_RKL_REVID(p, since, until) \
+ (IS_ROCKETLAKE(p) && IS_REVID(p, since, until))
+
#define IS_LP(dev_priv)(INTEL_INFO(dev_priv)->is_lp)
#define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
#define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 1faf9d6ec0a4..5a470bab2214 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -863,6 +863,15 @@ static const struct intel_device_info tgl_info = {
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
};
+static const struct intel_device_info rkl_info = {
+ GEN12_FEATURES,
+ PLATFORM(INTEL_ROCKETLAKE),
+ .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+ .require_force_probe = 1,
+ .engine_mask =
+ BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
+};
+
#define GEN12_DGFX_FEATURES \
GEN12_FEATURES, \
.is_dgfx = 1
@@ -941,6 +950,7 @@ static const struct pci_device_id pciidlist[] = {
INTEL_ICL_11_IDS(&icl_info),
INTEL_EHL_IDS(&ehl_info),
INTEL_TGL_12_IDS(&tgl_info),
+ INTEL_RKL_IDS(&rkl_info),
{0, 0, 0}
};
MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index 91bb7891c70c..9862c1185059 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -61,6 +61,7 @@ static const char * const platform_names[] = {
PLATFORM_NAME(ICELAKE),
PLATFORM_NAME(ELKHARTLAKE),
PLATFORM_NAME(TIGERLAKE),
+ PLATFORM_NAME(ROCKETLAKE),
};
#undef PLATFORM_NAME
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 69c9257c6c6a..a126984cef7f 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -80,6 +80,7 @@ enum intel_platform {
INTEL_ELKHARTLAKE,
/* gen12 */
INTEL_TIGERLAKE,
+ INTEL_ROCKETLAKE,
INTEL_MAX_PLATFORMS
};
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 662d8351c87a..bc989de2aac2 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -605,4 +605,13 @@
INTEL_VGA_DEVICE(0x9AD9, info), \
INTEL_VGA_DEVICE(0x9AF8, info)
+/* RKL */
+#define INTEL_RKL_IDS(info) \
+ INTEL_VGA_DEVICE(0x4C80, info), \
+ INTEL_VGA_DEVICE(0x4C8A, info), \
+ INTEL_VGA_DEVICE(0x4C8B, info), \
+ INTEL_VGA_DEVICE(0x4C8C, info), \
+ INTEL_VGA_DEVICE(0x4C90, info), \
+ INTEL_VGA_DEVICE(0x4C9A, info)
+
#endif /* _I915_PCIIDS_H */
--
2.24.1
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[Intel-gfx] [PATCH v2 07/22] drm/i915/rkl: Limit number of universal planes to 5
RKL only has five universal planes, plus a cursor. Since the
bottom-most universal plane is considered the primary plane, set the
number of sprites available on this platform to 4.
In general, the plane capabilities of the remaining planes stay the same
as TGL. However the NV12 Y-plane support moves down to the new top two
planes and now only the bottom three planes can be used for NV12 UV.
Bspec: 49181
Bspec: 49251
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 17 -
drivers/gpu/drm/i915/display/intel_sprite.h | 11 ++-
drivers/gpu/drm/i915/i915_irq.c | 4 +++-
drivers/gpu/drm/i915/i915_reg.h | 5 +
drivers/gpu/drm/i915/intel_device_info.c | 5 -
6 files changed, 35 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index fd6d63b03489..7d7a5b66f2cb 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -12500,7 +12500,7 @@ static int icl_check_nv12_planes(struct
intel_crtc_state *crtc_state)
continue;
for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
- if (!icl_is_nv12_y_plane(linked->id))
+ if (!icl_is_nv12_y_plane(dev_priv, linked->id))
continue;
if (crtc_state->active_planes & BIT(linked->id))
@@ -12546,6 +12546,10 @@ static int icl_check_nv12_planes(struct
intel_crtc_state *crtc_state)
plane_state->cus_ctl |= PLANE_CUS_PLANE_7;
else if (linked->id == PLANE_SPRITE4)
plane_state->cus_ctl |= PLANE_CUS_PLANE_6;
+ else if (linked->id == PLANE_SPRITE3)
+ plane_state->cus_ctl |= PLANE_CUS_PLANE_5_RKL;
+ else if (linked->id == PLANE_SPRITE2)
+ plane_state->cus_ctl |= PLANE_CUS_PLANE_4_RKL;
else
MISSING_CASE(linked->id);
}
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index ec7055f7..571c36f929bd 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -333,6 +333,21 @@ int intel_plane_check_src_coordinates(struct
intel_plane_state *plane_state)
return 0;
}
+static u8 icl_nv12_y_plane_mask(struct drm_i915_private *i915)
+{
+ if (IS_ROCKETLAKE(i915))
+ return BIT(PLANE_SPRITE2) | BIT(PLANE_SPRITE3);
+ else
+ return BIT(PLANE_SPRITE4) | BIT(PLANE_SPRITE5);
+}
+
+bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv,
+enum plane_id plane_id)
+{
+ return INTEL_GEN(dev_priv) >= 11 &&
+ icl_nv12_y_plane_mask(dev_priv) & BIT(plane_id);
+}
+
bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id
plane_id)
{
return INTEL_GEN(dev_priv) >= 11 &&
@@ -3003,7 +3018,7 @@ static const u32 *icl_get_plane_formats(struct
drm_i915_private *dev_priv,
if (icl_is_hdr_plane(dev_priv, plane_id)) {
*num_formats = ARRAY_SIZE(icl_hdr_plane_formats);
return icl_hdr_plane_formats;
- } else if (icl_is_nv12_y_plane(plane_id)) {
+ } else if (icl_is_nv12_y_plane(dev_priv, plane_id)) {
*num_formats = ARRAY_SIZE(icl_sdr_y_plane_formats);
return icl_sdr_y_plane_formats;
} else {
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.h
b/drivers/gpu/drm/i915/display/intel_sprite.h
index 5eeaa92420d1..cd2104ba1ca1 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.h
+++ b/drivers/gpu/drm/i915/display/intel_sprite.h
@@ -32,21 +32,14 @@ struct intel_plane *
skl_universal_plane_create(struct drm_i915_private *dev_priv,
enum pipe pipe, enum plane_id plane_id);
-static inline bool icl_is_nv12_y_plane(enum plane_id id)
-{
- /* Don't need to do a gen check, these planes are only available on
gen11 */
- if (id == PLANE_SPRITE4 || id == PLANE_SPRITE5)
- return true;
-
- return false;
-}
-
static inline u8 icl_hdr_plane_mask(void)
{
return BIT(PLANE_PRIMARY) |
BIT(PLANE_SPRITE0) | BIT(PLANE_SPRITE1);
}
+bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv,
+enum plane_id plane_id);
bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id
plane_id);
int ivb_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index bd722d0650c8..622986759ec6 100644
--- a/drivers/gpu/drm/i91
[Intel-gfx] [PATCH v2 18/22] drm/i915/rkl: Handle comp master/slave relationships for PHYs
Certain combo PHYs act as a compensation master to other PHYs and need
to be initialized with a special irefgen bit in the PORT_COMP_DW8
register. Previously PHY A was the only compensation master (for PHYs
B & C), but RKL adds a fourth PHY which is slaved to PHY C instead.
Bspec: 49291
Cc: Lucas De Marchi
Cc: José Roberto de Souza
Cc: Aditya Swarup
Signed-off-by: Matt Roper
---
.../gpu/drm/i915/display/intel_combo_phy.c| 25 +--
1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c
b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 43d8784f6fa0..77b04bb3ec62 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -234,6 +234,27 @@ static bool ehl_vbt_ddi_d_present(struct drm_i915_private
*i915)
return false;
}
+static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy)
+{
+ /*
+* Certain PHYs are connected to compensation resistors and act
+* as masters to other PHYs.
+*
+* ICL,TGL:
+* A(master) -> B(slave), C(slave)
+* RKL:
+* A(master) -> B(slave)
+* C(master) -> D(slave)
+*
+* We must set the IREFGEN bit for any PHY acting as a master
+* to another PHY.
+*/
+ if (IS_ROCKETLAKE(dev_priv) && phy == PHY_C)
+ return true;
+
+ return phy == PHY_A;
+}
+
static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
enum phy phy)
{
@@ -245,7 +266,7 @@ static bool icl_combo_phy_verify_state(struct
drm_i915_private *dev_priv,
ret = cnl_verify_procmon_ref_values(dev_priv, phy);
- if (phy == PHY_A) {
+ if (phy_is_master(dev_priv, phy)) {
ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),
IREFGEN, IREFGEN);
@@ -356,7 +377,7 @@ static void icl_combo_phys_init(struct drm_i915_private
*dev_priv)
skip_phy_misc:
cnl_set_procmon_ref_values(dev_priv, phy);
- if (phy == PHY_A) {
+ if (phy_is_master(dev_priv, phy)) {
val = intel_de_read(dev_priv, ICL_PORT_COMP_DW8(phy));
val |= IREFGEN;
intel_de_write(dev_priv, ICL_PORT_COMP_DW8(phy), val);
--
2.24.1
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[Intel-gfx] [PATCH v2 12/22] drm/i915/rkl: Check proper SDEISR bits for TC1 and TC2 outputs
When Rocket Lake is paired with a TGP PCH, the last two outputs utilize
the TC1 and TC2 hpd pins, even though these are combo outputs.
Bspec: 49181
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_dp.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 6952b0295096..d32bbcd99b8a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6172,8 +6172,12 @@ static bool bxt_digital_port_connected(struct
intel_encoder *encoder)
static bool intel_combo_phy_connected(struct drm_i915_private *dev_priv,
enum phy phy)
{
- if (HAS_PCH_MCC(dev_priv) && phy == PHY_C)
- return intel_de_read(dev_priv, SDEISR) &
SDE_TC_HOTPLUG_ICP(PORT_TC1);
+ if (IS_ROCKETLAKE(dev_priv) && phy >= PHY_C)
+ return intel_de_read(dev_priv, SDEISR) &
+ SDE_TC_HOTPLUG_ICP(phy - PHY_C);
+ else if (HAS_PCH_MCC(dev_priv) && phy == PHY_C)
+ return intel_de_read(dev_priv, SDEISR) &
+ SDE_TC_HOTPLUG_ICP(PORT_TC1);
return intel_de_read(dev_priv, SDEISR) & SDE_DDI_HOTPLUG_ICP(phy);
}
--
2.24.1
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[Intel-gfx] [PATCH v2 03/22] drm/i915/rkl: Re-use TGL GuC/HuC firmware
RKL uses the same GuC and HuC as TGL and should load the same firmwares. Bspec: 50668 Cc: Anusha Srivatsa Signed-off-by: Matt Roper Reviewed-by: Anusha Srivatsa --- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c index e1caae93996d..9b6218128d09 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c @@ -47,8 +47,11 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw, * TGL 35.2 is interface-compatible with 33.0 for previous Gens. The deltas * between 33.0 and 35.2 are only related to new additions to support new Gen12 * features. + * + * Note that RKL uses the same firmware as TGL. */ #define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \ + fw_def(ROCKETLAKE, 0, guc_def(tgl, 35, 2, 0), huc_def(tgl, 7, 0, 12)) \ fw_def(TIGERLAKE, 0, guc_def(tgl, 35, 2, 0), huc_def(tgl, 7, 0, 12)) \ fw_def(ELKHARTLAKE, 0, guc_def(ehl, 33, 0, 4), huc_def(ehl, 9, 0, 0)) \ fw_def(ICELAKE, 0, guc_def(icl, 33, 0, 0), huc_def(icl, 9, 0, 0)) \ -- 2.24.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 11/22] drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout
RKL uses a slightly different bit layout for the DPCLKA_CFGCR0 register.
v2:
- Fix inverted mask application when updating ICL_DPCLKA_CFGCR0
- Checkpatch style fixes
Bspec: 50287
Cc: Aditya Swarup
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_ddi.c | 18 +++---
drivers/gpu/drm/i915/display/intel_display.c | 15 ---
drivers/gpu/drm/i915/i915_reg.h | 6 ++
3 files changed, 33 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 5601673c3f30..0ab03282c397 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2732,7 +2732,9 @@ hsw_set_signal_levels(struct intel_dp *intel_dp)
static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
enum phy phy)
{
- if (intel_phy_is_combo(dev_priv, phy)) {
+ if (IS_ROCKETLAKE(dev_priv)) {
+ return RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
+ } else if (intel_phy_is_combo(dev_priv, phy)) {
return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
} else if (intel_phy_is_tc(dev_priv, phy)) {
enum tc_port tc_port = intel_port_to_tc(dev_priv,
@@ -2759,6 +2761,16 @@ static void icl_map_plls_to_ports(struct intel_encoder
*encoder,
(val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
if (intel_phy_is_combo(dev_priv, phy)) {
+ u32 mask, sel;
+
+ if (IS_ROCKETLAKE(dev_priv)) {
+ mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+ sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
+ } else {
+ mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+ sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
+ }
+
/*
* Even though this register references DDIs, note that we
* want to pass the PHY rather than the port (DDI). For
@@ -2769,8 +2781,8 @@ static void icl_map_plls_to_ports(struct intel_encoder
*encoder,
* Clock Select chooses the PLL for both DDIA and DDID and
* drives port A in all cases."
*/
- val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
- val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
+ val &= ~mask;
+ val |= sel;
intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 7d7a5b66f2cb..e30b765d271d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10773,9 +10773,18 @@ static void icl_get_ddi_pll(struct drm_i915_private
*dev_priv, enum port port,
u32 temp;
if (intel_phy_is_combo(dev_priv, phy)) {
- temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) &
- ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
- id = temp >> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
+ u32 mask, shift;
+
+ if (IS_ROCKETLAKE(dev_priv)) {
+ mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+ shift = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
+ } else {
+ mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+ shift = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
+ }
+
+ temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) & mask;
+ id = temp >> shift;
port_dpll_id = ICL_PORT_DPLL_DEFAULT;
} else if (intel_phy_is_tc(dev_priv, phy)) {
u32 clk_sel = intel_de_read(dev_priv, DDI_CLK_SEL(port)) &
DDI_CLK_SEL_MASK;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2266f9fc2d79..516bfbad0eb9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10163,12 +10163,18 @@ enum skl_power_gate {
#define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)(1 << _PICK(phy, 10, 11, 24))
+#define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)REG_BIT((phy) + 10)
#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < PORT_TC4 ? \
(tc_port) + 12 : \
(tc_port) - PORT_TC4 +
21))
#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2)
#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 <<
ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) <<
ICL_DPCLKA_CFGCR0_DDI_CLK_SEL
[Intel-gfx] [PATCH v2 19/22] drm/i915/rkl: Add DPLL4 support
Rocket Lake has a third DPLL (called 'DPLL4') that must be used to
enable a third display. Unlike EHL's variant of DPLL4, the RKL variant
behaves the same as DPLL0/1. And despite its name, the DPLL4 registers
are offset as if it were DPLL2, so no extra offset handling is needed
either.
Bspec: 49202
Bspec: 49443
Bspec: 50288
Bspec: 50289
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 28 +--
1 file changed, 25 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index b45185b80bec..196d9eb3a77b 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3506,13 +3506,19 @@ static bool icl_get_combo_phy_dpll(struct
intel_atomic_state *state,
return false;
}
- if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A)
+ if (IS_ROCKETLAKE(dev_priv)) {
dpll_mask =
BIT(DPLL_ID_EHL_DPLL4) |
BIT(DPLL_ID_ICL_DPLL1) |
BIT(DPLL_ID_ICL_DPLL0);
- else
+ } else if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A) {
+ dpll_mask =
+ BIT(DPLL_ID_EHL_DPLL4) |
+ BIT(DPLL_ID_ICL_DPLL1) |
+ BIT(DPLL_ID_ICL_DPLL0);
+ } else {
dpll_mask = BIT(DPLL_ID_ICL_DPLL1) | BIT(DPLL_ID_ICL_DPLL0);
+ }
port_dpll->pll = intel_find_shared_dpll(state, crtc,
&port_dpll->hw_state,
@@ -4275,6 +4281,20 @@ static const struct intel_dpll_mgr tgl_pll_mgr = {
.dump_hw_state = icl_dump_hw_state,
};
+static const struct dpll_info rkl_plls[] = {
+ { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
+ { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
+ { "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 },
+ { },
+};
+
+static const struct intel_dpll_mgr rkl_pll_mgr = {
+ .dpll_info = rkl_plls,
+ .get_dplls = icl_get_dplls,
+ .put_dplls = icl_put_dplls,
+ .dump_hw_state = icl_dump_hw_state,
+};
+
/**
* intel_shared_dpll_init - Initialize shared DPLLs
* @dev: drm device
@@ -4288,7 +4308,9 @@ void intel_shared_dpll_init(struct drm_device *dev)
const struct dpll_info *dpll_info;
int i;
- if (INTEL_GEN(dev_priv) >= 12)
+ if (IS_ROCKETLAKE(dev_priv))
+ dpll_mgr = &rkl_pll_mgr;
+ else if (INTEL_GEN(dev_priv) >= 12)
dpll_mgr = &tgl_pll_mgr;
else if (IS_ELKHARTLAKE(dev_priv))
dpll_mgr = &ehl_pll_mgr;
--
2.24.1
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[Intel-gfx] [PATCH v2 14/22] drm/i915/rkl: provide port/phy mapping for vbt
From: Lucas De Marchi
RKL uses the DDI A, DDI B, DDI USBC1, DDI USBC2 from the DE point of
view, so all DDI/pipe/transcoder register use these indexes to refer to
them. Combo phy and IO functions follow another namespace that we keep
as "enum phy". The VBT in theory would use the DE point of view, but
that does not happen in practice.
Provide a table to convert the child devices to the "correct" port
numbering we use. Now this is the output we get while reading the VBT:
DDIA:
[drm:intel_bios_port_aux_ch [i915]] using AUX A for port A (VBT)
[drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:275:DDI A]
[drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on
[ENCODER:275:DDI A]
[drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x1 for port A (VBT)
DDIB:
[drm:intel_bios_port_aux_ch [i915]] using AUX B for port B (platform default)
[drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on
[ENCODER:291:DDI B]
[drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x2 for port B (VBT)
DDI USBC1:
[drm:intel_bios_port_aux_ch [i915]] using AUX D for port D (VBT)
[drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:295:DDI D]
[drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on
[ENCODER:295:DDI D]
[drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x3 for port D (VBT)
DDI USBC2:
[drm:intel_bios_port_aux_ch [i915]] using AUX E for port E (VBT)
[drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:306:DDI E]
[drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on
[ENCODER:306:DDI E]
[drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x9 for port E (VBT)
Cc: Clinton Taylor
Cc: Aditya Swarup
Signed-off-by: Lucas De Marchi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_bios.c | 72 ---
1 file changed, 51 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 839124647202..4f1a72a90b8f 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1619,30 +1619,18 @@ static u8 map_ddc_pin(struct drm_i915_private
*dev_priv, u8 vbt_pin)
return 0;
}
-static enum port dvo_port_to_port(u8 dvo_port)
+static enum port __dvo_port_to_port(int n_ports, int n_dvo,
+ const int port_mapping[][3], u8 dvo_port)
{
- /*
-* Each DDI port can have more than one value on the "DVO Port" field,
-* so look for all the possible values for each port.
-*/
- static const int dvo_ports[][3] = {
- [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1},
- [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1},
- [PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1},
- [PORT_D] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1},
- [PORT_E] = { DVO_PORT_CRT, DVO_PORT_HDMIE, DVO_PORT_DPE},
- [PORT_F] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1},
- [PORT_G] = { DVO_PORT_HDMIG, DVO_PORT_DPG, -1},
- };
enum port port;
int i;
- for (port = PORT_A; port < ARRAY_SIZE(dvo_ports); port++) {
- for (i = 0; i < ARRAY_SIZE(dvo_ports[port]); i++) {
- if (dvo_ports[port][i] == -1)
+ for (port = PORT_A; port < n_ports; port++) {
+ for (i = 0; i < n_dvo; i++) {
+ if (port_mapping[port][i] == -1)
break;
- if (dvo_port == dvo_ports[port][i])
+ if (dvo_port == port_mapping[port][i])
return port;
}
}
@@ -1650,6 +1638,48 @@ static enum port dvo_port_to_port(u8 dvo_port)
return PORT_NONE;
}
+static enum port dvo_port_to_port(struct drm_i915_private *dev_priv,
+ u8 dvo_port)
+{
+ /*
+* Each DDI port can have more than one value on the "DVO Port" field,
+* so look for all the possible values for each port.
+*/
+ static const int port_mapping[][3] = {
+ [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
+ [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },
+ [PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
+ [PORT_D] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
+ [PORT_E] = { DVO_PORT_CRT, DVO_PORT_HDMIE, -1 },
+ [PORT_F] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1 },
+ [PORT_G] = { DVO_PORT_HDMIG, DVO_PORT_DPG, -1 },
+ };
+ /*
+* Bspec lists the ports as A, B, C, D - however internally in our
+* driver we keep them as PORT_A, PORT_B, PORT_D and PORT_E so the
+* registers in Display Engine match the right offsets. Apply the
+* mapping here to translate from VBT to internal convention.
+*/
+ static const int rkl_port_mapping[][3]
[Intel-gfx] [PATCH v2 10/22] drm/i915/rkl: RKL only uses PHY_MISC for PHY's A and B
Since the number of platforms with this restriction are growing, let's
separate out the platform logic into a has_phy_misc() function.
Bspec: 50107
Signed-off-by: Matt Roper
---
.../gpu/drm/i915/display/intel_combo_phy.c| 30 +++
1 file changed, 17 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c
b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 9ff05ec12115..43d8784f6fa0 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -181,11 +181,25 @@ static void cnl_combo_phys_uninit(struct drm_i915_private
*dev_priv)
intel_de_write(dev_priv, CHICKEN_MISC_2, val);
}
+static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy)
+{
+ /*
+* Some platforms only expect PHY_MISC to be programmed for PHY-A and
+* PHY-B and may not even have instances of the register for the
+* other combo PHY's.
+*/
+ if (IS_ELKHARTLAKE(i915) ||
+ IS_ROCKETLAKE(i915))
+ return phy < PHY_C;
+
+ return true;
+}
+
static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv,
enum phy phy)
{
/* The PHY C added by EHL has no PHY_MISC register */
- if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C)
+ if (!has_phy_misc(dev_priv, phy))
return intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) &
COMP_INIT;
else
return !(intel_de_read(dev_priv, ICL_PHY_MISC(phy)) &
@@ -317,12 +331,7 @@ static void icl_combo_phys_init(struct drm_i915_private
*dev_priv)
continue;
}
- /*
-* Although EHL adds a combo PHY C, there's no PHY_MISC
-* register for it and no need to program the
-* DE_IO_COMP_PWR_DOWN setting on PHY C.
-*/
- if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C)
+ if (!has_phy_misc(dev_priv, phy))
goto skip_phy_misc;
/*
@@ -376,12 +385,7 @@ static void icl_combo_phys_uninit(struct drm_i915_private
*dev_priv)
"Combo PHY %c HW state changed unexpectedly\n",
phy_name(phy));
- /*
-* Although EHL adds a combo PHY C, there's no PHY_MISC
-* register for it and no need to program the
-* DE_IO_COMP_PWR_DOWN setting on PHY C.
-*/
- if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C)
+ if (!has_phy_misc(dev_priv, phy))
goto skip_phy_misc;
val = intel_de_read(dev_priv, ICL_PHY_MISC(phy));
--
2.24.1
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[Intel-gfx] [PATCH v2 13/22] drm/i915/rkl: Setup ports/phys
RKL uses DDI's A, B, TC1, and TC2 which need to map to combo PHY's A-D.
Bspec: 49181
Cc: Imre Deak
Cc: Aditya Swarup
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_display.c | 34
drivers/gpu/drm/i915/i915_reg.h | 4 ++-
2 files changed, 24 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index e30b765d271d..fcfc3812ef28 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7212,30 +7212,33 @@ bool intel_phy_is_combo(struct drm_i915_private
*dev_priv, enum phy phy)
{
if (phy == PHY_NONE)
return false;
-
- if (IS_ELKHARTLAKE(dev_priv))
+ else if (IS_ROCKETLAKE(dev_priv))
+ return phy <= PHY_D;
+ else if (IS_ELKHARTLAKE(dev_priv))
return phy <= PHY_C;
-
- if (INTEL_GEN(dev_priv) >= 11)
+ else if (INTEL_GEN(dev_priv) >= 11)
return phy <= PHY_B;
-
- return false;
+ else
+ return false;
}
bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
{
- if (INTEL_GEN(dev_priv) >= 12)
+ if (IS_ROCKETLAKE(dev_priv))
+ return false;
+ else if (INTEL_GEN(dev_priv) >= 12)
return phy >= PHY_D && phy <= PHY_I;
-
- if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
+ else if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
return phy >= PHY_C && phy <= PHY_F;
-
- return false;
+ else
+ return false;
}
enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
{
- if (IS_ELKHARTLAKE(i915) && port == PORT_D)
+ if (IS_ROCKETLAKE(i915) && port >= PORT_D)
+ return (enum phy)port - 1;
+ else if (IS_ELKHARTLAKE(i915) && port == PORT_D)
return PHY_A;
return (enum phy)port;
@@ -16691,7 +16694,12 @@ static void intel_setup_outputs(struct
drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
return;
- if (INTEL_GEN(dev_priv) >= 12) {
+ if (IS_ROCKETLAKE(dev_priv)) {
+ intel_ddi_init(dev_priv, PORT_A);
+ intel_ddi_init(dev_priv, PORT_B);
+ intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */
+ intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */
+ } else if (INTEL_GEN(dev_priv) >= 12) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
intel_ddi_init(dev_priv, PORT_D);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 516bfbad0eb9..e1db65dc5a87 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1869,9 +1869,11 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define _ICL_COMBOPHY_A0x162000
#define _ICL_COMBOPHY_B0x6C000
#define _EHL_COMBOPHY_C0x16
+#define _RKL_COMBOPHY_D0x161000
#define _ICL_COMBOPHY(phy) _PICK(phy, _ICL_COMBOPHY_A, \
_ICL_COMBOPHY_B, \
- _EHL_COMBOPHY_C)
+ _EHL_COMBOPHY_C, \
+ _RKL_COMBOPHY_D)
/* CNL/ICL Port CL_DW registers */
#define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
--
2.24.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/24] perf/core: Only copy-to-user after completely unlocking all locks, v3.
== Series Details ==
Series: series starting with [01/24] perf/core: Only copy-to-user after
completely unlocking all locks, v3.
URL : https://patchwork.freedesktop.org/series/76816/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8405_full -> Patchwork_17539_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_17539_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_17539_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_17539_full:
### IGT changes ###
Possible regressions
* igt@gem_close@many-handles-one-vma:
- shard-glk: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8405/shard-glk2/igt@gem_cl...@many-handles-one-vma.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17539/shard-glk5/igt@gem_cl...@many-handles-one-vma.html
- shard-apl: [PASS][3] -> [FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8405/shard-apl4/igt@gem_cl...@many-handles-one-vma.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17539/shard-apl8/igt@gem_cl...@many-handles-one-vma.html
- shard-skl: [PASS][5] -> [FAIL][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8405/shard-skl9/igt@gem_cl...@many-handles-one-vma.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17539/shard-skl5/igt@gem_cl...@many-handles-one-vma.html
- shard-tglb: [PASS][7] -> [FAIL][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8405/shard-tglb2/igt@gem_cl...@many-handles-one-vma.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17539/shard-tglb6/igt@gem_cl...@many-handles-one-vma.html
- shard-kbl: [PASS][9] -> [FAIL][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8405/shard-kbl7/igt@gem_cl...@many-handles-one-vma.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17539/shard-kbl1/igt@gem_cl...@many-handles-one-vma.html
- shard-hsw: [PASS][11] -> [FAIL][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8405/shard-hsw7/igt@gem_cl...@many-handles-one-vma.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17539/shard-hsw1/igt@gem_cl...@many-handles-one-vma.html
- shard-snb: [PASS][13] -> [FAIL][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8405/shard-snb5/igt@gem_cl...@many-handles-one-vma.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17539/shard-snb5/igt@gem_cl...@many-handles-one-vma.html
- shard-iclb: [PASS][15] -> [FAIL][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8405/shard-iclb4/igt@gem_cl...@many-handles-one-vma.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17539/shard-iclb3/igt@gem_cl...@many-handles-one-vma.html
* igt@i915_selftest@live@gem_contexts:
- shard-kbl: [PASS][17] -> [DMESG-WARN][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8405/shard-kbl2/igt@i915_selftest@live@gem_contexts.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17539/shard-kbl3/igt@i915_selftest@live@gem_contexts.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_exec_reloc@basic-many-active@vcs1}:
- shard-tglb: [FAIL][19] ([i915#1815]) -> [FAIL][20] +1 similar
issue
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8405/shard-tglb6/igt@gem_exec_reloc@basic-many-act...@vcs1.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17539/shard-tglb2/igt@gem_exec_reloc@basic-many-act...@vcs1.html
* {igt@gem_exec_reloc@basic-parallel}:
- shard-kbl: [PASS][21] -> [TIMEOUT][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8405/shard-kbl6/igt@gem_exec_re...@basic-parallel.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17539/shard-kbl7/igt@gem_exec_re...@basic-parallel.html
- shard-tglb: [PASS][23] -> [TIMEOUT][24]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8405/shard-tglb2/igt@gem_exec_re...@basic-parallel.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17539/shard-tglb8/igt@gem_exec_re...@basic-parallel.html
- shard-apl: [PASS][25] -> [TIMEOUT][26]
[25]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8405/shard-apl7/igt@gem_exec_re...@basic-parallel.html
[26]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17539/shard-apl8/igt@gem_exec_re...@basic-parallel.html
- shard-iclb: [PASS][27] -> [TIMEOUT][28]
[27]:
[Intel-gfx] ✗ Fi.CI.BUILD: failure for Introduce Rocket Lake (rev3)
== Series Details == Series: Introduce Rocket Lake (rev3) URL : https://patchwork.freedesktop.org/series/76826/ State : failure == Summary == Applying: drm/i915/rkl: Add RKL platform info and PCI ids Applying: x86/gpu: add RKL stolen memory support Applying: drm/i915/rkl: Re-use TGL GuC/HuC firmware Applying: drm/i915/rkl: Load DMC firmware for Rocket Lake Applying: drm/i915/rkl: Add PCH support Applying: drm/i915/rkl: Update memory bandwidth parameters Applying: drm/i915/rkl: Limit number of universal planes to 5 Applying: drm/i915/rkl: Add power well support Applying: drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2 Applying: drm/i915/rkl: RKL only uses PHY_MISC for PHY's A and B Applying: drm/i915/rkl: Add cdclk support error: patch fragment without header at line 14: @@ -1414,7 +1448,8 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv, error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0011 drm/i915/rkl: Add cdclk support When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Show per-engine default property values in sysfs
Quoting Chris Wilson (2020-04-23 15:26:04) > Why? Actually this would be quite useful! > /sys/class/drm/card0/engine/rcs0/ > ├── capabilities > ├── class > ├── .defaults > │ ├── heartbeat_interval_ms > │ ├── max_busywait_duration_ns > │ ├── preempt_timeout_ms > │ ├── stop_timeout_ms > │ └── timeslice_duration_ms > ├── heartbeat_interval_ms > ├── instance > ├── known_capabilities > ├── max_busywait_duration_ns > ├── mmio_base > ├── name > ├── preempt_timeout_ms > ├── stop_timeout_ms > └── timeslice_duration_ms > > Signed-off-by: Chris Wilson > Cc: Joonas Lahtinen > Cc: Tvrtko Ursulin ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl+: Fix interrupt handling for DP AUX transactions
Hi Imre, Yes, I have addressed the issue and re-reported. Thanks, Lakshmi. -Original Message- From: Imre Deak Sent: Monday, May 4, 2020 10:30 PM To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana Subject: Re: ✗ Fi.CI.IGT: failure for drm/i915/tgl+: Fix interrupt handling for DP AUX transactions Hi Lakshmi, On Mon, May 04, 2020 at 06:31:06PM +, Patchwork wrote: > == Series Details == > > Series: drm/i915/tgl+: Fix interrupt handling for DP AUX transactions > URL : https://patchwork.freedesktop.org/series/76892/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_8416_full -> Patchwork_17564_full > > > Summary > --- > > **FAILURE** > > Serious unknown changes coming with Patchwork_17564_full absolutely need to > be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_17564_full, please notify your bug team to allow > them > to document this new failure mode, which will reduce false positives in CI. > > > > Possible new issues > --- > > Here are the unknown changes that may have been introduced in > Patchwork_17564_full: > > ### IGT changes ### > > Possible regressions > > * igt@kms_atomic_transition@plane-toggle-modeset-transition: > - shard-apl: [PASS][1] -> [INCOMPLETE][2] >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-apl8/igt@kms_atomic_transit...@plane-toggle-modeset-transition.html >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17564/shard-apl8/ig > t@kms_atomic_transit...@plane-toggle-modeset-transition.html On GEN9 nothing changed, so this must be unrelated. I couldn't find any similar issues on gitlab, so could you add there a new ticket for it? Thanks, Imre > > > Known issues > > > Here are the changes found in Patchwork_17564_full that come from known > issues: > > ### IGT changes ### > > Issues hit > > * igt@gem_exec_flush@basic-wb-ro-before-default: > - shard-hsw: [PASS][3] -> [INCOMPLETE][4] ([i915#61]) >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-hsw6/igt@gem_exec_fl...@basic-wb-ro-before-default.html >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17564/shard-hsw1/ig > t@gem_exec_fl...@basic-wb-ro-before-default.html > > * igt@gem_workarounds@suspend-resume-fd: > - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-apl4/igt@gem_workarou...@suspend-resume-fd.html >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17564/shard-apl6/ig > t@gem_workarou...@suspend-resume-fd.html > > * igt@kms_cursor_crc@pipe-c-cursor-64x21-onscreen: > - shard-glk: [PASS][7] -> [FAIL][8] ([i915#54]) >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-glk8/igt@kms_cursor_...@pipe-c-cursor-64x21-onscreen.html >[8]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17564/shard-glk2/ig > t@kms_cursor_...@pipe-c-cursor-64x21-onscreen.html > > * igt@kms_cursor_edge_walk@pipe-a-256x256-bottom-edge: > - shard-apl: [PASS][9] -> [FAIL][10] ([i915#70] / [i915#95]) >[9]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-apl3/igt@kms_cursor_edge_w...@pipe-a-256x256-bottom-edge.html >[10]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17564/shard-apl4/ig > t@kms_cursor_edge_w...@pipe-a-256x256-bottom-edge.html > > * igt@kms_flip_tiling@flip-changes-tiling-y: > - shard-apl: [PASS][11] -> [FAIL][12] ([i915#95]) >[11]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-apl1/igt@kms_flip_til...@flip-changes-tiling-y.html >[12]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17564/shard-apl3/igt@kms_flip_til...@flip-changes-tiling-y.html > - shard-kbl: [PASS][13] -> [FAIL][14] ([i915#699] / [i915#93] / > [i915#95]) >[13]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-kbl1/igt@kms_flip_til...@flip-changes-tiling-y.html >[14]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17564/shard-kbl6/ig > t@kms_flip_til...@flip-changes-tiling-y.html > > * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render: > - shard-skl: [PASS][15] -> [FAIL][16] ([i915#49]) >[15]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-skl9/igt@kms_frontbuffer_track...@psr-1p-primscrn-pri-indfb-draw-render.html >[16]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17564/shard-skl8/ig > t@kms_frontbuffer_track...@psr-1p-primscrn-pri-indfb-draw-render.html > > * igt@kms_pipe_crc_basic@hang-read-crc-pipe-a: > - shard-snb: [PASS][17] -> [SKIP][18] ([fdo#109271]) +3 similar > issues >[17]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_D
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/tgl+: Fix interrupt handling for DP AUX transactions
== Series Details == Series: drm/i915/tgl+: Fix interrupt handling for DP AUX transactions URL : https://patchwork.freedesktop.org/series/76892/ State : success == Summary == CI Bug Log - changes from CI_DRM_8416_full -> Patchwork_17564_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_17564_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_flush@basic-wb-ro-before-default: - shard-hsw: [PASS][1] -> [INCOMPLETE][2] ([i915#61]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-hsw6/igt@gem_exec_fl...@basic-wb-ro-before-default.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17564/shard-hsw1/igt@gem_exec_fl...@basic-wb-ro-before-default.html * igt@gem_workarounds@suspend-resume-fd: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-apl4/igt@gem_workarou...@suspend-resume-fd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17564/shard-apl6/igt@gem_workarou...@suspend-resume-fd.html * igt@kms_atomic_transition@plane-toggle-modeset-transition: - shard-apl: [PASS][5] -> [INCOMPLETE][6] ([CI#80]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-apl8/igt@kms_atomic_transit...@plane-toggle-modeset-transition.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17564/shard-apl8/igt@kms_atomic_transit...@plane-toggle-modeset-transition.html * igt@kms_cursor_crc@pipe-c-cursor-64x21-onscreen: - shard-glk: [PASS][7] -> [FAIL][8] ([i915#54]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-glk8/igt@kms_cursor_...@pipe-c-cursor-64x21-onscreen.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17564/shard-glk2/igt@kms_cursor_...@pipe-c-cursor-64x21-onscreen.html * igt@kms_cursor_edge_walk@pipe-a-256x256-bottom-edge: - shard-apl: [PASS][9] -> [FAIL][10] ([i915#70] / [i915#95]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-apl3/igt@kms_cursor_edge_w...@pipe-a-256x256-bottom-edge.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17564/shard-apl4/igt@kms_cursor_edge_w...@pipe-a-256x256-bottom-edge.html * igt@kms_flip_tiling@flip-changes-tiling-y: - shard-apl: [PASS][11] -> [FAIL][12] ([i915#95]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-apl1/igt@kms_flip_til...@flip-changes-tiling-y.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17564/shard-apl3/igt@kms_flip_til...@flip-changes-tiling-y.html - shard-kbl: [PASS][13] -> [FAIL][14] ([i915#699] / [i915#93] / [i915#95]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-kbl1/igt@kms_flip_til...@flip-changes-tiling-y.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17564/shard-kbl6/igt@kms_flip_til...@flip-changes-tiling-y.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#49]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-skl9/igt@kms_frontbuffer_track...@psr-1p-primscrn-pri-indfb-draw-render.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17564/shard-skl8/igt@kms_frontbuffer_track...@psr-1p-primscrn-pri-indfb-draw-render.html * igt@kms_pipe_crc_basic@hang-read-crc-pipe-a: - shard-snb: [PASS][17] -> [SKIP][18] ([fdo#109271]) +3 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-snb6/igt@kms_pipe_crc_ba...@hang-read-crc-pipe-a.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17564/shard-snb2/igt@kms_pipe_crc_ba...@hang-read-crc-pipe-a.html * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145] / [i915#265]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-skl9/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17564/shard-skl8/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html * igt@kms_psr@psr2_primary_mmap_gtt: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17564/shard-iclb5/igt@kms_psr@psr2_primary_mmap_gtt.html * igt@kms_vblank@pipe-b-ts-continuation-suspend: - shard-kbl: [PASS][23] -> [DMESG-WARN][24] ([i915#180]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-kbl3/igt@kms_vbl...@pipe-b-ts-continuation-suspend.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17564/shard-k
[Intel-gfx] ✓ Fi.CI.BAT: success for Prefer drm_WARN* over WARN* (rev3)
== Series Details == Series: Prefer drm_WARN* over WARN* (rev3) URL : https://patchwork.freedesktop.org/series/75543/ State : success == Summary == CI Bug Log - changes from CI_DRM_8424 -> Patchwork_17575 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17575/index.html Known issues Here are the changes found in Patchwork_17575 that come from known issues: ### IGT changes ### Warnings * igt@i915_pm_rpm@module-reload: - fi-kbl-x1275: [FAIL][1] ([i915#62]) -> [SKIP][2] ([fdo#109271]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8424/fi-kbl-x1275/igt@i915_pm_...@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17575/fi-kbl-x1275/igt@i915_pm_...@module-reload.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 Participating hosts (51 -> 44) -- Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8424 -> Patchwork_17575 CI-20190529: 20190529 CI_DRM_8424: 69ecf47ef1aabcdc8a4e070584d0a717bbabf4fe @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5628: 652a3fd8966345fa5498904ce80a2027a6782783 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17575: 5f984d13c80e508c7cdc67f51e18f102d5ac309f @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 5f984d13c80e drm/i915/runtime_pm: Prefer drm_WARN* over WARN* fd2a05cb030c drm/i915/pm: Prefer drm_WARN_ON over WARN_ON adfccabbfb60 drm/i915/pmu: Prefer drm_WARN_ON over WARN_ON 57cd2a85fcd4 drm/i915/i915_drv: Prefer drm_WARN_ON over WARN_ON f41a15c05f60 drm/i915/gem: Prefer drm_WARN* over WARN* 700fd559057c drm/i915/display/tc: Prefer drm_WARN_ON over WARN_ON 6f400e74f722 drm/i915/display/sdvo: Prefer drm_WARN* over WARN* 1007d6a2e1d7 drm/i915/display/dp: Prefer drm_WARN* over WARN* e13909e4cad6 drm/i915/display/display_power: Prefer drm_WARN_ON over WARN_ON == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17575/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Prefer drm_WARN* over WARN* (rev3)
== Series Details == Series: Prefer drm_WARN* over WARN* (rev3) URL : https://patchwork.freedesktop.org/series/75543/ State : warning == Summary == $ dim checkpatch origin/drm-tip e13909e4cad6 drm/i915/display/display_power: Prefer drm_WARN_ON over WARN_ON -:19: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #19: + struct drm_i915_private *i915 = container_of(T, struct drm_i915_private, power_domains); total: 0 errors, 1 warnings, 0 checks, 71 lines checked 1007d6a2e1d7 drm/i915/display/dp: Prefer drm_WARN* over WARN* 6f400e74f722 drm/i915/display/sdvo: Prefer drm_WARN* over WARN* 700fd559057c drm/i915/display/tc: Prefer drm_WARN_ON over WARN_ON f41a15c05f60 drm/i915/gem: Prefer drm_WARN* over WARN* -:24: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #24: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1630: + if (drm_WARN_ONCE(&i915->drm, err, "Unexpected failure to bind target VMA!")) -:50: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "!obj->userptr.mm" #50: FILE: drivers/gpu/drm/i915/gem/i915_gem_userptr.c:238: + if (drm_WARN_ON(obj->base.dev, obj->userptr.mm == NULL)) total: 0 errors, 0 warnings, 2 checks, 25 lines checked 57cd2a85fcd4 drm/i915/i915_drv: Prefer drm_WARN_ON over WARN_ON -:25: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #25: FILE: drivers/gpu/drm/i915/i915_drv.h:1652: +#define INTEL_DISPLAY_ENABLED(dev_priv) \ + (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !i915_modparams.disable_display) -:26: WARNING:LONG_LINE: line over 100 characters #26: FILE: drivers/gpu/drm/i915/i915_drv.h:1653: + (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !i915_modparams.disable_display) total: 0 errors, 1 warnings, 1 checks, 9 lines checked adfccabbfb60 drm/i915/pmu: Prefer drm_WARN_ON over WARN_ON fd2a05cb030c drm/i915/pm: Prefer drm_WARN_ON over WARN_ON 5f984d13c80e drm/i915/runtime_pm: Prefer drm_WARN* over WARN* -:17: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #17: + struct drm_i915_private *i915 = container_of(T, struct drm_i915_private, runtime_pm); total: 0 errors, 1 warnings, 0 checks, 89 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/perf: Add support for multi context perf queries (rev6)
== Series Details == Series: drm/i915/perf: Add support for multi context perf queries (rev6) URL : https://patchwork.freedesktop.org/series/76588/ State : success == Summary == CI Bug Log - changes from CI_DRM_8417_full -> Patchwork_17566_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_17566_full that come from known issues: ### IGT changes ### Issues hit * igt@gen9_exec_parse@allowed-all: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([i915#716]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8417/shard-apl2/igt@gen9_exec_pa...@allowed-all.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17566/shard-apl1/igt@gen9_exec_pa...@allowed-all.html * igt@kms_cursor_crc@pipe-b-cursor-suspend: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8417/shard-apl4/igt@kms_cursor_...@pipe-b-cursor-suspend.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17566/shard-apl6/igt@kms_cursor_...@pipe-b-cursor-suspend.html * igt@kms_cursor_edge_walk@pipe-a-256x256-bottom-edge: - shard-apl: [PASS][5] -> [FAIL][6] ([i915#70] / [i915#95]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8417/shard-apl1/igt@kms_cursor_edge_w...@pipe-a-256x256-bottom-edge.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17566/shard-apl4/igt@kms_cursor_edge_w...@pipe-a-256x256-bottom-edge.html * igt@kms_flip_tiling@flip-changes-tiling-y: - shard-apl: [PASS][7] -> [FAIL][8] ([i915#95]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8417/shard-apl6/igt@kms_flip_til...@flip-changes-tiling-y.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17566/shard-apl7/igt@kms_flip_til...@flip-changes-tiling-y.html - shard-kbl: [PASS][9] -> [FAIL][10] ([i915#699] / [i915#93] / [i915#95]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8417/shard-kbl6/igt@kms_flip_til...@flip-changes-tiling-y.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17566/shard-kbl1/igt@kms_flip_til...@flip-changes-tiling-y.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([i915#180]) +4 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8417/shard-kbl7/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17566/shard-kbl1/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-kbl: [PASS][13] -> [FAIL][14] ([fdo#108145] / [i915#265] / [i915#93] / [i915#95]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8417/shard-kbl6/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17566/shard-kbl6/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][15] -> [FAIL][16] ([fdo#108145] / [i915#265]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8417/shard-skl2/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17566/shard-skl10/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html * igt@kms_plane_lowres@pipe-a-tiling-x: - shard-glk: [PASS][17] -> [FAIL][18] ([i915#899]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8417/shard-glk6/igt@kms_plane_low...@pipe-a-tiling-x.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17566/shard-glk6/igt@kms_plane_low...@pipe-a-tiling-x.html * igt@kms_psr@psr2_primary_page_flip: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8417/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17566/shard-iclb1/igt@kms_psr@psr2_primary_page_flip.html * igt@kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [PASS][21] -> [DMESG-WARN][22] ([i915#180] / [i915#93] / [i915#95]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8417/shard-kbl7/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17566/shard-kbl2/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html * igt@kms_vblank@pipe-c-ts-continuation-suspend: - shard-kbl: [PASS][23] -> [INCOMPLETE][24] ([i915#155] / [i915#794]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8417/shard-kbl7/igt@kms_vbl...@pipe-c-ts-continuation-suspend.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17566/shard-kbl2/igt@kms_vbl...@pipe-c-ts-continuation-suspend.html
[Intel-gfx] [PATCH v2] drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout
RKL uses a slightly different bit layout for the DPCLKA_CFGCR0 register.
v2:
- Fix inverted mask application when updating ICL_DPCLKA_CFGCR0
- Checkpatch style fixes
Bspec: 50287
Cc: Aditya Swarup
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_ddi.c | 18 +++---
drivers/gpu/drm/i915/display/intel_display.c | 15 ---
drivers/gpu/drm/i915/i915_reg.h | 6 ++
3 files changed, 33 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 5601673c3f30..0ab03282c397 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2732,7 +2732,9 @@ hsw_set_signal_levels(struct intel_dp *intel_dp)
static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
enum phy phy)
{
- if (intel_phy_is_combo(dev_priv, phy)) {
+ if (IS_ROCKETLAKE(dev_priv)) {
+ return RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
+ } else if (intel_phy_is_combo(dev_priv, phy)) {
return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
} else if (intel_phy_is_tc(dev_priv, phy)) {
enum tc_port tc_port = intel_port_to_tc(dev_priv,
@@ -2759,6 +2761,16 @@ static void icl_map_plls_to_ports(struct intel_encoder
*encoder,
(val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
if (intel_phy_is_combo(dev_priv, phy)) {
+ u32 mask, sel;
+
+ if (IS_ROCKETLAKE(dev_priv)) {
+ mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+ sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
+ } else {
+ mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+ sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
+ }
+
/*
* Even though this register references DDIs, note that we
* want to pass the PHY rather than the port (DDI). For
@@ -2769,8 +2781,8 @@ static void icl_map_plls_to_ports(struct intel_encoder
*encoder,
* Clock Select chooses the PLL for both DDIA and DDID and
* drives port A in all cases."
*/
- val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
- val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
+ val &= ~mask;
+ val |= sel;
intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 7d7a5b66f2cb..e30b765d271d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10773,9 +10773,18 @@ static void icl_get_ddi_pll(struct drm_i915_private
*dev_priv, enum port port,
u32 temp;
if (intel_phy_is_combo(dev_priv, phy)) {
- temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) &
- ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
- id = temp >> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
+ u32 mask, shift;
+
+ if (IS_ROCKETLAKE(dev_priv)) {
+ mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+ shift = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
+ } else {
+ mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+ shift = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
+ }
+
+ temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) & mask;
+ id = temp >> shift;
port_dpll_id = ICL_PORT_DPLL_DEFAULT;
} else if (intel_phy_is_tc(dev_priv, phy)) {
u32 clk_sel = intel_de_read(dev_priv, DDI_CLK_SEL(port)) &
DDI_CLK_SEL_MASK;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2266f9fc2d79..516bfbad0eb9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10163,12 +10163,18 @@ enum skl_power_gate {
#define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)(1 << _PICK(phy, 10, 11, 24))
+#define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)REG_BIT((phy) + 10)
#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < PORT_TC4 ? \
(tc_port) + 12 : \
(tc_port) - PORT_TC4 +
21))
#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2)
#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 <<
ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) <<
ICL_DPCLKA_CFGCR0_DDI_CLK_SEL
Re: [Intel-gfx] [PATCH] drm/i915: HDCP: retry link integrity check on failure
On Mon, May 4, 2020 at 1:32 PM Oliver Barta wrote:
>
> From: Oliver Barta
>
> A single Ri mismatch doesn't automatically mean that the link integrity
> is broken. Update and check of Ri and Ri' are done asynchronously. In
> case an update happens just between the read of Ri' and the check against
> Ri there will be a mismatch even if the link integrity is fine otherwise.
>
> Signed-off-by: Oliver Barta
> ---
> drivers/gpu/drm/i915/display/intel_hdmi.c | 19 ---
> 1 file changed, 16 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 010f37240710..3156fde392f2 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -1540,7 +1540,7 @@ int intel_hdmi_hdcp_toggle_signalling(struct
> intel_digital_port *intel_dig_port,
> }
>
> static
> -bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
> +bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port
> *intel_dig_port)
> {
> struct drm_i915_private *i915 =
> to_i915(intel_dig_port->base.base.dev);
> struct intel_connector *connector =
> @@ -1563,8 +1563,7 @@ bool intel_hdmi_hdcp_check_link(struct
> intel_digital_port *intel_dig_port)
> if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder,
> port)) &
> (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) ==
> (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
Why doesn't the wait_for catch this?
Sean
> - drm_err(&i915->drm,
> - "Ri' mismatch detected, link check failed (%x)\n",
> + drm_dbg_kms(&i915->drm, "Ri' mismatch detected (%x)\n",
> intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder,
> port)));
> return false;
> @@ -1572,6 +1571,20 @@ bool intel_hdmi_hdcp_check_link(struct
> intel_digital_port *intel_dig_port)
> return true;
> }
>
> +static
> +bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
> +{
> + struct drm_i915_private *i915 =
> to_i915(intel_dig_port->base.base.dev);
> + int retry;
> +
> + for (retry = 0; retry < 3; retry++)
> + if (intel_hdmi_hdcp_check_link_once(intel_dig_port))
> + return true;
> +
> + drm_err(&i915->drm, "Link check failed\n");
> + return false;
> +}
> +
> struct hdcp2_hdmi_msg_timeout {
> u8 msg_id;
> u16 timeout;
> --
> 2.20.1
>
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Re: [Intel-gfx] [PATCH 11/23] drm/i915/rkl: Add cdclk support
On Mon, May 04, 2020 at 10:33:41AM -0700, Matt Roper wrote:
> On Sat, May 02, 2020 at 09:26:51AM -0700, Khor, Swee Aun wrote:
> > Hi Matt,
> > The follow cdclk doesn't looked right, isn’t it should be 96000 and 54
> > according to their respective divider and ratio?
> >
> > +{ .refclk = 19200, .cdclk = 192000, .divider = 3, .ratio = 15 },
> >
> > +{ .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 45 },
> >
>
> Yeah, you're right. The first one appears to have been removed from the
> bspec now and the second one appears to be a typo on my part (ratio
> should be 46 instead of 45).
>
> Looks like there have been a couple other recent modifications to the
> bspec as well that I should update this patch to capture. Thanks for
> pointing that out!
Actually, it looks like the latest updates in the bspec have now made
the RKL cdclk table identical to the TGL/ICL table. So we should be
able to drop this patch completely now.
Matt
>
>
> Matt
>
> >
> > Regards,
> > SweeAun
> >
> > -Original Message-
> > From: Intel-gfx On Behalf Of Matt
> > Roper
> > Sent: Saturday, May 2, 2020 1:08 AM
> > To: intel-gfx@lists.freedesktop.org
> > Subject: [Intel-gfx] [PATCH 11/23] drm/i915/rkl: Add cdclk support
> >
> > Note that the 192000 clock frequencies can be achieved with different pairs
> > of ratio+divider, which is something we haven't encountered before. If any
> > of those ratios were common with other legal cdclk values, then it would
> > mean we could avoid triggering full modesets if we just needed to change
> > the divider. However at the moment there don't appear to be any valid
> > cdclks that share the same ratio so we can't take advantage of this and it
> > doesn't really matter which approach we use to achieve the 192000 cdclk.
> > For now our driver functions that operate on the table will just always
> > pick the first entry (lower ratio + lower divider).
> >
> > Bspec: 49202
> > Cc: Ville Syrjälä
> > Signed-off-by: Matt Roper
> > ---
> > drivers/gpu/drm/i915/display/intel_cdclk.c | 54 +++---
> > 1 file changed, 48 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index 979a0241fdcb..4ca87260e8ba 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -1230,6 +1230,40 @@ static const struct intel_cdclk_vals
> > icl_cdclk_table[] = {
> > {}
> > };
> >
> > +/*
> > + * RKL has multiple divider+ratio pairs that can hit cdclk=192000. Our
> > + * functions to read these tables will just always pick the first one
> > +which
> > + * should be fine since there's no other valid cdclk value that can be
> > +achieved
> > + * via the same ratio with a different divider (i.e., no opportunity to
> > +avoid a
> > + * full modeset).
> > + */
> > +static const struct intel_cdclk_vals rkl_cdclk_table[] = {
> > +{ .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
> > +{ .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
> > +{ .refclk = 19200, .cdclk = 192000, .divider = 3, .ratio = 15 },
> > +{ .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
> > +{ .refclk = 19200, .cdclk = 326400, .divider = 4, .ratio = 68 },
> > +{ .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> > +{ .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> > +
> > +{ .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
> > +{ .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
> > +{ .refclk = 24000, .cdclk = 192000, .divider = 3, .ratio = 24 },
> > +{ .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
> > +{ .refclk = 24000, .cdclk = 324000, .divider = 4, .ratio = 54 },
> > +{ .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 45 },
> > +{ .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
> > +
> > +{ .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
> > +{ .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
> > +{ .refclk = 38400, .cdclk = 192000, .divider = 3, .ratio = 15 },
> > +{ .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
> > +{ .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 },
> > +{ .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> > +{ .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> > +{}
> > +};
> > +
> > static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int
> > min_cdclk) {
> > const struct intel_cdclk_vals *table = dev_priv->cdclk.table; @@ -1405,8
> > +1439,8 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
> > div = 2;
> > break;
> > case BXT_CDCLK_CD2X_DIV_SEL_1_5:
> > -drm_WARN(&dev_priv->drm,
> > - IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10,
> > +drm_WARN(&dev_priv->drm, IS_GEMINILAKE(dev_priv) ||
> > + (INTEL_GEN(dev_priv) >= 10 && !IS_ROCKETLAKE(dev
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Stop holding onto the pinned_default_state (rev2)
== Series Details == Series: drm/i915/gt: Stop holding onto the pinned_default_state (rev2) URL : https://patchwork.freedesktop.org/series/76738/ State : success == Summary == CI Bug Log - changes from CI_DRM_8422 -> Patchwork_17574 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17574/index.html Known issues Here are the changes found in Patchwork_17574 that come from known issues: ### IGT changes ### Possible fixes * igt@i915_selftest@live@perf: - fi-bwr-2160:[INCOMPLETE][1] ([i915#489]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8422/fi-bwr-2160/igt@i915_selftest@l...@perf.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17574/fi-bwr-2160/igt@i915_selftest@l...@perf.html [i915#489]: https://gitlab.freedesktop.org/drm/intel/issues/489 Participating hosts (52 -> 44) -- Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8422 -> Patchwork_17574 CI-20190529: 20190529 CI_DRM_8422: 0ca0fee447b032331962bc5c717786bdb3594bd9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5628: 652a3fd8966345fa5498904ce80a2027a6782783 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17574: ca23be75c4c21a2a54eec2b4836307b869e4356f @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ca23be75c4c2 drm/i915/gt: Stop holding onto the pinned_default_state == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17574/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] i915/gem_ctx_exec: Exploit resource contention to verify execbuf independence
Even if one client is blocked on a resource, that should not impact
another client.
Signed-off-by: Chris Wilson
---
tests/i915/gem_ctx_exec.c | 122 +-
1 file changed, 121 insertions(+), 1 deletion(-)
diff --git a/tests/i915/gem_ctx_exec.c b/tests/i915/gem_ctx_exec.c
index ad2f9e545..d7cd56424 100644
--- a/tests/i915/gem_ctx_exec.c
+++ b/tests/i915/gem_ctx_exec.c
@@ -35,8 +35,9 @@
#include
#include
#include
-#include
#include
+#include
+#include
#include
#include
@@ -331,6 +332,122 @@ static void nohangcheck_hostile(int i915)
close(i915);
}
+static void kill_children(int sig)
+{
+ sighandler_t old;
+
+ old = signal(sig, SIG_IGN);
+ kill(-getpgrp(), sig);
+ signal(sig, old);
+}
+
+static bool has_persistence(int i915)
+{
+ struct drm_i915_gem_context_param p = {
+ .param = I915_CONTEXT_PARAM_PERSISTENCE,
+ };
+ uint64_t saved;
+
+ if (__gem_context_get_param(i915, &p))
+ return false;
+
+ saved = p.value;
+ p.value = 0;
+ if (__gem_context_set_param(i915, &p))
+ return false;
+
+ p.value = saved;
+ return __gem_context_set_param(i915, &p) == 0;
+}
+
+static void pi_active(int i915)
+{
+ igt_spin_t *spin = igt_spin_new(i915);
+ unsigned long count = 0;
+ bool blocked = false;
+ struct pollfd pfd;
+ int lnk[2];
+ int *done;
+
+ igt_require(gem_scheduler_enabled(i915));
+ igt_require(has_persistence(i915)); /* for graceful error recovery */
+
+ done = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0);
+ igt_assert(done != MAP_FAILED);
+
+ igt_assert(pipe(lnk) == 0);
+
+ igt_fork(child, 1) {
+ struct sigaction sa = { .sa_handler = alarm_handler };
+
+ sigaction(SIGHUP, &sa, NULL);
+
+ do {
+ uint32_t ctx;
+
+ if (__gem_context_clone(i915, 0,
+ I915_CONTEXT_CLONE_ENGINES |
+ I915_CONTEXT_CLONE_VM,
+ 0, &ctx))
+ break;
+
+ gem_context_set_persistence(i915, ctx, false);
+ if (READ_ONCE(*done))
+ break;
+
+ spin->execbuf.rsvd1 = ctx;
+ if (__execbuf(i915, &spin->execbuf))
+ break;
+
+ count++;
+ write(lnk[1], &count, sizeof(count));
+ } while (1);
+ }
+
+ pfd.fd = lnk[0];
+ pfd.events = POLLIN;
+ close(lnk[1]);
+
+ igt_until_timeout(90) {
+ if (poll(&pfd, 1, 1000) == 0) {
+ igt_info("Child blocked after %lu active contexts\n",
+count);
+ blocked = true;
+ break;
+ }
+ read(pfd.fd, &count, sizeof(count));
+ }
+
+ if (blocked) {
+ struct sigaction old_sa, sa = { .sa_handler = alarm_handler };
+ struct itimerval itv;
+
+ sigaction(SIGALRM, &sa, &old_sa);
+ itv.it_value.tv_sec = 0;
+ itv.it_value.tv_usec = 25; /* 250ms */
+ setitimer(ITIMER_REAL, &itv, NULL);
+
+ igt_assert_f(__execbuf(i915, &spin->execbuf) == 0,
+"Active execbuf blocked for more than 250ms by %lu
child contexts\n",
+count);
+
+ memset(&itv, 0, sizeof(itv));
+ setitimer(ITIMER_REAL, &itv, NULL);
+ sigaction(SIGALRM, &old_sa, NULL);
+ } else {
+ igt_info("Not blocked after %lu active contexts\n",
+count);
+ }
+
+ *done = 1;
+ kill_children(SIGHUP);
+ igt_waitchildren();
+ gem_quiescent_gpu(i915);
+ close(lnk[0]);
+
+ munmap(done, 4096);
+}
+
igt_main
{
const uint32_t batch[2] = { 0, MI_BATCH_BUFFER_END };
@@ -375,6 +492,9 @@ igt_main
igt_subtest("basic-nohangcheck")
nohangcheck_hostile(fd);
+ igt_subtest("basic-pi-active")
+ pi_active(fd);
+
igt_subtest("reset-pin-leak") {
int i;
--
2.26.2
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Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl+: Fix interrupt handling for DP AUX transactions
Hi Lakshmi, On Mon, May 04, 2020 at 06:31:06PM +, Patchwork wrote: > == Series Details == > > Series: drm/i915/tgl+: Fix interrupt handling for DP AUX transactions > URL : https://patchwork.freedesktop.org/series/76892/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_8416_full -> Patchwork_17564_full > > > Summary > --- > > **FAILURE** > > Serious unknown changes coming with Patchwork_17564_full absolutely need to > be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_17564_full, please notify your bug team to allow > them > to document this new failure mode, which will reduce false positives in CI. > > > > Possible new issues > --- > > Here are the unknown changes that may have been introduced in > Patchwork_17564_full: > > ### IGT changes ### > > Possible regressions > > * igt@kms_atomic_transition@plane-toggle-modeset-transition: > - shard-apl: [PASS][1] -> [INCOMPLETE][2] >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-apl8/igt@kms_atomic_transit...@plane-toggle-modeset-transition.html >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17564/shard-apl8/igt@kms_atomic_transit...@plane-toggle-modeset-transition.html On GEN9 nothing changed, so this must be unrelated. I couldn't find any similar issues on gitlab, so could you add there a new ticket for it? Thanks, Imre > > > Known issues > > > Here are the changes found in Patchwork_17564_full that come from known > issues: > > ### IGT changes ### > > Issues hit > > * igt@gem_exec_flush@basic-wb-ro-before-default: > - shard-hsw: [PASS][3] -> [INCOMPLETE][4] ([i915#61]) >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-hsw6/igt@gem_exec_fl...@basic-wb-ro-before-default.html >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17564/shard-hsw1/igt@gem_exec_fl...@basic-wb-ro-before-default.html > > * igt@gem_workarounds@suspend-resume-fd: > - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-apl4/igt@gem_workarou...@suspend-resume-fd.html >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17564/shard-apl6/igt@gem_workarou...@suspend-resume-fd.html > > * igt@kms_cursor_crc@pipe-c-cursor-64x21-onscreen: > - shard-glk: [PASS][7] -> [FAIL][8] ([i915#54]) >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-glk8/igt@kms_cursor_...@pipe-c-cursor-64x21-onscreen.html >[8]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17564/shard-glk2/igt@kms_cursor_...@pipe-c-cursor-64x21-onscreen.html > > * igt@kms_cursor_edge_walk@pipe-a-256x256-bottom-edge: > - shard-apl: [PASS][9] -> [FAIL][10] ([i915#70] / [i915#95]) >[9]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-apl3/igt@kms_cursor_edge_w...@pipe-a-256x256-bottom-edge.html >[10]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17564/shard-apl4/igt@kms_cursor_edge_w...@pipe-a-256x256-bottom-edge.html > > * igt@kms_flip_tiling@flip-changes-tiling-y: > - shard-apl: [PASS][11] -> [FAIL][12] ([i915#95]) >[11]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-apl1/igt@kms_flip_til...@flip-changes-tiling-y.html >[12]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17564/shard-apl3/igt@kms_flip_til...@flip-changes-tiling-y.html > - shard-kbl: [PASS][13] -> [FAIL][14] ([i915#699] / [i915#93] / > [i915#95]) >[13]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-kbl1/igt@kms_flip_til...@flip-changes-tiling-y.html >[14]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17564/shard-kbl6/igt@kms_flip_til...@flip-changes-tiling-y.html > > * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render: > - shard-skl: [PASS][15] -> [FAIL][16] ([i915#49]) >[15]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-skl9/igt@kms_frontbuffer_track...@psr-1p-primscrn-pri-indfb-draw-render.html >[16]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17564/shard-skl8/igt@kms_frontbuffer_track...@psr-1p-primscrn-pri-indfb-draw-render.html > > * igt@kms_pipe_crc_basic@hang-read-crc-pipe-a: > - shard-snb: [PASS][17] -> [SKIP][18] ([fdo#109271]) +3 similar > issues >[17]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-snb6/igt@kms_pipe_crc_ba...@hang-read-crc-pipe-a.html >[18]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17564/shard-snb2/igt@kms_pipe_crc_ba...@hang-read-crc-pipe-a.html > > * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: > - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145] / [i915#265]) >[1
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Small tidy of gen8+ breadcrumb emission
== Series Details == Series: drm/i915/gt: Small tidy of gen8+ breadcrumb emission URL : https://patchwork.freedesktop.org/series/76918/ State : success == Summary == CI Bug Log - changes from CI_DRM_8422 -> Patchwork_17573 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17573/index.html Known issues Here are the changes found in Patchwork_17573 that come from known issues: ### IGT changes ### Possible fixes * igt@i915_selftest@live@perf: - fi-bwr-2160:[INCOMPLETE][1] ([i915#489]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8422/fi-bwr-2160/igt@i915_selftest@l...@perf.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17573/fi-bwr-2160/igt@i915_selftest@l...@perf.html Warnings * igt@i915_pm_rpm@module-reload: - fi-kbl-x1275: [SKIP][3] ([fdo#109271]) -> [FAIL][4] ([i915#62] / [i915#95]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8422/fi-kbl-x1275/igt@i915_pm_...@module-reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17573/fi-kbl-x1275/igt@i915_pm_...@module-reload.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#489]: https://gitlab.freedesktop.org/drm/intel/issues/489 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (52 -> 44) -- Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8422 -> Patchwork_17573 CI-20190529: 20190529 CI_DRM_8422: 0ca0fee447b032331962bc5c717786bdb3594bd9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5628: 652a3fd8966345fa5498904ce80a2027a6782783 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17573: db12f2b422f468c0354ffd75c2e8449721dea5a3 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == db12f2b422f4 drm/i915/gt: Small tidy of gen8+ breadcrumb emission == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17573/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: HDCP: retry link integrity check on failure
== Series Details ==
Series: drm/i915: HDCP: retry link integrity check on failure
URL : https://patchwork.freedesktop.org/series/76917/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8422 -> Patchwork_17572
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17572/index.html
Known issues
Here are the changes found in Patchwork_17572 that come from known issues:
### IGT changes ###
Possible fixes
* igt@i915_selftest@live@perf:
- fi-bwr-2160:[INCOMPLETE][1] ([i915#489]) -> [PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8422/fi-bwr-2160/igt@i915_selftest@l...@perf.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17572/fi-bwr-2160/igt@i915_selftest@l...@perf.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
[i915#489]: https://gitlab.freedesktop.org/drm/intel/issues/489
Participating hosts (52 -> 45)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_8422 -> Patchwork_17572
CI-20190529: 20190529
CI_DRM_8422: 0ca0fee447b032331962bc5c717786bdb3594bd9 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5628: 652a3fd8966345fa5498904ce80a2027a6782783 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17572: a62240c79605a8b651272b2eb4b9d879f81f0504 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
a62240c79605 drm/i915: HDCP: retry link integrity check on failure
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17572/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl+: Fix interrupt handling for DP AUX transactions
== Series Details == Series: drm/i915/tgl+: Fix interrupt handling for DP AUX transactions URL : https://patchwork.freedesktop.org/series/76892/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8416_full -> Patchwork_17564_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_17564_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17564_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_17564_full: ### IGT changes ### Possible regressions * igt@kms_atomic_transition@plane-toggle-modeset-transition: - shard-apl: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-apl8/igt@kms_atomic_transit...@plane-toggle-modeset-transition.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17564/shard-apl8/igt@kms_atomic_transit...@plane-toggle-modeset-transition.html Known issues Here are the changes found in Patchwork_17564_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_flush@basic-wb-ro-before-default: - shard-hsw: [PASS][3] -> [INCOMPLETE][4] ([i915#61]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-hsw6/igt@gem_exec_fl...@basic-wb-ro-before-default.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17564/shard-hsw1/igt@gem_exec_fl...@basic-wb-ro-before-default.html * igt@gem_workarounds@suspend-resume-fd: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-apl4/igt@gem_workarou...@suspend-resume-fd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17564/shard-apl6/igt@gem_workarou...@suspend-resume-fd.html * igt@kms_cursor_crc@pipe-c-cursor-64x21-onscreen: - shard-glk: [PASS][7] -> [FAIL][8] ([i915#54]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-glk8/igt@kms_cursor_...@pipe-c-cursor-64x21-onscreen.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17564/shard-glk2/igt@kms_cursor_...@pipe-c-cursor-64x21-onscreen.html * igt@kms_cursor_edge_walk@pipe-a-256x256-bottom-edge: - shard-apl: [PASS][9] -> [FAIL][10] ([i915#70] / [i915#95]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-apl3/igt@kms_cursor_edge_w...@pipe-a-256x256-bottom-edge.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17564/shard-apl4/igt@kms_cursor_edge_w...@pipe-a-256x256-bottom-edge.html * igt@kms_flip_tiling@flip-changes-tiling-y: - shard-apl: [PASS][11] -> [FAIL][12] ([i915#95]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-apl1/igt@kms_flip_til...@flip-changes-tiling-y.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17564/shard-apl3/igt@kms_flip_til...@flip-changes-tiling-y.html - shard-kbl: [PASS][13] -> [FAIL][14] ([i915#699] / [i915#93] / [i915#95]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-kbl1/igt@kms_flip_til...@flip-changes-tiling-y.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17564/shard-kbl6/igt@kms_flip_til...@flip-changes-tiling-y.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#49]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-skl9/igt@kms_frontbuffer_track...@psr-1p-primscrn-pri-indfb-draw-render.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17564/shard-skl8/igt@kms_frontbuffer_track...@psr-1p-primscrn-pri-indfb-draw-render.html * igt@kms_pipe_crc_basic@hang-read-crc-pipe-a: - shard-snb: [PASS][17] -> [SKIP][18] ([fdo#109271]) +3 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-snb6/igt@kms_pipe_crc_ba...@hang-read-crc-pipe-a.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17564/shard-snb2/igt@kms_pipe_crc_ba...@hang-read-crc-pipe-a.html * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145] / [i915#265]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-skl9/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17564/shard-skl8/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html * igt@kms_psr@psr2_primary_mmap_gtt: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-iclb2/igt@kms_ps
[Intel-gfx] [PATCH v2 9/9] drm/i915/runtime_pm: Prefer drm_WARN* over WARN*
struct drm_device specific drm_WARN* macros include device information
in the backtrace, so we know what device the warnings originate from.
Prefer drm_WARN* over WARN*.
Conversion is done with below semantic patch:
@@
identifier func, T;
@@
func(struct intel_runtime_pm *T,...) {
+ struct drm_i915_private *i915 = container_of(T, struct drm_i915_private,
runtime_pm);
<+...
(
-WARN(
+drm_WARN(&i915->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&i915->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&i915->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&i915->drm,
...)
)
...+>
}
Signed-off-by: Pankaj Bharadiya
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 39 ++---
1 file changed, 28 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index ad719c9602af..31ccd0559c55 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -116,6 +116,9 @@ track_intel_runtime_pm_wakeref(struct intel_runtime_pm *rpm)
static void untrack_intel_runtime_pm_wakeref(struct intel_runtime_pm *rpm,
depot_stack_handle_t stack)
{
+ struct drm_i915_private *i915 = container_of(rpm,
+struct drm_i915_private,
+runtime_pm);
unsigned long flags, n;
bool found = false;
@@ -134,9 +137,9 @@ static void untrack_intel_runtime_pm_wakeref(struct
intel_runtime_pm *rpm,
}
spin_unlock_irqrestore(&rpm->debug.lock, flags);
- if (WARN(!found,
-"Unmatched wakeref (tracking %lu), count %u\n",
-rpm->debug.count, atomic_read(&rpm->wakeref_count))) {
+ if (drm_WARN(&i915->drm, !found,
+"Unmatched wakeref (tracking %lu), count %u\n",
+rpm->debug.count, atomic_read(&rpm->wakeref_count))) {
char *buf;
buf = kmalloc(PAGE_SIZE, GFP_NOWAIT | __GFP_NOWARN);
@@ -355,10 +358,14 @@ intel_runtime_pm_release(struct intel_runtime_pm *rpm,
int wakelock)
static intel_wakeref_t __intel_runtime_pm_get(struct intel_runtime_pm *rpm,
bool wakelock)
{
+ struct drm_i915_private *i915 = container_of(rpm,
+struct drm_i915_private,
+runtime_pm);
int ret;
ret = pm_runtime_get_sync(rpm->kdev);
- WARN_ONCE(ret < 0, "pm_runtime_get_sync() failed: %d\n", ret);
+ drm_WARN_ONCE(&i915->drm, ret < 0,
+ "pm_runtime_get_sync() failed: %d\n", ret);
intel_runtime_pm_acquire(rpm, wakelock);
@@ -539,6 +546,9 @@ void intel_runtime_pm_put(struct intel_runtime_pm *rpm,
intel_wakeref_t wref)
*/
void intel_runtime_pm_enable(struct intel_runtime_pm *rpm)
{
+ struct drm_i915_private *i915 = container_of(rpm,
+struct drm_i915_private,
+runtime_pm);
struct device *kdev = rpm->kdev;
/*
@@ -565,7 +575,8 @@ void intel_runtime_pm_enable(struct intel_runtime_pm *rpm)
pm_runtime_dont_use_autosuspend(kdev);
ret = pm_runtime_get_sync(kdev);
- WARN(ret < 0, "pm_runtime_get_sync() failed: %d\n", ret);
+ drm_WARN(&i915->drm, ret < 0,
+"pm_runtime_get_sync() failed: %d\n", ret);
} else {
pm_runtime_use_autosuspend(kdev);
}
@@ -580,11 +591,14 @@ void intel_runtime_pm_enable(struct intel_runtime_pm *rpm)
void intel_runtime_pm_disable(struct intel_runtime_pm *rpm)
{
+ struct drm_i915_private *i915 = container_of(rpm,
+struct drm_i915_private,
+runtime_pm);
struct device *kdev = rpm->kdev;
/* Transfer rpm ownership back to core */
- WARN(pm_runtime_get_sync(kdev) < 0,
-"Failed to pass rpm ownership back to core\n");
+ drm_WARN(&i915->drm, pm_runtime_get_sync(kdev) < 0,
+"Failed to pass rpm ownership back to core\n");
pm_runtime_dont_use_autosuspend(kdev);
@@ -594,12 +608,15 @@ void intel_runtime_pm_disable(struct intel_runtime_pm
*rpm)
void intel_runtime_pm_driver_release(struct intel_runtime_pm *rpm)
{
+ struct drm_i915_private *i915 = container_of(rpm,
+struct drm_i915_private,
+runtime_pm);
int count = atomic_read(&rpm->wakeref_count);
- WARN(count,
-"i915 raw-wakerefs=%d wakelocks=%d on cleanup\n",
-intel_rpm_raw_wakeref_count(count),
-intel_rpm_wakelock_count(count));
+ drm_
[Intel-gfx] [PATCH v2 4/9] drm/i915/display/tc: Prefer drm_WARN_ON over WARN_ON
struct drm_device specific drm_WARN* macros include device information
in the backtrace, so we know what device the warnings originate from.
Prefer drm_WARN_ON over WARN_ON.
Conversion is done with below sementic patch:
@@
identifier func, T;
@@
func(...) {
...
struct drm_i915_private *T = ...;
<+...
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
...+>
}
@@
identifier func, T;
@@
func(struct intel_digital_port *T,...) {
+struct drm_i915_private *i915 = to_i915(T->base.base.dev);
<+...
-WARN_ON(
+drm_WARN_ON(&i915->drm,
...)
...+>
}
changes since v1:
- Add i915 local variable and use it in drm_WARN_ON (Jani)
Signed-off-by: Pankaj Bharadiya
---
drivers/gpu/drm/i915/display/intel_tc.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
b/drivers/gpu/drm/i915/display/intel_tc.c
index d3bd5e798fbc..a2ffc991bc0e 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -360,12 +360,12 @@ static void icl_tc_phy_connect(struct intel_digital_port
*dig_port,
}
if (!icl_tc_phy_set_safe_mode(dig_port, false) &&
- !WARN_ON(dig_port->tc_legacy_port))
+ !drm_WARN_ON(&i915->drm, dig_port->tc_legacy_port))
goto out_set_tbt_alt_mode;
max_lanes = intel_tc_port_fia_max_lane_count(dig_port);
if (dig_port->tc_legacy_port) {
- WARN_ON(max_lanes != 4);
+ drm_WARN_ON(&i915->drm, max_lanes != 4);
dig_port->tc_mode = TC_PORT_LEGACY;
return;
@@ -445,18 +445,20 @@ static bool icl_tc_phy_is_connected(struct
intel_digital_port *dig_port)
static enum tc_port_mode
intel_tc_port_get_current_mode(struct intel_digital_port *dig_port)
{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
u32 live_status_mask = tc_port_live_status_mask(dig_port);
bool in_safe_mode = icl_tc_phy_is_in_safe_mode(dig_port);
enum tc_port_mode mode;
- if (in_safe_mode || WARN_ON(!icl_tc_phy_status_complete(dig_port)))
+ if (in_safe_mode ||
+ drm_WARN_ON(&i915->drm, !icl_tc_phy_status_complete(dig_port)))
return TC_PORT_TBT_ALT;
mode = dig_port->tc_legacy_port ? TC_PORT_LEGACY : TC_PORT_DP_ALT;
if (live_status_mask) {
enum tc_port_mode live_mode = fls(live_status_mask) - 1;
- if (!WARN_ON(live_mode == TC_PORT_TBT_ALT))
+ if (!drm_WARN_ON(&i915->drm, live_mode == TC_PORT_TBT_ALT))
mode = live_mode;
}
@@ -505,7 +507,9 @@ static void
intel_tc_port_link_init_refcount(struct intel_digital_port *dig_port,
int refcount)
{
- WARN_ON(dig_port->tc_link_refcount);
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+
+ drm_WARN_ON(&i915->drm, dig_port->tc_link_refcount);
dig_port->tc_link_refcount = refcount;
}
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 3/9] drm/i915/display/sdvo: Prefer drm_WARN* over WARN*
struct drm_device specific drm_WARN* macros include device information
in the backtrace, so we know what device the warnings originate from.
Prefer drm_WARN* over WARN* calls.
changes since v1:
- Added dev_priv local variable and used it in drm_WARN* calls (Jani)
Signed-off-by: Pankaj Bharadiya
---
drivers/gpu/drm/i915/display/intel_sdvo.c | 21 ++---
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c
b/drivers/gpu/drm/i915/display/intel_sdvo.c
index bc6c26818e15..773523dcd107 100644
--- a/drivers/gpu/drm/i915/display/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
@@ -411,6 +411,7 @@ static const char *sdvo_cmd_name(u8 cmd)
static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
const void *args, int args_len)
{
+ struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
const char *cmd_name;
int i, pos = 0;
char buffer[64];
@@ -431,7 +432,7 @@ static void intel_sdvo_debug_write(struct intel_sdvo
*intel_sdvo, u8 cmd,
else
BUF_PRINT("(%02X)", cmd);
- WARN_ON(pos >= sizeof(buffer) - 1);
+ drm_WARN_ON(&dev_priv->drm, pos >= sizeof(buffer) - 1);
#undef BUF_PRINT
DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer);
@@ -533,6 +534,7 @@ static bool intel_sdvo_write_cmd(struct intel_sdvo
*intel_sdvo, u8 cmd,
static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
void *response, int response_len)
{
+ struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
const char *cmd_status;
u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
u8 status;
@@ -597,7 +599,7 @@ static bool intel_sdvo_read_response(struct intel_sdvo
*intel_sdvo,
BUF_PRINT(" %02X", ((u8 *)response)[i]);
}
- WARN_ON(pos >= sizeof(buffer) - 1);
+ drm_WARN_ON(&dev_priv->drm, pos >= sizeof(buffer) - 1);
#undef BUF_PRINT
DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer);
@@ -1081,6 +1083,7 @@ static bool intel_sdvo_compute_avi_infoframe(struct
intel_sdvo *intel_sdvo,
struct intel_crtc_state
*crtc_state,
struct drm_connector_state
*conn_state)
{
+ struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
const struct drm_display_mode *adjusted_mode =
&crtc_state->hw.adjusted_mode;
@@ -1106,7 +1109,7 @@ static bool intel_sdvo_compute_avi_infoframe(struct
intel_sdvo *intel_sdvo,
HDMI_QUANTIZATION_RANGE_FULL);
ret = hdmi_avi_infoframe_check(frame);
- if (WARN_ON(ret))
+ if (drm_WARN_ON(&dev_priv->drm, ret))
return false;
return true;
@@ -1115,6 +1118,7 @@ static bool intel_sdvo_compute_avi_infoframe(struct
intel_sdvo *intel_sdvo,
static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
const struct intel_crtc_state
*crtc_state)
{
+ struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
const union hdmi_infoframe *frame = &crtc_state->infoframes.avi;
ssize_t len;
@@ -1123,11 +1127,12 @@ static bool intel_sdvo_set_avi_infoframe(struct
intel_sdvo *intel_sdvo,
intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI)) == 0)
return true;
- if (WARN_ON(frame->any.type != HDMI_INFOFRAME_TYPE_AVI))
+ if (drm_WARN_ON(&dev_priv->drm,
+ frame->any.type != HDMI_INFOFRAME_TYPE_AVI))
return false;
len = hdmi_infoframe_pack_only(frame, sdvo_data, sizeof(sdvo_data));
- if (WARN_ON(len < 0))
+ if (drm_WARN_ON(&dev_priv->drm, len < 0))
return false;
return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
@@ -1237,6 +1242,7 @@ intel_sdvo_get_preferred_input_mode(struct intel_sdvo
*intel_sdvo,
static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config)
{
+ struct drm_i915_private *dev_priv =
to_i915(pipe_config->uapi.crtc->dev);
unsigned dotclock = pipe_config->port_clock;
struct dpll *clock = &pipe_config->dpll;
@@ -1257,7 +1263,8 @@ static void i9xx_adjust_sdvo_tv_clock(struct
intel_crtc_state *pipe_config)
clock->m1 = 12;
clock->m2 = 8;
} else {
- WARN(1, "SDVO TV clock out of range: %i\n", dotclock);
+ drm_WARN(&dev_priv->drm, 1,
+"SDVO TV clock out of range: %i\n", dotclock);
}
pipe_config->clock_set = true;
@@ -2293,7 +
[Intel-gfx] [PATCH v2 5/9] drm/i915/gem: Prefer drm_WARN* over WARN*
struct drm_device specific drm_WARN* macros include device information in the backtrace, so we know what device the warnings originate from. Prefer drm_WARN* over WARN* at places where struct drm_device pointer can be extracted. Signed-off-by: Pankaj Bharadiya --- drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_phys.c | 3 ++- drivers/gpu/drm/i915/gem/i915_gem_userptr.c| 2 +- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index cce7df231cb9..cf9f0e078202 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -1574,7 +1574,7 @@ eb_relocate_entry(struct i915_execbuffer *eb, err = i915_vma_bind(target->vma, target->vma->obj->cache_level, PIN_GLOBAL, NULL); - if (WARN_ONCE(err, + if (drm_WARN_ONCE(&i915->drm, err, "Unexpected failure to bind target VMA!")) return err; } diff --git a/drivers/gpu/drm/i915/gem/i915_gem_phys.c b/drivers/gpu/drm/i915/gem/i915_gem_phys.c index 7fe9831aa9ba..4c1c7232b024 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_phys.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_phys.c @@ -27,7 +27,8 @@ static int i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) void *dst; int i; - if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj))) + if (drm_WARN_ON(obj->base.dev, + i915_gem_object_needs_bit17_swizzle(obj))) return -EINVAL; /* diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c index 7ffd7afeb7a5..8b0708708671 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c @@ -235,7 +235,7 @@ i915_gem_userptr_init__mmu_notifier(struct drm_i915_gem_object *obj, if (flags & I915_USERPTR_UNSYNCHRONIZED) return capable(CAP_SYS_ADMIN) ? 0 : -EPERM; - if (WARN_ON(obj->userptr.mm == NULL)) + if (drm_WARN_ON(obj->base.dev, obj->userptr.mm == NULL)) return -EINVAL; mn = i915_mmu_notifier_find(obj->userptr.mm); -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 7/9] drm/i915/pmu: Prefer drm_WARN_ON over WARN_ON
struct drm_device specific drm_WARN* macros include device information
in the backtrace, so we know what device the warnings originate from.
Prefer drm_WARN_ON over WARN_ON.
Signed-off-by: Pankaj Bharadiya
---
drivers/gpu/drm/i915/i915_pmu.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index e991a707bdb7..f6f44ad5e335 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -441,7 +441,11 @@ static u64 count_interrupts(struct drm_i915_private *i915)
static void i915_pmu_event_destroy(struct perf_event *event)
{
- WARN_ON(event->parent);
+ struct drm_i915_private *i915 =
+ container_of(event->pmu, typeof(*i915), pmu.base);
+
+ drm_WARN_ON(&i915->drm, event->parent);
+
module_put(THIS_MODULE);
}
@@ -1058,8 +1062,10 @@ static int i915_pmu_register_cpuhp_state(struct i915_pmu
*pmu)
static void i915_pmu_unregister_cpuhp_state(struct i915_pmu *pmu)
{
- WARN_ON(pmu->cpuhp.slot == CPUHP_INVALID);
- WARN_ON(cpuhp_state_remove_instance(pmu->cpuhp.slot, &pmu->cpuhp.node));
+ struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu);
+
+ drm_WARN_ON(&i915->drm, pmu->cpuhp.slot == CPUHP_INVALID);
+ drm_WARN_ON(&i915->drm, cpuhp_state_remove_instance(pmu->cpuhp.slot,
&pmu->cpuhp.node));
cpuhp_remove_multi_state(pmu->cpuhp.slot);
pmu->cpuhp.slot = CPUHP_INVALID;
}
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 6/9] drm/i915/i915_drv: Prefer drm_WARN_ON over WARN_ON
struct drm_device specific drm_WARN* macros include device information
in the backtrace, so we know what device the warnings originate from.
Prefer drm_WARN_ON over WARN_ON.
changes since v1:
- Add parentheses around the dev_priv macro argument (Jani)
Signed-off-by: Pankaj Bharadiya
---
drivers/gpu/drm/i915/i915_drv.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6af69555733e..9fdf4bcd06e1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1649,7 +1649,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)
/* Only valid when HAS_DISPLAY() is true */
-#define INTEL_DISPLAY_ENABLED(dev_priv) (WARN_ON(!HAS_DISPLAY(dev_priv)),
!i915_modparams.disable_display)
+#define INTEL_DISPLAY_ENABLED(dev_priv) \
+ (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)),
!i915_modparams.disable_display)
static inline bool intel_vtd_active(void)
{
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 8/9] drm/i915/pm: Prefer drm_WARN_ON over WARN_ON
struct drm_device specific drm_WARN* macros include device information
in the backtrace, so we know what device the warnings originate from.
Prefer drm_WARN_ON over WARN_ON.
Conversion is done with below sementic patch:
@@
identifier func, T;
@@
func(...) {
...
struct intel_crtc *T = ...;
+struct drm_i915_private *dev_priv = to_i915(T->base.dev);
<+...
-WARN_ON(
+drm_WARN_ON(&dev_priv->drm,
...)
...+>
}
@@
identifier func, T;
@@
func(struct intel_crtc_state *T,...) {
+struct drm_i915_private *dev_priv = to_i915(T->uapi.crtc->dev);
<+...
-WARN_ON(
+drm_WARN_ON(&dev_priv->drm,
...)
...+>
}
changes since v1:
- Added dev_priv local variable and used it in drm_WARN_ON calls (Jani)
Signed-off-by: Pankaj Bharadiya
---
drivers/gpu/drm/i915/intel_pm.c | 63 -
1 file changed, 38 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bfb180fe8047..7e8da6c5bfb9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1436,6 +1436,7 @@ static int g4x_compute_pipe_wm(struct intel_crtc_state
*crtc_state)
static int g4x_compute_intermediate_wm(struct intel_crtc_state *new_crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct g4x_wm_state *intermediate =
&new_crtc_state->wm.g4x.intermediate;
const struct g4x_wm_state *optimal = &new_crtc_state->wm.g4x.optimal;
struct intel_atomic_state *intel_state =
@@ -1464,8 +1465,8 @@ static int g4x_compute_intermediate_wm(struct
intel_crtc_state *new_crtc_state)
max(optimal->wm.plane[plane_id],
active->wm.plane[plane_id]);
- WARN_ON(intermediate->wm.plane[plane_id] >
- g4x_plane_fifo_size(plane_id, G4X_WM_LEVEL_NORMAL));
+ drm_WARN_ON(&dev_priv->drm, intermediate->wm.plane[plane_id] >
+ g4x_plane_fifo_size(plane_id, G4X_WM_LEVEL_NORMAL));
}
intermediate->sr.plane = max(optimal->sr.plane,
@@ -1482,21 +1483,25 @@ static int g4x_compute_intermediate_wm(struct
intel_crtc_state *new_crtc_state)
intermediate->hpll.fbc = max(optimal->hpll.fbc,
active->hpll.fbc);
- WARN_ON((intermediate->sr.plane >
-g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_SR) ||
-intermediate->sr.cursor >
-g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_SR)) &&
- intermediate->cxsr);
- WARN_ON((intermediate->sr.plane >
-g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_HPLL) ||
-intermediate->sr.cursor >
-g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_HPLL)) &&
- intermediate->hpll_en);
-
- WARN_ON(intermediate->sr.fbc > g4x_fbc_fifo_size(1) &&
- intermediate->fbc_en && intermediate->cxsr);
- WARN_ON(intermediate->hpll.fbc > g4x_fbc_fifo_size(2) &&
- intermediate->fbc_en && intermediate->hpll_en);
+ drm_WARN_ON(&dev_priv->drm,
+ (intermediate->sr.plane >
+g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_SR) ||
+intermediate->sr.cursor >
+g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_SR)) &&
+ intermediate->cxsr);
+ drm_WARN_ON(&dev_priv->drm,
+ (intermediate->sr.plane >
+g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_HPLL) ||
+intermediate->sr.cursor >
+g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_HPLL)) &&
+ intermediate->hpll_en);
+
+ drm_WARN_ON(&dev_priv->drm,
+ intermediate->sr.fbc > g4x_fbc_fifo_size(1) &&
+ intermediate->fbc_en && intermediate->cxsr);
+ drm_WARN_ON(&dev_priv->drm,
+ intermediate->hpll.fbc > g4x_fbc_fifo_size(2) &&
+ intermediate->fbc_en && intermediate->hpll_en);
out:
/*
@@ -1680,6 +1685,7 @@ static bool vlv_need_sprite0_fifo_workaround(unsigned int
active_planes)
static int vlv_compute_fifo(struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
const struct g4x_pipe_wm *raw =
&crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2];
struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
@@ -1748,11 +1754,11 @@ static int vlv_compute_fifo(struct intel_crtc_state
*crtc_state)
fifo_left -= plane_extra;
}
- WARN_ON(active_planes != 0 && fifo_left != 0);
+ drm_WARN_ON(&dev_priv->drm, active_planes != 0 && fifo_left != 0);
/* give it all to the first plane if none
[Intel-gfx] [PATCH v2 2/9] drm/i915/display/dp: Prefer drm_WARN* over WARN*
struct drm_device specific drm_WARN* macros include device information
in the backtrace, so we know what device the warnings originate from.
Prefer drm_WARN* over WARN* at places where struct intel_dp or struct
drm_i915_private pointer is available.
Conversion is done with below sementic patch:
@rule1@
identifier func, T;
@@
func(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}
@rule2@
identifier func, T;
@@
func(struct drm_i915_private *T,...) {
<+...
(
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}
@rule3@
identifier func, T;
@@
func(struct intel_dp *T,...) {
+ struct drm_i915_private *i915 = dp_to_i915(T);
<+...
(
-WARN_ON(
+drm_WARN_ON(&i915->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&i915->drm,
...)
)
...+>
}
@rule4@
identifier func, T;
@@
func(...) {
...
struct intel_dp *T = ...;
+ struct drm_i915_private *i915 = dp_to_i915(T);
<+...
(
-WARN_ON(
+drm_WARN_ON(&i915->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&i915->drm,
...)
)
...+>
}
Signed-off-by: Pankaj Bharadiya
---
drivers/gpu/drm/i915/display/intel_dp.c | 24 +++-
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 6952b0295096..ac44fc242879 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -409,7 +409,10 @@ static int intel_dp_rate_index(const int *rates, int len,
int rate)
static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
{
- WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+
+ drm_WARN_ON(&i915->drm,
+ !intel_dp->num_source_rates || !intel_dp->num_sink_rates);
intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
intel_dp->num_source_rates,
@@ -418,7 +421,7 @@ static void intel_dp_set_common_rates(struct intel_dp
*intel_dp)
intel_dp->common_rates);
/* Paranoia, there should always be something in common. */
- if (WARN_ON(intel_dp->num_common_rates == 0)) {
+ if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) {
intel_dp->common_rates[0] = 162000;
intel_dp->num_common_rates = 1;
}
@@ -1554,6 +1557,7 @@ static ssize_t
intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
{
struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
u8 txbuf[20], rxbuf[20];
size_t txsize, rxsize;
int ret;
@@ -1567,10 +1571,10 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct
drm_dp_aux_msg *msg)
txsize = msg->size ? HEADER_SIZE + msg->size :
BARE_ADDRESS_SIZE;
rxsize = 2; /* 0 or 1 data bytes */
- if (WARN_ON(txsize > 20))
+ if (drm_WARN_ON(&i915->drm, txsize > 20))
return -E2BIG;
- WARN_ON(!msg->buffer != !msg->size);
+ drm_WARN_ON(&i915->drm, !msg->buffer != !msg->size);
if (msg->buffer)
memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
@@ -1595,7 +1599,7 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct
drm_dp_aux_msg *msg)
txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
rxsize = msg->size + 1;
- if (WARN_ON(rxsize > 20))
+ if (drm_WARN_ON(&i915->drm, rxsize > 20))
return -E2BIG;
ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
@@ -1870,10 +1874,11 @@ static void intel_dp_print_rates(struct intel_dp
*intel_dp)
int
intel_dp_max_link_rate(struct intel_dp *intel_dp)
{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
int len;
len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
- if (WARN_ON(len <= 0))
+ if (drm_WARN_ON(&i915->drm, len <= 0))
return 162000;
return intel_dp->common_rates[len - 1];
@@ -1881,10 +1886,11 @@ intel_dp_max_link_rate(struct intel_dp *intel_dp)
int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
int i = intel_dp_rate_index(intel_dp->sink_rates,
intel_dp->num_sink_rates, rate);
- if (WARN_ON(i < 0))
+ if (drm_WARN_ON(&i915->drm, i < 0))
i = 0;
return i;
@@ -5580,7 +5586,7 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp)
if (!intel_dp->is_mst)
return -EINVAL;
- WARN_ON_ONCE(intel_dp->active_
[Intel-gfx] [PATCH v2 1/9] drm/i915/display/display_power: Prefer drm_WARN_ON over WARN_ON
struct drm_device specific drm_WARN* macros include device information
in the backtrace, so we know what device the warnings originate from.
Prefer drm_WARN_ON over WARN_ON at places where struct i915_power_domains
struct is available.
Conversion is done with below sementic patch:
@@
identifier func, T;
@@
func(struct i915_power_domains *T,...) {
+ struct drm_i915_private *i915 = container_of(T, struct drm_i915_private,
power_domains);
<+...
-WARN_ON(
+drm_WARN_ON(&i915->drm,
...)
...+>
}
changes since v1:
- Fix commit subject (Jani)
Signed-off-by: Pankaj Bharadiya
---
.../drm/i915/display/intel_display_power.c| 35 +--
1 file changed, 24 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 49998906cc61..69039cea1b5a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1943,22 +1943,29 @@ static u64 __async_put_domains_mask(struct
i915_power_domains *power_domains)
static bool
assert_async_put_domain_masks_disjoint(struct i915_power_domains
*power_domains)
{
- return !WARN_ON(power_domains->async_put_domains[0] &
- power_domains->async_put_domains[1]);
+ struct drm_i915_private *i915 = container_of(power_domains,
+struct drm_i915_private,
+power_domains);
+ return !drm_WARN_ON(&i915->drm, power_domains->async_put_domains[0] &
+ power_domains->async_put_domains[1]);
}
static bool
__async_put_domains_state_ok(struct i915_power_domains *power_domains)
{
+ struct drm_i915_private *i915 = container_of(power_domains,
+struct drm_i915_private,
+power_domains);
enum intel_display_power_domain domain;
bool err = false;
err |= !assert_async_put_domain_masks_disjoint(power_domains);
- err |= WARN_ON(!!power_domains->async_put_wakeref !=
- !!__async_put_domains_mask(power_domains));
+ err |= drm_WARN_ON(&i915->drm, !!power_domains->async_put_wakeref !=
+ !!__async_put_domains_mask(power_domains));
for_each_power_domain(domain, __async_put_domains_mask(power_domains))
- err |= WARN_ON(power_domains->domain_use_count[domain] != 1);
+ err |= drm_WARN_ON(&i915->drm,
+ power_domains->domain_use_count[domain] !=
1);
return !err;
}
@@ -2200,11 +2207,14 @@ static void
queue_async_put_domains_work(struct i915_power_domains *power_domains,
intel_wakeref_t wakeref)
{
- WARN_ON(power_domains->async_put_wakeref);
+ struct drm_i915_private *i915 = container_of(power_domains,
+struct drm_i915_private,
+power_domains);
+ drm_WARN_ON(&i915->drm, power_domains->async_put_wakeref);
power_domains->async_put_wakeref = wakeref;
- WARN_ON(!queue_delayed_work(system_unbound_wq,
- &power_domains->async_put_work,
- msecs_to_jiffies(100)));
+ drm_WARN_ON(&i915->drm, !queue_delayed_work(system_unbound_wq,
+
&power_domains->async_put_work,
+ msecs_to_jiffies(100)));
}
static void
@@ -4365,6 +4375,9 @@ __set_power_wells(struct i915_power_domains
*power_domains,
const struct i915_power_well_desc *power_well_descs,
int power_well_count)
{
+ struct drm_i915_private *i915 = container_of(power_domains,
+struct drm_i915_private,
+power_domains);
u64 power_well_ids = 0;
int i;
@@ -4384,8 +4397,8 @@ __set_power_wells(struct i915_power_domains
*power_domains,
if (id == DISP_PW_ID_NONE)
continue;
- WARN_ON(id >= sizeof(power_well_ids) * 8);
- WARN_ON(power_well_ids & BIT_ULL(id));
+ drm_WARN_ON(&i915->drm, id >= sizeof(power_well_ids) * 8);
+ drm_WARN_ON(&i915->drm, power_well_ids & BIT_ULL(id));
power_well_ids |= BIT_ULL(id);
}
--
2.23.0
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 0/9] Prefer drm_WARN* over WARN*
Now we have struct drm_device specific drm_WARN* macros which include device information in the backtrace, so we know what device the warnings originate from. This series converts WARN* with drm_WARN* where struct drm_device pointer can be extracted. This series is the continuation of: https://patchwork.freedesktop.org/series/72035/ changes since v1: - Addressed Jani's review comments - Rebase patches on latest tip. Pankaj Bharadiya (9): drm/i915/display/display_power: Prefer drm_WARN_ON over WARN_ON drm/i915/display/dp: Prefer drm_WARN* over WARN* drm/i915/display/sdvo: Prefer drm_WARN* over WARN* drm/i915/display/tc: Prefer drm_WARN_ON over WARN_ON drm/i915/gem: Prefer drm_WARN* over WARN* drm/i915/i915_drv: Prefer drm_WARN_ON over WARN_ON drm/i915/pmu: Prefer drm_WARN_ON over WARN_ON drm/i915/pm: Prefer drm_WARN_ON over WARN_ON drm/i915/runtime_pm: Prefer drm_WARN* over WARN* .../drm/i915/display/intel_display_power.c| 35 +++ drivers/gpu/drm/i915/display/intel_dp.c | 24 --- drivers/gpu/drm/i915/display/intel_sdvo.c | 21 --- drivers/gpu/drm/i915/display/intel_tc.c | 14 +++-- .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 2 +- drivers/gpu/drm/i915/gem/i915_gem_phys.c | 3 +- drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 3 +- drivers/gpu/drm/i915/i915_pmu.c | 12 +++- drivers/gpu/drm/i915/intel_pm.c | 63 +++ drivers/gpu/drm/i915/intel_runtime_pm.c | 39 11 files changed, 143 insertions(+), 75 deletions(-) -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: HDCP: retry link integrity check on failure
== Series Details == Series: drm/i915: HDCP: retry link integrity check on failure URL : https://patchwork.freedesktop.org/series/76917/ State : warning == Summary == $ dim checkpatch origin/drm-tip a62240c79605 drm/i915: HDCP: retry link integrity check on failure -:33: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #33: FILE: drivers/gpu/drm/i915/display/intel_hdmi.c:1567: + drm_dbg_kms(&i915->drm, "Ri' mismatch detected (%x)\n", intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, total: 0 errors, 0 warnings, 1 checks, 37 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI] drm/i915/gt: Stop holding onto the pinned_default_state
As we only restore the default context state upon banning a context, we
only need enough of the state to run the ring and nothing more. That is
we only need our bare protocontext.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
Cc: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_engine_pm.c| 14 +-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 -
drivers/gpu/drm/i915/gt/intel_lrc.c | 14 ++
drivers/gpu/drm/i915/gt/selftest_context.c | 11 ++--
drivers/gpu/drm/i915/gt/selftest_lrc.c | 53 +++-
5 files changed, 47 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index 811debefebc0..d0a1078ef632 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -21,18 +21,11 @@ static int __engine_unpark(struct intel_wakeref *wf)
struct intel_engine_cs *engine =
container_of(wf, typeof(*engine), wakeref);
struct intel_context *ce;
- void *map;
ENGINE_TRACE(engine, "\n");
intel_gt_pm_get(engine->gt);
- /* Pin the default state for fast resets from atomic context. */
- map = NULL;
- if (engine->default_state)
- map = shmem_pin_map(engine->default_state);
- engine->pinned_default_state = map;
-
/* Discard stale context state from across idling */
ce = engine->kernel_context;
if (ce) {
@@ -42,6 +35,7 @@ static int __engine_unpark(struct intel_wakeref *wf)
if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM) && ce->state) {
struct drm_i915_gem_object *obj = ce->state->obj;
int type = i915_coherent_map_type(engine->i915);
+ void *map;
map = i915_gem_object_pin_map(obj, type);
if (!IS_ERR(map)) {
@@ -260,12 +254,6 @@ static int __engine_park(struct intel_wakeref *wf)
if (engine->park)
engine->park(engine);
- if (engine->pinned_default_state) {
- shmem_unpin_map(engine->default_state,
- engine->pinned_default_state);
- engine->pinned_default_state = NULL;
- }
-
engine->execlists.no_priolist = false;
/* While gt calls i915_vma_parked(), we have to break the lock cycle */
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 6c676774dcd9..c84525363bb7 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -339,7 +339,6 @@ struct intel_engine_cs {
unsigned long wakeref_serial;
struct intel_wakeref wakeref;
struct file *default_state;
- void *pinned_default_state;
struct {
struct intel_ring *ring;
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index d4ef344657b0..100ed0fce2e2 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1271,14 +1271,11 @@ execlists_check_context(const struct intel_context *ce,
static void restore_default_state(struct intel_context *ce,
struct intel_engine_cs *engine)
{
- u32 *regs = ce->lrc_reg_state;
+ u32 *regs;
- if (engine->pinned_default_state)
- memcpy(regs, /* skip restoring the vanilla PPHWSP */
- engine->pinned_default_state + LRC_STATE_OFFSET,
- engine->context_size - PAGE_SIZE);
+ regs = memset(ce->lrc_reg_state, 0, engine->context_size - PAGE_SIZE);
+ execlists_init_reg_state(regs, ce, engine, ce->ring, true);
- execlists_init_reg_state(regs, ce, engine, ce->ring, false);
ce->runtime.last = intel_context_get_runtime(ce);
}
@@ -4166,8 +4163,6 @@ static void __execlists_reset(struct intel_engine_cs
*engine, bool stalled)
* image back to the expected values to skip over the guilty request.
*/
__i915_request_reset(rq, stalled);
- if (!stalled)
- goto out_replay;
/*
* We want a simple context + ring to execute the breadcrumb update.
@@ -4177,9 +4172,6 @@ static void __execlists_reset(struct intel_engine_cs
*engine, bool stalled)
* future request will be after userspace has had the opportunity
* to recreate its own state.
*/
- GEM_BUG_ON(!intel_context_is_pinned(ce));
- restore_default_state(ce, engine);
-
out_replay:
ENGINE_TRACE(engine, "replay {head:%04x, tail:%04x}\n",
head, ce->ring->tail);
diff --git a/drivers/gpu/drm/i915/gt/selftest_context.c
b/drivers/gpu/drm/i915/gt/selftest_context.c
index b8ed3cbe1277..a56dff3b157a 100644
--- a/drivers/gpu/drm/i915/gt/selftest_context.c
+++ b/drivers/gpu/drm/i915/gt/selftest_cont
[Intel-gfx] [CI] drm/i915/gt: Small tidy of gen8+ breadcrumb emission
Use a local to shrink a line under 80 columns, and refactor the common
emit_xcs_breadcrumb() wrapper of ggtt-write.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 34 +
1 file changed, 15 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index d4ef344657b0..c00366387b54 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -4641,8 +4641,7 @@ static u32 *emit_preempt_busywait(struct i915_request
*request, u32 *cs)
}
static __always_inline u32*
-gen8_emit_fini_breadcrumb_footer(struct i915_request *request,
-u32 *cs)
+gen8_emit_fini_breadcrumb_tail(struct i915_request *request, u32 *cs)
{
*cs++ = MI_USER_INTERRUPT;
@@ -4656,14 +4655,16 @@ gen8_emit_fini_breadcrumb_footer(struct i915_request
*request,
return gen8_emit_wa_tail(request, cs);
}
-static u32 *gen8_emit_fini_breadcrumb(struct i915_request *request, u32 *cs)
+static u32 *emit_xcs_breadcrumb(struct i915_request *request, u32 *cs)
{
- cs = gen8_emit_ggtt_write(cs,
- request->fence.seqno,
-
i915_request_active_timeline(request)->hwsp_offset,
- 0);
+ u32 addr = i915_request_active_timeline(request)->hwsp_offset;
- return gen8_emit_fini_breadcrumb_footer(request, cs);
+ return gen8_emit_ggtt_write(cs, request->fence.seqno, addr, 0);
+}
+
+static u32 *gen8_emit_fini_breadcrumb(struct i915_request *rq, u32 *cs)
+{
+ return gen8_emit_fini_breadcrumb_tail(rq, emit_xcs_breadcrumb(rq, cs));
}
static u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *request, u32
*cs)
@@ -4681,7 +4682,7 @@ static u32 *gen8_emit_fini_breadcrumb_rcs(struct
i915_request *request, u32 *cs)
PIPE_CONTROL_FLUSH_ENABLE |
PIPE_CONTROL_CS_STALL);
- return gen8_emit_fini_breadcrumb_footer(request, cs);
+ return gen8_emit_fini_breadcrumb_tail(request, cs);
}
static u32 *
@@ -4697,7 +4698,7 @@ gen11_emit_fini_breadcrumb_rcs(struct i915_request
*request, u32 *cs)
PIPE_CONTROL_DC_FLUSH_ENABLE |
PIPE_CONTROL_FLUSH_ENABLE);
- return gen8_emit_fini_breadcrumb_footer(request, cs);
+ return gen8_emit_fini_breadcrumb_tail(request, cs);
}
/*
@@ -4735,7 +4736,7 @@ static u32 *gen12_emit_preempt_busywait(struct
i915_request *request, u32 *cs)
}
static __always_inline u32*
-gen12_emit_fini_breadcrumb_footer(struct i915_request *request, u32 *cs)
+gen12_emit_fini_breadcrumb_tail(struct i915_request *request, u32 *cs)
{
*cs++ = MI_USER_INTERRUPT;
@@ -4749,14 +4750,9 @@ gen12_emit_fini_breadcrumb_footer(struct i915_request
*request, u32 *cs)
return gen8_emit_wa_tail(request, cs);
}
-static u32 *gen12_emit_fini_breadcrumb(struct i915_request *request, u32 *cs)
+static u32 *gen12_emit_fini_breadcrumb(struct i915_request *rq, u32 *cs)
{
- cs = gen8_emit_ggtt_write(cs,
- request->fence.seqno,
-
i915_request_active_timeline(request)->hwsp_offset,
- 0);
-
- return gen12_emit_fini_breadcrumb_footer(request, cs);
+ return gen12_emit_fini_breadcrumb_tail(rq, emit_xcs_breadcrumb(rq, cs));
}
static u32 *
@@ -4775,7 +4771,7 @@ gen12_emit_fini_breadcrumb_rcs(struct i915_request
*request, u32 *cs)
PIPE_CONTROL_FLUSH_ENABLE |
PIPE_CONTROL_HDC_PIPELINE_FLUSH);
- return gen12_emit_fini_breadcrumb_footer(request, cs);
+ return gen12_emit_fini_breadcrumb_tail(request, cs);
}
static void execlists_park(struct intel_engine_cs *engine)
--
2.20.1
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display: Fix the encoder type check
== Series Details == Series: drm/i915/display: Fix the encoder type check URL : https://patchwork.freedesktop.org/series/76891/ State : success == Summary == CI Bug Log - changes from CI_DRM_8416_full -> Patchwork_17563_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_17563_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_params@invalid-bsd-ring: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#109276]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-iclb2/igt@gem_exec_par...@invalid-bsd-ring.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17563/shard-iclb8/igt@gem_exec_par...@invalid-bsd-ring.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +5 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-kbl2/igt@kms_cursor_...@pipe-a-cursor-suspend.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17563/shard-kbl3/igt@kms_cursor_...@pipe-a-cursor-suspend.html * igt@kms_cursor_edge_walk@pipe-a-256x256-bottom-edge: - shard-apl: [PASS][5] -> [FAIL][6] ([i915#70] / [i915#95]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-apl3/igt@kms_cursor_edge_w...@pipe-a-256x256-bottom-edge.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17563/shard-apl7/igt@kms_cursor_edge_w...@pipe-a-256x256-bottom-edge.html * igt@kms_cursor_legacy@pipe-b-forked-bo: - shard-hsw: [PASS][7] -> [INCOMPLETE][8] ([i915#61]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-hsw1/igt@kms_cursor_leg...@pipe-b-forked-bo.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17563/shard-hsw2/igt@kms_cursor_leg...@pipe-b-forked-bo.html * igt@kms_draw_crc@draw-method-rgb565-mmap-wc-untiled: - shard-glk: [PASS][9] -> [FAIL][10] ([i915#52] / [i915#54]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-glk7/igt@kms_draw_...@draw-method-rgb565-mmap-wc-untiled.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17563/shard-glk6/igt@kms_draw_...@draw-method-rgb565-mmap-wc-untiled.html * igt@kms_flip_tiling@flip-changes-tiling-y: - shard-apl: [PASS][11] -> [FAIL][12] ([i915#95]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-apl1/igt@kms_flip_til...@flip-changes-tiling-y.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17563/shard-apl3/igt@kms_flip_til...@flip-changes-tiling-y.html - shard-kbl: [PASS][13] -> [FAIL][14] ([i915#699] / [i915#93] / [i915#95]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-kbl1/igt@kms_flip_til...@flip-changes-tiling-y.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17563/shard-kbl1/igt@kms_flip_til...@flip-changes-tiling-y.html * igt@kms_hdr@bpc-switch: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#1188]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-skl6/igt@kms_...@bpc-switch.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17563/shard-skl10/igt@kms_...@bpc-switch.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-apl: [PASS][17] -> [DMESG-WARN][18] ([i915#180]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-apl7/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17563/shard-apl6/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt@kms_psr@psr2_primary_mmap_gtt: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17563/shard-iclb3/igt@kms_psr@psr2_primary_mmap_gtt.html * igt@kms_vblank@pipe-c-ts-continuation-suspend: - shard-kbl: [PASS][21] -> [INCOMPLETE][22] ([i915#155] / [i915#794]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-kbl7/igt@kms_vbl...@pipe-c-ts-continuation-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17563/shard-kbl6/igt@kms_vbl...@pipe-c-ts-continuation-suspend.html Possible fixes * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-skl: [FAIL][23] ([i915#54]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8416/shard-skl5/igt@kms_cursor_...@pipe-a-cursor-suspend.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17563/shard-skl10/igt@kms_cursor_...@pipe-a-cursor-suspend.html * igt@kms_dp_dsc@basic-dsc-enable-edp: - shar
Re: [Intel-gfx] [PATCH 11/23] drm/i915/rkl: Add cdclk support
On Sat, May 02, 2020 at 09:26:51AM -0700, Khor, Swee Aun wrote:
> Hi Matt,
> The follow cdclk doesn't looked right, isn’t it should be 96000 and 54
> according to their respective divider and ratio?
>
> +{ .refclk = 19200, .cdclk = 192000, .divider = 3, .ratio = 15 },
>
> +{ .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 45 },
>
Yeah, you're right. The first one appears to have been removed from the
bspec now and the second one appears to be a typo on my part (ratio
should be 46 instead of 45).
Looks like there have been a couple other recent modifications to the
bspec as well that I should update this patch to capture. Thanks for
pointing that out!
Matt
>
> Regards,
> SweeAun
>
> -Original Message-
> From: Intel-gfx On Behalf Of Matt
> Roper
> Sent: Saturday, May 2, 2020 1:08 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 11/23] drm/i915/rkl: Add cdclk support
>
> Note that the 192000 clock frequencies can be achieved with different pairs
> of ratio+divider, which is something we haven't encountered before. If any
> of those ratios were common with other legal cdclk values, then it would mean
> we could avoid triggering full modesets if we just needed to change the
> divider. However at the moment there don't appear to be any valid cdclks
> that share the same ratio so we can't take advantage of this and it doesn't
> really matter which approach we use to achieve the 192000 cdclk. For now our
> driver functions that operate on the table will just always pick the first
> entry (lower ratio + lower divider).
>
> Bspec: 49202
> Cc: Ville Syrjälä
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 54 +++---
> 1 file changed, 48 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 979a0241fdcb..4ca87260e8ba 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1230,6 +1230,40 @@ static const struct intel_cdclk_vals icl_cdclk_table[]
> = {
> {}
> };
>
> +/*
> + * RKL has multiple divider+ratio pairs that can hit cdclk=192000. Our
> + * functions to read these tables will just always pick the first one
> +which
> + * should be fine since there's no other valid cdclk value that can be
> +achieved
> + * via the same ratio with a different divider (i.e., no opportunity to
> +avoid a
> + * full modeset).
> + */
> +static const struct intel_cdclk_vals rkl_cdclk_table[] = {
> +{ .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
> +{ .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
> +{ .refclk = 19200, .cdclk = 192000, .divider = 3, .ratio = 15 },
> +{ .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
> +{ .refclk = 19200, .cdclk = 326400, .divider = 4, .ratio = 68 },
> +{ .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> +{ .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> +
> +{ .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
> +{ .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
> +{ .refclk = 24000, .cdclk = 192000, .divider = 3, .ratio = 24 },
> +{ .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
> +{ .refclk = 24000, .cdclk = 324000, .divider = 4, .ratio = 54 },
> +{ .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 45 },
> +{ .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
> +
> +{ .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
> +{ .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
> +{ .refclk = 38400, .cdclk = 192000, .divider = 3, .ratio = 15 },
> +{ .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
> +{ .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 },
> +{ .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> +{ .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> +{}
> +};
> +
> static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
> {
> const struct intel_cdclk_vals *table = dev_priv->cdclk.table; @@ -1405,8
> +1439,8 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
> div = 2;
> break;
> case BXT_CDCLK_CD2X_DIV_SEL_1_5:
> -drm_WARN(&dev_priv->drm,
> - IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10,
> +drm_WARN(&dev_priv->drm, IS_GEMINILAKE(dev_priv) ||
> + (INTEL_GEN(dev_priv) >= 10 && !IS_ROCKETLAKE(dev_priv)),
> "Unsupported divider\n");
> div = 3;
> break;
> @@ -1414,7 +1448,8 @@ static void bxt_get_cdclk(struct drm_i915_private
> *dev_priv,
> div = 4;
> break;
> case BXT_CDCLK_CD2X_DIV_SEL_4:
> -drm_WARN(&dev_priv->drm, INTEL_GEN(dev_priv) >= 10,
> +drm_WARN(&dev_priv->drm,
> + INTEL_GEN(dev_priv) >= 10 && !IS_ROCKETLAKE(dev_priv),
> "Unsupported divider\n");
> div = 8;
> break;
> @@ -1564,7 +1599,8 @@ static void bxt_set_cdclk(struct drm_i9
Re: [Intel-gfx] [PATCH] drm/i915/gem: Fix inconsistent IS_ERR and PTR_ERR
…
> The proper pointer to be passed as argument is ce.
>
> This bug was detected with the help of Coccinelle.
My software development attention was caught also by your commit message.
…
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> @@ -1325,7 +1325,7 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
>
> ce = intel_context_create(engine);
> if (IS_ERR(ce)) {
> - err = PTR_ERR(rq);
> + err = PTR_ERR(ce);
> goto err_unpin;
> }
>
Are you looking for any more questionable identifier (or expression)
combinations
also at other places by the means of advanced source code analysis?
Regards,
Markus
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Re: [Intel-gfx] [PATCH] drm/i915: check to see if SIMD registers are available before using SIMD
On Sun, May 03, 2020 at 09:20:19PM +0100, Chris Wilson wrote: > > Err, why does i915 implements its own uncached memcpy instead of relying > > on core functionality to start with? > > What is this core functionality that provides movntqda? A sensible name might be memcpy_uncached or mempcy_nontemporal. But the important point is that this should be arch code with a common fallback rather than hacking it up in drivers. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH hmm v2 1/5] mm/hmm: make CONFIG_DEVICE_PRIVATE into a select
On 2020-05-01 11:20, Jason Gunthorpe wrote: From: Jason Gunthorpe There is no reason for a user to select this or not directly - it should be selected by drivers that are going to use the feature, similar to how CONFIG_HMM_MIRROR works. Yes, this is a nice touch. Reviewed-by: John Hubbard thanks, -- John Hubbard NVIDIA Currently all drivers provide a feature kconfig that will disable use of DEVICE_PRIVATE in that driver, allowing users to avoid enabling this if they don't want the overhead. Acked-by: Felix Kuehling Reviewed-by: Christoph Hellwig Signed-off-by: Jason Gunthorpe --- arch/powerpc/Kconfig| 2 +- drivers/gpu/drm/nouveau/Kconfig | 2 +- mm/Kconfig | 7 +-- 3 files changed, 3 insertions(+), 8 deletions(-) diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 924c541a926008..8de52aefdc74cc 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -455,7 +455,7 @@ config PPC_TRANSACTIONAL_MEM config PPC_UV bool "Ultravisor support" depends on KVM_BOOK3S_HV_POSSIBLE - depends on DEVICE_PRIVATE + select DEVICE_PRIVATE default n help This option paravirtualizes the kernel to run in POWER platforms that diff --git a/drivers/gpu/drm/nouveau/Kconfig b/drivers/gpu/drm/nouveau/Kconfig index d6e4ae1ef7053a..af5793f3e7c2cf 100644 --- a/drivers/gpu/drm/nouveau/Kconfig +++ b/drivers/gpu/drm/nouveau/Kconfig @@ -86,10 +86,10 @@ config DRM_NOUVEAU_BACKLIGHT config DRM_NOUVEAU_SVM bool "(EXPERIMENTAL) Enable SVM (Shared Virtual Memory) support" - depends on DEVICE_PRIVATE depends on DRM_NOUVEAU depends on MMU depends on STAGING + select DEVICE_PRIVATE select HMM_MIRROR select MMU_NOTIFIER default n diff --git a/mm/Kconfig b/mm/Kconfig index c1acc34c1c358c..7ca36bf5f5058e 100644 --- a/mm/Kconfig +++ b/mm/Kconfig @@ -805,15 +805,10 @@ config HMM_MIRROR depends on MMU config DEVICE_PRIVATE - bool "Unaddressable device memory (GPU memory, ...)" + bool depends on ZONE_DEVICE select DEV_PAGEMAP_OPS - help - Allows creation of struct pages to represent unaddressable device - memory; i.e., memory that is only accessible from the device (or - group of devices). You likely also want to select HMM_MIRROR. - config FRAME_VECTOR bool ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: check to see if SIMD registers are available before using SIMD
On Sun, May 3, 2020 at 2:30 PM Chris Wilson wrote: > > Quoting Jason A. Donenfeld (2020-04-30 23:10:16) > > Sometimes it's not okay to use SIMD registers, the conditions for which > > have changed subtly from kernel release to kernel release. Usually the > > pattern is to check for may_use_simd() and then fallback to using > > something slower in the unlikely case SIMD registers aren't available. > > So, this patch fixes up i915's accelerated memcpy routines to fallback > > to boring memcpy if may_use_simd() is false. > > > > Cc: sta...@vger.kernel.org > > The same argument as on the previous submission is that we return to the > caller if we can't use movntqda as their fallback path should be faster > than uncached memcpy. Oh, THAT's what you meant before. Okay, will follow up. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: HDCP: retry link integrity check on failure
From: Oliver Barta
A single Ri mismatch doesn't automatically mean that the link integrity
is broken. Update and check of Ri and Ri' are done asynchronously. In
case an update happens just between the read of Ri' and the check against
Ri there will be a mismatch even if the link integrity is fine otherwise.
Signed-off-by: Oliver Barta
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 19 ---
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 010f37240710..3156fde392f2 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1540,7 +1540,7 @@ int intel_hdmi_hdcp_toggle_signalling(struct
intel_digital_port *intel_dig_port,
}
static
-bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
+bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *intel_dig_port)
{
struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
struct intel_connector *connector =
@@ -1563,8 +1563,7 @@ bool intel_hdmi_hdcp_check_link(struct intel_digital_port
*intel_dig_port)
if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder,
port)) &
(HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) ==
(HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
- drm_err(&i915->drm,
- "Ri' mismatch detected, link check failed (%x)\n",
+ drm_dbg_kms(&i915->drm, "Ri' mismatch detected (%x)\n",
intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder,
port)));
return false;
@@ -1572,6 +1571,20 @@ bool intel_hdmi_hdcp_check_link(struct
intel_digital_port *intel_dig_port)
return true;
}
+static
+bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
+{
+ struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
+ int retry;
+
+ for (retry = 0; retry < 3; retry++)
+ if (intel_hdmi_hdcp_check_link_once(intel_dig_port))
+ return true;
+
+ drm_err(&i915->drm, "Link check failed\n");
+ return false;
+}
+
struct hdcp2_hdmi_msg_timeout {
u8 msg_id;
u16 timeout;
--
2.20.1
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Re: [Intel-gfx] [PATCH] drm/i915: Avoid using simd from interrupt context
On Sun, May 3, 2020 at 2:31 PM Chris Wilson wrote:
>
> Query whether or not we are in a legal context for using SIMD, before
> using SSE4.2 registers.
>
> Suggested-by: Jason A. Donenfeld
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/i915_memcpy.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_memcpy.c
> b/drivers/gpu/drm/i915/i915_memcpy.c
> index 7b3b83bd5ab8..fc18d6c28d5f 100644
> --- a/drivers/gpu/drm/i915/i915_memcpy.c
> +++ b/drivers/gpu/drm/i915/i915_memcpy.c
> @@ -24,6 +24,7 @@
>
> #include
> #include
> +#include
>
> #include "i915_memcpy.h"
>
> @@ -115,6 +116,9 @@ bool i915_memcpy_from_wc(void *dst, const void *src,
> unsigned long len)
> if (unlikely(((unsigned long)dst | (unsigned long)src | len) & 15))
> return false;
>
> + if (unlikely(!may_use_simd()))
> + return false;
> +
> if (static_branch_likely(&has_movntdqa)) {
> if (likely(len))
> __memcpy_ntdqa(dst, src, len >> 4);
> --
> 2.20.1
Looks like you beat me to the punch. Thanks for doing this.
Reviewed-by: Jason A. Donenfeld
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Re: [Intel-gfx] [PATCH 06/22] drm/i915/selftests: Repeat the rps clock frequency measurement
Chris Wilson writes:
> Repeat the measurement of the clock frequency a few times and use the
> median to try and reduce the systematic measurement error.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/gt/selftest_rps.c | 54 +++---
> 1 file changed, 40 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c
> b/drivers/gpu/drm/i915/gt/selftest_rps.c
> index b89a7d7611f6..bfa1a15564f7 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_rps.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
> @@ -56,6 +56,18 @@ static int cmp_u64(const void *A, const void *B)
> return 0;
> }
>
> +static int cmp_u32(const void *A, const void *B)
> +{
> + const u32 *a = A, *b = B;
> +
> + if (a < b)
> + return -1;
> + else if (a > b)
> + return 1;
> + else
> + return 0;
> +}
> +
> static struct i915_vma *
> create_spin_counter(struct intel_engine_cs *engine,
> struct i915_address_space *vm,
> @@ -236,8 +248,8 @@ int live_rps_clock_interval(void *arg)
> for_each_engine(engine, gt, id) {
> unsigned long saved_heartbeat;
> struct i915_request *rq;
> - ktime_t dt;
> u32 cycles;
> + u64 dt;
>
> if (!intel_engine_can_store_dword(engine))
> continue;
> @@ -286,15 +298,29 @@ int live_rps_clock_interval(void *arg)
> engine->name);
> err = -ENODEV;
> } else {
> - preempt_disable();
> - dt = ktime_get();
> - cycles = -intel_uncore_read_fw(gt->uncore,
> -GEN6_RP_CUR_UP_EI);
> - udelay(1000);
> - dt = ktime_sub(ktime_get(), dt);
> - cycles += intel_uncore_read_fw(gt->uncore,
> -GEN6_RP_CUR_UP_EI);
> - preempt_enable();
> + ktime_t dt_[5];
> + u32 cycles_[5];
> + int i;
> +
> + for (i = 0; i < 5; i++) {
Could be sizeof.
Reviewed-by: Mika Kuoppala
> + preempt_disable();
> +
> + dt_[i] = ktime_get();
> + cycles_[i] = -intel_uncore_read_fw(gt->uncore,
> GEN6_RP_CUR_UP_EI);
> +
> + udelay(1000);
> +
> + dt_[i] = ktime_sub(ktime_get(), dt_[i]);
> + cycles_[i] += intel_uncore_read_fw(gt->uncore,
> GEN6_RP_CUR_UP_EI);
> +
> + preempt_enable();
> + }
> +
> + /* Use the median of both cycle/dt; close enough */
> + sort(cycles_, 5, sizeof(*cycles_), cmp_u32, NULL);
> + cycles = (cycles_[1] + 2 * cycles_[2] + cycles_[3]) / 4;
> + sort(dt_, 5, sizeof(*dt_), cmp_u64, NULL);
> + dt = div_u64(dt_[1] + 2 * dt_[2] + dt_[3], 4);
> }
>
> intel_uncore_write_fw(gt->uncore, GEN6_RP_CONTROL, 0);
> @@ -306,14 +332,14 @@ int live_rps_clock_interval(void *arg)
> if (err == 0) {
> u64 time = intel_gt_pm_interval_to_ns(gt, cycles);
> u32 expected =
> - intel_gt_ns_to_pm_interval(gt, ktime_to_ns(dt));
> + intel_gt_ns_to_pm_interval(gt, dt);
>
> pr_info("%s: rps counted %d C0 cycles [%lldns] in
> %lldns [%d cycles], using GT clock frequency of %uKHz\n",
> - engine->name, cycles, time, ktime_to_ns(dt),
> expected,
> + engine->name, cycles, time, dt, expected,
> gt->clock_frequency / 1000);
>
> - if (10 * time < 8 * ktime_to_ns(dt) ||
> - 8 * time > 10 * ktime_to_ns(dt)) {
> + if (10 * time < 8 * dt ||
> + 8 * time > 10 * dt) {
> pr_err("%s: rps clock time does not match
> walltime!\n",
> engine->name);
> err = -EINVAL;
> --
> 2.20.1
>
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gem: Fix inconsistent IS_ERR and PTR_ERR
== Series Details == Series: drm/i915/gem: Fix inconsistent IS_ERR and PTR_ERR URL : https://patchwork.freedesktop.org/series/76916/ State : failure == Summary == Applying: drm/i915/gem: Fix inconsistent IS_ERR and PTR_ERR Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c No changes -- Patch already applied. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH][next] drm/i915/gem: Fix inconsistent IS_ERR and PTR_ERR
Fix inconsistent IS_ERR and PTR_ERR in __reloc_gpu_alloc().
The proper pointer to be passed as argument is ce.
This bug was detected with the help of Coccinelle.
Fixes: 6f576d6277ce ("drm/i915/gem: Try an alternate engine for relocations")
Signed-off-by: Gustavo A. R. Silva
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index cce7df231cb9..78fdbfd068d3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1325,7 +1325,7 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
ce = intel_context_create(engine);
if (IS_ERR(ce)) {
- err = PTR_ERR(rq);
+ err = PTR_ERR(ce);
goto err_unpin;
}
--
2.26.0
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Re: [Intel-gfx] [PATCH] drm/i915: check to see if SIMD registers are available before using SIMD
From: Christoph Hellwig > Sent: 04 May 2020 17:03 > > On Sun, May 03, 2020 at 09:20:19PM +0100, Chris Wilson wrote: > > > Err, why does i915 implements its own uncached memcpy instead of relying > > > on core functionality to start with? > > > > What is this core functionality that provides movntqda? > > A sensible name might be memcpy_uncached or mempcy_nontemporal. > But the important point is that this should be arch code with a common > fallback rather than hacking it up in drivers. More the point, you are trying to do a copy where: 1) The kernel isn't expected to read the data - so can bypass the cache. and maybe: 2) The data needs flushing from the cache to actual memory. and maybe: 3) The cache lines need invalidating. The fallbacks depend on the required behaviour. David - Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK Registration No: 1397386 (Wales) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v26 6/9] drm/i915: Added required new PCode commands
On Thu, Apr 23, 2020 at 10:58:59AM +0300, Stanislav Lisovskiy wrote:
> We need a new PCode request commands and reply codes
> to be added as a prepartion patch for QGV points
> restricting for new SAGV support.
>
> v2: - Extracted those changes into separate patch
> (Ville Syrjälä)
>
> v3: - Moved new PCode masks to another place from
> PCode commands(Ville)
>
> Signed-off-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/i915_reg.h | 5 +
> drivers/gpu/drm/i915/intel_sideband.c | 2 ++
> 2 files changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4a1965467374..5a077a921568 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9086,6 +9086,7 @@ enum {
> #define GEN7_PCODE_ILLEGAL_DATA 0x3
> #define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4
> #define GEN11_PCODE_LOCKED 0x6
> +#define GEN11_PCODE_REJECTED 0x11
> #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
> #define GEN6_PCODE_WRITE_RC6VIDS 0x4
> #define GEN6_PCODE_READ_RC6VIDS0x5
> @@ -9107,6 +9108,7 @@ enum {
> #define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
> #define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO(0x0 << 8)
> #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) <<
> 16) | (0x1 << 8))
> +#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG0xe
> #define GEN6_PCODE_READ_D_COMP 0x10
> #define GEN6_PCODE_WRITE_D_COMP0x11
> #define ICL_PCODE_EXIT_TCCOLD 0x12
> @@ -9140,6 +9142,9 @@ enum {
> #define GEN8_GT_SLICE_INFO _MMIO(0x138064)
> #define GEN8_LSLICESTAT_MASK 0x7
>
> +#define GEN11_PCODE_POINTS_RESTRICTED0x0
> +#define GEN11_PCODE_POINTS_RESTRICTED_MASK 0x1
These still look misplaced. They are things you specify to the
ICL_PCODE_SAGV_DE_MEM_SS_CONFIG command no?
In the meantime pushed patches 2,3,7. With those it looks like
we should finally have sensible sagv support for pre-icl. Yay!
> +
> #define CHV_POWER_SS0_SIG1 _MMIO(0xa720)
> #define CHV_POWER_SS1_SIG1 _MMIO(0xa728)
> #define CHV_SS_PG_ENABLE (1 << 1)
> diff --git a/drivers/gpu/drm/i915/intel_sideband.c
> b/drivers/gpu/drm/i915/intel_sideband.c
> index 14daf6af6854..59ef364549cf 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.c
> +++ b/drivers/gpu/drm/i915/intel_sideband.c
> @@ -371,6 +371,8 @@ static int gen7_check_mailbox_status(u32 mbox)
> return -ENXIO;
> case GEN11_PCODE_LOCKED:
> return -EBUSY;
> + case GEN11_PCODE_REJECTED:
> + return -EACCES;
> case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
> return -EOVERFLOW;
> default:
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
___
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Re: [Intel-gfx] [PATCH] drm/i915: Don't enable WaIncreaseLatencyIPCEnabled when IPC is disabled
On Thu, Apr 30, 2020 at 02:46:54PM -0700, Sultan Alsawaf wrote:
> From: Sultan Alsawaf
>
> In commit 5a7d202b1574, a logical AND was erroneously changed to an OR,
> causing WaIncreaseLatencyIPCEnabled to be enabled unconditionally for
> kabylake and coffeelake, even when IPC is disabled. Fix the logic so
> that WaIncreaseLatencyIPCEnabled is only used when IPC is enabled.
>
> Fixes: 5a7d202b1574 ("drm/i915: Drop WaIncreaseLatencyIPCEnabled/1140 for
> cnl")
> Cc: sta...@vger.kernel.org # 5.3.x+
> Signed-off-by: Sultan Alsawaf
> ---
> drivers/gpu/drm/i915/intel_pm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 8375054ba27d..a52986a9e7a6 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4992,7 +4992,7 @@ static void skl_compute_plane_wm(const struct
> intel_crtc_state *crtc_state,
>* WaIncreaseLatencyIPCEnabled: kbl,cfl
>* Display WA #1141: kbl,cfl
>*/
> - if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) ||
> + if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) &&
Whoops. Thanks for the fix. Pushed.
> dev_priv->ipc_enabled)
> latency += 4;
>
> --
> 2.26.2
--
Ville Syrjälä
Intel
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gem: Implement legacy MI_STORE_DATA_IMM (rev2)
== Series Details ==
Series: drm/i915/gem: Implement legacy MI_STORE_DATA_IMM (rev2)
URL : https://patchwork.freedesktop.org/series/76866/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8419 -> Patchwork_17570
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17570/index.html
New tests
-
New tests have been introduced between CI_DRM_8419 and Patchwork_17570:
### New IGT tests (1) ###
* igt@i915_selftest@live@gem_execbuf:
- Statuses : 41 pass(s)
- Exec time: [0.46, 2.62] s
Known issues
Here are the changes found in Patchwork_17570 that come from known issues:
### IGT changes ###
Possible fixes
* igt@kms_chamelium@dp-crc-fast:
- fi-cml-u2: [FAIL][1] ([i915#262]) -> [PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8419/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17570/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
* {igt@kms_flip@basic-flip-vs-wf_vblank@a-vga1}:
- fi-pnv-d510:[FAIL][3] ([i915#34]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8419/fi-pnv-d510/igt@kms_flip@basic-flip-vs-wf_vbl...@a-vga1.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17570/fi-pnv-d510/igt@kms_flip@basic-flip-vs-wf_vbl...@a-vga1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
[i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
Participating hosts (51 -> 44)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_8419 -> Patchwork_17570
CI-20190529: 20190529
CI_DRM_8419: 4331ff197d0a7330c311830569aee90bab940694 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5628: 652a3fd8966345fa5498904ce80a2027a6782783 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17570: ff32ff0a01797ee7c806f0f18b0da8d4be57366b @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
ff32ff0a0179 drm/i915/gem: Implement legacy MI_STORE_DATA_IMM
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17570/index.html
___
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Don't enable WaIncreaseLatencyIPCEnabled when IPC is disabled
== Series Details == Series: drm/i915: Don't enable WaIncreaseLatencyIPCEnabled when IPC is disabled URL : https://patchwork.freedesktop.org/series/76889/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8415_full -> Patchwork_17562_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_17562_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17562_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_17562_full: ### IGT changes ### Possible regressions * igt@gem_mmap_offset@open-flood: - shard-kbl: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8415/shard-kbl1/igt@gem_mmap_off...@open-flood.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17562/shard-kbl4/igt@gem_mmap_off...@open-flood.html Known issues Here are the changes found in Patchwork_17562_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_render_copy@yf-tiled-ccs-to-y-tiled-ccs: - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#165]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8415/shard-kbl2/igt@gem_render_c...@yf-tiled-ccs-to-y-tiled-ccs.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17562/shard-kbl2/igt@gem_render_c...@yf-tiled-ccs-to-y-tiled-ccs.html * igt@kms_cursor_edge_walk@pipe-a-256x256-bottom-edge: - shard-apl: [PASS][5] -> [FAIL][6] ([i915#70] / [i915#95]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8415/shard-apl3/igt@kms_cursor_edge_w...@pipe-a-256x256-bottom-edge.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17562/shard-apl4/igt@kms_cursor_edge_w...@pipe-a-256x256-bottom-edge.html * igt@kms_dp_dsc@basic-dsc-enable-edp: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109349]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8415/shard-iclb2/igt@kms_dp_...@basic-dsc-enable-edp.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17562/shard-iclb4/igt@kms_dp_...@basic-dsc-enable-edp.html * igt@kms_fence_pin_leak: - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([i915#78]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8415/shard-kbl2/igt@kms_fence_pin_leak.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17562/shard-kbl2/igt@kms_fence_pin_leak.html * igt@kms_flip_tiling@flip-changes-tiling-y: - shard-apl: [PASS][11] -> [FAIL][12] ([i915#95]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8415/shard-apl7/igt@kms_flip_til...@flip-changes-tiling-y.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17562/shard-apl7/igt@kms_flip_til...@flip-changes-tiling-y.html - shard-kbl: [PASS][13] -> [FAIL][14] ([i915#699] / [i915#93] / [i915#95]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8415/shard-kbl2/igt@kms_flip_til...@flip-changes-tiling-y.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17562/shard-kbl2/igt@kms_flip_til...@flip-changes-tiling-y.html * igt@kms_hdr@bpc-switch-dpms: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#1188]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8415/shard-skl5/igt@kms_...@bpc-switch-dpms.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17562/shard-skl9/igt@kms_...@bpc-switch-dpms.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - shard-snb: [PASS][17] -> [SKIP][18] ([fdo#109271]) +4 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8415/shard-snb5/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-b.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17562/shard-snb2/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-b.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([i915#180]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8415/shard-kbl6/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17562/shard-kbl1/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-apl: [PASS][21] -> [DMESG-WARN][22] ([i915#180]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8415/shard-apl2/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-c-planes.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17562/shard-apl1/igt@kms_pl...@plane-panning-bottom-right
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gem: Implement legacy MI_STORE_DATA_IMM (rev2)
== Series Details == Series: drm/i915/gem: Implement legacy MI_STORE_DATA_IMM (rev2) URL : https://patchwork.freedesktop.org/series/76866/ State : warning == Summary == $ dim checkpatch origin/drm-tip ff32ff0a0179 drm/i915/gem: Implement legacy MI_STORE_DATA_IMM -:339: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #339: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 562 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/6] drm/i915: Mark concurrent submissions with a weak-dependency
== Series Details ==
Series: series starting with [1/6] drm/i915: Mark concurrent submissions with a
weak-dependency
URL : https://patchwork.freedesktop.org/series/76912/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8419 -> Patchwork_17569
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_17569 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_17569, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17569/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_17569:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live@execlists:
- fi-icl-u2: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8419/fi-icl-u2/igt@i915_selftest@l...@execlists.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17569/fi-icl-u2/igt@i915_selftest@l...@execlists.html
New tests
-
New tests have been introduced between CI_DRM_8419 and Patchwork_17569:
### New IGT tests (1) ###
* igt@dmabuf@all@dma_fence_proxy:
- Statuses : 40 pass(s)
- Exec time: [0.03, 0.10] s
Known issues
Here are the changes found in Patchwork_17569 that come from known issues:
### IGT changes ###
Possible fixes
* igt@kms_chamelium@dp-crc-fast:
- fi-cml-u2: [FAIL][3] ([i915#262]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8419/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17569/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
* {igt@kms_flip@basic-flip-vs-wf_vblank@a-vga1}:
- fi-pnv-d510:[FAIL][5] ([i915#34]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8419/fi-pnv-d510/igt@kms_flip@basic-flip-vs-wf_vbl...@a-vga1.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17569/fi-pnv-d510/igt@kms_flip@basic-flip-vs-wf_vbl...@a-vga1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
[i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
Participating hosts (51 -> 44)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_8419 -> Patchwork_17569
CI-20190529: 20190529
CI_DRM_8419: 4331ff197d0a7330c311830569aee90bab940694 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5628: 652a3fd8966345fa5498904ce80a2027a6782783 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17569: 8bd2f81ece028dc8a4c91f64d193d7f563ddcc64 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
8bd2f81ece02 drm/i915/gt: Declare when we enabled timeslicing
ce52e4177208 drm/i915/gem: Allow combining submit-fences with syncobj
09b46dbf7d9f drm/i915/gem: Teach execbuf how to wait on future syncobj
2f097bd40cbf drm/syncobj: Allow use of dma-fence-proxy
55c216ab5caf dma-buf: Proxy fence, an unsignaled fence placeholder
aa08f9739363 drm/i915: Mark concurrent submissions with a weak-dependency
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17569/index.html
___
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Re: [Intel-gfx] [PATCH 04/12] drm/i915/fbc: Fix nuke for pre-snb platforms
On Fri, May 01, 2020 at 06:18:18PM -0700, Matt Roper wrote:
> On Wed, Apr 29, 2020 at 01:10:26PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > The MSG_FBC_REND_STATE register only exists on snb+. For older
>
> I only find this register in the bspec for HSW+. Is the spec incomplete
> or am I looking in the wrong place?
The docs are a bit of a mess around this area. IIRC this rcs nuke
workaround was documented for ivb+ (presumably due to ppgtt).
I thinka the bltter counterpart (part of the BCS_ECOSKPD dance)
was documented for SNB as well which implies the register is there
and working. Also the fact that the code works does confirm that.
We're not really following much of the documented stuff for
FBC since we basically don't use the hardware tracking all.
So the value of the docs is mostly in finding the right bits
to cause nukes and turn off hw tracking as much as possible.
>
> It's a bit hard to review these changes for older platforms since there
> doesn't really seem to be much FBC/DPFC documentation at all in the
> bspec until we get to BDW and beyond. The only explicit mention I can
> find of nuke-on-flip for older platforms is a SNB-specific bit in
> FBC_CTL that disables that behavior. Do you have other documents that
> clarify that this will indeed work farther back?
gen2-gen4 bspec has slightly better docs on FBC compared to more recent
platforms. Sadly I've never been able to find a way to trigger a nuke
explicitly, hence we resort to (ab)using a flip nuke.
>
>
> Matt
>
> > platforms (would also work for snb+) we can simply rewite DSPSURF
> > to trigger a flip nuke.
> >
> > While generally RMW is considered harmful we'll use it here for
> > simplicity. And since FBC doesn't exist in i830 we don't have to
> > worry about the DSPSURF double buffering hardware fails present
> > on that platform.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/display/intel_fbc.c | 34 +++-
> > 1 file changed, 33 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index 613ab499d42e..983224e07eaf 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -188,8 +188,30 @@ static bool g4x_fbc_is_active(struct drm_i915_private
> > *dev_priv)
> > return intel_de_read(dev_priv, DPFC_CONTROL) & DPFC_CTL_EN;
> > }
> >
> > +static void i8xx_fbc_recompress(struct drm_i915_private *dev_priv)
> > +{
> > + struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
> > + enum i9xx_plane_id i9xx_plane = params->crtc.i9xx_plane;
> > +
> > + spin_lock_irq(&dev_priv->uncore.lock);
> > + intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane),
> > + intel_de_read_fw(dev_priv, DSPADDR(i9xx_plane)));
> > + spin_unlock_irq(&dev_priv->uncore.lock);
> > +}
> > +
> > +static void i965_fbc_recompress(struct drm_i915_private *dev_priv)
> > +{
> > + struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
> > + enum i9xx_plane_id i9xx_plane = params->crtc.i9xx_plane;
> > +
> > + spin_lock_irq(&dev_priv->uncore.lock);
> > + intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
> > + intel_de_read_fw(dev_priv, DSPSURF(i9xx_plane)));
> > + spin_unlock_irq(&dev_priv->uncore.lock);
> > +}
> > +
> > /* This function forces a CFB recompression through the nuke operation. */
> > -static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
> > +static void snb_fbc_recompress(struct drm_i915_private *dev_priv)
> > {
> > struct intel_fbc *fbc = &dev_priv->fbc;
> >
> > @@ -199,6 +221,16 @@ static void intel_fbc_recompress(struct
> > drm_i915_private *dev_priv)
> > intel_de_posting_read(dev_priv, MSG_FBC_REND_STATE);
> > }
> >
> > +static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
> > +{
> > + if (INTEL_GEN(dev_priv) >= 6)
> > + snb_fbc_recompress(dev_priv);
> > + else if (INTEL_GEN(dev_priv) >= 4)
> > + i965_fbc_recompress(dev_priv);
> > + else
> > + i8xx_fbc_recompress(dev_priv);
> > +}
> > +
> > static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
> > {
> > struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
> > --
> > 2.24.1
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795
--
Ville Syrjälä
Intel
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/6] drm/i915: Mark concurrent submissions with a weak-dependency
== Series Details == Series: series starting with [1/6] drm/i915: Mark concurrent submissions with a weak-dependency URL : https://patchwork.freedesktop.org/series/76912/ State : warning == Summary == $ dim checkpatch origin/drm-tip aa08f9739363 drm/i915: Mark concurrent submissions with a weak-dependency 55c216ab5caf dma-buf: Proxy fence, an unsignaled fence placeholder -:45: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #45: new file mode 100644 -:387: CHECK:UNCOMMENTED_DEFINITION: spinlock_t definition without comment #387: FILE: drivers/dma-buf/st-dma-fence-proxy.c:20: + spinlock_t lock; -:547: WARNING:MEMORY_BARRIER: memory barrier without comment #547: FILE: drivers/dma-buf/st-dma-fence-proxy.c:180: + smp_store_mb(container_of(cb, struct simple_cb, cb)->seen, true); total: 0 errors, 2 warnings, 1 checks, 1050 lines checked 2f097bd40cbf drm/syncobj: Allow use of dma-fence-proxy 09b46dbf7d9f drm/i915/gem: Teach execbuf how to wait on future syncobj ce52e4177208 drm/i915/gem: Allow combining submit-fences with syncobj 8bd2f81ece02 drm/i915/gt: Declare when we enabled timeslicing ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 02/12] drm/i915/fbc: Use the correct plane stride
On Fri, May 01, 2020 at 05:16:13PM -0700, Matt Roper wrote:
> On Wed, Apr 29, 2020 at 06:29:21PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Consult the actual plane stride instead of the fb stride. The two
> > will disagree when we remap the gtt. The plane stride is what the
> > hw will be fed so that's what we should look at for the FBC
> > retrictions/cfb allocation.
> >
> > Since we no longer require a fence we are going to attempt using
> > FBC with remapping, and so we should look at correct stride.
> >
> > With 90/270 degree rotation the plane stride is stored in units
> > of pixels, so we need to conver it to bytes for the purposes
> > of calculating the cfb stride. Not entirely sure if this matches
> > the hw behaviour though. Need to reverse engineer that at some
> > point...
> >
> > We also need to reorder the pixel format check vs. stride check
> > to avoid triggering a spurious WARN(stride & 63) with cpp==1 and
> > plane stride==32.
> >
> > v2: Try to deal with rotated stride and related WARN
> >
> > Cc: José Roberto de Souza
> > Fixes: 691f7ba58d52 ("drm/i915/display/fbc: Make fences a nice-to-have for
> > GEN9+")
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/display/intel_fbc.c | 16 ++--
> > 1 file changed, 10 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index 7194f9bc62c5..7f2b2382b813 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -707,9 +707,13 @@ static void intel_fbc_update_state_cache(struct
> > intel_crtc *crtc,
> > cache->plane.pixel_blend_mode = plane_state->hw.pixel_blend_mode;
> >
> > cache->fb.format = fb->format;
> > - cache->fb.stride = fb->pitches[0];
> > cache->fb.modifier = fb->modifier;
> >
> > + /* FIXME is this correct? */
> > + cache->fb.stride = plane_state->color_plane[0].stride;
>
> We still have a comment in intel_fbc_calculate_cfb_size() that indicates
> that we need to use the framebuffer stride instead of the plane stride
> (explicitly added in commit 850bfaab7120a).
That's not really what it's saying. full buffer stride == plane stride,
vs. active area == plane width
> The bspec (page 49227) uses
> terminology "Stride of plane uncompressed surface" which sounds like
> framebuffer size to me; I'm not sure if switching it to the plane's size
> will cause problems if the plane is only scanning out a subregion of the
> framebuffer?
There is no framebuffer stride as far as the hardware is concerned.
There is only plane width and plane stride.
>
> If it really is safe to use the plane size instead of the framebuffer
> size, then I think we at least need to remove or change that comment
> too.
>
>
> Matt
>
> > + if (drm_rotation_90_or_270(plane_state->hw.rotation))
> > + cache->fb.stride *= fb->format->cpp[0];
> > +
> > drm_WARN_ON(&dev_priv->drm, plane_state->flags & PLANE_HAS_FENCE &&
> > !plane_state->vma->fence);
> >
> > @@ -804,6 +808,11 @@ static bool intel_fbc_can_activate(struct intel_crtc
> > *crtc)
> > return false;
> > }
> >
> > + if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) {
> > + fbc->no_fbc_reason = "pixel format is invalid";
> > + return false;
> > + }
> > +
> > if (!rotation_is_valid(dev_priv, cache->fb.format->format,
> >cache->plane.rotation)) {
> > fbc->no_fbc_reason = "rotation unsupported";
> > @@ -820,11 +829,6 @@ static bool intel_fbc_can_activate(struct intel_crtc
> > *crtc)
> > return false;
> > }
> >
> > - if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) {
> > - fbc->no_fbc_reason = "pixel format is invalid";
> > - return false;
> > - }
> > -
> > if (cache->plane.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE &&
> > cache->fb.format->has_alpha) {
> > fbc->no_fbc_reason = "per-pixel alpha blending is incompatible
> > with FBC";
> > --
> > 2.24.1
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH] drm/i915/display: Warn if the FBC is still writing to stolen on removal
Quoting Ville Syrjälä (2020-05-04 14:49:28)
> On Sun, May 03, 2020 at 07:00:34PM +0100, Chris Wilson wrote:
> > If the FBC is still writing into stolen, it will overwrite any future
> > users of that stolen region. Check before release.
> >
> > References: https://gitlab.freedesktop.org/drm/intel/-/issues/1635
> > Signed-off-by: Chris Wilson
> > ---
> > drivers/gpu/drm/i915/display/intel_fbc.c | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index c6afa10e814c..37244ed92ae4 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -540,6 +540,9 @@ static void __intel_fbc_cleanup_cfb(struct
> > drm_i915_private *dev_priv)
> > {
> > struct intel_fbc *fbc = &dev_priv->fbc;
> >
> > + if (WARN_ON(intel_fbc_hw_is_active(dev_priv)))
> > + return;
> > +
>
> Can't immediately see how that would hapoen, but no harm in checking.
I'm clutching at straws to explain how come fi-bxt-dsi is overwriting
<7> [592.789844] heartbeat [] f0101011 f12ff12f f12ff12f f12ff12f f12ff12f
f12ff12f f12ff12f f12ff12f
<7> [592.789853] heartbeat [0020] f12ff12f f12ff12f f12ff12f f12ff12f f12ff12f
f12ff12f f12ff12f f12ff12f
<7> [592.789860] heartbeat *
<7> [592.789869] heartbeat [0060] f12ff12f f12ff12f f12ff12f f12ff12f c12ff12f
f10f f12ff12f f12ff12f
into sensitive locations. My theory is that it is stolen memory being
clobbers with what looks like some odd pixel data. FBC being a suspect,
hence getting something like this check in place for the idle runs and
see what turns up.
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/22] drm/i915: Allow some leniency in PCU reads (rev2)
== Series Details == Series: series starting with [01/22] drm/i915: Allow some leniency in PCU reads (rev2) URL : https://patchwork.freedesktop.org/series/76885/ State : success == Summary == CI Bug Log - changes from CI_DRM_8418 -> Patchwork_17568 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17568/index.html New tests - New tests have been introduced between CI_DRM_8418 and Patchwork_17568: ### New IGT tests (2) ### * igt@dmabuf@all@dma_fence_proxy: - Statuses : 41 pass(s) - Exec time: [0.03, 0.10] s * igt@i915_selftest@live@gem_execbuf: - Statuses : 41 pass(s) - Exec time: [0.42, 2.55] s Known issues Here are the changes found in Patchwork_17568 that come from known issues: ### IGT changes ### Possible fixes * igt@i915_selftest@live@gt_pm: - fi-bwr-2160:[INCOMPLETE][1] ([i915#489]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8418/fi-bwr-2160/igt@i915_selftest@live@gt_pm.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17568/fi-bwr-2160/igt@i915_selftest@live@gt_pm.html Warnings * igt@i915_pm_rpm@module-reload: - fi-kbl-x1275: [SKIP][3] ([fdo#109271]) -> [FAIL][4] ([i915#62]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8418/fi-kbl-x1275/igt@i915_pm_...@module-reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17568/fi-kbl-x1275/igt@i915_pm_...@module-reload.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#489]: https://gitlab.freedesktop.org/drm/intel/issues/489 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 Participating hosts (51 -> 44) -- Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8418 -> Patchwork_17568 CI-20190529: 20190529 CI_DRM_8418: bdfc2bf07b3e68612db8955fc3df80ad5b6c9a8d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5628: 652a3fd8966345fa5498904ce80a2027a6782783 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17568: 521d3542c857f910bfff1940ced5f65412023df2 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 521d3542c857 drm/i915/gem: Bind the fence async for execbuf 85b00e9cfc8b drm/i915/gem: Asynchronous GTT unbinding be6fb364f8d6 drm/i915/gem: Separate the ww_mutex walker into its own list ed2c711193c2 drm/i915: Export a preallocate variant of i915_active_acquire() a22d55e2deae drm/i915/gem: Assign context id for async work 4326f797fff7 drm/i915: Always defer fenced work to the worker f09d9b73e50d drm/i915: Drop I915_IDLE_ENGINES_TIMEOUT 961120507200 drm/i915: Drop I915_RESET_TIMEOUT and friends d53f22cfe300 drm/i915: Replace the hardcoded I915_FENCE_TIMEOUT 790bb35fea74 drm/i915/gt: Declare when we enabled timeslicing 33eac422e35d drm/i915/gem: Allow combining submit-fences with syncobj b0aa4798a0df drm/i915/gem: Teach execbuf how to wait on future syncobj 490d576eff67 drm/syncobj: Allow use of dma-fence-proxy 3874422ce21d dma-buf: Proxy fence, an unsignaled fence placeholder 2c95e99a6959 drm/i915/gt: Stop holding onto the pinned_default_state de29266bc3fa drm/i915/selftests: Repeat the rps clock frequency measurement 16d136335185 drm/i915: Mark concurrent submissions with a weak-dependency b97355c82125 drm/i915/gt: Small tidy of gen8+ breadcrumb emission e515da211062 drm/i915/gem: Implement legacy MI_STORE_DATA_IMM 3420e18d19f1 drm/i915/gem: Specify address type for chained reloc batches == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17568/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI] drm/i915/gem: Implement legacy MI_STORE_DATA_IMM
The older arches did not convert MI_STORE_DATA_IMM to using the GTT, but
left them writing to a physical address. The notes suggest that the
primary reason would be so that the writes were cache coherent, as the
CPU cache uses physical tagging. As such we did not implement the
legacy variant of MI_STORE_DATA_IMM and so left all the relocations
synchronous -- but with a small function to convert from the vma address
into the physical address, we can implement asynchronous relocs on these
older arches, fixing up a few tests that require them.
In order to be able to test the legacy paths, refactor the gpu
relocations so that we can hook them up to a selftest.
v2: Use an array of offsets not enum labels for the selftest
v3: Refactor the common igt_hexdump()
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/757
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 204 +++---
.../i915/gem/selftests/i915_gem_client_blt.c | 31 +--
.../i915/gem/selftests/i915_gem_execbuffer.c | 171 +++
drivers/gpu/drm/i915/gt/selftest_lrc.c| 33 +--
drivers/gpu/drm/i915/i915_selftest.h | 2 +
.../drm/i915/selftests/i915_live_selftests.h | 1 +
.../gpu/drm/i915/selftests/i915_selftest.c| 29 +++
7 files changed, 336 insertions(+), 135 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 1c247ad0971a..966523a8503f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -955,7 +955,7 @@ static void reloc_cache_init(struct reloc_cache *cache,
cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment;
cache->node.flags = 0;
cache->rq = NULL;
- cache->rq_size = 0;
+ cache->target = NULL;
}
static inline void *unmask_page(unsigned long p)
@@ -1325,7 +1325,7 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
ce = intel_context_create(engine);
if (IS_ERR(ce)) {
- err = PTR_ERR(rq);
+ err = PTR_ERR(ce);
goto err_unpin;
}
@@ -1376,6 +1376,11 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
return err;
}
+static bool reloc_can_use_engine(const struct intel_engine_cs *engine)
+{
+ return engine->class != VIDEO_DECODE_CLASS || !IS_GEN(engine->i915, 6);
+}
+
static u32 *reloc_gpu(struct i915_execbuffer *eb,
struct i915_vma *vma,
unsigned int len)
@@ -1387,9 +1392,9 @@ static u32 *reloc_gpu(struct i915_execbuffer *eb,
if (unlikely(!cache->rq)) {
struct intel_engine_cs *engine = eb->engine;
- if (!intel_engine_can_store_dword(engine)) {
+ if (!reloc_can_use_engine(engine)) {
engine = engine->gt->engine_class[COPY_ENGINE_CLASS][0];
- if (!engine || !intel_engine_can_store_dword(engine))
+ if (!engine)
return ERR_PTR(-ENODEV);
}
@@ -1435,91 +1440,138 @@ static inline bool use_reloc_gpu(struct i915_vma *vma)
return !dma_resv_test_signaled_rcu(vma->resv, true);
}
-static u64
-relocate_entry(struct i915_vma *vma,
- const struct drm_i915_gem_relocation_entry *reloc,
- struct i915_execbuffer *eb,
- const struct i915_vma *target)
+static unsigned long vma_phys_addr(struct i915_vma *vma, u32 offset)
{
- u64 offset = reloc->offset;
- u64 target_offset = relocation_target(reloc, target);
- bool wide = eb->reloc_cache.use_64bit_reloc;
- void *vaddr;
+ struct page *page;
+ unsigned long addr;
- if (!eb->reloc_cache.vaddr && use_reloc_gpu(vma)) {
- const unsigned int gen = eb->reloc_cache.gen;
- unsigned int len;
- u32 *batch;
- u64 addr;
+ GEM_BUG_ON(vma->pages != vma->obj->mm.pages);
- if (wide)
- len = offset & 7 ? 8 : 5;
- else if (gen >= 4)
- len = 4;
- else
- len = 3;
+ page = i915_gem_object_get_page(vma->obj, offset >> PAGE_SHIFT);
+ addr = PFN_PHYS(page_to_pfn(page));
+ GEM_BUG_ON(overflows_type(addr, u32)); /* expected dma32 */
- batch = reloc_gpu(eb, vma, len);
- if (IS_ERR(batch))
- goto repeat;
+ return addr + offset_in_page(offset);
+}
+
+static bool __reloc_entry_gpu(struct i915_execbuffer *eb,
+ struct i915_vma *vma,
+ u64 offset,
+ u64 target_addr)
+{
+
Re: [Intel-gfx] Wait-for-submit on future syncobj
Quoting Chris Wilson (2020-05-04 14:50:24)
> A simplified example of out-of-order execution that is required by iris:
>
> struct drm_i915_gem_exec_object2 obj = {
> .offset = 24 << 20,
> .handle = future_submit_batch(i915, 24 << 20),
> .flags = EXEC_OBJECT_PINNED,
> };
> struct drm_i915_gem_exec_fence fence = {
> .handle = syncobj_create(i915, 0),
> };
> struct drm_i915_gem_execbuffer2 execbuf = {
> .buffers_ptr = to_user_pointer(&obj),
> .buffer_count = 1,
> .cliprects_ptr = to_user_pointer(&fence),
> .num_cliprects = 1,
> .flags = engine | I915_EXEC_FENCE_ARRAY,
> };
> uint32_t result;
> int out;
>
> /*
> * Here we submit client A waiting on client B, but internally client
> * B has a semaphore that waits on client A. This relies on
> timeslicing
> * to reorder B before A, even though userspace has asked to submit
A before B
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[Intel-gfx] [PATCH 2/6] dma-buf: Proxy fence, an unsignaled fence placeholder
Often we need to create a fence for a future event that has not yet been
associated with a fence. We can store a proxy fence, a placeholder, in
the timeline and replace it later when the real fence is known. Any
listeners that attach to the proxy fence will automatically be signaled
when the real fence completes, and any future listeners will instead be
attach directly to the real fence avoiding any indirection overhead.
Signed-off-by: Chris Wilson
Cc: Lionel Landwerlin
---
drivers/dma-buf/Makefile | 13 +-
drivers/dma-buf/dma-fence-private.h | 20 +
drivers/dma-buf/dma-fence-proxy.c| 255 ++
drivers/dma-buf/dma-fence.c | 4 +-
drivers/dma-buf/selftests.h | 1 +
drivers/dma-buf/st-dma-fence-proxy.c | 699 +++
include/linux/dma-fence-proxy.h | 34 ++
7 files changed, 1022 insertions(+), 4 deletions(-)
create mode 100644 drivers/dma-buf/dma-fence-private.h
create mode 100644 drivers/dma-buf/dma-fence-proxy.c
create mode 100644 drivers/dma-buf/st-dma-fence-proxy.c
create mode 100644 include/linux/dma-fence-proxy.h
diff --git a/drivers/dma-buf/Makefile b/drivers/dma-buf/Makefile
index 995e05f609ff..afaf6dadd9a3 100644
--- a/drivers/dma-buf/Makefile
+++ b/drivers/dma-buf/Makefile
@@ -1,6 +1,12 @@
# SPDX-License-Identifier: GPL-2.0-only
-obj-y := dma-buf.o dma-fence.o dma-fence-array.o dma-fence-chain.o \
-dma-resv.o seqno-fence.o
+obj-y := \
+ dma-buf.o \
+ dma-fence.o \
+ dma-fence-array.o \
+ dma-fence-chain.o \
+ dma-fence-proxy.o \
+ dma-resv.o \
+ seqno-fence.o
obj-$(CONFIG_DMABUF_HEAPS) += dma-heap.o
obj-$(CONFIG_DMABUF_HEAPS) += heaps/
obj-$(CONFIG_SYNC_FILE)+= sync_file.o
@@ -10,6 +16,7 @@ obj-$(CONFIG_UDMABUF) += udmabuf.o
dmabuf_selftests-y := \
selftest.o \
st-dma-fence.o \
- st-dma-fence-chain.o
+ st-dma-fence-chain.o \
+ st-dma-fence-proxy.o
obj-$(CONFIG_DMABUF_SELFTESTS) += dmabuf_selftests.o
diff --git a/drivers/dma-buf/dma-fence-private.h
b/drivers/dma-buf/dma-fence-private.h
new file mode 100644
index ..6924d28af0fa
--- /dev/null
+++ b/drivers/dma-buf/dma-fence-private.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Fence mechanism for dma-buf and to allow for asynchronous dma access
+ *
+ * Copyright (C) 2012 Canonical Ltd
+ * Copyright (C) 2012 Texas Instruments
+ *
+ * Authors:
+ * Rob Clark
+ * Maarten Lankhorst
+ */
+
+#ifndef DMA_FENCE_PRIVATE_H
+#define DMA_FENCE_PRIAVTE_H
+
+struct dma_fence;
+
+bool __dma_fence_enable_signaling(struct dma_fence *fence);
+
+#endif /* DMA_FENCE_PRIAVTE_H */
diff --git a/drivers/dma-buf/dma-fence-proxy.c
b/drivers/dma-buf/dma-fence-proxy.c
new file mode 100644
index ..d6cde1f30ef4
--- /dev/null
+++ b/drivers/dma-buf/dma-fence-proxy.c
@@ -0,0 +1,255 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * dma-fence-proxy: placeholder unsignaled fence
+ *
+ * Copyright (C) 2017-2019 Intel Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "dma-fence-private.h"
+
+struct dma_fence_proxy {
+ struct dma_fence base;
+
+ struct dma_fence *real;
+ struct dma_fence_cb cb;
+ struct irq_work work;
+
+ wait_queue_head_t wq;
+};
+
+#ifdef CONFIG_DEBUG_LOCK_ALLOC
+#define same_lockclass(A, B) (A)->dep_map.key == (B)->dep_map.key
+#else
+#define same_lockclass(A, B) 0
+#endif
+
+static const char *proxy_get_driver_name(struct dma_fence *fence)
+{
+ struct dma_fence_proxy *p = container_of(fence, typeof(*p), base);
+ struct dma_fence *real = READ_ONCE(p->real);
+
+ return real ? real->ops->get_driver_name(real) : "proxy";
+}
+
+static const char *proxy_get_timeline_name(struct dma_fence *fence)
+{
+ struct dma_fence_proxy *p = container_of(fence, typeof(*p), base);
+ struct dma_fence *real = READ_ONCE(p->real);
+
+ return real ? real->ops->get_timeline_name(real) : "unset";
+}
+
+static void proxy_irq_work(struct irq_work *work)
+{
+ struct dma_fence_proxy *p = container_of(work, typeof(*p), work);
+
+ dma_fence_signal(&p->base);
+ dma_fence_put(&p->base);
+}
+
+static void proxy_callback(struct dma_fence *real, struct dma_fence_cb *cb)
+{
+ struct dma_fence_proxy *p = container_of(cb, typeof(*p), cb);
+
+ if (real->error)
+ dma_fence_set_error(&p->base, real->error);
+
+ /* Lower the height of the proxy chain -> single stack frame */
+ irq_work_queue(&p->work);
+}
+
+static bool proxy_enable_signaling(struct dma_fence *fence)
+{
+ struct dma_fence_proxy *p = container_of(fence, typeof(*p), base);
+ struct dma_fence *real = READ_ONCE(p->real);
+ bool ret = true;
+
+ if (real) {
+ spin_lock_nested(real->lock,
+same_lockclass(&p->wq.lock, real->lock));
+ ret = __dma_fence_enable_si
[Intel-gfx] [PATCH 4/6] drm/i915/gem: Teach execbuf how to wait on future syncobj
If a syncobj has not yet been assigned, treat it as a future fence and
install and wait upon a dma-fence-proxy. The proxy will be replace by
the real fence later, and that fence will be responsible for signaling
our waiter.
Link: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4854
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 21 +++-
drivers/gpu/drm/i915/i915_request.c | 113 ++
2 files changed, 132 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index cce7df231cb9..71e4dbf7b9a8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -5,6 +5,7 @@
*/
#include
+#include
#include
#include
#include
@@ -2472,8 +2473,24 @@ await_fence_array(struct i915_execbuffer *eb,
continue;
fence = drm_syncobj_fence_get(syncobj);
- if (!fence)
- return -EINVAL;
+ if (!fence) {
+ struct dma_fence *old;
+
+ fence = dma_fence_create_proxy();
+ if (!fence)
+ return -ENOMEM;
+
+ spin_lock(&syncobj->lock);
+ old = rcu_dereference_protected(syncobj->fence, true);
+ if (unlikely(old)) {
+ dma_fence_put(fence);
+ fence = dma_fence_get(old);
+ } else {
+ rcu_assign_pointer(syncobj->fence,
+ dma_fence_get(fence));
+ }
+ spin_unlock(&syncobj->lock);
+ }
err = i915_request_await_dma_fence(eb->request, fence);
dma_fence_put(fence);
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 95edc5523a01..8583fe5bb3b6 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -23,6 +23,7 @@
*/
#include
+#include
#include
#include
#include
@@ -1065,6 +1066,116 @@ i915_request_await_request(struct i915_request *to,
struct i915_request *from)
return 0;
}
+struct await_proxy {
+ struct wait_queue_entry base;
+ struct i915_request *request;
+ struct dma_fence *fence;
+ struct timer_list timer;
+ struct work_struct work;
+ int (*attach)(struct await_proxy *ap);
+ void *data;
+};
+
+static void await_proxy_work(struct work_struct *work)
+{
+ struct await_proxy *ap = container_of(work, typeof(*ap), work);
+ struct i915_request *rq = ap->request;
+ int err;
+
+ del_timer_sync(&ap->timer);
+
+ if (ap->fence) {
+ mutex_lock(&rq->context->timeline->mutex);
+ err = ap->attach(ap);
+ mutex_unlock(&rq->context->timeline->mutex);
+ if (err < 0)
+ i915_sw_fence_set_error_once(&rq->submit, err);
+ }
+
+ i915_sw_fence_complete(&rq->submit);
+
+ dma_fence_put(ap->fence);
+ kfree(ap);
+}
+
+static int
+await_proxy_wake(struct wait_queue_entry *entry,
+unsigned int mode,
+int flags,
+void *fence)
+{
+ struct await_proxy *ap = container_of(entry, typeof(*ap), base);
+
+ ap->fence = dma_fence_get(fence);
+ schedule_work(&ap->work);
+
+ return 0;
+}
+
+static void
+await_proxy_timer(struct timer_list *t)
+{
+ struct await_proxy *ap = container_of(t, typeof(*ap), timer);
+
+ if (dma_fence_remove_proxy_listener(ap->base.private, &ap->base)) {
+ struct i915_request *rq = ap->request;
+
+ pr_notice("Asynchronous wait on unset proxy fence by %s:%s:%llx
timed out\n",
+ rq->fence.ops->get_driver_name(&rq->fence),
+ rq->fence.ops->get_timeline_name(&rq->fence),
+ rq->fence.seqno);
+ i915_sw_fence_set_error_once(&rq->submit, -ETIMEDOUT);
+
+ schedule_work(&ap->work);
+ }
+}
+
+static int
+__i915_request_await_proxy(struct i915_request *rq,
+ struct dma_fence *fence,
+ unsigned long timeout,
+ int (*attach)(struct await_proxy *ap),
+ void *data)
+{
+ struct await_proxy *ap;
+
+ ap = kzalloc(sizeof(*ap), I915_FENCE_GFP);
+ if (!ap)
+ return -ENOMEM;
+
+ i915_sw_fence_await(&rq->submit);
+
+ ap->base.private = fence;
+ ap->base.func = await_proxy_wake;
+ ap->request = rq;
+ INIT_WORK(&ap->work, await_proxy_work);
+ ap->attach = attach;
+ ap->data = data;
+
+ timer_setup(&ap->timer, await
[Intel-gfx] [PATCH 5/6] drm/i915/gem: Allow combining submit-fences with syncobj
We allow exported sync_file fences to be used as submit fences, but they
are not the only source of user fences. We also accept an array of
syncobj, and as with sync_file these are dma_fences underneath and so
feature the same set of controls. The submit-fence allows for a request
to be scheduled at the same time as the signaler, rather than as normal
after. Userspace can combine submit-fence with its own semaphores for
intra-batch scheduling.
Not exposing submit-fences to syncobj was at the time just a matter of
pragmatic expediency.
Fixes: a88b6e4cbafd ("drm/i915: Allow specification of parallel execbuf")
Link: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4854
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Lionel Landwerlin
Reviewed-by: Tvrtko Ursulin
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 14 ++
drivers/gpu/drm/i915/i915_request.c | 26 ++-
include/uapi/drm/i915_drm.h | 7 ++---
3 files changed, 38 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 71e4dbf7b9a8..a47aa33e722e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -2380,7 +2380,7 @@ static void
__free_fence_array(struct drm_syncobj **fences, unsigned int n)
{
while (n--)
- drm_syncobj_put(ptr_mask_bits(fences[n], 2));
+ drm_syncobj_put(ptr_mask_bits(fences[n], 3));
kvfree(fences);
}
@@ -2437,7 +2437,7 @@ get_fence_array(struct drm_i915_gem_execbuffer2 *args,
BUILD_BUG_ON(~(ARCH_KMALLOC_MINALIGN - 1) &
~__I915_EXEC_FENCE_UNKNOWN_FLAGS);
- fences[n] = ptr_pack_bits(syncobj, fence.flags, 2);
+ fences[n] = ptr_pack_bits(syncobj, fence.flags, 3);
}
return fences;
@@ -2468,7 +2468,7 @@ await_fence_array(struct i915_execbuffer *eb,
struct dma_fence *fence;
unsigned int flags;
- syncobj = ptr_unpack_bits(fences[n], &flags, 2);
+ syncobj = ptr_unpack_bits(fences[n], &flags, 3);
if (!(flags & I915_EXEC_FENCE_WAIT))
continue;
@@ -2492,7 +2492,11 @@ await_fence_array(struct i915_execbuffer *eb,
spin_unlock(&syncobj->lock);
}
- err = i915_request_await_dma_fence(eb->request, fence);
+ if (flags & I915_EXEC_FENCE_WAIT_SUBMIT)
+ err = i915_request_await_execution(eb->request, fence,
+
eb->engine->bond_execute);
+ else
+ err = i915_request_await_dma_fence(eb->request, fence);
dma_fence_put(fence);
if (err < 0)
return err;
@@ -2513,7 +2517,7 @@ signal_fence_array(struct i915_execbuffer *eb,
struct drm_syncobj *syncobj;
unsigned int flags;
- syncobj = ptr_unpack_bits(fences[n], &flags, 2);
+ syncobj = ptr_unpack_bits(fences[n], &flags, 3);
if (!(flags & I915_EXEC_FENCE_SIGNAL))
continue;
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 8583fe5bb3b6..92fa5267bcce 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -1326,6 +1326,26 @@ __i915_request_await_execution(struct i915_request *to,
&from->fence);
}
+static int execution_proxy(struct await_proxy *ap)
+{
+ return i915_request_await_execution(ap->request, ap->fence, ap->data);
+}
+
+static int
+i915_request_await_proxy_execution(struct i915_request *rq,
+ struct dma_fence *fence,
+ void (*hook)(struct i915_request *rq,
+ struct dma_fence *signal))
+{
+ /*
+* We have to wait until the real request is known in order to
+* be able to hook into its execution, as opposed to waiting for
+* its completion.
+*/
+ return __i915_request_await_proxy(rq, fence, I915_FENCE_TIMEOUT,
+ execution_proxy, hook);
+}
+
int
i915_request_await_execution(struct i915_request *rq,
struct dma_fence *fence,
@@ -1362,10 +1382,14 @@ i915_request_await_execution(struct i915_request *rq,
ret = __i915_request_await_execution(rq,
to_request(fence),
hook);
+ else if (dma_fence_is_proxy(fence))
+ ret = i915_request_await_proxy_execution(rq,
+
[Intel-gfx] [PATCH 6/6] drm/i915/gt: Declare when we enabled timeslicing
Let userspace know if they can trust timeslicing by including it as part
of the I915_PARAM_HAS_SCHEDULER::I915_SCHEDULER_CAP_TIMESLICING
v2: Only declare timeslicing if we can safely preempt userspace.
Fixes: 8ee36e048c98 ("drm/i915/execlists: Minimalistic timeslicing")
Link: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3802
Link: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4854
Signed-off-by: Chris Wilson
Cc: Kenneth Graunke
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine_user.c | 1 +
include/uapi/drm/i915_drm.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c
b/drivers/gpu/drm/i915/gt/intel_engine_user.c
index 848decee9066..8415511f1465 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
@@ -98,6 +98,7 @@ static void set_scheduler_caps(struct drm_i915_private *i915)
MAP(HAS_PREEMPTION, PREEMPTION),
MAP(HAS_SEMAPHORES, SEMAPHORES),
MAP(SUPPORTS_STATS, ENGINE_BUSY_STATS),
+ MAP(HAS_TIMESLICES, TIMESLICING),
#undef MAP
};
struct intel_engine_cs *engine;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 704dd0e3bc1d..1ee227b5131a 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -523,6 +523,7 @@ typedef struct drm_i915_irq_wait {
#define I915_SCHEDULER_CAP_PREEMPTION(1ul << 2)
#define I915_SCHEDULER_CAP_SEMAPHORES(1ul << 3)
#define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4)
+#define I915_SCHEDULER_CAP_TIMESLICING (1ul << 5)
#define I915_PARAM_HUC_STATUS 42
--
2.20.1
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[Intel-gfx] [PATCH 3/6] drm/syncobj: Allow use of dma-fence-proxy
Allow the callers to supply a dma-fence-proxy for asynchronous waiting on
future fences.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/drm_syncobj.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c
index 42d46414f767..e141db0e1eb6 100644
--- a/drivers/gpu/drm/drm_syncobj.c
+++ b/drivers/gpu/drm/drm_syncobj.c
@@ -184,6 +184,7 @@
*/
#include
+#include
#include
#include
#include
@@ -324,14 +325,9 @@ void drm_syncobj_replace_fence(struct drm_syncobj *syncobj,
struct dma_fence *old_fence;
struct syncobj_wait_entry *cur, *tmp;
- if (fence)
- dma_fence_get(fence);
-
spin_lock(&syncobj->lock);
- old_fence = rcu_dereference_protected(syncobj->fence,
- lockdep_is_held(&syncobj->lock));
- rcu_assign_pointer(syncobj->fence, fence);
+ old_fence = dma_fence_replace_proxy(&syncobj->fence, fence);
if (fence != old_fence) {
list_for_each_entry_safe(cur, tmp, &syncobj->cb_list, node)
--
2.20.1
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[Intel-gfx] [PATCH 1/6] drm/i915: Mark concurrent submissions with a weak-dependency
We recorded the dependencies for WAIT_FOR_SUBMIT in order that we could
correctly perform priority inheritance from the parallel branches to the
common trunk. However, for the purpose of timeslicing and reset
handling, the dependency is weak -- as we the pair of requests are
allowed to run in parallel and not in strict succession. So for example
we do need to suspend one if the other hangs.
The real significance though is that this allows us to rearrange
groups of WAIT_FOR_SUBMIT linked requests along the single engine, and
so can resolve user level inter-batch scheduling dependencies from user
semaphores.
Fixes: c81471f5e95c ("drm/i915: Copy across scheduler behaviour flags across
submit fences")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: # v5.6+
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 9 +
drivers/gpu/drm/i915/i915_request.c | 8 ++--
drivers/gpu/drm/i915/i915_scheduler.c | 4 +++-
drivers/gpu/drm/i915/i915_scheduler.h | 3 ++-
drivers/gpu/drm/i915/i915_scheduler_types.h | 1 +
5 files changed, 21 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index d4ef344657b0..a47e4e15cbaa 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1883,6 +1883,9 @@ static void defer_request(struct i915_request *rq, struct
list_head * const pl)
struct i915_request *w =
container_of(p->waiter, typeof(*w), sched);
+ if (p->flags & I915_DEPENDENCY_WEAK)
+ continue;
+
/* Leave semaphores spinning on the other engines */
if (w->engine != rq->engine)
continue;
@@ -2729,6 +2732,9 @@ static void __execlists_hold(struct i915_request *rq)
struct i915_request *w =
container_of(p->waiter, typeof(*w), sched);
+ if (p->flags & I915_DEPENDENCY_WEAK)
+ continue;
+
/* Leave semaphores spinning on the other engines */
if (w->engine != rq->engine)
continue;
@@ -2853,6 +2859,9 @@ static void __execlists_unhold(struct i915_request *rq)
struct i915_request *w =
container_of(p->waiter, typeof(*w), sched);
+ if (p->flags & I915_DEPENDENCY_WEAK)
+ continue;
+
/* Propagate any change in error status */
if (rq->fence.error)
i915_request_set_error_once(w, rq->fence.error);
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 22635bbabf06..95edc5523a01 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -1038,7 +1038,9 @@ i915_request_await_request(struct i915_request *to,
struct i915_request *from)
return 0;
if (to->engine->schedule) {
- ret = i915_sched_node_add_dependency(&to->sched, &from->sched);
+ ret = i915_sched_node_add_dependency(&to->sched,
+&from->sched,
+0);
if (ret < 0)
return ret;
}
@@ -1200,7 +1202,9 @@ __i915_request_await_execution(struct i915_request *to,
/* Couple the dependency tree for PI on this exposed to->fence */
if (to->engine->schedule) {
- err = i915_sched_node_add_dependency(&to->sched, &from->sched);
+ err = i915_sched_node_add_dependency(&to->sched,
+&from->sched,
+I915_DEPENDENCY_WEAK);
if (err < 0)
return err;
}
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index 37cfcf5b321b..5f4c1e49e974 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -462,7 +462,8 @@ bool __i915_sched_node_add_dependency(struct
i915_sched_node *node,
}
int i915_sched_node_add_dependency(struct i915_sched_node *node,
- struct i915_sched_node *signal)
+ struct i915_sched_node *signal,
+ unsigned long flags)
{
struct i915_dependency *dep;
@@ -473,6 +474,7 @@ int i915_sched_node_add_dependency(struct i915_sched_node
*node,
local_bh_disable();
if (!__i915_sched_node_add_dependency(node, signal, dep,
+ flags |
I915_DEPENDENCY_EXTERNAL |
[Intel-gfx] Wait-for-submit on future syncobj
This series extends the I915_EXEC_FENCE_SUBMIT to syncobj; with the
primary motivation for this to allow userspace to schedule between
individual clients coordinating with semaphores. The advantage syncobj
have over sync-file is that since the syncobj is known a priori, it can
be used to pass the location of a not-yet-submitted fence. This is used
by iris in its deferred flush implementations where a fence is acquired
for an incomplete batch, and that future-fence may be used to
serlisation execution in another context. Since we already handle
'bonded execution' for media submission, we need only extend support to
syncobjs.
A simplified example of out-of-order execution that is required by iris:
struct drm_i915_gem_exec_object2 obj = {
.offset = 24 << 20,
.handle = future_submit_batch(i915, 24 << 20),
.flags = EXEC_OBJECT_PINNED,
};
struct drm_i915_gem_exec_fence fence = {
.handle = syncobj_create(i915, 0),
};
struct drm_i915_gem_execbuffer2 execbuf = {
.buffers_ptr = to_user_pointer(&obj),
.buffer_count = 1,
.cliprects_ptr = to_user_pointer(&fence),
.num_cliprects = 1,
.flags = engine | I915_EXEC_FENCE_ARRAY,
};
uint32_t result;
int out;
/*
* Here we submit client A waiting on client B, but internally client
* B has a semaphore that waits on client A. This relies on timeslicing
* to reorder B before A, even though userspace has asked to submit
* A & B simultaneously (and due to the sequence we will submit B
* then A).
*/
igt_require(gem_scheduler_has_timeslicing(i915));
execbuf.rsvd1 = gem_context_create(i915);
fence.flags = I915_EXEC_FENCE_WAIT | I915_EXEC_FENCE_WAIT_SUBMIT;
execbuf.batch_start_offset = 0;
execbuf.flags |= I915_EXEC_FENCE_OUT;
igt_require(__gem_execbuf_wr(i915, &execbuf) == 0); /* writes 1 */
execbuf.flags &= ~I915_EXEC_FENCE_OUT;
gem_context_destroy(i915, execbuf.rsvd1);
execbuf.rsvd1 = gem_context_create(i915);
fence.flags = I915_EXEC_FENCE_SIGNAL;
execbuf.batch_start_offset = 64;
gem_execbuf(i915, &execbuf); /* writes 2 */
gem_context_destroy(i915, execbuf.rsvd1);
gem_sync(i915, obj.handle); /* write hazard lies */
gem_read(i915, obj.handle, 4000, &result, sizeof(result));
igt_assert_eq(result, 2);
/* check we didn't autotimeout */
out = execbuf.rsvd2 >> 32;
igt_assert_eq(sync_fence_status(out), 1);
close(out);
gem_close(i915, obj.handle);
syncobj_destroy(i915, fence.handle);
Link: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3802
Link: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4854
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Re: [Intel-gfx] [PATCH] drm/i915/display: Warn if the FBC is still writing to stolen on removal
On Sun, May 03, 2020 at 07:00:34PM +0100, Chris Wilson wrote:
> If the FBC is still writing into stolen, it will overwrite any future
> users of that stolen region. Check before release.
>
> References: https://gitlab.freedesktop.org/drm/intel/-/issues/1635
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index c6afa10e814c..37244ed92ae4 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -540,6 +540,9 @@ static void __intel_fbc_cleanup_cfb(struct
> drm_i915_private *dev_priv)
> {
> struct intel_fbc *fbc = &dev_priv->fbc;
>
> + if (WARN_ON(intel_fbc_hw_is_active(dev_priv)))
> + return;
> +
Can't immediately see how that would hapoen, but no harm in checking.
Reviewed-by: Ville Syrjälä
> if (!drm_mm_node_allocated(&fbc->compressed_fb))
> return;
>
> --
> 2.20.1
>
> ___
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--
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [01/22] drm/i915: Allow some leniency in PCU reads
== Series Details == Series: series starting with [01/22] drm/i915: Allow some leniency in PCU reads URL : https://patchwork.freedesktop.org/series/76885/ State : success == Summary == CI Bug Log - changes from CI_DRM_8415_full -> Patchwork_17561_full Summary --- **SUCCESS** No regressions found. New tests - New tests have been introduced between CI_DRM_8415_full and Patchwork_17561_full: ### New IGT tests (2) ### * igt@dmabuf@all@dma_fence_proxy: - Statuses : 8 pass(s) - Exec time: [0.03, 0.11] s * igt@i915_selftest@live@gem_execbuf: - Statuses : 8 pass(s) - Exec time: [0.44, 2.51] s Known issues Here are the changes found in Patchwork_17561_full that come from known issues: ### IGT changes ### Issues hit * igt@i915_suspend@forcewake: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +3 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8415/shard-kbl6/igt@i915_susp...@forcewake.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17561/shard-kbl6/igt@i915_susp...@forcewake.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8415/shard-apl8/igt@kms_cursor_...@pipe-c-cursor-suspend.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17561/shard-apl1/igt@kms_cursor_...@pipe-c-cursor-suspend.html * igt@kms_cursor_edge_walk@pipe-a-256x256-bottom-edge: - shard-apl: [PASS][5] -> [FAIL][6] ([i915#70] / [i915#95]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8415/shard-apl3/igt@kms_cursor_edge_w...@pipe-a-256x256-bottom-edge.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17561/shard-apl4/igt@kms_cursor_edge_w...@pipe-a-256x256-bottom-edge.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: - shard-glk: [PASS][7] -> [FAIL][8] ([i915#72]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8415/shard-glk8/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17561/shard-glk6/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html * igt@kms_cursor_legacy@pipe-b-forked-bo: - shard-hsw: [PASS][9] -> [INCOMPLETE][10] ([i915#61]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8415/shard-hsw6/igt@kms_cursor_leg...@pipe-b-forked-bo.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17561/shard-hsw7/igt@kms_cursor_leg...@pipe-b-forked-bo.html * igt@kms_dp_dsc@basic-dsc-enable-edp: - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109349]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8415/shard-iclb2/igt@kms_dp_...@basic-dsc-enable-edp.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17561/shard-iclb5/igt@kms_dp_...@basic-dsc-enable-edp.html * igt@kms_draw_crc@draw-method-rgb565-pwrite-untiled: - shard-glk: [PASS][13] -> [FAIL][14] ([i915#177] / [i915#52] / [i915#54]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8415/shard-glk6/igt@kms_draw_...@draw-method-rgb565-pwrite-untiled.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17561/shard-glk8/igt@kms_draw_...@draw-method-rgb565-pwrite-untiled.html * igt@kms_flip_tiling@flip-changes-tiling-y: - shard-apl: [PASS][15] -> [FAIL][16] ([i915#95]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8415/shard-apl7/igt@kms_flip_til...@flip-changes-tiling-y.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17561/shard-apl8/igt@kms_flip_til...@flip-changes-tiling-y.html - shard-kbl: [PASS][17] -> [FAIL][18] ([i915#699] / [i915#93] / [i915#95]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8415/shard-kbl2/igt@kms_flip_til...@flip-changes-tiling-y.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17561/shard-kbl3/igt@kms_flip_til...@flip-changes-tiling-y.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#49]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8415/shard-skl1/igt@kms_frontbuffer_track...@psr-1p-primscrn-pri-indfb-draw-render.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17561/shard-skl9/igt@kms_frontbuffer_track...@psr-1p-primscrn-pri-indfb-draw-render.html * igt@kms_hdr@bpc-switch-dpms: - shard-skl: [PASS][21] -> [FAIL][22] ([i915#1188]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8415/shard-skl5/igt@kms_...@bpc-switch-dpms.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17561/shard-skl3/igt@kms_...@bpc-switch-dpms.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-skl: [PASS][23]
