Re: [Intel-gfx] [PATCH 15/27] drm/i915/pxp: Destroy all type0 sessions upon teardown
Hi Sean,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on next-20201113]
[also build test WARNING on v5.10-rc3]
[cannot apply to drm-intel/for-linux-next char-misc/char-misc-testing v5.10-rc3
v5.10-rc2 v5.10-rc1]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Sean-Z-Huang/drm-i915-pxp-Introduce-Intel-PXP-component/20201114-094926
base:92edc4aef86780a8ad01b092c6d6630bb3cb423d
config: x86_64-randconfig-a004-20201113 (attached as .config)
compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project
9a85643cd357e412cff69067bb5c4840e228c2ab)
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
# install x86_64 cross compiling tool for clang build
# apt-get install binutils-x86-64-linux-gnu
#
https://github.com/0day-ci/linux/commit/b2c5c38f134701a462cb7e880c4cebcd79e1d8c6
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review
Sean-Z-Huang/drm-i915-pxp-Introduce-Intel-PXP-component/20201114-094926
git checkout b2c5c38f134701a462cb7e880c4cebcd79e1d8c6
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All warnings (new ones prefixed by >>):
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c:175:5: warning: no previous
prototype for function 'pxp_sm_reg_read' [-Wmissing-prototypes]
int pxp_sm_reg_read(struct drm_i915_private *i915, u32 offset, u32 *regval)
^
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c:175:1: note: declare 'static' if the
function is not intended to be used outside of this translation unit
int pxp_sm_reg_read(struct drm_i915_private *i915, u32 offset, u32 *regval)
^
static
>> drivers/gpu/drm/i915/pxp/intel_pxp_sm.c:1146:5: warning: no previous
>> prototype for function 'intel_pxp_sm_destroy_all_sw_sessions'
>> [-Wmissing-prototypes]
int intel_pxp_sm_destroy_all_sw_sessions(struct drm_i915_private *i915, int
session_type)
^
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c:1146:1: note: declare 'static' if
the function is not intended to be used outside of this translation unit
int intel_pxp_sm_destroy_all_sw_sessions(struct drm_i915_private *i915, int
session_type)
^
static
2 warnings generated.
vim +/intel_pxp_sm_destroy_all_sw_sessions +1146
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
1145
> 1146 int intel_pxp_sm_destroy_all_sw_sessions(struct drm_i915_private *i915,
> int session_type)
1147 {
1148 int ret = 0;
1149 struct pxp_protected_session *current_session, *n;
1150
1151 list_for_each_entry_safe(current_session, n,
pxp_session_list(i915, session_type), session_list) {
1152 ret = pxp_set_pxp_tag(i915, session_type,
current_session->session_index, PROTECTION_MODE_NONE);
1153 if (ret)
1154 drm_dbg(&i915->drm, "Failed to
pxp_set_pxp_tag()\n");
1155
1156 list_del(¤t_session->session_list);
1157 kfree(current_session);
1158 }
1159
1160 return ret;
1161 }
1162
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
.config.gz
Description: application/gzip
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 15/27] drm/i915/pxp: Destroy all type0 sessions upon teardown
Hi Sean, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on next-20201113] [also build test WARNING on v5.10-rc3] [cannot apply to drm-intel/for-linux-next char-misc/char-misc-testing v5.10-rc3 v5.10-rc2 v5.10-rc1] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Sean-Z-Huang/drm-i915-pxp-Introduce-Intel-PXP-component/20201114-094926 base:92edc4aef86780a8ad01b092c6d6630bb3cb423d config: i386-randconfig-s001-20201114 (attached as .config) compiler: gcc-9 (Debian 9.3.0-15) 9.3.0 reproduce: # apt-get install sparse # sparse version: v0.6.3-107-gaf3512a6-dirty # https://github.com/0day-ci/linux/commit/b2c5c38f134701a462cb7e880c4cebcd79e1d8c6 git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Sean-Z-Huang/drm-i915-pxp-Introduce-Intel-PXP-component/20201114-094926 git checkout b2c5c38f134701a462cb7e880c4cebcd79e1d8c6 # save the attached .config to linux build tree make W=1 C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' ARCH=i386 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot "sparse warnings: (new ones prefixed by >>)" drivers/gpu/drm/i915/pxp/intel_pxp_sm.c:175:5: sparse: sparse: symbol 'pxp_sm_reg_read' was not declared. Should it be static? >> drivers/gpu/drm/i915/pxp/intel_pxp_sm.c:1146:5: sparse: sparse: symbol >> 'intel_pxp_sm_destroy_all_sw_sessions' was not declared. Should it be static? Please review and possibly fold the followup patch. --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org .config.gz Description: application/gzip ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC PATCH] drm/i915/pxp: intel_pxp_sm_destroy_all_sw_sessions() can be static
Reported-by: kernel test robot
Signed-off-by: kernel test robot
---
intel_pxp_sm.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index 37fe2e5af88dcb..79dd930f1c0d8b 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -1143,7 +1143,7 @@ int pxp_sm_terminate_protected_session_unsafe(struct
drm_i915_private *i915, int
return ret;
}
-int intel_pxp_sm_destroy_all_sw_sessions(struct drm_i915_private *i915, int
session_type)
+static int intel_pxp_sm_destroy_all_sw_sessions(struct drm_i915_private *i915,
int session_type)
{
int ret = 0;
struct pxp_protected_session *current_session, *n;
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 08/27] drm/i915/pxp: Read register to check hardware session state
Hi Sean,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on next-20201113]
[also build test WARNING on v5.10-rc3]
[cannot apply to drm-intel/for-linux-next char-misc/char-misc-testing v5.10-rc3
v5.10-rc2 v5.10-rc1]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Sean-Z-Huang/drm-i915-pxp-Introduce-Intel-PXP-component/20201114-094926
base:92edc4aef86780a8ad01b092c6d6630bb3cb423d
config: x86_64-randconfig-a004-20201113 (attached as .config)
compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project
9a85643cd357e412cff69067bb5c4840e228c2ab)
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
# install x86_64 cross compiling tool for clang build
# apt-get install binutils-x86-64-linux-gnu
#
https://github.com/0day-ci/linux/commit/c0c82470e52f95847f54cd65e470ba01a13d71ab
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review
Sean-Z-Huang/drm-i915-pxp-Introduce-Intel-PXP-component/20201114-094926
git checkout c0c82470e52f95847f54cd65e470ba01a13d71ab
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/i915/pxp/intel_pxp_sm.c:13:5: warning: no previous prototype
>> for function 'pxp_sm_reg_read' [-Wmissing-prototypes]
int pxp_sm_reg_read(struct drm_i915_private *i915, u32 offset, u32 *regval)
^
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c:13:1: note: declare 'static' if the
function is not intended to be used outside of this translation unit
int pxp_sm_reg_read(struct drm_i915_private *i915, u32 offset, u32 *regval)
^
static
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c:162:12: warning: unused function
'sync_hw_sw_state' [-Wunused-function]
static int sync_hw_sw_state(struct drm_i915_private *i915, int
session_index, int session_type)
^
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c:195:13: warning: unused function
'check_if_protected_type0_sessions_are_attacked' [-Wunused-function]
static bool check_if_protected_type0_sessions_are_attacked(struct
drm_i915_private *i915)
^
3 warnings generated.
vim +/pxp_sm_reg_read +13 drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
12
> 13 int pxp_sm_reg_read(struct drm_i915_private *i915, u32 offset, u32
*regval)
14 {
15 intel_wakeref_t wakeref;
16 int err = 0;
17
18 if (!i915 || !regval) {
19 err = -EINVAL;
20 drm_dbg(&i915->drm, "Failed to %s bad params\n",
__func__);
21 goto end;
22 }
23
24 with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
25 i915_reg_t reg_offset = {offset};
26 *regval = intel_uncore_read(&i915->uncore, reg_offset);
27 }
28 end:
29 return err;
30 }
31
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
.config.gz
Description: application/gzip
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC PATCH] drm/i915/pxp: pxp_sm_reg_read() can be static
Reported-by: kernel test robot
Signed-off-by: kernel test robot
---
intel_pxp_sm.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index 3dd5a9e3926ba4..7f5c47ee452d61 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -10,7 +10,7 @@
#include "intel_pxp_sm.h"
#include "intel_pxp_context.h"
-int pxp_sm_reg_read(struct drm_i915_private *i915, u32 offset, u32 *regval)
+static int pxp_sm_reg_read(struct drm_i915_private *i915, u32 offset, u32
*regval)
{
intel_wakeref_t wakeref;
int err = 0;
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 08/27] drm/i915/pxp: Read register to check hardware session state
Hi Sean, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on next-20201113] [also build test WARNING on v5.10-rc3] [cannot apply to drm-intel/for-linux-next char-misc/char-misc-testing v5.10-rc3 v5.10-rc2 v5.10-rc1] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Sean-Z-Huang/drm-i915-pxp-Introduce-Intel-PXP-component/20201114-094926 base:92edc4aef86780a8ad01b092c6d6630bb3cb423d config: i386-randconfig-s001-20201114 (attached as .config) compiler: gcc-9 (Debian 9.3.0-15) 9.3.0 reproduce: # apt-get install sparse # sparse version: v0.6.3-107-gaf3512a6-dirty # https://github.com/0day-ci/linux/commit/c0c82470e52f95847f54cd65e470ba01a13d71ab git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Sean-Z-Huang/drm-i915-pxp-Introduce-Intel-PXP-component/20201114-094926 git checkout c0c82470e52f95847f54cd65e470ba01a13d71ab # save the attached .config to linux build tree make W=1 C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' ARCH=i386 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot "sparse warnings: (new ones prefixed by >>)" >> drivers/gpu/drm/i915/pxp/intel_pxp_sm.c:13:5: sparse: sparse: symbol >> 'pxp_sm_reg_read' was not declared. Should it be static? Please review and possibly fold the followup patch. --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org .config.gz Description: application/gzip ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 05/27] drm/i915/pxp: Enable ioctl action to set the ring3 context
Hi Sean,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on next-20201113]
[also build test WARNING on v5.10-rc3]
[cannot apply to drm-intel/for-linux-next char-misc/char-misc-testing v5.10-rc3
v5.10-rc2 v5.10-rc1]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Sean-Z-Huang/drm-i915-pxp-Introduce-Intel-PXP-component/20201114-094926
base:92edc4aef86780a8ad01b092c6d6630bb3cb423d
config: i386-randconfig-a012-20201113 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
reproduce (this is a W=1 build):
#
https://github.com/0day-ci/linux/commit/1d109ada10e82c324682792cb0a20deef302336e
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review
Sean-Z-Huang/drm-i915-pxp-Introduce-Intel-PXP-component/20201114-094926
git checkout 1d109ada10e82c324682792cb0a20deef302336e
# save the attached .config to linux build tree
make W=1 ARCH=i386
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All warnings (new ones prefixed by >>):
drivers/gpu/drm/i915/pxp/intel_pxp.c: In function 'i915_pxp_ops_ioctl':
>> drivers/gpu/drm/i915/pxp/intel_pxp.c:26:32: warning: cast to pointer from
>> integer of different size [-Wint-to-pointer-cast]
26 | if (copy_from_user(&pxp_info, (void __user *)pxp_ops->pxp_info_ptr,
sizeof(pxp_info)) != 0) {
|^
drivers/gpu/drm/i915/pxp/intel_pxp.c:65:20: warning: cast to pointer from
integer of different size [-Wint-to-pointer-cast]
65 | if (copy_to_user((void __user *)pxp_ops->pxp_info_ptr, &pxp_info,
sizeof(pxp_info)) != 0)
|^
vim +26 drivers/gpu/drm/i915/pxp/intel_pxp.c
10
11 int i915_pxp_ops_ioctl(struct drm_device *dev, void *data, struct
drm_file *drmfile)
12 {
13 int ret;
14 struct pxp_info pxp_info = {0};
15 struct drm_i915_pxp_ops *pxp_ops = data;
16 struct drm_i915_private *i915 = to_i915(dev);
17
18 drm_dbg(&i915->drm, ">>> %s\n", __func__);
19
20 if (!i915 || !drmfile || !pxp_ops || pxp_ops->pxp_info_size !=
sizeof(pxp_info)) {
21 drm_dbg(&i915->drm, "Failed to %s, invalid params\n",
__func__);
22 ret = -EINVAL;
23 goto end;
24 }
25
> 26 if (copy_from_user(&pxp_info, (void __user
*)pxp_ops->pxp_info_ptr, sizeof(pxp_info)) != 0) {
27 ret = -EFAULT;
28 goto end;
29 }
30
31 drm_dbg(&i915->drm, "i915 pxp ioctl call with action=[%d]\n",
pxp_info.action);
32
33 mutex_lock(&i915->pxp.r0ctx->ctx_mutex);
34
35 if (i915->pxp.r0ctx->global_state_in_suspend) {
36 drm_dbg(&i915->drm, "Return failure due to state in
suspend\n");
37 pxp_info.sm_status =
PXP_SM_STATUS_SESSION_NOT_AVAILABLE;
38 ret = 0;
39 goto end;
40 }
41
42 if (i915->pxp.r0ctx->global_state_attacked) {
43 drm_dbg(&i915->drm, "Retry required due to state
attacked\n");
44 pxp_info.sm_status = PXP_SM_STATUS_RETRY_REQUIRED;
45 ret = 0;
46 goto end;
47 }
48
49 switch (pxp_info.action) {
50 case PXP_ACTION_SET_R3_CONTEXT:
51 {
52 ret = intel_pxp_set_r3ctx(i915, pxp_info.set_r3ctx);
53 break;
54 }
55 default:
56 drm_dbg(&i915->drm, "Failed to %s due to bad params\n",
__func__);
57 ret = -EINVAL;
58 goto end;
59 }
60
61 end:
62 mutex_unlock(&i915->pxp.r0ctx->ctx_mutex);
63
64 if (ret == 0)
65 if (copy_to_user((void __user *)pxp_ops->pxp_info_ptr,
&pxp_info, sizeof(pxp_info)) != 0)
66 ret = -EFAULT;
67
68 if (ret)
69 dev_err(&dev->pdev->dev, "pid=%d, ret = %d\n",
task_pid_nr(current), ret);
70
71 drm_dbg(&i915->drm, "<<< %s\n", __func__);
72 return ret;
73 }
74
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
.config.gz
Description: application/gzip
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Big bigjoiner series
== Series Details == Series: drm/i915: Big bigjoiner series URL : https://patchwork.freedesktop.org/series/83837/ State : success == Summary == CI Bug Log - changes from CI_DRM_9326_full -> Patchwork_18904_full Summary --- **WARNING** Minor unknown changes coming with Patchwork_18904_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18904_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_18904_full: ### IGT changes ### Warnings * igt@i915_pm_rc6_residency@rc6-fence: - shard-iclb: [WARN][1] ([i915#1515]) -> [WARN][2] +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-iclb4/igt@i915_pm_rc6_reside...@rc6-fence.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18904/shard-iclb1/igt@i915_pm_rc6_reside...@rc6-fence.html New tests - New tests have been introduced between CI_DRM_9326_full and Patchwork_18904_full: ### New CI tests (1) ### * boot: - Statuses : 175 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_18904_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_whisper@basic-contexts-forked-all: - shard-glk: [PASS][3] -> [DMESG-WARN][4] ([i915#118] / [i915#95]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-glk8/igt@gem_exec_whis...@basic-contexts-forked-all.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18904/shard-glk7/igt@gem_exec_whis...@basic-contexts-forked-all.html * igt@kms_cursor_crc@pipe-b-cursor-suspend: - shard-apl: [PASS][5] -> [FAIL][6] ([i915#1635] / [i915#54]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-apl6/igt@kms_cursor_...@pipe-b-cursor-suspend.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18904/shard-apl1/igt@kms_cursor_...@pipe-b-cursor-suspend.html * igt@kms_flip@2x-plain-flip-fb-recreate@ab-hdmi-a1-hdmi-a2: - shard-glk: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-glk5/igt@kms_flip@2x-plain-flip-fb-recre...@ab-hdmi-a1-hdmi-a2.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18904/shard-glk1/igt@kms_flip@2x-plain-flip-fb-recre...@ab-hdmi-a1-hdmi-a2.html * igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1: - shard-skl: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) +4 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-skl3/igt@kms_flip@flip-vs-blocking-wf-vbl...@a-edp1.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18904/shard-skl9/igt@kms_flip@flip-vs-blocking-wf-vbl...@a-edp1.html * igt@kms_flip@plain-flip-ts-check@a-dp1: - shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +4 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-kbl1/igt@kms_flip@plain-flip-ts-ch...@a-dp1.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18904/shard-kbl2/igt@kms_flip@plain-flip-ts-ch...@a-dp1.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt: - shard-tglb: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-tglb2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18904/shard-tglb1/igt@kms_frontbuffer_track...@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt.html * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-wc: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#49]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-skl10/igt@kms_frontbuffer_track...@psr-1p-offscren-pri-shrfb-draw-mmap-wc.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18904/shard-skl3/igt@kms_frontbuffer_track...@psr-1p-offscren-pri-shrfb-draw-mmap-wc.html * igt@kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#1188]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-skl3/igt@kms_...@bpc-switch-suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18904/shard-skl5/igt@kms_...@bpc-switch-suspend.html * igt@kms_psr@psr2_sprite_render: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-iclb2/igt@kms_psr@psr2_sprite_render.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18904/shard-iclb7/igt@kms_psr@ps
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Small tweak to put the termination conditions together
== Series Details ==
Series: drm/i915/selftests: Small tweak to put the termination conditions
together
URL : https://patchwork.freedesktop.org/series/83823/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9326_full -> Patchwork_18902_full
Summary
---
**WARNING**
Minor unknown changes coming with Patchwork_18902_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18902_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_18902_full:
### IGT changes ###
Warnings
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: [WARN][1] ([i915#1515]) -> [WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-iclb4/igt@i915_pm_rc6_reside...@rc6-fence.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18902/shard-iclb3/igt@i915_pm_rc6_reside...@rc6-fence.html
### Piglit changes ###
Possible regressions
* spec@glsl-1.30@execution@built-in-functions@fs-op-assign-bitxor-int-int
(NEW):
- {pig-icl-1065g7}: NOTRUN -> [CRASH][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18902/pig-icl-1065g7/spec@glsl-1.30@execution@built-in-functi...@fs-op-assign-bitxor-int-int.html
* spec@glsl-1.30@execution@built-in-functions@vs-op-bitxor-not-uint-uvec4
(NEW):
- {pig-icl-1065g7}: NOTRUN -> [INCOMPLETE][4] +5 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18902/pig-icl-1065g7/spec@glsl-1.30@execution@built-in-functi...@vs-op-bitxor-not-uint-uvec4.html
New tests
-
New tests have been introduced between CI_DRM_9326_full and
Patchwork_18902_full:
### New CI tests (1) ###
* boot:
- Statuses : 200 pass(s)
- Exec time: [0.0] s
### New Piglit tests (7) ###
* spec@glsl-1.30@execution@built-in-functions@fs-op-assign-bitxor-int-int:
- Statuses : 1 crash(s)
- Exec time: [0.59] s
* spec@glsl-1.30@execution@built-in-functions@fs-op-bitxor-neg-abs-int-ivec3:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
*
spec@glsl-1.30@execution@built-in-functions@fs-op-bitxor-neg-abs-ivec3-ivec3:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@glsl-1.30@execution@built-in-functions@fs-sinh-vec3:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@glsl-1.30@execution@built-in-functions@vs-op-bitor-abs-not-ivec2-int:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@glsl-1.30@execution@built-in-functions@vs-op-bitxor-ivec4-ivec4:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@glsl-1.30@execution@built-in-functions@vs-op-bitxor-not-uint-uvec4:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_18902_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_reloc@basic-many-active@rcs0:
- shard-glk: [PASS][5] -> [FAIL][6] ([i915#2389])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-glk7/igt@gem_exec_reloc@basic-many-act...@rcs0.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18902/shard-glk4/igt@gem_exec_reloc@basic-many-act...@rcs0.html
- shard-hsw: [PASS][7] -> [FAIL][8] ([i915#2389])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-hsw8/igt@gem_exec_reloc@basic-many-act...@rcs0.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18902/shard-hsw4/igt@gem_exec_reloc@basic-many-act...@rcs0.html
* igt@kms_cursor_crc@pipe-c-cursor-128x42-random:
- shard-skl: [PASS][9] -> [FAIL][10] ([i915#54]) +1 similar issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-skl2/igt@kms_cursor_...@pipe-c-cursor-128x42-random.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18902/shard-skl6/igt@kms_cursor_...@pipe-c-cursor-128x42-random.html
* igt@kms_draw_crc@draw-method-xrgb-blt-untiled:
- shard-hsw: [PASS][11] -> [FAIL][12] ([i915#54])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-hsw1/igt@kms_draw_...@draw-method-xrgb-blt-untiled.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18902/shard-hsw8/igt@kms_draw_...@draw-method-xrgb-blt-untiled.html
* igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ab-vga1-hdmi-a1:
- shard-hsw: [PASS][13] -> [DMESG-WARN][14] ([i915#1982])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-hsw5/igt@kms_flip@2x-plain-flip-fb-recreate-interrupti...@ab-vga1-hdmi-a1.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18902/shard-hsw6/igt@kms_flip@2x-p
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,v11,1/3] drm/i915: Pass intel_atomic_state instead of drm_atomic_state
== Series Details == Series: series starting with [CI,v11,1/3] drm/i915: Pass intel_atomic_state instead of drm_atomic_state URL : https://patchwork.freedesktop.org/series/83816/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9326_full -> Patchwork_18901_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_18901_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18901_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_18901_full: ### IGT changes ### Possible regressions * igt@core_hotunplug@hotrebind-lateclose: - shard-snb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-snb4/igt@core_hotunp...@hotrebind-lateclose.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18901/shard-snb2/igt@core_hotunp...@hotrebind-lateclose.html * igt@i915_selftest@live@hangcheck: - shard-tglb: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-tglb6/igt@i915_selftest@l...@hangcheck.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18901/shard-tglb5/igt@i915_selftest@l...@hangcheck.html Warnings * igt@i915_pm_rc6_residency@rc6-fence: - shard-iclb: [WARN][5] ([i915#1515]) -> [WARN][6] +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-iclb4/igt@i915_pm_rc6_reside...@rc6-fence.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18901/shard-iclb4/igt@i915_pm_rc6_reside...@rc6-fence.html New tests - New tests have been introduced between CI_DRM_9326_full and Patchwork_18901_full: ### New CI tests (1) ### * boot: - Statuses : 200 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_18901_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_reloc@basic-many-active@rcs0: - shard-glk: [PASS][7] -> [FAIL][8] ([i915#2389]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-glk7/igt@gem_exec_reloc@basic-many-act...@rcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18901/shard-glk4/igt@gem_exec_reloc@basic-many-act...@rcs0.html - shard-hsw: [PASS][9] -> [FAIL][10] ([i915#2389]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-hsw8/igt@gem_exec_reloc@basic-many-act...@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18901/shard-hsw4/igt@gem_exec_reloc@basic-many-act...@rcs0.html * igt@i915_module_load@reload-with-fault-injection: - shard-skl: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +7 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-skl6/igt@i915_module_l...@reload-with-fault-injection.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18901/shard-skl7/igt@i915_module_l...@reload-with-fault-injection.html * igt@i915_pm_rpm@system-suspend: - shard-skl: [PASS][13] -> [INCOMPLETE][14] ([i915#146] / [i915#151]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-skl3/igt@i915_pm_...@system-suspend.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18901/shard-skl1/igt@i915_pm_...@system-suspend.html * igt@kms_cursor_crc@pipe-c-cursor-128x42-random: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#54]) +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-skl2/igt@kms_cursor_...@pipe-c-cursor-128x42-random.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18901/shard-skl9/igt@kms_cursor_...@pipe-c-cursor-128x42-random.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt: - shard-tglb: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-tglb2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18901/shard-tglb7/igt@kms_frontbuffer_track...@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt.html * igt@kms_frontbuffer_tracking@fbc-badstride: - shard-iclb: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-iclb2/igt@kms_frontbuffer_track...@fbc-badstride.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18901/shard-iclb8/igt@kms_frontbuffer_track...@fbc-badstride.html - shard-kbl: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) +
Re: [Intel-gfx] [PXP CLEAN PATCH v06 08/27] drm/i915/pxp: Read register to check hardware session state
Hi Sean,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on next-20201113]
[also build test WARNING on v5.10-rc3]
[cannot apply to drm-intel/for-linux-next char-misc/char-misc-testing v5.10-rc3
v5.10-rc2 v5.10-rc1]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Sean-Z-Huang/drm-i915-pxp-Introduce-Intel-PXP-component/20201114-084506
base:92edc4aef86780a8ad01b092c6d6630bb3cb423d
config: x86_64-allyesconfig (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
reproduce (this is a W=1 build):
#
https://github.com/0day-ci/linux/commit/a8b258b463bb1fd193cf33be15a5909bc428d52b
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review
Sean-Z-Huang/drm-i915-pxp-Introduce-Intel-PXP-component/20201114-084506
git checkout a8b258b463bb1fd193cf33be15a5909bc428d52b
# save the attached .config to linux build tree
make W=1 ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/i915/pxp/intel_pxp_sm.c:13:5: warning: no previous prototype
>> for 'pxp_sm_reg_read' [-Wmissing-prototypes]
13 | int pxp_sm_reg_read(struct drm_i915_private *i915, u32 offset, u32
*regval)
| ^~~
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c:195:13: warning:
'check_if_protected_type0_sessions_are_attacked' defined but not used
[-Wunused-function]
195 | static bool check_if_protected_type0_sessions_are_attacked(struct
drm_i915_private *i915)
| ^~
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c:162:12: warning: 'sync_hw_sw_state'
defined but not used [-Wunused-function]
162 | static int sync_hw_sw_state(struct drm_i915_private *i915, int
session_index, int session_type)
|^~~~
vim +/pxp_sm_reg_read +13 drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
12
> 13 int pxp_sm_reg_read(struct drm_i915_private *i915, u32 offset, u32
*regval)
14 {
15 intel_wakeref_t wakeref;
16 int err = 0;
17
18 if (!i915 || !regval) {
19 err = -EINVAL;
20 drm_dbg(&i915->drm, "Failed to %s bad params\n",
__func__);
21 goto end;
22 }
23
24 with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
25 i915_reg_t reg_offset = {offset};
26 *regval = intel_uncore_read(&i915->uncore, reg_offset);
27 }
28 end:
29 return err;
30 }
31
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
.config.gz
Description: application/gzip
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Eliminate intel_atomic_crtc_state_for_each_plane_state() from skl+ wm code (rev2)
== Series Details ==
Series: drm/i915: Eliminate intel_atomic_crtc_state_for_each_plane_state() from
skl+ wm code (rev2)
URL : https://patchwork.freedesktop.org/series/83589/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9326_full -> Patchwork_18900_full
Summary
---
**WARNING**
Minor unknown changes coming with Patchwork_18900_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18900_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_18900_full:
### IGT changes ###
Warnings
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: [WARN][1] ([i915#1515]) -> [WARN][2] +1 similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-iclb4/igt@i915_pm_rc6_reside...@rc6-fence.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/shard-iclb6/igt@i915_pm_rc6_reside...@rc6-fence.html
### Piglit changes ###
Possible regressions
*
spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-bitand-abs-neg-ivec2-int
(NEW):
- {pig-icl-1065g7}: NOTRUN -> [INCOMPLETE][3] +7 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/pig-icl-1065g7/spec@arb_tessellation_shader@execution@built-in-functi...@tcs-op-bitand-abs-neg-ivec2-int.html
New tests
-
New tests have been introduced between CI_DRM_9326_full and
Patchwork_18900_full:
### New CI tests (1) ###
* boot:
- Statuses : 199 pass(s)
- Exec time: [0.0] s
### New Piglit tests (8) ###
*
spec@arb_tessellation_shader@execution@built-in-functions@tcs-clamp-uvec2-uint-uint:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
*
spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-assign-bitand-ivec2-int:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
*
spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-assign-bitxor-uvec2-uint:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
*
spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-bitand-abs-neg-ivec2-int:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
*
spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-div-int-int:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
*
spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-lshift-uint-uint:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
*
spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-selection-bool-ivec2-ivec2:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_tessellation_shader@execution@built-in-functions@tcs-trunc-float:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_18900_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_reloc@basic-many-active@rcs0:
- shard-glk: [PASS][4] -> [FAIL][5] ([i915#2389])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-glk7/igt@gem_exec_reloc@basic-many-act...@rcs0.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/shard-glk4/igt@gem_exec_reloc@basic-many-act...@rcs0.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-skl: [PASS][6] -> [INCOMPLETE][7] ([i915#198])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-skl7/igt@gem_workarou...@suspend-resume-fd.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/shard-skl9/igt@gem_workarou...@suspend-resume-fd.html
* igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding:
- shard-skl: [PASS][8] -> [FAIL][9] ([i915#54]) +2 similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-skl2/igt@kms_cursor_...@pipe-b-cursor-128x42-sliding.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/shard-skl10/igt@kms_cursor_...@pipe-b-cursor-128x42-sliding.html
* igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic:
- shard-kbl: [PASS][10] -> [DMESG-WARN][11] ([i915#1982]) +1
similar issue
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-kbl3/igt@kms_cursor_leg...@flip-vs-cursor-crc-atomic.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/shard-kbl3/igt@kms_cursor_leg...@flip-vs-cursor-crc-atomic.html
* igt@kms_draw_crc@draw-method-xrgb-mmap-cpu-untiled:
- shard-skl: [PASS][12] -> [FAIL][13] ([i915#177] / [i915#52] /
[i915#54])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-skl10/igt@kms_draw_...@draw-method-xrgb-mmap-cpu-untiled.html
[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [01/27] drm/i915/pxp: Introduce Intel PXP component
== Series Details == Series: series starting with [01/27] drm/i915/pxp: Introduce Intel PXP component URL : https://patchwork.freedesktop.org/series/83845/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_pm.h In file included from : ./drivers/gpu/drm/i915/pxp/intel_pxp_pm.h:9:42: error: ‘struct drm_i915_private’ declared inside parameter list will not be visible outside of this definition or declaration [-Werror] void intel_pxp_pm_prepare_suspend(struct drm_i915_private *i915); ^~~~ ./drivers/gpu/drm/i915/pxp/intel_pxp_pm.h:11:39: error: ‘struct drm_i915_private’ declared inside parameter list will not be visible outside of this definition or declaration [-Werror] void intel_pxp_pm_resume_early(struct drm_i915_private *i915); ^~~~ ./drivers/gpu/drm/i915/pxp/intel_pxp_pm.h:12:32: error: ‘struct drm_i915_private’ declared inside parameter list will not be visible outside of this definition or declaration [-Werror] int intel_pxp_pm_resume(struct drm_i915_private *i915); ^~~~ cc1: all warnings being treated as errors drivers/gpu/drm/i915/Makefile:312: recipe for target 'drivers/gpu/drm/i915/pxp/intel_pxp_pm.hdrtest' failed make[4]: *** [drivers/gpu/drm/i915/pxp/intel_pxp_pm.hdrtest] Error 1 scripts/Makefile.build:500: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:500: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:500: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1799: recipe for target 'drivers' failed make: *** [drivers] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 14/27] drm/i915/pxp: Enable ioctl action to query PXP tag
From: "Huang, Sean Z"
Enable the PXP ioctl action to allow ring3 PXP to query the PXP
tag, which is a 32-bit bitwise value indicating the current
session info, including protection type, session id, and whether
the session is enabled.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c| 7 +++
drivers/gpu/drm/i915/pxp/intel_pxp.h| 7 +++
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 28 +
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 3 +++
4 files changed, 45 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 72a2237b504b..2121db05fdb6 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -78,6 +78,13 @@ int i915_pxp_ops_ioctl(struct drm_device *dev, void *data,
struct drm_file *drmf
}
break;
}
+ case PXP_ACTION_QUERY_PXP_TAG:
+ {
+ struct pxp_sm_query_pxp_tag *params = &pxp_info.query_pxp_tag;
+
+ ret = pxp_sm_ioctl_query_pxp_tag(i915,
¶ms->session_is_alive, ¶ms->pxp_tag);
+ break;
+ }
case PXP_ACTION_SET_R3_CONTEXT:
{
ret = intel_pxp_set_r3ctx(i915, pxp_info.set_r3ctx);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index cbaf25690596..8851c28a0e57 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -31,6 +31,7 @@ enum pxp_sm_session_req {
};
enum pxp_ioctl_action {
+ PXP_ACTION_QUERY_PXP_TAG = 0,
PXP_ACTION_SET_SESSION_STATUS = 1,
PXP_ACTION_SET_R3_CONTEXT = 5,
};
@@ -42,6 +43,11 @@ enum pxp_sm_status {
PXP_SM_STATUS_ERROR_UNKNOWN
};
+struct pxp_sm_query_pxp_tag {
+ u32 session_is_alive;
+ u32 pxp_tag; /* in - Session ID, out pxp tag */
+};
+
struct pxp_sm_set_session_status_params {
/** @pxp_tag: in [optional], for Arbitrator session, out pxp tag */
u32 pxp_tag;
@@ -57,6 +63,7 @@ struct pxp_info {
u32 action;
u32 sm_status;
union {
+ struct pxp_sm_query_pxp_tag query_pxp_tag;
struct pxp_sm_set_session_status_params set_session_status;
u32 set_r3ctx;
};
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index b1adfa735d4f..994abf5a8d36 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -1076,6 +1076,34 @@ int pxp_sm_terminate_protected_session_unsafe(struct
drm_i915_private *i915, int
return ret;
}
+int pxp_sm_ioctl_query_pxp_tag(struct drm_i915_private *i915, u32
*session_is_alive, u32 *pxp_tag)
+{
+ int session_type = 0;
+ int session_index = 0;
+ int ret;
+
+ drm_dbg(&i915->drm, ">>> %s\n", __func__);
+
+ if (!session_is_alive || !pxp_tag) {
+ ret = -EINVAL;
+ drm_dbg(&i915->drm, "Failed to %s, bad param\n", __func__);
+ goto end;
+ }
+
+ ret = pxp_get_session_index(i915, *pxp_tag, &session_index,
&session_type);
+ if (ret) {
+ drm_dbg(&i915->drm, "Failed to __pxpsessionid_to_sessionid\n");
+ goto end;
+ }
+
+ *pxp_tag = intel_pxp_get_pxp_tag(i915, session_index, session_type,
session_is_alive);
+
+ ret = 0;
+end:
+ drm_dbg(&i915->drm, "<<< %s ret=[%d]\n", __func__, ret);
+ return ret;
+}
+
int pxp_sm_set_kcr_init_reg(struct drm_i915_private *i915)
{
int ret;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
index 26597b1d18e1..859f3c1f8c6e 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
@@ -108,7 +108,10 @@ int pxp_sm_terminate_protected_session_safe(struct
drm_i915_private *i915, int c
int session_type, int session_id);
int pxp_sm_terminate_protected_session_unsafe(struct drm_i915_private *i915,
int session_type,
int session_id);
+int pxp_sm_ioctl_query_pxp_tag(struct drm_i915_private *i915, u32
*session_is_alive, u32 *pxp_tag);
int pxp_sm_set_kcr_init_reg(struct drm_i915_private *i915);
+u32 intel_pxp_get_pxp_tag(struct drm_i915_private *i915, int session_idx,
+ int session_type, u32 *session_is_alive);
bool intel_pxp_sm_is_any_type0_session_in_play(struct drm_i915_private *i915,
int protection_mode);
#endif /* __INTEL_PXP_SM_H__ */
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 18/27] drm/i915/pxp: Implement funcs to create the TEE channel
From: "Huang, Sean Z"
Currently ring3 driver sends the TEE commands directly to TEE, but
later, as our design, we would like to make ring3 sending the TEE
commands via the ring0 PXP ioctl action instead of TEE ioctl, so
we can centralize those protection operations at ring0 PXP.
Co-developed-by: Vitaly Lubart
Co-developed-by: Tomas Winkler
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 6 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 4 +
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 140 +++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 14 +++
include/drm/i915_component.h | 1 +
include/drm/i915_pxp_tee_interface.h | 45
8 files changed, 212 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
create mode 100644 include/drm/i915_pxp_tee_interface.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 6858392c1ef2..1f3e0b89ae42 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -259,6 +259,7 @@ i915-y += \
pxp/intel_pxp.o \
pxp/intel_pxp_context.o \
pxp/intel_pxp_sm.o \
+ pxp/intel_pxp_tee.o \
pxp/intel_pxp_pm.o
# Post-mortem debug and GPU hang state capture
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 830708414f92..73c77a4e8216 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -324,6 +324,7 @@ static int i915_driver_early_probe(struct drm_i915_private
*dev_priv)
mutex_init(&dev_priv->wm.wm_mutex);
mutex_init(&dev_priv->pps_mutex);
mutex_init(&dev_priv->hdcp_comp_mutex);
+ mutex_init(&dev_priv->pxp_tee_comp_mutex);
i915_memcpy_init_early(dev_priv);
intel_runtime_pm_init_early(&dev_priv->runtime_pm);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f34ed07a68ee..9ba6eada4f84 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1219,6 +1219,12 @@ struct drm_i915_private {
struct intel_pxp pxp;
+ struct i915_pxp_comp_master *pxp_tee_master;
+ bool pxp_tee_comp_added;
+
+ /* Mutex to protect the above pxp_tee component related values. */
+ struct mutex pxp_tee_comp_mutex;
+
I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
/*
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 75858c0842ba..2cbdc6fa7cf6 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -227,6 +227,8 @@ int intel_pxp_init(struct drm_i915_private *i915)
return ret;
}
+ intel_pxp_tee_component_init(i915);
+
INIT_WORK(&i915->pxp.irq_work, intel_pxp_irq_work);
i915->pxp.handled_irr = (PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED |
@@ -238,6 +240,8 @@ int intel_pxp_init(struct drm_i915_private *i915)
void intel_pxp_uninit(struct drm_i915_private *i915)
{
+ intel_pxp_tee_component_fini(i915);
+
intel_pxp_destroy_r0ctx(i915);
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
new file mode 100644
index ..5bf79ca45cea
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -0,0 +1,140 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+
+#include
+#include "i915_drv.h"
+#include "drm/i915_component.h"
+#include "intel_pxp.h"
+#include "intel_pxp_context.h"
+#include "intel_pxp_tee.h"
+
+static int intel_pxp_tee_io_message(struct drm_i915_private *i915,
+ void *msg_in, u32 msg_in_size,
+ void *msg_out, u32 *msg_out_size_ptr,
+ u32 msg_out_buf_size)
+{
+ int ret;
+ struct i915_pxp_comp_master *pxp_tee_master = i915->pxp_tee_master;
+
+ if (!pxp_tee_master || !msg_in || !msg_out || !msg_out_size_ptr) {
+ ret = -EINVAL;
+ drm_dbg(&i915->drm, "Failed to %s, invalid params\n", __func__);
+ goto end;
+ }
+
+ lockdep_assert_held(&i915->pxp_tee_comp_mutex);
+
+ if (drm_debug_enabled(DRM_UT_DRIVER))
+ print_hex_dump(KERN_DEBUG, "TEE input message binaries:",
+ DUMP_PREFIX_OFFSET, 4, 4, msg_in, msg_in_size,
true);
+
+ ret = pxp_tee_master->ops->send(pxp_tee_master->tee_dev, msg_in,
msg_in_size);
+ if (ret) {
+ ret = -EFAULT;
+ drm_dbg(&i915->drm, "Failed to send TEE message\n");
+ goto end;
+ }
+
+ ret = pxp_tee_master->ops->receive(pxp_tee_master->tee_dev, msg_out,
msg_out_buf_size);
+ if (re
[Intel-gfx] [PATCH 03/27] drm/i915/pxp: Add PXP context for logical hardware states.
From: "Huang, Sean Z"
Add PXP context which represents combined view
of driver and logical HW states.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile| 3 +-
drivers/gpu/drm/i915/pxp/intel_pxp.c | 32 ++--
drivers/gpu/drm/i915/pxp/intel_pxp.h | 3 ++
drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 51
drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 44 +
5 files changed, 128 insertions(+), 5 deletions(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 8274fea96009..831e8ad57560 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -256,7 +256,8 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support
i915-y += \
- pxp/intel_pxp.o
+ pxp/intel_pxp.o \
+ pxp/intel_pxp_context.o \
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index d98bff4a0fde..6d358f241406 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -5,6 +5,7 @@
#include "i915_drv.h"
#include "intel_pxp.h"
+#include "intel_pxp_context.h"
static void intel_pxp_write_irq_mask_reg(struct drm_i915_private *i915, u32
mask)
{
@@ -32,14 +33,32 @@ static int intel_pxp_teardown_required_callback(struct
drm_i915_private *i915)
{
drm_dbg(&i915->drm, "%s was called\n", __func__);
+ mutex_lock(&i915->pxp.r0ctx->ctx_mutex);
+
+ i915->pxp.r0ctx->global_state_attacked = true;
+ i915->pxp.r0ctx->flag_display_hm_surface_keys = false;
+
+ mutex_unlock(&i915->pxp.r0ctx->ctx_mutex);
+
return 0;
}
static int intel_pxp_global_terminate_complete_callback(struct
drm_i915_private *i915)
{
+ int ret = 0;
+
drm_dbg(&i915->drm, ">>> %s\n", __func__);
- return 0;
+ mutex_lock(&i915->pxp.r0ctx->ctx_mutex);
+
+ if (i915->pxp.r0ctx->global_state_attacked)
+ i915->pxp.r0ctx->global_state_attacked = false;
+
+ mutex_unlock(&i915->pxp.r0ctx->ctx_mutex);
+
+ drm_dbg(&i915->drm, "<<< %s ret=[%d]\n", __func__, ret);
+
+ return ret;
}
static void intel_pxp_irq_work(struct work_struct *work)
@@ -68,21 +87,26 @@ static void intel_pxp_irq_work(struct work_struct *work)
int intel_pxp_init(struct drm_i915_private *i915)
{
- int ret;
-
drm_info(&i915->drm, "i915_pxp_init\n");
+ i915->pxp.r0ctx = intel_pxp_create_r0ctx(i915);
+ if (!i915->pxp.r0ctx) {
+ drm_dbg(&i915->drm, "Failed to create pxp ctx\n");
+ return -EFAULT;
+ }
+
INIT_WORK(&i915->pxp.irq_work, intel_pxp_irq_work);
i915->pxp.handled_irr = (PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED |
PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ |
PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE);
- return ret;
+ return 0;
}
void intel_pxp_uninit(struct drm_i915_private *i915)
{
+ intel_pxp_destroy_r0ctx(i915);
}
/**
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 620774fc32e2..4dec35bb834d 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -12,6 +12,9 @@
#define PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ BIT(2)
#define PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE BIT(3)
+#define MAX_TYPE0_SESSIONS 16
+#define MAX_TYPE1_SESSIONS 6
+
enum pxp_sm_session_req {
/* Request KMD to allocate session id and move it to IN INIT */
PXP_SM_REQ_SESSION_ID_INIT = 0x0,
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
new file mode 100644
index ..692370e758de
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#include "intel_pxp_context.h"
+
+/**
+ * intel_pxp_create_ctx - To create a new pxp context.
+ * @i915: i915 device handle.
+ *
+ * Return: pointer to new_ctx, NULL for failure
+ */
+struct pxp_context *intel_pxp_create_r0ctx(struct drm_i915_private *i915)
+{
+ struct pxp_context *new_ctx = NULL;
+
+ drm_dbg(&i915->drm, ">>> %s\n", __func__);
+
+ new_ctx = kzalloc(sizeof(*new_ctx), GFP_KERNEL);
+ if (!new_ctx) {
+ drm_dbg(&i915->drm, "unable to allocate new pxp context!\n");
+ return NULL;
+ }
+
+ get_random_bytes(&new_ctx->r0ctx_id, sizeof(new_ctx->r0ctx_id));
+
+ new_ctx->global_state_attacked = false;
+
+ mutex_init(&new_ctx->ctx_mutex);
+
+ INIT_LIST_
[Intel-gfx] [PATCH 10/27] drm/i915/pxp: Enable ioctl action to reserve session slot
From: "Huang, Sean Z"
With this ioctl action, ring3 driver can reserve a specific
session slot/id assigned by ring0 PXP, as the first step of PXP
session establishment flow. Ring3 PXP stores the session info in
the session list structure.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c| 20 +++
drivers/gpu/drm/i915/pxp/intel_pxp.h| 24 +++-
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 168
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 3 +
4 files changed, 213 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index a83fa7cd749f..0f684851ecb2 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -47,6 +47,26 @@ int i915_pxp_ops_ioctl(struct drm_device *dev, void *data,
struct drm_file *drmf
}
switch (pxp_info.action) {
+ case PXP_ACTION_SET_SESSION_STATUS:
+ {
+ struct pxp_sm_set_session_status_params *params =
&pxp_info.set_session_status;
+
+ if (params->req_session_state == PXP_SM_REQ_SESSION_ID_INIT) {
+ ret = intel_pxp_sm_reserve_session(i915, drmfile, 0,
+ params->session_type,
+ params->session_mode,
+ ¶ms->pxp_tag);
+ if (ret == PXP_SM_STATUS_RETRY_REQUIRED ||
+ ret == PXP_SM_STATUS_SESSION_NOT_AVAILABLE) {
+ pxp_info.sm_status = ret;
+ ret = 0;
+ }
+ } else {
+ ret = -EINVAL;
+ goto end;
+ }
+ break;
+ }
case PXP_ACTION_SET_R3_CONTEXT:
{
ret = intel_pxp_set_r3ctx(i915, pxp_info.set_r3ctx);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 95d3deba7ade..cbaf25690596 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -15,6 +15,9 @@
#define pxp_session_list(i915, session_type) (((session_type) ==
SESSION_TYPE_TYPE0) ? \
&(i915)->pxp.r0ctx->active_pxp_type0_sessions :
&(i915)->pxp.r0ctx->active_pxp_type1_sessions)
+#define pxp_session_max(session_type) (((session_type) == SESSION_TYPE_TYPE0)
? \
+ MAX_TYPE0_SESSIONS : MAX_TYPE1_SESSIONS)
+
#define MAX_TYPE0_SESSIONS 16
#define MAX_TYPE1_SESSIONS 6
@@ -27,7 +30,10 @@ enum pxp_sm_session_req {
PXP_SM_REQ_SESSION_TERMINATE
};
-#define PXP_ACTION_SET_R3_CONTEXT 5
+enum pxp_ioctl_action {
+ PXP_ACTION_SET_SESSION_STATUS = 1,
+ PXP_ACTION_SET_R3_CONTEXT = 5,
+};
enum pxp_sm_status {
PXP_SM_STATUS_SUCCESS,
@@ -36,10 +42,24 @@ enum pxp_sm_status {
PXP_SM_STATUS_ERROR_UNKNOWN
};
+struct pxp_sm_set_session_status_params {
+ /** @pxp_tag: in [optional], for Arbitrator session, out pxp tag */
+ u32 pxp_tag;
+ /** @session_type: in, session type */
+ u32 session_type;
+ /** @session_mode: in, session mode */
+ u32 session_mode;
+ /** @req_session_state: in, new session state */
+ u32 req_session_state;
+};
+
struct pxp_info {
u32 action;
u32 sm_status;
- u32 set_r3ctx;
+ union {
+ struct pxp_sm_set_session_status_params set_session_status;
+ u32 set_r3ctx;
+ };
} __packed;
struct pxp_context;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index fd5d10e71a27..62303dc197e2 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -324,6 +324,174 @@ static bool
check_if_protected_type0_sessions_are_attacked(struct drm_i915_priva
return false;
}
+/**
+ * create_new_session_entry - Create a new session entry with provided info.
+ * @i915: i915 device handle.
+ * @drmfile: pointer to drm_file
+ * @context_id: Numeric identifier of the context created by the caller.
+ * @session_type: Type of the session requested. One of enum pxp_session_types.
+ * @protection_mode: Type of protection requested for the session.
+ * One of the enum pxp_protection_modes.
+ * @session_index: Numeric session identifier.
+ *
+ * Return: status. 0 means creation is successful.
+ */
+static int create_new_session_entry(struct drm_i915_private *i915, struct
drm_file *drmfile,
+ int context_id, int session_type, int
protection_mode,
+ int session_index)
+{
+ int ret;
+ struct pxp_protected_session *new_session = NULL;
+ int pid = 0;
+
+ if (drmfile)
+ pid = pid_nr(drmfile->pid);
+
+ drm_dbg(&i915->drm, ">>> %s context_id=[%d] sess
[Intel-gfx] [PATCH 27/27] drm/i915/pxp: Add plane decryption support
From: Anshuman Gupta
Add support to enable/disable PLANE_SURF Decryption Request bit.
It requires only to enable plane decryption support when following
condition met.
1. PAVP session is enabled.
2. Buffer object is protected.
v2:
- Rebased to libva_cp-drm-tip_tgl_cp tree.
- Used gen fb obj user_flags instead gem_object_metadata. [Krishna]
Cc: Bommu Krishnaiah
Cc: Huang, Sean Z
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_sprite.c | 21 ++---
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index a3ab44694118..12c549beb05f 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -39,6 +39,8 @@
#include
#include
+#include "pxp/intel_pxp.h"
+
#include "i915_drv.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
@@ -752,6 +754,11 @@ icl_program_input_csc(struct intel_plane *plane,
PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
}
+static bool intel_fb_obj_protected(const struct drm_i915_gem_object *obj)
+{
+ return obj->user_flags & I915_BO_PROTECTED ? true : false;
+}
+
static void
skl_plane_async_flip(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
@@ -788,6 +795,7 @@ skl_program_plane(struct intel_plane *plane,
u32 surf_addr = plane_state->color_plane[color_plane].offset;
u32 stride = skl_plane_stride(plane_state, color_plane);
const struct drm_framebuffer *fb = plane_state->hw.fb;
+ const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
int aux_plane = intel_main_to_aux_plane(fb, color_plane);
int crtc_x = plane_state->uapi.dst.x1;
int crtc_y = plane_state->uapi.dst.y1;
@@ -798,7 +806,7 @@ skl_program_plane(struct intel_plane *plane,
u8 alpha = plane_state->hw.alpha >> 8;
u32 plane_color_ctl = 0, aux_dist = 0;
unsigned long irqflags;
- u32 keymsk, keymax;
+ u32 keymsk, keymax, plane_surf;
u32 plane_ctl = plane_state->ctl;
plane_ctl |= skl_plane_ctl_crtc(crtc_state);
@@ -874,8 +882,15 @@ skl_program_plane(struct intel_plane *plane,
* the control register just before the surface register.
*/
intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
- intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
- intel_plane_ggtt_offset(plane_state) + surf_addr);
+ plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
+
+ if (intel_pxp_gem_object_status(dev_priv, obj->user_flags) &&
+ intel_fb_obj_protected(obj))
+ plane_surf |= PLANE_SURF_DECRYPTION_ENABLED;
+ else
+ plane_surf &= ~PLANE_SURF_DECRYPTION_ENABLED;
+
+ intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf);
if (plane_state->scaler_id >= 0)
skl_program_scaler(plane, crtc_state, plane_state);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5c51c9df8b28..0ac7678cd6ba 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7206,6 +7206,7 @@ enum {
#define _PLANE_SURF_3(pipe)_PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
#define PLANE_SURF(pipe, plane)\
_MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
+#define PLANE_SURF_DECRYPTION_ENABLEDREG_BIT(2)
#define _PLANE_OFFSET_1_B 0x711a4
#define _PLANE_OFFSET_2_B 0x712a4
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 01/27] drm/i915/pxp: Introduce Intel PXP component
From: "Huang, Sean Z"
PXP (Protected Xe Path) is an i915 componment, that
helps ring3 to establish the hardware protected session and
manage the status of each alive software session, as well as
the life cycle of each session.
By design PXP will expose ioctl so allow ring3 to create, set,
and destroy each session. It will also provide the communication
chanel to TEE (Trusted Execution Environment) for the protected
hardware session creation.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile| 4
drivers/gpu/drm/i915/i915_drv.c | 4
drivers/gpu/drm/i915/i915_drv.h | 4
drivers/gpu/drm/i915/pxp/intel_pxp.c | 20
drivers/gpu/drm/i915/pxp/intel_pxp.h | 22 ++
include/uapi/drm/i915_drm.h | 5 +
6 files changed, 59 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index e5574e506a5c..8274fea96009 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -254,6 +254,10 @@ i915-y += \
i915-y += i915_perf.o
+# Protected execution platform (PXP) support
+i915-y += \
+ pxp/intel_pxp.o
+
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
i915-$(CONFIG_DRM_I915_SELFTEST) += \
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index f2389ba49c69..c8b9c42fcbd6 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -889,6 +889,8 @@ int i915_driver_probe(struct pci_dev *pdev, const struct
pci_device_id *ent)
if (ret)
goto out_cleanup_gem;
+ intel_pxp_init(i915);
+
i915_driver_register(i915);
enable_rpm_wakeref_asserts(&i915->runtime_pm);
@@ -938,6 +940,8 @@ void i915_driver_remove(struct drm_i915_private *i915)
/* Flush any external code that still may be under the RCU lock */
synchronize_rcu();
+ intel_pxp_uninit(i915);
+
i915_gem_suspend(i915);
drm_atomic_helper_shutdown(&i915->drm);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 15be8debae54..f34ed07a68ee 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -105,6 +105,8 @@
#include "intel_region_lmem.h"
+#include "pxp/intel_pxp.h"
+
/* General customization:
*/
@@ -1215,6 +1217,8 @@ struct drm_i915_private {
/* Mutex to protect the above hdcp component related values. */
struct mutex hdcp_comp_mutex;
+ struct intel_pxp pxp;
+
I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
/*
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
new file mode 100644
index ..a469c55e3e54
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+
+#include "i915_drv.h"
+#include "intel_pxp.h"
+
+int intel_pxp_init(struct drm_i915_private *i915)
+{
+ int ret;
+
+ drm_info(&i915->drm, "i915_pxp_init\n");
+
+ return ret;
+}
+
+void intel_pxp_uninit(struct drm_i915_private *i915)
+{
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
new file mode 100644
index ..578f1126bada
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_H__
+#define __INTEL_PXP_H__
+
+#include
+
+struct pxp_context;
+
+struct intel_pxp {
+ struct pxp_context *r0ctx;
+};
+
+struct drm_i915_private;
+
+int intel_pxp_init(struct drm_i915_private *i915);
+void intel_pxp_uninit(struct drm_i915_private *i915);
+
+#endif
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index fa1f3d62f9a6..dc101264176b 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1898,6 +1898,11 @@ struct drm_i915_gem_vm_control {
__u32 vm_id;
};
+struct drm_i915_pxp_ops {
+ __u64 pxp_info_ptr;
+ __u32 pxp_info_size;
+};
+
struct drm_i915_reg_read {
/*
* Register offset.
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 08/27] drm/i915/pxp: Read register to check hardware session state
From: "Huang, Sean Z"
Implement the functions to check the hardware protected session
state via reading the hardware register session in play.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.h| 3 +
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 189
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 51 +++
3 files changed, 243 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 21a6964fc64e..95d3deba7ade 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -12,6 +12,9 @@
#define PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ BIT(2)
#define PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE BIT(3)
+#define pxp_session_list(i915, session_type) (((session_type) ==
SESSION_TYPE_TYPE0) ? \
+ &(i915)->pxp.r0ctx->active_pxp_type0_sessions :
&(i915)->pxp.r0ctx->active_pxp_type1_sessions)
+
#define MAX_TYPE0_SESSIONS 16
#define MAX_TYPE1_SESSIONS 6
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index 75e4b229d9f8..3dd5a9e3926b 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -10,6 +10,25 @@
#include "intel_pxp_sm.h"
#include "intel_pxp_context.h"
+int pxp_sm_reg_read(struct drm_i915_private *i915, u32 offset, u32 *regval)
+{
+ intel_wakeref_t wakeref;
+ int err = 0;
+
+ if (!i915 || !regval) {
+ err = -EINVAL;
+ drm_dbg(&i915->drm, "Failed to %s bad params\n", __func__);
+ goto end;
+ }
+
+ with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
+ i915_reg_t reg_offset = {offset};
+ *regval = intel_uncore_read(&i915->uncore, reg_offset);
+ }
+end:
+ return err;
+}
+
static int pxp_reg_write(struct drm_i915_private *i915, u32 offset, u32 regval)
{
intel_wakeref_t wakeref;
@@ -30,6 +49,176 @@ static int pxp_reg_write(struct drm_i915_private *i915, u32
offset, u32 regval)
return err;
}
+/**
+ * is_sw_session_active - Check if the given sw session id is active.
+ * @i915: i915 device handle.
+ * @session_type: Specified session type
+ * @session_index: Numeric session identifier.
+ * @is_in_play: Set false to return true if the specified session is active.
+ * Set true to also check if the session is active and in_play.
+ * @protection_mode: get the protection mode of specified session.
+ *
+ * The caller needs to use ctx_mutex lock to protect the session_list
+ * inside this function.
+ *
+ * Return : true if session with the same identifier is active (and in_play).
+ */
+static bool is_sw_session_active(struct drm_i915_private *i915, int
session_type,
+int session_index, bool is_in_play, int
*protection_mode)
+{
+ struct pxp_protected_session *current_session;
+
+ lockdep_assert_held(&i915->pxp.r0ctx->ctx_mutex);
+
+ list_for_each_entry(current_session, pxp_session_list(i915,
session_type), session_list) {
+ if (current_session->session_index == session_index) {
+ if (protection_mode)
+ *protection_mode =
current_session->protection_mode;
+
+ if (is_in_play && !current_session->session_is_in_play)
+ return false;
+
+ return true;
+ }
+ }
+
+ /* session id not found. return false */
+ return false;
+}
+
+static bool is_hw_type0_session_in_play(struct drm_i915_private *i915, int
session_index)
+{
+ u32 regval_sip = 0;
+ u32 reg_session_id_mask;
+ bool hw_session_is_in_play = false;
+ int ret = 0;
+
+ if (!i915 || session_index < 0 || session_index >= MAX_TYPE0_SESSIONS) {
+ drm_dbg(&i915->drm, "Failed to %s due to invalid params",
__func__);
+ goto end;
+ }
+
+ ret = pxp_sm_reg_read(i915, GEN12_KCR_SIP.reg, ®val_sip);
+ if (ret) {
+ drm_dbg(&i915->drm, "Failed to read()\n");
+ goto end;
+ }
+
+ reg_session_id_mask = (1 << session_index);
+ hw_session_is_in_play = (bool)(regval_sip & reg_session_id_mask);
+end:
+ return hw_session_is_in_play;
+}
+
+static bool is_hw_type1_session_in_play(struct drm_i915_private *i915, int
session_index)
+{
+ int ret = 0;
+ u32 regval_tsip_low = 0;
+ u32 regval_tsip_high = 0;
+ u64 reg_session_id_mask;
+ u64 regval_tsip;
+ bool hw_session_is_in_play = false;
+
+ if (!i915 || session_index < 0 || session_index >= MAX_TYPE1_SESSIONS) {
+ drm_dbg(&i915->drm, "Failed to %s due to invalid params",
__func__);
+ goto end;
+ }
+
+ ret = pxp_sm_reg_read(i915, GEN12_KCR_TSIP_LOW.reg, ®val_tsip_low);
+ if (ret) {
+ drm_dbg(&i915->drm, "Failed to pxp
[Intel-gfx] [PATCH 09/27] drm/i915/pxp: Implement funcs to get/set PXP tag
From: "Huang, Sean Z"
Implement the functions to get/set the PXP tag, which is 32-bit
bitwise value containing the hardware session info, such as its
session id, protection mode or whether it's enabled.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 105
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 18
2 files changed, 123 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index 3dd5a9e3926b..fd5d10e71a27 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -49,6 +49,16 @@ static int pxp_reg_write(struct drm_i915_private *i915, u32
offset, u32 regval)
return err;
}
+static u8 pxp_get_session_id(int session_index, int session_type)
+{
+ u8 session_id = session_index & SESSION_ID_MASK;
+
+ if (session_type == SESSION_TYPE_TYPE1)
+ session_id |= SESSION_TYPE_MASK;
+
+ return session_id;
+}
+
/**
* is_sw_session_active - Check if the given sw session id is active.
* @i915: i915 device handle.
@@ -86,6 +96,101 @@ static bool is_sw_session_active(struct drm_i915_private
*i915, int session_type
return false;
}
+static int pxp_set_pxp_tag(struct drm_i915_private *i915, int session_type,
+ int session_idx, int protection_mode)
+{
+ struct pxp_tag *pxp_tag;
+ int ret;
+
+ if (!i915 || session_type >= SESSION_TYPE_MAX) {
+ ret = -EINVAL;
+ drm_dbg(&i915->drm, "Failed to %s, bad params\n", __func__);
+ goto end;
+ }
+
+ if (session_type == SESSION_TYPE_TYPE0 && session_idx <
MAX_TYPE0_SESSIONS) {
+ pxp_tag = (struct pxp_tag
*)&i915->pxp.r0ctx->type0_session_pxp_tag[session_idx];
+ } else if (session_type == SESSION_TYPE_TYPE1 && session_idx <
MAX_TYPE1_SESSIONS) {
+ pxp_tag = (struct pxp_tag
*)&i915->pxp.r0ctx->type1_session_pxp_tag[session_idx];
+ } else {
+ ret = -EINVAL;
+ drm_dbg(&i915->drm, "Failed to %s, bad params
session_type=[%d], session_idx=[%d]\n",
+ __func__, session_type, session_idx);
+ goto end;
+ }
+
+ switch (protection_mode) {
+ case PROTECTION_MODE_NONE:
+ {
+ pxp_tag->enable = false;
+ pxp_tag->hm = false;
+ pxp_tag->sm = false;
+ break;
+ }
+ case PROTECTION_MODE_LM:
+ {
+ pxp_tag->enable = true;
+ pxp_tag->hm = false;
+ pxp_tag->sm = false;
+ pxp_tag->instance_id++;
+ break;
+ }
+ case PROTECTION_MODE_HM:
+ {
+ pxp_tag->enable = true;
+ pxp_tag->hm = true;
+ pxp_tag->sm = false;
+ pxp_tag->instance_id++;
+ break;
+ }
+ case PROTECTION_MODE_SM:
+ {
+ pxp_tag->enable = true;
+ pxp_tag->hm = true;
+ pxp_tag->sm = true;
+ pxp_tag->instance_id++;
+ break;
+ }
+ default:
+ ret = -EINVAL;
+ drm_dbg(&i915->drm, "Failed to %s, bad params
protection_mode=[%d]\n",
+ __func__, protection_mode);
+ goto end;
+ }
+
+ pxp_tag->session_id = pxp_get_session_id(session_idx, session_type);
+
+ ret = 0;
+end:
+ return ret;
+}
+
+u32 intel_pxp_get_pxp_tag(struct drm_i915_private *i915, int session_idx,
+ int session_type, u32 *session_is_alive)
+{
+ struct pxp_tag *pxp_tag;
+
+ if (!i915 || session_type >= SESSION_TYPE_MAX) {
+ drm_dbg(&i915->drm, "Failed to %s, bad params\n", __func__);
+ return -EINVAL;
+ }
+
+ if (session_type == SESSION_TYPE_TYPE0 && session_idx <
MAX_TYPE0_SESSIONS) {
+ pxp_tag = (struct pxp_tag
*)&i915->pxp.r0ctx->type0_session_pxp_tag[session_idx];
+ } else if (session_type == SESSION_TYPE_TYPE1 && session_idx <
MAX_TYPE1_SESSIONS) {
+ pxp_tag = (struct pxp_tag
*)&i915->pxp.r0ctx->type1_session_pxp_tag[session_idx];
+ } else {
+ drm_dbg(&i915->drm, "Failed to %s, bad params
session_type=[%d], session_idx=[%d]\n",
+ __func__, session_type, session_idx);
+ return -EINVAL;
+ }
+
+ if (session_is_alive)
+ *session_is_alive = pxp_tag->enable;
+
+ return pxp_tag->value;
+}
+
static bool is_hw_type0_session_in_play(struct drm_i915_private *i915, int
session_index)
{
u32 regval_sip = 0;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
index a3149c18c831..c1f6b1be3fd1 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
@@ -19,6 +19,9 @
[Intel-gfx] [PATCH 13/27] drm/i915/pxp: Enable ioctl action to terminate the session
From: "Huang, Sean Z"
Enable the PXP ioctl action to allow ring3 PXP to terminate the
hardware session and cleanup its software session state.
Ring0 PXP sends the session termination command to GPU once
receves this ioctl action.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c| 7 +
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 205
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 5 +
3 files changed, 217 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index baa61a3a70ff..72a2237b504b 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -65,6 +65,13 @@ int i915_pxp_ops_ioctl(struct drm_device *dev, void *data,
struct drm_file *drmf
ret = pxp_sm_mark_protected_session_in_play(i915,
params->session_type,
params->pxp_tag);
+ } else if (params->req_session_state ==
PXP_SM_REQ_SESSION_TERMINATE) {
+ ret = pxp_sm_terminate_protected_session_safe(i915, 0,
+
params->session_type,
+
params->pxp_tag);
+
+ if (!intel_pxp_sm_is_any_type0_session_in_play(i915,
PROTECTION_MODE_ALL))
+ intel_pxp_destroy_r3ctx_list(i915);
} else {
ret = -EINVAL;
goto end;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index 0e1ce75f9ccd..b1adfa735d4f 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -893,6 +893,189 @@ static int issue_hw_terminate_for_session(struct
drm_i915_private *i915, int ses
return ret;
}
+/**
+ * terminate_protected_session - To terminate an active HW session and free
its entry.
+ * @i915: i915 device handle.
+ * @context_id: context identifier of the requestor. only relevant if
do_safety_check is true.
+ * @session_type: type of the session to be terminated. One of enum
pxp_session_types.
+ * @session_index: session index of the session to be terminated.
+ * @do_safety_check: if enabled the context Id sent by the caller is
+ * matched with the one associated with the terminated
+ * session entry.
+ *
+ * Return: status. 0 means terminate is successful.
+ */
+static int terminate_protected_session(struct drm_i915_private *i915, int
context_id,
+ int session_type, int session_index,
+ bool do_safety_check)
+{
+ int ret;
+ struct pxp_protected_session *current_session, *n;
+
+ drm_dbg(&i915->drm, ">>> %s conext_id=[%d] session_type=[%d]
session_index=[0x%08x] do_safety_check=[%d]\n",
+ __func__, context_id, session_type, session_index,
do_safety_check);
+
+ lockdep_assert_held(&i915->pxp.r0ctx->ctx_mutex);
+
+ switch (session_type) {
+ case SESSION_TYPE_TYPE0:
+ list_for_each_entry_safe(current_session, n,
&i915->pxp.r0ctx->active_pxp_type0_sessions, session_list) {
+ if (current_session->session_index == session_index) {
+ if (do_safety_check &&
current_session->context_id != context_id) {
+ ret = -EPERM;
+ drm_dbg(&i915->drm, "Failed to %s due
to invalid context_id=[%d]\n", __func__, context_id);
+ goto end;
+ }
+
+ ret = issue_hw_terminate_for_session(i915,
session_type, session_index);
+ if (ret) {
+ drm_dbg(&i915->drm, "Failed to
issue_hw_terminate_for_session()\n");
+ goto end;
+ }
+
+ ret = pxp_set_pxp_tag(i915, session_type,
session_index, PROTECTION_MODE_NONE);
+ if (ret) {
+ drm_dbg(&i915->drm, "Failed to
pxp_set_pxp_tag()\n");
+ goto end;
+ }
+
+ /* delete the current session entry from the
linked list */
+ list_del(¤t_session->session_list);
+
+ /* free the memory associated with the current
context entry */
+ kfree(current_session);
+
+ /* TODO: special arbitrator session checks? */
+
+ ret = 0;
+ goto end;
+ }
+ }
+
+
[Intel-gfx] [PATCH 06/27] drm/i915: Rename the whitelist to allowlist
From: "Huang, Sean Z"
Rename the whitelist to allowlist as suggested
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/intel_uncore.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 1c14a07eba7d..c9ef0025c60e 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1989,12 +1989,12 @@ void intel_uncore_fini_mmio(struct intel_uncore *uncore)
uncore_mmio_cleanup(uncore);
}
-static const struct reg_whitelist {
+static const struct reg_allowlist {
i915_reg_t offset_ldw;
i915_reg_t offset_udw;
u16 gen_mask;
u8 size;
-} reg_read_whitelist[] = { {
+} reg_read_allowlist[] = { {
.offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
.offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
.gen_mask = INTEL_GEN_MASK(4, 12),
@@ -2007,14 +2007,14 @@ int i915_reg_read_ioctl(struct drm_device *dev,
struct drm_i915_private *i915 = to_i915(dev);
struct intel_uncore *uncore = &i915->uncore;
struct drm_i915_reg_read *reg = data;
- struct reg_whitelist const *entry;
+ struct reg_allowlist const *entry;
intel_wakeref_t wakeref;
unsigned int flags;
int remain;
int ret = 0;
- entry = reg_read_whitelist;
- remain = ARRAY_SIZE(reg_read_whitelist);
+ entry = reg_read_allowlist;
+ remain = ARRAY_SIZE(reg_read_allowlist);
while (remain) {
u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw);
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 26/27] drm/i915/pavp: User interface for Protected buffer
From: Bommu Krishnaiah
This api allow user mode to create Protected buffer and context creation.
Signed-off-by: Bommu Krishnaiah
Cc: Telukuntla Sreedhar
Cc: Kondapally Kalyan
Cc: Gupta Anshuman
Cc: Huang Sean Z
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 15 ++--
drivers/gpu/drm/i915/gem/i915_gem_context.h | 10
.../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +-
.../gpu/drm/i915/gem/i915_gem_object_types.h | 5
drivers/gpu/drm/i915/i915_gem.c | 23 +++
include/uapi/drm/i915_drm.h | 19 +++
6 files changed, 67 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 4fd38101bb56..1ca3265d6ca3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -2063,12 +2063,23 @@ static int ctx_setparam(struct drm_i915_file_private
*fpriv,
case I915_CONTEXT_PARAM_RECOVERABLE:
if (args->size)
ret = -EINVAL;
- else if (args->value)
- i915_gem_context_set_recoverable(ctx);
+ else if (args->value) {
+ if (!i915_gem_context_is_protected(ctx))
+ i915_gem_context_set_recoverable(ctx);
+ else
+ ret = -EPERM;
+ }
else
i915_gem_context_clear_recoverable(ctx);
break;
+ case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
+ if (args->size)
+ ret = -EINVAL;
+ else if (args->value)
+ i915_gem_context_set_protected(ctx);
+ break;
+
case I915_CONTEXT_PARAM_PRIORITY:
ret = set_priority(ctx, args);
break;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h
b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index a133f92bbedb..5897e7ca11a8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -70,6 +70,16 @@ static inline void i915_gem_context_set_recoverable(struct
i915_gem_context *ctx
set_bit(UCONTEXT_RECOVERABLE, &ctx->user_flags);
}
+static inline void i915_gem_context_set_protected(struct i915_gem_context *ctx)
+{
+ set_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
+}
+
+static inline bool i915_gem_context_is_protected(struct i915_gem_context *ctx)
+{
+ return test_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
+}
+
static inline void i915_gem_context_clear_recoverable(struct i915_gem_context
*ctx)
{
clear_bit(UCONTEXT_RECOVERABLE, &ctx->user_flags);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
index ae14ca24a11f..81ae94c2be86 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
@@ -135,7 +135,7 @@ struct i915_gem_context {
#define UCONTEXT_BANNABLE 2
#define UCONTEXT_RECOVERABLE 3
#define UCONTEXT_PERSISTENCE 4
-
+#define UCONTEXT_PROTECTED 5
/**
* @flags: small set of booleans
*/
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index e2d9b7e1e152..90ac955463f4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -161,6 +161,11 @@ struct drm_i915_gem_object {
} mmo;
I915_SELFTEST_DECLARE(struct list_head st_link);
+ /**
+* @user_flags: small set of booleans set by the user
+*/
+ unsigned long user_flags;
+#define I915_BO_PROTECTED BIT(0)
unsigned long flags;
#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 41698a823737..6a791fd24eaa 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -184,7 +184,8 @@ static int
i915_gem_create(struct drm_file *file,
struct intel_memory_region *mr,
u64 *size_p,
- u32 *handle_p)
+ u32 *handle_p,
+ u64 user_flags)
{
struct drm_i915_gem_object *obj;
u32 handle;
@@ -204,6 +205,8 @@ i915_gem_create(struct drm_file *file,
if (IS_ERR(obj))
return PTR_ERR(obj);
+ obj->user_flags = user_flags;
+
ret = drm_gem_handle_create(file, &obj->base, &handle);
/* drop reference from allocate - handle holds it now */
i915_gem_object_put(obj);
@@ -258,11 +261,12 @@ i915_gem_dumb_create(struct drm_file *file,
return i915_gem_create(file,
intel_memory_region_by_type(to_i915(dev),
[Intel-gfx] [PATCH 15/27] drm/i915/pxp: Destroy all type0 sessions upon teardown
From: "Huang, Sean Z"
Teardown is triggered when the display topology changes and no
long meets the secure playback requirement, and hardware trashes
all the encryption keys for display. So as a result, ring0 PXP
should handle such case and terminate all the type0 sessions.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c| 6 +-
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 118
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 1 +
3 files changed, 124 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 2121db05fdb6..40728ef70e20 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -134,6 +134,8 @@ static void intel_pxp_mask_irq(struct intel_gt *gt, u32
mask)
static int intel_pxp_teardown_required_callback(struct drm_i915_private *i915)
{
+ int ret;
+
drm_dbg(&i915->drm, "%s was called\n", __func__);
mutex_lock(&i915->pxp.r0ctx->ctx_mutex);
@@ -141,11 +143,13 @@ static int intel_pxp_teardown_required_callback(struct
drm_i915_private *i915)
i915->pxp.r0ctx->global_state_attacked = true;
i915->pxp.r0ctx->flag_display_hm_surface_keys = false;
+ ret = intel_pxp_sm_terminate_all_active_sessions(i915,
SESSION_TYPE_TYPE0);
+
intel_pxp_destroy_r3ctx_list(i915);
mutex_unlock(&i915->pxp.r0ctx->ctx_mutex);
- return 0;
+ return ret;
}
static int intel_pxp_global_terminate_complete_callback(struct
drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index 994abf5a8d36..37fe2e5af88d 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -893,6 +893,73 @@ static int issue_hw_terminate_for_session(struct
drm_i915_private *i915, int ses
return ret;
}
+static int terminate_all_hw_sessions_with_global_termination(struct
drm_i915_private *i915,
+int session_type)
+{
+ u32 *cmd = NULL;
+ u32 *cmd_ptr = NULL;
+ int cmd_size_in_dw = 0;
+ int ret;
+ int session_index;
+ const int session_num_max = pxp_session_max(session_type);
+
+ drm_dbg(&i915->drm, ">>> %s session_type=[%d]\n", __func__,
session_type);
+
+ if (!i915) {
+ ret = -EINVAL;
+ drm_dbg(&i915->drm, "Failed to %s due to bad params\n",
__func__);
+ goto end;
+ }
+
+ /* Calculate how many bytes need to be alloc */
+ for (session_index = 0; session_index < session_num_max;
session_index++) {
+ if (is_hw_session_in_play(i915, session_type, session_index)) {
+ cmd_size_in_dw += add_pxp_prolog(i915, NULL,
session_type, session_index);
+ cmd_size_in_dw += add_pxp_inline_termination(NULL);
+ }
+ }
+ cmd_size_in_dw += add_pxp_epilog(NULL);
+
+ cmd = kzalloc(cmd_size_in_dw * 4, GFP_KERNEL);
+ if (!cmd) {
+ ret = -ENOMEM;
+ drm_dbg(&i915->drm, "Failed to kzalloc()\n");
+ goto end;
+ }
+
+ /* Program the command */
+ cmd_ptr = cmd;
+ for (session_index = 0; session_index < session_num_max;
session_index++) {
+ if (is_hw_session_in_play(i915, session_type, session_index)) {
+ cmd_ptr += add_pxp_prolog(i915, cmd_ptr, session_type,
session_index);
+ cmd_ptr += add_pxp_inline_termination(cmd_ptr);
+ }
+ }
+ cmd_ptr += add_pxp_epilog(cmd_ptr);
+
+ if (cmd_size_in_dw != (cmd_ptr - cmd)) {
+ ret = -EINVAL;
+ drm_dbg(&i915->drm, "Failed to %s\n", __func__);
+ goto end;
+ }
+
+ if (drm_debug_enabled(DRM_UT_DRIVER)) {
+ print_hex_dump(KERN_DEBUG, "global termination cmd binaries:",
+ DUMP_PREFIX_OFFSET, 4, 4, cmd, cmd_size_in_dw *
4, true);
+ }
+
+ ret = pxp_submit_cmd(i915, cmd, cmd_size_in_dw);
+ if (ret) {
+ drm_dbg(&i915->drm, "Failed to pxp_submit_cmd()\n");
+ goto end;
+ }
+
+end:
+ kfree(cmd);
+ drm_dbg(&i915->drm, "<<< %s ret=[%d]\n", __func__, ret);
+ return ret;
+}
+
/**
* terminate_protected_session - To terminate an active HW session and free
its entry.
* @i915: i915 device handle.
@@ -1076,6 +1143,57 @@ int pxp_sm_terminate_protected_session_unsafe(struct
drm_i915_private *i915, int
return ret;
}
+int intel_pxp_sm_destroy_all_sw_sessions(struct drm_i915_private *i915, int
session_type)
+{
+ int ret = 0;
+ struct pxp_protected_session *current_session, *n;
+
+ list_for_each_entry_safe(current_session, n, pxp_session_list(i915,
session_type), session_list) {
+ ret = pxp
[Intel-gfx] [PATCH 19/27] drm/i915/pxp: Enable ioctl action to send TEE commands
From: "Huang, Sean Z"
Enable the ioctl action to allow ring3 driver sends TEE commands
via ring0 PXP ioctl, instead of TEE iotcl. So we can centralize
those protection operations at ring0 PXP.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 15 ++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 18 +++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 65
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 5 ++
4 files changed, 103 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 2cbdc6fa7cf6..1a6cad0502c5 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -7,6 +7,7 @@
#include "intel_pxp.h"
#include "intel_pxp_context.h"
#include "intel_pxp_sm.h"
+#include "intel_pxp_tee.h"
int i915_pxp_ops_ioctl(struct drm_device *dev, void *data, struct drm_file
*drmfile)
{
@@ -85,6 +86,20 @@ int i915_pxp_ops_ioctl(struct drm_device *dev, void *data,
struct drm_file *drmf
ret = pxp_sm_ioctl_query_pxp_tag(i915,
¶ms->session_is_alive, ¶ms->pxp_tag);
break;
}
+ case PXP_ACTION_TEE_IO_MESSAGE:
+ {
+ struct pxp_tee_io_message_params *params =
&pxp_info.tee_io_message;
+
+ ret = pxp_tee_ioctl_io_message(i915,
+ params->msg_in,
params->msg_in_size,
+ params->msg_out,
¶ms->msg_out_size,
+ params->msg_out_buf_size);
+ if (ret) {
+ drm_dbg(&i915->drm, "Failed to send TEE IO message\n");
+ ret = -EFAULT;
+ }
+ break;
+ }
case PXP_ACTION_SET_R3_CONTEXT:
{
ret = intel_pxp_set_r3ctx(i915, pxp_info.set_r3ctx);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 3d70b9bab79f..2c16ed0b5c0b 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -33,6 +33,7 @@ enum pxp_sm_session_req {
enum pxp_ioctl_action {
PXP_ACTION_QUERY_PXP_TAG = 0,
PXP_ACTION_SET_SESSION_STATUS = 1,
+ PXP_ACTION_TEE_IO_MESSAGE = 4,
PXP_ACTION_SET_R3_CONTEXT = 5,
};
@@ -59,12 +60,29 @@ struct pxp_sm_set_session_status_params {
u32 req_session_state;
};
+/**
+ * struct pxp_tee_io_message_params - Params to send/receive message to/from
TEE.
+ */
+struct pxp_tee_io_message_params {
+ /** @msg_in: in - message input from UMD */
+ u8 __user *msg_in;
+ /** @msg_in_size: in - message input size from UMD */
+ u32 msg_in_size;
+ /** @msg_out: in - message output buffer from UMD */
+ u8 __user *msg_out;
+ /** @msg_out_size: out- message output size from TEE */
+ u32 msg_out_size;
+ /** @msg_out_buf_size: in - message output buffer size from UMD */
+ u32 msg_out_buf_size;
+};
+
struct pxp_info {
u32 action;
u32 sm_status;
union {
struct pxp_sm_query_pxp_tag query_pxp_tag;
struct pxp_sm_set_session_status_params set_session_status;
+ struct pxp_tee_io_message_paramstee_io_message;
u32 set_r3ctx;
};
} __packed;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
index 5bf79ca45cea..7e10b7ac584f 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -60,6 +60,71 @@ static int intel_pxp_tee_io_message(struct drm_i915_private
*i915,
return ret;
}
+int pxp_tee_ioctl_io_message(struct drm_i915_private *i915,
+void __user *msg_in_user_ptr, u32 msg_in_size,
+void __user *msg_out_user_ptr, u32
*msg_out_size_ptr,
+u32 msg_out_buf_size)
+{
+ int ret;
+ void *msg_in = NULL;
+ void *msg_out = NULL;
+
+ drm_dbg(&i915->drm, ">>> %s\n", __func__);
+
+ if (!msg_in_user_ptr || !msg_out_user_ptr || msg_out_buf_size == 0 ||
+ msg_in_size == 0 || !msg_out_size_ptr) {
+ ret = -EINVAL;
+ drm_dbg(&i915->drm, "Failed to %s, invalid params\n", __func__);
+ goto end;
+ }
+
+ msg_in = kzalloc(msg_in_size, GFP_KERNEL);
+ if (!msg_in) {
+ ret = -ENOMEM;
+ drm_dbg(&i915->drm, "Failed to kzalloc\n");
+ goto end;
+ }
+
+ msg_out = kzalloc(msg_out_buf_size, GFP_KERNEL);
+ if (!msg_out) {
+ ret = -ENOMEM;
+ drm_dbg(&i915->drm, "Failed to kzalloc\n");
+ goto end;
+ }
+
+ if (copy_from_user(msg_in, msg_in_user_ptr, msg_in_size) != 0) {
+ ret = -EFAULT;
+ drm_dbg(&i915->drm, "Failed to copy_f
[Intel-gfx] [PATCH 23/27] mei: bus: enable pavp device.
From: Tomas Winkler
Enable protected audio video path client on mei client
bus.
Signed-off-by: Tomas Winkler
---
drivers/misc/mei/bus-fixup.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c
index 4e30fa98fe7d..042399b397c9 100644
--- a/drivers/misc/mei/bus-fixup.c
+++ b/drivers/misc/mei/bus-fixup.c
@@ -33,6 +33,9 @@ static const uuid_le mei_nfc_info_guid = MEI_UUID_NFC_INFO;
#define MEI_UUID_HDCP UUID_LE(0xB638AB7E, 0x94E2, 0x4EA2, \
0xA5, 0x52, 0xD1, 0xC5, 0x4B, 0x62, 0x7F, 0x04)
+#define MEI_UUID_PAVP UUID_LE(0xfbf6fcf1, 0x96cf, 0x4e2e, 0xA6, \
+ 0xa6, 0x1b, 0xab, 0x8c, 0xbe, 0x36, 0xb1)
+
#define MEI_UUID_ANY NULL_UUID_LE
/**
@@ -488,6 +491,7 @@ static struct mei_fixup {
MEI_FIXUP(MEI_UUID_MKHIF_FIX, mei_mkhi_fix),
MEI_FIXUP(MEI_UUID_HDCP, whitelist),
MEI_FIXUP(MEI_UUID_ANY, vt_support),
+ MEI_FIXUP(MEI_UUID_PAVP, whitelist),
};
/**
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 04/27] drm/i915/pxp: set KCR reg init during the boot time
From: "Huang, Sean Z"
Set the KCR init during the boot time, which is required by
hardware, to allow us doing further protection operation such
as sending commands to GPU or TEE
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c| 11 +-
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 48 +
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 19 ++
4 files changed, 78 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 831e8ad57560..81432a9f44d6 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -258,6 +258,7 @@ i915-y += i915_perf.o
i915-y += \
pxp/intel_pxp.o \
pxp/intel_pxp_context.o \
+ pxp/intel_pxp_sm.o
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 6d358f241406..3a24c2b13b14 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -6,6 +6,7 @@
#include "i915_drv.h"
#include "intel_pxp.h"
#include "intel_pxp_context.h"
+#include "intel_pxp_sm.h"
static void intel_pxp_write_irq_mask_reg(struct drm_i915_private *i915, u32
mask)
{
@@ -87,6 +88,8 @@ static void intel_pxp_irq_work(struct work_struct *work)
int intel_pxp_init(struct drm_i915_private *i915)
{
+ int ret;
+
drm_info(&i915->drm, "i915_pxp_init\n");
i915->pxp.r0ctx = intel_pxp_create_r0ctx(i915);
@@ -95,13 +98,19 @@ int intel_pxp_init(struct drm_i915_private *i915)
return -EFAULT;
}
+ ret = pxp_sm_set_kcr_init_reg(i915);
+ if (ret) {
+ drm_dbg(&i915->drm, "Failed to set kcr init reg\n");
+ return ret;
+ }
+
INIT_WORK(&i915->pxp.irq_work, intel_pxp_irq_work);
i915->pxp.handled_irr = (PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED |
PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ |
PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE);
- return 0;
+ return ret;
}
void intel_pxp_uninit(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
new file mode 100644
index ..75e4b229d9f8
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#include "gt/intel_context.h"
+#include "gt/intel_engine_pm.h"
+
+#include "intel_pxp.h"
+#include "intel_pxp_sm.h"
+#include "intel_pxp_context.h"
+
+static int pxp_reg_write(struct drm_i915_private *i915, u32 offset, u32 regval)
+{
+ intel_wakeref_t wakeref;
+ int err = 0;
+
+ if (!i915) {
+ err = -EINVAL;
+ drm_dbg(&i915->drm, "Failed to %s bad params\n", __func__);
+ goto end;
+ }
+
+ with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
+ i915_reg_t reg_offset = {offset};
+
+ intel_uncore_write(&i915->uncore, reg_offset, regval);
+ }
+end:
+ return err;
+}
+
+int pxp_sm_set_kcr_init_reg(struct drm_i915_private *i915)
+{
+ int ret;
+
+ drm_dbg(&i915->drm, ">>> %s\n", __func__);
+
+ ret = pxp_reg_write(i915, KCR_INIT.reg,
KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
+ if (ret) {
+ drm_dbg(&i915->drm, "Failed to write()\n");
+ goto end;
+ }
+
+end:
+ drm_dbg(&i915->drm, "<<< %s ret=[%d]\n", __func__, ret);
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
new file mode 100644
index ..59ce2394b590
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_SM_H__
+#define __INTEL_PXP_SM_H__
+
+#include "i915_reg.h"
+
+/* KCR register definitions */
+#define KCR_INIT_MMIO(0x320f0)
+#define KCR_INIT_MASK_SHIFT (16)
+/* Setting KCR Init bit is required after system boot */
+#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) <<
KCR_INIT_MASK_SHIFT))
+
+int pxp_sm_set_kcr_init_reg(struct drm_i915_private *i915);
+
+#endif /* __INTEL_PXP_SM_H__ */
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 22/27] drm/i915/pxp: Expose session state for display protection flip
From: "Huang, Sean Z"
Implement the intel_pxp_gem_object_status() to allow ring0 i915
display querying the current PXP session state. In the design,
ring0 display should not perform protection flip on the protected
buffers if there is no PXP session alive.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 8
drivers/gpu/drm/i915/pxp/intel_pxp.h | 2 ++
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 23955d7a3c3d..082c1aaabaa8 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -341,3 +341,11 @@ void intel_pxp_irq_handler(struct intel_gt *gt, u16 iir)
end:
return;
}
+
+bool intel_pxp_gem_object_status(struct drm_i915_private *i915, u64
gem_object_metadata)
+{
+ if (i915->pxp.r0ctx && i915->pxp.r0ctx->flag_display_hm_surface_keys)
+ return true;
+ else
+ return false;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index c0119ccdab08..eb0e548ce434 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -111,4 +111,6 @@ int i915_pxp_global_terminate_complete_callback(struct
drm_i915_private *i915);
int intel_pxp_init(struct drm_i915_private *i915);
void intel_pxp_uninit(struct drm_i915_private *i915);
+bool intel_pxp_gem_object_status(struct drm_i915_private *i915, u64
gem_object_metadata);
+
#endif
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 11/27] drm/i915/pxp: Enable ioctl action to set session in play
From: "Huang, Sean Z"
With this ioctl action, ring3 driver can set the session in state
"session in play", after ring3 reserved the session slot/id from
ring3 PXP, and sent the TEE commands to activate the corresponding
hardware session. Session state "session in play" means this
session is ready for secure playback.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c| 4 ++
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 92 +
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 2 +
3 files changed, 98 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 0f684851ecb2..baa61a3a70ff 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -61,6 +61,10 @@ int i915_pxp_ops_ioctl(struct drm_device *dev, void *data,
struct drm_file *drmf
pxp_info.sm_status = ret;
ret = 0;
}
+ } else if (params->req_session_state ==
PXP_SM_REQ_SESSION_IN_PLAY) {
+ ret = pxp_sm_mark_protected_session_in_play(i915,
params->session_type,
+
params->pxp_tag);
+
} else {
ret = -EINVAL;
goto end;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index 62303dc197e2..eb77380367aa 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -49,6 +49,25 @@ static int pxp_reg_write(struct drm_i915_private *i915, u32
offset, u32 regval)
return err;
}
+static int pxp_get_session_index(struct drm_i915_private *i915, u32 pxp_tag,
+int *session_index_out, int *session_type_out)
+{
+ int ret;
+
+ if (!session_index_out || !session_type_out) {
+ ret = -EINVAL;
+ drm_dbg(&i915->drm, "Failed to %s, bad params\n", __func__);
+ goto end;
+ }
+
+ *session_type_out = (pxp_tag & SESSION_TYPE_MASK) ? SESSION_TYPE_TYPE1
: SESSION_TYPE_TYPE0;
+ *session_index_out = pxp_tag & SESSION_ID_MASK;
+
+ ret = 0;
+end:
+ return ret;
+}
+
static u8 pxp_get_session_id(int session_index, int session_type)
{
u8 session_id = session_index & SESSION_ID_MASK;
@@ -492,6 +511,79 @@ int intel_pxp_sm_reserve_session(struct drm_i915_private
*i915, struct drm_file
return ret;
}
+/**
+ * pxp_sm_mark_protected_session_in_play - To put an reserved protected
session to "in_play" state
+ * @i915: i915 device handle.
+ * @session_type: Type of the session to be updated. One of enum
pxp_session_types.
+ * @session_id: Session id identifier of the protected session.
+ *
+ * Return: status. 0 means update is successful.
+ */
+int pxp_sm_mark_protected_session_in_play(struct drm_i915_private *i915, int
session_type,
+ u32 session_id)
+{
+ int ret;
+ int session_index;
+ int session_type_in_id;
+ struct pxp_protected_session *current_session;
+
+ drm_dbg(&i915->drm, ">>> %s session_type=[%d] session_id=[0x%08x]\n",
__func__,
+ session_type, session_id);
+
+ ret = pxp_get_session_index(i915, session_id, &session_index,
&session_type_in_id);
+ if (ret) {
+ drm_dbg(&i915->drm, "Failed to pxp_get_session_index\n");
+ goto end;
+ }
+
+ if (session_type != session_type_in_id) {
+ ret = -EINVAL;
+ drm_dbg(&i915->drm, "Failed to session_type and
session_type_in_id don't match\n");
+ goto end;
+ }
+
+ lockdep_assert_held(&i915->pxp.r0ctx->ctx_mutex);
+
+ switch (session_type) {
+ case SESSION_TYPE_TYPE0:
+ list_for_each_entry(current_session,
&i915->pxp.r0ctx->active_pxp_type0_sessions, session_list) {
+ DRM_DEBUG("Traverse the active type0 list,
session_index=[%d]\n", current_session->session_index);
+ drm_dbg(&i915->drm, "Traverse the active type0 list,
session_index=[%d]\n", current_session->session_index);
+ if (current_session->session_index == session_index) {
+ current_session->session_is_in_play = true;
+ ret = 0;
+ goto end;
+ }
+ }
+
+ drm_dbg(&i915->drm, "Failed to %s couldn't find active type0
session\n", __func__);
+ ret = -EINVAL;
+ goto end;
+
+ case SESSION_TYPE_TYPE1:
+ list_for_each_entry(current_session,
&i915->pxp.r0ctx->active_pxp_type1_sessions, session_list) {
+ drm_dbg(&i915->drm, "Traverse the active type1 list,
session_index=[%d]\n", current_session->session_i
[Intel-gfx] [PATCH 16/27] drm/i915/pxp: Termiante the session upon app crash
From: "Huang, Sean Z"
Ring0 PXP should terminate the hardware session and cleanup the
software state gracefully when the application has established
the protection session, but doesn't close the session correctly
due to some cases like application crash.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/i915_drv.c | 2 ++
drivers/gpu/drm/i915/pxp/intel_pxp.c| 15 +++
drivers/gpu/drm/i915/pxp/intel_pxp.h| 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 21 +
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 1 +
5 files changed, 40 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 43ea85b5f14b..e61ffce52e3e 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1028,6 +1028,8 @@ static void i915_driver_postclose(struct drm_device *dev,
struct drm_file *file)
/* Catch up with all the deferred frees from "this" client */
i915_gem_flush_free_objects(to_i915(dev));
+
+ intel_pxp_close(to_i915(dev), file);
}
static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 40728ef70e20..75858c0842ba 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -110,6 +110,21 @@ int i915_pxp_ops_ioctl(struct drm_device *dev, void *data,
struct drm_file *drmf
return ret;
}
+int intel_pxp_close(struct drm_i915_private *i915, struct drm_file *drmfile)
+{
+ int ret;
+
+ drm_dbg(&i915->drm, ">>> %s i915=[%p] drmfile=[%p] pid=[%d]\n",
__func__,
+ i915, drmfile, pid_nr(drmfile->pid));
+
+ mutex_lock(&i915->pxp.r0ctx->ctx_mutex);
+ ret = intel_pxp_sm_close(i915, drmfile);
+ mutex_unlock(&i915->pxp.r0ctx->ctx_mutex);
+
+ drm_dbg(&i915->drm, "<<< %s ret=[%d]\n", __func__, ret);
+ return ret;
+}
+
static void intel_pxp_write_irq_mask_reg(struct drm_i915_private *i915, u32
mask)
{
WARN_ON(INTEL_GEN(i915) < 11);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 8851c28a0e57..3d70b9bab79f 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -83,6 +83,7 @@ struct intel_gt;
struct drm_i915_private;
int i915_pxp_ops_ioctl(struct drm_device *dev, void *data, struct drm_file
*drmfile);
+int intel_pxp_close(struct drm_i915_private *i915, struct drm_file *drmfile);
void intel_pxp_irq_handler(struct intel_gt *gt, u16 iir);
int i915_pxp_teardown_required_callback(struct drm_i915_private *i915);
int i915_pxp_global_terminate_complete_callback(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index 37fe2e5af88d..71082938b9f0 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -1260,3 +1260,24 @@ bool intel_pxp_sm_is_any_type0_session_in_play(struct
drm_i915_private *i915, in
return false;
}
+
+int intel_pxp_sm_close(struct drm_i915_private *i915, struct drm_file *drmfile)
+{
+ struct pxp_protected_session *s, *n;
+ int ret = 0;
+
+ drm_dbg(&i915->drm, ">>> %s\n", __func__);
+
+ list_for_each_entry_safe(s, n, pxp_session_list(i915,
SESSION_TYPE_TYPE0), session_list) {
+ if (s->drmfile && s->drmfile == drmfile && s->pid ==
pid_nr(drmfile->pid)) {
+ ret = terminate_protected_session(i915, 0,
s->session_type, s->session_index, false);
+ if (ret) {
+ drm_dbg(&i915->drm, "Failed to
terminate_protected_session()\n");
+ return ret;
+ }
+ }
+ }
+
+ drm_dbg(&i915->drm, "<<< %s ret=[%d]\n", __func__, ret);
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
index 955182a90bfe..b968a3169133 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
@@ -114,5 +114,6 @@ int pxp_sm_set_kcr_init_reg(struct drm_i915_private *i915);
u32 intel_pxp_get_pxp_tag(struct drm_i915_private *i915, int session_idx,
int session_type, u32 *session_is_alive);
bool intel_pxp_sm_is_any_type0_session_in_play(struct drm_i915_private *i915,
int protection_mode);
+int intel_pxp_sm_close(struct drm_i915_private *i915, struct drm_file
*drmfile);
#endif /* __INTEL_PXP_SM_H__ */
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 25/27] drm/i915/uapi: introduce drm_i915_gem_create_ext for TGL
From: Bommu Krishnaiah
Same old gem_create but with now with extensions support. This is needed
to support various upcoming usecases. For now we use the extensions
mechanism to support PAVP.
Signed-off-by: Bommu Krishnaiah
Cc: Joonas Lahtinen joonas.lahti...@linux.intel.com
Cc: Matthew Auld matthew.a...@intel.com
Cc: Telukuntla Sreedhar
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 42 -
include/uapi/drm/i915_drm.h | 47 +
3 files changed, 89 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 73c77a4e8216..a2b5b6f2723f 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1742,7 +1742,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop,
DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop,
DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
- DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl,
DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 58276694c848..41698a823737 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -53,6 +53,7 @@
#include "i915_drv.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
+#include "i915_user_extensions.h"
#include "intel_pm.h"
@@ -260,6 +261,35 @@ i915_gem_dumb_create(struct drm_file *file,
&args->size, &args->handle);
}
+struct create_ext {
+struct drm_i915_private *i915;
+};
+
+static int __create_setparam(struct drm_i915_gem_object_param *args,
+ struct create_ext
*ext_data)
+{
+ if (!(args->param & I915_OBJECT_PARAM)) {
+ DRM_DEBUG("Missing I915_OBJECT_PARAM namespace\n");
+ return -EINVAL;
+ }
+
+ return -EINVAL;
+}
+
+static int create_setparam(struct i915_user_extension __user *base, void *data)
+{
+ struct drm_i915_gem_create_ext_setparam ext;
+
+ if (copy_from_user(&ext, base, sizeof(ext)))
+ return -EFAULT;
+
+ return __create_setparam(&ext.param, data);
+}
+
+static const i915_user_extension_fn create_extensions[] = {
+ [I915_GEM_CREATE_EXT_SETPARAM] = create_setparam,
+};
+
/**
* Creates a new mm object and returns a handle to it.
* @dev: drm device pointer
@@ -271,10 +301,20 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
{
struct drm_i915_private *i915 = to_i915(dev);
- struct drm_i915_gem_create *args = data;
+ struct create_ext ext_data = { .i915 = i915 };
+ struct drm_i915_gem_create_ext *args = data;
+ int ret;
i915_gem_flush_free_objects(i915);
+ ret = i915_user_extensions(u64_to_user_ptr(args->extensions),
+ create_extensions,
+ ARRAY_SIZE(create_extensions),
+ &ext_data);
+ if (ret)
+ return ret;
+
+
return i915_gem_create(file,
intel_memory_region_by_type(i915,
INTEL_MEMORY_SYSTEM),
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 180f97fd91dc..97d4fefa7ad8 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -392,6 +392,7 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE +
DRM_I915_GEM_ENTERVT)
#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE +
DRM_I915_GEM_LEAVEVT)
#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
+#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext)
#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE +
DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE +
DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
#define DRM_IOCTL_I915_GEM_MMAPDRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
@@ -730,6 +731,27 @@ struct drm_i915_gem_create {
__u32 pad;
};
+struct drm_i915_gem_create_ext {
+ /**
+* Requested size for the object.
+*
+
[Intel-gfx] [PATCH 05/27] drm/i915/pxp: Enable ioctl action to set the ring3 context
From: "Huang, Sean Z"
Enable one ioctl action to allow ring3 driver to set its ring3
context, so ring0 PXP can track the context id through this ring3
context list.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 66
drivers/gpu/drm/i915/pxp/intel_pxp.h | 16 +
drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 34 ++
drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 3 +
include/uapi/drm/i915_drm.h | 2 +
6 files changed, 122 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index c8b9c42fcbd6..43ea85b5f14b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1761,6 +1761,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl,
DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(I915_PXP_OPS, i915_pxp_ops_ioctl, DRM_RENDER_ALLOW),
};
static const struct drm_driver driver = {
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 3a24c2b13b14..a83fa7cd749f 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -8,6 +8,70 @@
#include "intel_pxp_context.h"
#include "intel_pxp_sm.h"
+int i915_pxp_ops_ioctl(struct drm_device *dev, void *data, struct drm_file
*drmfile)
+{
+ int ret;
+ struct pxp_info pxp_info = {0};
+ struct drm_i915_pxp_ops *pxp_ops = data;
+ struct drm_i915_private *i915 = to_i915(dev);
+
+ drm_dbg(&i915->drm, ">>> %s\n", __func__);
+
+ if (!i915 || !drmfile || !pxp_ops || pxp_ops->pxp_info_size !=
sizeof(pxp_info)) {
+ drm_dbg(&i915->drm, "Failed to %s, invalid params\n", __func__);
+ ret = -EINVAL;
+ goto end;
+ }
+
+ if (copy_from_user(&pxp_info, (void __user *)pxp_ops->pxp_info_ptr,
sizeof(pxp_info)) != 0) {
+ ret = -EFAULT;
+ goto end;
+ }
+
+ drm_dbg(&i915->drm, "i915 pxp ioctl call with action=[%d]\n",
pxp_info.action);
+
+ mutex_lock(&i915->pxp.r0ctx->ctx_mutex);
+
+ if (i915->pxp.r0ctx->global_state_in_suspend) {
+ drm_dbg(&i915->drm, "Return failure due to state in suspend\n");
+ pxp_info.sm_status = PXP_SM_STATUS_SESSION_NOT_AVAILABLE;
+ ret = 0;
+ goto end;
+ }
+
+ if (i915->pxp.r0ctx->global_state_attacked) {
+ drm_dbg(&i915->drm, "Retry required due to state attacked\n");
+ pxp_info.sm_status = PXP_SM_STATUS_RETRY_REQUIRED;
+ ret = 0;
+ goto end;
+ }
+
+ switch (pxp_info.action) {
+ case PXP_ACTION_SET_R3_CONTEXT:
+ {
+ ret = intel_pxp_set_r3ctx(i915, pxp_info.set_r3ctx);
+ break;
+ }
+ default:
+ drm_dbg(&i915->drm, "Failed to %s due to bad params\n",
__func__);
+ ret = -EINVAL;
+ goto end;
+ }
+
+end:
+ mutex_unlock(&i915->pxp.r0ctx->ctx_mutex);
+
+ if (ret == 0)
+ if (copy_to_user((void __user *)pxp_ops->pxp_info_ptr,
&pxp_info, sizeof(pxp_info)) != 0)
+ ret = -EFAULT;
+
+ if (ret)
+ dev_err(&dev->pdev->dev, "pid=%d, ret = %d\n",
task_pid_nr(current), ret);
+
+ drm_dbg(&i915->drm, "<<< %s\n", __func__);
+ return ret;
+}
+
static void intel_pxp_write_irq_mask_reg(struct drm_i915_private *i915, u32
mask)
{
WARN_ON(INTEL_GEN(i915) < 11);
@@ -39,6 +103,8 @@ static int intel_pxp_teardown_required_callback(struct
drm_i915_private *i915)
i915->pxp.r0ctx->global_state_attacked = true;
i915->pxp.r0ctx->flag_display_hm_surface_keys = false;
+ intel_pxp_destroy_r3ctx_list(i915);
+
mutex_unlock(&i915->pxp.r0ctx->ctx_mutex);
return 0;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 4dec35bb834d..21a6964fc64e 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -24,6 +24,21 @@ enum pxp_sm_session_req {
PXP_SM_REQ_SESSION_TERMINATE
};
+#define PXP_ACTION_SET_R3_CONTEXT 5
+
+enum pxp_sm_status {
+ PXP_SM_STATUS_SUCCESS,
+ PXP_SM_STATUS_RETRY_REQUIRED,
+ PXP_SM_STATUS_SESSION_NOT_AVAILABLE,
+ PXP_SM_STATUS_ERROR_UNKNOWN
+};
+
+struct pxp_info {
+ u32 action;
+ u32 sm_status;
+ u32 set_r3ctx;
+} __packed;
+
struct pxp_context;
struct intel_pxp {
@@ -37,6 +52,7 @@ struct intel_pxp {
struct intel_gt;
struct drm_i915_private;
+int i915_pxp_ops_ioctl(struct drm_device *dev, void *data, struct drm_file
[Intel-gfx] [PATCH 17/27] drm/i915/pxp: Enable PXP power management
From: "Huang, Sean Z"
During the power event S3+ sleep/resume, hardware will lose all the
encryption keys for every hardware session, even though the
software session state was marked as alive after resume. So to
handle such case, ring0 PXP should terminate all the hardware
sessions and cleanup all the software states after the power cycle.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/i915_drv.c | 8 +++
drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 83 +
drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 14 +
4 files changed, 107 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 81432a9f44d6..6858392c1ef2 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -258,7 +258,8 @@ i915-y += i915_perf.o
i915-y += \
pxp/intel_pxp.o \
pxp/intel_pxp_context.o \
- pxp/intel_pxp_sm.o
+ pxp/intel_pxp_sm.o \
+ pxp/intel_pxp_pm.o
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e61ffce52e3e..830708414f92 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -68,6 +68,8 @@
#include "gt/intel_gt_pm.h"
#include "gt/intel_rc6.h"
+#include "pxp/intel_pxp_pm.h"
+
#include "i915_debugfs.h"
#include "i915_drv.h"
#include "i915_ioc32.h"
@@ -1094,6 +1096,8 @@ static int i915_drm_prepare(struct drm_device *dev)
*/
i915_gem_suspend(i915);
+ intel_pxp_pm_prepare_suspend(i915);
+
return 0;
}
@@ -1277,6 +1281,8 @@ static int i915_drm_resume(struct drm_device *dev)
intel_power_domains_enable(dev_priv);
+ intel_pxp_pm_resume(dev_priv);
+
enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
return 0;
@@ -1348,6 +1354,8 @@ static int i915_drm_resume_early(struct drm_device *dev)
intel_power_domains_resume(dev_priv);
+ intel_pxp_pm_resume_early(dev_priv);
+
enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
return ret;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
new file mode 100644
index ..18d33efca9d9
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+
+#include "i915_drv.h"
+#include "intel_pxp_context.h"
+#include "intel_pxp_sm.h"
+#include "intel_pxp_pm.h"
+
+void intel_pxp_pm_prepare_suspend(struct drm_i915_private *i915)
+{
+ drm_dbg(&i915->drm, ">>> %s\n", __func__);
+
+ if (!i915->pxp.r0ctx)
+ return;
+
+ mutex_lock(&i915->pxp.r0ctx->ctx_mutex);
+
+ /* Disable PXP-IOCTLs */
+ i915->pxp.r0ctx->global_state_in_suspend = true;
+
+ mutex_unlock(&i915->pxp.r0ctx->ctx_mutex);
+
+ drm_dbg(&i915->drm, "<<< %s\n", __func__);
+}
+
+void intel_pxp_pm_resume_early(struct drm_i915_private *i915)
+{
+ drm_dbg(&i915->drm, ">>> %s\n", __func__);
+
+ if (!i915->pxp.r0ctx)
+ return;
+
+ mutex_lock(&i915->pxp.r0ctx->ctx_mutex);
+
+ if (i915->pxp.r0ctx->global_state_in_suspend) {
+ /* reset the attacked flag even there was a pending */
+ i915->pxp.r0ctx->global_state_attacked = false;
+
+ i915->pxp.r0ctx->flag_display_hm_surface_keys = false;
+ }
+
+ mutex_unlock(&i915->pxp.r0ctx->ctx_mutex);
+ drm_dbg(&i915->drm, "<<< %s\n", __func__);
+}
+
+int intel_pxp_pm_resume(struct drm_i915_private *i915)
+{
+ int ret = 0;
+
+ drm_dbg(&i915->drm, ">>> %s\n", __func__);
+
+ if (!i915->pxp.r0ctx)
+ return 0;
+
+ mutex_lock(&i915->pxp.r0ctx->ctx_mutex);
+
+ /* Re-enable PXP-IOCTLs */
+ if (i915->pxp.r0ctx->global_state_in_suspend) {
+ intel_pxp_destroy_r3ctx_list(i915);
+
+ ret = intel_pxp_sm_terminate_all_active_sessions(i915,
SESSION_TYPE_TYPE0);
+ if (ret) {
+ drm_dbg(&i915->drm, "Failed to
intel_pxp_sm_terminate_all_active_sessions with type0\n");
+ goto end;
+ }
+
+ ret = intel_pxp_sm_terminate_all_active_sessions(i915,
SESSION_TYPE_TYPE1);
+ if (ret) {
+ drm_dbg(&i915->drm, "Failed to
intel_pxp_sm_terminate_all_active_sessions with type1\n");
+ goto end;
+ }
+
+ i915->pxp.r0ctx->global_state_in_suspend = false;
+ }
+
+end:
+ mutex_unlock(&i915->pxp.r0ctx->ctx_mutex);
+ drm_dbg(&i915->drm, "<<< %s ret=[%d]\n", __func__, ret);
+
+ return ret;
+}
diff
[Intel-gfx] [PATCH 12/27] drm/i915/pxp: Func to send hardware session termination
From: "Huang, Sean Z"
Implement the functions to allow ring0 PXP to send a GPU command
in order to terminate the hardware session, so hardware can
recycle this session slot for the next usage.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 309
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 16 ++
2 files changed, 325 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index eb77380367aa..0e1ce75f9ccd 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -3,13 +3,175 @@
* Copyright(c) 2020, Intel Corporation. All rights reserved.
*/
+#include "gt/intel_gpu_commands.h"
+#include "gt/intel_gt.h"
#include "gt/intel_context.h"
+#include "gt/intel_gt_buffer_pool.h"
#include "gt/intel_engine_pm.h"
#include "intel_pxp.h"
#include "intel_pxp_sm.h"
#include "intel_pxp_context.h"
+static struct i915_vma *pxp_get_batch(struct drm_i915_private *i915,
+ struct intel_context *ce,
+ struct intel_gt_buffer_pool_node *pool,
+ u32 *cmd_buf, int cmd_size_in_dw)
+{
+ struct i915_vma *batch = ERR_PTR(-EINVAL);
+ u32 *cmd;
+
+ drm_dbg(&i915->drm, ">>> %s cmd_buf=[%p] cmd_size_in_dw=[%d]\n",
__func__, cmd_buf, cmd_size_in_dw);
+
+ if (!ce || !ce->engine || !cmd_buf) {
+ drm_dbg(&i915->drm, "Failed to %s due to nullptr\n", __func__);
+ goto end;
+ }
+
+ if (cmd_size_in_dw * 4 > PAGE_SIZE) {
+ drm_dbg(&i915->drm, "Failed to %s, invalid
cmd_size_id_dw=[%d]\n",
+ __func__, cmd_size_in_dw);
+ goto end;
+ }
+
+ cmd = i915_gem_object_pin_map(pool->obj, I915_MAP_FORCE_WC);
+ if (IS_ERR(cmd)) {
+ drm_dbg(&i915->drm, "Failed to i915_gem_object_pin_map()\n ");
+ goto end;
+ }
+
+ memcpy(cmd, cmd_buf, cmd_size_in_dw * 4);
+
+ if (drm_debug_enabled(DRM_UT_DRIVER)) {
+ print_hex_dump(KERN_DEBUG, "cmd binaries:",
+ DUMP_PREFIX_OFFSET, 4, 4, cmd, cmd_size_in_dw *
4, true);
+ }
+
+ i915_gem_object_unpin_map(pool->obj);
+
+ batch = i915_vma_instance(pool->obj, ce->vm, NULL);
+ if (IS_ERR(batch)) {
+ drm_dbg(&i915->drm, "Failed to i915_vma_instance()\n ");
+ goto end;
+ }
+
+end:
+ drm_dbg(&i915->drm, "<<< %s: batch=[%p]\n", __func__, batch);
+ return batch;
+}
+
+static int pxp_submit_cmd(struct drm_i915_private *i915, u32 *cmd, int
cmd_size_in_dw)
+{
+ int err = -EINVAL;
+ struct i915_vma *batch;
+ struct i915_request *rq;
+ struct intel_context *ce = NULL;
+ bool is_engine_pm_get = false;
+ bool is_batch_vma_pin = false;
+ bool is_skip_req_on_err = false;
+ bool is_engine_get_pool = false;
+ struct intel_gt_buffer_pool_node *pool = NULL;
+ struct intel_gt *gt = NULL;
+
+ drm_dbg(&i915->drm, ">>> %s: cmd=[%p] cmd_size_in_dw=[%d]\n",
+ __func__, cmd, cmd_size_in_dw);
+
+ if (!i915 || !HAS_ENGINE(&i915->gt, VCS0) ||
+ !i915->gt.engine[VCS0]->kernel_context) {
+ err = -EINVAL;
+ drm_dbg(&i915->drm, "Failed to %s bad params\n", __func__);
+ goto end;
+ }
+
+ if (!cmd || (cmd_size_in_dw * 4) > PAGE_SIZE) {
+ err = -EINVAL;
+ drm_dbg(&i915->drm, "Failed to %s bad params\n", __func__);
+ goto end;
+ }
+
+ gt = &i915->gt;
+ ce = i915->gt.engine[VCS0]->kernel_context;
+
+ intel_engine_pm_get(ce->engine);
+ is_engine_pm_get = true;
+
+ pool = intel_gt_get_buffer_pool(gt, PAGE_SIZE);
+ if (IS_ERR(pool)) {
+ drm_dbg(&i915->drm, "Failed to intel_engine_get_pool()\n");
+ goto end;
+ }
+ is_engine_get_pool = true;
+
+ batch = pxp_get_batch(i915, ce, pool, cmd, cmd_size_in_dw);
+ if (IS_ERR(batch)) {
+ drm_dbg(&i915->drm, "Failed to pxp_get_batch()\n");
+ goto end;
+ }
+
+ err = i915_vma_pin(batch, 0, 0, PIN_USER);
+ if (err) {
+ drm_dbg(&i915->drm, "Failed to i915_vma_pin()\n");
+ goto end;
+ }
+ is_batch_vma_pin = true;
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq)) {
+ drm_dbg(&i915->drm, "Failed to
intel_context_create_request()\n");
+ goto end;
+ }
+ is_skip_req_on_err = true;
+
+ err = intel_gt_buffer_pool_mark_active(pool, rq);
+ if (err) {
+ drm_dbg(&i915->drm, "Failed to
intel_engine_pool_mark_active()\n");
+ goto end;
+ }
+
+ i915_vma_lock(batch);
+ err = i915_request_await_object(rq, batch->obj
[Intel-gfx] [PATCH 07/27] drm/i915/pxp: Add PXP-related registers into allowlist
From: "Huang, Sean Z"
Add several PXP-related reg into allowlist to allow
ring3 driver to read the those register values.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/i915_reg.h | 8
drivers/gpu/drm/i915/intel_uncore.c | 57 +
2 files changed, 50 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index faf6b06145fa..5c51c9df8b28 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -12419,4 +12419,12 @@ enum skl_power_gate {
#define TGL_ROOT_DEVICE_SKU_ULX0x2
#define TGL_ROOT_DEVICE_SKU_ULT0x4
+/* Registers for passlist check */
+#define PXP_REG_01_LOWERBOUND _MMIO(0x32260)
+#define PXP_REG_01_UPPERBOUND _MMIO(0x32268)
+#define PXP_REG_02_LOWERBOUND _MMIO(0x32670)
+#define PXP_REG_02_UPPERBOUND _MMIO(0x32678)
+#define PXP_REG_03_LOWERBOUND _MMIO(0x32860)
+#define PXP_REG_03_UPPERBOUND _MMIO(0x32c7c)
+
#endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index c9ef0025c60e..670856e095c4 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1990,16 +1990,41 @@ void intel_uncore_fini_mmio(struct intel_uncore *uncore)
}
static const struct reg_allowlist {
- i915_reg_t offset_ldw;
+ i915_reg_t offset_ldw_lowerbound;
+ i915_reg_t offset_ldw_upperbound;
i915_reg_t offset_udw;
u16 gen_mask;
u8 size;
-} reg_read_allowlist[] = { {
- .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
+} reg_read_allowlist[] = {
+ {
+ .offset_ldw_lowerbound = RING_TIMESTAMP(RENDER_RING_BASE),
+ .offset_ldw_upperbound = RING_TIMESTAMP(RENDER_RING_BASE),
.offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
.gen_mask = INTEL_GEN_MASK(4, 12),
.size = 8
-} };
+ },
+ {
+ .offset_ldw_lowerbound = PXP_REG_01_LOWERBOUND,
+ .offset_ldw_upperbound = PXP_REG_01_UPPERBOUND,
+ .offset_udw = {0},
+ .gen_mask = INTEL_GEN_MASK(4, 12),
+ .size = 4
+ },
+ {
+ .offset_ldw_lowerbound = PXP_REG_02_LOWERBOUND,
+ .offset_ldw_upperbound = PXP_REG_02_UPPERBOUND,
+ .offset_udw = {0},
+ .gen_mask = INTEL_GEN_MASK(4, 12),
+ .size = 4
+ },
+ {
+ .offset_ldw_lowerbound = PXP_REG_03_LOWERBOUND,
+ .offset_ldw_upperbound = PXP_REG_03_UPPERBOUND,
+ .offset_udw = {0},
+ .gen_mask = INTEL_GEN_MASK(4, 12),
+ .size = 4
+ }
+};
int i915_reg_read_ioctl(struct drm_device *dev,
void *data, struct drm_file *file)
@@ -2012,18 +2037,22 @@ int i915_reg_read_ioctl(struct drm_device *dev,
unsigned int flags;
int remain;
int ret = 0;
+ i915_reg_t offset_ldw;
entry = reg_read_allowlist;
remain = ARRAY_SIZE(reg_read_allowlist);
while (remain) {
- u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw);
+ u32 entry_offset_lb =
i915_mmio_reg_offset(entry->offset_ldw_lowerbound);
+ u32 entry_offset_ub =
i915_mmio_reg_offset(entry->offset_ldw_upperbound);
GEM_BUG_ON(!is_power_of_2(entry->size));
GEM_BUG_ON(entry->size > 8);
- GEM_BUG_ON(entry_offset & (entry->size - 1));
+ GEM_BUG_ON(entry_offset_lb & (entry->size - 1));
+ GEM_BUG_ON(entry_offset_ub & (entry->size - 1));
if (INTEL_INFO(i915)->gen_mask & entry->gen_mask &&
- entry_offset == (reg->offset & -entry->size))
+ entry_offset_lb <= (reg->offset & -entry->size) &&
+ (reg->offset & -entry->size) <= entry_offset_ub)
break;
entry++;
remain--;
@@ -2033,23 +2062,21 @@ int i915_reg_read_ioctl(struct drm_device *dev,
return -EINVAL;
flags = reg->offset & (entry->size - 1);
+ offset_ldw = _MMIO(reg->offset - flags);
with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
if (entry->size == 8 && flags == I915_REG_READ_8B_WA)
reg->val = intel_uncore_read64_2x32(uncore,
- entry->offset_ldw,
+ offset_ldw,
entry->offset_udw);
else if (entry->size == 8 && flags == 0)
- reg->val = intel_uncore_read64(uncore,
- entry->offset_ldw);
+ reg->val = intel_uncore_read64(uncore, offset_ldw);
else if (entry->size == 4 && flags == 0)
- reg->val = intel_uncore_read(uncore, entry->offset
[Intel-gfx] [PATCH 24/27] mei: pxp: export pavp client to me client bus
From: Vitaly Lubart
Export PAVP client to work with i915_cp driver,
for binding it uses kernel component framework.
Signed-off-by: Vitaly Lubart
Signed-off-by: Tomas Winkler
---
drivers/misc/mei/Kconfig | 2 +
drivers/misc/mei/Makefile | 1 +
drivers/misc/mei/pxp/Kconfig | 13 ++
drivers/misc/mei/pxp/Makefile | 7 +
drivers/misc/mei/pxp/mei_pxp.c | 230 +
drivers/misc/mei/pxp/mei_pxp.h | 18 +++
6 files changed, 271 insertions(+)
create mode 100644 drivers/misc/mei/pxp/Kconfig
create mode 100644 drivers/misc/mei/pxp/Makefile
create mode 100644 drivers/misc/mei/pxp/mei_pxp.c
create mode 100644 drivers/misc/mei/pxp/mei_pxp.h
diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig
index c06581ffa7bd..36884b0a6395 100644
--- a/drivers/misc/mei/Kconfig
+++ b/drivers/misc/mei/Kconfig
@@ -57,3 +57,5 @@ config INTEL_MEI_VIRTIO
device over virtio.
source "drivers/misc/mei/hdcp/Kconfig"
+source "drivers/misc/mei/pxp/Kconfig"
+
diff --git a/drivers/misc/mei/Makefile b/drivers/misc/mei/Makefile
index 52aefaab5c1b..cab19c96ba7a 100644
--- a/drivers/misc/mei/Makefile
+++ b/drivers/misc/mei/Makefile
@@ -29,3 +29,4 @@ mei-$(CONFIG_EVENT_TRACING) += mei-trace.o
CFLAGS_mei-trace.o = -I$(src)
obj-$(CONFIG_INTEL_MEI_HDCP) += hdcp/
+obj-$(CONFIG_INTEL_MEI_PXP) += pxp/
diff --git a/drivers/misc/mei/pxp/Kconfig b/drivers/misc/mei/pxp/Kconfig
new file mode 100644
index ..4029b96afc04
--- /dev/null
+++ b/drivers/misc/mei/pxp/Kconfig
@@ -0,0 +1,13 @@
+
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
+#
+config INTEL_MEI_PXP
+ tristate "Intel PXP services of ME Interface"
+ select INTEL_MEI_ME
+ depends on DRM_I915
+ help
+ MEI Support for PXP Services on Intel platforms.
+
+ Enables the ME FW services required for PXP support through
+ I915 display driver of Intel.
diff --git a/drivers/misc/mei/pxp/Makefile b/drivers/misc/mei/pxp/Makefile
new file mode 100644
index ..0329950d5794
--- /dev/null
+++ b/drivers/misc/mei/pxp/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
+#
+# Makefile - PXP client driver for Intel MEI Bus Driver.
+
+obj-$(CONFIG_INTEL_MEI_PXP) += mei_pxp.o
diff --git a/drivers/misc/mei/pxp/mei_pxp.c b/drivers/misc/mei/pxp/mei_pxp.c
new file mode 100644
index ..5bd61fe445e3
--- /dev/null
+++ b/drivers/misc/mei/pxp/mei_pxp.c
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+/**
+ * DOC: MEI_PXP Client Driver
+ *
+ * The mei_pxp driver acts as a translation layer between PXP
+ * protocol implementer (I915) and ME FW by translating PXP
+ * negotiation messages to ME FW command payloads and vice versa.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "mei_pxp.h"
+
+/**
+ * mei_pxp_send_message() - Sends a PXP message to ME FW.
+ * @dev: device corresponding to the mei_cl_device
+ * @message: a message buffer to send
+ * @size: size of the message
+ * Return: 0 on Success, <0 on Failure
+ */
+static int
+mei_pxp_send_message(struct device *dev, const void *message, size_t size)
+{
+ struct mei_cl_device *cldev;
+ ssize_t byte;
+
+ if (!dev || !message)
+ return -EINVAL;
+
+ cldev = to_mei_cl_device(dev);
+
+ /* temporary drop const qualifier till the API is fixed */
+ byte = mei_cldev_send(cldev, (u8 *)message, size);
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte);
+ return byte;
+ }
+
+ return 0;
+}
+
+/**
+ * mei_pxp_receive_message() - Receives a PXP message from ME FW.
+ * @dev: device corresponding to the mei_cl_device
+ * @buffer: a message buffer to contain the received message
+ * @size: size of the buffer
+ * Return: bytes sent on Success, <0 on Failure
+ */
+static int
+mei_pxp_receive_message(struct device *dev, void *buffer, size_t size)
+{
+ struct mei_cl_device *cldev;
+ ssize_t byte;
+
+ if (!dev || !buffer)
+ return -EINVAL;
+
+ cldev = to_mei_cl_device(dev);
+
+ byte = mei_cldev_recv(cldev, buffer, size);
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte);
+ return byte;
+ }
+
+ return byte;
+}
+
+static const struct i915_pxp_component_ops mei_pxp_ops = {
+ .owner = THIS_MODULE,
+ .send = mei_pxp_send_message,
+ .receive = mei_pxp_receive_message,
+};
+
+static int mei_component_master_bind(struct device *dev)
+{
+ struct mei_cl_device *cldev = to_mei_cl_device(dev);
+ struct i915_pxp_comp_master *comp_master = mei_cldev_get_drvdata(cldev);
+ int ret;
+
+ dev_dbg(dev, "%s\n", __func__);
+ comp_master->ops = &mei_pxp_ops;
+
[Intel-gfx] [PATCH 21/27] drm/i915/pxp: Add i915 trace logs for PXP operations
From: "Huang, Sean Z"
Add several i915 trace logs for PXP calls for debugging or
performance measurement, including:
(1) PXP ioctl
(2) PXP teardown callbacks
To trun on this feature, we need to set
"CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS=y" in .config for compiling
the Linux kernel.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/i915_trace.h| 44
drivers/gpu/drm/i915/pxp/intel_pxp.c | 5
2 files changed, 49 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_trace.h
b/drivers/gpu/drm/i915/i915_trace.h
index a4addcc64978..36470e20dc61 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -1031,6 +1031,50 @@ DEFINE_EVENT(i915_context, i915_context_free,
TP_ARGS(ctx)
);
+TRACE_EVENT(i915_pxp_ops_ioctl,
+ TP_PROTO(struct drm_device *dev, void *data, struct drm_file *file,
u32 action),
+ TP_ARGS(dev, data, file, action),
+
+ TP_STRUCT__entry(
+__field(struct drm_device *, dev)
+__field(void *, data)
+__field(struct drm_file *, file)
+__field(u32, action)
+ ),
+
+ TP_fast_assign(
+ __entry->dev = dev;
+ __entry->data = data;
+ __entry->file = file;
+ __entry->action = action;
+ ),
+
+ TP_printk("dev=%p, data=%p, file=%p, action=%u",
+ __entry->dev, __entry->data, __entry->file,
__entry->action)
+);
+
+TRACE_EVENT(i915_pxp_teardown_required_callback,
+ TP_PROTO(bool global_state_attacked),
+ TP_ARGS(global_state_attacked),
+
+ TP_STRUCT__entry(__field(bool, global_state_attacked)),
+
+ TP_fast_assign(__entry->global_state_attacked =
global_state_attacked;),
+
+ TP_printk("global_state_attacked=%s",
yesno(__entry->global_state_attacked))
+);
+
+TRACE_EVENT(i915_pxp_global_terminate_complete_callback,
+ TP_PROTO(bool global_state_attacked),
+ TP_ARGS(global_state_attacked),
+
+ TP_STRUCT__entry(__field(bool, global_state_attacked)),
+
+ TP_fast_assign(__entry->global_state_attacked =
global_state_attacked;),
+
+ TP_printk("global_state_attacked=%s",
yesno(__entry->global_state_attacked))
+);
+
#endif /* _I915_TRACE_H_ */
/* This part must be outside protection */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 80e632b614f5..23955d7a3c3d 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -8,6 +8,7 @@
#include "intel_pxp_context.h"
#include "intel_pxp_sm.h"
#include "intel_pxp_tee.h"
+#include "i915_trace.h"
int i915_pxp_ops_ioctl(struct drm_device *dev, void *data, struct drm_file
*drmfile)
{
@@ -30,6 +31,7 @@ int i915_pxp_ops_ioctl(struct drm_device *dev, void *data,
struct drm_file *drmf
}
drm_dbg(&i915->drm, "i915 pxp ioctl call with action=[%d]\n",
pxp_info.action);
+ trace_i915_pxp_ops_ioctl(dev, data, drmfile, pxp_info.action);
mutex_lock(&i915->pxp.r0ctx->ctx_mutex);
@@ -219,6 +221,8 @@ static int intel_pxp_teardown_required_callback(struct
drm_i915_private *i915)
mutex_unlock(&i915->pxp.r0ctx->ctx_mutex);
+
trace_i915_pxp_teardown_required_callback(i915->pxp.r0ctx->global_state_attacked);
+
return ret;
}
@@ -243,6 +247,7 @@ static int
intel_pxp_global_terminate_complete_callback(struct drm_i915_private
end:
mutex_unlock(&i915->pxp.r0ctx->ctx_mutex);
+
trace_i915_pxp_global_terminate_complete_callback(i915->pxp.r0ctx->global_state_attacked);
drm_dbg(&i915->drm, "<<< %s ret=[%d]\n", __func__, ret);
return ret;
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 02/27] drm/i915/pxp: Enable PXP irq worker and callback stub
From: "Huang, Sean Z"
Create the irq worker that serves as callback handler, those
callback stubs should be called while the hardware key teardown
occurs.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 4 ++
drivers/gpu/drm/i915/i915_reg.h| 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 95 ++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 22 ++
4 files changed, 122 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index 257063a57101..d64013d0afb5 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -13,6 +13,7 @@
#include "intel_gt_irq.h"
#include "intel_uncore.h"
#include "intel_rps.h"
+#include "pxp/intel_pxp.h"
static void guc_irq_handler(struct intel_guc *guc, u16 iir)
{
@@ -106,6 +107,9 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8
instance,
if (instance == OTHER_GTPM_INSTANCE)
return gen11_rps_irq_handler(>->rps, iir);
+ if (instance == OTHER_KCR_INSTANCE)
+ return intel_pxp_irq_handler(gt, iir);
+
WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
instance, iir);
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7ea70b7ffcc6..faf6b06145fa 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7941,6 +7941,7 @@ enum {
/* irq instances for OTHER_CLASS */
#define OTHER_GUC_INSTANCE 0
#define OTHER_GTPM_INSTANCE1
+#define OTHER_KCR_INSTANCE 4
#define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index a469c55e3e54..d98bff4a0fde 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -6,15 +6,110 @@
#include "i915_drv.h"
#include "intel_pxp.h"
+static void intel_pxp_write_irq_mask_reg(struct drm_i915_private *i915, u32
mask)
+{
+ WARN_ON(INTEL_GEN(i915) < 11);
+
+ /* crypto mask is in bit31-16 (Engine1 Interrupt Mask) */
+ intel_uncore_write(&i915->uncore, GEN11_CRYPTO_RSVD_INTR_MASK, mask <<
16);
+}
+
+static void intel_pxp_unmask_irq(struct intel_gt *gt)
+{
+ lockdep_assert_held(>->irq_lock);
+
+ intel_pxp_write_irq_mask_reg(gt->i915, 0);
+}
+
+static void intel_pxp_mask_irq(struct intel_gt *gt, u32 mask)
+{
+ lockdep_assert_held(>->irq_lock);
+
+ intel_pxp_write_irq_mask_reg(gt->i915, mask);
+}
+
+static int intel_pxp_teardown_required_callback(struct drm_i915_private *i915)
+{
+ drm_dbg(&i915->drm, "%s was called\n", __func__);
+
+ return 0;
+}
+
+static int intel_pxp_global_terminate_complete_callback(struct
drm_i915_private *i915)
+{
+ drm_dbg(&i915->drm, ">>> %s\n", __func__);
+
+ return 0;
+}
+
+static void intel_pxp_irq_work(struct work_struct *work)
+{
+ struct intel_pxp *pxp_ptr = container_of(work, typeof(*pxp_ptr),
irq_work);
+ struct drm_i915_private *i915 = container_of(pxp_ptr, typeof(*i915),
pxp);
+ u32 events = 0;
+
+ spin_lock_irq(&i915->gt.irq_lock);
+ events = fetch_and_zero(&pxp_ptr->current_events);
+ spin_unlock_irq(&i915->gt.irq_lock);
+
+ drm_dbg(&i915->drm, "%s was called with events=[%d]\n", __func__,
events);
+
+ if (events & PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED ||
+ events & PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ)
+ intel_pxp_teardown_required_callback(i915);
+
+ if (events & PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE)
+ intel_pxp_global_terminate_complete_callback(i915);
+
+ spin_lock_irq(&i915->gt.irq_lock);
+ intel_pxp_unmask_irq(&i915->gt);
+ spin_unlock_irq(&i915->gt.irq_lock);
+}
+
int intel_pxp_init(struct drm_i915_private *i915)
{
int ret;
drm_info(&i915->drm, "i915_pxp_init\n");
+ INIT_WORK(&i915->pxp.irq_work, intel_pxp_irq_work);
+
+ i915->pxp.handled_irr = (PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED |
+PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ |
+PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE);
+
return ret;
}
void intel_pxp_uninit(struct drm_i915_private *i915)
{
}
+
+/**
+ * intel_pxp_irq_handler - Proxies KCR interrupts to PXP.
+ * @gt: valid GT instance
+ * @iir: GT interrupt vector associated with the interrupt
+ *
+ * Dispatches each vector element into an IRQ to PXP.
+ */
+void intel_pxp_irq_handler(struct intel_gt *gt, u16 iir)
+{
+ struct drm_i915_private *i915 = gt->i915;
+ const u32 events = iir & i915->pxp.handled_irr;
+
+ drm_dbg(&i915->drm, "%s was called with iir=[0x%04x]\n", __func__, iir);
+
+ lockdep_assert_held(>->irq_lock);
+
+ if (unlikely(!events)) {
+ drm_dbg(&i915->drm, "%s returned due to
[Intel-gfx] [PATCH 20/27] drm/i915/pxp: Create the arbitrary session after boot
From: "Huang, Sean Z"
Create the arbitrary session, with the fixed session id 0xf, after
system boot, for the case that application allocates the protected
buffer without establishing any protection session. Because the
hardware requires at least one alive session for protected buffer
creation. This arbitrary session needs to be re-created after
teardown or power event because hardware encryption key won't be
valid after such cases.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 50 +++-
drivers/gpu/drm/i915/pxp/intel_pxp.h | 2 +
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 33
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 6 +++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 34
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 6 +++
6 files changed, 130 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 1a6cad0502c5..80e632b614f5 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -140,6 +140,46 @@ int intel_pxp_close(struct drm_i915_private *i915, struct
drm_file *drmfile)
return ret;
}
+int intel_pxp_create_arb_session(struct drm_i915_private *i915)
+{
+ struct pxp_tag pxptag;
+ int ret;
+
+ drm_dbg(&i915->drm, ">>> %s\n", __func__);
+
+ lockdep_assert_held(&i915->pxp.r0ctx->ctx_mutex);
+
+ if (i915->pxp.r0ctx->flag_display_hm_surface_keys) {
+ drm_dbg(&i915->drm, "%s: arb session is alive so skipping the
creation\n",
+ __func__);
+ return 0;
+ }
+
+ ret = intel_pxp_sm_reserve_arb_session(i915, &pxptag.value);
+ if (ret) {
+ drm_dbg(&i915->drm, "Failed to reserve session\n");
+ goto end;
+ }
+
+ ret = intel_pxp_tee_cmd_create_arb_session(i915);
+ if (ret) {
+ drm_dbg(&i915->drm, "Failed to send tee cmd for arb session
creation\n");
+ goto end;
+ }
+
+ ret = pxp_sm_mark_protected_session_in_play(i915, ARB_SESSION_TYPE,
pxptag.session_id);
+ if (ret) {
+ drm_dbg(&i915->drm, "Failed to mark session status in play\n");
+ goto end;
+ }
+
+ i915->pxp.r0ctx->flag_display_hm_surface_keys = true;
+
+end:
+ drm_dbg(&i915->drm, "<<< %s ret=[%d]\n", __func__, ret);
+ return ret;
+}
+
static void intel_pxp_write_irq_mask_reg(struct drm_i915_private *i915, u32
mask)
{
WARN_ON(INTEL_GEN(i915) < 11);
@@ -190,9 +230,17 @@ static int
intel_pxp_global_terminate_complete_callback(struct drm_i915_private
mutex_lock(&i915->pxp.r0ctx->ctx_mutex);
- if (i915->pxp.r0ctx->global_state_attacked)
+ if (i915->pxp.r0ctx->global_state_attacked) {
i915->pxp.r0ctx->global_state_attacked = false;
+ /* Re-create the arb session after teardown handle complete */
+ ret = intel_pxp_create_arb_session(i915);
+ if (ret) {
+ drm_dbg(&i915->drm, "Failed to create arb session\n");
+ goto end;
+ }
+ }
+end:
mutex_unlock(&i915->pxp.r0ctx->ctx_mutex);
drm_dbg(&i915->drm, "<<< %s ret=[%d]\n", __func__, ret);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 2c16ed0b5c0b..c0119ccdab08 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -102,6 +102,8 @@ struct drm_i915_private;
int i915_pxp_ops_ioctl(struct drm_device *dev, void *data, struct drm_file
*drmfile);
int intel_pxp_close(struct drm_i915_private *i915, struct drm_file *drmfile);
+int intel_pxp_create_arb_session(struct drm_i915_private *i915);
+
void intel_pxp_irq_handler(struct intel_gt *gt, u16 iir);
int i915_pxp_teardown_required_callback(struct drm_i915_private *i915);
int i915_pxp_global_terminate_complete_callback(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index 71082938b9f0..55cdd402f704 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -673,6 +673,39 @@ int intel_pxp_sm_reserve_session(struct drm_i915_private
*i915, struct drm_file
return ret;
}
+int intel_pxp_sm_reserve_arb_session(struct drm_i915_private *i915, u32
*pxp_tag)
+{
+ int ret;
+
+ drm_dbg(&i915->drm, ">>> %s\n", __func__);
+
+ lockdep_assert_held(&i915->pxp.r0ctx->ctx_mutex);
+
+ if (!pxp_tag || !i915) {
+ ret = -EINVAL;
+ drm_dbg(&i915->drm, "Failed to %s, bad params\n", __func__);
+ goto end;
+ }
+
+ ret = sync_hw_sw_state(i915, ARB_SESSION_INDEX, ARB_SESSION_TYPE);
+ if (unlikely(ret))
+ goto end;
+
+ ret = create_new_session_entry(i915, NULL, 0,
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Avoid memory leak with more than 16 workarounds on a list
== Series Details == Series: drm/i915: Avoid memory leak with more than 16 workarounds on a list URL : https://patchwork.freedesktop.org/series/83806/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9326_full -> Patchwork_18898_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_18898_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18898_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_18898_full: ### IGT changes ### Possible regressions * igt@core_hotunplug@hotrebind-lateclose: - shard-snb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-snb4/igt@core_hotunp...@hotrebind-lateclose.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18898/shard-snb4/igt@core_hotunp...@hotrebind-lateclose.html Warnings * igt@i915_pm_rc6_residency@rc6-fence: - shard-iclb: [WARN][3] ([i915#1515]) -> [WARN][4] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-iclb4/igt@i915_pm_rc6_reside...@rc6-fence.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18898/shard-iclb4/igt@i915_pm_rc6_reside...@rc6-fence.html New tests - New tests have been introduced between CI_DRM_9326_full and Patchwork_18898_full: ### New CI tests (1) ### * boot: - Statuses : 200 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_18898_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_reloc@basic-many-active@rcs0: - shard-hsw: [PASS][5] -> [FAIL][6] ([i915#2389]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-hsw8/igt@gem_exec_reloc@basic-many-act...@rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18898/shard-hsw4/igt@gem_exec_reloc@basic-many-act...@rcs0.html * igt@gem_exec_whisper@basic-contexts-forked-all: - shard-glk: [PASS][7] -> [DMESG-WARN][8] ([i915#118] / [i915#95]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-glk8/igt@gem_exec_whis...@basic-contexts-forked-all.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18898/shard-glk3/igt@gem_exec_whis...@basic-contexts-forked-all.html * igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen: - shard-skl: [PASS][9] -> [FAIL][10] ([i915#54]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-skl7/igt@kms_cursor_...@pipe-a-cursor-64x64-onscreen.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18898/shard-skl9/igt@kms_cursor_...@pipe-a-cursor-64x64-onscreen.html * igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic: - shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-kbl3/igt@kms_cursor_leg...@flip-vs-cursor-crc-atomic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18898/shard-kbl4/igt@kms_cursor_leg...@flip-vs-cursor-crc-atomic.html * igt@kms_draw_crc@draw-method-xrgb-mmap-cpu-untiled: - shard-skl: [PASS][13] -> [FAIL][14] ([i915#177] / [i915#52] / [i915#54]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-skl10/igt@kms_draw_...@draw-method-xrgb-mmap-cpu-untiled.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18898/shard-skl5/igt@kms_draw_...@draw-method-xrgb-mmap-cpu-untiled.html * igt@kms_flip@2x-flip-vs-panning-vs-hang@ab-hdmi-a1-hdmi-a2: - shard-glk: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-glk1/igt@kms_flip@2x-flip-vs-panning-vs-h...@ab-hdmi-a1-hdmi-a2.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18898/shard-glk9/igt@kms_flip@2x-flip-vs-panning-vs-h...@ab-hdmi-a1-hdmi-a2.html * igt@kms_flip@2x-flip-vs-suspend-interruptible@bc-vga1-hdmi-a1: - shard-hsw: [PASS][17] -> [INCOMPLETE][18] ([i915#2055]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-hsw1/igt@kms_flip@2x-flip-vs-suspend-interrupti...@bc-vga1-hdmi-a1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18898/shard-hsw6/igt@kms_flip@2x-flip-vs-suspend-interrupti...@bc-vga1-hdmi-a1.html * igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1: - shard-skl: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +8 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-skl3/igt@kms_flip@flip-vs-blocking-wf-vbl...@a-edp1.html [20]: http
[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [PXP,CLEAN,v06,01/27] drm/i915/pxp: Introduce Intel PXP component
== Series Details == Series: series starting with [PXP,CLEAN,v06,01/27] drm/i915/pxp: Introduce Intel PXP component URL : https://patchwork.freedesktop.org/series/83843/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_context.h In file included from : ./drivers/gpu/drm/i915/pxp/intel_pxp_context.h:14:15: error: field ‘ctx_mutex’ has incomplete type struct mutex ctx_mutex; ^ ./drivers/gpu/drm/i915/pxp/intel_pxp_context.h:21:28: error: ‘MAX_TYPE0_SESSIONS’ undeclared here (not in a function) u32 type0_session_pxp_tag[MAX_TYPE0_SESSIONS]; ^~ ./drivers/gpu/drm/i915/pxp/intel_pxp_context.h:22:28: error: ‘MAX_TYPE1_SESSIONS’ undeclared here (not in a function) u32 type1_session_pxp_tag[MAX_TYPE1_SESSIONS]; ^~ ./drivers/gpu/drm/i915/pxp/intel_pxp_context.h:39:51: error: ‘struct drm_i915_private’ declared inside parameter list will not be visible outside of this definition or declaration [-Werror] struct pxp_context *intel_pxp_create_r0ctx(struct drm_i915_private *i915); ^~~~ ./drivers/gpu/drm/i915/pxp/intel_pxp_context.h:40:37: error: ‘struct drm_i915_private’ declared inside parameter list will not be visible outside of this definition or declaration [-Werror] void intel_pxp_destroy_r0ctx(struct drm_i915_private *i915); ^~~~ ./drivers/gpu/drm/i915/pxp/intel_pxp_context.h:42:32: error: ‘struct drm_i915_private’ declared inside parameter list will not be visible outside of this definition or declaration [-Werror] int intel_pxp_set_r3ctx(struct drm_i915_private *i915, u32 r3ctx); ^~~~ ./drivers/gpu/drm/i915/pxp/intel_pxp_context.h:43:42: error: ‘struct drm_i915_private’ declared inside parameter list will not be visible outside of this definition or declaration [-Werror] void intel_pxp_destroy_r3ctx_list(struct drm_i915_private *i915); ^~~~ cc1: all warnings being treated as errors drivers/gpu/drm/i915/Makefile:312: recipe for target 'drivers/gpu/drm/i915/pxp/intel_pxp_context.hdrtest' failed make[4]: *** [drivers/gpu/drm/i915/pxp/intel_pxp_context.hdrtest] Error 1 scripts/Makefile.build:500: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:500: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:500: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1799: recipe for target 'drivers' failed make: *** [drivers] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Big bigjoiner series
== Series Details ==
Series: drm/i915: Big bigjoiner series
URL : https://patchwork.freedesktop.org/series/83837/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9326 -> Patchwork_18904
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18904/index.html
New tests
-
New tests have been introduced between CI_DRM_9326 and Patchwork_18904:
### New CI tests (1) ###
* boot:
- Statuses : 1 fail(s) 37 pass(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_18904 that come from known issues:
### CI changes ###
Issues hit
* boot (NEW):
- {fi-tgl-dsi}: [PASS][1] -> [FAIL][2] ([i915#2448])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-tgl-dsi/boot.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18904/fi-tgl-dsi/boot.html
### IGT changes ###
Issues hit
* igt@core_hotunplug@unbind-rebind:
- fi-tgl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18904/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18904/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html
* igt@i915_selftest@live@gt_pm:
- fi-byt-j1900: [PASS][7] -> [DMESG-FAIL][8] ([i915#2420])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-byt-j1900/igt@i915_selftest@live@gt_pm.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18904/fi-byt-j1900/igt@i915_selftest@live@gt_pm.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-skl-6700k2: [PASS][9] -> [DMESG-WARN][10] ([i915#1982])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-skl-6700k2/igt@kms_chamel...@hdmi-crc-fast.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18904/fi-skl-6700k2/igt@kms_chamel...@hdmi-crc-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-snb-2520m: [PASS][11] -> [DMESG-WARN][12] ([i915#1982])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-snb-2520m/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18904/fi-snb-2520m/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- fi-icl-u2: [PASS][13] -> [DMESG-WARN][14] ([i915#1982])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-legacy.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18904/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-legacy.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-tgl-y: [PASS][15] -> [DMESG-WARN][16] ([i915#1982])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-tgl-y/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18904/fi-tgl-y/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
* igt@prime_vgem@basic-gtt:
- fi-tgl-y: [PASS][17] -> [DMESG-WARN][18] ([i915#402]) +2
similar issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-tgl-y/igt@prime_v...@basic-gtt.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18904/fi-tgl-y/igt@prime_v...@basic-gtt.html
Possible fixes
* igt@kms_chamelium@dp-crc-fast:
- fi-cml-u2: [FAIL][19] ([i915#1161] / [i915#262]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18904/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-byt-j1900: [DMESG-WARN][21] ([i915#1982]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18904/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2: [DMESG-WARN][23] ([i915#1982]) -> [PASS][24]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
[24]:
https
[Intel-gfx] [PXP CLEAN PATCH v06 18/27] drm/i915/pxp: Implement funcs to create the TEE channel
From: "Huang, Sean Z"
Currently ring3 driver sends the TEE commands directly to TEE, but
later, as our design, we would like to make ring3 sending the TEE
commands via the ring0 PXP ioctl action instead of TEE ioctl, so
we can centralize those protection operations at ring0 PXP.
Co-developed-by: Vitaly Lubart
Co-developed-by: Tomas Winkler
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 6 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 4 +
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 140 +++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 14 +++
include/drm/i915_component.h | 1 +
include/drm/i915_pxp_tee_interface.h | 45
8 files changed, 212 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
create mode 100644 include/drm/i915_pxp_tee_interface.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 6858392c1ef2..1f3e0b89ae42 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -259,6 +259,7 @@ i915-y += \
pxp/intel_pxp.o \
pxp/intel_pxp_context.o \
pxp/intel_pxp_sm.o \
+ pxp/intel_pxp_tee.o \
pxp/intel_pxp_pm.o
# Post-mortem debug and GPU hang state capture
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 830708414f92..73c77a4e8216 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -324,6 +324,7 @@ static int i915_driver_early_probe(struct drm_i915_private
*dev_priv)
mutex_init(&dev_priv->wm.wm_mutex);
mutex_init(&dev_priv->pps_mutex);
mutex_init(&dev_priv->hdcp_comp_mutex);
+ mutex_init(&dev_priv->pxp_tee_comp_mutex);
i915_memcpy_init_early(dev_priv);
intel_runtime_pm_init_early(&dev_priv->runtime_pm);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f34ed07a68ee..9ba6eada4f84 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1219,6 +1219,12 @@ struct drm_i915_private {
struct intel_pxp pxp;
+ struct i915_pxp_comp_master *pxp_tee_master;
+ bool pxp_tee_comp_added;
+
+ /* Mutex to protect the above pxp_tee component related values. */
+ struct mutex pxp_tee_comp_mutex;
+
I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
/*
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 75858c0842ba..2cbdc6fa7cf6 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -227,6 +227,8 @@ int intel_pxp_init(struct drm_i915_private *i915)
return ret;
}
+ intel_pxp_tee_component_init(i915);
+
INIT_WORK(&i915->pxp.irq_work, intel_pxp_irq_work);
i915->pxp.handled_irr = (PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED |
@@ -238,6 +240,8 @@ int intel_pxp_init(struct drm_i915_private *i915)
void intel_pxp_uninit(struct drm_i915_private *i915)
{
+ intel_pxp_tee_component_fini(i915);
+
intel_pxp_destroy_r0ctx(i915);
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
new file mode 100644
index ..5bf79ca45cea
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -0,0 +1,140 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+
+#include
+#include "i915_drv.h"
+#include "drm/i915_component.h"
+#include "intel_pxp.h"
+#include "intel_pxp_context.h"
+#include "intel_pxp_tee.h"
+
+static int intel_pxp_tee_io_message(struct drm_i915_private *i915,
+ void *msg_in, u32 msg_in_size,
+ void *msg_out, u32 *msg_out_size_ptr,
+ u32 msg_out_buf_size)
+{
+ int ret;
+ struct i915_pxp_comp_master *pxp_tee_master = i915->pxp_tee_master;
+
+ if (!pxp_tee_master || !msg_in || !msg_out || !msg_out_size_ptr) {
+ ret = -EINVAL;
+ drm_dbg(&i915->drm, "Failed to %s, invalid params\n", __func__);
+ goto end;
+ }
+
+ lockdep_assert_held(&i915->pxp_tee_comp_mutex);
+
+ if (drm_debug_enabled(DRM_UT_DRIVER))
+ print_hex_dump(KERN_DEBUG, "TEE input message binaries:",
+ DUMP_PREFIX_OFFSET, 4, 4, msg_in, msg_in_size,
true);
+
+ ret = pxp_tee_master->ops->send(pxp_tee_master->tee_dev, msg_in,
msg_in_size);
+ if (ret) {
+ ret = -EFAULT;
+ drm_dbg(&i915->drm, "Failed to send TEE message\n");
+ goto end;
+ }
+
+ ret = pxp_tee_master->ops->receive(pxp_tee_master->tee_dev, msg_out,
msg_out_buf_size);
+ if (re
[Intel-gfx] [PXP CLEAN PATCH v06 22/27] drm/i915/pxp: Expose session state for display protection flip
From: "Huang, Sean Z"
Implement the intel_pxp_gem_object_status() to allow ring0 i915
display querying the current PXP session state. In the design,
ring0 display should not perform protection flip on the protected
buffers if there is no PXP session alive.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 8
drivers/gpu/drm/i915/pxp/intel_pxp.h | 2 ++
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 23955d7a3c3d..082c1aaabaa8 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -341,3 +341,11 @@ void intel_pxp_irq_handler(struct intel_gt *gt, u16 iir)
end:
return;
}
+
+bool intel_pxp_gem_object_status(struct drm_i915_private *i915, u64
gem_object_metadata)
+{
+ if (i915->pxp.r0ctx && i915->pxp.r0ctx->flag_display_hm_surface_keys)
+ return true;
+ else
+ return false;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index c0119ccdab08..eb0e548ce434 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -111,4 +111,6 @@ int i915_pxp_global_terminate_complete_callback(struct
drm_i915_private *i915);
int intel_pxp_init(struct drm_i915_private *i915);
void intel_pxp_uninit(struct drm_i915_private *i915);
+bool intel_pxp_gem_object_status(struct drm_i915_private *i915, u64
gem_object_metadata);
+
#endif
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PXP CLEAN PATCH v06 11/27] drm/i915/pxp: Enable ioctl action to set session in play
From: "Huang, Sean Z"
With this ioctl action, ring3 driver can set the session in state
"session in play", after ring3 reserved the session slot/id from
ring3 PXP, and sent the TEE commands to activate the corresponding
hardware session. Session state "session in play" means this
session is ready for secure playback.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c| 4 ++
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 92 +
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 2 +
3 files changed, 98 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 0f684851ecb2..baa61a3a70ff 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -61,6 +61,10 @@ int i915_pxp_ops_ioctl(struct drm_device *dev, void *data,
struct drm_file *drmf
pxp_info.sm_status = ret;
ret = 0;
}
+ } else if (params->req_session_state ==
PXP_SM_REQ_SESSION_IN_PLAY) {
+ ret = pxp_sm_mark_protected_session_in_play(i915,
params->session_type,
+
params->pxp_tag);
+
} else {
ret = -EINVAL;
goto end;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index 62303dc197e2..eb77380367aa 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -49,6 +49,25 @@ static int pxp_reg_write(struct drm_i915_private *i915, u32
offset, u32 regval)
return err;
}
+static int pxp_get_session_index(struct drm_i915_private *i915, u32 pxp_tag,
+int *session_index_out, int *session_type_out)
+{
+ int ret;
+
+ if (!session_index_out || !session_type_out) {
+ ret = -EINVAL;
+ drm_dbg(&i915->drm, "Failed to %s, bad params\n", __func__);
+ goto end;
+ }
+
+ *session_type_out = (pxp_tag & SESSION_TYPE_MASK) ? SESSION_TYPE_TYPE1
: SESSION_TYPE_TYPE0;
+ *session_index_out = pxp_tag & SESSION_ID_MASK;
+
+ ret = 0;
+end:
+ return ret;
+}
+
static u8 pxp_get_session_id(int session_index, int session_type)
{
u8 session_id = session_index & SESSION_ID_MASK;
@@ -492,6 +511,79 @@ int intel_pxp_sm_reserve_session(struct drm_i915_private
*i915, struct drm_file
return ret;
}
+/**
+ * pxp_sm_mark_protected_session_in_play - To put an reserved protected
session to "in_play" state
+ * @i915: i915 device handle.
+ * @session_type: Type of the session to be updated. One of enum
pxp_session_types.
+ * @session_id: Session id identifier of the protected session.
+ *
+ * Return: status. 0 means update is successful.
+ */
+int pxp_sm_mark_protected_session_in_play(struct drm_i915_private *i915, int
session_type,
+ u32 session_id)
+{
+ int ret;
+ int session_index;
+ int session_type_in_id;
+ struct pxp_protected_session *current_session;
+
+ drm_dbg(&i915->drm, ">>> %s session_type=[%d] session_id=[0x%08x]\n",
__func__,
+ session_type, session_id);
+
+ ret = pxp_get_session_index(i915, session_id, &session_index,
&session_type_in_id);
+ if (ret) {
+ drm_dbg(&i915->drm, "Failed to pxp_get_session_index\n");
+ goto end;
+ }
+
+ if (session_type != session_type_in_id) {
+ ret = -EINVAL;
+ drm_dbg(&i915->drm, "Failed to session_type and
session_type_in_id don't match\n");
+ goto end;
+ }
+
+ lockdep_assert_held(&i915->pxp.r0ctx->ctx_mutex);
+
+ switch (session_type) {
+ case SESSION_TYPE_TYPE0:
+ list_for_each_entry(current_session,
&i915->pxp.r0ctx->active_pxp_type0_sessions, session_list) {
+ DRM_DEBUG("Traverse the active type0 list,
session_index=[%d]\n", current_session->session_index);
+ drm_dbg(&i915->drm, "Traverse the active type0 list,
session_index=[%d]\n", current_session->session_index);
+ if (current_session->session_index == session_index) {
+ current_session->session_is_in_play = true;
+ ret = 0;
+ goto end;
+ }
+ }
+
+ drm_dbg(&i915->drm, "Failed to %s couldn't find active type0
session\n", __func__);
+ ret = -EINVAL;
+ goto end;
+
+ case SESSION_TYPE_TYPE1:
+ list_for_each_entry(current_session,
&i915->pxp.r0ctx->active_pxp_type1_sessions, session_list) {
+ drm_dbg(&i915->drm, "Traverse the active type1 list,
session_index=[%d]\n", current_session->session_i
[Intel-gfx] [PXP CLEAN PATCH v06 23/27] mei: bus: enable pavp device.
From: Tomas Winkler
Enable protected audio video path client on mei client
bus.
Signed-off-by: Tomas Winkler
---
drivers/misc/mei/bus-fixup.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c
index 4e30fa98fe7d..042399b397c9 100644
--- a/drivers/misc/mei/bus-fixup.c
+++ b/drivers/misc/mei/bus-fixup.c
@@ -33,6 +33,9 @@ static const uuid_le mei_nfc_info_guid = MEI_UUID_NFC_INFO;
#define MEI_UUID_HDCP UUID_LE(0xB638AB7E, 0x94E2, 0x4EA2, \
0xA5, 0x52, 0xD1, 0xC5, 0x4B, 0x62, 0x7F, 0x04)
+#define MEI_UUID_PAVP UUID_LE(0xfbf6fcf1, 0x96cf, 0x4e2e, 0xA6, \
+ 0xa6, 0x1b, 0xab, 0x8c, 0xbe, 0x36, 0xb1)
+
#define MEI_UUID_ANY NULL_UUID_LE
/**
@@ -488,6 +491,7 @@ static struct mei_fixup {
MEI_FIXUP(MEI_UUID_MKHIF_FIX, mei_mkhi_fix),
MEI_FIXUP(MEI_UUID_HDCP, whitelist),
MEI_FIXUP(MEI_UUID_ANY, vt_support),
+ MEI_FIXUP(MEI_UUID_PAVP, whitelist),
};
/**
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PXP CLEAN PATCH v06 25/27] drm/i915/uapi: introduce drm_i915_gem_create_ext for TGL
From: Bommu Krishnaiah
Same old gem_create but with now with extensions support. This is needed
to support various upcoming usecases. For now we use the extensions
mechanism to support PAVP.
Signed-off-by: Bommu Krishnaiah
Cc: Joonas Lahtinen joonas.lahti...@linux.intel.com
Cc: Matthew Auld matthew.a...@intel.com
Cc: Telukuntla Sreedhar
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 42 -
include/uapi/drm/i915_drm.h | 47 +
3 files changed, 89 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 73c77a4e8216..a2b5b6f2723f 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1742,7 +1742,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop,
DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop,
DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
- DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl,
DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 58276694c848..41698a823737 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -53,6 +53,7 @@
#include "i915_drv.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
+#include "i915_user_extensions.h"
#include "intel_pm.h"
@@ -260,6 +261,35 @@ i915_gem_dumb_create(struct drm_file *file,
&args->size, &args->handle);
}
+struct create_ext {
+struct drm_i915_private *i915;
+};
+
+static int __create_setparam(struct drm_i915_gem_object_param *args,
+ struct create_ext
*ext_data)
+{
+ if (!(args->param & I915_OBJECT_PARAM)) {
+ DRM_DEBUG("Missing I915_OBJECT_PARAM namespace\n");
+ return -EINVAL;
+ }
+
+ return -EINVAL;
+}
+
+static int create_setparam(struct i915_user_extension __user *base, void *data)
+{
+ struct drm_i915_gem_create_ext_setparam ext;
+
+ if (copy_from_user(&ext, base, sizeof(ext)))
+ return -EFAULT;
+
+ return __create_setparam(&ext.param, data);
+}
+
+static const i915_user_extension_fn create_extensions[] = {
+ [I915_GEM_CREATE_EXT_SETPARAM] = create_setparam,
+};
+
/**
* Creates a new mm object and returns a handle to it.
* @dev: drm device pointer
@@ -271,10 +301,20 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
{
struct drm_i915_private *i915 = to_i915(dev);
- struct drm_i915_gem_create *args = data;
+ struct create_ext ext_data = { .i915 = i915 };
+ struct drm_i915_gem_create_ext *args = data;
+ int ret;
i915_gem_flush_free_objects(i915);
+ ret = i915_user_extensions(u64_to_user_ptr(args->extensions),
+ create_extensions,
+ ARRAY_SIZE(create_extensions),
+ &ext_data);
+ if (ret)
+ return ret;
+
+
return i915_gem_create(file,
intel_memory_region_by_type(i915,
INTEL_MEMORY_SYSTEM),
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 180f97fd91dc..97d4fefa7ad8 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -392,6 +392,7 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE +
DRM_I915_GEM_ENTERVT)
#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE +
DRM_I915_GEM_LEAVEVT)
#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
+#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext)
#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE +
DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE +
DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
#define DRM_IOCTL_I915_GEM_MMAPDRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
@@ -730,6 +731,27 @@ struct drm_i915_gem_create {
__u32 pad;
};
+struct drm_i915_gem_create_ext {
+ /**
+* Requested size for the object.
+*
+
[Intel-gfx] [PXP CLEAN PATCH v06 16/27] drm/i915/pxp: Termiante the session upon app crash
From: "Huang, Sean Z"
Ring0 PXP should terminate the hardware session and cleanup the
software state gracefully when the application has established
the protection session, but doesn't close the session correctly
due to some cases like application crash.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/i915_drv.c | 2 ++
drivers/gpu/drm/i915/pxp/intel_pxp.c| 15 +++
drivers/gpu/drm/i915/pxp/intel_pxp.h| 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 21 +
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 1 +
5 files changed, 40 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 43ea85b5f14b..e61ffce52e3e 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1028,6 +1028,8 @@ static void i915_driver_postclose(struct drm_device *dev,
struct drm_file *file)
/* Catch up with all the deferred frees from "this" client */
i915_gem_flush_free_objects(to_i915(dev));
+
+ intel_pxp_close(to_i915(dev), file);
}
static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 40728ef70e20..75858c0842ba 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -110,6 +110,21 @@ int i915_pxp_ops_ioctl(struct drm_device *dev, void *data,
struct drm_file *drmf
return ret;
}
+int intel_pxp_close(struct drm_i915_private *i915, struct drm_file *drmfile)
+{
+ int ret;
+
+ drm_dbg(&i915->drm, ">>> %s i915=[%p] drmfile=[%p] pid=[%d]\n",
__func__,
+ i915, drmfile, pid_nr(drmfile->pid));
+
+ mutex_lock(&i915->pxp.r0ctx->ctx_mutex);
+ ret = intel_pxp_sm_close(i915, drmfile);
+ mutex_unlock(&i915->pxp.r0ctx->ctx_mutex);
+
+ drm_dbg(&i915->drm, "<<< %s ret=[%d]\n", __func__, ret);
+ return ret;
+}
+
static void intel_pxp_write_irq_mask_reg(struct drm_i915_private *i915, u32
mask)
{
WARN_ON(INTEL_GEN(i915) < 11);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 8851c28a0e57..3d70b9bab79f 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -83,6 +83,7 @@ struct intel_gt;
struct drm_i915_private;
int i915_pxp_ops_ioctl(struct drm_device *dev, void *data, struct drm_file
*drmfile);
+int intel_pxp_close(struct drm_i915_private *i915, struct drm_file *drmfile);
void intel_pxp_irq_handler(struct intel_gt *gt, u16 iir);
int i915_pxp_teardown_required_callback(struct drm_i915_private *i915);
int i915_pxp_global_terminate_complete_callback(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index 37fe2e5af88d..71082938b9f0 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -1260,3 +1260,24 @@ bool intel_pxp_sm_is_any_type0_session_in_play(struct
drm_i915_private *i915, in
return false;
}
+
+int intel_pxp_sm_close(struct drm_i915_private *i915, struct drm_file *drmfile)
+{
+ struct pxp_protected_session *s, *n;
+ int ret = 0;
+
+ drm_dbg(&i915->drm, ">>> %s\n", __func__);
+
+ list_for_each_entry_safe(s, n, pxp_session_list(i915,
SESSION_TYPE_TYPE0), session_list) {
+ if (s->drmfile && s->drmfile == drmfile && s->pid ==
pid_nr(drmfile->pid)) {
+ ret = terminate_protected_session(i915, 0,
s->session_type, s->session_index, false);
+ if (ret) {
+ drm_dbg(&i915->drm, "Failed to
terminate_protected_session()\n");
+ return ret;
+ }
+ }
+ }
+
+ drm_dbg(&i915->drm, "<<< %s ret=[%d]\n", __func__, ret);
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
index 955182a90bfe..b968a3169133 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
@@ -114,5 +114,6 @@ int pxp_sm_set_kcr_init_reg(struct drm_i915_private *i915);
u32 intel_pxp_get_pxp_tag(struct drm_i915_private *i915, int session_idx,
int session_type, u32 *session_is_alive);
bool intel_pxp_sm_is_any_type0_session_in_play(struct drm_i915_private *i915,
int protection_mode);
+int intel_pxp_sm_close(struct drm_i915_private *i915, struct drm_file
*drmfile);
#endif /* __INTEL_PXP_SM_H__ */
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PXP CLEAN PATCH v06 24/27] mei: pxp: export pavp client to me client bus
From: Vitaly Lubart
Export PAVP client to work with i915_cp driver,
for binding it uses kernel component framework.
Signed-off-by: Vitaly Lubart
Signed-off-by: Tomas Winkler
---
drivers/misc/mei/Kconfig | 2 +
drivers/misc/mei/Makefile | 1 +
drivers/misc/mei/pxp/Kconfig | 13 ++
drivers/misc/mei/pxp/Makefile | 7 +
drivers/misc/mei/pxp/mei_pxp.c | 230 +
drivers/misc/mei/pxp/mei_pxp.h | 18 +++
6 files changed, 271 insertions(+)
create mode 100644 drivers/misc/mei/pxp/Kconfig
create mode 100644 drivers/misc/mei/pxp/Makefile
create mode 100644 drivers/misc/mei/pxp/mei_pxp.c
create mode 100644 drivers/misc/mei/pxp/mei_pxp.h
diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig
index c06581ffa7bd..36884b0a6395 100644
--- a/drivers/misc/mei/Kconfig
+++ b/drivers/misc/mei/Kconfig
@@ -57,3 +57,5 @@ config INTEL_MEI_VIRTIO
device over virtio.
source "drivers/misc/mei/hdcp/Kconfig"
+source "drivers/misc/mei/pxp/Kconfig"
+
diff --git a/drivers/misc/mei/Makefile b/drivers/misc/mei/Makefile
index 52aefaab5c1b..cab19c96ba7a 100644
--- a/drivers/misc/mei/Makefile
+++ b/drivers/misc/mei/Makefile
@@ -29,3 +29,4 @@ mei-$(CONFIG_EVENT_TRACING) += mei-trace.o
CFLAGS_mei-trace.o = -I$(src)
obj-$(CONFIG_INTEL_MEI_HDCP) += hdcp/
+obj-$(CONFIG_INTEL_MEI_PXP) += pxp/
diff --git a/drivers/misc/mei/pxp/Kconfig b/drivers/misc/mei/pxp/Kconfig
new file mode 100644
index ..4029b96afc04
--- /dev/null
+++ b/drivers/misc/mei/pxp/Kconfig
@@ -0,0 +1,13 @@
+
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
+#
+config INTEL_MEI_PXP
+ tristate "Intel PXP services of ME Interface"
+ select INTEL_MEI_ME
+ depends on DRM_I915
+ help
+ MEI Support for PXP Services on Intel platforms.
+
+ Enables the ME FW services required for PXP support through
+ I915 display driver of Intel.
diff --git a/drivers/misc/mei/pxp/Makefile b/drivers/misc/mei/pxp/Makefile
new file mode 100644
index ..0329950d5794
--- /dev/null
+++ b/drivers/misc/mei/pxp/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
+#
+# Makefile - PXP client driver for Intel MEI Bus Driver.
+
+obj-$(CONFIG_INTEL_MEI_PXP) += mei_pxp.o
diff --git a/drivers/misc/mei/pxp/mei_pxp.c b/drivers/misc/mei/pxp/mei_pxp.c
new file mode 100644
index ..5bd61fe445e3
--- /dev/null
+++ b/drivers/misc/mei/pxp/mei_pxp.c
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+/**
+ * DOC: MEI_PXP Client Driver
+ *
+ * The mei_pxp driver acts as a translation layer between PXP
+ * protocol implementer (I915) and ME FW by translating PXP
+ * negotiation messages to ME FW command payloads and vice versa.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "mei_pxp.h"
+
+/**
+ * mei_pxp_send_message() - Sends a PXP message to ME FW.
+ * @dev: device corresponding to the mei_cl_device
+ * @message: a message buffer to send
+ * @size: size of the message
+ * Return: 0 on Success, <0 on Failure
+ */
+static int
+mei_pxp_send_message(struct device *dev, const void *message, size_t size)
+{
+ struct mei_cl_device *cldev;
+ ssize_t byte;
+
+ if (!dev || !message)
+ return -EINVAL;
+
+ cldev = to_mei_cl_device(dev);
+
+ /* temporary drop const qualifier till the API is fixed */
+ byte = mei_cldev_send(cldev, (u8 *)message, size);
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte);
+ return byte;
+ }
+
+ return 0;
+}
+
+/**
+ * mei_pxp_receive_message() - Receives a PXP message from ME FW.
+ * @dev: device corresponding to the mei_cl_device
+ * @buffer: a message buffer to contain the received message
+ * @size: size of the buffer
+ * Return: bytes sent on Success, <0 on Failure
+ */
+static int
+mei_pxp_receive_message(struct device *dev, void *buffer, size_t size)
+{
+ struct mei_cl_device *cldev;
+ ssize_t byte;
+
+ if (!dev || !buffer)
+ return -EINVAL;
+
+ cldev = to_mei_cl_device(dev);
+
+ byte = mei_cldev_recv(cldev, buffer, size);
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte);
+ return byte;
+ }
+
+ return byte;
+}
+
+static const struct i915_pxp_component_ops mei_pxp_ops = {
+ .owner = THIS_MODULE,
+ .send = mei_pxp_send_message,
+ .receive = mei_pxp_receive_message,
+};
+
+static int mei_component_master_bind(struct device *dev)
+{
+ struct mei_cl_device *cldev = to_mei_cl_device(dev);
+ struct i915_pxp_comp_master *comp_master = mei_cldev_get_drvdata(cldev);
+ int ret;
+
+ dev_dbg(dev, "%s\n", __func__);
+ comp_master->ops = &mei_pxp_ops;
+
[Intel-gfx] [PXP CLEAN PATCH v06 27/27] drm/i915/pxp: Add plane decryption support
From: Anshuman Gupta
Add support to enable/disable PLANE_SURF Decryption Request bit.
It requires only to enable plane decryption support when following
condition met.
1. PAVP session is enabled.
2. Buffer object is protected.
v2:
- Rebased to libva_cp-drm-tip_tgl_cp tree.
- Used gen fb obj user_flags instead gem_object_metadata. [Krishna]
Cc: Bommu Krishnaiah
Cc: Huang, Sean Z
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_sprite.c | 21 ++---
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index a3ab44694118..12c549beb05f 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -39,6 +39,8 @@
#include
#include
+#include "pxp/intel_pxp.h"
+
#include "i915_drv.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
@@ -752,6 +754,11 @@ icl_program_input_csc(struct intel_plane *plane,
PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
}
+static bool intel_fb_obj_protected(const struct drm_i915_gem_object *obj)
+{
+ return obj->user_flags & I915_BO_PROTECTED ? true : false;
+}
+
static void
skl_plane_async_flip(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
@@ -788,6 +795,7 @@ skl_program_plane(struct intel_plane *plane,
u32 surf_addr = plane_state->color_plane[color_plane].offset;
u32 stride = skl_plane_stride(plane_state, color_plane);
const struct drm_framebuffer *fb = plane_state->hw.fb;
+ const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
int aux_plane = intel_main_to_aux_plane(fb, color_plane);
int crtc_x = plane_state->uapi.dst.x1;
int crtc_y = plane_state->uapi.dst.y1;
@@ -798,7 +806,7 @@ skl_program_plane(struct intel_plane *plane,
u8 alpha = plane_state->hw.alpha >> 8;
u32 plane_color_ctl = 0, aux_dist = 0;
unsigned long irqflags;
- u32 keymsk, keymax;
+ u32 keymsk, keymax, plane_surf;
u32 plane_ctl = plane_state->ctl;
plane_ctl |= skl_plane_ctl_crtc(crtc_state);
@@ -874,8 +882,15 @@ skl_program_plane(struct intel_plane *plane,
* the control register just before the surface register.
*/
intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
- intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
- intel_plane_ggtt_offset(plane_state) + surf_addr);
+ plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
+
+ if (intel_pxp_gem_object_status(dev_priv, obj->user_flags) &&
+ intel_fb_obj_protected(obj))
+ plane_surf |= PLANE_SURF_DECRYPTION_ENABLED;
+ else
+ plane_surf &= ~PLANE_SURF_DECRYPTION_ENABLED;
+
+ intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf);
if (plane_state->scaler_id >= 0)
skl_program_scaler(plane, crtc_state, plane_state);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5c51c9df8b28..0ac7678cd6ba 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7206,6 +7206,7 @@ enum {
#define _PLANE_SURF_3(pipe)_PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
#define PLANE_SURF(pipe, plane)\
_MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
+#define PLANE_SURF_DECRYPTION_ENABLEDREG_BIT(2)
#define _PLANE_OFFSET_1_B 0x711a4
#define _PLANE_OFFSET_2_B 0x712a4
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PXP CLEAN PATCH v06 17/27] drm/i915/pxp: Enable PXP power management
From: "Huang, Sean Z"
During the power event S3+ sleep/resume, hardware will lose all the
encryption keys for every hardware session, even though the
software session state was marked as alive after resume. So to
handle such case, ring0 PXP should terminate all the hardware
sessions and cleanup all the software states after the power cycle.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/i915_drv.c | 8 +++
drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 83 +
drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 14 +
4 files changed, 107 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 81432a9f44d6..6858392c1ef2 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -258,7 +258,8 @@ i915-y += i915_perf.o
i915-y += \
pxp/intel_pxp.o \
pxp/intel_pxp_context.o \
- pxp/intel_pxp_sm.o
+ pxp/intel_pxp_sm.o \
+ pxp/intel_pxp_pm.o
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e61ffce52e3e..830708414f92 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -68,6 +68,8 @@
#include "gt/intel_gt_pm.h"
#include "gt/intel_rc6.h"
+#include "pxp/intel_pxp_pm.h"
+
#include "i915_debugfs.h"
#include "i915_drv.h"
#include "i915_ioc32.h"
@@ -1094,6 +1096,8 @@ static int i915_drm_prepare(struct drm_device *dev)
*/
i915_gem_suspend(i915);
+ intel_pxp_pm_prepare_suspend(i915);
+
return 0;
}
@@ -1277,6 +1281,8 @@ static int i915_drm_resume(struct drm_device *dev)
intel_power_domains_enable(dev_priv);
+ intel_pxp_pm_resume(dev_priv);
+
enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
return 0;
@@ -1348,6 +1354,8 @@ static int i915_drm_resume_early(struct drm_device *dev)
intel_power_domains_resume(dev_priv);
+ intel_pxp_pm_resume_early(dev_priv);
+
enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
return ret;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
new file mode 100644
index ..18d33efca9d9
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+
+#include "i915_drv.h"
+#include "intel_pxp_context.h"
+#include "intel_pxp_sm.h"
+#include "intel_pxp_pm.h"
+
+void intel_pxp_pm_prepare_suspend(struct drm_i915_private *i915)
+{
+ drm_dbg(&i915->drm, ">>> %s\n", __func__);
+
+ if (!i915->pxp.r0ctx)
+ return;
+
+ mutex_lock(&i915->pxp.r0ctx->ctx_mutex);
+
+ /* Disable PXP-IOCTLs */
+ i915->pxp.r0ctx->global_state_in_suspend = true;
+
+ mutex_unlock(&i915->pxp.r0ctx->ctx_mutex);
+
+ drm_dbg(&i915->drm, "<<< %s\n", __func__);
+}
+
+void intel_pxp_pm_resume_early(struct drm_i915_private *i915)
+{
+ drm_dbg(&i915->drm, ">>> %s\n", __func__);
+
+ if (!i915->pxp.r0ctx)
+ return;
+
+ mutex_lock(&i915->pxp.r0ctx->ctx_mutex);
+
+ if (i915->pxp.r0ctx->global_state_in_suspend) {
+ /* reset the attacked flag even there was a pending */
+ i915->pxp.r0ctx->global_state_attacked = false;
+
+ i915->pxp.r0ctx->flag_display_hm_surface_keys = false;
+ }
+
+ mutex_unlock(&i915->pxp.r0ctx->ctx_mutex);
+ drm_dbg(&i915->drm, "<<< %s\n", __func__);
+}
+
+int intel_pxp_pm_resume(struct drm_i915_private *i915)
+{
+ int ret = 0;
+
+ drm_dbg(&i915->drm, ">>> %s\n", __func__);
+
+ if (!i915->pxp.r0ctx)
+ return 0;
+
+ mutex_lock(&i915->pxp.r0ctx->ctx_mutex);
+
+ /* Re-enable PXP-IOCTLs */
+ if (i915->pxp.r0ctx->global_state_in_suspend) {
+ intel_pxp_destroy_r3ctx_list(i915);
+
+ ret = intel_pxp_sm_terminate_all_active_sessions(i915,
SESSION_TYPE_TYPE0);
+ if (ret) {
+ drm_dbg(&i915->drm, "Failed to
intel_pxp_sm_terminate_all_active_sessions with type0\n");
+ goto end;
+ }
+
+ ret = intel_pxp_sm_terminate_all_active_sessions(i915,
SESSION_TYPE_TYPE1);
+ if (ret) {
+ drm_dbg(&i915->drm, "Failed to
intel_pxp_sm_terminate_all_active_sessions with type1\n");
+ goto end;
+ }
+
+ i915->pxp.r0ctx->global_state_in_suspend = false;
+ }
+
+end:
+ mutex_unlock(&i915->pxp.r0ctx->ctx_mutex);
+ drm_dbg(&i915->drm, "<<< %s ret=[%d]\n", __func__, ret);
+
+ return ret;
+}
diff
[Intel-gfx] [PXP CLEAN PATCH v06 12/27] drm/i915/pxp: Func to send hardware session termination
From: "Huang, Sean Z"
Implement the functions to allow ring0 PXP to send a GPU command
in order to terminate the hardware session, so hardware can
recycle this session slot for the next usage.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 309
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 16 ++
2 files changed, 325 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index eb77380367aa..0e1ce75f9ccd 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -3,13 +3,175 @@
* Copyright(c) 2020, Intel Corporation. All rights reserved.
*/
+#include "gt/intel_gpu_commands.h"
+#include "gt/intel_gt.h"
#include "gt/intel_context.h"
+#include "gt/intel_gt_buffer_pool.h"
#include "gt/intel_engine_pm.h"
#include "intel_pxp.h"
#include "intel_pxp_sm.h"
#include "intel_pxp_context.h"
+static struct i915_vma *pxp_get_batch(struct drm_i915_private *i915,
+ struct intel_context *ce,
+ struct intel_gt_buffer_pool_node *pool,
+ u32 *cmd_buf, int cmd_size_in_dw)
+{
+ struct i915_vma *batch = ERR_PTR(-EINVAL);
+ u32 *cmd;
+
+ drm_dbg(&i915->drm, ">>> %s cmd_buf=[%p] cmd_size_in_dw=[%d]\n",
__func__, cmd_buf, cmd_size_in_dw);
+
+ if (!ce || !ce->engine || !cmd_buf) {
+ drm_dbg(&i915->drm, "Failed to %s due to nullptr\n", __func__);
+ goto end;
+ }
+
+ if (cmd_size_in_dw * 4 > PAGE_SIZE) {
+ drm_dbg(&i915->drm, "Failed to %s, invalid
cmd_size_id_dw=[%d]\n",
+ __func__, cmd_size_in_dw);
+ goto end;
+ }
+
+ cmd = i915_gem_object_pin_map(pool->obj, I915_MAP_FORCE_WC);
+ if (IS_ERR(cmd)) {
+ drm_dbg(&i915->drm, "Failed to i915_gem_object_pin_map()\n ");
+ goto end;
+ }
+
+ memcpy(cmd, cmd_buf, cmd_size_in_dw * 4);
+
+ if (drm_debug_enabled(DRM_UT_DRIVER)) {
+ print_hex_dump(KERN_DEBUG, "cmd binaries:",
+ DUMP_PREFIX_OFFSET, 4, 4, cmd, cmd_size_in_dw *
4, true);
+ }
+
+ i915_gem_object_unpin_map(pool->obj);
+
+ batch = i915_vma_instance(pool->obj, ce->vm, NULL);
+ if (IS_ERR(batch)) {
+ drm_dbg(&i915->drm, "Failed to i915_vma_instance()\n ");
+ goto end;
+ }
+
+end:
+ drm_dbg(&i915->drm, "<<< %s: batch=[%p]\n", __func__, batch);
+ return batch;
+}
+
+static int pxp_submit_cmd(struct drm_i915_private *i915, u32 *cmd, int
cmd_size_in_dw)
+{
+ int err = -EINVAL;
+ struct i915_vma *batch;
+ struct i915_request *rq;
+ struct intel_context *ce = NULL;
+ bool is_engine_pm_get = false;
+ bool is_batch_vma_pin = false;
+ bool is_skip_req_on_err = false;
+ bool is_engine_get_pool = false;
+ struct intel_gt_buffer_pool_node *pool = NULL;
+ struct intel_gt *gt = NULL;
+
+ drm_dbg(&i915->drm, ">>> %s: cmd=[%p] cmd_size_in_dw=[%d]\n",
+ __func__, cmd, cmd_size_in_dw);
+
+ if (!i915 || !HAS_ENGINE(&i915->gt, VCS0) ||
+ !i915->gt.engine[VCS0]->kernel_context) {
+ err = -EINVAL;
+ drm_dbg(&i915->drm, "Failed to %s bad params\n", __func__);
+ goto end;
+ }
+
+ if (!cmd || (cmd_size_in_dw * 4) > PAGE_SIZE) {
+ err = -EINVAL;
+ drm_dbg(&i915->drm, "Failed to %s bad params\n", __func__);
+ goto end;
+ }
+
+ gt = &i915->gt;
+ ce = i915->gt.engine[VCS0]->kernel_context;
+
+ intel_engine_pm_get(ce->engine);
+ is_engine_pm_get = true;
+
+ pool = intel_gt_get_buffer_pool(gt, PAGE_SIZE);
+ if (IS_ERR(pool)) {
+ drm_dbg(&i915->drm, "Failed to intel_engine_get_pool()\n");
+ goto end;
+ }
+ is_engine_get_pool = true;
+
+ batch = pxp_get_batch(i915, ce, pool, cmd, cmd_size_in_dw);
+ if (IS_ERR(batch)) {
+ drm_dbg(&i915->drm, "Failed to pxp_get_batch()\n");
+ goto end;
+ }
+
+ err = i915_vma_pin(batch, 0, 0, PIN_USER);
+ if (err) {
+ drm_dbg(&i915->drm, "Failed to i915_vma_pin()\n");
+ goto end;
+ }
+ is_batch_vma_pin = true;
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq)) {
+ drm_dbg(&i915->drm, "Failed to
intel_context_create_request()\n");
+ goto end;
+ }
+ is_skip_req_on_err = true;
+
+ err = intel_gt_buffer_pool_mark_active(pool, rq);
+ if (err) {
+ drm_dbg(&i915->drm, "Failed to
intel_engine_pool_mark_active()\n");
+ goto end;
+ }
+
+ i915_vma_lock(batch);
+ err = i915_request_await_object(rq, batch->obj
[Intel-gfx] [PXP CLEAN PATCH v06 01/27] drm/i915/pxp: Introduce Intel PXP component
From: "Huang, Sean Z"
PXP (Protected Xe Path) is an i915 componment, that
helps ring3 to establish the hardware protected session and
manage the status of each alive software session, as well as
the life cycle of each session.
By design PXP will expose ioctl so allow ring3 to create, set,
and destroy each session. It will also provide the communication
chanel to TEE (Trusted Execution Environment) for the protected
hardware session creation.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile| 4
drivers/gpu/drm/i915/i915_drv.c | 4
drivers/gpu/drm/i915/i915_drv.h | 4
drivers/gpu/drm/i915/pxp/intel_pxp.c | 20
drivers/gpu/drm/i915/pxp/intel_pxp.h | 22 ++
include/uapi/drm/i915_drm.h | 5 +
6 files changed, 59 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index e5574e506a5c..8274fea96009 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -254,6 +254,10 @@ i915-y += \
i915-y += i915_perf.o
+# Protected execution platform (PXP) support
+i915-y += \
+ pxp/intel_pxp.o
+
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
i915-$(CONFIG_DRM_I915_SELFTEST) += \
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index f2389ba49c69..c8b9c42fcbd6 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -889,6 +889,8 @@ int i915_driver_probe(struct pci_dev *pdev, const struct
pci_device_id *ent)
if (ret)
goto out_cleanup_gem;
+ intel_pxp_init(i915);
+
i915_driver_register(i915);
enable_rpm_wakeref_asserts(&i915->runtime_pm);
@@ -938,6 +940,8 @@ void i915_driver_remove(struct drm_i915_private *i915)
/* Flush any external code that still may be under the RCU lock */
synchronize_rcu();
+ intel_pxp_uninit(i915);
+
i915_gem_suspend(i915);
drm_atomic_helper_shutdown(&i915->drm);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 15be8debae54..f34ed07a68ee 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -105,6 +105,8 @@
#include "intel_region_lmem.h"
+#include "pxp/intel_pxp.h"
+
/* General customization:
*/
@@ -1215,6 +1217,8 @@ struct drm_i915_private {
/* Mutex to protect the above hdcp component related values. */
struct mutex hdcp_comp_mutex;
+ struct intel_pxp pxp;
+
I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
/*
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
new file mode 100644
index ..a469c55e3e54
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+
+#include "i915_drv.h"
+#include "intel_pxp.h"
+
+int intel_pxp_init(struct drm_i915_private *i915)
+{
+ int ret;
+
+ drm_info(&i915->drm, "i915_pxp_init\n");
+
+ return ret;
+}
+
+void intel_pxp_uninit(struct drm_i915_private *i915)
+{
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
new file mode 100644
index ..578f1126bada
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_H__
+#define __INTEL_PXP_H__
+
+#include
+
+struct pxp_context;
+
+struct intel_pxp {
+ struct pxp_context *r0ctx;
+};
+
+struct drm_i915_private;
+
+int intel_pxp_init(struct drm_i915_private *i915);
+void intel_pxp_uninit(struct drm_i915_private *i915);
+
+#endif
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index fa1f3d62f9a6..dc101264176b 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1898,6 +1898,11 @@ struct drm_i915_gem_vm_control {
__u32 vm_id;
};
+struct drm_i915_pxp_ops {
+ __u64 pxp_info_ptr;
+ __u32 pxp_info_size;
+};
+
struct drm_i915_reg_read {
/*
* Register offset.
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PXP CLEAN PATCH v06 19/27] drm/i915/pxp: Enable ioctl action to send TEE commands
From: "Huang, Sean Z"
Enable the ioctl action to allow ring3 driver sends TEE commands
via ring0 PXP ioctl, instead of TEE iotcl. So we can centralize
those protection operations at ring0 PXP.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 15 ++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 18 +++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 65
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 5 ++
4 files changed, 103 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 2cbdc6fa7cf6..1a6cad0502c5 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -7,6 +7,7 @@
#include "intel_pxp.h"
#include "intel_pxp_context.h"
#include "intel_pxp_sm.h"
+#include "intel_pxp_tee.h"
int i915_pxp_ops_ioctl(struct drm_device *dev, void *data, struct drm_file
*drmfile)
{
@@ -85,6 +86,20 @@ int i915_pxp_ops_ioctl(struct drm_device *dev, void *data,
struct drm_file *drmf
ret = pxp_sm_ioctl_query_pxp_tag(i915,
¶ms->session_is_alive, ¶ms->pxp_tag);
break;
}
+ case PXP_ACTION_TEE_IO_MESSAGE:
+ {
+ struct pxp_tee_io_message_params *params =
&pxp_info.tee_io_message;
+
+ ret = pxp_tee_ioctl_io_message(i915,
+ params->msg_in,
params->msg_in_size,
+ params->msg_out,
¶ms->msg_out_size,
+ params->msg_out_buf_size);
+ if (ret) {
+ drm_dbg(&i915->drm, "Failed to send TEE IO message\n");
+ ret = -EFAULT;
+ }
+ break;
+ }
case PXP_ACTION_SET_R3_CONTEXT:
{
ret = intel_pxp_set_r3ctx(i915, pxp_info.set_r3ctx);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 3d70b9bab79f..2c16ed0b5c0b 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -33,6 +33,7 @@ enum pxp_sm_session_req {
enum pxp_ioctl_action {
PXP_ACTION_QUERY_PXP_TAG = 0,
PXP_ACTION_SET_SESSION_STATUS = 1,
+ PXP_ACTION_TEE_IO_MESSAGE = 4,
PXP_ACTION_SET_R3_CONTEXT = 5,
};
@@ -59,12 +60,29 @@ struct pxp_sm_set_session_status_params {
u32 req_session_state;
};
+/**
+ * struct pxp_tee_io_message_params - Params to send/receive message to/from
TEE.
+ */
+struct pxp_tee_io_message_params {
+ /** @msg_in: in - message input from UMD */
+ u8 __user *msg_in;
+ /** @msg_in_size: in - message input size from UMD */
+ u32 msg_in_size;
+ /** @msg_out: in - message output buffer from UMD */
+ u8 __user *msg_out;
+ /** @msg_out_size: out- message output size from TEE */
+ u32 msg_out_size;
+ /** @msg_out_buf_size: in - message output buffer size from UMD */
+ u32 msg_out_buf_size;
+};
+
struct pxp_info {
u32 action;
u32 sm_status;
union {
struct pxp_sm_query_pxp_tag query_pxp_tag;
struct pxp_sm_set_session_status_params set_session_status;
+ struct pxp_tee_io_message_paramstee_io_message;
u32 set_r3ctx;
};
} __packed;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
index 5bf79ca45cea..7e10b7ac584f 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -60,6 +60,71 @@ static int intel_pxp_tee_io_message(struct drm_i915_private
*i915,
return ret;
}
+int pxp_tee_ioctl_io_message(struct drm_i915_private *i915,
+void __user *msg_in_user_ptr, u32 msg_in_size,
+void __user *msg_out_user_ptr, u32
*msg_out_size_ptr,
+u32 msg_out_buf_size)
+{
+ int ret;
+ void *msg_in = NULL;
+ void *msg_out = NULL;
+
+ drm_dbg(&i915->drm, ">>> %s\n", __func__);
+
+ if (!msg_in_user_ptr || !msg_out_user_ptr || msg_out_buf_size == 0 ||
+ msg_in_size == 0 || !msg_out_size_ptr) {
+ ret = -EINVAL;
+ drm_dbg(&i915->drm, "Failed to %s, invalid params\n", __func__);
+ goto end;
+ }
+
+ msg_in = kzalloc(msg_in_size, GFP_KERNEL);
+ if (!msg_in) {
+ ret = -ENOMEM;
+ drm_dbg(&i915->drm, "Failed to kzalloc\n");
+ goto end;
+ }
+
+ msg_out = kzalloc(msg_out_buf_size, GFP_KERNEL);
+ if (!msg_out) {
+ ret = -ENOMEM;
+ drm_dbg(&i915->drm, "Failed to kzalloc\n");
+ goto end;
+ }
+
+ if (copy_from_user(msg_in, msg_in_user_ptr, msg_in_size) != 0) {
+ ret = -EFAULT;
+ drm_dbg(&i915->drm, "Failed to copy_f
[Intel-gfx] [PXP CLEAN PATCH v06 06/27] drm/i915: Rename the whitelist to allowlist
From: "Huang, Sean Z"
Rename the whitelist to allowlist as suggested
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/intel_uncore.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 1c14a07eba7d..c9ef0025c60e 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1989,12 +1989,12 @@ void intel_uncore_fini_mmio(struct intel_uncore *uncore)
uncore_mmio_cleanup(uncore);
}
-static const struct reg_whitelist {
+static const struct reg_allowlist {
i915_reg_t offset_ldw;
i915_reg_t offset_udw;
u16 gen_mask;
u8 size;
-} reg_read_whitelist[] = { {
+} reg_read_allowlist[] = { {
.offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
.offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
.gen_mask = INTEL_GEN_MASK(4, 12),
@@ -2007,14 +2007,14 @@ int i915_reg_read_ioctl(struct drm_device *dev,
struct drm_i915_private *i915 = to_i915(dev);
struct intel_uncore *uncore = &i915->uncore;
struct drm_i915_reg_read *reg = data;
- struct reg_whitelist const *entry;
+ struct reg_allowlist const *entry;
intel_wakeref_t wakeref;
unsigned int flags;
int remain;
int ret = 0;
- entry = reg_read_whitelist;
- remain = ARRAY_SIZE(reg_read_whitelist);
+ entry = reg_read_allowlist;
+ remain = ARRAY_SIZE(reg_read_allowlist);
while (remain) {
u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw);
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PXP CLEAN PATCH v06 09/27] drm/i915/pxp: Implement funcs to get/set PXP tag
From: "Huang, Sean Z"
Implement the functions to get/set the PXP tag, which is 32-bit
bitwise value containing the hardware session info, such as its
session id, protection mode or whether it's enabled.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 105
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 18
2 files changed, 123 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index 3dd5a9e3926b..fd5d10e71a27 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -49,6 +49,16 @@ static int pxp_reg_write(struct drm_i915_private *i915, u32
offset, u32 regval)
return err;
}
+static u8 pxp_get_session_id(int session_index, int session_type)
+{
+ u8 session_id = session_index & SESSION_ID_MASK;
+
+ if (session_type == SESSION_TYPE_TYPE1)
+ session_id |= SESSION_TYPE_MASK;
+
+ return session_id;
+}
+
/**
* is_sw_session_active - Check if the given sw session id is active.
* @i915: i915 device handle.
@@ -86,6 +96,101 @@ static bool is_sw_session_active(struct drm_i915_private
*i915, int session_type
return false;
}
+static int pxp_set_pxp_tag(struct drm_i915_private *i915, int session_type,
+ int session_idx, int protection_mode)
+{
+ struct pxp_tag *pxp_tag;
+ int ret;
+
+ if (!i915 || session_type >= SESSION_TYPE_MAX) {
+ ret = -EINVAL;
+ drm_dbg(&i915->drm, "Failed to %s, bad params\n", __func__);
+ goto end;
+ }
+
+ if (session_type == SESSION_TYPE_TYPE0 && session_idx <
MAX_TYPE0_SESSIONS) {
+ pxp_tag = (struct pxp_tag
*)&i915->pxp.r0ctx->type0_session_pxp_tag[session_idx];
+ } else if (session_type == SESSION_TYPE_TYPE1 && session_idx <
MAX_TYPE1_SESSIONS) {
+ pxp_tag = (struct pxp_tag
*)&i915->pxp.r0ctx->type1_session_pxp_tag[session_idx];
+ } else {
+ ret = -EINVAL;
+ drm_dbg(&i915->drm, "Failed to %s, bad params
session_type=[%d], session_idx=[%d]\n",
+ __func__, session_type, session_idx);
+ goto end;
+ }
+
+ switch (protection_mode) {
+ case PROTECTION_MODE_NONE:
+ {
+ pxp_tag->enable = false;
+ pxp_tag->hm = false;
+ pxp_tag->sm = false;
+ break;
+ }
+ case PROTECTION_MODE_LM:
+ {
+ pxp_tag->enable = true;
+ pxp_tag->hm = false;
+ pxp_tag->sm = false;
+ pxp_tag->instance_id++;
+ break;
+ }
+ case PROTECTION_MODE_HM:
+ {
+ pxp_tag->enable = true;
+ pxp_tag->hm = true;
+ pxp_tag->sm = false;
+ pxp_tag->instance_id++;
+ break;
+ }
+ case PROTECTION_MODE_SM:
+ {
+ pxp_tag->enable = true;
+ pxp_tag->hm = true;
+ pxp_tag->sm = true;
+ pxp_tag->instance_id++;
+ break;
+ }
+ default:
+ ret = -EINVAL;
+ drm_dbg(&i915->drm, "Failed to %s, bad params
protection_mode=[%d]\n",
+ __func__, protection_mode);
+ goto end;
+ }
+
+ pxp_tag->session_id = pxp_get_session_id(session_idx, session_type);
+
+ ret = 0;
+end:
+ return ret;
+}
+
+u32 intel_pxp_get_pxp_tag(struct drm_i915_private *i915, int session_idx,
+ int session_type, u32 *session_is_alive)
+{
+ struct pxp_tag *pxp_tag;
+
+ if (!i915 || session_type >= SESSION_TYPE_MAX) {
+ drm_dbg(&i915->drm, "Failed to %s, bad params\n", __func__);
+ return -EINVAL;
+ }
+
+ if (session_type == SESSION_TYPE_TYPE0 && session_idx <
MAX_TYPE0_SESSIONS) {
+ pxp_tag = (struct pxp_tag
*)&i915->pxp.r0ctx->type0_session_pxp_tag[session_idx];
+ } else if (session_type == SESSION_TYPE_TYPE1 && session_idx <
MAX_TYPE1_SESSIONS) {
+ pxp_tag = (struct pxp_tag
*)&i915->pxp.r0ctx->type1_session_pxp_tag[session_idx];
+ } else {
+ drm_dbg(&i915->drm, "Failed to %s, bad params
session_type=[%d], session_idx=[%d]\n",
+ __func__, session_type, session_idx);
+ return -EINVAL;
+ }
+
+ if (session_is_alive)
+ *session_is_alive = pxp_tag->enable;
+
+ return pxp_tag->value;
+}
+
static bool is_hw_type0_session_in_play(struct drm_i915_private *i915, int
session_index)
{
u32 regval_sip = 0;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
index a3149c18c831..c1f6b1be3fd1 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
@@ -19,6 +19,9 @
[Intel-gfx] [PXP CLEAN PATCH v06 04/27] drm/i915/pxp: set KCR reg init during the boot time
From: "Huang, Sean Z"
Set the KCR init during the boot time, which is required by
hardware, to allow us doing further protection operation such
as sending commands to GPU or TEE
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c| 11 +-
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 48 +
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 19 ++
4 files changed, 78 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 831e8ad57560..81432a9f44d6 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -258,6 +258,7 @@ i915-y += i915_perf.o
i915-y += \
pxp/intel_pxp.o \
pxp/intel_pxp_context.o \
+ pxp/intel_pxp_sm.o
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 6d358f241406..3a24c2b13b14 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -6,6 +6,7 @@
#include "i915_drv.h"
#include "intel_pxp.h"
#include "intel_pxp_context.h"
+#include "intel_pxp_sm.h"
static void intel_pxp_write_irq_mask_reg(struct drm_i915_private *i915, u32
mask)
{
@@ -87,6 +88,8 @@ static void intel_pxp_irq_work(struct work_struct *work)
int intel_pxp_init(struct drm_i915_private *i915)
{
+ int ret;
+
drm_info(&i915->drm, "i915_pxp_init\n");
i915->pxp.r0ctx = intel_pxp_create_r0ctx(i915);
@@ -95,13 +98,19 @@ int intel_pxp_init(struct drm_i915_private *i915)
return -EFAULT;
}
+ ret = pxp_sm_set_kcr_init_reg(i915);
+ if (ret) {
+ drm_dbg(&i915->drm, "Failed to set kcr init reg\n");
+ return ret;
+ }
+
INIT_WORK(&i915->pxp.irq_work, intel_pxp_irq_work);
i915->pxp.handled_irr = (PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED |
PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ |
PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE);
- return 0;
+ return ret;
}
void intel_pxp_uninit(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
new file mode 100644
index ..75e4b229d9f8
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#include "gt/intel_context.h"
+#include "gt/intel_engine_pm.h"
+
+#include "intel_pxp.h"
+#include "intel_pxp_sm.h"
+#include "intel_pxp_context.h"
+
+static int pxp_reg_write(struct drm_i915_private *i915, u32 offset, u32 regval)
+{
+ intel_wakeref_t wakeref;
+ int err = 0;
+
+ if (!i915) {
+ err = -EINVAL;
+ drm_dbg(&i915->drm, "Failed to %s bad params\n", __func__);
+ goto end;
+ }
+
+ with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
+ i915_reg_t reg_offset = {offset};
+
+ intel_uncore_write(&i915->uncore, reg_offset, regval);
+ }
+end:
+ return err;
+}
+
+int pxp_sm_set_kcr_init_reg(struct drm_i915_private *i915)
+{
+ int ret;
+
+ drm_dbg(&i915->drm, ">>> %s\n", __func__);
+
+ ret = pxp_reg_write(i915, KCR_INIT.reg,
KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
+ if (ret) {
+ drm_dbg(&i915->drm, "Failed to write()\n");
+ goto end;
+ }
+
+end:
+ drm_dbg(&i915->drm, "<<< %s ret=[%d]\n", __func__, ret);
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
new file mode 100644
index ..59ce2394b590
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_SM_H__
+#define __INTEL_PXP_SM_H__
+
+#include "i915_reg.h"
+
+/* KCR register definitions */
+#define KCR_INIT_MMIO(0x320f0)
+#define KCR_INIT_MASK_SHIFT (16)
+/* Setting KCR Init bit is required after system boot */
+#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) <<
KCR_INIT_MASK_SHIFT))
+
+int pxp_sm_set_kcr_init_reg(struct drm_i915_private *i915);
+
+#endif /* __INTEL_PXP_SM_H__ */
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PXP CLEAN PATCH v06 26/27] drm/i915/pavp: User interface for Protected buffer
From: Bommu Krishnaiah
This api allow user mode to create Protected buffer and context creation.
Signed-off-by: Bommu Krishnaiah
Cc: Telukuntla Sreedhar
Cc: Kondapally Kalyan
Cc: Gupta Anshuman
Cc: Huang Sean Z
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 15 ++--
drivers/gpu/drm/i915/gem/i915_gem_context.h | 10
.../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +-
.../gpu/drm/i915/gem/i915_gem_object_types.h | 5
drivers/gpu/drm/i915/i915_gem.c | 23 +++
include/uapi/drm/i915_drm.h | 19 +++
6 files changed, 67 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 4fd38101bb56..1ca3265d6ca3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -2063,12 +2063,23 @@ static int ctx_setparam(struct drm_i915_file_private
*fpriv,
case I915_CONTEXT_PARAM_RECOVERABLE:
if (args->size)
ret = -EINVAL;
- else if (args->value)
- i915_gem_context_set_recoverable(ctx);
+ else if (args->value) {
+ if (!i915_gem_context_is_protected(ctx))
+ i915_gem_context_set_recoverable(ctx);
+ else
+ ret = -EPERM;
+ }
else
i915_gem_context_clear_recoverable(ctx);
break;
+ case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
+ if (args->size)
+ ret = -EINVAL;
+ else if (args->value)
+ i915_gem_context_set_protected(ctx);
+ break;
+
case I915_CONTEXT_PARAM_PRIORITY:
ret = set_priority(ctx, args);
break;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h
b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index a133f92bbedb..5897e7ca11a8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -70,6 +70,16 @@ static inline void i915_gem_context_set_recoverable(struct
i915_gem_context *ctx
set_bit(UCONTEXT_RECOVERABLE, &ctx->user_flags);
}
+static inline void i915_gem_context_set_protected(struct i915_gem_context *ctx)
+{
+ set_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
+}
+
+static inline bool i915_gem_context_is_protected(struct i915_gem_context *ctx)
+{
+ return test_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
+}
+
static inline void i915_gem_context_clear_recoverable(struct i915_gem_context
*ctx)
{
clear_bit(UCONTEXT_RECOVERABLE, &ctx->user_flags);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
index ae14ca24a11f..81ae94c2be86 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
@@ -135,7 +135,7 @@ struct i915_gem_context {
#define UCONTEXT_BANNABLE 2
#define UCONTEXT_RECOVERABLE 3
#define UCONTEXT_PERSISTENCE 4
-
+#define UCONTEXT_PROTECTED 5
/**
* @flags: small set of booleans
*/
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index e2d9b7e1e152..90ac955463f4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -161,6 +161,11 @@ struct drm_i915_gem_object {
} mmo;
I915_SELFTEST_DECLARE(struct list_head st_link);
+ /**
+* @user_flags: small set of booleans set by the user
+*/
+ unsigned long user_flags;
+#define I915_BO_PROTECTED BIT(0)
unsigned long flags;
#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 41698a823737..6a791fd24eaa 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -184,7 +184,8 @@ static int
i915_gem_create(struct drm_file *file,
struct intel_memory_region *mr,
u64 *size_p,
- u32 *handle_p)
+ u32 *handle_p,
+ u64 user_flags)
{
struct drm_i915_gem_object *obj;
u32 handle;
@@ -204,6 +205,8 @@ i915_gem_create(struct drm_file *file,
if (IS_ERR(obj))
return PTR_ERR(obj);
+ obj->user_flags = user_flags;
+
ret = drm_gem_handle_create(file, &obj->base, &handle);
/* drop reference from allocate - handle holds it now */
i915_gem_object_put(obj);
@@ -258,11 +261,12 @@ i915_gem_dumb_create(struct drm_file *file,
return i915_gem_create(file,
intel_memory_region_by_type(to_i915(dev),
[Intel-gfx] [PXP CLEAN PATCH v06 02/27] drm/i915/pxp: Enable PXP irq worker and callback stub
From: "Huang, Sean Z"
Create the irq worker that serves as callback handler, those
callback stubs should be called while the hardware key teardown
occurs.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 4 ++
drivers/gpu/drm/i915/i915_reg.h| 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 95 ++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 22 ++
4 files changed, 122 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index 257063a57101..d64013d0afb5 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -13,6 +13,7 @@
#include "intel_gt_irq.h"
#include "intel_uncore.h"
#include "intel_rps.h"
+#include "pxp/intel_pxp.h"
static void guc_irq_handler(struct intel_guc *guc, u16 iir)
{
@@ -106,6 +107,9 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8
instance,
if (instance == OTHER_GTPM_INSTANCE)
return gen11_rps_irq_handler(>->rps, iir);
+ if (instance == OTHER_KCR_INSTANCE)
+ return intel_pxp_irq_handler(gt, iir);
+
WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
instance, iir);
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7ea70b7ffcc6..faf6b06145fa 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7941,6 +7941,7 @@ enum {
/* irq instances for OTHER_CLASS */
#define OTHER_GUC_INSTANCE 0
#define OTHER_GTPM_INSTANCE1
+#define OTHER_KCR_INSTANCE 4
#define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index a469c55e3e54..d98bff4a0fde 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -6,15 +6,110 @@
#include "i915_drv.h"
#include "intel_pxp.h"
+static void intel_pxp_write_irq_mask_reg(struct drm_i915_private *i915, u32
mask)
+{
+ WARN_ON(INTEL_GEN(i915) < 11);
+
+ /* crypto mask is in bit31-16 (Engine1 Interrupt Mask) */
+ intel_uncore_write(&i915->uncore, GEN11_CRYPTO_RSVD_INTR_MASK, mask <<
16);
+}
+
+static void intel_pxp_unmask_irq(struct intel_gt *gt)
+{
+ lockdep_assert_held(>->irq_lock);
+
+ intel_pxp_write_irq_mask_reg(gt->i915, 0);
+}
+
+static void intel_pxp_mask_irq(struct intel_gt *gt, u32 mask)
+{
+ lockdep_assert_held(>->irq_lock);
+
+ intel_pxp_write_irq_mask_reg(gt->i915, mask);
+}
+
+static int intel_pxp_teardown_required_callback(struct drm_i915_private *i915)
+{
+ drm_dbg(&i915->drm, "%s was called\n", __func__);
+
+ return 0;
+}
+
+static int intel_pxp_global_terminate_complete_callback(struct
drm_i915_private *i915)
+{
+ drm_dbg(&i915->drm, ">>> %s\n", __func__);
+
+ return 0;
+}
+
+static void intel_pxp_irq_work(struct work_struct *work)
+{
+ struct intel_pxp *pxp_ptr = container_of(work, typeof(*pxp_ptr),
irq_work);
+ struct drm_i915_private *i915 = container_of(pxp_ptr, typeof(*i915),
pxp);
+ u32 events = 0;
+
+ spin_lock_irq(&i915->gt.irq_lock);
+ events = fetch_and_zero(&pxp_ptr->current_events);
+ spin_unlock_irq(&i915->gt.irq_lock);
+
+ drm_dbg(&i915->drm, "%s was called with events=[%d]\n", __func__,
events);
+
+ if (events & PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED ||
+ events & PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ)
+ intel_pxp_teardown_required_callback(i915);
+
+ if (events & PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE)
+ intel_pxp_global_terminate_complete_callback(i915);
+
+ spin_lock_irq(&i915->gt.irq_lock);
+ intel_pxp_unmask_irq(&i915->gt);
+ spin_unlock_irq(&i915->gt.irq_lock);
+}
+
int intel_pxp_init(struct drm_i915_private *i915)
{
int ret;
drm_info(&i915->drm, "i915_pxp_init\n");
+ INIT_WORK(&i915->pxp.irq_work, intel_pxp_irq_work);
+
+ i915->pxp.handled_irr = (PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED |
+PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ |
+PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE);
+
return ret;
}
void intel_pxp_uninit(struct drm_i915_private *i915)
{
}
+
+/**
+ * intel_pxp_irq_handler - Proxies KCR interrupts to PXP.
+ * @gt: valid GT instance
+ * @iir: GT interrupt vector associated with the interrupt
+ *
+ * Dispatches each vector element into an IRQ to PXP.
+ */
+void intel_pxp_irq_handler(struct intel_gt *gt, u16 iir)
+{
+ struct drm_i915_private *i915 = gt->i915;
+ const u32 events = iir & i915->pxp.handled_irr;
+
+ drm_dbg(&i915->drm, "%s was called with iir=[0x%04x]\n", __func__, iir);
+
+ lockdep_assert_held(>->irq_lock);
+
+ if (unlikely(!events)) {
+ drm_dbg(&i915->drm, "%s returned due to
[Intel-gfx] [PXP CLEAN PATCH v06 10/27] drm/i915/pxp: Enable ioctl action to reserve session slot
From: "Huang, Sean Z"
With this ioctl action, ring3 driver can reserve a specific
session slot/id assigned by ring0 PXP, as the first step of PXP
session establishment flow. Ring3 PXP stores the session info in
the session list structure.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c| 20 +++
drivers/gpu/drm/i915/pxp/intel_pxp.h| 24 +++-
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 168
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 3 +
4 files changed, 213 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index a83fa7cd749f..0f684851ecb2 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -47,6 +47,26 @@ int i915_pxp_ops_ioctl(struct drm_device *dev, void *data,
struct drm_file *drmf
}
switch (pxp_info.action) {
+ case PXP_ACTION_SET_SESSION_STATUS:
+ {
+ struct pxp_sm_set_session_status_params *params =
&pxp_info.set_session_status;
+
+ if (params->req_session_state == PXP_SM_REQ_SESSION_ID_INIT) {
+ ret = intel_pxp_sm_reserve_session(i915, drmfile, 0,
+ params->session_type,
+ params->session_mode,
+ ¶ms->pxp_tag);
+ if (ret == PXP_SM_STATUS_RETRY_REQUIRED ||
+ ret == PXP_SM_STATUS_SESSION_NOT_AVAILABLE) {
+ pxp_info.sm_status = ret;
+ ret = 0;
+ }
+ } else {
+ ret = -EINVAL;
+ goto end;
+ }
+ break;
+ }
case PXP_ACTION_SET_R3_CONTEXT:
{
ret = intel_pxp_set_r3ctx(i915, pxp_info.set_r3ctx);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 95d3deba7ade..cbaf25690596 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -15,6 +15,9 @@
#define pxp_session_list(i915, session_type) (((session_type) ==
SESSION_TYPE_TYPE0) ? \
&(i915)->pxp.r0ctx->active_pxp_type0_sessions :
&(i915)->pxp.r0ctx->active_pxp_type1_sessions)
+#define pxp_session_max(session_type) (((session_type) == SESSION_TYPE_TYPE0)
? \
+ MAX_TYPE0_SESSIONS : MAX_TYPE1_SESSIONS)
+
#define MAX_TYPE0_SESSIONS 16
#define MAX_TYPE1_SESSIONS 6
@@ -27,7 +30,10 @@ enum pxp_sm_session_req {
PXP_SM_REQ_SESSION_TERMINATE
};
-#define PXP_ACTION_SET_R3_CONTEXT 5
+enum pxp_ioctl_action {
+ PXP_ACTION_SET_SESSION_STATUS = 1,
+ PXP_ACTION_SET_R3_CONTEXT = 5,
+};
enum pxp_sm_status {
PXP_SM_STATUS_SUCCESS,
@@ -36,10 +42,24 @@ enum pxp_sm_status {
PXP_SM_STATUS_ERROR_UNKNOWN
};
+struct pxp_sm_set_session_status_params {
+ /** @pxp_tag: in [optional], for Arbitrator session, out pxp tag */
+ u32 pxp_tag;
+ /** @session_type: in, session type */
+ u32 session_type;
+ /** @session_mode: in, session mode */
+ u32 session_mode;
+ /** @req_session_state: in, new session state */
+ u32 req_session_state;
+};
+
struct pxp_info {
u32 action;
u32 sm_status;
- u32 set_r3ctx;
+ union {
+ struct pxp_sm_set_session_status_params set_session_status;
+ u32 set_r3ctx;
+ };
} __packed;
struct pxp_context;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index fd5d10e71a27..62303dc197e2 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -324,6 +324,174 @@ static bool
check_if_protected_type0_sessions_are_attacked(struct drm_i915_priva
return false;
}
+/**
+ * create_new_session_entry - Create a new session entry with provided info.
+ * @i915: i915 device handle.
+ * @drmfile: pointer to drm_file
+ * @context_id: Numeric identifier of the context created by the caller.
+ * @session_type: Type of the session requested. One of enum pxp_session_types.
+ * @protection_mode: Type of protection requested for the session.
+ * One of the enum pxp_protection_modes.
+ * @session_index: Numeric session identifier.
+ *
+ * Return: status. 0 means creation is successful.
+ */
+static int create_new_session_entry(struct drm_i915_private *i915, struct
drm_file *drmfile,
+ int context_id, int session_type, int
protection_mode,
+ int session_index)
+{
+ int ret;
+ struct pxp_protected_session *new_session = NULL;
+ int pid = 0;
+
+ if (drmfile)
+ pid = pid_nr(drmfile->pid);
+
+ drm_dbg(&i915->drm, ">>> %s context_id=[%d] sess
[Intel-gfx] [PXP CLEAN PATCH v06 20/27] drm/i915/pxp: Create the arbitrary session after boot
From: "Huang, Sean Z"
Create the arbitrary session, with the fixed session id 0xf, after
system boot, for the case that application allocates the protected
buffer without establishing any protection session. Because the
hardware requires at least one alive session for protected buffer
creation. This arbitrary session needs to be re-created after
teardown or power event because hardware encryption key won't be
valid after such cases.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 50 +++-
drivers/gpu/drm/i915/pxp/intel_pxp.h | 2 +
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 33
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 6 +++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 34
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 6 +++
6 files changed, 130 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 1a6cad0502c5..80e632b614f5 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -140,6 +140,46 @@ int intel_pxp_close(struct drm_i915_private *i915, struct
drm_file *drmfile)
return ret;
}
+int intel_pxp_create_arb_session(struct drm_i915_private *i915)
+{
+ struct pxp_tag pxptag;
+ int ret;
+
+ drm_dbg(&i915->drm, ">>> %s\n", __func__);
+
+ lockdep_assert_held(&i915->pxp.r0ctx->ctx_mutex);
+
+ if (i915->pxp.r0ctx->flag_display_hm_surface_keys) {
+ drm_dbg(&i915->drm, "%s: arb session is alive so skipping the
creation\n",
+ __func__);
+ return 0;
+ }
+
+ ret = intel_pxp_sm_reserve_arb_session(i915, &pxptag.value);
+ if (ret) {
+ drm_dbg(&i915->drm, "Failed to reserve session\n");
+ goto end;
+ }
+
+ ret = intel_pxp_tee_cmd_create_arb_session(i915);
+ if (ret) {
+ drm_dbg(&i915->drm, "Failed to send tee cmd for arb session
creation\n");
+ goto end;
+ }
+
+ ret = pxp_sm_mark_protected_session_in_play(i915, ARB_SESSION_TYPE,
pxptag.session_id);
+ if (ret) {
+ drm_dbg(&i915->drm, "Failed to mark session status in play\n");
+ goto end;
+ }
+
+ i915->pxp.r0ctx->flag_display_hm_surface_keys = true;
+
+end:
+ drm_dbg(&i915->drm, "<<< %s ret=[%d]\n", __func__, ret);
+ return ret;
+}
+
static void intel_pxp_write_irq_mask_reg(struct drm_i915_private *i915, u32
mask)
{
WARN_ON(INTEL_GEN(i915) < 11);
@@ -190,9 +230,17 @@ static int
intel_pxp_global_terminate_complete_callback(struct drm_i915_private
mutex_lock(&i915->pxp.r0ctx->ctx_mutex);
- if (i915->pxp.r0ctx->global_state_attacked)
+ if (i915->pxp.r0ctx->global_state_attacked) {
i915->pxp.r0ctx->global_state_attacked = false;
+ /* Re-create the arb session after teardown handle complete */
+ ret = intel_pxp_create_arb_session(i915);
+ if (ret) {
+ drm_dbg(&i915->drm, "Failed to create arb session\n");
+ goto end;
+ }
+ }
+end:
mutex_unlock(&i915->pxp.r0ctx->ctx_mutex);
drm_dbg(&i915->drm, "<<< %s ret=[%d]\n", __func__, ret);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 2c16ed0b5c0b..c0119ccdab08 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -102,6 +102,8 @@ struct drm_i915_private;
int i915_pxp_ops_ioctl(struct drm_device *dev, void *data, struct drm_file
*drmfile);
int intel_pxp_close(struct drm_i915_private *i915, struct drm_file *drmfile);
+int intel_pxp_create_arb_session(struct drm_i915_private *i915);
+
void intel_pxp_irq_handler(struct intel_gt *gt, u16 iir);
int i915_pxp_teardown_required_callback(struct drm_i915_private *i915);
int i915_pxp_global_terminate_complete_callback(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index 71082938b9f0..55cdd402f704 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -673,6 +673,39 @@ int intel_pxp_sm_reserve_session(struct drm_i915_private
*i915, struct drm_file
return ret;
}
+int intel_pxp_sm_reserve_arb_session(struct drm_i915_private *i915, u32
*pxp_tag)
+{
+ int ret;
+
+ drm_dbg(&i915->drm, ">>> %s\n", __func__);
+
+ lockdep_assert_held(&i915->pxp.r0ctx->ctx_mutex);
+
+ if (!pxp_tag || !i915) {
+ ret = -EINVAL;
+ drm_dbg(&i915->drm, "Failed to %s, bad params\n", __func__);
+ goto end;
+ }
+
+ ret = sync_hw_sw_state(i915, ARB_SESSION_INDEX, ARB_SESSION_TYPE);
+ if (unlikely(ret))
+ goto end;
+
+ ret = create_new_session_entry(i915, NULL, 0,
[Intel-gfx] [PXP CLEAN PATCH v06 03/27] drm/i915/pxp: Add PXP context for logical hardware states.
From: "Huang, Sean Z"
Add PXP context which represents combined view
of driver and logical HW states.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile| 3 +-
drivers/gpu/drm/i915/pxp/intel_pxp.c | 32 ++--
drivers/gpu/drm/i915/pxp/intel_pxp.h | 3 ++
drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 52
drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 42
5 files changed, 127 insertions(+), 5 deletions(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 8274fea96009..831e8ad57560 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -256,7 +256,8 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support
i915-y += \
- pxp/intel_pxp.o
+ pxp/intel_pxp.o \
+ pxp/intel_pxp_context.o \
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index d98bff4a0fde..6d358f241406 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -5,6 +5,7 @@
#include "i915_drv.h"
#include "intel_pxp.h"
+#include "intel_pxp_context.h"
static void intel_pxp_write_irq_mask_reg(struct drm_i915_private *i915, u32
mask)
{
@@ -32,14 +33,32 @@ static int intel_pxp_teardown_required_callback(struct
drm_i915_private *i915)
{
drm_dbg(&i915->drm, "%s was called\n", __func__);
+ mutex_lock(&i915->pxp.r0ctx->ctx_mutex);
+
+ i915->pxp.r0ctx->global_state_attacked = true;
+ i915->pxp.r0ctx->flag_display_hm_surface_keys = false;
+
+ mutex_unlock(&i915->pxp.r0ctx->ctx_mutex);
+
return 0;
}
static int intel_pxp_global_terminate_complete_callback(struct
drm_i915_private *i915)
{
+ int ret = 0;
+
drm_dbg(&i915->drm, ">>> %s\n", __func__);
- return 0;
+ mutex_lock(&i915->pxp.r0ctx->ctx_mutex);
+
+ if (i915->pxp.r0ctx->global_state_attacked)
+ i915->pxp.r0ctx->global_state_attacked = false;
+
+ mutex_unlock(&i915->pxp.r0ctx->ctx_mutex);
+
+ drm_dbg(&i915->drm, "<<< %s ret=[%d]\n", __func__, ret);
+
+ return ret;
}
static void intel_pxp_irq_work(struct work_struct *work)
@@ -68,21 +87,26 @@ static void intel_pxp_irq_work(struct work_struct *work)
int intel_pxp_init(struct drm_i915_private *i915)
{
- int ret;
-
drm_info(&i915->drm, "i915_pxp_init\n");
+ i915->pxp.r0ctx = intel_pxp_create_r0ctx(i915);
+ if (!i915->pxp.r0ctx) {
+ drm_dbg(&i915->drm, "Failed to create pxp ctx\n");
+ return -EFAULT;
+ }
+
INIT_WORK(&i915->pxp.irq_work, intel_pxp_irq_work);
i915->pxp.handled_irr = (PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED |
PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ |
PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE);
- return ret;
+ return 0;
}
void intel_pxp_uninit(struct drm_i915_private *i915)
{
+ intel_pxp_destroy_r0ctx(i915);
}
/**
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 620774fc32e2..4dec35bb834d 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -12,6 +12,9 @@
#define PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ BIT(2)
#define PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE BIT(3)
+#define MAX_TYPE0_SESSIONS 16
+#define MAX_TYPE1_SESSIONS 6
+
enum pxp_sm_session_req {
/* Request KMD to allocate session id and move it to IN INIT */
PXP_SM_REQ_SESSION_ID_INIT = 0x0,
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
new file mode 100644
index ..daa93f9bd595
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#include "i915_drv.h"
+#include "intel_pxp_context.h"
+
+/**
+ * intel_pxp_create_ctx - To create a new pxp context.
+ * @i915: i915 device handle.
+ *
+ * Return: pointer to new_ctx, NULL for failure
+ */
+struct pxp_context *intel_pxp_create_r0ctx(struct drm_i915_private *i915)
+{
+ struct pxp_context *new_ctx = NULL;
+
+ drm_dbg(&i915->drm, ">>> %s\n", __func__);
+
+ new_ctx = kzalloc(sizeof(*new_ctx), GFP_KERNEL);
+ if (!new_ctx) {
+ drm_dbg(&i915->drm, "unable to allocate new pxp context!\n");
+ return NULL;
+ }
+
+ get_random_bytes(&new_ctx->r0ctx_id, sizeof(new_ctx->r0ctx_id));
+
+ new_ctx->global_state_attacked = false;
+
+ mutex_init(&new_ctx->ctx_mutex)
[Intel-gfx] [PXP CLEAN PATCH v06 05/27] drm/i915/pxp: Enable ioctl action to set the ring3 context
From: "Huang, Sean Z"
Enable one ioctl action to allow ring3 driver to set its ring3
context, so ring0 PXP can track the context id through this ring3
context list.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 66
drivers/gpu/drm/i915/pxp/intel_pxp.h | 16 +
drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 34 ++
drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 3 +
include/uapi/drm/i915_drm.h | 2 +
6 files changed, 122 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index c8b9c42fcbd6..43ea85b5f14b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1761,6 +1761,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl,
DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(I915_PXP_OPS, i915_pxp_ops_ioctl, DRM_RENDER_ALLOW),
};
static const struct drm_driver driver = {
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 3a24c2b13b14..a83fa7cd749f 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -8,6 +8,70 @@
#include "intel_pxp_context.h"
#include "intel_pxp_sm.h"
+int i915_pxp_ops_ioctl(struct drm_device *dev, void *data, struct drm_file
*drmfile)
+{
+ int ret;
+ struct pxp_info pxp_info = {0};
+ struct drm_i915_pxp_ops *pxp_ops = data;
+ struct drm_i915_private *i915 = to_i915(dev);
+
+ drm_dbg(&i915->drm, ">>> %s\n", __func__);
+
+ if (!i915 || !drmfile || !pxp_ops || pxp_ops->pxp_info_size !=
sizeof(pxp_info)) {
+ drm_dbg(&i915->drm, "Failed to %s, invalid params\n", __func__);
+ ret = -EINVAL;
+ goto end;
+ }
+
+ if (copy_from_user(&pxp_info, (void __user *)pxp_ops->pxp_info_ptr,
sizeof(pxp_info)) != 0) {
+ ret = -EFAULT;
+ goto end;
+ }
+
+ drm_dbg(&i915->drm, "i915 pxp ioctl call with action=[%d]\n",
pxp_info.action);
+
+ mutex_lock(&i915->pxp.r0ctx->ctx_mutex);
+
+ if (i915->pxp.r0ctx->global_state_in_suspend) {
+ drm_dbg(&i915->drm, "Return failure due to state in suspend\n");
+ pxp_info.sm_status = PXP_SM_STATUS_SESSION_NOT_AVAILABLE;
+ ret = 0;
+ goto end;
+ }
+
+ if (i915->pxp.r0ctx->global_state_attacked) {
+ drm_dbg(&i915->drm, "Retry required due to state attacked\n");
+ pxp_info.sm_status = PXP_SM_STATUS_RETRY_REQUIRED;
+ ret = 0;
+ goto end;
+ }
+
+ switch (pxp_info.action) {
+ case PXP_ACTION_SET_R3_CONTEXT:
+ {
+ ret = intel_pxp_set_r3ctx(i915, pxp_info.set_r3ctx);
+ break;
+ }
+ default:
+ drm_dbg(&i915->drm, "Failed to %s due to bad params\n",
__func__);
+ ret = -EINVAL;
+ goto end;
+ }
+
+end:
+ mutex_unlock(&i915->pxp.r0ctx->ctx_mutex);
+
+ if (ret == 0)
+ if (copy_to_user((void __user *)pxp_ops->pxp_info_ptr,
&pxp_info, sizeof(pxp_info)) != 0)
+ ret = -EFAULT;
+
+ if (ret)
+ dev_err(&dev->pdev->dev, "pid=%d, ret = %d\n",
task_pid_nr(current), ret);
+
+ drm_dbg(&i915->drm, "<<< %s\n", __func__);
+ return ret;
+}
+
static void intel_pxp_write_irq_mask_reg(struct drm_i915_private *i915, u32
mask)
{
WARN_ON(INTEL_GEN(i915) < 11);
@@ -39,6 +103,8 @@ static int intel_pxp_teardown_required_callback(struct
drm_i915_private *i915)
i915->pxp.r0ctx->global_state_attacked = true;
i915->pxp.r0ctx->flag_display_hm_surface_keys = false;
+ intel_pxp_destroy_r3ctx_list(i915);
+
mutex_unlock(&i915->pxp.r0ctx->ctx_mutex);
return 0;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 4dec35bb834d..21a6964fc64e 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -24,6 +24,21 @@ enum pxp_sm_session_req {
PXP_SM_REQ_SESSION_TERMINATE
};
+#define PXP_ACTION_SET_R3_CONTEXT 5
+
+enum pxp_sm_status {
+ PXP_SM_STATUS_SUCCESS,
+ PXP_SM_STATUS_RETRY_REQUIRED,
+ PXP_SM_STATUS_SESSION_NOT_AVAILABLE,
+ PXP_SM_STATUS_ERROR_UNKNOWN
+};
+
+struct pxp_info {
+ u32 action;
+ u32 sm_status;
+ u32 set_r3ctx;
+} __packed;
+
struct pxp_context;
struct intel_pxp {
@@ -37,6 +52,7 @@ struct intel_pxp {
struct intel_gt;
struct drm_i915_private;
+int i915_pxp_ops_ioctl(struct drm_device *dev, void *data, struct drm_file
[Intel-gfx] [PXP CLEAN PATCH v06 07/27] drm/i915/pxp: Add PXP-related registers into allowlist
From: "Huang, Sean Z"
Add several PXP-related reg into allowlist to allow
ring3 driver to read the those register values.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/i915_reg.h | 8
drivers/gpu/drm/i915/intel_uncore.c | 57 +
2 files changed, 50 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index faf6b06145fa..5c51c9df8b28 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -12419,4 +12419,12 @@ enum skl_power_gate {
#define TGL_ROOT_DEVICE_SKU_ULX0x2
#define TGL_ROOT_DEVICE_SKU_ULT0x4
+/* Registers for passlist check */
+#define PXP_REG_01_LOWERBOUND _MMIO(0x32260)
+#define PXP_REG_01_UPPERBOUND _MMIO(0x32268)
+#define PXP_REG_02_LOWERBOUND _MMIO(0x32670)
+#define PXP_REG_02_UPPERBOUND _MMIO(0x32678)
+#define PXP_REG_03_LOWERBOUND _MMIO(0x32860)
+#define PXP_REG_03_UPPERBOUND _MMIO(0x32c7c)
+
#endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index c9ef0025c60e..670856e095c4 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1990,16 +1990,41 @@ void intel_uncore_fini_mmio(struct intel_uncore *uncore)
}
static const struct reg_allowlist {
- i915_reg_t offset_ldw;
+ i915_reg_t offset_ldw_lowerbound;
+ i915_reg_t offset_ldw_upperbound;
i915_reg_t offset_udw;
u16 gen_mask;
u8 size;
-} reg_read_allowlist[] = { {
- .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
+} reg_read_allowlist[] = {
+ {
+ .offset_ldw_lowerbound = RING_TIMESTAMP(RENDER_RING_BASE),
+ .offset_ldw_upperbound = RING_TIMESTAMP(RENDER_RING_BASE),
.offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
.gen_mask = INTEL_GEN_MASK(4, 12),
.size = 8
-} };
+ },
+ {
+ .offset_ldw_lowerbound = PXP_REG_01_LOWERBOUND,
+ .offset_ldw_upperbound = PXP_REG_01_UPPERBOUND,
+ .offset_udw = {0},
+ .gen_mask = INTEL_GEN_MASK(4, 12),
+ .size = 4
+ },
+ {
+ .offset_ldw_lowerbound = PXP_REG_02_LOWERBOUND,
+ .offset_ldw_upperbound = PXP_REG_02_UPPERBOUND,
+ .offset_udw = {0},
+ .gen_mask = INTEL_GEN_MASK(4, 12),
+ .size = 4
+ },
+ {
+ .offset_ldw_lowerbound = PXP_REG_03_LOWERBOUND,
+ .offset_ldw_upperbound = PXP_REG_03_UPPERBOUND,
+ .offset_udw = {0},
+ .gen_mask = INTEL_GEN_MASK(4, 12),
+ .size = 4
+ }
+};
int i915_reg_read_ioctl(struct drm_device *dev,
void *data, struct drm_file *file)
@@ -2012,18 +2037,22 @@ int i915_reg_read_ioctl(struct drm_device *dev,
unsigned int flags;
int remain;
int ret = 0;
+ i915_reg_t offset_ldw;
entry = reg_read_allowlist;
remain = ARRAY_SIZE(reg_read_allowlist);
while (remain) {
- u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw);
+ u32 entry_offset_lb =
i915_mmio_reg_offset(entry->offset_ldw_lowerbound);
+ u32 entry_offset_ub =
i915_mmio_reg_offset(entry->offset_ldw_upperbound);
GEM_BUG_ON(!is_power_of_2(entry->size));
GEM_BUG_ON(entry->size > 8);
- GEM_BUG_ON(entry_offset & (entry->size - 1));
+ GEM_BUG_ON(entry_offset_lb & (entry->size - 1));
+ GEM_BUG_ON(entry_offset_ub & (entry->size - 1));
if (INTEL_INFO(i915)->gen_mask & entry->gen_mask &&
- entry_offset == (reg->offset & -entry->size))
+ entry_offset_lb <= (reg->offset & -entry->size) &&
+ (reg->offset & -entry->size) <= entry_offset_ub)
break;
entry++;
remain--;
@@ -2033,23 +2062,21 @@ int i915_reg_read_ioctl(struct drm_device *dev,
return -EINVAL;
flags = reg->offset & (entry->size - 1);
+ offset_ldw = _MMIO(reg->offset - flags);
with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
if (entry->size == 8 && flags == I915_REG_READ_8B_WA)
reg->val = intel_uncore_read64_2x32(uncore,
- entry->offset_ldw,
+ offset_ldw,
entry->offset_udw);
else if (entry->size == 8 && flags == 0)
- reg->val = intel_uncore_read64(uncore,
- entry->offset_ldw);
+ reg->val = intel_uncore_read64(uncore, offset_ldw);
else if (entry->size == 4 && flags == 0)
- reg->val = intel_uncore_read(uncore, entry->offset
[Intel-gfx] [PXP CLEAN PATCH v06 13/27] drm/i915/pxp: Enable ioctl action to terminate the session
From: "Huang, Sean Z"
Enable the PXP ioctl action to allow ring3 PXP to terminate the
hardware session and cleanup its software session state.
Ring0 PXP sends the session termination command to GPU once
receves this ioctl action.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c| 7 +
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 205
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 5 +
3 files changed, 217 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index baa61a3a70ff..72a2237b504b 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -65,6 +65,13 @@ int i915_pxp_ops_ioctl(struct drm_device *dev, void *data,
struct drm_file *drmf
ret = pxp_sm_mark_protected_session_in_play(i915,
params->session_type,
params->pxp_tag);
+ } else if (params->req_session_state ==
PXP_SM_REQ_SESSION_TERMINATE) {
+ ret = pxp_sm_terminate_protected_session_safe(i915, 0,
+
params->session_type,
+
params->pxp_tag);
+
+ if (!intel_pxp_sm_is_any_type0_session_in_play(i915,
PROTECTION_MODE_ALL))
+ intel_pxp_destroy_r3ctx_list(i915);
} else {
ret = -EINVAL;
goto end;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index 0e1ce75f9ccd..b1adfa735d4f 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -893,6 +893,189 @@ static int issue_hw_terminate_for_session(struct
drm_i915_private *i915, int ses
return ret;
}
+/**
+ * terminate_protected_session - To terminate an active HW session and free
its entry.
+ * @i915: i915 device handle.
+ * @context_id: context identifier of the requestor. only relevant if
do_safety_check is true.
+ * @session_type: type of the session to be terminated. One of enum
pxp_session_types.
+ * @session_index: session index of the session to be terminated.
+ * @do_safety_check: if enabled the context Id sent by the caller is
+ * matched with the one associated with the terminated
+ * session entry.
+ *
+ * Return: status. 0 means terminate is successful.
+ */
+static int terminate_protected_session(struct drm_i915_private *i915, int
context_id,
+ int session_type, int session_index,
+ bool do_safety_check)
+{
+ int ret;
+ struct pxp_protected_session *current_session, *n;
+
+ drm_dbg(&i915->drm, ">>> %s conext_id=[%d] session_type=[%d]
session_index=[0x%08x] do_safety_check=[%d]\n",
+ __func__, context_id, session_type, session_index,
do_safety_check);
+
+ lockdep_assert_held(&i915->pxp.r0ctx->ctx_mutex);
+
+ switch (session_type) {
+ case SESSION_TYPE_TYPE0:
+ list_for_each_entry_safe(current_session, n,
&i915->pxp.r0ctx->active_pxp_type0_sessions, session_list) {
+ if (current_session->session_index == session_index) {
+ if (do_safety_check &&
current_session->context_id != context_id) {
+ ret = -EPERM;
+ drm_dbg(&i915->drm, "Failed to %s due
to invalid context_id=[%d]\n", __func__, context_id);
+ goto end;
+ }
+
+ ret = issue_hw_terminate_for_session(i915,
session_type, session_index);
+ if (ret) {
+ drm_dbg(&i915->drm, "Failed to
issue_hw_terminate_for_session()\n");
+ goto end;
+ }
+
+ ret = pxp_set_pxp_tag(i915, session_type,
session_index, PROTECTION_MODE_NONE);
+ if (ret) {
+ drm_dbg(&i915->drm, "Failed to
pxp_set_pxp_tag()\n");
+ goto end;
+ }
+
+ /* delete the current session entry from the
linked list */
+ list_del(¤t_session->session_list);
+
+ /* free the memory associated with the current
context entry */
+ kfree(current_session);
+
+ /* TODO: special arbitrator session checks? */
+
+ ret = 0;
+ goto end;
+ }
+ }
+
+
[Intel-gfx] [PXP CLEAN PATCH v06 08/27] drm/i915/pxp: Read register to check hardware session state
From: "Huang, Sean Z"
Implement the functions to check the hardware protected session
state via reading the hardware register session in play.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.h| 3 +
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 189
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 51 +++
3 files changed, 243 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 21a6964fc64e..95d3deba7ade 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -12,6 +12,9 @@
#define PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ BIT(2)
#define PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE BIT(3)
+#define pxp_session_list(i915, session_type) (((session_type) ==
SESSION_TYPE_TYPE0) ? \
+ &(i915)->pxp.r0ctx->active_pxp_type0_sessions :
&(i915)->pxp.r0ctx->active_pxp_type1_sessions)
+
#define MAX_TYPE0_SESSIONS 16
#define MAX_TYPE1_SESSIONS 6
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index 75e4b229d9f8..3dd5a9e3926b 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -10,6 +10,25 @@
#include "intel_pxp_sm.h"
#include "intel_pxp_context.h"
+int pxp_sm_reg_read(struct drm_i915_private *i915, u32 offset, u32 *regval)
+{
+ intel_wakeref_t wakeref;
+ int err = 0;
+
+ if (!i915 || !regval) {
+ err = -EINVAL;
+ drm_dbg(&i915->drm, "Failed to %s bad params\n", __func__);
+ goto end;
+ }
+
+ with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
+ i915_reg_t reg_offset = {offset};
+ *regval = intel_uncore_read(&i915->uncore, reg_offset);
+ }
+end:
+ return err;
+}
+
static int pxp_reg_write(struct drm_i915_private *i915, u32 offset, u32 regval)
{
intel_wakeref_t wakeref;
@@ -30,6 +49,176 @@ static int pxp_reg_write(struct drm_i915_private *i915, u32
offset, u32 regval)
return err;
}
+/**
+ * is_sw_session_active - Check if the given sw session id is active.
+ * @i915: i915 device handle.
+ * @session_type: Specified session type
+ * @session_index: Numeric session identifier.
+ * @is_in_play: Set false to return true if the specified session is active.
+ * Set true to also check if the session is active and in_play.
+ * @protection_mode: get the protection mode of specified session.
+ *
+ * The caller needs to use ctx_mutex lock to protect the session_list
+ * inside this function.
+ *
+ * Return : true if session with the same identifier is active (and in_play).
+ */
+static bool is_sw_session_active(struct drm_i915_private *i915, int
session_type,
+int session_index, bool is_in_play, int
*protection_mode)
+{
+ struct pxp_protected_session *current_session;
+
+ lockdep_assert_held(&i915->pxp.r0ctx->ctx_mutex);
+
+ list_for_each_entry(current_session, pxp_session_list(i915,
session_type), session_list) {
+ if (current_session->session_index == session_index) {
+ if (protection_mode)
+ *protection_mode =
current_session->protection_mode;
+
+ if (is_in_play && !current_session->session_is_in_play)
+ return false;
+
+ return true;
+ }
+ }
+
+ /* session id not found. return false */
+ return false;
+}
+
+static bool is_hw_type0_session_in_play(struct drm_i915_private *i915, int
session_index)
+{
+ u32 regval_sip = 0;
+ u32 reg_session_id_mask;
+ bool hw_session_is_in_play = false;
+ int ret = 0;
+
+ if (!i915 || session_index < 0 || session_index >= MAX_TYPE0_SESSIONS) {
+ drm_dbg(&i915->drm, "Failed to %s due to invalid params",
__func__);
+ goto end;
+ }
+
+ ret = pxp_sm_reg_read(i915, GEN12_KCR_SIP.reg, ®val_sip);
+ if (ret) {
+ drm_dbg(&i915->drm, "Failed to read()\n");
+ goto end;
+ }
+
+ reg_session_id_mask = (1 << session_index);
+ hw_session_is_in_play = (bool)(regval_sip & reg_session_id_mask);
+end:
+ return hw_session_is_in_play;
+}
+
+static bool is_hw_type1_session_in_play(struct drm_i915_private *i915, int
session_index)
+{
+ int ret = 0;
+ u32 regval_tsip_low = 0;
+ u32 regval_tsip_high = 0;
+ u64 reg_session_id_mask;
+ u64 regval_tsip;
+ bool hw_session_is_in_play = false;
+
+ if (!i915 || session_index < 0 || session_index >= MAX_TYPE1_SESSIONS) {
+ drm_dbg(&i915->drm, "Failed to %s due to invalid params",
__func__);
+ goto end;
+ }
+
+ ret = pxp_sm_reg_read(i915, GEN12_KCR_TSIP_LOW.reg, ®val_tsip_low);
+ if (ret) {
+ drm_dbg(&i915->drm, "Failed to pxp
[Intel-gfx] [PXP CLEAN PATCH v06 14/27] drm/i915/pxp: Enable ioctl action to query PXP tag
From: "Huang, Sean Z"
Enable the PXP ioctl action to allow ring3 PXP to query the PXP
tag, which is a 32-bit bitwise value indicating the current
session info, including protection type, session id, and whether
the session is enabled.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c| 7 +++
drivers/gpu/drm/i915/pxp/intel_pxp.h| 7 +++
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 28 +
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 3 +++
4 files changed, 45 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 72a2237b504b..2121db05fdb6 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -78,6 +78,13 @@ int i915_pxp_ops_ioctl(struct drm_device *dev, void *data,
struct drm_file *drmf
}
break;
}
+ case PXP_ACTION_QUERY_PXP_TAG:
+ {
+ struct pxp_sm_query_pxp_tag *params = &pxp_info.query_pxp_tag;
+
+ ret = pxp_sm_ioctl_query_pxp_tag(i915,
¶ms->session_is_alive, ¶ms->pxp_tag);
+ break;
+ }
case PXP_ACTION_SET_R3_CONTEXT:
{
ret = intel_pxp_set_r3ctx(i915, pxp_info.set_r3ctx);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index cbaf25690596..8851c28a0e57 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -31,6 +31,7 @@ enum pxp_sm_session_req {
};
enum pxp_ioctl_action {
+ PXP_ACTION_QUERY_PXP_TAG = 0,
PXP_ACTION_SET_SESSION_STATUS = 1,
PXP_ACTION_SET_R3_CONTEXT = 5,
};
@@ -42,6 +43,11 @@ enum pxp_sm_status {
PXP_SM_STATUS_ERROR_UNKNOWN
};
+struct pxp_sm_query_pxp_tag {
+ u32 session_is_alive;
+ u32 pxp_tag; /* in - Session ID, out pxp tag */
+};
+
struct pxp_sm_set_session_status_params {
/** @pxp_tag: in [optional], for Arbitrator session, out pxp tag */
u32 pxp_tag;
@@ -57,6 +63,7 @@ struct pxp_info {
u32 action;
u32 sm_status;
union {
+ struct pxp_sm_query_pxp_tag query_pxp_tag;
struct pxp_sm_set_session_status_params set_session_status;
u32 set_r3ctx;
};
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index b1adfa735d4f..994abf5a8d36 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -1076,6 +1076,34 @@ int pxp_sm_terminate_protected_session_unsafe(struct
drm_i915_private *i915, int
return ret;
}
+int pxp_sm_ioctl_query_pxp_tag(struct drm_i915_private *i915, u32
*session_is_alive, u32 *pxp_tag)
+{
+ int session_type = 0;
+ int session_index = 0;
+ int ret;
+
+ drm_dbg(&i915->drm, ">>> %s\n", __func__);
+
+ if (!session_is_alive || !pxp_tag) {
+ ret = -EINVAL;
+ drm_dbg(&i915->drm, "Failed to %s, bad param\n", __func__);
+ goto end;
+ }
+
+ ret = pxp_get_session_index(i915, *pxp_tag, &session_index,
&session_type);
+ if (ret) {
+ drm_dbg(&i915->drm, "Failed to __pxpsessionid_to_sessionid\n");
+ goto end;
+ }
+
+ *pxp_tag = intel_pxp_get_pxp_tag(i915, session_index, session_type,
session_is_alive);
+
+ ret = 0;
+end:
+ drm_dbg(&i915->drm, "<<< %s ret=[%d]\n", __func__, ret);
+ return ret;
+}
+
int pxp_sm_set_kcr_init_reg(struct drm_i915_private *i915)
{
int ret;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
index 26597b1d18e1..859f3c1f8c6e 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
@@ -108,7 +108,10 @@ int pxp_sm_terminate_protected_session_safe(struct
drm_i915_private *i915, int c
int session_type, int session_id);
int pxp_sm_terminate_protected_session_unsafe(struct drm_i915_private *i915,
int session_type,
int session_id);
+int pxp_sm_ioctl_query_pxp_tag(struct drm_i915_private *i915, u32
*session_is_alive, u32 *pxp_tag);
int pxp_sm_set_kcr_init_reg(struct drm_i915_private *i915);
+u32 intel_pxp_get_pxp_tag(struct drm_i915_private *i915, int session_idx,
+ int session_type, u32 *session_is_alive);
bool intel_pxp_sm_is_any_type0_session_in_play(struct drm_i915_private *i915,
int protection_mode);
#endif /* __INTEL_PXP_SM_H__ */
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PXP CLEAN PATCH v06 21/27] drm/i915/pxp: Add i915 trace logs for PXP operations
From: "Huang, Sean Z"
Add several i915 trace logs for PXP calls for debugging or
performance measurement, including:
(1) PXP ioctl
(2) PXP teardown callbacks
To trun on this feature, we need to set
"CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS=y" in .config for compiling
the Linux kernel.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/i915_trace.h| 44
drivers/gpu/drm/i915/pxp/intel_pxp.c | 5
2 files changed, 49 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_trace.h
b/drivers/gpu/drm/i915/i915_trace.h
index a4addcc64978..36470e20dc61 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -1031,6 +1031,50 @@ DEFINE_EVENT(i915_context, i915_context_free,
TP_ARGS(ctx)
);
+TRACE_EVENT(i915_pxp_ops_ioctl,
+ TP_PROTO(struct drm_device *dev, void *data, struct drm_file *file,
u32 action),
+ TP_ARGS(dev, data, file, action),
+
+ TP_STRUCT__entry(
+__field(struct drm_device *, dev)
+__field(void *, data)
+__field(struct drm_file *, file)
+__field(u32, action)
+ ),
+
+ TP_fast_assign(
+ __entry->dev = dev;
+ __entry->data = data;
+ __entry->file = file;
+ __entry->action = action;
+ ),
+
+ TP_printk("dev=%p, data=%p, file=%p, action=%u",
+ __entry->dev, __entry->data, __entry->file,
__entry->action)
+);
+
+TRACE_EVENT(i915_pxp_teardown_required_callback,
+ TP_PROTO(bool global_state_attacked),
+ TP_ARGS(global_state_attacked),
+
+ TP_STRUCT__entry(__field(bool, global_state_attacked)),
+
+ TP_fast_assign(__entry->global_state_attacked =
global_state_attacked;),
+
+ TP_printk("global_state_attacked=%s",
yesno(__entry->global_state_attacked))
+);
+
+TRACE_EVENT(i915_pxp_global_terminate_complete_callback,
+ TP_PROTO(bool global_state_attacked),
+ TP_ARGS(global_state_attacked),
+
+ TP_STRUCT__entry(__field(bool, global_state_attacked)),
+
+ TP_fast_assign(__entry->global_state_attacked =
global_state_attacked;),
+
+ TP_printk("global_state_attacked=%s",
yesno(__entry->global_state_attacked))
+);
+
#endif /* _I915_TRACE_H_ */
/* This part must be outside protection */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 80e632b614f5..23955d7a3c3d 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -8,6 +8,7 @@
#include "intel_pxp_context.h"
#include "intel_pxp_sm.h"
#include "intel_pxp_tee.h"
+#include "i915_trace.h"
int i915_pxp_ops_ioctl(struct drm_device *dev, void *data, struct drm_file
*drmfile)
{
@@ -30,6 +31,7 @@ int i915_pxp_ops_ioctl(struct drm_device *dev, void *data,
struct drm_file *drmf
}
drm_dbg(&i915->drm, "i915 pxp ioctl call with action=[%d]\n",
pxp_info.action);
+ trace_i915_pxp_ops_ioctl(dev, data, drmfile, pxp_info.action);
mutex_lock(&i915->pxp.r0ctx->ctx_mutex);
@@ -219,6 +221,8 @@ static int intel_pxp_teardown_required_callback(struct
drm_i915_private *i915)
mutex_unlock(&i915->pxp.r0ctx->ctx_mutex);
+
trace_i915_pxp_teardown_required_callback(i915->pxp.r0ctx->global_state_attacked);
+
return ret;
}
@@ -243,6 +247,7 @@ static int
intel_pxp_global_terminate_complete_callback(struct drm_i915_private
end:
mutex_unlock(&i915->pxp.r0ctx->ctx_mutex);
+
trace_i915_pxp_global_terminate_complete_callback(i915->pxp.r0ctx->global_state_attacked);
drm_dbg(&i915->drm, "<<< %s ret=[%d]\n", __func__, ret);
return ret;
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PXP CLEAN PATCH v06 15/27] drm/i915/pxp: Destroy all type0 sessions upon teardown
From: "Huang, Sean Z"
Teardown is triggered when the display topology changes and no
long meets the secure playback requirement, and hardware trashes
all the encryption keys for display. So as a result, ring0 PXP
should handle such case and terminate all the type0 sessions.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c| 6 +-
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 118
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 1 +
3 files changed, 124 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 2121db05fdb6..40728ef70e20 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -134,6 +134,8 @@ static void intel_pxp_mask_irq(struct intel_gt *gt, u32
mask)
static int intel_pxp_teardown_required_callback(struct drm_i915_private *i915)
{
+ int ret;
+
drm_dbg(&i915->drm, "%s was called\n", __func__);
mutex_lock(&i915->pxp.r0ctx->ctx_mutex);
@@ -141,11 +143,13 @@ static int intel_pxp_teardown_required_callback(struct
drm_i915_private *i915)
i915->pxp.r0ctx->global_state_attacked = true;
i915->pxp.r0ctx->flag_display_hm_surface_keys = false;
+ ret = intel_pxp_sm_terminate_all_active_sessions(i915,
SESSION_TYPE_TYPE0);
+
intel_pxp_destroy_r3ctx_list(i915);
mutex_unlock(&i915->pxp.r0ctx->ctx_mutex);
- return 0;
+ return ret;
}
static int intel_pxp_global_terminate_complete_callback(struct
drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index 994abf5a8d36..37fe2e5af88d 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -893,6 +893,73 @@ static int issue_hw_terminate_for_session(struct
drm_i915_private *i915, int ses
return ret;
}
+static int terminate_all_hw_sessions_with_global_termination(struct
drm_i915_private *i915,
+int session_type)
+{
+ u32 *cmd = NULL;
+ u32 *cmd_ptr = NULL;
+ int cmd_size_in_dw = 0;
+ int ret;
+ int session_index;
+ const int session_num_max = pxp_session_max(session_type);
+
+ drm_dbg(&i915->drm, ">>> %s session_type=[%d]\n", __func__,
session_type);
+
+ if (!i915) {
+ ret = -EINVAL;
+ drm_dbg(&i915->drm, "Failed to %s due to bad params\n",
__func__);
+ goto end;
+ }
+
+ /* Calculate how many bytes need to be alloc */
+ for (session_index = 0; session_index < session_num_max;
session_index++) {
+ if (is_hw_session_in_play(i915, session_type, session_index)) {
+ cmd_size_in_dw += add_pxp_prolog(i915, NULL,
session_type, session_index);
+ cmd_size_in_dw += add_pxp_inline_termination(NULL);
+ }
+ }
+ cmd_size_in_dw += add_pxp_epilog(NULL);
+
+ cmd = kzalloc(cmd_size_in_dw * 4, GFP_KERNEL);
+ if (!cmd) {
+ ret = -ENOMEM;
+ drm_dbg(&i915->drm, "Failed to kzalloc()\n");
+ goto end;
+ }
+
+ /* Program the command */
+ cmd_ptr = cmd;
+ for (session_index = 0; session_index < session_num_max;
session_index++) {
+ if (is_hw_session_in_play(i915, session_type, session_index)) {
+ cmd_ptr += add_pxp_prolog(i915, cmd_ptr, session_type,
session_index);
+ cmd_ptr += add_pxp_inline_termination(cmd_ptr);
+ }
+ }
+ cmd_ptr += add_pxp_epilog(cmd_ptr);
+
+ if (cmd_size_in_dw != (cmd_ptr - cmd)) {
+ ret = -EINVAL;
+ drm_dbg(&i915->drm, "Failed to %s\n", __func__);
+ goto end;
+ }
+
+ if (drm_debug_enabled(DRM_UT_DRIVER)) {
+ print_hex_dump(KERN_DEBUG, "global termination cmd binaries:",
+ DUMP_PREFIX_OFFSET, 4, 4, cmd, cmd_size_in_dw *
4, true);
+ }
+
+ ret = pxp_submit_cmd(i915, cmd, cmd_size_in_dw);
+ if (ret) {
+ drm_dbg(&i915->drm, "Failed to pxp_submit_cmd()\n");
+ goto end;
+ }
+
+end:
+ kfree(cmd);
+ drm_dbg(&i915->drm, "<<< %s ret=[%d]\n", __func__, ret);
+ return ret;
+}
+
/**
* terminate_protected_session - To terminate an active HW session and free
its entry.
* @i915: i915 device handle.
@@ -1076,6 +1143,57 @@ int pxp_sm_terminate_protected_session_unsafe(struct
drm_i915_private *i915, int
return ret;
}
+int intel_pxp_sm_destroy_all_sw_sessions(struct drm_i915_private *i915, int
session_type)
+{
+ int ret = 0;
+ struct pxp_protected_session *current_session, *n;
+
+ list_for_each_entry_safe(current_session, n, pxp_session_list(i915,
session_type), session_list) {
+ ret = pxp
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Big bigjoiner series
== Series Details == Series: drm/i915: Big bigjoiner series URL : https://patchwork.freedesktop.org/series/83837/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_reset.c:1312:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:expected unsigned int [usertype] *s +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gvt/mmio.c:290:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1440:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1494:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/intel_wakeref.c:137:19: warning: context imbalance in 'wakeref_auto_timeout' - unexpected unlock +./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:864:16: warning: trying to copy expression type 31 +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_writ
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Big bigjoiner series
== Series Details == Series: drm/i915: Big bigjoiner series URL : https://patchwork.freedesktop.org/series/83837/ State : warning == Summary == $ dim checkpatch origin/drm-tip 787f109da8f7 drm/i915: Copy the plane hw state directly for Y planes 200e8d85a273 drm/i915: Pass intel_atomic_state around 0bf0fbc51029 drm/i915: Nuke intel_atomic_crtc_state_for_each_plane_state() from skl+ wm code 76f19438bbac drm/i915: Pimp the watermark documentation a bit ffa8b5ec12d6 drm/i915: Precompute can_sagv for each wm level 93f51a472bfb drm/i915: Store plane relative data rate in crtc_state 65f73587d676 drm/i915: Remove skl_adjusted_plane_pixel_rate() 49685428c7ed drm/i915: Pass intel_atomic_state instead of drm_atomic_state 52b4804fb66d drm/i915/dp: Add from_crtc_state to copy color blobs 9c8fa6e879fc drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3. 7b54f1a8cd69 drm/i915: Try to make bigjoiner work in atomic check -:78: WARNING:LONG_LINE: line length of 101 exceeds 100 columns #78: FILE: drivers/gpu/drm/i915/display/intel_display.c:13442: + crtc_state->bigjoiner_linked_crtc); -:124: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided #124: FILE: drivers/gpu/drm/i915/display/intel_display.c:13516: + crtc_state->nv12_planes = crtc_state->c8_planes = crtc_state->update_planes = 0; -:168: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided #168: FILE: drivers/gpu/drm/i915/display/intel_display.c:15135: + slave = new_crtc_state->bigjoiner_linked_crtc = -:202: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided #202: FILE: drivers/gpu/drm/i915/display/intel_display.c:15169: + slave_crtc_state->bigjoiner = master_crtc_state->bigjoiner = false; -:203: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided #203: FILE: drivers/gpu/drm/i915/display/intel_display.c:15170: + slave_crtc_state->bigjoiner_slave = master_crtc_state->bigjoiner_slave = false; -:204: WARNING:LONG_LINE: line length of 106 exceeds 100 columns #204: FILE: drivers/gpu/drm/i915/display/intel_display.c:15171: + slave_crtc_state->bigjoiner_linked_crtc = master_crtc_state->bigjoiner_linked_crtc = NULL; -:204: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided #204: FILE: drivers/gpu/drm/i915/display/intel_display.c:15171: + slave_crtc_state->bigjoiner_linked_crtc = master_crtc_state->bigjoiner_linked_crtc = NULL; total: 0 errors, 2 warnings, 5 checks, 266 lines checked a88c0f99027f drm/i915/dp: Modify VDSC helpers to configure DSC for Bigjoiner slave 0dd1ccb66cf4 drm/i915/dp: Master/Slave enable/disable sequence for bigjoiner 3df07ac789a2 drm/i915: HW state readout for Bigjoiner case -:91: WARNING:LONG_LINE_COMMENT: line length of 106 exceeds 100 columns #91: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:4696: + /* Our own transcoder needs to be disabled when reading it in intel_ddi_read_func_ctl() */ -:93: WARNING:LONG_LINE: line length of 104 exceeds 100 columns #93: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:4698: + pipe_config->cpu_transcoder = (enum transcoder)pipe_config->bigjoiner_linked_crtc->pipe; -:120: WARNING:TABSTOP: Statements should start on a tabstop #120: FILE: drivers/gpu/drm/i915/display/intel_display.c:3634: +struct intel_crtc_state *crtc_state = -:602: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #602: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:853: +#define PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE (1<<1) /* bigjoiner slave, partial readout */ ^ total: 0 errors, 3 warnings, 1 checks, 531 lines checked 76672e003ef1 drm/i915: Add crtcs affected by bigjoiner to the state 6429c52b56f9 drm/i915: Add planes affected by bigjoiner to the state 777362899f26 drm/i915: Get the uapi state from the correct plane when bigjoiner is used 43eaeb52a244 drm/i915: Add bigjoiner aware plane clipping checks a63a8532e9c7 drm/i915: Add debugfs dumping for bigjoiner, v3. -:46: WARNING:LONG_LINE: line length of 132 exceeds 100 columns #46: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs.c:787: + seq_printf(m, "\t\tuapi: [FB:%d] %s,0x%llx,%dx%d, visible=%s, src=" DRM_RECT_FP_FMT ", dst=" DRM_RECT_FMT ", rotation=%s\n", -:57: WARNING:LONG_LINE: line length of 119 exceeds 100 columns #57: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs.c:798: + plane_state->planar_linked_plane->base.base.id, plane_state->planar_linked_plane->base.name, total: 0 errors, 2 warnings, 0 checks, 49 lines checked c7d08ccf925b drm/i915: Disable legacy cursor fastpath for bigjoiner 79ea1ef5dad1 drm/i915: Fix cursor src/dst rectangle with bigjoiner ec5f31858af8 drm/i915: Add bigjoiner state dump 7fd1ad48f2a3 drm/i915: Enable bigjoiner ___ I
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Allow privileged user to map the OA buffer
== Series Details == Series: Allow privileged user to map the OA buffer URL : https://patchwork.freedesktop.org/series/83831/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +drivers/gpu/drm/i915/gt/intel_workarounds.c:167:9: warning: context imbalance in '_wa_list_grow' - different lock contexts for basic block ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Small tweak to put the termination conditions together
== Series Details ==
Series: drm/i915/selftests: Small tweak to put the termination conditions
together
URL : https://patchwork.freedesktop.org/series/83823/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9326 -> Patchwork_18902
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18902/index.html
New tests
-
New tests have been introduced between CI_DRM_9326 and Patchwork_18902:
### New CI tests (1) ###
* boot:
- Statuses : 41 pass(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_18902 that come from known issues:
### IGT changes ###
Issues hit
* igt@prime_vgem@basic-write:
- fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) +1 similar
issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-tgl-y/igt@prime_v...@basic-write.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18902/fi-tgl-y/igt@prime_v...@basic-write.html
Possible fixes
* igt@kms_chamelium@dp-crc-fast:
- fi-cml-u2: [FAIL][3] ([i915#1161] / [i915#262]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18902/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-byt-j1900: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18902/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18902/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
* igt@kms_pipe_crc_basic@read-crc-pipe-c:
- fi-tgl-y: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-tgl-y/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18902/fi-tgl-y/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html
* igt@prime_vgem@basic-read:
- fi-tgl-y: [DMESG-WARN][11] ([i915#402]) -> [PASS][12] +2
similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-tgl-y/igt@prime_v...@basic-read.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18902/fi-tgl-y/igt@prime_v...@basic-read.html
Warnings
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-tgl-y: [DMESG-WARN][13] ([i915#2411]) -> [DMESG-WARN][14]
([i915#1982] / [i915#2411])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-tgl-y/igt@i915_pm_...@basic-pci-d3-state.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18902/fi-tgl-y/igt@i915_pm_...@basic-pci-d3-state.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1161]: https://gitlab.freedesktop.org/drm/intel/issues/1161
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (46 -> 41)
--
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9326 -> Patchwork_18902
CI-20190529: 20190529
CI_DRM_9326: 3048c2a1dcf02422e89930148ffad9e91d690499 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5850: 9748a4a0f93d108955d374a866e60cb962da9b5d @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18902: 9d9489635552253b4a92441e7a637fd768b207a7 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
9d9489635552 drm/i915/selftests: Small tweak to put the termination conditions
together
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18902/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,v11,1/3] drm/i915: Pass intel_atomic_state instead of drm_atomic_state
== Series Details == Series: series starting with [CI,v11,1/3] drm/i915: Pass intel_atomic_state instead of drm_atomic_state URL : https://patchwork.freedesktop.org/series/83816/ State : success == Summary == CI Bug Log - changes from CI_DRM_9326 -> Patchwork_18901 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18901/index.html New tests - New tests have been introduced between CI_DRM_9326 and Patchwork_18901: ### New CI tests (1) ### * boot: - Statuses : 41 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_18901 that come from known issues: ### IGT changes ### Issues hit * igt@core_hotunplug@unbind-rebind: - fi-tgl-u2: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18901/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html * igt@gem_exec_suspend@basic-s3: - fi-cfl-8109u: [PASS][3] -> [INCOMPLETE][4] ([i915#2369] / [i915#2473]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-cfl-8109u/igt@gem_exec_susp...@basic-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18901/fi-cfl-8109u/igt@gem_exec_susp...@basic-s3.html * igt@i915_module_load@reload: - fi-byt-j1900: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-byt-j1900/igt@i915_module_l...@reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18901/fi-byt-j1900/igt@i915_module_l...@reload.html * igt@i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18901/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html * igt@prime_self_import@basic-with_one_bo_two_files: - fi-tgl-y: [PASS][9] -> [DMESG-WARN][10] ([i915#402]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18901/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html Possible fixes * igt@kms_chamelium@dp-crc-fast: - fi-cml-u2: [FAIL][11] ([i915#1161] / [i915#262]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18901/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-n3050: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-bsw-n3050/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18901/fi-bsw-n3050/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html - fi-byt-j1900: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18901/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-icl-u2: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18901/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_pipe_crc_basic@read-crc-pipe-c: - fi-tgl-y: [DMESG-WARN][19] ([i915#1982]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-tgl-y/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18901/fi-tgl-y/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html * igt@prime_vgem@basic-read: - fi-tgl-y: [DMESG-WARN][21] ([i915#402]) -> [PASS][22] +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-tgl-y/igt@prime_v...@basic-read.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18901/fi-tgl-y/igt@prime_v...@basic-read.html Warnings * igt@gem_exec_suspend@basic-s3: - fi-tgl-y: [DMESG-WARN][23] ([i915#2411]) -> [DMESG-WARN][24] ([i915#2411] / [i915#402]) [23]: https://intel-gfx-ci.01
Re: [Intel-gfx] [PATCH 4/7] drm/i915/perf: Whitelist OA report trigger registers
On Fri, 13 Nov 2020 14:12:09 -0800, Umesh Nerlige Ramappa wrote:
>
> > + if (wal->engine)
> > + spin_lock_irqsave(&wal->engine->uncore->lock, flags);
> > +
> > + kfree(wal->list);
>
> if (wal->list)
> kfree(wal->list);
void kfree(const void *objp)
{
...
if (unlikely(ZERO_OR_NULL_PTR(objp)))
return;
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,v11,1/3] drm/i915: Pass intel_atomic_state instead of drm_atomic_state
== Series Details ==
Series: series starting with [CI,v11,1/3] drm/i915: Pass intel_atomic_state
instead of drm_atomic_state
URL : https://patchwork.freedesktop.org/series/83816/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
fe509581680b drm/i915: Pass intel_atomic_state instead of drm_atomic_state
54a85f772310 drm/i915/dp: Add from_crtc_state to copy color blobs
0b30149d1170 drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.
-:192: CHECK:LOGICAL_CONTINUATIONS: Logical continuations should be on the
previous line
#192: FILE: drivers/gpu/drm/i915/display/intel_dp.c:774:
+ if ((target_clock > max_dotclk || mode->hdisplay > 5120)
+ && intel_dp_can_bigjoiner(intel_dp)) {
total: 0 errors, 0 warnings, 1 checks, 211 lines checked
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/7] drm/i915/perf: Whitelist OA report trigger registers
On Fri, Nov 13, 2020 at 10:03:56AM -0800, Umesh Nerlige Ramappa wrote:
OA reports can be triggered into the OA buffer by writing into the
OAREPORTTRIG registers. Whitelist the registers to allow non-privileged
user to trigger reports.
Whitelist registers only if perf_stream_paranoid is set to 0. In
i915_perf_open_ioctl, this setting is checked and the whitelist is
enabled accordingly. On closing the perf fd, the whitelist is removed.
This ensures that the access to the whitelist is gated by
perf_stream_paranoid.
v2:
- Move related change to this patch (Lionel)
- Bump up perf revision (Lionel)
v3: Pardon whitelisted registers for selftest (Umesh)
v4: Document supported gens for the feature (Lionel)
v5: Whitelist registers only if perf_stream_paranoid is set to 0 (Jon)
v6: Move oa whitelist array to i915_perf (Chris)
v7: Fix OA writing beyond the wal->list memory (CI)
v8: Protect write to engine whitelist registers
v9: (Umesh)
- Use uncore->lock to protect write to forcepriv regs
- In case wal->count falls to zero on _wa_remove, make sure you still
clear the registers. Remove wal->count check when applying whitelist.
v10: (Umesh)
- Split patches modifying intel_workarounds
- On some platforms there are no whitelisted regs. intel_engine_resume
applies whitelist on these platforms too and the wal->count gates such
platforms. Bring back the wal->count check.
- intel_engine_allow/deny_user_register_access modifies the engine
whitelist and the wal->count. Use uncore->lock to serialize it with
intel_engine_apply_whitelist.
- Grow the wal->list when adding whitelist registers after driver load.
v11:
- Fix memory leak in _wa_list_grow (Chris)
- Serialize kfree with engine resume using uncore->lock (Umesh)
- Grow the list only if wal->count is not aligned (Umesh)
Signed-off-by: Piotr Maciejewski
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 138 ++
drivers/gpu/drm/i915/gt/intel_workarounds.h | 7 +
.../gpu/drm/i915/gt/intel_workarounds_types.h | 5 +
drivers/gpu/drm/i915/i915_perf.c | 79 +-
drivers/gpu/drm/i915/i915_perf_types.h| 8 +
5 files changed, 234 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 0f9d2a65dcfe..722f11e43dad 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -114,6 +114,80 @@ static void wa_init_finish(struct i915_wa_list *wal)
wal->wa_count, wal->name, wal->engine_name);
}
+static int _wa_index(struct i915_wa_list *wal, i915_reg_t reg)
+{
+ unsigned int addr = i915_mmio_reg_offset(reg);
+ int start = 0, end = wal->count;
+
+ /* addr and wal->list[].reg, both include the R/W flags */
+ while (start < end) {
+ unsigned int mid = start + (end - start) / 2;
+
+ if (i915_mmio_reg_offset(wal->list[mid].reg) < addr)
+ start = mid + 1;
+ else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr)
+ end = mid;
+ else
+ return mid;
+ }
+
+ return -ENOENT;
+}
+
+static int _wa_list_grow(struct i915_wa_list *wal, size_t count)
+{
+ struct i915_wa *list;
+ unsigned long flags;
+
+ list = kmalloc_array(ALIGN(count + 1, WA_LIST_CHUNK), sizeof(*list),
+GFP_KERNEL);
+ if (!list) {
+ DRM_ERROR("No space for workaround init!\n");
+ return -ENOMEM;
+ }
+
+ if (wal->list)
+ memcpy(list, wal->list, sizeof(*list) * count);
+
+ /*
+* Most wal->lists are only modified during driver init and do not
+* require to be serialized with application of workarounds. The one
+* case where this is required is when OA adds/removes whitelist entries
+* from the wal->list and engine resume is in progress.
+*/
+ if (wal->engine)
+ spin_lock_irqsave(&wal->engine->uncore->lock, flags);
+
+ kfree(wal->list);
if (wal->list)
kfree(wal->list);
+ wal->list = list;
+
+ if (wal->engine)
+ spin_unlock_irqrestore(&wal->engine->uncore->lock, flags);
+
+ return 0;
+}
+
+static void _wa_remove(struct i915_wa_list *wal, i915_reg_t reg, u32 flags)
+{
+ int index;
+ struct i915_wa *wa = wal->list;
+
+ reg.reg |= flags;
+
+ index = _wa_index(wal, reg);
+ if (GEM_DEBUG_WARN_ON(index < 0))
+ return;
+
+ memset(wa + index, 0, sizeof(*wa));
+
+ while (index < wal->count - 1) {
+ swap(wa[index], wa[index + 1]);
+ index++;
+ }
+
+ wal->count--;
+}
+
static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
{
unsigned int addr = i915_mmio_reg_offset(wa->reg);
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Eliminate intel_atomic_crtc_state_for_each_plane_state() from skl+ wm code (rev2)
== Series Details ==
Series: drm/i915: Eliminate intel_atomic_crtc_state_for_each_plane_state() from
skl+ wm code (rev2)
URL : https://patchwork.freedesktop.org/series/83589/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9326 -> Patchwork_18900
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_18900:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@gt_pm:
- {fi-tgl-dsi}: [DMESG-FAIL][1] ([i915#1759]) -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-tgl-dsi/igt@i915_selftest@live@gt_pm.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/fi-tgl-dsi/igt@i915_selftest@live@gt_pm.html
New tests
-
New tests have been introduced between CI_DRM_9326 and Patchwork_18900:
### New CI tests (1) ###
* boot:
- Statuses : 41 pass(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_18900 that come from known issues:
### IGT changes ###
Issues hit
* igt@debugfs_test@read_all_entries:
- fi-bsw-nick:[PASS][3] -> [INCOMPLETE][4] ([i915#1250] /
[i915#1436])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-bsw-nick/igt@debugfs_test@read_all_entries.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/fi-bsw-nick/igt@debugfs_test@read_all_entries.html
* igt@gem_sync@basic-all:
- fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +1 similar
issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-tgl-y/igt@gem_s...@basic-all.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/fi-tgl-y/igt@gem_s...@basic-all.html
* igt@i915_module_load@reload:
- fi-icl-u2: [PASS][7] -> [DMESG-WARN][8] ([i915#1982])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-icl-u2/igt@i915_module_l...@reload.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/fi-icl-u2/igt@i915_module_l...@reload.html
- fi-byt-j1900: [PASS][9] -> [DMESG-WARN][10] ([i915#1982])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-byt-j1900/igt@i915_module_l...@reload.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/fi-byt-j1900/igt@i915_module_l...@reload.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: [PASS][11] -> [DMESG-WARN][12] ([i915#1982])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html
* igt@kms_busy@basic@flip:
- fi-kbl-soraka: [PASS][13] -> [DMESG-WARN][14] ([i915#1982])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-kbl-soraka/igt@kms_busy@ba...@flip.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/fi-kbl-soraka/igt@kms_busy@ba...@flip.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-tgl-y: [PASS][15] -> [DMESG-WARN][16] ([i915#1982])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-tgl-y/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/fi-tgl-y/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html
Possible fixes
* igt@kms_chamelium@dp-crc-fast:
- fi-cml-u2: [FAIL][17] ([i915#1161] / [i915#262]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-byt-j1900: [DMESG-WARN][19] ([i915#1982]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
- {fi-kbl-7560u}: [DMESG-WARN][21] ([i915#1982]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-kbl-7560u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/fi-kbl-7560u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2: [DMESG-WARN][2
[Intel-gfx] [PATCH 22/23] drm/i915: Add bigjoiner state dump
From: Ville Syrjälä Add a big of bigjoiner information to the state dump. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 7607bcd9b7fe..8b51bb096b48 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -13345,6 +13345,10 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config, transcoder_name(pipe_config->master_transcoder), pipe_config->sync_mode_slaves_mask); + drm_dbg_kms(&dev_priv->drm, "bigjoiner: %s\n", + pipe_config->bigjoiner_slave ? "slave" : + pipe_config->bigjoiner ? "master" : "no"); + if (pipe_config->has_pch_encoder) intel_dump_m_n_config(pipe_config, "fdi", pipe_config->fdi_lanes, -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 20/23] drm/i915: Disable legacy cursor fastpath for bigjoiner
From: Ville Syrjälä The legacy cursor fastpath code doesn't deal with bigjoiner. Disable the fastpath for now. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index eeb50413fc8e..19e9c3795265 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -16892,9 +16892,11 @@ intel_legacy_cursor_update(struct drm_plane *_plane, /* * When crtc is inactive or there is a modeset pending, * wait for it to complete in the slowpath +* +* FIXME bigjoiner fastpath would be good */ if (!crtc_state->hw.active || needs_modeset(crtc_state) || - crtc_state->update_pipe) + crtc_state->update_pipe || crtc_state->bigjoiner) goto slow; /* -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 19/23] drm/i915: Add debugfs dumping for bigjoiner, v3.
From: Maarten Lankhorst
Dump debugfs and planar links as well, this will make it easier to debug
when things go wrong.
v4:
* Rebase
Changes since v1:
- Report planar slaves as such, now that we have the plane_state switch.
Changes since v2:
- Rebase on top of the new plane format dumping
Signed-off-by: Maarten Lankhorst
Signed-off-by: Manasi Navare
---
.../drm/i915/display/intel_display_debugfs.c | 25 ++-
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 00b79593bcef..ca41e8c00ad7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -755,6 +755,17 @@ static void plane_rotation(char *buf, size_t bufsize,
unsigned int rotation)
rotation);
}
+static const char *plane_visibility(const struct intel_plane_state
*plane_state)
+{
+ if (plane_state->uapi.visible)
+ return "visible";
+
+ if (plane_state->planar_slave)
+ return "planar-slave";
+
+ return "hidden";
+}
+
static void intel_plane_uapi_info(struct seq_file *m, struct intel_plane
*plane)
{
const struct intel_plane_state *plane_state =
@@ -773,13 +784,19 @@ static void intel_plane_uapi_info(struct seq_file *m,
struct intel_plane *plane)
plane_rotation(rot_str, sizeof(rot_str),
plane_state->uapi.rotation);
- seq_printf(m, "\t\tuapi: [FB:%d] %s,0x%llx,%dx%d, src=" DRM_RECT_FP_FMT
", dst=" DRM_RECT_FMT ", rotation=%s\n",
+ seq_printf(m, "\t\tuapi: [FB:%d] %s,0x%llx,%dx%d, visible=%s, src="
DRM_RECT_FP_FMT ", dst=" DRM_RECT_FMT ", rotation=%s\n",
fb ? fb->base.id : 0, fb ? format_name.str : "n/a",
fb ? fb->modifier : 0,
fb ? fb->width : 0, fb ? fb->height : 0,
+ plane_visibility(plane_state),
DRM_RECT_FP_ARG(&src),
DRM_RECT_ARG(&dst),
rot_str);
+
+ if (plane_state->planar_linked_plane)
+ seq_printf(m, "\t\tplanar: Linked to [PLANE:%d:%s] as a %s\n",
+ plane_state->planar_linked_plane->base.base.id,
plane_state->planar_linked_plane->base.name,
+ plane_state->planar_slave ? "slave" : "master");
}
static void intel_plane_hw_info(struct seq_file *m, struct intel_plane *plane)
@@ -875,6 +892,12 @@ static void intel_crtc_info(struct seq_file *m, struct
intel_crtc *crtc)
intel_scaler_info(m, crtc);
}
+ if (crtc_state->bigjoiner)
+ seq_printf(m, "\tLinked to [CRTC:%d:%s] as a %s\n",
+ crtc_state->bigjoiner_linked_crtc->base.base.id,
+ crtc_state->bigjoiner_linked_crtc->base.name,
+ crtc_state->bigjoiner_slave ? "slave" : "master");
+
for_each_intel_encoder_mask(&dev_priv->drm, encoder,
crtc_state->uapi.encoder_mask)
intel_encoder_info(m, crtc, encoder);
--
2.26.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 23/23] drm/i915: Enable bigjoiner
From: Ville Syrjälä Enough plumbing should be in place to throw the bigjoiner switch. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dp.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 857f39779654..3896d08c4177 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -260,9 +260,6 @@ bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp) struct intel_encoder *encoder = &intel_dig_port->base; struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - /* FIXME remove once everything is in place */ - return false; - return INTEL_GEN(dev_priv) >= 12 || (INTEL_GEN(dev_priv) == 11 && encoder->port != PORT_A); -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 21/23] drm/i915: Fix cursor src/dst rectangle with bigjoiner
From: Ville Syrjälä
We can't call drm_plane_state_src() this late for the slave plane since
it would consult the wrong uapi state. We've alreayd done the correct
uapi->hw copy earlier, so let's just preserve the unclipped src/dst
rects using a temp copy across the intel_atomic_plane_check_clipping()
call.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 19e9c3795265..7607bcd9b7fe 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11651,6 +11651,8 @@ static int intel_check_cursor(struct intel_crtc_state
*crtc_state,
{
const struct drm_framebuffer *fb = plane_state->hw.fb;
struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
+ const struct drm_rect src = plane_state->uapi.src;
+ const struct drm_rect dst = plane_state->uapi.dst;
int ret;
if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
@@ -11666,8 +11668,8 @@ static int intel_check_cursor(struct intel_crtc_state
*crtc_state,
return ret;
/* Use the unclipped src/dst rectangles, which we program to hw */
- plane_state->uapi.src = drm_plane_state_src(&plane_state->uapi);
- plane_state->uapi.dst = drm_plane_state_dest(&plane_state->uapi);
+ plane_state->uapi.src = src;
+ plane_state->uapi.dst = dst;
ret = intel_cursor_check_surface(plane_state);
if (ret)
--
2.26.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 18/23] drm/i915: Add bigjoiner aware plane clipping checks
From: Maarten Lankhorst
We need to look at hw.fb for the framebuffer, and add the translation
for the slave_plane_state. With these changes we set the correct
rectangle on the bigjoiner slave, and don't set incorrect
src/dst/visibility on the slave plane.
v2:
* Manual rebase (Manasi)
v3:
* hw.rotation instead of uapi.rotation (Ville)
Signed-off-by: Maarten Lankhorst
Signed-off-by: Manasi Navare
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 60 +++
.../gpu/drm/i915/display/intel_atomic_plane.h | 4 ++
drivers/gpu/drm/i915/display/intel_display.c | 19 +++---
drivers/gpu/drm/i915/display/intel_sprite.c | 21 +++
4 files changed, 80 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 7abb0e3d6c0b..7e9f84b00859 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -271,6 +271,9 @@ void intel_plane_copy_uapi_to_hw_state(struct
intel_plane_state *plane_state,
plane_state->hw.color_encoding = from_plane_state->uapi.color_encoding;
plane_state->hw.color_range = from_plane_state->uapi.color_range;
plane_state->hw.scaling_filter = from_plane_state->uapi.scaling_filter;
+
+ plane_state->uapi.src = drm_plane_state_src(&from_plane_state->uapi);
+ plane_state->uapi.dst = drm_plane_state_dest(&from_plane_state->uapi);
}
void intel_plane_copy_hw_state(struct intel_plane_state *plane_state,
@@ -514,6 +517,63 @@ void i9xx_update_planes_on_crtc(struct intel_atomic_state
*state,
}
}
+int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state,
+ struct intel_crtc_state *crtc_state,
+ int min_scale, int max_scale,
+ bool can_position)
+{
+ struct drm_framebuffer *fb = plane_state->hw.fb;
+ struct drm_rect *src = &plane_state->uapi.src;
+ struct drm_rect *dst = &plane_state->uapi.dst;
+ unsigned int rotation = plane_state->hw.rotation;
+ struct drm_rect clip = {};
+ int hscale, vscale;
+
+ if (!fb) {
+ plane_state->uapi.visible = false;
+ return 0;
+ }
+
+ drm_rect_rotate(src, fb->width << 16, fb->height << 16, rotation);
+
+ /* Check scaling */
+ hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
+ vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
+ if (hscale < 0 || vscale < 0) {
+ DRM_DEBUG_KMS("Invalid scaling of plane\n");
+ drm_rect_debug_print("src: ", src, true);
+ drm_rect_debug_print("dst: ", dst, false);
+ return -ERANGE;
+ }
+
+ if (crtc_state->hw.enable) {
+ clip.x2 = crtc_state->pipe_src_w;
+ clip.y2 = crtc_state->pipe_src_h;
+ }
+
+ /* right side of the image is on the slave crtc, adjust dst to match */
+ if (crtc_state->bigjoiner_slave)
+ drm_rect_translate(dst, -crtc_state->pipe_src_w, 0);
+
+ /*
+* FIXME: This might need further adjustment for seamless scaling
+* with phase information, for the 2p2 and 2p1 scenarios.
+*/
+ plane_state->uapi.visible = drm_rect_clip_scaled(src, dst, &clip);
+
+ drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16, rotation);
+
+ if (!can_position && plane_state->uapi.visible &&
+ !drm_rect_equals(dst, &clip)) {
+ DRM_DEBUG_KMS("Plane must cover entire CRTC\n");
+ drm_rect_debug_print("dst: ", dst, false);
+ drm_rect_debug_print("clip: ", &clip, false);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
const struct drm_plane_helper_funcs intel_plane_helper_funcs = {
.prepare_fb = intel_prepare_plane_fb,
.cleanup_fb = intel_cleanup_plane_fb,
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index 5cae9db41062..5c78a087ed86 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -55,6 +55,10 @@ int intel_plane_atomic_calc_changes(const struct
intel_crtc_state *old_crtc_stat
int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
struct intel_plane *plane,
bool *need_cdclk_calc);
+int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state,
+ struct intel_crtc_state *crtc_state,
+ int min_scale, int max_scale,
+ bool can_position);
void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
struct intel_plane_state *plane_state);
diff --git a/drivers
[Intel-gfx] [PATCH 12/23] drm/i915/dp: Modify VDSC helpers to configure DSC for Bigjoiner slave
From: Manasi Navare
Make vdsc work when no output is enabled. The big joiner needs VDSC
on the slave, so enable it and set the appropriate bits.
So remove encoder usage from dsc functions.
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 9 +-
drivers/gpu/drm/i915/display/intel_display.c | 3 +
drivers/gpu/drm/i915/display/intel_dp.c | 6 +-
drivers/gpu/drm/i915/display/intel_vdsc.c| 197 ++-
drivers/gpu/drm/i915/display/intel_vdsc.h| 6 +-
6 files changed, 108 insertions(+), 115 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index 096652921453..0fecf372be11 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1492,7 +1492,7 @@ static void gen11_dsi_get_config(struct intel_encoder
*encoder,
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
- intel_dsc_get_config(encoder, pipe_config);
+ intel_dsc_get_config(pipe_config);
/* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
pipe_config->port_clock = intel_dpll_get_freq(i915,
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index d4b1b73c7aab..439b92710fe6 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2295,13 +2295,6 @@ static void intel_ddi_get_power_domains(struct
intel_encoder *encoder,
intel_phy_is_tc(dev_priv, phy))
intel_display_power_get(dev_priv,
intel_ddi_main_link_aux_domain(dig_port));
-
- /*
-* VDSC power is needed when DSC is enabled
-*/
- if (crtc_state->dsc.compression_enable)
- intel_display_power_get(dev_priv,
- intel_dsc_power_domain(crtc_state));
}
void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder,
@@ -4576,7 +4569,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))
return;
- intel_dsc_get_config(encoder, pipe_config);
+ intel_dsc_get_config(pipe_config);
temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
if (temp & TRANS_DDI_PHSYNC)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index e2baf342a112..aea2ff3ef8c4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7508,6 +7508,9 @@ static u64 get_crtc_power_domains(struct intel_crtc_state
*crtc_state)
if (crtc_state->shared_dpll)
mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
+ if (crtc_state->dsc.compression_enable)
+ mask |= BIT_ULL(intel_dsc_power_domain(crtc_state));
+
return mask;
}
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 9430caf053cd..857f39779654 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2103,12 +2103,10 @@ static bool intel_dp_supports_fec(struct intel_dp
*intel_dp,
static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
- struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
-
- if (!intel_dp_is_edp(intel_dp) && !crtc_state->fec_enable)
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) &&
!crtc_state->fec_enable)
return false;
- return intel_dsc_source_support(encoder, crtc_state) &&
+ return intel_dsc_source_support(crtc_state) &&
drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
}
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
b/drivers/gpu/drm/i915/display/intel_vdsc.c
index c5735c365659..e2716a67b281 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -332,11 +332,10 @@ static const struct rc_parameters *get_rc_params(u16
compressed_bpp,
return &rc_parameters[row_index][column_index];
}
-bool intel_dsc_source_support(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state)
+bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
{
const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
enum pipe pipe = crtc->pipe;
@@ -490,11 +489,10 @@ intel_dsc_power_domain(const struct intel_c
[Intel-gfx] [PATCH 17/23] drm/i915: Get the uapi state from the correct plane when bigjoiner is used
From: Ville Syrjälä
When using bigjoiner userspace is only controlling the "master"
plane, so use its uapi state for the "slave" plane as well.
hw.crtc needs a bit of magic since we don't want to copy that from
the uapi state (as it points to the wrong pipe for the "slave
" plane). Instead we pass the right crtc in explicitly but only
assign it when the uapi state indicates the plane to be logically
enabled (ie. uapi.crtc != NULL).
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 59 +--
.../gpu/drm/i915/display/intel_atomic_plane.h | 3 +-
drivers/gpu/drm/i915/display/intel_display.c | 5 +-
3 files changed, 46 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index f47558efb3c2..7abb0e3d6c0b 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -247,11 +247,19 @@ static void intel_plane_clear_hw_state(struct
intel_plane_state *plane_state)
}
void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
- const struct intel_plane_state
*from_plane_state)
+ const struct intel_plane_state
*from_plane_state,
+ struct intel_crtc *crtc)
{
intel_plane_clear_hw_state(plane_state);
- plane_state->hw.crtc = from_plane_state->uapi.crtc;
+ /*
+* For the bigjoiner slave uapi.crtc will point at
+* the master crtc. So we explicitly assign the right
+* slave crtc to hw.crtc. uapi.crtc!=NULL simply indicates
+* the plane is logically enabled on the uapi level.
+*/
+ plane_state->hw.crtc = from_plane_state->uapi.crtc ? &crtc->base : NULL;
+
plane_state->hw.fb = from_plane_state->uapi.fb;
if (plane_state->hw.fb)
drm_framebuffer_get(plane_state->hw.fb);
@@ -331,15 +339,16 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
old_plane_state,
new_plane_state);
}
-static struct intel_crtc *
-get_crtc_from_states(const struct intel_plane_state *old_plane_state,
-const struct intel_plane_state *new_plane_state)
+static struct intel_plane *
+intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id)
{
- if (new_plane_state->uapi.crtc)
- return to_intel_crtc(new_plane_state->uapi.crtc);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ struct intel_plane *plane;
- if (old_plane_state->uapi.crtc)
- return to_intel_crtc(old_plane_state->uapi.crtc);
+ for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
+ if (plane->id == plane_id)
+ return plane;
+ }
return NULL;
}
@@ -347,23 +356,37 @@ get_crtc_from_states(const struct intel_plane_state
*old_plane_state,
int intel_plane_atomic_check(struct intel_atomic_state *state,
struct intel_plane *plane)
{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
struct intel_plane_state *new_plane_state =
intel_atomic_get_new_plane_state(state, plane);
const struct intel_plane_state *old_plane_state =
intel_atomic_get_old_plane_state(state, plane);
- struct intel_crtc *crtc =
- get_crtc_from_states(old_plane_state, new_plane_state);
- const struct intel_crtc_state *old_crtc_state;
- struct intel_crtc_state *new_crtc_state;
+ const struct intel_plane_state *new_master_plane_state;
+ struct intel_crtc *crtc = intel_get_crtc_for_pipe(i915, plane->pipe);
+ const struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(state, crtc);
+ struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+
+ if (new_crtc_state && new_crtc_state->bigjoiner_slave) {
+ struct intel_plane *master_plane =
+
intel_crtc_get_plane(new_crtc_state->bigjoiner_linked_crtc,
+plane->id);
+
+ new_master_plane_state =
+ intel_atomic_get_new_plane_state(state, master_plane);
+ } else {
+ new_master_plane_state = new_plane_state;
+ }
+
+ intel_plane_copy_uapi_to_hw_state(new_plane_state,
+ new_master_plane_state,
+ crtc);
- intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state);
new_plane_state->uapi.visible = false;
- if (!crtc)
+ if (!new_crtc_state)
return 0;
- old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
-
[Intel-gfx] [PATCH 04/23] drm/i915: Pimp the watermark documentation a bit
From: Ville Syrjälä
Document what each of the "raw" vs. "optimal" vs. "intermediate"
watermarks do.
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/intel_display_types.h| 48 ++-
1 file changed, 25 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 3d91b116aadc..0c1df34a0cce 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -737,25 +737,34 @@ struct g4x_wm_state {
struct intel_crtc_wm_state {
union {
+ /*
+* raw:
+* The "raw" watermark values produced by the formula
+* given the plane's current state. They do not consider
+* how much FIFO is actually allocated for each plane.
+*
+* optimal:
+* The "optimal" watermark values given the current
+* state of the planes and the amount of FIFO
+* allocated to each, ignoring any previous state
+* of the planes.
+*
+* intermediate:
+* The "intermediate" watermark values when transitioning
+* between the old and new "optimal" values. Used when
+* the watermark registers are single buffered and hence
+* their state changes asynchronously with regards to the
+* actual plane registers. These are essentially the
+* worst case combination of the old and new "optimal"
+* watermarks, which are therefore safe to use when the
+* plane is in either its old or new state.
+*/
struct {
- /*
-* Intermediate watermarks; these can be
-* programmed immediately since they satisfy
-* both the current configuration we're
-* switching away from and the new
-* configuration we're switching to.
-*/
struct intel_pipe_wm intermediate;
-
- /*
-* Optimal watermarks, programmed post-vblank
-* when this state is committed.
-*/
struct intel_pipe_wm optimal;
} ilk;
struct {
- /* "raw" watermarks */
struct skl_pipe_wm raw;
/* gen9+ only needs 1-step wm programming */
struct skl_pipe_wm optimal;
@@ -765,22 +774,15 @@ struct intel_crtc_wm_state {
} skl;
struct {
- /* "raw" watermarks (not inverted) */
- struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
- /* intermediate watermarks (inverted) */
- struct vlv_wm_state intermediate;
- /* optimal watermarks (inverted) */
- struct vlv_wm_state optimal;
- /* display FIFO split */
+ struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS]; /* not
inverted */
+ struct vlv_wm_state intermediate; /* inverted */
+ struct vlv_wm_state optimal; /* inverted */
struct vlv_fifo_state fifo_state;
} vlv;
struct {
- /* "raw" watermarks */
struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
- /* intermediate watermarks */
struct g4x_wm_state intermediate;
- /* optimal watermarks */
struct g4x_wm_state optimal;
} g4x;
};
--
2.26.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 03/23] drm/i915: Nuke intel_atomic_crtc_state_for_each_plane_state() from skl+ wm code
From: Ville Syrjälä
intel_atomic_crtc_state_for_each_plane_state() peeks at the
plane's current state without holding the plane's mutex, trusting
that the crtc's mutex will protect it. In practice that does work
since our planes can't move between pipes, but it sets a bad
example. intel_atomic_crtc_state_for_each_plane_state() also
relies on crtc_state.uapi.plane_mask which may be full of lies
when it comes to the bigjoiner stuff, so soon we can't use it as
is anyway. So best to just get rid of it entirely. Which we can
easily do by switching to the g4x/vlv "raw" watermark approach.
Later on we should even be able to move the "raw" watermark
computation into the normal .plane_check() code, leaving only
the merging/clamping of the final watermarks to the later
stages. But that will require adjusting the ilk+ wm code
similarly as well.
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/intel_display_types.h| 2 +
drivers/gpu/drm/i915/intel_pm.c | 41 +++
2 files changed, 27 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 35ab5944a3f7..3d91b116aadc 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -755,6 +755,8 @@ struct intel_crtc_wm_state {
} ilk;
struct {
+ /* "raw" watermarks */
+ struct skl_pipe_wm raw;
/* gen9+ only needs 1-step wm programming */
struct skl_pipe_wm optimal;
struct skl_ddb_entry ddb;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 24813bd3847e..5a04be58e0b9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5480,7 +5480,7 @@ static int skl_build_plane_wm_single(struct
intel_crtc_state *crtc_state,
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
+ struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];
struct skl_wm_params wm_params;
int ret;
@@ -5503,7 +5503,7 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state
*crtc_state,
const struct intel_plane_state *plane_state,
enum plane_id plane_id)
{
- struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
+ struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];
struct skl_wm_params wm_params;
int ret;
@@ -5524,10 +5524,13 @@ static int skl_build_plane_wm(struct intel_crtc_state
*crtc_state,
const struct intel_plane_state *plane_state)
{
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
- const struct drm_framebuffer *fb = plane_state->hw.fb;
enum plane_id plane_id = plane->id;
+ struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
int ret;
+ memset(wm, 0, sizeof(*wm));
+
if (!intel_wm_plane_visible(crtc_state, plane_state))
return 0;
@@ -5549,10 +5552,14 @@ static int skl_build_plane_wm(struct intel_crtc_state
*crtc_state,
static int icl_build_plane_wm(struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- enum plane_id plane_id = to_intel_plane(plane_state->uapi.plane)->id;
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ enum plane_id plane_id = plane->id;
+ struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];
int ret;
+ memset(wm, 0, sizeof(*wm));
+
/* Watermarks calculated in master */
if (plane_state->planar_slave)
return 0;
@@ -5591,19 +5598,18 @@ static int skl_build_pipe_wm(struct intel_atomic_state
*state,
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
- struct intel_plane *plane;
const struct intel_plane_state *plane_state;
- int ret;
+ struct intel_plane *plane;
+ int ret, i;
- /*
-* We'll only calculate watermarks for planes that are actually
-* enabled, so make sure all other planes are set as disabled.
-*/
- memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
-
-
[Intel-gfx] [PATCH 05/23] drm/i915: Precompute can_sagv for each wm level
From: Ville Syrjälä
In order to remove intel_atomic_crtc_state_for_each_plane_state()
from skl_crtc_can_enable_sagv() we can simply precompute whether
each wm level can tolerate the SAGV block time latency or not.
This has the nice side benefit that we remove the duplicated
wm level latency calculation. In fact the copy of that code
we had in skl_crtc_can_enable_sagv() didn't even handle
WaIncreaseLatencyIPCEnabled/Display WA #1141 whereas the copy
in skl_compute_plane_wm() did. So now we just have the one
copy which handles all the w/as.
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/intel_pm.c | 21 +++
2 files changed, 9 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 0c1df34a0cce..86de89d621d8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -686,6 +686,7 @@ struct skl_wm_level {
u8 plane_res_l;
bool plane_en;
bool ignore_lines;
+ bool can_sagv;
};
struct skl_plane_wm {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5a04be58e0b9..6e64580a1a8c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3873,9 +3873,7 @@ static bool skl_crtc_can_enable_sagv(const struct
intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- struct intel_plane *plane;
- const struct intel_plane_state *plane_state;
- int level, latency;
+ enum plane_id plane_id;
if (!intel_has_sagv(dev_priv))
return false;
@@ -3886,9 +3884,10 @@ static bool skl_crtc_can_enable_sagv(const struct
intel_crtc_state *crtc_state)
if (crtc_state->hw.pipe_mode.flags & DRM_MODE_FLAG_INTERLACE)
return false;
- intel_atomic_crtc_state_for_each_plane_state(plane, plane_state,
crtc_state) {
+ for_each_plane_id_on_crtc(crtc, plane_id) {
const struct skl_plane_wm *wm =
- &crtc_state->wm.skl.optimal.planes[plane->id];
+ &crtc_state->wm.skl.optimal.planes[plane_id];
+ int level;
/* Skip this plane if it's not enabled */
if (!wm->wm[0].plane_en)
@@ -3899,19 +3898,12 @@ static bool skl_crtc_can_enable_sagv(const struct
intel_crtc_state *crtc_state)
!wm->wm[level].plane_en; --level)
{ }
- latency = dev_priv->wm.skl_latency[level];
-
- if (skl_needs_memory_bw_wa(dev_priv) &&
- plane_state->uapi.fb->modifier ==
- I915_FORMAT_MOD_X_TILED)
- latency += 15;
-
/*
* If any of the planes on this pipe don't enable wm levels that
* incur memory latencies higher than sagv_block_time_us we
* can't enable SAGV.
*/
- if (latency < dev_priv->sagv_block_time_us)
+ if (!wm->wm[level].can_sagv)
return false;
}
@@ -5375,6 +5367,9 @@ static void skl_compute_plane_wm(const struct
intel_crtc_state *crtc_state,
/* Bspec says: value >= plane ddb allocation -> invalid, hence the +1
here */
result->min_ddb_alloc = max(min_ddb_alloc, res_blocks) + 1;
result->plane_en = true;
+
+ if (INTEL_GEN(dev_priv) < 12)
+ result->can_sagv = latency >= dev_priv->sagv_block_time_us;
}
static void
--
2.26.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 10/23] drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.
From: Maarten Lankhorst
Small changes to intel_dp_mode_valid(), allow listing modes that
can only be supported in the bigjoiner configuration, which is
not supported yet.
v13:
* Allow bigjoiner if hdisplay >5120
v12:
* slice_count logic simplify (Ville)
* Fix unnecessary changes in downstream_mode_valid (Ville)
v11:
* Make intel_dp_can_bigjoiner non static
so it can be used in intel_display (Manasi)
v10:
* Simplify logic (Ville)
* Allow bigjoiner on edp (Ville)
v9:
* Restric Bigjoiner on PORT A (Ville)
v8:
* use source dotclock for max dotclock (Manasi)
v7:
* Add can_bigjoiner() helper (Ville)
* Pass bigjoiner to plane_size validation (Ville)
v6:
* Rebase after dp_downstream mode valid changes (Manasi)
v5:
* Increase max plane width to support 8K with bigjoiner (Maarten)
v4:
* Rebase (Manasi)
Changes since v1:
- Disallow bigjoiner on eDP.
Changes since v2:
- Rename intel_dp_downstream_max_dotclock to intel_dp_max_dotclock,
and split off the downstream and source checking to its own function.
(Ville)
v3:
* Rebase (Manasi)
Signed-off-by: Manasi Navare
Signed-off-by: Maarten Lankhorst
[vsyrjala:
* Keep bigjoiner disabled until everything is ready
* Appease checkpatch]
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +-
drivers/gpu/drm/i915/display/intel_display.h | 3 +-
drivers/gpu/drm/i915/display/intel_dp.c | 81
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
drivers/gpu/drm/i915/display/intel_dsi.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdmi.c| 2 +-
7 files changed, 76 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index be56fe782b41..004ae95ede19 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -17741,7 +17741,8 @@ intel_mode_valid(struct drm_device *dev,
enum drm_mode_status
intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
- const struct drm_display_mode *mode)
+ const struct drm_display_mode *mode,
+ bool bigjoiner)
{
int plane_width_max, plane_height_max;
@@ -17758,7 +17759,7 @@ intel_mode_valid_max_plane_size(struct drm_i915_private
*dev_priv,
* too big for that.
*/
if (INTEL_GEN(dev_priv) >= 11) {
- plane_width_max = 5120;
+ plane_width_max = 5120 << bigjoiner;
plane_height_max = 4320;
} else {
plane_width_max = 5120;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index 6be14e8571aa..5e0d42d82c11 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -513,7 +513,8 @@ u32 intel_plane_fb_max_stride(struct drm_i915_private
*dev_priv,
bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
enum drm_mode_status
intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
- const struct drm_display_mode *mode);
+ const struct drm_display_mode *mode,
+ bool bigjoiner);
enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index ec8359f03aaf..5ad59610eb12 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -254,6 +254,20 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes)
return max_link_clock * max_lanes;
}
+bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
+{
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct intel_encoder *encoder = &intel_dig_port->base;
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
+ /* FIXME remove once everything is in place */
+ return false;
+
+ return INTEL_GEN(dev_priv) >= 12 ||
+ (INTEL_GEN(dev_priv) == 11 &&
+encoder->port != PORT_A);
+}
+
static int cnl_max_source_rate(struct intel_dp *intel_dp)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
@@ -519,7 +533,8 @@ small_joiner_ram_size_bits(struct drm_i915_private *i915)
static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
u32 link_clock, u32 lane_count,
- u32 mode_clock, u32 mode_hdisplay)
+ u32 mode_clock, u32 mode_hdisplay,
+ bool bigjoiner)
{
u32 bits_per_pixel, max_bpp_small_joiner_ram;
int i;
@@ -
[Intel-gfx] [PATCH 15/23] drm/i915: Add crtcs affected by bigjoiner to the state
From: Ville Syrjälä
Make sure both crtcs participating in the bigjoiner stuff
are in the state.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 25
1 file changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 07bee5caacfe..465877097582 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15422,6 +15422,27 @@ static int intel_atomic_check_async(struct
intel_atomic_state *state)
return 0;
}
+static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state)
+{
+ const struct intel_crtc_state *crtc_state;
+ struct intel_crtc *crtc;
+ int i;
+
+ for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
+ struct intel_crtc_state *linked_crtc_state;
+
+ if (!crtc_state->bigjoiner)
+ continue;
+
+ linked_crtc_state = intel_atomic_get_crtc_state(&state->base,
+
crtc_state->bigjoiner_linked_crtc);
+ if (IS_ERR(linked_crtc_state))
+ return PTR_ERR(linked_crtc_state);
+ }
+
+ return 0;
+}
+
/**
* intel_atomic_check - validate state object
* @dev: drm device
@@ -15447,6 +15468,10 @@ static int intel_atomic_check(struct drm_device *dev,
if (ret)
goto fail;
+ ret = intel_bigjoiner_add_affected_crtcs(state);
+ if (ret)
+ goto fail;
+
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
if (!needs_modeset(new_crtc_state)) {
--
2.26.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 14/23] drm/i915: HW state readout for Bigjoiner case
From: Manasi Navare
Skip iterating over bigjoiner slaves, only the master has the state we
care about.
Add the width of the bigjoiner slave to the reconstructed fb.
Hide the bigjoiner slave to userspace, and double the mode on bigjoiner
master.
And last, disable bigjoiner slave from primary if reconstruction fails.
v3:
* Fix the ddi_get_config slave error (Ankit Nautiyal)
v2:
* Unsupported bigjoiner config for initial fb (Ville)
Signed-off-by: Manasi Navare
[vsyrjala:
* Don't do any hw->uapi state copy for bigjoiner slave
* We still have hw.mode so no need to pass it in
* Appease checkpatch]
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/icl_dsi.c| 2 -
drivers/gpu/drm/i915/display/intel_ddi.c | 37 ++-
drivers/gpu/drm/i915/display/intel_display.c | 291 --
.../drm/i915/display/intel_display_types.h| 1 +
4 files changed, 230 insertions(+), 101 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index 0fecf372be11..104a423e0cd5 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1492,8 +1492,6 @@ static void gen11_dsi_get_config(struct intel_encoder
*encoder,
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
- intel_dsc_get_config(pipe_config);
-
/* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
pipe_config->port_clock = intel_dpll_get_freq(i915,
pipe_config->shared_dpll);
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 9c4ad0392025..aa444c428949 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4576,20 +4576,14 @@ static void bdw_get_trans_port_sync_config(struct
intel_crtc_state *crtc_state)
crtc_state->sync_mode_slaves_mask);
}
-void intel_ddi_get_config(struct intel_encoder *encoder,
- struct intel_crtc_state *pipe_config)
+static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
+ struct intel_crtc_state *pipe_config)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
u32 temp, flags = 0;
- /* XXX: DSI transcoder paranoia */
- if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))
- return;
-
- intel_dsc_get_config(pipe_config);
-
temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
if (temp & TRANS_DDI_PHSYNC)
flags |= DRM_MODE_FLAG_PHSYNC;
@@ -4683,6 +4677,30 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
default:
break;
}
+}
+
+void intel_ddi_get_config(struct intel_encoder *encoder,
+ struct intel_crtc_state *pipe_config)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
+
+ /* XXX: DSI transcoder paranoia */
+ if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))
+ return;
+
+ if (pipe_config->bigjoiner_slave) {
+ /* read out pipe settings from master */
+ enum transcoder save = pipe_config->cpu_transcoder;
+
+ /* Our own transcoder needs to be disabled when reading it in
intel_ddi_read_func_ctl() */
+ WARN_ON(pipe_config->output_types);
+ pipe_config->cpu_transcoder = (enum
transcoder)pipe_config->bigjoiner_linked_crtc->pipe;
+ intel_ddi_read_func_ctl(encoder, pipe_config);
+ pipe_config->cpu_transcoder = save;
+ } else {
+ intel_ddi_read_func_ctl(encoder, pipe_config);
+ }
pipe_config->has_audio =
intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
@@ -4708,7 +4726,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
}
- intel_ddi_clock_get(encoder, pipe_config);
+ if (!pipe_config->bigjoiner_slave)
+ intel_ddi_clock_get(encoder, pipe_config);
if (IS_GEN9_LP(dev_priv))
pipe_config->lane_lat_optim_mask =
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 60669bef659f..07bee5caacfe 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3631,6 +3631,8 @@ intel_find_initial_plane_obj(struct intel_crtc
*intel_crtc,
struct intel_plane *intel_plane = to_intel_plane(primary);
[Intel-gfx] [PATCH 09/23] drm/i915/dp: Add from_crtc_state to copy color blobs
From: Manasi Navare
No functional changes here, just adds a from_crtc_state
as a prep for bigjoiner
v2:
* More prep with intel_atomic_state (Ville)
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_atomic.c | 9 +
drivers/gpu/drm/i915/display/intel_atomic.h | 3 ++-
drivers/gpu/drm/i915/display/intel_display.c | 4 +++-
3 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
b/drivers/gpu/drm/i915/display/intel_atomic.c
index 63d8d6840655..e00fdc47c0eb 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -269,14 +269,15 @@ void intel_crtc_free_hw_state(struct intel_crtc_state
*crtc_state)
intel_crtc_put_color_blobs(crtc_state);
}
-void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state)
+void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state,
+const struct intel_crtc_state *from_crtc_state)
{
drm_property_replace_blob(&crtc_state->hw.degamma_lut,
- crtc_state->uapi.degamma_lut);
+ from_crtc_state->uapi.degamma_lut);
drm_property_replace_blob(&crtc_state->hw.gamma_lut,
- crtc_state->uapi.gamma_lut);
+ from_crtc_state->uapi.gamma_lut);
drm_property_replace_blob(&crtc_state->hw.ctm,
- crtc_state->uapi.ctm);
+ from_crtc_state->uapi.ctm);
}
/**
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h
b/drivers/gpu/drm/i915/display/intel_atomic.h
index 285de07011dc..62a3365ed5e6 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic.h
@@ -43,7 +43,8 @@ struct drm_crtc_state *intel_crtc_duplicate_state(struct
drm_crtc *crtc);
void intel_crtc_destroy_state(struct drm_crtc *crtc,
struct drm_crtc_state *state);
void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state);
-void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state);
+void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state,
+const struct intel_crtc_state
*from_crtc_state);
struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
void intel_atomic_state_free(struct drm_atomic_state *state);
void intel_atomic_state_clear(struct drm_atomic_state *state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index df1f22fc4369..be56fe782b41 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13421,7 +13421,9 @@ static void
intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state,
struct intel_crtc_state *crtc_state)
{
- intel_crtc_copy_color_blobs(crtc_state);
+ const struct intel_crtc_state *from_crtc_state = crtc_state;
+
+ intel_crtc_copy_color_blobs(crtc_state, from_crtc_state);
}
static void
--
2.26.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 08/23] drm/i915: Pass intel_atomic_state instead of drm_atomic_state
From: Manasi Navare
No functional changes, to align with previous cleanups pass
intel_atomic_state instead of drm_atomic_state.
Also pass this intel_atomic_state with crtc_state to
some of the atomic_check functions.
v2:
* Squash some changes from next patch (Ville)
Signed-off-by: Manasi Navare
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 32 +++-
1 file changed, 18 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 62d96e6946e6..df1f22fc4369 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -12630,7 +12630,7 @@ static bool encoders_cloneable(const struct
intel_encoder *a,
b->cloneable & (1 << a->type));
}
-static bool check_single_encoder_cloning(struct drm_atomic_state *state,
+static bool check_single_encoder_cloning(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder)
{
@@ -12639,7 +12639,7 @@ static bool check_single_encoder_cloning(struct
drm_atomic_state *state,
struct drm_connector_state *connector_state;
int i;
- for_each_new_connector_in_state(state, connector, connector_state, i) {
+ for_each_new_connector_in_state(&state->base, connector,
connector_state, i) {
if (connector_state->crtc != &crtc->base)
continue;
@@ -13418,20 +13418,23 @@ static bool check_digital_port_conflicts(struct
intel_atomic_state *state)
}
static void
-intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_crtc_state *crtc_state)
+intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state,
+ struct intel_crtc_state *crtc_state)
{
intel_crtc_copy_color_blobs(crtc_state);
}
static void
-intel_crtc_copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
+intel_crtc_copy_uapi_to_hw_state(struct intel_atomic_state *state,
+struct intel_crtc_state *crtc_state)
{
crtc_state->hw.enable = crtc_state->uapi.enable;
crtc_state->hw.active = crtc_state->uapi.active;
crtc_state->hw.mode = crtc_state->uapi.mode;
crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;
- intel_crtc_copy_uapi_to_hw_state_nomodeset(crtc_state);
+
+ intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc_state);
}
static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state
*crtc_state)
@@ -13454,7 +13457,8 @@ static void intel_crtc_copy_hw_to_uapi_state(struct
intel_crtc_state *crtc_state
}
static int
-intel_crtc_prepare_cleared_state(struct intel_crtc_state *crtc_state)
+intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
+struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -13486,16 +13490,16 @@ intel_crtc_prepare_cleared_state(struct
intel_crtc_state *crtc_state)
memcpy(crtc_state, saved_state, sizeof(*crtc_state));
kfree(saved_state);
- intel_crtc_copy_uapi_to_hw_state(crtc_state);
+ intel_crtc_copy_uapi_to_hw_state(state, crtc_state);
return 0;
}
static int
-intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
+intel_modeset_pipe_config(struct intel_atomic_state *state,
+ struct intel_crtc_state *pipe_config)
{
struct drm_crtc *crtc = pipe_config->uapi.crtc;
- struct drm_atomic_state *state = pipe_config->uapi.state;
struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
struct drm_connector *connector;
struct drm_connector_state *connector_state;
@@ -13537,7 +13541,7 @@ intel_modeset_pipe_config(struct intel_crtc_state
*pipe_config)
&pipe_config->pipe_src_w,
&pipe_config->pipe_src_h);
- for_each_new_connector_in_state(state, connector, connector_state, i) {
+ for_each_new_connector_in_state(&state->base, connector,
connector_state, i) {
struct intel_encoder *encoder =
to_intel_encoder(connector_state->best_encoder);
@@ -13575,7 +13579,7 @@ intel_modeset_pipe_config(struct intel_crtc_state
*pipe_config)
* adjust it according to limitations or connector properties, and also
* a chance to reject the mode entirely.
*/
- for_each_new_connector_in_state(state, connector, connector_state, i) {
+ for_each_new_connector_in_state(&state->base, connector,
connector_state, i) {
struct intel_encoder *encoder
[Intel-gfx] [PATCH 16/23] drm/i915: Add planes affected by bigjoiner to the state
From: Ville Syrjälä
Make sure both the bigjoiner "master" and "slave" plane are
in the state whenever either of them is in the state.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 42
1 file changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 465877097582..1118ff73c0d4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15069,6 +15069,44 @@ static bool active_planes_affects_min_cdclk(struct
drm_i915_private *dev_priv)
IS_IVYBRIDGE(dev_priv) || (INTEL_GEN(dev_priv) >= 11);
}
+static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_crtc *other)
+{
+ const struct intel_plane_state *plane_state;
+ struct intel_plane *plane;
+ u8 plane_ids = 0;
+ int i;
+
+ for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
+ if (plane->pipe == crtc->pipe)
+ plane_ids |= BIT(plane->id);
+ }
+
+ return intel_crtc_add_planes_to_state(state, other, plane_ids);
+}
+
+static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state
*state)
+{
+ const struct intel_crtc_state *crtc_state;
+ struct intel_crtc *crtc;
+ int i;
+
+ for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
+ int ret;
+
+ if (!crtc_state->bigjoiner)
+ continue;
+
+ ret = intel_crtc_add_bigjoiner_planes(state, crtc,
+
crtc_state->bigjoiner_linked_crtc);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
static int intel_atomic_check_planes(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
@@ -15082,6 +15120,10 @@ static int intel_atomic_check_planes(struct
intel_atomic_state *state)
if (ret)
return ret;
+ ret = intel_bigjoiner_add_affected_planes(state);
+ if (ret)
+ return ret;
+
for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
ret = intel_plane_atomic_check(state, plane);
if (ret) {
--
2.26.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 06/23] drm/i915: Store plane relative data rate in crtc_state
From: Ville Syrjälä
Store the relative data rate for planes in the crtc state
so that we don't have to use
intel_atomic_crtc_state_for_each_plane_state() to compute
it even for the planes that are no part of the current state.
Should probably just nuke this stuff entirely an use the normal
plane data rate instead. The two are slightly different since this
relative data rate doesn't factor in the actual pixel clock, so
it's a bit odd thing to even call a "data rate". And since the
watermarks are computed based on the actual data rate anyway
I don't really see what the point of this relative data rate
is. But that's for the future...
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/intel_display_types.h| 4 +
drivers/gpu/drm/i915/intel_pm.c | 83 ++-
2 files changed, 50 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 86de89d621d8..5bb7adc1ff3e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1031,6 +1031,10 @@ struct intel_crtc_state {
u32 data_rate[I915_MAX_PLANES];
+ /* FIXME unify with data_rate[] */
+ u64 plane_data_rate[I915_MAX_PLANES];
+ u64 uv_plane_data_rate[I915_MAX_PLANES];
+
/* Gamma mode programmed on the pipe */
u32 gamma_mode;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6e64580a1a8c..6ccacd07ab94 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4696,50 +4696,63 @@ skl_plane_relative_data_rate(const struct
intel_crtc_state *crtc_state,
}
static u64
-skl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
-u64 *plane_data_rate,
-u64 *uv_plane_data_rate)
+skl_get_total_relative_data_rate(struct intel_atomic_state *state,
+struct intel_crtc *crtc)
{
- struct intel_plane *plane;
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
const struct intel_plane_state *plane_state;
+ struct intel_plane *plane;
u64 total_data_rate = 0;
+ enum plane_id plane_id;
+ int i;
/* Calculate and cache data rate for each plane */
- intel_atomic_crtc_state_for_each_plane_state(plane, plane_state,
crtc_state) {
- enum plane_id plane_id = plane->id;
- u64 rate;
+ for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
+ if (plane->pipe != crtc->pipe)
+ continue;
+
+ plane_id = plane->id;
/* packed/y */
- rate = skl_plane_relative_data_rate(crtc_state, plane_state, 0);
- plane_data_rate[plane_id] = rate;
- total_data_rate += rate;
+ crtc_state->plane_data_rate[plane_id] =
+ skl_plane_relative_data_rate(crtc_state, plane_state,
0);
/* uv-plane */
- rate = skl_plane_relative_data_rate(crtc_state, plane_state, 1);
- uv_plane_data_rate[plane_id] = rate;
- total_data_rate += rate;
+ crtc_state->uv_plane_data_rate[plane_id] =
+ skl_plane_relative_data_rate(crtc_state, plane_state,
1);
+ }
+
+ for_each_plane_id_on_crtc(crtc, plane_id) {
+ total_data_rate += crtc_state->plane_data_rate[plane_id];
+ total_data_rate += crtc_state->uv_plane_data_rate[plane_id];
}
return total_data_rate;
}
static u64
-icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
-u64 *plane_data_rate)
+icl_get_total_relative_data_rate(struct intel_atomic_state *state,
+struct intel_crtc *crtc)
{
- struct intel_plane *plane;
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
const struct intel_plane_state *plane_state;
+ struct intel_plane *plane;
u64 total_data_rate = 0;
+ enum plane_id plane_id;
+ int i;
/* Calculate and cache data rate for each plane */
- intel_atomic_crtc_state_for_each_plane_state(plane, plane_state,
crtc_state) {
- enum plane_id plane_id = plane->id;
- u64 rate;
+ for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
+ if (plane->pipe != crtc->pipe)
+ continue;
+
+ plane_id = plane->id;
if (!plane_state->planar_linked_plane) {
- rate = skl_plane_relative_data_rate(crtc_state,
plane_state, 0);
- plane_data_rate[plane_id] = rate;
- total_data_rate +=
[Intel-gfx] [PATCH 13/23] drm/i915/dp: Master/Slave enable/disable sequence for bigjoiner
From: Manasi Navare
Enabling is done in a special sequence and so should plane updates
be. Ideally the end user never notices the second pipe is used.
This way ideally everything will be tear free, and updates are
really atomic as userspace expects it.
This uses generic modeset_enables() calls like trans port sync
but still has special handling for disable since for slave we
should not disable things like encoder, plls that are not enabled
for slave.
Signed-off-by: Manasi Navare
[vsyrjala: Appease checkpatch]
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 25 +++-
drivers/gpu/drm/i915/display/intel_display.c | 126 +++
2 files changed, 122 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 439b92710fe6..9c4ad0392025 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -28,6 +28,7 @@
#include
#include "i915_drv.h"
+#include "i915_trace.h"
#include "intel_audio.h"
#include "intel_combo_phy.h"
#include "intel_connector.h"
@@ -3664,7 +3665,8 @@ static void tgl_ddi_pre_enable_dp(struct
intel_atomic_state *state,
/* 7.l Configure and enable FEC if needed */
intel_ddi_enable_fec(encoder, crtc_state);
- intel_dsc_enable(encoder, crtc_state);
+ if (!crtc_state->bigjoiner)
+ intel_dsc_enable(encoder, crtc_state);
}
static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
@@ -3736,7 +3738,8 @@ static void hsw_ddi_pre_enable_dp(struct
intel_atomic_state *state,
if (!is_mst)
intel_ddi_enable_pipe_clock(encoder, crtc_state);
- intel_dsc_enable(encoder, crtc_state);
+ if (!crtc_state->bigjoiner)
+ intel_dsc_enable(encoder, crtc_state);
}
static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
@@ -3987,6 +3990,21 @@ static void intel_ddi_post_disable(struct
intel_atomic_state *state,
ilk_pfit_disable(old_crtc_state);
}
+ if (old_crtc_state->bigjoiner_linked_crtc) {
+ struct intel_atomic_state *state =
+ to_intel_atomic_state(old_crtc_state->uapi.state);
+ struct intel_crtc *slave =
+ old_crtc_state->bigjoiner_linked_crtc;
+ const struct intel_crtc_state *old_slave_crtc_state =
+ intel_atomic_get_old_crtc_state(state, slave);
+
+ intel_crtc_vblank_off(old_slave_crtc_state);
+ trace_intel_pipe_disable(slave);
+
+ intel_dsc_disable(old_slave_crtc_state);
+ skl_scaler_disable(old_slave_crtc_state);
+ }
+
/*
* When called from DP MST code:
* - old_conn_state will be NULL
@@ -4205,7 +4223,8 @@ static void intel_enable_ddi(struct intel_atomic_state
*state,
{
drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);
- intel_ddi_enable_transcoder_func(encoder, crtc_state);
+ if (!crtc_state->bigjoiner_slave)
+ intel_ddi_enable_transcoder_func(encoder, crtc_state);
intel_enable_pipe(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index aea2ff3ef8c4..60669bef659f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7138,6 +7138,45 @@ static void hsw_set_frame_start_delay(const struct
intel_crtc_state *crtc_state)
intel_de_write(dev_priv, reg, val);
}
+static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
+const struct intel_crtc_state
*crtc_state)
+{
+ struct intel_crtc *master = to_intel_crtc(crtc_state->uapi.crtc);
+ struct intel_crtc_state *master_crtc_state;
+ struct drm_connector_state *conn_state;
+ struct drm_connector *conn;
+ struct intel_encoder *encoder = NULL;
+ int i;
+
+ if (crtc_state->bigjoiner_slave)
+ master = crtc_state->bigjoiner_linked_crtc;
+
+ master_crtc_state = intel_atomic_get_new_crtc_state(state, master);
+
+ for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
+ if (conn_state->crtc != &master->base)
+ continue;
+
+ encoder = to_intel_encoder(conn_state->best_encoder);
+ break;
+ }
+
+ if (!crtc_state->bigjoiner_slave) {
+ /* need to enable VDSC, which we skipped in pre-enable */
+ intel_dsc_enable(encoder, crtc_state);
+ } else {
+ /*
+* Enable sequence steps 1-7 on bigjoiner master
+*/
+ intel_encoders_pre_pll_enable(state, master);
+ intel_enable_shared_dpll(master_crtc_state);
+ intel_encoders_pre_enable(state, m
[Intel-gfx] [PATCH 11/23] drm/i915: Try to make bigjoiner work in atomic check
From: Maarten Lankhorst
When the clock is higher than the dotclock, try with 2 pipes enabled.
If we can enable 2, then we will go into big joiner mode, and steal
the adjacent crtc.
This only links the crtc's in software, no hardware or plane
programming is done yet. Blobs are also copied from the master's
crtc_state, so it doesn't depend at commit time on the other
crtc_state.
v6:
* Enable dSC for any mode->hdisplay > 5120
v5:
* Remove intel_dp_max_dotclock (Manasi)
v4:
* Fixes in intel_crtc_compute_config (Ville)
v3:
* Manual Rebase (Manasi)
Changes since v1:
- Rename pipe timings to transcoder timings, as they are now different.
Changes since v2:
- Rework bigjoiner checks; always disable slave when recalculating
master. No need to have a separate bigjoiner pass any more.
- Use pipe_mode instead of transcoder_mode, to clean up the code.
Signed-off-by: Maarten Lankhorst
Signed-off-by: Manasi Navare
[vsyrjala:
* hskew isn't a thing
* Do the dsc compute if bigjoiner is enabled, not the other way around]
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 156 +-
.../drm/i915/display/intel_display_types.h| 9 +
drivers/gpu/drm/i915/display/intel_dp.c | 20 ++-
3 files changed, 175 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 004ae95ede19..e2baf342a112 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8194,6 +8194,19 @@ static int intel_crtc_compute_config(struct intel_crtc
*crtc,
int clock_limit = dev_priv->max_dotclk_freq;
drm_mode_copy(pipe_mode, &pipe_config->hw.adjusted_mode);
+
+ /* Adjust pipe_mode for bigjoiner, with half the horizontal mode */
+ if (pipe_config->bigjoiner) {
+ pipe_mode->crtc_clock /= 2;
+ pipe_mode->crtc_hdisplay /= 2;
+ pipe_mode->crtc_hblank_start /= 2;
+ pipe_mode->crtc_hblank_end /= 2;
+ pipe_mode->crtc_hsync_start /= 2;
+ pipe_mode->crtc_hsync_end /= 2;
+ pipe_mode->crtc_htotal /= 2;
+ pipe_config->pipe_src_w /= 2;
+ }
+
intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
if (INTEL_GEN(dev_priv) < 4) {
@@ -12879,6 +12892,7 @@ static int intel_crtc_atomic_check(struct
intel_atomic_state *state,
if (mode_changed && crtc_state->hw.enable &&
dev_priv->display.crtc_compute_clock &&
+ !crtc_state->bigjoiner_slave &&
!drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) {
ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state);
if (ret)
@@ -13423,6 +13437,15 @@ intel_crtc_copy_uapi_to_hw_state_nomodeset(struct
intel_atomic_state *state,
{
const struct intel_crtc_state *from_crtc_state = crtc_state;
+ if (crtc_state->bigjoiner_slave) {
+ from_crtc_state = intel_atomic_get_new_crtc_state(state,
+
crtc_state->bigjoiner_linked_crtc);
+
+ /* No need to copy state if the master state is unchanged */
+ if (!from_crtc_state)
+ return;
+ }
+
intel_crtc_copy_color_blobs(crtc_state, from_crtc_state);
}
@@ -13458,6 +13481,47 @@ static void intel_crtc_copy_hw_to_uapi_state(struct
intel_crtc_state *crtc_state
crtc_state->hw.ctm);
}
+static int
+copy_bigjoiner_crtc_state(struct intel_crtc_state *crtc_state,
+ const struct intel_crtc_state *from_crtc_state)
+{
+ struct intel_crtc_state *saved_state;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+ saved_state = kmemdup(from_crtc_state, sizeof(*saved_state),
GFP_KERNEL);
+ if (!saved_state)
+ return -ENOMEM;
+
+ saved_state->uapi = crtc_state->uapi;
+ saved_state->scaler_state = crtc_state->scaler_state;
+ saved_state->shared_dpll = crtc_state->shared_dpll;
+ saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
+ saved_state->crc_enabled = crtc_state->crc_enabled;
+
+ intel_crtc_free_hw_state(crtc_state);
+ memcpy(crtc_state, saved_state, sizeof(*crtc_state));
+ kfree(saved_state);
+
+ /* Re-init hw state */
+ memset(&crtc_state->hw, 0, sizeof(saved_state->hw));
+ crtc_state->hw.enable = from_crtc_state->hw.enable;
+ crtc_state->hw.active = from_crtc_state->hw.active;
+ crtc_state->hw.pipe_mode = from_crtc_state->hw.pipe_mode;
+ crtc_state->hw.adjusted_mode = from_crtc_state->hw.adjusted_mode;
+
+ /* Some fixups */
+ crtc_state->uapi.mode_changed = from_crtc_state->uapi.mode_changed;
+ crtc_state->uapi.connectors_changed =
from_crtc_state->uapi.connectors_changed;
+ crtc_state
[Intel-gfx] [PATCH 07/23] drm/i915: Remove skl_adjusted_plane_pixel_rate()
From: Ville Syrjälä
Replace skl_adjusted_plane_pixel_rate() with the generic
intel_plane_pixel_rate(). The two should produce identical
results.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 27 ++-
1 file changed, 2 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6ccacd07ab94..a20b5051f18c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -33,6 +33,7 @@
#include
#include "display/intel_atomic.h"
+#include "display/intel_atomic_plane.h"
#include "display/intel_bw.h"
#include "display/intel_display_types.h"
#include "display/intel_fbc.h"
@@ -5102,30 +5103,6 @@ intel_get_linetime_us(const struct intel_crtc_state
*crtc_state)
return linetime_us;
}
-static u32
-skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state)
-{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- u64 adjusted_pixel_rate;
- uint_fixed_16_16_t downscale_amount;
-
- /* Shouldn't reach here on disabled planes... */
- if (drm_WARN_ON(&dev_priv->drm,
- !intel_wm_plane_visible(crtc_state, plane_state)))
- return 0;
-
- /*
-* Adjusted plane pixel rate is just the pipe's adjusted pixel rate
-* with additional adjustments for plane-specific scaling.
-*/
- adjusted_pixel_rate = crtc_state->pixel_rate;
- downscale_amount = skl_plane_downscale_amount(crtc_state, plane_state);
-
- return mul_round_up_u32_fixed16(adjusted_pixel_rate,
- downscale_amount);
-}
-
static int
skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
int width, const struct drm_format_info *format,
@@ -5238,7 +5215,7 @@ skl_compute_plane_wm_params(const struct intel_crtc_state
*crtc_state,
return skl_compute_wm_params(crtc_state, width,
fb->format, fb->modifier,
plane_state->hw.rotation,
-skl_adjusted_plane_pixel_rate(crtc_state,
plane_state),
+intel_plane_pixel_rate(crtc_state,
plane_state),
wp, color_plane);
}
--
2.26.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
