[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [01/11] drm/i915/display: move needs_modeset to an inline in header
== Series Details == Series: series starting with [01/11] drm/i915/display: move needs_modeset to an inline in header URL : https://patchwork.freedesktop.org/series/84812/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h HDRTEST drivers/gpu/drm/i915/display/intel_fdi.h In file included from : ./drivers/gpu/drm/i915/display/intel_fdi.h:20:33: error: ‘struct drm_i915_private’ declared inside parameter list will not be visible outside of this definition or declaration [-Werror] void intel_fdi_init_hook(struct drm_i915_private *dev_priv); ^~~~ cc1: all warnings being treated as errors drivers/gpu/drm/i915/Makefile:310: recipe for target 'drivers/gpu/drm/i915/display/intel_fdi.hdrtest' failed make[4]: *** [drivers/gpu/drm/i915/display/intel_fdi.hdrtest] Error 1 scripts/Makefile.build:496: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:496: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:496: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1805: recipe for target 'drivers' failed make: *** [drivers] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC-v7 15/21] drm/i915/pxp: Implement ioctl action to set session in play
With this ioctl action, userspace driver can set the session in
state "session in play", after dirver reserved the session slot/id
from kernel PXP, and sent the TEE commands to activate the
corresponding hardware session. Session state "session in play"
means this session is ready for secure playback.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c| 11 +-
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 51 +
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 2 +
3 files changed, 63 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index e294134fef78..e000a78b782e 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -16,7 +16,13 @@
#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) <<
KCR_INIT_MASK_SHIFT))
#define PXP_ACTION_SET_SESSION_STATUS 1
-#define PXP_REQ_SESSION_ID_INIT 0
+
+enum pxp_session_req {
+ /* Request KMD to allocate session id and move it to IN INIT */
+ PXP_REQ_SESSION_ID_INIT = 0x0,
+ /* Inform KMD that UMD has completed the initialization */
+ PXP_REQ_SESSION_IN_PLAY,
+};
/*
* struct pxp_set_session_status_params - Params to reserved, set or destroy
@@ -228,6 +234,9 @@ int i915_pxp_ops_ioctl(struct drm_device *dev, void *data,
struct drm_file *drmf
pxp_info.sm_status = ret;
ret = 0;
}
+ } else if (params->req_session_state ==
PXP_REQ_SESSION_IN_PLAY) {
+ ret = intel_pxp_sm_ioctl_mark_session_in_play(pxp,
params->session_type,
+
params->pxp_tag);
} else {
ret = -EINVAL;
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index e30be334d0dd..a657c5c7f013 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -12,6 +12,9 @@
#define GEN12_KCR_TSIP _MMIO(0x32264) /* KCR type1 session in play 0-63 */
+#define SESSION_TYPE_MASK BIT(7)
+#define SESSION_ID_MASK (BIT(7) - 1)
+
static inline int session_max(int session_type)
{
return (session_type == SESSION_TYPE_TYPE0) ?
@@ -148,6 +151,17 @@ static int create_session_entry(struct intel_pxp *pxp,
struct drm_file *drmfile,
return 0;
}
+static int pxp_get_session_index(u32 session_id, int *index_out, int *type_out)
+{
+ if (!index_out || !type_out)
+ return -EINVAL;
+
+ *type_out = (session_id & SESSION_TYPE_MASK) ? SESSION_TYPE_TYPE1 :
SESSION_TYPE_TYPE0;
+ *index_out = session_id & SESSION_ID_MASK;
+
+ return 0;
+}
+
/**
* intel_pxp_sm_ioctl_reserve_session - To reserve an available protected
session.
* @pxp: pointer to pxp struct
@@ -192,3 +206,40 @@ int intel_pxp_sm_ioctl_reserve_session(struct intel_pxp
*pxp, struct drm_file *d
return PXP_SM_STATUS_SESSION_NOT_AVAILABLE;
}
+
+/**
+ * intel_pxp_sm_ioctl_mark_session_in_play - Put an reserved session to
"in_play" state
+ * @pxp: pointer to pxp struct
+ * @session_type: Type of the session to be updated. One of enum
pxp_session_types.
+ * @session_id: Session identifier of the session, containing type and index
info
+ *
+ * Return: status. 0 means update is successful.
+ */
+int intel_pxp_sm_ioctl_mark_session_in_play(struct intel_pxp *pxp, int
session_type,
+ u32 session_id)
+{
+ int ret;
+ int session_index;
+ int session_type_in_id;
+ struct intel_pxp_sm_session *curr, *n;
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+
+ ret = pxp_get_session_index(session_id, _index,
_type_in_id);
+ if (ret)
+ return ret;
+
+ if (session_type != session_type_in_id)
+ return -EINVAL;
+
+ lockdep_assert_held(>ctx.mutex);
+
+ list_for_each_entry_safe(curr, n, session_list(pxp, session_type),
list) {
+ if (curr->index == session_index) {
+ curr->is_in_play = true;
+ return 0;
+ }
+ }
+
+ drm_err(>i915->drm, "Failed to %s couldn't find active session\n",
__func__);
+ return -EINVAL;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
index 75fffb7d8b0e..aaa44d365f39 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
@@ -40,4 +40,6 @@ struct intel_pxp_sm_session {
int intel_pxp_sm_ioctl_reserve_session(struct intel_pxp *pxp, struct drm_file
*drmfile,
int session_type, int protection_mode,
u32 *pxp_tag);
+int intel_pxp_sm_ioctl_mark_session_in_play(struct intel_pxp *pxp, int
[Intel-gfx] [RFC-v7 14/21] drm/i915/pxp: Implement ioctl action to reserve session slots
With this ioctl action, userspace driver can reserve one or
multiple session slot/id assigned by kernel PXP, as the first
step of PXP session establishment flow. The session info is
stored in the session list structure.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 91 +
drivers/gpu/drm/i915/pxp/intel_pxp.h | 22 +++
drivers/gpu/drm/i915/pxp/intel_pxp_arb.c | 2 -
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 3 -
drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 3 +
drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 3 +
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 194 +++
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 43
9 files changed, 357 insertions(+), 5 deletions(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index d419dfa4923d..f8ef435b35d4 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -262,6 +262,7 @@ i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp_cmd.o \
pxp/intel_pxp_context.o \
pxp/intel_pxp_pm.o \
+ pxp/intel_pxp_sm.o \
pxp/intel_pxp_tee.o
# Post-mortem debug and GPU hang state capture
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index ce3760206b76..e294134fef78 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -7,6 +7,7 @@
#include "intel_pxp_context.h"
#include "intel_pxp_tee.h"
#include "intel_pxp_arb.h"
+#include "intel_pxp_sm.h"
/* KCR register definitions */
#define KCR_INIT_MMIO(0x320f0)
@@ -14,6 +15,36 @@
/* Setting KCR Init bit is required after system boot */
#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) <<
KCR_INIT_MASK_SHIFT))
+#define PXP_ACTION_SET_SESSION_STATUS 1
+#define PXP_REQ_SESSION_ID_INIT 0
+
+/*
+ * struct pxp_set_session_status_params - Params to reserved, set or destroy
+ * the session from the PXP state machine.
+ */
+struct pxp_set_session_status_params {
+ u32 pxp_tag; /* in [optional], out pxp tag */
+ u32 session_type; /* in, session type */
+ u32 session_mode; /* in, session mode */
+ u32 req_session_state; /* in, new session state */
+};
+
+/* struct pxp_info - Params for PXP operation. */
+struct pxp_info {
+ u32 action; /* in - specified action of this operation */
+ u32 sm_status; /* out - status output for this operation */
+
+ /* in - action params to set the PXP session state */
+ struct pxp_set_session_status_params set_session_status;
+} __attribute__((packed));
+
+struct drm_i915_pxp_ops {
+ /* in - user space pointer to struct pxp_info */
+ struct pxp_info __user *info_ptr;
+ /* in - memory size that info_ptr points to */
+ u32 info_size;
+};
+
static void intel_pxp_write_irq_mask_reg(struct intel_gt *gt, u32 mask)
{
lockdep_assert_held(>irq_lock);
@@ -152,3 +183,63 @@ bool intel_pxp_gem_object_status(struct drm_i915_private
*i915)
else
return false;
}
+
+int i915_pxp_ops_ioctl(struct drm_device *dev, void *data, struct drm_file
*drmfile)
+{
+ int ret;
+ struct pxp_info pxp_info = {0};
+ struct drm_i915_pxp_ops *pxp_ops = data;
+ struct drm_i915_private *i915 = to_i915(dev);
+ struct intel_pxp *pxp = >gt.pxp;
+
+ if (pxp->ctx.id == 0 || !drmfile || !pxp_ops ||
+ pxp_ops->info_size != sizeof(pxp_info))
+ return -EINVAL;
+
+ if (copy_from_user(_info, pxp_ops->info_ptr, sizeof(pxp_info)) != 0)
+ return -EFAULT;
+
+ mutex_lock(>ctx.mutex);
+
+ if (pxp->ctx.global_state_in_suspend) {
+ drm_err(>drm, "Return failure due to state in suspend\n");
+ pxp_info.sm_status = PXP_SM_STATUS_SESSION_NOT_AVAILABLE;
+ ret = 0;
+ goto end;
+ }
+
+ if (pxp->ctx.global_state_attacked) {
+ drm_err(>drm, "Retry required due to state attacked\n");
+ pxp_info.sm_status = PXP_SM_STATUS_RETRY_REQUIRED;
+ ret = 0;
+ goto end;
+ }
+
+ if (pxp_info.action == PXP_ACTION_SET_SESSION_STATUS) {
+ struct pxp_set_session_status_params *params =
_info.set_session_status;
+
+ if (params->req_session_state == PXP_REQ_SESSION_ID_INIT) {
+ ret = intel_pxp_sm_ioctl_reserve_session(pxp, drmfile,
+
params->session_type,
+
params->session_mode,
+
>pxp_tag);
+ if (ret == PXP_SM_STATUS_RETRY_REQUIRED ||
+
[Intel-gfx] [RFC-v7 21/21] drm/i915/pxp: Enable the PXP ioctl for protected session
In the previous commits, we have implemented the PXP ioctl
functions. Now we enable those handlers and expose them as PXP
ioctl, so allow the userspace driver can establish, set, or
destory the protected session via this ioctl.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 53
include/uapi/drm/i915_drm.h | 72
3 files changed, 73 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e74201e81369..201550ffb353 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1766,6 +1766,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl,
DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(I915_PXP_OPS, i915_pxp_ops_ioctl, DRM_RENDER_ALLOW),
};
static const struct drm_driver driver = {
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 3a49dd97cab2..51e09224d7c6 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -31,59 +31,6 @@ enum pxp_session_req {
PXP_REQ_SESSION_TERMINATE
};
-/*
- * struct pxp_sm_query_pxp_tag - Params to query the PXP tag of specified
- * session id and whether the session is alive from PXP state machine.
- */
-struct pxp_sm_query_pxp_tag {
- u32 session_is_alive;
- u32 pxp_tag; /* in - Session ID, out pxp tag */
-};
-
-/*
- * struct pxp_set_session_status_params - Params to reserved, set or destroy
- * the session from the PXP state machine.
- */
-struct pxp_set_session_status_params {
- u32 pxp_tag; /* in [optional], out pxp tag */
- u32 session_type; /* in, session type */
- u32 session_mode; /* in, session mode */
- u32 req_session_state; /* in, new session state */
-};
-
-/*
- * struct pxp_tee_io_message_params - Params to send/receive message to/from
TEE.
- */
-struct pxp_tee_io_message_params {
- u8 __user *msg_in; /* in - message input */
- u32 msg_in_size; /* in - message input size */
- u8 __user *msg_out; /* in - message output buffer */
- u32 msg_out_size; /* out- message output size from TEE */
- u32 msg_out_buf_size; /* in - message output buffer size */
-};
-
-/* struct pxp_info - Params for PXP operation. */
-struct pxp_info {
- u32 action; /* in - specified action of this operation */
- u32 sm_status; /* out - status output for this operation */
-
- union {
- /* in - action params to query PXP tag */
- struct pxp_sm_query_pxp_tag query_pxp_tag;
- /* in - action params to set the PXP session state */
- struct pxp_set_session_status_params set_session_status;
- /* in - action params to send TEE commands */
- struct pxp_tee_io_message_params tee_io_message;
- };
-} __attribute__((packed));
-
-struct drm_i915_pxp_ops {
- /* in - user space pointer to struct pxp_info */
- struct pxp_info __user *info_ptr;
- /* in - memory size that info_ptr points to */
- u32 info_size;
-};
-
static void intel_pxp_write_irq_mask_reg(struct intel_gt *gt, u32 mask)
{
lockdep_assert_held(>irq_lock);
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index d6085a328b2c..17cf25bdc3c4 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -359,6 +359,7 @@ typedef struct _drm_i915_sarea {
#define DRM_I915_QUERY 0x39
#define DRM_I915_GEM_VM_CREATE 0x3a
#define DRM_I915_GEM_VM_DESTROY0x3b
+#define DRM_I915_PXP_OPS 0x3c
/* Must be kept compact -- no holes */
#define DRM_IOCTL_I915_INITDRM_IOW( DRM_COMMAND_BASE +
DRM_I915_INIT, drm_i915_init_t)
@@ -423,6 +424,7 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_QUERY, struct drm_i915_query)
#define DRM_IOCTL_I915_GEM_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control)
#define DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW (DRM_COMMAND_BASE +
DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control)
+#define DRM_IOCTL_I915_PXP_OPS DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_PXP_OPS, struct drm_i915_pxp_ops)
/* Allow drivers to submit batchbuffers directly to hardware, relying
* on the security mechanisms provided by hardware.
@@ -1964,6 +1966,76 @@ struct drm_i915_gem_vm_control {
__u32 vm_id;
};
+/*
+ * struct pxp_sm_query_pxp_tag - Params to query the PXP tag of specified
+ * session id and whether the session is alive from PXP state machine.
+ */
[Intel-gfx] [RFC-v7 11/21] drm/i915/uapi: introduce drm_i915_gem_create_ext
From: Bommu Krishnaiah
Same old gem_create but with now with extensions support. This is needed
to support various upcoming usecases. For now we use the extensions
mechanism to support PAVP.
Signed-off-by: Bommu Krishnaiah
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen joonas.lahti...@linux.intel.com
Cc: Matthew Auld matthew.a...@intel.com
Cc: Telukuntla Sreedhar
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 42 -
include/uapi/drm/i915_drm.h | 47 +
3 files changed, 89 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index af06c85e6ba7..3dbda949bf71 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1733,7 +1733,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop,
DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop,
DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
- DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl,
DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 58276694c848..41698a823737 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -53,6 +53,7 @@
#include "i915_drv.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
+#include "i915_user_extensions.h"
#include "intel_pm.h"
@@ -260,6 +261,35 @@ i915_gem_dumb_create(struct drm_file *file,
>size, >handle);
}
+struct create_ext {
+struct drm_i915_private *i915;
+};
+
+static int __create_setparam(struct drm_i915_gem_object_param *args,
+ struct create_ext
*ext_data)
+{
+ if (!(args->param & I915_OBJECT_PARAM)) {
+ DRM_DEBUG("Missing I915_OBJECT_PARAM namespace\n");
+ return -EINVAL;
+ }
+
+ return -EINVAL;
+}
+
+static int create_setparam(struct i915_user_extension __user *base, void *data)
+{
+ struct drm_i915_gem_create_ext_setparam ext;
+
+ if (copy_from_user(, base, sizeof(ext)))
+ return -EFAULT;
+
+ return __create_setparam(, data);
+}
+
+static const i915_user_extension_fn create_extensions[] = {
+ [I915_GEM_CREATE_EXT_SETPARAM] = create_setparam,
+};
+
/**
* Creates a new mm object and returns a handle to it.
* @dev: drm device pointer
@@ -271,10 +301,20 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
{
struct drm_i915_private *i915 = to_i915(dev);
- struct drm_i915_gem_create *args = data;
+ struct create_ext ext_data = { .i915 = i915 };
+ struct drm_i915_gem_create_ext *args = data;
+ int ret;
i915_gem_flush_free_objects(i915);
+ ret = i915_user_extensions(u64_to_user_ptr(args->extensions),
+ create_extensions,
+ ARRAY_SIZE(create_extensions),
+ _data);
+ if (ret)
+ return ret;
+
+
return i915_gem_create(file,
intel_memory_region_by_type(i915,
INTEL_MEMORY_SYSTEM),
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 6edcb2b6c708..e918ccc81c74 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -391,6 +391,7 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE +
DRM_I915_GEM_ENTERVT)
#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE +
DRM_I915_GEM_LEAVEVT)
#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
+#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext)
#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE +
DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE +
DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
#define DRM_IOCTL_I915_GEM_MMAPDRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
@@ -728,6 +729,27 @@ struct drm_i915_gem_create {
__u32 pad;
};
+struct drm_i915_gem_create_ext {
+ /**
+* Requested size for the object.
+*
+
[Intel-gfx] [RFC-v7 17/21] drm/i915/pxp: Implement ioctl action to send TEE commands
Implement the ioctl action to allow userspace driver sends TEE
commands via PXP ioctl, instead of TEE iotcl. So we can
centralize those protection operations at PXP.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 48 +---
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 57
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 5 +++
3 files changed, 105 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index c35011b84f5a..2445af5f763c 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -16,7 +16,10 @@
/* Setting KCR Init bit is required after system boot */
#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) <<
KCR_INIT_MASK_SHIFT))
-#define PXP_ACTION_SET_SESSION_STATUS 1
+enum pxp_ioctl_action {
+ PXP_ACTION_SET_SESSION_STATUS = 1,
+ PXP_ACTION_TEE_IO_MESSAGE = 4,
+};
enum pxp_session_req {
/* Request KMD to allocate session id and move it to IN INIT */
@@ -38,13 +41,28 @@ struct pxp_set_session_status_params {
u32 req_session_state; /* in, new session state */
};
+/*
+ * struct pxp_tee_io_message_params - Params to send/receive message to/from
TEE.
+ */
+struct pxp_tee_io_message_params {
+ u8 __user *msg_in; /* in - message input */
+ u32 msg_in_size; /* in - message input size */
+ u8 __user *msg_out; /* in - message output buffer */
+ u32 msg_out_size; /* out- message output size from TEE */
+ u32 msg_out_buf_size; /* in - message output buffer size */
+};
+
/* struct pxp_info - Params for PXP operation. */
struct pxp_info {
u32 action; /* in - specified action of this operation */
u32 sm_status; /* out - status output for this operation */
- /* in - action params to set the PXP session state */
- struct pxp_set_session_status_params set_session_status;
+ union {
+ /* in - action params to set the PXP session state */
+ struct pxp_set_session_status_params set_session_status;
+ /* in - action params to send TEE commands */
+ struct pxp_tee_io_message_params tee_io_message;
+ };
} __attribute__((packed));
struct drm_i915_pxp_ops {
@@ -228,7 +246,9 @@ int i915_pxp_ops_ioctl(struct drm_device *dev, void *data,
struct drm_file *drmf
goto end;
}
- if (pxp_info.action == PXP_ACTION_SET_SESSION_STATUS) {
+ switch (pxp_info.action) {
+ case PXP_ACTION_SET_SESSION_STATUS:
+ {
struct pxp_set_session_status_params *params =
_info.set_session_status;
if (params->req_session_state == PXP_REQ_SESSION_ID_INIT) {
@@ -250,8 +270,26 @@ int i915_pxp_ops_ioctl(struct drm_device *dev, void *data,
struct drm_file *drmf
} else {
ret = -EINVAL;
}
- } else {
+ break;
+ }
+ case PXP_ACTION_TEE_IO_MESSAGE:
+ {
+ struct pxp_tee_io_message_params *params =
_info.tee_io_message;
+
+ ret = intel_pxp_tee_ioctl_io_message(pxp,
+params->msg_in,
params->msg_in_size,
+params->msg_out,
>msg_out_size,
+params->msg_out_buf_size);
+ if (ret) {
+ drm_err(>drm, "Failed to send TEE IO message\n");
+ ret = -EFAULT;
+ }
+ break;
+ }
+ default:
+ drm_err(>drm, "Failed to %s due to bad params\n",
__func__);
ret = -EINVAL;
+ break;
}
end:
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
index 816a6d5a54e4..e0815b2ee9ab 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -168,3 +168,60 @@ int intel_pxp_tee_cmd_create_arb_session(struct intel_pxp
*pxp)
return ret;
}
+
+int intel_pxp_tee_ioctl_io_message(struct intel_pxp *pxp,
+ void __user *msg_in_user_ptr, u32
msg_in_size,
+ void __user *msg_out_user_ptr, u32
*msg_out_size_ptr,
+ u32 msg_out_buf_size)
+{
+ int ret;
+ void *msg_in = NULL;
+ void *msg_out = NULL;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+ struct drm_i915_private *i915 = gt->i915;
+
+ if (!msg_in_user_ptr || !msg_out_user_ptr || msg_out_buf_size == 0 ||
+ msg_in_size == 0 || !msg_out_size_ptr)
+ return -EINVAL;
+
+ msg_in = kzalloc(msg_in_size, GFP_KERNEL);
+ if (!msg_in)
+ return -ENOMEM;
+
+ msg_out = kzalloc(msg_out_buf_size, GFP_KERNEL);
+ if
[Intel-gfx] [RFC-v7 04/21] drm/i915/pxp: Create the arbitrary session after boot
Create the arbitrary session, with the fixed session id 0xf, after
system boot, for the case that application allocates the protected
buffer without establishing any protection session. Because the
hardware requires at least one alive session for protected buffer
creation. This arbitrary session needs to be re-created after
teardown or power event because hardware encryption key won't be
valid after such cases.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.h | 16 +++
drivers/gpu/drm/i915/pxp/intel_pxp_arb.c | 134 +++
drivers/gpu/drm/i915/pxp/intel_pxp_arb.h | 38 ++
drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 6 +
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 38 ++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 6 +
8 files changed, 240 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 57447887d352..2c84f75b41da 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -258,6 +258,7 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
+ pxp/intel_pxp_arb.o \
pxp/intel_pxp_context.o \
pxp/intel_pxp_tee.o
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 4104dd89ca7f..67bdaeb79b40 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -6,6 +6,7 @@
#include "intel_pxp.h"
#include "intel_pxp_context.h"
#include "intel_pxp_tee.h"
+#include "intel_pxp_arb.h"
/* KCR register definitions */
#define KCR_INIT_MMIO(0x320f0)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 7c3d49a6a3ab..1841a9aa972d 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -8,6 +8,22 @@
#include "intel_pxp_context.h"
+enum pxp_session_types {
+ SESSION_TYPE_TYPE0 = 0,
+ SESSION_TYPE_TYPE1 = 1,
+
+ SESSION_TYPE_MAX
+};
+
+enum pxp_protection_modes {
+ PROTECTION_MODE_NONE = 0,
+ PROTECTION_MODE_LM = 2,
+ PROTECTION_MODE_HM = 3,
+ PROTECTION_MODE_SM = 6,
+
+ PROTECTION_MODE_ALL
+};
+
struct intel_pxp {
struct pxp_context ctx;
};
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
new file mode 100644
index ..9611cd53d3a4
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#include "gt/intel_context.h"
+#include "gt/intel_engine_pm.h"
+
+#include "intel_pxp_arb.h"
+#include "intel_pxp.h"
+#include "intel_pxp_context.h"
+#include "intel_pxp_tee.h"
+
+#define GEN12_KCR_SIP _MMIO(0x32260) /* KCR type0 session in play 0-31 */
+
+/* Arbitrary session */
+#define ARB_SESSION_INDEX 0xf
+#define ARB_SESSION_TYPE SESSION_TYPE_TYPE0
+#define ARB_PROTECTION_MODE PROTECTION_MODE_HM
+
+static bool is_hw_arb_session_in_play(struct intel_pxp *pxp)
+{
+ u32 regval_sip = 0;
+ intel_wakeref_t wakeref;
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+
+ with_intel_runtime_pm(>i915->runtime_pm, wakeref) {
+ regval_sip = intel_uncore_read(gt->uncore, GEN12_KCR_SIP);
+ }
+
+ return regval_sip & BIT(ARB_SESSION_INDEX);
+}
+
+/* wait hw session_in_play reg to match the current sw state */
+static int wait_arb_hw_sw_state(struct intel_pxp *pxp)
+{
+ const int max_retry = 10;
+ const int ms_delay = 10;
+ int retry = 0;
+ int ret;
+ struct pxp_protected_session *arb = >ctx.arb_session;
+
+ ret = -EINVAL;
+ for (retry = 0; retry < max_retry; retry++) {
+ if (is_hw_arb_session_in_play(pxp) ==
+ arb->is_in_play) {
+ ret = 0;
+ break;
+ }
+
+ msleep(ms_delay);
+ }
+
+ return ret;
+}
+
+static void arb_session_entry_init(struct intel_pxp *pxp)
+{
+ struct pxp_protected_session *arb = >ctx.arb_session;
+
+ arb->context_id = pxp->ctx.id;
+ arb->type = ARB_SESSION_TYPE;
+ arb->protection_mode = ARB_PROTECTION_MODE;
+ arb->index = ARB_SESSION_INDEX;
+ arb->is_in_play = false;
+}
+
+int intel_pxp_arb_reserve_session(struct intel_pxp *pxp)
+{
+ int ret;
+
+ lockdep_assert_held(>ctx.mutex);
+
+ arb_session_entry_init(pxp);
+ ret = wait_arb_hw_sw_state(pxp);
+
+ return ret;
+}
+
+/**
+ * intel_pxp_arb_mark_session_in_play - To put an reserved protected session
to "in_play"
[Intel-gfx] [RFC-v7 18/21] drm/i915/pxp: Implement ioctl action to query PXP tag
Enable the PXP ioctl action to allow userspace driver to query the
PXP tag, which is a 32-bit bitwise value indicating the current
session info, including protection type, session id, and whether
the session is enabled.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 20 +++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 6 -
drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 9 ++
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 130 ++-
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 2 +
5 files changed, 160 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 2445af5f763c..46ad2ab229c1 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -17,6 +17,7 @@
#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) <<
KCR_INIT_MASK_SHIFT))
enum pxp_ioctl_action {
+ PXP_ACTION_QUERY_PXP_TAG = 0,
PXP_ACTION_SET_SESSION_STATUS = 1,
PXP_ACTION_TEE_IO_MESSAGE = 4,
};
@@ -30,6 +31,15 @@ enum pxp_session_req {
PXP_REQ_SESSION_TERMINATE
};
+/*
+ * struct pxp_sm_query_pxp_tag - Params to query the PXP tag of specified
+ * session id and whether the session is alive from PXP state machine.
+ */
+struct pxp_sm_query_pxp_tag {
+ u32 session_is_alive;
+ u32 pxp_tag; /* in - Session ID, out pxp tag */
+};
+
/*
* struct pxp_set_session_status_params - Params to reserved, set or destroy
* the session from the PXP state machine.
@@ -58,6 +68,8 @@ struct pxp_info {
u32 sm_status; /* out - status output for this operation */
union {
+ /* in - action params to query PXP tag */
+ struct pxp_sm_query_pxp_tag query_pxp_tag;
/* in - action params to set the PXP session state */
struct pxp_set_session_status_params set_session_status;
/* in - action params to send TEE commands */
@@ -272,6 +284,14 @@ int i915_pxp_ops_ioctl(struct drm_device *dev, void *data,
struct drm_file *drmf
}
break;
}
+ case PXP_ACTION_QUERY_PXP_TAG:
+ {
+ struct pxp_sm_query_pxp_tag *params = _info.query_pxp_tag;
+
+ ret = intel_pxp_sm_ioctl_query_pxp_tag(pxp,
>session_is_alive,
+ >pxp_tag);
+ break;
+ }
case PXP_ACTION_TEE_IO_MESSAGE:
{
struct pxp_tee_io_message_params *params =
_info.tee_io_message;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index e68c035d8448..133e3df9b1f6 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -16,12 +16,6 @@
#define GEN12_KCR_SIP _MMIO(0x32260) /* KCR type0 session in play 0-31 */
-#define PXP_MAX_TYPE0_SESSIONS 16
-#define PXP_MAX_TYPE1_SESSIONS 6
-
-/* we need to reserve one type0 slot for arbitrary session */
-#define PXP_MAX_NORMAL_TYPE0_SESSIONS (PXP_MAX_TYPE0_SESSIONS - 1)
-
enum pxp_session_types {
SESSION_TYPE_TYPE0 = 0,
SESSION_TYPE_TYPE1 = 1,
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
index 4c583f831831..ad9e278f3fb2 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
@@ -9,6 +9,12 @@
#include
#include "intel_pxp_arb.h"
+#define PXP_MAX_TYPE0_SESSIONS 16
+#define PXP_MAX_TYPE1_SESSIONS 6
+
+/* we need to reserve one type0 slot for arbitrary session */
+#define PXP_MAX_NORMAL_TYPE0_SESSIONS (PXP_MAX_TYPE0_SESSIONS - 1)
+
/* struct pxp_context - Represents combined view of driver and logical HW
states. */
struct pxp_context {
/** @mutex: mutex to protect the pxp context */
@@ -20,6 +26,9 @@ struct pxp_context {
struct list_head type0_sessions;
struct list_head type1_sessions;
+ u32 type0_pxp_tag[PXP_MAX_NORMAL_TYPE0_SESSIONS];
+ u32 type1_pxp_tag[PXP_MAX_TYPE1_SESSIONS];
+
int id;
bool global_state_attacked;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index a94897768c41..c4b55e1531c1 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -16,6 +16,21 @@
#define SESSION_TYPE_MASK BIT(7)
#define SESSION_ID_MASK (BIT(7) - 1)
+struct pxp_tag {
+ union {
+ u32 value;
+ struct {
+ u32 session_id : 8;
+ u32 instance_id : 8;
+ u32 enable : 1;
+ u32 hm : 1;
+ u32 reserved_1 : 1;
+ u32 sm : 1;
+ u32 reserved_2 : 12;
+ };
+ };
+};
+
static inline struct list_head *session_list(struct intel_pxp *pxp,
[Intel-gfx] [RFC-v7 10/21] mei: pxp: export pavp client to me client bus
From: Vitaly Lubart
Export PAVP client to work with i915_cp driver,
for binding it uses kernel component framework.
Signed-off-by: Vitaly Lubart
Signed-off-by: Tomas Winkler
---
drivers/misc/mei/Kconfig | 2 +
drivers/misc/mei/Makefile | 1 +
drivers/misc/mei/pxp/Kconfig | 13 ++
drivers/misc/mei/pxp/Makefile | 7 +
drivers/misc/mei/pxp/mei_pxp.c | 230 +
drivers/misc/mei/pxp/mei_pxp.h | 18 +++
6 files changed, 271 insertions(+)
create mode 100644 drivers/misc/mei/pxp/Kconfig
create mode 100644 drivers/misc/mei/pxp/Makefile
create mode 100644 drivers/misc/mei/pxp/mei_pxp.c
create mode 100644 drivers/misc/mei/pxp/mei_pxp.h
diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig
index f5fd5b786607..0e0bcd0da852 100644
--- a/drivers/misc/mei/Kconfig
+++ b/drivers/misc/mei/Kconfig
@@ -47,3 +47,5 @@ config INTEL_MEI_TXE
Intel Bay Trail
source "drivers/misc/mei/hdcp/Kconfig"
+source "drivers/misc/mei/pxp/Kconfig"
+
diff --git a/drivers/misc/mei/Makefile b/drivers/misc/mei/Makefile
index f1c76f7ee804..d8e5165917f2 100644
--- a/drivers/misc/mei/Makefile
+++ b/drivers/misc/mei/Makefile
@@ -26,3 +26,4 @@ mei-$(CONFIG_EVENT_TRACING) += mei-trace.o
CFLAGS_mei-trace.o = -I$(src)
obj-$(CONFIG_INTEL_MEI_HDCP) += hdcp/
+obj-$(CONFIG_INTEL_MEI_PXP) += pxp/
diff --git a/drivers/misc/mei/pxp/Kconfig b/drivers/misc/mei/pxp/Kconfig
new file mode 100644
index ..4029b96afc04
--- /dev/null
+++ b/drivers/misc/mei/pxp/Kconfig
@@ -0,0 +1,13 @@
+
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
+#
+config INTEL_MEI_PXP
+ tristate "Intel PXP services of ME Interface"
+ select INTEL_MEI_ME
+ depends on DRM_I915
+ help
+ MEI Support for PXP Services on Intel platforms.
+
+ Enables the ME FW services required for PXP support through
+ I915 display driver of Intel.
diff --git a/drivers/misc/mei/pxp/Makefile b/drivers/misc/mei/pxp/Makefile
new file mode 100644
index ..0329950d5794
--- /dev/null
+++ b/drivers/misc/mei/pxp/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
+#
+# Makefile - PXP client driver for Intel MEI Bus Driver.
+
+obj-$(CONFIG_INTEL_MEI_PXP) += mei_pxp.o
diff --git a/drivers/misc/mei/pxp/mei_pxp.c b/drivers/misc/mei/pxp/mei_pxp.c
new file mode 100644
index ..5bd61fe445e3
--- /dev/null
+++ b/drivers/misc/mei/pxp/mei_pxp.c
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+/**
+ * DOC: MEI_PXP Client Driver
+ *
+ * The mei_pxp driver acts as a translation layer between PXP
+ * protocol implementer (I915) and ME FW by translating PXP
+ * negotiation messages to ME FW command payloads and vice versa.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "mei_pxp.h"
+
+/**
+ * mei_pxp_send_message() - Sends a PXP message to ME FW.
+ * @dev: device corresponding to the mei_cl_device
+ * @message: a message buffer to send
+ * @size: size of the message
+ * Return: 0 on Success, <0 on Failure
+ */
+static int
+mei_pxp_send_message(struct device *dev, const void *message, size_t size)
+{
+ struct mei_cl_device *cldev;
+ ssize_t byte;
+
+ if (!dev || !message)
+ return -EINVAL;
+
+ cldev = to_mei_cl_device(dev);
+
+ /* temporary drop const qualifier till the API is fixed */
+ byte = mei_cldev_send(cldev, (u8 *)message, size);
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte);
+ return byte;
+ }
+
+ return 0;
+}
+
+/**
+ * mei_pxp_receive_message() - Receives a PXP message from ME FW.
+ * @dev: device corresponding to the mei_cl_device
+ * @buffer: a message buffer to contain the received message
+ * @size: size of the buffer
+ * Return: bytes sent on Success, <0 on Failure
+ */
+static int
+mei_pxp_receive_message(struct device *dev, void *buffer, size_t size)
+{
+ struct mei_cl_device *cldev;
+ ssize_t byte;
+
+ if (!dev || !buffer)
+ return -EINVAL;
+
+ cldev = to_mei_cl_device(dev);
+
+ byte = mei_cldev_recv(cldev, buffer, size);
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte);
+ return byte;
+ }
+
+ return byte;
+}
+
+static const struct i915_pxp_component_ops mei_pxp_ops = {
+ .owner = THIS_MODULE,
+ .send = mei_pxp_send_message,
+ .receive = mei_pxp_receive_message,
+};
+
+static int mei_component_master_bind(struct device *dev)
+{
+ struct mei_cl_device *cldev = to_mei_cl_device(dev);
+ struct i915_pxp_comp_master *comp_master = mei_cldev_get_drvdata(cldev);
+ int ret;
+
+ dev_dbg(dev, "%s\n", __func__);
+ comp_master->ops = _pxp_ops;
+
[Intel-gfx] [RFC-v7 16/21] drm/i915/pxp: Implement ioctl action to terminate the session
Implement the PXP ioctl action to allow userspace driver to
terminate the hardware session and cleanup its software session
state. PXP sends the session termination command to GPU once
receves this ioctl action.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 10 +++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 6 ++
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 56
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 2 +
drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 7 ++
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 109 ---
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 6 ++
7 files changed, 186 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index e000a78b782e..c35011b84f5a 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -8,6 +8,7 @@
#include "intel_pxp_tee.h"
#include "intel_pxp_arb.h"
#include "intel_pxp_sm.h"
+#include "intel_pxp_cmd.h"
/* KCR register definitions */
#define KCR_INIT_MMIO(0x320f0)
@@ -22,6 +23,8 @@ enum pxp_session_req {
PXP_REQ_SESSION_ID_INIT = 0x0,
/* Inform KMD that UMD has completed the initialization */
PXP_REQ_SESSION_IN_PLAY,
+ /* Request KMD to terminate the session */
+ PXP_REQ_SESSION_TERMINATE
};
/*
@@ -68,7 +71,11 @@ static int intel_pxp_teardown_required_callback(struct
intel_pxp *pxp)
pxp->ctx.flag_display_hm_surface_keys = false;
ret = intel_pxp_arb_terminate_session(pxp);
+ if (ret)
+ goto end;
+ ret = intel_pxp_sm_terminate_all_sessions(pxp, SESSION_TYPE_TYPE0);
+end:
mutex_unlock(>ctx.mutex);
return ret;
@@ -237,6 +244,9 @@ int i915_pxp_ops_ioctl(struct drm_device *dev, void *data,
struct drm_file *drmf
} else if (params->req_session_state ==
PXP_REQ_SESSION_IN_PLAY) {
ret = intel_pxp_sm_ioctl_mark_session_in_play(pxp,
params->session_type,
params->pxp_tag);
+ } else if (params->req_session_state ==
PXP_REQ_SESSION_TERMINATE) {
+ ret = intel_pxp_sm_ioctl_terminate_session(pxp,
params->session_type,
+
params->pxp_tag);
} else {
ret = -EINVAL;
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 461b9321441f..e68c035d8448 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -53,6 +53,12 @@ struct intel_pxp {
struct pxp_context ctx;
};
+static inline int pxp_session_max(int session_type)
+{
+ return (session_type == SESSION_TYPE_TYPE0) ?
+ PXP_MAX_NORMAL_TYPE0_SESSIONS : PXP_MAX_TYPE1_SESSIONS;
+}
+
struct drm_i915_private;
#ifdef CONFIG_DRM_I915_PXP
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
index 17ff6bd61d20..3a4c8022a5d0 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
@@ -7,6 +7,7 @@
#include "i915_drv.h"
#include "gt/intel_context.h"
#include "gt/intel_engine_pm.h"
+#include "intel_pxp_sm.h"
/* PXP GPU command definitions */
@@ -270,3 +271,58 @@ int intel_pxp_cmd_add_inline_termination(u32 *cmd)
increased_size_in_dw = (cmd_termin - cmd);
return increased_size_in_dw;
}
+
+int intel_pxp_cmd_terminate_all_hw_session(struct intel_pxp *pxp,
+ int session_type)
+{
+ u32 *cmd = NULL;
+ u32 *cmd_ptr = NULL;
+ int cmd_size_in_dw = 0;
+ int ret;
+ int idx;
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+
+ /* Calculate how many bytes need to be alloc */
+ for (idx = 0; idx < pxp_session_max(session_type); idx++) {
+ if (intel_pxp_sm_is_hw_session_in_play(pxp, session_type, idx))
{
+ cmd_size_in_dw += intel_pxp_cmd_add_prolog(pxp, NULL,
session_type, idx);
+ cmd_size_in_dw +=
intel_pxp_cmd_add_inline_termination(NULL);
+ }
+ }
+ cmd_size_in_dw += intel_pxp_cmd_add_epilog(NULL);
+
+ cmd = kzalloc(cmd_size_in_dw * 4, GFP_KERNEL);
+ if (!cmd)
+ return -ENOMEM;
+
+ /* Program the command */
+ cmd_ptr = cmd;
+ for (idx = 0; idx < pxp_session_max(session_type); idx++) {
+ if (intel_pxp_sm_is_hw_session_in_play(pxp, session_type, idx))
{
+ cmd_ptr += intel_pxp_cmd_add_prolog(pxp, cmd_ptr,
session_type, idx);
+ cmd_ptr +=
intel_pxp_cmd_add_inline_termination(cmd_ptr);
+ }
+ }
+ cmd_ptr += intel_pxp_cmd_add_epilog(cmd_ptr);
+
+ if
[Intel-gfx] [RFC-v7 13/21] drm/i915/pxp: Add plane decryption support
From: Anshuman Gupta
Add support to enable/disable PLANE_SURF Decryption Request bit.
It requires only to enable plane decryption support when following
condition met.
1. PAVP session is enabled.
2. Buffer object is protected.
v2:
- Rebased to libva_cp-drm-tip_tgl_cp tree.
- Used gen fb obj user_flags instead gem_object_metadata. [Krishna]
Cc: Bommu Krishnaiah
Cc: Huang, Sean Z
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_sprite.c | 21 ++---
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index b7e208816074..273bdc031e8d 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -39,6 +39,8 @@
#include
#include
+#include "pxp/intel_pxp.h"
+
#include "i915_drv.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
@@ -767,6 +769,11 @@ icl_program_input_csc(struct intel_plane *plane,
PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
}
+static bool intel_fb_obj_protected(const struct drm_i915_gem_object *obj)
+{
+ return obj->user_flags & I915_BO_PROTECTED ? true : false;
+}
+
static void
skl_plane_async_flip(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
@@ -803,6 +810,7 @@ skl_program_plane(struct intel_plane *plane,
u32 surf_addr = plane_state->color_plane[color_plane].offset;
u32 stride = skl_plane_stride(plane_state, color_plane);
const struct drm_framebuffer *fb = plane_state->hw.fb;
+ const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
int aux_plane = intel_main_to_aux_plane(fb, color_plane);
int crtc_x = plane_state->uapi.dst.x1;
int crtc_y = plane_state->uapi.dst.y1;
@@ -813,7 +821,7 @@ skl_program_plane(struct intel_plane *plane,
u8 alpha = plane_state->hw.alpha >> 8;
u32 plane_color_ctl = 0, aux_dist = 0;
unsigned long irqflags;
- u32 keymsk, keymax;
+ u32 keymsk, keymax, plane_surf;
u32 plane_ctl = plane_state->ctl;
plane_ctl |= skl_plane_ctl_crtc(crtc_state);
@@ -889,8 +897,15 @@ skl_program_plane(struct intel_plane *plane,
* the control register just before the surface register.
*/
intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
- intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
- intel_plane_ggtt_offset(plane_state) + surf_addr);
+ plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
+
+ if (intel_pxp_gem_object_status(dev_priv) &&
+ intel_fb_obj_protected(obj))
+ plane_surf |= PLANE_SURF_DECRYPTION_ENABLED;
+ else
+ plane_surf &= ~PLANE_SURF_DECRYPTION_ENABLED;
+
+ intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf);
if (plane_state->scaler_id >= 0)
skl_program_scaler(plane, crtc_state, plane_state);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1e8dfe435ca8..0ea7e2a402ae 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7209,6 +7209,7 @@ enum {
#define _PLANE_SURF_3(pipe)_PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
#define PLANE_SURF(pipe, plane)\
_MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
+#define PLANE_SURF_DECRYPTION_ENABLEDREG_BIT(2)
#define _PLANE_OFFSET_1_B 0x711a4
#define _PLANE_OFFSET_2_B 0x712a4
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC-v7 09/21] drm/i915/pxp: Expose session state for display protection flip
Implement the intel_pxp_gem_object_status() to allow i915 display
querying the current PXP session state. In the design, display
should not perform protection flip on the protected buffers if
there is no PXP session alive.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 9 +
drivers/gpu/drm/i915/pxp/intel_pxp.h | 8
2 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 48e926363696..ce3760206b76 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -143,3 +143,12 @@ void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
pxp->current_events |= events;
schedule_work(>irq_work);
}
+
+bool intel_pxp_gem_object_status(struct drm_i915_private *i915)
+{
+ if (i915->gt.pxp.ctx.id != 0 &&
+ i915->gt.pxp.ctx.flag_display_hm_surface_keys)
+ return true;
+ else
+ return false;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index ddcc3faa4ea3..027c0eb84a52 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -37,6 +37,8 @@ struct intel_pxp {
struct pxp_context ctx;
};
+struct drm_i915_private;
+
#ifdef CONFIG_DRM_I915_PXP
void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir);
int i915_pxp_teardown_required_callback(struct intel_pxp *pxp);
@@ -44,6 +46,7 @@ int i915_pxp_global_terminate_complete_callback(struct
intel_pxp *pxp);
int intel_pxp_init(struct intel_pxp *pxp);
void intel_pxp_uninit(struct intel_pxp *pxp);
+bool intel_pxp_gem_object_status(struct drm_i915_private *i915);
#else
static inline void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
{
@@ -67,6 +70,11 @@ static inline int intel_pxp_init(struct intel_pxp *pxp)
static inline void intel_pxp_uninit(struct intel_pxp *pxp)
{
}
+
+static inline bool intel_pxp_gem_object_status(struct drm_i915_private *i915)
+{
+ return false;
+}
#endif
#endif /* __INTEL_PXP_PM_H__ */
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC-v7 05/21] drm/i915/pxp: Func to send hardware session termination
Implement the functions to allow PXP to send a GPU command, in
order to terminate the hardware session, so hardware can recycle
this session slot for the next usage.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 156 +++
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 18 +++
3 files changed, 175 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 2c84f75b41da..abe52189986a 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -259,6 +259,7 @@ i915-y += i915_perf.o
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
pxp/intel_pxp_arb.o \
+ pxp/intel_pxp_cmd.o \
pxp/intel_pxp_context.o \
pxp/intel_pxp_tee.o
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
new file mode 100644
index ..e531ea9f3cdc
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#include "intel_pxp_cmd.h"
+#include "i915_drv.h"
+#include "gt/intel_context.h"
+#include "gt/intel_engine_pm.h"
+
+struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp,
+struct intel_context *ce,
+struct intel_gt_buffer_pool_node *pool,
+u32 *cmd_buf, int cmd_size_in_dw)
+{
+ struct i915_vma *batch = ERR_PTR(-EINVAL);
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+ u32 *cmd;
+
+ if (!ce || !ce->engine || !cmd_buf)
+ return ERR_PTR(-EINVAL);
+
+ if (cmd_size_in_dw * 4 > PAGE_SIZE) {
+ drm_err(>i915->drm, "Failed to %s, invalid
cmd_size_id_dw=[%d]\n",
+ __func__, cmd_size_in_dw);
+ return ERR_PTR(-EINVAL);
+ }
+
+ cmd = i915_gem_object_pin_map(pool->obj, I915_MAP_FORCE_WC);
+ if (IS_ERR(cmd)) {
+ drm_err(>i915->drm, "Failed to
i915_gem_object_pin_map()\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ memcpy(cmd, cmd_buf, cmd_size_in_dw * 4);
+
+ if (drm_debug_enabled(DRM_UT_DRIVER)) {
+ print_hex_dump(KERN_DEBUG, "cmd binaries:",
+ DUMP_PREFIX_OFFSET, 4, 4, cmd, cmd_size_in_dw *
4, true);
+ }
+
+ i915_gem_object_unpin_map(pool->obj);
+
+ batch = i915_vma_instance(pool->obj, ce->vm, NULL);
+ if (IS_ERR(batch)) {
+ drm_err(>i915->drm, "Failed to i915_vma_instance()\n");
+ return batch;
+ }
+
+ return batch;
+}
+
+int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int cmd_size_in_dw)
+{
+ int err = -EINVAL;
+ struct i915_vma *batch;
+ struct i915_request *rq;
+ struct intel_context *ce = NULL;
+ bool is_engine_pm_get = false;
+ bool is_batch_vma_pin = false;
+ bool is_skip_req_on_err = false;
+ bool is_engine_get_pool = false;
+ struct intel_gt_buffer_pool_node *pool = NULL;
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+
+ if (!HAS_ENGINE(gt, VCS0) ||
+ !gt->engine[VCS0]->kernel_context) {
+ err = -EINVAL;
+ goto end;
+ }
+
+ if (!cmd || (cmd_size_in_dw * 4) > PAGE_SIZE) {
+ drm_err(>i915->drm, "Failed to %s bad params\n", __func__);
+ return -EINVAL;
+ }
+
+ ce = gt->engine[VCS0]->kernel_context;
+
+ intel_engine_pm_get(ce->engine);
+ is_engine_pm_get = true;
+
+ pool = intel_gt_get_buffer_pool(gt, PAGE_SIZE);
+ if (IS_ERR(pool)) {
+ drm_err(>i915->drm, "Failed to intel_engine_get_pool()\n");
+ goto end;
+ }
+ is_engine_get_pool = true;
+
+ batch = intel_pxp_cmd_get_batch(pxp, ce, pool, cmd, cmd_size_in_dw);
+ if (IS_ERR(batch)) {
+ drm_err(>i915->drm, "Failed to
intel_pxp_cmd_get_batch()\n");
+ goto end;
+ }
+
+ err = i915_vma_pin(batch, 0, 0, PIN_USER);
+ if (err) {
+ drm_err(>i915->drm, "Failed to i915_vma_pin()\n");
+ goto end;
+ }
+ is_batch_vma_pin = true;
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq)) {
+ drm_err(>i915->drm, "Failed to
intel_context_create_request()\n");
+ goto end;
+ }
+ is_skip_req_on_err = true;
+
+ err = intel_gt_buffer_pool_mark_active(pool, rq);
+ if (err) {
+ drm_err(>i915->drm, "Failed to
intel_engine_pool_mark_active()\n");
+ goto end;
+ }
+
+
[Intel-gfx] [RFC-v7 08/21] drm/i915/pxp: Enable PXP power management
During the power event S3+ sleep/resume, hardware will lose all the
encryption keys for every hardware session, even though the
software session state was marked as alive after resume. So to
handle such case, PXP should terminate all the hardware sessions
and cleanup all the software states after the power cycle.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/gt/intel_gt_pm.c| 4 ++
drivers/gpu/drm/i915/i915_drv.c | 4 ++
drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 65
drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 31 ++
6 files changed, 106 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index abe52189986a..d419dfa4923d 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -261,6 +261,7 @@ i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp_arb.o \
pxp/intel_pxp_cmd.o \
pxp/intel_pxp_context.o \
+ pxp/intel_pxp_pm.o \
pxp/intel_pxp_tee.o
# Post-mortem debug and GPU hang state capture
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index 274aa0dd7050..09a64d0feafe 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -20,6 +20,7 @@
#include "intel_rc6.h"
#include "intel_rps.h"
#include "intel_wakeref.h"
+#include "pxp/intel_pxp_pm.h"
static void user_forcewake(struct intel_gt *gt, bool suspend)
{
@@ -241,6 +242,8 @@ int intel_gt_resume(struct intel_gt *gt)
intel_uc_resume(>uc);
+ intel_pxp_pm_resume(>pxp);
+
user_forcewake(gt, false);
out_fw:
@@ -275,6 +278,7 @@ void intel_gt_suspend_prepare(struct intel_gt *gt)
user_forcewake(gt, true);
wait_for_suspend(gt);
+ intel_pxp_pm_prepare_suspend(>pxp);
intel_uc_suspend(>uc);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9299a456adb0..af06c85e6ba7 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -68,6 +68,8 @@
#include "gt/intel_gt_pm.h"
#include "gt/intel_rc6.h"
+#include "pxp/intel_pxp_pm.h"
+
#include "i915_debugfs.h"
#include "i915_drv.h"
#include "i915_ioc32.h"
@@ -1344,6 +1346,8 @@ static int i915_drm_resume_early(struct drm_device *dev)
intel_power_domains_resume(dev_priv);
+ intel_pxp_pm_resume_early(_priv->gt.pxp);
+
enable_rpm_wakeref_asserts(_priv->runtime_pm);
return ret;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
index 3ba891f9ac26..8d3308ac3120 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
@@ -20,6 +20,7 @@ struct pxp_context {
int id;
bool global_state_attacked;
+ bool global_state_in_suspend;
bool flag_display_hm_surface_keys;
};
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
new file mode 100644
index ..0da2ecbf3b4d
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+
+#include "intel_pxp_context.h"
+#include "intel_pxp_arb.h"
+#include "intel_pxp_pm.h"
+
+void intel_pxp_pm_prepare_suspend(struct intel_pxp *pxp)
+{
+ if (pxp->ctx.id == 0)
+ return;
+
+ mutex_lock(>ctx.mutex);
+
+ /* Disable PXP-IOCTLs */
+ pxp->ctx.global_state_in_suspend = true;
+
+ mutex_unlock(>ctx.mutex);
+}
+
+void intel_pxp_pm_resume_early(struct intel_pxp *pxp)
+{
+ if (pxp->ctx.id == 0)
+ return;
+
+ mutex_lock(>ctx.mutex);
+
+ if (pxp->ctx.global_state_in_suspend) {
+ /* reset the attacked flag even there was a pending */
+ pxp->ctx.global_state_attacked = false;
+
+ pxp->ctx.flag_display_hm_surface_keys = false;
+ }
+
+ mutex_unlock(>ctx.mutex);
+}
+
+int intel_pxp_pm_resume(struct intel_pxp *pxp)
+{
+ int ret = 0;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+
+ if (pxp->ctx.id == 0)
+ return 0;
+
+ mutex_lock(>ctx.mutex);
+
+ /* Re-enable PXP-IOCTLs */
+ if (pxp->ctx.global_state_in_suspend) {
+ ret = intel_pxp_arb_terminate_session(pxp);
+ if (ret) {
+ drm_err(>i915->drm, "Failed to terminate the arb
session\n");
+ goto end;
+ }
+
+ pxp->ctx.global_state_in_suspend = false;
+ }
+
+end:
+ mutex_unlock(>ctx.mutex);
+
+ return ret;
+}
diff --git
[Intel-gfx] [RFC-v7 01/21] drm/i915/pxp: Introduce Intel PXP component
PXP (Protected Xe Path) is an i915 componment, available on GEN12+,
that helps to establish the hardware protected session and manage
the status of the alive software session, as well as its life cycle.
This patch series is to allow the kernel space to create and
manage a single hardware session (a.k.a default session or
arbitrary session). So Mesa can allocate the protected buffer,
which is encrypted with the leverage of the arbitrary hardware
session.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Kconfig | 19 +
drivers/gpu/drm/i915/Makefile| 5
drivers/gpu/drm/i915/gt/intel_gt.c | 7 +
drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 ++
drivers/gpu/drm/i915/pxp/intel_pxp.c | 27 ++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 29
drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 27 ++
drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 22 +++
8 files changed, 139 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.h
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 1e1cb245fca7..a42b9b031455 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -130,6 +130,25 @@ config DRM_I915_GVT_KVMGT
Choose this option if you want to enable KVMGT support for
Intel GVT-g.
+config DRM_I915_PXP
+ bool "Enable Intel PXP support for Intel Gen12+ platform"
+ depends on DRM_I915
+ select INTEL_MEI_PXP
+ default n
+ help
+ This option selects INTEL_MEI_ME if it isn't already selected to
+ enabled full PXP Services on Intel platforms.
+
+ PXP (Protected Xe Path) is an i915 componment, available on GEN12+,
+ that helps to establish the hardware protected session and manage
+ the status of the alive software session, as well as its life cycle.
+
+ This patch series is to allow the kernel space to create and
+ manage a single hardware session (a.k.a default session or
+ arbitrary session). So Mesa can allocate the protected buffer,
+ which is encrypted with the leverage of the arbitrary hardware
+ session.
+
menu "drm/i915 Debugging"
depends on DRM_I915
depends on EXPERT
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index f9ef5199b124..53be29dbc07d 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -255,6 +255,11 @@ i915-y += \
i915-y += i915_perf.o
+# Protected execution platform (PXP) support
+i915-$(CONFIG_DRM_I915_PXP) += \
+ pxp/intel_pxp.o \
+ pxp/intel_pxp_context.o
+
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
i915-$(CONFIG_DRM_I915_SELFTEST) += \
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 44f1d51e5ae5..d8e20ede7326 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -584,6 +584,12 @@ int intel_gt_init(struct intel_gt *gt)
if (err)
goto err_gt;
+ if (INTEL_GEN(gt->i915) >= 12) {
+ err = intel_pxp_init(>pxp);
+ if (err)
+ goto err_gt;
+ }
+
goto out_fw;
err_gt:
__intel_gt_disable(gt);
@@ -638,6 +644,7 @@ void intel_gt_driver_release(struct intel_gt *gt)
if (vm) /* FIXME being called twice on error paths :( */
i915_vm_put(vm);
+ intel_pxp_uninit(>pxp);
intel_gt_pm_fini(gt);
intel_gt_fini_scratch(gt);
intel_gt_fini_buffer_pool(gt);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 6d39a4a11bf3..05255632c2c0 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -23,6 +23,7 @@
#include "intel_rc6_types.h"
#include "intel_rps_types.h"
#include "intel_wakeref.h"
+#include "pxp/intel_pxp.h"
struct drm_i915_private;
struct i915_ggtt;
@@ -120,6 +121,8 @@ struct intel_gt {
/* Slice/subslice/EU info */
struct sseu_dev_info sseu;
} info;
+
+ struct intel_pxp pxp;
};
enum intel_gt_scratch_field {
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
new file mode 100644
index ..ba43b2c923c7
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+#include "i915_drv.h"
+#include "intel_pxp.h"
+#include "intel_pxp_context.h"
+
+int intel_pxp_init(struct intel_pxp *pxp)
+{
+ struct intel_gt *gt =
[Intel-gfx] [RFC-v7 20/21] drm/i915/pxp: Add PXP-related registers into allowlist
Add several PXP-related reg into allowlist to allow user space
driver to read the those register values.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/i915_reg.h | 6
drivers/gpu/drm/i915/intel_uncore.c | 50 -
2 files changed, 41 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0ea7e2a402ae..bcb7eb7a0e3c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -12425,4 +12425,10 @@ enum skl_power_gate {
#define TGL_ROOT_DEVICE_SKU_ULX0x2
#define TGL_ROOT_DEVICE_SKU_ULT0x4
+/* Registers for allowlist check */
+#define PXP_REG_01_LOWERBOUND _MMIO(0x32260)
+#define PXP_REG_01_UPPERBOUND _MMIO(0x32268)
+#define PXP_REG_02_LOWERBOUND _MMIO(0x32670)
+#define PXP_REG_02_UPPERBOUND _MMIO(0x32678)
+
#endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 9ac501bcfdad..dc97ec240571 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1990,16 +1990,34 @@ void intel_uncore_fini_mmio(struct intel_uncore *uncore)
}
static const struct reg_whitelist {
- i915_reg_t offset_ldw;
+ i915_reg_t offset_ldw_lowerbound;
+ i915_reg_t offset_ldw_upperbound;
i915_reg_t offset_udw;
u16 gen_mask;
u8 size;
-} reg_read_whitelist[] = { {
- .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
+} reg_read_whitelist[] = {
+ {
+ .offset_ldw_lowerbound = RING_TIMESTAMP(RENDER_RING_BASE),
+ .offset_ldw_upperbound = RING_TIMESTAMP(RENDER_RING_BASE),
.offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
.gen_mask = INTEL_GEN_MASK(4, 12),
.size = 8
-} };
+ },
+ {
+ .offset_ldw_lowerbound = PXP_REG_01_LOWERBOUND,
+ .offset_ldw_upperbound = PXP_REG_01_UPPERBOUND,
+ .offset_udw = {0},
+ .gen_mask = INTEL_GEN_MASK(4, 12),
+ .size = 4
+ },
+ {
+ .offset_ldw_lowerbound = PXP_REG_02_LOWERBOUND,
+ .offset_ldw_upperbound = PXP_REG_02_UPPERBOUND,
+ .offset_udw = {0},
+ .gen_mask = INTEL_GEN_MASK(4, 12),
+ .size = 4
+ }
+};
int i915_reg_read_ioctl(struct drm_device *dev,
void *data, struct drm_file *file)
@@ -2012,18 +2030,22 @@ int i915_reg_read_ioctl(struct drm_device *dev,
unsigned int flags;
int remain;
int ret = 0;
+ i915_reg_t offset_ldw;
entry = reg_read_whitelist;
remain = ARRAY_SIZE(reg_read_whitelist);
while (remain) {
- u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw);
+ u32 entry_offset_lb =
i915_mmio_reg_offset(entry->offset_ldw_lowerbound);
+ u32 entry_offset_ub =
i915_mmio_reg_offset(entry->offset_ldw_upperbound);
GEM_BUG_ON(!is_power_of_2(entry->size));
GEM_BUG_ON(entry->size > 8);
- GEM_BUG_ON(entry_offset & (entry->size - 1));
+ GEM_BUG_ON(entry_offset_lb & (entry->size - 1));
+ GEM_BUG_ON(entry_offset_ub & (entry->size - 1));
if (INTEL_INFO(i915)->gen_mask & entry->gen_mask &&
- entry_offset == (reg->offset & -entry->size))
+ entry_offset_lb <= (reg->offset & -entry->size) &&
+ (reg->offset & -entry->size) <= entry_offset_ub)
break;
entry++;
remain--;
@@ -2033,23 +2055,21 @@ int i915_reg_read_ioctl(struct drm_device *dev,
return -EINVAL;
flags = reg->offset & (entry->size - 1);
+ offset_ldw = _MMIO(reg->offset - flags);
with_intel_runtime_pm(>runtime_pm, wakeref) {
if (entry->size == 8 && flags == I915_REG_READ_8B_WA)
reg->val = intel_uncore_read64_2x32(uncore,
- entry->offset_ldw,
+ offset_ldw,
entry->offset_udw);
else if (entry->size == 8 && flags == 0)
- reg->val = intel_uncore_read64(uncore,
- entry->offset_ldw);
+ reg->val = intel_uncore_read64(uncore, offset_ldw);
else if (entry->size == 4 && flags == 0)
- reg->val = intel_uncore_read(uncore, entry->offset_ldw);
+ reg->val = intel_uncore_read(uncore, offset_ldw);
else if (entry->size == 2 && flags == 0)
- reg->val = intel_uncore_read16(uncore,
- entry->offset_ldw);
+ reg->val = intel_uncore_read16(uncore, offset_ldw);
[Intel-gfx] [RFC-v7 02/21] drm/i915/pxp: set KCR reg init during the boot time
Set the KCR init during the boot time, which is
required by hardware, to allow us doing further
protection operation such as sending commands to
GPU or TEE.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index ba43b2c923c7..c4815950567d 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -6,6 +6,12 @@
#include "intel_pxp.h"
#include "intel_pxp_context.h"
+/* KCR register definitions */
+#define KCR_INIT_MMIO(0x320f0)
+#define KCR_INIT_MASK_SHIFT (16)
+/* Setting KCR Init bit is required after system boot */
+#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) <<
KCR_INIT_MASK_SHIFT))
+
int intel_pxp_init(struct intel_pxp *pxp)
{
struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
@@ -16,6 +22,8 @@ int intel_pxp_init(struct intel_pxp *pxp)
intel_pxp_ctx_init(>ctx);
+ intel_uncore_write(gt->uncore, KCR_INIT,
KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
+
drm_info(>i915->drm, "Protected Xe Path (PXP) protected content
support initialized\n");
return 0;
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC-v7 19/21] drm/i915/pxp: Termiante the session upon app crash
PXP should terminate the hardware session and cleanup the software
state gracefully when the application has established the
protection session, but doesn't close the session correctly due to
some cases like application crash.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/i915_drv.c | 3 +++
drivers/gpu/drm/i915/pxp/intel_pxp.c| 15 +++
drivers/gpu/drm/i915/pxp/intel_pxp.h| 5 +
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 25 +
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 1 +
5 files changed, 49 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 3dbda949bf71..e74201e81369 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -69,6 +69,7 @@
#include "gt/intel_rc6.h"
#include "pxp/intel_pxp_pm.h"
+#include "pxp/intel_pxp.h"
#include "i915_debugfs.h"
#include "i915_drv.h"
@@ -1026,6 +1027,8 @@ static void i915_driver_postclose(struct drm_device *dev,
struct drm_file *file)
/* Catch up with all the deferred frees from "this" client */
i915_gem_flush_free_objects(to_i915(dev));
+
+ intel_pxp_close(&(to_i915(dev)->gt.pxp), file);
}
static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 46ad2ab229c1..3a49dd97cab2 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -320,3 +320,18 @@ int i915_pxp_ops_ioctl(struct drm_device *dev, void *data,
struct drm_file *drmf
ret = -EFAULT;
return ret;
}
+
+void intel_pxp_close(struct intel_pxp *pxp, struct drm_file *drmfile)
+{
+ int ret;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+
+ if (pxp->ctx.id == 0 || !drmfile)
+ return;
+
+ mutex_lock(>ctx.mutex);
+ ret = intel_pxp_sm_close(pxp, drmfile);
+ if (ret)
+ drm_err(>i915->drm, "Failed to %s, ret=[%d]\n", __func__,
ret);
+ mutex_unlock(>ctx.mutex);
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 133e3df9b1f6..ffb460327315 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -64,6 +64,7 @@ int intel_pxp_init(struct intel_pxp *pxp);
void intel_pxp_uninit(struct intel_pxp *pxp);
bool intel_pxp_gem_object_status(struct drm_i915_private *i915);
int i915_pxp_ops_ioctl(struct drm_device *dev, void *data, struct drm_file
*drmfile);
+void intel_pxp_close(struct intel_pxp *pxp, struct drm_file *drmfile);
#else
static inline void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
{
@@ -97,6 +98,10 @@ static inline int i915_pxp_ops_ioctl(struct drm_device *dev,
void *data, struct
{
return 0;
}
+
+static inline void intel_pxp_close(struct intel_pxp *pxp, struct drm_file
*drmfile)
+{
+}
#endif
#endif /* __INTEL_PXP_PM_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index c4b55e1531c1..e03c2b039192 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -460,3 +460,28 @@ int intel_pxp_sm_ioctl_query_pxp_tag(struct intel_pxp *pxp,
return 0;
}
+
+int intel_pxp_sm_close(struct intel_pxp *pxp, struct drm_file *drmfile)
+{
+ int ret;
+ struct intel_pxp_sm_session *curr, *n;
+
+ list_for_each_entry_safe(curr, n, session_list(pxp,
SESSION_TYPE_TYPE0), list) {
+ if (curr->drmfile && curr->drmfile == drmfile &&
+ curr->pid == pid_nr(drmfile->pid)) {
+ ret = pxp_terminate_hw_session(pxp, curr->type,
+ curr->index);
+ if (ret)
+ return ret;
+
+ ret = pxp_set_pxp_tag(pxp, curr->type, curr->index,
+ PROTECTION_MODE_NONE);
+ if (ret)
+ return ret;
+
+ list_del(>list);
+ kfree(curr);
+ }
+ }
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
index 09a26bb7a1a4..d2acbd1298b4 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
@@ -50,4 +50,5 @@ int intel_pxp_sm_ioctl_query_pxp_tag(struct intel_pxp *pxp,
bool intel_pxp_sm_is_hw_session_in_play(struct intel_pxp *pxp,
int session_type, int session_index);
int intel_pxp_sm_terminate_all_sessions(struct intel_pxp *pxp, int
session_type);
+int intel_pxp_sm_close(struct intel_pxp *pxp, struct drm_file *drmfile);
#endif /* __INTEL_PXP_SM_H__ */
--
2.17.1
___
Intel-gfx mailing list
[Intel-gfx] [RFC-v7 12/21] drm/i915/pxp: User interface for Protected buffer
From: Bommu Krishnaiah
This api allow user mode to create Protected buffer and context creation.
Signed-off-by: Bommu Krishnaiah
Cc: Telukuntla Sreedhar
Cc: Kondapally Kalyan
Cc: Gupta Anshuman
Cc: Huang Sean Z
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 15 ++--
drivers/gpu/drm/i915/gem/i915_gem_context.h | 10
.../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +-
.../gpu/drm/i915/gem/i915_gem_object_types.h | 5
drivers/gpu/drm/i915/i915_gem.c | 23 +++
include/uapi/drm/i915_drm.h | 19 +++
6 files changed, 67 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index ad136d009d9b..56cf03cec355 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -2061,12 +2061,23 @@ static int ctx_setparam(struct drm_i915_file_private
*fpriv,
case I915_CONTEXT_PARAM_RECOVERABLE:
if (args->size)
ret = -EINVAL;
- else if (args->value)
- i915_gem_context_set_recoverable(ctx);
+ else if (args->value) {
+ if (!i915_gem_context_is_protected(ctx))
+ i915_gem_context_set_recoverable(ctx);
+ else
+ ret = -EPERM;
+ }
else
i915_gem_context_clear_recoverable(ctx);
break;
+ case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
+ if (args->size)
+ ret = -EINVAL;
+ else if (args->value)
+ i915_gem_context_set_protected(ctx);
+ break;
+
case I915_CONTEXT_PARAM_PRIORITY:
ret = set_priority(ctx, args);
break;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h
b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index a133f92bbedb..5897e7ca11a8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -70,6 +70,16 @@ static inline void i915_gem_context_set_recoverable(struct
i915_gem_context *ctx
set_bit(UCONTEXT_RECOVERABLE, >user_flags);
}
+static inline void i915_gem_context_set_protected(struct i915_gem_context *ctx)
+{
+ set_bit(UCONTEXT_PROTECTED, >user_flags);
+}
+
+static inline bool i915_gem_context_is_protected(struct i915_gem_context *ctx)
+{
+ return test_bit(UCONTEXT_PROTECTED, >user_flags);
+}
+
static inline void i915_gem_context_clear_recoverable(struct i915_gem_context
*ctx)
{
clear_bit(UCONTEXT_RECOVERABLE, >user_flags);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
index ae14ca24a11f..81ae94c2be86 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
@@ -135,7 +135,7 @@ struct i915_gem_context {
#define UCONTEXT_BANNABLE 2
#define UCONTEXT_RECOVERABLE 3
#define UCONTEXT_PERSISTENCE 4
-
+#define UCONTEXT_PROTECTED 5
/**
* @flags: small set of booleans
*/
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index e2d9b7e1e152..90ac955463f4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -161,6 +161,11 @@ struct drm_i915_gem_object {
} mmo;
I915_SELFTEST_DECLARE(struct list_head st_link);
+ /**
+* @user_flags: small set of booleans set by the user
+*/
+ unsigned long user_flags;
+#define I915_BO_PROTECTED BIT(0)
unsigned long flags;
#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 41698a823737..6a791fd24eaa 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -184,7 +184,8 @@ static int
i915_gem_create(struct drm_file *file,
struct intel_memory_region *mr,
u64 *size_p,
- u32 *handle_p)
+ u32 *handle_p,
+ u64 user_flags)
{
struct drm_i915_gem_object *obj;
u32 handle;
@@ -204,6 +205,8 @@ i915_gem_create(struct drm_file *file,
if (IS_ERR(obj))
return PTR_ERR(obj);
+ obj->user_flags = user_flags;
+
ret = drm_gem_handle_create(file, >base, );
/* drop reference from allocate - handle holds it now */
i915_gem_object_put(obj);
@@ -258,11 +261,12 @@ i915_gem_dumb_create(struct drm_file *file,
return i915_gem_create(file,
intel_memory_region_by_type(to_i915(dev),
[Intel-gfx] [RFC-v7 06/21] drm/i915/pxp: Enable PXP irq worker and callback stub
Create the irq worker that serves as callback handler, those
callback stubs should be called while the hardware key teardown
occurs.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 4 +
drivers/gpu/drm/i915/i915_reg.h | 3 +-
drivers/gpu/drm/i915/pxp/intel_pxp.c | 101 +++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 27 +
drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 2 +
drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 1 +
6 files changed, 137 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index 9830342aa6f4..b92072554ab3 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -14,6 +14,7 @@
#include "intel_lrc_reg.h"
#include "intel_uncore.h"
#include "intel_rps.h"
+#include "pxp/intel_pxp.h"
static void guc_irq_handler(struct intel_guc *guc, u16 iir)
{
@@ -107,6 +108,9 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8
instance,
if (instance == OTHER_GTPM_INSTANCE)
return gen11_rps_irq_handler(>rps, iir);
+ if (instance == OTHER_KCR_INSTANCE)
+ return intel_pxp_irq_handler(>pxp, iir);
+
WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
instance, iir);
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0023c023f472..1e8dfe435ca8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7944,6 +7944,7 @@ enum {
/* irq instances for OTHER_CLASS */
#define OTHER_GUC_INSTANCE 0
#define OTHER_GTPM_INSTANCE1
+#define OTHER_KCR_INSTANCE 4
#define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
@@ -7966,7 +7967,7 @@ enum {
#define GEN11_VECS0_VECS1_INTR_MASK_MMIO(0x1900d0)
#define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8)
#define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec)
-#define GEN11_CRYPTO_RSVD_INTR_MASK_MMIO(0x1900f0)
+#define GEN11_CRYPTO_INTR_MASK _MMIO(0x1900f0) /* crypto mask is in
bit31-16 (Engine1 Interrupt Mask) */
#define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4)
#define ENGINE1_MASK REG_GENMASK(31, 16)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 67bdaeb79b40..9bcb170b34f1 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -14,6 +14,70 @@
/* Setting KCR Init bit is required after system boot */
#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) <<
KCR_INIT_MASK_SHIFT))
+static void intel_pxp_write_irq_mask_reg(struct intel_gt *gt, u32 mask)
+{
+ lockdep_assert_held(>irq_lock);
+
+ intel_uncore_write(gt->uncore, GEN11_CRYPTO_INTR_MASK, mask << 16);
+}
+
+static int intel_pxp_teardown_required_callback(struct intel_pxp *pxp)
+{
+ int ret;
+
+ mutex_lock(>ctx.mutex);
+
+ pxp->ctx.global_state_attacked = true;
+
+ mutex_unlock(>ctx.mutex);
+
+ return ret;
+}
+
+static int intel_pxp_global_terminate_complete_callback(struct intel_pxp *pxp)
+{
+ int ret = 0;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+
+ mutex_lock(>ctx.mutex);
+
+ if (pxp->ctx.global_state_attacked) {
+ pxp->ctx.global_state_attacked = false;
+
+ /* Re-create the arb session after teardown handle complete */
+ ret = intel_pxp_arb_create_session(pxp);
+ if (ret) {
+ drm_err(>i915->drm, "Failed to create arb
session\n");
+ goto end;
+ }
+ }
+end:
+ mutex_unlock(>ctx.mutex);
+ return ret;
+}
+
+static void intel_pxp_irq_work(struct work_struct *work)
+{
+ struct intel_pxp *pxp = container_of(work, typeof(*pxp), irq_work);
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+ u32 events = 0;
+
+ spin_lock_irq(>irq_lock);
+ events = fetch_and_zero(>current_events);
+ spin_unlock_irq(>irq_lock);
+
+ if (events & PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED ||
+ events & PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ)
+ intel_pxp_teardown_required_callback(pxp);
+
+ if (events & PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE)
+ intel_pxp_global_terminate_complete_callback(pxp);
+
+ spin_lock_irq(>irq_lock);
+ intel_pxp_write_irq_mask_reg(gt, 0);
+ spin_unlock_irq(>irq_lock);
+}
+
int intel_pxp_init(struct intel_pxp *pxp)
{
struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
@@ -28,6 +92,12 @@ int intel_pxp_init(struct intel_pxp *pxp)
intel_pxp_tee_component_init(pxp);
+ INIT_WORK(>irq_work, intel_pxp_irq_work);
+
+ pxp->handled_irr = (PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED |
+
[Intel-gfx] [RFC-v7 07/21] drm/i915/pxp: Destroy arb session upon teardown
Teardown is triggered when the display topology changes and no
long meets the secure playback requirement, and hardware trashes
all the encryption keys for display. So as a result, PXP should
handle such case and terminate the type0 sessions, which including
arb session
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 3 +
drivers/gpu/drm/i915/pxp/intel_pxp_arb.c | 76 +
drivers/gpu/drm/i915/pxp/intel_pxp_arb.h | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 129 ++-
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 12 ++-
5 files changed, 211 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 9bcb170b34f1..48e926363696 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -28,6 +28,9 @@ static int intel_pxp_teardown_required_callback(struct
intel_pxp *pxp)
mutex_lock(>ctx.mutex);
pxp->ctx.global_state_attacked = true;
+ pxp->ctx.flag_display_hm_surface_keys = false;
+
+ ret = intel_pxp_arb_terminate_session(pxp);
mutex_unlock(>ctx.mutex);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
index 9611cd53d3a4..d94b08fe9190 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
@@ -10,6 +10,7 @@
#include "intel_pxp.h"
#include "intel_pxp_context.h"
#include "intel_pxp_tee.h"
+#include "intel_pxp_cmd.h"
#define GEN12_KCR_SIP _MMIO(0x32260) /* KCR type0 session in play 0-31 */
@@ -132,3 +133,78 @@ int intel_pxp_arb_create_session(struct intel_pxp *pxp)
end:
return ret;
}
+
+static int intel_pxp_arb_session_with_global_termination(struct intel_pxp *pxp)
+{
+ u32 *cmd = NULL;
+ u32 *cmd_ptr = NULL;
+ int cmd_size_in_dw = 0;
+ int ret;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+
+ /* Calculate how many bytes need to be alloc */
+ cmd_size_in_dw += intel_pxp_cmd_add_prolog(pxp, NULL, ARB_SESSION_TYPE,
ARB_SESSION_INDEX);
+ cmd_size_in_dw += intel_pxp_cmd_add_inline_termination(NULL);
+ cmd_size_in_dw += intel_pxp_cmd_add_epilog(NULL);
+
+ cmd = kzalloc(cmd_size_in_dw * 4, GFP_KERNEL);
+ if (!cmd)
+ return -ENOMEM;
+
+ /* Program the command */
+ cmd_ptr = cmd;
+ cmd_ptr += intel_pxp_cmd_add_prolog(pxp, cmd_ptr, ARB_SESSION_TYPE,
ARB_SESSION_INDEX);
+ cmd_ptr += intel_pxp_cmd_add_inline_termination(cmd_ptr);
+ cmd_ptr += intel_pxp_cmd_add_epilog(cmd_ptr);
+
+ if (cmd_size_in_dw != (cmd_ptr - cmd)) {
+ ret = -EINVAL;
+ drm_err(>i915->drm, "Failed to %s\n", __func__);
+ goto end;
+ }
+
+ if (drm_debug_enabled(DRM_UT_DRIVER)) {
+ print_hex_dump(KERN_DEBUG, "global termination cmd binaries:",
+ DUMP_PREFIX_OFFSET, 4, 4, cmd, cmd_size_in_dw *
4, true);
+ }
+
+ ret = intel_pxp_cmd_submit(pxp, cmd, cmd_size_in_dw);
+ if (ret) {
+ drm_err(>i915->drm, "Failed to intel_pxp_cmd_submit()\n");
+ goto end;
+ }
+
+end:
+ kfree(cmd);
+ return ret;
+}
+
+/**
+ * intel_pxp_arb_terminate_session - Terminate the arb hw session and its
entries.
+ * @pxp: pointer to pxp struct.
+ *
+ * This function is NOT intended to be called from the ioctl, and need to be
protected by
+ * ctx.mutex to ensure no SIP change during the call.
+ *
+ * Return: status. 0 means terminate is successful.
+ */
+int intel_pxp_arb_terminate_session(struct intel_pxp *pxp)
+{
+ int ret;
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+ struct pxp_protected_session *arb = >ctx.arb_session;
+
+ lockdep_assert_held(>ctx.mutex);
+
+ /* terminate the hw sessions */
+ ret = intel_pxp_arb_session_with_global_termination(pxp);
+ if (ret) {
+ drm_err(>i915->drm, "Failed to
intel_pxp_arb_session_with_global_termination\n");
+ return ret;
+ }
+
+ arb->is_in_play = false;
+
+ return ret;
+}
+
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
index c6a6000f5be5..d4e33ac7c2bd 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
@@ -34,5 +34,6 @@ struct pxp_protected_session {
};
int intel_pxp_arb_create_session(struct intel_pxp *pxp);
+int intel_pxp_arb_terminate_session(struct intel_pxp *pxp);
#endif /* __INTEL_PXP_ARB_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
index e531ea9f3cdc..079024d5f063 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
@@ -8,10 +8,29 @@
#include "gt/intel_context.h"
#include "gt/intel_engine_pm.h"
-struct
[Intel-gfx] [RFC-v7 03/21] drm/i915/pxp: Implement funcs to create the TEE channel
Implement the funcs to create the TEE channel, so kernel can
send the TEE commands directly to TEE for creating the arbitrary
(defualt) session.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile| 3 +-
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 6 ++
drivers/gpu/drm/i915/pxp/intel_pxp.c | 5 +
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 132 +++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 14 +++
include/drm/i915_component.h | 1 +
include/drm/i915_pxp_tee_interface.h | 45
8 files changed, 206 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
create mode 100644 include/drm/i915_pxp_tee_interface.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 53be29dbc07d..57447887d352 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -258,7 +258,8 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
- pxp/intel_pxp_context.o
+ pxp/intel_pxp_context.o \
+ pxp/intel_pxp_tee.o
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5708e11d917b..9299a456adb0 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -322,6 +322,7 @@ static int i915_driver_early_probe(struct drm_i915_private
*dev_priv)
mutex_init(_priv->wm.wm_mutex);
mutex_init(_priv->pps_mutex);
mutex_init(_priv->hdcp_comp_mutex);
+ mutex_init(_priv->pxp_tee_comp_mutex);
i915_memcpy_init_early(dev_priv);
intel_runtime_pm_init_early(_priv->runtime_pm);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5d04b282c060..2e997f753054 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1215,6 +1215,12 @@ struct drm_i915_private {
/* Mutex to protect the above hdcp component related values. */
struct mutex hdcp_comp_mutex;
+ struct i915_pxp_comp_master *pxp_tee_master;
+ bool pxp_tee_comp_added;
+
+ /* Mutex to protect the above pxp_tee component related values. */
+ struct mutex pxp_tee_comp_mutex;
+
I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
/*
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index c4815950567d..4104dd89ca7f 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -5,6 +5,7 @@
#include "i915_drv.h"
#include "intel_pxp.h"
#include "intel_pxp_context.h"
+#include "intel_pxp_tee.h"
/* KCR register definitions */
#define KCR_INIT_MMIO(0x320f0)
@@ -24,6 +25,8 @@ int intel_pxp_init(struct intel_pxp *pxp)
intel_uncore_write(gt->uncore, KCR_INIT,
KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
+ intel_pxp_tee_component_init(pxp);
+
drm_info(>i915->drm, "Protected Xe Path (PXP) protected content
support initialized\n");
return 0;
@@ -31,5 +34,7 @@ int intel_pxp_init(struct intel_pxp *pxp)
void intel_pxp_uninit(struct intel_pxp *pxp)
{
+ intel_pxp_tee_component_fini(pxp);
+
intel_pxp_ctx_fini(>ctx);
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
new file mode 100644
index ..ca6b61099aee
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+
+#include
+#include "drm/i915_pxp_tee_interface.h"
+#include "drm/i915_component.h"
+#include "i915_drv.h"
+#include "intel_pxp.h"
+#include "intel_pxp_context.h"
+#include "intel_pxp_tee.h"
+
+static int intel_pxp_tee_io_message(struct intel_pxp *pxp,
+ void *msg_in, u32 msg_in_size,
+ void *msg_out, u32 *msg_out_size_ptr,
+ u32 msg_out_buf_size)
+{
+ int ret;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+ struct drm_i915_private *i915 = gt->i915;
+ struct i915_pxp_comp_master *pxp_tee_master = i915->pxp_tee_master;
+
+ if (!pxp_tee_master || !msg_in || !msg_out || !msg_out_size_ptr)
+ return -EINVAL;
+
+ lockdep_assert_held(>pxp_tee_comp_mutex);
+
+ if (drm_debug_enabled(DRM_UT_DRIVER))
+ print_hex_dump(KERN_DEBUG, "TEE input message binaries:",
+ DUMP_PREFIX_OFFSET, 4, 4, msg_in, msg_in_size,
true);
+
+ ret = pxp_tee_master->ops->send(pxp_tee_master->tee_dev, msg_in,
msg_in_size);
+ if (ret) {
+ drm_err(>drm, "Failed
[Intel-gfx] [RFC-v7 00/21] Introduce Intel PXP component - Mesa single session
PXP (Protected Xe Path) is an i915 componment, available on GEN12+ that helps to establish the hardware protected session and manage the status of the alive software session, as well as its life cycle. [commit #1 - #13] This patch series is to allow the kernel space to create and manage a single hardware session (a.k.a default session or arbitrary session). So user can allocate the protected buffer, which is encrypted with the leverage of the arbitrary hardware session. [commit #14 - #21] This patch series exposes ioctl so allow userspace to create, set, and destroy one or multiple sessions. It will also provide the communication chanel to TEE (Trusted Execution Environment) for the protected hardware session creation. v2: - modification based on code reivew feedbacks received - passing pxp instead of i915 as funciton argument - remove dead code only for multi-session - move the pxp init call from i915_drv.c to intel_gt.c - reove the tautology naming v3: - rebase to latest drm-tip v4: - Append the split non-mesa patch sereis (commit #14 - #21) into this patch series v5: - include "intel_pxp.h" in intel_pxp_sm.h at commit #14 to fix the build problem. v6: - Fix the null pointer arb_session access bug in intel_pxp_arb.c in "04 [RFC-v5] drm/i915/pxp: Create the arbitrary session after boot" v7: - Use list_for_each_entry_safe instead of list_for_each_entry Anshuman Gupta (1): drm/i915/pxp: Add plane decryption support Bommu Krishnaiah (2): drm/i915/uapi: introduce drm_i915_gem_create_ext drm/i915/pxp: User interface for Protected buffer Huang, Sean Z (17): drm/i915/pxp: Introduce Intel PXP component drm/i915/pxp: set KCR reg init during the boot time drm/i915/pxp: Implement funcs to create the TEE channel drm/i915/pxp: Create the arbitrary session after boot drm/i915/pxp: Func to send hardware session termination drm/i915/pxp: Enable PXP irq worker and callback stub drm/i915/pxp: Destroy arb session upon teardown drm/i915/pxp: Enable PXP power management drm/i915/pxp: Expose session state for display protection flip drm/i915/pxp: Implement ioctl action to reserve session slots drm/i915/pxp: Implement ioctl action to set session in play drm/i915/pxp: Implement ioctl action to terminate the session drm/i915/pxp: Implement ioctl action to send TEE commands drm/i915/pxp: Implement ioctl action to query PXP tag drm/i915/pxp: Termiante the session upon app crash drm/i915/pxp: Add PXP-related registers into allowlist drm/i915/pxp: Enable the PXP ioctl for protected session Vitaly Lubart (1): mei: pxp: export pavp client to me client bus drivers/gpu/drm/i915/Kconfig | 19 + drivers/gpu/drm/i915/Makefile | 10 + drivers/gpu/drm/i915/display/intel_sprite.c | 21 +- drivers/gpu/drm/i915/gem/i915_gem_context.c | 15 +- drivers/gpu/drm/i915/gem/i915_gem_context.h | 10 + .../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +- .../gpu/drm/i915/gem/i915_gem_object_types.h | 5 + drivers/gpu/drm/i915/gt/intel_gt.c| 7 + drivers/gpu/drm/i915/gt/intel_gt_irq.c| 4 + drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 + drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 + drivers/gpu/drm/i915/i915_drv.c | 11 +- drivers/gpu/drm/i915/i915_drv.h | 6 + drivers/gpu/drm/i915/i915_gem.c | 63 ++- drivers/gpu/drm/i915/i915_reg.h | 10 +- drivers/gpu/drm/i915/intel_uncore.c | 50 +- drivers/gpu/drm/i915/pxp/intel_pxp.c | 284 ++ drivers/gpu/drm/i915/pxp/intel_pxp.h | 107 drivers/gpu/drm/i915/pxp/intel_pxp_arb.c | 208 drivers/gpu/drm/i915/pxp/intel_pxp_arb.h | 39 ++ drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 328 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 22 + drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 32 ++ drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 42 ++ drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 72 +++ drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 31 ++ drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 487 ++ drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 54 ++ drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 227 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 25 + drivers/misc/mei/Kconfig | 2 + drivers/misc/mei/Makefile | 1 + drivers/misc/mei/pxp/Kconfig | 13 + drivers/misc/mei/pxp/Makefile | 7 + drivers/misc/mei/pxp/mei_pxp.c| 230 + drivers/misc/mei/pxp/mei_pxp.h| 18 + include/drm/i915_component.h | 1 + include/drm/i915_pxp_tee_interface.h | 45 ++ include/uapi/drm/i915_drm.h | 138 + 39 files changed, 2626 insertions(+), 27 deletions(-) create mode 100644
[Intel-gfx] [PATCH 10/11] drm/i915: move pipe update code into crtc.
From: Dave Airlie
Daniel suggested this should move here.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_crtc.c | 230
drivers/gpu/drm/i915/display/intel_sprite.c | 228 ---
2 files changed, 230 insertions(+), 228 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
b/drivers/gpu/drm/i915/display/intel_crtc.c
index 0161e18f1a50..9010c55bbc4e 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -10,6 +10,9 @@
#include
#include
+#include "i915_trace.h"
+#include "i915_vgpu.h"
+
#include "intel_atomic.h"
#include "intel_atomic_plane.h"
#include "intel_color.h"
@@ -17,7 +20,9 @@
#include "intel_cursor.h"
#include "intel_display_debugfs.h"
#include "intel_display_types.h"
+#include "intel_dsi.h"
#include "intel_pipe_crc.h"
+#include "intel_psr.h"
#include "intel_sprite.h"
/* Primary plane formats for gen <= 3 */
@@ -955,3 +960,228 @@ int intel_crtc_init(struct drm_i915_private *dev_priv,
enum pipe pipe)
return ret;
}
+
+int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
+int usecs)
+{
+ /* paranoia */
+ if (!adjusted_mode->crtc_htotal)
+ return 1;
+
+ return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
+ 1000 * adjusted_mode->crtc_htotal);
+}
+
+/**
+ * intel_pipe_update_start() - start update of a set of display registers
+ * @new_crtc_state: the new crtc state
+ *
+ * Mark the start of an update to pipe registers that should be updated
+ * atomically regarding vblank. If the next vblank will happens within
+ * the next 100 us, this function waits until the vblank passes.
+ *
+ * After a successful call to this function, interrupts will be disabled
+ * until a subsequent call to intel_pipe_update_end(). That is done to
+ * avoid random delays.
+ */
+void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct drm_display_mode *adjusted_mode =
_crtc_state->hw.adjusted_mode;
+ long timeout = msecs_to_jiffies_timeout(1);
+ int scanline, min, max, vblank_start;
+ wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(>base);
+ bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) ||
IS_CHERRYVIEW(dev_priv)) &&
+ intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI);
+ DEFINE_WAIT(wait);
+ u32 psr_status;
+
+ if (new_crtc_state->uapi.async_flip)
+ return;
+
+ vblank_start = adjusted_mode->crtc_vblank_start;
+ if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
+ vblank_start = DIV_ROUND_UP(vblank_start, 2);
+
+ /* FIXME needs to be calibrated sensibly */
+ min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
+ VBLANK_EVASION_TIME_US);
+ max = vblank_start - 1;
+
+ if (min <= 0 || max <= 0)
+ goto irq_disable;
+
+ if (drm_WARN_ON(_priv->drm, drm_crtc_vblank_get(>base)))
+ goto irq_disable;
+
+ /*
+* Wait for psr to idle out after enabling the VBL interrupts
+* VBL interrupts will start the PSR exit and prevent a PSR
+* re-entry as well.
+*/
+ if (intel_psr_wait_for_idle(new_crtc_state, _status))
+ drm_err(_priv->drm,
+ "PSR idle timed out 0x%x, atomic update may fail\n",
+ psr_status);
+
+ local_irq_disable();
+
+ crtc->debug.min_vbl = min;
+ crtc->debug.max_vbl = max;
+ trace_intel_pipe_update_start(crtc);
+
+ for (;;) {
+ /*
+* prepare_to_wait() has a memory barrier, which guarantees
+* other CPUs can see the task state update by the time we
+* read the scanline.
+*/
+ prepare_to_wait(wq, , TASK_UNINTERRUPTIBLE);
+
+ scanline = intel_get_crtc_scanline(crtc);
+ if (scanline < min || scanline > max)
+ break;
+
+ if (!timeout) {
+ drm_err(_priv->drm,
+ "Potential atomic update failure on pipe %c\n",
+ pipe_name(crtc->pipe));
+ break;
+ }
+
+ local_irq_enable();
+
+ timeout = schedule_timeout(timeout);
+
+ local_irq_disable();
+ }
+
+ finish_wait(wq, );
+
+ drm_crtc_vblank_put(>base);
+
+ /*
+* On VLV/CHV DSI the scanline counter would appear to
+* increment approx. 1/3 of a scanline before start of vblank.
+* The registers still get latched at start of vblank however.
+*
[Intel-gfx] [PATCH 07/11] drm/i915: split fdi code out from intel_display.c
From: Dave Airlie
This just refactors out the fdi code to a separate file.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 685 +-
.../drm/i915/display/intel_display_types.h| 9 +
drivers/gpu/drm/i915/display/intel_fdi.c | 683 +
drivers/gpu/drm/i915/display/intel_fdi.h | 21 +
5 files changed, 717 insertions(+), 682 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_fdi.c
create mode 100644 drivers/gpu/drm/i915/display/intel_fdi.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 5d533de16335..c46c19a4e830 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -206,6 +206,7 @@ i915-y += \
display/intel_dpll_mgr.o \
display/intel_dsb.o \
display/intel_fbc.o \
+ display/intel_fdi.o \
display/intel_fifo_underrun.o \
display/intel_frontbuffer.o \
display/intel_global_state.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index a0d9cd7b4e34..b582114a9d63 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -74,6 +74,7 @@
#include "intel_display_types.h"
#include "intel_dp_link_training.h"
#include "intel_fbc.h"
+#include "intel_fdi.h"
#include "intel_fbdev.h"
#include "intel_fifo_underrun.h"
#include "intel_frontbuffer.h"
@@ -172,16 +173,6 @@ static void intel_update_czclk(struct drm_i915_private
*dev_priv)
dev_priv->czclk_freq);
}
-/* units of 100MHz */
-static u32 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
- const struct intel_crtc_state *pipe_config)
-{
- if (HAS_DDI(dev_priv))
- return pipe_config->port_clock; /* SPLL */
- else
- return dev_priv->fdi_pll_freq;
-}
-
/* WA Display #0827: Gen9:all */
static void
skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
@@ -3766,532 +3757,6 @@ static void icl_set_pipe_chicken(struct intel_crtc
*crtc)
intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
}
-static void intel_fdi_normal_train(struct intel_crtc *crtc)
-{
- struct drm_device *dev = crtc->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- enum pipe pipe = crtc->pipe;
- i915_reg_t reg;
- u32 temp;
-
- /* enable normal train */
- reg = FDI_TX_CTL(pipe);
- temp = intel_de_read(dev_priv, reg);
- if (IS_IVYBRIDGE(dev_priv)) {
- temp &= ~FDI_LINK_TRAIN_NONE_IVB;
- temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
- } else {
- temp &= ~FDI_LINK_TRAIN_NONE;
- temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
- }
- intel_de_write(dev_priv, reg, temp);
-
- reg = FDI_RX_CTL(pipe);
- temp = intel_de_read(dev_priv, reg);
- if (HAS_PCH_CPT(dev_priv)) {
- temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
- temp |= FDI_LINK_TRAIN_NORMAL_CPT;
- } else {
- temp &= ~FDI_LINK_TRAIN_NONE;
- temp |= FDI_LINK_TRAIN_NONE;
- }
- intel_de_write(dev_priv, reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
-
- /* wait one idle pattern time */
- intel_de_posting_read(dev_priv, reg);
- udelay(1000);
-
- /* IVB wants error correction enabled */
- if (IS_IVYBRIDGE(dev_priv))
- intel_de_write(dev_priv, reg,
- intel_de_read(dev_priv, reg) |
FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE);
-}
-
-/* The FDI link training functions for ILK/Ibexpeak. */
-static void ilk_fdi_link_train(struct intel_crtc *crtc,
- const struct intel_crtc_state *crtc_state)
-{
- struct drm_device *dev = crtc->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- enum pipe pipe = crtc->pipe;
- i915_reg_t reg;
- u32 temp, tries;
-
- /* FDI needs bits from pipe first */
- assert_pipe_enabled(dev_priv, crtc_state->cpu_transcoder);
-
- /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
- for train result */
- reg = FDI_RX_IMR(pipe);
- temp = intel_de_read(dev_priv, reg);
- temp &= ~FDI_RX_SYMBOL_LOCK;
- temp &= ~FDI_RX_BIT_LOCK;
- intel_de_write(dev_priv, reg, temp);
- intel_de_read(dev_priv, reg);
- udelay(150);
-
- /* enable CPU FDI TX and PCH FDI RX */
- reg = FDI_TX_CTL(pipe);
- temp = intel_de_read(dev_priv, reg);
- temp &= ~FDI_DP_PORT_WIDTH_MASK;
- temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
- temp &= ~FDI_LINK_TRAIN_NONE;
- temp |= FDI_LINK_TRAIN_PATTERN_1;
- intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
-
- reg =
[Intel-gfx] [PATCH 11/11] drm/i915: split fb scalable checks into g4x and skl versions
From: Dave Airlie
This just cleans these up a bit.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_gen9_plane.c | 4 ++--
drivers/gpu/drm/i915/display/intel_sprite.c | 7 +++
2 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_gen9_plane.c
b/drivers/gpu/drm/i915/display/intel_gen9_plane.c
index d547edabb5ce..487bc0166e31 100644
--- a/drivers/gpu/drm/i915/display/intel_gen9_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_gen9_plane.c
@@ -2139,7 +2139,7 @@ static int skl_check_plane_surface(struct
intel_plane_state *plane_state)
return 0;
}
-static bool intel_fb_scalable(const struct drm_framebuffer *fb)
+static bool skl_fb_scalable(const struct drm_framebuffer *fb)
{
if (!fb)
return false;
@@ -2172,7 +2172,7 @@ static int skl_plane_check(struct intel_crtc_state
*crtc_state,
return ret;
/* use scaler when colorkey is not required */
- if (!plane_state->ckey.flags && intel_fb_scalable(fb)) {
+ if (!plane_state->ckey.flags && skl_fb_scalable(fb)) {
min_scale = 1;
max_scale = skl_plane_max_scale(dev_priv, fb);
}
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index cc3bec42d04c..4cb6339d12be 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -1282,19 +1282,18 @@ g4x_plane_get_hw_state(struct intel_plane *plane,
return ret;
}
-static bool intel_fb_scalable(const struct drm_framebuffer *fb)
+static bool g4x_fb_scalable(const struct drm_framebuffer *fb)
{
if (!fb)
return false;
switch (fb->format->format) {
case DRM_FORMAT_C8:
- return false;
case DRM_FORMAT_XRGB16161616F:
case DRM_FORMAT_ARGB16161616F:
case DRM_FORMAT_XBGR16161616F:
case DRM_FORMAT_ABGR16161616F:
- return INTEL_GEN(to_i915(fb->dev)) >= 11;
+ return false;
default:
return true;
}
@@ -1371,7 +1370,7 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
int max_scale = DRM_PLANE_HELPER_NO_SCALING;
int ret;
- if (intel_fb_scalable(plane_state->hw.fb)) {
+ if (g4x_fb_scalable(plane_state->hw.fb)) {
if (INTEL_GEN(dev_priv) < 7) {
min_scale = 1;
max_scale = 16 << 16;
--
2.27.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 05/11] drm/i915: refactor some crtc code out of intel display.
From: Dave Airlie
There may be more crtc code that can be pulled out, but this
is a good start.
RFC: maybe call the new file something different
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/display/intel_crtc.c| 953 +++
drivers/gpu/drm/i915/display/intel_crtc.h| 20 +
drivers/gpu/drm/i915/display/intel_display.c | 934 +-
4 files changed, 975 insertions(+), 933 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_crtc.c
create mode 100644 drivers/gpu/drm/i915/display/intel_crtc.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 98a35b939052..ffec257702af 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -196,6 +196,7 @@ i915-y += \
display/intel_color.o \
display/intel_combo_phy.o \
display/intel_connector.o \
+ display/intel_crtc.o \
display/intel_csr.o \
display/intel_cursor.o \
display/intel_display.o \
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
b/drivers/gpu/drm/i915/display/intel_crtc.c
new file mode 100644
index ..d26beb8ad9ed
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -0,0 +1,953 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+#include "intel_atomic.h"
+#include "intel_atomic_plane.h"
+#include "intel_color.h"
+#include "intel_crtc.h"
+#include "intel_cursor.h"
+#include "intel_display_debugfs.h"
+#include "intel_display_types.h"
+#include "intel_pipe_crc.h"
+#include "intel_sprite.h"
+
+/* Primary plane formats for gen <= 3 */
+static const u32 i8xx_primary_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_XRGB1555,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+};
+
+/* Primary plane formats for ivb (no fp16 due to hw issue) */
+static const u32 ivb_primary_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+};
+
+/* Primary plane formats for gen >= 4, except ivb */
+static const u32 i965_primary_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_XBGR16161616F,
+};
+
+/* Primary plane formats for vlv/chv */
+static const u32 vlv_primary_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_ARGB2101010,
+ DRM_FORMAT_ABGR2101010,
+ DRM_FORMAT_XBGR16161616F,
+};
+
+static const u64 i9xx_format_modifiers[] = {
+ I915_FORMAT_MOD_X_TILED,
+ DRM_FORMAT_MOD_LINEAR,
+ DRM_FORMAT_MOD_INVALID
+};
+
+static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
+ u32 format, u64 modifier)
+{
+ switch (modifier) {
+ case DRM_FORMAT_MOD_LINEAR:
+ case I915_FORMAT_MOD_X_TILED:
+ break;
+ default:
+ return false;
+ }
+
+ switch (format) {
+ case DRM_FORMAT_C8:
+ case DRM_FORMAT_RGB565:
+ case DRM_FORMAT_XRGB1555:
+ case DRM_FORMAT_XRGB:
+ return modifier == DRM_FORMAT_MOD_LINEAR ||
+ modifier == I915_FORMAT_MOD_X_TILED;
+ default:
+ return false;
+ }
+}
+
+static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
+ u32 format, u64 modifier)
+{
+ switch (modifier) {
+ case DRM_FORMAT_MOD_LINEAR:
+ case I915_FORMAT_MOD_X_TILED:
+ break;
+ default:
+ return false;
+ }
+
+ switch (format) {
+ case DRM_FORMAT_C8:
+ case DRM_FORMAT_RGB565:
+ case DRM_FORMAT_XRGB:
+ case DRM_FORMAT_XBGR:
+ case DRM_FORMAT_ARGB:
+ case DRM_FORMAT_ABGR:
+ case DRM_FORMAT_XRGB2101010:
+ case DRM_FORMAT_XBGR2101010:
+ case DRM_FORMAT_ARGB2101010:
+ case DRM_FORMAT_ABGR2101010:
+ case DRM_FORMAT_XBGR16161616F:
+ return modifier == DRM_FORMAT_MOD_LINEAR ||
+ modifier == I915_FORMAT_MOD_X_TILED;
+ default:
+ return false;
+ }
+}
+
+static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
+ enum i9xx_plane_id i9xx_plane)
+{
+ if (!HAS_FBC(dev_priv))
+ return false;
+
+ if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
+ return i9xx_plane == PLANE_A; /* tied to pipe A */
+ else
[Intel-gfx] [PATCH 08/11] drm/i915: migrate hsw fdi code to new file.
From: Dave Airlie
Daniel asked for this, but it's a bit messy and I'm not sure
how best to clean it up yet.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_crt.c | 1 +
drivers/gpu/drm/i915/display/intel_ddi.c | 151 +--
drivers/gpu/drm/i915/display/intel_ddi.h | 14 ++-
drivers/gpu/drm/i915/display/intel_fdi.c | 147 ++
drivers/gpu/drm/i915/display/intel_fdi.h | 3 +
5 files changed, 168 insertions(+), 148 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c
b/drivers/gpu/drm/i915/display/intel_crt.c
index 4934edd51cb0..077ebc7e6396 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -38,6 +38,7 @@
#include "intel_crt.h"
#include "intel_ddi.h"
#include "intel_display_types.h"
+#include "intel_fdi.h"
#include "intel_fifo_underrun.h"
#include "intel_gmbus.h"
#include "intel_hotplug.h"
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 6863236df1d0..2d903962f9dd 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -51,12 +51,6 @@
#include "intel_tc.h"
#include "intel_vdsc.h"
-struct ddi_buf_trans {
- u32 trans1; /* balance leg enable, de-emph level */
- u32 trans2; /* vref sel, vswing */
- u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
-};
-
static const u8 index_to_dp_signal_levels[] = {
[0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
[1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
@@ -1398,8 +1392,8 @@ static int intel_ddi_hdmi_level(struct intel_encoder
*encoder,
* values in advance. This function programs the correct values for
* DP/eDP/FDI use cases.
*/
-static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
-const struct intel_crtc_state
*crtc_state)
+void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
u32 iboost_bit = 0;
@@ -1461,8 +1455,8 @@ static void intel_prepare_hdmi_ddi_buffers(struct
intel_encoder *encoder,
ddi_translations[level].trans2);
}
-static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
- enum port port)
+void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
+enum port port)
{
if (IS_BROXTON(dev_priv)) {
udelay(16);
@@ -1490,7 +1484,7 @@ static void intel_wait_ddi_buf_active(struct
drm_i915_private *dev_priv,
port_name(port));
}
-static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
+u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
{
switch (pll->info->id) {
case DPLL_ID_WRPLL1:
@@ -1550,141 +1544,6 @@ static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder
*encoder,
}
}
-/* Starting with Haswell, different DDI ports can work in FDI mode for
- * connection to the PCH-located connectors. For this, it is necessary to train
- * both the DDI port and PCH receiver for the desired DDI buffer settings.
- *
- * The recommended port to work in FDI mode is DDI E, which we use here. Also,
- * please note that when FDI mode is active on DDI E, it shares 2 lines with
- * DDI A (which is used for eDP)
- */
-
-void hsw_fdi_link_train(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state)
-{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- u32 temp, i, rx_ctl_val, ddi_pll_sel;
-
- intel_prepare_dp_ddi_buffers(encoder, crtc_state);
-
- /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
-* mode set "sequence for CRT port" document:
-* - TP1 to TP2 time with the default value
-* - FDI delay to 90h
-*
-* WaFDIAutoLinkSetTimingOverrride:hsw
-*/
- intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A),
- FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2) |
FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
-
- /* Enable the PCH Receiver FDI PLL */
- rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
-FDI_RX_PLL_ENABLE |
-FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
- intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
- intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
- udelay(220);
-
- /* Switch from Rawclk to PCDclk */
- rx_ctl_val |= FDI_PCDCLK;
- intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
-
- /* Configure Port Clock Select */
-
[Intel-gfx] [PATCH 06/11] drm/i915: refactor pll code out into intel_dpll.c
From: Dave Airlie
This pulls a large chunk of the pll calculation code out of
intel_display.c to a new file.
One function makse sense to be an inline, otherwise this
is pretty much a straight copy cover. also all the
remaining hooks for g45 and older end up the same now.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/Makefile |1 +
drivers/gpu/drm/i915/display/intel_display.c | 1394 +
drivers/gpu/drm/i915/display/intel_display.h |3 +
.../drm/i915/display/intel_display_types.h|5 +
drivers/gpu/drm/i915/display/intel_dpll.c | 1371
drivers/gpu/drm/i915/display/intel_dpll.h | 22 +
6 files changed, 1413 insertions(+), 1383 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_dpll.c
create mode 100644 drivers/gpu/drm/i915/display/intel_dpll.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index ffec257702af..5d533de16335 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -202,6 +202,7 @@ i915-y += \
display/intel_display.o \
display/intel_display_power.o \
display/intel_dpio_phy.o \
+ display/intel_dpll.o \
display/intel_dpll_mgr.o \
display/intel_dsb.o \
display/intel_fbc.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 5dfec950c144..a0d9cd7b4e34 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -48,6 +48,7 @@
#include "display/intel_display_debugfs.h"
#include "display/intel_dp.h"
#include "display/intel_dp_mst.h"
+#include "display/intel_dpll.h"
#include "display/intel_dpll_mgr.h"
#include "display/intel_dsi.h"
#include "display/intel_dvo.h"
@@ -114,17 +115,6 @@ static void ilk_pfit_enable(const struct intel_crtc_state
*crtc_state);
static void intel_modeset_setup_hw_state(struct drm_device *dev,
struct drm_modeset_acquire_ctx *ctx);
-struct intel_limit {
- struct {
- int min, max;
- } dot, vco, n, m, m1, m2, p, p1;
-
- struct {
- int dot_limit;
- int p2_slow, p2_fast;
- } p2;
-};
-
/* returns HPLL frequency in kHz */
int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
{
@@ -192,271 +182,6 @@ static u32 intel_fdi_link_freq(struct drm_i915_private
*dev_priv,
return dev_priv->fdi_pll_freq;
}
-static const struct intel_limit intel_limits_i8xx_dac = {
- .dot = { .min = 25000, .max = 35 },
- .vco = { .min = 908000, .max = 1512000 },
- .n = { .min = 2, .max = 16 },
- .m = { .min = 96, .max = 140 },
- .m1 = { .min = 18, .max = 26 },
- .m2 = { .min = 6, .max = 16 },
- .p = { .min = 4, .max = 128 },
- .p1 = { .min = 2, .max = 33 },
- .p2 = { .dot_limit = 165000,
- .p2_slow = 4, .p2_fast = 2 },
-};
-
-static const struct intel_limit intel_limits_i8xx_dvo = {
- .dot = { .min = 25000, .max = 35 },
- .vco = { .min = 908000, .max = 1512000 },
- .n = { .min = 2, .max = 16 },
- .m = { .min = 96, .max = 140 },
- .m1 = { .min = 18, .max = 26 },
- .m2 = { .min = 6, .max = 16 },
- .p = { .min = 4, .max = 128 },
- .p1 = { .min = 2, .max = 33 },
- .p2 = { .dot_limit = 165000,
- .p2_slow = 4, .p2_fast = 4 },
-};
-
-static const struct intel_limit intel_limits_i8xx_lvds = {
- .dot = { .min = 25000, .max = 35 },
- .vco = { .min = 908000, .max = 1512000 },
- .n = { .min = 2, .max = 16 },
- .m = { .min = 96, .max = 140 },
- .m1 = { .min = 18, .max = 26 },
- .m2 = { .min = 6, .max = 16 },
- .p = { .min = 4, .max = 128 },
- .p1 = { .min = 1, .max = 6 },
- .p2 = { .dot_limit = 165000,
- .p2_slow = 14, .p2_fast = 7 },
-};
-
-static const struct intel_limit intel_limits_i9xx_sdvo = {
- .dot = { .min = 2, .max = 40 },
- .vco = { .min = 140, .max = 280 },
- .n = { .min = 1, .max = 6 },
- .m = { .min = 70, .max = 120 },
- .m1 = { .min = 8, .max = 18 },
- .m2 = { .min = 3, .max = 7 },
- .p = { .min = 5, .max = 80 },
- .p1 = { .min = 1, .max = 8 },
- .p2 = { .dot_limit = 20,
- .p2_slow = 10, .p2_fast = 5 },
-};
-
-static const struct intel_limit intel_limits_i9xx_lvds = {
- .dot = { .min = 2, .max = 40 },
- .vco = { .min = 140, .max = 280 },
- .n = { .min = 1, .max = 6 },
- .m = { .min = 70, .max = 120 },
- .m1 = { .min = 8, .max = 18 },
- .m2 = { .min = 3, .max = 7 },
- .p = { .min = 7, .max = 98 },
- .p1 = { .min = 1, .max = 8 },
- .p2 = { .dot_limit = 112000,
- .p2_slow = 14, .p2_fast = 7 },
-};
-
-
-static const struct intel_limit intel_limits_g4x_sdvo = {
- .dot = {
[Intel-gfx] [PATCH 04/11] drm/i915: refactor cursor code out of i915_display.c
From: Dave Airlie
This file is a monster, let's start simple, the cursor plane code
seems pretty standalone, and splits out easily enough.
Reviewed-by: Ville Syrjälä
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/display/intel_cursor.c | 806 +++
drivers/gpu/drm/i915/display/intel_cursor.h | 18 +
drivers/gpu/drm/i915/display/intel_display.c | 797 +-
drivers/gpu/drm/i915/display/intel_display.h | 7 +
5 files changed, 839 insertions(+), 790 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_cursor.c
create mode 100644 drivers/gpu/drm/i915/display/intel_cursor.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index e5574e506a5c..98a35b939052 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -197,6 +197,7 @@ i915-y += \
display/intel_combo_phy.o \
display/intel_connector.o \
display/intel_csr.o \
+ display/intel_cursor.o \
display/intel_display.o \
display/intel_display_power.o \
display/intel_dpio_phy.o \
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c
b/drivers/gpu/drm/i915/display/intel_cursor.c
new file mode 100644
index ..276d2bb0e2cf
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -0,0 +1,806 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#include "intel_atomic.h"
+#include "intel_atomic_plane.h"
+#include "intel_cursor.h"
+#include "intel_display_types.h"
+#include "intel_display.h"
+
+#include "intel_frontbuffer.h"
+#include "intel_pm.h"
+#include "intel_psr.h"
+#include "intel_sprite.h"
+
+/* Cursor formats */
+static const u32 intel_cursor_formats[] = {
+ DRM_FORMAT_ARGB,
+};
+
+static const u64 cursor_format_modifiers[] = {
+ DRM_FORMAT_MOD_LINEAR,
+ DRM_FORMAT_MOD_INVALID
+};
+
+static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
+{
+ struct drm_i915_private *dev_priv =
+ to_i915(plane_state->uapi.plane->dev);
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+ const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
+ u32 base;
+
+ if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)
+ base = sg_dma_address(obj->mm.pages->sgl);
+ else
+ base = intel_plane_ggtt_offset(plane_state);
+
+ return base + plane_state->color_plane[0].offset;
+}
+
+static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
+{
+ int x = plane_state->uapi.dst.x1;
+ int y = plane_state->uapi.dst.y1;
+ u32 pos = 0;
+
+ if (x < 0) {
+ pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
+ x = -x;
+ }
+ pos |= x << CURSOR_X_SHIFT;
+
+ if (y < 0) {
+ pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
+ y = -y;
+ }
+ pos |= y << CURSOR_Y_SHIFT;
+
+ return pos;
+}
+
+static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
+{
+ const struct drm_mode_config *config =
+ _state->uapi.plane->dev->mode_config;
+ int width = drm_rect_width(_state->uapi.dst);
+ int height = drm_rect_height(_state->uapi.dst);
+
+ return width > 0 && width <= config->cursor_width &&
+ height > 0 && height <= config->cursor_height;
+}
+
+static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
+{
+ struct drm_i915_private *dev_priv =
+ to_i915(plane_state->uapi.plane->dev);
+ unsigned int rotation = plane_state->hw.rotation;
+ int src_x, src_y;
+ u32 offset;
+ int ret;
+
+ ret = intel_plane_compute_gtt(plane_state);
+ if (ret)
+ return ret;
+
+ if (!plane_state->uapi.visible)
+ return 0;
+
+ src_x = plane_state->uapi.src.x1 >> 16;
+ src_y = plane_state->uapi.src.y1 >> 16;
+
+ intel_add_fb_offsets(_x, _y, plane_state, 0);
+ offset = intel_plane_compute_aligned_offset(_x, _y,
+ plane_state, 0);
+
+ if (src_x != 0 || src_y != 0) {
+ drm_dbg_kms(_priv->drm,
+ "Arbitrary cursor panning not supported\n");
+ return -EINVAL;
+ }
+
+ /*
+* Put the final coordinates back so that the src
+* coordinate checks will see the right values.
+*/
+ drm_rect_translate_to(_state->uapi.src,
+ src_x << 16, src_y << 16);
+
+ /* ILK+ do this automagically in hardware */
+ if (HAS_GMCH(dev_priv) && rotation & DRM_MODE_ROTATE_180) {
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+ int src_w = drm_rect_width(_state->uapi.src)
[Intel-gfx] [RFC v3] refactor intel display a bit more
The first 4 patches are fixed up and reviewed, so it would be good if we could land those at least. I haven't had much time to rework the others, I've removed the legacy, and added header files and renamed some functions where it wasn't too intrusive. I think the file names probably do need revisiting, for the later patches and the hsw fdi patch is still a bit rough IMO. I'm away for a week now, so I'll see what I can revisit when I return or feel free to munge these in the meantime into whatever works. Dave. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 03/11] drm/i915/display: fix misused comma
From: Dave Airlie
There is no need for a comma use here.
Reviewed-by: Ville Syrjälä
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 62e22d832cab..79d7479beed2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -989,7 +989,8 @@ chv_find_best_dpll(const struct intel_limit *limit,
* set to 2. If requires to support 200Mhz refclk, we need to
* revisit this because n may not 1 anymore.
*/
- clock.n = 1, clock.m1 = 2;
+ clock.n = 1;
+ clock.m1 = 2;
target *= 5;/* fast clock */
for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
--
2.27.0
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[Intel-gfx] [PATCH 02/11] drm/i915/display: move to_intel_frontbuffer to header
From: Dave Airlie
This will be used for some refactoring in other files, so move it
first.
Signed-off-by: Dave Airlie
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 6 --
drivers/gpu/drm/i915/display/intel_display_types.h | 6 ++
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 80103211f407..62e22d832cab 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3611,12 +3611,6 @@ static void intel_plane_disable_noatomic(struct
intel_crtc *crtc,
intel_disable_plane(plane, crtc_state);
}
-static struct intel_frontbuffer *
-to_intel_frontbuffer(struct drm_framebuffer *fb)
-{
- return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
-}
-
static void
intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
struct intel_initial_plane_config *plane_config)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index a2f6b7c161a4..dfa3966e5fa1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1805,4 +1805,10 @@ static inline u32 intel_plane_ggtt_offset(const struct
intel_plane_state *state)
return i915_ggtt_offset(state->vma);
}
+static inline struct intel_frontbuffer *
+to_intel_frontbuffer(struct drm_framebuffer *fb)
+{
+ return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
+}
+
#endif /* __INTEL_DISPLAY_TYPES_H__ */
--
2.27.0
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[Intel-gfx] [PATCH 01/11] drm/i915/display: move needs_modeset to an inline in header
From: Dave Airlie
This function is going to be used in a later change, so clean it
up first before moving it.
Reviewed-by: Ville Syrjälä
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_display.c | 78 +--
.../drm/i915/display/intel_display_types.h| 6 ++
2 files changed, 42 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index c567c0cada7e..80103211f407 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -542,12 +542,6 @@ icl_wa_scalerclkgating(struct drm_i915_private *dev_priv,
enum pipe pipe,
intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) &
~DPFR_GATING_DIS);
}
-static bool
-needs_modeset(const struct intel_crtc_state *state)
-{
- return drm_atomic_crtc_needs_modeset(>uapi);
-}
-
static bool
is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
{
@@ -6474,7 +6468,7 @@ static bool hsw_pre_update_disable_ips(const struct
intel_crtc_state *old_crtc_s
if (!old_crtc_state->ips_enabled)
return false;
- if (needs_modeset(new_crtc_state))
+ if (intel_crtc_needs_modeset(new_crtc_state))
return true;
/*
@@ -6501,7 +6495,7 @@ static bool hsw_post_update_enable_ips(const struct
intel_crtc_state *old_crtc_s
if (!new_crtc_state->ips_enabled)
return false;
- if (needs_modeset(new_crtc_state))
+ if (intel_crtc_needs_modeset(new_crtc_state))
return true;
/*
@@ -6554,7 +6548,7 @@ static bool needs_scalerclk_wa(const struct
intel_crtc_state *crtc_state)
static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
const struct intel_crtc_state *new_crtc_state)
{
- return (!old_crtc_state->active_planes ||
needs_modeset(new_crtc_state)) &&
+ return (!old_crtc_state->active_planes ||
intel_crtc_needs_modeset(new_crtc_state)) &&
new_crtc_state->active_planes;
}
@@ -6562,7 +6556,7 @@ static bool planes_disabling(const struct
intel_crtc_state *old_crtc_state,
const struct intel_crtc_state *new_crtc_state)
{
return old_crtc_state->active_planes &&
- (!new_crtc_state->active_planes ||
needs_modeset(new_crtc_state));
+ (!new_crtc_state->active_planes ||
intel_crtc_needs_modeset(new_crtc_state));
}
static void intel_post_plane_update(struct intel_atomic_state *state,
@@ -6685,7 +6679,7 @@ static void intel_pre_plane_update(struct
intel_atomic_state *state,
* If we're doing a modeset we don't need to do any
* pre-vblank watermark programming here.
*/
- if (!needs_modeset(new_crtc_state)) {
+ if (!intel_crtc_needs_modeset(new_crtc_state)) {
/*
* For platforms that support atomic watermarks, program the
* 'intermediate' watermarks immediately. On pre-gen9
platforms, these
@@ -12046,7 +12040,7 @@ static void i9xx_update_cursor(struct intel_plane
*plane,
if (INTEL_GEN(dev_priv) >= 9)
skl_write_cursor_wm(plane, crtc_state);
- if (!needs_modeset(crtc_state))
+ if (!intel_crtc_needs_modeset(crtc_state))
intel_psr2_program_plane_sel_fetch(plane, crtc_state,
plane_state, 0);
if (plane->cursor.base != base ||
@@ -12616,7 +12610,7 @@ int intel_plane_atomic_calc_changes(const struct
intel_crtc_state *old_crtc_stat
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- bool mode_changed = needs_modeset(crtc_state);
+ bool mode_changed = intel_crtc_needs_modeset(crtc_state);
bool was_crtc_enabled = old_crtc_state->hw.active;
bool is_crtc_enabled = crtc_state->hw.active;
bool turn_off, turn_on, visible, was_visible;
@@ -12980,7 +12974,7 @@ static int intel_crtc_atomic_check(struct
intel_atomic_state *state,
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- bool mode_changed = needs_modeset(crtc_state);
+ bool mode_changed = intel_crtc_needs_modeset(crtc_state);
int ret;
if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
@@ -14812,7 +14806,7 @@ intel_modeset_verify_crtc(struct intel_crtc *crtc,
struct intel_crtc_state *old_crtc_state,
struct intel_crtc_state *new_crtc_state)
{
- if (!needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)
+ if (!intel_crtc_needs_modeset(new_crtc_state) &&
!new_crtc_state->update_pipe)
Re: [Intel-gfx] [PATCH v7 18/18] drm/i915/hdcp: Enable HDCP 2.2 MST support
On 2020-12-10 at 11:56:40 +0530, Anshuman Gupta wrote:
> Enable HDCP 2.2 over DP MST.
> Authenticate and enable port encryption only once for
> an active HDCP 2.2 session, once port is authenticated
> and encrypted enable encryption for each stream that
> requires encryption on this port.
>
> Similarly disable the stream encryption for each encrypted
> stream, once all encrypted stream encryption is disabled,
> disable the port HDCP encryption and deauthenticate the port.
>
Like in the previous patch (for 1.4 MST?) split this patch into 2. one
for configuring the stream encryptions status for 2.2 another one for
enabling the HDCP2.2 MST support.
Ram
> v2:
> - Add connector details in drm_err. [Ram]
> - 's/port_auth/hdcp_auth_status'. [Ram]
> - Added a debug print for stream enc.
> v3:
> - uniformity for connector detail in DMESG. [Ram]
>
> Cc: Ramalingam C
> Reviewed-by: Uma Shankar
> Tested-by: Karthik B S
> Signed-off-by: Anshuman Gupta
> ---
> drivers/gpu/drm/i915/display/intel_hdcp.c | 53 ++-
> 1 file changed, 51 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index 65dd39b44688..4b221c298835 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -1700,6 +1700,36 @@ static int hdcp2_authenticate_sink(struct
> intel_connector *connector)
> return ret;
> }
>
> +static int hdcp2_enable_stream_encryption(struct intel_connector *connector)
> +{
> + struct intel_digital_port *dig_port =
> intel_attached_dig_port(connector);
> + struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> + struct intel_hdcp *hdcp = >hdcp;
> + enum transcoder cpu_transcoder = hdcp->cpu_transcoder;
> + enum port port = dig_port->base.port;
> + int ret = 0;
> +
> + if (!(intel_de_read(dev_priv, HDCP2_STATUS(dev_priv, cpu_transcoder,
> port)) &
> + LINK_ENCRYPTION_STATUS)) {
> + drm_err(_priv->drm, "[%s:%d] HDCP 2.2 Link is not
> encrypted\n",
> + connector->base.name, connector->base.base.id);
> + return -EPERM;
> + }
> +
> + if (hdcp->shim->stream_2_2_encryption) {
> + ret = hdcp->shim->stream_2_2_encryption(connector, true);
> + if (ret) {
> + drm_err(_priv->drm, "[%s:%d] Failed to enable HDCP
> 2.2 stream enc\n",
> + connector->base.name, connector->base.base.id);
> + return ret;
> + }
> + drm_dbg_kms(_priv->drm, "HDCP 2.2 transcoder: %s stream
> encrypted\n",
> + transcoder_name(hdcp->stream_transcoder));
> + }
> +
> + return ret;
> +}
> +
> static int hdcp2_enable_encryption(struct intel_connector *connector)
> {
> struct intel_digital_port *dig_port =
> intel_attached_dig_port(connector);
> @@ -1838,7 +1868,7 @@ static int hdcp2_authenticate_and_encrypt(struct
> intel_connector *connector)
> drm_dbg_kms(>drm, "Port deauth failed.\n");
> }
>
> - if (!ret) {
> + if (!ret && !dig_port->hdcp_auth_status) {
> /*
>* Ensuring the required 200mSec min time interval between
>* Session Key Exchange and encryption.
> @@ -1853,6 +1883,8 @@ static int hdcp2_authenticate_and_encrypt(struct
> intel_connector *connector)
> }
> }
>
> + ret = hdcp2_enable_stream_encryption(connector);
> +
> return ret;
> }
>
> @@ -1898,11 +1930,26 @@ static int _intel_hdcp2_disable(struct
> intel_connector *connector)
> struct intel_digital_port *dig_port =
> intel_attached_dig_port(connector);
> struct drm_i915_private *i915 = to_i915(connector->base.dev);
> struct hdcp_port_data *data = _port->hdcp_port_data;
> + struct intel_hdcp *hdcp = >hdcp;
> int ret;
>
> drm_dbg_kms(>drm, "[%s:%d] HDCP2.2 is being Disabled\n",
> connector->base.name, connector->base.base.id);
>
> + if (hdcp->shim->stream_2_2_encryption) {
> + ret = hdcp->shim->stream_2_2_encryption(connector, false);
> + if (ret) {
> + drm_err(>drm, "[%s:%d] Failed to disable HDCP 2.2
> stream enc\n",
> + connector->base.name, connector->base.base.id);
> + return ret;
> + }
> + drm_dbg_kms(>drm, "HDCP 2.2 transcoder: %s stream
> encryption disabled\n",
> + transcoder_name(hdcp->stream_transcoder));
> + }
> +
> + if (dig_port->num_hdcp_streams > 0)
> + return ret;
> +
> ret = hdcp2_disable_encryption(connector);
>
> if (hdcp2_deauthenticate_port(connector) < 0)
> @@ -1926,6 +1973,7 @@ static int intel_hdcp2_check_link(struct
> intel_connector *connector)
> int ret = 0;
>
>
Re: [Intel-gfx] [PATCH v7 17/18] drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks
On 2020-12-10 at 11:56:39 +0530, Anshuman Gupta wrote:
> Add support for HDCP 2.2 DP MST shim callback.
> This adds existing DP HDCP shim callback for Link Authentication
> and Encryption and HDCP 2.2 stream encryption
> callback.
>
> v2:
> - Added a WARN_ON() instead of drm_err. [Uma]
> - Cosmetic changes. [Uma]
> v3:
> - 's/port_data/hdcp_port_data' [Ram]
> - skip redundant link check. [Ram]
> v4:
> - use pipe instead of port to access HDCP2_STREAM_STATUS
How this missed the functional test till now?
Always true because port's stream status was referred?
>
> Cc: Ramalingam C
> Reviewed-by: Uma Shankar
> Tested-by: Karthik B S
> Signed-off-by: Anshuman Gupta
> ---
> .../drm/i915/display/intel_display_types.h| 4 +
> drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 89 +--
> 2 files changed, 85 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 63de25b40eff..da91e3f4ff27 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -378,6 +378,10 @@ struct intel_hdcp_shim {
> int (*config_stream_type)(struct intel_digital_port *dig_port,
> bool is_repeater, u8 type);
>
> + /* Enable/Disable HDCP 2.2 stream encryption on DP MST Transport Link */
> + int (*stream_2_2_encryption)(struct intel_connector *connector,
> + bool enable);
> +
> /* HDCP2.2 Link Integrity Check */
> int (*check_2_2_link)(struct intel_digital_port *dig_port,
> struct intel_connector *connector);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> index 9ade1ad3a80c..f372e25edab4 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> @@ -698,18 +698,14 @@ intel_dp_mst_hdcp_stream_encryption(struct
> intel_connector *connector,
> return 0;
> }
>
> -static
> -bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
> - struct intel_connector *connector)
> +static bool intel_dp_mst_get_qses_status(struct intel_digital_port *dig_port,
> + struct intel_connector *connector)
> {
> struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> - struct intel_dp *intel_dp = _port->dp;
> struct drm_dp_query_stream_enc_status_ack_reply reply;
> + struct intel_dp *intel_dp = _port->dp;
> int ret;
>
> - if (!intel_dp_hdcp_check_link(dig_port, connector))
> - return false;
> -
> ret = drm_dp_send_query_stream_enc_status(_dp->mst_mgr,
> connector->port, );
> if (ret) {
> @@ -726,6 +722,78 @@ bool intel_dp_mst_hdcp_check_link(struct
> intel_digital_port *dig_port,
> return reply.auth_completed && reply.encryption_enabled;
> }
>
> +static
> +bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
> + struct intel_connector *connector)
> +{
> + if (!intel_dp_hdcp_check_link(dig_port, connector))
> + return false;
this also could be optimised for the connector with port authentication
only?
> +
> + return intel_dp_mst_get_qses_status(dig_port, connector);
> +}
> +
> +static int
> +intel_dp_mst_hdcp2_stream_encryption(struct intel_connector *connector,
> + bool enable)
> +{
> + struct intel_digital_port *dig_port =
> intel_attached_dig_port(connector);
> + struct drm_i915_private *i915 = to_i915(connector->base.dev);
> + struct hdcp_port_data *data = _port->hdcp_port_data;
> + struct intel_hdcp *hdcp = >hdcp;
> + enum transcoder cpu_transcoder = hdcp->stream_transcoder;
> + enum pipe pipe = (enum pipe)cpu_transcoder;
> + enum port port = dig_port->base.port;
> + int ret;
> +
> + drm_WARN_ON(>drm, enable &&
> + !!(intel_de_read(i915, HDCP2_AUTH_STREAM(i915,
> cpu_transcoder, port))
> + & AUTH_STREAM_TYPE) != data->streams[0].stream_type);
> +
> + ret = intel_dp_mst_toggle_hdcp_stream_select(connector, enable);
> + if (ret)
> + return ret;
> +
> + /* Wait for encryption confirmation */
> + if (intel_de_wait_for_register(i915,
> +HDCP2_STREAM_STATUS(i915,
> cpu_transcoder, pipe),
> +STREAM_ENCRYPTION_STATUS,
> +enable ? STREAM_ENCRYPTION_STATUS : 0,
> +HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
> + drm_err(>drm, "Timed out waiting for transcoder: %s
> stream encryption %s\n",
> + transcoder_name(cpu_transcoder), enable ? "enabled" :
>
Re: [Intel-gfx] [PATCH 1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
> -Original Message- > From: Imre Deak > Sent: Tuesday, December 1, 2020 4:05 AM > To: Chery, Nanley G ; Chris Wilson wilson.co.uk>; Ville Syrjälä > Cc: Daniel Vetter ; intel-gfx@lists.freedesktop.org; Nikula, > Jani ; Daniel Vetter ; > Kondapally, Kalyan ; Pandiyan, Dhinakaran > ; dri-de...@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH 1/2] drm/framebuffer: Format modifier for > Intel Gen 12 render compression with Clear Color > > Hi Nanley, > > thanks for the review. > > +Ville, Chris. > > On Tue, Dec 01, 2020 at 02:18:26AM +0200, Chery, Nanley G wrote: > > Hi Imre, > > > > I have a question and a couple comments: > > > > Is the map of the clear color address creating a new synchronization > > point between the GPU and CPU? If so, I wonder how this will impact > > performance. > > The kmap to read the clear value is not adding any sync overhead if > that's what you mean. But the clear value must be in place before we > read it out and that should be guaranteed by the flush we do anyway to wait > for the render result (even considering the explicit L3/RT flush, depth > stall the spec requires for fast clears). > > However now that you mention: atm the kmap/readout happens after the > explicit but before the implicit fence-wait. I think it should happen > after the implicit fence-wait. > > Ville, Chris, could you confirm the above and also that the above flush > is enough to ensure the CPU read is coherent? > > > There was some talk of asynchronously updating the clear color > > register a while back. > > Couldn't find anything with a quick search, do you have a pointer? Just > before the flip we must wait for the render results anyway, as we do > now, so not sure how it could be optimized. > There were some offline discussions, so I don't have a reference unfortunately. Though, given what you shared above it seems like it's actually not an issue. > > We probably don't have to update the header, but we noticed in our > > testing that the clear color prefers an alignment greater than 64B. > > Unfortunately, I can't find any bspec note about this. As long as the > > buffer creators are aware though, I think we should be fine. I don't > > know if this is the best forum to bring it up, but I thought I'd > > share. > > Yes, would be good to clarify this and get it also to the spec. Then the > driver should also check the alignment of the 3rd FB plane. > I plan to run some more tests and file a bug in the spec. I see that the IGT test only clears the fb once. Just to confirm, is the clear color offset read from on every frame? Userspace would like to be able to pass different clear colors for an fb. -Nanley > > Seems like the upper converted clear color is untested due to the lack > > of RGBX16 support. I suppose that if there are any issues there, they > > can be fixed later... > > Yes, a 64bpp RC-CC subtest in IGT is missing, should be easy to add > that. > > --Imre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v7 14/18] drm/i915/hdcp: MST streams support in hdcp port_data
On 2020-12-10 at 11:56:36 +0530, Anshuman Gupta wrote:
> Add support for multiple mst stream in hdcp port data
> which will be used by RepeaterAuthStreamManage msg and
> HDCP 2.2 security f/w for m' validation.
>
> Security f/w doesn't have any provision to mark the
> stream_type for each stream separately, it just take
> single input of stream_type while authenticating the
> port.
".. authenticating the port and applies the same stream type to all ports"
> So driver mark each stream_type with common
> highest supported content type for all streams in
> DP MST Topology.
>
> Security f/w supports RepeaterAuthStreamManage msg and m'
You could add "though it is not mandatory"
> validation only once during port authentication and encryption.
> Ideally it should support dynamic update of content_type
> and should support RepeaterAuthStreamManage msg and m' validation
> whenever required.
>
> v2:
> - Init the hdcp port data k for HDMI/DP SST stream.
> v3:
> - Cosmetic changes. [Uma]
> v4:
> - 's/port_auth/hdcp_port_auth'. [Ram]
> - Commit log improvement.
> v5:
> - Comment and commit log improvement. [Ram]
>
> Cc: Ramalingam C
> Reviewed-by: Uma Shankar
> Tested-by: Karthik B S
> Signed-off-by: Anshuman Gupta
> ---
> .../drm/i915/display/intel_display_types.h| 4 +-
> drivers/gpu/drm/i915/display/intel_hdcp.c | 113 +++---
> 2 files changed, 102 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index b74c10c8b01c..b37a02a73de6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1502,10 +1502,12 @@ struct intel_digital_port {
> enum phy_fia tc_phy_fia;
> u8 tc_phy_fia_idx;
>
> - /* protects num_hdcp_streams reference count, hdcp_port_data */
> + /* protects num_hdcp_streams reference count, hdcp_port_data and
> hdcp_auth_status */
> struct mutex hdcp_mutex;
> /* the number of pipes using HDCP signalling out of this port */
> unsigned int num_hdcp_streams;
> + /* port HDCP auth status */
> + bool hdcp_auth_status;
> /* HDCP port data need to pass to security f/w */
> struct hdcp_port_data hdcp_port_data;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index 2bec26123a05..c21a6a6c545c 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -26,6 +26,74 @@
> #define KEY_LOAD_TRIES 5
> #define HDCP2_LC_RETRY_CNT 3
>
> +static int intel_conn_to_vcpi(struct intel_connector *connector)
> +{
> + /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */
> + return connector->port ? connector->port->vcpi.vcpi : 0;
> +}
> +
> +/*
> + * intel_hdcp_required_content_stream select most highest common possible
> HDCP
selects the most
> + * content_type for all streams in DP MST topology because security f/w
> doesn't
> + * have any provision to mark content_type for each stream separately, it
> marks
> + * all available streams with the content_type proivided at the time of port
> + * authentication. This may prohibit the userspace to use type1 content on
> + * HDCP 2.2 capable sink because of other sink are not capable of HDCP 2.2 in
> + * DP MST topology. Ideally security f/w should change its policy to mark
Though it is not compulsary, security fw should
> + * different content_type for different streams.
content types
with these addressed LGTM.
Reviewed-by: Ramalingam C
> + */
> +static int
> +intel_hdcp_required_content_stream(struct intel_digital_port *dig_port)
> +{
> + struct drm_connector_list_iter conn_iter;
> + struct intel_digital_port *conn_dig_port;
> + struct intel_connector *connector;
> + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> + struct hdcp_port_data *data = _port->hdcp_port_data;
> + bool enforce_type0 = false;
> + int k;
> +
> + if (dig_port->hdcp_auth_status)
> + return 0;
> +
> + drm_connector_list_iter_begin(>drm, _iter);
> + for_each_intel_connector_iter(connector, _iter) {
> + if (!intel_encoder_is_mst(intel_attached_encoder(connector)))
> + continue;
> +
> + conn_dig_port = intel_attached_dig_port(connector);
> + if (conn_dig_port != dig_port)
> + continue;
> +
> + if (connector->base.status == connector_status_disconnected)
> + continue;
> +
> + if (!enforce_type0 && !intel_hdcp2_capable(connector))
> + enforce_type0 = true;
> +
> + data->streams[data->k].stream_id =
> intel_conn_to_vcpi(connector);
> + data->k++;
> +
> + /* if there is only one active stream */
> + if
Re: [Intel-gfx] [PATCH v7 09/18] drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support
On 2020-12-10 at 11:56:31 +0530, Anshuman Gupta wrote:
> Enable HDCP 1.4 over DP MST for Gen12.
>
> v2:
> - Enable HDCP for <= Gen12 platforms. [Ram]
>
> Cc: Ramalingam C
> Tested-by: Karthik B S
> Signed-off-by: Anshuman Gupta
> ---
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 6 ++
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 47beb442094f..ae24e1af49be 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -829,12 +829,10 @@ static struct drm_connector
> *intel_dp_add_mst_connector(struct drm_dp_mst_topolo
> intel_attach_force_audio_property(connector);
> intel_attach_broadcast_rgb_property(connector);
>
> -
> - /* TODO: Figure out how to make HDCP work on GEN12+ */
> - if (INTEL_GEN(dev_priv) < 12) {
> + if (INTEL_GEN(dev_priv) <= 12) {
> ret = intel_dp_init_hdcp(dig_port, intel_connector);
> if (ret)
> - DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
> + drm_dbg_kms(_priv->drm, "HDCP init failed,
> skipping.\n");
"HDCP MST init failed" might be more meaningful with connector name and
ID.
With that addressed
Reviewed-by: Ramalingam C
> }
>
> /*
> --
> 2.26.2
>
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v7 08/18] drm/i915/hdcp: Enable HDCP 1.4 stream encryption
On 2020-12-10 at 11:56:30 +0530, Anshuman Gupta wrote:
> Enable HDCP 1.4 DP MST stream encryption.
IMHO tile of "Configure HDCP1.4 MST steram encryption status" would suit
more.
But i leave that to your call.
>
> Enable stream encryption once encryption is enabled on
> the DP transport driving the link for each stream which
> has requested encryption.
>
> Disable stream encryption for each stream that no longer
> requires encryption before disabling HDCP encryption on
> the link.
>
> v2:
> - Added debug print for stream encryption.
> - Disable the hdcp on port after disabling last stream
> encryption.
> v3:
> - Cosmetic change, removed the value less comment. [Uma]
> v4:
> - Split the Gen12 HDCP enablement patch. [Ram]
> - Add connector details in drm_err.
> v5:
> - uniformity for connector detail in DMESG. [Ram]
> - comments improvement. [Ram]
>
Patch LGTM.
Reviewed-by: Ramalingam C
> Cc: Ramalingam C
> Reviewed-by: Uma Shankar
> Tested-by: Karthik B S
> Signed-off-by: Anshuman Gupta
> ---
> drivers/gpu/drm/i915/display/intel_hdcp.c | 38 +++
> 1 file changed, 25 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index 6e6465b4ecfa..fce444d69521 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -766,10 +766,17 @@ static int intel_hdcp_auth(struct intel_connector
> *connector)
> return -ETIMEDOUT;
> }
>
> - /*
> - * XXX: If we have MST-connected devices, we need to enable encryption
> - * on those as well.
> - */
> + /* DP MST Auth Part 1 Step 2.a and Step 2.b */
> + if (shim->stream_encryption) {
> + ret = shim->stream_encryption(connector, true);
> + if (ret) {
> + drm_err(_priv->drm, "[%s:%d] Failed to enable HDCP
> 1.4 stream enc\n",
> + connector->base.name, connector->base.base.id);
> + return ret;
> + }
> + drm_dbg_kms(_priv->drm, "HDCP 1.4 transcoder: %s stream
> encrypted\n",
> + transcoder_name(hdcp->stream_transcoder));
> + }
>
> if (repeater_present)
> return intel_hdcp_auth_downstream(connector);
> @@ -791,18 +798,23 @@ static int _intel_hdcp_disable(struct intel_connector
> *connector)
> drm_dbg_kms(_priv->drm, "[%s:%d] HDCP is being disabled...\n",
> connector->base.name, connector->base.base.id);
>
> + if (hdcp->shim->stream_encryption) {
> + ret = hdcp->shim->stream_encryption(connector, false);
> + if (ret) {
> + drm_err(_priv->drm, "[%s:%d] Failed to disable HDCP
> 1.4 stream enc\n",
> + connector->base.name, connector->base.base.id);
> + return ret;
> + }
> + drm_dbg_kms(_priv->drm, "HDCP 1.4 transcoder: %s stream
> encryption disabled\n",
> + transcoder_name(hdcp->stream_transcoder));
> + }
> +
> /*
> - * If there are other connectors on this port using HDCP, don't disable
> - * it. Instead, toggle the HDCP signalling off on that particular
> - * connector/pipe and exit.
> + * If there are other connectors on this port using HDCP, don't disable
> it
> + * until it disabled HDCP encryption for all connectors in MST topology.
>*/
> - if (dig_port->num_hdcp_streams > 0) {
> - ret = hdcp->shim->toggle_signalling(dig_port,
> - cpu_transcoder, false);
> - if (ret)
> - DRM_ERROR("Failed to disable HDCP signalling\n");
> + if (dig_port->num_hdcp_streams > 0)
> return ret;
> - }
>
> hdcp->hdcp_encrypted = false;
> intel_de_write(dev_priv, HDCP_CONF(dev_priv, cpu_transcoder, port), 0);
> --
> 2.26.2
>
___
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Re: [Intel-gfx] [PATCH v7 04/18] drm/i915/hdcp: No HDCP when encoder is't initialized
On 2020-12-10 at 11:56:26 +0530, Anshuman Gupta wrote:
> There can be situation when DP MST connector is created without
> mst modeset being done, in those cases connector->encoder will be
> NULL. MST connector->encoder initializes after modeset.
> Don't enable HDCP in such cases to prevent any crash.
LGTM..
Reviewed-by: Ramalingam C
>
> Cc: Ramalingam C
> Cc: Juston Li
> Tested-by: Karthik B S
> Signed-off-by: Anshuman Gupta
> ---
> drivers/gpu/drm/i915/display/intel_hdcp.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index b9d8825e2bb1..7d63e9495956 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -2106,6 +2106,12 @@ int intel_hdcp_enable(struct intel_connector
> *connector,
> if (!hdcp->shim)
> return -ENOENT;
>
> + if (!connector->encoder) {
> + drm_err(_priv->drm, "[%s:%d] encoder is not initialized\n",
> + connector->base.name, connector->base.base.id);
> + return -ENODEV;
> + }
> +
> mutex_lock(>mutex);
> mutex_lock(_port->hdcp_mutex);
> drm_WARN_ON(_priv->drm,
> --
> 2.26.2
>
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[Intel-gfx] ✓ Fi.CI.IGT: success for Introduce Intel PXP component - Mesa single session (rev6)
== Series Details == Series: Introduce Intel PXP component - Mesa single session (rev6) URL : https://patchwork.freedesktop.org/series/84620/ State : success == Summary == CI Bug Log - changes from CI_DRM_9473_full -> Patchwork_19118_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_19118_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_balancer@full: - shard-hsw: NOTRUN -> [SKIP][1] ([fdo#109271]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19118/shard-hsw2/igt@gem_exec_balan...@full.html * igt@gem_exec_whisper@basic-contexts-priority: - shard-glk: [PASS][2] -> [DMESG-WARN][3] ([i915#118] / [i915#95]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9473/shard-glk5/igt@gem_exec_whis...@basic-contexts-priority.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19118/shard-glk3/igt@gem_exec_whis...@basic-contexts-priority.html * igt@gem_exec_whisper@basic-queues-forked: - shard-iclb: [PASS][4] -> [INCOMPLETE][5] ([i915#1895] / [i915#2405]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9473/shard-iclb3/igt@gem_exec_whis...@basic-queues-forked.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19118/shard-iclb2/igt@gem_exec_whis...@basic-queues-forked.html * igt@i915_pm_dc@dc6-psr: - shard-skl: NOTRUN -> [FAIL][6] ([i915#454]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19118/shard-skl8/igt@i915_pm...@dc6-psr.html * igt@kms_ccs@pipe-c-crc-sprite-planes-basic: - shard-skl: NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111304]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19118/shard-skl1/igt@kms_...@pipe-c-crc-sprite-planes-basic.html * igt@kms_color@pipe-d-ctm-max: - shard-skl: NOTRUN -> [SKIP][8] ([fdo#109271]) +37 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19118/shard-skl9/igt@kms_co...@pipe-d-ctm-max.html * igt@kms_color_chamelium@pipe-c-ctm-0-25: - shard-skl: NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +6 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19118/shard-skl1/igt@kms_color_chamel...@pipe-c-ctm-0-25.html * igt@kms_cursor_crc@pipe-c-cursor-64x21-random: - shard-skl: [PASS][10] -> [FAIL][11] ([i915#54]) +3 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9473/shard-skl7/igt@kms_cursor_...@pipe-c-cursor-64x21-random.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19118/shard-skl7/igt@kms_cursor_...@pipe-c-cursor-64x21-random.html * igt@kms_flip@flip-vs-expired-vblank@a-edp1: - shard-tglb: [PASS][12] -> [FAIL][13] ([i915#2598]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9473/shard-tglb6/igt@kms_flip@flip-vs-expired-vbl...@a-edp1.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19118/shard-tglb1/igt@kms_flip@flip-vs-expired-vbl...@a-edp1.html * igt@kms_hdr@bpc-switch: - shard-skl: [PASS][14] -> [FAIL][15] ([i915#1188]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9473/shard-skl5/igt@kms_...@bpc-switch.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19118/shard-skl9/igt@kms_...@bpc-switch.html * igt@kms_psr@psr2_sprite_blt: - shard-iclb: [PASS][16] -> [SKIP][17] ([fdo#109441]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9473/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19118/shard-iclb5/igt@kms_psr@psr2_sprite_blt.html Possible fixes * igt@gem_exec_reloc@basic-many-active@rcs0: - shard-apl: [FAIL][18] ([i915#2389]) -> [PASS][19] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9473/shard-apl7/igt@gem_exec_reloc@basic-many-act...@rcs0.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19118/shard-apl4/igt@gem_exec_reloc@basic-many-act...@rcs0.html * igt@gem_exec_whisper@basic-fds-forked: - shard-glk: [DMESG-WARN][20] ([i915#118] / [i915#95]) -> [PASS][21] [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9473/shard-glk3/igt@gem_exec_whis...@basic-fds-forked.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19118/shard-glk9/igt@gem_exec_whis...@basic-fds-forked.html * igt@kms_color@pipe-b-ctm-0-25: - shard-skl: [DMESG-WARN][22] ([i915#1982]) -> [PASS][23] [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9473/shard-skl8/igt@kms_co...@pipe-b-ctm-0-25.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19118/shard-skl8/igt@kms_co...@pipe-b-ctm-0-25.html * igt@kms_cursor_crc@pipe-a-cursor-64x21-sliding: - shard-skl: [FAIL][24] ([i915#54]) -> [PASS][25] +2
[Intel-gfx] ✓ Fi.CI.IGT: success for drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev3)
== Series Details == Series: drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev3) URL : https://patchwork.freedesktop.org/series/84754/ State : success == Summary == CI Bug Log - changes from CI_DRM_9473_full -> Patchwork_19117_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_19117_full that come from known issues: ### IGT changes ### Issues hit * igt@kms_ccs@pipe-c-crc-sprite-planes-basic: - shard-skl: NOTRUN -> [SKIP][1] ([fdo#109271] / [fdo#111304]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19117/shard-skl7/igt@kms_...@pipe-c-crc-sprite-planes-basic.html * igt@kms_color@pipe-d-ctm-max: - shard-skl: NOTRUN -> [SKIP][2] ([fdo#109271]) +27 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19117/shard-skl2/igt@kms_co...@pipe-d-ctm-max.html * igt@kms_color_chamelium@pipe-c-ctm-0-25: - shard-skl: NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19117/shard-skl7/igt@kms_color_chamel...@pipe-c-ctm-0-25.html * igt@kms_cursor_crc@pipe-a-cursor-dpms: - shard-skl: [PASS][4] -> [FAIL][5] ([i915#54]) +3 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9473/shard-skl5/igt@kms_cursor_...@pipe-a-cursor-dpms.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19117/shard-skl2/igt@kms_cursor_...@pipe-a-cursor-dpms.html * igt@kms_flip@flip-vs-expired-vblank@a-edp1: - shard-tglb: [PASS][6] -> [FAIL][7] ([i915#2598]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9473/shard-tglb6/igt@kms_flip@flip-vs-expired-vbl...@a-edp1.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19117/shard-tglb5/igt@kms_flip@flip-vs-expired-vbl...@a-edp1.html * igt@kms_flip@flip-vs-expired-vblank@c-dp1: - shard-kbl: [PASS][8] -> [FAIL][9] ([i915#79]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9473/shard-kbl7/igt@kms_flip@flip-vs-expired-vbl...@c-dp1.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19117/shard-kbl3/igt@kms_flip@flip-vs-expired-vbl...@c-dp1.html * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [PASS][10] -> [FAIL][11] ([fdo#108145] / [i915#265]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9473/shard-skl5/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19117/shard-skl2/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html * igt@kms_properties@connector-properties-legacy: - shard-kbl: [PASS][12] -> [DMESG-WARN][13] ([i915#165] / [i915#180] / [i915#78]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9473/shard-kbl7/igt@kms_propert...@connector-properties-legacy.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19117/shard-kbl2/igt@kms_propert...@connector-properties-legacy.html * igt@kms_psr@psr2_sprite_blt: - shard-iclb: [PASS][14] -> [SKIP][15] ([fdo#109441]) +1 similar issue [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9473/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19117/shard-iclb3/igt@kms_psr@psr2_sprite_blt.html * igt@perf@polling-parameterized: - shard-iclb: [PASS][16] -> [FAIL][17] ([i915#1542]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9473/shard-iclb7/igt@p...@polling-parameterized.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19117/shard-iclb2/igt@p...@polling-parameterized.html * igt@sysfs_timeslice_duration@invalid@vecs0: - shard-hsw: NOTRUN -> [SKIP][18] ([fdo#109271]) +9 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19117/shard-hsw8/igt@sysfs_timeslice_duration@inva...@vecs0.html Possible fixes * igt@gem_exec_reloc@basic-many-active@rcs0: - shard-apl: [FAIL][19] ([i915#2389]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9473/shard-apl7/igt@gem_exec_reloc@basic-many-act...@rcs0.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19117/shard-apl4/igt@gem_exec_reloc@basic-many-act...@rcs0.html * igt@kms_cursor_crc@pipe-a-cursor-64x21-sliding: - shard-skl: [FAIL][21] ([i915#54]) -> [PASS][22] +3 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9473/shard-skl1/igt@kms_cursor_...@pipe-a-cursor-64x21-sliding.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19117/shard-skl9/igt@kms_cursor_...@pipe-a-cursor-64x21-sliding.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic: - shard-skl: [FAIL][23] ([i915#2346]) -> [PASS][24] [23]:
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display: Go softly softly on initial modeset failure
== Series Details == Series: drm/i915/display: Go softly softly on initial modeset failure URL : https://patchwork.freedesktop.org/series/84808/ State : failure == Summary == Applying: drm/i915/display: Go softly softly on initial modeset failure Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/display/intel_display.c Falling back to patching base and 3-way merge... No changes -- Patch already applied. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] i915/gem_exec_fence: Check a submit chain
Submit a chain of spinners across all the engines, using the submit
fence to launch them in parallel.
Signed-off-by: Chris Wilson
---
lib/igt_dummyload.c | 7 +-
lib/igt_dummyload.h | 15 ++--
tests/i915/gem_exec_fence.c | 46 +
3 files changed, 60 insertions(+), 8 deletions(-)
diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
index 891e4eaab..4ef79cc4a 100644
--- a/lib/igt_dummyload.c
+++ b/lib/igt_dummyload.c
@@ -326,11 +326,16 @@ emit_recursive_batch(igt_spin_t *spin,
if (opts->flags & IGT_SPIN_FENCE_OUT)
execbuf->flags |= I915_EXEC_FENCE_OUT;
- if (opts->flags & IGT_SPIN_FENCE_IN) {
+ if (opts->flags & IGT_SPIN_FENCE_IN && opts->fence != -1) {
execbuf->flags |= I915_EXEC_FENCE_IN;
execbuf->rsvd2 = opts->fence;
}
+ if (opts->flags & IGT_SPIN_FENCE_SUBMIT && opts->fence != -1) {
+ execbuf->flags |= I915_EXEC_FENCE_SUBMIT;
+ execbuf->rsvd2 = opts->fence;
+ }
+
for (i = 0; i < nengine; i++) {
execbuf->flags &= ~ENGINE_MASK;
execbuf->flags |= flags[i];
diff --git a/lib/igt_dummyload.h b/lib/igt_dummyload.h
index b8baaa6b4..3ece70a50 100644
--- a/lib/igt_dummyload.h
+++ b/lib/igt_dummyload.h
@@ -65,13 +65,14 @@ struct igt_spin_factory {
};
#define IGT_SPIN_FENCE_IN (1 << 0)
-#define IGT_SPIN_FENCE_OUT (1 << 1)
-#define IGT_SPIN_POLL_RUN (1 << 2)
-#define IGT_SPIN_FAST (1 << 3)
-#define IGT_SPIN_NO_PREEMPTION (1 << 4)
-#define IGT_SPIN_INVALID_CS(1 << 5)
-#define IGT_SPIN_USERPTR (1 << 6)
-#define IGT_SPIN_SOFTDEP (1 << 7)
+#define IGT_SPIN_FENCE_SUBMIT (1 << 1)
+#define IGT_SPIN_FENCE_OUT (1 << 2)
+#define IGT_SPIN_POLL_RUN (1 << 3)
+#define IGT_SPIN_FAST (1 << 4)
+#define IGT_SPIN_NO_PREEMPTION (1 << 5)
+#define IGT_SPIN_INVALID_CS(1 << 6)
+#define IGT_SPIN_USERPTR (1 << 7)
+#define IGT_SPIN_SOFTDEP (1 << 8)
igt_spin_t *
__igt_spin_factory(int fd, const struct igt_spin_factory *opts);
diff --git a/tests/i915/gem_exec_fence.c b/tests/i915/gem_exec_fence.c
index 6eea050d8..ba454fcdb 100644
--- a/tests/i915/gem_exec_fence.c
+++ b/tests/i915/gem_exec_fence.c
@@ -796,6 +796,47 @@ static void test_concurrent(int i915, const struct
intel_execution_engine2 *e)
igt_spin_free(i915, spin);
}
+static void test_submit_chain(int i915)
+{
+ const struct intel_execution_engine2 *e;
+ igt_spin_t *spin, *sn;
+ IGT_LIST_HEAD(list);
+ IGT_CORK_FENCE(cork);
+ int fence;
+
+ /* Check that we can simultaneously launch spinners on each engine */
+
+ fence = igt_cork_plug(, i915);
+ __for_each_physical_engine(i915, e) {
+ spin = igt_spin_new(i915,
+ .engine = e->flags,
+ .fence = fence,
+ .flags = (IGT_SPIN_POLL_RUN |
+ IGT_SPIN_FENCE_OUT |
+ IGT_SPIN_FENCE_SUBMIT));
+
+ fence = spin->out_fence;
+ igt_list_move(>link, );
+ }
+
+ /* Nothing shall run until we pop the cork */
+ igt_list_for_each_entry(spin, , link) {
+ igt_assert(gem_bo_busy(i915, spin->handle));
+ igt_assert(!igt_spin_has_started(spin));
+ }
+
+ igt_cork_unplug();
+
+ /* Then everything shall run in parallel */
+ igt_list_for_each_entry_safe(spin, sn, , link) {
+ igt_spin_busywait_until_started(spin);
+ igt_spin_end(spin);
+ igt_assert_eq(sync_fence_wait(spin->out_fence, 50), 0);
+ igt_assert_eq(sync_fence_status(spin->out_fence), 1);
+ igt_spin_free(i915, spin);
+ }
+}
+
static uint32_t batch_create(int fd)
{
const uint32_t bbe = MI_BATCH_BUFFER_END;
@@ -3032,6 +3073,11 @@ igt_main
}
}
+ igt_subtest("submit-chain") {
+ igt_require(has_submit_fence(i915));
+ test_submit_chain(i915);
+ }
+
igt_fixture {
igt_stop_hang_detector();
}
--
2.29.2
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Split logical ring contexts from execlist submission (rev2)
== Series Details == Series: drm/i915/gt: Split logical ring contexts from execlist submission (rev2) URL : https://patchwork.freedesktop.org/series/84752/ State : success == Summary == CI Bug Log - changes from CI_DRM_9473_full -> Patchwork_19116_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_19116_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@hang: - shard-hsw: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19116/shard-hsw2/igt@gem_ctx_persiste...@hang.html * igt@i915_pm_dc@dc6-psr: - shard-skl: NOTRUN -> [FAIL][2] ([i915#454]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19116/shard-skl9/igt@i915_pm...@dc6-psr.html * igt@kms_async_flips@test-time-stamp: - shard-tglb: [PASS][3] -> [FAIL][4] ([i915#2597]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9473/shard-tglb8/igt@kms_async_fl...@test-time-stamp.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19116/shard-tglb8/igt@kms_async_fl...@test-time-stamp.html * igt@kms_ccs@pipe-c-crc-sprite-planes-basic: - shard-skl: NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111304]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19116/shard-skl2/igt@kms_...@pipe-c-crc-sprite-planes-basic.html * igt@kms_color@pipe-d-ctm-max: - shard-skl: NOTRUN -> [SKIP][6] ([fdo#109271]) +31 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19116/shard-skl1/igt@kms_co...@pipe-d-ctm-max.html * igt@kms_color_chamelium@pipe-b-gamma: - shard-hsw: NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19116/shard-hsw2/igt@kms_color_chamel...@pipe-b-gamma.html * igt@kms_color_chamelium@pipe-c-ctm-0-25: - shard-skl: NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827]) +5 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19116/shard-skl2/igt@kms_color_chamel...@pipe-c-ctm-0-25.html * igt@kms_cursor_crc@pipe-a-cursor-dpms: - shard-skl: [PASS][9] -> [FAIL][10] ([i915#54]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9473/shard-skl5/igt@kms_cursor_...@pipe-a-cursor-dpms.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19116/shard-skl1/igt@kms_cursor_...@pipe-a-cursor-dpms.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-skl: [PASS][11] -> [INCOMPLETE][12] ([i915#2295] / [i915#300]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9473/shard-skl5/igt@kms_cursor_...@pipe-a-cursor-suspend.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19116/shard-skl3/igt@kms_cursor_...@pipe-a-cursor-suspend.html * igt@kms_flip@flip-vs-expired-vblank@a-edp1: - shard-tglb: [PASS][13] -> [FAIL][14] ([i915#2598]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9473/shard-tglb6/igt@kms_flip@flip-vs-expired-vbl...@a-edp1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19116/shard-tglb2/igt@kms_flip@flip-vs-expired-vbl...@a-edp1.html * igt@kms_hdr@bpc-switch: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#1188]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9473/shard-skl5/igt@kms_...@bpc-switch.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19116/shard-skl1/igt@kms_...@bpc-switch.html * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145] / [i915#265]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9473/shard-skl5/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19116/shard-skl1/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html * igt@kms_psr@psr2_dpms: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9473/shard-iclb2/igt@kms_psr@psr2_dpms.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19116/shard-iclb3/igt@kms_psr@psr2_dpms.html * igt@nouveau_crc@pipe-c-source-rg: - shard-hsw: NOTRUN -> [SKIP][21] ([fdo#109271]) +18 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19116/shard-hsw2/igt@nouveau_...@pipe-c-source-rg.html Possible fixes * igt@gem_exec_reloc@basic-many-active@rcs0: - shard-apl: [FAIL][22] ([i915#2389]) -> [PASS][23] [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9473/shard-apl7/igt@gem_exec_reloc@basic-many-act...@rcs0.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19116/shard-apl6/igt@gem_exec_reloc@basic-many-act...@rcs0.html *
Re: [Intel-gfx] [patch 27/30] xen/events: Only force affinity mask for percpu interrupts
On Thu, Dec 10 2020 at 18:20, boris ostrovsky wrote: > On 12/10/20 2:26 PM, Thomas Gleixner wrote: >> All event channel setups bind the interrupt on CPU0 or the target CPU for >> percpu interrupts and overwrite the affinity mask with the corresponding >> cpumask. That does not make sense. >> >> The XEN implementation of irqchip::irq_set_affinity() already picks a >> single target CPU out of the affinity mask and the actual target is stored >> in the effective CPU mask, so destroying the user chosen affinity mask >> which might contain more than one CPU is wrong. >> >> Change the implementation so that the channel is bound to CPU0 at the XEN >> level and leave the affinity mask alone. At startup of the interrupt >> affinity will be assigned out of the affinity mask and the XEN binding will >> be updated. > > If that's the case then I wonder whether we need this call at all and > instead bind at startup time. I was wondering about that, but my knowledge about the Xen internal requirements is pretty limited. The current set at least survived basic testing by Jürgen. Thanks, tglx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for Introduce Intel PXP component - Mesa single session (rev6)
== Series Details == Series: Introduce Intel PXP component - Mesa single session (rev6) URL : https://patchwork.freedesktop.org/series/84620/ State : success == Summary == CI Bug Log - changes from CI_DRM_9473 -> Patchwork_19118 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19118/index.html Known issues Here are the changes found in Patchwork_19118 that come from known issues: ### IGT changes ### Issues hit * igt@gem_mmap_gtt@basic: - fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9473/fi-tgl-y/igt@gem_mmap_...@basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19118/fi-tgl-y/igt@gem_mmap_...@basic.html Possible fixes * igt@debugfs_test@read_all_entries: - fi-apl-guc: [DMESG-WARN][3] ([i915#62]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9473/fi-apl-guc/igt@debugfs_test@read_all_entries.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19118/fi-apl-guc/igt@debugfs_test@read_all_entries.html * igt@gem_exec_suspend@basic-s0: - fi-apl-guc: [DMESG-WARN][5] ([i915#180] / [i915#62]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9473/fi-apl-guc/igt@gem_exec_susp...@basic-s0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19118/fi-apl-guc/igt@gem_exec_susp...@basic-s0.html * igt@gem_linear_blits@basic: - fi-tgl-y: [DMESG-WARN][7] ([i915#402]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9473/fi-tgl-y/igt@gem_linear_bl...@basic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19118/fi-tgl-y/igt@gem_linear_bl...@basic.html [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 Participating hosts (44 -> 40) -- Missing(4): fi-ctg-p8600 fi-ilk-m540 fi-bdw-samus fi-hsw-4200u Build changes - * Linux: CI_DRM_9473 -> Patchwork_19118 CI-20190529: 20190529 CI_DRM_9473: c64377fd4f00a839c5b25b9e3bae1052fee113b5 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5888: c79d4e88f4162905da400360b6fa4940122f3a2c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19118: c5cb8520b5e1530d14c42e4b7830e7b53ff2878b @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c5cb8520b5e1 drm/i915/pxp: Enable the PXP ioctl for protected session 2d36ea7befb9 drm/i915/pxp: Add PXP-related registers into allowlist 611b466b4273 drm/i915/pxp: Termiante the session upon app crash e9386b8ba7be drm/i915/pxp: Implement ioctl action to query PXP tag 733af51aac06 drm/i915/pxp: Implement ioctl action to send TEE commands f2c7fba3da45 drm/i915/pxp: Implement ioctl action to terminate the session cd05c940fecf drm/i915/pxp: Implement ioctl action to set session in play 717f710b867c drm/i915/pxp: Implement ioctl action to reserve session slots 6b8e71a51390 drm/i915/pxp: Add plane decryption support 9d0636e9498a drm/i915/pxp: User interface for Protected buffer 238291470e9d drm/i915/uapi: introduce drm_i915_gem_create_ext d2ed1fac0c2c mei: pxp: export pavp client to me client bus c78a877702c7 drm/i915/pxp: Expose session state for display protection flip 1cc947ef42df drm/i915/pxp: Enable PXP power management 4243dda12065 drm/i915/pxp: Destroy arb session upon teardown e1072de8779e drm/i915/pxp: Enable PXP irq worker and callback stub 6e0495763e2b drm/i915/pxp: Func to send hardware session termination 1269b2f4bf9b drm/i915/pxp: Create the arbitrary session after boot cb091c29444b drm/i915/pxp: Implement funcs to create the TEE channel b12972ae3297 drm/i915/pxp: set KCR reg init during the boot time 483cb19f6248 drm/i915/pxp: Introduce Intel PXP component == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19118/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [patch 24/30] xen/events: Remove unused bind_evtchn_to_irq_lateeoi()
On Thu, Dec 10 2020 at 18:19, boris ostrovsky wrote: > On 12/10/20 2:26 PM, Thomas Gleixner wrote: >> -EXPORT_SYMBOL_GPL(bind_evtchn_to_irq_lateeoi); > > include/xen/events.h also needs to be updated (and in the next patch for > xen_set_affinity_evtchn() as well). Darn, I lost that. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.DOCS: warning for Introduce Intel PXP component - Mesa single session (rev6)
== Series Details == Series: Introduce Intel PXP component - Mesa single session (rev6) URL : https://patchwork.freedesktop.org/series/84620/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 Error: Cannot open file ./drivers/gpu/drm/i915/gt/intel_lrc.c WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -sphinx-version 1.7.9 -function Logical Rings, Logical Ring Contexts and Execlists ./drivers/gpu/drm/i915/gt/intel_lrc.c' failed with return code 1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/display: Go softly softly on initial modeset failure
On Thu, Dec 10, 2020 at 3:13 PM Rodrigo Vivi wrote:
>
> On Thu, Dec 10, 2020 at 11:07:41PM +, Chris Wilson wrote:
> > Reduce the module/device probe error into a mere debug to hide issues
> > where the initial modeset is failing (after lies told by hw probe) and
> > the system hangs with a livelock in cleaning up the failed commit.
> >
> > Reported-by: H.J. Lu
> > Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=210619
> > Fixes: b3bf99daaee9 ("drm/i915/display: Defer initial modeset until after
> > GGTT is initialised")
> > Fixes: ccc9e67ab26f ("drm/i915/display: Defer initial modeset until after
> > GGTT is initialised")
> > Signed-off-by: Chris Wilson
> > Cc: "Ville Syrjälä"
> > Cc: Rodrigo Vivi
> > Cc: H.J. Lu
> > Cc: Dave Airlie
>
> Reviewed-by: Rodrigo Vivi
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index c567c0cada7e..761be8deaa9b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -18755,7 +18755,7 @@ int intel_modeset_init(struct drm_i915_private
> > *i915)
> >*/
> > ret = intel_initial_commit(>drm);
> > if (ret)
> > - return ret;
> > + drm_dbg_kms(>drm, "Initial modeset failed, %d\n", ret);
Yes, it fixed the problem.
Thanks.
> > intel_overlay_setup(i915);
> >
> > --
> > 2.20.1
> >
--
H.J.
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Intel PXP component - Mesa single session (rev6)
== Series Details == Series: Introduce Intel PXP component - Mesa single session (rev6) URL : https://patchwork.freedesktop.org/series/84620/ State : warning == Summary == $ dim checkpatch origin/drm-tip 483cb19f6248 drm/i915/pxp: Introduce Intel PXP component -:111: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #111: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 175 lines checked b12972ae3297 drm/i915/pxp: set KCR reg init during the boot time cb091c29444b drm/i915/pxp: Implement funcs to create the TEE channel -:8: WARNING:TYPO_SPELLING: 'defualt' may be misspelled - perhaps 'default'? #8: (defualt) session. -:85: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #85: new file mode 100644 total: 0 errors, 2 warnings, 0 checks, 248 lines checked 1269b2f4bf9b drm/i915/pxp: Create the arbitrary session after boot -:68: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #68: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 297 lines checked 6e0495763e2b drm/i915/pxp: Func to send hardware session termination -:25: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #25: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 181 lines checked e1072de8779e drm/i915/pxp: Enable PXP irq worker and callback stub -:51: WARNING:LONG_LINE_COMMENT: line length of 113 exceeds 100 columns #51: FILE: drivers/gpu/drm/i915/i915_reg.h:7970: +#define GEN11_CRYPTO_INTR_MASK _MMIO(0x1900f0) /* crypto mask is in bit31-16 (Engine1 Interrupt Mask) */ total: 0 errors, 1 warnings, 0 checks, 210 lines checked 4243dda12065 drm/i915/pxp: Destroy arb session upon teardown 1cc947ef42df drm/i915/pxp: Enable PXP power management -:90: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #90: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 148 lines checked c78a877702c7 drm/i915/pxp: Expose session state for display protection flip d2ed1fac0c2c mei: pxp: export pavp client to me client bus -:32: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #32: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 277 lines checked 238291470e9d drm/i915/uapi: introduce drm_i915_gem_create_ext -:12: ERROR:BAD_SIGN_OFF: Unrecognized email address: 'Joonas Lahtinen joonas.lahti...@linux.intel.com' #12: Cc: Joonas Lahtinen joonas.lahti...@linux.intel.com -:13: ERROR:BAD_SIGN_OFF: Unrecognized email address: 'Matthew Auld matthew.a...@intel.com' #13: Cc: Matthew Auld matthew.a...@intel.com -:46: ERROR:CODE_INDENT: code indent should use tabs where possible #46: FILE: drivers/gpu/drm/i915/i915_gem.c:265: +struct drm_i915_private *i915;$ -:46: WARNING:LEADING_SPACE: please, no spaces at the start of a line #46: FILE: drivers/gpu/drm/i915/i915_gem.c:265: +struct drm_i915_private *i915;$ -:50: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #50: FILE: drivers/gpu/drm/i915/i915_gem.c:269: +static int __create_setparam(struct drm_i915_gem_object_param *args, + struct create_ext *ext_data) -:95: CHECK:LINE_SPACING: Please don't use multiple blank lines #95: FILE: drivers/gpu/drm/i915/i915_gem.c:317: + + -:107: WARNING:LONG_LINE: line length of 120 exceeds 100 columns #107: FILE: include/uapi/drm/i915_drm.h:394: +#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext) -:155: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #155: FILE: include/uapi/drm/i915_drm.h:1735: +#define I915_OBJECT_PARAM (1ull<<32) ^ total: 3 errors, 2 warnings, 3 checks, 136 lines checked 9d0636e9498a drm/i915/pxp: User interface for Protected buffer 6b8e71a51390 drm/i915/pxp: Add plane decryption support 717f710b867c drm/i915/pxp: Implement ioctl action to reserve session slots -:62: WARNING:PREFER_PACKED: __packed is preferred over __attribute__((packed)) #62: FILE: drivers/gpu/drm/i915/pxp/intel_pxp.c:39: +} __attribute__((packed)); -:254: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #254: new file mode 100644 -:345: WARNING:MSLEEP: msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.rst #345: FILE: drivers/gpu/drm/i915/pxp/intel_pxp_sm.c:87: + msleep(10); total: 0 errors, 3 warnings, 0 checks, 437 lines checked cd05c940fecf drm/i915/pxp: Implement ioctl action to set session in play f2c7fba3da45 drm/i915/pxp: Implement ioctl action to terminate the session 733af51aac06 drm/i915/pxp: Implement ioctl action to send TEE commands e9386b8ba7be drm/i915/pxp: Implement ioctl action to query PXP tag 611b466b4273 drm/i915/pxp: Termiante the session upon app crash
[Intel-gfx] ✓ Fi.CI.BAT: success for drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev3)
== Series Details == Series: drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev3) URL : https://patchwork.freedesktop.org/series/84754/ State : success == Summary == CI Bug Log - changes from CI_DRM_9473 -> Patchwork_19117 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19117/index.html Known issues Here are the changes found in Patchwork_19117 that come from known issues: ### IGT changes ### Issues hit * igt@fbdev@read: - fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9473/fi-tgl-y/igt@fb...@read.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19117/fi-tgl-y/igt@fb...@read.html * igt@i915_selftest@live@coherency: - fi-gdg-551: [PASS][3] -> [DMESG-FAIL][4] ([i915#1748]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9473/fi-gdg-551/igt@i915_selftest@l...@coherency.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19117/fi-gdg-551/igt@i915_selftest@l...@coherency.html Possible fixes * igt@debugfs_test@read_all_entries: - fi-apl-guc: [DMESG-WARN][5] ([i915#62]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9473/fi-apl-guc/igt@debugfs_test@read_all_entries.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19117/fi-apl-guc/igt@debugfs_test@read_all_entries.html * igt@gem_exec_suspend@basic-s0: - fi-apl-guc: [DMESG-WARN][7] ([i915#180] / [i915#62]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9473/fi-apl-guc/igt@gem_exec_susp...@basic-s0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19117/fi-apl-guc/igt@gem_exec_susp...@basic-s0.html [i915#1748]: https://gitlab.freedesktop.org/drm/intel/issues/1748 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 Participating hosts (44 -> 40) -- Missing(4): fi-ctg-p8600 fi-ilk-m540 fi-bdw-samus fi-hsw-4200u Build changes - * Linux: CI_DRM_9473 -> Patchwork_19117 CI-20190529: 20190529 CI_DRM_9473: c64377fd4f00a839c5b25b9e3bae1052fee113b5 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5888: c79d4e88f4162905da400360b6fa4940122f3a2c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19117: e9d81787a6e79b5b7cd1caaf750cd18d35d4cb8c @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == e9d81787a6e7 drm/nouveau/kms/nv50-: Add basic DPCD backlight support for nouveau f4bf871fa73a drm/dp: Extract i915's eDP backlight code into DRM helpers f4762128551a drm/i915/dp: Remove redundant AUX backlight frequency calculations 945b0c32e7e2 drm/nouveau/kms: Don't probe eDP connectors more then once cfc42e455a86 drm/nouveau/kms/nv40-/backlight: Assign prop type once == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19117/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/display: Go softly softly on initial modeset failure
On Thu, Dec 10, 2020 at 11:07:41PM +, Chris Wilson wrote:
> Reduce the module/device probe error into a mere debug to hide issues
> where the initial modeset is failing (after lies told by hw probe) and
> the system hangs with a livelock in cleaning up the failed commit.
>
> Reported-by: H.J. Lu
> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=210619
> Fixes: b3bf99daaee9 ("drm/i915/display: Defer initial modeset until after
> GGTT is initialised")
> Fixes: ccc9e67ab26f ("drm/i915/display: Defer initial modeset until after
> GGTT is initialised")
> Signed-off-by: Chris Wilson
> Cc: "Ville Syrjälä"
> Cc: Rodrigo Vivi
> Cc: H.J. Lu
> Cc: Dave Airlie
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index c567c0cada7e..761be8deaa9b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -18755,7 +18755,7 @@ int intel_modeset_init(struct drm_i915_private *i915)
>*/
> ret = intel_initial_commit(>drm);
> if (ret)
> - return ret;
> + drm_dbg_kms(>drm, "Initial modeset failed, %d\n", ret);
>
> intel_overlay_setup(i915);
>
> --
> 2.20.1
>
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[Intel-gfx] [PATCH] drm/i915/display: Go softly softly on initial modeset failure
Reduce the module/device probe error into a mere debug to hide issues
where the initial modeset is failing (after lies told by hw probe) and
the system hangs with a livelock in cleaning up the failed commit.
Reported-by: H.J. Lu
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=210619
Fixes: b3bf99daaee9 ("drm/i915/display: Defer initial modeset until after GGTT
is initialised")
Fixes: ccc9e67ab26f ("drm/i915/display: Defer initial modeset until after GGTT
is initialised")
Signed-off-by: Chris Wilson
Cc: "Ville Syrjälä"
Cc: Rodrigo Vivi
Cc: H.J. Lu
Cc: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index c567c0cada7e..761be8deaa9b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -18755,7 +18755,7 @@ int intel_modeset_init(struct drm_i915_private *i915)
*/
ret = intel_initial_commit(>drm);
if (ret)
- return ret;
+ drm_dbg_kms(>drm, "Initial modeset failed, %d\n", ret);
intel_overlay_setup(i915);
--
2.20.1
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[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev3)
== Series Details == Series: drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev3) URL : https://patchwork.freedesktop.org/series/84754/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 Error: Cannot open file ./drivers/gpu/drm/i915/gt/intel_lrc.c WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -sphinx-version 1.7.9 -function Logical Rings, Logical Ring Contexts and Execlists ./drivers/gpu/drm/i915/gt/intel_lrc.c' failed with return code 1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev3)
== Series Details == Series: drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev3) URL : https://patchwork.freedesktop.org/series/84754/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev3)
== Series Details ==
Series: drm: Extract DPCD backlight helpers from i915, add support in nouveau
(rev3)
URL : https://patchwork.freedesktop.org/series/84754/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
cfc42e455a86 drm/nouveau/kms/nv40-/backlight: Assign prop type once
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
total: 0 errors, 1 warnings, 0 checks, 22 lines checked
945b0c32e7e2 drm/nouveau/kms: Don't probe eDP connectors more then once
-:6: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#6:
eDP doesn't do hotplugging, so there's no reason for us to reprobe it (unless a
-:23: CHECK:CAMELCASE: Avoid CamelCase:
#23: FILE: drivers/gpu/drm/nouveau/nouveau_connector.c:558:
+ if (nv_connector->type == DCB_CONNECTOR_eDP &&
total: 0 errors, 1 warnings, 1 checks, 12 lines checked
f4762128551a drm/i915/dp: Remove redundant AUX backlight frequency calculations
f4bf871fa73a drm/dp: Extract i915's eDP backlight code into DRM helpers
e9d81787a6e7 drm/nouveau/kms/nv50-: Add basic DPCD backlight support for nouveau
-:247: CHECK:CAMELCASE: Avoid CamelCase:
#247: FILE: drivers/gpu/drm/nouveau/nouveau_backlight.c:299:
+ if (nv_conn->type == DCB_CONNECTOR_eDP) {
total: 0 errors, 0 warnings, 1 checks, 311 lines checked
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Re: [Intel-gfx] [patch 19/30] PCI: mobiveil: Use irq_data_get_irq_chip_data()
On Thu, Dec 10, 2020 at 1:42 PM Thomas Gleixner wrote: > > Going through a full irq descriptor lookup instead of just using the proper > helper function which provides direct access is suboptimal. > > In fact it _is_ wrong because the chip callback needs to get the chip data > which is relevant for the chip while using the irq descriptor variant > returns the irq chip data of the top level chip of a hierarchy. It does not > matter in this case because the chip is the top level chip, but that > doesn't make it more correct. > > Signed-off-by: Thomas Gleixner > Cc: Karthikeyan Mitran > Cc: Hou Zhiqiang > Cc: Lorenzo Pieralisi > Cc: Rob Herring > Cc: Bjorn Helgaas > Cc: linux-...@vger.kernel.org > --- > drivers/pci/controller/mobiveil/pcie-mobiveil-host.c |8 ++-- > 1 file changed, 2 insertions(+), 6 deletions(-) Reviewed-by: Rob Herring ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Split logical ring contexts from execlist submission (rev2)
== Series Details == Series: drm/i915/gt: Split logical ring contexts from execlist submission (rev2) URL : https://patchwork.freedesktop.org/series/84752/ State : success == Summary == CI Bug Log - changes from CI_DRM_9473 -> Patchwork_19116 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19116/index.html Known issues Here are the changes found in Patchwork_19116 that come from known issues: ### IGT changes ### Issues hit * igt@prime_self_import@basic-with_two_bos: - fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9473/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19116/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html Possible fixes * igt@debugfs_test@read_all_entries: - fi-apl-guc: [DMESG-WARN][3] ([i915#62]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9473/fi-apl-guc/igt@debugfs_test@read_all_entries.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19116/fi-apl-guc/igt@debugfs_test@read_all_entries.html * igt@gem_exec_suspend@basic-s0: - fi-apl-guc: [DMESG-WARN][5] ([i915#180] / [i915#62]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9473/fi-apl-guc/igt@gem_exec_susp...@basic-s0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19116/fi-apl-guc/igt@gem_exec_susp...@basic-s0.html * igt@prime_self_import@basic-with_one_bo_two_files: - fi-tgl-y: [DMESG-WARN][7] ([i915#402]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9473/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19116/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 Participating hosts (44 -> 40) -- Missing(4): fi-ctg-p8600 fi-ilk-m540 fi-bdw-samus fi-hsw-4200u Build changes - * Linux: CI_DRM_9473 -> Patchwork_19116 CI-20190529: 20190529 CI_DRM_9473: c64377fd4f00a839c5b25b9e3bae1052fee113b5 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5888: c79d4e88f4162905da400360b6fa4940122f3a2c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19116: 45457993418238faaf6aa208e4db58e4d12b9db6 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 454579934182 drm/i915/gt: Split logical ring contexts from execlist submission == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19116/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [patch 18/30] PCI: xilinx-nwl: Use irq_data_get_irq_chip_data()
On Thu, Dec 10, 2020 at 1:42 PM Thomas Gleixner wrote: > > Going through a full irq descriptor lookup instead of just using the proper > helper function which provides direct access is suboptimal. > > In fact it _is_ wrong because the chip callback needs to get the chip data > which is relevant for the chip while using the irq descriptor variant > returns the irq chip data of the top level chip of a hierarchy. It does not > matter in this case because the chip is the top level chip, but that > doesn't make it more correct. > > Signed-off-by: Thomas Gleixner > Cc: Lorenzo Pieralisi > Cc: Rob Herring > Cc: Bjorn Helgaas > Cc: Michal Simek > Cc: linux-...@vger.kernel.org > Cc: linux-arm-ker...@lists.infradead.org > --- > drivers/pci/controller/pcie-xilinx-nwl.c |8 ++-- > 1 file changed, 2 insertions(+), 6 deletions(-) Reviewed-by: Rob Herring ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC-v6 06/21] drm/i915/pxp: Enable PXP irq worker and callback stub
Create the irq worker that serves as callback handler, those
callback stubs should be called while the hardware key teardown
occurs.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 4 +
drivers/gpu/drm/i915/i915_reg.h | 3 +-
drivers/gpu/drm/i915/pxp/intel_pxp.c | 101 +++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 27 +
drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 2 +
drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 1 +
6 files changed, 137 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index 257063a57101..fbe9ef88b905 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -13,6 +13,7 @@
#include "intel_gt_irq.h"
#include "intel_uncore.h"
#include "intel_rps.h"
+#include "pxp/intel_pxp.h"
static void guc_irq_handler(struct intel_guc *guc, u16 iir)
{
@@ -106,6 +107,9 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8
instance,
if (instance == OTHER_GTPM_INSTANCE)
return gen11_rps_irq_handler(>rps, iir);
+ if (instance == OTHER_KCR_INSTANCE)
+ return intel_pxp_irq_handler(>pxp, iir);
+
WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
instance, iir);
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0023c023f472..1e8dfe435ca8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7944,6 +7944,7 @@ enum {
/* irq instances for OTHER_CLASS */
#define OTHER_GUC_INSTANCE 0
#define OTHER_GTPM_INSTANCE1
+#define OTHER_KCR_INSTANCE 4
#define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
@@ -7966,7 +7967,7 @@ enum {
#define GEN11_VECS0_VECS1_INTR_MASK_MMIO(0x1900d0)
#define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8)
#define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec)
-#define GEN11_CRYPTO_RSVD_INTR_MASK_MMIO(0x1900f0)
+#define GEN11_CRYPTO_INTR_MASK _MMIO(0x1900f0) /* crypto mask is in
bit31-16 (Engine1 Interrupt Mask) */
#define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4)
#define ENGINE1_MASK REG_GENMASK(31, 16)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 67bdaeb79b40..9bcb170b34f1 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -14,6 +14,70 @@
/* Setting KCR Init bit is required after system boot */
#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) <<
KCR_INIT_MASK_SHIFT))
+static void intel_pxp_write_irq_mask_reg(struct intel_gt *gt, u32 mask)
+{
+ lockdep_assert_held(>irq_lock);
+
+ intel_uncore_write(gt->uncore, GEN11_CRYPTO_INTR_MASK, mask << 16);
+}
+
+static int intel_pxp_teardown_required_callback(struct intel_pxp *pxp)
+{
+ int ret;
+
+ mutex_lock(>ctx.mutex);
+
+ pxp->ctx.global_state_attacked = true;
+
+ mutex_unlock(>ctx.mutex);
+
+ return ret;
+}
+
+static int intel_pxp_global_terminate_complete_callback(struct intel_pxp *pxp)
+{
+ int ret = 0;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+
+ mutex_lock(>ctx.mutex);
+
+ if (pxp->ctx.global_state_attacked) {
+ pxp->ctx.global_state_attacked = false;
+
+ /* Re-create the arb session after teardown handle complete */
+ ret = intel_pxp_arb_create_session(pxp);
+ if (ret) {
+ drm_err(>i915->drm, "Failed to create arb
session\n");
+ goto end;
+ }
+ }
+end:
+ mutex_unlock(>ctx.mutex);
+ return ret;
+}
+
+static void intel_pxp_irq_work(struct work_struct *work)
+{
+ struct intel_pxp *pxp = container_of(work, typeof(*pxp), irq_work);
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+ u32 events = 0;
+
+ spin_lock_irq(>irq_lock);
+ events = fetch_and_zero(>current_events);
+ spin_unlock_irq(>irq_lock);
+
+ if (events & PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED ||
+ events & PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ)
+ intel_pxp_teardown_required_callback(pxp);
+
+ if (events & PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE)
+ intel_pxp_global_terminate_complete_callback(pxp);
+
+ spin_lock_irq(>irq_lock);
+ intel_pxp_write_irq_mask_reg(gt, 0);
+ spin_unlock_irq(>irq_lock);
+}
+
int intel_pxp_init(struct intel_pxp *pxp)
{
struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
@@ -28,6 +92,12 @@ int intel_pxp_init(struct intel_pxp *pxp)
intel_pxp_tee_component_init(pxp);
+ INIT_WORK(>irq_work, intel_pxp_irq_work);
+
+ pxp->handled_irr = (PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED |
+
[Intel-gfx] [RFC-v6 03/21] drm/i915/pxp: Implement funcs to create the TEE channel
Implement the funcs to create the TEE channel, so kernel can
send the TEE commands directly to TEE for creating the arbitrary
(defualt) session.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile| 3 +-
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 6 ++
drivers/gpu/drm/i915/pxp/intel_pxp.c | 5 +
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 132 +++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 14 +++
include/drm/i915_component.h | 1 +
include/drm/i915_pxp_tee_interface.h | 45
8 files changed, 206 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
create mode 100644 include/drm/i915_pxp_tee_interface.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 99efac469cc2..c703dbd91158 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -257,7 +257,8 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
- pxp/intel_pxp_context.o
+ pxp/intel_pxp_context.o \
+ pxp/intel_pxp_tee.o
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5708e11d917b..9299a456adb0 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -322,6 +322,7 @@ static int i915_driver_early_probe(struct drm_i915_private
*dev_priv)
mutex_init(_priv->wm.wm_mutex);
mutex_init(_priv->pps_mutex);
mutex_init(_priv->hdcp_comp_mutex);
+ mutex_init(_priv->pxp_tee_comp_mutex);
i915_memcpy_init_early(dev_priv);
intel_runtime_pm_init_early(_priv->runtime_pm);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fc1090c6889c..66f91d8a575b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1216,6 +1216,12 @@ struct drm_i915_private {
/* Mutex to protect the above hdcp component related values. */
struct mutex hdcp_comp_mutex;
+ struct i915_pxp_comp_master *pxp_tee_master;
+ bool pxp_tee_comp_added;
+
+ /* Mutex to protect the above pxp_tee component related values. */
+ struct mutex pxp_tee_comp_mutex;
+
I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
/*
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index c4815950567d..4104dd89ca7f 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -5,6 +5,7 @@
#include "i915_drv.h"
#include "intel_pxp.h"
#include "intel_pxp_context.h"
+#include "intel_pxp_tee.h"
/* KCR register definitions */
#define KCR_INIT_MMIO(0x320f0)
@@ -24,6 +25,8 @@ int intel_pxp_init(struct intel_pxp *pxp)
intel_uncore_write(gt->uncore, KCR_INIT,
KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
+ intel_pxp_tee_component_init(pxp);
+
drm_info(>i915->drm, "Protected Xe Path (PXP) protected content
support initialized\n");
return 0;
@@ -31,5 +34,7 @@ int intel_pxp_init(struct intel_pxp *pxp)
void intel_pxp_uninit(struct intel_pxp *pxp)
{
+ intel_pxp_tee_component_fini(pxp);
+
intel_pxp_ctx_fini(>ctx);
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
new file mode 100644
index ..ca6b61099aee
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+
+#include
+#include "drm/i915_pxp_tee_interface.h"
+#include "drm/i915_component.h"
+#include "i915_drv.h"
+#include "intel_pxp.h"
+#include "intel_pxp_context.h"
+#include "intel_pxp_tee.h"
+
+static int intel_pxp_tee_io_message(struct intel_pxp *pxp,
+ void *msg_in, u32 msg_in_size,
+ void *msg_out, u32 *msg_out_size_ptr,
+ u32 msg_out_buf_size)
+{
+ int ret;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+ struct drm_i915_private *i915 = gt->i915;
+ struct i915_pxp_comp_master *pxp_tee_master = i915->pxp_tee_master;
+
+ if (!pxp_tee_master || !msg_in || !msg_out || !msg_out_size_ptr)
+ return -EINVAL;
+
+ lockdep_assert_held(>pxp_tee_comp_mutex);
+
+ if (drm_debug_enabled(DRM_UT_DRIVER))
+ print_hex_dump(KERN_DEBUG, "TEE input message binaries:",
+ DUMP_PREFIX_OFFSET, 4, 4, msg_in, msg_in_size,
true);
+
+ ret = pxp_tee_master->ops->send(pxp_tee_master->tee_dev, msg_in,
msg_in_size);
+ if (ret) {
+ drm_err(>drm, "Failed
[Intel-gfx] [RFC-v6 08/21] drm/i915/pxp: Enable PXP power management
During the power event S3+ sleep/resume, hardware will lose all the
encryption keys for every hardware session, even though the
software session state was marked as alive after resume. So to
handle such case, PXP should terminate all the hardware sessions
and cleanup all the software states after the power cycle.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/gt/intel_gt_pm.c| 4 ++
drivers/gpu/drm/i915/i915_drv.c | 4 ++
drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 65
drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 31 ++
6 files changed, 106 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 2da904cda49f..2545b59fa4f2 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -260,6 +260,7 @@ i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp_arb.o \
pxp/intel_pxp_cmd.o \
pxp/intel_pxp_context.o \
+ pxp/intel_pxp_pm.o \
pxp/intel_pxp_tee.o
# Post-mortem debug and GPU hang state capture
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index 274aa0dd7050..09a64d0feafe 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -20,6 +20,7 @@
#include "intel_rc6.h"
#include "intel_rps.h"
#include "intel_wakeref.h"
+#include "pxp/intel_pxp_pm.h"
static void user_forcewake(struct intel_gt *gt, bool suspend)
{
@@ -241,6 +242,8 @@ int intel_gt_resume(struct intel_gt *gt)
intel_uc_resume(>uc);
+ intel_pxp_pm_resume(>pxp);
+
user_forcewake(gt, false);
out_fw:
@@ -275,6 +278,7 @@ void intel_gt_suspend_prepare(struct intel_gt *gt)
user_forcewake(gt, true);
wait_for_suspend(gt);
+ intel_pxp_pm_prepare_suspend(>pxp);
intel_uc_suspend(>uc);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9299a456adb0..af06c85e6ba7 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -68,6 +68,8 @@
#include "gt/intel_gt_pm.h"
#include "gt/intel_rc6.h"
+#include "pxp/intel_pxp_pm.h"
+
#include "i915_debugfs.h"
#include "i915_drv.h"
#include "i915_ioc32.h"
@@ -1344,6 +1346,8 @@ static int i915_drm_resume_early(struct drm_device *dev)
intel_power_domains_resume(dev_priv);
+ intel_pxp_pm_resume_early(_priv->gt.pxp);
+
enable_rpm_wakeref_asserts(_priv->runtime_pm);
return ret;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
index 3ba891f9ac26..8d3308ac3120 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
@@ -20,6 +20,7 @@ struct pxp_context {
int id;
bool global_state_attacked;
+ bool global_state_in_suspend;
bool flag_display_hm_surface_keys;
};
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
new file mode 100644
index ..0da2ecbf3b4d
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+
+#include "intel_pxp_context.h"
+#include "intel_pxp_arb.h"
+#include "intel_pxp_pm.h"
+
+void intel_pxp_pm_prepare_suspend(struct intel_pxp *pxp)
+{
+ if (pxp->ctx.id == 0)
+ return;
+
+ mutex_lock(>ctx.mutex);
+
+ /* Disable PXP-IOCTLs */
+ pxp->ctx.global_state_in_suspend = true;
+
+ mutex_unlock(>ctx.mutex);
+}
+
+void intel_pxp_pm_resume_early(struct intel_pxp *pxp)
+{
+ if (pxp->ctx.id == 0)
+ return;
+
+ mutex_lock(>ctx.mutex);
+
+ if (pxp->ctx.global_state_in_suspend) {
+ /* reset the attacked flag even there was a pending */
+ pxp->ctx.global_state_attacked = false;
+
+ pxp->ctx.flag_display_hm_surface_keys = false;
+ }
+
+ mutex_unlock(>ctx.mutex);
+}
+
+int intel_pxp_pm_resume(struct intel_pxp *pxp)
+{
+ int ret = 0;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+
+ if (pxp->ctx.id == 0)
+ return 0;
+
+ mutex_lock(>ctx.mutex);
+
+ /* Re-enable PXP-IOCTLs */
+ if (pxp->ctx.global_state_in_suspend) {
+ ret = intel_pxp_arb_terminate_session(pxp);
+ if (ret) {
+ drm_err(>i915->drm, "Failed to terminate the arb
session\n");
+ goto end;
+ }
+
+ pxp->ctx.global_state_in_suspend = false;
+ }
+
+end:
+ mutex_unlock(>ctx.mutex);
+
+ return ret;
+}
diff --git
[Intel-gfx] [RFC-v6 15/21] drm/i915/pxp: Implement ioctl action to set session in play
With this ioctl action, userspace driver can set the session in
state "session in play", after dirver reserved the session slot/id
from kernel PXP, and sent the TEE commands to activate the
corresponding hardware session. Session state "session in play"
means this session is ready for secure playback.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c| 11 +-
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 51 +
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 2 +
3 files changed, 63 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index e294134fef78..e000a78b782e 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -16,7 +16,13 @@
#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) <<
KCR_INIT_MASK_SHIFT))
#define PXP_ACTION_SET_SESSION_STATUS 1
-#define PXP_REQ_SESSION_ID_INIT 0
+
+enum pxp_session_req {
+ /* Request KMD to allocate session id and move it to IN INIT */
+ PXP_REQ_SESSION_ID_INIT = 0x0,
+ /* Inform KMD that UMD has completed the initialization */
+ PXP_REQ_SESSION_IN_PLAY,
+};
/*
* struct pxp_set_session_status_params - Params to reserved, set or destroy
@@ -228,6 +234,9 @@ int i915_pxp_ops_ioctl(struct drm_device *dev, void *data,
struct drm_file *drmf
pxp_info.sm_status = ret;
ret = 0;
}
+ } else if (params->req_session_state ==
PXP_REQ_SESSION_IN_PLAY) {
+ ret = intel_pxp_sm_ioctl_mark_session_in_play(pxp,
params->session_type,
+
params->pxp_tag);
} else {
ret = -EINVAL;
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index a68316be1bfd..e5858c17e62f 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -12,6 +12,9 @@
#define GEN12_KCR_TSIP _MMIO(0x32264) /* KCR type1 session in play 0-63 */
+#define SESSION_TYPE_MASK BIT(7)
+#define SESSION_ID_MASK (BIT(7) - 1)
+
static inline int session_max(int session_type)
{
return (session_type == SESSION_TYPE_TYPE0) ?
@@ -148,6 +151,17 @@ static int create_session_entry(struct intel_pxp *pxp,
struct drm_file *drmfile,
return 0;
}
+static int pxp_get_session_index(u32 session_id, int *index_out, int *type_out)
+{
+ if (!index_out || !type_out)
+ return -EINVAL;
+
+ *type_out = (session_id & SESSION_TYPE_MASK) ? SESSION_TYPE_TYPE1 :
SESSION_TYPE_TYPE0;
+ *index_out = session_id & SESSION_ID_MASK;
+
+ return 0;
+}
+
/**
* intel_pxp_sm_ioctl_reserve_session - To reserve an available protected
session.
* @pxp: pointer to pxp struct
@@ -192,3 +206,40 @@ int intel_pxp_sm_ioctl_reserve_session(struct intel_pxp
*pxp, struct drm_file *d
return PXP_SM_STATUS_SESSION_NOT_AVAILABLE;
}
+
+/**
+ * intel_pxp_sm_ioctl_mark_session_in_play - Put an reserved session to
"in_play" state
+ * @pxp: pointer to pxp struct
+ * @session_type: Type of the session to be updated. One of enum
pxp_session_types.
+ * @session_id: Session identifier of the session, containing type and index
info
+ *
+ * Return: status. 0 means update is successful.
+ */
+int intel_pxp_sm_ioctl_mark_session_in_play(struct intel_pxp *pxp, int
session_type,
+ u32 session_id)
+{
+ int ret;
+ int session_index;
+ int session_type_in_id;
+ struct intel_pxp_sm_session *curr;
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+
+ ret = pxp_get_session_index(session_id, _index,
_type_in_id);
+ if (ret)
+ return ret;
+
+ if (session_type != session_type_in_id)
+ return -EINVAL;
+
+ lockdep_assert_held(>ctx.mutex);
+
+ list_for_each_entry(curr, session_list(pxp, session_type), list) {
+ if (curr->index == session_index) {
+ curr->is_in_play = true;
+ return 0;
+ }
+ }
+
+ drm_err(>i915->drm, "Failed to %s couldn't find active session\n",
__func__);
+ return -EINVAL;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
index 75fffb7d8b0e..aaa44d365f39 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
@@ -40,4 +40,6 @@ struct intel_pxp_sm_session {
int intel_pxp_sm_ioctl_reserve_session(struct intel_pxp *pxp, struct drm_file
*drmfile,
int session_type, int protection_mode,
u32 *pxp_tag);
+int intel_pxp_sm_ioctl_mark_session_in_play(struct intel_pxp *pxp, int
session_type,
+
[Intel-gfx] [RFC-v6 16/21] drm/i915/pxp: Implement ioctl action to terminate the session
Implement the PXP ioctl action to allow userspace driver to
terminate the hardware session and cleanup its software session
state. PXP sends the session termination command to GPU once
receves this ioctl action.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 10 +++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 6 ++
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 56
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 2 +
drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 7 ++
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 109 ---
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 6 ++
7 files changed, 186 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index e000a78b782e..c35011b84f5a 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -8,6 +8,7 @@
#include "intel_pxp_tee.h"
#include "intel_pxp_arb.h"
#include "intel_pxp_sm.h"
+#include "intel_pxp_cmd.h"
/* KCR register definitions */
#define KCR_INIT_MMIO(0x320f0)
@@ -22,6 +23,8 @@ enum pxp_session_req {
PXP_REQ_SESSION_ID_INIT = 0x0,
/* Inform KMD that UMD has completed the initialization */
PXP_REQ_SESSION_IN_PLAY,
+ /* Request KMD to terminate the session */
+ PXP_REQ_SESSION_TERMINATE
};
/*
@@ -68,7 +71,11 @@ static int intel_pxp_teardown_required_callback(struct
intel_pxp *pxp)
pxp->ctx.flag_display_hm_surface_keys = false;
ret = intel_pxp_arb_terminate_session(pxp);
+ if (ret)
+ goto end;
+ ret = intel_pxp_sm_terminate_all_sessions(pxp, SESSION_TYPE_TYPE0);
+end:
mutex_unlock(>ctx.mutex);
return ret;
@@ -237,6 +244,9 @@ int i915_pxp_ops_ioctl(struct drm_device *dev, void *data,
struct drm_file *drmf
} else if (params->req_session_state ==
PXP_REQ_SESSION_IN_PLAY) {
ret = intel_pxp_sm_ioctl_mark_session_in_play(pxp,
params->session_type,
params->pxp_tag);
+ } else if (params->req_session_state ==
PXP_REQ_SESSION_TERMINATE) {
+ ret = intel_pxp_sm_ioctl_terminate_session(pxp,
params->session_type,
+
params->pxp_tag);
} else {
ret = -EINVAL;
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 461b9321441f..e68c035d8448 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -53,6 +53,12 @@ struct intel_pxp {
struct pxp_context ctx;
};
+static inline int pxp_session_max(int session_type)
+{
+ return (session_type == SESSION_TYPE_TYPE0) ?
+ PXP_MAX_NORMAL_TYPE0_SESSIONS : PXP_MAX_TYPE1_SESSIONS;
+}
+
struct drm_i915_private;
#ifdef CONFIG_DRM_I915_PXP
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
index 17ff6bd61d20..3a4c8022a5d0 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
@@ -7,6 +7,7 @@
#include "i915_drv.h"
#include "gt/intel_context.h"
#include "gt/intel_engine_pm.h"
+#include "intel_pxp_sm.h"
/* PXP GPU command definitions */
@@ -270,3 +271,58 @@ int intel_pxp_cmd_add_inline_termination(u32 *cmd)
increased_size_in_dw = (cmd_termin - cmd);
return increased_size_in_dw;
}
+
+int intel_pxp_cmd_terminate_all_hw_session(struct intel_pxp *pxp,
+ int session_type)
+{
+ u32 *cmd = NULL;
+ u32 *cmd_ptr = NULL;
+ int cmd_size_in_dw = 0;
+ int ret;
+ int idx;
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+
+ /* Calculate how many bytes need to be alloc */
+ for (idx = 0; idx < pxp_session_max(session_type); idx++) {
+ if (intel_pxp_sm_is_hw_session_in_play(pxp, session_type, idx))
{
+ cmd_size_in_dw += intel_pxp_cmd_add_prolog(pxp, NULL,
session_type, idx);
+ cmd_size_in_dw +=
intel_pxp_cmd_add_inline_termination(NULL);
+ }
+ }
+ cmd_size_in_dw += intel_pxp_cmd_add_epilog(NULL);
+
+ cmd = kzalloc(cmd_size_in_dw * 4, GFP_KERNEL);
+ if (!cmd)
+ return -ENOMEM;
+
+ /* Program the command */
+ cmd_ptr = cmd;
+ for (idx = 0; idx < pxp_session_max(session_type); idx++) {
+ if (intel_pxp_sm_is_hw_session_in_play(pxp, session_type, idx))
{
+ cmd_ptr += intel_pxp_cmd_add_prolog(pxp, cmd_ptr,
session_type, idx);
+ cmd_ptr +=
intel_pxp_cmd_add_inline_termination(cmd_ptr);
+ }
+ }
+ cmd_ptr += intel_pxp_cmd_add_epilog(cmd_ptr);
+
+ if
[Intel-gfx] [RFC-v6 10/21] mei: pxp: export pavp client to me client bus
From: Vitaly Lubart
Export PAVP client to work with i915_cp driver,
for binding it uses kernel component framework.
Signed-off-by: Vitaly Lubart
Signed-off-by: Tomas Winkler
---
drivers/misc/mei/Kconfig | 2 +
drivers/misc/mei/Makefile | 1 +
drivers/misc/mei/pxp/Kconfig | 13 ++
drivers/misc/mei/pxp/Makefile | 7 +
drivers/misc/mei/pxp/mei_pxp.c | 230 +
drivers/misc/mei/pxp/mei_pxp.h | 18 +++
6 files changed, 271 insertions(+)
create mode 100644 drivers/misc/mei/pxp/Kconfig
create mode 100644 drivers/misc/mei/pxp/Makefile
create mode 100644 drivers/misc/mei/pxp/mei_pxp.c
create mode 100644 drivers/misc/mei/pxp/mei_pxp.h
diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig
index f5fd5b786607..0e0bcd0da852 100644
--- a/drivers/misc/mei/Kconfig
+++ b/drivers/misc/mei/Kconfig
@@ -47,3 +47,5 @@ config INTEL_MEI_TXE
Intel Bay Trail
source "drivers/misc/mei/hdcp/Kconfig"
+source "drivers/misc/mei/pxp/Kconfig"
+
diff --git a/drivers/misc/mei/Makefile b/drivers/misc/mei/Makefile
index f1c76f7ee804..d8e5165917f2 100644
--- a/drivers/misc/mei/Makefile
+++ b/drivers/misc/mei/Makefile
@@ -26,3 +26,4 @@ mei-$(CONFIG_EVENT_TRACING) += mei-trace.o
CFLAGS_mei-trace.o = -I$(src)
obj-$(CONFIG_INTEL_MEI_HDCP) += hdcp/
+obj-$(CONFIG_INTEL_MEI_PXP) += pxp/
diff --git a/drivers/misc/mei/pxp/Kconfig b/drivers/misc/mei/pxp/Kconfig
new file mode 100644
index ..4029b96afc04
--- /dev/null
+++ b/drivers/misc/mei/pxp/Kconfig
@@ -0,0 +1,13 @@
+
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
+#
+config INTEL_MEI_PXP
+ tristate "Intel PXP services of ME Interface"
+ select INTEL_MEI_ME
+ depends on DRM_I915
+ help
+ MEI Support for PXP Services on Intel platforms.
+
+ Enables the ME FW services required for PXP support through
+ I915 display driver of Intel.
diff --git a/drivers/misc/mei/pxp/Makefile b/drivers/misc/mei/pxp/Makefile
new file mode 100644
index ..0329950d5794
--- /dev/null
+++ b/drivers/misc/mei/pxp/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
+#
+# Makefile - PXP client driver for Intel MEI Bus Driver.
+
+obj-$(CONFIG_INTEL_MEI_PXP) += mei_pxp.o
diff --git a/drivers/misc/mei/pxp/mei_pxp.c b/drivers/misc/mei/pxp/mei_pxp.c
new file mode 100644
index ..5bd61fe445e3
--- /dev/null
+++ b/drivers/misc/mei/pxp/mei_pxp.c
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+/**
+ * DOC: MEI_PXP Client Driver
+ *
+ * The mei_pxp driver acts as a translation layer between PXP
+ * protocol implementer (I915) and ME FW by translating PXP
+ * negotiation messages to ME FW command payloads and vice versa.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "mei_pxp.h"
+
+/**
+ * mei_pxp_send_message() - Sends a PXP message to ME FW.
+ * @dev: device corresponding to the mei_cl_device
+ * @message: a message buffer to send
+ * @size: size of the message
+ * Return: 0 on Success, <0 on Failure
+ */
+static int
+mei_pxp_send_message(struct device *dev, const void *message, size_t size)
+{
+ struct mei_cl_device *cldev;
+ ssize_t byte;
+
+ if (!dev || !message)
+ return -EINVAL;
+
+ cldev = to_mei_cl_device(dev);
+
+ /* temporary drop const qualifier till the API is fixed */
+ byte = mei_cldev_send(cldev, (u8 *)message, size);
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte);
+ return byte;
+ }
+
+ return 0;
+}
+
+/**
+ * mei_pxp_receive_message() - Receives a PXP message from ME FW.
+ * @dev: device corresponding to the mei_cl_device
+ * @buffer: a message buffer to contain the received message
+ * @size: size of the buffer
+ * Return: bytes sent on Success, <0 on Failure
+ */
+static int
+mei_pxp_receive_message(struct device *dev, void *buffer, size_t size)
+{
+ struct mei_cl_device *cldev;
+ ssize_t byte;
+
+ if (!dev || !buffer)
+ return -EINVAL;
+
+ cldev = to_mei_cl_device(dev);
+
+ byte = mei_cldev_recv(cldev, buffer, size);
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte);
+ return byte;
+ }
+
+ return byte;
+}
+
+static const struct i915_pxp_component_ops mei_pxp_ops = {
+ .owner = THIS_MODULE,
+ .send = mei_pxp_send_message,
+ .receive = mei_pxp_receive_message,
+};
+
+static int mei_component_master_bind(struct device *dev)
+{
+ struct mei_cl_device *cldev = to_mei_cl_device(dev);
+ struct i915_pxp_comp_master *comp_master = mei_cldev_get_drvdata(cldev);
+ int ret;
+
+ dev_dbg(dev, "%s\n", __func__);
+ comp_master->ops = _pxp_ops;
+
[Intel-gfx] [RFC-v6 17/21] drm/i915/pxp: Implement ioctl action to send TEE commands
Implement the ioctl action to allow userspace driver sends TEE
commands via PXP ioctl, instead of TEE iotcl. So we can
centralize those protection operations at PXP.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 48 +---
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 57
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 5 +++
3 files changed, 105 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index c35011b84f5a..2445af5f763c 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -16,7 +16,10 @@
/* Setting KCR Init bit is required after system boot */
#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) <<
KCR_INIT_MASK_SHIFT))
-#define PXP_ACTION_SET_SESSION_STATUS 1
+enum pxp_ioctl_action {
+ PXP_ACTION_SET_SESSION_STATUS = 1,
+ PXP_ACTION_TEE_IO_MESSAGE = 4,
+};
enum pxp_session_req {
/* Request KMD to allocate session id and move it to IN INIT */
@@ -38,13 +41,28 @@ struct pxp_set_session_status_params {
u32 req_session_state; /* in, new session state */
};
+/*
+ * struct pxp_tee_io_message_params - Params to send/receive message to/from
TEE.
+ */
+struct pxp_tee_io_message_params {
+ u8 __user *msg_in; /* in - message input */
+ u32 msg_in_size; /* in - message input size */
+ u8 __user *msg_out; /* in - message output buffer */
+ u32 msg_out_size; /* out- message output size from TEE */
+ u32 msg_out_buf_size; /* in - message output buffer size */
+};
+
/* struct pxp_info - Params for PXP operation. */
struct pxp_info {
u32 action; /* in - specified action of this operation */
u32 sm_status; /* out - status output for this operation */
- /* in - action params to set the PXP session state */
- struct pxp_set_session_status_params set_session_status;
+ union {
+ /* in - action params to set the PXP session state */
+ struct pxp_set_session_status_params set_session_status;
+ /* in - action params to send TEE commands */
+ struct pxp_tee_io_message_params tee_io_message;
+ };
} __attribute__((packed));
struct drm_i915_pxp_ops {
@@ -228,7 +246,9 @@ int i915_pxp_ops_ioctl(struct drm_device *dev, void *data,
struct drm_file *drmf
goto end;
}
- if (pxp_info.action == PXP_ACTION_SET_SESSION_STATUS) {
+ switch (pxp_info.action) {
+ case PXP_ACTION_SET_SESSION_STATUS:
+ {
struct pxp_set_session_status_params *params =
_info.set_session_status;
if (params->req_session_state == PXP_REQ_SESSION_ID_INIT) {
@@ -250,8 +270,26 @@ int i915_pxp_ops_ioctl(struct drm_device *dev, void *data,
struct drm_file *drmf
} else {
ret = -EINVAL;
}
- } else {
+ break;
+ }
+ case PXP_ACTION_TEE_IO_MESSAGE:
+ {
+ struct pxp_tee_io_message_params *params =
_info.tee_io_message;
+
+ ret = intel_pxp_tee_ioctl_io_message(pxp,
+params->msg_in,
params->msg_in_size,
+params->msg_out,
>msg_out_size,
+params->msg_out_buf_size);
+ if (ret) {
+ drm_err(>drm, "Failed to send TEE IO message\n");
+ ret = -EFAULT;
+ }
+ break;
+ }
+ default:
+ drm_err(>drm, "Failed to %s due to bad params\n",
__func__);
ret = -EINVAL;
+ break;
}
end:
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
index 816a6d5a54e4..e0815b2ee9ab 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -168,3 +168,60 @@ int intel_pxp_tee_cmd_create_arb_session(struct intel_pxp
*pxp)
return ret;
}
+
+int intel_pxp_tee_ioctl_io_message(struct intel_pxp *pxp,
+ void __user *msg_in_user_ptr, u32
msg_in_size,
+ void __user *msg_out_user_ptr, u32
*msg_out_size_ptr,
+ u32 msg_out_buf_size)
+{
+ int ret;
+ void *msg_in = NULL;
+ void *msg_out = NULL;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+ struct drm_i915_private *i915 = gt->i915;
+
+ if (!msg_in_user_ptr || !msg_out_user_ptr || msg_out_buf_size == 0 ||
+ msg_in_size == 0 || !msg_out_size_ptr)
+ return -EINVAL;
+
+ msg_in = kzalloc(msg_in_size, GFP_KERNEL);
+ if (!msg_in)
+ return -ENOMEM;
+
+ msg_out = kzalloc(msg_out_buf_size, GFP_KERNEL);
+ if
[Intel-gfx] [RFC-v6 20/21] drm/i915/pxp: Add PXP-related registers into allowlist
Add several PXP-related reg into allowlist to allow user space
driver to read the those register values.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/i915_reg.h | 6
drivers/gpu/drm/i915/intel_uncore.c | 50 -
2 files changed, 41 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0ea7e2a402ae..bcb7eb7a0e3c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -12425,4 +12425,10 @@ enum skl_power_gate {
#define TGL_ROOT_DEVICE_SKU_ULX0x2
#define TGL_ROOT_DEVICE_SKU_ULT0x4
+/* Registers for allowlist check */
+#define PXP_REG_01_LOWERBOUND _MMIO(0x32260)
+#define PXP_REG_01_UPPERBOUND _MMIO(0x32268)
+#define PXP_REG_02_LOWERBOUND _MMIO(0x32670)
+#define PXP_REG_02_UPPERBOUND _MMIO(0x32678)
+
#endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 9ac501bcfdad..dc97ec240571 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1990,16 +1990,34 @@ void intel_uncore_fini_mmio(struct intel_uncore *uncore)
}
static const struct reg_whitelist {
- i915_reg_t offset_ldw;
+ i915_reg_t offset_ldw_lowerbound;
+ i915_reg_t offset_ldw_upperbound;
i915_reg_t offset_udw;
u16 gen_mask;
u8 size;
-} reg_read_whitelist[] = { {
- .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
+} reg_read_whitelist[] = {
+ {
+ .offset_ldw_lowerbound = RING_TIMESTAMP(RENDER_RING_BASE),
+ .offset_ldw_upperbound = RING_TIMESTAMP(RENDER_RING_BASE),
.offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
.gen_mask = INTEL_GEN_MASK(4, 12),
.size = 8
-} };
+ },
+ {
+ .offset_ldw_lowerbound = PXP_REG_01_LOWERBOUND,
+ .offset_ldw_upperbound = PXP_REG_01_UPPERBOUND,
+ .offset_udw = {0},
+ .gen_mask = INTEL_GEN_MASK(4, 12),
+ .size = 4
+ },
+ {
+ .offset_ldw_lowerbound = PXP_REG_02_LOWERBOUND,
+ .offset_ldw_upperbound = PXP_REG_02_UPPERBOUND,
+ .offset_udw = {0},
+ .gen_mask = INTEL_GEN_MASK(4, 12),
+ .size = 4
+ }
+};
int i915_reg_read_ioctl(struct drm_device *dev,
void *data, struct drm_file *file)
@@ -2012,18 +2030,22 @@ int i915_reg_read_ioctl(struct drm_device *dev,
unsigned int flags;
int remain;
int ret = 0;
+ i915_reg_t offset_ldw;
entry = reg_read_whitelist;
remain = ARRAY_SIZE(reg_read_whitelist);
while (remain) {
- u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw);
+ u32 entry_offset_lb =
i915_mmio_reg_offset(entry->offset_ldw_lowerbound);
+ u32 entry_offset_ub =
i915_mmio_reg_offset(entry->offset_ldw_upperbound);
GEM_BUG_ON(!is_power_of_2(entry->size));
GEM_BUG_ON(entry->size > 8);
- GEM_BUG_ON(entry_offset & (entry->size - 1));
+ GEM_BUG_ON(entry_offset_lb & (entry->size - 1));
+ GEM_BUG_ON(entry_offset_ub & (entry->size - 1));
if (INTEL_INFO(i915)->gen_mask & entry->gen_mask &&
- entry_offset == (reg->offset & -entry->size))
+ entry_offset_lb <= (reg->offset & -entry->size) &&
+ (reg->offset & -entry->size) <= entry_offset_ub)
break;
entry++;
remain--;
@@ -2033,23 +2055,21 @@ int i915_reg_read_ioctl(struct drm_device *dev,
return -EINVAL;
flags = reg->offset & (entry->size - 1);
+ offset_ldw = _MMIO(reg->offset - flags);
with_intel_runtime_pm(>runtime_pm, wakeref) {
if (entry->size == 8 && flags == I915_REG_READ_8B_WA)
reg->val = intel_uncore_read64_2x32(uncore,
- entry->offset_ldw,
+ offset_ldw,
entry->offset_udw);
else if (entry->size == 8 && flags == 0)
- reg->val = intel_uncore_read64(uncore,
- entry->offset_ldw);
+ reg->val = intel_uncore_read64(uncore, offset_ldw);
else if (entry->size == 4 && flags == 0)
- reg->val = intel_uncore_read(uncore, entry->offset_ldw);
+ reg->val = intel_uncore_read(uncore, offset_ldw);
else if (entry->size == 2 && flags == 0)
- reg->val = intel_uncore_read16(uncore,
- entry->offset_ldw);
+ reg->val = intel_uncore_read16(uncore, offset_ldw);
[Intel-gfx] [RFC-v6 07/21] drm/i915/pxp: Destroy arb session upon teardown
Teardown is triggered when the display topology changes and no
long meets the secure playback requirement, and hardware trashes
all the encryption keys for display. So as a result, PXP should
handle such case and terminate the type0 sessions, which including
arb session
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 3 +
drivers/gpu/drm/i915/pxp/intel_pxp_arb.c | 76 +
drivers/gpu/drm/i915/pxp/intel_pxp_arb.h | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 129 ++-
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 12 ++-
5 files changed, 211 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 9bcb170b34f1..48e926363696 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -28,6 +28,9 @@ static int intel_pxp_teardown_required_callback(struct
intel_pxp *pxp)
mutex_lock(>ctx.mutex);
pxp->ctx.global_state_attacked = true;
+ pxp->ctx.flag_display_hm_surface_keys = false;
+
+ ret = intel_pxp_arb_terminate_session(pxp);
mutex_unlock(>ctx.mutex);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
index 9611cd53d3a4..d94b08fe9190 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
@@ -10,6 +10,7 @@
#include "intel_pxp.h"
#include "intel_pxp_context.h"
#include "intel_pxp_tee.h"
+#include "intel_pxp_cmd.h"
#define GEN12_KCR_SIP _MMIO(0x32260) /* KCR type0 session in play 0-31 */
@@ -132,3 +133,78 @@ int intel_pxp_arb_create_session(struct intel_pxp *pxp)
end:
return ret;
}
+
+static int intel_pxp_arb_session_with_global_termination(struct intel_pxp *pxp)
+{
+ u32 *cmd = NULL;
+ u32 *cmd_ptr = NULL;
+ int cmd_size_in_dw = 0;
+ int ret;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+
+ /* Calculate how many bytes need to be alloc */
+ cmd_size_in_dw += intel_pxp_cmd_add_prolog(pxp, NULL, ARB_SESSION_TYPE,
ARB_SESSION_INDEX);
+ cmd_size_in_dw += intel_pxp_cmd_add_inline_termination(NULL);
+ cmd_size_in_dw += intel_pxp_cmd_add_epilog(NULL);
+
+ cmd = kzalloc(cmd_size_in_dw * 4, GFP_KERNEL);
+ if (!cmd)
+ return -ENOMEM;
+
+ /* Program the command */
+ cmd_ptr = cmd;
+ cmd_ptr += intel_pxp_cmd_add_prolog(pxp, cmd_ptr, ARB_SESSION_TYPE,
ARB_SESSION_INDEX);
+ cmd_ptr += intel_pxp_cmd_add_inline_termination(cmd_ptr);
+ cmd_ptr += intel_pxp_cmd_add_epilog(cmd_ptr);
+
+ if (cmd_size_in_dw != (cmd_ptr - cmd)) {
+ ret = -EINVAL;
+ drm_err(>i915->drm, "Failed to %s\n", __func__);
+ goto end;
+ }
+
+ if (drm_debug_enabled(DRM_UT_DRIVER)) {
+ print_hex_dump(KERN_DEBUG, "global termination cmd binaries:",
+ DUMP_PREFIX_OFFSET, 4, 4, cmd, cmd_size_in_dw *
4, true);
+ }
+
+ ret = intel_pxp_cmd_submit(pxp, cmd, cmd_size_in_dw);
+ if (ret) {
+ drm_err(>i915->drm, "Failed to intel_pxp_cmd_submit()\n");
+ goto end;
+ }
+
+end:
+ kfree(cmd);
+ return ret;
+}
+
+/**
+ * intel_pxp_arb_terminate_session - Terminate the arb hw session and its
entries.
+ * @pxp: pointer to pxp struct.
+ *
+ * This function is NOT intended to be called from the ioctl, and need to be
protected by
+ * ctx.mutex to ensure no SIP change during the call.
+ *
+ * Return: status. 0 means terminate is successful.
+ */
+int intel_pxp_arb_terminate_session(struct intel_pxp *pxp)
+{
+ int ret;
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+ struct pxp_protected_session *arb = >ctx.arb_session;
+
+ lockdep_assert_held(>ctx.mutex);
+
+ /* terminate the hw sessions */
+ ret = intel_pxp_arb_session_with_global_termination(pxp);
+ if (ret) {
+ drm_err(>i915->drm, "Failed to
intel_pxp_arb_session_with_global_termination\n");
+ return ret;
+ }
+
+ arb->is_in_play = false;
+
+ return ret;
+}
+
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
index c6a6000f5be5..d4e33ac7c2bd 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
@@ -34,5 +34,6 @@ struct pxp_protected_session {
};
int intel_pxp_arb_create_session(struct intel_pxp *pxp);
+int intel_pxp_arb_terminate_session(struct intel_pxp *pxp);
#endif /* __INTEL_PXP_ARB_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
index e531ea9f3cdc..079024d5f063 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
@@ -8,10 +8,29 @@
#include "gt/intel_context.h"
#include "gt/intel_engine_pm.h"
-struct
[Intel-gfx] [RFC-v6 01/21] drm/i915/pxp: Introduce Intel PXP component
PXP (Protected Xe Path) is an i915 componment, available on GEN12+,
that helps to establish the hardware protected session and manage
the status of the alive software session, as well as its life cycle.
This patch series is to allow the kernel space to create and
manage a single hardware session (a.k.a default session or
arbitrary session). So Mesa can allocate the protected buffer,
which is encrypted with the leverage of the arbitrary hardware
session.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Kconfig | 19 +
drivers/gpu/drm/i915/Makefile| 5
drivers/gpu/drm/i915/gt/intel_gt.c | 7 +
drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 ++
drivers/gpu/drm/i915/pxp/intel_pxp.c | 27 ++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 29
drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 27 ++
drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 22 +++
8 files changed, 139 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.h
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 1e1cb245fca7..a42b9b031455 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -130,6 +130,25 @@ config DRM_I915_GVT_KVMGT
Choose this option if you want to enable KVMGT support for
Intel GVT-g.
+config DRM_I915_PXP
+ bool "Enable Intel PXP support for Intel Gen12+ platform"
+ depends on DRM_I915
+ select INTEL_MEI_PXP
+ default n
+ help
+ This option selects INTEL_MEI_ME if it isn't already selected to
+ enabled full PXP Services on Intel platforms.
+
+ PXP (Protected Xe Path) is an i915 componment, available on GEN12+,
+ that helps to establish the hardware protected session and manage
+ the status of the alive software session, as well as its life cycle.
+
+ This patch series is to allow the kernel space to create and
+ manage a single hardware session (a.k.a default session or
+ arbitrary session). So Mesa can allocate the protected buffer,
+ which is encrypted with the leverage of the arbitrary hardware
+ session.
+
menu "drm/i915 Debugging"
depends on DRM_I915
depends on EXPERT
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index e5574e506a5c..99efac469cc2 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -254,6 +254,11 @@ i915-y += \
i915-y += i915_perf.o
+# Protected execution platform (PXP) support
+i915-$(CONFIG_DRM_I915_PXP) += \
+ pxp/intel_pxp.o \
+ pxp/intel_pxp_context.o
+
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
i915-$(CONFIG_DRM_I915_SELFTEST) += \
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 44f1d51e5ae5..d8e20ede7326 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -584,6 +584,12 @@ int intel_gt_init(struct intel_gt *gt)
if (err)
goto err_gt;
+ if (INTEL_GEN(gt->i915) >= 12) {
+ err = intel_pxp_init(>pxp);
+ if (err)
+ goto err_gt;
+ }
+
goto out_fw;
err_gt:
__intel_gt_disable(gt);
@@ -638,6 +644,7 @@ void intel_gt_driver_release(struct intel_gt *gt)
if (vm) /* FIXME being called twice on error paths :( */
i915_vm_put(vm);
+ intel_pxp_uninit(>pxp);
intel_gt_pm_fini(gt);
intel_gt_fini_scratch(gt);
intel_gt_fini_buffer_pool(gt);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 6d39a4a11bf3..05255632c2c0 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -23,6 +23,7 @@
#include "intel_rc6_types.h"
#include "intel_rps_types.h"
#include "intel_wakeref.h"
+#include "pxp/intel_pxp.h"
struct drm_i915_private;
struct i915_ggtt;
@@ -120,6 +121,8 @@ struct intel_gt {
/* Slice/subslice/EU info */
struct sseu_dev_info sseu;
} info;
+
+ struct intel_pxp pxp;
};
enum intel_gt_scratch_field {
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
new file mode 100644
index ..ba43b2c923c7
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+#include "i915_drv.h"
+#include "intel_pxp.h"
+#include "intel_pxp_context.h"
+
+int intel_pxp_init(struct intel_pxp *pxp)
+{
+ struct intel_gt *gt =
[Intel-gfx] [RFC-v6 21/21] drm/i915/pxp: Enable the PXP ioctl for protected session
In the previous commits, we have implemented the PXP ioctl
functions. Now we enable those handlers and expose them as PXP
ioctl, so allow the userspace driver can establish, set, or
destory the protected session via this ioctl.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 53
include/uapi/drm/i915_drm.h | 72
3 files changed, 73 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e74201e81369..201550ffb353 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1766,6 +1766,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl,
DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(I915_PXP_OPS, i915_pxp_ops_ioctl, DRM_RENDER_ALLOW),
};
static const struct drm_driver driver = {
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 789990b3a5e3..0c490fccdc71 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -31,59 +31,6 @@ enum pxp_session_req {
PXP_REQ_SESSION_TERMINATE
};
-/*
- * struct pxp_sm_query_pxp_tag - Params to query the PXP tag of specified
- * session id and whether the session is alive from PXP state machine.
- */
-struct pxp_sm_query_pxp_tag {
- u32 session_is_alive;
- u32 pxp_tag; /* in - Session ID, out pxp tag */
-};
-
-/*
- * struct pxp_set_session_status_params - Params to reserved, set or destroy
- * the session from the PXP state machine.
- */
-struct pxp_set_session_status_params {
- u32 pxp_tag; /* in [optional], out pxp tag */
- u32 session_type; /* in, session type */
- u32 session_mode; /* in, session mode */
- u32 req_session_state; /* in, new session state */
-};
-
-/*
- * struct pxp_tee_io_message_params - Params to send/receive message to/from
TEE.
- */
-struct pxp_tee_io_message_params {
- u8 __user *msg_in; /* in - message input */
- u32 msg_in_size; /* in - message input size */
- u8 __user *msg_out; /* in - message output buffer */
- u32 msg_out_size; /* out- message output size from TEE */
- u32 msg_out_buf_size; /* in - message output buffer size */
-};
-
-/* struct pxp_info - Params for PXP operation. */
-struct pxp_info {
- u32 action; /* in - specified action of this operation */
- u32 sm_status; /* out - status output for this operation */
-
- union {
- /* in - action params to query PXP tag */
- struct pxp_sm_query_pxp_tag query_pxp_tag;
- /* in - action params to set the PXP session state */
- struct pxp_set_session_status_params set_session_status;
- /* in - action params to send TEE commands */
- struct pxp_tee_io_message_params tee_io_message;
- };
-} __attribute__((packed));
-
-struct drm_i915_pxp_ops {
- /* in - user space pointer to struct pxp_info */
- struct pxp_info __user *info_ptr;
- /* in - memory size that info_ptr points to */
- u32 info_size;
-};
-
static void intel_pxp_write_irq_mask_reg(struct intel_gt *gt, u32 mask)
{
lockdep_assert_held(>irq_lock);
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index d6085a328b2c..17cf25bdc3c4 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -359,6 +359,7 @@ typedef struct _drm_i915_sarea {
#define DRM_I915_QUERY 0x39
#define DRM_I915_GEM_VM_CREATE 0x3a
#define DRM_I915_GEM_VM_DESTROY0x3b
+#define DRM_I915_PXP_OPS 0x3c
/* Must be kept compact -- no holes */
#define DRM_IOCTL_I915_INITDRM_IOW( DRM_COMMAND_BASE +
DRM_I915_INIT, drm_i915_init_t)
@@ -423,6 +424,7 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_QUERY, struct drm_i915_query)
#define DRM_IOCTL_I915_GEM_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control)
#define DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW (DRM_COMMAND_BASE +
DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control)
+#define DRM_IOCTL_I915_PXP_OPS DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_PXP_OPS, struct drm_i915_pxp_ops)
/* Allow drivers to submit batchbuffers directly to hardware, relying
* on the security mechanisms provided by hardware.
@@ -1964,6 +1966,76 @@ struct drm_i915_gem_vm_control {
__u32 vm_id;
};
+/*
+ * struct pxp_sm_query_pxp_tag - Params to query the PXP tag of specified
+ * session id and whether the session is alive from PXP state machine.
+ */
[Intel-gfx] [RFC-v6 05/21] drm/i915/pxp: Func to send hardware session termination
Implement the functions to allow PXP to send a GPU command, in
order to terminate the hardware session, so hardware can recycle
this session slot for the next usage.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 156 +++
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 18 +++
3 files changed, 175 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 0710cc522f38..2da904cda49f 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -258,6 +258,7 @@ i915-y += i915_perf.o
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
pxp/intel_pxp_arb.o \
+ pxp/intel_pxp_cmd.o \
pxp/intel_pxp_context.o \
pxp/intel_pxp_tee.o
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
new file mode 100644
index ..e531ea9f3cdc
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#include "intel_pxp_cmd.h"
+#include "i915_drv.h"
+#include "gt/intel_context.h"
+#include "gt/intel_engine_pm.h"
+
+struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp,
+struct intel_context *ce,
+struct intel_gt_buffer_pool_node *pool,
+u32 *cmd_buf, int cmd_size_in_dw)
+{
+ struct i915_vma *batch = ERR_PTR(-EINVAL);
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+ u32 *cmd;
+
+ if (!ce || !ce->engine || !cmd_buf)
+ return ERR_PTR(-EINVAL);
+
+ if (cmd_size_in_dw * 4 > PAGE_SIZE) {
+ drm_err(>i915->drm, "Failed to %s, invalid
cmd_size_id_dw=[%d]\n",
+ __func__, cmd_size_in_dw);
+ return ERR_PTR(-EINVAL);
+ }
+
+ cmd = i915_gem_object_pin_map(pool->obj, I915_MAP_FORCE_WC);
+ if (IS_ERR(cmd)) {
+ drm_err(>i915->drm, "Failed to
i915_gem_object_pin_map()\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ memcpy(cmd, cmd_buf, cmd_size_in_dw * 4);
+
+ if (drm_debug_enabled(DRM_UT_DRIVER)) {
+ print_hex_dump(KERN_DEBUG, "cmd binaries:",
+ DUMP_PREFIX_OFFSET, 4, 4, cmd, cmd_size_in_dw *
4, true);
+ }
+
+ i915_gem_object_unpin_map(pool->obj);
+
+ batch = i915_vma_instance(pool->obj, ce->vm, NULL);
+ if (IS_ERR(batch)) {
+ drm_err(>i915->drm, "Failed to i915_vma_instance()\n");
+ return batch;
+ }
+
+ return batch;
+}
+
+int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int cmd_size_in_dw)
+{
+ int err = -EINVAL;
+ struct i915_vma *batch;
+ struct i915_request *rq;
+ struct intel_context *ce = NULL;
+ bool is_engine_pm_get = false;
+ bool is_batch_vma_pin = false;
+ bool is_skip_req_on_err = false;
+ bool is_engine_get_pool = false;
+ struct intel_gt_buffer_pool_node *pool = NULL;
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+
+ if (!HAS_ENGINE(gt, VCS0) ||
+ !gt->engine[VCS0]->kernel_context) {
+ err = -EINVAL;
+ goto end;
+ }
+
+ if (!cmd || (cmd_size_in_dw * 4) > PAGE_SIZE) {
+ drm_err(>i915->drm, "Failed to %s bad params\n", __func__);
+ return -EINVAL;
+ }
+
+ ce = gt->engine[VCS0]->kernel_context;
+
+ intel_engine_pm_get(ce->engine);
+ is_engine_pm_get = true;
+
+ pool = intel_gt_get_buffer_pool(gt, PAGE_SIZE);
+ if (IS_ERR(pool)) {
+ drm_err(>i915->drm, "Failed to intel_engine_get_pool()\n");
+ goto end;
+ }
+ is_engine_get_pool = true;
+
+ batch = intel_pxp_cmd_get_batch(pxp, ce, pool, cmd, cmd_size_in_dw);
+ if (IS_ERR(batch)) {
+ drm_err(>i915->drm, "Failed to
intel_pxp_cmd_get_batch()\n");
+ goto end;
+ }
+
+ err = i915_vma_pin(batch, 0, 0, PIN_USER);
+ if (err) {
+ drm_err(>i915->drm, "Failed to i915_vma_pin()\n");
+ goto end;
+ }
+ is_batch_vma_pin = true;
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq)) {
+ drm_err(>i915->drm, "Failed to
intel_context_create_request()\n");
+ goto end;
+ }
+ is_skip_req_on_err = true;
+
+ err = intel_gt_buffer_pool_mark_active(pool, rq);
+ if (err) {
+ drm_err(>i915->drm, "Failed to
intel_engine_pool_mark_active()\n");
+ goto end;
+ }
+
+
[Intel-gfx] [RFC-v6 14/21] drm/i915/pxp: Implement ioctl action to reserve session slots
With this ioctl action, userspace driver can reserve one or
multiple session slot/id assigned by kernel PXP, as the first
step of PXP session establishment flow. The session info is
stored in the session list structure.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 91 +
drivers/gpu/drm/i915/pxp/intel_pxp.h | 22 +++
drivers/gpu/drm/i915/pxp/intel_pxp_arb.c | 2 -
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 3 -
drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 3 +
drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 3 +
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 194 +++
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 43
9 files changed, 357 insertions(+), 5 deletions(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 2545b59fa4f2..c96c5ed48e51 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -261,6 +261,7 @@ i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp_cmd.o \
pxp/intel_pxp_context.o \
pxp/intel_pxp_pm.o \
+ pxp/intel_pxp_sm.o \
pxp/intel_pxp_tee.o
# Post-mortem debug and GPU hang state capture
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index ce3760206b76..e294134fef78 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -7,6 +7,7 @@
#include "intel_pxp_context.h"
#include "intel_pxp_tee.h"
#include "intel_pxp_arb.h"
+#include "intel_pxp_sm.h"
/* KCR register definitions */
#define KCR_INIT_MMIO(0x320f0)
@@ -14,6 +15,36 @@
/* Setting KCR Init bit is required after system boot */
#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) <<
KCR_INIT_MASK_SHIFT))
+#define PXP_ACTION_SET_SESSION_STATUS 1
+#define PXP_REQ_SESSION_ID_INIT 0
+
+/*
+ * struct pxp_set_session_status_params - Params to reserved, set or destroy
+ * the session from the PXP state machine.
+ */
+struct pxp_set_session_status_params {
+ u32 pxp_tag; /* in [optional], out pxp tag */
+ u32 session_type; /* in, session type */
+ u32 session_mode; /* in, session mode */
+ u32 req_session_state; /* in, new session state */
+};
+
+/* struct pxp_info - Params for PXP operation. */
+struct pxp_info {
+ u32 action; /* in - specified action of this operation */
+ u32 sm_status; /* out - status output for this operation */
+
+ /* in - action params to set the PXP session state */
+ struct pxp_set_session_status_params set_session_status;
+} __attribute__((packed));
+
+struct drm_i915_pxp_ops {
+ /* in - user space pointer to struct pxp_info */
+ struct pxp_info __user *info_ptr;
+ /* in - memory size that info_ptr points to */
+ u32 info_size;
+};
+
static void intel_pxp_write_irq_mask_reg(struct intel_gt *gt, u32 mask)
{
lockdep_assert_held(>irq_lock);
@@ -152,3 +183,63 @@ bool intel_pxp_gem_object_status(struct drm_i915_private
*i915)
else
return false;
}
+
+int i915_pxp_ops_ioctl(struct drm_device *dev, void *data, struct drm_file
*drmfile)
+{
+ int ret;
+ struct pxp_info pxp_info = {0};
+ struct drm_i915_pxp_ops *pxp_ops = data;
+ struct drm_i915_private *i915 = to_i915(dev);
+ struct intel_pxp *pxp = >gt.pxp;
+
+ if (pxp->ctx.id == 0 || !drmfile || !pxp_ops ||
+ pxp_ops->info_size != sizeof(pxp_info))
+ return -EINVAL;
+
+ if (copy_from_user(_info, pxp_ops->info_ptr, sizeof(pxp_info)) != 0)
+ return -EFAULT;
+
+ mutex_lock(>ctx.mutex);
+
+ if (pxp->ctx.global_state_in_suspend) {
+ drm_err(>drm, "Return failure due to state in suspend\n");
+ pxp_info.sm_status = PXP_SM_STATUS_SESSION_NOT_AVAILABLE;
+ ret = 0;
+ goto end;
+ }
+
+ if (pxp->ctx.global_state_attacked) {
+ drm_err(>drm, "Retry required due to state attacked\n");
+ pxp_info.sm_status = PXP_SM_STATUS_RETRY_REQUIRED;
+ ret = 0;
+ goto end;
+ }
+
+ if (pxp_info.action == PXP_ACTION_SET_SESSION_STATUS) {
+ struct pxp_set_session_status_params *params =
_info.set_session_status;
+
+ if (params->req_session_state == PXP_REQ_SESSION_ID_INIT) {
+ ret = intel_pxp_sm_ioctl_reserve_session(pxp, drmfile,
+
params->session_type,
+
params->session_mode,
+
>pxp_tag);
+ if (ret == PXP_SM_STATUS_RETRY_REQUIRED ||
+
[Intel-gfx] [RFC-v6 09/21] drm/i915/pxp: Expose session state for display protection flip
Implement the intel_pxp_gem_object_status() to allow i915 display
querying the current PXP session state. In the design, display
should not perform protection flip on the protected buffers if
there is no PXP session alive.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 9 +
drivers/gpu/drm/i915/pxp/intel_pxp.h | 8
2 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 48e926363696..ce3760206b76 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -143,3 +143,12 @@ void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
pxp->current_events |= events;
schedule_work(>irq_work);
}
+
+bool intel_pxp_gem_object_status(struct drm_i915_private *i915)
+{
+ if (i915->gt.pxp.ctx.id != 0 &&
+ i915->gt.pxp.ctx.flag_display_hm_surface_keys)
+ return true;
+ else
+ return false;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index ddcc3faa4ea3..027c0eb84a52 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -37,6 +37,8 @@ struct intel_pxp {
struct pxp_context ctx;
};
+struct drm_i915_private;
+
#ifdef CONFIG_DRM_I915_PXP
void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir);
int i915_pxp_teardown_required_callback(struct intel_pxp *pxp);
@@ -44,6 +46,7 @@ int i915_pxp_global_terminate_complete_callback(struct
intel_pxp *pxp);
int intel_pxp_init(struct intel_pxp *pxp);
void intel_pxp_uninit(struct intel_pxp *pxp);
+bool intel_pxp_gem_object_status(struct drm_i915_private *i915);
#else
static inline void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
{
@@ -67,6 +70,11 @@ static inline int intel_pxp_init(struct intel_pxp *pxp)
static inline void intel_pxp_uninit(struct intel_pxp *pxp)
{
}
+
+static inline bool intel_pxp_gem_object_status(struct drm_i915_private *i915)
+{
+ return false;
+}
#endif
#endif /* __INTEL_PXP_PM_H__ */
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC-v6 02/21] drm/i915/pxp: set KCR reg init during the boot time
Set the KCR init during the boot time, which is
required by hardware, to allow us doing further
protection operation such as sending commands to
GPU or TEE.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index ba43b2c923c7..c4815950567d 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -6,6 +6,12 @@
#include "intel_pxp.h"
#include "intel_pxp_context.h"
+/* KCR register definitions */
+#define KCR_INIT_MMIO(0x320f0)
+#define KCR_INIT_MASK_SHIFT (16)
+/* Setting KCR Init bit is required after system boot */
+#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) <<
KCR_INIT_MASK_SHIFT))
+
int intel_pxp_init(struct intel_pxp *pxp)
{
struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
@@ -16,6 +22,8 @@ int intel_pxp_init(struct intel_pxp *pxp)
intel_pxp_ctx_init(>ctx);
+ intel_uncore_write(gt->uncore, KCR_INIT,
KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
+
drm_info(>i915->drm, "Protected Xe Path (PXP) protected content
support initialized\n");
return 0;
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC-v6 00/21] Introduce Intel PXP component - Mesa single session
PXP (Protected Xe Path) is an i915 componment, available on GEN12+ that helps to establish the hardware protected session and manage the status of the alive software session, as well as its life cycle. [commit #1 - #13] This patch series is to allow the kernel space to create and manage a single hardware session (a.k.a default session or arbitrary session). So user can allocate the protected buffer, which is encrypted with the leverage of the arbitrary hardware session. [commit #14 - #21] This patch series exposes ioctl so allow userspace to create, set, and destroy one or multiple sessions. It will also provide the communication chanel to TEE (Trusted Execution Environment) for the protected hardware session creation. v2: - modification based on code reivew feedbacks received - passing pxp instead of i915 as funciton argument - remove dead code only for multi-session - move the pxp init call from i915_drv.c to intel_gt.c - reove the tautology naming v3: - rebase to latest drm-tip v4: - Append the split non-mesa patch sereis (commit #14 - #21) into this patch series v5: - include "intel_pxp.h" in intel_pxp_sm.h at commit #14 to fix the build problem. v6: - Fix the null pointer arb_session access bug in intel_pxp_arb.c in "04 [RFC-v5] drm/i915/pxp: Create the arbitrary session after boot" Anshuman Gupta (1): drm/i915/pxp: Add plane decryption support Bommu Krishnaiah (2): drm/i915/uapi: introduce drm_i915_gem_create_ext drm/i915/pxp: User interface for Protected buffer Huang, Sean Z (17): drm/i915/pxp: Introduce Intel PXP component drm/i915/pxp: set KCR reg init during the boot time drm/i915/pxp: Implement funcs to create the TEE channel drm/i915/pxp: Create the arbitrary session after boot drm/i915/pxp: Func to send hardware session termination drm/i915/pxp: Enable PXP irq worker and callback stub drm/i915/pxp: Destroy arb session upon teardown drm/i915/pxp: Enable PXP power management drm/i915/pxp: Expose session state for display protection flip drm/i915/pxp: Implement ioctl action to reserve session slots drm/i915/pxp: Implement ioctl action to set session in play drm/i915/pxp: Implement ioctl action to terminate the session drm/i915/pxp: Implement ioctl action to send TEE commands drm/i915/pxp: Implement ioctl action to query PXP tag drm/i915/pxp: Termiante the session upon app crash drm/i915/pxp: Add PXP-related registers into allowlist drm/i915/pxp: Enable the PXP ioctl for protected session Vitaly Lubart (1): mei: pxp: export pavp client to me client bus drivers/gpu/drm/i915/Kconfig | 19 + drivers/gpu/drm/i915/Makefile | 10 + drivers/gpu/drm/i915/display/intel_sprite.c | 21 +- drivers/gpu/drm/i915/gem/i915_gem_context.c | 15 +- drivers/gpu/drm/i915/gem/i915_gem_context.h | 10 + .../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +- .../gpu/drm/i915/gem/i915_gem_object_types.h | 5 + drivers/gpu/drm/i915/gt/intel_gt.c| 7 + drivers/gpu/drm/i915/gt/intel_gt_irq.c| 4 + drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 + drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 + drivers/gpu/drm/i915/i915_drv.c | 11 +- drivers/gpu/drm/i915/i915_drv.h | 6 + drivers/gpu/drm/i915/i915_gem.c | 63 ++- drivers/gpu/drm/i915/i915_reg.h | 10 +- drivers/gpu/drm/i915/intel_uncore.c | 50 +- drivers/gpu/drm/i915/pxp/intel_pxp.c | 284 ++ drivers/gpu/drm/i915/pxp/intel_pxp.h | 107 drivers/gpu/drm/i915/pxp/intel_pxp_arb.c | 208 drivers/gpu/drm/i915/pxp/intel_pxp_arb.h | 39 ++ drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 328 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 22 + drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 32 ++ drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 42 ++ drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 72 +++ drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 31 ++ drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 487 ++ drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 54 ++ drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 227 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 25 + drivers/misc/mei/Kconfig | 2 + drivers/misc/mei/Makefile | 1 + drivers/misc/mei/pxp/Kconfig | 13 + drivers/misc/mei/pxp/Makefile | 7 + drivers/misc/mei/pxp/mei_pxp.c| 230 + drivers/misc/mei/pxp/mei_pxp.h| 18 + include/drm/i915_component.h | 1 + include/drm/i915_pxp_tee_interface.h | 45 ++ include/uapi/drm/i915_drm.h | 138 + 39 files changed, 2626 insertions(+), 27 deletions(-) create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c create mode 100644
[Intel-gfx] [RFC-v6 19/21] drm/i915/pxp: Termiante the session upon app crash
PXP should terminate the hardware session and cleanup the software
state gracefully when the application has established the
protection session, but doesn't close the session correctly due to
some cases like application crash.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/i915_drv.c | 3 +++
drivers/gpu/drm/i915/pxp/intel_pxp.c| 15 +++
drivers/gpu/drm/i915/pxp/intel_pxp.h| 5 +
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 25 +
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 1 +
5 files changed, 49 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 3dbda949bf71..e74201e81369 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -69,6 +69,7 @@
#include "gt/intel_rc6.h"
#include "pxp/intel_pxp_pm.h"
+#include "pxp/intel_pxp.h"
#include "i915_debugfs.h"
#include "i915_drv.h"
@@ -1026,6 +1027,8 @@ static void i915_driver_postclose(struct drm_device *dev,
struct drm_file *file)
/* Catch up with all the deferred frees from "this" client */
i915_gem_flush_free_objects(to_i915(dev));
+
+ intel_pxp_close(&(to_i915(dev)->gt.pxp), file);
}
static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 46ad2ab229c1..789990b3a5e3 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -320,3 +320,18 @@ int i915_pxp_ops_ioctl(struct drm_device *dev, void *data,
struct drm_file *drmf
ret = -EFAULT;
return ret;
}
+
+void intel_pxp_close(struct intel_pxp *pxp, struct drm_file *drmfile)
+{
+ int ret;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+
+ if (!drmfile)
+ return;
+
+ mutex_lock(>ctx.mutex);
+ ret = intel_pxp_sm_close(pxp, drmfile);
+ if (ret)
+ drm_err(>i915->drm, "Failed to %s, ret=[%d]\n", __func__,
ret);
+ mutex_unlock(>ctx.mutex);
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 133e3df9b1f6..ffb460327315 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -64,6 +64,7 @@ int intel_pxp_init(struct intel_pxp *pxp);
void intel_pxp_uninit(struct intel_pxp *pxp);
bool intel_pxp_gem_object_status(struct drm_i915_private *i915);
int i915_pxp_ops_ioctl(struct drm_device *dev, void *data, struct drm_file
*drmfile);
+void intel_pxp_close(struct intel_pxp *pxp, struct drm_file *drmfile);
#else
static inline void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
{
@@ -97,6 +98,10 @@ static inline int i915_pxp_ops_ioctl(struct drm_device *dev,
void *data, struct
{
return 0;
}
+
+static inline void intel_pxp_close(struct intel_pxp *pxp, struct drm_file
*drmfile)
+{
+}
#endif
#endif /* __INTEL_PXP_PM_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index fd1dc1269c4e..fcf11c61bffb 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -460,3 +460,28 @@ int intel_pxp_sm_ioctl_query_pxp_tag(struct intel_pxp *pxp,
return 0;
}
+
+int intel_pxp_sm_close(struct intel_pxp *pxp, struct drm_file *drmfile)
+{
+ int ret;
+ struct intel_pxp_sm_session *curr;
+
+ list_for_each_entry(curr, session_list(pxp, SESSION_TYPE_TYPE0), list) {
+ if (curr->drmfile && curr->drmfile == drmfile &&
+ curr->pid == pid_nr(drmfile->pid)) {
+ ret = pxp_terminate_hw_session(pxp, curr->type,
+ curr->index);
+ if (ret)
+ return ret;
+
+ ret = pxp_set_pxp_tag(pxp, curr->type, curr->index,
+ PROTECTION_MODE_NONE);
+ if (ret)
+ return ret;
+
+ list_del(>list);
+ kfree(curr);
+ }
+ }
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
index 09a26bb7a1a4..d2acbd1298b4 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
@@ -50,4 +50,5 @@ int intel_pxp_sm_ioctl_query_pxp_tag(struct intel_pxp *pxp,
bool intel_pxp_sm_is_hw_session_in_play(struct intel_pxp *pxp,
int session_type, int session_index);
int intel_pxp_sm_terminate_all_sessions(struct intel_pxp *pxp, int
session_type);
+int intel_pxp_sm_close(struct intel_pxp *pxp, struct drm_file *drmfile);
#endif /* __INTEL_PXP_SM_H__ */
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
[Intel-gfx] [RFC-v6 13/21] drm/i915/pxp: Add plane decryption support
From: Anshuman Gupta
Add support to enable/disable PLANE_SURF Decryption Request bit.
It requires only to enable plane decryption support when following
condition met.
1. PAVP session is enabled.
2. Buffer object is protected.
v2:
- Rebased to libva_cp-drm-tip_tgl_cp tree.
- Used gen fb obj user_flags instead gem_object_metadata. [Krishna]
Cc: Bommu Krishnaiah
Cc: Huang, Sean Z
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_sprite.c | 21 ++---
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index b7e208816074..273bdc031e8d 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -39,6 +39,8 @@
#include
#include
+#include "pxp/intel_pxp.h"
+
#include "i915_drv.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
@@ -767,6 +769,11 @@ icl_program_input_csc(struct intel_plane *plane,
PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
}
+static bool intel_fb_obj_protected(const struct drm_i915_gem_object *obj)
+{
+ return obj->user_flags & I915_BO_PROTECTED ? true : false;
+}
+
static void
skl_plane_async_flip(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
@@ -803,6 +810,7 @@ skl_program_plane(struct intel_plane *plane,
u32 surf_addr = plane_state->color_plane[color_plane].offset;
u32 stride = skl_plane_stride(plane_state, color_plane);
const struct drm_framebuffer *fb = plane_state->hw.fb;
+ const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
int aux_plane = intel_main_to_aux_plane(fb, color_plane);
int crtc_x = plane_state->uapi.dst.x1;
int crtc_y = plane_state->uapi.dst.y1;
@@ -813,7 +821,7 @@ skl_program_plane(struct intel_plane *plane,
u8 alpha = plane_state->hw.alpha >> 8;
u32 plane_color_ctl = 0, aux_dist = 0;
unsigned long irqflags;
- u32 keymsk, keymax;
+ u32 keymsk, keymax, plane_surf;
u32 plane_ctl = plane_state->ctl;
plane_ctl |= skl_plane_ctl_crtc(crtc_state);
@@ -889,8 +897,15 @@ skl_program_plane(struct intel_plane *plane,
* the control register just before the surface register.
*/
intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
- intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
- intel_plane_ggtt_offset(plane_state) + surf_addr);
+ plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
+
+ if (intel_pxp_gem_object_status(dev_priv) &&
+ intel_fb_obj_protected(obj))
+ plane_surf |= PLANE_SURF_DECRYPTION_ENABLED;
+ else
+ plane_surf &= ~PLANE_SURF_DECRYPTION_ENABLED;
+
+ intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf);
if (plane_state->scaler_id >= 0)
skl_program_scaler(plane, crtc_state, plane_state);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1e8dfe435ca8..0ea7e2a402ae 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7209,6 +7209,7 @@ enum {
#define _PLANE_SURF_3(pipe)_PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
#define PLANE_SURF(pipe, plane)\
_MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
+#define PLANE_SURF_DECRYPTION_ENABLEDREG_BIT(2)
#define _PLANE_OFFSET_1_B 0x711a4
#define _PLANE_OFFSET_2_B 0x712a4
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC-v6 18/21] drm/i915/pxp: Implement ioctl action to query PXP tag
Enable the PXP ioctl action to allow userspace driver to query the
PXP tag, which is a 32-bit bitwise value indicating the current
session info, including protection type, session id, and whether
the session is enabled.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 20 +++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 6 -
drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 9 ++
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 130 ++-
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 2 +
5 files changed, 160 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 2445af5f763c..46ad2ab229c1 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -17,6 +17,7 @@
#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) <<
KCR_INIT_MASK_SHIFT))
enum pxp_ioctl_action {
+ PXP_ACTION_QUERY_PXP_TAG = 0,
PXP_ACTION_SET_SESSION_STATUS = 1,
PXP_ACTION_TEE_IO_MESSAGE = 4,
};
@@ -30,6 +31,15 @@ enum pxp_session_req {
PXP_REQ_SESSION_TERMINATE
};
+/*
+ * struct pxp_sm_query_pxp_tag - Params to query the PXP tag of specified
+ * session id and whether the session is alive from PXP state machine.
+ */
+struct pxp_sm_query_pxp_tag {
+ u32 session_is_alive;
+ u32 pxp_tag; /* in - Session ID, out pxp tag */
+};
+
/*
* struct pxp_set_session_status_params - Params to reserved, set or destroy
* the session from the PXP state machine.
@@ -58,6 +68,8 @@ struct pxp_info {
u32 sm_status; /* out - status output for this operation */
union {
+ /* in - action params to query PXP tag */
+ struct pxp_sm_query_pxp_tag query_pxp_tag;
/* in - action params to set the PXP session state */
struct pxp_set_session_status_params set_session_status;
/* in - action params to send TEE commands */
@@ -272,6 +284,14 @@ int i915_pxp_ops_ioctl(struct drm_device *dev, void *data,
struct drm_file *drmf
}
break;
}
+ case PXP_ACTION_QUERY_PXP_TAG:
+ {
+ struct pxp_sm_query_pxp_tag *params = _info.query_pxp_tag;
+
+ ret = intel_pxp_sm_ioctl_query_pxp_tag(pxp,
>session_is_alive,
+ >pxp_tag);
+ break;
+ }
case PXP_ACTION_TEE_IO_MESSAGE:
{
struct pxp_tee_io_message_params *params =
_info.tee_io_message;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index e68c035d8448..133e3df9b1f6 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -16,12 +16,6 @@
#define GEN12_KCR_SIP _MMIO(0x32260) /* KCR type0 session in play 0-31 */
-#define PXP_MAX_TYPE0_SESSIONS 16
-#define PXP_MAX_TYPE1_SESSIONS 6
-
-/* we need to reserve one type0 slot for arbitrary session */
-#define PXP_MAX_NORMAL_TYPE0_SESSIONS (PXP_MAX_TYPE0_SESSIONS - 1)
-
enum pxp_session_types {
SESSION_TYPE_TYPE0 = 0,
SESSION_TYPE_TYPE1 = 1,
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
index 4c583f831831..ad9e278f3fb2 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
@@ -9,6 +9,12 @@
#include
#include "intel_pxp_arb.h"
+#define PXP_MAX_TYPE0_SESSIONS 16
+#define PXP_MAX_TYPE1_SESSIONS 6
+
+/* we need to reserve one type0 slot for arbitrary session */
+#define PXP_MAX_NORMAL_TYPE0_SESSIONS (PXP_MAX_TYPE0_SESSIONS - 1)
+
/* struct pxp_context - Represents combined view of driver and logical HW
states. */
struct pxp_context {
/** @mutex: mutex to protect the pxp context */
@@ -20,6 +26,9 @@ struct pxp_context {
struct list_head type0_sessions;
struct list_head type1_sessions;
+ u32 type0_pxp_tag[PXP_MAX_NORMAL_TYPE0_SESSIONS];
+ u32 type1_pxp_tag[PXP_MAX_TYPE1_SESSIONS];
+
int id;
bool global_state_attacked;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index c18802010ef6..fd1dc1269c4e 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -16,6 +16,21 @@
#define SESSION_TYPE_MASK BIT(7)
#define SESSION_ID_MASK (BIT(7) - 1)
+struct pxp_tag {
+ union {
+ u32 value;
+ struct {
+ u32 session_id : 8;
+ u32 instance_id : 8;
+ u32 enable : 1;
+ u32 hm : 1;
+ u32 reserved_1 : 1;
+ u32 sm : 1;
+ u32 reserved_2 : 12;
+ };
+ };
+};
+
static inline struct list_head *session_list(struct intel_pxp *pxp,
[Intel-gfx] [RFC-v6 12/21] drm/i915/pxp: User interface for Protected buffer
From: Bommu Krishnaiah
This api allow user mode to create Protected buffer and context creation.
Signed-off-by: Bommu Krishnaiah
Cc: Telukuntla Sreedhar
Cc: Kondapally Kalyan
Cc: Gupta Anshuman
Cc: Huang Sean Z
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 15 ++--
drivers/gpu/drm/i915/gem/i915_gem_context.h | 10
.../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +-
.../gpu/drm/i915/gem/i915_gem_object_types.h | 5
drivers/gpu/drm/i915/i915_gem.c | 23 +++
include/uapi/drm/i915_drm.h | 19 +++
6 files changed, 67 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index a6299da64de4..dd5d24a13cb9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -2060,12 +2060,23 @@ static int ctx_setparam(struct drm_i915_file_private
*fpriv,
case I915_CONTEXT_PARAM_RECOVERABLE:
if (args->size)
ret = -EINVAL;
- else if (args->value)
- i915_gem_context_set_recoverable(ctx);
+ else if (args->value) {
+ if (!i915_gem_context_is_protected(ctx))
+ i915_gem_context_set_recoverable(ctx);
+ else
+ ret = -EPERM;
+ }
else
i915_gem_context_clear_recoverable(ctx);
break;
+ case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
+ if (args->size)
+ ret = -EINVAL;
+ else if (args->value)
+ i915_gem_context_set_protected(ctx);
+ break;
+
case I915_CONTEXT_PARAM_PRIORITY:
ret = set_priority(ctx, args);
break;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h
b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index a133f92bbedb..5897e7ca11a8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -70,6 +70,16 @@ static inline void i915_gem_context_set_recoverable(struct
i915_gem_context *ctx
set_bit(UCONTEXT_RECOVERABLE, >user_flags);
}
+static inline void i915_gem_context_set_protected(struct i915_gem_context *ctx)
+{
+ set_bit(UCONTEXT_PROTECTED, >user_flags);
+}
+
+static inline bool i915_gem_context_is_protected(struct i915_gem_context *ctx)
+{
+ return test_bit(UCONTEXT_PROTECTED, >user_flags);
+}
+
static inline void i915_gem_context_clear_recoverable(struct i915_gem_context
*ctx)
{
clear_bit(UCONTEXT_RECOVERABLE, >user_flags);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
index ae14ca24a11f..81ae94c2be86 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
@@ -135,7 +135,7 @@ struct i915_gem_context {
#define UCONTEXT_BANNABLE 2
#define UCONTEXT_RECOVERABLE 3
#define UCONTEXT_PERSISTENCE 4
-
+#define UCONTEXT_PROTECTED 5
/**
* @flags: small set of booleans
*/
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index e2d9b7e1e152..90ac955463f4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -161,6 +161,11 @@ struct drm_i915_gem_object {
} mmo;
I915_SELFTEST_DECLARE(struct list_head st_link);
+ /**
+* @user_flags: small set of booleans set by the user
+*/
+ unsigned long user_flags;
+#define I915_BO_PROTECTED BIT(0)
unsigned long flags;
#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 41698a823737..6a791fd24eaa 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -184,7 +184,8 @@ static int
i915_gem_create(struct drm_file *file,
struct intel_memory_region *mr,
u64 *size_p,
- u32 *handle_p)
+ u32 *handle_p,
+ u64 user_flags)
{
struct drm_i915_gem_object *obj;
u32 handle;
@@ -204,6 +205,8 @@ i915_gem_create(struct drm_file *file,
if (IS_ERR(obj))
return PTR_ERR(obj);
+ obj->user_flags = user_flags;
+
ret = drm_gem_handle_create(file, >base, );
/* drop reference from allocate - handle holds it now */
i915_gem_object_put(obj);
@@ -258,11 +261,12 @@ i915_gem_dumb_create(struct drm_file *file,
return i915_gem_create(file,
intel_memory_region_by_type(to_i915(dev),
[Intel-gfx] [RFC-v6 04/21] drm/i915/pxp: Create the arbitrary session after boot
Create the arbitrary session, with the fixed session id 0xf, after
system boot, for the case that application allocates the protected
buffer without establishing any protection session. Because the
hardware requires at least one alive session for protected buffer
creation. This arbitrary session needs to be re-created after
teardown or power event because hardware encryption key won't be
valid after such cases.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.h | 16 +++
drivers/gpu/drm/i915/pxp/intel_pxp_arb.c | 134 +++
drivers/gpu/drm/i915/pxp/intel_pxp_arb.h | 38 ++
drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 6 +
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 38 ++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 6 +
8 files changed, 240 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index c703dbd91158..0710cc522f38 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -257,6 +257,7 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
+ pxp/intel_pxp_arb.o \
pxp/intel_pxp_context.o \
pxp/intel_pxp_tee.o
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 4104dd89ca7f..67bdaeb79b40 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -6,6 +6,7 @@
#include "intel_pxp.h"
#include "intel_pxp_context.h"
#include "intel_pxp_tee.h"
+#include "intel_pxp_arb.h"
/* KCR register definitions */
#define KCR_INIT_MMIO(0x320f0)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 7c3d49a6a3ab..1841a9aa972d 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -8,6 +8,22 @@
#include "intel_pxp_context.h"
+enum pxp_session_types {
+ SESSION_TYPE_TYPE0 = 0,
+ SESSION_TYPE_TYPE1 = 1,
+
+ SESSION_TYPE_MAX
+};
+
+enum pxp_protection_modes {
+ PROTECTION_MODE_NONE = 0,
+ PROTECTION_MODE_LM = 2,
+ PROTECTION_MODE_HM = 3,
+ PROTECTION_MODE_SM = 6,
+
+ PROTECTION_MODE_ALL
+};
+
struct intel_pxp {
struct pxp_context ctx;
};
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
new file mode 100644
index ..9611cd53d3a4
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#include "gt/intel_context.h"
+#include "gt/intel_engine_pm.h"
+
+#include "intel_pxp_arb.h"
+#include "intel_pxp.h"
+#include "intel_pxp_context.h"
+#include "intel_pxp_tee.h"
+
+#define GEN12_KCR_SIP _MMIO(0x32260) /* KCR type0 session in play 0-31 */
+
+/* Arbitrary session */
+#define ARB_SESSION_INDEX 0xf
+#define ARB_SESSION_TYPE SESSION_TYPE_TYPE0
+#define ARB_PROTECTION_MODE PROTECTION_MODE_HM
+
+static bool is_hw_arb_session_in_play(struct intel_pxp *pxp)
+{
+ u32 regval_sip = 0;
+ intel_wakeref_t wakeref;
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+
+ with_intel_runtime_pm(>i915->runtime_pm, wakeref) {
+ regval_sip = intel_uncore_read(gt->uncore, GEN12_KCR_SIP);
+ }
+
+ return regval_sip & BIT(ARB_SESSION_INDEX);
+}
+
+/* wait hw session_in_play reg to match the current sw state */
+static int wait_arb_hw_sw_state(struct intel_pxp *pxp)
+{
+ const int max_retry = 10;
+ const int ms_delay = 10;
+ int retry = 0;
+ int ret;
+ struct pxp_protected_session *arb = >ctx.arb_session;
+
+ ret = -EINVAL;
+ for (retry = 0; retry < max_retry; retry++) {
+ if (is_hw_arb_session_in_play(pxp) ==
+ arb->is_in_play) {
+ ret = 0;
+ break;
+ }
+
+ msleep(ms_delay);
+ }
+
+ return ret;
+}
+
+static void arb_session_entry_init(struct intel_pxp *pxp)
+{
+ struct pxp_protected_session *arb = >ctx.arb_session;
+
+ arb->context_id = pxp->ctx.id;
+ arb->type = ARB_SESSION_TYPE;
+ arb->protection_mode = ARB_PROTECTION_MODE;
+ arb->index = ARB_SESSION_INDEX;
+ arb->is_in_play = false;
+}
+
+int intel_pxp_arb_reserve_session(struct intel_pxp *pxp)
+{
+ int ret;
+
+ lockdep_assert_held(>ctx.mutex);
+
+ arb_session_entry_init(pxp);
+ ret = wait_arb_hw_sw_state(pxp);
+
+ return ret;
+}
+
+/**
+ * intel_pxp_arb_mark_session_in_play - To put an reserved protected session
to "in_play"
[Intel-gfx] [RFC-v6 11/21] drm/i915/uapi: introduce drm_i915_gem_create_ext
From: Bommu Krishnaiah
Same old gem_create but with now with extensions support. This is needed
to support various upcoming usecases. For now we use the extensions
mechanism to support PAVP.
Signed-off-by: Bommu Krishnaiah
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen joonas.lahti...@linux.intel.com
Cc: Matthew Auld matthew.a...@intel.com
Cc: Telukuntla Sreedhar
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 42 -
include/uapi/drm/i915_drm.h | 47 +
3 files changed, 89 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index af06c85e6ba7..3dbda949bf71 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1733,7 +1733,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop,
DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop,
DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
- DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl,
DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 58276694c848..41698a823737 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -53,6 +53,7 @@
#include "i915_drv.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
+#include "i915_user_extensions.h"
#include "intel_pm.h"
@@ -260,6 +261,35 @@ i915_gem_dumb_create(struct drm_file *file,
>size, >handle);
}
+struct create_ext {
+struct drm_i915_private *i915;
+};
+
+static int __create_setparam(struct drm_i915_gem_object_param *args,
+ struct create_ext
*ext_data)
+{
+ if (!(args->param & I915_OBJECT_PARAM)) {
+ DRM_DEBUG("Missing I915_OBJECT_PARAM namespace\n");
+ return -EINVAL;
+ }
+
+ return -EINVAL;
+}
+
+static int create_setparam(struct i915_user_extension __user *base, void *data)
+{
+ struct drm_i915_gem_create_ext_setparam ext;
+
+ if (copy_from_user(, base, sizeof(ext)))
+ return -EFAULT;
+
+ return __create_setparam(, data);
+}
+
+static const i915_user_extension_fn create_extensions[] = {
+ [I915_GEM_CREATE_EXT_SETPARAM] = create_setparam,
+};
+
/**
* Creates a new mm object and returns a handle to it.
* @dev: drm device pointer
@@ -271,10 +301,20 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
{
struct drm_i915_private *i915 = to_i915(dev);
- struct drm_i915_gem_create *args = data;
+ struct create_ext ext_data = { .i915 = i915 };
+ struct drm_i915_gem_create_ext *args = data;
+ int ret;
i915_gem_flush_free_objects(i915);
+ ret = i915_user_extensions(u64_to_user_ptr(args->extensions),
+ create_extensions,
+ ARRAY_SIZE(create_extensions),
+ _data);
+ if (ret)
+ return ret;
+
+
return i915_gem_create(file,
intel_memory_region_by_type(i915,
INTEL_MEMORY_SYSTEM),
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 6edcb2b6c708..e918ccc81c74 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -391,6 +391,7 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE +
DRM_I915_GEM_ENTERVT)
#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE +
DRM_I915_GEM_LEAVEVT)
#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
+#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext)
#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE +
DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE +
DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
#define DRM_IOCTL_I915_GEM_MMAPDRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
@@ -728,6 +729,27 @@ struct drm_i915_gem_create {
__u32 pad;
};
+struct drm_i915_gem_create_ext {
+ /**
+* Requested size for the object.
+*
+
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/gt: Split logical ring contexts from execlist submission (rev2)
== Series Details == Series: drm/i915/gt: Split logical ring contexts from execlist submission (rev2) URL : https://patchwork.freedesktop.org/series/84752/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/gt/intel_lrc.c:1: warning: 'Logical Rings, Logical Ring Contexts and Execlists' not found ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Add support for Intel's eDP backlight controls (rev4)
== Series Details == Series: drm/i915: Add support for Intel's eDP backlight controls (rev4) URL : https://patchwork.freedesktop.org/series/81702/ State : success == Summary == CI Bug Log - changes from CI_DRM_9472_full -> Patchwork_19113_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_19113_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_reloc@basic-wide-active@vcs1: - shard-iclb: NOTRUN -> [FAIL][1] ([i915#2389]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19113/shard-iclb2/igt@gem_exec_reloc@basic-wide-act...@vcs1.html * igt@gem_userptr_blits@process-exit-mmap@wb: - shard-skl: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1699]) +3 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19113/shard-skl6/igt@gem_userptr_blits@process-exit-m...@wb.html * igt@kms_ccs@pipe-c-crc-sprite-planes-basic: - shard-skl: NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111304]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19113/shard-skl10/igt@kms_...@pipe-c-crc-sprite-planes-basic.html * igt@kms_color@pipe-b-ctm-0-75: - shard-skl: [PASS][4] -> [DMESG-WARN][5] ([i915#1982]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9472/shard-skl7/igt@kms_co...@pipe-b-ctm-0-75.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19113/shard-skl5/igt@kms_co...@pipe-b-ctm-0-75.html * igt@kms_color_chamelium@pipe-d-ctm-0-5: - shard-skl: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +4 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19113/shard-skl5/igt@kms_color_chamel...@pipe-d-ctm-0-5.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-skl: [PASS][7] -> [INCOMPLETE][8] ([i915#2295] / [i915#300]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9472/shard-skl8/igt@kms_cursor_...@pipe-a-cursor-suspend.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19113/shard-skl8/igt@kms_cursor_...@pipe-a-cursor-suspend.html * igt@kms_cursor_crc@pipe-c-cursor-256x85-random: - shard-skl: [PASS][9] -> [FAIL][10] ([i915#54]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9472/shard-skl6/igt@kms_cursor_...@pipe-c-cursor-256x85-random.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19113/shard-skl5/igt@kms_cursor_...@pipe-c-cursor-256x85-random.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: - shard-hsw: [PASS][11] -> [FAIL][12] ([i915#96]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9472/shard-hsw7/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-legacy.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19113/shard-hsw1/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-legacy.html * igt@kms_flip@flip-vs-expired-vblank@c-dp1: - shard-apl: [PASS][13] -> [FAIL][14] ([i915#79]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9472/shard-apl6/igt@kms_flip@flip-vs-expired-vbl...@c-dp1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19113/shard-apl2/igt@kms_flip@flip-vs-expired-vbl...@c-dp1.html * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-pwrite: - shard-skl: NOTRUN -> [SKIP][15] ([fdo#109271]) +45 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19113/shard-skl2/igt@kms_frontbuffer_track...@fbc-2p-primscrn-pri-indfb-draw-pwrite.html * igt@kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][16] -> [FAIL][17] ([i915#1188]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9472/shard-skl7/igt@kms_...@bpc-switch-suspend.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19113/shard-skl7/igt@kms_...@bpc-switch-suspend.html * igt@kms_pipe_crc_basic@read-crc-pipe-d: - shard-skl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#533]) +1 similar issue [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19113/shard-skl2/igt@kms_pipe_crc_ba...@read-crc-pipe-d.html * igt@kms_psr@psr2_primary_mmap_cpu: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9472/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19113/shard-iclb6/igt@kms_psr@psr2_primary_mmap_cpu.html Possible fixes * igt@feature_discovery@psr2: - shard-iclb: [SKIP][21] ([i915#658]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9472/shard-iclb8/igt@feature_discov...@psr2.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19113/shard-iclb2/igt@feature_discov...@psr2.html *
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Split logical ring contexts from execlist submission (rev2)
== Series Details == Series: drm/i915/gt: Split logical ring contexts from execlist submission (rev2) URL : https://patchwork.freedesktop.org/series/84752/ State : warning == Summary == $ dim checkpatch origin/drm-tip 454579934182 drm/i915/gt: Split logical ring contexts from execlist submission -:1747: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #1747: new file mode 100644 -:1776: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'count' - possible side-effects? #1776: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:25: +#define LRI(count, flags) ((flags) << 6 | (count) | BUILD_BUG_ON_ZERO(count >= BIT(6))) -:1778: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'x' - possible side-effects? #1778: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:27: +#define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200)) -:1779: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #1779: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:28: +#define REG16(x) \ + (((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x1)), \ + (((x) >> 2) & 0x7f) -:1779: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'x' - possible side-effects? #1779: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:28: +#define REG16(x) \ + (((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x1)), \ + (((x) >> 2) & 0x7f) -:1782: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #1782: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:31: +#define END(total_state_size) 0, (total_state_size) -:2426: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #2426: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:675: + lrc_setup_indirect_ctx(regs, engine, + i915_ggtt_offset(wa_ctx->vma) + -:5754: WARNING:MEMORY_BARRIER: memory barrier without comment #5754: FILE: drivers/gpu/drm/i915/gt/selftest_lrc.c:638: + wmb(); -:5783: WARNING:MEMORY_BARRIER: memory barrier without comment #5783: FILE: drivers/gpu/drm/i915/gt/selftest_lrc.c:667: + wmb(); -:5915: WARNING:MEMORY_BARRIER: memory barrier without comment #5915: FILE: drivers/gpu/drm/i915/gt/selftest_lrc.c:799: + wmb(); -:6463: WARNING:MEMORY_BARRIER: memory barrier without comment #6463: FILE: drivers/gpu/drm/i915/gt/selftest_lrc.c:1347: + wmb(); -:6877: WARNING:LINE_SPACING: Missing a blank line after declarations #6877: FILE: drivers/gpu/drm/i915/gt/selftest_lrc.c:1761: + struct i915_request *rq; + IGT_TIMEOUT(end_time); total: 2 errors, 6 warnings, 4 checks, 5153 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 19/21] drm/i915/gt: Use indices for writing into relative timelines
On Thu, Dec 10, 2020 at 09:05:44PM +, Chris Wilson wrote: > Quoting Matthew Brost (2020-12-10 19:16:44) > > On Thu, Dec 10, 2020 at 08:02:38AM +, Chris Wilson wrote: > > > Relative timelines are relative to either the global or per-process > > > HWSP, and so we can replace the absolute addressing with store-index > > > variants for position invariance. > > > > > > > Can you explain the benifit of relative addressing? Why can't we also > > use absolute? If we can always use absolute, I don't see the point > > complicating the breadcrumb code. > > It basically allows a third party to move the contexts between hosts > with far less patching of global state. They want us to avoid all fixed > GGTT addressing. > > The breadcrumbs themselves do not notice at all, it's just the timeline > setup and decision to take advantage of the relative commands. The > breadcrumb patches in this series are some outstanding fixes from ~6 > months ago. By breadcrumbs, I meant the emit code. Relative addressing for GVT makes sense. With that, for this patch: Reviewed-by: Matthew Brost > -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 17/21] drm/i915/gt: Track timeline GGTT offset separately from subpage offset
On Thu, Dec 10, 2020 at 08:02:36AM +, Chris Wilson wrote:
> Currently we know that the timeline status page is at most a page in
> size, and so we can preserve the lower 12bits of the offset when
> relocating the status page in the GGTT. If we want to use a larger
> object, such as the context state, we may not necessarily use a position
> within the first page and so need more than 12b.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Matthew Brost
> ---
> drivers/gpu/drm/i915/gt/gen6_engine_cs.c | 4 ++--
> drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 ++--
> drivers/gpu/drm/i915/gt/intel_timeline.c | 17 +++--
> drivers/gpu/drm/i915/gt/intel_timeline_types.h | 1 +
> drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 2 +-
> drivers/gpu/drm/i915/gt/selftest_rc6.c | 2 +-
> drivers/gpu/drm/i915/gt/selftest_timeline.c| 16
> 8 files changed, 23 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/gen6_engine_cs.c
> b/drivers/gpu/drm/i915/gt/gen6_engine_cs.c
> index ce38d1bcaba3..2f59dd3bdc18 100644
> --- a/drivers/gpu/drm/i915/gt/gen6_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen6_engine_cs.c
> @@ -161,7 +161,7 @@ u32 *gen6_emit_breadcrumb_rcs(struct i915_request *rq,
> u32 *cs)
>PIPE_CONTROL_DC_FLUSH_ENABLE |
>PIPE_CONTROL_QW_WRITE |
>PIPE_CONTROL_CS_STALL);
> - *cs++ = i915_request_active_timeline(rq)->hwsp_offset |
> + *cs++ = i915_request_active_timeline(rq)->ggtt_offset |
> PIPE_CONTROL_GLOBAL_GTT;
> *cs++ = rq->fence.seqno;
>
> @@ -359,7 +359,7 @@ u32 *gen7_emit_breadcrumb_rcs(struct i915_request *rq,
> u32 *cs)
>PIPE_CONTROL_QW_WRITE |
>PIPE_CONTROL_GLOBAL_GTT_IVB |
>PIPE_CONTROL_CS_STALL);
> - *cs++ = i915_request_active_timeline(rq)->hwsp_offset;
> + *cs++ = i915_request_active_timeline(rq)->ggtt_offset;
> *cs++ = rq->fence.seqno;
>
> *cs++ = MI_USER_INTERRUPT;
> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> index ebf043692eef..ed88dc4de72c 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> @@ -346,7 +346,7 @@ static u32 hwsp_offset(const struct i915_request *rq)
> if (cl)
> return cl->ggtt_offset;
>
> - return rcu_dereference_protected(rq->timeline, 1)->hwsp_offset;
> + return rcu_dereference_protected(rq->timeline, 1)->ggtt_offset;
> }
>
> int gen8_emit_init_breadcrumb(struct i915_request *rq)
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 6c08e74edcae..55856c230779 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -1340,7 +1340,7 @@ static int print_ring(char *buf, int sz, struct
> i915_request *rq)
> len = scnprintf(buf, sz,
> "ring:{start:%08x, hwsp:%08x, seqno:%08x,
> runtime:%llums}, ",
> i915_ggtt_offset(rq->ring->vma),
> - tl ? tl->hwsp_offset : 0,
> + tl ? tl->ggtt_offset : 0,
> hwsp_seqno(rq),
>
> DIV_ROUND_CLOSEST_ULL(intel_context_get_total_runtime_ns(rq->context),
> 1000 * 1000));
> @@ -1679,7 +1679,7 @@ void intel_engine_dump(struct intel_engine_cs *engine,
>
> if (tl) {
> drm_printf(m, "\t\tring->hwsp: 0x%08x\n",
> -tl->hwsp_offset);
> +tl->ggtt_offset);
> intel_timeline_put(tl);
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c
> b/drivers/gpu/drm/i915/gt/intel_timeline.c
> index ddc8e1b4f3b8..cb20fcbb326b 100644
> --- a/drivers/gpu/drm/i915/gt/intel_timeline.c
> +++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
> @@ -338,13 +338,11 @@ int intel_timeline_pin(struct intel_timeline *tl,
> struct i915_gem_ww_ctx *ww)
> if (err)
> return err;
>
> - tl->hwsp_offset =
> - i915_ggtt_offset(tl->hwsp_ggtt) +
> - offset_in_page(tl->hwsp_offset);
> + tl->ggtt_offset = i915_ggtt_offset(tl->hwsp_ggtt) + tl->hwsp_offset;
> GT_TRACE(tl->gt, "timeline:%llx using HWSP offset:%x\n",
> - tl->fence_context, tl->hwsp_offset);
> + tl->fence_context, tl->ggtt_offset);
>
> - cacheline_acquire(tl->hwsp_cacheline, tl->hwsp_offset);
> + cacheline_acquire(tl->hwsp_cacheline, tl->ggtt_offset);
> if (atomic_fetch_inc(>pin_count)) {
> cacheline_release(tl->hwsp_cacheline);
> __i915_vma_unpin(tl->hwsp_ggtt);
> @@ -512,14 +510,13 @@
Re: [Intel-gfx] [PATCH 21/21] drm/i915/gt: Use ppHWSP for unshared non-semaphore related timelines
On Thu, Dec 10, 2020 at 08:02:40AM +, Chris Wilson wrote:
> When we are not using semaphores with a context/engine, we can simply
> reuse the same seqno location across wraps, but we still require each
> timeline to have its own address. For LRC submission, each context is
> prefixed by a per-process HWSP, which provides us with a unique location
> for each context-local timeline. A shared timeline that is common to
> multiple contexts will continue to use a separate page.
>
> This enables us to create position invariant contexts should we feel the
> need to relocate them.
>
Reviewed-by: Matthew Brost
> Signed-off-by: Chris Wilson
> Cc: Joonas Lahtinen
> ---
> .../drm/i915/gt/intel_execlists_submission.c | 37 +++
> 1 file changed, 22 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index 8bff0559a6a9..cc1b3509d808 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -4749,6 +4749,14 @@ static struct intel_timeline *pinned_timeline(struct
> intel_context *ce)
>page_unmask_bits(tl));
> }
>
> +static struct intel_timeline *pphwsp_timeline(struct intel_context *ce,
> + struct i915_vma *state)
> +{
> + return __intel_timeline_create(ce->engine->gt, state,
> +I915_GEM_HWS_SEQNO_ADDR |
> +INTEL_TIMELINE_CONTEXT);
> +}
> +
> static int __execlists_context_alloc(struct intel_context *ce,
>struct intel_engine_cs *engine)
> {
> @@ -4779,6 +4787,16 @@ static int __execlists_context_alloc(struct
> intel_context *ce,
> goto error_deref_obj;
> }
>
> + ring = intel_engine_create_ring(engine, (unsigned long)ce->ring);
> + if (IS_ERR(ring)) {
> + ret = PTR_ERR(ring);
> + goto error_deref_obj;
> + }
> +
> + ret = populate_lr_context(ce, ctx_obj, engine, ring);
> + if (ret)
> + goto error_ring_free;
> +
> if (!page_mask_bits(ce->timeline)) {
> struct intel_timeline *tl;
>
> @@ -4788,29 +4806,18 @@ static int __execlists_context_alloc(struct
> intel_context *ce,
>*/
> if (unlikely(ce->timeline))
> tl = pinned_timeline(ce);
> - else
> + else if (intel_engine_has_semaphores(engine))
> tl = intel_timeline_create(engine->gt);
> + else
> + tl = pphwsp_timeline(ce, vma);
> if (IS_ERR(tl)) {
> ret = PTR_ERR(tl);
> - goto error_deref_obj;
> + goto error_ring_free;
> }
>
> ce->timeline = tl;
> }
>
> - ring = intel_engine_create_ring(engine, (unsigned long)ce->ring);
> - if (IS_ERR(ring)) {
> - ret = PTR_ERR(ring);
> - goto error_deref_obj;
> - }
> -
> - ret = populate_lr_context(ce, ctx_obj, engine, ring);
> - if (ret) {
> - drm_dbg(>i915->drm,
> - "Failed to populate LRC: %d\n", ret);
> - goto error_ring_free;
> - }
> -
> ce->ring = ring;
> ce->state = vma;
>
> --
> 2.20.1
>
> ___
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Re: [Intel-gfx] [PATCH 18/21] drm/i915/gt: Add timeline "mode"
On Thu, Dec 10, 2020 at 09:00:53PM +, Chris Wilson wrote:
> Quoting Matthew Brost (2020-12-10 19:28:06)
> > On Thu, Dec 10, 2020 at 08:02:37AM +, Chris Wilson wrote:
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_timeline_types.h
> > > b/drivers/gpu/drm/i915/gt/intel_timeline_types.h
> > > index f187c5aac11c..32c51425a0c4 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_timeline_types.h
> > > +++ b/drivers/gpu/drm/i915/gt/intel_timeline_types.h
> > > @@ -20,6 +20,12 @@ struct i915_syncmap;
> > > struct intel_gt;
> > > struct intel_timeline_hwsp;
> > >
> > > +enum intel_timeline_mode {
> > > + INTEL_TIMELINE_ABSOLUTE = 0,
> > > + INTEL_TIMELINE_CONTEXT = BIT(0),
> > > + INTEL_TIMELINE_GLOBAL = BIT(1),
> > > +};
> > > +
> >
> > Not sure I like these names.
> >
> > How about:
> > INTEL_TIMELINE_ABSOLUTE_GGTT
> > INTEL_TIMELINE_RELATIVE_PPGTT
> > INTEL_TIMELINE_RELATIVE_GGTT
>
> They are all in the GGTT, including the ppHWSP.
>
Ah, got it. The 'MI_FLUSH_DW_USE_GTT' in a later patch threw me off. I
see now that it is picking between global status page and per-process
page in that case.
> One is relative to the context, the other relative to the engine.
>
> INTEL_TIMELINE_ABSOLUTE
> INTEL_TIMELINE_RELATIVE_CONTEXT
> INTEL_TIMELINE_RELATIVE_ENGINE
>
I like these names better.
> > Also not convinced we need the 'RELATIVE' modes. See my comments in 'Use
> > indices for writing into relative'.
>
> It saves extra allocations for when we don't (e.g. gen8, and other
> contexts where we know we will never require disposable slots), and
> there's a strong incentive to not use absolute addressing with GVT
Understand using the status page to save on allocations.
I could see relative addressing helping with GVT.
With the name nits:
Reviewed-by: Matthew Brost
> -Chris
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Re: [Intel-gfx] [PATCH 19/21] drm/i915/gt: Use indices for writing into relative timelines
Quoting Matthew Brost (2020-12-10 19:16:44) > On Thu, Dec 10, 2020 at 08:02:38AM +, Chris Wilson wrote: > > Relative timelines are relative to either the global or per-process > > HWSP, and so we can replace the absolute addressing with store-index > > variants for position invariance. > > > > Can you explain the benifit of relative addressing? Why can't we also > use absolute? If we can always use absolute, I don't see the point > complicating the breadcrumb code. It basically allows a third party to move the contexts between hosts with far less patching of global state. They want us to avoid all fixed GGTT addressing. The breadcrumbs themselves do not notice at all, it's just the timeline setup and decision to take advantage of the relative commands. The breadcrumb patches in this series are some outstanding fixes from ~6 months ago. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [patch 17/30] NTB/msi: Use irq_has_action()
On 2020-12-10 12:25 p.m., Thomas Gleixner wrote:
> Use the proper core function.
>
> Signed-off-by: Thomas Gleixner
> Cc: Jon Mason
> Cc: Dave Jiang
> Cc: Allen Hubbe
> Cc: linux-...@googlegroups.com
Looks good to me.
Reviewed-by: Logan Gunthorpe
> ---
> drivers/ntb/msi.c |4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> --- a/drivers/ntb/msi.c
> +++ b/drivers/ntb/msi.c
> @@ -282,15 +282,13 @@ int ntbm_msi_request_threaded_irq(struct
> struct ntb_msi_desc *msi_desc)
> {
> struct msi_desc *entry;
> - struct irq_desc *desc;
> int ret;
>
> if (!ntb->msi)
> return -EINVAL;
>
> for_each_pci_msi_entry(entry, ntb->pdev) {
> - desc = irq_to_desc(entry->irq);
> - if (desc->action)
> + if (irq_has_action(entry->irq))
> continue;
>
> ret = devm_request_threaded_irq(>dev, entry->irq, handler,
>
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Re: [Intel-gfx] [PATCH 18/21] drm/i915/gt: Add timeline "mode"
Quoting Matthew Brost (2020-12-10 19:28:06)
> On Thu, Dec 10, 2020 at 08:02:37AM +, Chris Wilson wrote:
> > diff --git a/drivers/gpu/drm/i915/gt/intel_timeline_types.h
> > b/drivers/gpu/drm/i915/gt/intel_timeline_types.h
> > index f187c5aac11c..32c51425a0c4 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_timeline_types.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_timeline_types.h
> > @@ -20,6 +20,12 @@ struct i915_syncmap;
> > struct intel_gt;
> > struct intel_timeline_hwsp;
> >
> > +enum intel_timeline_mode {
> > + INTEL_TIMELINE_ABSOLUTE = 0,
> > + INTEL_TIMELINE_CONTEXT = BIT(0),
> > + INTEL_TIMELINE_GLOBAL = BIT(1),
> > +};
> > +
>
> Not sure I like these names.
>
> How about:
> INTEL_TIMELINE_ABSOLUTE_GGTT
> INTEL_TIMELINE_RELATIVE_PPGTT
> INTEL_TIMELINE_RELATIVE_GGTT
They are all in the GGTT, including the ppHWSP.
One is relative to the context, the other relative to the engine.
INTEL_TIMELINE_ABSOLUTE
INTEL_TIMELINE_RELATIVE_CONTEXT
INTEL_TIMELINE_RELATIVE_ENGINE
> Also not convinced we need the 'RELATIVE' modes. See my comments in 'Use
> indices for writing into relative'.
It saves extra allocations for when we don't (e.g. gen8, and other
contexts where we know we will never require disposable slots), and
there's a strong incentive to not use absolute addressing with GVT.
-Chris
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/pmu: Stop peeking at kernel internals for counting interrupts
== Series Details == Series: drm/i915/pmu: Stop peeking at kernel internals for counting interrupts URL : https://patchwork.freedesktop.org/series/84800/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9472 -> Patchwork_19114 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19114 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19114, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19114/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19114: ### IGT changes ### Possible regressions * igt@i915_selftest@live@ring_submission: - fi-apl-guc: [PASS][1] -> [DMESG-WARN][2] +13 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9472/fi-apl-guc/igt@i915_selftest@live@ring_submission.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19114/fi-apl-guc/igt@i915_selftest@live@ring_submission.html Known issues Here are the changes found in Patchwork_19114 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@execlists: - fi-apl-guc: [PASS][3] -> [DMESG-WARN][4] ([i915#1037]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9472/fi-apl-guc/igt@i915_selftest@l...@execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19114/fi-apl-guc/igt@i915_selftest@l...@execlists.html * igt@kms_addfb_basic@addfb25-modifier-no-flag: - fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9472/fi-tgl-y/igt@kms_addfb_ba...@addfb25-modifier-no-flag.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19114/fi-tgl-y/igt@kms_addfb_ba...@addfb25-modifier-no-flag.html Possible fixes * igt@debugfs_test@read_all_entries: - fi-tgl-y: [DMESG-WARN][7] ([i915#402]) -> [PASS][8] +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9472/fi-tgl-y/igt@debugfs_test@read_all_entries.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19114/fi-tgl-y/igt@debugfs_test@read_all_entries.html [i915#1037]: https://gitlab.freedesktop.org/drm/intel/issues/1037 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (44 -> 40) -- Missing(4): fi-ctg-p8600 fi-ilk-m540 fi-bdw-samus fi-hsw-4200u Build changes - * Linux: CI_DRM_9472 -> Patchwork_19114 CI-20190529: 20190529 CI_DRM_9472: 661399b277bad4b274f9c7dc8ee8a967f5353cb5 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5888: c79d4e88f4162905da400360b6fa4940122f3a2c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19114: fe77a262404fb4e2128ee608bd14ac219764a669 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == fe77a262404f drm/i915/pmu: Stop peeking at kernel internals for counting interrupts == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19114/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BUILD: failure for genirq: Treewide hunt for irq descriptor abuse and assorted fixes
== Series Details == Series: genirq: Treewide hunt for irq descriptor abuse and assorted fixes URL : https://patchwork.freedesktop.org/series/84805/ State : failure == Summary == Applying: genirq: Move irq_has_action() into core code Applying: genirq: Move status flag checks to core Applying: genirq: Move irq_set_lockdep_class() to core Applying: genirq: Provide irq_get_effective_affinity() Applying: genirq: Annotate irq stats data races Applying: parisc/irq: Simplify irq count output for /proc/interrupts Applying: genirq: Make kstat_irqs() static Applying: genirq: Provide kstat_irqdesc_cpu() Applying: ARM: smp: Use irq_desc_kstat_cpu() in show_ipi_list() Applying: arm64/smp: Use irq_desc_kstat_cpu() in arch_show_interrupts() Applying: parisc/irq: Use irq_desc_kstat_cpu() in show_interrupts() Applying: s390/irq: Use irq_desc_kstat_cpu() in show_msi_interrupt() Applying: drm/i915/lpe_audio: Remove pointless irq_to_desc() usage Applying: drm/i915/pmu: Replace open coded kstat_irqs() copy error: sha1 information is lacking or useless (drivers/gpu/drm/i915/i915_irq.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0014 drm/i915/pmu: Replace open coded kstat_irqs() copy When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev2)
== Series Details == Series: drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev2) URL : https://patchwork.freedesktop.org/series/84754/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9471_full -> Patchwork_19112_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19112_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19112_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19112_full: ### IGT changes ### Possible regressions * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic: - shard-glk: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9471/shard-glk1/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-atomic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19112/shard-glk7/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-atomic.html Known issues Here are the changes found in Patchwork_19112_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@legacy-engines-mixed-process: - shard-hsw: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19112/shard-hsw4/igt@gem_ctx_persiste...@legacy-engines-mixed-process.html * igt@gem_huc_copy@huc-copy: - shard-tglb: [PASS][4] -> [SKIP][5] ([i915#2190]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9471/shard-tglb2/igt@gem_huc_c...@huc-copy.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19112/shard-tglb6/igt@gem_huc_c...@huc-copy.html * igt@gem_workarounds@suspend-resume: - shard-kbl: [PASS][6] -> [DMESG-WARN][7] ([i915#180]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9471/shard-kbl2/igt@gem_workarou...@suspend-resume.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19112/shard-kbl6/igt@gem_workarou...@suspend-resume.html * igt@i915_pm_dc@dc5-psr: - shard-skl: [PASS][8] -> [INCOMPLETE][9] ([i915#198]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9471/shard-skl1/igt@i915_pm...@dc5-psr.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19112/shard-skl5/igt@i915_pm...@dc5-psr.html * igt@i915_pm_rpm@gem-execbuf-stress-pc8: - shard-hsw: NOTRUN -> [SKIP][10] ([fdo#109271]) +53 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19112/shard-hsw4/igt@i915_pm_...@gem-execbuf-stress-pc8.html * igt@kms_async_flips@alternate-sync-async-flip: - shard-apl: [PASS][11] -> [FAIL][12] ([i915#2521]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9471/shard-apl1/igt@kms_async_fl...@alternate-sync-async-flip.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19112/shard-apl7/igt@kms_async_fl...@alternate-sync-async-flip.html * igt@kms_chamelium@hdmi-audio: - shard-skl: NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19112/shard-skl5/igt@kms_chamel...@hdmi-audio.html * igt@kms_color@pipe-b-ctm-0-75: - shard-skl: [PASS][14] -> [DMESG-WARN][15] ([i915#1982]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9471/shard-skl8/igt@kms_co...@pipe-b-ctm-0-75.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19112/shard-skl2/igt@kms_co...@pipe-b-ctm-0-75.html * igt@kms_color_chamelium@pipe-a-ctm-blue-to-red: - shard-hsw: NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827]) +3 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19112/shard-hsw4/igt@kms_color_chamel...@pipe-a-ctm-blue-to-red.html * igt@kms_cursor_crc@pipe-c-cursor-256x85-sliding: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#54]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9471/shard-skl4/igt@kms_cursor_...@pipe-c-cursor-256x85-sliding.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19112/shard-skl1/igt@kms_cursor_...@pipe-c-cursor-256x85-sliding.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#79]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9471/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interrupti...@c-edp1.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19112/shard-skl3/igt@kms_flip@flip-vs-expired-vblank-interrupti...@c-edp1.html * igt@kms_flip@flip-vs-suspend@b-hdmi-a1: - shard-hsw: NOTRUN -> [INCOMPLETE][21] ([i915#2055] /
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/pmu: Stop peeking at kernel internals for counting interrupts
== Series Details == Series: drm/i915/pmu: Stop peeking at kernel internals for counting interrupts URL : https://patchwork.freedesktop.org/series/84800/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 Error: Cannot open file ./drivers/gpu/drm/i915/gt/intel_lrc.c WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -sphinx-version 1.7.9 -function Logical Rings, Logical Ring Contexts and Execlists ./drivers/gpu/drm/i915/gt/intel_lrc.c' failed with return code 1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add support for Intel's eDP backlight controls (rev4)
== Series Details == Series: drm/i915: Add support for Intel's eDP backlight controls (rev4) URL : https://patchwork.freedesktop.org/series/81702/ State : success == Summary == CI Bug Log - changes from CI_DRM_9472 -> Patchwork_19113 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19113/index.html Known issues Here are the changes found in Patchwork_19113 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@execlists: - fi-icl-y: [PASS][1] -> [INCOMPLETE][2] ([i915#1037] / [i915#2276]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9472/fi-icl-y/igt@i915_selftest@l...@execlists.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19113/fi-icl-y/igt@i915_selftest@l...@execlists.html * igt@prime_self_import@basic-with_one_bo_two_files: - fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9472/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19113/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html * igt@runner@aborted: - fi-bsw-kefka: NOTRUN -> [FAIL][5] ([i915#1302] / [i915#2722]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19113/fi-bsw-kefka/igt@run...@aborted.html Possible fixes * igt@debugfs_test@read_all_entries: - fi-tgl-y: [DMESG-WARN][6] ([i915#402]) -> [PASS][7] +2 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9472/fi-tgl-y/igt@debugfs_test@read_all_entries.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19113/fi-tgl-y/igt@debugfs_test@read_all_entries.html Warnings * igt@i915_pm_rpm@basic-pci-d3-state: - fi-kbl-guc: [SKIP][8] ([fdo#109271]) -> [FAIL][9] ([i915#138]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9472/fi-kbl-guc/igt@i915_pm_...@basic-pci-d3-state.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19113/fi-kbl-guc/igt@i915_pm_...@basic-pci-d3-state.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1037]: https://gitlab.freedesktop.org/drm/intel/issues/1037 [i915#1302]: https://gitlab.freedesktop.org/drm/intel/issues/1302 [i915#138]: https://gitlab.freedesktop.org/drm/intel/issues/138 [i915#2276]: https://gitlab.freedesktop.org/drm/intel/issues/2276 [i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (44 -> 40) -- Missing(4): fi-ctg-p8600 fi-ilk-m540 fi-bdw-samus fi-hsw-4200u Build changes - * Linux: CI_DRM_9472 -> Patchwork_19113 CI-20190529: 20190529 CI_DRM_9472: 661399b277bad4b274f9c7dc8ee8a967f5353cb5 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5888: c79d4e88f4162905da400360b6fa4940122f3a2c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19113: b5315912cc7f80cbd9b1288f75b0ff9f31e1cb81 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == b5315912cc7f drm/dp: Revert "drm/dp: Introduce EDID-based quirks" d6f6f3fa825f drm/i915/dp: Allow forcing specific interfaces through enable_dpcd_backlight 9a7fd4a45094 drm/i915/dp: Enable Intel's HDR backlight interface (only SDR for now) a39270383236 drm/i915/dp: Add register definitions for Intel HDR backlight interface d2b61f334725 drm/i915/dp: Rename eDP VESA backlight interface functions a0b1c9f85b6d drm/i915: Keep track of pwm-related backlight hooks separately 67aeac3f4a13 drm/i915: Pass down brightness values to enable/disable backlight callbacks 512d305a2664 drm/i915: Rename pwm_* backlight callbacks to ext_pwm_* d5d9ce10b038 drm/i915/dp: Program source OUI on eDP panels == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19113/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Correct location of Wa_1408615072 (rev2)
== Series Details == Series: drm/i915: Correct location of Wa_1408615072 (rev2) URL : https://patchwork.freedesktop.org/series/79370/ State : success == Summary == CI Bug Log - changes from CI_DRM_9471_full -> Patchwork_19111_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_19111_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@legacy-engines-mixed-process: - shard-hsw: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19111/shard-hsw6/igt@gem_ctx_persiste...@legacy-engines-mixed-process.html * igt@gem_exec_whisper@basic-fds-priority-all: - shard-glk: [PASS][2] -> [DMESG-WARN][3] ([i915#118] / [i915#95]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9471/shard-glk2/igt@gem_exec_whis...@basic-fds-priority-all.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19111/shard-glk7/igt@gem_exec_whis...@basic-fds-priority-all.html * igt@i915_pm_rpm@gem-execbuf-stress-pc8: - shard-hsw: NOTRUN -> [SKIP][4] ([fdo#109271]) +49 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19111/shard-hsw6/igt@i915_pm_...@gem-execbuf-stress-pc8.html * igt@i915_pm_rpm@system-suspend-execbuf: - shard-skl: [PASS][5] -> [INCOMPLETE][6] ([i915#151]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9471/shard-skl5/igt@i915_pm_...@system-suspend-execbuf.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19111/shard-skl7/igt@i915_pm_...@system-suspend-execbuf.html * igt@i915_suspend@forcewake: - shard-skl: [PASS][7] -> [INCOMPLETE][8] ([i915#636]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9471/shard-skl9/igt@i915_susp...@forcewake.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19111/shard-skl9/igt@i915_susp...@forcewake.html * igt@kms_ccs@pipe-c-bad-aux-stride: - shard-skl: NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111304]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19111/shard-skl2/igt@kms_...@pipe-c-bad-aux-stride.html * igt@kms_chamelium@dp-edid-change-during-suspend: - shard-skl: NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19111/shard-skl6/igt@kms_chamel...@dp-edid-change-during-suspend.html * igt@kms_color_chamelium@pipe-a-ctm-blue-to-red: - shard-hsw: NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +4 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19111/shard-hsw6/igt@kms_color_chamel...@pipe-a-ctm-blue-to-red.html * igt@kms_cursor_crc@pipe-a-cursor-256x256-sliding: - shard-skl: NOTRUN -> [FAIL][12] ([i915#54]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19111/shard-skl7/igt@kms_cursor_...@pipe-a-cursor-256x256-sliding.html * igt@kms_cursor_crc@pipe-c-cursor-256x85-sliding: - shard-skl: [PASS][13] -> [FAIL][14] ([i915#54]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9471/shard-skl4/igt@kms_cursor_...@pipe-c-cursor-256x85-sliding.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19111/shard-skl10/igt@kms_cursor_...@pipe-c-cursor-256x85-sliding.html * igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions: - shard-hsw: NOTRUN -> [INCOMPLETE][15] ([i915#2295]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19111/shard-hsw2/igt@kms_cursor_leg...@cursor-vs-flip-atomic-transitions.html * igt@kms_flip@flip-vs-suspend@c-dp1: - shard-kbl: [PASS][16] -> [DMESG-WARN][17] ([i915#180]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9471/shard-kbl3/igt@kms_flip@flip-vs-susp...@c-dp1.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19111/shard-kbl7/igt@kms_flip@flip-vs-susp...@c-dp1.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt: - shard-skl: NOTRUN -> [SKIP][18] ([fdo#109271]) +13 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19111/shard-skl2/igt@kms_frontbuffer_track...@fbc-2p-scndscrn-pri-indfb-draw-blt.html * igt@kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9471/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19111/shard-iclb5/igt@kms_psr@psr2_cursor_mmap_cpu.html Possible fixes * igt@kms_cursor_crc@pipe-c-cursor-128x128-random: - shard-skl: [FAIL][21] ([i915#54]) -> [PASS][22] +2 similar issues [21]:
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Add support for Intel's eDP backlight controls (rev4)
== Series Details == Series: drm/i915: Add support for Intel's eDP backlight controls (rev4) URL : https://patchwork.freedesktop.org/series/81702/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 Error: Cannot open file ./drivers/gpu/drm/i915/gt/intel_lrc.c WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -sphinx-version 1.7.9 -function Logical Rings, Logical Ring Contexts and Execlists ./drivers/gpu/drm/i915/gt/intel_lrc.c' failed with return code 1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
