[Intel-gfx] ✓ Fi.CI.BAT: success for Multi DSB instance support (rev2)
== Series Details == Series: Multi DSB instance support (rev2) URL : https://patchwork.freedesktop.org/series/84934/ State : success == Summary == CI Bug Log - changes from CI_DRM_9509 -> Patchwork_19195 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19195/index.html Known issues Here are the changes found in Patchwork_19195 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_cs_nop@fork-compute0: - fi-tgl-u2: NOTRUN -> [SKIP][1] ([fdo#109315] / [i915#2575]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19195/fi-tgl-u2/igt@amdgpu/amd_cs_...@fork-compute0.html * igt@prime_vgem@basic-read: - fi-tgl-y: [PASS][2] -> [DMESG-WARN][3] ([i915#402]) +1 similar issue [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/fi-tgl-y/igt@prime_v...@basic-read.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19195/fi-tgl-y/igt@prime_v...@basic-read.html Possible fixes * igt@gem_tiled_blits@basic: - fi-tgl-y: [DMESG-WARN][4] ([i915#402]) -> [PASS][5] +2 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/fi-tgl-y/igt@gem_tiled_bl...@basic.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19195/fi-tgl-y/igt@gem_tiled_bl...@basic.html * igt@i915_selftest@live@hangcheck: - fi-tgl-u2: [INCOMPLETE][6] -> [PASS][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/fi-tgl-u2/igt@i915_selftest@l...@hangcheck.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19195/fi-tgl-u2/igt@i915_selftest@l...@hangcheck.html * igt@kms_chamelium@dp-edid-read: - fi-cml-u2: [FAIL][8] ([i915#2679]) -> [PASS][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/fi-cml-u2/igt@kms_chamel...@dp-edid-read.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19195/fi-cml-u2/igt@kms_chamel...@dp-edid-read.html [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575 [i915#2679]: https://gitlab.freedesktop.org/drm/intel/issues/2679 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (42 -> 38) -- Missing(4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u Build changes - * Linux: CI_DRM_9509 -> Patchwork_19195 CI-20190529: 20190529 CI_DRM_9509: 66ecfb1df07b703dc4e83e8c520b186dffe6d2b3 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5913: b30bdfecaf1ff38b83c0bfbcf5981732a968a464 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19195: cfe4b9b4b20bf17a2d6f581b02b722ce310b94f1 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == cfe4b9b4b20b drm/i915/dsb: multi dsb instance support in dsb-commit() 7701fb147537 drm/i915/dsb: multi dsb instance support in dsb-write() 0c7de4da8b93 drm/i915/dsb: multi dsb instance support in prepare() and cleanup() == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19195/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Multi DSB instance support (rev2)
== Series Details == Series: Multi DSB instance support (rev2) URL : https://patchwork.freedesktop.org/series/84934/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/selftest_reset.c:101:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:101:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:101:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:102:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:102:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:102:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:137:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:137:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:137:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:138:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:138:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:138:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:99:34:expected unsigned int [usertype] *s +drivers/gpu/drm/i915/gt/selftest_reset.c:99:34:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:99:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1449:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1503:15: warning: memset with byte count of 16777216 +./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:864:16: warning: trying to copy expression type 31 +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Multi DSB instance support (rev2)
== Series Details ==
Series: Multi DSB instance support (rev2)
URL : https://patchwork.freedesktop.org/series/84934/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0c7de4da8b93 drm/i915/dsb: multi dsb instance support in prepare() and cleanup()
-:167: WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message
#167: FILE: drivers/gpu/drm/i915/display/intel_dsb.c:277:
+ if (!dsb) {
+ drm_err(>drm, "DSB%d obj creation failed\n", i);
total: 0 errors, 1 warnings, 0 checks, 187 lines checked
7701fb147537 drm/i915/dsb: multi dsb instance support in dsb-write()
cfe4b9b4b20b drm/i915/dsb: multi dsb instance support in dsb-commit()
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/3] drm/i915/dsb: multi dsb instance support in dsb-commit()
To support multiple dsb instances per pipe dsb-id is passed
as argumnet in dsb-commit() and respective cmd-buffer will
be updated in actual hardware.
v1: Initial version.
v2: Improved commit description.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 74 +---
1 file changed, 39 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index 2a9df1d7cbc5..be301cb292dc 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -210,46 +210,50 @@ void intel_dsb_commit(const struct intel_crtc_state
*crtc_state)
struct drm_i915_private *dev_priv = to_i915(dev);
enum pipe pipe = crtc->pipe;
u32 tail;
+ int i;
- if (!(dsb && dsb->free_pos))
- return;
+ for (i = 0; i < MAX_DSB_PER_PIPE; i++) {
+ dsb = crtc_state->dsb[i];
+ if (!(dsb && dsb->free_pos))
+ continue;
- if (!intel_dsb_enable_engine(dev_priv, pipe, dsb->id))
- goto reset;
+ if (!intel_dsb_enable_engine(dev_priv, pipe, dsb->id))
+ goto reset;
- if (is_dsb_busy(dev_priv, pipe, dsb->id)) {
- drm_err(_priv->drm,
- "HEAD_PTR write failed - dsb engine is busy.\n");
- goto reset;
- }
- intel_de_write(dev_priv, DSB_HEAD(pipe, dsb->id),
- i915_ggtt_offset(dsb->vma));
-
- tail = ALIGN(dsb->free_pos * 4, CACHELINE_BYTES);
- if (tail > dsb->free_pos * 4)
- memset(>cmd_buf[dsb->free_pos], 0,
- (tail - dsb->free_pos * 4));
-
- if (is_dsb_busy(dev_priv, pipe, dsb->id)) {
- drm_err(_priv->drm,
- "TAIL_PTR write failed - dsb engine is busy.\n");
- goto reset;
- }
- drm_dbg_kms(_priv->drm,
- "DSB execution started - head 0x%x, tail 0x%x\n",
- i915_ggtt_offset(dsb->vma), tail);
- intel_de_write(dev_priv, DSB_TAIL(pipe, dsb->id),
- i915_ggtt_offset(dsb->vma) + tail);
- if (wait_for(!is_dsb_busy(dev_priv, pipe, dsb->id), 1)) {
- drm_err(_priv->drm,
- "Timed out waiting for DSB workload completion.\n");
- goto reset;
- }
+ if (is_dsb_busy(dev_priv, pipe, dsb->id)) {
+ drm_err(_priv->drm,
+ "HEAD_PTR write failed - dsb engine is busy\n");
+ goto reset;
+ }
+ intel_de_write(dev_priv, DSB_HEAD(pipe, dsb->id),
+ i915_ggtt_offset(dsb->vma));
+
+ tail = ALIGN(dsb->free_pos * 4, CACHELINE_BYTES);
+ if (tail > dsb->free_pos * 4)
+ memset(>cmd_buf[dsb->free_pos], 0,
+ (tail - dsb->free_pos * 4));
+
+ if (is_dsb_busy(dev_priv, pipe, dsb->id)) {
+ drm_err(_priv->drm,
+ "TAIL_PTR write failed - dsb engine is busy\n");
+ goto reset;
+ }
+ drm_dbg_kms(_priv->drm,
+ "DSB execution started - head 0x%x, tail 0x%x\n",
+ i915_ggtt_offset(dsb->vma), tail);
+ intel_de_write(dev_priv, DSB_TAIL(pipe, dsb->id),
+ i915_ggtt_offset(dsb->vma) + tail);
+ if (wait_for(!is_dsb_busy(dev_priv, pipe, dsb->id), 1)) {
+ drm_err(_priv->drm,
+ "Timed out waiting for DSB workload
completion\n");
+ goto reset;
+ }
reset:
- dsb->free_pos = 0;
- dsb->ins_start_offset = 0;
- intel_dsb_disable_engine(dev_priv, pipe, dsb->id);
+ dsb->free_pos = 0;
+ dsb->ins_start_offset = 0;
+ intel_dsb_disable_engine(dev_priv, pipe, dsb->id);
+ }
}
/**
--
2.26.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/3] drm/i915/dsb: multi dsb instance support in dsb-write()
To support multiple dsb instances per pipe dsb-id is passed
as argumnet in dsb-write() which will write into respective
dsb cmd-buffer.
v1: Initial version.
v2: Improved commit description.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_color.c | 40 +-
drivers/gpu/drm/i915/display/intel_dsb.c | 10 +++---
drivers/gpu/drm/i915/display/intel_dsb.h | 4 +--
3 files changed, 31 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 172d398081ee..02f31bcf0d24 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -728,9 +728,12 @@ static void ivb_load_lut_ext_max(const struct
intel_crtc_state *crtc_state)
enum pipe pipe = crtc->pipe;
/* Program the max register to clamp values > 1.0. */
- intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16);
- intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16);
- intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16);
+ intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16,
+ DSB1);
+ intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16,
+ DSB1);
+ intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16,
+ DSB1);
/*
* Program the gc max 2 register to clamp values > 1.0.
@@ -739,11 +742,11 @@ static void ivb_load_lut_ext_max(const struct
intel_crtc_state *crtc_state)
*/
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 0),
- 1 << 16);
+ 1 << 16, DSB1);
intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 1),
- 1 << 16);
+ 1 << 16, DSB1);
intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 2),
- 1 << 16);
+ 1 << 16, DSB1);
}
}
@@ -931,9 +934,12 @@ icl_load_gcmax(const struct intel_crtc_state *crtc_state,
enum pipe pipe = crtc->pipe;
/* FIXME LUT entries are 16 bit only, so we can prog 0x max */
- intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 0), color->red);
- intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 1), color->green);
- intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 2), color->blue);
+ intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 0), color->red,
+ DSB1);
+ intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 1), color->green,
+ DSB1);
+ intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 2), color->blue,
+ DSB1);
}
static void
@@ -953,15 +959,15 @@ icl_program_gamma_superfine_segment(const struct
intel_crtc_state *crtc_state)
* 2/(8 * 128 * 256) ... 8/(8 * 128 * 256).
*/
intel_dsb_reg_write(crtc_state, PREC_PAL_MULTI_SEG_INDEX(pipe),
- PAL_PREC_AUTO_INCREMENT);
+ PAL_PREC_AUTO_INCREMENT, DSB1);
for (i = 0; i < 9; i++) {
const struct drm_color_lut *entry = [i];
intel_dsb_indexed_reg_write(crtc_state,
PREC_PAL_MULTI_SEG_DATA(pipe),
- ilk_lut_12p4_ldw(entry));
+ ilk_lut_12p4_ldw(entry), DSB1);
intel_dsb_indexed_reg_write(crtc_state,
PREC_PAL_MULTI_SEG_DATA(pipe),
- ilk_lut_12p4_udw(entry));
+ ilk_lut_12p4_udw(entry), DSB1);
}
}
@@ -986,13 +992,13 @@ icl_program_gamma_multi_segment(const struct
intel_crtc_state *crtc_state)
* seg2[0] being unused by the hardware.
*/
intel_dsb_reg_write(crtc_state, PREC_PAL_INDEX(pipe),
- PAL_PREC_AUTO_INCREMENT);
+ PAL_PREC_AUTO_INCREMENT, DSB1);
for (i = 1; i < 257; i++) {
entry = [i * 8];
intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe),
- ilk_lut_12p4_ldw(entry));
+ ilk_lut_12p4_ldw(entry), DSB1);
intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe),
- ilk_lut_12p4_udw(entry));
+ ilk_lut_12p4_udw(entry), DSB1);
}
/*
@@ -1010,9 +1016,9 @@ icl_program_gamma_multi_segment(const struct
intel_crtc_state *crtc_state)
for (i = 0; i
[Intel-gfx] [PATCH 1/3] drm/i915/dsb: multi dsb instance support in prepare() and cleanup()
Command buffer allocation is done for all 3 dsb instances for every
pipe and cleanup code is modified accordingly.
v1: Initial version.
v2: Improved commit description.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_atomic.c | 9 +-
drivers/gpu/drm/i915/display/intel_display.c | 6 +-
.../drm/i915/display/intel_display_types.h| 2 +-
drivers/gpu/drm/i915/display/intel_dsb.c | 99 ++-
4 files changed, 65 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
b/drivers/gpu/drm/i915/display/intel_atomic.c
index e00fdc47c0eb..3833f3b4851b 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -226,6 +226,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
{
const struct intel_crtc_state *old_crtc_state =
to_intel_crtc_state(crtc->state);
struct intel_crtc_state *crtc_state;
+ int i;
crtc_state = kmemdup(old_crtc_state, sizeof(*crtc_state), GFP_KERNEL);
if (!crtc_state)
@@ -252,7 +253,9 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
crtc_state->wm.need_postvbl_update = false;
crtc_state->fb_bits = 0;
crtc_state->update_planes = 0;
- crtc_state->dsb = NULL;
+
+ for (i = 0; i < MAX_DSB_PER_PIPE; i++)
+ crtc_state->dsb[i] = NULL;
return _state->uapi;
}
@@ -293,8 +296,10 @@ intel_crtc_destroy_state(struct drm_crtc *crtc,
struct drm_crtc_state *state)
{
struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);
+ int i;
- drm_WARN_ON(crtc->dev, crtc_state->dsb);
+ for (i = 0; i < MAX_DSB_PER_PIPE; i++)
+ drm_WARN_ON(crtc->dev, crtc_state->dsb[i]);
__drm_atomic_helper_crtc_destroy_state(_state->uapi);
intel_crtc_free_hw_state(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 78452de5e12f..3afe8a22c784 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -16256,7 +16256,7 @@ static void intel_atomic_commit_tail(struct
intel_atomic_state *state)
struct intel_crtc *crtc;
u64 put_domains[I915_MAX_PIPES] = {};
intel_wakeref_t wakeref = 0;
- int i;
+ int i, j;
intel_atomic_commit_fence_wait(state);
@@ -16386,7 +16386,9 @@ static void intel_atomic_commit_tail(struct
intel_atomic_state *state)
* cleanup. So copy and reset the dsb structure to sync with
* commit_done and later do dsb cleanup in cleanup_work.
*/
- old_crtc_state->dsb = fetch_and_zero(_crtc_state->dsb);
+ for (j = 0; j < MAX_DSB_PER_PIPE; j++)
+ old_crtc_state->dsb[j] =
+ fetch_and_zero(_crtc_state->dsb[j]);
}
/* Underruns don't always raise interrupts, so check manually */
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 5bc5bfbc4551..06ae7470ab8c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1124,7 +1124,7 @@ struct intel_crtc_state {
enum transcoder mst_master_transcoder;
/* For DSB related info */
- struct intel_dsb *dsb;
+ struct intel_dsb *dsb[MAX_DSB_PER_PIPE];
u32 psr2_man_track_ctl;
};
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index 566fa72427b3..cef1015cc04f 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -92,7 +92,7 @@ static bool intel_dsb_disable_engine(struct drm_i915_private
*i915,
void intel_dsb_indexed_reg_write(const struct intel_crtc_state *crtc_state,
i915_reg_t reg, u32 val)
{
- struct intel_dsb *dsb = crtc_state->dsb;
+ struct intel_dsb *dsb = crtc_state->dsb[0];
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 *buf;
@@ -174,7 +174,7 @@ void intel_dsb_reg_write(const struct intel_crtc_state
*crtc_state,
struct intel_dsb *dsb;
u32 *buf;
- dsb = crtc_state->dsb;
+ dsb = crtc_state->dsb[0];
if (!dsb) {
intel_de_write(dev_priv, reg, val);
return;
@@ -202,7 +202,7 @@ void intel_dsb_reg_write(const struct intel_crtc_state
*crtc_state,
*/
void intel_dsb_commit(const struct intel_crtc_state *crtc_state)
{
- struct intel_dsb *dsb = crtc_state->dsb;
+ struct intel_dsb *dsb = crtc_state->dsb[0];
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_device *dev = crtc->base.dev;
struct
[Intel-gfx] [PATCH 0/3] Multi DSB instance support
As an enhancement of dsb multi instance support added which can be used by color framework for big lut programming in future. Signed-off-by: Animesh Manna Animesh Manna (3): drm/i915/dsb: multi dsb instance support in prepare() and cleanup() drm/i915/dsb: multi dsb instance support in dsb-write() drm/i915/dsb: multi dsb instance support in dsb-commit() drivers/gpu/drm/i915/display/intel_atomic.c | 9 +- drivers/gpu/drm/i915/display/intel_color.c| 40 ++-- drivers/gpu/drm/i915/display/intel_display.c | 6 +- .../drm/i915/display/intel_display_types.h| 2 +- drivers/gpu/drm/i915/display/intel_dsb.c | 185 ++ drivers/gpu/drm/i915/display/intel_dsb.h | 4 +- 6 files changed, 136 insertions(+), 110 deletions(-) -- 2.26.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915: Try to guess PCH type even without ISA bridge
On 2020.12.18 17:05:31 +0800, Xiong Zhang wrote:
> From: Zhenyu Wang
>
> Some vmm like hyperv and crosvm don't supply any ISA bridge to their guest,
> when igd passthrough is equipped on these vmm, guest i915 display may
> couldn't work as guest i915 detects PCH_NONE pch type.
>
> When i915 runs as guest, this patch guess pch type through gpu type even
> without ISA bridge.
>
> v2: Fix CI warning
>
> Signed-off-by: Zhenyu Wang
Need to add yourself in sob.
> ---
> drivers/gpu/drm/i915/i915_drv.h | 7 +-
> drivers/gpu/drm/i915/intel_pch.c | 38 ++--
> 2 files changed, 32 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 5a7df5621aa3..df0b8f9268b2 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1758,6 +1758,11 @@ tgl_revids_get(struct drm_i915_private *dev_priv)
> #define INTEL_DISPLAY_ENABLED(dev_priv) \
> (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)),
> !(dev_priv)->params.disable_display)
>
> +static inline bool run_as_guest(void)
> +{
> + return !hypervisor_is_type(X86_HYPER_NATIVE);
> +}
> +
> static inline bool intel_vtd_active(void)
> {
> #ifdef CONFIG_INTEL_IOMMU
> @@ -1766,7 +1771,7 @@ static inline bool intel_vtd_active(void)
> #endif
>
> /* Running as a guest, we assume the host is enforcing VT'd */
> - return !hypervisor_is_type(X86_HYPER_NATIVE);
> + return run_as_guest();
> }
>
> static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private
> *dev_priv)
> diff --git a/drivers/gpu/drm/i915/intel_pch.c
> b/drivers/gpu/drm/i915/intel_pch.c
> index f31c0dabd0cc..a73c60bf349e 100644
> --- a/drivers/gpu/drm/i915/intel_pch.c
> +++ b/drivers/gpu/drm/i915/intel_pch.c
> @@ -184,6 +184,23 @@ intel_virt_detect_pch(const struct drm_i915_private
> *dev_priv)
> return id;
> }
>
> +static void intel_detect_pch_virt(struct drm_i915_private *dev_priv)
> +{
> + unsigned short id;
> + enum intel_pch pch_type;
> +
> + id = intel_virt_detect_pch(dev_priv);
> + pch_type = intel_pch_type(dev_priv, id);
> +
> + /* Sanity check virtual PCH id */
> + if (drm_WARN_ON(_priv->drm,
> + id && pch_type == PCH_NONE))
> + id = 0;
> +
> + dev_priv->pch_type = pch_type;
> + dev_priv->pch_id = id;
> +}
> +
> void intel_detect_pch(struct drm_i915_private *dev_priv)
> {
> struct pci_dev *pch = NULL;
> @@ -221,16 +238,7 @@ void intel_detect_pch(struct drm_i915_private *dev_priv)
> break;
> } else if (intel_is_virt_pch(id, pch->subsystem_vendor,
>pch->subsystem_device)) {
> - id = intel_virt_detect_pch(dev_priv);
> - pch_type = intel_pch_type(dev_priv, id);
> -
> - /* Sanity check virtual PCH id */
> - if (drm_WARN_ON(_priv->drm,
> - id && pch_type == PCH_NONE))
> - id = 0;
> -
> - dev_priv->pch_type = pch_type;
> - dev_priv->pch_id = id;
> + intel_detect_pch_virt(dev_priv);
> break;
> }
> }
> @@ -246,8 +254,14 @@ void intel_detect_pch(struct drm_i915_private *dev_priv)
> dev_priv->pch_id = 0;
> }
>
> - if (!pch)
> - drm_dbg_kms(_priv->drm, "No PCH found.\n");
> + if (!pch) {
Require HAS_DISPLAY() here?
> + if (run_as_guest()) {
> + drm_dbg_kms(_priv->drm, "No PCH found in vm, try
> guess..\n");
> + intel_detect_pch_virt(dev_priv);
> + } else {
> + drm_dbg_kms(_priv->drm, "No PCH found.\n");
> + }
> + }
>
> pci_dev_put(pch);
> }
> --
> 2.17.1
>
--
$gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827
signature.asc
Description: PGP signature
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/5] drm/i915/display: move needs_modeset to an inline in header (rev3)
== Series Details == Series: series starting with [CI,1/5] drm/i915/display: move needs_modeset to an inline in header (rev3) URL : https://patchwork.freedesktop.org/series/85132/ State : success == Summary == CI Bug Log - changes from CI_DRM_9509_full -> Patchwork_19193_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_19193_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@legacy-engines-cleanup: - shard-hsw: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19193/shard-hsw8/igt@gem_ctx_persiste...@legacy-engines-cleanup.html * igt@gem_exec_whisper@basic-queues-forked: - shard-glk: [PASS][2] -> [DMESG-WARN][3] ([i915#118] / [i915#95]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/shard-glk8/igt@gem_exec_whis...@basic-queues-forked.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19193/shard-glk3/igt@gem_exec_whis...@basic-queues-forked.html * igt@kms_big_fb@y-tiled-addfb-size-overflow: - shard-hsw: NOTRUN -> [SKIP][4] ([fdo#109271]) +64 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19193/shard-hsw8/igt@kms_big...@y-tiled-addfb-size-overflow.html * igt@kms_chamelium@hdmi-hpd-enable-disable-mode: - shard-hsw: NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +6 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19193/shard-hsw8/igt@kms_chamel...@hdmi-hpd-enable-disable-mode.html * igt@kms_color@pipe-a-ctm-0-5: - shard-skl: [PASS][6] -> [DMESG-WARN][7] ([i915#1982]) +2 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/shard-skl2/igt@kms_co...@pipe-a-ctm-0-5.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19193/shard-skl8/igt@kms_co...@pipe-a-ctm-0-5.html * igt@kms_color_chamelium@pipe-c-degamma: - shard-skl: NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827]) +2 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19193/shard-skl2/igt@kms_color_chamel...@pipe-c-degamma.html * igt@kms_cursor_crc@pipe-a-cursor-128x128-offscreen: - shard-skl: [PASS][9] -> [FAIL][10] ([i915#54]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/shard-skl6/igt@kms_cursor_...@pipe-a-cursor-128x128-offscreen.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19193/shard-skl9/igt@kms_cursor_...@pipe-a-cursor-128x128-offscreen.html * igt@kms_cursor_crc@pipe-a-cursor-128x42-offscreen: - shard-glk: [PASS][11] -> [FAIL][12] ([i915#54]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/shard-glk4/igt@kms_cursor_...@pipe-a-cursor-128x42-offscreen.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19193/shard-glk2/igt@kms_cursor_...@pipe-a-cursor-128x42-offscreen.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: - shard-hsw: [PASS][13] -> [FAIL][14] ([i915#96]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/shard-hsw8/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-legacy.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19193/shard-hsw6/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-legacy.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1: - shard-tglb: [PASS][15] -> [FAIL][16] ([i915#2598]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/shard-tglb5/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-edp1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19193/shard-tglb8/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-edp1.html * igt@kms_flip@plain-flip-fb-recreate@c-edp1: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#2122]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/shard-skl8/igt@kms_flip@plain-flip-fb-recre...@c-edp1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19193/shard-skl10/igt@kms_flip@plain-flip-fb-recre...@c-edp1.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt: - shard-skl: NOTRUN -> [SKIP][19] ([fdo#109271]) +10 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19193/shard-skl2/igt@kms_frontbuffer_track...@fbc-2p-scndscrn-pri-indfb-draw-blt.html * igt@kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][20] -> [FAIL][21] ([i915#1188]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/shard-skl6/igt@kms_...@bpc-switch-suspend.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19193/shard-skl1/igt@kms_...@bpc-switch-suspend.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][22] -> [FAIL][23] ([fdo#108145] /
[Intel-gfx] ✗ Fi.CI.BAT: failure for Introduce Intel PXP component - Mesa single session (rev14)
== Series Details ==
Series: Introduce Intel PXP component - Mesa single session (rev14)
URL : https://patchwork.freedesktop.org/series/84620/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9509 -> Patchwork_19194
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_19194 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19194, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19194/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_19194:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live@gtt:
- fi-kbl-soraka: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/fi-kbl-soraka/igt@i915_selftest@l...@gtt.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19194/fi-kbl-soraka/igt@i915_selftest@l...@gtt.html
Known issues
Here are the changes found in Patchwork_19194 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_cs_nop@fork-compute0:
- fi-tgl-u2: NOTRUN -> [SKIP][3] ([fdo#109315] / [i915#2575]) +17
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19194/fi-tgl-u2/igt@amdgpu/amd_cs_...@fork-compute0.html
* igt@gem_exec_store@basic:
- fi-tgl-y: [PASS][4] -> [DMESG-WARN][5] ([i915#402]) +2 similar
issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/fi-tgl-y/igt@gem_exec_st...@basic.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19194/fi-tgl-y/igt@gem_exec_st...@basic.html
* igt@i915_selftest@live@active:
- fi-icl-u2: [PASS][6] -> [DMESG-FAIL][7] ([i915#2291])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/fi-icl-u2/igt@i915_selftest@l...@active.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19194/fi-icl-u2/igt@i915_selftest@l...@active.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-tgl-y: [PASS][8] -> [DMESG-FAIL][9] ([i915#2601])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/fi-tgl-y/igt@i915_selftest@live@gt_heartbeat.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19194/fi-tgl-y/igt@i915_selftest@live@gt_heartbeat.html
* igt@runner@aborted:
- fi-kbl-soraka: NOTRUN -> [FAIL][10] ([i915#1436] / [i915#2295])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19194/fi-kbl-soraka/igt@run...@aborted.html
Possible fixes
* igt@gem_tiled_blits@basic:
- fi-tgl-y: [DMESG-WARN][11] ([i915#402]) -> [PASS][12] +2
similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/fi-tgl-y/igt@gem_tiled_bl...@basic.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19194/fi-tgl-y/igt@gem_tiled_bl...@basic.html
* igt@i915_selftest@live@hangcheck:
- fi-tgl-u2: [INCOMPLETE][13] -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/fi-tgl-u2/igt@i915_selftest@l...@hangcheck.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19194/fi-tgl-u2/igt@i915_selftest@l...@hangcheck.html
* igt@kms_chamelium@dp-edid-read:
- fi-cml-u2: [FAIL][15] ([i915#2679]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/fi-cml-u2/igt@kms_chamel...@dp-edid-read.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19194/fi-cml-u2/igt@kms_chamel...@dp-edid-read.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
[i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2601]: https://gitlab.freedesktop.org/drm/intel/issues/2601
[i915#2679]: https://gitlab.freedesktop.org/drm/intel/issues/2679
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (42 -> 38)
--
Missing(4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u
Build changes
-
* Linux: CI_DRM_9509 -> Patchwork_19194
CI-20190529: 20190529
CI_DRM_9509: 66ecfb1df07b703dc4e83e8c520b186dffe6d2b3 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5913: b30bdfecaf1ff38b83c0bfbcf5981732a968a464 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19194:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Introduce Intel PXP component - Mesa single session (rev14)
== Series Details == Series: Introduce Intel PXP component - Mesa single session (rev14) URL : https://patchwork.freedesktop.org/series/84620/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +drivers/gpu/drm/i915/pxp/intel_pxp_arb.c:68:5: warning: symbol 'intel_pxp_arb_reserve_session' was not declared. Should it be static? ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Intel PXP component - Mesa single session (rev14)
== Series Details == Series: Introduce Intel PXP component - Mesa single session (rev14) URL : https://patchwork.freedesktop.org/series/84620/ State : warning == Summary == $ dim checkpatch origin/drm-tip f633f387f40f drm/i915/pxp: Introduce Intel PXP component -:118: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #118: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 193 lines checked d3cca8a46779 drm/i915/pxp: set KCR reg init during the boot time 329b3f86c96b drm/i915/pxp: Implement funcs to create the TEE channel -:8: WARNING:TYPO_SPELLING: 'defualt' may be misspelled - perhaps 'default'? #8: (defualt) session. -:85: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #85: new file mode 100644 total: 0 errors, 2 warnings, 0 checks, 248 lines checked 4c4c7fbf6cb6 drm/i915/pxp: Create the arbitrary session after boot -:68: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #68: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 299 lines checked 4ac08ed07b09 drm/i915/pxp: Func to send hardware session termination -:53: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #53: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 222 lines checked b035a9ceab1c drm/i915/pxp: Enable PXP irq worker and callback stub -:51: WARNING:LONG_LINE_COMMENT: line length of 113 exceeds 100 columns #51: FILE: drivers/gpu/drm/i915/i915_reg.h:7970: +#define GEN11_CRYPTO_INTR_MASK _MMIO(0x1900f0) /* crypto mask is in bit31-16 (Engine1 Interrupt Mask) */ total: 0 errors, 1 warnings, 0 checks, 230 lines checked ea8020913889 drm/i915/pxp: Destroy arb session upon teardown b88d49c029f8 drm/i915/pxp: Enable PXP power management -:78: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #78: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 148 lines checked 838a0b841cc1 drm/i915/pxp: Expose session state for display protection flip 37bec98c389d mei: pxp: export pavp client to me client bus -:32: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #32: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 277 lines checked f8e781060b2d drm/i915/uapi: introduce drm_i915_gem_create_ext -:12: ERROR:BAD_SIGN_OFF: Unrecognized email address: 'Joonas Lahtinen joonas.lahti...@linux.intel.com' #12: Cc: Joonas Lahtinen joonas.lahti...@linux.intel.com -:13: ERROR:BAD_SIGN_OFF: Unrecognized email address: 'Matthew Auld matthew.a...@intel.com' #13: Cc: Matthew Auld matthew.a...@intel.com -:46: ERROR:CODE_INDENT: code indent should use tabs where possible #46: FILE: drivers/gpu/drm/i915/i915_gem.c:265: +struct drm_i915_private *i915;$ -:46: WARNING:LEADING_SPACE: please, no spaces at the start of a line #46: FILE: drivers/gpu/drm/i915/i915_gem.c:265: +struct drm_i915_private *i915;$ -:50: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #50: FILE: drivers/gpu/drm/i915/i915_gem.c:269: +static int __create_setparam(struct drm_i915_gem_object_param *args, + struct create_ext *ext_data) -:95: CHECK:LINE_SPACING: Please don't use multiple blank lines #95: FILE: drivers/gpu/drm/i915/i915_gem.c:317: + + -:107: WARNING:LONG_LINE: line length of 120 exceeds 100 columns #107: FILE: include/uapi/drm/i915_drm.h:395: +#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext) -:155: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #155: FILE: include/uapi/drm/i915_drm.h:1736: +#define I915_OBJECT_PARAM (1ull<<32) ^ total: 3 errors, 2 warnings, 3 checks, 136 lines checked 6e1b59021dc6 drm/i915/pxp: User interface for Protected buffer 36ac68ca392f drm/i915/pxp: Add plane decryption support ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC-v14 05/13] drm/i915/pxp: Func to send hardware session termination
Implement the functions to allow PXP to send a GPU command, in
order to terminate the hardware session, so hardware can recycle
this session slot for the next usage.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 13 ++
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 158 +
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 18 +++
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 4 +
5 files changed, 194 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 2c84f75b41da..abe52189986a 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -259,6 +259,7 @@ i915-y += i915_perf.o
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
pxp/intel_pxp_arb.o \
+ pxp/intel_pxp_cmd.o \
pxp/intel_pxp_context.o \
pxp/intel_pxp_tee.o
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 3868e8c697f9..2f63801748f8 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -17,10 +17,23 @@
void intel_pxp_init(struct intel_pxp *pxp)
{
struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+ int i;
if (INTEL_GEN(gt->i915) < 12)
return;
+ /* Find the first VCS engine present */
+ for (i = 0; i < I915_MAX_VCS; i++) {
+ if (HAS_ENGINE(gt, _VCS(i))) {
+ pxp->vcs_engine = gt->engine[_VCS(i)];
+ break;
+ }
+ }
+ if (!pxp->vcs_engine) {
+ drm_err(>i915->drm, "Could not find a VCS engine\n");
+ return;
+ }
+
intel_pxp_ctx_init(>ctx);
intel_uncore_write(gt->uncore, KCR_INIT,
KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
new file mode 100644
index ..d9298cf5e1a7
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
@@ -0,0 +1,158 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#include "intel_pxp_cmd.h"
+#include "i915_drv.h"
+#include "gt/intel_context.h"
+#include "gt/intel_engine_pm.h"
+
+struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp,
+struct intel_context *ce,
+struct intel_gt_buffer_pool_node *pool,
+u32 *cmd_buf, int cmd_size_in_dw)
+{
+ struct i915_vma *batch = ERR_PTR(-EINVAL);
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+ u32 *cmd;
+
+ if (!ce || !ce->engine || !cmd_buf)
+ return ERR_PTR(-EINVAL);
+
+ if (cmd_size_in_dw * 4 > PAGE_SIZE) {
+ drm_err(>i915->drm, "Failed to %s, invalid
cmd_size_id_dw=[%d]\n",
+ __func__, cmd_size_in_dw);
+ return ERR_PTR(-EINVAL);
+ }
+
+ cmd = i915_gem_object_pin_map(pool->obj, I915_MAP_FORCE_WC);
+ if (IS_ERR(cmd)) {
+ drm_err(>i915->drm, "Failed to
i915_gem_object_pin_map()\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ memcpy(cmd, cmd_buf, cmd_size_in_dw * 4);
+
+ if (drm_debug_enabled(DRM_UT_DRIVER)) {
+ print_hex_dump(KERN_DEBUG, "cmd binaries:",
+ DUMP_PREFIX_OFFSET, 4, 4, cmd, cmd_size_in_dw *
4, true);
+ }
+
+ i915_gem_object_unpin_map(pool->obj);
+
+ batch = i915_vma_instance(pool->obj, ce->vm, NULL);
+ if (IS_ERR(batch)) {
+ drm_err(>i915->drm, "Failed to i915_vma_instance()\n");
+ return batch;
+ }
+
+ return batch;
+}
+
+int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int cmd_size_in_dw)
+{
+ int err = -EINVAL;
+ struct i915_vma *batch;
+ struct i915_request *rq;
+ struct intel_context *ce = NULL;
+ bool is_engine_pm_get = false;
+ bool is_batch_vma_pin = false;
+ bool is_skip_req_on_err = false;
+ bool is_engine_get_pool = false;
+ struct intel_gt_buffer_pool_node *pool = NULL;
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+
+ ce = pxp->vcs_engine->kernel_context;
+ if (!ce) {
+ drm_err(>i915->drm, "VCS engine does not have context\n");
+ err = -EINVAL;
+ goto end;
+ }
+
+ if (!cmd || (cmd_size_in_dw * 4) > PAGE_SIZE) {
+ drm_err(>i915->drm, "Failed to %s bad params\n", __func__);
+ return -EINVAL;
+ }
+
+ intel_engine_pm_get(ce->engine);
+ is_engine_pm_get = true;
+
+ pool = intel_gt_get_buffer_pool(gt,
[Intel-gfx] [RFC-v14 10/13] mei: pxp: export pavp client to me client bus
From: Vitaly Lubart
Export PAVP client to work with i915_cp driver,
for binding it uses kernel component framework.
Signed-off-by: Vitaly Lubart
Signed-off-by: Tomas Winkler
---
drivers/misc/mei/Kconfig | 2 +
drivers/misc/mei/Makefile | 1 +
drivers/misc/mei/pxp/Kconfig | 13 ++
drivers/misc/mei/pxp/Makefile | 7 +
drivers/misc/mei/pxp/mei_pxp.c | 230 +
drivers/misc/mei/pxp/mei_pxp.h | 18 +++
6 files changed, 271 insertions(+)
create mode 100644 drivers/misc/mei/pxp/Kconfig
create mode 100644 drivers/misc/mei/pxp/Makefile
create mode 100644 drivers/misc/mei/pxp/mei_pxp.c
create mode 100644 drivers/misc/mei/pxp/mei_pxp.h
diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig
index f5fd5b786607..0e0bcd0da852 100644
--- a/drivers/misc/mei/Kconfig
+++ b/drivers/misc/mei/Kconfig
@@ -47,3 +47,5 @@ config INTEL_MEI_TXE
Intel Bay Trail
source "drivers/misc/mei/hdcp/Kconfig"
+source "drivers/misc/mei/pxp/Kconfig"
+
diff --git a/drivers/misc/mei/Makefile b/drivers/misc/mei/Makefile
index f1c76f7ee804..d8e5165917f2 100644
--- a/drivers/misc/mei/Makefile
+++ b/drivers/misc/mei/Makefile
@@ -26,3 +26,4 @@ mei-$(CONFIG_EVENT_TRACING) += mei-trace.o
CFLAGS_mei-trace.o = -I$(src)
obj-$(CONFIG_INTEL_MEI_HDCP) += hdcp/
+obj-$(CONFIG_INTEL_MEI_PXP) += pxp/
diff --git a/drivers/misc/mei/pxp/Kconfig b/drivers/misc/mei/pxp/Kconfig
new file mode 100644
index ..4029b96afc04
--- /dev/null
+++ b/drivers/misc/mei/pxp/Kconfig
@@ -0,0 +1,13 @@
+
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
+#
+config INTEL_MEI_PXP
+ tristate "Intel PXP services of ME Interface"
+ select INTEL_MEI_ME
+ depends on DRM_I915
+ help
+ MEI Support for PXP Services on Intel platforms.
+
+ Enables the ME FW services required for PXP support through
+ I915 display driver of Intel.
diff --git a/drivers/misc/mei/pxp/Makefile b/drivers/misc/mei/pxp/Makefile
new file mode 100644
index ..0329950d5794
--- /dev/null
+++ b/drivers/misc/mei/pxp/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
+#
+# Makefile - PXP client driver for Intel MEI Bus Driver.
+
+obj-$(CONFIG_INTEL_MEI_PXP) += mei_pxp.o
diff --git a/drivers/misc/mei/pxp/mei_pxp.c b/drivers/misc/mei/pxp/mei_pxp.c
new file mode 100644
index ..5bd61fe445e3
--- /dev/null
+++ b/drivers/misc/mei/pxp/mei_pxp.c
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+/**
+ * DOC: MEI_PXP Client Driver
+ *
+ * The mei_pxp driver acts as a translation layer between PXP
+ * protocol implementer (I915) and ME FW by translating PXP
+ * negotiation messages to ME FW command payloads and vice versa.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "mei_pxp.h"
+
+/**
+ * mei_pxp_send_message() - Sends a PXP message to ME FW.
+ * @dev: device corresponding to the mei_cl_device
+ * @message: a message buffer to send
+ * @size: size of the message
+ * Return: 0 on Success, <0 on Failure
+ */
+static int
+mei_pxp_send_message(struct device *dev, const void *message, size_t size)
+{
+ struct mei_cl_device *cldev;
+ ssize_t byte;
+
+ if (!dev || !message)
+ return -EINVAL;
+
+ cldev = to_mei_cl_device(dev);
+
+ /* temporary drop const qualifier till the API is fixed */
+ byte = mei_cldev_send(cldev, (u8 *)message, size);
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte);
+ return byte;
+ }
+
+ return 0;
+}
+
+/**
+ * mei_pxp_receive_message() - Receives a PXP message from ME FW.
+ * @dev: device corresponding to the mei_cl_device
+ * @buffer: a message buffer to contain the received message
+ * @size: size of the buffer
+ * Return: bytes sent on Success, <0 on Failure
+ */
+static int
+mei_pxp_receive_message(struct device *dev, void *buffer, size_t size)
+{
+ struct mei_cl_device *cldev;
+ ssize_t byte;
+
+ if (!dev || !buffer)
+ return -EINVAL;
+
+ cldev = to_mei_cl_device(dev);
+
+ byte = mei_cldev_recv(cldev, buffer, size);
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte);
+ return byte;
+ }
+
+ return byte;
+}
+
+static const struct i915_pxp_component_ops mei_pxp_ops = {
+ .owner = THIS_MODULE,
+ .send = mei_pxp_send_message,
+ .receive = mei_pxp_receive_message,
+};
+
+static int mei_component_master_bind(struct device *dev)
+{
+ struct mei_cl_device *cldev = to_mei_cl_device(dev);
+ struct i915_pxp_comp_master *comp_master = mei_cldev_get_drvdata(cldev);
+ int ret;
+
+ dev_dbg(dev, "%s\n", __func__);
+ comp_master->ops = _pxp_ops;
+
[Intel-gfx] [RFC-v14 08/13] drm/i915/pxp: Enable PXP power management
During the power event S3+ sleep/resume, hardware will lose all the
encryption keys for every hardware session, even though the
software session state was marked as alive after resume. So to
handle such case, PXP should terminate all the hardware sessions
and cleanup all the software states after the power cycle.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 ++
drivers/gpu/drm/i915/i915_drv.c| 4 ++
drivers/gpu/drm/i915/pxp/intel_pxp_pm.c| 65 ++
drivers/gpu/drm/i915/pxp/intel_pxp_pm.h| 31 +++
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 1 +
6 files changed, 106 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index abe52189986a..d419dfa4923d 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -261,6 +261,7 @@ i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp_arb.o \
pxp/intel_pxp_cmd.o \
pxp/intel_pxp_context.o \
+ pxp/intel_pxp_pm.o \
pxp/intel_pxp_tee.o
# Post-mortem debug and GPU hang state capture
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index 274aa0dd7050..09a64d0feafe 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -20,6 +20,7 @@
#include "intel_rc6.h"
#include "intel_rps.h"
#include "intel_wakeref.h"
+#include "pxp/intel_pxp_pm.h"
static void user_forcewake(struct intel_gt *gt, bool suspend)
{
@@ -241,6 +242,8 @@ int intel_gt_resume(struct intel_gt *gt)
intel_uc_resume(>uc);
+ intel_pxp_pm_resume(>pxp);
+
user_forcewake(gt, false);
out_fw:
@@ -275,6 +278,7 @@ void intel_gt_suspend_prepare(struct intel_gt *gt)
user_forcewake(gt, true);
wait_for_suspend(gt);
+ intel_pxp_pm_prepare_suspend(>pxp);
intel_uc_suspend(>uc);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9299a456adb0..af06c85e6ba7 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -68,6 +68,8 @@
#include "gt/intel_gt_pm.h"
#include "gt/intel_rc6.h"
+#include "pxp/intel_pxp_pm.h"
+
#include "i915_debugfs.h"
#include "i915_drv.h"
#include "i915_ioc32.h"
@@ -1344,6 +1346,8 @@ static int i915_drm_resume_early(struct drm_device *dev)
intel_power_domains_resume(dev_priv);
+ intel_pxp_pm_resume_early(_priv->gt.pxp);
+
enable_rpm_wakeref_asserts(_priv->runtime_pm);
return ret;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
new file mode 100644
index ..ebe89262485c
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+
+#include "intel_pxp_context.h"
+#include "intel_pxp_arb.h"
+#include "intel_pxp_pm.h"
+
+void intel_pxp_pm_prepare_suspend(struct intel_pxp *pxp)
+{
+ if (!pxp->ctx.inited)
+ return;
+
+ mutex_lock(>ctx.mutex);
+
+ /* Disable PXP-IOCTLs */
+ pxp->ctx.global_state_in_suspend = true;
+
+ mutex_unlock(>ctx.mutex);
+}
+
+void intel_pxp_pm_resume_early(struct intel_pxp *pxp)
+{
+ if (!pxp->ctx.inited)
+ return;
+
+ mutex_lock(>ctx.mutex);
+
+ if (pxp->ctx.global_state_in_suspend) {
+ /* reset the attacked flag even there was a pending */
+ pxp->ctx.global_state_attacked = false;
+
+ pxp->ctx.flag_display_hm_surface_keys = false;
+ }
+
+ mutex_unlock(>ctx.mutex);
+}
+
+int intel_pxp_pm_resume(struct intel_pxp *pxp)
+{
+ int ret = 0;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+
+ if (!pxp->ctx.inited)
+ return 0;
+
+ mutex_lock(>ctx.mutex);
+
+ /* Re-enable PXP-IOCTLs */
+ if (pxp->ctx.global_state_in_suspend) {
+ ret = intel_pxp_arb_terminate_session(pxp);
+ if (ret) {
+ drm_err(>i915->drm, "Failed to terminate the arb
session\n");
+ goto end;
+ }
+
+ pxp->ctx.global_state_in_suspend = false;
+ }
+
+end:
+ mutex_unlock(>ctx.mutex);
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
new file mode 100644
index ..135bfb59aaf7
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_PM_H__
+#define __INTEL_PXP_PM_H__
+
+#include "i915_drv.h"
+
+#ifdef CONFIG_DRM_I915_PXP
+void
[Intel-gfx] [RFC-v14 13/13] drm/i915/pxp: Add plane decryption support
From: Anshuman Gupta
Add support to enable/disable PLANE_SURF Decryption Request bit.
It requires only to enable plane decryption support when following
condition met.
1. PAVP session is enabled.
2. Buffer object is protected.
v2:
- Rebased to libva_cp-drm-tip_tgl_cp tree.
- Used gen fb obj user_flags instead gem_object_metadata. [Krishna]
Cc: Bommu Krishnaiah
Cc: Huang, Sean Z
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_sprite.c | 21 ++---
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index b7e208816074..273bdc031e8d 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -39,6 +39,8 @@
#include
#include
+#include "pxp/intel_pxp.h"
+
#include "i915_drv.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
@@ -767,6 +769,11 @@ icl_program_input_csc(struct intel_plane *plane,
PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
}
+static bool intel_fb_obj_protected(const struct drm_i915_gem_object *obj)
+{
+ return obj->user_flags & I915_BO_PROTECTED ? true : false;
+}
+
static void
skl_plane_async_flip(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
@@ -803,6 +810,7 @@ skl_program_plane(struct intel_plane *plane,
u32 surf_addr = plane_state->color_plane[color_plane].offset;
u32 stride = skl_plane_stride(plane_state, color_plane);
const struct drm_framebuffer *fb = plane_state->hw.fb;
+ const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
int aux_plane = intel_main_to_aux_plane(fb, color_plane);
int crtc_x = plane_state->uapi.dst.x1;
int crtc_y = plane_state->uapi.dst.y1;
@@ -813,7 +821,7 @@ skl_program_plane(struct intel_plane *plane,
u8 alpha = plane_state->hw.alpha >> 8;
u32 plane_color_ctl = 0, aux_dist = 0;
unsigned long irqflags;
- u32 keymsk, keymax;
+ u32 keymsk, keymax, plane_surf;
u32 plane_ctl = plane_state->ctl;
plane_ctl |= skl_plane_ctl_crtc(crtc_state);
@@ -889,8 +897,15 @@ skl_program_plane(struct intel_plane *plane,
* the control register just before the surface register.
*/
intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
- intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
- intel_plane_ggtt_offset(plane_state) + surf_addr);
+ plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
+
+ if (intel_pxp_gem_object_status(dev_priv) &&
+ intel_fb_obj_protected(obj))
+ plane_surf |= PLANE_SURF_DECRYPTION_ENABLED;
+ else
+ plane_surf &= ~PLANE_SURF_DECRYPTION_ENABLED;
+
+ intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf);
if (plane_state->scaler_id >= 0)
skl_program_scaler(plane, crtc_state, plane_state);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1e8dfe435ca8..0ea7e2a402ae 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7209,6 +7209,7 @@ enum {
#define _PLANE_SURF_3(pipe)_PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
#define PLANE_SURF(pipe, plane)\
_MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
+#define PLANE_SURF_DECRYPTION_ENABLEDREG_BIT(2)
#define _PLANE_OFFSET_1_B 0x711a4
#define _PLANE_OFFSET_2_B 0x712a4
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC-v14 09/13] drm/i915/pxp: Expose session state for display protection flip
Implement the intel_pxp_gem_object_status() to allow i915 display
querying the current PXP session state. In the design, display
should not perform protection flip on the protected buffers if
there is no PXP session alive.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 9 +
drivers/gpu/drm/i915/pxp/intel_pxp.h | 8
2 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 23d4cfc1fb1f..72f7d9d966a8 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -158,3 +158,12 @@ void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
pxp->current_events |= events;
schedule_work(>irq_work);
}
+
+bool intel_pxp_gem_object_status(struct drm_i915_private *i915)
+{
+ if (i915->gt.pxp.ctx.inited &&
+ i915->gt.pxp.ctx.flag_display_hm_surface_keys)
+ return true;
+ else
+ return false;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index cdaa6ce6fdca..976baf9b08e3 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -29,6 +29,8 @@ enum pxp_protection_modes {
PROTECTION_MODE_ALL
};
+struct drm_i915_private;
+
#ifdef CONFIG_DRM_I915_PXP
void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir);
int i915_pxp_teardown_required_callback(struct intel_pxp *pxp);
@@ -36,6 +38,7 @@ int i915_pxp_global_terminate_complete_callback(struct
intel_pxp *pxp);
void intel_pxp_init(struct intel_pxp *pxp);
void intel_pxp_fini(struct intel_pxp *pxp);
+bool intel_pxp_gem_object_status(struct drm_i915_private *i915);
#else
static inline void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
{
@@ -58,6 +61,11 @@ static inline void intel_pxp_init(struct intel_pxp *pxp)
static inline void intel_pxp_fini(struct intel_pxp *pxp)
{
}
+
+static inline bool intel_pxp_gem_object_status(struct drm_i915_private *i915)
+{
+ return false;
+}
#endif
#endif /* __INTEL_PXP_H__ */
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC-v14 01/13] drm/i915/pxp: Introduce Intel PXP component
PXP (Protected Xe Path) is an i915 componment, available on GEN12+,
that helps to establish the hardware protected session and manage
the status of the alive software session, as well as its life cycle.
This patch series is to allow the kernel space to create and
manage a single hardware session (a.k.a default session or
arbitrary session). So Mesa can allocate the protected buffer,
which is encrypted with the leverage of the arbitrary hardware
session.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Kconfig | 22 +++
drivers/gpu/drm/i915/Makefile| 5
drivers/gpu/drm/i915/gt/intel_gt.c | 4 +++
drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 ++
drivers/gpu/drm/i915/pxp/intel_pxp.c | 29
drivers/gpu/drm/i915/pxp/intel_pxp.h | 25 +
drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 25 +
drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 15 ++
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 23
9 files changed, 151 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.h
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_types.h
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 1e1cb245fca7..594775c11e19 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -130,6 +130,28 @@ config DRM_I915_GVT_KVMGT
Choose this option if you want to enable KVMGT support for
Intel GVT-g.
+config DRM_I915_PXP
+ bool "Enable Intel PXP support for Intel Gen12+ platform"
+ depends on DRM_I915
+ select INTEL_MEI
+ select INTEL_MEI_ME
+ select INTEL_MEI_TXE
+ select INTEL_MEI_PXP
+ default y
+ help
+ This option selects INTEL_MEI_ME if it isn't already selected to
+ enabled full PXP Services on Intel platforms.
+
+ PXP (Protected Xe Path) is an i915 componment, available on GEN12+,
+ that helps to establish the hardware protected session and manage
+ the status of the alive software session, as well as its life cycle.
+
+ This patch series is to allow the kernel space to create and
+ manage a single hardware session (a.k.a default session or
+ arbitrary session). So Mesa can allocate the protected buffer,
+ which is encrypted with the leverage of the arbitrary hardware
+ session.
+
menu "drm/i915 Debugging"
depends on DRM_I915
depends on EXPERT
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index f9ef5199b124..53be29dbc07d 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -255,6 +255,11 @@ i915-y += \
i915-y += i915_perf.o
+# Protected execution platform (PXP) support
+i915-$(CONFIG_DRM_I915_PXP) += \
+ pxp/intel_pxp.o \
+ pxp/intel_pxp_context.o
+
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
i915-$(CONFIG_DRM_I915_SELFTEST) += \
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 44f1d51e5ae5..d2448be36ded 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -18,6 +18,7 @@
#include "intel_uncore.h"
#include "intel_pm.h"
#include "shmem_utils.h"
+#include "pxp/intel_pxp.h"
void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
{
@@ -584,6 +585,8 @@ int intel_gt_init(struct intel_gt *gt)
if (err)
goto err_gt;
+ intel_pxp_init(>pxp);
+
goto out_fw;
err_gt:
__intel_gt_disable(gt);
@@ -638,6 +641,7 @@ void intel_gt_driver_release(struct intel_gt *gt)
if (vm) /* FIXME being called twice on error paths :( */
i915_vm_put(vm);
+ intel_pxp_fini(>pxp);
intel_gt_pm_fini(gt);
intel_gt_fini_scratch(gt);
intel_gt_fini_buffer_pool(gt);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 6d39a4a11bf3..caa3e1403945 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -23,6 +23,7 @@
#include "intel_rc6_types.h"
#include "intel_rps_types.h"
#include "intel_wakeref.h"
+#include "pxp/intel_pxp_types.h"
struct drm_i915_private;
struct i915_ggtt;
@@ -120,6 +121,8 @@ struct intel_gt {
/* Slice/subslice/EU info */
struct sseu_dev_info sseu;
} info;
+
+ struct intel_pxp pxp;
};
enum intel_gt_scratch_field {
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
new file mode 100644
index ..9bc3c7e30654
--- /dev/null
+++
[Intel-gfx] [RFC-v14 07/13] drm/i915/pxp: Destroy arb session upon teardown
Teardown is triggered when the display topology changes and no
long meets the secure playback requirement, and hardware trashes
all the encryption keys for display. So as a result, PXP should
handle such case and terminate the type0 sessions, which including
arb session
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 3 +
drivers/gpu/drm/i915/pxp/intel_pxp_arb.c | 76 +
drivers/gpu/drm/i915/pxp/intel_pxp_arb.h | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 130 ++-
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 12 ++-
5 files changed, 212 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index fa15e3ad2f92..23d4cfc1fb1f 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -28,6 +28,9 @@ static int intel_pxp_teardown_required_callback(struct
intel_pxp *pxp)
mutex_lock(>ctx.mutex);
pxp->ctx.global_state_attacked = true;
+ pxp->ctx.flag_display_hm_surface_keys = false;
+
+ ret = intel_pxp_arb_terminate_session(pxp);
mutex_unlock(>ctx.mutex);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
index d3da72969349..54a5d7c26e4b 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
@@ -10,6 +10,7 @@
#include "intel_pxp_arb.h"
#include "intel_pxp.h"
#include "intel_pxp_tee.h"
+#include "intel_pxp_cmd.h"
#define GEN12_KCR_SIP _MMIO(0x32260) /* KCR type0 session in play 0-31 */
@@ -131,3 +132,78 @@ int intel_pxp_arb_create_session(struct intel_pxp *pxp)
end:
return ret;
}
+
+static int intel_pxp_arb_session_with_global_termination(struct intel_pxp *pxp)
+{
+ u32 *cmd = NULL;
+ u32 *cmd_ptr = NULL;
+ int cmd_size_in_dw = 0;
+ int ret;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+
+ /* Calculate how many bytes need to be alloc */
+ cmd_size_in_dw += intel_pxp_cmd_add_prolog(pxp, NULL, ARB_SESSION_TYPE,
ARB_SESSION_INDEX);
+ cmd_size_in_dw += intel_pxp_cmd_add_inline_termination(NULL);
+ cmd_size_in_dw += intel_pxp_cmd_add_epilog(NULL);
+
+ cmd = kzalloc(cmd_size_in_dw * 4, GFP_KERNEL);
+ if (!cmd)
+ return -ENOMEM;
+
+ /* Program the command */
+ cmd_ptr = cmd;
+ cmd_ptr += intel_pxp_cmd_add_prolog(pxp, cmd_ptr, ARB_SESSION_TYPE,
ARB_SESSION_INDEX);
+ cmd_ptr += intel_pxp_cmd_add_inline_termination(cmd_ptr);
+ cmd_ptr += intel_pxp_cmd_add_epilog(cmd_ptr);
+
+ if (cmd_size_in_dw != (cmd_ptr - cmd)) {
+ ret = -EINVAL;
+ drm_err(>i915->drm, "Failed to %s\n", __func__);
+ goto end;
+ }
+
+ if (drm_debug_enabled(DRM_UT_DRIVER)) {
+ print_hex_dump(KERN_DEBUG, "global termination cmd binaries:",
+ DUMP_PREFIX_OFFSET, 4, 4, cmd, cmd_size_in_dw *
4, true);
+ }
+
+ ret = intel_pxp_cmd_submit(pxp, cmd, cmd_size_in_dw);
+ if (ret) {
+ drm_err(>i915->drm, "Failed to intel_pxp_cmd_submit()\n");
+ goto end;
+ }
+
+end:
+ kfree(cmd);
+ return ret;
+}
+
+/**
+ * intel_pxp_arb_terminate_session - Terminate the arb hw session and its
entries.
+ * @pxp: pointer to pxp struct.
+ *
+ * This function is NOT intended to be called from the ioctl, and need to be
protected by
+ * ctx.mutex to ensure no SIP change during the call.
+ *
+ * Return: status. 0 means terminate is successful.
+ */
+int intel_pxp_arb_terminate_session(struct intel_pxp *pxp)
+{
+ int ret;
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+ struct pxp_protected_session *arb = >ctx.arb_session;
+
+ lockdep_assert_held(>ctx.mutex);
+
+ /* terminate the hw sessions */
+ ret = intel_pxp_arb_session_with_global_termination(pxp);
+ if (ret) {
+ drm_err(>i915->drm, "Failed to
intel_pxp_arb_session_with_global_termination\n");
+ return ret;
+ }
+
+ arb->is_in_play = false;
+
+ return ret;
+}
+
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
index 1eb8db6deb0e..c1ed4ab176aa 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
@@ -11,5 +11,6 @@
struct intel_pxp;
int intel_pxp_arb_create_session(struct intel_pxp *pxp);
+int intel_pxp_arb_terminate_session(struct intel_pxp *pxp);
#endif /* __INTEL_PXP_ARB_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
index d9298cf5e1a7..ae338ab2e629 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
@@ -5,13 +5,33 @@
#include "intel_pxp_cmd.h"
#include "i915_drv.h"
+#include "gt/intel_gpu_commands.h"
[Intel-gfx] [RFC-v14 04/13] drm/i915/pxp: Create the arbitrary session after boot
Create the arbitrary session, with the fixed session id 0xf, after
system boot, for the case that application allocates the protected
buffer without establishing any protection session. Because the
hardware requires at least one alive session for protected buffer
creation. This arbitrary session needs to be re-created after
teardown or power event because hardware encryption key won't be
valid after such cases.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.h | 16 +++
drivers/gpu/drm/i915/pxp/intel_pxp_arb.c | 133 +++
drivers/gpu/drm/i915/pxp/intel_pxp_arb.h | 15 +++
drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 38 ++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 6 +
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 26
9 files changed, 237 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 57447887d352..2c84f75b41da 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -258,6 +258,7 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
+ pxp/intel_pxp_arb.o \
pxp/intel_pxp_context.o \
pxp/intel_pxp_tee.o
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index c819f3791ee4..3868e8c697f9 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -6,6 +6,7 @@
#include "intel_pxp.h"
#include "intel_pxp_context.h"
#include "intel_pxp_tee.h"
+#include "intel_pxp_arb.h"
/* KCR register definitions */
#define KCR_INIT_MMIO(0x320f0)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index f47bc6bea34f..8fc91e900b16 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -8,6 +8,22 @@
#include "intel_pxp_types.h"
+enum pxp_session_types {
+ SESSION_TYPE_TYPE0 = 0,
+ SESSION_TYPE_TYPE1 = 1,
+
+ SESSION_TYPE_MAX
+};
+
+enum pxp_protection_modes {
+ PROTECTION_MODE_NONE = 0,
+ PROTECTION_MODE_LM = 2,
+ PROTECTION_MODE_HM = 3,
+ PROTECTION_MODE_SM = 6,
+
+ PROTECTION_MODE_ALL
+};
+
#ifdef CONFIG_DRM_I915_PXP
void intel_pxp_init(struct intel_pxp *pxp);
void intel_pxp_fini(struct intel_pxp *pxp);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
new file mode 100644
index ..d3da72969349
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#include "gt/intel_context.h"
+#include "gt/intel_engine_pm.h"
+
+#include "intel_pxp_types.h"
+#include "intel_pxp_arb.h"
+#include "intel_pxp.h"
+#include "intel_pxp_tee.h"
+
+#define GEN12_KCR_SIP _MMIO(0x32260) /* KCR type0 session in play 0-31 */
+
+/* Arbitrary session */
+#define ARB_SESSION_INDEX 0xf
+#define ARB_SESSION_TYPE SESSION_TYPE_TYPE0
+#define ARB_PROTECTION_MODE PROTECTION_MODE_HM
+
+static bool is_hw_arb_session_in_play(struct intel_pxp *pxp)
+{
+ u32 regval_sip = 0;
+ intel_wakeref_t wakeref;
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+
+ with_intel_runtime_pm(>i915->runtime_pm, wakeref) {
+ regval_sip = intel_uncore_read(gt->uncore, GEN12_KCR_SIP);
+ }
+
+ return regval_sip & BIT(ARB_SESSION_INDEX);
+}
+
+/* wait hw session_in_play reg to match the current sw state */
+static int wait_arb_hw_sw_state(struct intel_pxp *pxp)
+{
+ const int max_retry = 10;
+ const int ms_delay = 10;
+ int retry = 0;
+ int ret;
+ struct pxp_protected_session *arb = >ctx.arb_session;
+
+ ret = -EINVAL;
+ for (retry = 0; retry < max_retry; retry++) {
+ if (is_hw_arb_session_in_play(pxp) ==
+ arb->is_in_play) {
+ ret = 0;
+ break;
+ }
+
+ msleep(ms_delay);
+ }
+
+ return ret;
+}
+
+static void arb_session_entry_init(struct intel_pxp *pxp)
+{
+ struct pxp_protected_session *arb = >ctx.arb_session;
+
+ arb->type = ARB_SESSION_TYPE;
+ arb->protection_mode = ARB_PROTECTION_MODE;
+ arb->index = ARB_SESSION_INDEX;
+ arb->is_in_play = false;
+}
+
+int intel_pxp_arb_reserve_session(struct intel_pxp *pxp)
+{
+ int ret;
+
+ lockdep_assert_held(>ctx.mutex);
+
+ arb_session_entry_init(pxp);
+ ret = wait_arb_hw_sw_state(pxp);
+
+ return ret;
+}
+
+/**
+ *
[Intel-gfx] [RFC-v14 02/13] drm/i915/pxp: set KCR reg init during the boot time
Set the KCR init during the boot time, which is
required by hardware, to allow us doing further
protection operation such as sending commands to
GPU or TEE.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 9bc3c7e30654..f566a4fda044 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -6,6 +6,12 @@
#include "intel_pxp.h"
#include "intel_pxp_context.h"
+/* KCR register definitions */
+#define KCR_INIT_MMIO(0x320f0)
+#define KCR_INIT_MASK_SHIFT (16)
+/* Setting KCR Init bit is required after system boot */
+#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) <<
KCR_INIT_MASK_SHIFT))
+
void intel_pxp_init(struct intel_pxp *pxp)
{
struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
@@ -15,6 +21,8 @@ void intel_pxp_init(struct intel_pxp *pxp)
intel_pxp_ctx_init(>ctx);
+ intel_uncore_write(gt->uncore, KCR_INIT,
KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
+
drm_info(>i915->drm, "Protected Xe Path (PXP) protected content
support initialized\n");
}
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC-v14 03/13] drm/i915/pxp: Implement funcs to create the TEE channel
Implement the funcs to create the TEE channel, so kernel can
send the TEE commands directly to TEE for creating the arbitrary
(defualt) session.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile| 3 +-
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 6 ++
drivers/gpu/drm/i915/pxp/intel_pxp.c | 5 +
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 132 +++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 14 +++
include/drm/i915_component.h | 1 +
include/drm/i915_pxp_tee_interface.h | 45
8 files changed, 206 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
create mode 100644 include/drm/i915_pxp_tee_interface.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 53be29dbc07d..57447887d352 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -258,7 +258,8 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
- pxp/intel_pxp_context.o
+ pxp/intel_pxp_context.o \
+ pxp/intel_pxp_tee.o
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5708e11d917b..9299a456adb0 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -322,6 +322,7 @@ static int i915_driver_early_probe(struct drm_i915_private
*dev_priv)
mutex_init(_priv->wm.wm_mutex);
mutex_init(_priv->pps_mutex);
mutex_init(_priv->hdcp_comp_mutex);
+ mutex_init(_priv->pxp_tee_comp_mutex);
i915_memcpy_init_early(dev_priv);
intel_runtime_pm_init_early(_priv->runtime_pm);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c2d0156e8a5d..aaf452115c2f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1212,6 +1212,12 @@ struct drm_i915_private {
/* Mutex to protect the above hdcp component related values. */
struct mutex hdcp_comp_mutex;
+ struct i915_pxp_comp_master *pxp_tee_master;
+ bool pxp_tee_comp_added;
+
+ /* Mutex to protect the above pxp_tee component related values. */
+ struct mutex pxp_tee_comp_mutex;
+
I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
/*
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index f566a4fda044..c819f3791ee4 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -5,6 +5,7 @@
#include "i915_drv.h"
#include "intel_pxp.h"
#include "intel_pxp_context.h"
+#include "intel_pxp_tee.h"
/* KCR register definitions */
#define KCR_INIT_MMIO(0x320f0)
@@ -23,6 +24,8 @@ void intel_pxp_init(struct intel_pxp *pxp)
intel_uncore_write(gt->uncore, KCR_INIT,
KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
+ intel_pxp_tee_component_init(pxp);
+
drm_info(>i915->drm, "Protected Xe Path (PXP) protected content
support initialized\n");
}
@@ -33,5 +36,7 @@ void intel_pxp_fini(struct intel_pxp *pxp)
if (INTEL_GEN(gt->i915) < 12)
return;
+ intel_pxp_tee_component_fini(pxp);
+
intel_pxp_ctx_fini(>ctx);
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
new file mode 100644
index ..ca6b61099aee
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+
+#include
+#include "drm/i915_pxp_tee_interface.h"
+#include "drm/i915_component.h"
+#include "i915_drv.h"
+#include "intel_pxp.h"
+#include "intel_pxp_context.h"
+#include "intel_pxp_tee.h"
+
+static int intel_pxp_tee_io_message(struct intel_pxp *pxp,
+ void *msg_in, u32 msg_in_size,
+ void *msg_out, u32 *msg_out_size_ptr,
+ u32 msg_out_buf_size)
+{
+ int ret;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+ struct drm_i915_private *i915 = gt->i915;
+ struct i915_pxp_comp_master *pxp_tee_master = i915->pxp_tee_master;
+
+ if (!pxp_tee_master || !msg_in || !msg_out || !msg_out_size_ptr)
+ return -EINVAL;
+
+ lockdep_assert_held(>pxp_tee_comp_mutex);
+
+ if (drm_debug_enabled(DRM_UT_DRIVER))
+ print_hex_dump(KERN_DEBUG, "TEE input message binaries:",
+ DUMP_PREFIX_OFFSET, 4, 4, msg_in, msg_in_size,
true);
+
+ ret = pxp_tee_master->ops->send(pxp_tee_master->tee_dev, msg_in,
msg_in_size);
+ if (ret) {
+ drm_err(>drm, "Failed
[Intel-gfx] [RFC-v14 06/13] drm/i915/pxp: Enable PXP irq worker and callback stub
Create the irq worker that serves as callback handler, those
callback stubs should be called while the hardware key teardown
occurs.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 4 +
drivers/gpu/drm/i915/i915_reg.h | 3 +-
drivers/gpu/drm/i915/pxp/intel_pxp.c | 101 +++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 24 -
drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 3 +
drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 1 -
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 6 ++
7 files changed, 139 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index 9830342aa6f4..b92072554ab3 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -14,6 +14,7 @@
#include "intel_lrc_reg.h"
#include "intel_uncore.h"
#include "intel_rps.h"
+#include "pxp/intel_pxp.h"
static void guc_irq_handler(struct intel_guc *guc, u16 iir)
{
@@ -107,6 +108,9 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8
instance,
if (instance == OTHER_GTPM_INSTANCE)
return gen11_rps_irq_handler(>rps, iir);
+ if (instance == OTHER_KCR_INSTANCE)
+ return intel_pxp_irq_handler(>pxp, iir);
+
WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
instance, iir);
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0023c023f472..1e8dfe435ca8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7944,6 +7944,7 @@ enum {
/* irq instances for OTHER_CLASS */
#define OTHER_GUC_INSTANCE 0
#define OTHER_GTPM_INSTANCE1
+#define OTHER_KCR_INSTANCE 4
#define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
@@ -7966,7 +7967,7 @@ enum {
#define GEN11_VECS0_VECS1_INTR_MASK_MMIO(0x1900d0)
#define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8)
#define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec)
-#define GEN11_CRYPTO_RSVD_INTR_MASK_MMIO(0x1900f0)
+#define GEN11_CRYPTO_INTR_MASK _MMIO(0x1900f0) /* crypto mask is in
bit31-16 (Engine1 Interrupt Mask) */
#define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4)
#define ENGINE1_MASK REG_GENMASK(31, 16)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 2f63801748f8..fa15e3ad2f92 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -14,6 +14,70 @@
/* Setting KCR Init bit is required after system boot */
#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) <<
KCR_INIT_MASK_SHIFT))
+static void intel_pxp_write_irq_mask_reg(struct intel_gt *gt, u32 mask)
+{
+ lockdep_assert_held(>irq_lock);
+
+ intel_uncore_write(gt->uncore, GEN11_CRYPTO_INTR_MASK, mask << 16);
+}
+
+static int intel_pxp_teardown_required_callback(struct intel_pxp *pxp)
+{
+ int ret;
+
+ mutex_lock(>ctx.mutex);
+
+ pxp->ctx.global_state_attacked = true;
+
+ mutex_unlock(>ctx.mutex);
+
+ return ret;
+}
+
+static int intel_pxp_global_terminate_complete_callback(struct intel_pxp *pxp)
+{
+ int ret = 0;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+
+ mutex_lock(>ctx.mutex);
+
+ if (pxp->ctx.global_state_attacked) {
+ pxp->ctx.global_state_attacked = false;
+
+ /* Re-create the arb session after teardown handle complete */
+ ret = intel_pxp_arb_create_session(pxp);
+ if (ret) {
+ drm_err(>i915->drm, "Failed to create arb
session\n");
+ goto end;
+ }
+ }
+end:
+ mutex_unlock(>ctx.mutex);
+ return ret;
+}
+
+static void intel_pxp_irq_work(struct work_struct *work)
+{
+ struct intel_pxp *pxp = container_of(work, typeof(*pxp), irq_work);
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+ u32 events = 0;
+
+ spin_lock_irq(>irq_lock);
+ events = fetch_and_zero(>current_events);
+ spin_unlock_irq(>irq_lock);
+
+ if (events & PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED ||
+ events & PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ)
+ intel_pxp_teardown_required_callback(pxp);
+
+ if (events & PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE)
+ intel_pxp_global_terminate_complete_callback(pxp);
+
+ spin_lock_irq(>irq_lock);
+ intel_pxp_write_irq_mask_reg(gt, 0);
+ spin_unlock_irq(>irq_lock);
+}
+
void intel_pxp_init(struct intel_pxp *pxp)
{
struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
@@ -40,6 +104,12 @@ void intel_pxp_init(struct intel_pxp *pxp)
intel_pxp_tee_component_init(pxp);
+ INIT_WORK(>irq_work, intel_pxp_irq_work);
+
+ pxp->handled_irr =
[Intel-gfx] [RFC-v14 12/13] drm/i915/pxp: User interface for Protected buffer
From: Bommu Krishnaiah
This api allow user mode to create Protected buffer and context creation.
Signed-off-by: Bommu Krishnaiah
Cc: Telukuntla Sreedhar
Cc: Kondapally Kalyan
Cc: Gupta Anshuman
Cc: Huang Sean Z
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 15 ++--
drivers/gpu/drm/i915/gem/i915_gem_context.h | 10
.../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +-
.../gpu/drm/i915/gem/i915_gem_object_types.h | 5
drivers/gpu/drm/i915/i915_gem.c | 23 +++
include/uapi/drm/i915_drm.h | 19 +++
6 files changed, 67 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index c7363036765a..12847edec751 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -2019,12 +2019,23 @@ static int ctx_setparam(struct drm_i915_file_private
*fpriv,
case I915_CONTEXT_PARAM_RECOVERABLE:
if (args->size)
ret = -EINVAL;
- else if (args->value)
- i915_gem_context_set_recoverable(ctx);
+ else if (args->value) {
+ if (!i915_gem_context_is_protected(ctx))
+ i915_gem_context_set_recoverable(ctx);
+ else
+ ret = -EPERM;
+ }
else
i915_gem_context_clear_recoverable(ctx);
break;
+ case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
+ if (args->size)
+ ret = -EINVAL;
+ else if (args->value)
+ i915_gem_context_set_protected(ctx);
+ break;
+
case I915_CONTEXT_PARAM_PRIORITY:
ret = set_priority(ctx, args);
break;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h
b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index b5c908f3f4f2..f991e882bbe0 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -70,6 +70,16 @@ static inline void i915_gem_context_set_recoverable(struct
i915_gem_context *ctx
set_bit(UCONTEXT_RECOVERABLE, >user_flags);
}
+static inline void i915_gem_context_set_protected(struct i915_gem_context *ctx)
+{
+ set_bit(UCONTEXT_PROTECTED, >user_flags);
+}
+
+static inline bool i915_gem_context_is_protected(struct i915_gem_context *ctx)
+{
+ return test_bit(UCONTEXT_PROTECTED, >user_flags);
+}
+
static inline void i915_gem_context_clear_recoverable(struct i915_gem_context
*ctx)
{
clear_bit(UCONTEXT_RECOVERABLE, >user_flags);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
index 1449f54924e0..0917c9431c65 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
@@ -134,7 +134,7 @@ struct i915_gem_context {
#define UCONTEXT_BANNABLE 2
#define UCONTEXT_RECOVERABLE 3
#define UCONTEXT_PERSISTENCE 4
-
+#define UCONTEXT_PROTECTED 5
/**
* @flags: small set of booleans
*/
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index e2d9b7e1e152..90ac955463f4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -161,6 +161,11 @@ struct drm_i915_gem_object {
} mmo;
I915_SELFTEST_DECLARE(struct list_head st_link);
+ /**
+* @user_flags: small set of booleans set by the user
+*/
+ unsigned long user_flags;
+#define I915_BO_PROTECTED BIT(0)
unsigned long flags;
#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index c53b13c02e59..611a0b5ab51f 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -184,7 +184,8 @@ static int
i915_gem_create(struct drm_file *file,
struct intel_memory_region *mr,
u64 *size_p,
- u32 *handle_p)
+ u32 *handle_p,
+ u64 user_flags)
{
struct drm_i915_gem_object *obj;
u32 handle;
@@ -204,6 +205,8 @@ i915_gem_create(struct drm_file *file,
if (IS_ERR(obj))
return PTR_ERR(obj);
+ obj->user_flags = user_flags;
+
ret = drm_gem_handle_create(file, >base, );
/* drop reference from allocate - handle holds it now */
i915_gem_object_put(obj);
@@ -258,11 +261,12 @@ i915_gem_dumb_create(struct drm_file *file,
return i915_gem_create(file,
intel_memory_region_by_type(to_i915(dev),
[Intel-gfx] [RFC-v14 11/13] drm/i915/uapi: introduce drm_i915_gem_create_ext
From: Bommu Krishnaiah
Same old gem_create but with now with extensions support. This is needed
to support various upcoming usecases. For now we use the extensions
mechanism to support PAVP.
Signed-off-by: Bommu Krishnaiah
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen joonas.lahti...@linux.intel.com
Cc: Matthew Auld matthew.a...@intel.com
Cc: Telukuntla Sreedhar
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 42 -
include/uapi/drm/i915_drm.h | 47 +
3 files changed, 89 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index af06c85e6ba7..3dbda949bf71 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1733,7 +1733,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop,
DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop,
DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
- DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl,
DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 17a4636ee542..c53b13c02e59 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -53,6 +53,7 @@
#include "i915_drv.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
+#include "i915_user_extensions.h"
#include "intel_pm.h"
@@ -260,6 +261,35 @@ i915_gem_dumb_create(struct drm_file *file,
>size, >handle);
}
+struct create_ext {
+struct drm_i915_private *i915;
+};
+
+static int __create_setparam(struct drm_i915_gem_object_param *args,
+ struct create_ext
*ext_data)
+{
+ if (!(args->param & I915_OBJECT_PARAM)) {
+ DRM_DEBUG("Missing I915_OBJECT_PARAM namespace\n");
+ return -EINVAL;
+ }
+
+ return -EINVAL;
+}
+
+static int create_setparam(struct i915_user_extension __user *base, void *data)
+{
+ struct drm_i915_gem_create_ext_setparam ext;
+
+ if (copy_from_user(, base, sizeof(ext)))
+ return -EFAULT;
+
+ return __create_setparam(, data);
+}
+
+static const i915_user_extension_fn create_extensions[] = {
+ [I915_GEM_CREATE_EXT_SETPARAM] = create_setparam,
+};
+
/**
* Creates a new mm object and returns a handle to it.
* @dev: drm device pointer
@@ -271,10 +301,20 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
{
struct drm_i915_private *i915 = to_i915(dev);
- struct drm_i915_gem_create *args = data;
+ struct create_ext ext_data = { .i915 = i915 };
+ struct drm_i915_gem_create_ext *args = data;
+ int ret;
i915_gem_flush_free_objects(i915);
+ ret = i915_user_extensions(u64_to_user_ptr(args->extensions),
+ create_extensions,
+ ARRAY_SIZE(create_extensions),
+ _data);
+ if (ret)
+ return ret;
+
+
return i915_gem_create(file,
intel_memory_region_by_type(i915,
INTEL_MEMORY_SYSTEM),
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 6edcb2b6c708..e918ccc81c74 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -391,6 +391,7 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE +
DRM_I915_GEM_ENTERVT)
#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE +
DRM_I915_GEM_LEAVEVT)
#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
+#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext)
#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE +
DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE +
DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
#define DRM_IOCTL_I915_GEM_MMAPDRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
@@ -728,6 +729,27 @@ struct drm_i915_gem_create {
__u32 pad;
};
+struct drm_i915_gem_create_ext {
+ /**
+* Requested size for the object.
+*
+
[Intel-gfx] [RFC-v14 00/13] Introduce Intel PXP component - Mesa single session
PXP (Protected Xe Path) is an i915 component, available on GEN12+ that helps to establish the hardware protected session and manage the status of the alive software session, as well as its life cycle. This patch series is to allow the kernel space to create and manage a single hardware session (a.k.a. default session or arbitrary session). So user can allocate the protected buffer, which is encrypted with the leverage of the arbitrary hardware session. v2: - modification based on code review feedbacks received - passing pxp instead of i915 as function argument - remove dead code only for multi-session - move the pxp init call from i915_drv.c to intel_gt.c - remove the tautology naming v3: - rebase to latest drm-tip v4: - Append the split non-mesa patch sereis (commit #14 - #21) into this patch series v5: - include "intel_pxp.h" in intel_pxp_sm.h at commit #14 to fix the build problem. v6: - Fix the null pointer arb_session access bug in intel_pxp_arb.c in "04 [RFC-v5] drm/i915/pxp: Create the arbitrary session after boot" v7: - Use list_for_each_entry_safe instead of list_for_each_entry v8: - Add MEI vtag support for PXP multi-session usage v9: - Fix error handling bug in commit #5 "Func to send hardware session termination". In intel_pxp_cmd.c, we should properly assign "err = PTR_ERR(x)" if hitting the error case "IS_ERR(x)", this is the only change in v9. v10 - Remove the multi session commits #14-#21, for now we would like to keep the multi session patches as downstream. - Adopt the code review suggestion from Wilson in commit #1 v11 - In commit #05 "drm/i915/pxp: Func to send hardware session termination", we should not assume VCS0 is always on. Instead we use available VCS#, could be VCS0, VCS2, etc. v12 - Add "#include in #1 intel_pxp_types.h v13 - Add "#include in #1 intel_pxp_types.h (#v12 didn't actually update the _types.h file...) v14 - Add "if (INTEL_GEN(gt->i915) < 12) return;" in #1 intel_pxp_fini(), just skip for non gen12+ Anshuman Gupta (1): drm/i915/pxp: Add plane decryption support Bommu Krishnaiah (2): drm/i915/uapi: introduce drm_i915_gem_create_ext drm/i915/pxp: User interface for Protected buffer Huang, Sean Z (9): drm/i915/pxp: Introduce Intel PXP component drm/i915/pxp: set KCR reg init during the boot time drm/i915/pxp: Implement funcs to create the TEE channel drm/i915/pxp: Create the arbitrary session after boot drm/i915/pxp: Func to send hardware session termination drm/i915/pxp: Enable PXP irq worker and callback stub drm/i915/pxp: Destroy arb session upon teardown drm/i915/pxp: Enable PXP power management drm/i915/pxp: Expose session state for display protection flip Vitaly Lubart (1): mei: pxp: export pavp client to me client bus drivers/gpu/drm/i915/Kconfig | 22 ++ drivers/gpu/drm/i915/Makefile | 9 + drivers/gpu/drm/i915/display/intel_sprite.c | 21 +- drivers/gpu/drm/i915/gem/i915_gem_context.c | 15 +- drivers/gpu/drm/i915/gem/i915_gem_context.h | 10 + .../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +- .../gpu/drm/i915/gem/i915_gem_object_types.h | 5 + drivers/gpu/drm/i915/gt/intel_gt.c| 4 + drivers/gpu/drm/i915/gt/intel_gt_irq.c| 4 + drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 + drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 + drivers/gpu/drm/i915/i915_drv.c | 7 +- drivers/gpu/drm/i915/i915_drv.h | 6 + drivers/gpu/drm/i915/i915_gem.c | 63 +++- drivers/gpu/drm/i915/i915_reg.h | 4 +- drivers/gpu/drm/i915/pxp/intel_pxp.c | 169 +++ drivers/gpu/drm/i915/pxp/intel_pxp.h | 71 + drivers/gpu/drm/i915/pxp/intel_pxp_arb.c | 209 + drivers/gpu/drm/i915/pxp/intel_pxp_arb.h | 16 + drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 278 ++ drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 20 ++ drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 28 ++ drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 15 + drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 65 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 31 ++ drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 170 +++ drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 20 ++ drivers/gpu/drm/i915/pxp/intel_pxp_types.h| 60 drivers/misc/mei/Kconfig | 2 + drivers/misc/mei/Makefile | 1 + drivers/misc/mei/pxp/Kconfig | 13 + drivers/misc/mei/pxp/Makefile | 7 + drivers/misc/mei/pxp/mei_pxp.c| 230 +++ drivers/misc/mei/pxp/mei_pxp.h| 18 ++ include/drm/i915_component.h | 1 + include/drm/i915_pxp_tee_interface.h | 45 +++
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/5] drm/i915/display: move needs_modeset to an inline in header (rev3)
== Series Details == Series: series starting with [CI,1/5] drm/i915/display: move needs_modeset to an inline in header (rev3) URL : https://patchwork.freedesktop.org/series/85132/ State : success == Summary == CI Bug Log - changes from CI_DRM_9509 -> Patchwork_19193 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19193/index.html Known issues Here are the changes found in Patchwork_19193 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_cs_nop@fork-compute0: - fi-tgl-u2: NOTRUN -> [SKIP][1] ([fdo#109315] / [i915#2575]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19193/fi-tgl-u2/igt@amdgpu/amd_cs_...@fork-compute0.html * igt@gem_exec_gttfill@basic: - fi-tgl-y: [PASS][2] -> [DMESG-WARN][3] ([i915#402]) +2 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/fi-tgl-y/igt@gem_exec_gttf...@basic.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19193/fi-tgl-y/igt@gem_exec_gttf...@basic.html Possible fixes * igt@gem_tiled_blits@basic: - fi-tgl-y: [DMESG-WARN][4] ([i915#402]) -> [PASS][5] +2 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/fi-tgl-y/igt@gem_tiled_bl...@basic.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19193/fi-tgl-y/igt@gem_tiled_bl...@basic.html * igt@i915_selftest@live@hangcheck: - fi-tgl-u2: [INCOMPLETE][6] -> [PASS][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/fi-tgl-u2/igt@i915_selftest@l...@hangcheck.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19193/fi-tgl-u2/igt@i915_selftest@l...@hangcheck.html * igt@kms_chamelium@dp-edid-read: - fi-cml-u2: [FAIL][8] ([i915#2679]) -> [PASS][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/fi-cml-u2/igt@kms_chamel...@dp-edid-read.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19193/fi-cml-u2/igt@kms_chamel...@dp-edid-read.html [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575 [i915#2679]: https://gitlab.freedesktop.org/drm/intel/issues/2679 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (42 -> 37) -- Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-bsw-nick fi-bdw-samus Build changes - * Linux: CI_DRM_9509 -> Patchwork_19193 CI-20190529: 20190529 CI_DRM_9509: 66ecfb1df07b703dc4e83e8c520b186dffe6d2b3 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5913: b30bdfecaf1ff38b83c0bfbcf5981732a968a464 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19193: a759b1ea292e30f7d50c2f2aec7cb3d26a5be52b @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == a759b1ea292e drm/i915: refactor i915 plane code into separate file. 864517beaa0c drm/i915: refactor cursor code out of i915_display.c 9b2022983792 drm/i915/display: fix misused comma da73a1c19031 drm/i915/display: move to_intel_frontbuffer to header e8060d01a918 drm/i915/display: move needs_modeset to an inline in header == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19193/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/5] drm/i915/display: move needs_modeset to an inline in header (rev3)
== Series Details == Series: series starting with [CI,1/5] drm/i915/display: move needs_modeset to an inline in header (rev3) URL : https://patchwork.freedesktop.org/series/85132/ State : warning == Summary == $ dim checkpatch origin/drm-tip e8060d01a918 drm/i915/display: move needs_modeset to an inline in header da73a1c19031 drm/i915/display: move to_intel_frontbuffer to header 9b2022983792 drm/i915/display: fix misused comma 864517beaa0c drm/i915: refactor cursor code out of i915_display.c -:30: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #30: new file mode 100644 -:529: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned' #529: FILE: drivers/gpu/drm/i915/display/intel_cursor.c:495: + unsigned width = drm_rect_width(_state->uapi.dst); -:530: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned' #530: FILE: drivers/gpu/drm/i915/display/intel_cursor.c:496: + unsigned height = drm_rect_height(_state->uapi.dst); -:559: WARNING:REPEATED_WORD: Possible repeated word: 'by' #559: FILE: drivers/gpu/drm/i915/display/intel_cursor.c:525: +* The other registers are armed by by the CURBASE write -:786: CHECK:SPACING: No space is necessary after a cast #786: FILE: drivers/gpu/drm/i915/display/intel_cursor.c:752: + cursor->i9xx_plane = (enum i9xx_plane_id) pipe; total: 0 errors, 4 warnings, 1 checks, 1700 lines checked a759b1ea292e drm/i915: refactor i915 plane code into separate file. -:32: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #32: new file mode 100644 -:570: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #570: FILE: drivers/gpu/drm/i915/display/i9xx_plane.c:534: + return 32*1024; ^ -:573: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #573: FILE: drivers/gpu/drm/i915/display/i9xx_plane.c:537: + return 16*1024; ^ -:575: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #575: FILE: drivers/gpu/drm/i915/display/i9xx_plane.c:539: + return 32*1024; ^ -:578: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #578: FILE: drivers/gpu/drm/i915/display/i9xx_plane.c:542: + return 8*1024; ^ -:580: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #580: FILE: drivers/gpu/drm/i915/display/i9xx_plane.c:544: + return 16*1024; ^ -:583: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #583: FILE: drivers/gpu/drm/i915/display/i9xx_plane.c:547: + return 4*1024; ^ -:585: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #585: FILE: drivers/gpu/drm/i915/display/i9xx_plane.c:549: + return 8*1024; ^ -:632: CHECK:SPACING: No space is necessary after a cast #632: FILE: drivers/gpu/drm/i915/display/i9xx_plane.c:596: + plane->i9xx_plane = (enum i9xx_plane_id) !pipe; -:634: CHECK:SPACING: No space is necessary after a cast #634: FILE: drivers/gpu/drm/i915/display/i9xx_plane.c:598: + plane->i9xx_plane = (enum i9xx_plane_id) pipe; total: 0 errors, 1 warnings, 9 checks, 1462 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] i915/gem_exec_fair: Try to spot unfairness
An important property for multi-client systems is that each client gets
a 'fair' allotment of system time. (Where fairness is at the whim of the
context properties, such as priorities.) This test forks N independent
clients (albeit they happen to share a single vm), and does an equal
amount of work in client and asserts that they take an equal amount of
time.
Though we have never claimed to have a completely fair scheduler, that
is what is expected.
v2: igt_assert_f and more commentary; exclude vip from client stats,
include range of frame intervals from each individual client
v3: Write down what the test actually does!
v4: Split out to gem_exec_fair so that we can apply CI filtering to
reduce the test set
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Ramalingam C
---
tests/Makefile.sources | 3 +
tests/i915/gem_exec_fair.c | 916 +++
tests/intel-ci/blacklist.txt | 1 +
tests/meson.build| 1 +
4 files changed, 921 insertions(+)
create mode 100644 tests/i915/gem_exec_fair.c
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index d9c8f6104..db2be6a17 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -275,6 +275,9 @@ gem_exec_reloc_SOURCES = i915/gem_exec_reloc.c
TESTS_progs += gem_exec_schedule
gem_exec_schedule_SOURCES = i915/gem_exec_schedule.c
+TESTS_progs += gem_exec_fair
+gem_exec_fair_SOURCES = i915/gem_exec_fair.c
+
TESTS_progs += gem_exec_store
gem_exec_store_SOURCES = i915/gem_exec_store.c
diff --git a/tests/i915/gem_exec_fair.c b/tests/i915/gem_exec_fair.c
new file mode 100644
index 0..cc8e3962d
--- /dev/null
+++ b/tests/i915/gem_exec_fair.c
@@ -0,0 +1,916 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2016 Intel Corporation
+ */
+
+#include "config.h"
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "i915/gem.h"
+#include "i915/gem_ring.h"
+#include "igt.h"
+#include "igt_rand.h"
+#include "igt_rapl.h"
+#include "igt_sysfs.h"
+#include "igt_vgem.h"
+#include "sw_sync.h"
+
+IGT_TEST_DESCRIPTION("Check that GPU time and execution order is fairly
distributed across clients");
+
+#define NSEC64 ((uint64_t)NSEC_PER_SEC)
+
+static unsigned int offset_in_page(void *addr)
+{
+ return (uintptr_t)addr & 4095;
+}
+
+static uint32_t __batch_create(int i915, uint32_t offset)
+{
+ const uint32_t bbe = MI_BATCH_BUFFER_END;
+ uint32_t handle;
+
+ handle = gem_create(i915, ALIGN(offset + 4, 4096));
+ gem_write(i915, handle, offset, , sizeof(bbe));
+
+ return handle;
+}
+
+static uint32_t batch_create(int i915)
+{
+ return __batch_create(i915, 0);
+}
+
+static int read_timestamp_frequency(int i915)
+{
+ int value = 0;
+ drm_i915_getparam_t gp = {
+ .value = ,
+ .param = I915_PARAM_CS_TIMESTAMP_FREQUENCY,
+ };
+ ioctl(i915, DRM_IOCTL_I915_GETPARAM, );
+ return value;
+}
+
+static uint64_t div64_u64_round_up(uint64_t x, uint64_t y)
+{
+ return (x + y - 1) / y;
+}
+
+static uint64_t ns_to_ctx_ticks(int i915, uint64_t ns)
+{
+ int f = read_timestamp_frequency(i915);
+ if (intel_gen(intel_get_drm_devid(i915)) == 11)
+ f = 1250; /* icl!!! are you feeling alright? CTX vs CS */
+ return div64_u64_round_up(ns * f, NSEC64);
+}
+
+static uint64_t ticks_to_ns(int i915, uint64_t ticks)
+{
+ return div64_u64_round_up(ticks * NSEC64,
+ read_timestamp_frequency(i915));
+}
+
+#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
+
+#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
+#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
+/* Opcodes for MI_MATH_INSTR */
+#define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0)
+#define MI_MATH_LOAD(op1, op2)MI_MATH_INSTR(0x080, op1, op2)
+#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2)
+#define MI_MATH_LOAD0(op1)MI_MATH_INSTR(0x081, op1)
+#define MI_MATH_LOAD1(op1)MI_MATH_INSTR(0x481, op1)
+#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0)
+#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0)
+#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0)
+#define MI_MATH_ORMI_MATH_INSTR(0x103, 0x0, 0x0)
+#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0)
+#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2)
+#define MI_MATH_STOREINV(op1, op2)MI_MATH_INSTR(0x580, op1, op2)
+/* Registers used as operands in MI_MATH_INSTR */
+#define MI_MATH_REG(x)(x)
+#define MI_MATH_REG_SRCA 0x20
+#define MI_MATH_REG_SRCB 0x21
+#define MI_MATH_REG_ACCU 0x31
+#define MI_MATH_REG_ZF0x32
+#define MI_MATH_REG_CF
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Add a comment about how to use udev for configuring engines (rev2)
== Series Details == Series: drm/i915/gt: Add a comment about how to use udev for configuring engines (rev2) URL : https://patchwork.freedesktop.org/series/84578/ State : success == Summary == CI Bug Log - changes from CI_DRM_9509_full -> Patchwork_19192_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_19192_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_reloc@basic-wide-active@vcs1: - shard-iclb: NOTRUN -> [FAIL][1] ([i915#2389]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19192/shard-iclb2/igt@gem_exec_reloc@basic-wide-act...@vcs1.html * igt@gem_exec_whisper@basic-queues-forked: - shard-glk: [PASS][2] -> [DMESG-WARN][3] ([i915#118] / [i915#95]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/shard-glk8/igt@gem_exec_whis...@basic-queues-forked.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19192/shard-glk8/igt@gem_exec_whis...@basic-queues-forked.html * igt@kms_async_flips@alternate-sync-async-flip: - shard-skl: [PASS][4] -> [FAIL][5] ([i915#2521]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/shard-skl9/igt@kms_async_fl...@alternate-sync-async-flip.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19192/shard-skl8/igt@kms_async_fl...@alternate-sync-async-flip.html * igt@kms_color_chamelium@pipe-c-degamma: - shard-skl: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +4 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19192/shard-skl6/igt@kms_color_chamel...@pipe-c-degamma.html * igt@kms_cursor_crc@pipe-b-cursor-256x256-random: - shard-skl: [PASS][7] -> [FAIL][8] ([i915#54]) +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/shard-skl5/igt@kms_cursor_...@pipe-b-cursor-256x256-random.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19192/shard-skl7/igt@kms_cursor_...@pipe-b-cursor-256x256-random.html * igt@kms_flip@flip-vs-expired-vblank@b-edp1: - shard-skl: [PASS][9] -> [FAIL][10] ([i915#79]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/shard-skl3/igt@kms_flip@flip-vs-expired-vbl...@b-edp1.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19192/shard-skl1/igt@kms_flip@flip-vs-expired-vbl...@b-edp1.html * igt@kms_flip@flip-vs-suspend@a-dp1: - shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([i915#180]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/shard-kbl6/igt@kms_flip@flip-vs-susp...@a-dp1.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19192/shard-kbl2/igt@kms_flip@flip-vs-susp...@a-dp1.html * igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1: - shard-skl: [PASS][13] -> [FAIL][14] ([i915#2122]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/shard-skl9/igt@kms_flip@plain-flip-ts-check-interrupti...@c-edp1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19192/shard-skl9/igt@kms_flip@plain-flip-ts-check-interrupti...@c-edp1.html * igt@kms_flip@plain-flip-ts-check@a-hdmi-a1: - shard-glk: [PASS][15] -> [FAIL][16] ([i915#2122]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/shard-glk6/igt@kms_flip@plain-flip-ts-ch...@a-hdmi-a1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19192/shard-glk7/igt@kms_flip@plain-flip-ts-ch...@a-hdmi-a1.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt: - shard-skl: NOTRUN -> [SKIP][17] ([fdo#109271]) +29 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19192/shard-skl6/igt@kms_frontbuffer_track...@fbc-2p-scndscrn-pri-indfb-draw-blt.html * igt@kms_hdr@bpc-switch-dpms: - shard-skl: [PASS][18] -> [FAIL][19] ([i915#1188]) +1 similar issue [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/shard-skl10/igt@kms_...@bpc-switch-dpms.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19192/shard-skl2/igt@kms_...@bpc-switch-dpms.html * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-skl: NOTRUN -> [FAIL][20] ([fdo#108145] / [i915#265]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19192/shard-skl10/igt@kms_plane_alpha_bl...@pipe-b-constant-alpha-min.html * igt@kms_psr@psr2_sprite_plane_move: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19192/shard-iclb5/igt@kms_psr@psr2_sprite_plane_move.html Possible fixes * igt@gem_eio@in-flight-suspend: - shard-skl:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Add a comment about how to use udev for configuring engines (rev2)
== Series Details == Series: drm/i915/gt: Add a comment about how to use udev for configuring engines (rev2) URL : https://patchwork.freedesktop.org/series/84578/ State : success == Summary == CI Bug Log - changes from CI_DRM_9509 -> Patchwork_19192 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19192/index.html Known issues Here are the changes found in Patchwork_19192 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_cs_nop@fork-compute0: - fi-tgl-u2: NOTRUN -> [SKIP][1] ([fdo#109315] / [i915#2575]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19192/fi-tgl-u2/igt@amdgpu/amd_cs_...@fork-compute0.html * igt@gem_exec_suspend@basic-s3: - fi-tgl-y: [PASS][2] -> [DMESG-WARN][3] ([i915#2411] / [i915#402]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19192/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html * igt@i915_selftest@live@gt_heartbeat: - fi-kbl-soraka: [PASS][4] -> [DMESG-FAIL][5] ([i915#2291] / [i915#541]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19192/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html * igt@vgem_basic@setversion: - fi-tgl-y: [PASS][6] -> [DMESG-WARN][7] ([i915#402]) +1 similar issue [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/fi-tgl-y/igt@vgem_ba...@setversion.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19192/fi-tgl-y/igt@vgem_ba...@setversion.html Possible fixes * igt@gem_tiled_blits@basic: - fi-tgl-y: [DMESG-WARN][8] ([i915#402]) -> [PASS][9] +2 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/fi-tgl-y/igt@gem_tiled_bl...@basic.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19192/fi-tgl-y/igt@gem_tiled_bl...@basic.html * igt@i915_selftest@live@hangcheck: - fi-tgl-u2: [INCOMPLETE][10] -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/fi-tgl-u2/igt@i915_selftest@l...@hangcheck.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19192/fi-tgl-u2/igt@i915_selftest@l...@hangcheck.html * igt@kms_chamelium@dp-edid-read: - fi-cml-u2: [FAIL][12] ([i915#2679]) -> [PASS][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/fi-cml-u2/igt@kms_chamel...@dp-edid-read.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19192/fi-cml-u2/igt@kms_chamel...@dp-edid-read.html [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291 [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411 [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575 [i915#2679]: https://gitlab.freedesktop.org/drm/intel/issues/2679 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541 Participating hosts (42 -> 38) -- Missing(4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u Build changes - * Linux: CI_DRM_9509 -> Patchwork_19192 CI-20190529: 20190529 CI_DRM_9509: 66ecfb1df07b703dc4e83e8c520b186dffe6d2b3 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5913: b30bdfecaf1ff38b83c0bfbcf5981732a968a464 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19192: 0ff0eef96366bab3b72ac5d7b8ef63d2e59feb82 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 0ff0eef96366 drm/i915/gt: Add a comment about how to use udev for configuring engines == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19192/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,1/5] drm/i915/display: move needs_modeset to an inline in header (rev2)
== Series Details == Series: series starting with [CI,1/5] drm/i915/display: move needs_modeset to an inline in header (rev2) URL : https://patchwork.freedesktop.org/series/85132/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9509_full -> Patchwork_19191_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19191_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19191_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19191_full: ### IGT changes ### Possible regressions * igt@gem_exec_whisper@basic-forked: - shard-iclb: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/shard-iclb5/igt@gem_exec_whis...@basic-forked.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19191/shard-iclb2/igt@gem_exec_whis...@basic-forked.html * igt@i915_selftest@live@hugepages: - shard-skl: [PASS][3] -> [DMESG-WARN][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/shard-skl3/igt@i915_selftest@l...@hugepages.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19191/shard-skl8/igt@i915_selftest@l...@hugepages.html * igt@kms_cursor_legacy@cursor-vs-flip-legacy: - shard-hsw: [PASS][5] -> [INCOMPLETE][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/shard-hsw8/igt@kms_cursor_leg...@cursor-vs-flip-legacy.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19191/shard-hsw8/igt@kms_cursor_leg...@cursor-vs-flip-legacy.html * igt@kms_flip@basic-flip-vs-wf_vblank: - shard-iclb: NOTRUN -> [SKIP][7] +4 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19191/shard-iclb2/igt@kms_flip@basic-flip-vs-wf_vblank.html * igt@syncobj_wait@invalid-wait-bad-flags: - shard-iclb: [PASS][8] -> [SKIP][9] +19 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/shard-iclb5/igt@syncobj_w...@invalid-wait-bad-flags.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19191/shard-iclb2/igt@syncobj_w...@invalid-wait-bad-flags.html Warnings * igt@i915_pm_rpm@modeset-non-lpsp: - shard-iclb: [SKIP][10] ([fdo#110892]) -> [SKIP][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/shard-iclb5/igt@i915_pm_...@modeset-non-lpsp.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19191/shard-iclb2/igt@i915_pm_...@modeset-non-lpsp.html * igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes: - shard-iclb: [SKIP][12] ([fdo#109284] / [fdo#111827]) -> [SKIP][13] +2 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/shard-iclb5/igt@kms_color_chamel...@pipe-invalid-ctm-matrix-sizes.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19191/shard-iclb2/igt@kms_color_chamel...@pipe-invalid-ctm-matrix-sizes.html * igt@kms_cursor_legacy@cursora-vs-flipb-toggle: - shard-iclb: [SKIP][14] ([fdo#109274] / [fdo#109278]) -> [SKIP][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/shard-iclb5/igt@kms_cursor_leg...@cursora-vs-flipb-toggle.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19191/shard-iclb2/igt@kms_cursor_leg...@cursora-vs-flipb-toggle.html * igt@kms_dp_tiled_display@basic-test-pattern: - shard-iclb: [SKIP][16] ([i915#426]) -> [SKIP][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/shard-iclb5/igt@kms_dp_tiled_disp...@basic-test-pattern.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19191/shard-iclb2/igt@kms_dp_tiled_disp...@basic-test-pattern.html Known issues Here are the changes found in Patchwork_19191_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@legacy-engines-cleanup: - shard-hsw: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#1099]) +1 similar issue [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19191/shard-hsw1/igt@gem_ctx_persiste...@legacy-engines-cleanup.html * igt@gem_ctx_persistence@processes: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109315]) +21 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/shard-iclb5/igt@gem_ctx_persiste...@processes.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19191/shard-iclb2/igt@gem_ctx_persiste...@processes.html * igt@gem_exec_capture@pi@rcs0: - shard-skl: [PASS][21] -> [INCOMPLETE][22] ([i915#2369]) [21]:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Add a comment about how to use udev for configuring engines (rev2)
== Series Details == Series: drm/i915/gt: Add a comment about how to use udev for configuring engines (rev2) URL : https://patchwork.freedesktop.org/series/84578/ State : warning == Summary == $ dim checkpatch origin/drm-tip 0ff0eef96366 drm/i915/gt: Add a comment about how to use udev for configuring engines -:33: WARNING:LONG_LINE_COMMENT: line length of 111 exceeds 100 columns #33: FILE: drivers/gpu/drm/i915/gt/sysfs_engines.c:22: + * ACTION=="bind|add",SUBSYSTEM=="pci",DRIVER=="i915",RUN+="/usr/local/libexec/i915-disable-preempt-timeout.sh" total: 0 errors, 1 warnings, 0 checks, 22 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] Does the intel driver support faking a connected monitor?
On Sun, 20 Dec 2020, Paul Gardiner wrote: > The debug output was sufficient to track down the problem. It turned out > that the connection was called HDMI-A-1. When I used that name your > previous suggestion worked. To get exactly the behaviour I wanted I > needed to also load EDID. This is the extra boot command string I'm using: > > drm.edid_firmware=HDMI-A-1:edid/marantz_edid.bin video=HDMI-A-1:D > > > For that to work I also had to ensure the referenced edid file was in my > initramfs. > > Thanks again for the help. I'm glad you figured it out, and thanks for letting us know! > By the way, an EDID emulator is a small USB-stick-sized device that sits > in between computer and monitor and acts like a monitor when the actual > monitor is off. Ah, thanks for the info. BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v8,1/2] drm/i915/display: Support PSR Multiple Transcoders
== Series Details == Series: series starting with [v8,1/2] drm/i915/display: Support PSR Multiple Transcoders URL : https://patchwork.freedesktop.org/series/85136/ State : success == Summary == CI Bug Log - changes from CI_DRM_9509_full -> Patchwork_19190_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_19190_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@legacy-engines-cleanup: - shard-hsw: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19190/shard-hsw4/igt@gem_ctx_persiste...@legacy-engines-cleanup.html * igt@gem_fenced_exec_thrash@2-spare-fences: - shard-snb: [PASS][2] -> [INCOMPLETE][3] ([i915#2055]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/shard-snb2/igt@gem_fenced_exec_thr...@2-spare-fences.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19190/shard-snb5/igt@gem_fenced_exec_thr...@2-spare-fences.html * igt@kms_big_fb@y-tiled-addfb-size-overflow: - shard-hsw: NOTRUN -> [SKIP][4] ([fdo#109271]) +64 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19190/shard-hsw4/igt@kms_big...@y-tiled-addfb-size-overflow.html * igt@kms_chamelium@hdmi-hpd-enable-disable-mode: - shard-hsw: NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +6 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19190/shard-hsw4/igt@kms_chamel...@hdmi-hpd-enable-disable-mode.html * igt@kms_color_chamelium@pipe-c-degamma: - shard-skl: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +2 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19190/shard-skl3/igt@kms_color_chamel...@pipe-c-degamma.html * igt@kms_cursor_crc@pipe-b-cursor-suspend: - shard-skl: [PASS][7] -> [FAIL][8] ([i915#54]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/shard-skl8/igt@kms_cursor_...@pipe-b-cursor-suspend.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19190/shard-skl9/igt@kms_cursor_...@pipe-b-cursor-suspend.html * igt@kms_flip@2x-flip-vs-suspend-interruptible@bc-vga1-hdmi-a1: - shard-hsw: [PASS][9] -> [INCOMPLETE][10] ([i915#2055]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/shard-hsw8/igt@kms_flip@2x-flip-vs-suspend-interrupti...@bc-vga1-hdmi-a1.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19190/shard-hsw1/igt@kms_flip@2x-flip-vs-suspend-interrupti...@bc-vga1-hdmi-a1.html * igt@kms_flip@flip-vs-expired-vblank@a-edp1: - shard-skl: [PASS][11] -> [FAIL][12] ([i915#2122]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/shard-skl3/igt@kms_flip@flip-vs-expired-vbl...@a-edp1.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19190/shard-skl3/igt@kms_flip@flip-vs-expired-vbl...@a-edp1.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt: - shard-skl: NOTRUN -> [SKIP][13] ([fdo#109271]) +11 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19190/shard-skl3/igt@kms_frontbuffer_track...@fbc-2p-scndscrn-pri-indfb-draw-blt.html * igt@kms_hdr@bpc-switch-dpms: - shard-skl: [PASS][14] -> [FAIL][15] ([i915#1188]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/shard-skl10/igt@kms_...@bpc-switch-dpms.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19190/shard-skl1/igt@kms_...@bpc-switch-dpms.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-kbl: [PASS][16] -> [DMESG-WARN][17] ([i915#180] / [i915#533]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/shard-kbl7/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19190/shard-kbl3/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][18] -> [FAIL][19] ([fdo#108145] / [i915#265]) +1 similar issue [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/shard-skl9/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19190/shard-skl2/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html * igt@kms_psr@psr2_sprite_plane_move: - shard-iclb: [PASS][20] -> [SKIP][21] ([fdo#109441]) +2 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19190/shard-iclb3/igt@kms_psr@psr2_sprite_plane_move.html * igt@perf@polling-parameterized:
[Intel-gfx] [PATCH] drm/i915/gt: Add a comment about how to use udev for configuring engines
We expose engine properties under sysfs so that the sysadmin can
configure the driver according to their requirements. We can also use
udev rules to then apply that configuration anytime a device is
reloaded. Include a udev snippet provided by Joonas as an example.
v2: Update the snippet
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/gt/sysfs_engines.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/sysfs_engines.c
b/drivers/gpu/drm/i915/gt/sysfs_engines.c
index 9cf943b6a44b..37f078e69a42 100644
--- a/drivers/gpu/drm/i915/gt/sysfs_engines.c
+++ b/drivers/gpu/drm/i915/gt/sysfs_engines.c
@@ -11,6 +11,22 @@
#include "intel_engine_heartbeat.h"
#include "sysfs_engines.h"
+/*
+ * The sysfs provides a means for configuring each engine for the intended
+ * usecase, and by utilising a udev the configuration can be made persistent
+ * across reboots and device rebinding.
+ *
+ * An example udev rule to run a custom sysadmin script would be,
+ * /etc/udev/rules.d/50-intel-gpu.rules:
+ *
+ *
ACTION=="bind|add",SUBSYSTEM=="pci",DRIVER=="i915",RUN+="/usr/local/libexec/i915-disable-preempt-timeout.sh"
+ *
+ * where the script receives the device name and can open the sysfs, e.g.:
+ * for ENGINE in $(find /sys/$DEVPATH/drm/card?/engine -maxdepth 1) do
+ * echo 0 > $ENGINE/preempt_timeout_ms # Disable reset on preemption failure
+ * done
+ */
+
struct kobj_engine {
struct kobject base;
struct intel_engine_cs *engine;
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] i915/gem_exec_fair: Try to spot unfairness
An important property for multi-client systems is that each client gets
a 'fair' allotment of system time. (Where fairness is at the whim of the
context properties, such as priorities.) This test forks N independent
clients (albeit they happen to share a single vm), and does an equal
amount of work in client and asserts that they take an equal amount of
time.
Though we have never claimed to have a completely fair scheduler, that
is what is expected.
v2: igt_assert_f and more commentary; exclude vip from client stats,
include range of frame intervals from each individual client
v3: Write down what the test actually does!
v4: Split out to gem_exec_fair so that we can apply CI filtering to
reduce the test set
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Ramalingam C
---
tests/Makefile.sources | 3 +
tests/i915/gem_exec_fair.c | 916 +++
tests/intel-ci/blacklist.txt | 1 +
tests/meson.build| 1 +
4 files changed, 921 insertions(+)
create mode 100644 tests/i915/gem_exec_fair.c
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index d9c8f6104..db2be6a17 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -275,6 +275,9 @@ gem_exec_reloc_SOURCES = i915/gem_exec_reloc.c
TESTS_progs += gem_exec_schedule
gem_exec_schedule_SOURCES = i915/gem_exec_schedule.c
+TESTS_progs += gem_exec_fair
+gem_exec_fair_SOURCES = i915/gem_exec_fair.c
+
TESTS_progs += gem_exec_store
gem_exec_store_SOURCES = i915/gem_exec_store.c
diff --git a/tests/i915/gem_exec_fair.c b/tests/i915/gem_exec_fair.c
new file mode 100644
index 0..9153e0d95
--- /dev/null
+++ b/tests/i915/gem_exec_fair.c
@@ -0,0 +1,916 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2016 Intel Corporation
+ */
+
+#include "config.h"
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "i915/gem.h"
+#include "i915/gem_ring.h"
+#include "igt.h"
+#include "igt_rand.h"
+#include "igt_rapl.h"
+#include "igt_sysfs.h"
+#include "igt_vgem.h"
+#include "sw_sync.h"
+
+IGT_TEST_DESCRIPTION("Check that GPU time and execution order is fairly
distributed across clients");
+
+#define NSEC64 ((uint64_t)NSEC_PER_SEC)
+
+static unsigned int offset_in_page(void *addr)
+{
+ return (uintptr_t)addr & 4095;
+}
+
+static uint32_t __batch_create(int i915, uint32_t offset)
+{
+ const uint32_t bbe = MI_BATCH_BUFFER_END;
+ uint32_t handle;
+
+ handle = gem_create(i915, ALIGN(offset + 4, 4096));
+ gem_write(i915, handle, offset, , sizeof(bbe));
+
+ return handle;
+}
+
+static uint32_t batch_create(int i915)
+{
+ return __batch_create(i915, 0);
+}
+
+static int read_timestamp_frequency(int i915)
+{
+ int value = 0;
+ drm_i915_getparam_t gp = {
+ .value = ,
+ .param = I915_PARAM_CS_TIMESTAMP_FREQUENCY,
+ };
+ ioctl(i915, DRM_IOCTL_I915_GETPARAM, );
+ return value;
+}
+
+static uint64_t div64_u64_round_up(uint64_t x, uint64_t y)
+{
+ return (x + y - 1) / y;
+}
+
+static uint64_t ns_to_ctx_ticks(int i915, uint64_t ns)
+{
+ int f = read_timestamp_frequency(i915);
+ if (intel_gen(intel_get_drm_devid(i915)) == 11)
+ f = 1250; /* icl!!! are you feeling alright? CTX vs CS */
+ return div64_u64_round_up(ns * f, NSEC64);
+}
+
+static uint64_t ticks_to_ns(int i915, uint64_t ticks)
+{
+ return div64_u64_round_up(ticks * NSEC64,
+ read_timestamp_frequency(i915));
+}
+
+#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
+
+#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
+#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
+/* Opcodes for MI_MATH_INSTR */
+#define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0)
+#define MI_MATH_LOAD(op1, op2)MI_MATH_INSTR(0x080, op1, op2)
+#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2)
+#define MI_MATH_LOAD0(op1)MI_MATH_INSTR(0x081, op1)
+#define MI_MATH_LOAD1(op1)MI_MATH_INSTR(0x481, op1)
+#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0)
+#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0)
+#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0)
+#define MI_MATH_ORMI_MATH_INSTR(0x103, 0x0, 0x0)
+#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0)
+#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2)
+#define MI_MATH_STOREINV(op1, op2)MI_MATH_INSTR(0x580, op1, op2)
+/* Registers used as operands in MI_MATH_INSTR */
+#define MI_MATH_REG(x)(x)
+#define MI_MATH_REG_SRCA 0x20
+#define MI_MATH_REG_SRCB 0x21
+#define MI_MATH_REG_ACCU 0x31
+#define MI_MATH_REG_ZF0x32
+#define MI_MATH_REG_CF
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/5] drm/i915/display: move needs_modeset to an inline in header (rev2)
== Series Details == Series: series starting with [CI,1/5] drm/i915/display: move needs_modeset to an inline in header (rev2) URL : https://patchwork.freedesktop.org/series/85132/ State : success == Summary == CI Bug Log - changes from CI_DRM_9509 -> Patchwork_19191 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19191/index.html Known issues Here are the changes found in Patchwork_19191 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_cs_nop@fork-compute0: - fi-tgl-u2: NOTRUN -> [SKIP][1] ([fdo#109315] / [i915#2575]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19191/fi-tgl-u2/igt@amdgpu/amd_cs_...@fork-compute0.html * igt@i915_pm_rpm@module-reload: - fi-byt-j1900: [PASS][2] -> [INCOMPLETE][3] ([i915#142] / [i915#2405]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/fi-byt-j1900/igt@i915_pm_...@module-reload.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19191/fi-byt-j1900/igt@i915_pm_...@module-reload.html * igt@runner@aborted: - fi-byt-j1900: NOTRUN -> [FAIL][4] ([i915#1814]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19191/fi-byt-j1900/igt@run...@aborted.html * igt@vgem_basic@setversion: - fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/fi-tgl-y/igt@vgem_ba...@setversion.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19191/fi-tgl-y/igt@vgem_ba...@setversion.html Possible fixes * igt@gem_tiled_blits@basic: - fi-tgl-y: [DMESG-WARN][7] ([i915#402]) -> [PASS][8] +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/fi-tgl-y/igt@gem_tiled_bl...@basic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19191/fi-tgl-y/igt@gem_tiled_bl...@basic.html * igt@i915_selftest@live@hangcheck: - fi-tgl-u2: [INCOMPLETE][9] -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/fi-tgl-u2/igt@i915_selftest@l...@hangcheck.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19191/fi-tgl-u2/igt@i915_selftest@l...@hangcheck.html * igt@kms_chamelium@dp-edid-read: - fi-cml-u2: [FAIL][11] ([i915#2679]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/fi-cml-u2/igt@kms_chamel...@dp-edid-read.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19191/fi-cml-u2/igt@kms_chamel...@dp-edid-read.html [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [i915#142]: https://gitlab.freedesktop.org/drm/intel/issues/142 [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814 [i915#2405]: https://gitlab.freedesktop.org/drm/intel/issues/2405 [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575 [i915#2679]: https://gitlab.freedesktop.org/drm/intel/issues/2679 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (42 -> 37) -- Missing(5): fi-ilk-m540 fi-hsw-4200u fi-glk-dsi fi-bsw-cyan fi-bdw-samus Build changes - * Linux: CI_DRM_9509 -> Patchwork_19191 CI-20190529: 20190529 CI_DRM_9509: 66ecfb1df07b703dc4e83e8c520b186dffe6d2b3 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5913: b30bdfecaf1ff38b83c0bfbcf5981732a968a464 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19191: a324abeeea6f7aa420eb91630ffb657111fb7cd0 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == a324abeeea6f drm/i915: refactor i915 plane code into separate file. 9e8bf3e7db29 drm/i915: refactor cursor code out of i915_display.c c7a3e0296b01 drm/i915/display: fix misused comma e6777135cd18 drm/i915/display: move to_intel_frontbuffer to header f3393b6c2693 drm/i915/display: move needs_modeset to an inline in header == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19191/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] i915/gem_exec_fair: Try to spot unfairness
An important property for multi-client systems is that each client gets
a 'fair' allotment of system time. (Where fairness is at the whim of the
context properties, such as priorities.) This test forks N independent
clients (albeit they happen to share a single vm), and does an equal
amount of work in client and asserts that they take an equal amount of
time.
Though we have never claimed to have a completely fair scheduler, that
is what is expected.
v2: igt_assert_f and more commentary; exclude vip from client stats,
include range of frame intervals from each individual client
v3: Write down what the test actually does!
v4: Split out to gem_exec_fair so that we can apply CI filtering to
reduce the test set
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Ramalingam C
---
tests/Makefile.sources | 3 +
tests/i915/gem_exec_fair.c | 914 +++
tests/intel-ci/blacklist.txt | 1 +
tests/meson.build| 1 +
4 files changed, 919 insertions(+)
create mode 100644 tests/i915/gem_exec_fair.c
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index d9c8f6104..db2be6a17 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -275,6 +275,9 @@ gem_exec_reloc_SOURCES = i915/gem_exec_reloc.c
TESTS_progs += gem_exec_schedule
gem_exec_schedule_SOURCES = i915/gem_exec_schedule.c
+TESTS_progs += gem_exec_fair
+gem_exec_fair_SOURCES = i915/gem_exec_fair.c
+
TESTS_progs += gem_exec_store
gem_exec_store_SOURCES = i915/gem_exec_store.c
diff --git a/tests/i915/gem_exec_fair.c b/tests/i915/gem_exec_fair.c
new file mode 100644
index 0..76bf0f461
--- /dev/null
+++ b/tests/i915/gem_exec_fair.c
@@ -0,0 +1,914 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2016 Intel Corporation
+ */
+
+#include "config.h"
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "i915/gem.h"
+#include "i915/gem_ring.h"
+#include "igt.h"
+#include "igt_rand.h"
+#include "igt_rapl.h"
+#include "igt_sysfs.h"
+#include "igt_vgem.h"
+#include "sw_sync.h"
+
+IGT_TEST_DESCRIPTION("Check that GPU time and execution order is fairly
distributed across clients");
+
+static unsigned int offset_in_page(void *addr)
+{
+ return (uintptr_t)addr & 4095;
+}
+
+static uint32_t __batch_create(int i915, uint32_t offset)
+{
+ const uint32_t bbe = MI_BATCH_BUFFER_END;
+ uint32_t handle;
+
+ handle = gem_create(i915, ALIGN(offset + 4, 4096));
+ gem_write(i915, handle, offset, , sizeof(bbe));
+
+ return handle;
+}
+
+static uint32_t batch_create(int i915)
+{
+ return __batch_create(i915, 0);
+}
+
+static int read_timestamp_frequency(int i915)
+{
+ int value = 0;
+ drm_i915_getparam_t gp = {
+ .value = ,
+ .param = I915_PARAM_CS_TIMESTAMP_FREQUENCY,
+ };
+ ioctl(i915, DRM_IOCTL_I915_GETPARAM, );
+ return value;
+}
+
+static uint64_t div64_u64_round_up(uint64_t x, uint64_t y)
+{
+ return (x + y - 1) / y;
+}
+
+static uint64_t ns_to_ctx_ticks(int i915, uint64_t ns)
+{
+ int f = read_timestamp_frequency(i915);
+ if (intel_gen(intel_get_drm_devid(i915)) == 11)
+ f = 1250; /* icl!!! are you feeling alright? CTX vs CS */
+ return div64_u64_round_up(ns * f, NSEC_PER_SEC);
+}
+
+static uint64_t ticks_to_ns(int i915, uint64_t ticks)
+{
+ return div64_u64_round_up(ticks * NSEC_PER_SEC,
+ read_timestamp_frequency(i915));
+}
+
+#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
+
+#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
+#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
+/* Opcodes for MI_MATH_INSTR */
+#define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0)
+#define MI_MATH_LOAD(op1, op2)MI_MATH_INSTR(0x080, op1, op2)
+#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2)
+#define MI_MATH_LOAD0(op1)MI_MATH_INSTR(0x081, op1)
+#define MI_MATH_LOAD1(op1)MI_MATH_INSTR(0x481, op1)
+#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0)
+#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0)
+#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0)
+#define MI_MATH_ORMI_MATH_INSTR(0x103, 0x0, 0x0)
+#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0)
+#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2)
+#define MI_MATH_STOREINV(op1, op2)MI_MATH_INSTR(0x580, op1, op2)
+/* Registers used as operands in MI_MATH_INSTR */
+#define MI_MATH_REG(x)(x)
+#define MI_MATH_REG_SRCA 0x20
+#define MI_MATH_REG_SRCB 0x21
+#define MI_MATH_REG_ACCU 0x31
+#define MI_MATH_REG_ZF0x32
+#define MI_MATH_REG_CF0x33
+
+#define
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/5] drm/i915/display: move needs_modeset to an inline in header (rev2)
== Series Details == Series: series starting with [CI,1/5] drm/i915/display: move needs_modeset to an inline in header (rev2) URL : https://patchwork.freedesktop.org/series/85132/ State : warning == Summary == $ dim checkpatch origin/drm-tip f3393b6c2693 drm/i915/display: move needs_modeset to an inline in header e6777135cd18 drm/i915/display: move to_intel_frontbuffer to header c7a3e0296b01 drm/i915/display: fix misused comma 9e8bf3e7db29 drm/i915: refactor cursor code out of i915_display.c -:30: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #30: new file mode 100644 -:529: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned' #529: FILE: drivers/gpu/drm/i915/display/intel_cursor.c:495: + unsigned width = drm_rect_width(_state->uapi.dst); -:530: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned' #530: FILE: drivers/gpu/drm/i915/display/intel_cursor.c:496: + unsigned height = drm_rect_height(_state->uapi.dst); -:559: WARNING:REPEATED_WORD: Possible repeated word: 'by' #559: FILE: drivers/gpu/drm/i915/display/intel_cursor.c:525: +* The other registers are armed by by the CURBASE write -:786: CHECK:SPACING: No space is necessary after a cast #786: FILE: drivers/gpu/drm/i915/display/intel_cursor.c:752: + cursor->i9xx_plane = (enum i9xx_plane_id) pipe; total: 0 errors, 4 warnings, 1 checks, 1700 lines checked a324abeeea6f drm/i915: refactor i915 plane code into separate file. -:32: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #32: new file mode 100644 -:570: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #570: FILE: drivers/gpu/drm/i915/display/i9xx_plane.c:534: + return 32*1024; ^ -:573: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #573: FILE: drivers/gpu/drm/i915/display/i9xx_plane.c:537: + return 16*1024; ^ -:575: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #575: FILE: drivers/gpu/drm/i915/display/i9xx_plane.c:539: + return 32*1024; ^ -:578: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #578: FILE: drivers/gpu/drm/i915/display/i9xx_plane.c:542: + return 8*1024; ^ -:580: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #580: FILE: drivers/gpu/drm/i915/display/i9xx_plane.c:544: + return 16*1024; ^ -:583: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #583: FILE: drivers/gpu/drm/i915/display/i9xx_plane.c:547: + return 4*1024; ^ -:585: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #585: FILE: drivers/gpu/drm/i915/display/i9xx_plane.c:549: + return 8*1024; ^ -:632: CHECK:SPACING: No space is necessary after a cast #632: FILE: drivers/gpu/drm/i915/display/i9xx_plane.c:596: + plane->i9xx_plane = (enum i9xx_plane_id) !pipe; -:634: CHECK:SPACING: No space is necessary after a cast #634: FILE: drivers/gpu/drm/i915/display/i9xx_plane.c:598: + plane->i9xx_plane = (enum i9xx_plane_id) pipe; total: 0 errors, 1 warnings, 9 checks, 1462 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v8,1/2] drm/i915/display: Support PSR Multiple Transcoders
== Series Details ==
Series: series starting with [v8,1/2] drm/i915/display: Support PSR Multiple
Transcoders
URL : https://patchwork.freedesktop.org/series/85136/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9509 -> Patchwork_19190
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19190/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_19190:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_psr@primary_mmap_gtt:
- {fi-tgl-dsi}: [SKIP][1] ([fdo#110189]) -> [SKIP][2] +3 similar
issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/fi-tgl-dsi/igt@kms_psr@primary_mmap_gtt.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19190/fi-tgl-dsi/igt@kms_psr@primary_mmap_gtt.html
Known issues
Here are the changes found in Patchwork_19190 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_cs_nop@fork-compute0:
- fi-tgl-u2: NOTRUN -> [SKIP][3] ([fdo#109315] / [i915#2575]) +17
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19190/fi-tgl-u2/igt@amdgpu/amd_cs_...@fork-compute0.html
* igt@prime_self_import@basic-with_one_bo_two_files:
- fi-glk-dsi: [PASS][4] -> [INCOMPLETE][5] ([i915#2377])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/fi-glk-dsi/igt@prime_self_import@basic-with_one_bo_two_files.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19190/fi-glk-dsi/igt@prime_self_import@basic-with_one_bo_two_files.html
* igt@prime_self_import@basic-with_two_bos:
- fi-tgl-y: [PASS][6] -> [DMESG-WARN][7] ([i915#402]) +1 similar
issue
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19190/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html
* igt@runner@aborted:
- fi-glk-dsi: NOTRUN -> [FAIL][8] ([i915#2722] / [k.org#202321])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19190/fi-glk-dsi/igt@run...@aborted.html
Possible fixes
* igt@gem_tiled_blits@basic:
- fi-tgl-y: [DMESG-WARN][9] ([i915#402]) -> [PASS][10] +2 similar
issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/fi-tgl-y/igt@gem_tiled_bl...@basic.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19190/fi-tgl-y/igt@gem_tiled_bl...@basic.html
* igt@i915_selftest@live@hangcheck:
- fi-tgl-u2: [INCOMPLETE][11] -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/fi-tgl-u2/igt@i915_selftest@l...@hangcheck.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19190/fi-tgl-u2/igt@i915_selftest@l...@hangcheck.html
* igt@kms_chamelium@dp-edid-read:
- fi-cml-u2: [FAIL][13] ([i915#2679]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9509/fi-cml-u2/igt@kms_chamel...@dp-edid-read.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19190/fi-cml-u2/igt@kms_chamel...@dp-edid-read.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[i915#2377]: https://gitlab.freedesktop.org/drm/intel/issues/2377
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2679]: https://gitlab.freedesktop.org/drm/intel/issues/2679
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
Participating hosts (42 -> 38)
--
Missing(4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u
Build changes
-
* Linux: CI_DRM_9509 -> Patchwork_19190
CI-20190529: 20190529
CI_DRM_9509: 66ecfb1df07b703dc4e83e8c520b186dffe6d2b3 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5913: b30bdfecaf1ff38b83c0bfbcf5981732a968a464 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19190: 43bb135ca11c8f489256da40b5dc159d814e2a30 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
43bb135ca11c drm/i915/display: Support Multiple Transcoders' PSR status on
debugfs
b5d83e737ee4 drm/i915/display: Support PSR Multiple Transcoders
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19190/index.html
[Intel-gfx] [PATCH v2] drm/i915: refactor i915 plane code into separate file.
From: Dave Airlie
Ville suggested this as a good idea, let's move this before moving
the crtc code.
Signed-off-by: Dave Airlie
Reviewed-by: Ville Syrjälä
[Jani: fixed i915xx_plane.h standalone build.]
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/Makefile| 3 +-
drivers/gpu/drm/i915/display/i9xx_plane.c| 704 +++
drivers/gpu/drm/i915/display/i9xx_plane.h| 24 +
drivers/gpu/drm/i915/display/intel_display.c | 689 +-
drivers/gpu/drm/i915/display/intel_display.h | 4 -
drivers/gpu/drm/i915/display/intel_sprite.c | 1 +
6 files changed, 732 insertions(+), 693 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/i9xx_plane.c
create mode 100644 drivers/gpu/drm/i915/display/i9xx_plane.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index b6558401691e..3f674725cd1c 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -216,7 +216,8 @@ i915-y += \
display/intel_quirks.o \
display/intel_sprite.o \
display/intel_tc.o \
- display/intel_vga.o
+ display/intel_vga.o \
+ display/i9xx_plane.o
i915-$(CONFIG_ACPI) += \
display/intel_acpi.o \
display/intel_opregion.o
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
new file mode 100644
index ..b78985c855a5
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -0,0 +1,704 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+#include
+
+#include
+#include
+#include
+
+#include "intel_atomic.h"
+#include "intel_atomic_plane.h"
+#include "intel_display_types.h"
+#include "intel_sprite.h"
+#include "i9xx_plane.h"
+
+/* Primary plane formats for gen <= 3 */
+static const u32 i8xx_primary_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_XRGB1555,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+};
+
+/* Primary plane formats for ivb (no fp16 due to hw issue) */
+static const u32 ivb_primary_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+};
+
+/* Primary plane formats for gen >= 4, except ivb */
+static const u32 i965_primary_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_XBGR16161616F,
+};
+
+/* Primary plane formats for vlv/chv */
+static const u32 vlv_primary_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_ARGB2101010,
+ DRM_FORMAT_ABGR2101010,
+ DRM_FORMAT_XBGR16161616F,
+};
+
+static const u64 i9xx_format_modifiers[] = {
+ I915_FORMAT_MOD_X_TILED,
+ DRM_FORMAT_MOD_LINEAR,
+ DRM_FORMAT_MOD_INVALID
+};
+
+static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
+ u32 format, u64 modifier)
+{
+ switch (modifier) {
+ case DRM_FORMAT_MOD_LINEAR:
+ case I915_FORMAT_MOD_X_TILED:
+ break;
+ default:
+ return false;
+ }
+
+ switch (format) {
+ case DRM_FORMAT_C8:
+ case DRM_FORMAT_RGB565:
+ case DRM_FORMAT_XRGB1555:
+ case DRM_FORMAT_XRGB:
+ return modifier == DRM_FORMAT_MOD_LINEAR ||
+ modifier == I915_FORMAT_MOD_X_TILED;
+ default:
+ return false;
+ }
+}
+
+static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
+ u32 format, u64 modifier)
+{
+ switch (modifier) {
+ case DRM_FORMAT_MOD_LINEAR:
+ case I915_FORMAT_MOD_X_TILED:
+ break;
+ default:
+ return false;
+ }
+
+ switch (format) {
+ case DRM_FORMAT_C8:
+ case DRM_FORMAT_RGB565:
+ case DRM_FORMAT_XRGB:
+ case DRM_FORMAT_XBGR:
+ case DRM_FORMAT_ARGB:
+ case DRM_FORMAT_ABGR:
+ case DRM_FORMAT_XRGB2101010:
+ case DRM_FORMAT_XBGR2101010:
+ case DRM_FORMAT_ARGB2101010:
+ case DRM_FORMAT_ABGR2101010:
+ case DRM_FORMAT_XBGR16161616F:
+ return modifier == DRM_FORMAT_MOD_LINEAR ||
+ modifier == I915_FORMAT_MOD_X_TILED;
+ default:
+ return false;
+ }
+}
+
+static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
+ enum i9xx_plane_id i9xx_plane)
+{
+ if (!HAS_FBC(dev_priv))
+ return false;
+
+ if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
+
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v8,1/2] drm/i915/display: Support PSR Multiple Transcoders
== Series Details == Series: series starting with [v8,1/2] drm/i915/display: Support PSR Multiple Transcoders URL : https://patchwork.freedesktop.org/series/85136/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/selftest_reset.c:101:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:101:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:101:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:102:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:102:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:102:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:137:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:137:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:137:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:138:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:138:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:138:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:99:34:expected unsigned int [usertype] *s +drivers/gpu/drm/i915/gt/selftest_reset.c:99:34:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:99:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1449:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1503:15: warning: memset with byte count of 16777216 +./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:864:16: warning: trying to copy expression type 31 +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v8,1/2] drm/i915/display: Support PSR Multiple Transcoders
== Series Details == Series: series starting with [v8,1/2] drm/i915/display: Support PSR Multiple Transcoders URL : https://patchwork.freedesktop.org/series/85136/ State : warning == Summary == $ dim checkpatch origin/drm-tip b5d83e737ee4 drm/i915/display: Support PSR Multiple Transcoders -:1712: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'intel_dp' - possible side-effects? #1712: FILE: drivers/gpu/drm/i915/display/intel_psr.h:21: +#define CAN_PSR(intel_dp) (HAS_PSR(dp_to_i915(intel_dp)) && intel_dp->psr.sink_support) total: 0 errors, 0 warnings, 1 checks, 1737 lines checked 43bb135ca11c drm/i915/display: Support Multiple Transcoders' PSR status on debugfs ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v9 1/5] drm: Add function to convert rect in 16.16 fixed format to regular format
On Fri, 2020-12-18 at 10:46 -0800, José Roberto de Souza wrote:
> Much more clear to read one function call than four lines doing this
> conversion.
>
> v7:
> - function renamed
> - calculating width and height before truncate
> - inlined
>
> Cc: Ville Syrjälä
> Cc: dri-de...@lists.freedesktop.org
> Cc: Gwan-gyeong Mun
> Signed-off-by: José Roberto de Souza
> ---
> include/drm/drm_rect.h | 13 +
> 1 file changed, 13 insertions(+)
>
> diff --git a/include/drm/drm_rect.h b/include/drm/drm_rect.h
> index e7f4d24cdd00..7eb84af4a818 100644
> --- a/include/drm/drm_rect.h
> +++ b/include/drm/drm_rect.h
> @@ -206,6 +206,19 @@ static inline bool drm_rect_equals(const struct
> drm_rect *r1,
> r1->y1 == r2->y1 && r1->y2 == r2->y2;
> }
>
> +/**
> + * drm_rect_fp_to_int - Convert a rect in 16.16 fixed point form to
> int form.
> + * @destination: rect to be stored the converted value
> + * @source: rect in 16.16 fixed point form
> + */
> +static inline void drm_rect_fp_to_int(struct drm_rect *destination,
> + const struct drm_rect *source)
other drm_rect functions use input parameter names as src, dst.
( ex. drm_rect_clip_scaled(), drm_rect_calc_hscale(),
drm_rect_calc_vscale() )
if the names change to src and dst, other parts seem good to me.
Reviewed-by: Gwan-gyeong Mun
> +{
> + drm_rect_init(destination, source->x1 >> 16, source->y1 >> 16,
> + drm_rect_width(source) >> 16,
> + drm_rect_height(source) >> 16);
> +}
> +
> bool drm_rect_intersect(struct drm_rect *r, const struct drm_rect
> *clip);
> bool drm_rect_clip_scaled(struct drm_rect *src, struct drm_rect
> *dst,
> const struct drm_rect *clip);
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v8 1/2] drm/i915/display: Support PSR Multiple Transcoders
It is a preliminary work for supporting multiple EDP PSR and
DP PanelReplay. And it refactors singleton PSR to Multi Transcoder
supportable PSR.
And this moves and renames the i915_psr structure of drm_i915_private's to
intel_dp's intel_psr structure.
It also causes changes in PSR interrupt handling routine for supporting
multiple transcoders. But it does not change the scenario and timing of
enabling and disabling PSR. And it not support multiple pipes with
a single transcoder PSR case yet.
v2: Fix indentation and add comments
v3: Remove Blank line
v4: Rebased
v5: Rebased and Addressed Anshuman's review comment.
- Move calling of intel_psr_init() to intel_dp_init_connector()
v6: Address Anshuman's review comments
- Remove wrong comments and add comments for a limit of supporting of
a single pipe PSR
v7: Update intel_psr_compute_config() for supporting multiple transcoder
PSR on BDW+
v8: Address Anshuman's review comments
- Replace DRM_DEBUG_KMS with drm_dbg_kms() / DRM_WARN with drm_warn()
Signed-off-by: Gwan-gyeong Mun
Cc: José Roberto de Souza
Cc: Juha-Pekka Heikkila
Cc: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 +
drivers/gpu/drm/i915/display/intel_display.c | 4 -
.../drm/i915/display/intel_display_debugfs.c | 111 ++--
.../drm/i915/display/intel_display_types.h| 38 ++
drivers/gpu/drm/i915/display/intel_dp.c | 23 +-
drivers/gpu/drm/i915/display/intel_psr.c | 576 ++
drivers/gpu/drm/i915/display/intel_psr.h | 14 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 6 +-
drivers/gpu/drm/i915/i915_drv.h | 38 --
drivers/gpu/drm/i915/i915_irq.c | 49 +-
10 files changed, 485 insertions(+), 377 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 6863236df1d0..4b87f72cb9c0 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4320,7 +4320,10 @@ static void intel_ddi_update_pipe_dp(struct
intel_atomic_state *state,
intel_ddi_set_dp_msa(crtc_state, conn_state);
+ //TODO: move PSR related functions into intel_psr_update()
+ intel_psr2_program_trans_man_trk_ctl(intel_dp, crtc_state);
intel_psr_update(intel_dp, crtc_state, conn_state);
+
intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
intel_edp_drrs_update(intel_dp, crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 78452de5e12f..a753647b0bcb 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15869,8 +15869,6 @@ static void commit_pipe_config(struct
intel_atomic_state *state,
if (new_crtc_state->update_pipe)
intel_pipe_fastset(old_crtc_state, new_crtc_state);
-
- intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
}
if (dev_priv->display.atomic_update_watermarks)
@@ -17829,8 +17827,6 @@ static void intel_setup_outputs(struct drm_i915_private
*dev_priv)
intel_dvo_init(dev_priv);
}
- intel_psr_init(dev_priv);
-
for_each_intel_encoder(_priv->drm, encoder) {
encoder->base.possible_crtcs =
intel_encoder_possible_crtcs(encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index cd7e5519ee7d..041053167d7f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -249,18 +249,17 @@ static int i915_psr_sink_status_show(struct seq_file *m,
void *data)
"sink internal error",
};
struct drm_connector *connector = m->private;
- struct drm_i915_private *dev_priv = to_i915(connector->dev);
struct intel_dp *intel_dp =
intel_attached_dp(to_intel_connector(connector));
int ret;
- if (!CAN_PSR(dev_priv)) {
- seq_puts(m, "PSR Unsupported\n");
+ if (connector->status != connector_status_connected)
return -ENODEV;
- }
- if (connector->status != connector_status_connected)
+ if (!CAN_PSR(intel_dp)) {
+ seq_puts(m, "PSR Unsupported\n");
return -ENODEV;
+ }
ret = drm_dp_dpcd_readb(_dp->aux, DP_PSR_STATUS, );
@@ -280,12 +279,13 @@ static int i915_psr_sink_status_show(struct seq_file *m,
void *data)
DEFINE_SHOW_ATTRIBUTE(i915_psr_sink_status);
static void
-psr_source_status(struct drm_i915_private *dev_priv, struct seq_file *m)
+psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
{
u32 val, status_val;
const char *status = "unknown";
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- if
[Intel-gfx] [PATCH v8 2/2] drm/i915/display: Support Multiple Transcoders' PSR status on debugfs
In order to support the PSR state of each transcoder, it adds
i915_psr_status to sub-directory of each transcoder.
v2: Change using of Symbolic permissions 'S_IRUGO' to using of octal
permissions '0444'
v5: Addressed JJani Nikula's review comments
- Remove checking of Gen12 for i915_psr_status.
- Add check of HAS_PSR()
- Remove meaningless check routine.
Signed-off-by: Gwan-gyeong Mun
Cc: José Roberto de Souza
Cc: Jani Nikula
Cc: Anshuman Gupta
---
.../gpu/drm/i915/display/intel_display_debugfs.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 041053167d7f..d2dd61c4ee0b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -2224,6 +2224,16 @@ static int i915_hdcp_sink_capability_show(struct
seq_file *m, void *data)
}
DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability);
+static int i915_psr_status_show(struct seq_file *m, void *data)
+{
+ struct drm_connector *connector = m->private;
+ struct intel_dp *intel_dp =
+ intel_attached_dp(to_intel_connector(connector));
+
+ return intel_psr_status(m, intel_dp);
+}
+DEFINE_SHOW_ATTRIBUTE(i915_psr_status);
+
#define LPSP_CAPABLE(COND) (COND ? seq_puts(m, "LPSP: capable\n") : \
seq_puts(m, "LPSP: incapable\n"))
@@ -2399,6 +2409,12 @@ int intel_connector_debugfs_add(struct drm_connector
*connector)
connector, _psr_sink_status_fops);
}
+ if (HAS_PSR(dev_priv) &&
+ connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
+ debugfs_create_file("i915_psr_status", 0444, root,
+ connector, _psr_status_fops);
+ }
+
if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) {
--
2.25.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v7 1/2] drm/i915/display: Support PSR Multiple Transcoders
On Wed, 2020-12-16 at 18:56 +0530, Anshuman Gupta wrote:
> On 2020-12-16 at 14:47:42 +0200, Gwan-gyeong Mun wrote:
> > It is a preliminary work for supporting multiple EDP PSR and
> > DP PanelReplay. And it refactors singleton PSR to Multi Transcoder
> > supportable PSR.
> > And this moves and renames the i915_psr structure of
> > drm_i915_private's to
> > intel_dp's intel_psr structure.
> > It also causes changes in PSR interrupt handling routine for
> > supporting
> > multiple transcoders. But it does not change the scenario and
> > timing of
> > enabling and disabling PSR. And it not support multiple pipes with
> > a single transcoder PSR case yet.
> >
> > v2: Fix indentation and add comments
> > v3: Remove Blank line
> > v4: Rebased
> > v5: Rebased and Addressed Anshuman's review comment.
> > - Move calling of intel_psr_init() to intel_dp_init_connector()
> > v6: Address Anshuman's review comments
> >- Remove wrong comments and add comments for a limit of
> > supporting of
> > a single pipe PSR
> You missed some comment to address provided on v5.
> Is debugfs print in drrs_status_per_crtc is not required anymore ?
Current implementation does not enable drrs when the pipe has psr by
intel_dp_drrs_compute_config().
therefore the log message is not needed.
> Also please use drm_{dbg,warn} at every place in this patch.
I'll float a new patch which addresses it.
> > v7: Update intel_psr_compute_config() for supporting multiple
> > transcoder
> > PSR on BDW+
> Could you please send this in a separate patch, remove the PORT_A
> restriction so that we can support multiple psr instances.
>
IMHO, in order to enable PSRs on multiple transcoders, we have to
include this fix in this patch.
> Thanks,
> Anshuman Gupta.
> > Signed-off-by: Gwan-gyeong Mun
> > Cc: José Roberto de Souza
> > Cc: Juha-Pekka Heikkila
> > Cc: Anshuman Gupta
> > ---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 3 +
> > drivers/gpu/drm/i915/display/intel_display.c | 4 -
> > .../drm/i915/display/intel_display_debugfs.c | 111 ++--
> > .../drm/i915/display/intel_display_types.h| 38 ++
> > drivers/gpu/drm/i915/display/intel_dp.c | 23 +-
> > drivers/gpu/drm/i915/display/intel_psr.c | 588 +-
> >
> > drivers/gpu/drm/i915/display/intel_psr.h | 14 +-
> > drivers/gpu/drm/i915/display/intel_sprite.c | 6 +-
> > drivers/gpu/drm/i915/i915_drv.h | 38 --
> > drivers/gpu/drm/i915/i915_irq.c | 49 +-
> > 10 files changed, 490 insertions(+), 384 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 6863236df1d0..4b87f72cb9c0 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -4320,7 +4320,10 @@ static void intel_ddi_update_pipe_dp(struct
> > intel_atomic_state *state,
> >
> > intel_ddi_set_dp_msa(crtc_state, conn_state);
> >
> > + //TODO: move PSR related functions into intel_psr_update()
> > + intel_psr2_program_trans_man_trk_ctl(intel_dp, crtc_state);
> > intel_psr_update(intel_dp, crtc_state, conn_state);
> > +
> > intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
> > intel_edp_drrs_update(intel_dp, crtc_state);
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 78452de5e12f..a753647b0bcb 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -15869,8 +15869,6 @@ static void commit_pipe_config(struct
> > intel_atomic_state *state,
> >
> > if (new_crtc_state->update_pipe)
> > intel_pipe_fastset(old_crtc_state,
> > new_crtc_state);
> > -
> > - intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
> > }
> >
> > if (dev_priv->display.atomic_update_watermarks)
> > @@ -17829,8 +17827,6 @@ static void intel_setup_outputs(struct
> > drm_i915_private *dev_priv)
> > intel_dvo_init(dev_priv);
> > }
> >
> > - intel_psr_init(dev_priv);
> > -
> > for_each_intel_encoder(_priv->drm, encoder) {
> > encoder->base.possible_crtcs =
> > intel_encoder_possible_crtcs(encoder);
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > index cd7e5519ee7d..041053167d7f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > @@ -249,18 +249,17 @@ static int i915_psr_sink_status_show(struct
> > seq_file *m, void *data)
> > "sink internal error",
> > };
> > struct drm_connector *connector = m->private;
> > - struct drm_i915_private *dev_priv = to_i915(connector->dev);
> > struct intel_dp *intel_dp =
> >
Re: [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [01/16] drm/i915/display: move needs_modeset to an inline in header
On Mon, Dec 21, 2020 at 11:03:42AM +0200, Jani Nikula wrote: > On Mon, 21 Dec 2020, Patchwork wrote: > > == Series Details == > > > > Series: series starting with [01/16] drm/i915/display: move needs_modeset > > to an inline in header > > URL : https://patchwork.freedesktop.org/series/85129/ > > State : failure > > > > == Summary == > > > > Applying: drm/i915/display: move needs_modeset to an inline in header > > Applying: drm/i915/display: move to_intel_frontbuffer to header > > Applying: drm/i915/display: fix misused comma > > Applying: drm/i915: refactor cursor code out of i915_display.c > > Applying: drm/i915: refactor i915 plane code into separate file. > > Applying: drm/i915: refactor some crtc code out of intel display. (v2) > > error: sha1 information is lacking or useless > > (drivers/gpu/drm/i915/Makefile). > > error: could not build fake ancestor > > hint: Use 'git am --show-current-patch=diff' to see the failed patch > > Patch failed at 0006 drm/i915: refactor some crtc code out of intel > > display. (v2) > > When you have resolved this problem, run "git am --continue". > > If you prefer to skip this patch, run "git am --skip" instead. > > To restore the original branch and stop patching, run "git am --abort". > > I wonder what gives here. The same thing has been happening for several > versions of the series, including mine. I would've applied the early > patches already if I'd gotten some test results. What gives is the part of the patch that contains -#define INTEL_CRTC_FUNCS \ -.gamma_set = drm_atomic_helper_legacy_gamma_set, \ which doesn't apply anymore after commit 6ca2ab8086af8434a4c0990882321a345c3cc2c6 Author: Tomi Valkeinen Date: Fri Dec 11 13:42:36 2020 +0200 drm: automatic legacy gamma support -- Petri Latvala ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [CI,1/5] drm/i915/display: move needs_modeset to an inline in header
== Series Details == Series: series starting with [CI,1/5] drm/i915/display: move needs_modeset to an inline in header URL : https://patchwork.freedesktop.org/series/85132/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h HDRTEST drivers/gpu/drm/i915/display/i9xx_plane.h In file included from : ./drivers/gpu/drm/i915/display/i9xx_plane.h:14:8: error: unknown type name ‘u32’ u32 pixel_format, u64 modifier, ^~~ ./drivers/gpu/drm/i915/display/i9xx_plane.h:14:26: error: unknown type name ‘u64’ u32 pixel_format, u64 modifier, ^~~ ./drivers/gpu/drm/i915/display/i9xx_plane.h:16:37: error: ‘struct intel_plane_state’ declared inside parameter list will not be visible outside of this definition or declaration [-Werror] int i9xx_check_plane_surface(struct intel_plane_state *plane_state); ^ cc1: all warnings being treated as errors drivers/gpu/drm/i915/Makefile:307: recipe for target 'drivers/gpu/drm/i915/display/i9xx_plane.hdrtest' failed make[4]: *** [drivers/gpu/drm/i915/display/i9xx_plane.hdrtest] Error 1 scripts/Makefile.build:496: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:496: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:496: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1805: recipe for target 'drivers' failed make: *** [drivers] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 5/5] drm/i915: refactor i915 plane code into separate file.
From: Dave Airlie
Ville suggested this as a good idea, let's move this before moving
the crtc code.
Signed-off-by: Dave Airlie
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/Makefile| 3 +-
drivers/gpu/drm/i915/display/i9xx_plane.c| 704 +++
drivers/gpu/drm/i915/display/i9xx_plane.h| 21 +
drivers/gpu/drm/i915/display/intel_display.c | 689 +-
drivers/gpu/drm/i915/display/intel_display.h | 4 -
drivers/gpu/drm/i915/display/intel_sprite.c | 1 +
6 files changed, 729 insertions(+), 693 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/i9xx_plane.c
create mode 100644 drivers/gpu/drm/i915/display/i9xx_plane.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index b6558401691e..3f674725cd1c 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -216,7 +216,8 @@ i915-y += \
display/intel_quirks.o \
display/intel_sprite.o \
display/intel_tc.o \
- display/intel_vga.o
+ display/intel_vga.o \
+ display/i9xx_plane.o
i915-$(CONFIG_ACPI) += \
display/intel_acpi.o \
display/intel_opregion.o
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
new file mode 100644
index ..b78985c855a5
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -0,0 +1,704 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+#include
+
+#include
+#include
+#include
+
+#include "intel_atomic.h"
+#include "intel_atomic_plane.h"
+#include "intel_display_types.h"
+#include "intel_sprite.h"
+#include "i9xx_plane.h"
+
+/* Primary plane formats for gen <= 3 */
+static const u32 i8xx_primary_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_XRGB1555,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+};
+
+/* Primary plane formats for ivb (no fp16 due to hw issue) */
+static const u32 ivb_primary_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+};
+
+/* Primary plane formats for gen >= 4, except ivb */
+static const u32 i965_primary_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_XBGR16161616F,
+};
+
+/* Primary plane formats for vlv/chv */
+static const u32 vlv_primary_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_ARGB2101010,
+ DRM_FORMAT_ABGR2101010,
+ DRM_FORMAT_XBGR16161616F,
+};
+
+static const u64 i9xx_format_modifiers[] = {
+ I915_FORMAT_MOD_X_TILED,
+ DRM_FORMAT_MOD_LINEAR,
+ DRM_FORMAT_MOD_INVALID
+};
+
+static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
+ u32 format, u64 modifier)
+{
+ switch (modifier) {
+ case DRM_FORMAT_MOD_LINEAR:
+ case I915_FORMAT_MOD_X_TILED:
+ break;
+ default:
+ return false;
+ }
+
+ switch (format) {
+ case DRM_FORMAT_C8:
+ case DRM_FORMAT_RGB565:
+ case DRM_FORMAT_XRGB1555:
+ case DRM_FORMAT_XRGB:
+ return modifier == DRM_FORMAT_MOD_LINEAR ||
+ modifier == I915_FORMAT_MOD_X_TILED;
+ default:
+ return false;
+ }
+}
+
+static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
+ u32 format, u64 modifier)
+{
+ switch (modifier) {
+ case DRM_FORMAT_MOD_LINEAR:
+ case I915_FORMAT_MOD_X_TILED:
+ break;
+ default:
+ return false;
+ }
+
+ switch (format) {
+ case DRM_FORMAT_C8:
+ case DRM_FORMAT_RGB565:
+ case DRM_FORMAT_XRGB:
+ case DRM_FORMAT_XBGR:
+ case DRM_FORMAT_ARGB:
+ case DRM_FORMAT_ABGR:
+ case DRM_FORMAT_XRGB2101010:
+ case DRM_FORMAT_XBGR2101010:
+ case DRM_FORMAT_ARGB2101010:
+ case DRM_FORMAT_ABGR2101010:
+ case DRM_FORMAT_XBGR16161616F:
+ return modifier == DRM_FORMAT_MOD_LINEAR ||
+ modifier == I915_FORMAT_MOD_X_TILED;
+ default:
+ return false;
+ }
+}
+
+static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
+ enum i9xx_plane_id i9xx_plane)
+{
+ if (!HAS_FBC(dev_priv))
+ return false;
+
+ if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
+ return i9xx_plane == PLANE_A; /* tied to pipe A */
+ else if
[Intel-gfx] [CI 4/5] drm/i915: refactor cursor code out of i915_display.c
From: Dave Airlie
This file is a monster, let's start simple, the cursor plane code
seems pretty standalone, and splits out easily enough.
Reviewed-by: Ville Syrjälä
Signed-off-by: Dave Airlie
[Jani: cleaned up intel_cursor.h a bit.]
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/display/intel_cursor.c | 806 +++
drivers/gpu/drm/i915/display/intel_cursor.h | 17 +
drivers/gpu/drm/i915/display/intel_display.c | 797 +-
drivers/gpu/drm/i915/display/intel_display.h | 7 +
5 files changed, 838 insertions(+), 790 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_cursor.c
create mode 100644 drivers/gpu/drm/i915/display/intel_cursor.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index f9ef5199b124..b6558401691e 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -198,6 +198,7 @@ i915-y += \
display/intel_combo_phy.o \
display/intel_connector.o \
display/intel_csr.o \
+ display/intel_cursor.o \
display/intel_display.o \
display/intel_display_power.o \
display/intel_dpio_phy.o \
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c
b/drivers/gpu/drm/i915/display/intel_cursor.c
new file mode 100644
index ..276d2bb0e2cf
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -0,0 +1,806 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#include "intel_atomic.h"
+#include "intel_atomic_plane.h"
+#include "intel_cursor.h"
+#include "intel_display_types.h"
+#include "intel_display.h"
+
+#include "intel_frontbuffer.h"
+#include "intel_pm.h"
+#include "intel_psr.h"
+#include "intel_sprite.h"
+
+/* Cursor formats */
+static const u32 intel_cursor_formats[] = {
+ DRM_FORMAT_ARGB,
+};
+
+static const u64 cursor_format_modifiers[] = {
+ DRM_FORMAT_MOD_LINEAR,
+ DRM_FORMAT_MOD_INVALID
+};
+
+static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
+{
+ struct drm_i915_private *dev_priv =
+ to_i915(plane_state->uapi.plane->dev);
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+ const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
+ u32 base;
+
+ if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)
+ base = sg_dma_address(obj->mm.pages->sgl);
+ else
+ base = intel_plane_ggtt_offset(plane_state);
+
+ return base + plane_state->color_plane[0].offset;
+}
+
+static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
+{
+ int x = plane_state->uapi.dst.x1;
+ int y = plane_state->uapi.dst.y1;
+ u32 pos = 0;
+
+ if (x < 0) {
+ pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
+ x = -x;
+ }
+ pos |= x << CURSOR_X_SHIFT;
+
+ if (y < 0) {
+ pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
+ y = -y;
+ }
+ pos |= y << CURSOR_Y_SHIFT;
+
+ return pos;
+}
+
+static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
+{
+ const struct drm_mode_config *config =
+ _state->uapi.plane->dev->mode_config;
+ int width = drm_rect_width(_state->uapi.dst);
+ int height = drm_rect_height(_state->uapi.dst);
+
+ return width > 0 && width <= config->cursor_width &&
+ height > 0 && height <= config->cursor_height;
+}
+
+static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
+{
+ struct drm_i915_private *dev_priv =
+ to_i915(plane_state->uapi.plane->dev);
+ unsigned int rotation = plane_state->hw.rotation;
+ int src_x, src_y;
+ u32 offset;
+ int ret;
+
+ ret = intel_plane_compute_gtt(plane_state);
+ if (ret)
+ return ret;
+
+ if (!plane_state->uapi.visible)
+ return 0;
+
+ src_x = plane_state->uapi.src.x1 >> 16;
+ src_y = plane_state->uapi.src.y1 >> 16;
+
+ intel_add_fb_offsets(_x, _y, plane_state, 0);
+ offset = intel_plane_compute_aligned_offset(_x, _y,
+ plane_state, 0);
+
+ if (src_x != 0 || src_y != 0) {
+ drm_dbg_kms(_priv->drm,
+ "Arbitrary cursor panning not supported\n");
+ return -EINVAL;
+ }
+
+ /*
+* Put the final coordinates back so that the src
+* coordinate checks will see the right values.
+*/
+ drm_rect_translate_to(_state->uapi.src,
+ src_x << 16, src_y << 16);
+
+ /* ILK+ do this automagically in hardware */
+ if (HAS_GMCH(dev_priv) && rotation & DRM_MODE_ROTATE_180) {
+ const struct drm_framebuffer *fb =
[Intel-gfx] [CI 3/5] drm/i915/display: fix misused comma
From: Dave Airlie
There is no need for a comma use here.
Reviewed-by: Ville Syrjälä
Signed-off-by: Dave Airlie
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 9063922dc073..ec9a28b69e09 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -989,7 +989,8 @@ chv_find_best_dpll(const struct intel_limit *limit,
* set to 2. If requires to support 200Mhz refclk, we need to
* revisit this because n may not 1 anymore.
*/
- clock.n = 1, clock.m1 = 2;
+ clock.n = 1;
+ clock.m1 = 2;
target *= 5;/* fast clock */
for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
--
2.20.1
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[Intel-gfx] [CI 2/5] drm/i915/display: move to_intel_frontbuffer to header
From: Dave Airlie
This will be used for some refactoring in other files, so move it
first.
Signed-off-by: Dave Airlie
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 6 --
drivers/gpu/drm/i915/display/intel_display_types.h | 6 ++
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index c435d90ec000..9063922dc073 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3611,12 +3611,6 @@ static void intel_plane_disable_noatomic(struct
intel_crtc *crtc,
intel_disable_plane(plane, crtc_state);
}
-static struct intel_frontbuffer *
-to_intel_frontbuffer(struct drm_framebuffer *fb)
-{
- return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
-}
-
static void
intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
struct intel_initial_plane_config *plane_config)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index a2f6b7c161a4..dfa3966e5fa1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1805,4 +1805,10 @@ static inline u32 intel_plane_ggtt_offset(const struct
intel_plane_state *state)
return i915_ggtt_offset(state->vma);
}
+static inline struct intel_frontbuffer *
+to_intel_frontbuffer(struct drm_framebuffer *fb)
+{
+ return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
+}
+
#endif /* __INTEL_DISPLAY_TYPES_H__ */
--
2.20.1
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[Intel-gfx] [CI 1/5] drm/i915/display: move needs_modeset to an inline in header
From: Dave Airlie
This function is going to be used in a later change, so clean it
up first before moving it.
Reviewed-by: Ville Syrjälä
Signed-off-by: Dave Airlie
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 78 +--
.../drm/i915/display/intel_display_types.h| 6 ++
2 files changed, 42 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 78452de5e12f..c435d90ec000 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -542,12 +542,6 @@ icl_wa_scalerclkgating(struct drm_i915_private *dev_priv,
enum pipe pipe,
intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) &
~DPFR_GATING_DIS);
}
-static bool
-needs_modeset(const struct intel_crtc_state *state)
-{
- return drm_atomic_crtc_needs_modeset(>uapi);
-}
-
static bool
is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
{
@@ -6474,7 +6468,7 @@ static bool hsw_pre_update_disable_ips(const struct
intel_crtc_state *old_crtc_s
if (!old_crtc_state->ips_enabled)
return false;
- if (needs_modeset(new_crtc_state))
+ if (intel_crtc_needs_modeset(new_crtc_state))
return true;
/*
@@ -6501,7 +6495,7 @@ static bool hsw_post_update_enable_ips(const struct
intel_crtc_state *old_crtc_s
if (!new_crtc_state->ips_enabled)
return false;
- if (needs_modeset(new_crtc_state))
+ if (intel_crtc_needs_modeset(new_crtc_state))
return true;
/*
@@ -6554,7 +6548,7 @@ static bool needs_scalerclk_wa(const struct
intel_crtc_state *crtc_state)
static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
const struct intel_crtc_state *new_crtc_state)
{
- return (!old_crtc_state->active_planes ||
needs_modeset(new_crtc_state)) &&
+ return (!old_crtc_state->active_planes ||
intel_crtc_needs_modeset(new_crtc_state)) &&
new_crtc_state->active_planes;
}
@@ -6562,7 +6556,7 @@ static bool planes_disabling(const struct
intel_crtc_state *old_crtc_state,
const struct intel_crtc_state *new_crtc_state)
{
return old_crtc_state->active_planes &&
- (!new_crtc_state->active_planes ||
needs_modeset(new_crtc_state));
+ (!new_crtc_state->active_planes ||
intel_crtc_needs_modeset(new_crtc_state));
}
static void intel_post_plane_update(struct intel_atomic_state *state,
@@ -6685,7 +6679,7 @@ static void intel_pre_plane_update(struct
intel_atomic_state *state,
* If we're doing a modeset we don't need to do any
* pre-vblank watermark programming here.
*/
- if (!needs_modeset(new_crtc_state)) {
+ if (!intel_crtc_needs_modeset(new_crtc_state)) {
/*
* For platforms that support atomic watermarks, program the
* 'intermediate' watermarks immediately. On pre-gen9
platforms, these
@@ -12046,7 +12040,7 @@ static void i9xx_update_cursor(struct intel_plane
*plane,
if (INTEL_GEN(dev_priv) >= 9)
skl_write_cursor_wm(plane, crtc_state);
- if (!needs_modeset(crtc_state))
+ if (!intel_crtc_needs_modeset(crtc_state))
intel_psr2_program_plane_sel_fetch(plane, crtc_state,
plane_state, 0);
if (plane->cursor.base != base ||
@@ -12616,7 +12610,7 @@ int intel_plane_atomic_calc_changes(const struct
intel_crtc_state *old_crtc_stat
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- bool mode_changed = needs_modeset(crtc_state);
+ bool mode_changed = intel_crtc_needs_modeset(crtc_state);
bool was_crtc_enabled = old_crtc_state->hw.active;
bool is_crtc_enabled = crtc_state->hw.active;
bool turn_off, turn_on, visible, was_visible;
@@ -12980,7 +12974,7 @@ static int intel_crtc_atomic_check(struct
intel_atomic_state *state,
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- bool mode_changed = needs_modeset(crtc_state);
+ bool mode_changed = intel_crtc_needs_modeset(crtc_state);
int ret;
if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
@@ -14812,7 +14806,7 @@ intel_modeset_verify_crtc(struct intel_crtc *crtc,
struct intel_crtc_state *old_crtc_state,
struct intel_crtc_state *new_crtc_state)
{
- if (!needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)
+ if (!intel_crtc_needs_modeset(new_crtc_state) &&
Re: [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [01/16] drm/i915/display: move needs_modeset to an inline in header
On Mon, 21 Dec 2020, Patchwork wrote: > == Series Details == > > Series: series starting with [01/16] drm/i915/display: move needs_modeset to > an inline in header > URL : https://patchwork.freedesktop.org/series/85129/ > State : failure > > == Summary == > > Applying: drm/i915/display: move needs_modeset to an inline in header > Applying: drm/i915/display: move to_intel_frontbuffer to header > Applying: drm/i915/display: fix misused comma > Applying: drm/i915: refactor cursor code out of i915_display.c > Applying: drm/i915: refactor i915 plane code into separate file. > Applying: drm/i915: refactor some crtc code out of intel display. (v2) > error: sha1 information is lacking or useless (drivers/gpu/drm/i915/Makefile). > error: could not build fake ancestor > hint: Use 'git am --show-current-patch=diff' to see the failed patch > Patch failed at 0006 drm/i915: refactor some crtc code out of intel display. > (v2) > When you have resolved this problem, run "git am --continue". > If you prefer to skip this patch, run "git am --skip" instead. > To restore the original branch and stop patching, run "git am --abort". I wonder what gives here. The same thing has been happening for several versions of the series, including mine. I would've applied the early patches already if I'd gotten some test results. BR, Jani. > > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
