[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/bios: Fix ports mask
== Series Details ==
Series: drm/i915/bios: Fix ports mask
URL : https://patchwork.freedesktop.org/series/92850/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10367_full -> Patchwork_20672_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_20672_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_pm_rpm@gem-execbuf-stress:
- {shard-rkl}:[PASS][1] -> [SKIP][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-rkl-2/igt@i915_pm_...@gem-execbuf-stress.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20672/shard-rkl-6/igt@i915_pm_...@gem-execbuf-stress.html
* igt@i915_pm_rpm@gem-mmap-type:
- {shard-rkl}:NOTRUN -> [SKIP][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20672/shard-rkl-6/igt@i915_pm_...@gem-mmap-type.html
* igt@i915_pm_rpm@modeset-lpsp-stress:
- {shard-rkl}:[SKIP][4] ([i915#1397]) -> [SKIP][5] +1 similar issue
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-rkl-1/igt@i915_pm_...@modeset-lpsp-stress.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20672/shard-rkl-6/igt@i915_pm_...@modeset-lpsp-stress.html
* igt@i915_pm_rpm@system-suspend:
- {shard-rkl}:[FAIL][6] ([fdo#103375]) -> [SKIP][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-rkl-2/igt@i915_pm_...@system-suspend.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20672/shard-rkl-6/igt@i915_pm_...@system-suspend.html
* igt@kms_vblank@pipe-c-ts-continuation-dpms-rpm:
- {shard-rkl}:[SKIP][8] ([i915#1845]) -> [SKIP][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-rkl-5/igt@kms_vbl...@pipe-c-ts-continuation-dpms-rpm.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20672/shard-rkl-6/igt@kms_vbl...@pipe-c-ts-continuation-dpms-rpm.html
Known issues
Here are the changes found in Patchwork_20672_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@feature_discovery@display-3x:
- shard-glk: NOTRUN -> [SKIP][10] ([fdo#109271]) +69 similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20672/shard-glk6/igt@feature_discov...@display-3x.html
* igt@feature_discovery@display-4x:
- shard-tglb: NOTRUN -> [SKIP][11] ([i915#1839])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20672/shard-tglb5/igt@feature_discov...@display-4x.html
* igt@gem_ctx_persistence@engines-hostile:
- shard-snb: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#1099]) +1
similar issue
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20672/shard-snb2/igt@gem_ctx_persiste...@engines-hostile.html
* igt@gem_ctx_persistence@many-contexts:
- shard-iclb: [PASS][13] -> [FAIL][14] ([i915#2410])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-iclb8/igt@gem_ctx_persiste...@many-contexts.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20672/shard-iclb3/igt@gem_ctx_persiste...@many-contexts.html
- shard-tglb: [PASS][15] -> [FAIL][16] ([i915#2410])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-tglb7/igt@gem_ctx_persiste...@many-contexts.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20672/shard-tglb5/igt@gem_ctx_persiste...@many-contexts.html
* igt@gem_exec_fair@basic-deadline:
- shard-apl: NOTRUN -> [FAIL][17] ([i915#2846])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20672/shard-apl6/igt@gem_exec_f...@basic-deadline.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-tglb: [PASS][18] -> [FAIL][19] ([i915#2842])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-tglb7/igt@gem_exec_fair@basic-none-sh...@rcs0.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20672/shard-tglb5/igt@gem_exec_fair@basic-none-sh...@rcs0.html
- shard-glk: [PASS][20] -> [FAIL][21] ([i915#2842]) +1 similar
issue
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-glk6/igt@gem_exec_fair@basic-none-sh...@rcs0.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20672/shard-glk4/igt@gem_exec_fair@basic-none-sh...@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-iclb: [PASS][22] -> [FAIL][23] ([i915#2842])
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-iclb2/igt@gem_exec_fair@basic-pace-s...@rcs0.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20672/shard-iclb1/igt@gem_exec_fair@basic-pace-s...@rcs0.html
- shard-kbl:
Re: [Intel-gfx] 5.14-rc2 warnings with kvmgvt
On Thu, Jul 22, 2021 at 05:24:30AM +0100, Christoph Hellwig wrote:
On Wed, Jul 21, 2021 at 05:18:18PM -0400, Rodrigo Vivi wrote:
could you please try this small patch?
I had to hand apply it as it wa corruped to due to cut off context.
It fixes one of the warnings, new output below:
[4.182820] i915 :00:04.0: [drm] Virtual GPU for Intel GVT-g detected.
[4.184076] i915 :00:04.0: [drm] VT-d active for gfx access
[4.185199] i915 :00:04.0: [drm] iGVT-g active, disabling use of stolen
memory
[4.207889] i915 :00:04.0: BAR 6: can't assign [??? 0x flags
0x2000] (bogus a)
[4.210062] i915 :00:04.0: [drm] Failed to find VBIOS tables (VBT)
[4.212256] i915 :00:04.0: vgaarb: changed VGA decodes:
olddecodes=io+mem,decodes=none:owm
[4.214447] i915 :00:04.0: Direct firmware load for
i915/kbl_dmc_ver1_04.bin failed with 2
[4.215447] i915 :00:04.0: [drm] Failed to load DMC firmware
i915/kbl_dmc_ver1_04.bin. Di.
[4.216643] i915 :00:04.0: [drm] DMC firmware homepage:
https://git.kernel.org/pub/scm/li5
[4.227760] i915 :00:04.0: [drm] failed to retrieve link info, disabling
eDP
[4.229706] [ cut here ]
[4.230204] Missing case (port == 5)
humn... PORT_F. KBL doesn't have PORT_F. We decided to keep the handling
of DISPLAY_VER == 10 and DISPLAY_VER == 9 together and trust the VBT,
but when the VBT is not present, DDI F will get added unconditio.
maybe best thing to do is to split that
---8<-
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index c274bfb8e549..44cad63e20fb 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11371,6 +11371,13 @@ static void intel_setup_outputs(struct
drm_i915_private *dev_priv)
intel_ddi_init(dev_priv, PORT_E);
intel_ddi_init(dev_priv, PORT_F);
icl_dsi_init(dev_priv);
+ } else if (DISPLAY_VER(dev_priv) == 10) {
+ intel_ddi_init(dev_priv, PORT_A);
+ intel_ddi_init(dev_priv, PORT_B);
+ intel_ddi_init(dev_priv, PORT_C);
+ intel_ddi_init(dev_priv, PORT_D);
+ intel_ddi_init(dev_priv, PORT_E);
+ intel_ddi_init(dev_priv, PORT_F);
} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
@@ -11382,7 +11389,6 @@ static void intel_setup_outputs(struct drm_i915_private
*dev_priv)
intel_ddi_init(dev_priv, PORT_C);
intel_ddi_init(dev_priv, PORT_D);
intel_ddi_init(dev_priv, PORT_E);
- intel_ddi_init(dev_priv, PORT_F);
} else if (HAS_DDI(dev_priv)) {
u32 found;
---8<-
thanks
Lucas De Marchi
[4.230652] WARNING: CPU: 3 PID: 1 at
drivers/gpu/drm/i915/display/intel_hdmi.c:2740 intel_hd0
[4.231815] Modules linked in:
[4.232146] CPU: 3 PID: 1 Comm: swapper/0 Not tainted 5.14.0-rc2+ #40
[4.232826] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS
1.14.0-2 04/01/2014
[4.233706] RIP: 0010:intel_hdmi_init_connector+0x7cf/0x880
[4.234330] Code: b6 fb 45 89 fb e9 bd fb ff ff 49 63 d7 48 c7 c6 da 67 18
83 44 89 44 24 10 4
[4.236289] RSP: :c9013be8 EFLAGS: 00010282
[4.236949] RAX: RBX: 888104cda000 RCX:
[4.237703] RDX: 0001 RSI: 831a7617 RDI:
[4.238499] RBP: 888104c01000 R08: 0001 R09: 0001
[4.239240] R10: R11: 3fff R12: 8881054c
[4.240112] R13: 0005 R14: 8881054c R15: 0005
[4.240963] FS: () GS:88813bd8()
knlGS:
[4.241856] CS: 0010 DS: ES: CR0: 80050033
[4.242533] CR2: CR3: 03462000 CR4: 06e0
[4.243437] Call Trace:
[4.243754] intel_ddi_init+0x88d/0xc30
[4.244216] intel_modeset_init_nogem+0xdab/0x1310
[4.244792] ? intel_irq_postinstall+0x1aa/0x520
[4.245372] i915_driver_probe+0x695/0xd30
[4.245908] ? _raw_spin_unlock_irqrestore+0x33/0x50
[4.246507] pci_device_probe+0xcd/0x140
[4.246933] really_probe.part.0+0x99/0x270
[4.247421] __driver_probe_device+0x8b/0x120
[4.247887] driver_probe_device+0x19/0x90
[4.248328] __driver_attach+0x79/0x120
[4.248740] ? __device_attach_driver+0x90/0x90
[4.249225] bus_for_each_dev+0x78/0xc0
[4.249637] bus_add_driver+0x109/0x1b0
[4.250051] driver_register+0x86/0xd0
[4.250512] ? ttm_init+0x18/0x18
[4.250884] i915_init+0x58/0x72
[4.251234] do_one_initcall+0x56/0x2e0
[4.251644] ? rcu_read_lock_sched_held+0x3a/0x70
[4.252150]
Re: [Intel-gfx] 5.14-rc2 warnings with kvmgvt
On Thu, Jul 22, 2021 at 01:05:49PM +0800, Zhenyu Wang wrote: > On 2021.07.21 13:10:49 +0200, Christoph Hellwig wrote: > > Hi all, > > > > I'm trying to test some changes for the gvt code, but even with a baseline > > 5.14-rc2 host and guest the 915 driver does not seem overly happy: > > > > I think we also got bug report on those display related warnings, should be > some issue with our virtual display model that doesn't work nicely with more > i915 > display pipe/port check or exercises have been added...But I believe you > should > still get virtual framebuffer up and show, right? Well, as soon as I add a display the warnings disappear anyway. Not sure how to test if the framebuffers gets up without the display. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/bios: Fix ports mask
On Wed, 2021-07-21 at 18:00 -0400, Rodrigo Vivi wrote:
> PORT_A to PORT_F are regular integers defined in the enum port,
> while for_each_port_masked requires a bit mask for the ports.
>
> Current given mask: 0b111
> Desired mask: 0b11
>
> I noticed this while Christoph was reporting a bug found on headless
> GVT configuration which bisect blamed commit 3ae04c0c7e63 ("drm/i915/bios:
> limit default outputs to ports A through F")
>
Reviewed-by: José Roberto de Souza
> Cc: Christoph Hellwig
> Fixes: 3ae04c0c7e63 ("drm/i915/bios: limit default outputs to ports A through
> F")
> Cc: Lucas De Marchi
> Cc: Ville Syrjälä
> Cc: Jani Nikula
> Signed-off-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index 5b6922e28ef2..8bbeb5978bf7 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -2166,7 +2166,8 @@ static void
> init_vbt_missing_defaults(struct drm_i915_private *i915)
> {
> enum port port;
> - int ports = PORT_A | PORT_B | PORT_C | PORT_D | PORT_E | PORT_F;
> + int ports = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | \
> + BIT(PORT_D) | BIT(PORT_E) | BIT(PORT_F);
>
> if (!HAS_DDI(i915) && !IS_CHERRYVIEW(i915))
> return;
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 07/10] drm/i915/bios: Enable parse of two DSI panels data
Continuing the conversion from single integrated VBT data to two, now
handling DSI data.
Cc: Ville Syrjälä
Cc: Jani Nikula
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/icl_dsi.c | 12 +-
drivers/gpu/drm/i915/display/intel_bios.c| 163 ++-
drivers/gpu/drm/i915/display/intel_bios.h| 1 +
drivers/gpu/drm/i915/display/intel_dsi.c | 8 +-
drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 58 ---
drivers/gpu/drm/i915/display/intel_panel.c | 3 +-
drivers/gpu/drm/i915/display/vlv_dsi.c | 14 +-
drivers/gpu/drm/i915/i915_drv.h | 30 ++--
8 files changed, 161 insertions(+), 128 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index 43ec7fcd3f5d2..0a8360d196cc7 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1846,7 +1846,8 @@ static void icl_dphy_param_init(struct intel_dsi
*intel_dsi)
{
struct drm_device *dev = intel_dsi->base.base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
+ const struct vbt_dsi_info *vbt_dsi_info =
intel_bios_dsi_info(_dsi->base);
+ struct mipi_config *mipi_config = vbt_dsi_info->config;
u32 tlpx_ns;
u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
u32 ths_prepare_ns, tclk_trail_ns;
@@ -1977,6 +1978,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
struct intel_connector *intel_connector;
struct drm_connector *connector;
struct drm_display_mode *fixed_mode;
+ const struct vbt_dsi_info *vbt_dsi_info;
enum port port;
if (!intel_bios_is_dsi_present(dev_priv, ))
@@ -2044,13 +2046,15 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
intel_panel_init(_connector->panel, fixed_mode, NULL);
intel_panel_setup_backlight(connector, INVALID_PIPE);
- if (dev_priv->vbt.dsi.config->dual_link)
+ vbt_dsi_info = intel_bios_dsi_info(encoder);
+
+ if (vbt_dsi_info->config->dual_link)
intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B);
else
intel_dsi->ports = BIT(port);
- intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports;
- intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports;
+ intel_dsi->dcs_backlight_ports = vbt_dsi_info->bl_ports;
+ intel_dsi->dcs_cabc_ports = vbt_dsi_info->cabc_ports;
for_each_dsi_port(port, intel_dsi->ports) {
struct intel_dsi_host *host;
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index de690e96de723..a1a1cc0c462fd 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1022,55 +1022,56 @@ parse_psr(struct drm_i915_private *i915, const struct
bdb_header *bdb,
}
static void parse_dsi_backlight_ports(struct drm_i915_private *i915,
- u16 version, enum port port)
+ u16 version, enum port port,
+ struct ddi_vbt_port_info *info)
{
- if (!i915->vbt.dsi.config->dual_link || version < 197) {
- i915->vbt.dsi.bl_ports = BIT(port);
- if (i915->vbt.dsi.config->cabc_supported)
- i915->vbt.dsi.cabc_ports = BIT(port);
+ if (!info->dsi.config->dual_link || version < 197) {
+ info->dsi.bl_ports = BIT(port);
+ if (info->dsi.config->cabc_supported)
+ info->dsi.cabc_ports = BIT(port);
return;
}
- switch (i915->vbt.dsi.config->dl_dcs_backlight_ports) {
+ switch (info->dsi.config->dl_dcs_backlight_ports) {
case DL_DCS_PORT_A:
- i915->vbt.dsi.bl_ports = BIT(PORT_A);
+ info->dsi.bl_ports = BIT(PORT_A);
break;
case DL_DCS_PORT_C:
- i915->vbt.dsi.bl_ports = BIT(PORT_C);
+ info->dsi.bl_ports = BIT(PORT_C);
break;
default:
case DL_DCS_PORT_A_AND_C:
- i915->vbt.dsi.bl_ports = BIT(PORT_A) | BIT(PORT_C);
+ info->dsi.bl_ports = BIT(PORT_A) | BIT(PORT_C);
break;
}
- if (!i915->vbt.dsi.config->cabc_supported)
+ if (!info->dsi.config->cabc_supported)
return;
- switch (i915->vbt.dsi.config->dl_dcs_cabc_ports) {
+ switch (info->dsi.config->dl_dcs_cabc_ports) {
case DL_DCS_PORT_A:
- i915->vbt.dsi.cabc_ports = BIT(PORT_A);
+ info->dsi.cabc_ports = BIT(PORT_A);
break;
case DL_DCS_PORT_C:
- i915->vbt.dsi.cabc_ports = BIT(PORT_C);
+ info->dsi.cabc_ports = BIT(PORT_C);
break;
default:
case
[Intel-gfx] [PATCH 10/10] drm/i915/display/tgl+: Use PPS index from vbt
Tigerlake and newer has two instances of PPS, to support up to two eDP panels. Cc: Ville Syrjälä Cc: Jani Nikula Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_pps.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index f4c15a1f31d15..ee92f416834e5 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -368,7 +368,8 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp, memset(regs, 0, sizeof(*regs)); - if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) + if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) || + DISPLAY_VER(dev_priv) >= 12) pps_idx = bxt_power_sequencer_idx(intel_dp); else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) pps_idx = vlv_power_sequencer_pipe(intel_dp); -- 2.32.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 06/10] drm/i915/bios: Enable parse of two integrated panels PSR data
Continuing the conversion from single integrated VBT data to two, now
handling PSR data.
Cc: Ville Syrjälä
Cc: Jani Nikula
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_bios.c | 73 +--
drivers/gpu/drm/i915/display/intel_bios.h | 2 +
drivers/gpu/drm/i915/display/intel_psr.c | 30 ++
drivers/gpu/drm/i915/i915_drv.h | 34 +--
4 files changed, 77 insertions(+), 62 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index f0d49af8be036..de690e96de723 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -729,15 +729,12 @@ parse_driver_features(struct drm_i915_private *i915,
driver->lvds_config != BDB_DRIVER_FEATURE_INT_SDVO_LVDS)
i915->vbt.int_lvds_support = 0;
}
-
- if (bdb->version < 228)
- i915->vbt.psr.enable = driver->psr_enabled;
}
static void
-parse_driver_features_drrs_only(struct drm_i915_private *i915,
- const struct bdb_header *bdb,
- struct ddi_vbt_port_info *info)
+parse_driver_features_drrs_psr_only(struct drm_i915_private *i915,
+ const struct bdb_header *bdb,
+ struct ddi_vbt_port_info *info)
{
const struct bdb_driver_features *driver;
@@ -757,6 +754,8 @@ parse_driver_features_drrs_only(struct drm_i915_private
*i915,
*/
if (!driver->drrs_enabled)
info->drrs_type = DRRS_NOT_SUPPORTED;
+
+ info->psr.enable = driver->psr_enabled;
}
static void
@@ -774,7 +773,7 @@ parse_power_conservation_features(struct drm_i915_private
*i915,
if (!power)
return;
- i915->vbt.psr.enable = power->psr & BIT(panel_index);
+ info->psr.enable = power->psr & BIT(panel_index);
/*
* If DRRS is not supported, drrs_type has to be set to 0.
@@ -905,11 +904,11 @@ parse_edp(struct drm_i915_private *i915, const struct
bdb_header *bdb,
}
static void
-parse_psr(struct drm_i915_private *i915, const struct bdb_header *bdb)
+parse_psr(struct drm_i915_private *i915, const struct bdb_header *bdb,
+ struct ddi_vbt_port_info *info, int panel_index)
{
const struct bdb_psr *psr;
const struct psr_table *psr_table;
- int panel_type = i915->vbt.panel_type;
psr = find_section(bdb, BDB_PSR);
if (!psr) {
@@ -917,27 +916,27 @@ parse_psr(struct drm_i915_private *i915, const struct
bdb_header *bdb)
return;
}
- psr_table = >psr_table[panel_type];
+ psr_table = >psr_table[panel_index];
- i915->vbt.psr.full_link = psr_table->full_link;
- i915->vbt.psr.require_aux_wakeup = psr_table->require_aux_to_wakeup;
+ info->psr.full_link = psr_table->full_link;
+ info->psr.require_aux_wakeup = psr_table->require_aux_to_wakeup;
/* Allowed VBT values goes from 0 to 15 */
- i915->vbt.psr.idle_frames = psr_table->idle_frames < 0 ? 0 :
+ info->psr.idle_frames = psr_table->idle_frames < 0 ? 0 :
psr_table->idle_frames > 15 ? 15 : psr_table->idle_frames;
switch (psr_table->lines_to_wait) {
case 0:
- i915->vbt.psr.lines_to_wait = PSR_0_LINES_TO_WAIT;
+ info->psr.lines_to_wait = PSR_0_LINES_TO_WAIT;
break;
case 1:
- i915->vbt.psr.lines_to_wait = PSR_1_LINE_TO_WAIT;
+ info->psr.lines_to_wait = PSR_1_LINE_TO_WAIT;
break;
case 2:
- i915->vbt.psr.lines_to_wait = PSR_4_LINES_TO_WAIT;
+ info->psr.lines_to_wait = PSR_4_LINES_TO_WAIT;
break;
case 3:
- i915->vbt.psr.lines_to_wait = PSR_8_LINES_TO_WAIT;
+ info->psr.lines_to_wait = PSR_8_LINES_TO_WAIT;
break;
default:
drm_dbg_kms(>drm,
@@ -954,13 +953,13 @@ parse_psr(struct drm_i915_private *i915, const struct
bdb_header *bdb)
(DISPLAY_VER(i915) >= 9 && !IS_BROXTON(i915))) {
switch (psr_table->tp1_wakeup_time) {
case 0:
- i915->vbt.psr.tp1_wakeup_time_us = 500;
+ info->psr.tp1_wakeup_time_us = 500;
break;
case 1:
- i915->vbt.psr.tp1_wakeup_time_us = 100;
+ info->psr.tp1_wakeup_time_us = 100;
break;
case 3:
- i915->vbt.psr.tp1_wakeup_time_us = 0;
+ info->psr.tp1_wakeup_time_us = 0;
break;
default:
drm_dbg_kms(>drm,
@@ -968,19 +967,19 @@ parse_psr(struct drm_i915_private *i915, const struct
bdb_header *bdb)
[Intel-gfx] [PATCH 04/10] drm/i915/bios: Enable parse of two integrated panels backlight data
Continuing the conversion from single integrated VBT data to two, now
handling backlight data.
Cc: Ville Syrjälä
Cc: Jani Nikula
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_bios.c | 59 +++
drivers/gpu/drm/i915/display/intel_bios.h | 1 +
.../drm/i915/display/intel_dp_aux_backlight.c | 11 ++--
.../i915/display/intel_dsi_dcs_backlight.c| 5 +-
drivers/gpu/drm/i915/display/intel_panel.c| 32 ++
drivers/gpu/drm/i915/display/intel_pps.c | 8 ++-
drivers/gpu/drm/i915/i915_drv.h | 18 +++---
7 files changed, 83 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 5906e9fa8f976..6770ed8b260be 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -441,11 +441,12 @@ parse_panel_dtd(struct drm_i915_private *i915,
static void
parse_lfp_backlight(struct drm_i915_private *i915,
- const struct bdb_header *bdb)
+ const struct bdb_header *bdb,
+ struct ddi_vbt_port_info *info,
+ int panel_index)
{
const struct bdb_lfp_backlight_data *backlight_data;
const struct lfp_backlight_data_entry *entry;
- int panel_type = i915->vbt.panel_type;
u16 level;
backlight_data = find_section(bdb, BDB_LVDS_BACKLIGHT);
@@ -459,38 +460,38 @@ parse_lfp_backlight(struct drm_i915_private *i915,
return;
}
- entry = _data->data[panel_type];
+ entry = _data->data[panel_index];
- i915->vbt.backlight.present = entry->type == BDB_BACKLIGHT_TYPE_PWM;
- if (!i915->vbt.backlight.present) {
+ info->backlight.present = entry->type == BDB_BACKLIGHT_TYPE_PWM;
+ if (!info->backlight.present) {
drm_dbg_kms(>drm,
"PWM backlight not present in VBT (type %u)\n",
entry->type);
return;
}
- i915->vbt.backlight.type = INTEL_BACKLIGHT_DISPLAY_DDI;
+ info->backlight.type = INTEL_BACKLIGHT_DISPLAY_DDI;
if (bdb->version >= 191 &&
get_blocksize(backlight_data) >= sizeof(*backlight_data)) {
const struct lfp_backlight_control_method *method;
- method = _data->backlight_control[panel_type];
- i915->vbt.backlight.type = method->type;
- i915->vbt.backlight.controller = method->controller;
+ method = _data->backlight_control[panel_index];
+ info->backlight.type = method->type;
+ info->backlight.controller = method->controller;
}
- i915->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz;
- i915->vbt.backlight.active_low_pwm = entry->active_low_pwm;
+ info->backlight.pwm_freq_hz = entry->pwm_freq_hz;
+ info->backlight.active_low_pwm = entry->active_low_pwm;
if (bdb->version >= 234) {
u16 min_level;
bool scale;
- level = backlight_data->brightness_level[panel_type].level;
- min_level =
backlight_data->brightness_min_level[panel_type].level;
+ level = backlight_data->brightness_level[panel_index].level;
+ min_level =
backlight_data->brightness_min_level[panel_index].level;
if (bdb->version >= 236)
- scale =
backlight_data->brightness_precision_bits[panel_type] == 16;
+ scale =
backlight_data->brightness_precision_bits[panel_index] == 16;
else
scale = level > 255;
@@ -501,20 +502,20 @@ parse_lfp_backlight(struct drm_i915_private *i915,
drm_warn(>drm, "Brightness min level > 255\n");
level = 255;
}
- i915->vbt.backlight.min_brightness = min_level;
+ info->backlight.min_brightness = min_level;
} else {
- level = backlight_data->level[panel_type];
- i915->vbt.backlight.min_brightness = entry->min_brightness;
+ level = backlight_data->level[panel_index];
+ info->backlight.min_brightness = entry->min_brightness;
}
drm_dbg_kms(>drm,
"VBT backlight PWM modulation frequency %u Hz, "
"active %s, min brightness %u, level %u, controller %u\n",
- i915->vbt.backlight.pwm_freq_hz,
- i915->vbt.backlight.active_low_pwm ? "low" : "high",
- i915->vbt.backlight.min_brightness,
+ info->backlight.pwm_freq_hz,
+ info->backlight.active_low_pwm ? "low" : "high",
+ info->backlight.min_brightness,
level,
- i915->vbt.backlight.controller);
+
[Intel-gfx] [PATCH 08/10] drm/i915/bios: Nuke panel_type
All the users was converted now we can drop it.
Cc: Jani Nikula
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_bios.c | 36 ---
drivers/gpu/drm/i915/i915_drv.h | 1 -
2 files changed, 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index a1a1cc0c462fd..d1ad6d625e521 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -211,41 +211,6 @@ get_lvds_fp_timing(const struct bdb_header *bdb,
return (const struct lvds_fp_timing *)((const u8 *)bdb + ofs);
}
-/*
- * Parse and set vbt.panel_type, it will be used by the VBT blocks that are
- * not being called from parse_integrated_panel() yet.
- */
-static void parse_panel_type(struct drm_i915_private *i915,
-const struct bdb_header *bdb)
-{
- const struct bdb_lvds_options *lvds_options;
- int ret, panel_type;
-
- lvds_options = find_section(bdb, BDB_LVDS_OPTIONS);
- if (!lvds_options)
- return;
-
- ret = intel_opregion_get_panel_type(i915);
- if (ret >= 0) {
- drm_WARN_ON(>drm, ret > 0xf);
- panel_type = ret;
- drm_dbg_kms(>drm, "Panel type: %d (OpRegion)\n",
- panel_type);
- } else {
- if (lvds_options->panel_type > 0xf) {
- drm_dbg_kms(>drm,
- "Invalid VBT panel type 0x%x\n",
- lvds_options->panel_type);
- return;
- }
- panel_type = lvds_options->panel_type;
- drm_dbg_kms(>drm, "Panel type: %d (VBT)\n",
- panel_type);
- }
-
- i915->vbt.panel_type = panel_type;
-}
-
/* Parse general panel options */
static void
parse_panel_options(struct drm_i915_private *i915,
@@ -2489,7 +2454,6 @@ void intel_bios_init(struct drm_i915_private *i915)
/* Grab useful general definitions */
parse_general_features(i915, bdb);
parse_general_definitions(i915, bdb);
- parse_panel_type(i915, bdb);
parse_sdvo_panel_data(i915, bdb);
parse_driver_features(i915, bdb);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index adcacb8cb248a..8a09f9ed881b9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -729,7 +729,6 @@ struct intel_vbt_data {
unsigned int int_lvds_support:1;
unsigned int display_clock_mode:1;
unsigned int fdi_rx_polarity_inverted:1;
- unsigned int panel_type:4;
int lvds_ssc_freq;
unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
enum drm_panel_orientation orientation;
--
2.32.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 05/10] drm/i915/bios: Enable parse of two integrated panels eDP data
Continuing the conversion from single integrated VBT data to two, now
handling eDP data.
Cc: Ville Syrjälä
Cc: Jani Nikula
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/g4x_dp.c | 9 +--
drivers/gpu/drm/i915/display/intel_bios.c | 62 +---
drivers/gpu/drm/i915/display/intel_bios.h | 1 +
drivers/gpu/drm/i915/display/intel_ddi.c | 9 +--
.../drm/i915/display/intel_ddi_buf_trans.c| 71 ++-
drivers/gpu/drm/i915/display/intel_dp.c | 7 +-
drivers/gpu/drm/i915/display/intel_pps.c | 4 +-
drivers/gpu/drm/i915/i915_drv.h | 24 +++
8 files changed, 101 insertions(+), 86 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c
b/drivers/gpu/drm/i915/display/g4x_dp.c
index de0f358184aa3..273bc5295ae33 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -340,6 +340,7 @@ static void intel_dp_get_config(struct intel_encoder
*encoder,
u32 tmp, flags = 0;
enum port port = encoder->port;
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct vbt_edp_info *vbt_edp_info = intel_bios_edp_info(encoder);
if (encoder->type == INTEL_OUTPUT_EDP)
pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
@@ -396,8 +397,8 @@ static void intel_dp_get_config(struct intel_encoder
*encoder,
intel_dotclock_calculate(pipe_config->port_clock,
_config->dp_m_n);
- if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
- pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
+ if (intel_dp_is_edp(intel_dp) && vbt_edp_info->bpp &&
+ pipe_config->pipe_bpp > vbt_edp_info->bpp) {
/*
* This is a big fat ugly hack.
*
@@ -413,8 +414,8 @@ static void intel_dp_get_config(struct intel_encoder
*encoder,
*/
drm_dbg_kms(_priv->drm,
"pipe has %d bpp for eDP panel, overriding
BIOS-provided max %d bpp\n",
- pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
- dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
+ pipe_config->pipe_bpp, vbt_edp_info->bpp);
+ vbt_edp_info->bpp = pipe_config->pipe_bpp;
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 6770ed8b260be..f0d49af8be036 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -786,45 +786,45 @@ parse_power_conservation_features(struct drm_i915_private
*i915,
info->drrs_type = DRRS_NOT_SUPPORTED;
if (bdb->version >= 232)
- i915->vbt.edp.hobl = power->hobl & BIT(panel_index);
+ info->edp.hobl = power->hobl & BIT(panel_index);
}
static void
-parse_edp(struct drm_i915_private *i915, const struct bdb_header *bdb)
+parse_edp(struct drm_i915_private *i915, const struct bdb_header *bdb,
+ struct ddi_vbt_port_info *info, int panel_index)
{
const struct bdb_edp *edp;
const struct edp_power_seq *edp_pps;
const struct edp_fast_link_params *edp_link_params;
- int panel_type = i915->vbt.panel_type;
edp = find_section(bdb, BDB_EDP);
if (!edp)
return;
- switch ((edp->color_depth >> (panel_type * 2)) & 3) {
+ switch ((edp->color_depth >> (panel_index * 2)) & 3) {
case EDP_18BPP:
- i915->vbt.edp.bpp = 18;
+ info->edp.bpp = 18;
break;
case EDP_24BPP:
- i915->vbt.edp.bpp = 24;
+ info->edp.bpp = 24;
break;
case EDP_30BPP:
- i915->vbt.edp.bpp = 30;
+ info->edp.bpp = 30;
break;
}
/* Get the eDP sequencing and link info */
- edp_pps = >power_seqs[panel_type];
- edp_link_params = >fast_link_params[panel_type];
+ edp_pps = >power_seqs[panel_index];
+ edp_link_params = >fast_link_params[panel_index];
- i915->vbt.edp.pps = *edp_pps;
+ info->edp.pps = *edp_pps;
switch (edp_link_params->rate) {
case EDP_RATE_1_62:
- i915->vbt.edp.rate = DP_LINK_BW_1_62;
+ info->edp.rate = DP_LINK_BW_1_62;
break;
case EDP_RATE_2_7:
- i915->vbt.edp.rate = DP_LINK_BW_2_7;
+ info->edp.rate = DP_LINK_BW_2_7;
break;
default:
drm_dbg_kms(>drm,
@@ -835,13 +835,13 @@ parse_edp(struct drm_i915_private *i915, const struct
bdb_header *bdb)
switch (edp_link_params->lanes) {
case EDP_LANE_1:
- i915->vbt.edp.lanes = 1;
+ info->edp.lanes = 1;
break;
case EDP_LANE_2:
-
[Intel-gfx] [PATCH 09/10] drm/i915/bios: Only use opregion panel index for display ver 8 and older
On newer platform this opregion call always fails, also it do not
support multiple panels so dropping it.
Cc: Ville Syrjälä
Cc: Jani Nikula
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_bios.c | 19 +++
1 file changed, 7 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index d1ad6d625e521..6c848384a2ada 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1924,7 +1924,7 @@ static void parse_integrated_panel(struct
drm_i915_private *i915,
{
const struct vbt_header *vbt = i915->opregion.vbt;
const struct bdb_header *bdb;
- int lfp_inst = 0, panel_index, opregion_panel_index;
+ int lfp_inst = 0, panel_index;
if (devdata->child.handle == HANDLE_LFP_1)
lfp_inst = 1;
@@ -1937,17 +1937,12 @@ static void parse_integrated_panel(struct
drm_i915_private *i915,
bdb = get_bdb_header(vbt);
panel_index = get_lfp_panel_index(i915, bdb, lfp_inst);
- opregion_panel_index = intel_opregion_get_panel_type(i915);
- /*
-* TODO: the current implementation always use the panel index from
-* opregion if available due to issues with old platforms.
-* But this do not supports two panels and in SKL or newer I never saw a
-* system were this call returns a valid value.
-* So will change this to only use opregion up to BDW in a separated
-* commit.
-*/
- if (opregion_panel_index >= 0)
- panel_index = opregion_panel_index;
+ if (DISPLAY_VER(i915) < 9) {
+ int opregion_panel_index = intel_opregion_get_panel_type(i915);
+
+ if (opregion_panel_index >= 0)
+ opregion_panel_index = panel_index;
+ }
if (panel_index == -1)
return;
--
2.32.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 03/10] drm/i915/bios: Enable parse of two integrated panels timing data
Continuing the conversion from single integrated VBT data to two.
Cc: Ville Syrjälä
Cc: Jani Nikula
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_bios.c| 53 +---
drivers/gpu/drm/i915/display/intel_bios.h| 1 +
drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 7 ++-
drivers/gpu/drm/i915/display/intel_panel.c | 7 +--
drivers/gpu/drm/i915/i915_drv.h | 3 +-
5 files changed, 48 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 2b90efb41ecce..5906e9fa8f976 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -289,14 +289,15 @@ parse_panel_options(struct drm_i915_private *i915,
/* Try to find integrated panel timing data */
static void
parse_lfp_panel_dtd(struct drm_i915_private *i915,
- const struct bdb_header *bdb)
+ const struct bdb_header *bdb,
+ struct ddi_vbt_port_info *info,
+ int panel_index)
{
const struct bdb_lvds_lfp_data *lvds_lfp_data;
const struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs;
const struct lvds_dvo_timing *panel_dvo_timing;
const struct lvds_fp_timing *fp_timing;
struct drm_display_mode *panel_fixed_mode;
- int panel_type = i915->vbt.panel_type;
lvds_lfp_data = find_section(bdb, BDB_LVDS_LFP_DATA);
if (!lvds_lfp_data)
@@ -308,7 +309,7 @@ parse_lfp_panel_dtd(struct drm_i915_private *i915,
panel_dvo_timing = get_lvds_dvo_timing(lvds_lfp_data,
lvds_lfp_data_ptrs,
- panel_type);
+ panel_index);
panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);
if (!panel_fixed_mode)
@@ -316,7 +317,7 @@ parse_lfp_panel_dtd(struct drm_i915_private *i915,
fill_detail_timing_data(panel_fixed_mode, panel_dvo_timing);
- i915->vbt.lfp_lvds_vbt_mode = panel_fixed_mode;
+ info->lfp_lvds_vbt_mode = panel_fixed_mode;
drm_dbg_kms(>drm,
"Found panel mode in BIOS VBT legacy lfp table:\n");
@@ -324,7 +325,7 @@ parse_lfp_panel_dtd(struct drm_i915_private *i915,
fp_timing = get_lvds_fp_timing(bdb, lvds_lfp_data,
lvds_lfp_data_ptrs,
- panel_type);
+ panel_index);
if (fp_timing) {
/* check the resolution, just to be sure */
if (fp_timing->x_res == panel_fixed_mode->hdisplay &&
@@ -339,7 +340,9 @@ parse_lfp_panel_dtd(struct drm_i915_private *i915,
static void
parse_generic_dtd(struct drm_i915_private *i915,
- const struct bdb_header *bdb)
+ const struct bdb_header *bdb,
+ struct ddi_vbt_port_info *info,
+ int panel_index)
{
const struct bdb_generic_dtd *generic_dtd;
const struct generic_dtd_entry *dtd;
@@ -363,14 +366,14 @@ parse_generic_dtd(struct drm_i915_private *i915,
num_dtd = (get_blocksize(generic_dtd) -
sizeof(struct bdb_generic_dtd)) / generic_dtd->gdtd_size;
- if (i915->vbt.panel_type >= num_dtd) {
+ if (panel_index >= num_dtd) {
drm_err(>drm,
- "Panel type %d not found in table of %d DTD's\n",
- i915->vbt.panel_type, num_dtd);
+ "Panel index %d not found in table of %d DTD's\n",
+ panel_index, num_dtd);
return;
}
- dtd = _dtd->dtd[i915->vbt.panel_type];
+ dtd = _dtd->dtd[panel_index];
panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);
if (!panel_fixed_mode)
@@ -413,12 +416,14 @@ parse_generic_dtd(struct drm_i915_private *i915,
"Found panel mode in BIOS VBT generic dtd table:\n");
drm_mode_debug_printmodeline(panel_fixed_mode);
- i915->vbt.lfp_lvds_vbt_mode = panel_fixed_mode;
+ info->lfp_lvds_vbt_mode = panel_fixed_mode;
}
static void
parse_panel_dtd(struct drm_i915_private *i915,
- const struct bdb_header *bdb)
+ const struct bdb_header *bdb,
+ struct ddi_vbt_port_info *info,
+ int panel_index)
{
/*
* Older VBTs provided provided DTD information for internal displays
@@ -429,9 +434,9 @@ parse_panel_dtd(struct drm_i915_private *i915,
* back to trying the old LFP block if that fails.
*/
if (bdb->version >= 229)
- parse_generic_dtd(i915, bdb);
- if (!i915->vbt.lfp_lvds_vbt_mode)
- parse_lfp_panel_dtd(i915, bdb);
+ parse_generic_dtd(i915, bdb, info, panel_index);
+ if
[Intel-gfx] [PATCH 01/10] drm/i915/bios: Allow DSI ports to be parsed by parse_ddi_port()
Allow MIPI DSI ports to be parsed like any other DDI port.
This will be helpful to integrate into just one function the parse of
information about integrated panels(eDP and DSI).
Allow MIPI DSI ports to be parsed to be parsed like any other DDI
port.
This will be helpful to integrate into just one function the parse of
information about integrated panels(eDP and DSI).
Cc: Ville Syrjälä
Cc: Jani Nikula
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_bios.c | 22 +++---
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 5b6922e28ef28..5bc2c944d99b4 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1709,10 +1709,10 @@ static enum port dvo_port_to_port(struct
drm_i915_private *i915,
* so look for all the possible values for each port.
*/
static const int port_mapping[][3] = {
- [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
- [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },
- [PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
- [PORT_D] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
+ [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, DVO_PORT_MIPIA },
+ [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, DVO_PORT_MIPIB },
+ [PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, DVO_PORT_MIPIC },
+ [PORT_D] = { DVO_PORT_HDMID, DVO_PORT_DPD, DVO_PORT_MIPID },
[PORT_E] = { DVO_PORT_HDMIE, DVO_PORT_DPE, DVO_PORT_CRT },
[PORT_F] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1 },
[PORT_G] = { DVO_PORT_HDMIG, DVO_PORT_DPG, -1 },
@@ -1868,6 +1868,12 @@ intel_bios_encoder_supports_edp(const struct
intel_bios_encoder_data *devdata)
devdata->child.device_type & DEVICE_TYPE_INTERNAL_CONNECTOR;
}
+static bool
+intel_bios_encoder_supports_dsi(const struct intel_bios_encoder_data *devdata)
+{
+ return devdata->child.device_type & DEVICE_TYPE_MIPI_OUTPUT;
+}
+
static bool is_port_valid(struct drm_i915_private *i915, enum port port)
{
/*
@@ -1886,7 +1892,8 @@ static void parse_ddi_port(struct drm_i915_private *i915,
{
const struct child_device_config *child = >child;
struct ddi_vbt_port_info *info;
- bool is_dvi, is_hdmi, is_dp, is_edp, is_crt, supports_typec_usb,
supports_tbt;
+ bool is_dvi, is_hdmi, is_dp, is_edp, is_crt, supports_typec_usb;
+ bool supports_tbt, is_dsi;
int dp_boost_level, hdmi_boost_level;
enum port port;
@@ -1917,16 +1924,17 @@ static void parse_ddi_port(struct drm_i915_private
*i915,
is_crt = intel_bios_encoder_supports_crt(devdata);
is_hdmi = intel_bios_encoder_supports_hdmi(devdata);
is_edp = intel_bios_encoder_supports_edp(devdata);
+ is_dsi = intel_bios_encoder_supports_dsi(devdata);
supports_typec_usb = intel_bios_encoder_supports_typec_usb(devdata);
supports_tbt = intel_bios_encoder_supports_tbt(devdata);
drm_dbg_kms(>drm,
- "Port %c VBT info: CRT:%d DVI:%d HDMI:%d DP:%d eDP:%d
LSPCON:%d USB-Type-C:%d TBT:%d DSC:%d\n",
+ "Port %c VBT info: CRT:%d DVI:%d HDMI:%d DP:%d eDP:%d
LSPCON:%d USB-Type-C:%d TBT:%d DSC:%d DSI:%d\n",
port_name(port), is_crt, is_dvi, is_hdmi, is_dp, is_edp,
HAS_LSPCON(i915) && child->lspcon,
supports_typec_usb, supports_tbt,
- devdata->dsc != NULL);
+ devdata->dsc != NULL, is_dsi);
if (is_dvi) {
u8 ddc_pin;
--
2.32.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 02/10] drm/i915/bios: Start to support two integrated panels
VBT has support for up two integrated panels but i915 only supports one.
So here stating to add the basic support for two integrated panels
and moving the DRRS to ddi_vbt_port_info instead of keeping a global
one.
Other VBT blocks will be converted in following patches.
While at is also nucking lvds_dither as it is not used.
Cc: Ville Syrjälä
Cc: Jani Nikula
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_bios.c | 185 +-
drivers/gpu/drm/i915/display/intel_bios.h | 2 +
drivers/gpu/drm/i915/display/intel_dp.c | 5 +-
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 3 +
drivers/gpu/drm/i915/i915_drv.h | 5 +-
5 files changed, 150 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 5bc2c944d99b4..2b90efb41ecce 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -211,22 +211,20 @@ get_lvds_fp_timing(const struct bdb_header *bdb,
return (const struct lvds_fp_timing *)((const u8 *)bdb + ofs);
}
-/* Parse general panel options */
-static void
-parse_panel_options(struct drm_i915_private *i915,
- const struct bdb_header *bdb)
+/*
+ * Parse and set vbt.panel_type, it will be used by the VBT blocks that are
+ * not being called from parse_integrated_panel() yet.
+ */
+static void parse_panel_type(struct drm_i915_private *i915,
+const struct bdb_header *bdb)
{
const struct bdb_lvds_options *lvds_options;
- int panel_type;
- int drrs_mode;
- int ret;
+ int ret, panel_type;
lvds_options = find_section(bdb, BDB_LVDS_OPTIONS);
if (!lvds_options)
return;
- i915->vbt.lvds_dither = lvds_options->pixel_dither;
-
ret = intel_opregion_get_panel_type(i915);
if (ret >= 0) {
drm_WARN_ON(>drm, ret > 0xf);
@@ -246,9 +244,25 @@ parse_panel_options(struct drm_i915_private *i915,
}
i915->vbt.panel_type = panel_type;
+}
+
+/* Parse general panel options */
+static void
+parse_panel_options(struct drm_i915_private *i915,
+ const struct bdb_header *bdb,
+ struct ddi_vbt_port_info *info,
+ int panel_index)
+{
+ const struct bdb_lvds_options *lvds_options;
+ int drrs_mode;
+
+ lvds_options = find_section(bdb, BDB_LVDS_OPTIONS);
+ if (!lvds_options)
+ return;
+
+ drrs_mode = lvds_options->dps_panel_type_bits >> (panel_index * 2);
+ drrs_mode &= MODE_MASK;
- drrs_mode = (lvds_options->dps_panel_type_bits
- >> (panel_type * 2)) & MODE_MASK;
/*
* VBT has static DRRS = 0 and seamless DRRS = 2.
* The below piece of code is required to adjust vbt.drrs_type
@@ -256,16 +270,16 @@ parse_panel_options(struct drm_i915_private *i915,
*/
switch (drrs_mode) {
case 0:
- i915->vbt.drrs_type = STATIC_DRRS_SUPPORT;
+ info->drrs_type = STATIC_DRRS_SUPPORT;
drm_dbg_kms(>drm, "DRRS supported mode is static\n");
break;
case 2:
- i915->vbt.drrs_type = SEAMLESS_DRRS_SUPPORT;
+ info->drrs_type = SEAMLESS_DRRS_SUPPORT;
drm_dbg_kms(>drm,
"DRRS supported mode is seamless\n");
break;
default:
- i915->vbt.drrs_type = DRRS_NOT_SUPPORTED;
+ info->drrs_type = DRRS_NOT_SUPPORTED;
drm_dbg_kms(>drm,
"DRRS not supported (VBT input)\n");
break;
@@ -710,28 +724,42 @@ parse_driver_features(struct drm_i915_private *i915,
i915->vbt.int_lvds_support = 0;
}
- if (bdb->version < 228) {
- drm_dbg_kms(>drm, "DRRS State Enabled:%d\n",
- driver->drrs_enabled);
- /*
-* If DRRS is not supported, drrs_type has to be set to 0.
-* This is because, VBT is configured in such a way that
-* static DRRS is 0 and DRRS not supported is represented by
-* driver->drrs_enabled=false
-*/
- if (!driver->drrs_enabled)
- i915->vbt.drrs_type = DRRS_NOT_SUPPORTED;
-
+ if (bdb->version < 228)
i915->vbt.psr.enable = driver->psr_enabled;
- }
+}
+
+static void
+parse_driver_features_drrs_only(struct drm_i915_private *i915,
+ const struct bdb_header *bdb,
+ struct ddi_vbt_port_info *info)
+{
+ const struct bdb_driver_features *driver;
+
+ if (bdb->version >= 228)
+ return;
+
+ driver = find_section(bdb, BDB_DRIVER_FEATURES);
+ if (!driver)
+
Re: [Intel-gfx] 5.14-rc2 warnings with kvmgvt
On 2021.07.21 13:10:49 +0200, Christoph Hellwig wrote: > Hi all, > > I'm trying to test some changes for the gvt code, but even with a baseline > 5.14-rc2 host and guest the 915 driver does not seem overly happy: > I think we also got bug report on those display related warnings, should be some issue with our virtual display model that doesn't work nicely with more i915 display pipe/port check or exercises have been added...But I believe you should still get virtual framebuffer up and show, right? > [5.693099] i915 :00:04.0: [drm] Virtual GPU for Intel GVT-g detected. > [5.694841] i915 :00:04.0: [drm] VT-d active for gfx access > [5.696411] i915 :00:04.0: [drm] iGVT-g active, disabling use of > stolen memory > [5.711317] i915 :00:04.0: BAR 6: can't assign [??? 0x flags > 0x2000] (bogus alignm) > [5.712847] i915 :00:04.0: [drm] Failed to find VBIOS tables (VBT) > [5.714343] i915 :00:04.0: vgaarb: changed VGA decodes: > olddecodes=io+mem,decodes=none:owns=iom > [5.716466] i915 :00:04.0: Direct firmware load for > i915/kbl_dmc_ver1_04.bin failed with error2 > [5.718021] i915 :00:04.0: [drm] Failed to load DMC firmware > i915/kbl_dmc_ver1_04.bin. Disabli. > [5.719914] i915 :00:04.0: [drm] DMC firmware homepage: > https://git.kernel.org/pub/scm/linux/k5 > [5.733269] i915 :00:04.0: [drm] failed to retrieve link info, > disabling eDP > [5.735841] i915 :00:04.0: [drm] *ERROR* crtc 51: Can't calculate > constants, dotclock = 0! > [5.737354] [ cut here ] > [5.738141] i915 :00:04.0: > drm_WARN_ON_ONCE(drm_drv_uses_atomic_modeset(dev)) > [5.738165] WARNING: CPU: 0 PID: 1 at drivers/gpu/drm/drm_vblank.c:728 > drm_crtc_vblank_helper_get_0 > [5.738745] Modules linked in: > [5.738745] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.14.0-rc2+ #22 > [5.738745] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS > 1.14.0-2 04/01/2014 > [5.738745] RIP: > 0010:drm_crtc_vblank_helper_get_vblank_timestamp_internal+0x335/0x350 > [5.738745] Code: 4c 8b 6f 50 4d 85 ed 75 03 4c 8b 2f e8 34 10 26 00 48 c7 > c1 20 54 0d 83 4c 89 ea0 > [5.738745] RSP: :c9013a90 EFLAGS: 00010086 > [5.738745] RAX: RBX: 81c3c5b0 RCX: > > [5.738745] RDX: 0003 RSI: fffe RDI: > > [5.738745] RBP: c9013b00 R08: 83bb3e28 R09: > 0003 > [5.738745] R10: 834b3e40 R11: 3fff R12: > > [5.738745] R13: 888100e982f0 R14: 8881053f0340 R15: > 888105592178 > [5.738745] FS: () GS:88813bc0() > knlGS: > [5.738745] CS: 0010 DS: ES: CR0: 80050033 > [5.738745] CR2: CR3: 03462000 CR4: > 06f0 > [5.738745] Call Trace: > [5.738745] drm_get_last_vbltimestamp+0xa5/0xb0 > [5.738745] drm_reset_vblank_timestamp+0x56/0xc0 > [5.738745] drm_crtc_vblank_on+0x81/0x140 > [5.738745] intel_crtc_vblank_on+0x2b/0xe0 > [5.738745] intel_modeset_setup_hw_state+0xa9c/0x1ab0 > [5.738745] ? ww_mutex_lock+0x2b/0x90 > [5.738745] intel_modeset_init_nogem+0x3c5/0x1310 > [5.738745] ? intel_irq_postinstall+0x1aa/0x520 > [5.738745] i915_driver_probe+0x695/0xd30 > [5.738745] ? _raw_spin_unlock_irqrestore+0x33/0x50 > [5.738745] pci_device_probe+0xcd/0x140 > [5.738745] really_probe.part.0+0x99/0x270 > [5.738745] __driver_probe_device+0x8b/0x120 > [5.738745] driver_probe_device+0x19/0x90 > [5.738745] __driver_attach+0x79/0x120 > [5.738745] ? __device_attach_driver+0x90/0x90 > [5.738745] bus_for_each_dev+0x78/0xc0 > [5.738745] bus_add_driver+0x109/0x1b0 > [5.738745] driver_register+0x86/0xd0 > [5.738745] ? ttm_init+0x18/0x18 > [5.738745] i915_init+0x58/0x72 > [5.738745] do_one_initcall+0x56/0x2e0 > [5.738745] ? rcu_read_lock_sched_held+0x3a/0x70 > [5.738745] kernel_init_freeable+0x186/0x1ce > [5.738745] ? rest_init+0x250/0x250 > [5.738745] kernel_init+0x11/0x110 > [5.738745] ret_from_fork+0x22/0x30 > [5.738745] irq event stamp: 8200428 > [5.738745] hardirqs last enabled at (8200427): [] > _raw_spin_unlock_irqrestore+0 > [5.738745] hardirqs last disabled at (8200428): [] > _raw_spin_lock_irq+0x41/0x50 > [5.738745] softirqs last enabled at (8199086): [] > irq_exit_rcu+0x108/0x140 > [5.738745] softirqs last disabled at (8199079): [] > irq_exit_rcu+0x108/0x140 > [5.738745] ---[ end trace e99e0812b8ee9c5d ]--- > [5.786472] i915 :00:04.0: [drm] VGT ballooning configuration: > [5.787531] i915 :00:04.0: [drm] Mappable graphic memory: base > 0x31c7000 size 65536KiB > [5.788865] i915 :00:04.0: [drm] Unmappable graphic memory: base >
Re: [Intel-gfx] [PATCH 3/4] drm/i915/gt: rename legacy engine->hw_id to engine->gen6_hw_id
On Wed, Jul 21, 2021 at 3:51 PM Matt Roper wrote:
>
> On Tue, Jul 20, 2021 at 04:20:13PM -0700, Lucas De Marchi wrote:
> > We kept adding new engines and for that increasing hw_id unnecessarily:
> > it's not used since GRAPHICS_VER == 8. Prepend "gen6" to the field and
> > try to pack it in the structs to give a hint this field is actually not
> > used in recent platforms.
> >
> > Signed-off-by: Lucas De Marchi
>
> Reviewed-by: Matt Roper
>
> although if we apply patch #4 we could probably drop this intermediate
I was not so confident people would agree with that patch. Adding the macros to
the header as suggested helps it being more palatable though.
thanks
Lucas De Marchi
> step.
>
>
> Matt
>
> > ---
> > drivers/gpu/drm/i915/gt/intel_engine_cs.c| 12 ++--
> > drivers/gpu/drm/i915/gt/intel_engine_types.h | 2 +-
> > drivers/gpu/drm/i915/i915_reg.h | 2 +-
> > 3 files changed, 8 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > index a11f69f2e46e..508221de411c 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > @@ -42,7 +42,7 @@
> >
> > #define MAX_MMIO_BASES 3
> > struct engine_info {
> > - unsigned int hw_id;
> > + u8 gen6_hw_id;
> > u8 class;
> > u8 instance;
> > /* mmio bases table *must* be sorted in reverse graphics_ver order */
> > @@ -54,7 +54,7 @@ struct engine_info {
> >
> > static const struct engine_info intel_engines[] = {
> > [RCS0] = {
> > - .hw_id = RCS0_HW,
> > + .gen6_hw_id = RCS0_HW,
> > .class = RENDER_CLASS,
> > .instance = 0,
> > .mmio_bases = {
> > @@ -62,7 +62,7 @@ static const struct engine_info intel_engines[] = {
> > },
> > },
> > [BCS0] = {
> > - .hw_id = BCS0_HW,
> > + .gen6_hw_id = BCS0_HW,
> > .class = COPY_ENGINE_CLASS,
> > .instance = 0,
> > .mmio_bases = {
> > @@ -70,7 +70,7 @@ static const struct engine_info intel_engines[] = {
> > },
> > },
> > [VCS0] = {
> > - .hw_id = VCS0_HW,
> > + .gen6_hw_id = VCS0_HW,
> > .class = VIDEO_DECODE_CLASS,
> > .instance = 0,
> > .mmio_bases = {
> > @@ -102,7 +102,7 @@ static const struct engine_info intel_engines[] = {
> > },
> > },
> > [VECS0] = {
> > - .hw_id = VECS0_HW,
> > + .gen6_hw_id = VECS0_HW,
> > .class = VIDEO_ENHANCEMENT_CLASS,
> > .instance = 0,
> > .mmio_bases = {
> > @@ -290,7 +290,7 @@ static int intel_engine_setup(struct intel_gt *gt, enum
> > intel_engine_id id)
> > engine->i915 = i915;
> > engine->gt = gt;
> > engine->uncore = gt->uncore;
> > - engine->hw_id = info->hw_id;
> > + engine->gen6_hw_id = info->gen6_hw_id;
> > guc_class = engine_class_to_guc_class(info->class);
> > engine->guc_id = MAKE_GUC_ID(guc_class, info->instance);
> > engine->mmio_base = __engine_mmio_base(i915, info->mmio_bases);
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > index a107eb58ffa2..266422d8d1b1 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > @@ -264,11 +264,11 @@ struct intel_engine_cs {
> > enum intel_engine_id id;
> > enum intel_engine_id legacy_idx;
> >
> > - unsigned int hw_id;
> > unsigned int guc_id;
> >
> > intel_engine_mask_t mask;
> >
> > + u8 gen6_hw_id;
> > u8 class;
> > u8 instance;
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 943fe485c662..8750ffce9d61 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -2572,7 +2572,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> > #define ARB_MODE_BWGTLB_DISABLE (1 << 9)
> > #define ARB_MODE_SWIZZLE_BDW (1 << 1)
> > #define RENDER_HWS_PGA_GEN7 _MMIO(0x04080)
> > -#define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100 *
> > (engine)->hw_id)
> > +#define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100 *
> > (engine)->gen6_hw_id)
> > #define GEN8_RING_FAULT_REG _MMIO(0x4094)
> > #define GEN12_RING_FAULT_REG _MMIO(0xcec4)
> > #define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7)
> > --
> > 2.31.1
> >
>
> --
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
Intel-gfx mailing list
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/4] drm/i915/step: Add macro magic for handling steps
== Series Details ==
Series: series starting with [CI,1/4] drm/i915/step: Add macro magic for
handling steps
URL : https://patchwork.freedesktop.org/series/92849/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10367_full -> Patchwork_20671_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_20671_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_softpin@noreloc-s3:
- {shard-rkl}:[PASS][1] -> [DMESG-WARN][2] +6 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-rkl-5/igt@gem_soft...@noreloc-s3.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20671/shard-rkl-2/igt@gem_soft...@noreloc-s3.html
* igt@i915_pm_dc@dc6-dpms:
- {shard-rkl}:[FAIL][3] ([i915#2951]) -> [SKIP][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-rkl-2/igt@i915_pm...@dc6-dpms.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20671/shard-rkl-1/igt@i915_pm...@dc6-dpms.html
* igt@i915_pm_dc@dc6-psr:
- {shard-rkl}:[SKIP][5] ([i915#658]) -> [SKIP][6] +1 similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-rkl-5/igt@i915_pm...@dc6-psr.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20671/shard-rkl-5/igt@i915_pm...@dc6-psr.html
* igt@i915_pm_dc@dc9-dpms:
- {shard-rkl}:[SKIP][7] ([i915#3288]) -> [SKIP][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-rkl-5/igt@i915_pm...@dc9-dpms.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20671/shard-rkl-2/igt@i915_pm...@dc9-dpms.html
* igt@i915_pm_lpsp@kms-lpsp:
- {shard-rkl}:[SKIP][9] ([i915#3555]) -> [SKIP][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-rkl-5/igt@i915_pm_l...@kms-lpsp.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20671/shard-rkl-1/igt@i915_pm_l...@kms-lpsp.html
* igt@i915_pm_rpm@basic-rte:
- {shard-rkl}:NOTRUN -> [SKIP][11] +4 similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20671/shard-rkl-5/igt@i915_pm_...@basic-rte.html
* igt@i915_pm_rpm@cursor:
- {shard-rkl}:[SKIP][12] ([i915#1849]) -> [SKIP][13] +1 similar
issue
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-rkl-5/igt@i915_pm_...@cursor.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20671/shard-rkl-6/igt@i915_pm_...@cursor.html
* igt@i915_pm_rpm@gem-execbuf:
- {shard-rkl}:[SKIP][14] ([fdo#109308]) -> [SKIP][15] +3 similar
issues
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-rkl-2/igt@i915_pm_...@gem-execbuf.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20671/shard-rkl-1/igt@i915_pm_...@gem-execbuf.html
* igt@i915_pm_rpm@gem-execbuf-stress:
- {shard-rkl}:[PASS][16] -> [SKIP][17] +5 similar issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-rkl-2/igt@i915_pm_...@gem-execbuf-stress.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20671/shard-rkl-1/igt@i915_pm_...@gem-execbuf-stress.html
* igt@i915_pm_rpm@modeset-non-lpsp:
- {shard-rkl}:[SKIP][18] ([i915#1397]) -> [SKIP][19] +5 similar
issues
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-rkl-1/igt@i915_pm_...@modeset-non-lpsp.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20671/shard-rkl-2/igt@i915_pm_...@modeset-non-lpsp.html
* igt@i915_pm_rpm@modeset-pc8-residency-stress:
- {shard-rkl}:[SKIP][20] ([fdo#109506]) -> [SKIP][21]
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-rkl-5/igt@i915_pm_...@modeset-pc8-residency-stress.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20671/shard-rkl-5/igt@i915_pm_...@modeset-pc8-residency-stress.html
* igt@i915_pm_rpm@system-suspend:
- {shard-rkl}:[FAIL][22] ([fdo#103375]) -> [SKIP][23]
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-rkl-2/igt@i915_pm_...@system-suspend.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20671/shard-rkl-1/igt@i915_pm_...@system-suspend.html
* igt@i915_suspend@debugfs-reader:
- {shard-rkl}:NOTRUN -> [DMESG-WARN][24]
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20671/shard-rkl-5/igt@i915_susp...@debugfs-reader.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- {shard-rkl}:[SKIP][25] ([i915#1849]) -> [DMESG-WARN][26]
[25]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-rkl-5/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
[26]:
Re: [Intel-gfx] [PATCH 33/51] drm/i915/guc: Provide mmio list to be saved/restored on engine reset
On Fri, Jul 16, 2021 at 01:17:06PM -0700, Matthew Brost wrote:
> From: John Harrison
>
> The driver must provide GuC with a list of mmio registers
> that should be saved/restored during a GuC-based engine reset.
> Unfortunately, the list must be dynamically allocated as its size is
> variable. That means the driver must generate the list twice - once to
> work out the size and a second time to actually save it.
>
> v2:
> (Alan / CI)
> - GEN7_GT_MODE -> GEN6_GT_MODE to fix WA selftest failure
>
> Signed-off-by: John Harrison
> Signed-off-by: Fernando Pacheco
> Signed-off-by: Matthew Brost
Everything looks structurally correct. Feel confident on my below RB but
W/A are not my area of expertise. If any one else wanted to give it a
look, I wouldn't mind.
With that:
Reviewed-by: Matthew Brost
> Cc: Daniele Ceraolo Spurio
> Cc: Tvrtko Ursulin
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 46 ++--
> .../gpu/drm/i915/gt/intel_workarounds_types.h | 1 +
> drivers/gpu/drm/i915/gt/uc/intel_guc.h| 1 +
> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 199 +-
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 5 files changed, 222 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 72562c233ad2..34738ccab8bd 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -150,13 +150,14 @@ static void _wa_add(struct i915_wa_list *wal, const
> struct i915_wa *wa)
> }
>
> static void wa_add(struct i915_wa_list *wal, i915_reg_t reg,
> -u32 clear, u32 set, u32 read_mask)
> +u32 clear, u32 set, u32 read_mask, bool masked_reg)
> {
> struct i915_wa wa = {
> .reg = reg,
> .clr = clear,
> .set = set,
> .read = read_mask,
> + .masked_reg = masked_reg,
> };
>
> _wa_add(wal, );
> @@ -165,7 +166,7 @@ static void wa_add(struct i915_wa_list *wal, i915_reg_t
> reg,
> static void
> wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32
> set)
> {
> - wa_add(wal, reg, clear, set, clear);
> + wa_add(wal, reg, clear, set, clear, false);
> }
>
> static void
> @@ -200,20 +201,20 @@ wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg,
> u32 clr)
> static void
> wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
> {
> - wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val);
> + wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true);
> }
>
> static void
> wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
> {
> - wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val);
> + wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true);
> }
>
> static void
> wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg,
> u32 mask, u32 val)
> {
> - wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask);
> + wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true);
> }
>
> static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine,
> @@ -583,10 +584,10 @@ static void icl_ctx_workarounds_init(struct
> intel_engine_cs *engine,
>GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
>
> /* WaEnableFloatBlendOptimization:icl */
> - wa_write_clr_set(wal,
> - GEN10_CACHE_MODE_SS,
> - 0, /* write-only, so skip validation */
> - _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE));
> + wa_add(wal, GEN10_CACHE_MODE_SS, 0,
> +_MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE),
> +0 /* write-only, so skip validation */,
> +true);
>
> /* WaDisableGPGPUMidThreadPreemption:icl */
> wa_masked_field_set(wal, GEN8_CS_CHICKEN1,
> @@ -631,7 +632,7 @@ static void gen12_ctx_gt_tuning_init(struct
> intel_engine_cs *engine,
> FF_MODE2,
> FF_MODE2_TDS_TIMER_MASK,
> FF_MODE2_TDS_TIMER_128,
> -0);
> +0, false);
> }
>
> static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,
> @@ -669,7 +670,7 @@ static void gen12_ctx_workarounds_init(struct
> intel_engine_cs *engine,
> FF_MODE2,
> FF_MODE2_GS_TIMER_MASK,
> FF_MODE2_GS_TIMER_224,
> -0);
> +0, false);
>
> /*
>* Wa_14012131227:dg1
> @@ -847,7 +848,7 @@ hsw_gt_workarounds_init(struct drm_i915_private *i915,
> struct i915_wa_list *wal)
> wa_add(wal,
> HSW_ROW_CHICKEN3, 0,
> _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE),
> - 0 /* XXX does this reg exist? */);
> +0 /* XXX does this reg exist? */, true);
>
> /* WaVSRefCountFullforceMissDisable:hsw */
> wa_write_clr(wal,
Re: [Intel-gfx] 5.14-rc2 warnings with kvmgvt
On Wed, Jul 21, 2021 at 05:18:18PM -0400, Rodrigo Vivi wrote: > could you please try this small patch? I had to hand apply it as it wa corruped to due to cut off context. It fixes one of the warnings, new output below: [4.182820] i915 :00:04.0: [drm] Virtual GPU for Intel GVT-g detected. [4.184076] i915 :00:04.0: [drm] VT-d active for gfx access [4.185199] i915 :00:04.0: [drm] iGVT-g active, disabling use of stolen memory [4.207889] i915 :00:04.0: BAR 6: can't assign [??? 0x flags 0x2000] (bogus a) [4.210062] i915 :00:04.0: [drm] Failed to find VBIOS tables (VBT) [4.212256] i915 :00:04.0: vgaarb: changed VGA decodes: olddecodes=io+mem,decodes=none:owm [4.214447] i915 :00:04.0: Direct firmware load for i915/kbl_dmc_ver1_04.bin failed with 2 [4.215447] i915 :00:04.0: [drm] Failed to load DMC firmware i915/kbl_dmc_ver1_04.bin. Di. [4.216643] i915 :00:04.0: [drm] DMC firmware homepage: https://git.kernel.org/pub/scm/li5 [4.227760] i915 :00:04.0: [drm] failed to retrieve link info, disabling eDP [4.229706] [ cut here ] [4.230204] Missing case (port == 5) [4.230652] WARNING: CPU: 3 PID: 1 at drivers/gpu/drm/i915/display/intel_hdmi.c:2740 intel_hd0 [4.231815] Modules linked in: [4.232146] CPU: 3 PID: 1 Comm: swapper/0 Not tainted 5.14.0-rc2+ #40 [4.232826] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.14.0-2 04/01/2014 [4.233706] RIP: 0010:intel_hdmi_init_connector+0x7cf/0x880 [4.234330] Code: b6 fb 45 89 fb e9 bd fb ff ff 49 63 d7 48 c7 c6 da 67 18 83 44 89 44 24 10 4 [4.236289] RSP: :c9013be8 EFLAGS: 00010282 [4.236949] RAX: RBX: 888104cda000 RCX: [4.237703] RDX: 0001 RSI: 831a7617 RDI: [4.238499] RBP: 888104c01000 R08: 0001 R09: 0001 [4.239240] R10: R11: 3fff R12: 8881054c [4.240112] R13: 0005 R14: 8881054c R15: 0005 [4.240963] FS: () GS:88813bd8() knlGS: [4.241856] CS: 0010 DS: ES: CR0: 80050033 [4.242533] CR2: CR3: 03462000 CR4: 06e0 [4.243437] Call Trace: [4.243754] intel_ddi_init+0x88d/0xc30 [4.244216] intel_modeset_init_nogem+0xdab/0x1310 [4.244792] ? intel_irq_postinstall+0x1aa/0x520 [4.245372] i915_driver_probe+0x695/0xd30 [4.245908] ? _raw_spin_unlock_irqrestore+0x33/0x50 [4.246507] pci_device_probe+0xcd/0x140 [4.246933] really_probe.part.0+0x99/0x270 [4.247421] __driver_probe_device+0x8b/0x120 [4.247887] driver_probe_device+0x19/0x90 [4.248328] __driver_attach+0x79/0x120 [4.248740] ? __device_attach_driver+0x90/0x90 [4.249225] bus_for_each_dev+0x78/0xc0 [4.249637] bus_add_driver+0x109/0x1b0 [4.250051] driver_register+0x86/0xd0 [4.250512] ? ttm_init+0x18/0x18 [4.250884] i915_init+0x58/0x72 [4.251234] do_one_initcall+0x56/0x2e0 [4.251644] ? rcu_read_lock_sched_held+0x3a/0x70 [4.252150] kernel_init_freeable+0x186/0x1ce [4.252625] ? rest_init+0x250/0x250 [4.253032] kernel_init+0x11/0x110 [4.253464] ret_from_fork+0x22/0x30 [4.253864] irq event stamp: 8201065 [4.254308] hardirqs last enabled at (8201075): [] console_unlock+0x323/0x0 [4.255377] hardirqs last disabled at (8201082): [] console_unlock+0x3d0/0x0 [4.256325] softirqs last enabled at (8200736): [] irq_exit_rcu+0x108/0x140 [4.257234] softirqs last disabled at (8200695): [] irq_exit_rcu+0x108/0x140 [4.258142] ---[ end trace 2e5275f4e68f236b ]--- [4.259727] i915 :00:04.0: [drm] [ENCODER:94:DDI B/PHY B] is disabled/in DSI mode with ant [4.260917] i915 :00:04.0: [drm] [ENCODER:110:DDI C/PHY C] is disabled/in DSI mode with at [4.262086] i915 :00:04.0: [drm] [ENCODER:130:DDI F/PHY F] is disabled/in DSI mode with at [4.263764] i915 :00:04.0: [drm] VGT ballooning configuration: [4.264418] i915 :00:04.0: [drm] Mappable graphic memory: base 0x218 size 65536KiB [4.265284] i915 :00:04.0: [drm] Unmappable graphic memory: base 0x1000 size 393216KiB [4.266188] i915 :00:04.0: [drm] balloon space: range [ 0x2800 - 0x1 ] 353894. [4.267159] i915 :00:04.0: [drm] balloon space: range [ 0x0 - 0x218 ] 34304 KiB. [4.268025] i915 :00:04.0: [drm] balloon space: range [ 0x618 - 0x1000 ] 162304 K. [4.268968] i915 :00:04.0: [drm] VGT balloon successfully [4.888116] i915 :00:04.0: [drm] *ERROR* Failed to disable SAGV (-110) [4.908031] [drm] Initialized i915 1.6.0 20201103 for :00:04.0 on minor 0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org
[Intel-gfx] ✓ Fi.CI.IGT: success for Series to merge a subset of GuC submission (rev2)
== Series Details ==
Series: Series to merge a subset of GuC submission (rev2)
URL : https://patchwork.freedesktop.org/series/92791/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10367_full -> Patchwork_20670_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_20670_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_pm_rpm@cursor:
- {shard-rkl}:[SKIP][1] ([i915#1849]) -> [SKIP][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-rkl-5/igt@i915_pm_...@cursor.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20670/shard-rkl-6/igt@i915_pm_...@cursor.html
* igt@i915_pm_rpm@gem-execbuf:
- {shard-rkl}:[SKIP][3] ([fdo#109308]) -> [SKIP][4] +1 similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-rkl-2/igt@i915_pm_...@gem-execbuf.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20670/shard-rkl-6/igt@i915_pm_...@gem-execbuf.html
* igt@kms_async_flips@alternate-sync-async-flip:
- {shard-rkl}:[SKIP][5] ([i915#1845]) -> [FAIL][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-rkl-5/igt@kms_async_fl...@alternate-sync-async-flip.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20670/shard-rkl-6/igt@kms_async_fl...@alternate-sync-async-flip.html
* igt@kms_vblank@pipe-b-ts-continuation-modeset-rpm:
- {shard-rkl}:[SKIP][7] ([i915#1845]) -> [SKIP][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-rkl-2/igt@kms_vbl...@pipe-b-ts-continuation-modeset-rpm.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20670/shard-rkl-6/igt@kms_vbl...@pipe-b-ts-continuation-modeset-rpm.html
* igt@perf_pmu@rc6-runtime-pm-long:
- {shard-rkl}:[PASS][9] -> [SKIP][10] +2 similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-rkl-5/igt@perf_...@rc6-runtime-pm-long.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20670/shard-rkl-6/igt@perf_...@rc6-runtime-pm-long.html
Known issues
Here are the changes found in Patchwork_20670_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@feature_discovery@display-3x:
- shard-glk: NOTRUN -> [SKIP][11] ([fdo#109271]) +69 similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20670/shard-glk1/igt@feature_discov...@display-3x.html
* igt@feature_discovery@display-4x:
- shard-tglb: NOTRUN -> [SKIP][12] ([i915#1839])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20670/shard-tglb7/igt@feature_discov...@display-4x.html
* igt@gem_ctx_persistence@hostile:
- shard-tglb: [PASS][13] -> [FAIL][14] ([i915#2410])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-tglb5/igt@gem_ctx_persiste...@hostile.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20670/shard-tglb6/igt@gem_ctx_persiste...@hostile.html
* igt@gem_ctx_persistence@smoketest:
- shard-snb: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#1099]) +2
similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20670/shard-snb6/igt@gem_ctx_persiste...@smoketest.html
* igt@gem_exec_fair@basic-deadline:
- shard-apl: NOTRUN -> [FAIL][16] ([i915#2846])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20670/shard-apl6/igt@gem_exec_f...@basic-deadline.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-glk: [PASS][17] -> [FAIL][18] ([i915#2842]) +2 similar
issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-glk7/igt@gem_exec_fair@basic-none-s...@rcs0.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20670/shard-glk2/igt@gem_exec_fair@basic-none-s...@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-iclb: [PASS][19] -> [FAIL][20] ([i915#2842])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-iclb2/igt@gem_exec_fair@basic-pace-s...@rcs0.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20670/shard-iclb3/igt@gem_exec_fair@basic-pace-s...@rcs0.html
* igt@gem_exec_fair@basic-pace@bcs0:
- shard-tglb: [PASS][21] -> [FAIL][22] ([i915#2842]) +1 similar
issue
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-tglb1/igt@gem_exec_fair@basic-p...@bcs0.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20670/shard-tglb6/igt@gem_exec_fair@basic-p...@bcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl: [PASS][23] -> [FAIL][24] ([i915#2842]) +3 similar
issues
[23]:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Migrate memory to SMEM when imported cross-device (rev3)
== Series Details ==
Series: drm/i915: Migrate memory to SMEM when imported cross-device (rev3)
URL : https://patchwork.freedesktop.org/series/92617/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10367_full -> Patchwork_20668_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_20668_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_pm_rpm@gem-execbuf-stress:
- {shard-rkl}:[PASS][1] -> [SKIP][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-rkl-2/igt@i915_pm_...@gem-execbuf-stress.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20668/shard-rkl-6/igt@i915_pm_...@gem-execbuf-stress.html
* igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
- {shard-rkl}:[SKIP][3] ([i915#1397]) -> [SKIP][4] +1 similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-rkl-5/igt@i915_pm_...@modeset-lpsp-stress-no-wait.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20668/shard-rkl-6/igt@i915_pm_...@modeset-lpsp-stress-no-wait.html
* {igt@kms_dp_dsc@xrgb-dsc-compression}:
- {shard-rkl}:NOTRUN -> [SKIP][5]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20668/shard-rkl-2/igt@kms_dp_...@xrgb-dsc-compression.html
* igt@kms_vblank@pipe-c-ts-continuation-dpms-rpm:
- {shard-rkl}:[SKIP][6] ([i915#1845]) -> [SKIP][7] +1 similar issue
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-rkl-5/igt@kms_vbl...@pipe-c-ts-continuation-dpms-rpm.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20668/shard-rkl-6/igt@kms_vbl...@pipe-c-ts-continuation-dpms-rpm.html
Known issues
Here are the changes found in Patchwork_20668_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@drm_import_export@flink:
- shard-kbl: [PASS][8] -> [INCOMPLETE][9] ([i915#2369])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-kbl6/igt@drm_import_exp...@flink.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20668/shard-kbl3/igt@drm_import_exp...@flink.html
* igt@feature_discovery@display-3x:
- shard-glk: NOTRUN -> [SKIP][10] ([fdo#109271]) +69 similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20668/shard-glk1/igt@feature_discov...@display-3x.html
* igt@feature_discovery@display-4x:
- shard-tglb: NOTRUN -> [SKIP][11] ([i915#1839])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20668/shard-tglb1/igt@feature_discov...@display-4x.html
* igt@gem_ctx_persistence@engines-hostile:
- shard-snb: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#1099]) +1
similar issue
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20668/shard-snb2/igt@gem_ctx_persiste...@engines-hostile.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-apl: [PASS][13] -> [SKIP][14] ([fdo#109271])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-apl6/igt@gem_exec_fair@basic-none-sh...@rcs0.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20668/shard-apl2/igt@gem_exec_fair@basic-none-sh...@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-glk: [PASS][15] -> [FAIL][16] ([i915#2842]) +2 similar
issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-glk7/igt@gem_exec_fair@basic-none-s...@rcs0.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20668/shard-glk6/igt@gem_exec_fair@basic-none-s...@rcs0.html
* igt@gem_exec_fair@basic-none@rcs0:
- shard-kbl: [PASS][17] -> [FAIL][18] ([i915#2842]) +1 similar
issue
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-kbl7/igt@gem_exec_fair@basic-n...@rcs0.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20668/shard-kbl1/igt@gem_exec_fair@basic-n...@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-iclb: [PASS][19] -> [FAIL][20] ([i915#2842])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-iclb2/igt@gem_exec_fair@basic-pace-s...@rcs0.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20668/shard-iclb2/igt@gem_exec_fair@basic-pace-s...@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl: [PASS][21] -> [SKIP][22] ([fdo#109271]) +2 similar
issues
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-kbl7/igt@gem_exec_fair@basic-p...@rcs0.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20668/shard-kbl4/igt@gem_exec_fair@basic-p...@rcs0.html
- shard-tglb: [PASS][23] -> [FAIL][24]
Re: [Intel-gfx] [PATCH 06/14] drm/i915/guc/slpc: Enable SLPC and add related H2G events
Hi Vinay,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-tip/drm-tip]
[cannot apply to drm-intel/for-linux-next drm-exynos/exynos-drm-next
tegra-drm/drm/tegra/for-next drm/drm-next v5.14-rc2 next-20210721]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Vinay-Belgaumkar/drm-i915-guc-Enable-GuC-based-power-management-features/20210722-001528
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: x86_64-rhel-8.3-kselftests (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
#
https://github.com/0day-ci/linux/commit/14352081e4f18759e70413f3be4151d623c97b8c
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review
Vinay-Belgaumkar/drm-i915-guc-Enable-GuC-based-power-management-features/20210722-001528
git checkout 14352081e4f18759e70413f3be4151d623c97b8c
# save the attached .config to linux build tree
make W=1 ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c:217:5: warning: no previous
>> prototype for 'slpc_decode_min_freq' [-Wmissing-prototypes]
217 | u32 slpc_decode_min_freq(struct intel_guc_slpc *slpc)
| ^~~~
>> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c:229:5: warning: no previous
>> prototype for 'slpc_decode_max_freq' [-Wmissing-prototypes]
229 | u32 slpc_decode_max_freq(struct intel_guc_slpc *slpc)
| ^~~~
vim +/slpc_decode_min_freq +217 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
216
> 217 u32 slpc_decode_min_freq(struct intel_guc_slpc *slpc)
218 {
219 struct slpc_shared_data *data = slpc->vaddr;
220
221 GEM_BUG_ON(!slpc->vma);
222
223 return DIV_ROUND_CLOSEST(
224 REG_FIELD_GET(SLPC_MIN_UNSLICE_FREQ_MASK,
225 data->task_state_data.freq) *
226 GT_FREQUENCY_MULTIPLIER, GEN9_FREQ_SCALER);
227 }
228
> 229 u32 slpc_decode_max_freq(struct intel_guc_slpc *slpc)
230 {
231 struct slpc_shared_data *data = slpc->vaddr;
232
233 GEM_BUG_ON(!slpc->vma);
234
235 return DIV_ROUND_CLOSEST(
236 REG_FIELD_GET(SLPC_MAX_UNSLICE_FREQ_MASK,
237 data->task_state_data.freq) *
238 GT_FREQUENCY_MULTIPLIER, GEN9_FREQ_SCALER);
239 }
240
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
.config.gz
Description: application/gzip
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Ditch i915 globals shrink infrastructure
== Series Details ==
Series: drm/i915: Ditch i915 globals shrink infrastructure
URL : https://patchwork.freedesktop.org/series/92841/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10367_full -> Patchwork_20667_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_20667_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20667_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_20667_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_pm_rpm@basic-rte:
- {shard-rkl}:NOTRUN -> [FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20667/shard-rkl-6/igt@i915_pm_...@basic-rte.html
* igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
- {shard-rkl}:[SKIP][2] ([i915#1397]) -> [SKIP][3]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-rkl-5/igt@i915_pm_...@modeset-lpsp-stress-no-wait.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20667/shard-rkl-6/igt@i915_pm_...@modeset-lpsp-stress-no-wait.html
* igt@i915_pm_rpm@modeset-pc8-residency-stress:
- {shard-rkl}:[SKIP][4] ([fdo#109506]) -> [SKIP][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-rkl-5/igt@i915_pm_...@modeset-pc8-residency-stress.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20667/shard-rkl-6/igt@i915_pm_...@modeset-pc8-residency-stress.html
* igt@i915_pm_rpm@system-suspend-devices:
- {shard-rkl}:[PASS][6] -> [SKIP][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-rkl-5/igt@i915_pm_...@system-suspend-devices.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20667/shard-rkl-6/igt@i915_pm_...@system-suspend-devices.html
* igt@kms_ccs@pipe-a-bad-rotation-90-yf_tiled_ccs:
- {shard-rkl}:NOTRUN -> [SKIP][8]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20667/shard-rkl-6/igt@kms_ccs@pipe-a-bad-rotation-90-yf_tiled_ccs.html
* igt@kms_vblank@pipe-b-ts-continuation-dpms-rpm:
- {shard-rkl}:[SKIP][9] ([i915#1845]) -> [SKIP][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-rkl-5/igt@kms_vbl...@pipe-b-ts-continuation-dpms-rpm.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20667/shard-rkl-6/igt@kms_vbl...@pipe-b-ts-continuation-dpms-rpm.html
* igt@sysfs_heartbeat_interval@precise@bcs0:
- {shard-rkl}:[PASS][11] -> [FAIL][12] +1 similar issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-rkl-2/igt@sysfs_heartbeat_interval@prec...@bcs0.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20667/shard-rkl-1/igt@sysfs_heartbeat_interval@prec...@bcs0.html
### Piglit changes ###
Possible regressions
*
spec@amd_shader_trinary_minmax@execution@built-in-functions@gs-min3-ivec3-ivec3-ivec3
(NEW):
- pig-snb-2600: NOTRUN -> [FAIL][13] +1 similar issue
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20667/pig-snb-2600/spec@amd_shader_trinary_minmax@execution@built-in-functi...@gs-min3-ivec3-ivec3-ivec3.html
New tests
-
New tests have been introduced between CI_DRM_10367_full and
Patchwork_20667_full:
### New Piglit tests (1) ###
*
spec@amd_shader_trinary_minmax@execution@built-in-functions@gs-min3-ivec3-ivec3-ivec3:
- Statuses : 1 fail(s)
- Exec time: [0.19] s
Known issues
Here are the changes found in Patchwork_20667_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@feature_discovery@display-3x:
- shard-glk: NOTRUN -> [SKIP][14] ([fdo#109271]) +69 similar issues
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20667/shard-glk4/igt@feature_discov...@display-3x.html
* igt@feature_discovery@display-4x:
- shard-tglb: NOTRUN -> [SKIP][15] ([i915#1839])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20667/shard-tglb5/igt@feature_discov...@display-4x.html
* igt@gem_ctx_persistence@engines-hostile@vcs0:
- shard-tglb: [PASS][16] -> [FAIL][17] ([i915#2410])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-tglb5/igt@gem_ctx_persistence@engines-host...@vcs0.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20667/shard-tglb3/igt@gem_ctx_persistence@engines-host...@vcs0.html
* igt@gem_ctx_persistence@smoketest:
- shard-snb: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#1099])
[18]:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/guc: Enable GuC based power management features
== Series Details ==
Series: drm/i915/guc: Enable GuC based power management features
URL : https://patchwork.freedesktop.org/series/92831/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10367_full -> Patchwork_20666_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_20666_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_pm_rpm@cursor:
- {shard-rkl}:[SKIP][1] ([i915#1849]) -> [SKIP][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-rkl-5/igt@i915_pm_...@cursor.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20666/shard-rkl-6/igt@i915_pm_...@cursor.html
* igt@i915_pm_rpm@drm-resources-equal:
- {shard-rkl}:[SKIP][3] ([fdo#109308]) -> [SKIP][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-rkl-5/igt@i915_pm_...@drm-resources-equal.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20666/shard-rkl-6/igt@i915_pm_...@drm-resources-equal.html
* igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
- {shard-rkl}:[SKIP][5] ([i915#1397]) -> [SKIP][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-rkl-5/igt@i915_pm_...@modeset-lpsp-stress-no-wait.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20666/shard-rkl-6/igt@i915_pm_...@modeset-lpsp-stress-no-wait.html
* igt@kms_vblank@pipe-b-ts-continuation-dpms-rpm:
- {shard-rkl}:[SKIP][7] ([i915#1845]) -> [SKIP][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-rkl-5/igt@kms_vbl...@pipe-b-ts-continuation-dpms-rpm.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20666/shard-rkl-6/igt@kms_vbl...@pipe-b-ts-continuation-dpms-rpm.html
* igt@perf_pmu@rc6-runtime-pm-long:
- {shard-rkl}:[PASS][9] -> [SKIP][10] +1 similar issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-rkl-5/igt@perf_...@rc6-runtime-pm-long.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20666/shard-rkl-6/igt@perf_...@rc6-runtime-pm-long.html
New tests
-
New tests have been introduced between CI_DRM_10367_full and
Patchwork_20666_full:
### New IGT tests (1) ###
* igt@i915_selftest@live@slpc:
- Statuses : 8 pass(s)
- Exec time: [0.50, 4.91] s
Known issues
Here are the changes found in Patchwork_20666_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@feature_discovery@display-3x:
- shard-glk: NOTRUN -> [SKIP][11] ([fdo#109271]) +69 similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20666/shard-glk1/igt@feature_discov...@display-3x.html
* igt@feature_discovery@display-4x:
- shard-tglb: NOTRUN -> [SKIP][12] ([i915#1839])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20666/shard-tglb5/igt@feature_discov...@display-4x.html
* igt@gem_ctx_persistence@legacy-engines-queued:
- shard-snb: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#1099]) +3
similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20666/shard-snb5/igt@gem_ctx_persiste...@legacy-engines-queued.html
* igt@gem_ctx_persistence@many-contexts:
- shard-tglb: [PASS][14] -> [FAIL][15] ([i915#2410])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-tglb7/igt@gem_ctx_persiste...@many-contexts.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20666/shard-tglb5/igt@gem_ctx_persiste...@many-contexts.html
* igt@gem_exec_fair@basic-deadline:
- shard-apl: NOTRUN -> [FAIL][16] ([i915#2846])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20666/shard-apl6/igt@gem_exec_f...@basic-deadline.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-glk: [PASS][17] -> [FAIL][18] ([i915#2842]) +3 similar
issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-glk7/igt@gem_exec_fair@basic-none-s...@rcs0.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20666/shard-glk5/igt@gem_exec_fair@basic-none-s...@rcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-kbl: [PASS][19] -> [FAIL][20] ([i915#2842]) +2 similar
issues
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/shard-kbl7/igt@gem_exec_fair@basic-n...@vecs0.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20666/shard-kbl7/igt@gem_exec_fair@basic-n...@vecs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-iclb: [PASS][21] -> [FAIL][22] ([i915#2842])
[21]:
Re: [Intel-gfx] [PATCH 09/14] drm/i915/guc/slpc: Add debugfs for SLPC info
Hi Vinay,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-tip/drm-tip]
[cannot apply to drm-intel/for-linux-next drm-exynos/exynos-drm-next
tegra-drm/drm/tegra/for-next drm/drm-next v5.14-rc2 next-20210721]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Vinay-Belgaumkar/drm-i915-guc-Enable-GuC-based-power-management-features/20210722-001528
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: x86_64-randconfig-a016-20210720 (attached as .config)
compiler: clang version 13.0.0 (https://github.com/llvm/llvm-project
c781eb153bfbd1b52b03efe34f56bbeccbb8aba6)
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
# install x86_64 cross compiling tool for clang build
# apt-get install binutils-x86-64-linux-gnu
#
https://github.com/0day-ci/linux/commit/1c6f8cf3c2757db7a87fceef08834f4e0e14f2f9
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review
Vinay-Belgaumkar/drm-i915-guc-Enable-GuC-based-power-management-features/20210722-001528
git checkout 1c6f8cf3c2757db7a87fceef08834f4e0e14f2f9
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c:67:6: warning: no previous
>> prototype for function 'intel_eval_slpc_support' [-Wmissing-prototypes]
bool intel_eval_slpc_support(void *data)
^
drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c:67:1: note: declare 'static'
if the function is not intended to be used outside of this translation unit
bool intel_eval_slpc_support(void *data)
^
static
1 warning generated.
--
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c:238:5: warning: no previous
prototype for function 'slpc_decode_min_freq' [-Wmissing-prototypes]
u32 slpc_decode_min_freq(struct intel_guc_slpc *slpc)
^
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c:238:1: note: declare 'static' if
the function is not intended to be used outside of this translation unit
u32 slpc_decode_min_freq(struct intel_guc_slpc *slpc)
^
static
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c:250:5: warning: no previous
prototype for function 'slpc_decode_max_freq' [-Wmissing-prototypes]
u32 slpc_decode_max_freq(struct intel_guc_slpc *slpc)
^
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c:250:1: note: declare 'static' if
the function is not intended to be used outside of this translation unit
u32 slpc_decode_max_freq(struct intel_guc_slpc *slpc)
^
static
>> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c:445:17: warning: variable 'data'
>> is uninitialized when used here [-Wuninitialized]
slpc_tasks = >task_state_data;
^~~~
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c:436:31: note: initialize the
variable 'data' to silence this warning
struct slpc_shared_data *data;
^
= NULL
3 warnings generated.
vim +/intel_eval_slpc_support +67 drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c
66
> 67 bool intel_eval_slpc_support(void *data)
68 {
69 struct intel_guc *guc;
70
71 guc = (struct intel_guc *)data;
72 return intel_guc_slpc_is_used(guc);
73 }
74
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
.config.gz
Description: application/gzip
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 02/14] drm/i915/guc/slpc: Initial definitions for SLPC
On 7/21/2021 10:24 AM, Michal Wajdeczko wrote:
On 21.07.2021 18:11, Vinay Belgaumkar wrote:
Add macros to check for SLPC support. This feature is currently supported
for Gen12+ and enabled whenever GuC submission is enabled/selected.
Include templates for SLPC init/fini and enable.
v2: Move SLPC helper functions to intel_guc_slpc.c/.h. Define basic
template for SLPC structure in intel_guc_slpc_types.h. Fix copyright (Michal W)
Signed-off-by: Vinay Belgaumkar
Signed-off-by: Sundaresan Sujaritha
Signed-off-by: Daniele Ceraolo Spurio
drm/i915/guc/slpc: Lay out slpc init/enable/fini
Declare init/fini and enable function templates.
v2: Rebase
Signed-off-by: Vinay Belgaumkar
Signed-off-by: Sundaresan Sujaritha
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 2 +
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 4 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 63 +++
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h | 33 ++
.../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h | 15 +
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 6 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.h | 2 +
8 files changed, 124 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index ab7679957623..d8eac4468df9 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -186,6 +186,7 @@ i915-y += gt/uc/intel_uc.o \
gt/uc/intel_guc_fw.o \
gt/uc/intel_guc_log.o \
gt/uc/intel_guc_log_debugfs.o \
+ gt/uc/intel_guc_slpc.o \
gt/uc/intel_guc_submission.o \
gt/uc/intel_huc.o \
gt/uc/intel_huc_debugfs.o \
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 979128e28372..39bc3c16057b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -7,6 +7,7 @@
#include "gt/intel_gt_irq.h"
#include "gt/intel_gt_pm_irq.h"
#include "intel_guc.h"
+#include "intel_guc_slpc.h"
#include "intel_guc_ads.h"
#include "intel_guc_submission.h"
#include "i915_drv.h"
@@ -157,6 +158,7 @@ void intel_guc_init_early(struct intel_guc *guc)
intel_guc_ct_init_early(>ct);
intel_guc_log_init_early(>log);
intel_guc_submission_init_early(guc);
+ intel_guc_slpc_init_early(>slpc);
mutex_init(>send_mutex);
spin_lock_init(>irq_lock);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 9c62c68fb132..8cecfad9d7b1 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -15,6 +15,7 @@
#include "intel_guc_ct.h"
#include "intel_guc_log.h"
#include "intel_guc_reg.h"
+#include "intel_guc_slpc_types.h"
#include "intel_uc_fw.h"
#include "i915_utils.h"
#include "i915_vma.h"
@@ -30,6 +31,7 @@ struct intel_guc {
struct intel_uc_fw fw;
struct intel_guc_log log;
struct intel_guc_ct ct;
+ struct intel_guc_slpc slpc;
/* Global engine used to submit requests to GuC */
struct i915_sched_engine *sched_engine;
@@ -57,6 +59,8 @@ struct intel_guc {
bool submission_supported;
bool submission_selected;
+ bool slpc_supported;
+ bool slpc_selected;
struct i915_vma *ads_vma;
struct __guc_ads_blob *ads_blob;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
new file mode 100644
index ..d9feb430ce35
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include "i915_drv.h"
+#include "intel_guc_slpc.h"
+#include "gt/intel_gt.h"
+
+static inline struct intel_guc *slpc_to_guc(struct intel_guc_slpc *slpc)
+{
+ return container_of(slpc, struct intel_guc, slpc);
+}
+
+static bool __detect_slpc_supported(struct intel_guc *guc)
+{
+ /* GuC SLPC is unavailable for pre-Gen12 */
+ return guc->submission_supported &&
+ GRAPHICS_VER(guc_to_gt(guc)->i915) >= 12;
+}
+
+static bool __guc_slpc_selected(struct intel_guc *guc)
+{
+ if (!intel_guc_slpc_is_supported(guc))
+ return false;
+
+ return guc->submission_selected;
+}
+
+void intel_guc_slpc_init_early(struct intel_guc_slpc *slpc)
+{
+ struct intel_guc *guc = slpc_to_guc(slpc);
+
+ guc->slpc_supported = __detect_slpc_supported(guc);
+ guc->slpc_selected = __guc_slpc_selected(guc);
+}
+
+int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
+{
+ return 0;
+}
+
+/*
+ * intel_guc_slpc_enable() - Start SLPC
+ * @slpc: pointer to
[Intel-gfx] ✓ Fi.CI.BAT: success for CI pass for reviewed Xe_HP SDV and DG2 patches
== Series Details ==
Series: CI pass for reviewed Xe_HP SDV and DG2 patches
URL : https://patchwork.freedesktop.org/series/92853/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10367 -> Patchwork_20673
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20673/index.html
Known issues
Here are the changes found in Patchwork_20673 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@cs-gfx:
- fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20673/fi-kbl-soraka/igt@amdgpu/amd_ba...@cs-gfx.html
* igt@runner@aborted:
- fi-bdw-5557u: NOTRUN -> [FAIL][2] ([i915#1602] / [i915#2029])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20673/fi-bdw-5557u/igt@run...@aborted.html
Possible fixes
* igt@gem_exec_suspend@basic-s0:
- {fi-tgl-1115g4}:[FAIL][3] ([i915#1888]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20673/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s0.html
* igt@i915_selftest@live@execlists:
- fi-kbl-soraka: [INCOMPLETE][5] ([i915#2782] / [i915#794]) ->
[PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/fi-kbl-soraka/igt@i915_selftest@l...@execlists.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20673/fi-kbl-soraka/igt@i915_selftest@l...@execlists.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [FAIL][7] ([i915#1372]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20673/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372
[i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
[i915#794]: https://gitlab.freedesktop.org/drm/intel/issues/794
Participating hosts (38 -> 35)
--
Missing(3): fi-ilk-m540 fi-bdw-samus fi-hsw-4200u
Build changes
-
* Linux: CI_DRM_10367 -> Patchwork_20673
CI-20190529: 20190529
CI_DRM_10367: 598494d0149b67545593dfb1b5fa60278907749e @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6146: 6caef22e4aafed275771f564d4ea4cab09896ebc @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20673: 7704c9aa289a8f387a4ac8a18707cedb6f4ad6fa @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
7704c9aa289a drm/i915/dg2: DG2 has fixed memory bandwidth
358ea009b220 drm/i915/dg2: Don't read DRAM info
adb51870fc17 drm/i915/dg2: Don't program BW_BUDDY registers
4d664ff3d52d drm/i915/dg2: Add dbuf programming
f8744c6d424a drm/i915/dg2: Setup display outputs
ca6cdb06bc87 drm/i915/dg2: Don't wait for AUX power well enable ACKs
85a603e64280 drm/i915/dg2: Skip shared DPLL handling
ee4554dd0f46 drm/i915/dg2: Add cdclk table and reference clock
bf4e9f961c54 drm/i915/dg2: Add fake PCH
0f78529c87f9 drm/i915/xehp: New engine context offsets
66471aa168d2 drm/i915/xehp: Handle new device context ID format
748de8c99157 drm/i915/selftests: Allow for larger engine counts
54b16faca000 drm/i915/gen12: Use fuse info to enable SFC
2024f48f8303 drm/i915/xehp: VDBOX/VEBOX fusing registers are enable-based
2e778d91bf0c drm/i915: Fork DG1 interrupt handler
af8335fc25c0 drm/i915/dg2: add DG2 platform info
35b61c43f3e6 drm/i915/xehpsdv: add initial XeHP SDV definitions
3c0d66813984 drm/i915: Add XE_HP initial definitions
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20673/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for CI pass for reviewed Xe_HP SDV and DG2 patches
== Series Details == Series: CI pass for reviewed Xe_HP SDV and DG2 patches URL : https://patchwork.freedesktop.org/series/92853/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_display.c:1896:21:expected struct i915_vma *[assigned] vma +drivers/gpu/drm/i915/display/intel_display.c:1896:21:got void [noderef] __iomem *[assigned] iomem +drivers/gpu/drm/i915/display/intel_display.c:1896:21: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gem/i915_gem_context.c:1412:34:expected struct i915_address_space *vm +drivers/gpu/drm/i915/gem/i915_gem_context.c:1412:34:got struct i915_address_space [noderef] __rcu *vm +drivers/gpu/drm/i915/gem/i915_gem_context.c:1412:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25:expected struct i915_address_space [noderef] __rcu *vm +drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25:got struct i915_address_space * +drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34:expected struct i915_address_space *vm +drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34:got struct i915_address_space [noderef] __rcu *vm +drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1396:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/intel_ring_submission.c:1210:24: warning: Using plain integer as NULL pointer +drivers/gpu/drm/i915/i915_perf.c:1443:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1497:15: warning: memset with byte count of 16777216 +./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080) +./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080) +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for CI pass for reviewed Xe_HP SDV and DG2 patches
== Series Details == Series: CI pass for reviewed Xe_HP SDV and DG2 patches URL : https://patchwork.freedesktop.org/series/92853/ State : warning == Summary == $ dim checkpatch origin/drm-tip 3c0d66813984 drm/i915: Add XE_HP initial definitions 35b61c43f3e6 drm/i915/xehpsdv: add initial XeHP SDV definitions af8335fc25c0 drm/i915/dg2: add DG2 platform info -:53: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i915' - possible side-effects? #53: FILE: drivers/gpu/drm/i915/i915_drv.h:1580: +#define IS_DG2_GT_STEP(__i915, variant, since, until) \ + (IS_SUBPLATFORM(__i915, INTEL_DG2, INTEL_SUBPLATFORM_##variant) && \ +IS_GT_STEP(__i915, since, until)) -:57: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i915' - possible side-effects? #57: FILE: drivers/gpu/drm/i915/i915_drv.h:1584: +#define IS_DG2_DISP_STEP(__i915, since, until) \ + (IS_DG2(__i915) && \ +IS_DISPLAY_STEP(__i915, since, until)) total: 0 errors, 0 warnings, 2 checks, 117 lines checked 2e778d91bf0c drm/i915: Fork DG1 interrupt handler 2024f48f8303 drm/i915/xehp: VDBOX/VEBOX fusing registers are enable-based 54b16faca000 drm/i915/gen12: Use fuse info to enable SFC 748de8c99157 drm/i915/selftests: Allow for larger engine counts 66471aa168d2 drm/i915/xehp: Handle new device context ID format 0f78529c87f9 drm/i915/xehp: New engine context offsets bf4e9f961c54 drm/i915/dg2: Add fake PCH ee4554dd0f46 drm/i915/dg2: Add cdclk table and reference clock 85a603e64280 drm/i915/dg2: Skip shared DPLL handling ca6cdb06bc87 drm/i915/dg2: Don't wait for AUX power well enable ACKs f8744c6d424a drm/i915/dg2: Setup display outputs 4d664ff3d52d drm/i915/dg2: Add dbuf programming adb51870fc17 drm/i915/dg2: Don't program BW_BUDDY registers 358ea009b220 drm/i915/dg2: Don't read DRAM info 7704c9aa289a drm/i915/dg2: DG2 has fixed memory bandwidth ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 06/18] drm/i915/guc: Implement GuC context operations for new inteface
On 7/20/2021 6:51 PM, John Harrison wrote:
On 7/20/2021 15:39, Matthew Brost wrote:
Implement GuC context operations which includes GuC specific operations
alloc, pin, unpin, and destroy.
v2:
(Daniel Vetter)
- Use msleep_interruptible rather than cond_resched in busy loop
(Michal)
- Remove C++ style comment
v3:
(Matthew Brost)
- Drop GUC_ID_START
(John Harrison)
- Fix a bunch of typos
- Use drm_err rather than drm_dbg for G2H errors
(Daniele)
- Fix ;; typo
- Clean up sched state functions
- Add lockdep for guc_id functions
- Don't call __release_guc_id when guc_id is invalid
- Use MISSING_CASE
- Add comment in guc_context_pin
- Use shorter path to rpm
(Daniele / CI)
- Don't call release_guc_id on an invalid guc_id in destroy
Signed-off-by: John Harrison
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_context.c | 5 +
drivers/gpu/drm/i915/gt/intel_context_types.h | 22 +-
drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 1 -
drivers/gpu/drm/i915/gt/uc/intel_guc.h | 40 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 4 +
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 667 --
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/i915_request.c | 1 +
8 files changed, 686 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index bd63813c8a80..32fd6647154b 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -384,6 +384,11 @@ intel_context_init(struct intel_context *ce,
struct intel_engine_cs *engine)
mutex_init(>pin_mutex);
+ spin_lock_init(>guc_state.lock);
+
+ ce->guc_id = GUC_INVALID_LRC_ID;
+ INIT_LIST_HEAD(>guc_id_link);
+
i915_active_init(>active,
__intel_context_active, __intel_context_retire, 0);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 6d99631d19b9..606c480aec26 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -96,6 +96,7 @@ struct intel_context {
#define CONTEXT_BANNED 6
#define CONTEXT_FORCE_SINGLE_SUBMISSION 7
#define CONTEXT_NOPREEMPT 8
+#define CONTEXT_LRCA_DIRTY 9
struct {
u64 timeout_us;
@@ -138,14 +139,29 @@ struct intel_context {
u8 wa_bb_page; /* if set, page num reserved for context
workarounds */
+ struct {
+ /** lock: protects everything in guc_state */
+ spinlock_t lock;
+ /**
+ * sched_state: scheduling state of this context using GuC
+ * submission
+ */
+ u8 sched_state;
+ } guc_state;
+
/* GuC scheduling state flags that do not require a lock. */
atomic_t guc_sched_state_no_lock;
+ /* GuC LRC descriptor ID */
+ u16 guc_id;
+
+ /* GuC LRC descriptor reference count */
+ atomic_t guc_id_ref;
+
/*
- * GuC LRC descriptor ID - Not assigned in this patch but future
patches
- * in the series will.
+ * GuC ID link - in list when unpinned but guc_id still valid in
GuC
*/
- u16 guc_id;
+ struct list_head guc_id_link;
};
#endif /* __INTEL_CONTEXT_TYPES__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
index 41e5350a7a05..49d4857ad9b7 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
+++ b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
@@ -87,7 +87,6 @@
#define GEN11_CSB_WRITE_PTR_MASK (GEN11_CSB_PTR_MASK << 0)
#define MAX_CONTEXT_HW_ID (1 << 21) /* exclusive */
-#define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */
#define GEN11_MAX_CONTEXT_HW_ID (1 << 11) /* exclusive */
/* in Gen12 ID 0x7FF is reserved to indicate idle */
#define GEN12_MAX_CONTEXT_HW_ID (GEN11_MAX_CONTEXT_HW_ID - 1)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 8c7b92f699f1..30773cd699f5 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -7,6 +7,7 @@
#define _INTEL_GUC_H_
#include
+#include
#include "intel_uncore.h"
#include "intel_guc_fw.h"
@@ -44,6 +45,14 @@ struct intel_guc {
void (*disable)(struct intel_guc *guc);
} interrupts;
+ /*
+ * contexts_lock protects the pool of free guc ids and a linked
list of
+ * guc ids available to be stolen
+ */
+ spinlock_t contexts_lock;
+ struct ida guc_ids;
+ struct list_head guc_id_list;
+
bool submission_selected;
struct i915_vma *ads_vma;
@@ -101,6 +110,34 @@ intel_guc_send_and_receive(struct intel_guc
*guc, const u32 *action, u32 len,
response_buf, response_buf_size, 0);
}
+static inline int intel_guc_send_busy_loop(struct intel_guc* guc,
+
Re: [Intel-gfx] [PATCH 06/51] drm/i915/guc: Implement GuC context operations for new inteface
On 7/19/2021 9:04 PM, Matthew Brost wrote:
On Mon, Jul 19, 2021 at 05:51:46PM -0700, Daniele Ceraolo Spurio wrote:
On 7/16/2021 1:16 PM, Matthew Brost wrote:
Implement GuC context operations which includes GuC specific operations
alloc, pin, unpin, and destroy.
v2:
(Daniel Vetter)
- Use msleep_interruptible rather than cond_resched in busy loop
(Michal)
- Remove C++ style comment
Signed-off-by: John Harrison
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_context.c | 5 +
drivers/gpu/drm/i915/gt/intel_context_types.h | 22 +-
drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 1 -
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 40 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 4 +
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 666 --
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/i915_request.c | 1 +
8 files changed, 685 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index bd63813c8a80..32fd6647154b 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -384,6 +384,11 @@ intel_context_init(struct intel_context *ce, struct
intel_engine_cs *engine)
mutex_init(>pin_mutex);
+ spin_lock_init(>guc_state.lock);
+
+ ce->guc_id = GUC_INVALID_LRC_ID;
+ INIT_LIST_HEAD(>guc_id_link);
+
i915_active_init(>active,
__intel_context_active, __intel_context_retire, 0);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 6d99631d19b9..606c480aec26 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -96,6 +96,7 @@ struct intel_context {
#define CONTEXT_BANNED 6
#define CONTEXT_FORCE_SINGLE_SUBMISSION 7
#define CONTEXT_NOPREEMPT8
+#define CONTEXT_LRCA_DIRTY 9
struct {
u64 timeout_us;
@@ -138,14 +139,29 @@ struct intel_context {
u8 wa_bb_page; /* if set, page num reserved for context workarounds */
+ struct {
+ /** lock: protects everything in guc_state */
+ spinlock_t lock;
+ /**
+* sched_state: scheduling state of this context using GuC
+* submission
+*/
+ u8 sched_state;
+ } guc_state;
+
/* GuC scheduling state flags that do not require a lock. */
atomic_t guc_sched_state_no_lock;
+ /* GuC LRC descriptor ID */
+ u16 guc_id;
+
+ /* GuC LRC descriptor reference count */
+ atomic_t guc_id_ref;
+
/*
-* GuC LRC descriptor ID - Not assigned in this patch but future patches
-* in the series will.
+* GuC ID link - in list when unpinned but guc_id still valid in GuC
*/
- u16 guc_id;
+ struct list_head guc_id_link;
};
#endif /* __INTEL_CONTEXT_TYPES__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
index 41e5350a7a05..49d4857ad9b7 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
+++ b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
@@ -87,7 +87,6 @@
#define GEN11_CSB_WRITE_PTR_MASK (GEN11_CSB_PTR_MASK << 0)
#define MAX_CONTEXT_HW_ID(1 << 21) /* exclusive */
-#define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */
#define GEN11_MAX_CONTEXT_HW_ID (1 << 11) /* exclusive */
/* in Gen12 ID 0x7FF is reserved to indicate idle */
#define GEN12_MAX_CONTEXT_HW_ID (GEN11_MAX_CONTEXT_HW_ID - 1)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 8c7b92f699f1..30773cd699f5 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -7,6 +7,7 @@
#define _INTEL_GUC_H_
#include
+#include
#include "intel_uncore.h"
#include "intel_guc_fw.h"
@@ -44,6 +45,14 @@ struct intel_guc {
void (*disable)(struct intel_guc *guc);
} interrupts;
+ /*
+* contexts_lock protects the pool of free guc ids and a linked list of
+* guc ids available to be stolen
+*/
+ spinlock_t contexts_lock;
+ struct ida guc_ids;
+ struct list_head guc_id_list;
+
bool submission_selected;
struct i915_vma *ads_vma;
@@ -101,6 +110,34 @@ intel_guc_send_and_receive(struct intel_guc *guc, const
u32 *action, u32 len,
response_buf, response_buf_size, 0);
}
+static inline int intel_guc_send_busy_loop(struct intel_guc* guc,
+ const u32 *action,
+ u32 len,
+ bool loop)
+{
+ int err;
+ unsigned int sleep_period_ms = 1;
+
Re: [Intel-gfx] [PATCH 06/14] drm/i915/guc/slpc: Enable SLPC and add related H2G events
Hi Vinay,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-tip/drm-tip]
[cannot apply to drm-intel/for-linux-next drm-exynos/exynos-drm-next
tegra-drm/drm/tegra/for-next drm/drm-next v5.14-rc2 next-20210721]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Vinay-Belgaumkar/drm-i915-guc-Enable-GuC-based-power-management-features/20210722-001528
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: x86_64-randconfig-a016-20210720 (attached as .config)
compiler: clang version 13.0.0 (https://github.com/llvm/llvm-project
c781eb153bfbd1b52b03efe34f56bbeccbb8aba6)
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
# install x86_64 cross compiling tool for clang build
# apt-get install binutils-x86-64-linux-gnu
#
https://github.com/0day-ci/linux/commit/14352081e4f18759e70413f3be4151d623c97b8c
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review
Vinay-Belgaumkar/drm-i915-guc-Enable-GuC-based-power-management-features/20210722-001528
git checkout 14352081e4f18759e70413f3be4151d623c97b8c
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c:217:5: warning: no previous
>> prototype for function 'slpc_decode_min_freq' [-Wmissing-prototypes]
u32 slpc_decode_min_freq(struct intel_guc_slpc *slpc)
^
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c:217:1: note: declare 'static' if
the function is not intended to be used outside of this translation unit
u32 slpc_decode_min_freq(struct intel_guc_slpc *slpc)
^
static
>> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c:229:5: warning: no previous
>> prototype for function 'slpc_decode_max_freq' [-Wmissing-prototypes]
u32 slpc_decode_max_freq(struct intel_guc_slpc *slpc)
^
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c:229:1: note: declare 'static' if
the function is not intended to be used outside of this translation unit
u32 slpc_decode_max_freq(struct intel_guc_slpc *slpc)
^
static
2 warnings generated.
vim +/slpc_decode_min_freq +217 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
216
> 217 u32 slpc_decode_min_freq(struct intel_guc_slpc *slpc)
218 {
219 struct slpc_shared_data *data = slpc->vaddr;
220
221 GEM_BUG_ON(!slpc->vma);
222
223 return DIV_ROUND_CLOSEST(
224 REG_FIELD_GET(SLPC_MIN_UNSLICE_FREQ_MASK,
225 data->task_state_data.freq) *
226 GT_FREQUENCY_MULTIPLIER, GEN9_FREQ_SCALER);
227 }
228
> 229 u32 slpc_decode_max_freq(struct intel_guc_slpc *slpc)
230 {
231 struct slpc_shared_data *data = slpc->vaddr;
232
233 GEM_BUG_ON(!slpc->vma);
234
235 return DIV_ROUND_CLOSEST(
236 REG_FIELD_GET(SLPC_MAX_UNSLICE_FREQ_MASK,
237 data->task_state_data.freq) *
238 GT_FREQUENCY_MULTIPLIER, GEN9_FREQ_SCALER);
239 }
240
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
.config.gz
Description: application/gzip
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/bios: Fix ports mask
== Series Details ==
Series: drm/i915/bios: Fix ports mask
URL : https://patchwork.freedesktop.org/series/92850/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10367 -> Patchwork_20672
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20672/index.html
Known issues
Here are the changes found in Patchwork_20672 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@cs-gfx:
- fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20672/fi-kbl-soraka/igt@amdgpu/amd_ba...@cs-gfx.html
Possible fixes
* igt@gem_exec_suspend@basic-s0:
- {fi-tgl-1115g4}:[FAIL][2] ([i915#1888]) -> [PASS][3]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s0.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20672/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s0.html
* igt@i915_selftest@live@execlists:
- fi-kbl-soraka: [INCOMPLETE][4] ([i915#2782] / [i915#794]) ->
[PASS][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/fi-kbl-soraka/igt@i915_selftest@l...@execlists.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20672/fi-kbl-soraka/igt@i915_selftest@l...@execlists.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7500u: [DMESG-FAIL][6] ([i915#165]) -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20672/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
[i915#794]: https://gitlab.freedesktop.org/drm/intel/issues/794
Participating hosts (38 -> 35)
--
Missing(3): fi-ilk-m540 fi-bdw-samus fi-hsw-4200u
Build changes
-
* Linux: CI_DRM_10367 -> Patchwork_20672
CI-20190529: 20190529
CI_DRM_10367: 598494d0149b67545593dfb1b5fa60278907749e @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6146: 6caef22e4aafed275771f564d4ea4cab09896ebc @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20672: 69ca4ceb0ec678298a2639731d208dcf520e50d9 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
69ca4ceb0ec6 drm/i915/bios: Fix ports mask
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20672/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/4] drm/i915/gt: nuke unused legacy engine hw_id
On Wed, Jul 21, 2021 at 03:47:22PM -0700, Matt Roper wrote: On Tue, Jul 20, 2021 at 04:20:12PM -0700, Lucas De Marchi wrote: The engine hw_id is only used by RING_FAULT_REG(), which is not used since GRAPHICS_VER == 8. We tend to keep adding new defines just to be consistent, but let's try to remove them and let them defined to 0 when not used. s/when not used/for engines that only exist on gen8+ platforms/ Reviewed-by: Matt Roper For historical reference, we did use hw_id on gen8+ platforms too until relatively recently --- it was used to set the engine's guc_id as well up until: commit c784e5249e773689e38d2bc1749f08b986621a26 Author: John Harrison Date: Wed Oct 28 07:58:24 2020 -0700 drm/i915/guc: Update to use firmware v49.0.1 thanks for digging this, I will add that to the commit message as well. Lucas De Marchi ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/bios: Fix ports mask
== Series Details == Series: drm/i915/bios: Fix ports mask URL : https://patchwork.freedesktop.org/series/92850/ State : warning == Summary == $ dim checkpatch origin/drm-tip 69ca4ceb0ec6 drm/i915/bios: Fix ports mask -:35: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations #35: FILE: drivers/gpu/drm/i915/display/intel_bios.c:2169: + int ports = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | \ total: 0 errors, 1 warnings, 0 checks, 9 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/4] drm/i915/gt: nuke gen6_hw_id
On Tue, Jul 20, 2021 at 04:20:14PM -0700, Lucas De Marchi wrote:
> This is only used by GRAPHICS_VER == 6 and GRAPHICS_VER == 7. All other
> recent platforms do not depend on this field, so it doesn't make much
> sense to keep it generic like that. Instead, just do a mapping from
> engine class to HW ID in the single place that is needed.
>
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c| 6 --
> drivers/gpu/drm/i915/gt/intel_engine_types.h | 8
> drivers/gpu/drm/i915/i915_reg.h | 4 +++-
> 3 files changed, 3 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 508221de411c..0a04e8d90e9e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -42,7 +42,6 @@
>
> #define MAX_MMIO_BASES 3
> struct engine_info {
> - u8 gen6_hw_id;
> u8 class;
> u8 instance;
> /* mmio bases table *must* be sorted in reverse graphics_ver order */
> @@ -54,7 +53,6 @@ struct engine_info {
>
> static const struct engine_info intel_engines[] = {
> [RCS0] = {
> - .gen6_hw_id = RCS0_HW,
> .class = RENDER_CLASS,
> .instance = 0,
> .mmio_bases = {
> @@ -62,7 +60,6 @@ static const struct engine_info intel_engines[] = {
> },
> },
> [BCS0] = {
> - .gen6_hw_id = BCS0_HW,
> .class = COPY_ENGINE_CLASS,
> .instance = 0,
> .mmio_bases = {
> @@ -70,7 +67,6 @@ static const struct engine_info intel_engines[] = {
> },
> },
> [VCS0] = {
> - .gen6_hw_id = VCS0_HW,
> .class = VIDEO_DECODE_CLASS,
> .instance = 0,
> .mmio_bases = {
> @@ -102,7 +98,6 @@ static const struct engine_info intel_engines[] = {
> },
> },
> [VECS0] = {
> - .gen6_hw_id = VECS0_HW,
> .class = VIDEO_ENHANCEMENT_CLASS,
> .instance = 0,
> .mmio_bases = {
> @@ -290,7 +285,6 @@ static int intel_engine_setup(struct intel_gt *gt, enum
> intel_engine_id id)
> engine->i915 = i915;
> engine->gt = gt;
> engine->uncore = gt->uncore;
> - engine->gen6_hw_id = info->gen6_hw_id;
> guc_class = engine_class_to_guc_class(info->class);
> engine->guc_id = MAKE_GUC_ID(guc_class, info->instance);
> engine->mmio_base = __engine_mmio_base(i915, info->mmio_bases);
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index 266422d8d1b1..64330bfb7641 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -28,13 +28,6 @@
> #include "intel_wakeref.h"
> #include "intel_workarounds_types.h"
>
> -/* Legacy HW Engine ID */
> -
> -#define RCS0_HW 0
> -#define VCS0_HW 1
> -#define BCS0_HW 2
> -#define VECS0_HW 3
> -
> /* Gen11+ HW Engine class + instance */
> #define RENDER_CLASS 0
> #define VIDEO_DECODE_CLASS 1
> @@ -268,7 +261,6 @@ struct intel_engine_cs {
>
> intel_engine_mask_t mask;
>
> - u8 gen6_hw_id;
> u8 class;
> u8 instance;
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8750ffce9d61..d91386f4828e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2572,7 +2572,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define ARB_MODE_BWGTLB_DISABLE (1 << 9)
> #define ARB_MODE_SWIZZLE_BDW (1 << 1)
> #define RENDER_HWS_PGA_GEN7 _MMIO(0x04080)
> -#define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100 *
> (engine)->gen6_hw_id)
> +
> +#define _GEN6_ENGINE_CLASS_TO_ID(class) _PICK((class), 0, 1, 3, 2)
> +#define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100 *
> _GEN6_ENGINE_CLASS_TO_ID((engine)->class))
If you want to make this more clear to someone reading it down the road,
you could always do something explicit like:
#define _RING_FAULT_REG_RCS0x4094
#define _RING_FAULT_REG_VCS0x4194
#define _RING_FAULT_REG_BCS0x4294
#define _RING_FAULT_REG_VECS 0x4394
#define RING_FAULT_REG(engine) _MMIO(_PICK((engine)->class, \
_RING_FAULT_REG_RCS, \
_RING_FAULT_REG_VCS, \
_RING_FAULT_REG_VECS, \
_RING_FAULT_REG_BCS))
But in general,
Reviewed-by: Matt Roper
> #define GEN8_RING_FAULT_REG _MMIO(0x4094)
> #define GEN12_RING_FAULT_REG _MMIO(0xcec4)
> #define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7)
> --
> 2.31.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC
[Intel-gfx] [PATCH i-g-t 7/7] i915/gem_ctx_shared: Make gem_ctx_shared understand static priority mapping
The i915 currently has 2k visible priority levels which are currently unqiue. This is changing to statically map these 2k levels into 3 buckets: low: < 0 mid: 0 high: > 0 Update gem_scheduler to understand this. This entails updating promotion test to use 3 levels that will map into different buckets and also delete a racey check. Signed-off-by: Matthew Brost --- tests/i915/gem_ctx_shared.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/tests/i915/gem_ctx_shared.c b/tests/i915/gem_ctx_shared.c index 4441e6eb7..0d95df8a5 100644 --- a/tests/i915/gem_ctx_shared.c +++ b/tests/i915/gem_ctx_shared.c @@ -771,10 +771,10 @@ static void promotion(int i915, const intel_ctx_cfg_t *cfg, unsigned ring) gem_context_set_priority(i915, ctx[LO]->id, MIN_PRIO); ctx[HI] = intel_ctx_create(i915, _cfg); - gem_context_set_priority(i915, ctx[HI]->id, 0); + gem_context_set_priority(i915, ctx[HI]->id, MAX_PRIO); ctx[NOISE] = intel_ctx_create(i915, _cfg); - gem_context_set_priority(i915, ctx[NOISE]->id, MIN_PRIO/2); + gem_context_set_priority(i915, ctx[NOISE]->id, 0); result = gem_create(i915, 4096); dep = gem_create(i915, 4096); @@ -811,7 +811,6 @@ static void promotion(int i915, const intel_ctx_cfg_t *cfg, unsigned ring) I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT); gem_close(i915, result); - igt_assert_eq_u32(ptr[0], ctx[NOISE]->id); munmap(ptr, 4096); intel_ctx_destroy(i915, ctx[NOISE]); -- 2.28.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 6/7] i915/gem_scheduler: Make gem_scheduler understand static priority mapping
The i915 currently has 2k visible priority levels which are currently
unqiue. This is changing to statically map these 2k levels into 3
buckets:
low: < 0
mid: 0
high: > 0
Update gem_scheduler to understand this. This entails updating promotion
test to use 3 levels that will map into different buckets and also
delete a racey check. Also skip any tests that rely on having more than
3 priority levels.
Signed-off-by: Matthew Brost
---
lib/i915/gem_scheduler.c | 13 ++
lib/i915/gem_scheduler.h | 1 +
tests/i915/gem_exec_schedule.c | 47 --
3 files changed, 42 insertions(+), 19 deletions(-)
diff --git a/lib/i915/gem_scheduler.c b/lib/i915/gem_scheduler.c
index cdddf42ad..bec2e485a 100644
--- a/lib/i915/gem_scheduler.c
+++ b/lib/i915/gem_scheduler.c
@@ -90,6 +90,19 @@ bool gem_scheduler_has_ctx_priority(int fd)
I915_SCHEDULER_CAP_PRIORITY;
}
+/**
+ * gem_scheduler_has_ctx_priority:
+ * @fd: open i915 drm file descriptor
+ *
+ * Feature test macro to query whether the driver supports priority assigned
+ * from user space are statically mapping into 3 buckets.
+ */
+bool gem_scheduler_has_static_priority(int fd)
+{
+ return gem_scheduler_capability(fd) &
+ I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP;
+}
+
/**
* gem_scheduler_has_preemption:
* @fd: open i915 drm file descriptor
diff --git a/lib/i915/gem_scheduler.h b/lib/i915/gem_scheduler.h
index d43e84bd2..b00804f70 100644
--- a/lib/i915/gem_scheduler.h
+++ b/lib/i915/gem_scheduler.h
@@ -29,6 +29,7 @@
unsigned gem_scheduler_capability(int fd);
bool gem_scheduler_enabled(int fd);
bool gem_scheduler_has_ctx_priority(int fd);
+bool gem_scheduler_has_static_priority(int fd);
bool gem_scheduler_has_preemption(int fd);
bool gem_scheduler_has_semaphores(int fd);
bool gem_scheduler_has_engine_busy_stats(int fd);
diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
index e5fb45982..f03842478 100644
--- a/tests/i915/gem_exec_schedule.c
+++ b/tests/i915/gem_exec_schedule.c
@@ -1344,8 +1344,7 @@ static void reorder(int fd, const intel_ctx_cfg_t *cfg,
static void promotion(int fd, const intel_ctx_cfg_t *cfg, unsigned ring)
{
IGT_CORK_FENCE(cork);
- uint32_t result, dep;
- uint32_t result_read, dep_read;
+ uint32_t result, dep, dep_read;
const intel_ctx_t *ctx[3];
int fence;
@@ -1353,10 +1352,10 @@ static void promotion(int fd, const intel_ctx_cfg_t
*cfg, unsigned ring)
gem_context_set_priority(fd, ctx[LO]->id, MIN_PRIO);
ctx[HI] = intel_ctx_create(fd, cfg);
- gem_context_set_priority(fd, ctx[HI]->id, 0);
+ gem_context_set_priority(fd, ctx[HI]->id, MAX_PRIO);
ctx[NOISE] = intel_ctx_create(fd, cfg);
- gem_context_set_priority(fd, ctx[NOISE]->id, MIN_PRIO/2);
+ gem_context_set_priority(fd, ctx[NOISE]->id, 0);
result = gem_create(fd, 4096);
dep = gem_create(fd, 4096);
@@ -1383,11 +1382,9 @@ static void promotion(int fd, const intel_ctx_cfg_t
*cfg, unsigned ring)
dep_read = __sync_read_u32(fd, dep, 0);
gem_close(fd, dep);
- result_read = __sync_read_u32(fd, result, 0);
gem_close(fd, result);
igt_assert_eq_u32(dep_read, ctx[HI]->id);
- igt_assert_eq_u32(result_read, ctx[NOISE]->id);
intel_ctx_destroy(fd, ctx[NOISE]);
intel_ctx_destroy(fd, ctx[LO]);
@@ -2963,19 +2960,25 @@ igt_main
test_each_engine_store("preempt-other-chain", fd, ctx,
e)
preempt_other(fd, >cfg, e->flags, CHAIN);
- test_each_engine_store("preempt-queue", fd, ctx, e)
- preempt_queue(fd, >cfg, e->flags, 0);
+ test_each_engine_store("preempt-engines", fd, ctx, e)
+ preempt_engines(fd, e, 0);
- test_each_engine_store("preempt-queue-chain", fd, ctx,
e)
- preempt_queue(fd, >cfg, e->flags, CHAIN);
- test_each_engine_store("preempt-queue-contexts", fd,
ctx, e)
- preempt_queue(fd, >cfg, e->flags,
CONTEXTS);
+ igt_subtest_group {
+ igt_fixture {
+
igt_require(!gem_scheduler_has_static_priority(fd));
+ }
- test_each_engine_store("preempt-queue-contexts-chain",
fd, ctx, e)
- preempt_queue(fd, >cfg, e->flags, CONTEXTS
| CHAIN);
+ test_each_engine_store("preempt-queue", fd,
ctx, e)
+ preempt_queue(fd, >cfg, e->flags,
0);
- test_each_engine_store("preempt-engines", fd, ctx, e)
- preempt_engines(fd, e, 0);
+
[Intel-gfx] [PATCH i-g-t 3/7] lib/intel_ctx: Add support for parallel contexts to intel_ctx library
Signed-off-by: Matthew Brost
---
lib/intel_ctx.c | 28 +++-
lib/intel_ctx.h | 2 ++
2 files changed, 29 insertions(+), 1 deletion(-)
diff --git a/lib/intel_ctx.c b/lib/intel_ctx.c
index f28c15544..11ec6fca4 100644
--- a/lib/intel_ctx.c
+++ b/lib/intel_ctx.c
@@ -83,6 +83,7 @@ __context_create_cfg(int fd, const intel_ctx_cfg_t *cfg,
uint32_t *ctx_id)
{
uint64_t ext_root = 0;
I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(balance, GEM_MAX_ENGINES);
+ I915_DEFINE_CONTEXT_ENGINES_PARALLEL_SUBMIT(parallel, GEM_MAX_ENGINES);
I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, GEM_MAX_ENGINES);
struct drm_i915_gem_context_create_ext_setparam engines_param, vm_param;
struct drm_i915_gem_context_create_ext_setparam persist_param;
@@ -117,7 +118,29 @@ __context_create_cfg(int fd, const intel_ctx_cfg_t *cfg,
uint32_t *ctx_id)
unsigned num_logical_engines;
memset(, 0, sizeof(engines));
- if (cfg->load_balance) {
+ if (cfg->parallel) {
+ memset(, 0, sizeof(parallel));
+
+ num_logical_engines = 1;
+
+ parallel.base.name =
+ I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT;
+
+ engines.engines[0].engine_class =
+ I915_ENGINE_CLASS_INVALID;
+ engines.engines[0].engine_instance =
+ I915_ENGINE_CLASS_INVALID_NONE;
+
+ parallel.num_siblings = cfg->num_engines;
+ parallel.width = cfg->width;
+ for (i = 0; i < cfg->num_engines * cfg->width; i++) {
+ igt_assert_eq(cfg->engines[0].engine_class,
+ cfg->engines[i].engine_class);
+ parallel.engines[i] = cfg->engines[i];
+ }
+
+ engines.extensions = to_user_pointer();
+ } else if (cfg->load_balance) {
memset(, 0, sizeof(balance));
/* In this case, the first engine is the virtual
@@ -127,6 +150,9 @@ __context_create_cfg(int fd, const intel_ctx_cfg_t *cfg,
uint32_t *ctx_id)
igt_assert(cfg->num_engines + 1 <= GEM_MAX_ENGINES);
num_logical_engines = cfg->num_engines + 1;
+ balance.base.name =
+ I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE;
+
engines.engines[0].engine_class =
I915_ENGINE_CLASS_INVALID;
engines.engines[0].engine_instance =
diff --git a/lib/intel_ctx.h b/lib/intel_ctx.h
index 9649f6d96..89c65fcd3 100644
--- a/lib/intel_ctx.h
+++ b/lib/intel_ctx.h
@@ -46,7 +46,9 @@ typedef struct intel_ctx_cfg {
uint32_t vm;
bool nopersist;
bool load_balance;
+ bool parallel;
unsigned int num_engines;
+ unsigned int width;
struct i915_engine_class_instance engines[GEM_MAX_ENGINES];
} intel_ctx_cfg_t;
--
2.28.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 5/7] include/drm-uapi: Add static priority mapping UAPI
Signed-off-by: Matthew Brost
---
include/drm-uapi/i915_drm.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index 6ac6c76b4..008d39426 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -572,6 +572,15 @@ typedef struct drm_i915_irq_wait {
#define I915_SCHEDULER_CAP_PREEMPTION(1ul << 2)
#define I915_SCHEDULER_CAP_SEMAPHORES(1ul << 3)
#define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4)
+/*
+ * Indicates the 2k user priority levels are statically mapped into 3 buckets
as
+ * follows:
+ *
+ * -1k to -1 Low priority
+ * 0 Normal priority
+ * 1 to 1k Highest priority
+ */
+#define I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP (1ul << 5)
#define I915_PARAM_HUC_STATUS 42
--
2.28.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 4/7] i915/gem_exec_balancer: Test parallel execbuf
Add basic parallel execbuf submission test which more or less just
submits the same BB in loop a which does an atomic increment to a memory
location. The memory location is checked at the end for the correct
value. Different sections use various IOCTL options (e.g. fences,
location of BBs, etc...).
In addition to above sections, an additional section ensure the ordering
of parallel submission by submitting a spinning batch to 1 individual
engine, submit a parallel execbuf to all engines instances within the
class, verify none on parallel execbuf make to hardware, release
spinner, and finally verify everything has completed.
Signed-off-by: Matthew Brost
---
lib/intel_reg.h| 5 +
tests/i915/gem_exec_balancer.c | 487 +
2 files changed, 492 insertions(+)
diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index ac1fc6cbc..146ac76c9 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -2593,6 +2593,11 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define STATE3D_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x01<<16))
+/* Atomics */
+#define MI_ATOMIC ((0x2f << 23) | 2)
+#define MI_ATOMIC_INLINE_DATA (1 << 18)
+#define MI_ATOMIC_ADD (0x7 << 8)
+
/* Batch */
#define MI_BATCH_BUFFER((0x30 << 23) | 1)
#define MI_BATCH_BUFFER_START (0x31 << 23)
diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/gem_exec_balancer.c
index 2f98950bb..053f1d1f7 100644
--- a/tests/i915/gem_exec_balancer.c
+++ b/tests/i915/gem_exec_balancer.c
@@ -25,6 +25,7 @@
#include
#include
#include
+#include
#include "i915/gem.h"
#include "i915/gem_create.h"
@@ -56,6 +57,31 @@ static size_t sizeof_load_balance(int count)
#define alloca0(sz) ({ size_t sz__ = (sz); memset(alloca(sz__), 0, sz__); })
+static int
+__i915_query(int fd, struct drm_i915_query *q)
+{
+ if (igt_ioctl(fd, DRM_IOCTL_I915_QUERY, q))
+ return -errno;
+
+ return 0;
+}
+
+static int
+__i915_query_items(int fd, struct drm_i915_query_item *items, uint32_t n_items)
+{
+ struct drm_i915_query q = {
+ .num_items = n_items,
+ .items_ptr = to_user_pointer(items),
+ };
+
+ return __i915_query(fd, );
+}
+
+#define i915_query_items(fd, items, n_items) do { \
+ igt_assert_eq(__i915_query_items(fd, items, n_items), 0); \
+ errno = 0; \
+ } while (0)
+
static bool has_class_instance(int i915, uint16_t class, uint16_t instance)
{
int fd;
@@ -2691,6 +2717,380 @@ static void nohangcheck(int i915)
close(params);
}
+static void check_bo(int i915, uint32_t handle, unsigned int count, bool wait)
+{
+ uint32_t *map;
+
+ map = gem_mmap__cpu(i915, handle, 0, 4096, PROT_READ);
+ if (wait)
+ gem_set_domain(i915, handle, I915_GEM_DOMAIN_CPU,
+ I915_GEM_DOMAIN_CPU);
+ igt_assert_eq(map[0], count);
+ munmap(map, 4096);
+}
+
+static struct drm_i915_query_engine_info *query_engine_info(int i915)
+{
+ struct drm_i915_query_engine_info *engines;
+ struct drm_i915_query_item item;
+
+#define QUERY_SIZE 0x4000
+ engines = malloc(QUERY_SIZE);
+ igt_assert(engines);
+
+ memset(engines, 0, QUERY_SIZE);
+ memset(, 0, sizeof(item));
+ item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+ item.data_ptr = to_user_pointer(engines);
+ item.length = QUERY_SIZE;
+
+ i915_query_items(i915, , 1);
+ igt_assert(item.length >= 0);
+ igt_assert(item.length <= QUERY_SIZE);
+#undef QUERY_SIZE
+
+ return engines;
+}
+
+/* This function only works if siblings contains all instances of a class */
+static void logical_sort_siblings(int i915,
+ struct i915_engine_class_instance *siblings,
+ unsigned int count)
+{
+ struct i915_engine_class_instance *sorted;
+ struct drm_i915_query_engine_info *engines;
+ unsigned int i, j;
+
+ sorted = calloc(count, sizeof(*sorted));
+ igt_assert(sorted);
+
+ engines = query_engine_info(i915);
+
+ for (j = 0; j < count; ++j) {
+ for (i = 0; i < engines->num_engines; ++i) {
+ if (siblings[j].engine_class ==
+ engines->engines[i].engine.engine_class &&
+ siblings[j].engine_instance ==
+ engines->engines[i].engine.engine_instance) {
+ uint16_t logical_instance =
+ engines->engines[i].logical_instance;
+
+ igt_assert(logical_instance < count);
+
igt_assert(!sorted[logical_instance].engine_class);
+
igt_assert(!sorted[logical_instance].engine_instance);
+
+ sorted[logical_instance]
[Intel-gfx] [PATCH i-g-t 0/7] Updates for GuC & parallel execbuf
IGT updates for GuC submission [1] and parallel submission (aka multi-bb execbuf) [2]. This entails adding tests for parallel submission and teaching IGTs to know of static priority mapping. More IGTs likely need to be updated gem_ctx_persistence and i915_hangman come to mind. Expect following series to address those tests. Signed-off-by: Matthew Brost [1] https://patchwork.freedesktop.org/series/91840/ [2] https://patchwork.freedesktop.org/series/92789/ Matthew Brost (7): include/drm-uapi: Add parallel context configuration uAPI include/drm-uapi: Add logical mapping uAPI lib/intel_ctx: Add support for parallel contexts to intel_ctx library i915/gem_exec_balancer: Test parallel execbuf include/drm-uapi: Add static priority mapping UAPI i915/gem_scheduler: Make gem_scheduler understand static priority mapping i915/gem_ctx_shared: Make gem_ctx_shared understand static priority mapping include/drm-uapi/i915_drm.h| 145 +- lib/i915/gem_scheduler.c | 13 + lib/i915/gem_scheduler.h | 1 + lib/intel_ctx.c| 28 +- lib/intel_ctx.h| 2 + lib/intel_reg.h| 5 + tests/i915/gem_ctx_shared.c| 5 +- tests/i915/gem_exec_balancer.c | 487 + tests/i915/gem_exec_schedule.c | 47 ++-- 9 files changed, 709 insertions(+), 24 deletions(-) -- 2.28.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 2/7] include/drm-uapi: Add logical mapping uAPI
Signed-off-by: Matthew Brost
---
include/drm-uapi/i915_drm.h | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index 3c1aac348..6ac6c76b4 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -2518,14 +2518,20 @@ struct drm_i915_engine_info {
/** @flags: Engine flags. */
__u64 flags;
+#define I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE (1 << 0)
/** @capabilities: Capabilities of this engine. */
__u64 capabilities;
#define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0)
#define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC(1 << 1)
+ /** @logical_instance: Logical instance of engine */
+ __u16 logical_instance;
+
/** @rsvd1: Reserved fields. */
- __u64 rsvd1[4];
+ __u16 rsvd1[3];
+ /** @rsvd2: Reserved fields. */
+ __u64 rsvd2[2];
};
/**
--
2.28.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 1/7] include/drm-uapi: Add parallel context configuration uAPI
Signed-off-by: Matthew Brost
---
include/drm-uapi/i915_drm.h | 128
1 file changed, 128 insertions(+)
diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index a1c0030c3..3c1aac348 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -1705,6 +1705,7 @@ struct drm_i915_gem_context_param {
* Extensions:
* i915_context_engines_load_balance (I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE)
* i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND)
+ * i915_context_engines_parallel_submit
(I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT)
*/
#define I915_CONTEXT_PARAM_ENGINES 0xa
@@ -1883,10 +1884,137 @@ struct i915_context_engines_bond {
struct i915_engine_class_instance engines[N__]; \
} __attribute__((packed)) name__
+/**
+ * struct i915_context_engines_parallel_submit - Configure engine for
+ * parallel submission.
+ *
+ * Setup a slot in the context engine map to allow multiple BBs to be submitted
+ * in a single execbuf IOCTL. Those BBs will then be scheduled to run on the
GPU
+ * in parallel. Multiple hardware contexts are created internally in the i915
+ * run these BBs. Once a slot is configured for N BBs only N BBs can be
+ * submitted in each execbuf IOCTL and this is implicit behavior e.g. The user
+ * doesn't tell the execbuf IOCTL there are N BBs, the execbuf IOCTL knows how
+ * many BBs there are based on the slot's configuration. The N BBs are the last
+ * N buffer objects or first N if I915_EXEC_BATCH_FIRST is set.
+ *
+ * The default placement behavior is to create implicit bonds between each
+ * context if each context maps to more than 1 physical engine (e.g. context is
+ * a virtual engine). Also we only allow contexts of same engine class and
these
+ * contexts must be in logically contiguous order. Examples of the placement
+ * behavior described below. Lastly, the default is to not allow BBs to
+ * preempted mid BB rather insert coordinated preemption on all hardware
+ * contexts between each set of BBs. Flags may be added in the future to change
+ * both of these default behaviors.
+ *
+ * Returns -EINVAL if hardware context placement configuration is invalid or if
+ * the placement configuration isn't supported on the platform / submission
+ * interface.
+ * Returns -ENODEV if extension isn't supported on the platform / submission
+ * interface.
+ *
+ * .. code-block:: none
+ *
+ * Example 1 pseudo code:
+ * CS[X] = generic engine of same class, logical instance X
+ * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
+ * set_engines(INVALID)
+ * set_parallel(engine_index=0, width=2, num_siblings=1,
+ * engines=CS[0],CS[1])
+ *
+ * Results in the following valid placement:
+ * CS[0], CS[1]
+ *
+ * Example 2 pseudo code:
+ * CS[X] = generic engine of same class, logical instance X
+ * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
+ * set_engines(INVALID)
+ * set_parallel(engine_index=0, width=2, num_siblings=2,
+ * engines=CS[0],CS[2],CS[1],CS[3])
+ *
+ * Results in the following valid placements:
+ * CS[0], CS[1]
+ * CS[2], CS[3]
+ *
+ * This can also be thought of as 2 virtual engines described by 2-D array
+ * in the engines the field with bonds placed between each index of the
+ * virtual engines. e.g. CS[0] is bonded to CS[1], CS[2] is bonded to
+ * CS[3].
+ * VE[0] = CS[0], CS[2]
+ * VE[1] = CS[1], CS[3]
+ *
+ * Example 3 pseudo code:
+ * CS[X] = generic engine of same class, logical instance X
+ * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
+ * set_engines(INVALID)
+ * set_parallel(engine_index=0, width=2, num_siblings=2,
+ * engines=CS[0],CS[1],CS[1],CS[3])
+ *
+ * Results in the following valid and invalid placements:
+ * CS[0], CS[1]
+ * CS[1], CS[3] - Not logical contiguous, return -EINVAL
+ */
+struct i915_context_engines_parallel_submit {
+ /**
+* @base: base user extension.
+*/
+ struct i915_user_extension base;
+
+ /**
+* @engine_index: slot for parallel engine
+*/
+ __u16 engine_index;
+
+ /**
+* @width: number of contexts per parallel engine
+*/
+ __u16 width;
+
+ /**
+* @num_siblings: number of siblings per context
+*/
+ __u16 num_siblings;
+
+ /**
+* @mbz16: reserved for future use; must be zero
+*/
+ __u16 mbz16;
+
+ /**
+* @flags: all undefined flags must be zero, currently not defined flags
+*/
+ __u64 flags;
+
+ /**
+* @mbz64: reserved for future use; must be zero
+*/
+ __u64 mbz64[3];
+
+ /**
+* @engines: 2-d array of engine instances to configure parallel engine
+*
+* length = width (i) * num_siblings (j)
+
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/4] drm/i915/step: Add macro magic for handling steps
== Series Details ==
Series: series starting with [CI,1/4] drm/i915/step: Add macro magic for
handling steps
URL : https://patchwork.freedesktop.org/series/92849/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10367 -> Patchwork_20671
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20671/index.html
Known issues
Here are the changes found in Patchwork_20671 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@cs-gfx:
- fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20671/fi-kbl-soraka/igt@amdgpu/amd_ba...@cs-gfx.html
Possible fixes
* igt@gem_exec_suspend@basic-s0:
- {fi-tgl-1115g4}:[FAIL][2] ([i915#1888]) -> [PASS][3]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s0.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20671/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s0.html
* igt@i915_selftest@live@execlists:
- fi-kbl-soraka: [INCOMPLETE][4] ([i915#2782] / [i915#794]) ->
[PASS][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/fi-kbl-soraka/igt@i915_selftest@l...@execlists.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20671/fi-kbl-soraka/igt@i915_selftest@l...@execlists.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7500u: [DMESG-FAIL][6] ([i915#165]) -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20671/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [FAIL][8] ([i915#1372]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20671/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372
[i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
[i915#794]: https://gitlab.freedesktop.org/drm/intel/issues/794
Participating hosts (38 -> 35)
--
Missing(3): fi-ilk-m540 fi-bdw-samus fi-hsw-4200u
Build changes
-
* Linux: CI_DRM_10367 -> Patchwork_20671
CI-20190529: 20190529
CI_DRM_10367: 598494d0149b67545593dfb1b5fa60278907749e @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6146: 6caef22e4aafed275771f564d4ea4cab09896ebc @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20671: 55698bd418a0393b5b09555a1258cecd69654268 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
55698bd418a0 drm/i915/firmware: Update to DMC v2.03 on RKL
4a8d375d3242 drm/i915/firmware: Update to DMC v2.12 on TGL
ef7c2d172b12 drm/i915/dmc: Change intel_get_stepping_info()
c0b839cec037 drm/i915/step: Add macro magic for handling steps
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20671/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/4] drm/i915/gt: rename legacy engine->hw_id to engine->gen6_hw_id
On Tue, Jul 20, 2021 at 04:20:13PM -0700, Lucas De Marchi wrote:
> We kept adding new engines and for that increasing hw_id unnecessarily:
> it's not used since GRAPHICS_VER == 8. Prepend "gen6" to the field and
> try to pack it in the structs to give a hint this field is actually not
> used in recent platforms.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
although if we apply patch #4 we could probably drop this intermediate
step.
Matt
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c| 12 ++--
> drivers/gpu/drm/i915/gt/intel_engine_types.h | 2 +-
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> 3 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index a11f69f2e46e..508221de411c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -42,7 +42,7 @@
>
> #define MAX_MMIO_BASES 3
> struct engine_info {
> - unsigned int hw_id;
> + u8 gen6_hw_id;
> u8 class;
> u8 instance;
> /* mmio bases table *must* be sorted in reverse graphics_ver order */
> @@ -54,7 +54,7 @@ struct engine_info {
>
> static const struct engine_info intel_engines[] = {
> [RCS0] = {
> - .hw_id = RCS0_HW,
> + .gen6_hw_id = RCS0_HW,
> .class = RENDER_CLASS,
> .instance = 0,
> .mmio_bases = {
> @@ -62,7 +62,7 @@ static const struct engine_info intel_engines[] = {
> },
> },
> [BCS0] = {
> - .hw_id = BCS0_HW,
> + .gen6_hw_id = BCS0_HW,
> .class = COPY_ENGINE_CLASS,
> .instance = 0,
> .mmio_bases = {
> @@ -70,7 +70,7 @@ static const struct engine_info intel_engines[] = {
> },
> },
> [VCS0] = {
> - .hw_id = VCS0_HW,
> + .gen6_hw_id = VCS0_HW,
> .class = VIDEO_DECODE_CLASS,
> .instance = 0,
> .mmio_bases = {
> @@ -102,7 +102,7 @@ static const struct engine_info intel_engines[] = {
> },
> },
> [VECS0] = {
> - .hw_id = VECS0_HW,
> + .gen6_hw_id = VECS0_HW,
> .class = VIDEO_ENHANCEMENT_CLASS,
> .instance = 0,
> .mmio_bases = {
> @@ -290,7 +290,7 @@ static int intel_engine_setup(struct intel_gt *gt, enum
> intel_engine_id id)
> engine->i915 = i915;
> engine->gt = gt;
> engine->uncore = gt->uncore;
> - engine->hw_id = info->hw_id;
> + engine->gen6_hw_id = info->gen6_hw_id;
> guc_class = engine_class_to_guc_class(info->class);
> engine->guc_id = MAKE_GUC_ID(guc_class, info->instance);
> engine->mmio_base = __engine_mmio_base(i915, info->mmio_bases);
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index a107eb58ffa2..266422d8d1b1 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -264,11 +264,11 @@ struct intel_engine_cs {
> enum intel_engine_id id;
> enum intel_engine_id legacy_idx;
>
> - unsigned int hw_id;
> unsigned int guc_id;
>
> intel_engine_mask_t mask;
>
> + u8 gen6_hw_id;
> u8 class;
> u8 instance;
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 943fe485c662..8750ffce9d61 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2572,7 +2572,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define ARB_MODE_BWGTLB_DISABLE (1 << 9)
> #define ARB_MODE_SWIZZLE_BDW (1 << 1)
> #define RENDER_HWS_PGA_GEN7 _MMIO(0x04080)
> -#define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100 * (engine)->hw_id)
> +#define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100 *
> (engine)->gen6_hw_id)
> #define GEN8_RING_FAULT_REG _MMIO(0x4094)
> #define GEN12_RING_FAULT_REG _MMIO(0xcec4)
> #define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7)
> --
> 2.31.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/4] drm/i915/gt: nuke unused legacy engine hw_id
On Tue, Jul 20, 2021 at 04:20:12PM -0700, Lucas De Marchi wrote:
> The engine hw_id is only used by RING_FAULT_REG(), which is not used
> since GRAPHICS_VER == 8. We tend to keep adding new defines just to be
> consistent, but let's try to remove them and let them defined to 0 when
> not used.
s/when not used/for engines that only exist on gen8+ platforms/
Reviewed-by: Matt Roper
For historical reference, we did use hw_id on gen8+ platforms too until
relatively recently --- it was used to set the engine's guc_id as well
up until:
commit c784e5249e773689e38d2bc1749f08b986621a26
Author: John Harrison
Date: Wed Oct 28 07:58:24 2020 -0700
drm/i915/guc: Update to use firmware v49.0.1
Matt
>
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c| 4
> drivers/gpu/drm/i915/gt/intel_engine_types.h | 4
> 2 files changed, 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index d561573ed98c..a11f69f2e46e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -80,7 +80,6 @@ static const struct engine_info intel_engines[] = {
> },
> },
> [VCS1] = {
> - .hw_id = VCS1_HW,
> .class = VIDEO_DECODE_CLASS,
> .instance = 1,
> .mmio_bases = {
> @@ -89,7 +88,6 @@ static const struct engine_info intel_engines[] = {
> },
> },
> [VCS2] = {
> - .hw_id = VCS2_HW,
> .class = VIDEO_DECODE_CLASS,
> .instance = 2,
> .mmio_bases = {
> @@ -97,7 +95,6 @@ static const struct engine_info intel_engines[] = {
> },
> },
> [VCS3] = {
> - .hw_id = VCS3_HW,
> .class = VIDEO_DECODE_CLASS,
> .instance = 3,
> .mmio_bases = {
> @@ -114,7 +111,6 @@ static const struct engine_info intel_engines[] = {
> },
> },
> [VECS1] = {
> - .hw_id = VECS1_HW,
> .class = VIDEO_ENHANCEMENT_CLASS,
> .instance = 1,
> .mmio_bases = {
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index 1cb9c3b70b29..a107eb58ffa2 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -34,10 +34,6 @@
> #define VCS0_HW 1
> #define BCS0_HW 2
> #define VECS0_HW 3
> -#define VCS1_HW 4
> -#define VCS2_HW 6
> -#define VCS3_HW 7
> -#define VECS1_HW 12
>
> /* Gen11+ HW Engine class + instance */
> #define RENDER_CLASS 0
> --
> 2.31.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/4] drm/i915/gt: fix platform prefix
On Tue, Jul 20, 2021 at 04:20:11PM -0700, Lucas De Marchi wrote:
> gen8_clear_engine_error_register() is actually not used by
> GRAPHICS_VER >= 8, since for those we are using another register that is
> not engine-dependent. Fix the platform prefix, to make clear we are not
> using any GEN6_RING_FAULT_REG_* one GRAPHICS_VER >= 8.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
> b/drivers/gpu/drm/i915/gt/intel_gt.c
> index e714e21c0a4d..a8efdd44e9cf 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -205,7 +205,7 @@ static void clear_register(struct intel_uncore *uncore,
> i915_reg_t reg)
> intel_uncore_rmw(uncore, reg, 0, 0);
> }
>
> -static void gen8_clear_engine_error_register(struct intel_engine_cs *engine)
> +static void gen6_clear_engine_error_register(struct intel_engine_cs *engine)
> {
> GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0);
> GEN6_RING_FAULT_REG_POSTING_READ(engine);
> @@ -251,7 +251,7 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
> enum intel_engine_id id;
>
> for_each_engine_masked(engine, gt, engine_mask, id)
> - gen8_clear_engine_error_register(engine);
> + gen6_clear_engine_error_register(engine);
> }
> }
>
> --
> 2.31.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 13/18] drm/i915/dg2: Don't wait for AUX power well enable ACKs
On DG2 we're supposed to just wait 600us after programming the well
before moving on; there won't be an ack from the hardware.
Bspec: 49296
Signed-off-by: Matt Roper
Reviewed-by: José Roberto de Souza
---
.../gpu/drm/i915/display/intel_display_power.c | 16
.../gpu/drm/i915/display/intel_display_power.h | 6 ++
2 files changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index bec380e58f40..4732efbb02f9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -341,6 +341,17 @@ static void hsw_wait_for_power_well_enable(struct
drm_i915_private *dev_priv,
{
const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
int pw_idx = power_well->desc->hsw.idx;
+ int enable_delay = power_well->desc->hsw.fixed_enable_delay;
+
+ /*
+* For some power wells we're not supposed to watch the status bit for
+* an ack, but rather just wait a fixed amount of time and then
+* proceed. This is only used on DG2.
+*/
+ if (IS_DG2(dev_priv) && enable_delay) {
+ usleep_range(enable_delay, 2 * enable_delay);
+ return;
+ }
/* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */
if (intel_de_wait_for_set(dev_priv, regs->driver,
@@ -4828,6 +4839,7 @@ static const struct i915_power_well_desc
xelpd_power_wells[] = {
{
.hsw.regs = _aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_A,
+ .hsw.fixed_enable_delay = 600,
},
},
{
@@ -4838,6 +4850,7 @@ static const struct i915_power_well_desc
xelpd_power_wells[] = {
{
.hsw.regs = _aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_B,
+ .hsw.fixed_enable_delay = 600,
},
},
{
@@ -4848,6 +4861,7 @@ static const struct i915_power_well_desc
xelpd_power_wells[] = {
{
.hsw.regs = _aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_C,
+ .hsw.fixed_enable_delay = 600,
},
},
{
@@ -4858,6 +4872,7 @@ static const struct i915_power_well_desc
xelpd_power_wells[] = {
{
.hsw.regs = _aux_power_well_regs,
.hsw.idx = XELPD_PW_CTL_IDX_AUX_D,
+ .hsw.fixed_enable_delay = 600,
},
},
{
@@ -4878,6 +4893,7 @@ static const struct i915_power_well_desc
xelpd_power_wells[] = {
{
.hsw.regs = _aux_power_well_regs,
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
+ .hsw.fixed_enable_delay = 600,
},
},
{
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
b/drivers/gpu/drm/i915/display/intel_display_power.h
index 4f0917df4375..22367b5cba96 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -223,6 +223,12 @@ struct i915_power_well_desc {
u8 idx;
/* Mask of pipes whose IRQ logic is backed by the pw */
u8 irq_pipe_mask;
+ /*
+* Instead of waiting for the status bit to ack enables,
+* just wait a specific amount of time and then consider
+* the well enabled.
+*/
+ u16 fixed_enable_delay;
/* The pw is backing the VGA functionality */
bool has_vga:1;
bool has_fuses:1;
--
2.25.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 16/18] drm/i915/dg2: Don't program BW_BUDDY registers
Although the BW_BUDDY registers still exist, they are not used for anything on DG2. This change is expected to hold true for future dgpu's too. Bspec: 49218 Signed-off-by: Matt Roper Reviewed-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_display_power.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 4732efbb02f9..81efc77bada0 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -5814,6 +5814,10 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) unsigned long abox_mask = INTEL_INFO(dev_priv)->abox_mask; int config, i; + /* BW_BUDDY registers are not used on dgpu's beyond DG1 */ + if (IS_DGFX(dev_priv) && !IS_DG1(dev_priv)) + return; + if (IS_ALDERLAKE_S(dev_priv) || IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) || IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) || -- 2.25.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 12/18] drm/i915/dg2: Skip shared DPLL handling
DG2 has no shared DPLL's or DDI clock muxing. The Port PLL is embedded
within the PHY.
Bspec: 54032
Bspec: 54034
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_display.c | 10 +++---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 5 -
2 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index c274bfb8e549..a165bb8ca2f8 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3474,7 +3474,8 @@ static void icl_ddi_bigjoiner_pre_enable(struct
intel_atomic_state *state,
* Enable sequence steps 1-7 on bigjoiner master
*/
intel_encoders_pre_pll_enable(state, master);
- intel_enable_shared_dpll(master_crtc_state);
+ if (master_crtc_state->shared_dpll)
+ intel_enable_shared_dpll(master_crtc_state);
intel_encoders_pre_enable(state, master);
/* and DSC on slave */
@@ -8633,10 +8634,11 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
PIPE_CONF_CHECK_BOOL(double_wide);
- PIPE_CONF_CHECK_P(shared_dpll);
+ if (dev_priv->dpll.mgr)
+ PIPE_CONF_CHECK_P(shared_dpll);
/* FIXME do the readout properly and get rid of this quirk */
- if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
+ if (dev_priv->dpll.mgr &&
!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
@@ -8668,7 +8670,9 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
+ }
+ if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
PIPE_CONF_CHECK_X(dsi_pll.ctrl);
PIPE_CONF_CHECK_X(dsi_pll.div);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index dfc31b682848..8e2bd8fa090a 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4462,7 +4462,10 @@ void intel_shared_dpll_init(struct drm_device *dev)
const struct dpll_info *dpll_info;
int i;
- if (IS_ALDERLAKE_P(dev_priv))
+ if (IS_DG2(dev_priv))
+ /* No shared DPLLs on DG2; port PLLs are part of the PHY */
+ dpll_mgr = NULL;
+ else if (IS_ALDERLAKE_P(dev_priv))
dpll_mgr = _pll_mgr;
else if (IS_ALDERLAKE_S(dev_priv))
dpll_mgr = _pll_mgr;
--
2.25.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 08/18] drm/i915/xehp: Handle new device context ID format
From: Stuart Summers
Xe_HP changes the format of the context ID from past platforms.
Signed-off-by: Stuart Summers
Signed-off-by: Umesh Nerlige Ramappa
Signed-off-by: Matt Roper
Reviewed-by: Matt Atwood
---
.../drm/i915/gt/intel_execlists_submission.c | 74 ---
drivers/gpu/drm/i915/gt/intel_lrc.c | 8 ++
drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 2 +
drivers/gpu/drm/i915/i915_perf.c | 29 +---
drivers/gpu/drm/i915/i915_reg.h | 5 ++
5 files changed, 97 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 56e25090da67..87cedaeb4bf8 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -153,6 +153,12 @@
#define GEN12_CSB_CTX_VALID(csb_dw) \
(FIELD_GET(GEN12_CSB_SW_CTX_ID_MASK, csb_dw) != GEN12_IDLE_CTX_ID)
+#define XEHP_CTX_STATUS_SWITCHED_TO_NEW_QUEUE BIT(1) /* upper csb dword */
+#define XEHP_CSB_SW_CTX_ID_MASKGENMASK(31, 10)
+#define XEHP_IDLE_CTX_ID 0x
+#define XEHP_CSB_CTX_VALID(csb_dw) \
+ (FIELD_GET(XEHP_CSB_SW_CTX_ID_MASK, csb_dw) != XEHP_IDLE_CTX_ID)
+
/* Typical size of the average request (2 pipecontrols and a MI_BB) */
#define EXECLISTS_REQUEST_SIZE 64 /* bytes */
@@ -478,6 +484,16 @@ __execlists_schedule_in(struct i915_request *rq)
/* Use a fixed tag for OA and friends */
GEM_BUG_ON(ce->tag <= BITS_PER_LONG);
ce->lrc.ccid = ce->tag;
+ } else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50)) {
+ /* We don't need a strict matching tag, just different values */
+ unsigned int tag = ffs(READ_ONCE(engine->context_tag));
+
+ GEM_BUG_ON(tag == 0 || tag >= BITS_PER_LONG);
+ clear_bit(tag - 1, >context_tag);
+ ce->lrc.ccid = tag << (XEHP_SW_CTX_ID_SHIFT - 32);
+
+ BUILD_BUG_ON(BITS_PER_LONG > GEN12_MAX_CONTEXT_HW_ID);
+
} else {
/* We don't need a strict matching tag, just different values */
unsigned int tag = __ffs(engine->context_tag);
@@ -588,8 +604,14 @@ static void __execlists_schedule_out(struct i915_request *
const rq,
intel_engine_add_retire(engine, ce->timeline);
ccid = ce->lrc.ccid;
- ccid >>= GEN11_SW_CTX_ID_SHIFT - 32;
- ccid &= GEN12_MAX_CONTEXT_HW_ID;
+ if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50)) {
+ ccid >>= XEHP_SW_CTX_ID_SHIFT - 32;
+ ccid &= XEHP_MAX_CONTEXT_HW_ID;
+ } else {
+ ccid >>= GEN11_SW_CTX_ID_SHIFT - 32;
+ ccid &= GEN12_MAX_CONTEXT_HW_ID;
+ }
+
if (ccid < BITS_PER_LONG) {
GEM_BUG_ON(ccid == 0);
GEM_BUG_ON(test_bit(ccid - 1, >context_tag));
@@ -1648,13 +1670,24 @@ static void invalidate_csb_entries(const u64 *first,
const u64 *last)
* bits 44-46: reserved
* bits 47-57: sw context id of the lrc the GT switched away from
* bits 58-63: sw counter of the lrc the GT switched away from
+ *
+ * Xe_HP csb shuffles things around compared to TGL:
+ *
+ * bits 0-3: context switch detail (same possible values as TGL)
+ * bits 4-9: engine instance
+ * bits 10-25: sw context id of the lrc the GT switched to
+ * bits 26-31: sw counter of the lrc the GT switched to
+ * bit 32:semaphore wait mode (poll or signal), Only valid when
+ * switch detail is set to "wait on semaphore"
+ * bit 33:switched to new queue
+ * bits 34-41: wait detail (for switch detail 1 to 4)
+ * bits 42-57: sw context id of the lrc the GT switched away from
+ * bits 58-63: sw counter of the lrc the GT switched away from
*/
-static bool gen12_csb_parse(const u64 csb)
+static inline bool
+__gen12_csb_parse(bool ctx_to_valid, bool ctx_away_valid, bool new_queue,
+ u8 switch_detail)
{
- bool ctx_away_valid = GEN12_CSB_CTX_VALID(upper_32_bits(csb));
- bool new_queue =
- lower_32_bits(csb) & GEN12_CTX_STATUS_SWITCHED_TO_NEW_QUEUE;
-
/*
* The context switch detail is not guaranteed to be 5 when a preemption
* occurs, so we can't just check for that. The check below works for
@@ -1663,7 +1696,7 @@ static bool gen12_csb_parse(const u64 csb)
* would require some extra handling, but we don't support that.
*/
if (!ctx_away_valid || new_queue) {
- GEM_BUG_ON(!GEN12_CSB_CTX_VALID(lower_32_bits(csb)));
+ GEM_BUG_ON(!ctx_to_valid);
return true;
}
@@ -1672,10 +1705,26 @@ static bool gen12_csb_parse(const u64 csb)
* context switch on an unsuccessful wait instruction since we always
* use polling mode.
*/
-
[Intel-gfx] [CI 10/18] drm/i915/dg2: Add fake PCH
As with DG1, DG2 has an ICL-style south display interface provided on
the same PCI device. Add a fake PCH to ensure DG2 takes the appropriate
codepaths for south display handling.
Bspec: 54871, 50062, 49961, 53673
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
Signed-off-by: Aditya Swarup
Signed-off-by: José Roberto de Souza
Reviewed-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_irq.c | 2 +-
drivers/gpu/drm/i915/intel_pch.c | 3 +++
drivers/gpu/drm/i915/intel_pch.h | 2 ++
3 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 61dceb2a17c1..e2171bd2820e 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -207,7 +207,7 @@ static void intel_hpd_init_pins(struct drm_i915_private
*dev_priv)
(!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)))
return;
- if (HAS_PCH_DG1(dev_priv))
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
hpd->pch_hpd = hpd_sde_dg1;
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
hpd->pch_hpd = hpd_icp;
diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c
index 4e92ae19189e..cc44164e242b 100644
--- a/drivers/gpu/drm/i915/intel_pch.c
+++ b/drivers/gpu/drm/i915/intel_pch.c
@@ -211,6 +211,9 @@ void intel_detect_pch(struct drm_i915_private *dev_priv)
if (IS_DG1(dev_priv)) {
dev_priv->pch_type = PCH_DG1;
return;
+ } else if (IS_DG2(dev_priv)) {
+ dev_priv->pch_type = PCH_DG2;
+ return;
}
/*
diff --git a/drivers/gpu/drm/i915/intel_pch.h b/drivers/gpu/drm/i915/intel_pch.h
index e2f3f30c6445..7c0d83d292dc 100644
--- a/drivers/gpu/drm/i915/intel_pch.h
+++ b/drivers/gpu/drm/i915/intel_pch.h
@@ -30,6 +30,7 @@ enum intel_pch {
/* Fake PCHs, functionality handled on the same PCI dev */
PCH_DG1 = 1024,
+ PCH_DG2,
};
#define INTEL_PCH_DEVICE_ID_MASK 0xff80
@@ -62,6 +63,7 @@ enum intel_pch {
#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
#define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
+#define HAS_PCH_DG2(dev_priv) (INTEL_PCH_TYPE(dev_priv) ==
PCH_DG2)
#define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) ==
PCH_ADP)
#define HAS_PCH_DG1(dev_priv) (INTEL_PCH_TYPE(dev_priv) ==
PCH_DG1)
#define HAS_PCH_JSP(dev_priv) (INTEL_PCH_TYPE(dev_priv) ==
PCH_JSP)
--
2.25.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 15/18] drm/i915/dg2: Add dbuf programming
DG2 extends our DDB to four DBuf slices; pipes A+B only have access to
the first two slices, whereas pipes C+D only have access to the second
two.
Confusingly, our bspec decided to switch from 1-based numbering
of dbuf slices (S1, S2) to 0-based numbering (S0, S1, S2, S3) in
Display13. At the moment we're using the 0-based number scheme for the
DBUF_CTL_S() register addressing, but the 1-based number scheme in the
actual slice assignment tables. We may want to consider switching the
assignment over to 0-based numbering too at some point...
Bspec: 49255
Bspec: 50057
Cc: Stanislav Lisovskiy
Signed-off-by: Matt Roper
Reviewed-by: José Roberto de Souza
---
.../drm/i915/display/intel_display_power.h| 4 +
drivers/gpu/drm/i915/intel_pm.c | 120 +-
2 files changed, 123 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
b/drivers/gpu/drm/i915/display/intel_display_power.h
index 22367b5cba96..ad788bbd727d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -392,6 +392,10 @@ intel_display_power_put_all_in_set(struct drm_i915_private
*i915,
intel_display_power_put_mask_in_set(i915, power_domain_set,
power_domain_set->mask);
}
+/*
+ * FIXME: We should probably switch this to a 0-based scheme to be consistent
+ * with how we now name/number DBUF_CTL instances.
+ */
enum dbuf_slice {
DBUF_S1,
DBUF_S2,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 597383430ca6..aa64b2ef2efb 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4584,6 +4584,117 @@ static const struct dbuf_slice_conf_entry
tgl_allowed_dbufs[] =
{}
};
+static const struct dbuf_slice_conf_entry dg2_allowed_dbufs[] = {
+ {
+ .active_pipes = BIT(PIPE_A),
+ .dbuf_mask = {
+ [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
+ },
+ },
+ {
+ .active_pipes = BIT(PIPE_B),
+ .dbuf_mask = {
+ [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2),
+ },
+ },
+ {
+ .active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
+ .dbuf_mask = {
+ [PIPE_A] = BIT(DBUF_S1),
+ [PIPE_B] = BIT(DBUF_S2),
+ },
+ },
+ {
+ .active_pipes = BIT(PIPE_C),
+ .dbuf_mask = {
+ [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
+ },
+ },
+ {
+ .active_pipes = BIT(PIPE_A) | BIT(PIPE_C),
+ .dbuf_mask = {
+ [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
+ [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
+ },
+ },
+ {
+ .active_pipes = BIT(PIPE_B) | BIT(PIPE_C),
+ .dbuf_mask = {
+ [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2),
+ [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
+ },
+ },
+ {
+ .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+ .dbuf_mask = {
+ [PIPE_A] = BIT(DBUF_S1),
+ [PIPE_B] = BIT(DBUF_S2),
+ [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
+ },
+ },
+ {
+ .active_pipes = BIT(PIPE_D),
+ .dbuf_mask = {
+ [PIPE_D] = BIT(DBUF_S3) | BIT(DBUF_S4),
+ },
+ },
+ {
+ .active_pipes = BIT(PIPE_A) | BIT(PIPE_D),
+ .dbuf_mask = {
+ [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
+ [PIPE_D] = BIT(DBUF_S3) | BIT(DBUF_S4),
+ },
+ },
+ {
+ .active_pipes = BIT(PIPE_B) | BIT(PIPE_D),
+ .dbuf_mask = {
+ [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2),
+ [PIPE_D] = BIT(DBUF_S3) | BIT(DBUF_S4),
+ },
+ },
+ {
+ .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D),
+ .dbuf_mask = {
+ [PIPE_A] = BIT(DBUF_S1),
+ [PIPE_B] = BIT(DBUF_S2),
+ [PIPE_D] = BIT(DBUF_S3) | BIT(DBUF_S4),
+ },
+ },
+ {
+ .active_pipes = BIT(PIPE_C) | BIT(PIPE_D),
+ .dbuf_mask = {
+ [PIPE_C] = BIT(DBUF_S3),
+ [PIPE_D] = BIT(DBUF_S4),
+ },
+ },
+ {
+ .active_pipes = BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D),
+ .dbuf_mask = {
+ [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
+ [PIPE_C] = BIT(DBUF_S3),
+ [PIPE_D] = BIT(DBUF_S4),
+ },
+ },
+
[Intel-gfx] [CI 01/18] drm/i915: Add XE_HP initial definitions
From: Lucas De Marchi
Our _FEATURES macro went back to GEN7, extending each other, making it
difficult to grasp what was really enabled/disabled. Take the
opportunity of the GEN -> XE_HP name break and also break with the
feature inheritance.
For XE_HP this basically goes from GEN12 back to GEN7 coalescing the
features making sure the overrides remain, remove all the
display-specific features and sort it.
Then also remove the definitions that would be overridden by
DGFX_FEATURES and those that were 0 (since that is the default).
Exception here is has_master_unit_irq: although it is a feature that
started with DG1 and is true for all DGFX platforms, it's also true for
XE_HP in general.
Signed-off-by: Lucas De Marchi
Signed-off-by: Matt Roper
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_pci.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 67696d752271..be5ee5e0e324 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -995,6 +995,30 @@ static const struct intel_device_info adl_p_info = {
};
#undef GEN
+
+#define XE_HP_PAGE_SIZES \
+ .page_sizes = I915_GTT_PAGE_SIZE_4K | \
+ I915_GTT_PAGE_SIZE_64K | \
+ I915_GTT_PAGE_SIZE_2M
+
+#define XE_HP_FEATURES \
+ .graphics_ver = 12, \
+ .graphics_rel = 50, \
+ XE_HP_PAGE_SIZES, \
+ .dma_mask_size = 46, \
+ .has_64bit_reloc = 1, \
+ .has_global_mocs = 1, \
+ .has_gt_uc = 1, \
+ .has_llc = 1, \
+ .has_logical_ring_contexts = 1, \
+ .has_logical_ring_elsq = 1, \
+ .has_rc6 = 1, \
+ .has_reset_engine = 1, \
+ .has_rps = 1, \
+ .has_runtime_pm = 1, \
+ .ppgtt_size = 48, \
+ .ppgtt_type = INTEL_PPGTT_FULL
+
#undef PLATFORM
/*
--
2.25.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 11/18] drm/i915/dg2: Add cdclk table and reference clock
Note that DG2 only has a single possible refclk frequency (38.4 MHz).
v2:
- Drop two now-unused cdclk entries
Bspec: 54034
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
Signed-off-by: Matt Roper
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 22 --
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 944fb13b9d98..ff35c29508d5 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1290,6 +1290,16 @@ static const struct intel_cdclk_vals adlp_cdclk_table[]
= {
{}
};
+static const struct intel_cdclk_vals dg2_cdclk_table[] = {
+ { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 9 },
+ { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
+ { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
+ { .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 },
+ { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
+ { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
+ {}
+};
+
static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
{
const struct intel_cdclk_vals *table = dev_priv->cdclk.table;
@@ -1408,7 +1418,9 @@ static void bxt_de_pll_readout(struct drm_i915_private
*dev_priv,
{
u32 val, ratio;
- if (DISPLAY_VER(dev_priv) >= 11)
+ if (IS_DG2(dev_priv))
+ cdclk_config->ref = 38400;
+ else if (DISPLAY_VER(dev_priv) >= 11)
icl_readout_refclk(dev_priv, cdclk_config);
else if (IS_CANNONLAKE(dev_priv))
cnl_readout_refclk(dev_priv, cdclk_config);
@@ -2873,7 +2885,13 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
*/
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_ALDERLAKE_P(dev_priv)) {
+ if (IS_DG2(dev_priv)) {
+ dev_priv->display.set_cdclk = bxt_set_cdclk;
+ dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+ dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
+ dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+ dev_priv->cdclk.table = dg2_cdclk_table;
+ } else if (IS_ALDERLAKE_P(dev_priv)) {
dev_priv->display.set_cdclk = bxt_set_cdclk;
dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
--
2.25.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 09/18] drm/i915/xehp: New engine context offsets
From: Prathap Kumar Valsan
The layout of some engine contexts has changed on Xe_HP. Define the new
offsets.
Bspec: 45585, 46256
Signed-off-by: Prathap Kumar Valsan
Signed-off-by: Ramalingam C
Signed-off-by: Venkata Ramana Nayana
Signed-off-by: Akeem G Abodunrin
Signed-off-by: Matt Roper
Reviewed-by: Matt Atwood
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 65 ++---
1 file changed, 59 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 7f8fe6726504..c3f5bec8ae15 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -484,6 +484,47 @@ static const u8 gen12_rcs_offsets[] = {
END
};
+static const u8 xehp_rcs_offsets[] = {
+ NOP(1),
+ LRI(13, POSTED),
+ REG16(0x244),
+ REG(0x034),
+ REG(0x030),
+ REG(0x038),
+ REG(0x03c),
+ REG(0x168),
+ REG(0x140),
+ REG(0x110),
+ REG(0x1c0),
+ REG(0x1c4),
+ REG(0x1c8),
+ REG(0x180),
+ REG16(0x2b4),
+
+ NOP(5),
+ LRI(9, POSTED),
+ REG16(0x3a8),
+ REG16(0x28c),
+ REG16(0x288),
+ REG16(0x284),
+ REG16(0x280),
+ REG16(0x27c),
+ REG16(0x278),
+ REG16(0x274),
+ REG16(0x270),
+
+ LRI(3, POSTED),
+ REG(0x1b0),
+ REG16(0x5a8),
+ REG16(0x5ac),
+
+ NOP(6),
+ LRI(1, 0),
+ REG(0x0c8),
+
+ END
+};
+
#undef END
#undef REG16
#undef REG
@@ -502,7 +543,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs
*engine)
!intel_engine_has_relative_mmio(engine));
if (engine->class == RENDER_CLASS) {
- if (GRAPHICS_VER(engine->i915) >= 12)
+ if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
+ return xehp_rcs_offsets;
+ else if (GRAPHICS_VER(engine->i915) >= 12)
return gen12_rcs_offsets;
else if (GRAPHICS_VER(engine->i915) >= 11)
return gen11_rcs_offsets;
@@ -522,7 +565,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs
*engine)
static int lrc_ring_mi_mode(const struct intel_engine_cs *engine)
{
- if (GRAPHICS_VER(engine->i915) >= 12)
+ if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
+ return 0x70;
+ else if (GRAPHICS_VER(engine->i915) >= 12)
return 0x60;
else if (GRAPHICS_VER(engine->i915) >= 9)
return 0x54;
@@ -534,7 +579,9 @@ static int lrc_ring_mi_mode(const struct intel_engine_cs
*engine)
static int lrc_ring_gpr0(const struct intel_engine_cs *engine)
{
- if (GRAPHICS_VER(engine->i915) >= 12)
+ if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
+ return 0x84;
+ else if (GRAPHICS_VER(engine->i915) >= 12)
return 0x74;
else if (GRAPHICS_VER(engine->i915) >= 9)
return 0x68;
@@ -578,10 +625,16 @@ static int lrc_ring_indirect_offset(const struct
intel_engine_cs *engine)
static int lrc_ring_cmd_buf_cctl(const struct intel_engine_cs *engine)
{
- if (engine->class != RENDER_CLASS)
- return -1;
- if (GRAPHICS_VER(engine->i915) >= 12)
+ if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
+ /*
+* Note that the CSFE context has a dummy slot for CMD_BUF_CCTL
+* simply to match the RCS context image layout.
+*/
+ return 0xc6;
+ else if (engine->class != RENDER_CLASS)
+ return -1;
+ else if (GRAPHICS_VER(engine->i915) >= 12)
return 0xb6;
else if (GRAPHICS_VER(engine->i915) >= 11)
return 0xaa;
--
2.25.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 18/18] drm/i915/dg2: DG2 has fixed memory bandwidth
DG2 doesn't have a SAGV or QGV points that determine memory bandwidth.
Instead it has a constant amount of memory bandwidth available to
display that does not need to be reduced based on the number of active
planes.
For simplicity, we'll just modify driver initialization to create a
single dummy QGV point with the proper amount of memory bandwidth,
rather than trying to query the pcode for this information.
Bspec: 64631
Signed-off-by: Matt Roper
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_bw.c | 24 +++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index 0d5d52548925..f554c1974072 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -273,6 +273,26 @@ static int icl_get_bw_info(struct drm_i915_private
*dev_priv, const struct intel
return 0;
}
+static void dg2_get_bw_info(struct drm_i915_private *i915)
+{
+ struct intel_bw_info *bi = >max_bw[0];
+
+ /*
+* DG2 doesn't have SAGV or QGV points, just a constant max bandwidth
+* that doesn't depend on the number of planes enabled. Create a
+* single dummy QGV point to reflect that. DG2-G10 platforms have a
+* constant 50 GB/s bandwidth, whereas DG2-G11 platforms have 38 GB/s.
+*/
+ bi->num_planes = 1;
+ bi->num_qgv_points = 1;
+ if (IS_DG2_G11(i915))
+ bi->deratedbw[0] = 38000;
+ else
+ bi->deratedbw[0] = 5;
+
+ i915->sagv_status = I915_SAGV_NOT_CONTROLLED;
+}
+
static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,
int num_planes, int qgv_point)
{
@@ -306,7 +326,9 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv))
return;
- if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv))
+ if (IS_DG2(dev_priv))
+ dg2_get_bw_info(dev_priv);
+ else if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv))
icl_get_bw_info(dev_priv, _sa_info);
else if (IS_ROCKETLAKE(dev_priv))
icl_get_bw_info(dev_priv, _sa_info);
--
2.25.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 14/18] drm/i915/dg2: Setup display outputs
DG2 has outputs on DDI A-D attached to what the bspec diagram shows as
"Combo PHY A-D." Note that despite being labelled "combo" the PHYs on
these outputs are Synopsys PHYs rather than traditional Intel combo PHY
technology.
Cc: Anusha Srivatsa
Signed-off-by: Matt Roper
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_display.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index a165bb8ca2f8..2b082e1827a8 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11333,7 +11333,12 @@ static void intel_setup_outputs(struct
drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv))
return;
- if (IS_ALDERLAKE_P(dev_priv)) {
+ if (IS_DG2(dev_priv)) {
+ intel_ddi_init(dev_priv, PORT_A);
+ intel_ddi_init(dev_priv, PORT_B);
+ intel_ddi_init(dev_priv, PORT_C);
+ intel_ddi_init(dev_priv, PORT_D_XELPD);
+ } else if (IS_ALDERLAKE_P(dev_priv)) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
intel_ddi_init(dev_priv, PORT_TC1);
--
2.25.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 17/18] drm/i915/dg2: Don't read DRAM info
DG2 does not use system DRAM information for BW_BUDDY programming or watermark workarounds, so there's no need to read this out at startup. Cc: Anusha Srivatsa Signed-off-by: Matt Roper Reviewed-by: Anusha Srivatsa --- drivers/gpu/drm/i915/intel_dram.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c index 879b0f007be3..9675bb94b70b 100644 --- a/drivers/gpu/drm/i915/intel_dram.c +++ b/drivers/gpu/drm/i915/intel_dram.c @@ -494,15 +494,15 @@ void intel_dram_detect(struct drm_i915_private *i915) struct dram_info *dram_info = >dram_info; int ret; + if (GRAPHICS_VER(i915) < 9 || IS_DG2(i915) || !HAS_DISPLAY(i915)) + return; + /* * Assume level 0 watermark latency adjustment is needed until proven * otherwise, this w/a is not needed by bxt/glk. */ dram_info->wm_lv_0_adjust_needed = !IS_GEN9_LP(i915); - if (GRAPHICS_VER(i915) < 9 || !HAS_DISPLAY(i915)) - return; - if (GRAPHICS_VER(i915) >= 12) ret = gen12_get_dram_info(i915); else if (GRAPHICS_VER(i915) >= 11) -- 2.25.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 07/18] drm/i915/selftests: Allow for larger engine counts
From: John Harrison
Increasing the engine count causes a couple of local array variables
to exceed the kernel stack limit. So make them dynamic allocations
instead.
Signed-off-by: John Harrison
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/selftest_execlists.c | 10 --
.../gpu/drm/i915/gt/selftest_workarounds.c| 32 ---
2 files changed, 29 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c
b/drivers/gpu/drm/i915/gt/selftest_execlists.c
index 73ddc6e14730..22a124b134b6 100644
--- a/drivers/gpu/drm/i915/gt/selftest_execlists.c
+++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c
@@ -3561,12 +3561,16 @@ static int smoke_crescendo(struct preempt_smoke *smoke,
unsigned int flags)
#define BATCH BIT(0)
{
struct task_struct *tsk[I915_NUM_ENGINES] = {};
- struct preempt_smoke arg[I915_NUM_ENGINES];
+ struct preempt_smoke *arg;
struct intel_engine_cs *engine;
enum intel_engine_id id;
unsigned long count;
int err = 0;
+ arg = kmalloc_array(I915_NUM_ENGINES, sizeof(*arg), GFP_KERNEL);
+ if (!arg)
+ return -ENOMEM;
+
for_each_engine(engine, smoke->gt, id) {
arg[id] = *smoke;
arg[id].engine = engine;
@@ -3574,7 +3578,7 @@ static int smoke_crescendo(struct preempt_smoke *smoke,
unsigned int flags)
arg[id].batch = NULL;
arg[id].count = 0;
- tsk[id] = kthread_run(smoke_crescendo_thread, ,
+ tsk[id] = kthread_run(smoke_crescendo_thread, arg,
"igt/smoke:%d", id);
if (IS_ERR(tsk[id])) {
err = PTR_ERR(tsk[id]);
@@ -3603,6 +3607,8 @@ static int smoke_crescendo(struct preempt_smoke *smoke,
unsigned int flags)
pr_info("Submitted %lu crescendo:%x requests across %d engines and %d
contexts\n",
count, flags, smoke->gt->info.num_engines, smoke->ncontext);
+
+ kfree(arg);
return 0;
}
diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
index 7ebc4edb8ecf..7a38ce40feb2 100644
--- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
@@ -1175,31 +1175,36 @@ live_gpu_reset_workarounds(void *arg)
{
struct intel_gt *gt = arg;
intel_wakeref_t wakeref;
- struct wa_lists lists;
+ struct wa_lists *lists;
bool ok;
if (!intel_has_gpu_reset(gt))
return 0;
+ lists = kzalloc(sizeof(*lists), GFP_KERNEL);
+ if (!lists)
+ return -ENOMEM;
+
pr_info("Verifying after GPU reset...\n");
igt_global_reset_lock(gt);
wakeref = intel_runtime_pm_get(gt->uncore->rpm);
- reference_lists_init(gt, );
+ reference_lists_init(gt, lists);
- ok = verify_wa_lists(gt, , "before reset");
+ ok = verify_wa_lists(gt, lists, "before reset");
if (!ok)
goto out;
intel_gt_reset(gt, ALL_ENGINES, "live_workarounds");
- ok = verify_wa_lists(gt, , "after reset");
+ ok = verify_wa_lists(gt, lists, "after reset");
out:
- reference_lists_fini(gt, );
+ reference_lists_fini(gt, lists);
intel_runtime_pm_put(gt->uncore->rpm, wakeref);
igt_global_reset_unlock(gt);
+ kfree(lists);
return ok ? 0 : -ESRCH;
}
@@ -1214,16 +1219,20 @@ live_engine_reset_workarounds(void *arg)
struct igt_spinner spin;
struct i915_request *rq;
intel_wakeref_t wakeref;
- struct wa_lists lists;
+ struct wa_lists *lists;
int ret = 0;
if (!intel_has_reset_engine(gt))
return 0;
+ lists = kzalloc(sizeof(*lists), GFP_KERNEL);
+ if (!lists)
+ return -ENOMEM;
+
igt_global_reset_lock(gt);
wakeref = intel_runtime_pm_get(gt->uncore->rpm);
- reference_lists_init(gt, );
+ reference_lists_init(gt, lists);
for_each_engine(engine, gt, id) {
bool ok;
@@ -1235,7 +1244,7 @@ live_engine_reset_workarounds(void *arg)
break;
}
- ok = verify_wa_lists(gt, , "before reset");
+ ok = verify_wa_lists(gt, lists, "before reset");
if (!ok) {
ret = -ESRCH;
goto err;
@@ -1247,7 +1256,7 @@ live_engine_reset_workarounds(void *arg)
goto err;
}
- ok = verify_wa_lists(gt, , "after idle reset");
+ ok = verify_wa_lists(gt, lists, "after idle reset");
if (!ok) {
ret = -ESRCH;
goto err;
@@ -1282,7 +1291,7 @@ live_engine_reset_workarounds(void *arg)
[Intel-gfx] [CI 05/18] drm/i915/xehp: VDBOX/VEBOX fusing registers are enable-based
From: Tvrtko Ursulin On Xe_HP the fusing register is renamed and changed to have the "enable" semantics, but otherwise remains compatible (mmio address, bitmask ranges) with older platforms. To simplify things we do not add a new register definition but just stop inverting the fusing masks before processing them. Bspec: 52615 Cc: Daniele Ceraolo Spurio Signed-off-by: Tvrtko Ursulin Signed-off-by: Matt Roper Reviewed-by: Lucas De Marchi Reviewed-by: Matt Atwood --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index d561573ed98c..5cfeb91d1b7b 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -468,7 +468,14 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt) if (GRAPHICS_VER(i915) < 11) return info->engine_mask; - media_fuse = ~intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE); + /* +* On newer platforms the fusing register is called 'enable' and has +* enable semantics, while on older platforms it is called 'disable' +* and bits have disable semantices. +*/ + media_fuse = intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE); + if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) + media_fuse = ~media_fuse; vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK; vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >> -- 2.25.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 04/18] drm/i915: Fork DG1 interrupt handler
From: Paulo Zanoni
The current interrupt handler is getting increasingly complicated and
Xe_HP changes will bring even more complexity. Let's split off a new
interrupt handler starting with DG1 (i.e., when the master tile
interrupt register was added to the design) and use that as the basis
for the new Xe_HP changes.
Now that we track the hardware IP's release number as well as the
version number, we can also properly define DG1 has version "12.10" and
replace the has_master_unit_irq feature flag with an IP version test.
Bspec: 50875
Cc: Daniele Spurio Ceraolo
Cc: Stuart Summers
Signed-off-by: Paulo Zanoni
Signed-off-by: Lucas De Marchi
Signed-off-by: Tomasz Lis
Signed-off-by: Matt Roper
Reviewed-by: Matt Atwood
---
drivers/gpu/drm/i915/i915_drv.h | 2 -
drivers/gpu/drm/i915/i915_irq.c | 139 +++
drivers/gpu/drm/i915/i915_pci.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 4 +-
drivers/gpu/drm/i915/intel_device_info.h | 1 -
5 files changed, 95 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7c446f958357..944f6806549f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1622,8 +1622,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_LOGICAL_RING_ELSQ(dev_priv) \
(INTEL_INFO(dev_priv)->has_logical_ring_elsq)
-#define HAS_MASTER_UNIT_IRQ(dev_priv)
(INTEL_INFO(dev_priv)->has_master_unit_irq)
-
#define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
#define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 1d4c683c9de9..61dceb2a17c1 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2698,11 +2698,9 @@ gen11_display_irq_handler(struct drm_i915_private *i915)
enable_rpm_wakeref_asserts(>runtime_pm);
}
-static __always_inline irqreturn_t
-__gen11_irq_handler(struct drm_i915_private * const i915,
- u32 (*intr_disable)(void __iomem * const regs),
- void (*intr_enable)(void __iomem * const regs))
+static irqreturn_t gen11_irq_handler(int irq, void *arg)
{
+ struct drm_i915_private *i915 = arg;
void __iomem * const regs = i915->uncore.regs;
struct intel_gt *gt = >gt;
u32 master_ctl;
@@ -2711,9 +2709,9 @@ __gen11_irq_handler(struct drm_i915_private * const i915,
if (!intel_irqs_enabled(i915))
return IRQ_NONE;
- master_ctl = intr_disable(regs);
+ master_ctl = gen11_master_intr_disable(regs);
if (!master_ctl) {
- intr_enable(regs);
+ gen11_master_intr_enable(regs);
return IRQ_NONE;
}
@@ -2726,7 +2724,7 @@ __gen11_irq_handler(struct drm_i915_private * const i915,
gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
- intr_enable(regs);
+ gen11_master_intr_enable(regs);
gen11_gu_misc_irq_handler(gt, gu_misc_iir);
@@ -2735,51 +2733,69 @@ __gen11_irq_handler(struct drm_i915_private * const
i915,
return IRQ_HANDLED;
}
-static irqreturn_t gen11_irq_handler(int irq, void *arg)
-{
- return __gen11_irq_handler(arg,
- gen11_master_intr_disable,
- gen11_master_intr_enable);
-}
-
-static u32 dg1_master_intr_disable_and_ack(void __iomem * const regs)
+static inline u32 dg1_master_intr_disable(void __iomem * const regs)
{
u32 val;
/* First disable interrupts */
- raw_reg_write(regs, DG1_MSTR_UNIT_INTR, 0);
+ raw_reg_write(regs, DG1_MSTR_TILE_INTR, 0);
/* Get the indication levels and ack the master unit */
- val = raw_reg_read(regs, DG1_MSTR_UNIT_INTR);
+ val = raw_reg_read(regs, DG1_MSTR_TILE_INTR);
if (unlikely(!val))
return 0;
- raw_reg_write(regs, DG1_MSTR_UNIT_INTR, val);
-
- /*
-* Now with master disabled, get a sample of level indications
-* for this interrupt and ack them right away - we keep GEN11_MASTER_IRQ
-* out as this bit doesn't exist anymore for DG1
-*/
- val = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ) & ~GEN11_MASTER_IRQ;
- if (unlikely(!val))
- return 0;
-
- raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, val);
+ raw_reg_write(regs, DG1_MSTR_TILE_INTR, val);
return val;
}
static inline void dg1_master_intr_enable(void __iomem * const regs)
{
- raw_reg_write(regs, DG1_MSTR_UNIT_INTR, DG1_MSTR_IRQ);
+ raw_reg_write(regs, DG1_MSTR_TILE_INTR, DG1_MSTR_IRQ);
}
static irqreturn_t dg1_irq_handler(int irq, void *arg)
{
- return __gen11_irq_handler(arg,
- dg1_master_intr_disable_and_ack,
- dg1_master_intr_enable);
+ struct
[Intel-gfx] [CI 03/18] drm/i915/dg2: add DG2 platform info
DG2 has Xe_LPD display (version 13) and Xe_HPG (version 12.55) graphics.
There are two variants (treated as subplatforms in the code): DG2-G10
and DG2-G11 that require independent programming in some areas (e.g.,
workarounds).
Bspec: 44472, 44474, 46197, 48028, 48077
Cc: Anusha Srivatsa
Signed-off-by: Matt Roper
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.h | 27
drivers/gpu/drm/i915/i915_pci.c | 16 ++
drivers/gpu/drm/i915/intel_device_info.c | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 5 +
drivers/gpu/drm/i915/intel_step.c| 20 +-
5 files changed, 68 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 310f272a005f..7c446f958357 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1445,6 +1445,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
#define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P)
#define IS_XEHPSDV(dev_priv) IS_PLATFORM(dev_priv, INTEL_XEHPSDV)
+#define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG2)
+#define IS_DG2_G10(dev_priv) \
+ IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
+#define IS_DG2_G11(dev_priv) \
+ IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev_priv) \
@@ -1558,6 +1563,28 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_XEHPSDV_GT_STEP(p, since, until) \
(IS_XEHPSDV(p) && IS_GT_STEP(__i915, since, until))
+/*
+ * DG2 hardware steppings are a bit unusual. The hardware design was forked
+ * to create two variants (G10 and G11) which have distinct workaround sets.
+ * The G11 fork of the DG2 design resets the GT stepping back to "A0" for its
+ * first iteration, even though it's more similar to a G10 B0 stepping in terms
+ * of functionality and workarounds. However the display stepping does not
+ * reset in the same manner --- a specific stepping like "B0" has a consistent
+ * meaning regardless of whether it belongs to a G10 or G11 DG2.
+ *
+ * TLDR: All GT workarounds and stepping-specific logic must be applied in
+ * relation to a specific subplatform (G10 or G11), whereas display workarounds
+ * and stepping-specific logic will be applied with a general DG2-wide stepping
+ * number.
+ */
+#define IS_DG2_GT_STEP(__i915, variant, since, until) \
+ (IS_SUBPLATFORM(__i915, INTEL_DG2, INTEL_SUBPLATFORM_##variant) && \
+IS_GT_STEP(__i915, since, until))
+
+#define IS_DG2_DISP_STEP(__i915, since, until) \
+ (IS_DG2(__i915) && \
+IS_DISPLAY_STEP(__i915, since, until))
+
#define IS_LP(dev_priv)(INTEL_INFO(dev_priv)->is_lp)
#define IS_GEN9_LP(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && IS_LP(dev_priv))
#define IS_GEN9_BC(dev_priv) (GRAPHICS_VER(dev_priv) == 9 &&
!IS_LP(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 330b98396c7b..ec3f576f4247 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1038,6 +1038,22 @@ static const struct intel_device_info xehpsdv_info = {
.require_force_probe = 1,
};
+__maybe_unused
+static const struct intel_device_info dg2_info = {
+ XE_HP_FEATURES,
+ XE_HPM_FEATURES,
+ XE_LPD_FEATURES,
+ DGFX_FEATURES,
+ .graphics_rel = 55,
+ .media_rel = 55,
+ PLATFORM(INTEL_DG2),
+ .platform_engine_mask =
+ BIT(RCS0) | BIT(BCS0) |
+ BIT(VECS0) | BIT(VECS1) |
+ BIT(VCS0) | BIT(VCS2),
+ .require_force_probe = 1,
+};
+
#undef PLATFORM
/*
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index 71d679ea5779..d5cf5977938a 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -69,6 +69,7 @@ static const char * const platform_names[] = {
PLATFORM_NAME(ALDERLAKE_S),
PLATFORM_NAME(ALDERLAKE_P),
PLATFORM_NAME(XEHPSDV),
+ PLATFORM_NAME(DG2),
};
#undef PLATFORM_NAME
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 5db585b78cc7..c09f2dd24617 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -89,6 +89,7 @@ enum intel_platform {
INTEL_ALDERLAKE_S,
INTEL_ALDERLAKE_P,
INTEL_XEHPSDV,
+ INTEL_DG2,
INTEL_MAX_PLATFORMS
};
@@ -107,6 +108,10 @@ enum intel_platform {
/* CNL/ICL */
#define INTEL_SUBPLATFORM_PORTF(0)
+/* DG2 */
+#define INTEL_SUBPLATFORM_G10 0
+#define INTEL_SUBPLATFORM_G11 1
+
enum
[Intel-gfx] [CI 06/18] drm/i915/gen12: Use fuse info to enable SFC
From: Venkata Sandeep Dhanalakota
In Gen12 there are various fuse combinations and in each configuration
vdbox engine may be connected to SFC depending on which engines are
available, so we need to set the SFC capability based on fuse value from
the hardware. Even numbered physical instance always have SFC, odd
numbered physical instances have SFC only if previous even instance is
fused off.
v2:
- Minor style & typo fixes (Tvrtko)
- Drop an unwanted 'inline' (Tvrtko)
Bspec: 48028
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
Signed-off-by: Venkata Sandeep Dhanalakota
Signed-off-by: Matt Roper
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 30 ++-
1 file changed, 24 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 5cfeb91d1b7b..3f8013612a08 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -442,6 +442,28 @@ void intel_engines_free(struct intel_gt *gt)
}
}
+static
+bool gen11_vdbox_has_sfc(struct drm_i915_private *i915,
+unsigned int physical_vdbox,
+unsigned int logical_vdbox, u16 vdbox_mask)
+{
+ /*
+* In Gen11, only even numbered logical VDBOXes are hooked
+* up to an SFC (Scaler & Format Converter) unit.
+* In Gen12, Even numbered physical instance always are connected
+* to an SFC. Odd numbered physical instances have SFC only if
+* previous even instance is fused off.
+*/
+ if (GRAPHICS_VER(i915) == 12)
+ return (physical_vdbox % 2 == 0) ||
+ !(BIT(physical_vdbox - 1) & vdbox_mask);
+ else if (GRAPHICS_VER(i915) == 11)
+ return logical_vdbox % 2 == 0;
+
+ MISSING_CASE(GRAPHICS_VER(i915));
+ return false;
+}
+
/*
* Determine which engines are fused off in our particular hardware.
* Note that we have a catch-22 situation where we need to be able to access
@@ -493,13 +515,9 @@ static intel_engine_mask_t init_engine_mask(struct
intel_gt *gt)
continue;
}
- /*
-* In Gen11, only even numbered logical VDBOXes are
-* hooked up to an SFC (Scaler & Format Converter) unit.
-* In TGL each VDBOX has access to an SFC.
-*/
- if (GRAPHICS_VER(i915) >= 12 || logical_vdbox++ % 2 == 0)
+ if (gen11_vdbox_has_sfc(i915, i, logical_vdbox, vdbox_mask))
gt->info.vdbox_sfc_access |= BIT(i);
+ logical_vdbox++;
}
drm_dbg(>drm, "vdbox enable: %04x, instances: %04lx\n",
vdbox_mask, VDBOX_MASK(gt));
--
2.25.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 02/18] drm/i915/xehpsdv: add initial XeHP SDV definitions
From: Lucas De Marchi
XeHP SDV is a Intel® dGPU without display. This is just the definition
of some basic platform macros, by large a copy of current state of
Tigerlake which does not reflect the end state of this platform.
v2:
- Switch to intel_step infrastructure for stepping matches. (Jani)
v3:
- Bring earlier in patch series and leave addition of new media engines
to the engine mask for a later patch.
Bspec: 44467, 48077
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: José Roberto de Souza
Signed-off-by: Stuart Summers
Signed-off-by: Tomas Winkler
Signed-off-by: Matt Roper
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.h | 4
drivers/gpu/drm/i915/i915_pci.c | 19 +++
drivers/gpu/drm/i915/intel_device_info.c | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/intel_step.c| 12 +++-
5 files changed, 36 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0321a1f9738d..310f272a005f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1444,6 +1444,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_DG1(dev_priv)IS_PLATFORM(dev_priv, INTEL_DG1)
#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
#define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P)
+#define IS_XEHPSDV(dev_priv) IS_PLATFORM(dev_priv, INTEL_XEHPSDV)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev_priv) \
@@ -1554,6 +1555,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
(IS_ALDERLAKE_P(__i915) && \
IS_GT_STEP(__i915, since, until))
+#define IS_XEHPSDV_GT_STEP(p, since, until) \
+ (IS_XEHPSDV(p) && IS_GT_STEP(__i915, since, until))
+
#define IS_LP(dev_priv)(INTEL_INFO(dev_priv)->is_lp)
#define IS_GEN9_LP(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && IS_LP(dev_priv))
#define IS_GEN9_BC(dev_priv) (GRAPHICS_VER(dev_priv) == 9 &&
!IS_LP(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index be5ee5e0e324..330b98396c7b 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1019,6 +1019,25 @@ static const struct intel_device_info adl_p_info = {
.ppgtt_size = 48, \
.ppgtt_type = INTEL_PPGTT_FULL
+#define XE_HPM_FEATURES \
+ .media_ver = 12, \
+ .media_rel = 50
+
+__maybe_unused
+static const struct intel_device_info xehpsdv_info = {
+ XE_HP_FEATURES,
+ XE_HPM_FEATURES,
+ DGFX_FEATURES,
+ PLATFORM(INTEL_XEHPSDV),
+ .display = { },
+ .pipe_mask = 0,
+ .platform_engine_mask =
+ BIT(RCS0) | BIT(BCS0) |
+ BIT(VECS0) | BIT(VECS1) |
+ BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3),
+ .require_force_probe = 1,
+};
+
#undef PLATFORM
/*
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index 5c83b2ec69da..71d679ea5779 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -68,6 +68,7 @@ static const char * const platform_names[] = {
PLATFORM_NAME(DG1),
PLATFORM_NAME(ALDERLAKE_S),
PLATFORM_NAME(ALDERLAKE_P),
+ PLATFORM_NAME(XEHPSDV),
};
#undef PLATFORM_NAME
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index bd83004c78b6..5db585b78cc7 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -88,6 +88,7 @@ enum intel_platform {
INTEL_DG1,
INTEL_ALDERLAKE_S,
INTEL_ALDERLAKE_P,
+ INTEL_XEHPSDV,
INTEL_MAX_PLATFORMS
};
diff --git a/drivers/gpu/drm/i915/intel_step.c
b/drivers/gpu/drm/i915/intel_step.c
index 9fcf17708cc8..b99829bcb4f7 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -101,6 +101,13 @@ static const struct intel_step_info adlp_revids[] = {
[0xC] = { .gt_step = STEP_C0, .display_step = STEP_D0 },
};
+static const struct intel_step_info xehpsdv_revids[] = {
+ [0x0] = { .gt_step = STEP_A0 },
+ [0x1] = { .gt_step = STEP_A1 },
+ [0x4] = { .gt_step = STEP_B0 },
+ [0x8] = { .gt_step = STEP_C0 },
+};
+
void intel_step_init(struct drm_i915_private *i915)
{
const struct intel_step_info *revids = NULL;
@@ -108,7 +115,10 @@ void intel_step_init(struct drm_i915_private *i915)
int revid = INTEL_REVID(i915);
struct intel_step_info step = {};
- if (IS_ALDERLAKE_P(i915)) {
+ if (IS_XEHPSDV(i915)) {
+ revids = xehpsdv_revids;
+ size = ARRAY_SIZE(xehpsdv_revids);
+
[Intel-gfx] [CI 00/18] CI pass for reviewed Xe_HP SDV and DG2 patches
We have enough reviews that we can start applying some of these patches; let's kick off another CI run for the reviewed patches that don't have dependencies on other unreviewed patches. The plan is to apply the first couple patches (which have the definitions like IS_XEHPSDV and IS_DG2) to a topic branch that gets merged to both intel-next and gt-next. Then the rest of the patches should be able to be applied to whichever branch is appropriate after that. John Harrison (1): drm/i915/selftests: Allow for larger engine counts Lucas De Marchi (2): drm/i915: Add XE_HP initial definitions drm/i915/xehpsdv: add initial XeHP SDV definitions Matt Roper (10): drm/i915/dg2: add DG2 platform info drm/i915/dg2: Add fake PCH drm/i915/dg2: Add cdclk table and reference clock drm/i915/dg2: Skip shared DPLL handling drm/i915/dg2: Don't wait for AUX power well enable ACKs drm/i915/dg2: Setup display outputs drm/i915/dg2: Add dbuf programming drm/i915/dg2: Don't program BW_BUDDY registers drm/i915/dg2: Don't read DRAM info drm/i915/dg2: DG2 has fixed memory bandwidth Paulo Zanoni (1): drm/i915: Fork DG1 interrupt handler Prathap Kumar Valsan (1): drm/i915/xehp: New engine context offsets Stuart Summers (1): drm/i915/xehp: Handle new device context ID format Tvrtko Ursulin (1): drm/i915/xehp: VDBOX/VEBOX fusing registers are enable-based Venkata Sandeep Dhanalakota (1): drm/i915/gen12: Use fuse info to enable SFC drivers/gpu/drm/i915/display/intel_bw.c | 24 ++- drivers/gpu/drm/i915/display/intel_cdclk.c| 22 ++- drivers/gpu/drm/i915/display/intel_display.c | 17 ++- .../drm/i915/display/intel_display_power.c| 20 +++ .../drm/i915/display/intel_display_power.h| 10 ++ drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 5 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 39 - .../drm/i915/gt/intel_execlists_submission.c | 74 +++-- drivers/gpu/drm/i915/gt/intel_lrc.c | 73 - drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 2 + drivers/gpu/drm/i915/gt/selftest_execlists.c | 10 +- .../gpu/drm/i915/gt/selftest_workarounds.c| 32 ++-- drivers/gpu/drm/i915/i915_drv.h | 33 +++- drivers/gpu/drm/i915/i915_irq.c | 141 -- drivers/gpu/drm/i915/i915_pci.c | 61 +++- drivers/gpu/drm/i915/i915_perf.c | 29 ++-- drivers/gpu/drm/i915/i915_reg.h | 9 +- drivers/gpu/drm/i915/intel_device_info.c | 2 + drivers/gpu/drm/i915/intel_device_info.h | 7 +- drivers/gpu/drm/i915/intel_dram.c | 6 +- drivers/gpu/drm/i915/intel_pch.c | 3 + drivers/gpu/drm/i915/intel_pch.h | 2 + drivers/gpu/drm/i915/intel_pm.c | 120 ++- drivers/gpu/drm/i915/intel_step.c | 30 +++- 24 files changed, 657 insertions(+), 114 deletions(-) -- 2.25.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/4] drm/i915/step: Add macro magic for handling steps
== Series Details == Series: series starting with [CI,1/4] drm/i915/step: Add macro magic for handling steps URL : https://patchwork.freedesktop.org/series/92849/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_display.c:1896:21:expected struct i915_vma *[assigned] vma +drivers/gpu/drm/i915/display/intel_display.c:1896:21:got void [noderef] __iomem *[assigned] iomem +drivers/gpu/drm/i915/display/intel_display.c:1896:21: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gem/i915_gem_context.c:1412:34:expected struct i915_address_space *vm +drivers/gpu/drm/i915/gem/i915_gem_context.c:1412:34:got struct i915_address_space [noderef] __rcu *vm +drivers/gpu/drm/i915/gem/i915_gem_context.c:1412:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25:expected struct i915_address_space [noderef] __rcu *vm +drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25:got struct i915_address_space * +drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34:expected struct i915_address_space *vm +drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34:got struct i915_address_space [noderef] __rcu *vm +drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1396:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/intel_ring_submission.c:1210:24: warning: Using plain integer as NULL pointer +drivers/gpu/drm/i915/i915_perf.c:1434:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1488:15: warning: memset with byte count of 16777216 +./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080) +./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080) +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/4] drm/i915/step: Add macro magic for handling steps
== Series Details == Series: series starting with [CI,1/4] drm/i915/step: Add macro magic for handling steps URL : https://patchwork.freedesktop.org/series/92849/ State : warning == Summary == $ dim checkpatch origin/drm-tip c0b839cec037 drm/i915/step: Add macro magic for handling steps -:24: ERROR:MULTISTATEMENT_MACRO_USE_DO_WHILE: Macros with multiple statements should be enclosed in a do - while loop #24: FILE: drivers/gpu/drm/i915/intel_step.c:186: +#define STEP_NAME_CASE(name) \ + case STEP_##name: \ + return #name; -:24: WARNING:TRAILING_SEMICOLON: macros should not use a trailing semicolon #24: FILE: drivers/gpu/drm/i915/intel_step.c:186: +#define STEP_NAME_CASE(name) \ + case STEP_##name: \ + return #name; -:47: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #47: FILE: drivers/gpu/drm/i915/intel_step.h:20: +#define STEP_NAME_LIST(func) \ + func(A0)\ + func(A1)\ + func(A2)\ + func(B0)\ + func(B1)\ + func(B2)\ + func(C0)\ + func(C1)\ + func(D0)\ + func(D1)\ + func(E0)\ + func(F0)\ + func(G0)\ + func(H0)\ + func(I0)\ + func(I1)\ + func(J0) -:47: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'func' - possible side-effects? #47: FILE: drivers/gpu/drm/i915/intel_step.h:20: +#define STEP_NAME_LIST(func) \ + func(A0)\ + func(A1)\ + func(A2)\ + func(B0)\ + func(B1)\ + func(B2)\ + func(C0)\ + func(C1)\ + func(D0)\ + func(D1)\ + func(E0)\ + func(F0)\ + func(G0)\ + func(H0)\ + func(I0)\ + func(I1)\ + func(J0) total: 2 errors, 1 warnings, 1 checks, 71 lines checked ef7c2d172b12 drm/i915/dmc: Change intel_get_stepping_info() 4a8d375d3242 drm/i915/firmware: Update to DMC v2.12 on TGL -:10: ERROR:BAD_SIGN_OFF: Unrecognized email address: 'Madhumitha Pradeep <' #10: Reviewed-by: Madhumitha Pradeep < total: 1 errors, 0 warnings, 0 checks, 10 lines checked 55698bd418a0 drm/i915/firmware: Update to DMC v2.03 on RKL -:12: ERROR:BAD_SIGN_OFF: Unrecognized email address: 'Madhumitha Pradeep <' #12: Reviewed-by: Madhumitha Pradeep < total: 1 errors, 0 warnings, 0 checks, 10 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for Series to merge a subset of GuC submission (rev2)
== Series Details ==
Series: Series to merge a subset of GuC submission (rev2)
URL : https://patchwork.freedesktop.org/series/92791/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10367 -> Patchwork_20670
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20670/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_20670:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@dmabuf:
- {fi-tgl-dsi}: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/fi-tgl-dsi/igt@i915_selftest@l...@dmabuf.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20670/fi-tgl-dsi/igt@i915_selftest@l...@dmabuf.html
Known issues
Here are the changes found in Patchwork_20670 that come from known issues:
### IGT changes ###
Possible fixes
* igt@gem_exec_suspend@basic-s0:
- {fi-tgl-1115g4}:[FAIL][3] ([i915#1888]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20670/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s0.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7500u: [DMESG-FAIL][5] ([i915#165]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20670/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [FAIL][7] ([i915#1372]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20670/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#2966]: https://gitlab.freedesktop.org/drm/intel/issues/2966
Participating hosts (38 -> 34)
--
Missing(4): fi-kbl-soraka fi-ilk-m540 fi-bdw-samus fi-hsw-4200u
Build changes
-
* Linux: CI_DRM_10367 -> Patchwork_20670
CI-20190529: 20190529
CI_DRM_10367: 598494d0149b67545593dfb1b5fa60278907749e @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6146: 6caef22e4aafed275771f564d4ea4cab09896ebc @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20670: 61b81bfe2ddee11be2e8fd22f84ba4e548a90d77 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
61b81bfe2dde drm/i915: Add intel_context tracing
37a4e4eb390b drm/i915/guc: Add trace point for GuC submit
752e0551e1d6 drm/i915/guc: Update GuC debugfs to support new GuC
af704c4a01b5 drm/i915/guc: Update intel_gt_wait_for_idle to work with GuC
0c70454fb944 drm/i915/guc: Ensure G2H response has space in buffer
48900c02cbf4 drm/i915/guc: Disable semaphores when using GuC scheduling
a2e1e262476d drm/i915/guc: Ensure request ordering via completion fences
b7c5a26b4acb drm/i915: Disable preempt busywait when using GuC scheduling
9786ce9beec1 drm/i915/guc: Extend deregistration fence to schedule disable
68b4749ad89a drm/i915/guc: Disable engine barriers with GuC during unpin
2a7cea557692 drm/i915/guc: Defer context unpin until scheduling is disabled
ac2069bdddf5 drm/i915/guc: Insert fence on context when deregistering
ba27aaa2fae5 drm/i915/guc: Implement GuC context operations for new inteface
0d92798721fc drm/i915/guc: Add bypass tasklet submission path to GuC
c9e9768ec25b drm/i915/guc: Implement GuC submission tasklet
7b76cda1c85a drm/i915/guc: Add LRC descriptor context lookup array
87421139cc96 drm/i915/guc: Remove GuC stage descriptor, add LRC descriptor
081c22c811d7 drm/i915/guc: Add new GuC interface defines and structures
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20670/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/bios: Fix ports mask
PORT_A to PORT_F are regular integers defined in the enum port,
while for_each_port_masked requires a bit mask for the ports.
Current given mask: 0b111
Desired mask: 0b11
I noticed this while Christoph was reporting a bug found on headless
GVT configuration which bisect blamed commit 3ae04c0c7e63 ("drm/i915/bios:
limit default outputs to ports A through F")
Cc: Christoph Hellwig
Fixes: 3ae04c0c7e63 ("drm/i915/bios: limit default outputs to ports A through
F")
Cc: Lucas De Marchi
Cc: Ville Syrjälä
Cc: Jani Nikula
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/display/intel_bios.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 5b6922e28ef2..8bbeb5978bf7 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2166,7 +2166,8 @@ static void
init_vbt_missing_defaults(struct drm_i915_private *i915)
{
enum port port;
- int ports = PORT_A | PORT_B | PORT_C | PORT_D | PORT_E | PORT_F;
+ int ports = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | \
+ BIT(PORT_D) | BIT(PORT_E) | BIT(PORT_F);
if (!HAS_DDI(i915) && !IS_CHERRYVIEW(i915))
return;
--
2.31.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Series to merge a subset of GuC submission (rev2)
== Series Details == Series: Series to merge a subset of GuC submission (rev2) URL : https://patchwork.freedesktop.org/series/92791/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +drivers/gpu/drm/i915/gt/intel_reset.c:1396:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/intel_ring_submission.c:1210:24: warning: Using plain integer as NULL pointer +drivers/gpu/drm/i915/i915_perf.c:1434:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1488:15: warning: memset with byte count of 16777216 +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined +/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined +/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined +/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined +/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined +/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined +/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined +/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined +/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined +/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined +/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined +/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined +/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined +/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined +/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined +/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined +/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined +/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined +/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined +/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined +/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined +/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Series to merge a subset of GuC submission (rev2)
== Series Details ==
Series: Series to merge a subset of GuC submission (rev2)
URL : https://patchwork.freedesktop.org/series/92791/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
081c22c811d7 drm/i915/guc: Add new GuC interface defines and structures
87421139cc96 drm/i915/guc: Remove GuC stage descriptor, add LRC descriptor
7b76cda1c85a drm/i915/guc: Add LRC descriptor context lookup array
c9e9768ec25b drm/i915/guc: Implement GuC submission tasklet
0d92798721fc drm/i915/guc: Add bypass tasklet submission path to GuC
ba27aaa2fae5 drm/i915/guc: Implement GuC context operations for new inteface
-:150: ERROR:IN_ATOMIC: do not use in_atomic in drivers
#150: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc.h:120:
+ bool not_atomic = !in_atomic() && !irqs_disabled();
total: 1 errors, 0 warnings, 0 checks, 912 lines checked
ac2069bdddf5 drm/i915/guc: Insert fence on context when deregistering
2a7cea557692 drm/i915/guc: Defer context unpin until scheduling is disabled
68b4749ad89a drm/i915/guc: Disable engine barriers with GuC during unpin
9786ce9beec1 drm/i915/guc: Extend deregistration fence to schedule disable
b7c5a26b4acb drm/i915: Disable preempt busywait when using GuC scheduling
a2e1e262476d drm/i915/guc: Ensure request ordering via completion fences
48900c02cbf4 drm/i915/guc: Disable semaphores when using GuC scheduling
0c70454fb944 drm/i915/guc: Ensure G2H response has space in buffer
af704c4a01b5 drm/i915/guc: Update intel_gt_wait_for_idle to work with GuC
752e0551e1d6 drm/i915/guc: Update GuC debugfs to support new GuC
37a4e4eb390b drm/i915/guc: Add trace point for GuC submit
61b81bfe2dde drm/i915: Add intel_context tracing
-:145: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#145: FILE: drivers/gpu/drm/i915/i915_trace.h:902:
+ TP_STRUCT__entry(
-:152: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#152: FILE: drivers/gpu/drm/i915/i915_trace.h:909:
+ TP_fast_assign(
total: 0 errors, 0 warnings, 2 checks, 255 lines checked
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 2/4] drm/i915/dmc: Change intel_get_stepping_info()
Lets use RUNTIME_INFO->step since all platforms now have their
stepping info in intel_step.c. This makes intel_get_stepping_info()
a lot simpler.
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dmc.c | 50
1 file changed, 8 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index f8789d4543bf..1f6c32932331 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -247,50 +247,15 @@ bool intel_dmc_has_payload(struct drm_i915_private *i915)
return i915->dmc.dmc_info[DMC_FW_MAIN].payload;
}
-static const struct stepping_info skl_stepping_info[] = {
- {'A', '0'}, {'B', '0'}, {'C', '0'},
- {'D', '0'}, {'E', '0'}, {'F', '0'},
- {'G', '0'}, {'H', '0'}, {'I', '0'},
- {'J', '0'}, {'K', '0'}
-};
-
-static const struct stepping_info bxt_stepping_info[] = {
- {'A', '0'}, {'A', '1'}, {'A', '2'},
- {'B', '0'}, {'B', '1'}, {'B', '2'}
-};
-
-static const struct stepping_info icl_stepping_info[] = {
- {'A', '0'}, {'A', '1'}, {'A', '2'},
- {'B', '0'}, {'B', '2'},
- {'C', '0'}
-};
-
-static const struct stepping_info no_stepping_info = { '*', '*' };
-
static const struct stepping_info *
-intel_get_stepping_info(struct drm_i915_private *dev_priv)
+intel_get_stepping_info(struct drm_i915_private *i915,
+ struct stepping_info *si)
{
- const struct stepping_info *si;
- unsigned int size;
-
- if (IS_ICELAKE(dev_priv)) {
- size = ARRAY_SIZE(icl_stepping_info);
- si = icl_stepping_info;
- } else if (IS_SKYLAKE(dev_priv)) {
- size = ARRAY_SIZE(skl_stepping_info);
- si = skl_stepping_info;
- } else if (IS_BROXTON(dev_priv)) {
- size = ARRAY_SIZE(bxt_stepping_info);
- si = bxt_stepping_info;
- } else {
- size = 0;
- si = NULL;
- }
-
- if (INTEL_REVID(dev_priv) < size)
- return si + INTEL_REVID(dev_priv);
+ const char *step_name =
intel_step_name(RUNTIME_INFO(i915)->step.display_step);
- return _stepping_info;
+ si->stepping = step_name[0];
+ si->substepping = step_name[1];
+ return si;
}
static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
@@ -616,7 +581,8 @@ static void parse_dmc_fw(struct drm_i915_private *dev_priv,
struct intel_package_header *package_header;
struct intel_dmc_header_base *dmc_header;
struct intel_dmc *dmc = _priv->dmc;
- const struct stepping_info *si = intel_get_stepping_info(dev_priv);
+ struct stepping_info display_info = { '*', '*'};
+ const struct stepping_info *si = intel_get_stepping_info(dev_priv,
_info);
u32 readcount = 0;
u32 r, offset;
int id;
--
2.32.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 4/4] drm/i915/firmware: Update to DMC v2.03 on RKL
Add support to load latest DMC version. The Release Notes mentions that this version fixes timeout issues. Cc: Madhumitha Pradeep Signed-off-by: Anusha Srivatsa Reviewed-by: Madhumitha Pradeep < --- drivers/gpu/drm/i915/display/intel_dmc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c index 50093e7b088a..9895fd957df9 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -57,8 +57,8 @@ MODULE_FIRMWARE(ADLS_DMC_PATH); #define DG1_DMC_VERSION_REQUIRED DMC_VERSION(2, 2) MODULE_FIRMWARE(DG1_DMC_PATH); -#define RKL_DMC_PATH DMC_PATH(rkl, 2, 02) -#define RKL_DMC_VERSION_REQUIRED DMC_VERSION(2, 2) +#define RKL_DMC_PATH DMC_PATH(rkl, 2, 03) +#define RKL_DMC_VERSION_REQUIRED DMC_VERSION(2, 3) MODULE_FIRMWARE(RKL_DMC_PATH); #define TGL_DMC_PATH DMC_PATH(tgl, 2, 12) -- 2.32.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 3/4] drm/i915/firmware: Update to DMC v2.12 on TGL
Add support to the latest DMC firmware. Cc: Madhunitha Pradeep Signed-off-by: Anusha Srivatsa Reviewed-by: Madhumitha Pradeep < --- drivers/gpu/drm/i915/display/intel_dmc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c index 1f6c32932331..50093e7b088a 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -61,8 +61,8 @@ MODULE_FIRMWARE(DG1_DMC_PATH); #define RKL_DMC_VERSION_REQUIRED DMC_VERSION(2, 2) MODULE_FIRMWARE(RKL_DMC_PATH); -#define TGL_DMC_PATH DMC_PATH(tgl, 2, 08) -#define TGL_DMC_VERSION_REQUIRED DMC_VERSION(2, 8) +#define TGL_DMC_PATH DMC_PATH(tgl, 2, 12) +#define TGL_DMC_VERSION_REQUIRED DMC_VERSION(2, 12) MODULE_FIRMWARE(TGL_DMC_PATH); #define ICL_DMC_PATH DMC_PATH(icl, 1, 09) -- 2.32.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 1/4] drm/i915/step: Add macro magic for handling steps
With the addition of stepping info for
all platforms, lets use macros for handling them
and autogenerating code for all steps at a time.
Suggested-by: Matt Roper
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_step.c | 14
drivers/gpu/drm/i915/intel_step.h | 38 +++
2 files changed, 37 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_step.c
b/drivers/gpu/drm/i915/intel_step.c
index 9fcf17708cc8..e9ec111d6232 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -182,3 +182,17 @@ void intel_step_init(struct drm_i915_private *i915)
RUNTIME_INFO(i915)->step = step;
}
+
+#define STEP_NAME_CASE(name) \
+ case STEP_##name: \
+ return #name;
+
+const char *intel_step_name(enum intel_step step)
+{
+ switch (step) {
+ STEP_NAME_LIST(STEP_NAME_CASE);
+
+ default:
+ return "**";
+ }
+}
diff --git a/drivers/gpu/drm/i915/intel_step.h
b/drivers/gpu/drm/i915/intel_step.h
index 41567d9b7c35..f6641e2a3c77 100644
--- a/drivers/gpu/drm/i915/intel_step.h
+++ b/drivers/gpu/drm/i915/intel_step.h
@@ -15,31 +15,39 @@ struct intel_step_info {
u8 display_step;
};
+#define STEP_ENUM_VAL(name) STEP_##name,
+
+#define STEP_NAME_LIST(func) \
+ func(A0)\
+ func(A1)\
+ func(A2)\
+ func(B0)\
+ func(B1)\
+ func(B2)\
+ func(C0)\
+ func(C1)\
+ func(D0)\
+ func(D1)\
+ func(E0)\
+ func(F0)\
+ func(G0)\
+ func(H0)\
+ func(I0)\
+ func(I1)\
+ func(J0)
+
/*
* Symbolic steppings that do not match the hardware. These are valid both as
gt
* and display steppings as symbolic names.
*/
enum intel_step {
STEP_NONE = 0,
- STEP_A0,
- STEP_A1,
- STEP_A2,
- STEP_B0,
- STEP_B1,
- STEP_C0,
- STEP_D0,
- STEP_D1,
- STEP_E0,
- STEP_F0,
- STEP_G0,
- STEP_H0,
- STEP_I0,
- STEP_I1,
- STEP_J0,
+ STEP_NAME_LIST(STEP_ENUM_VAL)
STEP_FUTURE,
STEP_FOREVER,
};
void intel_step_init(struct drm_i915_private *i915);
+const char *intel_step_name(enum intel_step step);
#endif /* __INTEL_STEP_H__ */
--
2.32.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Migrate memory to SMEM when imported cross-device (rev3)
== Series Details ==
Series: drm/i915: Migrate memory to SMEM when imported cross-device (rev3)
URL : https://patchwork.freedesktop.org/series/92617/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10367 -> Patchwork_20668
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20668/index.html
Known issues
Here are the changes found in Patchwork_20668 that come from known issues:
### IGT changes ###
Possible fixes
* igt@gem_exec_suspend@basic-s0:
- {fi-tgl-1115g4}:[FAIL][1] ([i915#1888]) -> [PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s0.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20668/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s0.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7500u: [DMESG-FAIL][3] ([i915#165]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20668/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [FAIL][5] ([i915#1372]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10367/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20668/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372
[i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
Participating hosts (38 -> 34)
--
Missing(4): fi-kbl-soraka fi-ilk-m540 fi-bdw-samus fi-hsw-4200u
Build changes
-
* Linux: CI_DRM_10367 -> Patchwork_20668
CI-20190529: 20190529
CI_DRM_10367: 598494d0149b67545593dfb1b5fa60278907749e @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6146: 6caef22e4aafed275771f564d4ea4cab09896ebc @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20668: aef265c105907ab46375159b29676223f3dc15cd @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
aef265c10590 drm/i915/gem: Migrate to system at dma-buf attach time (v7)
ed5f8fe5c868 drm/i915/gem: Correct the locking and pin pattern for dma-buf (v8)
a341d44369d5 drm/i915/gem/ttm: Respect the objection region in
placement_from_obj
8e3b292518c5 drm/i915/gem: Unify user object creation (v3)
7e52c04eada6 drm/i915/gem: Call i915_gem_flush_free_objects() in
i915_gem_dumb_create()
30e5e6cbd8ab drm/i915/gem: Refactor placement setup for i915_gem_object_create*
(v2)
ac72c58af8ba drm/i915/gem: Check object_can_migrate from object_migrate
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20668/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BUILD: failure for 5.14-rc2 warnings with kvmgvt
== Series Details == Series: 5.14-rc2 warnings with kvmgvt URL : https://patchwork.freedesktop.org/series/92845/ State : failure == Summary == Applying: 5.14-rc2 warnings with kvmgvt error: corrupt patch at line 12 error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0001 5.14-rc2 warnings with kvmgvt When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 16/18] drm/i915/guc: Update GuC debugfs to support new GuC
Update GuC debugfs to support the new GuC structures.
v2:
(John Harrison)
- Remove intel_lrc_reg.h include from i915_debugfs.c
(Michal)
- Rename GuC debugfs functions
Signed-off-by: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 22
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 3 +
.../gpu/drm/i915/gt/uc/intel_guc_debugfs.c| 23 +++-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 55 +++
.../gpu/drm/i915/gt/uc/intel_guc_submission.h | 5 ++
5 files changed, 107 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index b6bbbdb4c689..8bb6b1bbcea1 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -1174,3 +1174,25 @@ void intel_guc_ct_event_handler(struct intel_guc_ct *ct)
ct_try_receive_message(ct);
}
+
+void intel_guc_ct_print_info(struct intel_guc_ct *ct,
+struct drm_printer *p)
+{
+ drm_printf(p, "CT %s\n", enableddisabled(ct->enabled));
+
+ if (!ct->enabled)
+ return;
+
+ drm_printf(p, "H2G Space: %u\n",
+ atomic_read(>ctbs.send.space) * 4);
+ drm_printf(p, "Head: %u\n",
+ ct->ctbs.send.desc->head);
+ drm_printf(p, "Tail: %u\n",
+ ct->ctbs.send.desc->tail);
+ drm_printf(p, "G2H Space: %u\n",
+ atomic_read(>ctbs.recv.space) * 4);
+ drm_printf(p, "Head: %u\n",
+ ct->ctbs.recv.desc->head);
+ drm_printf(p, "Tail: %u\n",
+ ct->ctbs.recv.desc->tail);
+}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
index 2758ee849a59..f709a19c7e21 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
@@ -16,6 +16,7 @@
struct i915_vma;
struct intel_guc;
+struct drm_printer;
/**
* DOC: Command Transport (CT).
@@ -114,4 +115,6 @@ int intel_guc_ct_send(struct intel_guc_ct *ct, const u32
*action, u32 len,
u32 *response_buf, u32 response_buf_size, u32 flags);
void intel_guc_ct_event_handler(struct intel_guc_ct *ct);
+void intel_guc_ct_print_info(struct intel_guc_ct *ct, struct drm_printer *p);
+
#endif /* _INTEL_GUC_CT_H_ */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c
index fe7cb7b29a1e..7a454c91a736 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c
@@ -9,6 +9,8 @@
#include "intel_guc.h"
#include "intel_guc_debugfs.h"
#include "intel_guc_log_debugfs.h"
+#include "gt/uc/intel_guc_ct.h"
+#include "gt/uc/intel_guc_submission.h"
static int guc_info_show(struct seq_file *m, void *data)
{
@@ -22,16 +24,35 @@ static int guc_info_show(struct seq_file *m, void *data)
drm_puts(, "\n");
intel_guc_log_info(>log, );
- /* Add more as required ... */
+ if (!intel_guc_submission_is_used(guc))
+ return 0;
+
+ intel_guc_ct_print_info(>ct, );
+ intel_guc_submission_print_info(guc, );
return 0;
}
DEFINE_GT_DEBUGFS_ATTRIBUTE(guc_info);
+static int guc_registered_contexts_show(struct seq_file *m, void *data)
+{
+ struct intel_guc *guc = m->private;
+ struct drm_printer p = drm_seq_file_printer(m);
+
+ if (!intel_guc_submission_is_used(guc))
+ return -ENODEV;
+
+ intel_guc_submission_print_context_info(guc, );
+
+ return 0;
+}
+DEFINE_GT_DEBUGFS_ATTRIBUTE(guc_registered_contexts);
+
void intel_guc_debugfs_register(struct intel_guc *guc, struct dentry *root)
{
static const struct debugfs_gt_file files[] = {
{ "guc_info", _info_fops, NULL },
+ { "guc_registered_contexts", _registered_contexts_fops,
NULL },
};
if (!intel_guc_is_supported(guc))
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index e4ce21c9b7ef..e6e5364beb1c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1609,3 +1609,58 @@ int intel_guc_sched_done_process_msg(struct intel_guc
*guc,
return 0;
}
+
+void intel_guc_submission_print_info(struct intel_guc *guc,
+struct drm_printer *p)
+{
+ struct i915_sched_engine *sched_engine = guc->sched_engine;
+ struct rb_node *rb;
+ unsigned long flags;
+
+ if (!sched_engine)
+ return;
+
+ drm_printf(p, "GuC Number Outstanding Submission G2H: %u\n",
+ atomic_read(>outstanding_submission_g2h));
+ drm_printf(p, "GuC tasklet count: %u\n\n",
+ atomic_read(_engine->tasklet.count));
+
+
[Intel-gfx] [PATCH 17/18] drm/i915/guc: Add trace point for GuC submit
Add trace point for GuC submit. Extended existing request trace points
to include submit fence value,, guc_id, and ring tail value.
v2: Fix white space alignment in i915_request_add trace point
v3: Delete dep_from , dep_to (Tvrtko)
Cc: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 3 +++
drivers/gpu/drm/i915/i915_trace.h | 23 +++
2 files changed, 22 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index e6e5364beb1c..d47a8358c831 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -418,6 +418,7 @@ static int guc_dequeue_one_context(struct intel_guc *guc)
guc->stalled_request = last;
return false;
}
+ trace_i915_request_guc_submit(last);
}
guc->stalled_request = NULL;
@@ -638,6 +639,8 @@ static int guc_bypass_tasklet_submit(struct intel_guc *guc,
ret = guc_add_request(guc, rq);
if (ret == -EBUSY)
guc->stalled_request = rq;
+ else
+ trace_i915_request_guc_submit(rq);
return ret;
}
diff --git a/drivers/gpu/drm/i915/i915_trace.h
b/drivers/gpu/drm/i915/i915_trace.h
index 6778ad2a14a4..478f5427531d 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -794,30 +794,40 @@ DECLARE_EVENT_CLASS(i915_request,
TP_STRUCT__entry(
__field(u32, dev)
__field(u64, ctx)
+__field(u32, guc_id)
__field(u16, class)
__field(u16, instance)
__field(u32, seqno)
+__field(u32, tail)
),
TP_fast_assign(
__entry->dev = rq->engine->i915->drm.primary->index;
__entry->class = rq->engine->uabi_class;
__entry->instance = rq->engine->uabi_instance;
+ __entry->guc_id = rq->context->guc_id;
__entry->ctx = rq->fence.context;
__entry->seqno = rq->fence.seqno;
+ __entry->tail = rq->tail;
),
- TP_printk("dev=%u, engine=%u:%u, ctx=%llu, seqno=%u",
+ TP_printk("dev=%u, engine=%u:%u, guc_id=%u, ctx=%llu, seqno=%u,
tail=%u",
__entry->dev, __entry->class, __entry->instance,
- __entry->ctx, __entry->seqno)
+ __entry->guc_id, __entry->ctx, __entry->seqno,
+ __entry->tail)
);
DEFINE_EVENT(i915_request, i915_request_add,
- TP_PROTO(struct i915_request *rq),
- TP_ARGS(rq)
+TP_PROTO(struct i915_request *rq),
+TP_ARGS(rq)
);
#if defined(CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS)
+DEFINE_EVENT(i915_request, i915_request_guc_submit,
+TP_PROTO(struct i915_request *rq),
+TP_ARGS(rq)
+);
+
DEFINE_EVENT(i915_request, i915_request_submit,
TP_PROTO(struct i915_request *rq),
TP_ARGS(rq)
@@ -887,6 +897,11 @@ TRACE_EVENT(i915_request_out,
#else
#if !defined(TRACE_HEADER_MULTI_READ)
+static inline void
+trace_i915_request_guc_submit(struct i915_request *rq)
+{
+}
+
static inline void
trace_i915_request_submit(struct i915_request *rq)
{
--
2.28.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 18/18] drm/i915: Add intel_context tracing
Add intel_context tracing. These trace points are particular helpful
when debugging the GuC firmware and can be enabled via
CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS kernel config option.
Cc: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/intel_context.c | 6 +
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 14 ++
drivers/gpu/drm/i915/i915_trace.h | 145 ++
3 files changed, 165 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index 91349d071e0e..251ff7eea22d 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -8,6 +8,7 @@
#include "i915_drv.h"
#include "i915_globals.h"
+#include "i915_trace.h"
#include "intel_context.h"
#include "intel_engine.h"
@@ -28,6 +29,7 @@ static void rcu_context_free(struct rcu_head *rcu)
{
struct intel_context *ce = container_of(rcu, typeof(*ce), rcu);
+ trace_intel_context_free(ce);
kmem_cache_free(global.slab_ce, ce);
}
@@ -46,6 +48,7 @@ intel_context_create(struct intel_engine_cs *engine)
return ERR_PTR(-ENOMEM);
intel_context_init(ce, engine);
+ trace_intel_context_create(ce);
return ce;
}
@@ -268,6 +271,8 @@ int __intel_context_do_pin_ww(struct intel_context *ce,
GEM_BUG_ON(!intel_context_is_pinned(ce)); /* no overflow! */
+ trace_intel_context_do_pin(ce);
+
err_unlock:
mutex_unlock(>pin_mutex);
err_post_unpin:
@@ -323,6 +328,7 @@ void __intel_context_do_unpin(struct intel_context *ce, int
sub)
*/
intel_context_get(ce);
intel_context_active_release(ce);
+ trace_intel_context_do_unpin(ce);
intel_context_put(ce);
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index d47a8358c831..26aadad10b12 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -344,6 +344,7 @@ static int guc_add_request(struct intel_guc *guc, struct
i915_request *rq)
err = intel_guc_send_nb(guc, action, len, g2h_len_dw);
if (!enabled && !err) {
+ trace_intel_context_sched_enable(ce);
atomic_inc(>outstanding_submission_g2h);
set_context_enabled(ce);
} else if (!enabled) {
@@ -815,6 +816,8 @@ static int register_context(struct intel_context *ce)
u32 offset = intel_guc_ggtt_offset(guc, guc->lrc_desc_pool) +
ce->guc_id * sizeof(struct guc_lrc_desc);
+ trace_intel_context_register(ce);
+
return __guc_action_register_context(guc, ce->guc_id, offset);
}
@@ -835,6 +838,8 @@ static int deregister_context(struct intel_context *ce, u32
guc_id)
{
struct intel_guc *guc = ce_to_guc(ce);
+ trace_intel_context_deregister(ce);
+
return __guc_action_deregister_context(guc, guc_id);
}
@@ -908,6 +913,7 @@ static int guc_lrc_desc_pin(struct intel_context *ce)
* registering this context.
*/
if (context_registered) {
+ trace_intel_context_steal_guc_id(ce);
set_context_wait_for_deregister_to_register(ce);
intel_context_get(ce);
@@ -971,6 +977,7 @@ static void __guc_context_sched_disable(struct intel_guc
*guc,
GEM_BUG_ON(guc_id == GUC_INVALID_LRC_ID);
+ trace_intel_context_sched_disable(ce);
intel_context_get(ce);
guc_submission_send_busy_loop(guc, action, ARRAY_SIZE(action),
@@ -1133,6 +1140,9 @@ static void __guc_signal_context_fence(struct
intel_context *ce)
lockdep_assert_held(>guc_state.lock);
+ if (!list_empty(>guc_state.fences))
+ trace_intel_context_fence_release(ce);
+
list_for_each_entry(rq, >guc_state.fences, guc_fence_link)
i915_sw_fence_complete(>submit);
@@ -1538,6 +1548,8 @@ int intel_guc_deregister_done_process_msg(struct
intel_guc *guc,
if (unlikely(!ce))
return -EPROTO;
+ trace_intel_context_deregister_done(ce);
+
if (context_wait_for_deregister_to_register(ce)) {
struct intel_runtime_pm *runtime_pm =
>engine->gt->i915->runtime_pm;
@@ -1589,6 +1601,8 @@ int intel_guc_sched_done_process_msg(struct intel_guc
*guc,
return -EPROTO;
}
+ trace_intel_context_sched_done(ce);
+
if (context_pending_enable(ce)) {
clr_context_pending_enable(ce);
} else if (context_pending_disable(ce)) {
diff --git a/drivers/gpu/drm/i915/i915_trace.h
b/drivers/gpu/drm/i915/i915_trace.h
index 478f5427531d..68b70626c3e2 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -895,6 +895,91 @@ TRACE_EVENT(i915_request_out,
__entry->ctx,
[Intel-gfx] [PATCH 11/18] drm/i915: Disable preempt busywait when using GuC scheduling
Disable preempt busywait when using GuC scheduling. This isn't needed as the GuC controls preemption when scheduling. v2: (John H): - Fix commit message Cc: John Harrison Signed-off-by: Matthew Brost Reviewed-by: John Harrison --- drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c index a69f5c438c72..b29eb9fd0009 100644 --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c @@ -506,7 +506,8 @@ gen8_emit_fini_breadcrumb_tail(struct i915_request *rq, u32 *cs) *cs++ = MI_USER_INTERRUPT; *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; - if (intel_engine_has_semaphores(rq->engine)) + if (intel_engine_has_semaphores(rq->engine) && + !intel_uc_uses_guc_submission(>engine->gt->uc)) cs = emit_preempt_busywait(rq, cs); rq->tail = intel_ring_offset(rq, cs); @@ -598,7 +599,8 @@ gen12_emit_fini_breadcrumb_tail(struct i915_request *rq, u32 *cs) *cs++ = MI_USER_INTERRUPT; *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; - if (intel_engine_has_semaphores(rq->engine)) + if (intel_engine_has_semaphores(rq->engine) && + !intel_uc_uses_guc_submission(>engine->gt->uc)) cs = gen12_emit_preempt_busywait(rq, cs); rq->tail = intel_ring_offset(rq, cs); -- 2.28.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 10/18] drm/i915/guc: Extend deregistration fence to schedule disable
Extend the deregistration context fence to fence whne a GuC context has
scheduling disable pending.
v2:
(John H)
- Update comment why we check the pin count within spin lock
Cc: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 40 +++
1 file changed, 33 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 2f393d9dba0d..fc0b36ab1e68 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -930,7 +930,22 @@ static void guc_context_sched_disable(struct intel_context
*ce)
goto unpin;
spin_lock_irqsave(>guc_state.lock, flags);
+
+ /*
+* We have to check if the context has been pinned again as another pin
+* operation is allowed to pass this function. Checking the pin count,
+* within ce->guc_state.lock, synchronizes this function with
+* guc_request_alloc ensuring a request doesn't slip through the
+* 'context_pending_disable' fence. Checking within the spin lock (can't
+* sleep) ensures another process doesn't pin this context and generate
+* a request before we set the 'context_pending_disable' flag here.
+*/
+ if (unlikely(atomic_add_unless(>pin_count, -2, 2))) {
+ spin_unlock_irqrestore(>guc_state.lock, flags);
+ return;
+ }
guc_id = prep_context_pending_disable(ce);
+
spin_unlock_irqrestore(>guc_state.lock, flags);
with_intel_runtime_pm(runtime_pm, wakeref)
@@ -1135,19 +1150,22 @@ static int guc_request_alloc(struct i915_request *rq)
out:
/*
* We block all requests on this context if a G2H is pending for a
-* context deregistration as the GuC will fail a context registration
-* while this G2H is pending. Once a G2H returns, the fence is released
-* that is blocking these requests (see guc_signal_context_fence).
+* schedule disable or context deregistration as the GuC will fail a
+* schedule enable or context registration if either G2H is pending
+* respectfully. Once a G2H returns, the fence is released that is
+* blocking these requests (see guc_signal_context_fence).
*
-* We can safely check the below field outside of the lock as it isn't
-* possible for this field to transition from being clear to set but
+* We can safely check the below fields outside of the lock as it isn't
+* possible for these fields to transition from being clear to set but
* converse is possible, hence the need for the check within the lock.
*/
- if (likely(!context_wait_for_deregister_to_register(ce)))
+ if (likely(!context_wait_for_deregister_to_register(ce) &&
+ !context_pending_disable(ce)))
return 0;
spin_lock_irqsave(>guc_state.lock, flags);
- if (context_wait_for_deregister_to_register(ce)) {
+ if (context_wait_for_deregister_to_register(ce) ||
+ context_pending_disable(ce)) {
i915_sw_fence_await(>submit);
list_add_tail(>guc_fence_link, >guc_state.fences);
@@ -1491,10 +1509,18 @@ int intel_guc_sched_done_process_msg(struct intel_guc
*guc,
if (context_pending_enable(ce)) {
clr_context_pending_enable(ce);
} else if (context_pending_disable(ce)) {
+ /*
+* Unpin must be done before __guc_signal_context_fence,
+* otherwise a race exists between the requests getting
+* submitted + retired before this unpin completes resulting in
+* the pin_count going to zero and the context still being
+* enabled.
+*/
intel_context_sched_disable_unpin(ce);
spin_lock_irqsave(>guc_state.lock, flags);
clr_context_pending_disable(ce);
+ __guc_signal_context_fence(ce);
spin_unlock_irqrestore(>guc_state.lock, flags);
}
--
2.28.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 09/18] drm/i915/guc: Disable engine barriers with GuC during unpin
Disable engine barriers for unpinning with GuC. This feature isn't
needed with the GuC as it disables context scheduling before unpinning
which guarantees the HW will not reference the context. Hence it is
not necessary to defer unpinning until a kernel context request
completes on each engine in the context engine mask.
Cc: John Harrison
Signed-off-by: Matthew Brost
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/intel_context.c| 2 +-
drivers/gpu/drm/i915/gt/selftest_context.c | 10 ++
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index 3d5b4116617f..91349d071e0e 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -80,7 +80,7 @@ static int intel_context_active_acquire(struct intel_context
*ce)
__i915_active_acquire(>active);
- if (intel_context_is_barrier(ce))
+ if (intel_context_is_barrier(ce) || intel_engine_uses_guc(ce->engine))
return 0;
/* Preallocate tracking nodes */
diff --git a/drivers/gpu/drm/i915/gt/selftest_context.c
b/drivers/gpu/drm/i915/gt/selftest_context.c
index 26685b927169..fa7b99a671dd 100644
--- a/drivers/gpu/drm/i915/gt/selftest_context.c
+++ b/drivers/gpu/drm/i915/gt/selftest_context.c
@@ -209,7 +209,13 @@ static int __live_active_context(struct intel_engine_cs
*engine)
* This test makes sure that the context is kept alive until a
* subsequent idle-barrier (emitted when the engine wakeref hits 0
* with no more outstanding requests).
+*
+* In GuC submission mode we don't use idle barriers and we instead
+* get a message from the GuC to signal that it is safe to unpin the
+* context from memory.
*/
+ if (intel_engine_uses_guc(engine))
+ return 0;
if (intel_engine_pm_is_awake(engine)) {
pr_err("%s is awake before starting %s!\n",
@@ -357,7 +363,11 @@ static int __live_remote_context(struct intel_engine_cs
*engine)
* on the context image remotely (intel_context_prepare_remote_request),
* which inserts foreign fences into intel_context.active, does not
* clobber the idle-barrier.
+*
+* In GuC submission mode we don't use idle barriers.
*/
+ if (intel_engine_uses_guc(engine))
+ return 0;
if (intel_engine_pm_is_awake(engine)) {
pr_err("%s is awake before starting %s!\n",
--
2.28.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 13/18] drm/i915/guc: Disable semaphores when using GuC scheduling
Semaphores are an optimization and not required for basic GuC submission to work properly. Disable until we have time to do the implementation to enable semaphores and tune them for performance. Also long direction is just to delete semaphores from the i915 so another reason to not enable these for GuC submission. This patch fixes an existing bugs where I915_ENGINE_HAS_SEMAPHORES was not honored correctly. v2: Reword commit message v3: (John H) - Add text to commit indicating this also fixing an existing bug v4: (John H) - s/bug/bugs Cc: John Harrison Signed-off-by: Matthew Brost Reviewed-by: John Harrison --- drivers/gpu/drm/i915/gem/i915_gem_context.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index 7d6f52d8a801..64659802d4df 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -799,7 +799,8 @@ static int intel_context_set_gem(struct intel_context *ce, } if (ctx->sched.priority >= I915_PRIORITY_NORMAL && - intel_engine_has_timeslices(ce->engine)) + intel_engine_has_timeslices(ce->engine) && + intel_engine_has_semaphores(ce->engine)) __set_bit(CONTEXT_USE_SEMAPHORES, >flags); if (IS_ACTIVE(CONFIG_DRM_I915_REQUEST_TIMEOUT) && @@ -1778,7 +1779,8 @@ static void __apply_priority(struct intel_context *ce, void *arg) if (!intel_engine_has_timeslices(ce->engine)) return; - if (ctx->sched.priority >= I915_PRIORITY_NORMAL) + if (ctx->sched.priority >= I915_PRIORITY_NORMAL && + intel_engine_has_semaphores(ce->engine)) intel_context_set_use_semaphores(ce); else intel_context_clear_use_semaphores(ce); -- 2.28.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 12/18] drm/i915/guc: Ensure request ordering via completion fences
If two requests are on the same ring, they are explicitly ordered by the
HW. So, a submission fence is sufficient to ensure ordering when using
the new GuC submission interface. Conversely, if two requests share a
timeline and are on the same physical engine but different context this
doesn't ensure ordering on the new GuC submission interface. So, a
completion fence needs to be used to ensure ordering.
v2:
(Daniele)
- Don't delete spin lock
v3:
(Daniele)
- Delete forward dec
Signed-off-by: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/i915_request.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index ef26724fe980..c55dea0edb09 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -432,6 +432,7 @@ void i915_request_retire_upto(struct i915_request *rq)
do {
tmp = list_first_entry(>requests, typeof(*tmp), link);
+ GEM_BUG_ON(!i915_request_completed(tmp));
} while (i915_request_retire(tmp) && tmp != rq);
}
@@ -1463,7 +1464,8 @@ i915_request_await_request(struct i915_request *to,
struct i915_request *from)
return ret;
}
- if (is_power_of_2(to->execution_mask | READ_ONCE(from->execution_mask)))
+ if (!intel_engine_uses_guc(to->engine) &&
+ is_power_of_2(to->execution_mask | READ_ONCE(from->execution_mask)))
ret = await_request_submit(to, from);
else
ret = emit_semaphore_wait(to, from, I915_FENCE_GFP);
@@ -1622,6 +1624,8 @@ __i915_request_add_to_timeline(struct i915_request *rq)
prev = to_request(__i915_active_fence_set(>last_request,
>fence));
if (prev && !__i915_request_is_complete(prev)) {
+ bool uses_guc = intel_engine_uses_guc(rq->engine);
+
/*
* The requests are supposed to be kept in order. However,
* we need to be wary in case the timeline->last_request
@@ -1632,7 +1636,9 @@ __i915_request_add_to_timeline(struct i915_request *rq)
i915_seqno_passed(prev->fence.seqno,
rq->fence.seqno));
- if (is_power_of_2(READ_ONCE(prev->engine)->mask |
rq->engine->mask))
+ if ((!uses_guc &&
+is_power_of_2(READ_ONCE(prev->engine)->mask |
rq->engine->mask)) ||
+ (uses_guc && prev->context == rq->context))
i915_sw_fence_await_sw_fence(>submit,
>submit,
>submitq);
--
2.28.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 15/18] drm/i915/guc: Update intel_gt_wait_for_idle to work with GuC
When running the GuC the GPU can't be considered idle if the GuC still
has contexts pinned. As such, a call has been added in
intel_gt_wait_for_idle to idle the UC and in turn the GuC by waiting for
the number of unpinned contexts to go to zero.
v2: rtimeout -> remaining_timeout
v3: Drop unnecessary includes, guc_submission_busy_loop ->
guc_submission_send_busy_loop, drop negatie timeout trick, move a
refactor of guc_context_unpin to earlier path (John H)
v4: Add stddef.h back into intel_gt_requests.h, sort circuit idle
function if not in GuC submission mode
Cc: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 3 +-
drivers/gpu/drm/i915/gt/intel_gt.c| 19
drivers/gpu/drm/i915/gt/intel_gt.h| 2 +
drivers/gpu/drm/i915/gt/intel_gt_requests.c | 21 ++---
drivers/gpu/drm/i915/gt/intel_gt_requests.h | 9 +-
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 4 +
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 1 +
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 4 +
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 88 +--
drivers/gpu/drm/i915/gt/uc/intel_uc.h | 5 ++
drivers/gpu/drm/i915/i915_gem_evict.c | 1 +
.../gpu/drm/i915/selftests/igt_live_test.c| 2 +-
.../gpu/drm/i915/selftests/mock_gem_device.c | 3 +-
13 files changed, 134 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index 2f3b7dc7b0e6..5130e8ed9564 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -645,7 +645,8 @@ mmap_offset_attach(struct drm_i915_gem_object *obj,
goto insert;
/* Attempt to reap some mmap space from dead objects */
- err = intel_gt_retire_requests_timeout(>gt, MAX_SCHEDULE_TIMEOUT);
+ err = intel_gt_retire_requests_timeout(>gt, MAX_SCHEDULE_TIMEOUT,
+ NULL);
if (err)
goto err;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index e714e21c0a4d..acfdd53b2678 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -585,6 +585,25 @@ static void __intel_gt_disable(struct intel_gt *gt)
GEM_BUG_ON(intel_gt_pm_is_awake(gt));
}
+int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout)
+{
+ long remaining_timeout;
+
+ /* If the device is asleep, we have no requests outstanding */
+ if (!intel_gt_pm_is_awake(gt))
+ return 0;
+
+ while ((timeout = intel_gt_retire_requests_timeout(gt, timeout,
+ _timeout))
> 0) {
+ cond_resched();
+ if (signal_pending(current))
+ return -EINTR;
+ }
+
+ return timeout ? timeout : intel_uc_wait_for_idle(>uc,
+ remaining_timeout);
+}
+
int intel_gt_init(struct intel_gt *gt)
{
int err;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
b/drivers/gpu/drm/i915/gt/intel_gt.h
index e7aabe0cc5bf..74e771871a9b 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -48,6 +48,8 @@ void intel_gt_driver_release(struct intel_gt *gt);
void intel_gt_driver_late_release(struct intel_gt *gt);
+int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout);
+
void intel_gt_check_and_clear_faults(struct intel_gt *gt);
void intel_gt_clear_error_registers(struct intel_gt *gt,
intel_engine_mask_t engine_mask);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_requests.c
b/drivers/gpu/drm/i915/gt/intel_gt_requests.c
index 647eca9d867a..edb881d75630 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_requests.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_requests.c
@@ -130,7 +130,8 @@ void intel_engine_fini_retire(struct intel_engine_cs
*engine)
GEM_BUG_ON(engine->retire);
}
-long intel_gt_retire_requests_timeout(struct intel_gt *gt, long timeout)
+long intel_gt_retire_requests_timeout(struct intel_gt *gt, long timeout,
+ long *remaining_timeout)
{
struct intel_gt_timelines *timelines = >timelines;
struct intel_timeline *tl, *tn;
@@ -195,22 +196,10 @@ out_active: spin_lock(>lock);
if (flush_submission(gt, timeout)) /* Wait, there's more! */
active_count++;
- return active_count ? timeout : 0;
-}
-
-int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout)
-{
- /* If the device is asleep, we have no requests outstanding */
- if (!intel_gt_pm_is_awake(gt))
- return 0;
-
- while ((timeout = intel_gt_retire_requests_timeout(gt, timeout)) > 0) {
- cond_resched();
- if (signal_pending(current))
-
[Intel-gfx] [PATCH 05/18] drm/i915/guc: Add bypass tasklet submission path to GuC
Add bypass tasklet submission path to GuC. The tasklet is only used if H2G
channel has backpresure.
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 37 +++
1 file changed, 29 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index ca0717166a27..53b4a5eb4a85 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -172,6 +172,12 @@ static int guc_add_request(struct intel_guc *guc, struct
i915_request *rq)
return err;
}
+static inline void guc_set_lrc_tail(struct i915_request *rq)
+{
+ rq->context->lrc_reg_state[CTX_RING_TAIL] =
+ intel_ring_set_tail(rq->ring, rq->tail);
+}
+
static inline int rq_prio(const struct i915_request *rq)
{
return rq->sched.attr.priority;
@@ -215,8 +221,7 @@ static int guc_dequeue_one_context(struct intel_guc *guc)
}
done:
if (submit) {
- last->context->lrc_reg_state[CTX_RING_TAIL] =
- intel_ring_set_tail(last->ring, last->tail);
+ guc_set_lrc_tail(last);
resubmit:
/*
* We only check for -EBUSY here even though it is possible for
@@ -496,20 +501,36 @@ static inline void queue_request(struct i915_sched_engine
*sched_engine,
set_bit(I915_FENCE_FLAG_PQUEUE, >fence.flags);
}
+static int guc_bypass_tasklet_submit(struct intel_guc *guc,
+struct i915_request *rq)
+{
+ int ret;
+
+ __i915_request_submit(rq);
+
+ trace_i915_request_in(rq, 0);
+
+ guc_set_lrc_tail(rq);
+ ret = guc_add_request(guc, rq);
+ if (ret == -EBUSY)
+ guc->stalled_request = rq;
+
+ return ret;
+}
+
static void guc_submit_request(struct i915_request *rq)
{
struct i915_sched_engine *sched_engine = rq->engine->sched_engine;
+ struct intel_guc *guc = >engine->gt->uc.guc;
unsigned long flags;
/* Will be called from irq-context when using foreign fences. */
spin_lock_irqsave(_engine->lock, flags);
- queue_request(sched_engine, rq, rq_prio(rq));
-
- GEM_BUG_ON(i915_sched_engine_is_empty(sched_engine));
- GEM_BUG_ON(list_empty(>sched.link));
-
- tasklet_hi_schedule(_engine->tasklet);
+ if (guc->stalled_request || !i915_sched_engine_is_empty(sched_engine))
+ queue_request(sched_engine, rq, rq_prio(rq));
+ else if (guc_bypass_tasklet_submit(guc, rq) == -EBUSY)
+ tasklet_hi_schedule(_engine->tasklet);
spin_unlock_irqrestore(_engine->lock, flags);
}
--
2.28.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 14/18] drm/i915/guc: Ensure G2H response has space in buffer
Ensure G2H response has space in the buffer before sending H2G CTB as
the GuC can't handle any backpressure on the G2H interface.
v2:
(Matthew)
- s/INTEL_GUC_SEND/INTEL_GUC_CT_SEND
v3:
(Matthew)
- Add G2H credit accounting to blocking path, add g2h_release_space
helper
(John H)
- CTB_G2H_BUFFER_SIZE / 4 == G2H_ROOM_BUFFER_SIZE
Signed-off-by: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 8 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 94 +++
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 11 ++-
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 4 +
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 13 ++-
5 files changed, 104 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 4d470ebeda95..451797c62b41 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -96,10 +96,11 @@ inline int intel_guc_send(struct intel_guc *guc, const u32
*action, u32 len)
}
static
-inline int intel_guc_send_nb(struct intel_guc *guc, const u32 *action, u32 len)
+inline int intel_guc_send_nb(struct intel_guc *guc, const u32 *action, u32 len,
+u32 g2h_len_dw)
{
return intel_guc_ct_send(>ct, action, len, NULL, 0,
-INTEL_GUC_CT_SEND_NB);
+MAKE_SEND_FLAGS(g2h_len_dw));
}
static inline int
@@ -113,6 +114,7 @@ intel_guc_send_and_receive(struct intel_guc *guc, const u32
*action, u32 len,
static inline int intel_guc_send_busy_loop(struct intel_guc *guc,
const u32 *action,
u32 len,
+ u32 g2h_len_dw,
bool loop)
{
int err;
@@ -130,7 +132,7 @@ static inline int intel_guc_send_busy_loop(struct intel_guc
*guc,
might_sleep_if(loop && not_atomic);
retry:
- err = intel_guc_send_nb(guc, action, len);
+ err = intel_guc_send_nb(guc, action, len, g2h_len_dw);
if (unlikely(err == -EBUSY && loop)) {
if (likely(not_atomic)) {
if (msleep_interruptible(sleep_period_ms))
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 019b25ff1888..75f69c28056e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -73,6 +73,7 @@ static inline struct drm_device *ct_to_drm(struct
intel_guc_ct *ct)
#define CTB_DESC_SIZE ALIGN(sizeof(struct guc_ct_buffer_desc), SZ_2K)
#define CTB_H2G_BUFFER_SIZE(SZ_4K)
#define CTB_G2H_BUFFER_SIZE(4 * CTB_H2G_BUFFER_SIZE)
+#define G2H_ROOM_BUFFER_SIZE (CTB_G2H_BUFFER_SIZE / 4)
struct ct_request {
struct list_head link;
@@ -129,23 +130,27 @@ static void guc_ct_buffer_desc_init(struct
guc_ct_buffer_desc *desc)
static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb)
{
+ u32 space;
+
ctb->broken = false;
ctb->tail = 0;
ctb->head = 0;
- ctb->space = CIRC_SPACE(ctb->tail, ctb->head, ctb->size);
+ space = CIRC_SPACE(ctb->tail, ctb->head, ctb->size) - ctb->resv_space;
+ atomic_set(>space, space);
guc_ct_buffer_desc_init(ctb->desc);
}
static void guc_ct_buffer_init(struct intel_guc_ct_buffer *ctb,
struct guc_ct_buffer_desc *desc,
- u32 *cmds, u32 size_in_bytes)
+ u32 *cmds, u32 size_in_bytes, u32 resv_space)
{
GEM_BUG_ON(size_in_bytes % 4);
ctb->desc = desc;
ctb->cmds = cmds;
ctb->size = size_in_bytes / 4;
+ ctb->resv_space = resv_space / 4;
guc_ct_buffer_reset(ctb);
}
@@ -226,6 +231,7 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
struct guc_ct_buffer_desc *desc;
u32 blob_size;
u32 cmds_size;
+ u32 resv_space;
void *blob;
u32 *cmds;
int err;
@@ -250,19 +256,23 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
desc = blob;
cmds = blob + 2 * CTB_DESC_SIZE;
cmds_size = CTB_H2G_BUFFER_SIZE;
- CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u\n", "send",
-ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size);
+ resv_space = 0;
+ CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "send",
+ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
+resv_space);
- guc_ct_buffer_init(>ctbs.send, desc, cmds, cmds_size);
+ guc_ct_buffer_init(>ctbs.send, desc, cmds, cmds_size, resv_space);
/* store pointers to desc and cmds for recv ctb */
desc = blob + CTB_DESC_SIZE;
cmds = blob + 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE;
cmds_size =
[Intel-gfx] [PATCH 02/18] drm/i915/guc: Remove GuC stage descriptor, add LRC descriptor
Remove old GuC stage descriptor, add LRC descriptor which will be used
by the new GuC interface implemented in this patch series.
v2:
(John Harrison)
- s/lrc/LRC/g
Cc: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 4 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 65 -
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 72 ++-
3 files changed, 25 insertions(+), 116 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 72e4653222e2..2625d2d5959f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -43,8 +43,8 @@ struct intel_guc {
struct i915_vma *ads_vma;
struct __guc_ads_blob *ads_blob;
- struct i915_vma *stage_desc_pool;
- void *stage_desc_pool_vaddr;
+ struct i915_vma *lrc_desc_pool;
+ void *lrc_desc_pool_vaddr;
/* Control params for fw initialization */
u32 params[GUC_CTL_MAX_DWORDS];
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index 3e060d5958cc..3489b390ae77 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -26,9 +26,6 @@
#define GUC_CLIENT_PRIORITY_NORMAL 3
#define GUC_CLIENT_PRIORITY_NUM4
-#define GUC_MAX_STAGE_DESCRIPTORS 1024
-#defineGUC_INVALID_STAGE_IDGUC_MAX_STAGE_DESCRIPTORS
-
#define GUC_MAX_LRC_DESCRIPTORS65535
#defineGUC_INVALID_LRC_ID GUC_MAX_LRC_DESCRIPTORS
@@ -181,68 +178,6 @@ struct guc_process_desc {
u32 reserved[30];
} __packed;
-/* engine id and context id is packed into guc_execlist_context.context_id*/
-#define GUC_ELC_CTXID_OFFSET 0
-#define GUC_ELC_ENGINE_OFFSET 29
-
-/* The execlist context including software and HW information */
-struct guc_execlist_context {
- u32 context_desc;
- u32 context_id;
- u32 ring_status;
- u32 ring_lrca;
- u32 ring_begin;
- u32 ring_end;
- u32 ring_next_free_location;
- u32 ring_current_tail_pointer_value;
- u8 engine_state_submit_value;
- u8 engine_state_wait_value;
- u16 pagefault_count;
- u16 engine_submit_queue_count;
-} __packed;
-
-/*
- * This structure describes a stage set arranged for a particular communication
- * between uKernel (GuC) and Driver (KMD). Technically, this is known as a
- * "GuC Context descriptor" in the specs, but we use the term "stage
descriptor"
- * to avoid confusion with all the other things already named "context" in the
- * driver. A static pool of these descriptors are stored inside a GEM object
- * (stage_desc_pool) which is held for the entire lifetime of our interaction
- * with the GuC, being allocated before the GuC is loaded with its firmware.
- */
-struct guc_stage_desc {
- u32 sched_common_area;
- u32 stage_id;
- u32 pas_id;
- u8 engines_used;
- u64 db_trigger_cpu;
- u32 db_trigger_uk;
- u64 db_trigger_phy;
- u16 db_id;
-
- struct guc_execlist_context lrc[GUC_MAX_ENGINES_NUM];
-
- u8 attribute;
-
- u32 priority;
-
- u32 wq_sampled_tail_offset;
- u32 wq_total_submit_enqueues;
-
- u32 process_desc;
- u32 wq_addr;
- u32 wq_size;
-
- u32 engine_presence;
-
- u8 engine_suspended;
-
- u8 reserved0[3];
- u64 reserved1[1];
-
- u64 desc_private;
-} __packed;
-
#define CONTEXT_REGISTRATION_FLAG_KMD BIT(0)
#define CONTEXT_POLICY_DEFAULT_EXECUTION_QUANTUM_US 100
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index e9c237b18692..ed5d8ab3624f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -65,57 +65,35 @@ static inline struct i915_priolist *to_priolist(struct
rb_node *rb)
return rb_entry(rb, struct i915_priolist, node);
}
-static struct guc_stage_desc *__get_stage_desc(struct intel_guc *guc, u32 id)
+/* Future patches will use this function */
+__maybe_unused
+static struct guc_lrc_desc *__get_lrc_desc(struct intel_guc *guc, u32 index)
{
- struct guc_stage_desc *base = guc->stage_desc_pool_vaddr;
+ struct guc_lrc_desc *base = guc->lrc_desc_pool_vaddr;
- return [id];
-}
-
-static int guc_stage_desc_pool_create(struct intel_guc *guc)
-{
- u32 size = PAGE_ALIGN(sizeof(struct guc_stage_desc) *
- GUC_MAX_STAGE_DESCRIPTORS);
+ GEM_BUG_ON(index >= GUC_MAX_LRC_DESCRIPTORS);
- return intel_guc_allocate_and_map_vma(guc, size, >stage_desc_pool,
- >stage_desc_pool_vaddr);
+ return [index];
}
-static void guc_stage_desc_pool_destroy(struct
[Intel-gfx] [PATCH 08/18] drm/i915/guc: Defer context unpin until scheduling is disabled
With GuC scheduling, it isn't safe to unpin a context while scheduling
is enabled for that context as the GuC may touch some of the pinned
state (e.g. LRC). To ensure scheduling isn't enabled when an unpin is
done, a call back is added to intel_context_unpin when pin count == 1
to disable scheduling for that context. When the response CTB is
received it is safe to do the final unpin.
Future patches may add a heuristic / delay to schedule the disable
call back to avoid thrashing on schedule enable / disable.
v2:
(John H)
- s/drm_dbg/drm_err
(Daneiel)
- Clean up sched state function
Cc: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/intel_context.c | 4 +-
drivers/gpu/drm/i915/gt/intel_context.h | 27 +++-
drivers/gpu/drm/i915/gt/intel_context_types.h | 2 +
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 2 +
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 3 +
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 146 +-
6 files changed, 180 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index ad7197c5910f..3d5b4116617f 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -306,9 +306,9 @@ int __intel_context_do_pin(struct intel_context *ce)
return err;
}
-void intel_context_unpin(struct intel_context *ce)
+void __intel_context_do_unpin(struct intel_context *ce, int sub)
{
- if (!atomic_dec_and_test(>pin_count))
+ if (!atomic_sub_and_test(sub, >pin_count))
return;
CE_TRACE(ce, "unpin\n");
diff --git a/drivers/gpu/drm/i915/gt/intel_context.h
b/drivers/gpu/drm/i915/gt/intel_context.h
index b10cbe8fee99..974ef85320c2 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.h
+++ b/drivers/gpu/drm/i915/gt/intel_context.h
@@ -113,7 +113,32 @@ static inline void __intel_context_pin(struct
intel_context *ce)
atomic_inc(>pin_count);
}
-void intel_context_unpin(struct intel_context *ce);
+void __intel_context_do_unpin(struct intel_context *ce, int sub);
+
+static inline void intel_context_sched_disable_unpin(struct intel_context *ce)
+{
+ __intel_context_do_unpin(ce, 2);
+}
+
+static inline void intel_context_unpin(struct intel_context *ce)
+{
+ if (!ce->ops->sched_disable) {
+ __intel_context_do_unpin(ce, 1);
+ } else {
+ /*
+* Move ownership of this pin to the scheduling disable which is
+* an async operation. When that operation completes the above
+* intel_context_sched_disable_unpin is called potentially
+* unpinning the context.
+*/
+ while (!atomic_add_unless(>pin_count, -1, 1)) {
+ if (atomic_cmpxchg(>pin_count, 1, 2) == 1) {
+ ce->ops->sched_disable(ce);
+ break;
+ }
+ }
+ }
+}
void intel_context_enter_engine(struct intel_context *ce);
void intel_context_exit_engine(struct intel_context *ce);
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index e0e3a937f709..4a5518d295c2 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -43,6 +43,8 @@ struct intel_context_ops {
void (*enter)(struct intel_context *ce);
void (*exit)(struct intel_context *ce);
+ void (*sched_disable)(struct intel_context *ce);
+
void (*reset)(struct intel_context *ce);
void (*destroy)(struct kref *kref);
};
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 7fd6c3e343e4..4d470ebeda95 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -248,6 +248,8 @@ int intel_guc_reset_engine(struct intel_guc *guc,
int intel_guc_deregister_done_process_msg(struct intel_guc *guc,
const u32 *msg, u32 len);
+int intel_guc_sched_done_process_msg(struct intel_guc *guc,
+const u32 *msg, u32 len);
void intel_guc_load_status(struct intel_guc *guc, struct drm_printer *p);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 28ff82c5be45..019b25ff1888 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -932,6 +932,9 @@ static int ct_process_request(struct intel_guc_ct *ct,
struct ct_incoming_msg *r
ret = intel_guc_deregister_done_process_msg(guc, payload,
len);
break;
+ case INTEL_GUC_ACTION_SCHED_CONTEXT_MODE_DONE:
+ ret = intel_guc_sched_done_process_msg(guc, payload,
[Intel-gfx] [PATCH 06/18] drm/i915/guc: Implement GuC context operations for new inteface
Implement GuC context operations which includes GuC specific operations
alloc, pin, unpin, and destroy.
v2:
(Daniel Vetter)
- Use msleep_interruptible rather than cond_resched in busy loop
(Michal)
- Remove C++ style comment
v3:
(Matthew Brost)
- Drop GUC_ID_START
(John Harrison)
- Fix a bunch of typos
- Use drm_err rather than drm_dbg for G2H errors
(Daniele)
- Fix ;; typo
- Clean up sched state functions
- Add lockdep for guc_id functions
- Don't call __release_guc_id when guc_id is invalid
- Use MISSING_CASE
- Add comment in guc_context_pin
- Use shorter path to rpm
(Daniele / CI)
- Don't call release_guc_id on an invalid guc_id in destroy
v4:
(Daniel Vetter)
- Add FIXME comment
Signed-off-by: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/intel_context.c | 5 +
drivers/gpu/drm/i915/gt/intel_context_types.h | 22 +-
drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 1 -
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 47 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 4 +
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 670 --
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/i915_request.c | 1 +
8 files changed, 696 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index bd63813c8a80..32fd6647154b 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -384,6 +384,11 @@ intel_context_init(struct intel_context *ce, struct
intel_engine_cs *engine)
mutex_init(>pin_mutex);
+ spin_lock_init(>guc_state.lock);
+
+ ce->guc_id = GUC_INVALID_LRC_ID;
+ INIT_LIST_HEAD(>guc_id_link);
+
i915_active_init(>active,
__intel_context_active, __intel_context_retire, 0);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 6d99631d19b9..606c480aec26 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -96,6 +96,7 @@ struct intel_context {
#define CONTEXT_BANNED 6
#define CONTEXT_FORCE_SINGLE_SUBMISSION7
#define CONTEXT_NOPREEMPT 8
+#define CONTEXT_LRCA_DIRTY 9
struct {
u64 timeout_us;
@@ -138,14 +139,29 @@ struct intel_context {
u8 wa_bb_page; /* if set, page num reserved for context workarounds */
+ struct {
+ /** lock: protects everything in guc_state */
+ spinlock_t lock;
+ /**
+* sched_state: scheduling state of this context using GuC
+* submission
+*/
+ u8 sched_state;
+ } guc_state;
+
/* GuC scheduling state flags that do not require a lock. */
atomic_t guc_sched_state_no_lock;
+ /* GuC LRC descriptor ID */
+ u16 guc_id;
+
+ /* GuC LRC descriptor reference count */
+ atomic_t guc_id_ref;
+
/*
-* GuC LRC descriptor ID - Not assigned in this patch but future patches
-* in the series will.
+* GuC ID link - in list when unpinned but guc_id still valid in GuC
*/
- u16 guc_id;
+ struct list_head guc_id_link;
};
#endif /* __INTEL_CONTEXT_TYPES__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
index 41e5350a7a05..49d4857ad9b7 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
+++ b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
@@ -87,7 +87,6 @@
#define GEN11_CSB_WRITE_PTR_MASK (GEN11_CSB_PTR_MASK << 0)
#define MAX_CONTEXT_HW_ID (1 << 21) /* exclusive */
-#define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */
#define GEN11_MAX_CONTEXT_HW_ID(1 << 11) /* exclusive */
/* in Gen12 ID 0x7FF is reserved to indicate idle */
#define GEN12_MAX_CONTEXT_HW_ID(GEN11_MAX_CONTEXT_HW_ID - 1)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 8c7b92f699f1..7fd6c3e343e4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -7,6 +7,7 @@
#define _INTEL_GUC_H_
#include
+#include
#include "intel_uncore.h"
#include "intel_guc_fw.h"
@@ -44,6 +45,14 @@ struct intel_guc {
void (*disable)(struct intel_guc *guc);
} interrupts;
+ /*
+* contexts_lock protects the pool of free guc ids and a linked list of
+* guc ids available to be stolen
+*/
+ spinlock_t contexts_lock;
+ struct ida guc_ids;
+ struct list_head guc_id_list;
+
bool submission_selected;
struct i915_vma *ads_vma;
@@ -101,6 +110,41 @@ intel_guc_send_and_receive(struct intel_guc *guc, const
u32 *action, u32 len,
[Intel-gfx] [PATCH 03/18] drm/i915/guc: Add LRC descriptor context lookup array
Add LRC descriptor context lookup array which can resolve the
intel_context from the LRC descriptor index. In addition to lookup, it
can determine if the LRC descriptor context is currently registered with
the GuC by checking if an entry for a descriptor index is present.
Future patches in the series will make use of this array.
v2:
(Michal)
- "linux/xarray.h" ->
- s/lrc/LRC
(John H)
- Fix commit message
Cc: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 5 +++
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 32 +--
2 files changed, 35 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 2625d2d5959f..35783558d261 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -6,6 +6,8 @@
#ifndef _INTEL_GUC_H_
#define _INTEL_GUC_H_
+#include
+
#include "intel_uncore.h"
#include "intel_guc_fw.h"
#include "intel_guc_fwif.h"
@@ -46,6 +48,9 @@ struct intel_guc {
struct i915_vma *lrc_desc_pool;
void *lrc_desc_pool_vaddr;
+ /* guc_id to intel_context lookup */
+ struct xarray context_lookup;
+
/* Control params for fw initialization */
u32 params[GUC_CTL_MAX_DWORDS];
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index ed5d8ab3624f..23a94a896a0b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -65,8 +65,6 @@ static inline struct i915_priolist *to_priolist(struct
rb_node *rb)
return rb_entry(rb, struct i915_priolist, node);
}
-/* Future patches will use this function */
-__maybe_unused
static struct guc_lrc_desc *__get_lrc_desc(struct intel_guc *guc, u32 index)
{
struct guc_lrc_desc *base = guc->lrc_desc_pool_vaddr;
@@ -76,6 +74,15 @@ static struct guc_lrc_desc *__get_lrc_desc(struct intel_guc
*guc, u32 index)
return [index];
}
+static inline struct intel_context *__get_context(struct intel_guc *guc, u32
id)
+{
+ struct intel_context *ce = xa_load(>context_lookup, id);
+
+ GEM_BUG_ON(id >= GUC_MAX_LRC_DESCRIPTORS);
+
+ return ce;
+}
+
static int guc_lrc_desc_pool_create(struct intel_guc *guc)
{
u32 size;
@@ -96,6 +103,25 @@ static void guc_lrc_desc_pool_destroy(struct intel_guc *guc)
i915_vma_unpin_and_release(>lrc_desc_pool, I915_VMA_RELEASE_MAP);
}
+static inline void reset_lrc_desc(struct intel_guc *guc, u32 id)
+{
+ struct guc_lrc_desc *desc = __get_lrc_desc(guc, id);
+
+ memset(desc, 0, sizeof(*desc));
+ xa_erase_irq(>context_lookup, id);
+}
+
+static inline bool lrc_desc_registered(struct intel_guc *guc, u32 id)
+{
+ return __get_context(guc, id);
+}
+
+static inline void set_lrc_desc_registered(struct intel_guc *guc, u32 id,
+ struct intel_context *ce)
+{
+ xa_store_irq(>context_lookup, id, ce, GFP_ATOMIC);
+}
+
static void guc_add_request(struct intel_guc *guc, struct i915_request *rq)
{
/* Leaving stub as this function will be used in future patches */
@@ -400,6 +426,8 @@ int intel_guc_submission_init(struct intel_guc *guc)
*/
GEM_BUG_ON(!guc->lrc_desc_pool);
+ xa_init_flags(>context_lookup, XA_FLAGS_LOCK_IRQ);
+
return 0;
}
--
2.28.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 01/18] drm/i915/guc: Add new GuC interface defines and structures
Add new GuC interface defines and structures while maintaining old ones
in parallel.
Cc: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
.../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 14 +++
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 42 +++
2 files changed, 56 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
index 2d6198e63ebe..57e18babdf4b 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
@@ -124,10 +124,24 @@ enum intel_guc_action {
INTEL_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH = 0x302,
INTEL_GUC_ACTION_ENTER_S_STATE = 0x501,
INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
+ INTEL_GUC_ACTION_GLOBAL_SCHED_POLICY_CHANGE = 0x506,
+ INTEL_GUC_ACTION_SCHED_CONTEXT = 0x1000,
+ INTEL_GUC_ACTION_SCHED_CONTEXT_MODE_SET = 0x1001,
+ INTEL_GUC_ACTION_SCHED_CONTEXT_MODE_DONE = 0x1002,
+ INTEL_GUC_ACTION_SCHED_ENGINE_MODE_SET = 0x1003,
+ INTEL_GUC_ACTION_SCHED_ENGINE_MODE_DONE = 0x1004,
+ INTEL_GUC_ACTION_SET_CONTEXT_PRIORITY = 0x1005,
+ INTEL_GUC_ACTION_SET_CONTEXT_EXECUTION_QUANTUM = 0x1006,
+ INTEL_GUC_ACTION_SET_CONTEXT_PREEMPTION_TIMEOUT = 0x1007,
+ INTEL_GUC_ACTION_CONTEXT_RESET_NOTIFICATION = 0x1008,
+ INTEL_GUC_ACTION_ENGINE_FAILURE_NOTIFICATION = 0x1009,
INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
+ INTEL_GUC_ACTION_REGISTER_CONTEXT = 0x4502,
+ INTEL_GUC_ACTION_DEREGISTER_CONTEXT = 0x4503,
INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505,
INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 0x4506,
+ INTEL_GUC_ACTION_DEREGISTER_CONTEXT_DONE = 0x4600,
INTEL_GUC_ACTION_LIMIT
};
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index 617ec601648d..3e060d5958cc 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -17,6 +17,9 @@
#include "abi/guc_communication_ctb_abi.h"
#include "abi/guc_messages_abi.h"
+#define GUC_CONTEXT_DISABLE0
+#define GUC_CONTEXT_ENABLE 1
+
#define GUC_CLIENT_PRIORITY_KMD_HIGH 0
#define GUC_CLIENT_PRIORITY_HIGH 1
#define GUC_CLIENT_PRIORITY_KMD_NORMAL 2
@@ -26,6 +29,9 @@
#define GUC_MAX_STAGE_DESCRIPTORS 1024
#defineGUC_INVALID_STAGE_IDGUC_MAX_STAGE_DESCRIPTORS
+#define GUC_MAX_LRC_DESCRIPTORS65535
+#defineGUC_INVALID_LRC_ID GUC_MAX_LRC_DESCRIPTORS
+
#define GUC_RENDER_ENGINE 0
#define GUC_VIDEO_ENGINE 1
#define GUC_BLITTER_ENGINE 2
@@ -237,6 +243,42 @@ struct guc_stage_desc {
u64 desc_private;
} __packed;
+#define CONTEXT_REGISTRATION_FLAG_KMD BIT(0)
+
+#define CONTEXT_POLICY_DEFAULT_EXECUTION_QUANTUM_US 100
+#define CONTEXT_POLICY_DEFAULT_PREEMPTION_TIME_US 50
+
+/* Preempt to idle on quantum expiry */
+#define CONTEXT_POLICY_FLAG_PREEMPT_TO_IDLEBIT(0)
+
+/*
+ * GuC Context registration descriptor.
+ * FIXME: This is only required to exist during context registration.
+ * The current 1:1 between guc_lrc_desc and LRCs for the lifetime of the LRC
+ * is not required.
+ */
+struct guc_lrc_desc {
+ u32 hw_context_desc;
+ u32 slpm_perf_mode_hint;/* SPLC v1 only */
+ u32 slpm_freq_hint;
+ u32 engine_submit_mask; /* In logical space */
+ u8 engine_class;
+ u8 reserved0[3];
+ u32 priority;
+ u32 process_desc;
+ u32 wq_addr;
+ u32 wq_size;
+ u32 context_flags; /* CONTEXT_REGISTRATION_* */
+ /* Time for one workload to execute. (in micro seconds) */
+ u32 execution_quantum;
+ /* Time to wait for a preemption request to complete before issuing a
+* reset. (in micro seconds).
+*/
+ u32 preemption_timeout;
+ u32 policy_flags; /* CONTEXT_POLICY_* */
+ u32 reserved1[19];
+} __packed;
+
#define GUC_POWER_UNSPECIFIED 0
#define GUC_POWER_D0 1
#define GUC_POWER_D1 2
--
2.28.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 07/18] drm/i915/guc: Insert fence on context when deregistering
Sometimes during context pinning a context with the same guc_id is
registered with the GuC. In this a case deregister must be done before
the context can be registered. A fence is inserted on all requests while
the deregister is in flight. Once the G2H is received indicating the
deregistration is complete the context is registered and the fence is
released.
v2:
(John H)
- Fix commit message
Cc: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/intel_context.c | 1 +
drivers/gpu/drm/i915/gt/intel_context_types.h | 5 ++
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 51 ++-
drivers/gpu/drm/i915/i915_request.h | 8 +++
4 files changed, 63 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index 32fd6647154b..ad7197c5910f 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -385,6 +385,7 @@ intel_context_init(struct intel_context *ce, struct
intel_engine_cs *engine)
mutex_init(>pin_mutex);
spin_lock_init(>guc_state.lock);
+ INIT_LIST_HEAD(>guc_state.fences);
ce->guc_id = GUC_INVALID_LRC_ID;
INIT_LIST_HEAD(>guc_id_link);
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 606c480aec26..e0e3a937f709 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -147,6 +147,11 @@ struct intel_context {
* submission
*/
u8 sched_state;
+ /*
+* fences: maintains of list of requests that have a submit
+* fence related to GuC submission
+*/
+ struct list_head fences;
} guc_state;
/* GuC scheduling state flags that do not require a lock. */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 463613a414d2..a0871b800153 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -935,6 +935,30 @@ static const struct intel_context_ops guc_context_ops = {
.destroy = guc_context_destroy,
};
+static void __guc_signal_context_fence(struct intel_context *ce)
+{
+ struct i915_request *rq;
+
+ lockdep_assert_held(>guc_state.lock);
+
+ list_for_each_entry(rq, >guc_state.fences, guc_fence_link)
+ i915_sw_fence_complete(>submit);
+
+ INIT_LIST_HEAD(>guc_state.fences);
+}
+
+static void guc_signal_context_fence(struct intel_context *ce)
+{
+ unsigned long flags;
+
+ GEM_BUG_ON(!context_wait_for_deregister_to_register(ce));
+
+ spin_lock_irqsave(>guc_state.lock, flags);
+ clr_context_wait_for_deregister_to_register(ce);
+ __guc_signal_context_fence(ce);
+ spin_unlock_irqrestore(>guc_state.lock, flags);
+}
+
static bool context_needs_register(struct intel_context *ce, bool new_guc_id)
{
return new_guc_id || test_bit(CONTEXT_LRCA_DIRTY, >flags) ||
@@ -945,6 +969,7 @@ static int guc_request_alloc(struct i915_request *rq)
{
struct intel_context *ce = rq->context;
struct intel_guc *guc = ce_to_guc(ce);
+ unsigned long flags;
int ret;
GEM_BUG_ON(!intel_context_is_pinned(rq->context));
@@ -989,7 +1014,7 @@ static int guc_request_alloc(struct i915_request *rq)
* increment (in pin_guc_id) is needed to seal a race with unpin_guc_id.
*/
if (atomic_add_unless(>guc_id_ref, 1, 0))
- return 0;
+ goto out;
ret = pin_guc_id(guc, ce); /* returns 1 if new guc_id assigned */
if (unlikely(ret < 0))
@@ -1005,6 +1030,28 @@ static int guc_request_alloc(struct i915_request *rq)
clear_bit(CONTEXT_LRCA_DIRTY, >flags);
+out:
+ /*
+* We block all requests on this context if a G2H is pending for a
+* context deregistration as the GuC will fail a context registration
+* while this G2H is pending. Once a G2H returns, the fence is released
+* that is blocking these requests (see guc_signal_context_fence).
+*
+* We can safely check the below field outside of the lock as it isn't
+* possible for this field to transition from being clear to set but
+* converse is possible, hence the need for the check within the lock.
+*/
+ if (likely(!context_wait_for_deregister_to_register(ce)))
+ return 0;
+
+ spin_lock_irqsave(>guc_state.lock, flags);
+ if (context_wait_for_deregister_to_register(ce)) {
+ i915_sw_fence_await(>submit);
+
+ list_add_tail(>guc_fence_link, >guc_state.fences);
+ }
+ spin_unlock_irqrestore(>guc_state.lock, flags);
+
return 0;
}
@@
[Intel-gfx] [PATCH 00/18] Series to merge a subset of GuC submission
The first 18 patches [1] are basically ready to merge. v2: Address NITs, add missing RBs, fix checkpatch warnings Signed-off-by: Matthew Brost [1] https://patchwork.freedesktop.org/series/91840/ Matthew Brost (18): drm/i915/guc: Add new GuC interface defines and structures drm/i915/guc: Remove GuC stage descriptor, add LRC descriptor drm/i915/guc: Add LRC descriptor context lookup array drm/i915/guc: Implement GuC submission tasklet drm/i915/guc: Add bypass tasklet submission path to GuC drm/i915/guc: Implement GuC context operations for new inteface drm/i915/guc: Insert fence on context when deregistering drm/i915/guc: Defer context unpin until scheduling is disabled drm/i915/guc: Disable engine barriers with GuC during unpin drm/i915/guc: Extend deregistration fence to schedule disable drm/i915: Disable preempt busywait when using GuC scheduling drm/i915/guc: Ensure request ordering via completion fences drm/i915/guc: Disable semaphores when using GuC scheduling drm/i915/guc: Ensure G2H response has space in buffer drm/i915/guc: Update intel_gt_wait_for_idle to work with GuC drm/i915/guc: Update GuC debugfs to support new GuC drm/i915/guc: Add trace point for GuC submit drm/i915: Add intel_context tracing drivers/gpu/drm/i915/gem/i915_gem_context.c |6 +- drivers/gpu/drm/i915/gem/i915_gem_mman.c |3 +- drivers/gpu/drm/i915/gt/gen8_engine_cs.c |6 +- drivers/gpu/drm/i915/gt/intel_context.c | 18 +- drivers/gpu/drm/i915/gt/intel_context.h | 27 +- drivers/gpu/drm/i915/gt/intel_context_types.h | 32 + drivers/gpu/drm/i915/gt/intel_gt.c| 19 + drivers/gpu/drm/i915/gt/intel_gt.h|2 + drivers/gpu/drm/i915/gt/intel_gt_requests.c | 21 +- drivers/gpu/drm/i915/gt/intel_gt_requests.h |9 +- drivers/gpu/drm/i915/gt/intel_lrc_reg.h |1 - drivers/gpu/drm/i915/gt/selftest_context.c| 10 + .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 14 + drivers/gpu/drm/i915/gt/uc/intel_guc.h| 72 +- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 124 +- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 18 +- .../gpu/drm/i915/gt/uc/intel_guc_debugfs.c| 23 +- drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 89 +- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 1290 ++--- .../gpu/drm/i915/gt/uc/intel_guc_submission.h |5 + drivers/gpu/drm/i915/gt/uc/intel_uc.h |5 + drivers/gpu/drm/i915/i915_gem_evict.c |1 + drivers/gpu/drm/i915/i915_reg.h |1 + drivers/gpu/drm/i915/i915_request.c | 11 +- drivers/gpu/drm/i915/i915_request.h |8 + drivers/gpu/drm/i915/i915_trace.h | 168 ++- .../gpu/drm/i915/selftests/igt_live_test.c|2 +- .../gpu/drm/i915/selftests/mock_gem_device.c |3 +- 28 files changed, 1707 insertions(+), 281 deletions(-) -- 2.28.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 04/18] drm/i915/guc: Implement GuC submission tasklet
Implement GuC submission tasklet for new interface. The new GuC
interface uses H2G to submit contexts to the GuC. Since H2G use a single
channel, a single tasklet is used for the submission path.
Also the per engine interrupt handler has been updated to disable the
rescheduling of the physical engine tasklet, when using GuC scheduling,
as the physical engine tasklet is no longer used.
In this patch the field, guc_id, has been added to intel_context and is
not assigned. Patches later in the series will assign this value.
v2:
(John Harrison)
- Clean up some comments
v3:
(John Harrison)
- More comment cleanups
Cc: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/intel_context_types.h | 9 +
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 4 +
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 231 +-
3 files changed, 127 insertions(+), 117 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 90026c177105..6d99631d19b9 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -137,6 +137,15 @@ struct intel_context {
struct intel_sseu sseu;
u8 wa_bb_page; /* if set, page num reserved for context workarounds */
+
+ /* GuC scheduling state flags that do not require a lock. */
+ atomic_t guc_sched_state_no_lock;
+
+ /*
+* GuC LRC descriptor ID - Not assigned in this patch but future patches
+* in the series will.
+*/
+ u16 guc_id;
};
#endif /* __INTEL_CONTEXT_TYPES__ */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 35783558d261..8c7b92f699f1 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -30,6 +30,10 @@ struct intel_guc {
struct intel_guc_log log;
struct intel_guc_ct ct;
+ /* Global engine used to submit requests to GuC */
+ struct i915_sched_engine *sched_engine;
+ struct i915_request *stalled_request;
+
/* intel_guc_recv interrupt related state */
spinlock_t irq_lock;
unsigned int msg_enabled_mask;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 23a94a896a0b..ca0717166a27 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -60,6 +60,31 @@
#define GUC_REQUEST_SIZE 64 /* bytes */
+/*
+ * Below is a set of functions which control the GuC scheduling state which do
+ * not require a lock as all state transitions are mutually exclusive. i.e. It
+ * is not possible for the context pinning code and submission, for the same
+ * context, to be executing simultaneously. We still need an atomic as it is
+ * possible for some of the bits to changing at the same time though.
+ */
+#define SCHED_STATE_NO_LOCK_ENABLEDBIT(0)
+static inline bool context_enabled(struct intel_context *ce)
+{
+ return (atomic_read(>guc_sched_state_no_lock) &
+ SCHED_STATE_NO_LOCK_ENABLED);
+}
+
+static inline void set_context_enabled(struct intel_context *ce)
+{
+ atomic_or(SCHED_STATE_NO_LOCK_ENABLED, >guc_sched_state_no_lock);
+}
+
+static inline void clr_context_enabled(struct intel_context *ce)
+{
+ atomic_and((u32)~SCHED_STATE_NO_LOCK_ENABLED,
+ >guc_sched_state_no_lock);
+}
+
static inline struct i915_priolist *to_priolist(struct rb_node *rb)
{
return rb_entry(rb, struct i915_priolist, node);
@@ -122,37 +147,29 @@ static inline void set_lrc_desc_registered(struct
intel_guc *guc, u32 id,
xa_store_irq(>context_lookup, id, ce, GFP_ATOMIC);
}
-static void guc_add_request(struct intel_guc *guc, struct i915_request *rq)
+static int guc_add_request(struct intel_guc *guc, struct i915_request *rq)
{
- /* Leaving stub as this function will be used in future patches */
-}
+ int err;
+ struct intel_context *ce = rq->context;
+ u32 action[3];
+ int len = 0;
+ bool enabled = context_enabled(ce);
-/*
- * When we're doing submissions using regular execlists backend, writing to
- * ELSP from CPU side is enough to make sure that writes to ringbuffer pages
- * pinned in mappable aperture portion of GGTT are visible to command streamer.
- * Writes done by GuC on our behalf are not guaranteeing such ordering,
- * therefore, to ensure the flush, we're issuing a POSTING READ.
- */
-static void flush_ggtt_writes(struct i915_vma *vma)
-{
- if (i915_vma_is_map_and_fenceable(vma))
- intel_uncore_posting_read_fw(vma->vm->gt->uncore,
-GUC_STATUS);
-}
+ if (!enabled) {
+ action[len++] = INTEL_GUC_ACTION_SCHED_CONTEXT_MODE_SET;
+ action[len++] = ce->guc_id;
+
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Migrate memory to SMEM when imported cross-device (rev3)
== Series Details == Series: drm/i915: Migrate memory to SMEM when imported cross-device (rev3) URL : https://patchwork.freedesktop.org/series/92617/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_display.c:1896:21:expected struct i915_vma *[assigned] vma +drivers/gpu/drm/i915/display/intel_display.c:1896:21:got void [noderef] __iomem *[assigned] iomem +drivers/gpu/drm/i915/display/intel_display.c:1896:21: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gem/i915_gem_context.c:1412:34:expected struct i915_address_space *vm +drivers/gpu/drm/i915/gem/i915_gem_context.c:1412:34:got struct i915_address_space [noderef] __rcu *vm +drivers/gpu/drm/i915/gem/i915_gem_context.c:1412:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25:expected struct i915_address_space [noderef] __rcu *vm +drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25:got struct i915_address_space * +drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34:expected struct i915_address_space *vm +drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34:got struct i915_address_space [noderef] __rcu *vm +drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1396:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/intel_ring_submission.c:1210:24: warning: Using plain integer as NULL pointer +drivers/gpu/drm/i915/i915_perf.c:1434:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1488:15: warning: memset with byte count of 16777216 +./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080) +./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080) +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
Re: [Intel-gfx] 5.14-rc2 warnings with kvmgvt
On Wed, Jul 21, 2021 at 09:40:03PM +0100, Christoph Hellwig wrote:
> On Wed, Jul 21, 2021 at 04:43:44PM +0100, Christoph Hellwig wrote:
> > > > I'm trying to test some changes for the gvt code, but even with a
> > > > baseline
> > > > 5.14-rc2 host and guest the 915 driver does not seem overly happy:
> > >
> > > Is this a regression over -rc1 or over 5.13?
> > > Bisect possible?
> >
> > This was introduced somewhere between 5.12 and 5.13, still bisecting.
> > Note that it only happens for "headless" setups. Once a display is
> > added on the qemu command line it goes away.
>
> The culprit is:
>
> commit f4eb6d4906669b4285c4f49c87814d4ce63c35bb
> Author: Jani Nikula
> Date: Wed Mar 17 18:36:45 2021 +0200
>
> drm/i915/bios: limit default outputs to ports A through F
>
could you please try this small patch?
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 5b6922e28ef2..8bbeb5978bf7 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2166,7 +2166,8 @@ static void
init_vbt_missing_defaults(struct drm_i915_private *i915)
{
enum port port;
- int ports = PORT_A | PORT_B | PORT_C | PORT_D | PORT_E | PORT_F;
+ int ports = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | \
+ BIT(PORT_D) | BIT(PORT_E) | BIT(PORT_F);
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
