Re: [Intel-gfx] [PATCH 02/19] dma-buf-map: Add helper to initialize second map
On Thu, Jan 27, 2022 at 08:27:11AM +0100, Christian König wrote:
Am 26.01.22 um 21:36 schrieb Lucas De Marchi:
When dma_buf_map struct is passed around, it's useful to be able to
initialize a second map that takes care of reading/writing to an offset
of the original map.
Add a helper that copies the struct and add the offset to the proper
address.
Well what you propose here can lead to all kind of problems and is
rather bad design as far as I can see.
The struct dma_buf_map is only to be filled in by the exporter and
should not be modified in this way by the importer.
humn... not sure if I was clear. There is no importer and exporter here.
There is a role delegation on filling out and reading a buffer when
that buffer represents a struct layout.
struct bla {
int a;
int b;
int c;
struct foo foo;
struct bar bar;
int d;
}
This implementation allows you to have:
fill_foo(struct dma_buf_map *bla_map) { ... }
fill_bar(struct dma_buf_map *bla_map) { ... }
and the first thing these do is to make sure the map it's pointing to
is relative to the struct it's supposed to write/read. Otherwise you're
suggesting everything to be relative to struct bla, or to do the same
I'm doing it, but IMO more prone to error:
struct dma_buf_map map = *bla_map;
dma_buf_map_incr(map, offsetof(...));
IMO this construct is worse because at a point in time in the function
the map was pointing to the wrong thing the function was supposed to
read/write.
It's also useful when the function has double duty, updating a global
part of the struct and a table inside it (see example in patch 6)
thanks
Lucas De Marchi
Re: [Intel-gfx] [PATCH 6/8] drm/i915/dp: add 128b/132b support to link status checks
On Tue, Jan 25, 2022 at 07:03:44PM +0200, Jani Nikula wrote:
> Abstract link status check to a function that takes 128b/132b and 8b/10b
> into account, and use it. Also dump link status on failures.
>
> Cc: Uma Shankar
> Cc: Ville Syrjälä
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 39 ++-
> .../drm/i915/display/intel_dp_link_training.c | 2 +-
> .../drm/i915/display/intel_dp_link_training.h | 4 ++
> 3 files changed, 34 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 4d4579a301f6..80fedd0e6212 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3628,6 +3628,32 @@ static void intel_dp_handle_test_request(struct
> intel_dp *intel_dp)
> "Could not write test response to sink\n");
> }
>
> +static bool intel_dp_link_ok(struct intel_dp *intel_dp,
> + u8 link_status[DP_LINK_STATUS_SIZE])
> +{
> + struct intel_encoder *encoder = _to_dig_port(intel_dp)->base;
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + bool uhbr = intel_dp->link_rate >= 100;
> + bool ok;
> +
> + if (uhbr)
> + ok = drm_dp_128b132b_lane_channel_eq_done(link_status,
> + intel_dp->lane_count);
That will only check the eq done bits. I think we want to keep the
symbol locked checks as well.
> + else
> + ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
> +
> + if (ok)
> + return true;
> +
> + intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
> + drm_dbg_kms(>drm,
> + "[ENCODER:%d:%s] %s link not ok, retraining\n",
> + encoder->base.base.id, encoder->base.name,
> + uhbr ? "128b/132b" : "8b/10b");
> +
> + return false;
> +}
> +
> static void
> intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack)
> {
> @@ -3658,14 +3684,7 @@ static bool intel_dp_mst_link_status(struct intel_dp
> *intel_dp)
> return false;
> }
>
> - if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
> - drm_dbg_kms(>drm,
> - "[ENCODER:%d:%s] channel EQ not ok, retraining\n",
> - encoder->base.base.id, encoder->base.name);
> - return false;
> - }
> -
> - return true;
> + return intel_dp_link_ok(intel_dp, link_status);
> }
>
> /**
> @@ -3779,8 +3798,8 @@ intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
> intel_dp->lane_count))
> return false;
>
> - /* Retrain if Channel EQ or CR not ok */
> - return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
> + /* Retrain if link not ok */
> + return !intel_dp_link_ok(intel_dp, link_status);
> }
>
> static bool intel_dp_has_connector(struct intel_dp *intel_dp,
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 8bb6a296f421..1e41a560204a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -712,7 +712,7 @@ static bool intel_dp_adjust_request_changed(const struct
> intel_crtc_state *crtc_
> return false;
> }
>
> -static void
> +void
> intel_dp_dump_link_status(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy,
> const u8 link_status[DP_LINK_STATUS_SIZE])
> {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> index dbfb15705aaa..dc1556b46b85 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> @@ -29,6 +29,10 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp,
> void intel_dp_stop_link_train(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state);
>
> +void
> +intel_dp_dump_link_status(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy,
> + const u8 link_status[DP_LINK_STATUS_SIZE]);
> +
> /* Get the TPSx symbol type of the value programmed to
> DP_TRAINING_PATTERN_SET */
> static inline u8 intel_dp_training_pattern_symbol(u8 pattern)
> {
> --
> 2.30.2
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH 5/8] drm/i915/dp: rewrite DP 2.0 128b/132b link training based on errata
On Tue, Jan 25, 2022 at 07:03:43PM +0200, Jani Nikula wrote:
> +static bool
> +intel_dp_128b132b_lane_cds(struct intel_dp *intel_dp,
> +const struct intel_crtc_state *crtc_state,
> +int lttpr_count)
> +{
> + struct intel_encoder *encoder = _to_dig_port(intel_dp)->base;
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + u8 link_status[DP_LINK_STATUS_SIZE];
> + unsigned long deadline;
> +
> + if (drm_dp_dpcd_writeb(_dp->aux, DP_TRAINING_PATTERN_SET,
> +DP_TRAINING_PATTERN_2_CDS) != 1) {
> + drm_err(>drm,
> + "[ENCODER:%d:%s] Failed to start 128b/132b TPS2 CDS\n",
> + encoder->base.base.id, encoder->base.name);
> + return false;
> + }
> +
> + deadline = jiffies + msecs_to_jiffies((lttpr_count + 1) * 20);
> + for (;;) {
> + usleep_range(2000, 3000);
> +
> + if (drm_dp_dpcd_read_link_status(_dp->aux, link_status) <
> 0) {
> + drm_err(>drm,
> + "[ENCODER:%d:%s] Failed to read link status\n",
> + encoder->base.base.id, encoder->base.name);
> + return false;
> + }
> +
> + if (drm_dp_128b132b_cds_interlane_align_done(link_status) &&
> + drm_dp_128b132b_lane_symbol_locked(link_status,
> crtc_state->lane_count)) {
I'm thinkin we want to check for both eq done and symbol locked here,
just like we do with 8b10b.
> + drm_dbg_kms(>drm,
> + "[ENCODER:%d:%s] CDS interlane align
> done\n",
> + encoder->base.base.id, encoder->base.name);
> + break;
> + }
> +
> + if (drm_dp_128b132b_link_training_failed(link_status)) {
> + intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX,
> link_status);
> + drm_err(>drm,
> + "[ENCODER:%d:%s] Downstream link training
> failure\n",
> + encoder->base.base.id, encoder->base.name);
> + return false;
> + }
> +
> + if (time_after(jiffies, deadline)) {
> + intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX,
> link_status);
> + drm_err(>drm,
> + "[ENCODER:%d:%s] CDS timeout\n",
> + encoder->base.base.id, encoder->base.name);
> + return false;
> + }
> + }
> +
> + /* FIXME: Should DP_TRAINING_PATTERN_DISABLE be written first? */
> + if (intel_dp->set_idle_link_train)
> + intel_dp->set_idle_link_train(intel_dp, crtc_state);
> +
> + return true;
> +}
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH 01/19] dma-buf-map: Add read/write helpers
On Thu, Jan 27, 2022 at 08:24:04AM +0100, Christian König wrote:
> Am 26.01.22 um 21:36 schrieb Lucas De Marchi:
> > In certain situations it's useful to be able to read or write to an
> > offset that is calculated by having the memory layout given by a struct
> > declaration. Usually we are going to read/write a u8, u16, u32 or u64.
> >
> > Add a pair of macros dma_buf_map_read_field()/dma_buf_map_write_field()
> > to calculate the offset of a struct member and memcpy the data from/to
> > the dma_buf_map. We could use readb, readw, readl, readq and the write*
> > counterparts, however due to alignment issues this may not work on all
> > architectures. If alignment needs to be checked to call the right
> > function, it's not possible to decide at compile-time which function to
> > call: so just leave the decision to the memcpy function that will do
> > exactly that on IO memory or dereference the pointer.
> >
> > Cc: Sumit Semwal
> > Cc: Christian König
> > Cc: linux-me...@vger.kernel.org
> > Cc: dri-de...@lists.freedesktop.org
> > Cc: linaro-mm-...@lists.linaro.org
> > Cc: linux-ker...@vger.kernel.org
> > Signed-off-by: Lucas De Marchi
> > ---
> > include/linux/dma-buf-map.h | 81 +
> > 1 file changed, 81 insertions(+)
> >
> > diff --git a/include/linux/dma-buf-map.h b/include/linux/dma-buf-map.h
> > index 19fa0b5ae5ec..65e927d9ce33 100644
> > --- a/include/linux/dma-buf-map.h
> > +++ b/include/linux/dma-buf-map.h
> > @@ -6,6 +6,7 @@
> > #ifndef __DMA_BUF_MAP_H__
> > #define __DMA_BUF_MAP_H__
> > +#include
> > #include
> > #include
> > @@ -229,6 +230,46 @@ static inline void dma_buf_map_clear(struct
> > dma_buf_map *map)
> > }
> > }
> > +/**
> > + * dma_buf_map_memcpy_to_offset - Memcpy into offset of dma-buf mapping
> > + * @dst: The dma-buf mapping structure
> > + * @offset:The offset from which to copy
> > + * @src: The source buffer
> > + * @len: The number of byte in src
> > + *
> > + * Copies data into a dma-buf mapping with an offset. The source buffer is
> > in
> > + * system memory. Depending on the buffer's location, the helper picks the
> > + * correct method of accessing the memory.
> > + */
> > +static inline void dma_buf_map_memcpy_to_offset(struct dma_buf_map *dst,
> > size_t offset,
> > + const void *src, size_t len)
> > +{
> > + if (dst->is_iomem)
> > + memcpy_toio(dst->vaddr_iomem + offset, src, len);
> > + else
> > + memcpy(dst->vaddr + offset, src, len);
> > +}
> > +
> > +/**
> > + * dma_buf_map_memcpy_from_offset - Memcpy from offset of dma-buf mapping
> > into system memory
> > + * @dst: Destination in system memory
> > + * @src: The dma-buf mapping structure
> > + * @src: The offset from which to copy
> > + * @len: The number of byte in src
> > + *
> > + * Copies data from a dma-buf mapping with an offset. The dest buffer is in
> > + * system memory. Depending on the mapping location, the helper picks the
> > + * correct method of accessing the memory.
> > + */
> > +static inline void dma_buf_map_memcpy_from_offset(void *dst, const struct
> > dma_buf_map *src,
> > + size_t offset, size_t len)
> > +{
> > + if (src->is_iomem)
> > + memcpy_fromio(dst, src->vaddr_iomem + offset, len);
> > + else
> > + memcpy(dst, src->vaddr + offset, len);
> > +}
> > +
>
> Well that's certainly a valid use case, but I suggest to change the
> implementation of the existing functions to call the new ones with offset=0.
>
> This way we only have one implementation.
>
Trivial - but agree with Christian that is a good cleanup.
> > /**
> >* dma_buf_map_memcpy_to - Memcpy into dma-buf mapping
> >* @dst: The dma-buf mapping structure
> > @@ -263,4 +304,44 @@ static inline void dma_buf_map_incr(struct dma_buf_map
> > *map, size_t incr)
> > map->vaddr += incr;
> > }
> > +/**
> > + * dma_buf_map_read_field - Read struct member from dma-buf mapping with
> > + * arbitrary size and handling un-aligned accesses
> > + *
> > + * @map__: The dma-buf mapping structure
> > + * @type__:The struct to be used containing the field to read
> > + * @field__: Member from struct we want to read
> > + *
> > + * Read a value from dma-buf mapping calculating the offset and size: this
> > assumes
> > + * the dma-buf mapping is aligned with a a struct type__. A single u8,
> > u16, u32
> > + * or u64 can be read, based on the offset and size of type__.field__.
> > + */
> > +#define dma_buf_map_read_field(map__, type__, field__) ({
> > \
> > + type__ *t__;
> > \
> > + typeof(t__->field__) val__;
> > \
> > + dma_buf_map_memcpy_from_offset(__, map__, offsetof(type__,
> > field__),\
> > +
Re: [Intel-gfx] [PATCH 3/8] drm/dp: add some new DPCD macros from DP 2.0 E11
On Tue, Jan 25, 2022 at 07:03:41PM +0200, Jani Nikula wrote:
> Add some of the new additions from DP 2.0 E11.
>
> Cc: Uma Shankar
> Cc: Ville Syrjälä
> Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
> ---
> include/drm/dp/drm_dp_helper.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/include/drm/dp/drm_dp_helper.h b/include/drm/dp/drm_dp_helper.h
> index c499d735b992..69487bd8ed56 100644
> --- a/include/drm/dp/drm_dp_helper.h
> +++ b/include/drm/dp/drm_dp_helper.h
> @@ -560,6 +560,7 @@ struct drm_panel;
> # define DP_TRAINING_PATTERN_DISABLE 0
> # define DP_TRAINING_PATTERN_1 1
> # define DP_TRAINING_PATTERN_2 2
> +# define DP_TRAINING_PATTERN_2_CDS 3 /* 2.0 E11 */
> # define DP_TRAINING_PATTERN_3 3 /* 1.2 */
> # define DP_TRAINING_PATTERN_4 7 /* 1.4 */
> # define DP_TRAINING_PATTERN_MASK0x3
> @@ -1350,6 +1351,7 @@ struct drm_panel;
> # define DP_PHY_REPEATER_128B132B_SUPPORTED (1 << 0)
> /* See DP_128B132B_SUPPORTED_LINK_RATES for values */
> #define DP_PHY_REPEATER_128B132B_RATES 0xf0007 /*
> 2.0 */
> +#define DP_PHY_REPEATER_EQ_DONE 0xf0008 /* 2.0
> E11 */
Wonder if we should look at that at some point? The spec doesn't really
say so. Or maybe we should just dump it out of the link training failed?
>
> enum drm_dp_phy {
> DP_PHY_DPRX,
> --
> 2.30.2
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH 1/8] drm/dp: add drm_dp_128b132b_read_aux_rd_interval()
On Tue, Jan 25, 2022 at 07:03:39PM +0200, Jani Nikula wrote:
> The DP 2.0 errata changes DP_128B132B_TRAINING_AUX_RD_INTERVAL (DPCD
> 0x2216) completely. Add a new function to read that. Follow-up will need
> to clean up existing functions.
>
> v2: fix reversed interpretation of bit 7 meaning (Uma)
>
> Cc: Uma Shankar
> Cc: Ville Syrjälä
> Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/dp/drm_dp.c| 20
> include/drm/dp/drm_dp_helper.h | 3 +++
> 2 files changed, 23 insertions(+)
>
> diff --git a/drivers/gpu/drm/dp/drm_dp.c b/drivers/gpu/drm/dp/drm_dp.c
> index 6d43325acca5..52c6da510142 100644
> --- a/drivers/gpu/drm/dp/drm_dp.c
> +++ b/drivers/gpu/drm/dp/drm_dp.c
> @@ -281,6 +281,26 @@ int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux,
> const u8 dpcd[DP_RECEIV
> }
> EXPORT_SYMBOL(drm_dp_read_channel_eq_delay);
>
> +/* Per DP 2.0 Errata */
> +int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux)
> +{
> + int unit;
> + u8 val;
> +
> + if (drm_dp_dpcd_readb(aux, DP_128B132B_TRAINING_AUX_RD_INTERVAL, )
> != 1) {
> + drm_err(aux->drm_dev, "%s: failed rd interval read\n",
> + aux->name);
> + /* default to max */
> + val = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK;
> + }
> +
> + unit = (val & DP_128B132B_TRAINING_AUX_RD_INTERVAL_1MS_UNIT) ? 1 : 2;
> + val &= DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK;
> +
> + return (val + 1) * unit * 1000;
> +}
> +EXPORT_SYMBOL(drm_dp_128b132b_read_aux_rd_interval);
> +
> void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux,
> const u8 dpcd[DP_RECEIVER_CAP_SIZE])
> {
> diff --git a/include/drm/dp/drm_dp_helper.h b/include/drm/dp/drm_dp_helper.h
> index 98d020835b49..aa73dfc817ff 100644
> --- a/include/drm/dp/drm_dp_helper.h
> +++ b/include/drm/dp/drm_dp_helper.h
> @@ -1112,6 +1112,7 @@ struct drm_panel;
> # define DP_UHBR13_5 (1 << 2)
>
> #define DP_128B132B_TRAINING_AUX_RD_INTERVAL0x2216 /*
> 2.0 */
> +# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_1MS_UNIT (1 << 7)
> # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f
> # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_400_US0x00
> # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_4_MS 0x01
> @@ -1549,6 +1550,8 @@ void drm_dp_link_train_channel_eq_delay(const struct
> drm_dp_aux *aux,
> void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
> const u8
> caps[DP_LTTPR_PHY_CAP_SIZE]);
>
> +int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux);
> +
> u8 drm_dp_link_rate_to_bw_code(int link_rate);
> int drm_dp_bw_code_to_link_rate(u8 link_bw);
>
> --
> 2.30.2
--
Ville Syrjälä
Intel
Re: [Intel-gfx] mmotm 2022-01-26-21-04 uploaded (gpu/drm/i915/i915_gem_evict.h)
On 1/26/22 21:04, a...@linux-foundation.org wrote: > The mm-of-the-moment snapshot 2022-01-26-21-04 has been uploaded to > >https://www.ozlabs.org/~akpm/mmotm/ > > mmotm-readme.txt says > > README for mm-of-the-moment: > > https://www.ozlabs.org/~akpm/mmotm/ > > This is a snapshot of my -mm patch queue. Uploaded at random hopefully > more than once a week. > > You will need quilt to apply these patches to the latest Linus release (5.x > or 5.x-rcY). The series file is in broken-out.tar.gz and is duplicated in > https://ozlabs.org/~akpm/mmotm/series > > The file broken-out.tar.gz contains two datestamp files: .DATE and > .DATE--mm-dd-hh-mm-ss. Both contain the string -mm-dd-hh-mm-ss, > followed by the base kernel version against which this patch series is to > be applied. on x86_64: (from linux-next.patch) HDRTEST drivers/gpu/drm/i915/i915_gem_evict.h In file included from :0:0: ./../drivers/gpu/drm/i915/i915_gem_evict.h:15:15: error: ‘struct i915_gem_ww_ctx’ declared inside parameter list will not be visible outside of this definition or declaration [-Werror] struct i915_gem_ww_ctx *ww, ^~~ ./../drivers/gpu/drm/i915/i915_gem_evict.h:21:14: error: ‘struct i915_gem_ww_ctx’ declared inside parameter list will not be visible outside of this definition or declaration [-Werror] struct i915_gem_ww_ctx *ww, ^~~ ./../drivers/gpu/drm/i915/i915_gem_evict.h:25:16: error: ‘struct i915_gem_ww_ctx’ declared inside parameter list will not be visible outside of this definition or declaration [-Werror] struct i915_gem_ww_ctx *ww); ^~~ cc1: all warnings being treated as errors -- ~Randy
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v10,1/5] drm: improve drm_buddy_alloc function
== Series Details == Series: series starting with [v10,1/5] drm: improve drm_buddy_alloc function URL : https://patchwork.freedesktop.org/series/99382/ State : success == Summary == CI Bug Log - changes from CI_DRM_11147_full -> Patchwork_22117_full Summary --- **SUCCESS** No regressions found. Participating hosts (10 -> 10) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_22117_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-massive: - shard-skl: NOTRUN -> [DMESG-WARN][1] ([i915#4991]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/shard-skl2/igt@gem_cre...@create-massive.html * igt@gem_ctx_persistence@legacy-engines-queued: - shard-snb: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1099]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/shard-snb6/igt@gem_ctx_persiste...@legacy-engines-queued.html * igt@gem_eio@in-flight-immediate: - shard-tglb: [PASS][3] -> [TIMEOUT][4] ([i915#3063]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11147/shard-tglb1/igt@gem_...@in-flight-immediate.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/shard-tglb5/igt@gem_...@in-flight-immediate.html * igt@gem_exec_capture@pi@vcs0: - shard-skl: NOTRUN -> [INCOMPLETE][5] ([i915#4547]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/shard-skl6/igt@gem_exec_capture@p...@vcs0.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-kbl: NOTRUN -> [FAIL][6] ([i915#2842]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/shard-kbl6/igt@gem_exec_fair@basic-none-s...@rcs0.html * igt@gem_exec_fair@basic-none@vecs0: - shard-apl: [PASS][7] -> [FAIL][8] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11147/shard-apl8/igt@gem_exec_fair@basic-n...@vecs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/shard-apl8/igt@gem_exec_fair@basic-n...@vecs0.html - shard-glk: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11147/shard-glk5/igt@gem_exec_fair@basic-n...@vecs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/shard-glk4/igt@gem_exec_fair@basic-n...@vecs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-kbl: [PASS][11] -> [FAIL][12] ([i915#2842]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11147/shard-kbl1/igt@gem_exec_fair@basic-pace-s...@rcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/shard-kbl4/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-tglb: NOTRUN -> [FAIL][13] ([i915#2842]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/shard-tglb3/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_lmem_swapping@basic: - shard-kbl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/shard-kbl1/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@heavy-random: - shard-glk: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/shard-glk7/igt@gem_lmem_swapp...@heavy-random.html * igt@gem_lmem_swapping@parallel-multi: - shard-tglb: NOTRUN -> [SKIP][16] ([i915#4613]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/shard-tglb3/igt@gem_lmem_swapp...@parallel-multi.html * igt@gem_lmem_swapping@parallel-random: - shard-apl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/shard-apl8/igt@gem_lmem_swapp...@parallel-random.html * igt@gem_lmem_swapping@parallel-random-engines: - shard-skl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/shard-skl10/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_pwrite@basic-exhaustion: - shard-snb: NOTRUN -> [WARN][19] ([i915#2658]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/shard-snb6/igt@gem_pwr...@basic-exhaustion.html * igt@gem_pxp@create-regular-context-1: - shard-tglb: NOTRUN -> [SKIP][20] ([i915#4270]) +1 similar issue [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/shard-tglb3/igt@gem_...@create-regular-context-1.html * igt@gem_pxp@verify-pxp-execution-after-suspend-resume: - shard-iclb: NOTRUN -> [SKIP][21] ([i915#4270]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/shard-iclb7/igt@gem_...@verify-pxp-execution-after-suspend-resume.html *
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/guc: Refactor ADS access to use dma_buf_map
== Series Details == Series: drm/i915/guc: Refactor ADS access to use dma_buf_map URL : https://patchwork.freedesktop.org/series/99378/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11147_full -> Patchwork_22116_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22116_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22116_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 10) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22116_full: ### IGT changes ### Possible regressions * igt@i915_pm_rpm@modeset-lpsp-stress: - shard-iclb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11147/shard-iclb7/igt@i915_pm_...@modeset-lpsp-stress.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/shard-iclb4/igt@i915_pm_...@modeset-lpsp-stress.html Known issues Here are the changes found in Patchwork_22116_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@legacy-engines-queued: - shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/shard-snb6/igt@gem_ctx_persiste...@legacy-engines-queued.html * igt@gem_eio@unwedge-stress: - shard-iclb: [PASS][4] -> [TIMEOUT][5] ([i915#2481] / [i915#3070]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11147/shard-iclb2/igt@gem_...@unwedge-stress.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/shard-iclb7/igt@gem_...@unwedge-stress.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-tglb: NOTRUN -> [FAIL][6] ([i915#2842]) +1 similar issue [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/shard-tglb2/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-kbl: [PASS][7] -> [FAIL][8] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11147/shard-kbl6/igt@gem_exec_fair@basic-p...@vcs1.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/shard-kbl7/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_suspend@basic-s3@smem: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#180]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11147/shard-apl2/igt@gem_exec_suspend@basic...@smem.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/shard-apl3/igt@gem_exec_suspend@basic...@smem.html * igt@gem_exec_whisper@basic-fds-forked-all: - shard-glk: [PASS][11] -> [DMESG-WARN][12] ([i915#118]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11147/shard-glk1/igt@gem_exec_whis...@basic-fds-forked-all.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/shard-glk4/igt@gem_exec_whis...@basic-fds-forked-all.html * igt@gem_lmem_swapping@basic: - shard-kbl: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4613]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/shard-kbl6/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@heavy-random: - shard-glk: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/shard-glk8/igt@gem_lmem_swapp...@heavy-random.html * igt@gem_lmem_swapping@parallel-multi: - shard-tglb: NOTRUN -> [SKIP][15] ([i915#4613]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/shard-tglb8/igt@gem_lmem_swapp...@parallel-multi.html * igt@gem_pwrite@basic-exhaustion: - shard-snb: NOTRUN -> [WARN][16] ([i915#2658]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/shard-snb6/igt@gem_pwr...@basic-exhaustion.html * igt@gem_pxp@create-regular-context-1: - shard-tglb: NOTRUN -> [SKIP][17] ([i915#4270]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/shard-tglb8/igt@gem_...@create-regular-context-1.html * igt@gem_pxp@verify-pxp-execution-after-suspend-resume: - shard-iclb: NOTRUN -> [SKIP][18] ([i915#4270]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/shard-iclb7/igt@gem_...@verify-pxp-execution-after-suspend-resume.html * igt@gem_softpin@allocator-evict-all-engines: - shard-glk: [PASS][19] -> [FAIL][20] ([i915#4171]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11147/shard-glk5/igt@gem_soft...@allocator-evict-all-engines.html [20]:
Re: [Intel-gfx] [PATCH 16/19] drm/i915/guc: Use a single pass to calculate regset
Hi Lucas,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-tip/drm-tip]
[also build test ERROR on next-20220125]
[cannot apply to drm-intel/for-linux-next drm-exynos/exynos-drm-next
drm/drm-next tegra-drm/drm/tegra/for-next linus/master airlied/drm-next
v5.17-rc1]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Lucas-De-Marchi/drm-i915-guc-Refactor-ADS-access-to-use-dma_buf_map/20220127-043912
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: i386-allyesconfig
(https://download.01.org/0day-ci/archive/20220127/202201271208.kelpe3mn-...@intel.com/config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
#
https://github.com/0day-ci/linux/commit/313757d9ed833acea4ee2bb0e3f3565d6efcf3cc
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review
Lucas-De-Marchi/drm-i915-guc-Refactor-ADS-access-to-use-dma_buf_map/20220127-043912
git checkout 313757d9ed833acea4ee2bb0e3f3565d6efcf3cc
# save the config file to linux build tree
mkdir build_dir
make W=1 O=build_dir ARCH=i386 SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All errors (new ones prefixed by >>):
In file included from include/drm/drm_mm.h:51,
from drivers/gpu/drm/i915/i915_vma.h:31,
from drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h:13,
from drivers/gpu/drm/i915/gt/uc/intel_guc.h:20,
from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
from drivers/gpu/drm/i915/gt/intel_gt_types.h:18,
from drivers/gpu/drm/i915/gt/intel_gt.h:10,
from drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c:9:
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c: In function
'guc_mmio_reg_state_create':
>> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c:369:38: error: format '%lu'
>> expects argument of type 'long unsigned int', but argument 4 has type 'u32'
>> {aka 'unsigned int'} [-Werror=format=]
369 | drm_dbg(_to_gt(guc)->i915->drm, "Used %lu KB for temporary ADS
regset\n",
|
^~~~
370 | (temp_set.storage_max * sizeof(struct guc_mmio_reg)) >> 10);
| ~~
||
|u32 {aka
unsigned int}
include/drm/drm_print.h:461:56: note: in definition of macro 'drm_dbg'
461 | drm_dev_dbg((drm) ? (drm)->dev : NULL, DRM_UT_DRIVER, fmt,
##__VA_ARGS__)
|^~~
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c:369:46: note: format string is
defined here
369 | drm_dbg(_to_gt(guc)->i915->drm, "Used %lu KB for temporary ADS
regset\n",
|~~^
| |
| long unsigned int
|%u
cc1: all warnings being treated as errors
vim +369 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
348
349 static long guc_mmio_reg_state_create(struct intel_guc *guc)
350 {
351 struct intel_gt *gt = guc_to_gt(guc);
352 struct intel_engine_cs *engine;
353 enum intel_engine_id id;
354 struct temp_regset temp_set = {};
355 long total = 0;
356
357 for_each_engine(engine, gt, id) {
358 u32 used = temp_set.storage_used;
359
360 if (guc_mmio_regset_init(_set, engine) < 0)
361 return -1;
362
363 guc->ads_regset_count[id] = temp_set.storage_used -
used;
364 total += guc->ads_regset_count[id];
365 }
366
367 guc->ads_regset = temp_set.storage;
368
> 369 drm_dbg(_to_gt(guc)->i915->drm, "Used %lu KB for temporary
> ADS regset\n",
370 (temp_set.storage_max * sizeof(struct guc_mmio_reg)) >>
10);
371
372 return total * sizeof(struct guc_mmio_reg);
373 }
374
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
Re: [Intel-gfx] [PATCH v5 06/10] drm/i915/guc: Update GuC's log-buffer-state access for error capture.
As per the rev 5 CI results between this patch and patch7, i have introduced a lockdep splat bug, i shall fix that in the next rev. ...alan On Wed, 2022-01-26 at 02:48 -0800, Alan Previn wrote: > GuC log buffer regions for debug-log-events, crash-dumps and > error-state-capture are all a single bo allocation that includes > the guc_log_buffer_state structures. > > Since the error-capture region is accessed with high priority at non- > deterministic times (as part of gpu coredump) while the debug-log-event > region is populated and accessed with different priorities, timings and > consumers, let's split out separate locks for buffer-state accesses > of each region. > > Also, ensure a global mapping is made up front for the entire bo > throughout GuC operation so that dynamic mapping and unmapping isn't > required for error capture log access if relay-logging isn't running. > > Additionally, while here, make some readibility improvements: > 1. change previous function names with "capture_logs" to >"copy_debug_logs" to help make the distinction clearer. > 2. Update the guc log region mapping comments to order them >according to the enum definition as per the GuC interface. >
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/adlp: Fix TypeC PHY-ready status readout
== Series Details == Series: drm/i915/adlp: Fix TypeC PHY-ready status readout URL : https://patchwork.freedesktop.org/series/99359/ State : success == Summary == CI Bug Log - changes from CI_DRM_11145 -> Patchwork_22111 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/index.html Participating hosts (46 -> 43) -- Additional (1): fi-pnv-d510 Missing(4): fi-ctg-p8600 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u Known issues Here are the changes found in Patchwork_22111 that come from known issues: ### CI changes ### Possible fixes * boot: - fi-ilk-650: [FAIL][1] -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/fi-ilk-650/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-ilk-650/boot.html ### IGT changes ### Issues hit * igt@amdgpu/amd_cs_nop@nop-compute0: - fi-ilk-650: NOTRUN -> [SKIP][3] ([fdo#109271]) +39 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-ilk-650/igt@amdgpu/amd_cs_...@nop-compute0.html * igt@gem_exec_suspend@basic-s3@smem: - fi-bdw-5557u: [PASS][4] -> [INCOMPLETE][5] ([i915#146]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html * igt@gem_huc_copy@huc-copy: - fi-skl-6600u: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#2190]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@verify-random: - fi-skl-6600u: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html * igt@i915_selftest@live@execlists: - fi-bsw-n3050: [PASS][8] -> [INCOMPLETE][9] ([i915#2940]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html * igt@i915_selftest@live@hangcheck: - fi-snb-2600:[PASS][10] -> [INCOMPLETE][11] ([i915#3921]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html * igt@i915_selftest@live@hugepages: - fi-rkl-guc: [PASS][12] -> [DMESG-WARN][13] ([i915#4993]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/fi-rkl-guc/igt@i915_selftest@l...@hugepages.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-rkl-guc/igt@i915_selftest@l...@hugepages.html * igt@kms_chamelium@dp-hpd-fast: - fi-ilk-650: NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827]) +8 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-ilk-650/igt@kms_chamel...@dp-hpd-fast.html * igt@kms_chamelium@vga-edid-read: - fi-skl-6600u: NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#111827]) +8 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-skl-6600u/igt@kms_chamel...@vga-edid-read.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-skl-6600u: NOTRUN -> [SKIP][16] ([fdo#109271]) +2 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-skl-6600u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-skl-6600u: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#533]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-skl-6600u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@kms_psr@primary_page_flip: - fi-skl-6600u: NOTRUN -> [FAIL][18] ([i915#4547]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-skl-6600u/igt@kms_psr@primary_page_flip.html * igt@prime_vgem@basic-userptr: - fi-pnv-d510:NOTRUN -> [SKIP][19] ([fdo#109271]) +57 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-pnv-d510/igt@prime_v...@basic-userptr.html * igt@runner@aborted: - fi-bsw-n3050: NOTRUN -> [FAIL][20] ([fdo#109271] / [i915#1436] / [i915#2722] / [i915#3428] / [i915#4312]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-bsw-n3050/igt@run...@aborted.html Possible fixes * igt@gem_flink_basic@bad-flink: - fi-skl-6600u: [FAIL][21] ([i915#4547]) -> [PASS][22] [21]:
Re: [Intel-gfx] [PATCH 2/2] drm/i915/pmu: Use existing uncore helper to read gpm_timestamp
Hi Umesh,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-tip/drm-tip]
[cannot apply to linus/master drm-intel/for-linux-next v5.17-rc1 next-20220125]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Umesh-Nerlige-Ramappa/drm-i915-pmu-Fix-KMD-and-GuC-race-on-accessing-busyness/20220127-081651
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: i386-randconfig-m021-20220124
(https://download.01.org/0day-ci/archive/20220127/202201271109.uuklswk3-...@intel.com/config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
#
https://github.com/0day-ci/linux/commit/2d74f201eae0c9ec06e6dc84b363089c0f190058
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review
Umesh-Nerlige-Ramappa/drm-i915-pmu-Fix-KMD-and-GuC-race-on-accessing-busyness/20220127-081651
git checkout 2d74f201eae0c9ec06e6dc84b363089c0f190058
# save the config file to linux build tree
mkdir build_dir
make W=1 O=build_dir ARCH=i386 SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All errors (new ones prefixed by >>):
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c: In function
'guc_update_pm_timestamp':
>> drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:1217:36: error: 'uncore'
>> undeclared (first use in this function)
1217 | gpm_ts = intel_uncore_read64_2x32(uncore, MISC_STATUS0,
MISC_STATUS1) >>
|^~
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:1217:36: note: each
undeclared identifier is reported only once for each function it appears in
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:1210:19: warning: unused
variable 'gt' [-Wunused-variable]
1210 | struct intel_gt *gt = guc_to_gt(guc);
| ^~
vim +/uncore +1217 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
1207
1208 static void guc_update_pm_timestamp(struct intel_guc *guc, ktime_t *now)
1209 {
1210 struct intel_gt *gt = guc_to_gt(guc);
1211 u32 gt_stamp_lo, gt_stamp_hi;
1212 u64 gpm_ts;
1213
1214 lockdep_assert_held(>timestamp.lock);
1215
1216 gt_stamp_hi = upper_32_bits(guc->timestamp.gt_stamp);
> 1217 gpm_ts = intel_uncore_read64_2x32(uncore, MISC_STATUS0,
> MISC_STATUS1) >>
1218 guc->timestamp.shift;
1219 gt_stamp_lo = lower_32_bits(gpm_ts);
1220 *now = ktime_get();
1221
1222 if (gt_stamp_lo < lower_32_bits(guc->timestamp.gt_stamp))
1223 gt_stamp_hi++;
1224
1225 guc->timestamp.gt_stamp = ((u64)gt_stamp_hi << 32) |
gt_stamp_lo;
1226 }
1227
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/pmu: Fix KMD and GuC race on accessing busyness
== Series Details == Series: series starting with [1/2] drm/i915/pmu: Fix KMD and GuC race on accessing busyness URL : https://patchwork.freedesktop.org/series/99388/ State : success == Summary == CI Bug Log - changes from CI_DRM_11148 -> Patchwork_22119 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22119/index.html Participating hosts (43 -> 42) -- Additional (3): fi-kbl-soraka fi-icl-u2 fi-pnv-d510 Missing(4): fi-ctg-p8600 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u Known issues Here are the changes found in Patchwork_22119 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@query-info: - fi-bsw-kefka: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22119/fi-bsw-kefka/igt@amdgpu/amd_ba...@query-info.html * igt@amdgpu/amd_cs_nop@fork-gfx0: - fi-icl-u2: NOTRUN -> [SKIP][2] ([fdo#109315]) +17 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22119/fi-icl-u2/igt@amdgpu/amd_cs_...@fork-gfx0.html * igt@amdgpu/amd_cs_nop@sync-gfx0: - fi-bsw-n3050: NOTRUN -> [SKIP][3] ([fdo#109271]) +17 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22119/fi-bsw-n3050/igt@amdgpu/amd_cs_...@sync-gfx0.html * igt@gem_exec_fence@basic-busy@bcs0: - fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271]) +8 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22119/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22119/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html - fi-icl-u2: NOTRUN -> [SKIP][6] ([i915#2190]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22119/fi-icl-u2/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-kbl-soraka: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22119/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@parallel-random-engines: - fi-icl-u2: NOTRUN -> [SKIP][8] ([i915#4613]) +3 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22119/fi-icl-u2/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][9] ([i915#1886] / [i915#2291]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22119/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@hangcheck: - bat-dg1-6: [PASS][10] -> [DMESG-FAIL][11] ([i915#4957]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11148/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22119/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-soraka: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22119/fi-kbl-soraka/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-icl-u2: NOTRUN -> [SKIP][13] ([fdo#111827]) +8 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22119/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-icl-u2: NOTRUN -> [SKIP][14] ([fdo#109278]) +2 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22119/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_force_connector_basic@force-load-detect: - fi-icl-u2: NOTRUN -> [SKIP][15] ([fdo#109285]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22119/fi-icl-u2/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-kbl-soraka: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#533]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22119/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@prime_vgem@basic-userptr: - fi-pnv-d510:NOTRUN -> [SKIP][17] ([fdo#109271]) +57 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22119/fi-pnv-d510/igt@prime_v...@basic-userptr.html - fi-icl-u2: NOTRUN -> [SKIP][18] ([i915#3301]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22119/fi-icl-u2/igt@prime_v...@basic-userptr.html Possible fixes * igt@i915_selftest@live@execlists: - fi-bsw-kefka:
Re: [Intel-gfx] [PATCH 16/19] drm/i915/guc: Use a single pass to calculate regset
Hi Lucas,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-tip/drm-tip]
[also build test WARNING on next-20220125]
[cannot apply to drm-intel/for-linux-next drm-exynos/exynos-drm-next
drm/drm-next tegra-drm/drm/tegra/for-next linus/master airlied/drm-next
v5.17-rc1]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Lucas-De-Marchi/drm-i915-guc-Refactor-ADS-access-to-use-dma_buf_map/20220127-043912
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: i386-randconfig-a011
(https://download.01.org/0day-ci/archive/20220127/202201270902.hcre2frp-...@intel.com/config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project
2a1b7aa016c0f4b5598806205bdfbab1ea2d92c4)
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
#
https://github.com/0day-ci/linux/commit/313757d9ed833acea4ee2bb0e3f3565d6efcf3cc
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review
Lucas-De-Marchi/drm-i915-guc-Refactor-ADS-access-to-use-dma_buf_map/20220127-043912
git checkout 313757d9ed833acea4ee2bb0e3f3565d6efcf3cc
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1
O=build_dir ARCH=i386 SHELL=/bin/bash drivers/gpu/drm/i915/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c:370:3: warning: format specifies
>> type 'unsigned long' but the argument has type 'unsigned int' [-Wformat]
(temp_set.storage_max * sizeof(struct guc_mmio_reg)) >> 10);
^~
include/drm/drm_print.h:461:63: note: expanded from macro 'drm_dbg'
drm_dev_dbg((drm) ? (drm)->dev : NULL, DRM_UT_DRIVER, fmt,
##__VA_ARGS__)
~~~
^~~
1 warning generated.
vim +370 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
348
349 static long guc_mmio_reg_state_create(struct intel_guc *guc)
350 {
351 struct intel_gt *gt = guc_to_gt(guc);
352 struct intel_engine_cs *engine;
353 enum intel_engine_id id;
354 struct temp_regset temp_set = {};
355 long total = 0;
356
357 for_each_engine(engine, gt, id) {
358 u32 used = temp_set.storage_used;
359
360 if (guc_mmio_regset_init(_set, engine) < 0)
361 return -1;
362
363 guc->ads_regset_count[id] = temp_set.storage_used -
used;
364 total += guc->ads_regset_count[id];
365 }
366
367 guc->ads_regset = temp_set.storage;
368
369 drm_dbg(_to_gt(guc)->i915->drm, "Used %lu KB for temporary
ADS regset\n",
> 370 (temp_set.storage_max * sizeof(struct guc_mmio_reg)) >>
> 10);
371
372 return total * sizeof(struct guc_mmio_reg);
373 }
374
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
[Intel-gfx] [PATCH 1/2] drm/i915/pmu: Fix KMD and GuC race on accessing busyness
GuC updates shared memory and KMD reads it. Since this is not
synchronized, we run into a race where the value read is inconsistent.
Sometimes the inconsistency is in reading the upper MSB bytes of the
last_switch_in value. 2 types of cases are seen - upper 8 bits are zero
and upper 24 bits are zero. Since these are non-zero values, it is
not trivial to determine validity of these values. Instead we read the
values multiple times until they are consistent. In test runs, 3
attempts results in consistent values. The upper bound is set to 6
attempts and may need to be tuned as per any new occurences.
Since the duration that gt is parked can vary, the patch also updates
the gt timestamp on unpark before starting the worker.
v2:
- Initialize i
- Use READ_ONCE to access engine record
Fixes: 77cdd054dd2c ("drm/i915/pmu: Connect engine busyness stats from GuC to
pmu")
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Alan Previn
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 58 +--
1 file changed, 54 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index db9615dcb0ec..4e9154cacc58 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1114,6 +1114,19 @@ __extend_last_switch(struct intel_guc *guc, u64
*prev_start, u32 new_start)
if (new_start == lower_32_bits(*prev_start))
return;
+ /*
+* When gt is unparked, we update the gt timestamp and start the ping
+* worker that updates the gt_stamp every POLL_TIME_CLKS. As long as gt
+* is unparked, all switched in contexts will have a start time that is
+* within +/- POLL_TIME_CLKS of the most recent gt_stamp.
+*
+* If neither gt_stamp nor new_start has rolled over, then the
+* gt_stamp_hi does not need to be adjusted, however if one of them has
+* rolled over, we need to adjust gt_stamp_hi accordingly.
+*
+* The below conditions address the cases of new_start rollover and
+* gt_stamp_last rollover respectively.
+*/
if (new_start < gt_stamp_last &&
(new_start - gt_stamp_last) <= POLL_TIME_CLKS)
gt_stamp_hi++;
@@ -1125,17 +1138,45 @@ __extend_last_switch(struct intel_guc *guc, u64
*prev_start, u32 new_start)
*prev_start = ((u64)gt_stamp_hi << 32) | new_start;
}
-static void guc_update_engine_gt_clks(struct intel_engine_cs *engine)
+/*
+ * GuC updates shared memory and KMD reads it. Since this is not synchronized,
+ * we run into a race where the value read is inconsistent. Sometimes the
+ * inconsistency is in reading the upper MSB bytes of the last_in value when
+ * this race occurs. 2 types of cases are seen - upper 8 bits are zero and
upper
+ * 24 bits are zero. Since these are non-zero values, it is non-trivial to
+ * determine validity of these values. Instead we read the values multiple
times
+ * until they are consistent. In test runs, 3 attempts results in consistent
+ * values. The upper bound is set to 6 attempts and may need to be tuned as per
+ * any new occurences.
+ */
+static void __get_engine_usage_record(struct intel_engine_cs *engine,
+ u32 *last_in, u32 *id, u32 *total)
{
struct guc_engine_usage_record *rec = intel_guc_engine_usage(engine);
+ int i = 0;
+
+ do {
+ *last_in = READ_ONCE(rec->last_switch_in_stamp);
+ *id = READ_ONCE(rec->current_context_index);
+ *total = READ_ONCE(rec->total_runtime);
+
+ if (READ_ONCE(rec->last_switch_in_stamp) == *last_in &&
+ READ_ONCE(rec->current_context_index) == *id &&
+ READ_ONCE(rec->total_runtime) == *total)
+ break;
+ } while (++i < 6);
+}
+
+static void guc_update_engine_gt_clks(struct intel_engine_cs *engine)
+{
struct intel_engine_guc_stats *stats = >stats.guc;
struct intel_guc *guc = >gt->uc.guc;
- u32 last_switch = rec->last_switch_in_stamp;
- u32 ctx_id = rec->current_context_index;
- u32 total = rec->total_runtime;
+ u32 last_switch, ctx_id, total;
lockdep_assert_held(>timestamp.lock);
+ __get_engine_usage_record(engine, _switch, _id, );
+
stats->running = ctx_id != ~0U && last_switch;
if (stats->running)
__extend_last_switch(guc, >start_gt_clk, last_switch);
@@ -1237,6 +1278,10 @@ static ktime_t guc_engine_busyness(struct
intel_engine_cs *engine, ktime_t *now)
if (!in_reset && intel_gt_pm_get_if_awake(gt)) {
stats_saved = *stats;
gt_stamp_saved = guc->timestamp.gt_stamp;
+ /*
+* Update gt_clks, then gt timestamp to simplify the 'gt_stamp -
+* start_gt_clk' calculation below for active
[Intel-gfx] [PATCH 2/2] drm/i915/pmu: Use existing uncore helper to read gpm_timestamp
Use intel_uncore_read64_2x32 to read upper and lower fields of the GPM
timestamp.
v2: Fix compile error
Signed-off-by: Umesh Nerlige Ramappa
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 17 ++---
1 file changed, 2 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 4e9154cacc58..6052148068d7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1205,20 +1205,6 @@ static u32 gpm_timestamp_shift(struct intel_gt *gt)
return 3 - shift;
}
-static u64 gpm_timestamp(struct intel_gt *gt)
-{
- u32 lo, hi, old_hi, loop = 0;
-
- hi = intel_uncore_read(gt->uncore, MISC_STATUS1);
- do {
- lo = intel_uncore_read(gt->uncore, MISC_STATUS0);
- old_hi = hi;
- hi = intel_uncore_read(gt->uncore, MISC_STATUS1);
- } while (old_hi != hi && loop++ < 2);
-
- return ((u64)hi << 32) | lo;
-}
-
static void guc_update_pm_timestamp(struct intel_guc *guc, ktime_t *now)
{
struct intel_gt *gt = guc_to_gt(guc);
@@ -1228,7 +1214,8 @@ static void guc_update_pm_timestamp(struct intel_guc
*guc, ktime_t *now)
lockdep_assert_held(>timestamp.lock);
gt_stamp_hi = upper_32_bits(guc->timestamp.gt_stamp);
- gpm_ts = gpm_timestamp(gt) >> guc->timestamp.shift;
+ gpm_ts = intel_uncore_read64_2x32(gt->uncore, MISC_STATUS0,
+ MISC_STATUS1) >> guc->timestamp.shift;
gt_stamp_lo = lower_32_bits(gpm_ts);
*now = ktime_get();
--
2.33.1
[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/2] drm/i915/pmu: Fix KMD and GuC race on accessing busyness
== Series Details == Series: series starting with [1/2] drm/i915/pmu: Fix KMD and GuC race on accessing busyness URL : https://patchwork.freedesktop.org/series/99386/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_submission.o drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c: In function ‘guc_update_pm_timestamp’: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:1217:36: error: ‘uncore’ undeclared (first use in this function); did you mean ‘node’? gpm_ts = intel_uncore_read64_2x32(uncore, MISC_STATUS0, MISC_STATUS1) >> ^~ node drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:1217:36: note: each undeclared identifier is reported only once for each function it appears in drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:1210:19: error: unused variable ‘gt’ [-Werror=unused-variable] struct intel_gt *gt = guc_to_gt(guc); ^~ cc1: all warnings being treated as errors scripts/Makefile.build:288: recipe for target 'drivers/gpu/drm/i915/gt/uc/intel_guc_submission.o' failed make[4]: *** [drivers/gpu/drm/i915/gt/uc/intel_guc_submission.o] Error 1 scripts/Makefile.build:550: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:550: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:550: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1831: recipe for target 'drivers' failed make: *** [drivers] Error 2
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Remove all frontbuffer tracking calls from the gem code
== Series Details == Series: drm/i915: Remove all frontbuffer tracking calls from the gem code URL : https://patchwork.freedesktop.org/series/99365/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11145_full -> Patchwork_22113_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22113_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22113_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 10) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22113_full: ### IGT changes ### Possible regressions * igt@i915_pm_dc@dc5-psr: - shard-iclb: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/shard-iclb7/igt@i915_pm...@dc5-psr.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22113/shard-iclb8/igt@i915_pm...@dc5-psr.html - shard-tglb: [PASS][3] -> [FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/shard-tglb5/igt@i915_pm...@dc5-psr.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22113/shard-tglb7/igt@i915_pm...@dc5-psr.html * igt@kms_plane@plane-position-hole-dpms@pipe-b-planes: - shard-tglb: [PASS][5] -> [INCOMPLETE][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/shard-tglb1/igt@kms_plane@plane-position-hole-d...@pipe-b-planes.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22113/shard-tglb8/igt@kms_plane@plane-position-hole-d...@pipe-b-planes.html Known issues Here are the changes found in Patchwork_22113_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@preservation-s3@vcs0: - shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([i915#180]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/shard-kbl3/igt@gem_ctx_isolation@preservation...@vcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22113/shard-kbl4/igt@gem_ctx_isolation@preservation...@vcs0.html * igt@gem_ctx_persistence@legacy-engines-queued: - shard-snb: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#1099]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22113/shard-snb6/igt@gem_ctx_persiste...@legacy-engines-queued.html * igt@gem_exec_balancer@parallel-keep-submit-fence: - shard-iclb: [PASS][10] -> [SKIP][11] ([i915#4525]) +1 similar issue [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/shard-iclb2/igt@gem_exec_balan...@parallel-keep-submit-fence.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22113/shard-iclb6/igt@gem_exec_balan...@parallel-keep-submit-fence.html * igt@gem_exec_fair@basic-none@rcs0: - shard-glk: NOTRUN -> [FAIL][12] ([i915#2842]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22113/shard-glk9/igt@gem_exec_fair@basic-n...@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-iclb: NOTRUN -> [FAIL][13] ([i915#2842]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22113/shard-iclb3/igt@gem_exec_fair@basic-pace-s...@rcs0.html - shard-tglb: NOTRUN -> [FAIL][14] ([i915#2842]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22113/shard-tglb1/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_exec_whisper@basic-normal-all: - shard-glk: [PASS][15] -> [DMESG-WARN][16] ([i915#118]) +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/shard-glk2/igt@gem_exec_whis...@basic-normal-all.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22113/shard-glk7/igt@gem_exec_whis...@basic-normal-all.html * igt@gem_exec_whisper@basic-queues-all: - shard-glk: NOTRUN -> [DMESG-WARN][17] ([i915#118]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22113/shard-glk9/igt@gem_exec_whis...@basic-queues-all.html * igt@gem_lmem_swapping@basic: - shard-skl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22113/shard-skl4/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@parallel-random: - shard-apl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#4613]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22113/shard-apl1/igt@gem_lmem_swapp...@parallel-random.html * igt@gem_lmem_swapping@parallel-random-verify: - shard-kbl: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#4613]) +2 similar issues
Re: [Intel-gfx] [PATCH 16/19] drm/i915/guc: Use a single pass to calculate regset
Hi Lucas,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-tip/drm-tip]
[also build test WARNING on next-20220125]
[cannot apply to drm-intel/for-linux-next drm-exynos/exynos-drm-next
drm/drm-next tegra-drm/drm/tegra/for-next linus/master airlied/drm-next
v5.17-rc1]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Lucas-De-Marchi/drm-i915-guc-Refactor-ADS-access-to-use-dma_buf_map/20220127-043912
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: i386-randconfig-m021-20220124
(https://download.01.org/0day-ci/archive/20220127/202201270827.clihfdpe-...@intel.com/config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
#
https://github.com/0day-ci/linux/commit/313757d9ed833acea4ee2bb0e3f3565d6efcf3cc
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review
Lucas-De-Marchi/drm-i915-guc-Refactor-ADS-access-to-use-dma_buf_map/20220127-043912
git checkout 313757d9ed833acea4ee2bb0e3f3565d6efcf3cc
# save the config file to linux build tree
mkdir build_dir
make W=1 O=build_dir ARCH=i386 SHELL=/bin/bash drivers/gpu/drm/i915/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All warnings (new ones prefixed by >>):
In file included from include/drm/drm_mm.h:51,
from drivers/gpu/drm/i915/i915_vma.h:31,
from drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h:13,
from drivers/gpu/drm/i915/gt/uc/intel_guc.h:20,
from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
from drivers/gpu/drm/i915/gt/intel_gt_types.h:18,
from drivers/gpu/drm/i915/gt/intel_gt.h:10,
from drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c:9:
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c: In function
'guc_mmio_reg_state_create':
>> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c:369:38: warning: format '%lu'
>> expects argument of type 'long unsigned int', but argument 4 has type 'u32'
>> {aka 'unsigned int'} [-Wformat=]
369 | drm_dbg(_to_gt(guc)->i915->drm, "Used %lu KB for temporary ADS
regset\n",
|
^~~~
370 | (temp_set.storage_max * sizeof(struct guc_mmio_reg)) >> 10);
| ~~
||
|u32 {aka
unsigned int}
include/drm/drm_print.h:461:56: note: in definition of macro 'drm_dbg'
461 | drm_dev_dbg((drm) ? (drm)->dev : NULL, DRM_UT_DRIVER, fmt,
##__VA_ARGS__)
|^~~
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c:369:46: note: format string is
defined here
369 | drm_dbg(_to_gt(guc)->i915->drm, "Used %lu KB for temporary ADS
regset\n",
|~~^
| |
| long unsigned int
|%u
vim +369 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
348
349 static long guc_mmio_reg_state_create(struct intel_guc *guc)
350 {
351 struct intel_gt *gt = guc_to_gt(guc);
352 struct intel_engine_cs *engine;
353 enum intel_engine_id id;
354 struct temp_regset temp_set = {};
355 long total = 0;
356
357 for_each_engine(engine, gt, id) {
358 u32 used = temp_set.storage_used;
359
360 if (guc_mmio_regset_init(_set, engine) < 0)
361 return -1;
362
363 guc->ads_regset_count[id] = temp_set.storage_used -
used;
364 total += guc->ads_regset_count[id];
365 }
366
367 guc->ads_regset = temp_set.storage;
368
> 369 drm_dbg(_to_gt(guc)->i915->drm, "Used %lu KB for temporary
> ADS regset\n",
370 (temp_set.storage_max * sizeof(struct guc_mmio_reg)) >>
10);
371
372 return total * sizeof(struct guc_mmio_reg);
373 }
374
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v10,1/5] drm: improve drm_buddy_alloc function
== Series Details ==
Series: series starting with [v10,1/5] drm: improve drm_buddy_alloc function
URL : https://patchwork.freedesktop.org/series/99382/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11147 -> Patchwork_22117
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/index.html
Participating hosts (48 -> 41)
--
Missing(7): fi-bxt-dsi fi-bdw-5557u fi-hsw-4200u fi-icl-u2 fi-bsw-cyan
fi-ctg-p8600 fi-bdw-samus
Known issues
Here are the changes found in Patchwork_22117 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600:NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html
* igt@gem_huc_copy@huc-copy:
- fi-skl-6600u: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@verify-random:
- fi-skl-6600u: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html
* igt@i915_selftest@live:
- fi-skl-6600u: NOTRUN -> [FAIL][4] ([i915#4547])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/fi-skl-6600u/igt@i915_selft...@live.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-5: [PASS][5] -> [DMESG-FAIL][6] ([i915#4494] /
[i915#4957])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11147/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
* igt@kms_chamelium@vga-edid-read:
- fi-skl-6600u: NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +8
similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/fi-skl-6600u/igt@kms_chamel...@vga-edid-read.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-skl-6600u: NOTRUN -> [SKIP][8] ([fdo#109271]) +3 similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/fi-skl-6600u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-skl-6600u: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#533])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/fi-skl-6600u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
* igt@runner@aborted:
- fi-skl-6600u: NOTRUN -> [FAIL][10] ([i915#1436] / [i915#4312])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/fi-skl-6600u/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@gt_pm:
- {fi-jsl-1}: [DMESG-FAIL][11] ([i915#1886]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11147/fi-jsl-1/igt@i915_selftest@live@gt_pm.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/fi-jsl-1/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[INCOMPLETE][13] ([i915#3921]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11147/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4898]: https://gitlab.freedesktop.org/drm/intel/issues/4898
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Build changes
-
* Linux: CI_DRM_11147 -> Patchwork_22117
CI-20190529: 20190529
CI_DRM_11147: ad57bf1ff13e1c4462f947398fbfb861f1b2e345 @
[Intel-gfx] [PATCH 2/2] drm/i915/pmu: Use existing uncore helper to read gpm_timestamp
Use intel_uncore_read64_2x32 to read upper and lower fields of the GPM
timestamp.
Signed-off-by: Umesh Nerlige Ramappa
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 17 ++---
1 file changed, 2 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 4e9154cacc58..0549b3edc4a2 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1205,20 +1205,6 @@ static u32 gpm_timestamp_shift(struct intel_gt *gt)
return 3 - shift;
}
-static u64 gpm_timestamp(struct intel_gt *gt)
-{
- u32 lo, hi, old_hi, loop = 0;
-
- hi = intel_uncore_read(gt->uncore, MISC_STATUS1);
- do {
- lo = intel_uncore_read(gt->uncore, MISC_STATUS0);
- old_hi = hi;
- hi = intel_uncore_read(gt->uncore, MISC_STATUS1);
- } while (old_hi != hi && loop++ < 2);
-
- return ((u64)hi << 32) | lo;
-}
-
static void guc_update_pm_timestamp(struct intel_guc *guc, ktime_t *now)
{
struct intel_gt *gt = guc_to_gt(guc);
@@ -1228,7 +1214,8 @@ static void guc_update_pm_timestamp(struct intel_guc
*guc, ktime_t *now)
lockdep_assert_held(>timestamp.lock);
gt_stamp_hi = upper_32_bits(guc->timestamp.gt_stamp);
- gpm_ts = gpm_timestamp(gt) >> guc->timestamp.shift;
+ gpm_ts = intel_uncore_read64_2x32(uncore, MISC_STATUS0, MISC_STATUS1) >>
+guc->timestamp.shift;
gt_stamp_lo = lower_32_bits(gpm_ts);
*now = ktime_get();
--
2.33.1
[Intel-gfx] [PATCH 1/2] drm/i915/pmu: Fix KMD and GuC race on accessing busyness
GuC updates shared memory and KMD reads it. Since this is not
synchronized, we run into a race where the value read is inconsistent.
Sometimes the inconsistency is in reading the upper MSB bytes of the
last_switch_in value. 2 types of cases are seen - upper 8 bits are zero
and upper 24 bits are zero. Since these are non-zero values, it is
not trivial to determine validity of these values. Instead we read the
values multiple times until they are consistent. In test runs, 3
attempts results in consistent values. The upper bound is set to 6
attempts and may need to be tuned as per any new occurences.
Since the duration that gt is parked can vary, the patch also updates
the gt timestamp on unpark before starting the worker.
v2:
- Initialize i
- Use READ_ONCE to access engine record
Fixes: 77cdd054dd2c ("drm/i915/pmu: Connect engine busyness stats from GuC to
pmu")
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Alan Previn
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 58 +--
1 file changed, 54 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index db9615dcb0ec..4e9154cacc58 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1114,6 +1114,19 @@ __extend_last_switch(struct intel_guc *guc, u64
*prev_start, u32 new_start)
if (new_start == lower_32_bits(*prev_start))
return;
+ /*
+* When gt is unparked, we update the gt timestamp and start the ping
+* worker that updates the gt_stamp every POLL_TIME_CLKS. As long as gt
+* is unparked, all switched in contexts will have a start time that is
+* within +/- POLL_TIME_CLKS of the most recent gt_stamp.
+*
+* If neither gt_stamp nor new_start has rolled over, then the
+* gt_stamp_hi does not need to be adjusted, however if one of them has
+* rolled over, we need to adjust gt_stamp_hi accordingly.
+*
+* The below conditions address the cases of new_start rollover and
+* gt_stamp_last rollover respectively.
+*/
if (new_start < gt_stamp_last &&
(new_start - gt_stamp_last) <= POLL_TIME_CLKS)
gt_stamp_hi++;
@@ -1125,17 +1138,45 @@ __extend_last_switch(struct intel_guc *guc, u64
*prev_start, u32 new_start)
*prev_start = ((u64)gt_stamp_hi << 32) | new_start;
}
-static void guc_update_engine_gt_clks(struct intel_engine_cs *engine)
+/*
+ * GuC updates shared memory and KMD reads it. Since this is not synchronized,
+ * we run into a race where the value read is inconsistent. Sometimes the
+ * inconsistency is in reading the upper MSB bytes of the last_in value when
+ * this race occurs. 2 types of cases are seen - upper 8 bits are zero and
upper
+ * 24 bits are zero. Since these are non-zero values, it is non-trivial to
+ * determine validity of these values. Instead we read the values multiple
times
+ * until they are consistent. In test runs, 3 attempts results in consistent
+ * values. The upper bound is set to 6 attempts and may need to be tuned as per
+ * any new occurences.
+ */
+static void __get_engine_usage_record(struct intel_engine_cs *engine,
+ u32 *last_in, u32 *id, u32 *total)
{
struct guc_engine_usage_record *rec = intel_guc_engine_usage(engine);
+ int i = 0;
+
+ do {
+ *last_in = READ_ONCE(rec->last_switch_in_stamp);
+ *id = READ_ONCE(rec->current_context_index);
+ *total = READ_ONCE(rec->total_runtime);
+
+ if (READ_ONCE(rec->last_switch_in_stamp) == *last_in &&
+ READ_ONCE(rec->current_context_index) == *id &&
+ READ_ONCE(rec->total_runtime) == *total)
+ break;
+ } while (++i < 6);
+}
+
+static void guc_update_engine_gt_clks(struct intel_engine_cs *engine)
+{
struct intel_engine_guc_stats *stats = >stats.guc;
struct intel_guc *guc = >gt->uc.guc;
- u32 last_switch = rec->last_switch_in_stamp;
- u32 ctx_id = rec->current_context_index;
- u32 total = rec->total_runtime;
+ u32 last_switch, ctx_id, total;
lockdep_assert_held(>timestamp.lock);
+ __get_engine_usage_record(engine, _switch, _id, );
+
stats->running = ctx_id != ~0U && last_switch;
if (stats->running)
__extend_last_switch(guc, >start_gt_clk, last_switch);
@@ -1237,6 +1278,10 @@ static ktime_t guc_engine_busyness(struct
intel_engine_cs *engine, ktime_t *now)
if (!in_reset && intel_gt_pm_get_if_awake(gt)) {
stats_saved = *stats;
gt_stamp_saved = guc->timestamp.gt_stamp;
+ /*
+* Update gt_clks, then gt timestamp to simplify the 'gt_stamp -
+* start_gt_clk' calculation below for active
[Intel-gfx] ✗ Fi.CI.IGT: failure for lib/string_helpers: Add a few string helpers (rev2)
== Series Details == Series: lib/string_helpers: Add a few string helpers (rev2) URL : https://patchwork.freedesktop.org/series/99030/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11145_full -> Patchwork_22110_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22110_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22110_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 10) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22110_full: ### IGT changes ### Possible regressions * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt: - shard-skl: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/shard-skl5/igt@kms_frontbuffer_track...@psr-1p-primscrn-pri-shrfb-draw-blt.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22110/shard-skl10/igt@kms_frontbuffer_track...@psr-1p-primscrn-pri-shrfb-draw-blt.html * igt@kms_vblank@pipe-c-query-busy-hang: - shard-tglb: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/shard-tglb3/igt@kms_vbl...@pipe-c-query-busy-hang.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22110/shard-tglb7/igt@kms_vbl...@pipe-c-query-busy-hang.html * igt@perf_pmu@busy-idle@rcs0: - shard-skl: [PASS][5] -> [FAIL][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/shard-skl4/igt@perf_pmu@busy-i...@rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22110/shard-skl1/igt@perf_pmu@busy-i...@rcs0.html Known issues Here are the changes found in Patchwork_22110_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@legacy-engines-queued: - shard-snb: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#1099]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22110/shard-snb7/igt@gem_ctx_persiste...@legacy-engines-queued.html * igt@gem_exec_balancer@parallel-keep-submit-fence: - shard-iclb: [PASS][8] -> [SKIP][9] ([i915#4525]) +1 similar issue [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/shard-iclb2/igt@gem_exec_balan...@parallel-keep-submit-fence.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22110/shard-iclb7/igt@gem_exec_balan...@parallel-keep-submit-fence.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-apl: [PASS][10] -> [FAIL][11] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/shard-apl2/igt@gem_exec_fair@basic-none-s...@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22110/shard-apl1/igt@gem_exec_fair@basic-none-s...@rcs0.html * igt@gem_exec_fair@basic-none@rcs0: - shard-glk: NOTRUN -> [FAIL][12] ([i915#2842]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22110/shard-glk1/igt@gem_exec_fair@basic-n...@rcs0.html * igt@gem_exec_fair@basic-none@vcs1: - shard-kbl: [PASS][13] -> [FAIL][14] ([i915#2842]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/shard-kbl3/igt@gem_exec_fair@basic-n...@vcs1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22110/shard-kbl6/igt@gem_exec_fair@basic-n...@vcs1.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [PASS][15] -> [FAIL][16] ([i915#2842]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/shard-glk4/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22110/shard-glk7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-iclb: NOTRUN -> [FAIL][17] ([i915#2842]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22110/shard-iclb4/igt@gem_exec_fair@basic-pace-s...@rcs0.html - shard-tglb: NOTRUN -> [FAIL][18] ([i915#2842]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22110/shard-tglb2/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_lmem_swapping@basic: - shard-skl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#4613]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22110/shard-skl4/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@parallel-random: - shard-apl: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#4613]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22110/shard-apl3/igt@gem_lmem_swapp...@parallel-random.html - shard-kbl:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v10,1/5] drm: improve drm_buddy_alloc function
== Series Details ==
Series: series starting with [v10,1/5] drm: improve drm_buddy_alloc function
URL : https://patchwork.freedesktop.org/series/99382/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c9a375384fb3 drm: improve drm_buddy_alloc function
-:383: WARNING:AVOID_BUG: Avoid crashing the kernel - try using WARN_ON &
recovery code rather than BUG() or BUG_ON()
#383: FILE: drivers/gpu/drm/drm_buddy.c:585:
+ BUG_ON(order > mm->max_order);
-:384: WARNING:AVOID_BUG: Avoid crashing the kernel - try using WARN_ON &
recovery code rather than BUG() or BUG_ON()
#384: FILE: drivers/gpu/drm/drm_buddy.c:586:
+ BUG_ON(order < min_order);
-:510: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#510: FILE: drivers/gpu/drm/i915/i915_ttm_buddy_manager.c:88:
+ err = drm_buddy_alloc_blocks(mm, (u64)place->fpfn << PAGE_SHIFT,
+ (u64)lpfn << PAGE_SHIFT,
total: 0 errors, 2 warnings, 1 checks, 506 lines checked
d007f812a25a drm: implement top-down allocation method
d01faa9bdacb drm: implement a method to free unused pages
69c19364e1f2 drm/amdgpu: move vram inline functions into a header
-:12: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#12:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 51 lines checked
9ce76c7fdbd5 drm/amdgpu: add drm buddy support to amdgpu
-:57: CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u32' over 'uint32_t'
#57: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h:41:
+ uint32_tmem_type;
-:338: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#338: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:325:
+ if (rsv->start <= start &&
+ (start < (rsv->start + rsv->size))) {
-:348: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#348: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:333:
+ if (rsv->start <= start &&
+ (start < (rsv->start + rsv->size))) {
-:414: CHECK:BRACES: Unbalanced braces around else statement
#414: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:387:
+ else {
-:447: WARNING:AVOID_BUG: Avoid crashing the kernel - try using WARN_ON &
recovery code rather than BUG() or BUG_ON()
#447: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:416:
+ BUG_ON(min_page_size < mm->chunk_size);
-:490: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#490: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:440:
+ r = drm_buddy_alloc_blocks(mm, (u64)place->fpfn << PAGE_SHIFT,
+ (u64)lpfn << PAGE_SHIFT,
total: 0 errors, 1 warnings, 5 checks, 594 lines checked
[Intel-gfx] ✗ Fi.CI.BUILD: warning for drm/i915/guc: Refactor ADS access to use dma_buf_map
== Series Details ==
Series: drm/i915/guc: Refactor ADS access to use dma_buf_map
URL : https://patchwork.freedesktop.org/series/99378/
State : warning
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_ads.o
In file included from ./include/drm/drm_mm.h:51,
from ./drivers/gpu/drm/i915/i915_vma.h:31,
from ./drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h:13,
from ./drivers/gpu/drm/i915/gt/uc/intel_guc.h:20,
from ./drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
from ./drivers/gpu/drm/i915/gt/intel_gt_types.h:18,
from ./drivers/gpu/drm/i915/gt/intel_gt.h:10,
from drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c:9:
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c: In function
‘guc_mmio_reg_state_create’:
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c:369:38: error: format ‘%lu’ expects
argument of type ‘long unsigned int’, but argument 4 has type ‘u32’ {aka
‘unsigned int’} [-Werror=format=]
drm_dbg(_to_gt(guc)->i915->drm, "Used %lu KB for temporary ADS regset\n",
^~~~
(temp_set.storage_max * sizeof(struct guc_mmio_reg)) >> 10);
~~
./include/drm/drm_print.h:461:56: note: in definition of macro ‘drm_dbg’
drm_dev_dbg((drm) ? (drm)->dev : NULL, DRM_UT_DRIVER, fmt, ##__VA_ARGS__)
^~~
cc1: all warnings being treated as errors
scripts/Makefile.build:288: recipe for target
'drivers/gpu/drm/i915/gt/uc/intel_guc_ads.o' failed
make[4]: *** [drivers/gpu/drm/i915/gt/uc/intel_guc_ads.o] Error 1
scripts/Makefile.build:550: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:550: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:550: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1831: recipe for target 'drivers' failed
make: *** [drivers] Error 2
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/build_32bit.log
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Refactor ADS access to use dma_buf_map
== Series Details ==
Series: drm/i915/guc: Refactor ADS access to use dma_buf_map
URL : https://patchwork.freedesktop.org/series/99378/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11147 -> Patchwork_22116
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/index.html
Participating hosts (48 -> 31)
--
Missing(17): fi-kbl-soraka fi-bxt-dsi fi-bdw-5557u fi-bsw-n3050
fi-hsw-4200u fi-glk-dsi fi-icl-u2 fi-bsw-cyan fi-apl-guc fi-snb-2520m
fi-ctg-p8600 fi-kbl-x1275 fi-kbl-8809g fi-elk-e7500 fi-bsw-kefka fi-bsw-nick
fi-bdw-samus
Known issues
Here are the changes found in Patchwork_22116 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600:NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html
* igt@gem_exec_suspend@basic-s3@smem:
- fi-skl-6600u: NOTRUN -> [INCOMPLETE][2] ([i915#4547])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html
* igt@runner@aborted:
- fi-pnv-d510:NOTRUN -> [FAIL][3] ([i915#2403] / [i915#4312])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/fi-pnv-d510/igt@run...@aborted.html
- fi-skl-6600u: NOTRUN -> [FAIL][4] ([i915#4312])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/fi-skl-6600u/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@gt_pm:
- {fi-jsl-1}: [DMESG-FAIL][5] ([i915#1886]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11147/fi-jsl-1/igt@i915_selftest@live@gt_pm.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/fi-jsl-1/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [DMESG-FAIL][7] ([i915#4494] / [i915#4957]) ->
[PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11147/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
- fi-snb-2600:[INCOMPLETE][9] ([i915#3921]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11147/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3194]: https://gitlab.freedesktop.org/drm/intel/issues/3194
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4898]: https://gitlab.freedesktop.org/drm/intel/issues/4898
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
Build changes
-
* Linux: CI_DRM_11147 -> Patchwork_22116
CI-20190529: 20190529
CI_DRM_11147: ad57bf1ff13e1c4462f947398fbfb861f1b2e345 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6335: 2b30115edd692b60d16cb10375730a87f51f0e37 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22116: 2788e054f9ce2eff704b9c331c3881bf035ee68f @
git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/Patchwork_22116/build_32bit.log
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_ads.o
In file included from ./include/drm/drm_mm.h:51,
from ./drivers/gpu/drm/i915/i915_vma.h:31,
from ./drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h:13,
from ./drivers/gpu/drm/i915/gt/uc/intel_guc.h:20,
from ./drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
from ./drivers/gpu/drm/i915/gt/intel_gt_types.h:18,
from ./drivers/gpu/drm/i915/gt/intel_gt.h:10,
from drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c:9:
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c: In function
‘guc_mmio_reg_state_create’:
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c:369:38: error: format ‘%lu’ expects
Re: [Intel-gfx] [PATCH 4/8] drm/i915: Use preempt_disable/enable_rt() where recommended
On Tue, Dec 14, 2021 at 3:03 PM Sebastian Andrzej Siewior <
bige...@linutronix.de> wrote:
> From: Mike Galbraith
>
> Mario Kleiner suggest in commit
> ad3543ede630f ("drm/intel: Push get_scanout_position() timestamping into
> kms driver.")
>
> a spots where preemption should be disabled on PREEMPT_RT. The
> difference is that on PREEMPT_RT the intel_uncore::lock disables neither
> preemption nor interrupts and so region remains preemptible.
>
>
Hi, first thank you for implementing these preempt disables according to
the markers i left long ago. And sorry for the rather late reply.
I had a look at the code, as of Linux 5.16, and did also a little test run
(of a standard kernel, not with PREEMPT_RT, only
CONFIG_PREEMPT_VOLUNTARY=y) on my Intel Kabylake GT2, so some thoughts:
The area covers only register reads and writes. The part that worries me
> is:
> - __intel_get_crtc_scanline() the worst case is 100us if no match is
> found.
>
This one can be a problem indeed on (maybe all?) modern Intel gpu's since
Haswell, ie. the last ~10 years. I was able to reproduce it on my Kabylake
Intel gpu.
Most of the time that for-loop with up to 100 repetitions (~ 100
udelay(1) + one mmio register read) (cfe.
https://elixir.bootlin.com/linux/v5.17-rc1/source/drivers/gpu/drm/i915/i915_irq.c#L856)
will not execute, because most of the time that function gets called from
the vblank irq handler and then that trigger condition (if
(HAS_DDI(dev_priv) && !position)) is not true. However, it also gets called
as part of power-saving on behalf of userspace context, whenever the
desktop graphics goes idle for two video refresh cycles. If the desktop
shows graphics activity again, and vblank interrupts need to get reenabled,
the probability of hitting that case is then ~1-4% depending on video mode.
How many loops it runs also varies.
On my little Intel(R) Core(TM) i5-8250U CPU machine with a mostly idle
desktop, I observed about one hit every couple of seconds of regular use,
and each hit took between 125 usecs and almost 250 usecs. I guess udelay(1)
can take a bit longer than 1 usec?
So that's too much for preempt-rt. What one could do is the following:
1. In the for-loop in __intel_get_crtc_scanline(), add a preempt_enable()
before the udelay(1); and a preempt_disable() again after it. Or
potentially around the whole for-loop if the overhead of
preempt_en/disable() is significant?
2. In intel_get_crtc_scanline() also wrap the call to
__intel_get_crtc_scanline() into a preempt_disable() and preempt_enable(),
so we can be sure that __intel_get_crtc_scanline() always gets called with
preemption disabled.
Why should this work ok'ish? The point of the original preempt disable
inside i915_get_crtc_scanoutpos
is that those two *stime = ktime_get() and *etime = ktime_get() clock
queries happen as close to the scanout position query as possible to get a
small confidence interval for when exactly the scanoutpos was
read/determined from the display hardware. error = (etime - stime) is the
error margin. If that margin becomes greater than 20 usecs, then the
higher-level code will consider the measurement invalid and repeat the
whole procedure up to 3 times before giving up.
Normally, in my experience with different graphics chips, one would observe
error < 3 usecs, so the measurement almost always succeeds at first try,
only very rarely takes two attempts. The preempt disable is meant to make
sure that this stays the case on a PREEMPT_RT kernel.
The problem here are the relatively rare cases where we hit that up to 100
iterations for-loop. Here even on a regular kernel, due to hardware quirks,
we already exceed the 20 usecs tolerance by a huge amount of more than 100
usecs, leading to a retry of the measurement. And my tests showed that
often the two succeeding retries also fail, because of hardware quirks can
apparently create a blackout situation approaching 1 msec, so we lose
anyway, regardless if we get preempted on a RT kernel or not. That's why
enabling preemption on RT again during that for-loop should not make the
situation worse and at least keep RT as real-time as intended.
In practice I would also expect that this failure case is the one least
likely to impair userspace applications greatly in practice. The cases that
mostly matter are the ones executed during vblank hardware irq, where the
for-loop never executes and error margin and preempt off time is only about
1 usec. My own software which depends on very precise timestamps from the
mechanism never reported >> 20 usecs errors during startup tests or runtime
tests.
> - intel_crtc_scanlines_since_frame_timestamp() not sure how long this
> may take in the worst case.
>
>
intel_crtc_scanlines_since_frame_timestamp() should be harmless. That
do-while loop just tries to make sure that two register reads that should
happen within the same video refresh cycle are happening in the same
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/guc: Refactor ADS access to use dma_buf_map
== Series Details == Series: drm/i915/guc: Refactor ADS access to use dma_buf_map URL : https://patchwork.freedesktop.org/series/99378/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/guc: Refactor ADS access to use dma_buf_map
== Series Details ==
Series: drm/i915/guc: Refactor ADS access to use dma_buf_map
URL : https://patchwork.freedesktop.org/series/99378/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
65454816ee9c dma-buf-map: Add read/write helpers
-:105: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'type__' may be better as
'(type__)' to avoid precedence issues
#105: FILE: include/linux/dma-buf-map.h:319:
+#define dma_buf_map_read_field(map__, type__, field__) ({
\
+ type__ *t__;
\
+ typeof(t__->field__) val__;
\
+ dma_buf_map_memcpy_from_offset(__, map__, offsetof(type__,
field__),\
+ sizeof(t__->field__));
\
+ val__;
\
+})
-:105: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'field__' - possible
side-effects?
#105: FILE: include/linux/dma-buf-map.h:319:
+#define dma_buf_map_read_field(map__, type__, field__) ({
\
+ type__ *t__;
\
+ typeof(t__->field__) val__;
\
+ dma_buf_map_memcpy_from_offset(__, map__, offsetof(type__,
field__),\
+ sizeof(t__->field__));
\
+ val__;
\
+})
-:105: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'field__' may be better as
'(field__)' to avoid precedence issues
#105: FILE: include/linux/dma-buf-map.h:319:
+#define dma_buf_map_read_field(map__, type__, field__) ({
\
+ type__ *t__;
\
+ typeof(t__->field__) val__;
\
+ dma_buf_map_memcpy_from_offset(__, map__, offsetof(type__,
field__),\
+ sizeof(t__->field__));
\
+ val__;
\
+})
-:126: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'type__' may be better as
'(type__)' to avoid precedence issues
#126: FILE: include/linux/dma-buf-map.h:340:
+#define dma_buf_map_write_field(map__, type__, field__, val__) ({
\
+ type__ *t__;
\
+ typeof(t__->field__) val = val__;
\
+ dma_buf_map_memcpy_to_offset(map__, offsetof(type__, field__),
\
+, sizeof(t__->field__));
\
+})
-:126: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'field__' - possible
side-effects?
#126: FILE: include/linux/dma-buf-map.h:340:
+#define dma_buf_map_write_field(map__, type__, field__, val__) ({
\
+ type__ *t__;
\
+ typeof(t__->field__) val = val__;
\
+ dma_buf_map_memcpy_to_offset(map__, offsetof(type__, field__),
\
+, sizeof(t__->field__));
\
+})
-:126: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'field__' may be better as
'(field__)' to avoid precedence issues
#126: FILE: include/linux/dma-buf-map.h:340:
+#define dma_buf_map_write_field(map__, type__, field__, val__) ({
\
+ type__ *t__;
\
+ typeof(t__->field__) val = val__;
\
+ dma_buf_map_memcpy_to_offset(map__, offsetof(type__, field__),
\
+, sizeof(t__->field__));
\
+})
total: 0 errors, 0 warnings, 6 checks, 97 lines checked
3e1d98022b1e dma-buf-map: Add helper to initialize second map
-:55: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in
parentheses
#55: FILE: include/linux/dma-buf-map.h:157:
+#define DMA_BUF_MAP_INIT_OFFSET(map_, offset_) (struct dma_buf_map)\
+ { \
+ .vaddr = (map_)->vaddr + (offset_), \
+ .is_iomem = (map_)->is_iomem, \
+ }
-:55: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'map_' - possible
side-effects?
#55: FILE: include/linux/dma-buf-map.h:157:
+#define DMA_BUF_MAP_INIT_OFFSET(map_, offset_) (struct dma_buf_map)\
+ {
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display/vrr: Reset VRR capable property on a long hpd (rev2)
== Series Details ==
Series: drm/i915/display/vrr: Reset VRR capable property on a long hpd (rev2)
URL : https://patchwork.freedesktop.org/series/98801/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11147 -> Patchwork_22115
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_22115 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22115, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22115/index.html
Participating hosts (48 -> 16)
--
ERROR: It appears as if the changes made in Patchwork_22115 prevented too
many machines from booting.
Additional (1): bat-adls-5
Missing(33): fi-kbl-soraka fi-bdw-gvtdvm fi-icl-u2 fi-apl-guc
fi-snb-2520m fi-pnv-d510 fi-skl-6600u fi-snb-2600 fi-cml-u2 fi-bxt-dsi
fi-bdw-5557u fi-bsw-n3050 fi-glk-dsi fi-ilk-650 fi-kbl-7500u fi-ctg-p8600
fi-hsw-4770 fi-ivb-3770 fi-elk-e7500 fi-bsw-nick fi-skl-6700k2 fi-kbl-7567u
fi-skl-guc fi-cfl-8700k fi-hsw-4200u fi-bsw-cyan fi-cfl-guc fi-kbl-guc
fi-kbl-x1275 fi-cfl-8109u fi-kbl-8809g fi-bsw-kefka fi-bdw-samus
Known issues
Here are the changes found in Patchwork_22115 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@hangcheck:
- bat-dg1-5: [PASS][1] -> [DMESG-FAIL][2] ([i915#4494])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11147/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22115/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
Possible fixes
* igt@i915_selftest@live@gt_pm:
- {fi-jsl-1}: [DMESG-FAIL][3] ([i915#1886]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11147/fi-jsl-1/igt@i915_selftest@live@gt_pm.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22115/fi-jsl-1/igt@i915_selftest@live@gt_pm.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4898]: https://gitlab.freedesktop.org/drm/intel/issues/4898
Build changes
-
* Linux: CI_DRM_11147 -> Patchwork_22115
CI-20190529: 20190529
CI_DRM_11147: ad57bf1ff13e1c4462f947398fbfb861f1b2e345 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6335: 2b30115edd692b60d16cb10375730a87f51f0e37 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22115: 071c4ebbb036b0f740a0a3b497efb2ad50588e54 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
071c4ebbb036 drm/i915/display/vrr: Reset VRR capable property on a long hpd
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22115/index.html
Re: [Intel-gfx] [PATCH v5 01/10] drm/i915/guc: Update GuC ADS size for error capture lists
On Wed, Jan 26, 2022 at 02:48:13AM -0800, Alan Previn wrote:
Update GuC ADS size allocation to include space for
the lists of error state capture register descriptors.
Also, populate the lists of registers we want GuC to report back to
Host on engine reset events. This list should include global,
engine-class and engine-instance registers for every engine-class
type on the current hardware.
NOTE: Start with a sample table of register lists to layout the
framework before adding real registers in subsequent patch.
Signed-off-by: Alan Previn
---
...
static void __guc_ads_init(struct intel_guc *guc)
{
struct intel_gt *gt = guc_to_gt(guc);
@@ -573,9 +553,9 @@ static void __guc_ads_init(struct intel_guc *guc)
base = intel_guc_ggtt_offset(guc, guc->ads_vma);
- /* Capture list for hang debug */
- guc_capture_list_init(guc, blob);
-
+ /* Lists for error capture debug */
+ intel_guc_capture_prep_lists(guc, (struct guc_ads *)blob, base,
no, please don't cast/export struct guc_ads like this. We can't really
dereference it since it may be in IO memory.
See https://patchwork.freedesktop.org/series/99378/ with the huge
refactor in this file to make it conform to the rules of accessing IO
memory.
Maybe this list could be appended in the same reglist buffer and we just
copy it once to its final location, like we are doing with the reglist?
Lucas De Marchi
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display/vrr: Reset VRR capable property on a long hpd (rev2)
== Series Details == Series: drm/i915/display/vrr: Reset VRR capable property on a long hpd (rev2) URL : https://patchwork.freedesktop.org/series/98801/ State : warning == Summary == $ dim checkpatch origin/drm-tip 071c4ebbb036 drm/i915/display/vrr: Reset VRR capable property on a long hpd -:7: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #7: With some VRR panels, user can turn VRR ON/OFF on the fly from the panel settings. total: 0 errors, 1 warnings, 0 checks, 33 lines checked
Re: [Intel-gfx] [PATCH v2 6/6] drm/i915: Only include i915_reg.h from .c files
On Mon, Jan 24, 2022 at 06:08:26PM -0800, Matt Roper wrote: Several of our i915 header files, have been including i915_reg.h. This means that any change to i915_reg.h will trigger a full rebuild of pretty much every file of the driver, even those that don't have any kind of register access. Let's delete the i915_reg.h include from all headers and include an explicit include from the .c files that truly if you're going to respin this or while applying, it may be good to reword this sentence as we have too many "include". Reviewed-by: Lucas De Marchi Lucas De Marchi
Re: [Intel-gfx] [PATCH v2 5/6] drm/i915: Move GT registers to their own header file
On Mon, Jan 24, 2022 at 06:08:25PM -0800, Matt Roper wrote: +#define MEMSWCTL _MMIO(0x11170) /* Ironlake only */ +#define MEMCTL_CMD_MASK 0xe000 +#define MEMCTL_CMD_SHIFT 13 +#define MEMCTL_CMD_RCLK_OFF 0 +#define MEMCTL_CMD_RCLK_ON 1 +#define MEMCTL_CMD_CHFREQ2 +#define MEMCTL_CMD_CHVID 3 +#define MEMCTL_CMD_VMMOFF4 +#define MEMCTL_CMD_VMMON 5 +#define MEMCTL_CMD_STS (1 << 12) /* write 1 triggers command, clears +when command complete */ formatting issue here +#define GEN9_SLICE_PGCTL_ACK(slice)_MMIO(0x804c + (slice) * 0x4) +#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \ +((slice) % 3) * 0x4) and here +#define GEN9_PGCTL_SLICE_ACK (1 << 0) +#define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice) * 2)) +#define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F) + +#define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice) * 0x8) +#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \ +((slice) % 3) * 0x8) and here +#define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice) * 0x8) +#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \ +((slice) % 3) * 0x8) and here. Rest looks sane. There's already a conflict in this patch, although following "this should be just code move", it's easy to solve. I wonder what is the strategy going to be for merging this because it will conflict badly between drm-intel-next and drm-intel-gt-next. Reviewed-by: Lucas De Marchi Lucas De Marchi
Re: [Intel-gfx] [PATCH v2 4/6] drm/i915: Parameterize MI_PREDICATE registers
On Mon, Jan 24, 2022 at 06:08:24PM -0800, Matt Roper wrote: The various MI_PREDICATE registers have per-engine instances. Today we only utilize the RCS0 instance of each, but that will likely change in the future; switch to parameterized register definitions to make these easier to work with going forward. Of special note is MI_PREDICATE_RESULT_2; we only use it in one place in the driver today in HSW-specific code. It turns out that the bspec (page 94) lists two different offsets for this register on HSW; one is in the standard location shared by all other platforms (base + 0x3bc) and the other is an unusual location (0x2214). We're using the second, non-standard offset in i915 today; that offset doesn't exist on any other platforms (and it's not even 100% clear that it's correct for HSW) so I've renamed the current non-standard definition to HSW_MI_PREDICATE_RESULT_2; the new cross-platform parameterized macro (which is still unused at the moment) uses the standard offset. Cc: Jani Nikula Signed-off-by: Matt Roper Reviewed-by: Lucas De Marchi Lucas De Marchi
Re: [Intel-gfx] [PATCH v2 2/6] drm/i915/perf: Express OA register ranges with i915_range
On Mon, Jan 24, 2022 at 06:08:22PM -0800, Matt Roper wrote: Let's use 'struct i915_range' to express sets of b-counter and mux registers in the perf code. This makes the code more similar to how we handle things like multicast register ranges, forcewake tables, shadow tables, etc. and also lets us avoid needing symbolic register name definitions for the various range end points. With this change, many of the OA register definitions are no longer used in the code, so we can drop their #define's for simplicity. v2: Drop 'inline' from reg_in_range_table(). (Jani) Cc: Jani Nikula Cc: Umesh Nerlige Ramappa Cc: Lionel Landwerlin Signed-off-by: Matt Roper I didn't come up with an idea to review the table ranges, but agree with the change: Acked-by: Lucas De Marchi Lucas De Marchi
Re: [Intel-gfx] [PATCH v2 3/6] drm/i915: Parameterize R_PWR_CLK_STATE register definition
On Mon, Jan 24, 2022 at 06:08:23PM -0800, Matt Roper wrote: At the moment we only use R_PWR_CLK_STATE in the context of the RCS engine, but upcoming support for compute engines will start using instances relative to the CCS engine base offsets. Let's parameterize the register and move it to the engine reg header. Cc: Jani Nikula Signed-off-by: Matt Roper Reviewed-by: Lucas De Marchi Lucas De Marchi
Re: [Intel-gfx] [PATCH v2 1/6] drm/i915/perf: Move OA regs to their own header
On Mon, Jan 24, 2022 at 06:08:21PM -0800, Matt Roper wrote: The OA unit registers are only used by the perf code; move them to their own header file. Cc: Jani Nikula Cc: Umesh Nerlige Ramappa Cc: Lionel Landwerlin Signed-off-by: Matt Roper I checked the output from git show --color-moved to help and indeed this is just moving the registers. Also, looking at the register names, they all seem to be OA/perf related. Reviewed-by: Lucas De Marchi Lucas De Marchi
Re: [Intel-gfx] [PATCH v5 02/10] drm/i915/guc: Add XE_LP registers for GuC error state capture.
Thanks Jani for taking the time to review...
1. apologies on the const issue, this is my bad, i think it was
one of the comments from earlier rev not sure how i missed it.
Will fix this on next rev.
2. I do have a question below on the const for one of specific types
of tables. Need your thoughts
...alan
On Wed, 2022-01-26 at 20:13 +0200, Jani Nikula wrote:
> On Wed, 26 Jan 2022, Alan Previn wrote:
> > Add device specific tables and register lists to cover different engines
> > class types for GuC error state capture for XE_LP products.
> >
...
> > +static struct __ext_steer_reg xelpd_extregs[] = {
> > + {"GEN7_SAMPLER_INSTDONE", GEN7_SAMPLER_INSTDONE},
> > + {"GEN7_ROW_INSTDONE", GEN7_ROW_INSTDONE}
> > +};
>
> Either this needs to be const or, if it needs to be mutable, moved to
> device specific data.
>
> Ditto for all such things all over the place.
>
> BR,
> Jani.
I had a question though... the list of registers like the one above as well
as below shall be made const... however, the table-of-lists (see farther down),
contains a pointer to "extended_regs"
that shall be allocated at startup - is it okay for that list to remain
non-const
since the others with actual register offsets remain const?
Alan: will add const for this and above tables:
static struct __guc_mmio_reg_descr xe_lpd_global_regs[] = {
COMMON_BASE_GLOBAL(),
COMMON_GEN9BASE_GLOBAL(),
COMMON_GEN12BASE_GLOBAL(),
};
Is this okay to not be const?:
static struct __guc_mmio_reg_descr_group default_lists[] = {
MAKE_REGLIST(default_global_regs, PF, GLOBAL, 0),
MAKE_REGLIST(default_rc_class_regs, PF, ENGINE_CLASS,
GUC_RENDER_CLASS),
MAKE_REGLIST(xe_lpd_rc_inst_regs, PF, ENGINE_INSTANCE,
GUC_RENDER_CLASS),
MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS,
GUC_VIDEO_CLASS),
MAKE_REGLIST(xe_lpd_vd_inst_regs, PF, ENGINE_INSTANCE,
GUC_VIDEO_CLASS),
MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS,
GUC_VIDEOENHANCE_CLASS),
MAKE_REGLIST(xe_lpd_vec_inst_regs, PF, ENGINE_INSTANCE,
GUC_VIDEOENHANCE_CLASS),
MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS,
GUC_BLITTER_CLASS),
MAKE_REGLIST(xe_lpd_blt_inst_regs, PF, ENGINE_INSTANCE,
GUC_BLITTER_CLASS),
{}
};
[Intel-gfx] ✗ Fi.CI.BAT: failure for Initial support for small BAR recovery
== Series Details ==
Series: Initial support for small BAR recovery
URL : https://patchwork.freedesktop.org/series/99370/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11146 -> Patchwork_22114
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_22114 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22114, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22114/index.html
Participating hosts (40 -> 44)
--
Additional (8): bat-dg1-6 bat-dg1-5 fi-icl-u2 bat-adlp-6 fi-pnv-d510
bat-rpls-1 bat-jsl-2 bat-jsl-1
Missing(4): fi-ctg-p8600 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_22114:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live@gem_contexts:
- bat-dg1-5: NOTRUN -> [INCOMPLETE][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22114/bat-dg1-5/igt@i915_selftest@live@gem_contexts.html
* igt@i915_selftest@live@hugepages:
- bat-dg1-6: NOTRUN -> [INCOMPLETE][2]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22114/bat-dg1-6/igt@i915_selftest@l...@hugepages.html
* igt@kms_frontbuffer_tracking@basic:
- bat-dg1-5: NOTRUN -> [CRASH][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22114/bat-dg1-5/igt@kms_frontbuffer_track...@basic.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling:
- {bat-adlp-6}: NOTRUN -> [DMESG-WARN][4]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22114/bat-adlp-6/igt@kms_addfb_ba...@addfb25-framebuffer-vs-set-tiling.html
Known issues
Here are the changes found in Patchwork_22114 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_cs_nop@fork-gfx0:
- fi-icl-u2: NOTRUN -> [SKIP][5] ([fdo#109315]) +17 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22114/fi-icl-u2/igt@amdgpu/amd_cs_...@fork-gfx0.html
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600:NOTRUN -> [SKIP][6] ([fdo#109271]) +17 similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22114/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html
* igt@core_hotunplug@unbind-rebind:
- fi-pnv-d510:NOTRUN -> [FAIL][7] ([i915#3194])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22114/fi-pnv-d510/igt@core_hotunp...@unbind-rebind.html
* igt@fbdev@info:
- bat-dg1-6: NOTRUN -> [SKIP][8] ([i915#2582]) +4 similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22114/bat-dg1-6/igt@fb...@info.html
* igt@gem_exec_gttfill@basic:
- bat-dg1-6: NOTRUN -> [SKIP][9] ([i915#4086])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22114/bat-dg1-6/igt@gem_exec_gttf...@basic.html
- bat-dg1-5: NOTRUN -> [SKIP][10] ([i915#4086])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22114/bat-dg1-5/igt@gem_exec_gttf...@basic.html
* igt@gem_huc_copy@huc-copy:
- fi-icl-u2: NOTRUN -> [SKIP][11] ([i915#2190])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22114/fi-icl-u2/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-icl-u2: NOTRUN -> [SKIP][12] ([i915#4613]) +3 similar issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22114/fi-icl-u2/igt@gem_lmem_swapp...@parallel-random-engines.html
* igt@gem_mmap@basic:
- bat-dg1-6: NOTRUN -> [SKIP][13] ([i915#4083])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22114/bat-dg1-6/igt@gem_m...@basic.html
- bat-dg1-5: NOTRUN -> [SKIP][14] ([i915#4083])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22114/bat-dg1-5/igt@gem_m...@basic.html
* igt@gem_tiled_blits@basic:
- bat-dg1-6: NOTRUN -> [SKIP][15] ([i915#4077]) +2 similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22114/bat-dg1-6/igt@gem_tiled_bl...@basic.html
* igt@gem_tiled_fence_blits@basic:
- bat-dg1-5: NOTRUN -> [SKIP][16] ([i915#4077]) +2 similar issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22114/bat-dg1-5/igt@gem_tiled_fence_bl...@basic.html
* igt@gem_tiled_pread_basic:
- bat-dg1-5: NOTRUN -> [SKIP][17] ([i915#4079]) +1 similar issue
[17]:
Re: [Intel-gfx] [PATCH 6/9] drm/i915: Clean up PIPESRC defines
On Wed, Jan 26, 2022 at 04:42:52PM +0200, Jani Nikula wrote: > On Fri, 12 Nov 2021, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > Use REG_GENMASK() & co. when dealing with PIPESRC. > > > > Signed-off-by: Ville Syrjälä > > --- > > drivers/gpu/drm/i915/display/i9xx_plane.c| 4 ++-- > > drivers/gpu/drm/i915/display/intel_display.c | 7 --- > > drivers/gpu/drm/i915/i915_reg.h | 4 > > 3 files changed, 10 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c > > b/drivers/gpu/drm/i915/display/i9xx_plane.c > > index 2194f74101ae..f586e39cb378 100644 > > --- a/drivers/gpu/drm/i915/display/i9xx_plane.c > > +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c > > @@ -1048,8 +1048,8 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, > > plane_config->base = base; > > > > val = intel_de_read(dev_priv, PIPESRC(pipe)); > > - fb->width = ((val >> 16) & 0xfff) + 1; > > - fb->height = ((val >> 0) & 0xfff) + 1; > > I guess the mask width change is worth noting in the commit message. Aye. I added a few notes about this and the DSL stuff. > > Reviewed-by: Jani Nikula Thanks. Series pushed to drm-intel-next. -- Ville Syrjälä Intel
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Initial support for small BAR recovery
== Series Details == Series: Initial support for small BAR recovery URL : https://patchwork.freedesktop.org/series/99370/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Initial support for small BAR recovery
== Series Details ==
Series: Initial support for small BAR recovery
URL : https://patchwork.freedesktop.org/series/99370/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
8c8317fbf210 drm: improve drm_buddy_alloc function
-:399: WARNING:AVOID_BUG: Avoid crashing the kernel - try using WARN_ON &
recovery code rather than BUG() or BUG_ON()
#399: FILE: drivers/gpu/drm/drm_buddy.c:586:
+ BUG_ON(order > mm->max_order);
-:400: WARNING:AVOID_BUG: Avoid crashing the kernel - try using WARN_ON &
recovery code rather than BUG() or BUG_ON()
#400: FILE: drivers/gpu/drm/drm_buddy.c:587:
+ BUG_ON(order < min_order);
-:527: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#527: FILE: drivers/gpu/drm/i915/i915_ttm_buddy_manager.c:88:
+ err = drm_buddy_alloc_blocks(mm, (u64)place->fpfn << PAGE_SHIFT,
+ (u64)lpfn << PAGE_SHIFT,
total: 0 errors, 2 warnings, 1 checks, 545 lines checked
06e1414d96cc drm: implement top-down allocation method
3bd9f95ffd60 drm: implement a method to free unused pages
106d4bacced1 drm/i915: add io_size plumbing
-:130: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#130: FILE: drivers/gpu/drm/i915/gt/intel_region_lmem.c:238:
+ drm_info(>drm, "Local memory IO size: %pa\n",
+ >io_size);
total: 0 errors, 0 warnings, 1 checks, 187 lines checked
ecf0c57686a0 drm/i915/ttm: require mappable by default
1577ab960e49 drm/i915: add I915_BO_ALLOC_TOPDOWN
fe790c61b74c drm/i915/buddy: track available visible size
b8dc57a8a6f5 drm/i915/buddy: adjust res->start
dfdefb960877 drm/i915/buddy: tweak 2big check
3a1b1417e181 drm/i915/selftests: mock test io_size
-:62: WARNING:LINE_SPACING: Missing a blank line after declarations
#62: FILE: drivers/gpu/drm/i915/selftests/intel_memory_region.c:548:
+ u64 size;
+ I915_RND_STATE(prng);
total: 0 errors, 1 warnings, 0 checks, 161 lines checked
9937084d5576 drm/i915/ttm: tweak priority hint selection
bd1c8f577dbe drm/i915/ttm: make eviction mappable aware
-:9: WARNING:REPEATED_WORD: Possible repeated word: 'some'
#9:
If we need to make room for some some mappable object, then we should
total: 0 errors, 1 warnings, 0 checks, 97 lines checked
5398c571b14c drm/i915/ttm: mappable migration on fault
-:38: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#38: FILE: drivers/gpu/drm/i915/gem/i915_gem_ttm.c:651:
{
+
total: 0 errors, 0 warnings, 1 checks, 104 lines checked
d96b8b24ddab drm/i915/selftests: exercise mmap migration
-:119: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#119: FILE: drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c:1091:
+ pr_info("igt_mmap(%s, %d) @ %lx\n",
+obj->mm.region->name, I915_MMAP_TYPE_FIXED, addr);
-:182: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#182: FILE: drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c:1154:
+#define IGT_MMAP_MIGRATE_TOPDOWN (1<<0)
^
-:183: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#183: FILE: drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c:1155:
+#define IGT_MMAP_MIGRATE_FILL(1<<1)
^
-:184: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#184: FILE: drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c:1156:
+#define IGT_MMAP_MIGRATE_EVICTABLE (1<<2)
^
-:185: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#185: FILE: drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c:1157:
+#define IGT_MMAP_MIGRATE_UNFAULTABLE (1<<3)
^
total: 0 errors, 0 warnings, 5 checks, 324 lines checked
4de3a89e9ae6 drm/i915/selftests: handle allocation failures
0187997a140b drm/i915/create: apply ALLOC_TOPDOWN by default
fc67630543c9 drm/i915/uapi: add NEEDS_CPU_ACCESS hint
-:118: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#118: FILE: include/uapi/drm/i915_drm.h:3189:
+#define I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS (1<<0)
^
total: 0 errors, 0 warnings, 1 checks, 89 lines checked
82b5e5021221 drm/i915/uapi: forbid ALLOC_TOPDOWN for error capture
-:17: WARNING:BAD_SIGN_OFF: Duplicate signature
#17:
Reported-by: kernel test robot
total: 0 errors, 1 warnings, 0 checks, 35 lines checked
2ec2549ba3d3 drm/i915/lmem: don't treat small BAR as an error
0e4cc9d13568 HAX: DG1 small BAR
[Intel-gfx] [PATCH 18/19] drm/i915/guc: Convert __guc_ads_init to dma_buf_map
Now that all the called functions from __guc_ads_init() are converted to
use ads_map, stop using ads_blob in __guc_ads_init().
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 25 --
1 file changed, 14 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index cb0f543b0e86..30edac93afbf 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -602,7 +602,6 @@ static void __guc_ads_init(struct intel_guc *guc)
{
struct intel_gt *gt = guc_to_gt(guc);
struct drm_i915_private *i915 = gt->i915;
- struct __guc_ads_blob *blob = guc->ads_blob;
struct dma_buf_map info_map = DMA_BUF_MAP_INIT_OFFSET(>ads_map,
offsetof(struct __guc_ads_blob, system_info));
u32 base;
@@ -613,17 +612,18 @@ static void __guc_ads_init(struct intel_guc *guc)
/* System info */
fill_engine_enable_masks(gt, _map);
-
blob->system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_SLICE_ENABLED] =
- hweight8(gt->info.sseu.slice_mask);
-
blob->system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_VDBOX_SFC_SUPPORT_MASK]
=
- gt->info.vdbox_sfc_access;
+ ads_blob_write(guc,
system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_SLICE_ENABLED],
+ hweight8(gt->info.sseu.slice_mask));
+ ads_blob_write(guc,
system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_VDBOX_SFC_SUPPORT_MASK],
+ gt->info.vdbox_sfc_access);
if (GRAPHICS_VER(i915) >= 12 && !IS_DGFX(i915)) {
u32 distdbreg = intel_uncore_read(gt->uncore,
GEN12_DIST_DBS_POPULATED);
-
blob->system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI]
=
- ((distdbreg >> GEN12_DOORBELLS_PER_SQIDI_SHIFT) &
-GEN12_DOORBELLS_PER_SQIDI) + 1;
+ ads_blob_write(guc,
+
system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI],
+ ((distdbreg >> GEN12_DOORBELLS_PER_SQIDI_SHIFT)
+ & GEN12_DOORBELLS_PER_SQIDI) + 1);
}
/* Golden contexts for re-initialising after a watchdog reset */
@@ -637,14 +637,17 @@ static void __guc_ads_init(struct intel_guc *guc)
guc_capture_list_init(guc);
/* ADS */
- blob->ads.scheduler_policies = base + ptr_offset(blob, policies);
- blob->ads.gt_system_info = base + ptr_offset(blob, system_info);
+ ads_blob_write(guc, ads.scheduler_policies, base +
+ offsetof(struct __guc_ads_blob, policies));
+ ads_blob_write(guc, ads.gt_system_info, base +
+ offsetof(struct __guc_ads_blob, system_info));
/* MMIO save/restore list */
guc_mmio_reg_state_init(guc);
/* Private Data */
- blob->ads.private_data = base + guc_ads_private_data_offset(guc);
+ ads_blob_write(guc, ads.private_data, base +
+ guc_ads_private_data_offset(guc));
i915_gem_object_flush_map(guc->ads_vma->obj);
}
--
2.35.0
[Intel-gfx] [PATCH 15/19] drm/i915/guc: Prepare for error propagation
Currently guc_mmio_reg_add() relies on having enough memory available in
the array to add a new slot. It uses
`GEM_BUG_ON(count >= regset->size);` to protect going above the
threshold.
In order to allow guc_mmio_reg_add() to handle the memory allocation by
itself, it must return an error in case of failures. Adjust return code
so this error can be propagated to the callers of guc_mmio_reg_add() and
guc_mmio_regset_init().
No intended change in behavior.
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 31 +-
1 file changed, 18 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index cad1e325656e..73ca34de44f7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -244,8 +244,8 @@ static int guc_mmio_reg_cmp(const void *a, const void *b)
return (int)ra->offset - (int)rb->offset;
}
-static void guc_mmio_reg_add(struct temp_regset *regset,
-u32 offset, u32 flags)
+static long __must_check guc_mmio_reg_add(struct temp_regset *regset,
+ u32 offset, u32 flags)
{
u32 count = regset->used;
struct guc_mmio_reg reg = {
@@ -264,7 +264,7 @@ static void guc_mmio_reg_add(struct temp_regset *regset,
*/
if (bsearch(, regset->registers, count,
sizeof(reg), guc_mmio_reg_cmp))
- return;
+ return 0;
slot = >registers[count];
regset->used++;
@@ -277,6 +277,8 @@ static void guc_mmio_reg_add(struct temp_regset *regset,
swap(slot[1], slot[0]);
}
+
+ return 0;
}
#define GUC_MMIO_REG_ADD(regset, reg, masked) \
@@ -284,32 +286,35 @@ static void guc_mmio_reg_add(struct temp_regset *regset,
i915_mmio_reg_offset((reg)), \
(masked) ? GUC_REGSET_MASKED : 0)
-static void guc_mmio_regset_init(struct temp_regset *regset,
-struct intel_engine_cs *engine)
+static int guc_mmio_regset_init(struct temp_regset *regset,
+ struct intel_engine_cs *engine)
{
const u32 base = engine->mmio_base;
struct i915_wa_list *wal = >wa_list;
struct i915_wa *wa;
unsigned int i;
+ int ret = 0;
regset->used = 0;
- GUC_MMIO_REG_ADD(regset, RING_MODE_GEN7(base), true);
- GUC_MMIO_REG_ADD(regset, RING_HWS_PGA(base), false);
- GUC_MMIO_REG_ADD(regset, RING_IMR(base), false);
+ ret |= GUC_MMIO_REG_ADD(regset, RING_MODE_GEN7(base), true);
+ ret |= GUC_MMIO_REG_ADD(regset, RING_HWS_PGA(base), false);
+ ret |= GUC_MMIO_REG_ADD(regset, RING_IMR(base), false);
for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
- GUC_MMIO_REG_ADD(regset, wa->reg, wa->masked_reg);
+ ret |= GUC_MMIO_REG_ADD(regset, wa->reg, wa->masked_reg);
/* Be extra paranoid and include all whitelist registers. */
for (i = 0; i < RING_MAX_NONPRIV_SLOTS; i++)
- GUC_MMIO_REG_ADD(regset,
-RING_FORCE_TO_NONPRIV(base, i),
-false);
+ ret |= GUC_MMIO_REG_ADD(regset,
+ RING_FORCE_TO_NONPRIV(base, i),
+ false);
/* add in local MOCS registers */
for (i = 0; i < GEN9_LNCFCMOCS_REG_COUNT; i++)
- GUC_MMIO_REG_ADD(regset, GEN9_LNCFCMOCS(i), false);
+ ret |= GUC_MMIO_REG_ADD(regset, GEN9_LNCFCMOCS(i), false);
+
+ return ret ? -1 : 0;
}
static int guc_mmio_reg_state_query(struct intel_guc *guc)
--
2.35.0
[Intel-gfx] [PATCH 08/19] drm/i915/guc: Convert engine record to dma_buf_map
Use dma_buf_map to read fields from the dma_blob so access to IO and
system memory is abstracted away.
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 14 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h| 3 ++-
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 11 +++
3 files changed, 15 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 2ffe5836f95e..fe1e71adfca1 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -698,18 +698,16 @@ void intel_guc_ads_reset(struct intel_guc *guc)
u32 intel_guc_engine_usage_offset(struct intel_guc *guc)
{
- struct __guc_ads_blob *blob = guc->ads_blob;
- u32 base = intel_guc_ggtt_offset(guc, guc->ads_vma);
- u32 offset = base + ptr_offset(blob, engine_usage);
-
- return offset;
+ return intel_guc_ggtt_offset(guc, guc->ads_vma) +
+ offsetof(struct __guc_ads_blob, engine_usage);
}
-struct guc_engine_usage_record *intel_guc_engine_usage(struct intel_engine_cs
*engine)
+struct dma_buf_map intel_guc_engine_usage_record_map(struct intel_engine_cs
*engine)
{
struct intel_guc *guc = >gt->uc.guc;
- struct __guc_ads_blob *blob = guc->ads_blob;
u8 guc_class = engine_class_to_guc_class(engine->class);
+ size_t offset = offsetof(struct __guc_ads_blob,
+
engine_usage.engines[guc_class][ilog2(engine->logical_mask)]);
- return
>engine_usage.engines[guc_class][ilog2(engine->logical_mask)];
+ return DMA_BUF_MAP_INIT_OFFSET(>ads_map, offset);
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h
index e74c110facff..27f5b1f9ddac 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h
@@ -7,6 +7,7 @@
#define _INTEL_GUC_ADS_H_
#include
+#include
struct intel_guc;
struct drm_printer;
@@ -18,7 +19,7 @@ void intel_guc_ads_init_late(struct intel_guc *guc);
void intel_guc_ads_reset(struct intel_guc *guc);
void intel_guc_ads_print_policy_info(struct intel_guc *guc,
struct drm_printer *p);
-struct guc_engine_usage_record *intel_guc_engine_usage(struct intel_engine_cs
*engine);
+struct dma_buf_map intel_guc_engine_usage_record_map(struct intel_engine_cs
*engine);
u32 intel_guc_engine_usage_offset(struct intel_guc *guc);
#endif
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index db9615dcb0ec..57bfb4ad0ab8 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1125,14 +1125,17 @@ __extend_last_switch(struct intel_guc *guc, u64
*prev_start, u32 new_start)
*prev_start = ((u64)gt_stamp_hi << 32) | new_start;
}
+#define record_read(map_, field_) \
+ dma_buf_map_read_field(map_, struct guc_engine_usage_record, field_)
+
static void guc_update_engine_gt_clks(struct intel_engine_cs *engine)
{
- struct guc_engine_usage_record *rec = intel_guc_engine_usage(engine);
+ struct dma_buf_map rec_map = intel_guc_engine_usage_record_map(engine);
struct intel_engine_guc_stats *stats = >stats.guc;
struct intel_guc *guc = >gt->uc.guc;
- u32 last_switch = rec->last_switch_in_stamp;
- u32 ctx_id = rec->current_context_index;
- u32 total = rec->total_runtime;
+ u32 last_switch = record_read(_map, last_switch_in_stamp);
+ u32 ctx_id = record_read(_map, current_context_index);
+ u32 total = record_read(_map, total_runtime);
lockdep_assert_held(>timestamp.lock);
--
2.35.0
[Intel-gfx] [PATCH 14/19] drm/i915/guc: Convert capture list to dma_buf_map
Use dma_buf_map to write the fields ads.capture_*.
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index dca7c3db9cdd..cad1e325656e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -544,7 +544,7 @@ static void guc_init_golden_context(struct intel_guc *guc)
GEM_BUG_ON(guc->ads_golden_ctxt_size != total_size);
}
-static void guc_capture_list_init(struct intel_guc *guc, struct __guc_ads_blob
*blob)
+static void guc_capture_list_init(struct intel_guc *guc)
{
int i, j;
u32 addr_ggtt, offset;
@@ -556,11 +556,11 @@ static void guc_capture_list_init(struct intel_guc *guc,
struct __guc_ads_blob *
for (i = 0; i < GUC_CAPTURE_LIST_INDEX_MAX; i++) {
for (j = 0; j < GUC_MAX_ENGINE_CLASSES; j++) {
- blob->ads.capture_instance[i][j] = addr_ggtt;
- blob->ads.capture_class[i][j] = addr_ggtt;
+ ads_blob_write(guc, ads.capture_instance[i][j],
addr_ggtt);
+ ads_blob_write(guc, ads.capture_class[i][j], addr_ggtt);
}
- blob->ads.capture_global[i] = addr_ggtt;
+ ads_blob_write(guc, ads.capture_global[i], addr_ggtt);
}
}
@@ -600,7 +600,7 @@ static void __guc_ads_init(struct intel_guc *guc)
base = intel_guc_ggtt_offset(guc, guc->ads_vma);
/* Capture list for hang debug */
- guc_capture_list_init(guc, blob);
+ guc_capture_list_init(guc);
/* ADS */
blob->ads.scheduler_policies = base + ptr_offset(blob, policies);
--
2.35.0
[Intel-gfx] [PATCH 16/19] drm/i915/guc: Use a single pass to calculate regset
The ADS initialitazion was using 2 passes to calculate the regset sent
to GuC to initialize each engine: the first pass to just have the final
object size and the second to set each register in place in the final
gem object.
However in order to maintain an ordered set of registers to pass to guc,
each register needs to be added and moved in the final array. The second
phase may actually happen in IO memory rather than system memory and
accessing IO memory by simply dereferencing the pointer doesn't work on
all architectures. Other places of the ADS initializaition were
converted to use the dma_buf_map API, but here there may be a lot more
accesses to IO memory. So, instead of following that same approach,
convert the regset initialization to calculate the final array in 1
pass and in the second pass that array is just copied to its final
location, updating the pointers for each engine written to the ADS blob.
One important thing is that struct temp_regset now have
different semantics: `registers` continues to track the registers of a
single engine, however the other fields are updated together, according
to the newly added `storage`, which tracks the memory allocated for
all the registers. So rename some of these fields and add a
__mmio_reg_add(): this function (possibly) allocates memory and operates
on the storage pointer while guc_mmio_reg_add() continues to manage the
registers pointer.
On a Tiger Lake system using enable_guc=3, the following log message is
now seen:
[ 187.334310] i915 :00:02.0: [drm:intel_guc_ads_create [i915]]
Used 4 KB for temporary ADS regset
This change has also been tested on an ARM64 host with DG2 and other
discrete graphics cards.
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h | 7 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 117 +
2 files changed, 79 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index e2e0df1c3d91..4c852eee3ad8 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -152,6 +152,13 @@ struct intel_guc {
struct dma_buf_map ads_map;
/** @ads_regset_size: size of the save/restore regsets in the ADS */
u32 ads_regset_size;
+ /**
+* @ads_regset_count: number of save/restore registers in the ADS for
+* each engine
+*/
+ u32 ads_regset_count[I915_NUM_ENGINES];
+ /** @ads_regset: save/restore regsets in the ADS */
+ struct guc_mmio_reg *ads_regset;
/** @ads_golden_ctxt_size: size of the golden contexts in the ADS */
u32 ads_golden_ctxt_size;
/** @ads_engine_usage_size: size of engine usage in the ADS */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 73ca34de44f7..390101ee3661 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -226,14 +226,13 @@ static void guc_mapping_table_init(struct intel_gt *gt,
/*
* The save/restore register list must be pre-calculated to a temporary
- * buffer of driver defined size before it can be generated in place
- * inside the ADS.
+ * buffer before it can be copied inside the ADS.
*/
-#define MAX_MMIO_REGS 128 /* Arbitrary size, increase as needed */
struct temp_regset {
struct guc_mmio_reg *registers;
- u32 used;
- u32 size;
+ struct guc_mmio_reg *storage;
+ u32 storage_used;
+ u32 storage_max;
};
static int guc_mmio_reg_cmp(const void *a, const void *b)
@@ -244,18 +243,44 @@ static int guc_mmio_reg_cmp(const void *a, const void *b)
return (int)ra->offset - (int)rb->offset;
}
+static struct guc_mmio_reg * __must_check
+__mmio_reg_add(struct temp_regset *regset, struct guc_mmio_reg *reg)
+{
+ u32 pos = regset->storage_used;
+ struct guc_mmio_reg *slot;
+
+ if (pos >= regset->storage_max) {
+ size_t size = ALIGN((pos + 1) * sizeof(*slot), PAGE_SIZE);
+ struct guc_mmio_reg *r = krealloc(regset->storage,
+ size, GFP_KERNEL);
+ if (!r) {
+ WARN_ONCE(1, "Incomplete regset list: can't add
register (%d)\n",
+ -ENOMEM);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ regset->registers = r + (regset->registers - regset->storage);
+ regset->storage = r;
+ regset->storage_max = size / sizeof(*slot);
+ }
+
+ slot = >storage[pos];
+ regset->storage_used++;
+ *slot = *reg;
+
+ return slot;
+}
+
static long __must_check guc_mmio_reg_add(struct temp_regset *regset,
[Intel-gfx] [PATCH 19/19] drm/i915/guc: Remove plain ads_blob pointer
Now we have the access to content of GuC ADS either using dma_buf_map
API or using a temporary buffer. Remove guc->ads_blob as there shouldn't
be updates using the bare pointer anymore.
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h | 3 +--
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 8
2 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 4c852eee3ad8..7349483d0e35 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -147,8 +147,7 @@ struct intel_guc {
/** @ads_vma: object allocated to hold the GuC ADS */
struct i915_vma *ads_vma;
- /** @ads_blob: contents of the GuC ADS */
- struct __guc_ads_blob *ads_blob;
+ /** @ads_map: contents of the GuC ADS */
struct dma_buf_map ads_map;
/** @ads_regset_size: size of the save/restore regsets in the ADS */
u32 ads_regset_size;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 30edac93afbf..b87269081650 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -661,6 +661,7 @@ static void __guc_ads_init(struct intel_guc *guc)
*/
int intel_guc_ads_create(struct intel_guc *guc)
{
+ void *ads_blob;
u32 size;
int ret;
@@ -685,14 +686,14 @@ int intel_guc_ads_create(struct intel_guc *guc)
size = guc_ads_blob_size(guc);
ret = intel_guc_allocate_and_map_vma(guc, size, >ads_vma,
-(void **)>ads_blob);
+_blob);
if (ret)
return ret;
if (i915_gem_object_is_lmem(guc->ads_vma->obj))
- dma_buf_map_set_vaddr_iomem(>ads_map, (void __iomem
*)guc->ads_blob);
+ dma_buf_map_set_vaddr_iomem(>ads_map, (void __iomem
*)ads_blob);
else
- dma_buf_map_set_vaddr(>ads_map, guc->ads_blob);
+ dma_buf_map_set_vaddr(>ads_map, ads_blob);
__guc_ads_init(guc);
@@ -714,7 +715,6 @@ void intel_guc_ads_init_late(struct intel_guc *guc)
void intel_guc_ads_destroy(struct intel_guc *guc)
{
i915_vma_unpin_and_release(>ads_vma, I915_VMA_RELEASE_MAP);
- guc->ads_blob = NULL;
dma_buf_map_clear(>ads_map);
kfree(guc->ads_regset);
}
--
2.35.0
[Intel-gfx] [PATCH 10/19] drm/i915/guc: Convert guc_ads_private_data_reset to dma_buf_map
Use dma_buf_map_memset() to zero the private data as ADS may be either
on system or IO memory.
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index fe1e71adfca1..15990c229b54 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -668,14 +668,15 @@ void intel_guc_ads_destroy(struct intel_guc *guc)
static void guc_ads_private_data_reset(struct intel_guc *guc)
{
+ struct dma_buf_map map =
+ DMA_BUF_MAP_INIT_OFFSET(>ads_map,
guc_ads_private_data_offset(guc));
u32 size;
size = guc_ads_private_data_size(guc);
if (!size)
return;
- memset((void *)guc->ads_blob + guc_ads_private_data_offset(guc), 0,
- size);
+ dma_buf_map_memset(, 0, size);
}
/**
--
2.35.0
[Intel-gfx] [PATCH 17/19] drm/i915/guc: Convert guc_mmio_reg_state_init to dma_buf_map
Now that the regset list is prepared, convert guc_mmio_reg_state_init()
to use dma_buf_map to copy the array to the final location and
initialize additional fields in ads.reg_state_list.
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 30 +-
1 file changed, 18 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 390101ee3661..cb0f543b0e86 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -372,40 +372,46 @@ static long guc_mmio_reg_state_create(struct intel_guc
*guc)
return total * sizeof(struct guc_mmio_reg);
}
-static void guc_mmio_reg_state_init(struct intel_guc *guc,
- struct __guc_ads_blob *blob)
+static void guc_mmio_reg_state_init(struct intel_guc *guc)
{
+ struct dma_buf_map ads_regset_map;
struct intel_gt *gt = guc_to_gt(guc);
struct intel_engine_cs *engine;
- struct guc_mmio_reg *ads_registers;
enum intel_engine_id id;
u32 addr_ggtt, offset;
offset = guc_ads_regset_offset(guc);
addr_ggtt = intel_guc_ggtt_offset(guc, guc->ads_vma) + offset;
- ads_registers = (struct guc_mmio_reg *)(((u8 *)blob) + offset);
+ ads_regset_map = DMA_BUF_MAP_INIT_OFFSET(>ads_map, offset);
- memcpy(ads_registers, guc->ads_regset, guc->ads_regset_size);
+ dma_buf_map_memcpy_to(_regset_map, guc->ads_regset,
+ guc->ads_regset_size);
for_each_engine(engine, gt, id) {
u32 count = guc->ads_regset_count[id];
- struct guc_mmio_reg_set *ads_reg_set;
u8 guc_class;
/* Class index is checked in class converter */
GEM_BUG_ON(engine->instance >= GUC_MAX_INSTANCES_PER_CLASS);
guc_class = engine_class_to_guc_class(engine->class);
- ads_reg_set =
>ads.reg_state_list[guc_class][engine->instance];
if (!count) {
- ads_reg_set->address = 0;
- ads_reg_set->count = 0;
+ ads_blob_write(guc,
+
ads.reg_state_list[guc_class][engine->instance].address,
+ 0);
+ ads_blob_write(guc,
+
ads.reg_state_list[guc_class][engine->instance].count,
+ 0);
continue;
}
- ads_reg_set->address = addr_ggtt;
- ads_reg_set->count = count;
+ ads_blob_write(guc,
+
ads.reg_state_list[guc_class][engine->instance].address,
+ addr_ggtt);
+ ads_blob_write(guc,
+
ads.reg_state_list[guc_class][engine->instance].count,
+ count);
addr_ggtt += count * sizeof(struct guc_mmio_reg);
}
@@ -635,7 +641,7 @@ static void __guc_ads_init(struct intel_guc *guc)
blob->ads.gt_system_info = base + ptr_offset(blob, system_info);
/* MMIO save/restore list */
- guc_mmio_reg_state_init(guc, blob);
+ guc_mmio_reg_state_init(guc);
/* Private Data */
blob->ads.private_data = base + guc_ads_private_data_offset(guc);
--
2.35.0
[Intel-gfx] [PATCH 12/19] drm/i915/guc: Replace check for golden context size
In the other places in this function, guc->ads_map is being protected from access when it's not yet set. However the last check is actually about guc->ads_golden_ctxt_size been set before. These checks should always match as the size is initialized on the first call to guc_prep_golden_context(), but it's clearer if we have a single return and check for guc->ads_golden_ctxt_size. This is just a readability improvement, no change in behavior. Cc: Matt Roper Cc: Thomas Hellström Cc: Daniel Vetter Cc: John Harrison Cc: Matthew Brost Cc: Daniele Ceraolo Spurio Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c index dd9ec47eed16..8e4768289792 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c @@ -461,10 +461,10 @@ static int guc_prep_golden_context(struct intel_guc *guc) addr_ggtt += alloc_size; } - if (dma_buf_map_is_null(>ads_map)) - return total_size; + /* Make sure current size matches what we calculated previously */ + if (guc->ads_golden_ctxt_size) + GEM_BUG_ON(guc->ads_golden_ctxt_size != total_size); - GEM_BUG_ON(guc->ads_golden_ctxt_size != total_size); return total_size; } -- 2.35.0
[Intel-gfx] [PATCH 07/19] drm/i915/guc: Convert policies update to dma_buf_map
Use dma_buf_map to write the policies update so access to IO and system
memory is abstracted away.
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 41 --
1 file changed, 23 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index bcf52ac4fe35..2ffe5836f95e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -130,33 +130,37 @@ static u32 guc_ads_blob_size(struct intel_guc *guc)
guc_ads_private_data_size(guc);
}
-static void guc_policies_init(struct intel_guc *guc, struct guc_policies
*policies)
+static void guc_policies_init(struct intel_guc *guc)
{
struct intel_gt *gt = guc_to_gt(guc);
struct drm_i915_private *i915 = gt->i915;
+ u32 global_flags = 0;
- policies->dpc_promote_time = GLOBAL_POLICY_DEFAULT_DPC_PROMOTE_TIME_US;
- policies->max_num_work_items = GLOBAL_POLICY_MAX_NUM_WI;
+ ads_blob_write(guc, policies.dpc_promote_time,
+ GLOBAL_POLICY_DEFAULT_DPC_PROMOTE_TIME_US);
+ ads_blob_write(guc, policies.max_num_work_items,
+ GLOBAL_POLICY_MAX_NUM_WI);
- policies->global_flags = 0;
if (i915->params.reset < 2)
- policies->global_flags |= GLOBAL_POLICY_DISABLE_ENGINE_RESET;
+ global_flags |= GLOBAL_POLICY_DISABLE_ENGINE_RESET;
- policies->is_valid = 1;
+ ads_blob_write(guc, policies.global_flags, global_flags);
+ ads_blob_write(guc, policies.is_valid, 1);
}
void intel_guc_ads_print_policy_info(struct intel_guc *guc,
struct drm_printer *dp)
{
- struct __guc_ads_blob *blob = guc->ads_blob;
-
- if (unlikely(!blob))
+ if (unlikely(dma_buf_map_is_null(>ads_map)))
return;
drm_printf(dp, "Global scheduling policies:\n");
- drm_printf(dp, " DPC promote time = %u\n",
blob->policies.dpc_promote_time);
- drm_printf(dp, " Max num work items = %u\n",
blob->policies.max_num_work_items);
- drm_printf(dp, " Flags = %u\n",
blob->policies.global_flags);
+ drm_printf(dp, " DPC promote time = %u\n",
+ ads_blob_read(guc, policies.dpc_promote_time));
+ drm_printf(dp, " Max num work items = %u\n",
+ ads_blob_read(guc, policies.max_num_work_items));
+ drm_printf(dp, " Flags = %u\n",
+ ads_blob_read(guc, policies.global_flags));
}
static int guc_action_policies_update(struct intel_guc *guc, u32 policy_offset)
@@ -171,23 +175,24 @@ static int guc_action_policies_update(struct intel_guc
*guc, u32 policy_offset)
int intel_guc_global_policies_update(struct intel_guc *guc)
{
- struct __guc_ads_blob *blob = guc->ads_blob;
struct intel_gt *gt = guc_to_gt(guc);
+ u32 scheduler_policies;
intel_wakeref_t wakeref;
int ret;
- if (!blob)
+ if (dma_buf_map_is_null(>ads_map))
return -EOPNOTSUPP;
- GEM_BUG_ON(!blob->ads.scheduler_policies);
+ scheduler_policies = ads_blob_read(guc, ads.scheduler_policies);
+ GEM_BUG_ON(!scheduler_policies);
- guc_policies_init(guc, >policies);
+ guc_policies_init(guc);
if (!intel_guc_is_ready(guc))
return 0;
with_intel_runtime_pm(>i915->runtime_pm, wakeref)
- ret = guc_action_policies_update(guc,
blob->ads.scheduler_policies);
+ ret = guc_action_policies_update(guc, scheduler_policies);
return ret;
}
@@ -557,7 +562,7 @@ static void __guc_ads_init(struct intel_guc *guc)
u32 base;
/* GuC scheduling policies */
- guc_policies_init(guc, >policies);
+ guc_policies_init(guc);
/* System info */
fill_engine_enable_masks(gt, >system_info);
--
2.35.0
[Intel-gfx] [PATCH 11/19] drm/i915/guc: Convert golden context prep to dma_buf_map
Use the saved ads_map to prepare the golden context. One difference from
the init context is that this function can be called before there is a
gem object (and thus the guc->ads_map) to calculare the size of the
golden context that should be allocated for that object.
So in this case the function needs to be prepared for not having the
system_info with enabled engines filled out. To accomplish that an
info_map is prepared on the side to point either to the gem object
or the local variable on the stack. This allows making
fill_engine_enable_masks() operate always with a dma_buf_map
argument.
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 52 +-
1 file changed, 32 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 15990c229b54..dd9ec47eed16 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -67,6 +67,12 @@ struct __guc_ads_blob {
dma_buf_map_write_field(&(guc_)->ads_map, struct __guc_ads_blob,\
field_, val_)
+#define info_map_write(map_, field_, val_) \
+ dma_buf_map_write_field(map_, struct guc_gt_system_info, field_, val_)
+
+#define info_map_read(map_, field_) \
+ dma_buf_map_read_field(map_, struct guc_gt_system_info, field_)
+
static u32 guc_ads_regset_size(struct intel_guc *guc)
{
GEM_BUG_ON(!guc->ads_regset_size);
@@ -378,24 +384,24 @@ static void guc_mmio_reg_state_init(struct intel_guc *guc,
}
static void fill_engine_enable_masks(struct intel_gt *gt,
-struct guc_gt_system_info *info)
+struct dma_buf_map *info_map)
{
- info->engine_enabled_masks[GUC_RENDER_CLASS] = 1;
- info->engine_enabled_masks[GUC_BLITTER_CLASS] = 1;
- info->engine_enabled_masks[GUC_VIDEO_CLASS] = VDBOX_MASK(gt);
- info->engine_enabled_masks[GUC_VIDEOENHANCE_CLASS] = VEBOX_MASK(gt);
+ info_map_write(info_map, engine_enabled_masks[GUC_RENDER_CLASS], 1);
+ info_map_write(info_map, engine_enabled_masks[GUC_BLITTER_CLASS], 1);
+ info_map_write(info_map, engine_enabled_masks[GUC_VIDEO_CLASS],
VDBOX_MASK(gt));
+ info_map_write(info_map, engine_enabled_masks[GUC_VIDEOENHANCE_CLASS],
VEBOX_MASK(gt));
}
#define LR_HW_CONTEXT_SIZE (80 * sizeof(u32))
#define LRC_SKIP_SIZE (LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE)
-static int guc_prep_golden_context(struct intel_guc *guc,
- struct __guc_ads_blob *blob)
+static int guc_prep_golden_context(struct intel_guc *guc)
{
struct intel_gt *gt = guc_to_gt(guc);
u32 addr_ggtt, offset;
u32 total_size = 0, alloc_size, real_size;
u8 engine_class, guc_class;
- struct guc_gt_system_info *info, local_info;
+ struct guc_gt_system_info local_info;
+ struct dma_buf_map info_map;
/*
* Reserve the memory for the golden contexts and point GuC at it but
@@ -409,14 +415,15 @@ static int guc_prep_golden_context(struct intel_guc *guc,
* GuC will also validate that the LRC base + size fall within the
* allowed GGTT range.
*/
- if (blob) {
+ if (!dma_buf_map_is_null(>ads_map)) {
offset = guc_ads_golden_ctxt_offset(guc);
addr_ggtt = intel_guc_ggtt_offset(guc, guc->ads_vma) + offset;
- info = >system_info;
+ info_map = DMA_BUF_MAP_INIT_OFFSET(>ads_map,
+ offsetof(struct
__guc_ads_blob, system_info));
} else {
memset(_info, 0, sizeof(local_info));
- info = _info;
- fill_engine_enable_masks(gt, info);
+ dma_buf_map_set_vaddr(_map, _info);
+ fill_engine_enable_masks(gt, _map);
}
for (engine_class = 0; engine_class <= MAX_ENGINE_CLASS;
++engine_class) {
@@ -425,14 +432,14 @@ static int guc_prep_golden_context(struct intel_guc *guc,
guc_class = engine_class_to_guc_class(engine_class);
- if (!info->engine_enabled_masks[guc_class])
+ if (!info_map_read(_map, engine_enabled_masks[guc_class]))
continue;
real_size = intel_engine_context_size(gt, engine_class);
alloc_size = PAGE_ALIGN(real_size);
total_size += alloc_size;
- if (!blob)
+ if (dma_buf_map_is_null(>ads_map))
continue;
/*
@@ -446,12 +453,15 @@ static int guc_prep_golden_context(struct intel_guc *guc,
* what comes before it in the context image (which is identical
* on all engines).
[Intel-gfx] [PATCH 03/19] drm/i915/gt: Add helper for shmem copy to dma_buf_map
Add a variant of shmem_read() that takes a dma_buf_map pointer rather
than a plain pointer as argument. It's mostly a copy __shmem_rw() but
adapting the api and removing the write support since there's currently
only need to use dma_buf_map as destination.
Reworking __shmem_rw() to share the implementation was tempting, but
finding a good balance between reuse and clarity pushed towards a little
code duplication. Since the function is small, just add the similar
function with a copy/paste/adapt approach.
Cc: Matt Roper
Cc: Joonas Lahtinen
Cc: Tvrtko Ursulin
Cc: David Airlie
Cc: Daniel Vetter
Cc: Matthew Auld
Cc: Thomas Hellström
Cc: Maarten Lankhorst
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/shmem_utils.c | 32 +++
drivers/gpu/drm/i915/gt/shmem_utils.h | 3 +++
2 files changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/shmem_utils.c
b/drivers/gpu/drm/i915/gt/shmem_utils.c
index 0683b27a3890..d7968e68ccfb 100644
--- a/drivers/gpu/drm/i915/gt/shmem_utils.c
+++ b/drivers/gpu/drm/i915/gt/shmem_utils.c
@@ -3,6 +3,7 @@
* Copyright © 2020 Intel Corporation
*/
+#include
#include
#include
#include
@@ -123,6 +124,37 @@ static int __shmem_rw(struct file *file, loff_t off,
return 0;
}
+int shmem_read_to_dma_buf_map(struct file *file, loff_t off,
+ struct dma_buf_map *map, size_t len)
+{
+ struct dma_buf_map map_iter = *map;
+ unsigned long pfn;
+
+ for (pfn = off >> PAGE_SHIFT; len; pfn++) {
+ unsigned int this =
+ min_t(size_t, PAGE_SIZE - offset_in_page(off), len);
+ struct page *page;
+ void *vaddr;
+
+ page = shmem_read_mapping_page_gfp(file->f_mapping, pfn,
+ GFP_KERNEL);
+ if (IS_ERR(page))
+ return PTR_ERR(page);
+
+ vaddr = kmap(page);
+ dma_buf_map_memcpy_to(_iter, vaddr + offset_in_page(off),
this);
+ mark_page_accessed(page);
+ kunmap(page);
+ put_page(page);
+
+ len -= this;
+ dma_buf_map_incr(_iter, this);
+ off = 0;
+ }
+
+ return 0;
+}
+
int shmem_read(struct file *file, loff_t off, void *dst, size_t len)
{
return __shmem_rw(file, off, dst, len, false);
diff --git a/drivers/gpu/drm/i915/gt/shmem_utils.h
b/drivers/gpu/drm/i915/gt/shmem_utils.h
index c1669170c351..a3d4ce966f74 100644
--- a/drivers/gpu/drm/i915/gt/shmem_utils.h
+++ b/drivers/gpu/drm/i915/gt/shmem_utils.h
@@ -8,6 +8,7 @@
#include
+struct dma_buf_map;
struct drm_i915_gem_object;
struct file;
@@ -17,6 +18,8 @@ struct file *shmem_create_from_object(struct
drm_i915_gem_object *obj);
void *shmem_pin_map(struct file *file);
void shmem_unpin_map(struct file *file, void *ptr);
+int shmem_read_to_dma_buf_map(struct file *file, loff_t off,
+ struct dma_buf_map *map, size_t len);
int shmem_read(struct file *file, loff_t off, void *dst, size_t len);
int shmem_write(struct file *file, loff_t off, void *src, size_t len);
--
2.35.0
[Intel-gfx] [PATCH 05/19] drm/i915/guc: Add read/write helpers for ADS blob
Add helpers on top of dma_buf_map_read_field() /
dma_buf_map_write_field() functions so they always use the right
arguments and make code easier to read.
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index c012858376f0..01d2c1ead680 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -59,6 +59,14 @@ struct __guc_ads_blob {
struct guc_mmio_reg regset[0];
} __packed;
+#define ads_blob_read(guc_, field_)\
+ dma_buf_map_read_field(&(guc_)->ads_map, struct __guc_ads_blob, \
+ field_)
+
+#define ads_blob_write(guc_, field_, val_) \
+ dma_buf_map_write_field(&(guc_)->ads_map, struct __guc_ads_blob,\
+ field_, val_)
+
static u32 guc_ads_regset_size(struct intel_guc *guc)
{
GEM_BUG_ON(!guc->ads_regset_size);
--
2.35.0
[Intel-gfx] [PATCH 13/19] drm/i915/guc: Convert mapping table to dma_buf_map
Use dma_buf_map to write the fields system_info.mapping_table[][].
Since we already have the info_map around where needed, just use it
instead of going through guc->ads_map.
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 8e4768289792..dca7c3db9cdd 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -204,7 +204,7 @@ int intel_guc_global_policies_update(struct intel_guc *guc)
}
static void guc_mapping_table_init(struct intel_gt *gt,
- struct guc_gt_system_info *system_info)
+ struct dma_buf_map *info_map)
{
unsigned int i, j;
struct intel_engine_cs *engine;
@@ -213,14 +213,14 @@ static void guc_mapping_table_init(struct intel_gt *gt,
/* Table must be set to invalid values for entries not used */
for (i = 0; i < GUC_MAX_ENGINE_CLASSES; ++i)
for (j = 0; j < GUC_MAX_INSTANCES_PER_CLASS; ++j)
- system_info->mapping_table[i][j] =
- GUC_MAX_INSTANCES_PER_CLASS;
+ info_map_write(info_map, mapping_table[i][j],
+ GUC_MAX_INSTANCES_PER_CLASS);
for_each_engine(engine, gt, id) {
u8 guc_class = engine_class_to_guc_class(engine->class);
-
system_info->mapping_table[guc_class][ilog2(engine->logical_mask)] =
- engine->instance;
+ info_map_write(info_map,
mapping_table[guc_class][ilog2(engine->logical_mask)],
+ engine->instance);
}
}
@@ -595,7 +595,7 @@ static void __guc_ads_init(struct intel_guc *guc)
/* Golden contexts for re-initialising after a watchdog reset */
guc_prep_golden_context(guc);
- guc_mapping_table_init(guc_to_gt(guc), >system_info);
+ guc_mapping_table_init(guc_to_gt(guc), _map);
base = intel_guc_ggtt_offset(guc, guc->ads_vma);
--
2.35.0
[Intel-gfx] [PATCH 01/19] dma-buf-map: Add read/write helpers
In certain situations it's useful to be able to read or write to an
offset that is calculated by having the memory layout given by a struct
declaration. Usually we are going to read/write a u8, u16, u32 or u64.
Add a pair of macros dma_buf_map_read_field()/dma_buf_map_write_field()
to calculate the offset of a struct member and memcpy the data from/to
the dma_buf_map. We could use readb, readw, readl, readq and the write*
counterparts, however due to alignment issues this may not work on all
architectures. If alignment needs to be checked to call the right
function, it's not possible to decide at compile-time which function to
call: so just leave the decision to the memcpy function that will do
exactly that on IO memory or dereference the pointer.
Cc: Sumit Semwal
Cc: Christian König
Cc: linux-me...@vger.kernel.org
Cc: dri-de...@lists.freedesktop.org
Cc: linaro-mm-...@lists.linaro.org
Cc: linux-ker...@vger.kernel.org
Signed-off-by: Lucas De Marchi
---
include/linux/dma-buf-map.h | 81 +
1 file changed, 81 insertions(+)
diff --git a/include/linux/dma-buf-map.h b/include/linux/dma-buf-map.h
index 19fa0b5ae5ec..65e927d9ce33 100644
--- a/include/linux/dma-buf-map.h
+++ b/include/linux/dma-buf-map.h
@@ -6,6 +6,7 @@
#ifndef __DMA_BUF_MAP_H__
#define __DMA_BUF_MAP_H__
+#include
#include
#include
@@ -229,6 +230,46 @@ static inline void dma_buf_map_clear(struct dma_buf_map
*map)
}
}
+/**
+ * dma_buf_map_memcpy_to_offset - Memcpy into offset of dma-buf mapping
+ * @dst: The dma-buf mapping structure
+ * @offset:The offset from which to copy
+ * @src: The source buffer
+ * @len: The number of byte in src
+ *
+ * Copies data into a dma-buf mapping with an offset. The source buffer is in
+ * system memory. Depending on the buffer's location, the helper picks the
+ * correct method of accessing the memory.
+ */
+static inline void dma_buf_map_memcpy_to_offset(struct dma_buf_map *dst,
size_t offset,
+ const void *src, size_t len)
+{
+ if (dst->is_iomem)
+ memcpy_toio(dst->vaddr_iomem + offset, src, len);
+ else
+ memcpy(dst->vaddr + offset, src, len);
+}
+
+/**
+ * dma_buf_map_memcpy_from_offset - Memcpy from offset of dma-buf mapping into
system memory
+ * @dst: Destination in system memory
+ * @src: The dma-buf mapping structure
+ * @src: The offset from which to copy
+ * @len: The number of byte in src
+ *
+ * Copies data from a dma-buf mapping with an offset. The dest buffer is in
+ * system memory. Depending on the mapping location, the helper picks the
+ * correct method of accessing the memory.
+ */
+static inline void dma_buf_map_memcpy_from_offset(void *dst, const struct
dma_buf_map *src,
+ size_t offset, size_t len)
+{
+ if (src->is_iomem)
+ memcpy_fromio(dst, src->vaddr_iomem + offset, len);
+ else
+ memcpy(dst, src->vaddr + offset, len);
+}
+
/**
* dma_buf_map_memcpy_to - Memcpy into dma-buf mapping
* @dst: The dma-buf mapping structure
@@ -263,4 +304,44 @@ static inline void dma_buf_map_incr(struct dma_buf_map
*map, size_t incr)
map->vaddr += incr;
}
+/**
+ * dma_buf_map_read_field - Read struct member from dma-buf mapping with
+ * arbitrary size and handling un-aligned accesses
+ *
+ * @map__: The dma-buf mapping structure
+ * @type__:The struct to be used containing the field to read
+ * @field__: Member from struct we want to read
+ *
+ * Read a value from dma-buf mapping calculating the offset and size: this
assumes
+ * the dma-buf mapping is aligned with a a struct type__. A single u8, u16, u32
+ * or u64 can be read, based on the offset and size of type__.field__.
+ */
+#define dma_buf_map_read_field(map__, type__, field__) ({
\
+ type__ *t__;
\
+ typeof(t__->field__) val__;
\
+ dma_buf_map_memcpy_from_offset(__, map__, offsetof(type__,
field__),\
+ sizeof(t__->field__));
\
+ val__;
\
+})
+
+/**
+ * dma_buf_map_write_field - Write struct member to the dma-buf mapping with
+ * arbitrary size and handling un-aligned accesses
+ *
+ * @map__: The dma-buf mapping structure
+ * @type__:The struct to be used containing the field to write
+ * @field__: Member from struct we want to write
+ * @val__: Value to be written
+ *
+ * Write a value to the dma-buf mapping calculating the offset and size.
+ * A single u8, u16, u32 or u64 can be written based on the offset and size of
+ * type__.field__.
+ */
+#define dma_buf_map_write_field(map__, type__, field__,
[Intel-gfx] [PATCH 02/19] dma-buf-map: Add helper to initialize second map
When dma_buf_map struct is passed around, it's useful to be able to
initialize a second map that takes care of reading/writing to an offset
of the original map.
Add a helper that copies the struct and add the offset to the proper
address.
Cc: Sumit Semwal
Cc: Christian König
Cc: linux-me...@vger.kernel.org
Cc: dri-de...@lists.freedesktop.org
Cc: linaro-mm-...@lists.linaro.org
Cc: linux-ker...@vger.kernel.org
Signed-off-by: Lucas De Marchi
---
include/linux/dma-buf-map.h | 29 +
1 file changed, 29 insertions(+)
diff --git a/include/linux/dma-buf-map.h b/include/linux/dma-buf-map.h
index 65e927d9ce33..3514a859f628 100644
--- a/include/linux/dma-buf-map.h
+++ b/include/linux/dma-buf-map.h
@@ -131,6 +131,35 @@ struct dma_buf_map {
.is_iomem = false, \
}
+/**
+ * DMA_BUF_MAP_INIT_OFFSET - Initializes struct dma_buf_map from another
dma_buf_map
+ * @map_: The dma-buf mapping structure to copy from
+ * @offset:Offset to add to the other mapping
+ *
+ * Initializes a new dma_buf_struct based on another. This is the equivalent
of doing:
+ *
+ * .. code-block: c
+ *
+ * dma_buf_map map = other_map;
+ * dma_buf_map_incr(, );
+ *
+ * Example usage:
+ *
+ * .. code-block: c
+ *
+ * void foo(struct device *dev, struct dma_buf_map *base_map)
+ * {
+ * ...
+ * struct dma_buf_map = DMA_BUF_MAP_INIT_OFFSET(base_map,
FIELD_OFFSET);
+ * ...
+ * }
+ */
+#define DMA_BUF_MAP_INIT_OFFSET(map_, offset_) (struct dma_buf_map)\
+ { \
+ .vaddr = (map_)->vaddr + (offset_), \
+ .is_iomem = (map_)->is_iomem, \
+ }
+
/**
* dma_buf_map_set_vaddr - Sets a dma-buf mapping structure to an address in
system memory
* @map: The dma-buf mapping structure
--
2.35.0
[Intel-gfx] [PATCH 09/19] dma-buf-map: Add wrapper over memset
Just like memcpy_toio(), there is also need to write a direct value to a
memory block. Add dma_buf_map_memset() to abstract memset() vs memset_io()
Cc: Matt Roper
Cc: Sumit Semwal
Cc: Christian König
Cc: linux-me...@vger.kernel.org
Cc: dri-de...@lists.freedesktop.org
Cc: linaro-mm-...@lists.linaro.org
Cc: linux-ker...@vger.kernel.org
Signed-off-by: Lucas De Marchi
---
include/linux/dma-buf-map.h | 17 +
1 file changed, 17 insertions(+)
diff --git a/include/linux/dma-buf-map.h b/include/linux/dma-buf-map.h
index 3514a859f628..c9fb04264cd0 100644
--- a/include/linux/dma-buf-map.h
+++ b/include/linux/dma-buf-map.h
@@ -317,6 +317,23 @@ static inline void dma_buf_map_memcpy_to(struct
dma_buf_map *dst, const void *sr
memcpy(dst->vaddr, src, len);
}
+/**
+ * dma_buf_map_memset - Memset into dma-buf mapping
+ * @dst: The dma-buf mapping structure
+ * @value: The value to set
+ * @len: The number of bytes to set in dst
+ *
+ * Set value in dma-buf mapping. Depending on the buffer's location, the helper
+ * picks the correct method of accessing the memory.
+ */
+static inline void dma_buf_map_memset(struct dma_buf_map *dst, int value,
size_t len)
+{
+ if (dst->is_iomem)
+ memset_io(dst->vaddr_iomem, value, len);
+ else
+ memset(dst->vaddr, value, len);
+}
+
/**
* dma_buf_map_incr - Increments the address stored in a dma-buf mapping
* @map: The dma-buf mapping structure
--
2.35.0
[Intel-gfx] [PATCH 06/19] drm/i915/guc: Convert golden context init to dma_buf_map
Now the map is saved during creation, so use it to initialize the
golden context, reading from shmem and writing to either system or IO
memory.
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 25 +++---
1 file changed, 13 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 01d2c1ead680..bcf52ac4fe35 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -473,18 +473,17 @@ static struct intel_engine_cs *find_engine_state(struct
intel_gt *gt, u8 engine_
static void guc_init_golden_context(struct intel_guc *guc)
{
- struct __guc_ads_blob *blob = guc->ads_blob;
struct intel_engine_cs *engine;
struct intel_gt *gt = guc_to_gt(guc);
+ struct dma_buf_map golden_context_map;
u32 addr_ggtt, offset;
u32 total_size = 0, alloc_size, real_size;
u8 engine_class, guc_class;
- u8 *ptr;
if (!intel_uc_uses_guc_submission(>uc))
return;
- GEM_BUG_ON(!blob);
+ GEM_BUG_ON(dma_buf_map_is_null(>ads_map));
/*
* Go back and fill in the golden context data now that it is
@@ -492,15 +491,15 @@ static void guc_init_golden_context(struct intel_guc *guc)
*/
offset = guc_ads_golden_ctxt_offset(guc);
addr_ggtt = intel_guc_ggtt_offset(guc, guc->ads_vma) + offset;
- ptr = ((u8 *)blob) + offset;
+
+ golden_context_map = DMA_BUF_MAP_INIT_OFFSET(>ads_map, offset);
for (engine_class = 0; engine_class <= MAX_ENGINE_CLASS;
++engine_class) {
if (engine_class == OTHER_CLASS)
continue;
guc_class = engine_class_to_guc_class(engine_class);
-
- if (!blob->system_info.engine_enabled_masks[guc_class])
+ if (!ads_blob_read(guc,
system_info.engine_enabled_masks[guc_class]))
continue;
real_size = intel_engine_context_size(gt, engine_class);
@@ -511,18 +510,20 @@ static void guc_init_golden_context(struct intel_guc *guc)
if (!engine) {
drm_err(>i915->drm, "No engine state recorded for
class %d!\n",
engine_class);
- blob->ads.eng_state_size[guc_class] = 0;
- blob->ads.golden_context_lrca[guc_class] = 0;
+ ads_blob_write(guc, ads.eng_state_size[guc_class], 0);
+ ads_blob_write(guc, ads.golden_context_lrca[guc_class],
0);
continue;
}
- GEM_BUG_ON(blob->ads.eng_state_size[guc_class] !=
+ GEM_BUG_ON(ads_blob_read(guc, ads.eng_state_size[guc_class]) !=
real_size - LRC_SKIP_SIZE);
- GEM_BUG_ON(blob->ads.golden_context_lrca[guc_class] !=
addr_ggtt);
+ GEM_BUG_ON(ads_blob_read(guc,
ads.golden_context_lrca[guc_class]) != addr_ggtt);
+
addr_ggtt += alloc_size;
- shmem_read(engine->default_state, 0, ptr, real_size);
- ptr += alloc_size;
+ shmem_read_to_dma_buf_map(engine->default_state, 0,
+ _context_map, real_size);
+ dma_buf_map_incr(_context_map, alloc_size);
}
GEM_BUG_ON(guc->ads_golden_ctxt_size != total_size);
--
2.35.0
[Intel-gfx] [PATCH 00/19] drm/i915/guc: Refactor ADS access to use dma_buf_map
While porting i915 to arm64 we noticed some issues accessing lmem. Some writes were getting corrupted and the final state of the buffer didn't have exactly what we wrote. This became evident when enabling GuC submission: depending on the number of engines the ADS struct was being corrupted and GuC would reject it, refusin to initialize. >From Documentation/core-api/bus-virt-phys-mapping.rst: This memory is called "PCI memory" or "shared memory" or "IO memory" or whatever, and there is only one way to access it: the readb/writeb and related functions. You should never take the address of such memory, because there is really nothing you can do with such an address: it's not conceptually in the same memory space as "real memory" at all, so you cannot just dereference a pointer. (Sadly, on x86 it **is** in the same memory space, so on x86 it actually works to just deference a pointer, but it's not portable). When reading or writing words directly to IO memory, in order to be portable the Linux kernel provides the abstraction detailed in section "Differences between I/O access functions" of Documentation/driver-api/device-io.rst. This limits our ability to simply overlay our structs on top a buffer and directly access it since that buffer may come from IO memory rather than system memory. Hence the approach taken in intel_guc_ads.c needs to be refactored. This is not the only place in i915 that neeed to be changed, but the one causing the most problems, with a real reproducer. This first set of patch focuses on fixing the gem object to pass the ADS After the addition of a few helpers in the dma_buf_map API, most of intel_guc_ads.c can be converted to use it. The exception is the regset initialization: we'd incur into a lot of extra indirection when reading/writting each register. So the regset is converted to use a temporary buffer allocated on probe, which is then copied to its final location when finishing the initialization or on gt reset. Testing on some discrete cards, after this change we can correctly pass the ADS struct to GuC and have it initialized correctly. thanks Lucas De Marchi Cc: linux-me...@vger.kernel.org Cc: dri-de...@lists.freedesktop.org Cc: linaro-mm-...@lists.linaro.org Cc: linux-ker...@vger.kernel.org Cc: Christian König Cc: Daniel Vetter Cc: Daniele Ceraolo Spurio Cc: David Airlie Cc: John Harrison Cc: Joonas Lahtinen Cc: Maarten Lankhorst Cc: Matt Roper Cc: Matthew Auld Cc: Matthew Brost Cc: Sumit Semwal Cc: Thomas Hellström Cc: Tvrtko Ursulin Lucas De Marchi (19): dma-buf-map: Add read/write helpers dma-buf-map: Add helper to initialize second map drm/i915/gt: Add helper for shmem copy to dma_buf_map drm/i915/guc: Keep dma_buf_map of ads_blob around drm/i915/guc: Add read/write helpers for ADS blob drm/i915/guc: Convert golden context init to dma_buf_map drm/i915/guc: Convert policies update to dma_buf_map drm/i915/guc: Convert engine record to dma_buf_map dma-buf-map: Add wrapper over memset drm/i915/guc: Convert guc_ads_private_data_reset to dma_buf_map drm/i915/guc: Convert golden context prep to dma_buf_map drm/i915/guc: Replace check for golden context size drm/i915/guc: Convert mapping table to dma_buf_map drm/i915/guc: Convert capture list to dma_buf_map drm/i915/guc: Prepare for error propagation drm/i915/guc: Use a single pass to calculate regset drm/i915/guc: Convert guc_mmio_reg_state_init to dma_buf_map drm/i915/guc: Convert __guc_ads_init to dma_buf_map drm/i915/guc: Remove plain ads_blob pointer drivers/gpu/drm/i915/gt/shmem_utils.c | 32 ++ drivers/gpu/drm/i915/gt/shmem_utils.h | 3 + drivers/gpu/drm/i915/gt/uc/intel_guc.h| 14 +- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 374 +++--- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h| 3 +- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 11 +- include/linux/dma-buf-map.h | 127 ++ 7 files changed, 405 insertions(+), 159 deletions(-) -- 2.35.0
[Intel-gfx] [PATCH 04/19] drm/i915/guc: Keep dma_buf_map of ads_blob around
Convert intel_guc_ads_create() and initialization to use dma_buf_map
rather than plain pointer and save it in the guc struct. This will help
with additional updates to the ads_blob after the
creation/initialization by abstracting the IO vs system memory.
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h | 4 +++-
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 6 ++
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 697d9d66acef..e2e0df1c3d91 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -6,8 +6,9 @@
#ifndef _INTEL_GUC_H_
#define _INTEL_GUC_H_
-#include
#include
+#include
+#include
#include "intel_uncore.h"
#include "intel_guc_fw.h"
@@ -148,6 +149,7 @@ struct intel_guc {
struct i915_vma *ads_vma;
/** @ads_blob: contents of the GuC ADS */
struct __guc_ads_blob *ads_blob;
+ struct dma_buf_map ads_map;
/** @ads_regset_size: size of the save/restore regsets in the ADS */
u32 ads_regset_size;
/** @ads_golden_ctxt_size: size of the golden contexts in the ADS */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 668bf4ac9b0c..c012858376f0 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -623,6 +623,11 @@ int intel_guc_ads_create(struct intel_guc *guc)
if (ret)
return ret;
+ if (i915_gem_object_is_lmem(guc->ads_vma->obj))
+ dma_buf_map_set_vaddr_iomem(>ads_map, (void __iomem
*)guc->ads_blob);
+ else
+ dma_buf_map_set_vaddr(>ads_map, guc->ads_blob);
+
__guc_ads_init(guc);
return 0;
@@ -644,6 +649,7 @@ void intel_guc_ads_destroy(struct intel_guc *guc)
{
i915_vma_unpin_and_release(>ads_vma, I915_VMA_RELEASE_MAP);
guc->ads_blob = NULL;
+ dma_buf_map_clear(>ads_map);
}
static void guc_ads_private_data_reset(struct intel_guc *guc)
--
2.35.0
Re: [Intel-gfx] [PATCH 2/4] drm/i915/guc: Cancel requests immediately
On Wed, Jan 26, 2022 at 10:58:46AM -0800, John Harrison wrote:
> On 1/24/2022 07:01, Matthew Brost wrote:
> > Change the preemption timeout to the smallest possible value (1 us) when
> > disabling scheduling to cancel a request and restore it after
> > cancellation. This not only cancels the request as fast as possible, it
> > fixes a bug where the preemption timeout is 0 which results in the
> > schedule disable hanging forever.
> Shouldn't there be an 'if' in the above statement? The pre-emption timeout
> is not normally zero.
>
Yes. Will reword.
> >
> > Reported-by: Jani Saarinen
> > Fixes: 62eaf0ae217d4 ("drm/i915/guc: Support request cancellation")
> > Link: https://gitlab.freedesktop.org/drm/intel/-/issues/4960
> > Signed-off-by: Matthew Brost
> > ---
> > drivers/gpu/drm/i915/gt/intel_context_types.h | 5 ++
> > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 46 +++
> > 2 files changed, 31 insertions(+), 20 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
> > b/drivers/gpu/drm/i915/gt/intel_context_types.h
> > index 30cd81ad8911a..730998823dbea 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_context_types.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
> > @@ -198,6 +198,11 @@ struct intel_context {
> > * each priority bucket
> > */
> > u32 prio_count[GUC_CLIENT_PRIORITY_NUM];
> > + /**
> > +* @preemption_timeout: preemption timeout of the context, used
> > +* to restore this value after request cancellation
> > +*/
> > + u32 preemption_timeout;
> > } guc_state;
> > struct {
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > index 3918f1be114fa..966947c450253 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > @@ -2147,7 +2147,8 @@ static inline u32 get_children_join_value(struct
> > intel_context *ce,
> > return __get_parent_scratch(ce)->join[child_index].semaphore;
> > }
> > -static void guc_context_policy_init(struct intel_engine_cs *engine,
> > +static void guc_context_policy_init(struct intel_context *ce,
> > + struct intel_engine_cs *engine,
> > struct guc_lrc_desc *desc)
> Shouldn't engine be before ce? The more general structure usually goes
> first.
>
Sure. Fix fix this in the next rev.
Matt
> John.
>
> > {
> > desc->policy_flags = 0;
> > @@ -2157,7 +2158,8 @@ static void guc_context_policy_init(struct
> > intel_engine_cs *engine,
> > /* NB: For both of these, zero means disabled. */
> > desc->execution_quantum = engine->props.timeslice_duration_ms * 1000;
> > - desc->preemption_timeout = engine->props.preempt_timeout_ms * 1000;
> > + ce->guc_state.preemption_timeout = engine->props.preempt_timeout_ms *
> > 1000;
> > + desc->preemption_timeout = ce->guc_state.preemption_timeout;
> > }
> > static int guc_lrc_desc_pin(struct intel_context *ce, bool loop)
> > @@ -2193,7 +2195,7 @@ static int guc_lrc_desc_pin(struct intel_context *ce,
> > bool loop)
> > desc->hw_context_desc = ce->lrc.lrca;
> > desc->priority = ce->guc_state.prio;
> > desc->context_flags = CONTEXT_REGISTRATION_FLAG_KMD;
> > - guc_context_policy_init(engine, desc);
> > + guc_context_policy_init(ce, engine, desc);
> > /*
> > * If context is a parent, we need to register a process descriptor
> > @@ -2226,7 +2228,7 @@ static int guc_lrc_desc_pin(struct intel_context *ce,
> > bool loop)
> > desc->hw_context_desc = child->lrc.lrca;
> > desc->priority = ce->guc_state.prio;
> > desc->context_flags = CONTEXT_REGISTRATION_FLAG_KMD;
> > - guc_context_policy_init(engine, desc);
> > + guc_context_policy_init(child, engine, desc);
> > }
> > clear_children_join_go_memory(ce);
> > @@ -2409,6 +2411,19 @@ static u16 prep_context_pending_disable(struct
> > intel_context *ce)
> > return ce->guc_id.id;
> > }
> > +static void __guc_context_set_preemption_timeout(struct intel_guc *guc,
> > +u16 guc_id,
> > +u32 preemption_timeout)
> > +{
> > + u32 action[] = {
> > + INTEL_GUC_ACTION_SET_CONTEXT_PREEMPTION_TIMEOUT,
> > + guc_id,
> > + preemption_timeout
> > + };
> > +
> > + intel_guc_send_busy_loop(guc, action, ARRAY_SIZE(action), 0, true);
> > +}
> > +
> > static struct i915_sw_fence *guc_context_block(struct intel_context *ce)
> > {
> > struct intel_guc *guc = ce_to_guc(ce);
> > @@ -2442,8 +2457,10 @@ static struct i915_sw_fence
> > *guc_context_block(struct intel_context *ce)
> > spin_unlock_irqrestore(>guc_state.lock, flags);
> > -
Re: [Intel-gfx] [PATCH 3/4] drm/i915/execlists: Fix execlists request cancellation corner case
On Wed, Jan 26, 2022 at 11:03:24AM -0800, John Harrison wrote:
> On 1/24/2022 07:01, Matthew Brost wrote:
> > More than 1 request can be submitted to a single ELSP at a time if
> > multiple requests are ready run to on the same context. When a request
> > is canceled it is marked bad, an idle pulse is triggered to the engine
> > (high priority kernel request), the execlists scheduler sees that
> > running request is bad and sets preemption timeout to minimum value (1
> > ms). This fails to work if multiple requests are combined on the ELSP as
> > only the most recent request is stored in the execlists schedule (the
> > request stored in the ELSP isn't marked bad, thus preemption timeout
> > isn't set to the minimum value). If the preempt timeout is configured to
> > zero, the engine is permanently hung. This is shown by an upcoming
> > selftest.
> >
> > To work around this, mark the idle pulse with a flag to force a preempt
> > with the minimum value.
> >
> > Fixes: 38b237eab2bc7 ("drm/i915: Individual request cancellation")
> > Signed-off-by: Matthew Brost
> > ---
> > .../gpu/drm/i915/gt/intel_engine_heartbeat.c | 23 +++
> > .../gpu/drm/i915/gt/intel_engine_heartbeat.h | 1 +
> > .../drm/i915/gt/intel_execlists_submission.c | 18 ++-
> > drivers/gpu/drm/i915/i915_request.h | 6 +
> > 4 files changed, 38 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
> > b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
> > index a3698f611f457..efd1c719b4072 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
> > @@ -243,7 +243,8 @@ void intel_engine_init_heartbeat(struct intel_engine_cs
> > *engine)
> > INIT_DELAYED_WORK(>heartbeat.work, heartbeat);
> > }
> > -static int __intel_engine_pulse(struct intel_engine_cs *engine)
> > +static int __intel_engine_pulse(struct intel_engine_cs *engine,
> > + bool force_preempt)
> > {
> > struct i915_sched_attr attr = { .priority = I915_PRIORITY_BARRIER };
> > struct intel_context *ce = engine->kernel_context;
> > @@ -258,6 +259,8 @@ static int __intel_engine_pulse(struct intel_engine_cs
> > *engine)
> > return PTR_ERR(rq);
> > __set_bit(I915_FENCE_FLAG_SENTINEL, >fence.flags);
> > + if (force_preempt)
> > + __set_bit(I915_FENCE_FLAG_FORCE_PREEMPT, >fence.flags);
> > heartbeat_commit(rq, );
> > GEM_BUG_ON(rq->sched.attr.priority < I915_PRIORITY_BARRIER);
> > @@ -299,7 +302,7 @@ int intel_engine_set_heartbeat(struct intel_engine_cs
> > *engine,
> > /* recheck current execution */
> > if (intel_engine_has_preemption(engine)) {
> > - err = __intel_engine_pulse(engine);
> > + err = __intel_engine_pulse(engine, false);
> > if (err)
> > set_heartbeat(engine, saved);
> > }
> > @@ -312,7 +315,8 @@ int intel_engine_set_heartbeat(struct intel_engine_cs
> > *engine,
> > return err;
> > }
> > -int intel_engine_pulse(struct intel_engine_cs *engine)
> > +static int _intel_engine_pulse(struct intel_engine_cs *engine,
> > + bool force_preempt)
> > {
> > struct intel_context *ce = engine->kernel_context;
> > int err;
> > @@ -325,7 +329,7 @@ int intel_engine_pulse(struct intel_engine_cs *engine)
> > err = -EINTR;
> > if (!mutex_lock_interruptible(>timeline->mutex)) {
> > - err = __intel_engine_pulse(engine);
> > + err = __intel_engine_pulse(engine, force_preempt);
> > mutex_unlock(>timeline->mutex);
> > }
> > @@ -334,6 +338,17 @@ int intel_engine_pulse(struct intel_engine_cs *engine)
> > return err;
> > }
> > +int intel_engine_pulse(struct intel_engine_cs *engine)
> > +{
> > + return _intel_engine_pulse(engine, false);
> > +}
> > +
> > +
> > +int intel_engine_pulse_force_preempt(struct intel_engine_cs *engine)
> > +{
> > + return _intel_engine_pulse(engine, true);
> > +}
> > +
> > int intel_engine_flush_barriers(struct intel_engine_cs *engine)
> > {
> > struct i915_sched_attr attr = { .priority = I915_PRIORITY_MIN };
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
> > b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
> > index 5da6d809a87a2..d9c8386754cb3 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
> > @@ -21,6 +21,7 @@ void intel_gt_park_heartbeats(struct intel_gt *gt);
> > void intel_gt_unpark_heartbeats(struct intel_gt *gt);
> > int intel_engine_pulse(struct intel_engine_cs *engine);
> > +int intel_engine_pulse_force_preempt(struct intel_engine_cs *engine);
> > int intel_engine_flush_barriers(struct intel_engine_cs *engine);
> > #endif /* INTEL_ENGINE_HEARTBEAT_H */
> > diff --git
Re: [Intel-gfx] [PATCH 1/3] drm: Stop spamming log with drm_cache message
On Wed, Jan 26, 2022 at 08:24:54PM +0200, Jani Nikula wrote:
On Tue, 25 Jan 2022, Lucas De Marchi wrote:
Only x86 and in some cases PPC have support added in drm_cache.c for the
clflush class of functions. However warning once is sufficient to taint
the log instead of spamming it with "Architecture has no drm_cache.c
support" every few millisecond.
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Thomas Zimmermann
Cc: David Airlie
Cc: Daniel Vetter
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/drm_cache.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
index f19d9acbe959..2d5a4c463a4f 100644
--- a/drivers/gpu/drm/drm_cache.c
+++ b/drivers/gpu/drm/drm_cache.c
@@ -112,7 +112,6 @@ drm_clflush_pages(struct page *pages[], unsigned long
num_pages)
kunmap_atomic(page_virtual);
}
#else
- pr_err("Architecture has no drm_cache.c support\n");
WARN_ON_ONCE(1);
An alternative would be to replace the two lines with:
WARN_ONCE(1, "Architecture has no drm_cache.c support\n");
But I'm not insisting.
I actually like that suggestion. I will change that in the next version.
Thanks
Lucas De Marchi
Re: [Intel-gfx] [2/2] drm/i915/pmu: Fix KMD and GuC race on accessing busyness
Thanks for the offline run through of all the corner
cases we are trying to handle through below codes.
Reviewed-by: Alan Previn
...alan
On Mon, 2022-01-24 at 18:01 -0800, Umesh Nerlige Ramappa wrote:
> GuC updates shared memory and KMD reads it. Since this is not
> synchronized, we run into a race where the value read is inconsistent.
> Sometimes the inconsistency is in reading the upper MSB bytes of the
> last_switch_in value. 2 types of cases are seen - upper 8 bits are zero
> and upper 24 bits are zero. Since these are non-zero values, it is
> not trivial to determine validity of these values. Instead we read the
> values multiple times until they are consistent. In test runs, 3
> attempts results in consistent values. The upper bound is set to 6
> attempts and may need to be tuned as per any new occurences.
>
> Since the duration that gt is parked can vary, the patch also updates
> the gt timestamp on unpark before starting the worker.
>
> v2:
> - Initialize i
> - Use READ_ONCE to access engine record
>
> Fixes: 77cdd054dd2c ("drm/i915/pmu: Connect engine busyness stats from GuC to
> pmu")
> Signed-off-by: Umesh Nerlige Ramappa
> ---
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 58 +--
> 1 file changed, 54 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 66760f5df0c1..75079e17e5b8 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -1114,6 +1114,19 @@ __extend_last_switch(struct intel_guc *guc, u64
> *prev_start, u32 new_start)
> if (new_start == lower_32_bits(*prev_start))
> return;
>
> + /*
> + * When gt is unparked, we update the gt timestamp and start the ping
> + * worker that updates the gt_stamp every POLL_TIME_CLKS. As long as gt
> + * is unparked, all switched in contexts will have a start time that is
> + * within +/- POLL_TIME_CLKS of the most recent gt_stamp.
> + *
> + * If neither gt_stamp nor new_start has rolled over, then the
> + * gt_stamp_hi does not need to be adjusted, however if one of them has
> + * rolled over, we need to adjust gt_stamp_hi accordingly.
> + *
> + * The below conditions address the cases of new_start rollover and
> + * gt_stamp_last rollover respectively.
> + */
> if (new_start < gt_stamp_last &&
> (new_start - gt_stamp_last) <= POLL_TIME_CLKS)
> gt_stamp_hi++;
> @@ -1125,17 +1138,45 @@ __extend_last_switch(struct intel_guc *guc, u64
> *prev_start, u32 new_start)
> *prev_start = ((u64)gt_stamp_hi << 32) | new_start;
> }
>
> -static void guc_update_engine_gt_clks(struct intel_engine_cs *engine)
> +/*
> + * GuC updates shared memory and KMD reads it. Since this is not
> synchronized,
> + * we run into a race where the value read is inconsistent. Sometimes the
> + * inconsistency is in reading the upper MSB bytes of the last_in value when
> + * this race occurs. 2 types of cases are seen - upper 8 bits are zero and
> upper
> + * 24 bits are zero. Since these are non-zero values, it is non-trivial to
> + * determine validity of these values. Instead we read the values multiple
> times
> + * until they are consistent. In test runs, 3 attempts results in consistent
> + * values. The upper bound is set to 6 attempts and may need to be tuned as
> per
> + * any new occurences.
> + */
> +static void __get_engine_usage_record(struct intel_engine_cs *engine,
> + u32 *last_in, u32 *id, u32 *total)
> {
> struct guc_engine_usage_record *rec = intel_guc_engine_usage(engine);
> + int i = 0;
> +
> + do {
> + *last_in = READ_ONCE(rec->last_switch_in_stamp);
> + *id = READ_ONCE(rec->current_context_index);
> + *total = READ_ONCE(rec->total_runtime);
> +
> + if (READ_ONCE(rec->last_switch_in_stamp) == *last_in &&
> + READ_ONCE(rec->current_context_index) == *id &&
> + READ_ONCE(rec->total_runtime) == *total)
> + break;
> + } while (++i < 6);
> +}
> +
> +static void guc_update_engine_gt_clks(struct intel_engine_cs *engine)
> +{
> struct intel_engine_guc_stats *stats = >stats.guc;
> struct intel_guc *guc = >gt->uc.guc;
> - u32 last_switch = rec->last_switch_in_stamp;
> - u32 ctx_id = rec->current_context_index;
> - u32 total = rec->total_runtime;
> + u32 last_switch, ctx_id, total;
>
> lockdep_assert_held(>timestamp.lock);
>
> + __get_engine_usage_record(engine, _switch, _id, );
> +
> stats->running = ctx_id != ~0U && last_switch;
> if (stats->running)
> __extend_last_switch(guc, >start_gt_clk, last_switch);
> @@ -1237,6 +1278,10 @@ static ktime_t guc_engine_busyness(struct
> intel_engine_cs *engine, ktime_t *now)
>
Re: [Intel-gfx] [PATCH 18/20] drm/i915/uapi: forbid ALLOC_TOPDOWN for error capture
Hi Matthew,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-tip/drm-tip]
[cannot apply to drm-intel/for-linux-next drm/drm-next v5.17-rc1 next-20220125]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Matthew-Auld/Initial-support-for-small-BAR-recovery/20220126-232640
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: x86_64-randconfig-a013-20220124
(https://download.01.org/0day-ci/archive/20220127/202201270346.fzrpmvzl-...@intel.com/config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project
2a1b7aa016c0f4b5598806205bdfbab1ea2d92c4)
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
#
https://github.com/0day-ci/linux/commit/33b0a9f1f9810bd16cef89ce1e5787751583661e
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review
Matthew-Auld/Initial-support-for-small-BAR-recovery/20220126-232640
git checkout 33b0a9f1f9810bd16cef89ce1e5787751583661e
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1
O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/drm/i915/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All errors (new ones prefixed by >>):
>> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:3426:6: error: assigning to
>> 'int' from incompatible type 'void'
err = eb_capture_stage();
^ ~
1 error generated.
vim +3426 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
3381
3382 if (args->flags & I915_EXEC_FENCE_OUT) {
3383 out_fence_fd = get_unused_fd_flags(O_CLOEXEC);
3384 if (out_fence_fd < 0) {
3385 err = out_fence_fd;
3386 goto err_in_fence;
3387 }
3388 }
3389
3390 err = eb_create();
3391 if (err)
3392 goto err_out_fence;
3393
3394 GEM_BUG_ON(!eb.lut_size);
3395
3396 err = eb_select_context();
3397 if (unlikely(err))
3398 goto err_destroy;
3399
3400 err = eb_select_engine();
3401 if (unlikely(err))
3402 goto err_context;
3403
3404 err = eb_lookup_vmas();
3405 if (err) {
3406 eb_release_vmas(, true);
3407 goto err_engine;
3408 }
3409
3410 i915_gem_ww_ctx_init(, true);
3411
3412 err = eb_relocate_parse();
3413 if (err) {
3414 /*
3415 * If the user expects the execobject.offset and
3416 * reloc.presumed_offset to be an exact match,
3417 * as for using NO_RELOC, then we cannot update
3418 * the execobject.offset until we have completed
3419 * relocation.
3420 */
3421 args->flags &= ~__EXEC_HAS_RELOC;
3422 goto err_vma;
3423 }
3424
3425 ww_acquire_done();
> 3426 err = eb_capture_stage();
3427 if (err)
3428 goto err_vma;
3429
3430 out_fence = eb_requests_create(, in_fence, out_fence_fd);
3431 if (IS_ERR(out_fence)) {
3432 err = PTR_ERR(out_fence);
3433 out_fence = NULL;
3434 if (eb.requests[0])
3435 goto err_request;
3436 else
3437 goto err_vma;
3438 }
3439
3440 err = eb_submit();
3441
3442 err_request:
3443 eb_requests_get();
3444 err = eb_requests_add(, err);
3445
3446 if (eb.fences)
3447 signal_fence_array(, eb.composite_fence ?
3448 eb.composite_fence :
3449 [0]->fence);
3450
3451 if (out_fence) {
3452 if (err == 0) {
3453 fd_install(out_fence_fd, out_fence->file);
3454 args->rsvd2 &= GENMASK_ULL(31, 0); /* keep
in-fence */
3455 args->rsvd2 |= (u64)out_fence_fd << 32;
3456 out_fence_fd = -1;
3457 } else {
3458 fput(out_fence->file);
3459 }
3460
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Remove all frontbuffer tracking calls from the gem code
== Series Details ==
Series: drm/i915: Remove all frontbuffer tracking calls from the gem code
URL : https://patchwork.freedesktop.org/series/99365/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11145 -> Patchwork_22113
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22113/index.html
Participating hosts (46 -> 43)
--
Additional (1): fi-icl-u2
Missing(4): fi-ctg-p8600 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u
Known issues
Here are the changes found in Patchwork_22113 that come from known issues:
### CI changes ###
Possible fixes
* boot:
- fi-ilk-650: [FAIL][1] -> [PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/fi-ilk-650/boot.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22113/fi-ilk-650/boot.html
### IGT changes ###
Issues hit
* igt@amdgpu/amd_cs_nop@fork-gfx0:
- fi-icl-u2: NOTRUN -> [SKIP][3] ([fdo#109315]) +17 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22113/fi-icl-u2/igt@amdgpu/amd_cs_...@fork-gfx0.html
* igt@amdgpu/amd_cs_nop@nop-compute0:
- fi-ilk-650: NOTRUN -> [SKIP][4] ([fdo#109271]) +39 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22113/fi-ilk-650/igt@amdgpu/amd_cs_...@nop-compute0.html
* igt@gem_exec_suspend@basic-s3:
- fi-skl-6600u: NOTRUN -> [INCOMPLETE][5] ([i915#4547])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22113/fi-skl-6600u/igt@gem_exec_susp...@basic-s3.html
* igt@gem_huc_copy@huc-copy:
- fi-icl-u2: NOTRUN -> [SKIP][6] ([i915#2190])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22113/fi-icl-u2/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-icl-u2: NOTRUN -> [SKIP][7] ([i915#4613]) +3 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22113/fi-icl-u2/igt@gem_lmem_swapp...@parallel-random-engines.html
* igt@kms_chamelium@dp-hpd-fast:
- fi-ilk-650: NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827]) +8
similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22113/fi-ilk-650/igt@kms_chamel...@dp-hpd-fast.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: NOTRUN -> [SKIP][9] ([fdo#111827]) +8 similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22113/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2: NOTRUN -> [SKIP][10] ([fdo#109278]) +2 similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22113/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-icl-u2: NOTRUN -> [SKIP][11] ([fdo#109285])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22113/fi-icl-u2/igt@kms_force_connector_ba...@force-load-detect.html
* igt@prime_vgem@basic-userptr:
- fi-icl-u2: NOTRUN -> [SKIP][12] ([i915#3301])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22113/fi-icl-u2/igt@prime_v...@basic-userptr.html
Possible fixes
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [DMESG-FAIL][13] ([i915#4494]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22113/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [DMESG-WARN][15] ([i915#4269]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22113/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
Re: [Intel-gfx] [PATCH 18/20] drm/i915/uapi: forbid ALLOC_TOPDOWN for error capture
Hi Matthew,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-tip/drm-tip]
[cannot apply to drm-intel/for-linux-next drm/drm-next v5.17-rc1 next-20220125]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Matthew-Auld/Initial-support-for-small-BAR-recovery/20220126-232640
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: i386-randconfig-a002-20220124
(https://download.01.org/0day-ci/archive/20220127/202201270314.twkiundm-...@intel.com/config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
#
https://github.com/0day-ci/linux/commit/33b0a9f1f9810bd16cef89ce1e5787751583661e
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review
Matthew-Auld/Initial-support-for-small-BAR-recovery/20220126-232640
git checkout 33b0a9f1f9810bd16cef89ce1e5787751583661e
# save the config file to linux build tree
mkdir build_dir
make W=1 O=build_dir ARCH=i386 SHELL=/bin/bash drivers/gpu/drm/i915/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All errors (new ones prefixed by >>):
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c: In function
'i915_gem_do_execbuffer':
>> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:3426:6: error: void value not
>> ignored as it ought to be
3426 | err = eb_capture_stage();
| ^
vim +3426 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
3381
3382 if (args->flags & I915_EXEC_FENCE_OUT) {
3383 out_fence_fd = get_unused_fd_flags(O_CLOEXEC);
3384 if (out_fence_fd < 0) {
3385 err = out_fence_fd;
3386 goto err_in_fence;
3387 }
3388 }
3389
3390 err = eb_create();
3391 if (err)
3392 goto err_out_fence;
3393
3394 GEM_BUG_ON(!eb.lut_size);
3395
3396 err = eb_select_context();
3397 if (unlikely(err))
3398 goto err_destroy;
3399
3400 err = eb_select_engine();
3401 if (unlikely(err))
3402 goto err_context;
3403
3404 err = eb_lookup_vmas();
3405 if (err) {
3406 eb_release_vmas(, true);
3407 goto err_engine;
3408 }
3409
3410 i915_gem_ww_ctx_init(, true);
3411
3412 err = eb_relocate_parse();
3413 if (err) {
3414 /*
3415 * If the user expects the execobject.offset and
3416 * reloc.presumed_offset to be an exact match,
3417 * as for using NO_RELOC, then we cannot update
3418 * the execobject.offset until we have completed
3419 * relocation.
3420 */
3421 args->flags &= ~__EXEC_HAS_RELOC;
3422 goto err_vma;
3423 }
3424
3425 ww_acquire_done();
> 3426 err = eb_capture_stage();
3427 if (err)
3428 goto err_vma;
3429
3430 out_fence = eb_requests_create(, in_fence, out_fence_fd);
3431 if (IS_ERR(out_fence)) {
3432 err = PTR_ERR(out_fence);
3433 out_fence = NULL;
3434 if (eb.requests[0])
3435 goto err_request;
3436 else
3437 goto err_vma;
3438 }
3439
3440 err = eb_submit();
3441
3442 err_request:
3443 eb_requests_get();
3444 err = eb_requests_add(, err);
3445
3446 if (eb.fences)
3447 signal_fence_array(, eb.composite_fence ?
3448 eb.composite_fence :
3449 [0]->fence);
3450
3451 if (out_fence) {
3452 if (err == 0) {
3453 fd_install(out_fence_fd, out_fence->file);
3454 args->rsvd2 &= GENMASK_ULL(31, 0); /* keep
in-fence */
3455 args->rsvd2 |= (u64)out_fence_fd << 32;
3456 out_fence_fd = -1;
3457 } else {
3458 fput(out_fence->file);
3459 }
3460 }
3461
3462 if (unlikely(eb.gem_context->syncobj)) {
3463 drm_syncobj_replace_fence(eb.gem_context->syncobj,
3464eb.composite_fence ?
3465
[Intel-gfx] [PATCH v2] drm/i915/display/vrr: Reset VRR capable property on a long hpd
With some VRR panels, user can turn VRR ON/OFF on the fly from the panel
settings.
When VRR is turned OFF ,sends a long HPD to the driver clearing the Ignore MSA
bit
in the DPCD. Currently the driver parses that onevery HPD but fails to reset
the corresponding VRR Capable Connector property.
Hence the userspace still sees this as VRR Capable panel which is incorrect.
Fix this by explicitly resetting the connector property.
v2: Reset vrr capable if status == connector_disconnected
v3: Use i915 and use bool vrr_capable (Jani Nikula)
Cc: Jani Nikula
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_dp.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 4d4579a301f6..687cb37bb22a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4446,6 +4446,12 @@ intel_dp_detect(struct drm_connector *connector,
memset(_dp->compliance, 0, sizeof(intel_dp->compliance));
memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
+ /* Reset VRR Capable property */
+ drm_dbg_kms(_priv->drm, "[CONNECTOR:%d:%s] VRR capable:
FALSE\n",
+ connector->base.id, connector->name);
+ drm_connector_set_vrr_capable_property(connector,
+ false);
+
if (intel_dp->is_mst) {
drm_dbg_kms(_priv->drm,
"MST device may have disappeared %d vs
%d\n",
@@ -4560,15 +4566,17 @@ static int intel_dp_get_modes(struct drm_connector
*connector)
{
struct intel_connector *intel_connector = to_intel_connector(connector);
struct edid *edid;
+ struct drm_i915_private *i915 = to_i915(connector->dev);
int num_modes = 0;
edid = intel_connector->detect_edid;
if (edid) {
- num_modes = intel_connector_update_modes(connector, edid);
+ bool vrr_capable = intel_vrr_is_capable(connector);
- if (intel_vrr_is_capable(connector))
- drm_connector_set_vrr_capable_property(connector,
- true);
+ num_modes = intel_connector_update_modes(connector, edid);
+ drm_dbg_kms(>drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
+ connector->base.id, connector->name,
yesno(vrr_capable));
+ drm_connector_set_vrr_capable_property(connector, vrr_capable);
}
/* Also add fixed mode, which may or may not be present in EDID */
--
2.19.1
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/adlp: Fix TypeC PHY-ready status readout
On Wed, Jan 26, 2022 at 06:47:33PM +, Patchwork wrote: > == Series Details == > > Series: drm/i915/adlp: Fix TypeC PHY-ready status readout > URL : https://patchwork.freedesktop.org/series/99359/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_11145 -> Patchwork_22111 > > > Summary > --- > > **FAILURE** > > Serious unknown changes coming with Patchwork_22111 absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_22111, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > External URL: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/index.html > > Participating hosts (46 -> 43) > -- > > Additional (1): fi-pnv-d510 > Missing(4): fi-ctg-p8600 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u > > Possible new issues > --- > > Here are the unknown changes that may have been introduced in > Patchwork_22111: > > ### IGT changes ### > > Possible regressions > > * igt@i915_selftest@live@hugepages: > - fi-rkl-guc: [PASS][1] -> [DMESG-WARN][2] >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/fi-rkl-guc/igt@i915_selftest@l...@hugepages.html >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-rkl-guc/igt@i915_selftest@l...@hugepages.html Looks like some GuC related issue, the patch shouldn't have an effect on RKL, which doesn't support TypeC outputs. <3> [219.132608] i915 :00:02.0: [drm] *ERROR* CT: Failed to process request 6000 (-EOPNOTSUPP) <3> [219.132641] DMAR: [DMA Write NO_PASID] Request device [00:02.0] fault addr 0xfcffc000 [fault reason 0x07] Next page table ptr is invalid <3> [219.132665] i915 :00:02.0: [drm] *ERROR* CT: Failed to process CT message (-EOPNOTSUPP) 02 00 00 00 00 60 00 90 1b 10 00 00 > > > Warnings > > * igt@i915_selftest@live@hangcheck: > - bat-dg1-6: [DMESG-FAIL][3] ([i915#4494]) -> [DMESG-FAIL][4] >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html > > > Known issues > > > Here are the changes found in Patchwork_22111 that come from known issues: > > ### CI changes ### > > Possible fixes > > * boot: > - fi-ilk-650: [FAIL][5] -> [PASS][6] >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/fi-ilk-650/boot.html >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-ilk-650/boot.html > > > > ### IGT changes ### > > Issues hit > > * igt@amdgpu/amd_cs_nop@nop-compute0: > - fi-ilk-650: NOTRUN -> [SKIP][7] ([fdo#109271]) +39 similar > issues >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-ilk-650/igt@amdgpu/amd_cs_...@nop-compute0.html > > * igt@gem_exec_suspend@basic-s3@smem: > - fi-bdw-5557u: [PASS][8] -> [INCOMPLETE][9] ([i915#146]) >[8]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html >[9]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html > > * igt@gem_huc_copy@huc-copy: > - fi-skl-6600u: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#2190]) >[10]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html > > * igt@gem_lmem_swapping@verify-random: > - fi-skl-6600u: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4613]) > +3 similar issues >[11]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html > > * igt@i915_selftest@live@execlists: > - fi-bsw-n3050: [PASS][12] -> [INCOMPLETE][13] ([i915#2940]) >[12]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html >[13]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html > > * igt@i915_selftest@live@hangcheck: > - fi-snb-2600:[PASS][14] -> [INCOMPLETE][15] ([i915#3921]) >[14]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html >[15]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html > > * igt@kms_chamelium@dp-hpd-fast: > - fi-ilk-650: NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827]) > +8 similar issues >[16]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-ilk-650/igt@kms_chamel...@dp-hpd-fast.html > > *
Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/rpl-s: Add stepping info (rev4)
On Wed, Jan 26, 2022 at 02:30:38AM +, Patchwork wrote: > == Series Details == > > Series: drm/i915/rpl-s: Add stepping info (rev4) > URL : https://patchwork.freedesktop.org/series/99162/ > State : success > > == Summary == > > CI Bug Log - changes from CI_DRM_11135_full -> Patchwork_22105_full > > > Summary > --- > > **SUCCESS** > > No regressions found. Applied to drm-intel-gt-next. Thanks for the patch. Matt > > > > Participating hosts (10 -> 10) > -- > > No changes in participating hosts > > Known issues > > > Here are the changes found in Patchwork_22105_full that come from known > issues: > > ### IGT changes ### > > Issues hit > > * igt@gem_eio@kms: > - shard-tglb: [PASS][1] -> [FAIL][2] ([i915#232]) >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11135/shard-tglb7/igt@gem_...@kms.html >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22105/shard-tglb3/igt@gem_...@kms.html > > * igt@gem_exec_balancer@parallel: > - shard-iclb: [PASS][3] -> [SKIP][4] ([i915#4525]) >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11135/shard-iclb2/igt@gem_exec_balan...@parallel.html >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22105/shard-iclb3/igt@gem_exec_balan...@parallel.html > > * igt@gem_exec_fair@basic-none@vcs0: > - shard-kbl: [PASS][5] -> [FAIL][6] ([i915#2842]) +3 similar > issues >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11135/shard-kbl1/igt@gem_exec_fair@basic-n...@vcs0.html >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22105/shard-kbl4/igt@gem_exec_fair@basic-n...@vcs0.html > > * igt@gem_exec_fair@basic-pace-solo@rcs0: > - shard-tglb: [PASS][7] -> [FAIL][8] ([i915#2842]) >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11135/shard-tglb2/igt@gem_exec_fair@basic-pace-s...@rcs0.html >[8]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22105/shard-tglb8/igt@gem_exec_fair@basic-pace-s...@rcs0.html > > * igt@gem_huc_copy@huc-copy: > - shard-tglb: [PASS][9] -> [SKIP][10] ([i915#2190]) >[9]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11135/shard-tglb3/igt@gem_huc_c...@huc-copy.html >[10]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22105/shard-tglb6/igt@gem_huc_c...@huc-copy.html > > * igt@gem_lmem_swapping@parallel-multi: > - shard-apl: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4613]) > +2 similar issues >[11]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22105/shard-apl7/igt@gem_lmem_swapp...@parallel-multi.html > - shard-skl: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4613]) >[12]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22105/shard-skl10/igt@gem_lmem_swapp...@parallel-multi.html > > * igt@gem_lmem_swapping@random: > - shard-kbl: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4613]) > +1 similar issue >[13]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22105/shard-kbl1/igt@gem_lmem_swapp...@random.html > > * igt@gem_spin_batch@spin-each: > - shard-apl: [PASS][14] -> [FAIL][15] ([i915#2898]) >[14]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11135/shard-apl2/igt@gem_spin_ba...@spin-each.html >[15]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22105/shard-apl2/igt@gem_spin_ba...@spin-each.html > > * igt@gem_userptr_blits@coherency-sync: > - shard-tglb: NOTRUN -> [SKIP][16] ([fdo#110542]) >[16]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22105/shard-tglb7/igt@gem_userptr_bl...@coherency-sync.html > > * igt@gem_userptr_blits@readonly-unsync: > - shard-tglb: NOTRUN -> [SKIP][17] ([i915#3297]) >[17]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22105/shard-tglb7/igt@gem_userptr_bl...@readonly-unsync.html > > * igt@gem_workarounds@suspend-resume: > - shard-kbl: [PASS][18] -> [DMESG-WARN][19] ([i915#180]) >[18]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11135/shard-kbl3/igt@gem_workarou...@suspend-resume.html >[19]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22105/shard-kbl7/igt@gem_workarou...@suspend-resume.html > > * igt@gem_workarounds@suspend-resume-context: > - shard-apl: [PASS][20] -> [DMESG-WARN][21] ([i915#180]) +3 > similar issues >[20]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11135/shard-apl2/igt@gem_workarou...@suspend-resume-context.html >[21]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22105/shard-apl8/igt@gem_workarou...@suspend-resume-context.html > > * igt@i915_pm_dc@dc6-psr: > - shard-skl: NOTRUN -> [FAIL][22] ([i915#454]) >[22]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22105/shard-skl10/igt@i915_pm...@dc6-psr.html > > *
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Remove all frontbuffer tracking calls from the gem code
== Series Details == Series: drm/i915: Remove all frontbuffer tracking calls from the gem code URL : https://patchwork.freedesktop.org/series/99365/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.BAT: failure for Add GuC Error Capture Support (rev5)
== Series Details == Series: Add GuC Error Capture Support (rev5) URL : https://patchwork.freedesktop.org/series/97187/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11145 -> Patchwork_22112 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22112 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22112, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22112/index.html Participating hosts (46 -> 43) -- Additional (1): fi-icl-u2 Missing(4): fi-ctg-p8600 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22112: ### IGT changes ### Possible regressions * igt@i915_selftest@live@gt_engines: - bat-dg1-6: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/bat-dg1-6/igt@i915_selftest@live@gt_engines.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22112/bat-dg1-6/igt@i915_selftest@live@gt_engines.html - fi-rkl-guc: [PASS][3] -> [DMESG-FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22112/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html - bat-dg1-5: [PASS][5] -> [DMESG-FAIL][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/bat-dg1-5/igt@i915_selftest@live@gt_engines.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22112/bat-dg1-5/igt@i915_selftest@live@gt_engines.html * igt@i915_selftest@live@workarounds: - bat-dg1-5: [PASS][7] -> [DMESG-WARN][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/bat-dg1-5/igt@i915_selftest@l...@workarounds.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22112/bat-dg1-5/igt@i915_selftest@l...@workarounds.html - bat-dg1-6: [PASS][9] -> [DMESG-WARN][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/bat-dg1-6/igt@i915_selftest@l...@workarounds.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22112/bat-dg1-6/igt@i915_selftest@l...@workarounds.html - fi-rkl-guc: [PASS][11] -> [DMESG-WARN][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/fi-rkl-guc/igt@i915_selftest@l...@workarounds.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22112/fi-rkl-guc/igt@i915_selftest@l...@workarounds.html Known issues Here are the changes found in Patchwork_22112 that come from known issues: ### CI changes ### Possible fixes * boot: - fi-ilk-650: [FAIL][13] -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/fi-ilk-650/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22112/fi-ilk-650/boot.html ### IGT changes ### Issues hit * igt@amdgpu/amd_cs_nop@fork-gfx0: - fi-icl-u2: NOTRUN -> [SKIP][15] ([fdo#109315]) +17 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22112/fi-icl-u2/igt@amdgpu/amd_cs_...@fork-gfx0.html * igt@amdgpu/amd_cs_nop@nop-compute0: - fi-ilk-650: NOTRUN -> [SKIP][16] ([fdo#109271]) +39 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22112/fi-ilk-650/igt@amdgpu/amd_cs_...@nop-compute0.html * igt@gem_huc_copy@huc-copy: - fi-skl-6600u: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#2190]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22112/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html - fi-icl-u2: NOTRUN -> [SKIP][18] ([i915#2190]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22112/fi-icl-u2/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@parallel-random-engines: - fi-icl-u2: NOTRUN -> [SKIP][19] ([i915#4613]) +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22112/fi-icl-u2/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_lmem_swapping@verify-random: - fi-skl-6600u: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#4613]) +3 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22112/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html * igt@i915_selftest@live: - fi-skl-6600u: NOTRUN -> [FAIL][21] ([i915#4547]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22112/fi-skl-6600u/igt@i915_selft...@live.html * igt@i915_selftest@live@hangcheck: - fi-hsw-4770:[PASS][22] -> [INCOMPLETE][23] ([i915#3303]) [22]:
Re: [Intel-gfx] [PATCH 3/4] drm/i915/execlists: Fix execlists request cancellation corner case
On 1/24/2022 07:01, Matthew Brost wrote:
More than 1 request can be submitted to a single ELSP at a time if
multiple requests are ready run to on the same context. When a request
is canceled it is marked bad, an idle pulse is triggered to the engine
(high priority kernel request), the execlists scheduler sees that
running request is bad and sets preemption timeout to minimum value (1
ms). This fails to work if multiple requests are combined on the ELSP as
only the most recent request is stored in the execlists schedule (the
request stored in the ELSP isn't marked bad, thus preemption timeout
isn't set to the minimum value). If the preempt timeout is configured to
zero, the engine is permanently hung. This is shown by an upcoming
selftest.
To work around this, mark the idle pulse with a flag to force a preempt
with the minimum value.
Fixes: 38b237eab2bc7 ("drm/i915: Individual request cancellation")
Signed-off-by: Matthew Brost
---
.../gpu/drm/i915/gt/intel_engine_heartbeat.c | 23 +++
.../gpu/drm/i915/gt/intel_engine_heartbeat.h | 1 +
.../drm/i915/gt/intel_execlists_submission.c | 18 ++-
drivers/gpu/drm/i915/i915_request.h | 6 +
4 files changed, 38 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
index a3698f611f457..efd1c719b4072 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
@@ -243,7 +243,8 @@ void intel_engine_init_heartbeat(struct intel_engine_cs
*engine)
INIT_DELAYED_WORK(>heartbeat.work, heartbeat);
}
-static int __intel_engine_pulse(struct intel_engine_cs *engine)
+static int __intel_engine_pulse(struct intel_engine_cs *engine,
+ bool force_preempt)
{
struct i915_sched_attr attr = { .priority = I915_PRIORITY_BARRIER };
struct intel_context *ce = engine->kernel_context;
@@ -258,6 +259,8 @@ static int __intel_engine_pulse(struct intel_engine_cs
*engine)
return PTR_ERR(rq);
__set_bit(I915_FENCE_FLAG_SENTINEL, >fence.flags);
+ if (force_preempt)
+ __set_bit(I915_FENCE_FLAG_FORCE_PREEMPT, >fence.flags);
heartbeat_commit(rq, );
GEM_BUG_ON(rq->sched.attr.priority < I915_PRIORITY_BARRIER);
@@ -299,7 +302,7 @@ int intel_engine_set_heartbeat(struct intel_engine_cs
*engine,
/* recheck current execution */
if (intel_engine_has_preemption(engine)) {
- err = __intel_engine_pulse(engine);
+ err = __intel_engine_pulse(engine, false);
if (err)
set_heartbeat(engine, saved);
}
@@ -312,7 +315,8 @@ int intel_engine_set_heartbeat(struct intel_engine_cs
*engine,
return err;
}
-int intel_engine_pulse(struct intel_engine_cs *engine)
+static int _intel_engine_pulse(struct intel_engine_cs *engine,
+ bool force_preempt)
{
struct intel_context *ce = engine->kernel_context;
int err;
@@ -325,7 +329,7 @@ int intel_engine_pulse(struct intel_engine_cs *engine)
err = -EINTR;
if (!mutex_lock_interruptible(>timeline->mutex)) {
- err = __intel_engine_pulse(engine);
+ err = __intel_engine_pulse(engine, force_preempt);
mutex_unlock(>timeline->mutex);
}
@@ -334,6 +338,17 @@ int intel_engine_pulse(struct intel_engine_cs *engine)
return err;
}
+int intel_engine_pulse(struct intel_engine_cs *engine)
+{
+ return _intel_engine_pulse(engine, false);
+}
+
+
+int intel_engine_pulse_force_preempt(struct intel_engine_cs *engine)
+{
+ return _intel_engine_pulse(engine, true);
+}
+
int intel_engine_flush_barriers(struct intel_engine_cs *engine)
{
struct i915_sched_attr attr = { .priority = I915_PRIORITY_MIN };
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
index 5da6d809a87a2..d9c8386754cb3 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
@@ -21,6 +21,7 @@ void intel_gt_park_heartbeats(struct intel_gt *gt);
void intel_gt_unpark_heartbeats(struct intel_gt *gt);
int intel_engine_pulse(struct intel_engine_cs *engine);
+int intel_engine_pulse_force_preempt(struct intel_engine_cs *engine);
int intel_engine_flush_barriers(struct intel_engine_cs *engine);
#endif /* INTEL_ENGINE_HEARTBEAT_H */
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 960a9aaf4f3a3..f0c2024058731 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1222,26 +1222,29 @@ static void record_preemption(struct
intel_engine_execlists
Re: [Intel-gfx] [PATCH 2/4] drm/i915/guc: Cancel requests immediately
On 1/24/2022 07:01, Matthew Brost wrote:
Change the preemption timeout to the smallest possible value (1 us) when
disabling scheduling to cancel a request and restore it after
cancellation. This not only cancels the request as fast as possible, it
fixes a bug where the preemption timeout is 0 which results in the
schedule disable hanging forever.
Shouldn't there be an 'if' in the above statement? The pre-emption
timeout is not normally zero.
Reported-by: Jani Saarinen
Fixes: 62eaf0ae217d4 ("drm/i915/guc: Support request cancellation")
Link: https://gitlab.freedesktop.org/drm/intel/-/issues/4960
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_context_types.h | 5 ++
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 46 +++
2 files changed, 31 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 30cd81ad8911a..730998823dbea 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -198,6 +198,11 @@ struct intel_context {
* each priority bucket
*/
u32 prio_count[GUC_CLIENT_PRIORITY_NUM];
+ /**
+* @preemption_timeout: preemption timeout of the context, used
+* to restore this value after request cancellation
+*/
+ u32 preemption_timeout;
} guc_state;
struct {
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 3918f1be114fa..966947c450253 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2147,7 +2147,8 @@ static inline u32 get_children_join_value(struct
intel_context *ce,
return __get_parent_scratch(ce)->join[child_index].semaphore;
}
-static void guc_context_policy_init(struct intel_engine_cs *engine,
+static void guc_context_policy_init(struct intel_context *ce,
+ struct intel_engine_cs *engine,
struct guc_lrc_desc *desc)
Shouldn't engine be before ce? The more general structure usually goes
first.
John.
{
desc->policy_flags = 0;
@@ -2157,7 +2158,8 @@ static void guc_context_policy_init(struct
intel_engine_cs *engine,
/* NB: For both of these, zero means disabled. */
desc->execution_quantum = engine->props.timeslice_duration_ms * 1000;
- desc->preemption_timeout = engine->props.preempt_timeout_ms * 1000;
+ ce->guc_state.preemption_timeout = engine->props.preempt_timeout_ms *
1000;
+ desc->preemption_timeout = ce->guc_state.preemption_timeout;
}
static int guc_lrc_desc_pin(struct intel_context *ce, bool loop)
@@ -2193,7 +2195,7 @@ static int guc_lrc_desc_pin(struct intel_context *ce,
bool loop)
desc->hw_context_desc = ce->lrc.lrca;
desc->priority = ce->guc_state.prio;
desc->context_flags = CONTEXT_REGISTRATION_FLAG_KMD;
- guc_context_policy_init(engine, desc);
+ guc_context_policy_init(ce, engine, desc);
/*
* If context is a parent, we need to register a process descriptor
@@ -2226,7 +2228,7 @@ static int guc_lrc_desc_pin(struct intel_context *ce,
bool loop)
desc->hw_context_desc = child->lrc.lrca;
desc->priority = ce->guc_state.prio;
desc->context_flags = CONTEXT_REGISTRATION_FLAG_KMD;
- guc_context_policy_init(engine, desc);
+ guc_context_policy_init(child, engine, desc);
}
clear_children_join_go_memory(ce);
@@ -2409,6 +2411,19 @@ static u16 prep_context_pending_disable(struct
intel_context *ce)
return ce->guc_id.id;
}
+static void __guc_context_set_preemption_timeout(struct intel_guc *guc,
+u16 guc_id,
+u32 preemption_timeout)
+{
+ u32 action[] = {
+ INTEL_GUC_ACTION_SET_CONTEXT_PREEMPTION_TIMEOUT,
+ guc_id,
+ preemption_timeout
+ };
+
+ intel_guc_send_busy_loop(guc, action, ARRAY_SIZE(action), 0, true);
+}
+
static struct i915_sw_fence *guc_context_block(struct intel_context *ce)
{
struct intel_guc *guc = ce_to_guc(ce);
@@ -2442,8 +2457,10 @@ static struct i915_sw_fence *guc_context_block(struct
intel_context *ce)
spin_unlock_irqrestore(>guc_state.lock, flags);
- with_intel_runtime_pm(runtime_pm, wakeref)
+ with_intel_runtime_pm(runtime_pm, wakeref) {
+ __guc_context_set_preemption_timeout(guc, guc_id, 1);
__guc_context_sched_disable(guc, ce, guc_id);
+ }
return >guc_state.blocked;
}
@@ -2492,8 +2509,10 @@ static void guc_context_unblock(struct intel_context *ce)
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add GuC Error Capture Support (rev5)
== Series Details == Series: Add GuC Error Capture Support (rev5) URL : https://patchwork.freedesktop.org/series/97187/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add GuC Error Capture Support (rev5)
== Series Details ==
Series: Add GuC Error Capture Support (rev5)
URL : https://patchwork.freedesktop.org/series/97187/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
233b325e5a87 drm/i915/guc: Update GuC ADS size for error capture lists
-:32: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#32:
new file mode 100644
-:307: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'regslist' - possible
side-effects?
#307: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:60:
+#define MAKE_REGLIST(regslist, regsowner, regstype, class) \
+ { \
+ .list = regslist, \
+ .num_regs = ARRAY_SIZE(regslist), \
+ .owner = TO_GCAP_DEF_OWNER(regsowner), \
+ .type = TO_GCAP_DEF_TYPE(regstype), \
+ .engine = class, \
+ }
-:356: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional
statements (16, 16)
#356: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:109:
+ if (reglists[i].owner == owner && reglists[i].type == type &&
[...]
+ return [i];
total: 0 errors, 2 warnings, 1 checks, 681 lines checked
34501e7d2c33 drm/i915/guc: Add XE_LP registers for GuC error state capture.
-:37: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in
parentheses
#37: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:22:
+#define COMMON_GEN12BASE_GLOBAL() \
+ {GEN12_FAULT_TLB_DATA0,0, 0, "GEN12_FAULT_TLB_DATA0"}, \
+ {GEN12_FAULT_TLB_DATA1,0, 0, "GEN12_FAULT_TLB_DATA1"}, \
+ {FORCEWAKE_MT, 0, 0, "FORCEWAKE_MT"}, \
+ {GEN12_AUX_ERR_DBG,0, 0, "GEN12_AUX_ERR_DBG"}, \
+ {GEN12_GAM_DONE, 0, 0, "GEN12_GAM_DONE"}, \
+ {GEN12_RING_FAULT_REG, 0, 0, "GEN12_RING_FAULT_REG"}
-:45: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in
parentheses
#45: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:30:
+#define COMMON_GEN12BASE_ENGINE_INSTANCE() \
+ {RING_PSMI_CTL(0), 0, 0, "RING_PSMI_CTL"}, \
+ {RING_ESR(0), 0, 0, "RING_ESR"}, \
+ {RING_DMA_FADD(0), 0, 0, "RING_DMA_FADD_LOW32"}, \
+ {RING_DMA_FADD_UDW(0), 0, 0, "RING_DMA_FADD_UP32"}, \
+ {RING_IPEIR(0),0, 0, "RING_IPEIR"}, \
+ {RING_IPEHR(0),0, 0, "RING_IPEHR"}, \
+ {RING_INSTPS(0), 0, 0, "RING_INSTPS"}, \
+ {RING_BBADDR(0), 0, 0, "RING_BBADDR_LOW32"}, \
+ {RING_BBADDR_UDW(0), 0, 0, "RING_BBADDR_UP32"}, \
+ {RING_BBSTATE(0), 0, 0, "RING_BBSTATE"}, \
+ {CCID(0), 0, 0, "CCID"}, \
+ {RING_ACTHD(0),0, 0, "RING_ACTHD_LOW32"}, \
+ {RING_ACTHD_UDW(0),0, 0, "RING_ACTHD_UP32"}, \
+ {RING_INSTPM(0), 0, 0, "RING_INSTPM"}, \
+ {RING_NOPID(0),0, 0, "RING_NOPID"}, \
+ {RING_START(0),0, 0, "RING_START"}, \
+ {RING_HEAD(0), 0, 0, "RING_HEAD"}, \
+ {RING_TAIL(0), 0, 0, "RING_TAIL"}, \
+ {RING_CTL(0), 0, 0, "RING_CTL"}, \
+ {RING_MI_MODE(0), 0, 0, "RING_MI_MODE"}, \
+ {RING_CONTEXT_CONTROL(0), 0, 0, "RING_CONTEXT_CONTROL"}, \
+ {RING_INSTDONE(0), 0, 0, "RING_INSTDONE"}, \
+ {RING_HWS_PGA(0), 0, 0, "RING_HWS_PGA"}, \
+ {RING_MODE_GEN7(0),0, 0, "RING_MODE_GEN7"}, \
+ {GEN8_RING_PDP_LDW(0, 0), 0, 0, "GEN8_RING_PDP0_LDW"}, \
+ {GEN8_RING_PDP_UDW(0, 0), 0, 0, "GEN8_RING_PDP0_UDW"}, \
+ {GEN8_RING_PDP_LDW(0, 1), 0, 0, "GEN8_RING_PDP1_LDW"}, \
+ {GEN8_RING_PDP_UDW(0, 1), 0, 0, "GEN8_RING_PDP1_UDW"}, \
+ {GEN8_RING_PDP_LDW(0, 2), 0, 0, "GEN8_RING_PDP2_LDW"}, \
+ {GEN8_RING_PDP_UDW(0, 2), 0, 0, "GEN8_RING_PDP2_UDW"}, \
+ {GEN8_RING_PDP_LDW(0, 3), 0, 0, "GEN8_RING_PDP3_LDW"}, \
+ {GEN8_RING_PDP_UDW(0, 3), 0, 0, "GEN8_RING_PDP3_UDW"}
-:82: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in
parentheses
#82: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:67:
+#define COMMON_GEN12BASE_RENDER() \
+ {GEN7_SC_INSTDONE, 0, 0, "GEN7_SC_INSTDONE"}, \
+ {GEN12_SC_INSTDONE_EXTRA, 0, 0, "GEN12_SC_INSTDONE_EXTRA"}, \
+ {GEN12_SC_INSTDONE_EXTRA2, 0, 0, "GEN12_SC_INSTDONE_EXTRA2"}
-:87: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in
parentheses
#87: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:72:
+#define COMMON_GEN12BASE_VEC() \
+ {GEN12_SFC_DONE(0),0, 0, "GEN12_SFC_DONE0"}, \
+ {GEN12_SFC_DONE(1),0, 0, "GEN12_SFC_DONE1"}, \
+ {GEN12_SFC_DONE(2),0, 0, "GEN12_SFC_DONE2"}, \
+
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/adlp: Fix TypeC PHY-ready status readout
== Series Details == Series: drm/i915/adlp: Fix TypeC PHY-ready status readout URL : https://patchwork.freedesktop.org/series/99359/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11145 -> Patchwork_22111 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22111 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22111, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/index.html Participating hosts (46 -> 43) -- Additional (1): fi-pnv-d510 Missing(4): fi-ctg-p8600 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22111: ### IGT changes ### Possible regressions * igt@i915_selftest@live@hugepages: - fi-rkl-guc: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/fi-rkl-guc/igt@i915_selftest@l...@hugepages.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-rkl-guc/igt@i915_selftest@l...@hugepages.html Warnings * igt@i915_selftest@live@hangcheck: - bat-dg1-6: [DMESG-FAIL][3] ([i915#4494]) -> [DMESG-FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html Known issues Here are the changes found in Patchwork_22111 that come from known issues: ### CI changes ### Possible fixes * boot: - fi-ilk-650: [FAIL][5] -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/fi-ilk-650/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-ilk-650/boot.html ### IGT changes ### Issues hit * igt@amdgpu/amd_cs_nop@nop-compute0: - fi-ilk-650: NOTRUN -> [SKIP][7] ([fdo#109271]) +39 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-ilk-650/igt@amdgpu/amd_cs_...@nop-compute0.html * igt@gem_exec_suspend@basic-s3@smem: - fi-bdw-5557u: [PASS][8] -> [INCOMPLETE][9] ([i915#146]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html * igt@gem_huc_copy@huc-copy: - fi-skl-6600u: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#2190]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@verify-random: - fi-skl-6600u: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4613]) +3 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html * igt@i915_selftest@live@execlists: - fi-bsw-n3050: [PASS][12] -> [INCOMPLETE][13] ([i915#2940]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html * igt@i915_selftest@live@hangcheck: - fi-snb-2600:[PASS][14] -> [INCOMPLETE][15] ([i915#3921]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html * igt@kms_chamelium@dp-hpd-fast: - fi-ilk-650: NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827]) +8 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-ilk-650/igt@kms_chamel...@dp-hpd-fast.html * igt@kms_chamelium@vga-edid-read: - fi-skl-6600u: NOTRUN -> [SKIP][17] ([fdo#109271] / [fdo#111827]) +8 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-skl-6600u/igt@kms_chamel...@vga-edid-read.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-skl-6600u: NOTRUN -> [SKIP][18] ([fdo#109271]) +2 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-skl-6600u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-skl-6600u: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#533]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-skl-6600u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html *
Re: [Intel-gfx] [PATCH 02/20] drm: implement top-down allocation method
On 26/01/2022 15:21, Matthew Auld wrote:
From: Arunpravin
Implemented a function which walk through the order list,
compares the offset and returns the maximum offset block,
this method is unpredictable in obtaining the high range
address blocks which depends on allocation and deallocation.
for instance, if driver requests address at a low specific
range, allocator traverses from the root block and splits
the larger blocks until it reaches the specific block and
in the process of splitting, lower orders in the freelist
are occupied with low range address blocks and for the
subsequent TOPDOWN memory request we may return the low
range blocks.To overcome this issue, we may go with the
below approach.
The other approach, sorting each order list entries in
ascending order and compares the last entry of each
order list in the freelist and return the max block.
This creates sorting overhead on every drm_buddy_free()
request and split up of larger blocks for a single page
request.
ooc, why did you choose to implement this as an alloc flag?
Seems to me like it would be a good candidate for a new memory region.
That way allocation algorithms wouldn't need exta logic and ttm can
already handle migrations.
v2:
- Fix alignment issues(Matthew Auld)
- Remove unnecessary list_empty check(Matthew Auld)
- merged the below patch to see the feature in action
- add top-down alloc support to i915 driver
Signed-off-by: Arunpravin
---
drivers/gpu/drm/drm_buddy.c | 36 ---
drivers/gpu/drm/i915/i915_ttm_buddy_manager.c | 3 ++
include/drm/drm_buddy.h | 1 +
3 files changed, 35 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/drm_buddy.c b/drivers/gpu/drm/drm_buddy.c
index 954e31962c74..6aa5c1ce25bf 100644
--- a/drivers/gpu/drm/drm_buddy.c
+++ b/drivers/gpu/drm/drm_buddy.c
@@ -371,6 +371,26 @@ alloc_range_bias(struct drm_buddy *mm,
return ERR_PTR(err);
}
+static struct drm_buddy_block *
+get_maxblock(struct list_head *head)
+{
+ struct drm_buddy_block *max_block = NULL, *node;
+
+ max_block = list_first_entry_or_null(head,
+struct drm_buddy_block,
+link);
+ if (!max_block)
+ return NULL;
+
+ list_for_each_entry(node, head, link) {
+ if (drm_buddy_block_offset(node) >
+ drm_buddy_block_offset(max_block))
+ max_block = node;
+ }
+
+ return max_block;
+}
+
static struct drm_buddy_block *
alloc_from_freelist(struct drm_buddy *mm,
unsigned int order,
@@ -381,11 +401,17 @@ alloc_from_freelist(struct drm_buddy *mm,
int err;
for (i = order; i <= mm->max_order; ++i) {
- block = list_first_entry_or_null(>free_list[i],
-struct drm_buddy_block,
-link);
- if (block)
- break;
+ if (flags & DRM_BUDDY_TOPDOWN_ALLOCATION) {
+ block = get_maxblock(>free_list[i]);
+ if (block)
+ break;
+ } else {
+ block = list_first_entry_or_null(>free_list[i],
+struct drm_buddy_block,
+link);
+ if (block)
+ break;
+ }
}
if (!block)
diff --git a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
b/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
index 1411f4cf1f21..3662434b64bb 100644
--- a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
+++ b/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
@@ -53,6 +53,9 @@ static int i915_ttm_buddy_man_alloc(struct
ttm_resource_manager *man,
INIT_LIST_HEAD(_res->blocks);
bman_res->mm = mm;
+ if (place->flags & TTM_PL_FLAG_TOPDOWN)
+ bman_res->flags |= DRM_BUDDY_TOPDOWN_ALLOCATION;
+
if (place->fpfn || lpfn != man->size)
bman_res->flags |= DRM_BUDDY_RANGE_ALLOCATION;
diff --git a/include/drm/drm_buddy.h b/include/drm/drm_buddy.h
index 865664b90a8a..424fc443115e 100644
--- a/include/drm/drm_buddy.h
+++ b/include/drm/drm_buddy.h
@@ -28,6 +28,7 @@
})
#define DRM_BUDDY_RANGE_ALLOCATION (1 << 0)
+#define DRM_BUDDY_TOPDOWN_ALLOCATION (1 << 1)
struct drm_buddy_block {
#define DRM_BUDDY_HEADER_OFFSET GENMASK_ULL(63, 12)
Re: [Intel-gfx] [CI] drm/i915/rpl-s: Add stepping info
On Tue, 25 Jan 2022, Anusha Srivatsa wrote:
> Add stepping-substepping info in
> accordance to BSpec changes.
> Though it looks weird, the revision ID
> for the newer stepping is indeed backwards
> and is in accordance to the spec.
>
> v2: Rearrange the platforms in logical order (Matt)
>
> Bspec: 53655
> Cc: Matt Roper
> Signed-off-by: Anusha Srivatsa
> Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/intel_step.c | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_step.c
> b/drivers/gpu/drm/i915/intel_step.c
> index a4b16b9e2e55..9012e4b76a49 100644
> --- a/drivers/gpu/drm/i915/intel_step.c
> +++ b/drivers/gpu/drm/i915/intel_step.c
> @@ -122,6 +122,11 @@ static const struct intel_step_info
> dg2_g11_revid_step_tbl[] = {
> [0x5] = { COMMON_GT_MEDIA_STEP(B1), .display_step = STEP_C0 },
> };
>
> +static const struct intel_step_info adls_rpls_revids[] = {
> + [0x4] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_D0 },
> + [0xC] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_C0 },
> +};
> +
> void intel_step_init(struct drm_i915_private *i915)
> {
> const struct intel_step_info *revids = NULL;
> @@ -129,6 +134,7 @@ void intel_step_init(struct drm_i915_private *i915)
> int revid = INTEL_REVID(i915);
> struct intel_step_info step = {};
>
> +
Superfluous newline.
BR,
Jani.
> if (IS_DG2_G10(i915)) {
> revids = dg2_g10_revid_step_tbl;
> size = ARRAY_SIZE(dg2_g10_revid_step_tbl);
> @@ -141,6 +147,9 @@ void intel_step_init(struct drm_i915_private *i915)
> } else if (IS_ALDERLAKE_P(i915)) {
> revids = adlp_revids;
> size = ARRAY_SIZE(adlp_revids);
> + } else if (IS_ADLS_RPLS(i915)) {
> + revids = adls_rpls_revids;
> + size = ARRAY_SIZE(adls_rpls_revids);
> } else if (IS_ALDERLAKE_S(i915)) {
> revids = adls_revids;
> size = ARRAY_SIZE(adls_revids);
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 1/3] drm: Stop spamming log with drm_cache message
On Tue, 25 Jan 2022, Lucas De Marchi wrote:
> Only x86 and in some cases PPC have support added in drm_cache.c for the
> clflush class of functions. However warning once is sufficient to taint
> the log instead of spamming it with "Architecture has no drm_cache.c
> support" every few millisecond.
>
> Cc: Maarten Lankhorst
> Cc: Maxime Ripard
> Cc: Thomas Zimmermann
> Cc: David Airlie
> Cc: Daniel Vetter
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/drm_cache.c | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
> index f19d9acbe959..2d5a4c463a4f 100644
> --- a/drivers/gpu/drm/drm_cache.c
> +++ b/drivers/gpu/drm/drm_cache.c
> @@ -112,7 +112,6 @@ drm_clflush_pages(struct page *pages[], unsigned long
> num_pages)
> kunmap_atomic(page_virtual);
> }
> #else
> - pr_err("Architecture has no drm_cache.c support\n");
> WARN_ON_ONCE(1);
An alternative would be to replace the two lines with:
WARN_ONCE(1, "Architecture has no drm_cache.c support\n");
But I'm not insisting.
BR,
Jani.
> #endif
> }
> @@ -143,7 +142,6 @@ drm_clflush_sg(struct sg_table *st)
> if (wbinvd_on_all_cpus())
> pr_err("Timed out waiting for cache flush\n");
> #else
> - pr_err("Architecture has no drm_cache.c support\n");
> WARN_ON_ONCE(1);
> #endif
> }
> @@ -177,7 +175,6 @@ drm_clflush_virt_range(void *addr, unsigned long length)
> if (wbinvd_on_all_cpus())
> pr_err("Timed out waiting for cache flush\n");
> #else
> - pr_err("Architecture has no drm_cache.c support\n");
> WARN_ON_ONCE(1);
> #endif
> }
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH] drm/i915/display/vrr: Reset VRR capable property on a long hpd
On Fri, Jan 14, 2022 at 02:33:29PM +0200, Jani Nikula wrote:
> On Wed, 12 Jan 2022, Manasi Navare wrote:
> > With some VRR panels, user can turn VRR ON/OFF on the fly from the panel
> > settings.
> > When VRR is turned OFF ,sends a long HPD to the driver clearing the Ignore
> > MSA bit
> > in the DPCD. Currently the driver parses that onevery HPD but fails to reset
> > the corresponding VRR Capable Connector property.
> > Hence the userspace still sees this as VRR Capable panel which is incorrect.
> >
> > Fix this by explicitly resetting the connector property.
> >
> > Signed-off-by: Manasi Navare
> > ---
> > drivers/gpu/drm/i915/display/intel_dp.c | 11 ++-
> > 1 file changed, 10 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index df2a7d86aef0..4f1418f02b76 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -4539,15 +4539,24 @@ static int intel_dp_get_modes(struct drm_connector
> > *connector)
> > {
> > struct intel_connector *intel_connector = to_intel_connector(connector);
> > struct edid *edid;
> > + struct drm_i915_private *dev_priv = to_i915(connector->dev);
>
> Please call it "i915" for new stuff.
Okay yes will change this to i915
>
> > int num_modes = 0;
> >
> > edid = intel_connector->detect_edid;
> > if (edid) {
> > num_modes = intel_connector_update_modes(connector, edid);
> >
> > - if (intel_vrr_is_capable(connector))
> > + if (intel_vrr_is_capable(connector)) {
> > + drm_dbg_kms(_priv->drm, "VRR capable = TRUE for
> > [CONNECTOR:%d:%s]\n",
> > + connector->base.id, connector->name);
> > drm_connector_set_vrr_capable_property(connector,
> >true);
> > + } else {
> > + drm_dbg_kms(_priv->drm, "VRR capable = false for
> > [CONNECTOR:%d:%s]\n",
> > + connector->base.id, connector->name);
> > + drm_connector_set_vrr_capable_property(connector,
> > + false);
> > + }
>
> Please don't repeat yourself! Also, prefer having [CONNECTOR:%d:%s] at
> the beginning.
>
> bool capable = intel_vrr_is_capable(connector);
>
> drm_dbg_kms(>drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
> connector->base.id, connector->name,
> yesno(capable));
> drm_connector_set_vrr_capable_property(connector, capable);
Okay agree, thanks for the suggestion, will change in the v2 and resend
Regards
Manasi
>
> BR,
> Jani.
>
>
> > }
> >
> > /* Also add fixed mode, which may or may not be present in EDID */
>
> --
> Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH v5 01/10] drm/i915/guc: Update GuC ADS size for error capture lists
On Wed, 26 Jan 2022, Alan Previn wrote:
> Update GuC ADS size allocation to include space for
> the lists of error state capture register descriptors.
>
> Also, populate the lists of registers we want GuC to report back to
> Host on engine reset events. This list should include global,
> engine-class and engine-instance registers for every engine-class
> type on the current hardware.
>
> NOTE: Start with a sample table of register lists to layout the
> framework before adding real registers in subsequent patch.
>
> Signed-off-by: Alan Previn
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h | 36 ++
> drivers/gpu/drm/i915/gt/uc/intel_guc.c| 13 +-
> drivers/gpu/drm/i915/gt/uc/intel_guc.h| 11 +-
> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 36 +-
> .../gpu/drm/i915/gt/uc/intel_guc_capture.c| 450 ++
> .../gpu/drm/i915/gt/uc/intel_guc_capture.h| 20 +
> drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 17 +
> 8 files changed, 555 insertions(+), 29 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
> create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_capture.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index a26e6736bebb..236bcd6cd8ea 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -183,6 +183,7 @@ i915-y += gt/uc/intel_uc.o \
> gt/uc/intel_uc_fw.o \
> gt/uc/intel_guc.o \
> gt/uc/intel_guc_ads.o \
> + gt/uc/intel_guc_capture.o \
> gt/uc/intel_guc_ct.o \
> gt/uc/intel_guc_debugfs.o \
> gt/uc/intel_guc_fw.o \
> diff --git a/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
> b/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
> new file mode 100644
> index ..15b8c02b8a76
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
> @@ -0,0 +1,36 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2021-2021 Intel Corporation
> + */
> +
> +#ifndef _INTEL_GUC_CAPTURE_FWIF_H
> +#define _INTEL_GUC_CAPTURE_FWIF_H
> +
> +#include
> +#include "intel_guc_fwif.h"
> +
> +struct intel_guc;
> +
> +struct __guc_mmio_reg_descr {
> + i915_reg_t reg;
> + u32 flags;
> + u32 mask;
> + const char *regname;
> +};
> +
> +struct __guc_mmio_reg_descr_group {
> + struct __guc_mmio_reg_descr *list;
> + u32 num_regs;
> + u32 owner; /* see enum guc_capture_owner */
> + u32 type; /* see enum guc_capture_type */
> + u32 engine; /* as per MAX_ENGINE_CLASS */
> +};
> +
> +struct __guc_state_capture_priv {
> + struct __guc_mmio_reg_descr_group *reglists;
> + u16
> num_instance_regs[GUC_CAPTURE_LIST_INDEX_MAX][GUC_MAX_ENGINE_CLASSES];
> + u16 num_class_regs[GUC_CAPTURE_LIST_INDEX_MAX][GUC_MAX_ENGINE_CLASSES];
> + u16 num_global_regs[GUC_CAPTURE_LIST_INDEX_MAX];
> +};
> +
> +#endif /* _INTEL_GUC_CAPTURE_FWIF_H */
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index ba2a67f9e500..d035a3ba8700 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -8,8 +8,9 @@
> #include "gt/intel_gt_irq.h"
> #include "gt/intel_gt_pm_irq.h"
> #include "intel_guc.h"
> -#include "intel_guc_slpc.h"
> #include "intel_guc_ads.h"
> +#include "intel_guc_capture.h"
> +#include "intel_guc_slpc.h"
> #include "intel_guc_submission.h"
> #include "i915_drv.h"
> #include "i915_irq.h"
> @@ -361,9 +362,14 @@ int intel_guc_init(struct intel_guc *guc)
> if (ret)
> goto err_fw;
>
> - ret = intel_guc_ads_create(guc);
> + ret = intel_guc_capture_init(guc);
> if (ret)
> goto err_log;
> +
> + ret = intel_guc_ads_create(guc);
> + if (ret)
> + goto err_capture;
> +
> GEM_BUG_ON(!guc->ads_vma);
>
> ret = intel_guc_ct_init(>ct);
> @@ -402,6 +408,8 @@ int intel_guc_init(struct intel_guc *guc)
> intel_guc_ct_fini(>ct);
> err_ads:
> intel_guc_ads_destroy(guc);
> +err_capture:
> + intel_guc_capture_destroy(guc);
> err_log:
> intel_guc_log_destroy(>log);
> err_fw:
> @@ -429,6 +437,7 @@ void intel_guc_fini(struct intel_guc *guc)
> intel_guc_ct_fini(>ct);
>
> intel_guc_ads_destroy(guc);
> + intel_guc_capture_destroy(guc);
> intel_guc_log_destroy(>log);
> intel_uc_fw_fini(>fw);
> }
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> index 697d9d66acef..4e819853ec2e 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> @@ -9,18 +9,19 @@
> #include
> #include
>
> -#include "intel_uncore.h"
> +#include "intel_guc_ct.h"
> #include "intel_guc_fw.h"
> #include "intel_guc_fwif.h"
> -#include "intel_guc_ct.h"
> #include
Re: [Intel-gfx] [PATCH v5 02/10] drm/i915/guc: Add XE_LP registers for GuC error state capture.
On Wed, 26 Jan 2022, Alan Previn wrote:
> Add device specific tables and register lists to cover different engines
> class types for GuC error state capture for XE_LP products.
>
> Also, add runtime allocation and freeing of extended register lists
> for registers that need steering identifiers that depend on
> the detected HW config.
>
> Signed-off-by: Alan Previn
> ---
> drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h | 2 +
> .../gpu/drm/i915/gt/uc/intel_guc_capture.c| 207 +++---
> drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 4 +-
> 3 files changed, 180 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
> b/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
> index 15b8c02b8a76..a2f97d04ff18 100644
> --- a/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
> +++ b/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
> @@ -24,6 +24,8 @@ struct __guc_mmio_reg_descr_group {
> u32 owner; /* see enum guc_capture_owner */
> u32 type; /* see enum guc_capture_type */
> u32 engine; /* as per MAX_ENGINE_CLASS */
> + int num_ext;
> + struct __guc_mmio_reg_descr *ext;
> };
>
> struct __guc_state_capture_priv {
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> index 06873d617b8b..b6882074fc8d 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> @@ -19,40 +19,101 @@
> * NOTE: For engine-registers, GuC only needs the register offsets
> * from the engine-mmio-base
> */
> +#define COMMON_GEN12BASE_GLOBAL() \
> + {GEN12_FAULT_TLB_DATA0,0, 0, "GEN12_FAULT_TLB_DATA0"}, \
> + {GEN12_FAULT_TLB_DATA1,0, 0, "GEN12_FAULT_TLB_DATA1"}, \
> + {FORCEWAKE_MT, 0, 0, "FORCEWAKE_MT"}, \
> + {GEN12_AUX_ERR_DBG,0, 0, "GEN12_AUX_ERR_DBG"}, \
> + {GEN12_GAM_DONE, 0, 0, "GEN12_GAM_DONE"}, \
> + {GEN12_RING_FAULT_REG, 0, 0, "GEN12_RING_FAULT_REG"}
> +
> +#define COMMON_GEN12BASE_ENGINE_INSTANCE() \
> + {RING_PSMI_CTL(0), 0, 0, "RING_PSMI_CTL"}, \
> + {RING_ESR(0), 0, 0, "RING_ESR"}, \
> + {RING_DMA_FADD(0), 0, 0, "RING_DMA_FADD_LOW32"}, \
> + {RING_DMA_FADD_UDW(0), 0, 0, "RING_DMA_FADD_UP32"}, \
> + {RING_IPEIR(0),0, 0, "RING_IPEIR"}, \
> + {RING_IPEHR(0),0, 0, "RING_IPEHR"}, \
> + {RING_INSTPS(0), 0, 0, "RING_INSTPS"}, \
> + {RING_BBADDR(0), 0, 0, "RING_BBADDR_LOW32"}, \
> + {RING_BBADDR_UDW(0), 0, 0, "RING_BBADDR_UP32"}, \
> + {RING_BBSTATE(0), 0, 0, "RING_BBSTATE"}, \
> + {CCID(0), 0, 0, "CCID"}, \
> + {RING_ACTHD(0),0, 0, "RING_ACTHD_LOW32"}, \
> + {RING_ACTHD_UDW(0),0, 0, "RING_ACTHD_UP32"}, \
> + {RING_INSTPM(0), 0, 0, "RING_INSTPM"}, \
> + {RING_NOPID(0),0, 0, "RING_NOPID"}, \
> + {RING_START(0),0, 0, "RING_START"}, \
> + {RING_HEAD(0), 0, 0, "RING_HEAD"}, \
> + {RING_TAIL(0), 0, 0, "RING_TAIL"}, \
> + {RING_CTL(0), 0, 0, "RING_CTL"}, \
> + {RING_MI_MODE(0), 0, 0, "RING_MI_MODE"}, \
> + {RING_CONTEXT_CONTROL(0), 0, 0, "RING_CONTEXT_CONTROL"}, \
> + {RING_INSTDONE(0), 0, 0, "RING_INSTDONE"}, \
> + {RING_HWS_PGA(0), 0, 0, "RING_HWS_PGA"}, \
> + {RING_MODE_GEN7(0),0, 0, "RING_MODE_GEN7"}, \
> + {GEN8_RING_PDP_LDW(0, 0), 0, 0, "GEN8_RING_PDP0_LDW"}, \
> + {GEN8_RING_PDP_UDW(0, 0), 0, 0, "GEN8_RING_PDP0_UDW"}, \
> + {GEN8_RING_PDP_LDW(0, 1), 0, 0, "GEN8_RING_PDP1_LDW"}, \
> + {GEN8_RING_PDP_UDW(0, 1), 0, 0, "GEN8_RING_PDP1_UDW"}, \
> + {GEN8_RING_PDP_LDW(0, 2), 0, 0, "GEN8_RING_PDP2_LDW"}, \
> + {GEN8_RING_PDP_UDW(0, 2), 0, 0, "GEN8_RING_PDP2_UDW"}, \
> + {GEN8_RING_PDP_LDW(0, 3), 0, 0, "GEN8_RING_PDP3_LDW"}, \
> + {GEN8_RING_PDP_UDW(0, 3), 0, 0, "GEN8_RING_PDP3_UDW"}
> +
> +#define COMMON_GEN12BASE_HAS_EU() \
> + {EIR, 0, 0, "EIR"}
> +
> +#define COMMON_GEN12BASE_RENDER() \
> + {GEN7_SC_INSTDONE, 0, 0, "GEN7_SC_INSTDONE"}, \
> + {GEN12_SC_INSTDONE_EXTRA, 0, 0, "GEN12_SC_INSTDONE_EXTRA"}, \
> + {GEN12_SC_INSTDONE_EXTRA2, 0, 0, "GEN12_SC_INSTDONE_EXTRA2"}
> +
> +#define COMMON_GEN12BASE_VEC() \
> + {GEN12_SFC_DONE(0),0, 0, "GEN12_SFC_DONE0"}, \
> + {GEN12_SFC_DONE(1),0, 0, "GEN12_SFC_DONE1"}, \
> + {GEN12_SFC_DONE(2),0, 0, "GEN12_SFC_DONE2"}, \
> + {GEN12_SFC_DONE(3),0, 0, "GEN12_SFC_DONE3"}
> +
> /* XE_LPD - Global */
> static struct __guc_mmio_reg_descr
[Intel-gfx] ✓ Fi.CI.BAT: success for lib/string_helpers: Add a few string helpers (rev2)
== Series Details ==
Series: lib/string_helpers: Add a few string helpers (rev2)
URL : https://patchwork.freedesktop.org/series/99030/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11145 -> Patchwork_22110
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22110/index.html
Participating hosts (46 -> 42)
--
Missing(4): fi-ctg-p8600 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u
Known issues
Here are the changes found in Patchwork_22110 that come from known issues:
### CI changes ###
Possible fixes
* boot:
- fi-ilk-650: [FAIL][1] -> [PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/fi-ilk-650/boot.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22110/fi-ilk-650/boot.html
### IGT changes ###
Issues hit
* igt@amdgpu/amd_cs_nop@nop-compute0:
- fi-ilk-650: NOTRUN -> [SKIP][3] ([fdo#109271]) +39 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22110/fi-ilk-650/igt@amdgpu/amd_cs_...@nop-compute0.html
* igt@amdgpu/amd_cs_nop@sync-fork-gfx0:
- fi-skl-6600u: NOTRUN -> [SKIP][4] ([fdo#109271]) +21 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22110/fi-skl-6600u/igt@amdgpu/amd_cs_...@sync-fork-gfx0.html
* igt@debugfs_test@read_all_entries:
- fi-kbl-soraka: [PASS][5] -> [DMESG-WARN][6] ([i915#1982] /
[i915#262])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/fi-kbl-soraka/igt@debugfs_test@read_all_entries.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22110/fi-kbl-soraka/igt@debugfs_test@read_all_entries.html
* igt@gem_exec_suspend@basic-s3@smem:
- fi-bdw-5557u: [PASS][7] -> [INCOMPLETE][8] ([i915#146])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22110/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html
* igt@gem_huc_copy@huc-copy:
- fi-skl-6600u: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#2190])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22110/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@verify-random:
- fi-skl-6600u: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4613]) +3
similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22110/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html
* igt@kms_chamelium@dp-hpd-fast:
- fi-ilk-650: NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +8
similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22110/fi-ilk-650/igt@kms_chamel...@dp-hpd-fast.html
* igt@kms_chamelium@vga-edid-read:
- fi-skl-6600u: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8
similar issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22110/fi-skl-6600u/igt@kms_chamel...@vga-edid-read.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-skl-6600u: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#533])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22110/fi-skl-6600u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
Possible fixes
* igt@gem_flink_basic@bad-flink:
- fi-skl-6600u: [FAIL][14] ([i915#4547]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22110/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [DMESG-WARN][16] ([i915#4269]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22110/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4898]: https://gitlab.freedesktop.org/drm/intel/issues/4898
[i915#533]:
Re: [Intel-gfx] [PATCH v5 01/10] drm/i915/guc: Update GuC ADS size for error capture lists
On Wed, 26 Jan 2022, Alan Previn wrote:
> Update GuC ADS size allocation to include space for
> the lists of error state capture register descriptors.
>
> Also, populate the lists of registers we want GuC to report back to
> Host on engine reset events. This list should include global,
> engine-class and engine-instance registers for every engine-class
> type on the current hardware.
>
> NOTE: Start with a sample table of register lists to layout the
> framework before adding real registers in subsequent patch.
>
> Signed-off-by: Alan Previn
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h | 36 ++
> drivers/gpu/drm/i915/gt/uc/intel_guc.c| 13 +-
> drivers/gpu/drm/i915/gt/uc/intel_guc.h| 11 +-
> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 36 +-
> .../gpu/drm/i915/gt/uc/intel_guc_capture.c| 450 ++
> .../gpu/drm/i915/gt/uc/intel_guc_capture.h| 20 +
> drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 17 +
> 8 files changed, 555 insertions(+), 29 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
> create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_capture.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index a26e6736bebb..236bcd6cd8ea 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -183,6 +183,7 @@ i915-y += gt/uc/intel_uc.o \
> gt/uc/intel_uc_fw.o \
> gt/uc/intel_guc.o \
> gt/uc/intel_guc_ads.o \
> + gt/uc/intel_guc_capture.o \
> gt/uc/intel_guc_ct.o \
> gt/uc/intel_guc_debugfs.o \
> gt/uc/intel_guc_fw.o \
> diff --git a/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
> b/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
> new file mode 100644
> index ..15b8c02b8a76
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
> @@ -0,0 +1,36 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2021-2021 Intel Corporation
> + */
> +
> +#ifndef _INTEL_GUC_CAPTURE_FWIF_H
> +#define _INTEL_GUC_CAPTURE_FWIF_H
> +
> +#include
> +#include "intel_guc_fwif.h"
> +
> +struct intel_guc;
> +
> +struct __guc_mmio_reg_descr {
> + i915_reg_t reg;
> + u32 flags;
> + u32 mask;
> + const char *regname;
> +};
> +
> +struct __guc_mmio_reg_descr_group {
> + struct __guc_mmio_reg_descr *list;
> + u32 num_regs;
> + u32 owner; /* see enum guc_capture_owner */
> + u32 type; /* see enum guc_capture_type */
> + u32 engine; /* as per MAX_ENGINE_CLASS */
> +};
> +
> +struct __guc_state_capture_priv {
> + struct __guc_mmio_reg_descr_group *reglists;
> + u16
> num_instance_regs[GUC_CAPTURE_LIST_INDEX_MAX][GUC_MAX_ENGINE_CLASSES];
> + u16 num_class_regs[GUC_CAPTURE_LIST_INDEX_MAX][GUC_MAX_ENGINE_CLASSES];
> + u16 num_global_regs[GUC_CAPTURE_LIST_INDEX_MAX];
> +};
> +
> +#endif /* _INTEL_GUC_CAPTURE_FWIF_H */
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index ba2a67f9e500..d035a3ba8700 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -8,8 +8,9 @@
> #include "gt/intel_gt_irq.h"
> #include "gt/intel_gt_pm_irq.h"
> #include "intel_guc.h"
> -#include "intel_guc_slpc.h"
> #include "intel_guc_ads.h"
> +#include "intel_guc_capture.h"
> +#include "intel_guc_slpc.h"
> #include "intel_guc_submission.h"
> #include "i915_drv.h"
> #include "i915_irq.h"
> @@ -361,9 +362,14 @@ int intel_guc_init(struct intel_guc *guc)
> if (ret)
> goto err_fw;
>
> - ret = intel_guc_ads_create(guc);
> + ret = intel_guc_capture_init(guc);
> if (ret)
> goto err_log;
> +
> + ret = intel_guc_ads_create(guc);
> + if (ret)
> + goto err_capture;
> +
> GEM_BUG_ON(!guc->ads_vma);
>
> ret = intel_guc_ct_init(>ct);
> @@ -402,6 +408,8 @@ int intel_guc_init(struct intel_guc *guc)
> intel_guc_ct_fini(>ct);
> err_ads:
> intel_guc_ads_destroy(guc);
> +err_capture:
> + intel_guc_capture_destroy(guc);
> err_log:
> intel_guc_log_destroy(>log);
> err_fw:
> @@ -429,6 +437,7 @@ void intel_guc_fini(struct intel_guc *guc)
> intel_guc_ct_fini(>ct);
>
> intel_guc_ads_destroy(guc);
> + intel_guc_capture_destroy(guc);
> intel_guc_log_destroy(>log);
> intel_uc_fw_fini(>fw);
> }
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> index 697d9d66acef..4e819853ec2e 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> @@ -9,18 +9,19 @@
> #include
> #include
>
> -#include "intel_uncore.h"
> +#include "intel_guc_ct.h"
> #include "intel_guc_fw.h"
> #include "intel_guc_fwif.h"
> -#include "intel_guc_ct.h"
> #include
Re: [Intel-gfx] [PATCH v2 4/5] mei: gsc: add runtime pm handlers
On Wed, Jan 19, 2022 at 05:58:06PM +0200, Alexander Usyskin wrote:
> From: Tomas Winkler
>
> Implement runtime handlers for mei-gsc, to track
> idle state of the device properly.
>
> CC: Rodrigo Vivi
> Signed-off-by: Tomas Winkler
> Signed-off-by: Alexander Usyskin
> ---
> drivers/misc/mei/gsc-me.c | 80 ++-
> 1 file changed, 79 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c
> index f58e54d2c1fc..fddae8009b62 100644
> --- a/drivers/misc/mei/gsc-me.c
> +++ b/drivers/misc/mei/gsc-me.c
> @@ -158,7 +158,85 @@ static int __maybe_unused mei_gsc_pm_resume(struct
> device *device)
> return 0;
> }
>
> -static SIMPLE_DEV_PM_OPS(mei_gsc_pm_ops, mei_gsc_pm_suspend,
> mei_gsc_pm_resume);
> +static int __maybe_unused mei_gsc_pm_runtime_idle(struct device *device)
> +{
> + struct mei_device *dev;
> +
> + dev_dbg(device, "rpm: me: runtime_idle\n");
> +
> + dev = dev_get_drvdata(device);
> + if (!dev)
> + return -ENODEV;
> + if (mei_write_is_idle(dev))
> + pm_runtime_autosuspend(device);
> +
> + return -EBUSY;
> +}
> +
> +static int __maybe_unused mei_gsc_pm_runtime_suspend(struct device *device)
> +{
> + struct mei_device *dev;
> + struct mei_me_hw *hw;
> + int ret;
> +
> + dev_dbg(device, "rpm: me: runtime suspend\n");
No need for debugging code to remain, use ftrace if you really need it.
Same for other dev_dbg() calls in this patch, they can all be removed.
thanks,
greg k-h
Re: [Intel-gfx] [PATCH v2 2/5] mei: add support for graphics system controller (gsc) devices
On Wed, Jan 19, 2022 at 05:58:04PM +0200, Alexander Usyskin wrote: > From: Tomas Winkler > > GSC is a graphics system controller, based on CSE, it provides > a chassis controller for graphics discrete cards, as well as it > supports media protection on selected devices. > > mei_gsc binds to a auxiliary devices exposed by Intel discrete > driver i915. > > Signed-off-by: Alexander Usyskin > Signed-off-by: Tomas Winkler > --- > drivers/misc/mei/Kconfig | 14 +++ > drivers/misc/mei/Makefile | 3 + > drivers/misc/mei/gsc-me.c | 192 ++ > drivers/misc/mei/hw-me.c | 27 +- > drivers/misc/mei/hw-me.h | 2 + > 5 files changed, 236 insertions(+), 2 deletions(-) > create mode 100644 drivers/misc/mei/gsc-me.c > > diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig > index 0e0bcd0da852..ec119bb98251 100644 > --- a/drivers/misc/mei/Kconfig > +++ b/drivers/misc/mei/Kconfig > @@ -46,6 +46,20 @@ config INTEL_MEI_TXE > Supported SoCs: > Intel Bay Trail > > +config INTEL_MEI_GSC > + tristate "Intel MEI GSC embedded device" > + select INTEL_MEI > + select INTEL_MEI_ME Please don't select, why not just depend on? thanks, greg k-h
Re: [Intel-gfx] [PATCH 01/20] drm: improve drm_buddy_alloc function
On Wed, 26 Jan 2022, Matthew Auld wrote:
> From: Arunpravin
>
> - Make drm_buddy_alloc a single function to handle
> range allocation and non-range allocation demands
>
> - Implemented a new function alloc_range() which allocates
> the requested power-of-two block comply with range limitations
>
> - Moved order computation and memory alignment logic from
> i915 driver to drm buddy
>
> v2:
> merged below changes to keep the build unbroken
>- drm_buddy_alloc_range() becomes obsolete and may be removed
>- enable ttm range allocation (fpfn / lpfn) support in i915 driver
>- apply enhanced drm_buddy_alloc() function to i915 driver
>
> v3(Matthew Auld):
> - Fix alignment issues and remove unnecessary list_empty check
> - add more validation checks for input arguments
> - make alloc_range() block allocations as bottom-up
> - optimize order computation logic
> - replace uint64_t with u64, which is preferred in the kernel
>
> v4(Matthew Auld):
> - keep drm_buddy_alloc_range() function implementation for generic
> actual range allocations
> - keep alloc_range() implementation for end bias allocations
>
> v5(Matthew Auld):
> - modify drm_buddy_alloc() passing argument place->lpfn to lpfn
> as place->lpfn will currently always be zero for i915
>
> v6(Matthew Auld):
> - fixup potential uaf - If we are unlucky and can't allocate
> enough memory when splitting blocks, where we temporarily
> end up with the given block and its buddy on the respective
> free list, then we need to ensure we delete both blocks,
> and no just the buddy, before potentially freeing them
>
> - fix warnings reported by kernel test robot
>
> Signed-off-by: Arunpravin
> ---
> drivers/gpu/drm/drm_buddy.c | 326 +-
> drivers/gpu/drm/i915/i915_ttm_buddy_manager.c | 67 ++--
> drivers/gpu/drm/i915/i915_ttm_buddy_manager.h | 2 +
> include/drm/drm_buddy.h | 22 +-
> 4 files changed, 293 insertions(+), 124 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_buddy.c b/drivers/gpu/drm/drm_buddy.c
> index d60878bc9c20..954e31962c74 100644
> --- a/drivers/gpu/drm/drm_buddy.c
> +++ b/drivers/gpu/drm/drm_buddy.c
> @@ -282,23 +282,99 @@ void drm_buddy_free_list(struct drm_buddy *mm, struct
> list_head *objects)
> }
> EXPORT_SYMBOL(drm_buddy_free_list);
>
> -/**
> - * drm_buddy_alloc_blocks - allocate power-of-two blocks
> - *
> - * @mm: DRM buddy manager to allocate from
> - * @order: size of the allocation
> - *
> - * The order value here translates to:
> - *
> - * 0 = 2^0 * mm->chunk_size
> - * 1 = 2^1 * mm->chunk_size
> - * 2 = 2^2 * mm->chunk_size
> - *
> - * Returns:
> - * allocated ptr to the _buddy_block on success
> - */
> -struct drm_buddy_block *
> -drm_buddy_alloc_blocks(struct drm_buddy *mm, unsigned int order)
> +static inline bool overlaps(u64 s1, u64 e1, u64 s2, u64 e2)
> +{
> + return s1 <= e2 && e1 >= s2;
> +}
> +
> +static inline bool contains(u64 s1, u64 e1, u64 s2, u64 e2)
> +{
> + return s1 <= s2 && e1 >= e2;
> +}
> +
> +static struct drm_buddy_block *
> +alloc_range_bias(struct drm_buddy *mm,
> + u64 start, u64 end,
> + unsigned int order)
> +{
> + struct drm_buddy_block *block;
> + struct drm_buddy_block *buddy;
> + LIST_HEAD(dfs);
> + int err;
> + int i;
> +
> + end = end - 1;
> +
> + for (i = 0; i < mm->n_roots; ++i)
> + list_add_tail(>roots[i]->tmp_link, );
> +
> + do {
> + u64 block_start;
> + u64 block_end;
> +
> + block = list_first_entry_or_null(,
> + struct drm_buddy_block,
> + tmp_link);
> + if (!block)
> + break;
> +
> + list_del(>tmp_link);
> +
> + if (drm_buddy_block_order(block) < order)
> + continue;
> +
> + block_start = drm_buddy_block_offset(block);
> + block_end = block_start + drm_buddy_block_size(mm, block) - 1;
> +
> + if (!overlaps(start, end, block_start, block_end))
> + continue;
> +
> + if (drm_buddy_block_is_allocated(block))
> + continue;
> +
> + if (contains(start, end, block_start, block_end) &&
> + order == drm_buddy_block_order(block)) {
> + /*
> + * Find the free block within the range.
> + */
> + if (drm_buddy_block_is_free(block))
> + return block;
> +
> + continue;
> + }
> +
> + if (!drm_buddy_block_is_split(block)) {
> + err = split_block(mm, block);
> + if (unlikely(err))
> + goto err_undo;
> + }
> +
> + list_add(>right->tmp_link, );
> +
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for lib/string_helpers: Add a few string helpers (rev2)
== Series Details == Series: lib/string_helpers: Add a few string helpers (rev2) URL : https://patchwork.freedesktop.org/series/99030/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for lib/string_helpers: Add a few string helpers (rev2)
== Series Details == Series: lib/string_helpers: Add a few string helpers (rev2) URL : https://patchwork.freedesktop.org/series/99030/ State : warning == Summary == $ dim checkpatch origin/drm-tip 7b5dcbd538bd lib/string_helpers: Consolidate string helpers implementation f129a0e5877f drm/i915: Fix trailing semicolon -:8: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #8: -:1189: WARNING:TRAILING_SEMICOLON: macros should not use a trailing semicolon total: 0 errors, 1 warnings, 0 checks, 8 lines checked f9c3d95ede47 drm/i915: Use str_yes_no() -:331: WARNING:LONG_LINE: line length of 104 exceeds 100 columns #331: FILE: drivers/gpu/drm/i915/display/intel_display_trace.h:213: + str_yes_no(__entry->cxsr), __entry->sr_plane, __entry->sr_cursor, __entry->sr_fbc, -:332: WARNING:LONG_LINE: line length of 110 exceeds 100 columns #332: FILE: drivers/gpu/drm/i915/display/intel_display_trace.h:214: + str_yes_no(__entry->hpll), __entry->hpll_plane, __entry->hpll_cursor, __entry->hpll_fbc, -:551: WARNING:LONG_LINE: line length of 107 exceeds 100 columns #551: FILE: drivers/gpu/drm/i915/gt/intel_engine_cs.c:1644: + str_yes_no(test_bit(TASKLET_STATE_SCHED, >sched_engine->tasklet.state)), -:728: WARNING:LONG_LINE: line length of 103 exceeds 100 columns #728: FILE: drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c:313: + str_yes_no((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == GEN6_RP_MEDIA_SW_MODE)); -:744: WARNING:LONG_LINE: line length of 103 exceeds 100 columns #744: FILE: drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c:422: + str_yes_no((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == GEN6_RP_MEDIA_SW_MODE)); -:1184: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'name' may be better as '(name)' to avoid precedence issues #1184: FILE: drivers/gpu/drm/i915/intel_device_info.c:115: +#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->name)) total: 0 errors, 5 warnings, 1 checks, 1086 lines checked bd7513369767 drm/i915: Use str_enable_disable() 29eecd097b7a drm/i915: Use str_enabled_disabled() 677b985a1afd drm/i915: Use str_on_off() 63c3bd9cc94f drm/amd/display: Use str_yes_no() 012e3664260b drm/gem: Sort includes alphabetically b23c0f35def5 drm: Convert open-coded yes/no strings to yesno() -:98: WARNING:LONG_LINE: line length of 108 exceeds 100 columns #98: FILE: drivers/gpu/drm/drm_client_modeset.c:245: + connector->display_info.non_desktop ? "non desktop" : str_yes_no(enabled[i])); total: 0 errors, 1 warnings, 0 checks, 136 lines checked 23940ca63a6c tomoyo: Use str_yes_no() faebfa7913d6 cxgb4: Use str_yes_no()
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915: Fix oops due to missing stack depot
== Series Details == Series: series starting with [1/2] drm/i915: Fix oops due to missing stack depot URL : https://patchwork.freedesktop.org/series/99353/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11141_full -> Patchwork_22109_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22109_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22109_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 10) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22109_full: ### IGT changes ### Possible regressions * igt@i915_selftest@mock@vma: - shard-skl: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22109/shard-skl10/igt@i915_selftest@m...@vma.html Known issues Here are the changes found in Patchwork_22109_full that come from known issues: ### CI changes ### Issues hit * boot: - shard-glk: ([PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26]) -> ([PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [FAIL][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51]) ([i915#4392]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11141/shard-glk9/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11141/shard-glk9/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11141/shard-glk8/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11141/shard-glk8/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11141/shard-glk8/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11141/shard-glk7/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11141/shard-glk7/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11141/shard-glk7/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11141/shard-glk6/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11141/shard-glk6/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11141/shard-glk6/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11141/shard-glk5/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11141/shard-glk5/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11141/shard-glk5/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11141/shard-glk4/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11141/shard-glk4/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11141/shard-glk4/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11141/shard-glk3/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11141/shard-glk3/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11141/shard-glk3/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11141/shard-glk2/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11141/shard-glk2/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11141/shard-glk1/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11141/shard-glk1/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11141/shard-glk1/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22109/shard-glk7/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22109/shard-glk7/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22109/shard-glk6/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22109/shard-glk6/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22109/shard-glk5/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22109/shard-glk5/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22109/shard-glk5/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22109/shard-glk4/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22109/shard-glk4/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22109/shard-glk4/boot.html [37]:
Re: [Intel-gfx] [PATCH v5 4/5] drm/i915: add gtt misalignment test
On 26/01/2022 14:05, Thomas Hellström (Intel) wrote:
On 1/25/22 20:35, Robert Beckett wrote:
add test to check handling of misaligned offsets and sizes
v4:
* remove spurious blank lines
* explicitly cast intel_region_id to intel_memory_type in
misaligned_pin
Reported-by: kernel test robot
Signed-off-by: Robert Beckett
---
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 128 ++
1 file changed, 128 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index b80788a2b7f9..f082b5ff3b5e 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -22,10 +22,12 @@
*
*/
+#include "gt/intel_gtt.h"
#include
#include
#include "gem/i915_gem_context.h"
+#include "gem/i915_gem_region.h"
#include "gem/selftests/mock_context.h"
#include "gt/intel_context.h"
#include "gt/intel_gpu_commands.h"
@@ -1067,6 +1069,120 @@ static int shrink_boom(struct
i915_address_space *vm,
return err;
}
+static int misaligned_case(struct i915_address_space *vm, struct
intel_memory_region *mr,
+ u64 addr, u64 size, unsigned long flags)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ int err = 0;
+ u64 expected_vma_size, expected_node_size;
+
+ obj = i915_gem_object_create_region(mr, size, 0, 0);
+ if (IS_ERR(obj))
+ return PTR_ERR(obj);
+
+ vma = i915_vma_instance(obj, vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto err_put;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, addr | flags);
+ if (err)
+ goto err_put;
+ i915_vma_unpin(vma);
+
+ if (!drm_mm_node_allocated(>node)) {
+ err = -EINVAL;
+ goto err_put;
+ }
+
+ if (i915_vma_misplaced(vma, 0, 0, addr | flags)) {
+ err = -EINVAL;
+ goto err_put;
+ }
+
+ expected_vma_size = round_up(size, 1 <<
(ffs(vma->resource->page_sizes_gtt) - 1));
+ expected_node_size = expected_vma_size;
+
+ if (IS_DG2(vm->i915) && i915_gem_object_is_lmem(obj)) {
+ /* dg2 should expand lmem node to 2MB */
Should this test be NEEDS_COMPACT_PT()?
Otherwise LGTM. Reviewed-by: Thomas Hellström
Thanks. Good catch, forgot to retrofit the new macro here.
Re: [Intel-gfx] [PATCH v5 2/5] drm/i915: enforce min GTT alignment for discrete cards
On 26/01/2022 15:45, Thomas Hellström (Intel) wrote:
On 1/25/22 20:35, Robert Beckett wrote:
From: Matthew Auld
For local-memory objects we need to align the GTT addresses
to 64K, both for the ppgtt and ggtt.
We need to support vm->min_alignment > 4K, depending
on the vm itself and the type of object we are inserting.
With this in mind update the GTT selftests to take this
into account.
For compact-pt we further align and pad lmem object GTT addresses
to 2MB to ensure PDEs contain consistent page sizes as
required by the HW.
v3:
* use needs_compact_pt flag to discriminate between
64K and 64K with compact-pt
* add i915_vm_obj_min_alignment
* use i915_vm_obj_min_alignment to round up vma reservation
if compact-pt instead of hard coding
v5:
* fix i915_vm_obj_min_alignment for internal objects which
have no memory region
Signed-off-by: Matthew Auld
Signed-off-by: Ramalingam C
Signed-off-by: Robert Beckett
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
---
.../i915/gem/selftests/i915_gem_client_blt.c | 23 +++--
drivers/gpu/drm/i915/gt/intel_gtt.c | 12 +++
drivers/gpu/drm/i915/gt/intel_gtt.h | 18
drivers/gpu/drm/i915/i915_vma.c | 9 ++
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 96 ---
5 files changed, 117 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
index c8ff8bf0986d..f0bfce53258f 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
@@ -39,6 +39,7 @@ struct tiled_blits {
struct blit_buffer scratch;
struct i915_vma *batch;
u64 hole;
+ u64 align;
u32 width;
u32 height;
};
@@ -410,14 +411,21 @@ tiled_blits_create(struct intel_engine_cs
*engine, struct rnd_state *prng)
goto err_free;
}
- hole_size = 2 * PAGE_ALIGN(WIDTH * HEIGHT * 4);
+ t->align = I915_GTT_PAGE_SIZE_2M; /* XXX worst case, derive from
vm! */
+ t->align = max(t->align,
+ i915_vm_min_alignment(t->ce->vm, INTEL_MEMORY_LOCAL));
+ t->align = max(t->align,
+ i915_vm_min_alignment(t->ce->vm, INTEL_MEMORY_SYSTEM));
Don't we always end up with 2M here, regardless of the vm restrictions?
agreed. I will drop the 2M worst case.
Re: [Intel-gfx] [PATCH v5 1/5] drm/i915: add needs_compact_pt flag
On 26/01/2022 13:49, Thomas Hellström (Intel) wrote:
On 1/25/22 20:35, Robert Beckett wrote:
From: Ramalingam C
Add a new platform flag, needs_compact_pt, to mark the requirement of
compact pt layout support for the ppGTT when using 64K GTT pages.
With this flag has_64k_pages will only indicate requirement of 64K
GTT page sizes or larger for device local memory access.
Suggested-by: Matthew Auld
Signed-off-by: Ramalingam C
Signed-off-by: Robert Beckett
---
drivers/gpu/drm/i915/i915_drv.h | 10 +++---
drivers/gpu/drm/i915/i915_pci.c | 2 ++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
3 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h
b/drivers/gpu/drm/i915/i915_drv.h
index 44c1f98144b4..1258b7779705 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1512,12 +1512,16 @@ IS_SUBPLATFORM(const struct drm_i915_private
*i915,
/*
* Set this flag, when platform requires 64K GTT page sizes or
larger for
- * device local memory access. Also this flag implies that we require or
- * at least support the compact PT layout for the ppGTT when using
the 64K
- * GTT pages.
Why do we remove these comment lines?
Because HAS_64K_PAGES now means just 64K page, it no longer means also
requires compact pt.
This is to support other products that will have 64K but not have the
PDE non-sharing restriction in future.
Those lines moved to the next change NEEDS_COMPACT_PT, which is now
separate.
+ * device local memory access.
*/
#define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)
+/* Set this flag when platform doesn't allow both 64k pages and 4k
pages in
First line of multi-line comments should be empty.
thanks. I'm surprised checkpatch didnt spot that.
+ * the same PT. this flag means we need to support compact PT layout
for the
+ * ppGTT when using the 64K GTT pages.
+ */
+#define NEEDS_COMPACT_PT(dev_priv)
(INTEL_INFO(dev_priv)->needs_compact_pt)
+
#define HAS_IPC(dev_priv)
(INTEL_INFO(dev_priv)->display.has_ipc)
#define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
diff --git a/drivers/gpu/drm/i915/i915_pci.c
b/drivers/gpu/drm/i915/i915_pci.c
index 4081fd50ba9d..799b56569ef5 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1028,6 +1028,7 @@ static const struct intel_device_info
xehpsdv_info = {
PLATFORM(INTEL_XEHPSDV),
.display = { },
.has_64k_pages = 1,
+ .needs_compact_pt = 1,
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) |
BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |
@@ -1045,6 +1046,7 @@ static const struct intel_device_info dg2_info = {
.media.rel = 55,
PLATFORM(INTEL_DG2),
.has_64k_pages = 1,
+ .needs_compact_pt = 1,
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) |
BIT(VECS0) | BIT(VECS1) |
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 3699b1c539ea..c8aaf646430c 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -130,6 +130,7 @@ enum intel_ppgtt_type {
/* Keep has_* in alphabetical order */ \
func(has_64bit_reloc); \
func(has_64k_pages); \
+ func(needs_compact_pt); \
func(gpu_reset_clobbers_display); \
func(has_reset_engine); \
func(has_global_mocs); \
Re: [Intel-gfx] [PATCH v5 2/5] drm/i915: enforce min GTT alignment for discrete cards
On 1/25/22 20:35, Robert Beckett wrote:
From: Matthew Auld
For local-memory objects we need to align the GTT addresses
to 64K, both for the ppgtt and ggtt.
We need to support vm->min_alignment > 4K, depending
on the vm itself and the type of object we are inserting.
With this in mind update the GTT selftests to take this
into account.
For compact-pt we further align and pad lmem object GTT addresses
to 2MB to ensure PDEs contain consistent page sizes as
required by the HW.
v3:
* use needs_compact_pt flag to discriminate between
64K and 64K with compact-pt
* add i915_vm_obj_min_alignment
* use i915_vm_obj_min_alignment to round up vma reservation
if compact-pt instead of hard coding
v5:
* fix i915_vm_obj_min_alignment for internal objects which
have no memory region
Signed-off-by: Matthew Auld
Signed-off-by: Ramalingam C
Signed-off-by: Robert Beckett
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
---
.../i915/gem/selftests/i915_gem_client_blt.c | 23 +++--
drivers/gpu/drm/i915/gt/intel_gtt.c | 12 +++
drivers/gpu/drm/i915/gt/intel_gtt.h | 18
drivers/gpu/drm/i915/i915_vma.c | 9 ++
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 96 ---
5 files changed, 117 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
index c8ff8bf0986d..f0bfce53258f 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
@@ -39,6 +39,7 @@ struct tiled_blits {
struct blit_buffer scratch;
struct i915_vma *batch;
u64 hole;
+ u64 align;
u32 width;
u32 height;
};
@@ -410,14 +411,21 @@ tiled_blits_create(struct intel_engine_cs *engine, struct
rnd_state *prng)
goto err_free;
}
- hole_size = 2 * PAGE_ALIGN(WIDTH * HEIGHT * 4);
+ t->align = I915_GTT_PAGE_SIZE_2M; /* XXX worst case, derive from vm! */
+ t->align = max(t->align,
+ i915_vm_min_alignment(t->ce->vm, INTEL_MEMORY_LOCAL));
+ t->align = max(t->align,
+ i915_vm_min_alignment(t->ce->vm, INTEL_MEMORY_SYSTEM));
Don't we always end up with 2M here, regardless of the vm restrictions?
[Intel-gfx] [PATCH 20/20] HAX: DG1 small BAR
Just for CI.
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_create.c | 5 ++---
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 2 +-
2 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c
b/drivers/gpu/drm/i915/gem/i915_gem_create.c
index 98d63cb21e94..6e6a3f6685ab 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
@@ -437,9 +437,8 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void
*data,
if (!(ext_data.placement_mask & BIT(INTEL_REGION_SMEM)))
return -EINVAL;
} else {
- if (!IS_DG1(i915) && (ext_data.n_placements > 1 ||
- ext_data.placements[0]->type !=
- INTEL_MEMORY_SYSTEM))
+ if (ext_data.n_placements > 1 ||
+ ext_data.placements[0]->type != INTEL_MEMORY_SYSTEM)
ext_data.flags |= I915_BO_ALLOC_TOPDOWN;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index b788fc2b3df8..a99516d2b706 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -211,7 +211,7 @@ static struct intel_memory_region *setup_lmem(struct
intel_gt *gt)
lmem_size = intel_uncore_read64(uncore, GEN12_GSMBASE);
io_start = pci_resource_start(pdev, 2);
- io_size = min(pci_resource_len(pdev, 2), lmem_size);
+ io_size = SZ_256M;
if (!io_size)
return ERR_PTR(-ENODEV);
--
2.34.1
